diff --git a/vunit/sim_if/rivierapro.py b/vunit/sim_if/rivierapro.py
index f398d9bb9..6e8870ef3 100644
--- a/vunit/sim_if/rivierapro.py
+++ b/vunit/sim_if/rivierapro.py
@@ -177,6 +177,10 @@ def compile_vhdl_file_command(self, source_file):
         """
         Returns the command to compile a VHDL file
         """
+        libraries = []
+        for library in self._libraries:
+            if library.name not in ["simprims_ver", "unifast_ver", "unimacro_ver", "unisims_ver"]:
+                libraries += ["-L", library.name]
 
         return (
             [
@@ -185,6 +189,7 @@ def compile_vhdl_file_command(self, source_file):
                 "-j",
                 str(Path(self._sim_cfg_file_name).parent),
             ]
+            + libraries
             + source_file.compile_options.get("rivierapro.vcom_flags", [])
             + [
                 self._std_str(source_file.get_vhdl_standard()),
@@ -310,6 +315,9 @@ def _create_load_function(
 
         vsim_flags += ["-lib", config.library_name]
 
+        for library in self._libraries:
+            vsim_flags += ["-L", library.name]
+
         if config.vhdl_configuration_name is None:
             # Add the the testbench top-level unit last as coverage is
             # only collected for the top-level unit specified last