aarch64: implements lifting (intrinsics) for LDXP/STXP

Author: themaks

arch/arm64/arch_arm64.cpp

@@ -1020,6 +1020,8 @@ class Arm64Architecture : public Architecture
 			return "__ldxrb";
 		case ARM64_INTRIN_LDXRH:
 			return "__ldxrh";
+		case ARM64_INTRIN_LDXP:
+			return "__ldxp";
 		case ARM64_INTRIN_LDAXR:
 			return "__ldaxr";
 		case ARM64_INTRIN_LDAXRB:
@@ -1032,6 +1034,8 @@ class Arm64Architecture : public Architecture
 			return "__stxrb";
 		case ARM64_INTRIN_STXRH:
 			return "__stxrh";
+		case ARM64_INTRIN_STXP:
+			return "__stxp";
 		case ARM64_INTRIN_STLXR:
 			return "__stlxr";
 		case ARM64_INTRIN_STLXRB:

arch/arm64/il.cpp

@@ -2313,6 +2313,9 @@ bool GetLowLevelILForInstruction(
 		il.AddInstruction(il.Intrinsic({ RegisterOrFlag::Register(REG_O(operand1)) }, ARM64_INTRIN_LDXRH, { ILREG_O(operand2) }));
 		break;
 	// We don't have a way to specify intrinsic register size, so we explicitly embed the size in the intrinsic name.
+	case ARM64_LDXP:
+		il.AddInstruction(il.Intrinsic({ RegisterOrFlag::Register(REG_O(operand1)), RegisterOrFlag::Register(REG_O(operand2)) }, ARM64_INTRIN_LDXP, { ILREG_O(operand3) }));
+		break;
 	case ARM64_LDAXR:
 		il.AddInstruction(il.Intrinsic({ RegisterOrFlag::Register(REG_O(operand1)) }, ARM64_INTRIN_LDAXR, { ILREG_O(operand2) }));
 		break;
@@ -2331,6 +2334,9 @@ bool GetLowLevelILForInstruction(
 	case ARM64_STXRH:
 		il.AddInstruction(il.Intrinsic({ RegisterOrFlag::Register(REG_O(operand1)) }, ARM64_INTRIN_STXRH, { ILREG_O(operand2), ILREG_O(operand3) }));
 		break;
+	case ARM64_STXP:
+		il.AddInstruction(il.Intrinsic({ RegisterOrFlag::Register(REG_O(operand1)) }, ARM64_INTRIN_STXP, { ILREG_O(operand2), ILREG_O(operand3), ILREG_O(operand4) }));
+		break;
 	case ARM64_STLXR:
 		il.AddInstruction(il.Intrinsic({ RegisterOrFlag::Register(REG_O(operand1)) }, ARM64_INTRIN_STLXR, { ILREG_O(operand2), ILREG_O(operand3) }));
 		break;

arch/arm64/il.h

@@ -85,12 +85,14 @@ enum Arm64Intrinsic : uint32_t
 	ARM64_INTRIN_LDXR,
 	ARM64_INTRIN_LDXRB,
 	ARM64_INTRIN_LDXRH,
+	ARM64_INTRIN_LDXP,
 	ARM64_INTRIN_LDAXR,
 	ARM64_INTRIN_LDAXRB,
 	ARM64_INTRIN_LDAXRH,
 	ARM64_INTRIN_STXR,
 	ARM64_INTRIN_STXRB,
 	ARM64_INTRIN_STXRH,
+	ARM64_INTRIN_STXP,
 	ARM64_INTRIN_STLXR,
 	ARM64_INTRIN_STLXRB,
 	ARM64_INTRIN_STLXRH,