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The issue is that modern compilers are sometimes too smart! It will be harder for us to use mistakes in our poor-organized Verilog code , since in -O2 , gcc may perform aggressive inlining and other optimizations to the code, which make it harder to debug!
The text was updated successfully, but these errors were encountered:
Link here
The issue is that modern compilers are sometimes too smart! It will be harder for us to use mistakes in our poor-organized Verilog code , since in -O2 , gcc may perform aggressive inlining and other optimizations to the code, which make it harder to debug!
The text was updated successfully, but these errors were encountered: