-
Notifications
You must be signed in to change notification settings - Fork 10
/
Copy pathPE_block.sv
305 lines (257 loc) · 9.91 KB
/
PE_block.sv
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
module PE1( input logic clk,
input logic pe_reset,
input logic [143:0] input_fm,
input logic [47:0] filter,
output logic [111:0] output_fm,
output logic output_en,
);
/* one PE contains 7 MACs, c.r.t. 7 output feature maps
* 9 input FM = 16 * 9 = 144
* 3 input filter = 16 * 3 = 48
* 7 output FM = 16 * 7 = 112 */
logic part_sum[111:0]; /* 7 output FM = 16 * 7 = 112 */
/* need at max 3 x 3 x 512 times of MAC per output,
* + 3 x 512 times of reset MAC,
* 6144 < 2 ^ 13 = 8296 */
logic count_output[12:0];
logic count_mac[1:0]; /* control reset signal of macs */
assign output_fm = part_sum;
/* whether reset MAC result */
always_ff @ (posedge clk) begin
/* when count = 3 -> overflow to 0 */
count_mac <= count_mac + 1'b1;
if (count_mac == 3) begin
/* when MAC finish a 3 * 1 convolution,
* add partial sum to output */
output_fm[111:96] <= output_fm[111:96] + part_sum[111:96];
output_fm[95:80] <= output_fm[95:80] + part_sum[95:80];
output_fm[79:64] <= output_fm[79:64] + part_sum[79:64];
output_fm[63:48] <= output_fm[63:48] + part_sum[63:48];
output_fm[47:32] <= output_fm[47:32] + part_sum[47:32];
output_fm[31:16] <= output_fm[31:16] + part_sum[31:16];
output_fm[15:0] <= output_fm[15:0] + part_sum[15:0];
end
end
mac1(clk, count_mac[1:0], input_fm[143:96], flt[47:0], part_sum[111:96]);
mac2(clk, count_mac[1:0], input_fm[127:80], flt[47:0], part_sum[95:80]);
mac3(clk, count_mac[1:0], input_fm[111:64], flt[47:0], part_sum[79:64]);
mac4(clk, count_mac[1:0], input_fm[95:48], flt[47:0], part_sum[63:48]);
mac5(clk, count_mac[1:0], input_fm[79:32], flt[47:0], part_sum[47:32]);
mac6(clk, count_mac[1:0], input_fm[63:16], flt[47:0], part_sum[31:16]);
mac7(clk, count_mac[1:0], input_fm[47:0], flt[47:0], part_sum[15:0]);
/* whether output result or continue computing partial sum */
always_ff @ (posedge clk) begin
count_output <= count_output + 1'b1;
/* enable output & reset register every 3 x 4 x 512 = 6144 clock cycles */
if (count_output == 6143)
output_en <= 1;
else if (count_output == 6144 || pe_reset) begin /* reset */
output_en <= 1'b0;
part_sum <= 112'b0;
count_output <= 13'b0;
count_mac <= 2'b0; end
end
endmodule
module mac1(input logic clk,
input logic [1:0] count_mac,
input logic [47:0] in_fm,
input logic [47:0] flt,
output logic [15:0] result);
/* in_fm: input feature map (3,1)
* flt: filter (3,1)
* result: (1,1), output this value after
* 3 times of MAC operations */
logic [31:0] mul_result;
logic [15:0] result; /* MAC result after 3 clock cycles */
/* count_mac = 0 -> in_fm[47:32] * flt[47:32]
* count_mac = 1 -> in_fm[31:16] * flt[31:16]
* count_mac = 2 -> in_fm[15:0] * flt[15:0]
* count_mac = 3 -> reset */
always_ff @(posedge clk or negedge mac_reset) begin
if (count_mac == 2'b0) begin
mul_result = in_fm[47:32] * flt[47:32];
result <= result + mul_result[23:8]; end
else if (count_mac == 2'b1) begin
mul_result = in_fm[31:16] * flt[31:16];
result <= result + mul_result[23:8]; end
else if (count_mac == 2'b2) begin
mul_result = in_fm[15:0] * flt[15:0];
result <= result + mul_result[23:8]; end
else begin /* count_mac == 3: reset */
result <= 16'b0; end
end
endmodule
module mac2(input logic clk,
input logic [1:0] count_mac,
input logic [47:0] in_fm,
input logic [47:0] flt,
output logic [15:0] result);
/* in_fm: input feature map (3,1)
* flt: filter (3,1)
* result: (1,1), output this value after
* 3 times of MAC operations */
logic [31:0] mul_result;
logic [15:0] result; /* MAC result after 3 clock cycles */
/* count_mac = 0 -> in_fm[47:32] * flt[47:32]
* count_mac = 1 -> in_fm[31:16] * flt[31:16]
* count_mac = 2 -> in_fm[15:0] * flt[15:0]
* count_mac = 3 -> reset */
always_ff @(posedge clk or negedge mac_reset) begin
if (count_mac == 2'b0) begin
mul_result = in_fm[47:32] * flt[47:32];
result <= result + mul_result[23:8]; end
else if (count_mac == 2'b1) begin
mul_result = in_fm[31:16] * flt[31:16];
result <= result + mul_result[23:8]; end
else if (count_mac == 2'b2) begin
mul_result = in_fm[15:0] * flt[15:0];
result <= result + mul_result[23:8]; end
else begin /* count_mac == 3: reset */
result <= 16'b0; end
end
endmodule
module mac3(input logic clk,
input logic [1:0] count_mac,
input logic [47:0] in_fm,
input logic [47:0] flt,
output logic [15:0] result);
/* in_fm: input feature map (3,1)
* flt: filter (3,1)
* result: (1,1), output this value after
* 3 times of MAC operations */
logic [31:0] mul_result;
logic [15:0] result; /* MAC result after 3 clock cycles */
/* count_mac = 0 -> in_fm[47:32] * flt[47:32]
* count_mac = 1 -> in_fm[31:16] * flt[31:16]
* count_mac = 2 -> in_fm[15:0] * flt[15:0]
* count_mac = 3 -> reset */
always_ff @(posedge clk or negedge mac_reset) begin
if (count_mac == 2'b0) begin
mul_result = in_fm[47:32] * flt[47:32];
result <= result + mul_result[23:8]; end
else if (count_mac == 2'b1) begin
mul_result = in_fm[31:16] * flt[31:16];
result <= result + mul_result[23:8]; end
else if (count_mac == 2'b2) begin
mul_result = in_fm[15:0] * flt[15:0];
result <= result + mul_result[23:8]; end
else begin /* count_mac == 3: reset */
result <= 16'b0; end
end
endmodule
module mac4(input logic clk,
input logic [1:0] count_mac,
input logic [47:0] in_fm,
input logic [47:0] flt,
output logic [15:0] result);
/* in_fm: input feature map (3,1)
* flt: filter (3,1)
* result: (1,1), output this value after
* 3 times of MAC operations */
logic [31:0] mul_result;
logic [15:0] result; /* MAC result after 3 clock cycles */
/* count_mac = 0 -> in_fm[47:32] * flt[47:32]
* count_mac = 1 -> in_fm[31:16] * flt[31:16]
* count_mac = 2 -> in_fm[15:0] * flt[15:0]
* count_mac = 3 -> reset */
always_ff @(posedge clk or negedge mac_reset) begin
if (count_mac == 2'b0) begin
mul_result = in_fm[47:32] * flt[47:32];
result <= result + mul_result[23:8]; end
else if (count_mac == 2'b1) begin
mul_result = in_fm[31:16] * flt[31:16];
result <= result + mul_result[23:8]; end
else if (count_mac == 2'b2) begin
mul_result = in_fm[15:0] * flt[15:0];
result <= result + mul_result[23:8]; end
else begin /* count_mac == 3: reset */
result <= 16'b0; end
end
endmodule
module mac5(input logic clk,
input logic [1:0] count_mac,
input logic [47:0] in_fm,
input logic [47:0] flt,
output logic [15:0] result);
/* in_fm: input feature map (3,1)
* flt: filter (3,1)
* result: (1,1), output this value after
* 3 times of MAC operations */
logic [31:0] mul_result;
logic [15:0] result; /* MAC result after 3 clock cycles */
/* count_mac = 0 -> in_fm[47:32] * flt[47:32]
* count_mac = 1 -> in_fm[31:16] * flt[31:16]
* count_mac = 2 -> in_fm[15:0] * flt[15:0]
* count_mac = 3 -> reset */
always_ff @(posedge clk or negedge mac_reset) begin
if (count_mac == 2'b0) begin
mul_result = in_fm[47:32] * flt[47:32];
result <= result + mul_result[23:8]; end
else if (count_mac == 2'b1) begin
mul_result = in_fm[31:16] * flt[31:16];
result <= result + mul_result[23:8]; end
else if (count_mac == 2'b2) begin
mul_result = in_fm[15:0] * flt[15:0];
result <= result + mul_result[23:8]; end
else begin /* count_mac == 3: reset */
result <= 16'b0; end
end
endmodule
module mac6(input logic clk,
input logic [1:0] count_mac,
input logic [47:0] in_fm,
input logic [47:0] flt,
output logic [15:0] result);
/* in_fm: input feature map (3,1)
* flt: filter (3,1)
* result: (1,1), output this value after
* 3 times of MAC operations */
logic [31:0] mul_result;
logic [15:0] result; /* MAC result after 3 clock cycles */
/* count_mac = 0 -> in_fm[47:32] * flt[47:32]
* count_mac = 1 -> in_fm[31:16] * flt[31:16]
* count_mac = 2 -> in_fm[15:0] * flt[15:0]
* count_mac = 3 -> reset */
always_ff @(posedge clk or negedge mac_reset) begin
if (count_mac == 2'b0) begin
mul_result = in_fm[47:32] * flt[47:32];
result <= result + mul_result[23:8]; end
else if (count_mac == 2'b1) begin
mul_result = in_fm[31:16] * flt[31:16];
result <= result + mul_result[23:8]; end
else if (count_mac == 2'b2) begin
mul_result = in_fm[15:0] * flt[15:0];
result <= result + mul_result[23:8]; end
else begin /* count_mac == 3: reset */
result <= 16'b0; end
end
endmodule
module mac7(input logic clk,
input logic [1:0] count_mac,
input logic [47:0] in_fm,
input logic [47:0] flt,
output logic [15:0] result);
/* in_fm: input feature map (3,1)
* flt: filter (3,1)
* result: (1,1), output this value after
* 3 times of MAC operations */
logic [31:0] mul_result;
logic [15:0] result; /* MAC result after 3 clock cycles */
/* count_mac = 0 -> in_fm[47:32] * flt[47:32]
* count_mac = 1 -> in_fm[31:16] * flt[31:16]
* count_mac = 2 -> in_fm[15:0] * flt[15:0]
* count_mac = 3 -> reset */
always_ff @(posedge clk or negedge mac_reset) begin
if (count_mac == 2'b0) begin
mul_result = in_fm[47:32] * flt[47:32];
result <= result + mul_result[23:8]; end
else if (count_mac == 2'b1) begin
mul_result = in_fm[31:16] * flt[31:16];
result <= result + mul_result[23:8]; end
else if (count_mac == 2'b2) begin
mul_result = in_fm[15:0] * flt[15:0];
result <= result + mul_result[23:8]; end
else begin /* count_mac == 3: reset */
result <= 16'b0; end
end
endmodule