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Version: Vitis 2024.1
This tutorial introduces you to performance analysis and optimization methods, and shows you how synchronization works in graph execution. It also demonstrates the analysis of a hang issue using an example.
IMPORTANT: Before beginning the tutorial, make sure that you have installed the AMD Vitis™ 2024.1 software. The Vitis release includes all the embedded base platforms, including the VCK190 base platform that is used in this tutorial. In addition, ensure that you have downloaded the Common Images for Embedded Vitis Platforms from this link https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-platforms.html
The ‘common image’ package contains a prebuilt Linux kernel and root file system that can be used with the AMD Versal™ board for embedded design development using Vitis.
Before starting this tutorial, run the following steps:
- Go to the directory where you have unzipped the Versal Common Image package.
- In a Bash shell, run the /Common Images Dir/xilinx-versal-common-v2024.1/environment-setup-cortexa72-cortexa53-xilinx-linux script. This script sets up the SDKTARGETSYSROOT and CXX variables. If the script is not present, you must run the /Common Images Dir/xilinx-versal-common-v2024.1/sdk.sh.
- Set up your ROOTFS, and IMAGE to point to the rootfs.ext4 and Image files located in the /Common Images Dir/xilinx-versal-common-v2024.1 directory.
- Set up your PLATFORM_REPO_PATHS environment variable to $XILINX_VITIS/base_platforms.
This tutorial targets VCK190 production board for 2024.1 version.
After completing this tutorial, you will understand how to:
- Read lock signals in Vitis Analyzer.
- Profile design performance.
- Identify a performance bottleneck.
- Analyze a deadlock (hang issue) in the design.
- Analyze AI Engine status using Vitis Analyzer.
Step 1: Learn about the execution model of an AI Engine graph, including how memory with lock and FIFO works. Learn performance measurement methods. Identify performance bottlenecks and practise optimization. Go to AI Engine Graph Execution and Measurement.
Step 2: Learn about how a deadlock might occur with an example design. Learn how to analyze a deadlock in the AI Engine simulator, hardware emulation, and hardware flows. Go to AI Engine Deadlock Analysis.
Step 3: Learn about AI Engine status analysis in the hardware and hardware emulation flows using Vitis Analyzer. Go to AI Engine Status Analysis.
Tip: In this tutorial, the designs are self contained in each step. You can choose to start at any step depending on your experience and requirements. Be aware that the concepts and options introduced in the previous step might not be repeated later. It is recommended to start from the beginning and progress through to completion.
GitHub issues will be used for tracking requests and bugs. For questions go to forums.xilinx.com.
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