See Vitis™ Development Environment on xilinx.com See Vitis™ AI Development Environment on xilinx.com |
Version: Vitis 2024.2
The aiecompiler
is evolving and therefore it may be difficult for you to keep up with new features. This tutorial shares a variety of features that are useful for AI Engine / AI Engine-ML (AIE-ML) programming to create more visible and efficient code compared to early versions of the compiler.
IMPORTANT: Before beginning the tutorial, make sure that you have installed the AMD Vitis™ Unified Software Platform 2024.2.
Data generation for this tutorial requires Python 3. The following packages are required:
- os
- sys
- numpy
All these designs will compile for AI Engine architecture (VCK190 production board using ARCH=aie
in make
command line) and the AI Engine ML architecture (VEK280 board using ARCH=aie-ml
in make
command line)
After completing this tutorial, you will be able to:
- Work with multirate design that allow the compiler to handle frame length mismatch between consecutive kernels in a kernel chain.
- Send output data to different other kernels for stream-based and buffer-based I/O.
- Conditionally instantiate graph objects.
This tutorial is based on simple data passthrough to avoid another level of complexity.
Section Link | Description |
---|---|
Conditional Objects | Shows how to conditionally instantiate graph objects |
Multirate | Explains how to handle mismatching frame length in between kernels |
Multicast | Provides examples on how to manipulate stream/buffer multicasting with multirate |
GitHub issues will be used for tracking requests and bugs. For questions, go to support.xilinx.com.
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