Versal AI Core devices are highly integrated, multicore compute platform that can adapt with evolving and diverse algorithms. These devices include both Programmable Logic (PL) and an AI Engine array. Vitis Model Composer provides a design environment, based on industry standard MATLAB and Simulink tools, to model and simulate designs with both PL and AI Engine components.
| Design with both AI Engines and HLS kernels | |
| Polyphase Channelizer | This example implements a high-speed channelizer design using a combination of AI Engine and Programmable Logic (PL) resources in Versal devices. |
Prime Factor FFT-1008 
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This example demonstrates a Prime Factor FFT algorithm on AIE-ML devices. It demonstrates the Shared Buffer block to access Memory Tiles on the AIE-ML array. |
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64K-Pt IFFT @ 2 Gsps Using a 2D Architecture
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This example demonstrates a 2D architecture to implement large point transforms in the SSR > 1 regime. |
| AI Engines and HLS Kernel with interface blocks | A design with both AI Engine and HLS Kernel blocks connected through interface blocks. |
| AI Engines and HLS Kernel connected directly | A design with both AI Engine and HLS Kernel blocks connected directly. |
| AI Engines and HLS Kernel with RTP | A design with AI Engine blocks and an HLS Kernel block with a Run-time Parameter (RTP). |
| 2D FFT | A 2D FFT design with both AI Engine and HLS Kernel. |
| Designs with both AI Engine and HDL blocks | |
| Design with HDL and AI Engine blocks | Design with HDL and AI Engine blocks |
| Design with imported RTL and AI Engine blocks | Design with imported RTL and AI Engine blocks. |
| 2D FFT | A 2D FFT design with both AI Engine and HDL Kernel. |
| Super Sample Rate FIR filter with PL | This design showcases a Super Sample Rate FIR filter to process a 4GSPS input stream. In this design we consider latencies within the kernels, which are implemented into the FIFO's included in AXI-Stream Interconnect(PL). |
| AIE-PL Multirate Design | This design highlights best practices for working with multirate designs. The example utilizes multirate AIE FIR filters to generate outputs in multiple clock domains which are then fed thru the PL. The DSP aspects are discussed separately, so for designers not interested in filtering the discussion still provides useful information. |
| Multirate Filter Chain | This design implements two decimation filters, one in AI Engine and the other in PL. See how to set the AI Engine sample time, PL Gateway block sample period, and the Simulink system period in the Model Composer Hub block to match the multirate behavior of your system. |