See Vitis™ Development Environment on xilinx.comSee Vitis™ AI Development Environment on xilinx.com |
Vitis Model Composer can be used to create complex systems targeting the PL (HDL and HLS block libraries) and the AI Engine array (AI Engine block library) at the same time. The complete system can be simulated in Simulink, and the design exported to generated code (RTL for the PL and C++ graph for the AI Engine array) or to Vitis. The Hardware Validation flow can be used to reproduce the Simulink testbench running on the hardware.
Vitis Model Composer simulates HDL designs in a cycle-accurate manner, while AIE and HLS simulation is functional only and does not provide cycle-accurate timing information. Because of this, Vitis Model Composer has interface blocks (AIE to HDL, HDL to AIE, AIE to HLS, HLS to AIE) that bridge between the simulation domains.
These tutorials will give a greater understanding of how the different processing domains are modeled in Simulink. They will also explain how to configure the interface blocks to accurately model how the AIE and PL will interact in hardware.
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