Click here to learn what you need to know about Simulink before you start using Vitis Model Composer.
These tutorials take users through the design methodology and programming model for developing algorithms in Vitis Model Composer for AMD devices, including Versal devices with AI Engines.
| HDL Library | |
| Lab 1 | Introduction to Vitis Model Composer HDL Library |
| Lab 2 | Importing Code into a Vitis Model Composer HDL Design |
| Lab 3 | Timing and Resource Analysis. |
| Lab 4 | Working with Multi-Rate Systems |
| Lab 5 | Using AXI Interfaces and IP Integrator |
| Lab 6 | Using a Vitis Model Composer HDL Design with a Zynq-7000 SoC |
| HLS Library | |
| Lab 1 | Introduction to Model Composer HLS Library |
| Lab 2 | Importing Code into Vitis Model Composer |
| Lab 3 | Debugging Imported C/C++-Code Using GDB Debugger |
| Lab 4 | Automatic Code Generation |
| AI Engine Library | |
| Lab 1 | Introduction to Versal Adaptive SoC and AI Engines |
| Lab 2 | Build and Simulate an AI Engine Design |
| Lab 3 | Import Custom AI Engine Code |
| Lab 4 | AI Engine Code Generation and Cycle-Approximate Simulation |
| Lab 5 | View AI Engine Designs in Vitis Analyzer |
| Lab 6 | Hardware Validation of Versal Adaptive SoC Design |
| Lab 7 |
Export AI Engine Design from Vitis Model Composer to Vitis 
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| AIE-PL System Development
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| Lab 1 | Connecting AI Engine and HDL Subsystems |
| Lab 2 | Connecting AI Engine and HLS Subsystems |
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http://www.apache.org/licenses/LICENSE-2.0
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