From 431625b6e07a9d77748aa4f0279fe2137593abd0 Mon Sep 17 00:00:00 2001 From: Felix Jentzsch Date: Wed, 7 Sep 2022 16:22:10 +0200 Subject: [PATCH 001/665] Initial VVAU SIMD support --- .../fpgadataflow/vectorvectoractivation.py | 37 +++++++++++++------ tests/fpgadataflow/test_fpgadataflow_vvau.py | 22 ++++++++--- 2 files changed, 42 insertions(+), 17 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index 27b23dd328..bc332b5944 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -54,6 +54,7 @@ def __init__(self, onnx_node): def get_nodeattr_types(self): my_attrs = { "PE": ("i", True, 0), + "SIMD": ("i", False, 1), "Dim": ("ints", True, []), # [H, W] "Channels": ("i", True, 0), "Kernel": ("ints", True, []), # [H, W] @@ -142,7 +143,8 @@ def calc_wmem(self): ch = self.get_nodeattr("Channels") k_h, k_w = self.get_nodeattr("Kernel") pe = self.get_nodeattr("PE") - wmem = k_h * k_w * ch // pe + simd = self.get_nodeattr("SIMD") + wmem = (k_h * k_w * ch // pe) // simd return wmem def calc_tmem(self): @@ -190,7 +192,12 @@ def get_output_datatype(self): def get_instream_width(self): i_bits = self.get_input_datatype().bitwidth() - in_width = i_bits * self.get_nodeattr("PE") + simd = self.get_nodeattr("SIMD") + if simd > 1: + pe = self.get_nodeattr("Channels") + else: + pe = self.get_nodeattr("PE") + in_width = i_bits * simd * pe return in_width def get_outstream_width(self): @@ -200,12 +207,16 @@ def get_outstream_width(self): def get_folded_input_shape(self): k_h, k_w = self.get_nodeattr("Kernel") - sf = k_h * k_w dim_h, dim_w = self.get_nodeattr("Dim") ch = self.get_nodeattr("Channels") - pe = self.get_nodeattr("PE") + simd = self.get_nodeattr("SIMD") + if simd > 1: + pe = self.get_nodeattr("Channels") + else: + pe = self.get_nodeattr("PE") + sf = k_h * k_w // simd nf = ch // pe - folded_input_shape = tuple([1, dim_h, dim_w, sf * nf, pe]) + folded_input_shape = tuple([1, dim_h, dim_w, sf * nf, simd * pe]) return folded_input_shape def get_folded_output_shape(self): @@ -235,6 +246,7 @@ def get_number_output_values(self): def get_exp_cycles(self): pe = self.get_nodeattr("PE") + simd = self.get_nodeattr("SIMD") ch = self.get_nodeattr("Channels") dim_h, dim_w = self.get_nodeattr("Dim") k_h, k_w = self.get_nodeattr("Kernel") @@ -242,7 +254,7 @@ def get_exp_cycles(self): batch_size = 1 # since mmv != 1 is not supported yet, we set mmv for now to 1 mmv = 1 - exp_cycles = ((ch * k_h * k_w) / pe) * batch_size * (dim_h * dim_w) / mmv + exp_cycles = ((ch * k_h * k_w) / pe / simd) * batch_size * (dim_h * dim_w) / mmv return int(exp_cycles) def get_template_param_values(self): @@ -268,6 +280,7 @@ def get_template_param_values(self): def get_hls_compatible_weight_tensor(self, orig_weight_matrix): pe = self.get_nodeattr("PE") + simd = self.get_nodeattr("SIMD") ch = self.get_nodeattr("Channels") k_h, k_w = self.get_nodeattr("Kernel") wmem = self.calc_wmem() @@ -282,7 +295,7 @@ def get_hls_compatible_weight_tensor(self, orig_weight_matrix): ret = ret.reshape(ch, k_h * k_w) # distribute rows between PEs ret = interleave_matrix_outer_dim_from_partitions(ret, pe) - ret = ret.reshape(1, pe, wmem, 1) + ret = ret.reshape(1, pe, wmem, simd) return ret def get_hls_compatible_threshold_tensor(self, orig_thres_matrix): @@ -334,7 +347,8 @@ def generate_params(self, model, path): if wdt.bitwidth() != 1: f_weights.write( - "const FixedPointWeights<1,{},{},{}> weights = ".format( + "const FixedPointWeights<{},{},{},{}> weights = ".format( + self.get_nodeattr("SIMD"), wdt.get_hls_datatype_str(), self.get_nodeattr("PE"), self.calc_wmem(), @@ -342,8 +356,8 @@ def generate_params(self, model, path): ) else: f_weights.write( - "const BinaryWeights<1,{},{}> weights = ".format( - self.get_nodeattr("PE"), self.calc_wmem() + "const BinaryWeights<{},{},{}> weights = ".format( + self.get_nodeattr("SIMD"), self.get_nodeattr("PE"), self.calc_wmem() ) ) f_weights.write(weight_hls_code) @@ -476,9 +490,10 @@ def defines(self, var): innerProdDim = k_h * k_w self.code_gen_dict["$DEFINES$"] = [ """#define Channels1 {}\n #define InnerProdDim {}\n - #define SIMD1 1\n #define PE1 {}\n #define numReps {}""".format( + #define SIMD1 {}\n #define PE1 {}\n #define numReps {}""".format( self.get_nodeattr("Channels"), innerProdDim, + self.get_nodeattr("SIMD"), self.get_nodeattr("PE"), numReps, ) diff --git a/tests/fpgadataflow/test_fpgadataflow_vvau.py b/tests/fpgadataflow/test_fpgadataflow_vvau.py index c48448787d..f854c997ff 100644 --- a/tests/fpgadataflow/test_fpgadataflow_vvau.py +++ b/tests/fpgadataflow/test_fpgadataflow_vvau.py @@ -75,7 +75,7 @@ def _calculate_dot_prod_range(dt_a, dt_b, len): def _make_single_vvau_modelwrapper( - W, pe, k_h, k_w, channels, dim_h, dim_w, wdt, idt, odt, T=None, tdt=None + W, pe, simd, k_h, k_w, channels, dim_h, dim_w, wdt, idt, odt, T=None, tdt=None ): in_shape = [1, dim_h, dim_w, k_h * k_w * channels] # [N, H, W, K*K*CH] out_shape = [ @@ -104,6 +104,7 @@ def _make_single_vvau_modelwrapper( domain="finn.custom_op.fpgadataflow", backend="fpgadataflow", PE=pe, + SIMD=simd, Dim=[dim_h, dim_w], Channels=channels, Kernel=[k_h, k_w], @@ -148,6 +149,8 @@ def prepare_inputs(input_tensor): @pytest.mark.parametrize("act", [DataType["UINT4"], None]) # PE @pytest.mark.parametrize("pe", [1, "channels"]) +# SIMD +@pytest.mark.parametrize("simd", [1]) # Input image shape @pytest.mark.parametrize("dim_h", [10]) @pytest.mark.parametrize("dim_w", [10, 1]) @@ -162,7 +165,7 @@ def prepare_inputs(input_tensor): @pytest.mark.slow @pytest.mark.vivado def test_fpgadataflow_vvau( - idt, wdt, act, pe, dim_h, dim_w, k_h, k_w, channels, exec_mode + idt, wdt, act, pe, simd, dim_h, dim_w, k_h, k_w, channels, exec_mode ): if pe == "channels": pe = channels @@ -198,7 +201,7 @@ def test_fpgadataflow_vvau( tdt = DataType["INT32"] model = _make_single_vvau_modelwrapper( - W, pe, k_h, k_w, channels, dim_h, dim_w, wdt, idt, odt, T, tdt + W, pe, simd, k_h, k_w, channels, dim_h, dim_w, wdt, idt, odt, T, tdt ) if exec_mode == "cppsim": @@ -230,7 +233,14 @@ def test_fpgadataflow_vvau( "outp" ] - assert (y_produced == y_expected).all(), "cppsim failed" + with open("vvau_test_expected.txt", "w") as f: + f.write("-------expected:\n") + f.write(str(y_expected)) + with open("vvau_test_produced.txt", "w") as f: + f.write("--------produced:\n") + f.write(str(y_produced)) + + assert (y_produced == y_expected).all(), "incorrect result" if exec_mode == "rtlsim": node = model.get_nodes_by_op_type("VectorVectorActivation")[0] @@ -238,5 +248,5 @@ def test_fpgadataflow_vvau( cycles_rtlsim = inst.get_nodeattr("cycles_rtlsim") exp_cycles_dict = model.analysis(exp_cycles_per_layer) exp_cycles = exp_cycles_dict[node.name] - assert np.isclose(exp_cycles, cycles_rtlsim, atol=10) - assert exp_cycles != 0 + # assert np.isclose(exp_cycles, cycles_rtlsim, atol=10) + # assert exp_cycles != 0 From 96a366a178cb5dfad0b1e9e2e6f899f23387c2fb Mon Sep 17 00:00:00 2001 From: Hendrik Borras Date: Thu, 8 Sep 2022 12:23:33 +0200 Subject: [PATCH 002/665] Rename brevitas_network_import notebook and add intro note --- .../basics/1_brevitas_network_import.ipynb | 319 ------- ...revitas_network_import_via_FINN-ONNX.ipynb | 882 ++++++++++++++++++ 2 files changed, 882 insertions(+), 319 deletions(-) delete mode 100644 notebooks/basics/1_brevitas_network_import.ipynb create mode 100644 notebooks/basics/1a_brevitas_network_import_via_FINN-ONNX.ipynb diff --git a/notebooks/basics/1_brevitas_network_import.ipynb b/notebooks/basics/1_brevitas_network_import.ipynb deleted file mode 100644 index 5fb29754dc..0000000000 --- a/notebooks/basics/1_brevitas_network_import.ipynb +++ /dev/null @@ -1,319 +0,0 @@ -{ - "cells": [ - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "# Importing Brevitas networks into FINN\n", - "\n", - "In this notebook we'll go through an example of how to import a Brevitas-trained QNN into FINN. The steps will be as follows:\n", - "\n", - "1. Load up the trained PyTorch model\n", - "2. Call Brevitas FINN-ONNX export and visualize with Netron\n", - "3. Import into FINN and call cleanup transformations\n", - "\n", - "We'll use the following utility functions to print the source code for function calls (`showSrc()`) and to visualize a network using netron (`showInNetron()`) in the Jupyter notebook:" - ] - }, - { - "cell_type": "code", - "execution_count": null, - "metadata": {}, - "outputs": [], - "source": [ - "import onnx\n", - "from finn.util.visualization import showSrc, showInNetron" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "## 1. Load up the trained PyTorch model\n", - "\n", - "The FINN Docker image comes with several [example Brevitas networks](https://github.com/Xilinx/brevitas/tree/master/src/brevitas_examples/bnn_pynq), and we'll use the LFC-w1a1 model as the example network here. This is a binarized fully connected network trained on the MNIST dataset. Let's start by looking at what the PyTorch network definition looks like:" - ] - }, - { - "cell_type": "code", - "execution_count": null, - "metadata": {}, - "outputs": [], - "source": [ - "from brevitas_examples import bnn_pynq\n", - "showSrc(bnn_pynq.models.FC)" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "We can see that the network topology is constructed using a few helper functions that generate the quantized linear layers and quantized activations. The bitwidth of the layers is actually parametrized in the constructor, so let's instantiate a 1-bit weights and activations version of this network. We also have pretrained weights for this network, which we will load into the model." - ] - }, - { - "cell_type": "code", - "execution_count": null, - "metadata": {}, - "outputs": [], - "source": [ - "from finn.util.test import get_test_model\n", - "lfc = get_test_model(netname = \"LFC\", wbits = 1, abits = 1, pretrained = True)\n", - "lfc" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "We have now instantiated our trained PyTorch network. Let's try to run an example MNIST image through the network using PyTorch." - ] - }, - { - "cell_type": "code", - "execution_count": null, - "metadata": {}, - "outputs": [], - "source": [ - "import torch\n", - "import matplotlib.pyplot as plt\n", - "from pkgutil import get_data\n", - "import onnx\n", - "import onnx.numpy_helper as nph\n", - "raw_i = get_data(\"qonnx.data\", \"onnx/mnist-conv/test_data_set_0/input_0.pb\")\n", - "input_tensor = onnx.load_tensor_from_string(raw_i)\n", - "input_tensor_npy = nph.to_array(input_tensor)\n", - "input_tensor_pyt = torch.from_numpy(input_tensor_npy).float()\n", - "imgplot = plt.imshow(input_tensor_npy.reshape(28,28), cmap='gray')" - ] - }, - { - "cell_type": "code", - "execution_count": null, - "metadata": {}, - "outputs": [], - "source": [ - "from torch.nn.functional import softmax\n", - "# do forward pass in PyTorch/Brevitas\n", - "produced = lfc.forward(input_tensor_pyt).detach()\n", - "probabilities = softmax(produced, dim=-1).flatten()\n", - "probabilities" - ] - }, - { - "cell_type": "code", - "execution_count": null, - "metadata": {}, - "outputs": [], - "source": [ - "import numpy as np\n", - "objects = [str(x) for x in range(10)]\n", - "y_pos = np.arange(len(objects))\n", - "plt.bar(y_pos, probabilities, align='center', alpha=0.5)\n", - "plt.xticks(y_pos, objects)\n", - "plt.ylabel('Predicted Probability')\n", - "plt.title('LFC-w1a1 Predictions for Image')\n", - "plt.show()" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "## 2. Call Brevitas FINN-ONNX export and visualize with Netron\n", - "\n", - "Brevitas comes with built-in FINN-ONNX export functionality. This is similar to the regular ONNX export capabilities of PyTorch, with a few differences:\n", - "\n", - "1. The weight quantization logic is not exported as part of the graph; rather, the quantized weights themselves are exported.\n", - "2. Special quantization annotations are used to preserve the low-bit quantization information. ONNX (at the time of writing) supports 8-bit quantization as the minimum bitwidth, whereas FINN-ONNX quantization annotations can go down to binary/bipolar quantization.\n", - "3. Low-bit quantized activation functions are exported as MultiThreshold operators.\n", - "\n", - "It's actually quite straightforward to export ONNX from our Brevitas model as follows:" - ] - }, - { - "cell_type": "code", - "execution_count": null, - "metadata": {}, - "outputs": [], - "source": [ - "import brevitas.onnx as bo\n", - "export_onnx_path = \"/tmp/LFCW1A1.onnx\"\n", - "input_shape = (1, 1, 28, 28)\n", - "bo.export_finn_onnx(lfc, input_shape, export_onnx_path)" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "Let's examine what the exported ONNX model looks like. For this, we will use the Netron visualizer:" - ] - }, - { - "cell_type": "code", - "execution_count": null, - "metadata": {}, - "outputs": [], - "source": [ - "showInNetron('/tmp/LFCW1A1.onnx')" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "When running this notebook in the FINN Docker container, you should be able to see an interactive visualization of the imported network above, and click on individual nodes to inspect their parameters. If you look at any of the MatMul nodes, you should be able to see that the weights are all {-1, +1} values, and the activations are Sign functions." - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "## 3. Import into FINN and call cleanup transformations\n", - "\n", - "We will now import this ONNX model into FINN using the ModelWrapper, and examine some of the graph attributes from Python." - ] - }, - { - "cell_type": "code", - "execution_count": null, - "metadata": {}, - "outputs": [], - "source": [ - "from qonnx.core.modelwrapper import ModelWrapper\n", - "model = ModelWrapper(export_onnx_path)\n", - "model.graph.node[8]" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "The ModelWrapper exposes a range of other useful functions as well. For instance, by convention the second input of the MatMul node will be a pre-initialized weight tensor, which we can view using the following:" - ] - }, - { - "cell_type": "code", - "execution_count": null, - "metadata": {}, - "outputs": [], - "source": [ - "model.get_initializer(model.graph.node[8].input[1])" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "We can also examine the quantization annotations and shapes of various tensors using the convenience functions provided by ModelWrapper." - ] - }, - { - "cell_type": "code", - "execution_count": null, - "metadata": {}, - "outputs": [], - "source": [ - "model.get_tensor_datatype(model.graph.node[8].input[1]).name" - ] - }, - { - "cell_type": "code", - "execution_count": null, - "metadata": {}, - "outputs": [], - "source": [ - "model.get_tensor_shape(model.graph.node[8].input[1])" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "If we want to operate further on this model in FINN, it is a good idea to execute certain \"cleanup\" transformations on this graph. Here, we will run shape inference and constant folding on this graph, and visualize the resulting graph in Netron again." - ] - }, - { - "cell_type": "code", - "execution_count": null, - "metadata": {}, - "outputs": [], - "source": [ - "from qonnx.transformation.fold_constants import FoldConstants\n", - "from qonnx.transformation.infer_shapes import InferShapes\n", - "model = model.transform(InferShapes())\n", - "model = model.transform(FoldConstants())\n", - "export_onnx_path_transformed = \"/tmp/LFCW1A1-clean.onnx\"\n", - "model.save(export_onnx_path_transformed)" - ] - }, - { - "cell_type": "code", - "execution_count": null, - "metadata": {}, - "outputs": [], - "source": [ - "showInNetron('/tmp/LFCW1A1-clean.onnx')" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "We can see that the resulting graph has become smaller and simpler. Specifically, the input reshaping is now a single Reshape node instead of the Shape -> Gather -> Unsqueeze -> Concat -> Reshape sequence. We can now use the internal ONNX execution capabilities of FINN to ensure that we still get the same output from this model as we did with PyTorch." - ] - }, - { - "cell_type": "code", - "execution_count": null, - "metadata": {}, - "outputs": [], - "source": [ - "import finn.core.onnx_exec as oxe\n", - "input_dict = {\"0\": nph.to_array(input_tensor)}\n", - "output_dict = oxe.execute_onnx(model, input_dict)\n", - "produced_finn = output_dict[list(output_dict.keys())[0]]\n", - "\n", - "produced_finn" - ] - }, - { - "cell_type": "code", - "execution_count": null, - "metadata": {}, - "outputs": [], - "source": [ - "np.isclose(produced, produced_finn).all()" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "We have succesfully verified that the transformed and cleaned-up FINN graph still produces the same output, and can now use this model for further processing in FINN." - ] - } - ], - "metadata": { - "kernelspec": { - "display_name": "Python 3", - "language": "python", - "name": "python3" - }, - "language_info": { - "codemirror_mode": { - "name": "ipython", - "version": 3 - }, - "file_extension": ".py", - "mimetype": "text/x-python", - "name": "python", - "nbconvert_exporter": "python", - "pygments_lexer": "ipython3", - "version": "3.8.5" - } - }, - "nbformat": 4, - "nbformat_minor": 2 -} diff --git a/notebooks/basics/1a_brevitas_network_import_via_FINN-ONNX.ipynb b/notebooks/basics/1a_brevitas_network_import_via_FINN-ONNX.ipynb new file mode 100644 index 0000000000..9f28459f77 --- /dev/null +++ b/notebooks/basics/1a_brevitas_network_import_via_FINN-ONNX.ipynb @@ -0,0 +1,882 @@ +{ + "cells": [ + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "# Importing Brevitas networks into FINN with the FINN-ONNX interchange format\n", + "\n", + "In this notebook we'll go through an example of how to import a Brevitas-trained QNN into FINN. The steps will be as follows:\n", + "\n", + "1. Load up the trained PyTorch model\n", + "2. Call Brevitas FINN-ONNX export and visualize with Netron\n", + "3. Import into FINN and call cleanup transformations\n", + "\n", + "We'll use the following utility functions to print the source code for function calls (`showSrc()`) and to visualize a network using netron (`showInNetron()`) in the Jupyter notebook:" + ] + }, + { + "cell_type": "code", + "execution_count": 1, + "metadata": {}, + "outputs": [], + "source": [ + "import onnx\n", + "from finn.util.visualization import showSrc, showInNetron" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "## 1. Load up the trained PyTorch model\n", + "\n", + "The FINN Docker image comes with several [example Brevitas networks](https://github.com/Xilinx/brevitas/tree/master/src/brevitas_examples/bnn_pynq), and we'll use the LFC-w1a1 model as the example network here. This is a binarized fully connected network trained on the MNIST dataset. Let's start by looking at what the PyTorch network definition looks like:" + ] + }, + { + "cell_type": "code", + "execution_count": 2, + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "# MIT License\n", + "#\n", + "# Copyright (c) 2019 Xilinx\n", + "#\n", + "# Permission is hereby granted, free of charge, to any person obtaining a copy\n", + "# of this software and associated documentation files (the \"Software\"), to deal\n", + "# in the Software without restriction, including without limitation the rights\n", + "# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n", + "# copies of the Software, and to permit persons to whom the Software is\n", + "# furnished to do so, subject to the following conditions:\n", + "#\n", + "# The above copyright notice and this permission notice shall be included in all\n", + "# copies or substantial portions of the Software.\n", + "#\n", + "# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n", + "# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n", + "# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n", + "# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n", + "# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n", + "# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n", + "# SOFTWARE.\n", + "\n", + "import ast\n", + "from functools import reduce\n", + "from operator import mul\n", + "\n", + "from torch.nn import Module, ModuleList, BatchNorm1d, Dropout\n", + "import torch\n", + "\n", + "from brevitas.nn import QuantIdentity, QuantLinear\n", + "from .common import CommonWeightQuant, CommonActQuant\n", + "from .tensor_norm import TensorNorm\n", + "\n", + "DROPOUT = 0.2\n", + "\n", + "\n", + "class FC(Module):\n", + "\n", + " def __init__(\n", + " self,\n", + " num_classes,\n", + " weight_bit_width,\n", + " act_bit_width,\n", + " in_bit_width,\n", + " in_channels,\n", + " out_features,\n", + " in_features=(28, 28)):\n", + " super(FC, self).__init__()\n", + "\n", + " self.features = ModuleList()\n", + " self.features.append(QuantIdentity(act_quant=CommonActQuant, bit_width=in_bit_width))\n", + " self.features.append(Dropout(p=DROPOUT))\n", + " in_features = reduce(mul, in_features)\n", + " for out_features in out_features:\n", + " self.features.append(QuantLinear(\n", + " in_features=in_features,\n", + " out_features=out_features,\n", + " bias=False,\n", + " weight_bit_width=weight_bit_width,\n", + " weight_quant=CommonWeightQuant))\n", + " in_features = out_features\n", + " self.features.append(BatchNorm1d(num_features=in_features))\n", + " self.features.append(QuantIdentity(act_quant=CommonActQuant, bit_width=act_bit_width))\n", + " self.features.append(Dropout(p=DROPOUT))\n", + " self.features.append(QuantLinear(\n", + " in_features=in_features,\n", + " out_features=num_classes,\n", + " bias=False,\n", + " weight_bit_width=weight_bit_width,\n", + " weight_quant=CommonWeightQuant))\n", + " self.features.append(TensorNorm())\n", + "\n", + " for m in self.modules():\n", + " if isinstance(m, QuantLinear):\n", + " torch.nn.init.uniform_(m.weight.data, -1, 1)\n", + "\n", + " def clip_weights(self, min_val, max_val):\n", + " for mod in self.features:\n", + " if isinstance(mod, QuantLinear):\n", + " mod.weight.data.clamp_(min_val, max_val)\n", + " \n", + " def forward(self, x):\n", + " x = x.view(x.shape[0], -1)\n", + " x = 2.0 * x - torch.tensor([1.0], device=x.device)\n", + " for mod in self.features:\n", + " x = mod(x)\n", + " return x\n", + "\n", + "\n", + "def fc(cfg):\n", + " weight_bit_width = cfg.getint('QUANT', 'WEIGHT_BIT_WIDTH')\n", + " act_bit_width = cfg.getint('QUANT', 'ACT_BIT_WIDTH')\n", + " in_bit_width = cfg.getint('QUANT', 'IN_BIT_WIDTH')\n", + " num_classes = cfg.getint('MODEL', 'NUM_CLASSES')\n", + " in_channels = cfg.getint('MODEL', 'IN_CHANNELS')\n", + " out_features = ast.literal_eval(cfg.get('MODEL', 'OUT_FEATURES'))\n", + " net = FC(\n", + " weight_bit_width=weight_bit_width,\n", + " act_bit_width=act_bit_width,\n", + " in_bit_width=in_bit_width,\n", + " in_channels=in_channels,\n", + " out_features=out_features,\n", + " num_classes=num_classes)\n", + " return net\n", + "\n" + ] + } + ], + "source": [ + "from brevitas_examples import bnn_pynq\n", + "showSrc(bnn_pynq.models.FC)" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "We can see that the network topology is constructed using a few helper functions that generate the quantized linear layers and quantized activations. The bitwidth of the layers is actually parametrized in the constructor, so let's instantiate a 1-bit weights and activations version of this network. We also have pretrained weights for this network, which we will load into the model." + ] + }, + { + "cell_type": "code", + "execution_count": 3, + "metadata": {}, + "outputs": [ + { + "data": { + "text/plain": [ + "FC(\n", + " (features): ModuleList(\n", + " (0): QuantIdentity(\n", + " (input_quant): ActQuantProxyFromInjector(\n", + " (_zero_hw_sentinel): StatelessBuffer()\n", + " )\n", + " (act_quant): ActQuantProxyFromInjector(\n", + " (_zero_hw_sentinel): StatelessBuffer()\n", + " (fused_activation_quant_proxy): FusedActivationQuantProxy(\n", + " (activation_impl): Identity()\n", + " (tensor_quant): ClampedBinaryQuant(\n", + " (scaling_impl): ConstScaling(\n", + " (restrict_clamp_scaling): _RestrictClampValue(\n", + " (clamp_min_ste): Identity()\n", + " (restrict_value_impl): FloatRestrictValue()\n", + " )\n", + " (value): StatelessBuffer()\n", + " )\n", + " (bit_width): BitWidthConst(\n", + " (bit_width): StatelessBuffer()\n", + " )\n", + " (zero_point): StatelessBuffer()\n", + " (delay_wrapper): DelayWrapper(\n", + " (delay_impl): _NoDelay()\n", + " )\n", + " (tensor_clamp_impl): TensorClamp()\n", + " )\n", + " )\n", + " )\n", + " )\n", + " (1): Dropout(p=0.2, inplace=False)\n", + " (2): QuantLinear(\n", + " in_features=784, out_features=1024, bias=False\n", + " (input_quant): ActQuantProxyFromInjector(\n", + " (_zero_hw_sentinel): StatelessBuffer()\n", + " )\n", + " (output_quant): ActQuantProxyFromInjector(\n", + " (_zero_hw_sentinel): StatelessBuffer()\n", + " )\n", + " (weight_quant): WeightQuantProxyFromInjector(\n", + " (_zero_hw_sentinel): StatelessBuffer()\n", + " (tensor_quant): BinaryQuant(\n", + " (scaling_impl): ConstScaling(\n", + " (restrict_clamp_scaling): _RestrictClampValue(\n", + " (clamp_min_ste): Identity()\n", + " (restrict_value_impl): FloatRestrictValue()\n", + " )\n", + " (value): StatelessBuffer()\n", + " )\n", + " (bit_width): BitWidthConst(\n", + " (bit_width): StatelessBuffer()\n", + " )\n", + " (zero_point): StatelessBuffer()\n", + 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StatelessBuffer()\n", + " )\n", + " (bit_width): BitWidthConst(\n", + " (bit_width): StatelessBuffer()\n", + " )\n", + " (zero_point): StatelessBuffer()\n", + " (delay_wrapper): DelayWrapper(\n", + " (delay_impl): _NoDelay()\n", + " )\n", + " (tensor_clamp_impl): TensorClamp()\n", + " )\n", + " )\n", + " )\n", + " )\n", + " (9): Dropout(p=0.2, inplace=False)\n", + " (10): QuantLinear(\n", + " in_features=1024, out_features=1024, bias=False\n", + " (input_quant): ActQuantProxyFromInjector(\n", + " (_zero_hw_sentinel): StatelessBuffer()\n", + " )\n", + " (output_quant): ActQuantProxyFromInjector(\n", + " (_zero_hw_sentinel): StatelessBuffer()\n", + " )\n", + " (weight_quant): WeightQuantProxyFromInjector(\n", + " (_zero_hw_sentinel): StatelessBuffer()\n", + " (tensor_quant): BinaryQuant(\n", + " (scaling_impl): ConstScaling(\n", + " (restrict_clamp_scaling): _RestrictClampValue(\n", + " (clamp_min_ste): Identity()\n", + " (restrict_value_impl): FloatRestrictValue()\n", + " )\n", + " (value): StatelessBuffer()\n", + " )\n", + " (bit_width): BitWidthConst(\n", + " (bit_width): StatelessBuffer()\n", + " )\n", + " (zero_point): StatelessBuffer()\n", + " (delay_wrapper): DelayWrapper(\n", + " (delay_impl): _NoDelay()\n", + " )\n", + " )\n", + " )\n", + " (bias_quant): BiasQuantProxyFromInjector(\n", + " (_zero_hw_sentinel): StatelessBuffer()\n", + " )\n", + " )\n", + " (11): BatchNorm1d(1024, eps=1e-05, momentum=0.1, affine=True, track_running_stats=True)\n", + " (12): QuantIdentity(\n", + " (input_quant): ActQuantProxyFromInjector(\n", + " (_zero_hw_sentinel): StatelessBuffer()\n", + " )\n", + " (act_quant): ActQuantProxyFromInjector(\n", + " (_zero_hw_sentinel): StatelessBuffer()\n", + " (fused_activation_quant_proxy): FusedActivationQuantProxy(\n", + " (activation_impl): Identity()\n", + " (tensor_quant): ClampedBinaryQuant(\n", + " (scaling_impl): ConstScaling(\n", + " (restrict_clamp_scaling): _RestrictClampValue(\n", + " (clamp_min_ste): Identity()\n", + " (restrict_value_impl): FloatRestrictValue()\n", + " )\n", + " (value): StatelessBuffer()\n", + " )\n", + " (bit_width): BitWidthConst(\n", + " (bit_width): StatelessBuffer()\n", + " )\n", + " (zero_point): StatelessBuffer()\n", + " (delay_wrapper): DelayWrapper(\n", + " (delay_impl): _NoDelay()\n", + " )\n", + " (tensor_clamp_impl): TensorClamp()\n", + " )\n", + " )\n", + " )\n", + " )\n", + " (13): Dropout(p=0.2, inplace=False)\n", + " (14): QuantLinear(\n", + " in_features=1024, out_features=10, bias=False\n", + " (input_quant): ActQuantProxyFromInjector(\n", + " (_zero_hw_sentinel): StatelessBuffer()\n", + " )\n", + " (output_quant): ActQuantProxyFromInjector(\n", + " (_zero_hw_sentinel): StatelessBuffer()\n", + " )\n", + " (weight_quant): WeightQuantProxyFromInjector(\n", + " (_zero_hw_sentinel): StatelessBuffer()\n", + " (tensor_quant): BinaryQuant(\n", + " (scaling_impl): ConstScaling(\n", + " (restrict_clamp_scaling): _RestrictClampValue(\n", + " (clamp_min_ste): Identity()\n", + " (restrict_value_impl): FloatRestrictValue()\n", + " )\n", + " (value): StatelessBuffer()\n", + " )\n", + " (bit_width): BitWidthConst(\n", + " (bit_width): StatelessBuffer()\n", + " )\n", + " (zero_point): StatelessBuffer()\n", + " (delay_wrapper): DelayWrapper(\n", + " (delay_impl): _NoDelay()\n", + " )\n", + " )\n", + " )\n", + " (bias_quant): BiasQuantProxyFromInjector(\n", + " (_zero_hw_sentinel): StatelessBuffer()\n", + " )\n", + " )\n", + " (15): TensorNorm()\n", + " )\n", + ")" + ] + }, + "execution_count": 3, + "metadata": {}, + "output_type": "execute_result" + } + ], + "source": [ + "from finn.util.test import get_test_model\n", + "lfc = get_test_model(netname = \"LFC\", wbits = 1, abits = 1, pretrained = True)\n", + "lfc" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "We have now instantiated our trained PyTorch network. Let's try to run an example MNIST image through the network using PyTorch." + ] + }, + { + "cell_type": "code", + "execution_count": 4, + "metadata": {}, + "outputs": [ + { + "name": "stderr", + "output_type": "stream", + "text": [ + ":9: UserWarning: The given NumPy array is not writeable, and PyTorch does not support non-writeable tensors. This means you can write to the underlying (supposedly non-writeable) NumPy array using the tensor. You may want to copy the array to protect its data or make it writeable before converting it to a tensor. This type of warning will be suppressed for the rest of this program. (Triggered internally at /opt/conda/conda-bld/pytorch_1607370172916/work/torch/csrc/utils/tensor_numpy.cpp:141.)\n", + " input_tensor_pyt = torch.from_numpy(input_tensor_npy).float()\n" + ] + }, + { + "data": { + "image/png": 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v3f2fhqnPkvSiu/9J4noIO1CzlifC2ODyoI9K+nBo0Is37k77gaQNVQcJoD4jeTd+gaTXJa2XdHpt3p9KukHSXA0+jf9U0i3Fm3nRdfHIDtSs0tP4diHsQP2Yzw5kjrADmSDsQCYIO5AJwg5kgrADmSDsQCYIO5AJwg5kgrADmSDsQCYIO5AJwg5kgrADmUguONlmeyRtHfL91OKybtStY+vWcUmMrVXtHNsFZYWOzmf/2o2brXX3eY0NINCtY+vWcUmMrVWdGhtP44FMEHYgE02HfUXDtx/p1rF167gkxtaqjoyt0dfsADqn6Ud2AB1C2IFMNBJ2M7vSzP7XzD4ys7uaGEMZM/vUzNYX21A3uj9dsYfeLjPbMOSyKWb2ipltLj4Pu8deQ2Prim28g23GG73vmt7+vOOv2c2sR9ImSX8paZukdyTd4O4bOzqQEmb2qaR57t74CRhmtlDSQUmrTm+tZWb/KGmvu99X/Ec52d3/rkvGtlx/4DbeNY2tbJvxv1aD9107tz9vRROP7PMlfeTuW9z9uKSnJS1pYBxdz91fk7T3KxcvkbSy+HqlBv9YOq5kbF3B3fvd/b3i6wOSTm8z3uh9F4yrI5oI+wxJvxvy/TZ1137vLuk3ZvaumS1rejDDmDZkm60dkqY1OZhhJLfx7qSvbDPeNfddK9ufV8UbdF+3wN3/TNL3Jf24eLralXzwNVg39U5/JunbGtwDsF/SQ00OpthmfI2k2919/9Bak/fdMOPqyP3WRNi3SzpvyPczi8u6grtvLz7vkvSsBl92dJOdp3fQLT7vang8X3L3ne4+4O6nJP1cDd53xTbjayT9wt2fKS5u/L4bblydut+aCPs7kmab2bfM7ExJP5T0fAPj+BozG1+8cSIzGy/pCnXfVtTPS7qp+PomSb9qcCy/p1u28S7bZlwN33eNb3/u7h3/kHSVBt+R/1jS3zcxhpJxXSjpv4uPD5oem6SnNPi07oQG39v4kaSzJb0qabOk/5A0pYvG9m8a3Nr7fQ0Ga3pDY1ugwafo70taV3xc1fR9F4yrI/cbp8sCmeANOiAThB3IBGEHMkHYgUwQdiAThB3IBGEHMvF/rSIwqVQD1iIAAAAASUVORK5CYII=\n", + "text/plain": [ + "
" + ] + }, + "metadata": { + "needs_background": "light" + }, + "output_type": "display_data" + } + ], + "source": [ + "import torch\n", + "import matplotlib.pyplot as plt\n", + "from pkgutil import get_data\n", + "import onnx\n", + "import onnx.numpy_helper as nph\n", + "raw_i = get_data(\"qonnx.data\", \"onnx/mnist-conv/test_data_set_0/input_0.pb\")\n", + "input_tensor = onnx.load_tensor_from_string(raw_i)\n", + "input_tensor_npy = nph.to_array(input_tensor)\n", + "input_tensor_pyt = torch.from_numpy(input_tensor_npy).float()\n", + "imgplot = plt.imshow(input_tensor_npy.reshape(28,28), cmap='gray')" + ] + }, + { + "cell_type": "code", + "execution_count": 5, + "metadata": {}, + "outputs": [ + { + "data": { + "text/plain": [ + "tensor([0.1020, 0.0113, 0.4806, 0.0571, 0.0482, 0.0079, 0.0450, 0.0076, 0.1851,\n", + " 0.0552])" + ] + }, + "execution_count": 5, + "metadata": {}, + "output_type": "execute_result" + } + ], + "source": [ + "from torch.nn.functional import softmax\n", + "# do forward pass in PyTorch/Brevitas\n", + "produced = lfc.forward(input_tensor_pyt).detach()\n", + "probabilities = softmax(produced, dim=-1).flatten()\n", + "probabilities" + ] + }, + { + "cell_type": "code", + "execution_count": 6, + "metadata": {}, + "outputs": [ + { + "data": { + "image/png": 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5ZcqUmuEjIqKOOlcNfQ04BLgSuAo4WNIxNY59KbCFpE0kTQT2BeYOO/YWPbN/A1xfN/GIiFg+6vQR7Az8hW0DSDoJmD/aTrYXS5oNnAtMAE6wPV/SUcA823OB2ZJ2BR4HHgDesZTvIyIillKdQrAA2Ai4pcxvWJaNyvY5DBuXyPZHe6YPq5dmREQ0ZdCgc9+jupxzEnCNpEvKqm2BS0baLyIiViyDzgg+31oWERExZgYNOnfR0LSk5wIvL7OX2L6n6cQiIqIdda4a2oeqKehNwD7AxZL2bjqxiIhoR53O4g8DLx86C5A0BbgAOLPJxCIioh11bihbaVhT0H0194uIiBVAnTOCH0o6lz89sD6PqoyIGEcGFgJJAr5M1VH8qrL4WNtnN51YRES0Y2AhsG1J59h+EXBWSzlFRESL6rT1Xy7p5aNvFhERK6I6fQTbAW+VdDPwCCCqk4UXN5lYRES0o04h+KvGs4iIiDEzaKyh5wAfAjanGoL608MeLRkREePAoD6Cb1E1BX0FWJPq6qGIiBhnBjUNrW/7w2X6XEmXt5FQRES0a7T7CNal6hwGmNA7b/v+hnOLiIgWDCoEawOX8adCADB0VmBg06aSioiI9gwahnp6i3lERMQYyeBxEREdl0IQEdFxKQQRER036IayZw/aMVcNRUSMD4OuGrqM6uogARsBD5TpdYBbgU2aTi4iIpo3YtOQ7U1sb0r1WMrX255sez3gdcB5bSUYERHNqtNHsL3tp55IZvsHwA7NpRQREW2qM/roHZKOBE4u828B7mgupYiIaFOdM4L9gCnA2VRPKZtSlkVExDgw6hlBuTroMElr2H6khZwiIqJFo54RSNpB0tXANWX+JZK+1nhmERHRijpNQ0dTPaXsPgDbvwZ2bDKpiIhoT607i23fNmzREw3kEhERY6DOVUO3SdoBsKRVgMMozUQREbHiq3NGcAhwKDAVuB3YGviHBnOKiIgW1Tkj2Mr2W3oXSHol8LNmUoqIiDbVOSP4Ss1lf0bSLEnXSVog6Yg+6w+XdLWk30j6b0kb1zluREQsP4NGH30F1VASUyQd3rNqLWDCaAeWNAE4BtgNWAhcKmmu7at7NvsVMNP2HyT9PfBZ4M1L/jYiImJpDTojmAisSVUsJvW8HgL2rnHsbYEFtm+0/RhwGrBn7wa2f2T7D2X2l8C0JUs/IiKW1aBnFl8EXCTpRNu3LMWxpwK9l50uBLYbsP27gB8sRZyIiFgGdfoIjpe0ztCMpHUlnbs8k5D0VmAm8LkR1h8kaZ6keYsWLVqeoSMiOq9OIZhs+8GhGdsPAM+psd/twIY989PKsqeRtCvwYWAP24/2O5DtY23PtD1zypQpNUJHRERddQrBk5I2GpopV/a4xn6XAltI2kTSRGBfYG7vBpJeCnyDqgjcUz/tiIhYXurcR/Bh4KeSLqJ6VOWrgYNG28n2YkmzgXOprjI6wfZ8SUcB82zPpWoKWhM4QxLArbb3WLq3EhERS6POMNQ/lLQNsH1Z9B7b99Y5eHmy2TnDln20Z3rXJcg1IiIaMGLTkKTnl3+3oXp4/R3ltVFZFhER48CgM4L3AQcCX+izzsDOjWQUEbGUjj7/t43HeO9uWzYeo22D7iM4sPy7U3vpRERE2wYNMbHXoB1tn7X804mIiLYNahp6ffn3OVRjDl1Y5ncCfk71IPuIiFjBDWoaeieApPOAGbbvLPPrAye2kl1ERDSuzg1lGw4VgeJuqquIIiJiHKhzQ9l/l7GFTi3zbwYuaC6liIhoU50bymZL+ltgx7LoWNtnN5tWRES0pc4ZAcDlwMO2L5C0uqRJth9uMrGIiGjHqH0Ekg4EzqQaHA6q5wx8t8GcIiKiRXU6iw8FXkn1ZDJsX0+9YagjImIFUKcQPFoeNQmApJWpNwx1RESsAOoUgoskfQhYTdJuwBnA95pNKyIi2lKnEHwAWARcCRxMNaz0kU0mFRER7Rl41ZCkCcB8288HjmsnpYiIaNPAMwLbTwDX9T6qMiIixpc69xGsC8yXdAnwyNDCPFIyImJ8qFMIPtJ4FhERMWYGPY9gVeAQYHOqjuI5the3lVhERLRjUB/BScBMqiKwO/0fWRkRESu4QU1DM2y/CEDSHOCSdlKKiIg2DTojeHxoIk1CERHj16AzgpdIeqhMi+rO4ofKtG2v1Xh2ERHRuEGPqpzQZiIRETE26gwxERER41gKQUREx6UQRER0XApBRETHpRBERHRcCkFERMelEEREdFwKQUREx6UQRER0XApBRETHNVoIJM2SdJ2kBZKO6LN+R0mXS1osae8mc4mIiP4aKwTlwffHUD3LYAawn6QZwza7FdgfOKWpPCIiYrA6j6pcWtsCC2zfCCDpNGBP4OqhDWzfXNY92WAeTzn6/N82HuO9u23ZeIyIiOWpyaahqcBtPfMLy7IlJukgSfMkzVu0aNFySS4iIiorRGex7WNtz7Q9c8qUKWOdTkTEuNJkIbgd2LBnflpZFhERzyBNFoJLgS0kbSJpIrAvMLfBeBERsRQaKwTlOcezgXOBa4DTbc+XdJSkPQAkvVzSQuBNwDckzW8qn4iI6K/Jq4awfQ5wzrBlH+2ZvpSqySgiIsbICtFZHBERzUkhiIjouBSCiIiOSyGIiOi4FIKIiI5LIYiI6LgUgoiIjkshiIjouBSCiIiOSyGIiOi4FIKIiI5LIYiI6LhGB52LyONBI575UggiIpaDFflHT5qGIiI6LoUgIqLj0jQU41rTp+vpn4jxIIUgYhxKAYwlkaahiIiOSyGIiOi4FIKIiI5LIYiI6LgUgoiIjkshiIjouBSCiIiOSyGIiOi4FIKIiI5LIYiI6LgUgoiIjkshiIjouBSCiIiOSyGIiOi4DEPdkhX5MXYRMb6lEEQ0JM8EiBVFo4VA0izg34AJwPG2PzNs/bOAbwEvA+4D3mz75iZziohm5ex3xdNYH4GkCcAxwO7ADGA/STOGbfYu4AHbmwNHA//aVD4REdFfk53F2wILbN9o+zHgNGDPYdvsCZxUps8EdpGkBnOKiIhhZLuZA0t7A7NsH1Dm3wZsZ3t2zzZXlW0Wlvkbyjb3DjvWQcBBZXYr4LpGku5vMnDvqFsldmIndmI/s2NvbHtKvxUrRGex7WOBY8citqR5tmcmdmIndmKPl9jDNdk0dDuwYc/8tLKs7zaSVgbWpuo0joiIljRZCC4FtpC0iaSJwL7A3GHbzAXeUab3Bi50U21VERHRV2NNQ7YXS5oNnEt1+egJtudLOgqYZ3suMAf4tqQFwP1UxeKZZkyapBI7sRM7sdvSWGdxRESsGDLWUEREx6UQRER0XArBCCTNknSdpAWSjmg59gmS7in3WbQZd0NJP5J0taT5kg5rMfaqki6R9OsS++Ntxe7JYYKkX0n6/hjEvlnSlZKukDSv5djrSDpT0rWSrpH0ipbiblXe79DrIUnvaSN2if/e8t/aVZJOlbRqi7EPK3Hnt/meR2Q7r2Evqs7tG4BNgYnAr4EZLcbfEdgGuKrl970+sE2ZngT8tq33DQhYs0yvAlwMbN/y+z8cOAX4fptxS+ybgcltxy2xTwIOKNMTgXXGIIcJwF1UNz21EW8qcBOwWpk/Hdi/pdgvBK4CVqe6YOcCYPOx+NsPvXJG0F+d4TEaY/t/qK6iapXtO21fXqYfBq6h+h+mjdi2/fsyu0p5tXYlg6RpwN8Ax7cV85lA0tpUPzzmANh+zPaDY5DKLsANtm9pMebKwGrlHqbVgTtaivsXwMW2/2B7MXARsFdLsftKIehvKnBbz/xCWvpCfKaQNB14KdUv87ZiTpB0BXAPcL7t1mIDXwL+CXiyxZi9DJwn6bIypEpbNgEWAd8szWLHS1qjxfhD9gVObSuY7duBzwO3AncCv7N9XkvhrwJeLWk9SasDf83Tb75tXQpB/BlJawLfAd5j+6G24tp+wvbWVHehbyvphW3ElfQ64B7bl7URbwSvsr0N1Wi9h0rasaW4K1M1Q/677ZcCjwBt94lNBPYAzmgx5rpUZ/mbABsAa0h6axuxbV9DNdLyecAPgSuAJ9qIPZIUgv7qDI8xLklahaoI/Ifts8Yih9I08SNgVkshXwnsIelmqmbAnSWd3FJs4KlfqNi+BzibqnmyDQuBhT1nX2dSFYY27Q5cbvvuFmPuCtxke5Htx4GzgB3aCm57ju2X2d4ReICqP27MpBD0V2d4jHGnDAE+B7jG9hdbjj1F0jplejVgN+DaNmLb/qDtabanU/2tL7Tdyq9DAElrSJo0NA38JVXzQeNs3wXcJmmrsmgX4Oo2YvfYjxabhYpbge0lrV7+u9+Fqk+sFZKeU/7diKp/4JS2YvezQow+2jaPMDxGW/ElnQq8FpgsaSHwMdtzWgj9SuBtwJWlrR7gQ7bPaSH2+sBJ5YFGKwGn2279Ms4x8lzg7PIojpWBU2z/sMX47wb+o/zouRF4Z1uBS+HbDTi4rZgAti+WdCZwObAY+BXtDvnwHUnrAY8Dh45RB/1TMsRERETHpWkoIqLjUggiIjouhSAiouNSCCIiOi6FICKi41IIIiI6LoUgIqLj/hdRB2LXFx7MKAAAAABJRU5ErkJggg==\n", + "text/plain": [ + "
" + ] + }, + "metadata": { + "needs_background": "light" + }, + "output_type": "display_data" + } + ], + "source": [ + "import numpy as np\n", + "objects = [str(x) for x in range(10)]\n", + "y_pos = np.arange(len(objects))\n", + "plt.bar(y_pos, probabilities, align='center', alpha=0.5)\n", + "plt.xticks(y_pos, objects)\n", + "plt.ylabel('Predicted Probability')\n", + "plt.title('LFC-w1a1 Predictions for Image')\n", + "plt.show()" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "## 2. Call Brevitas FINN-ONNX export and visualize with Netron\n", + "\n", + "Brevitas comes with built-in FINN-ONNX export functionality. This is similar to the regular ONNX export capabilities of PyTorch, with a few differences:\n", + "\n", + "1. The weight quantization logic is not exported as part of the graph; rather, the quantized weights themselves are exported.\n", + "2. Special quantization annotations are used to preserve the low-bit quantization information. ONNX (at the time of writing) supports 8-bit quantization as the minimum bitwidth, whereas FINN-ONNX quantization annotations can go down to binary/bipolar quantization.\n", + "3. Low-bit quantized activation functions are exported as MultiThreshold operators.\n", + "\n", + "It's actually quite straightforward to export ONNX from our Brevitas model as follows:" + ] + }, + { + "cell_type": "code", + "execution_count": 7, + "metadata": {}, + "outputs": [], + "source": [ + "import brevitas.onnx as bo\n", + "export_onnx_path = \"/tmp/LFCW1A1_finn-onnx.onnx\"\n", + "input_shape = (1, 1, 28, 28)\n", + "bo.export_finn_onnx(lfc, input_shape, export_onnx_path);" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "Let's examine what the exported ONNX model looks like. For this, we will use the Netron visualizer:" + ] + }, + { + "cell_type": "code", + "execution_count": 8, + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "Serving '/tmp/LFCW1A1_finn-onnx.onnx' at http://0.0.0.0:8081\n" + ] + }, + { + "data": { + "text/html": [ + "\n", + " \n", + " " + ], + "text/plain": [ + "" + ] + }, + "execution_count": 8, + "metadata": {}, + "output_type": "execute_result" + } + ], + "source": [ + "showInNetron(export_onnx_path)" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "When running this notebook in the FINN Docker container, you should be able to see an interactive visualization of the imported network above, and click on individual nodes to inspect their parameters. If you look at any of the MatMul nodes, you should be able to see that the weights are all {-1, +1} values, and the activations are Sign functions." + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "## 3. Import into FINN and call cleanup transformations\n", + "\n", + "We will now import this ONNX model into FINN using the ModelWrapper, and examine some of the graph attributes from Python." + ] + }, + { + "cell_type": "code", + "execution_count": 9, + "metadata": {}, + "outputs": [ + { + "name": "stderr", + "output_type": "stream", + "text": [ + "/home/hendrik/Dropbox/a_local/Uni/fpga_synth_system_data/finn_deving/finn/deps/qonnx/src/qonnx/core/modelwrapper.py:93: UserWarning: Some old-style domain attributes were automatically converted to new-style,\n", + " i.e. domain=finn to domain=qonnx.custom_op.\n", + " warnings.warn(\n" + ] + }, + { + "data": { + "text/plain": [ + "input: \"37\"\n", + "input: \"38\"\n", + "output: \"39\"\n", + "name: \"MatMul_13\"\n", + "op_type: \"MatMul\"\n", + "domain: \"\"" + ] + }, + "execution_count": 9, + "metadata": {}, + "output_type": "execute_result" + } + ], + "source": [ + "from qonnx.core.modelwrapper import ModelWrapper\n", + "model = ModelWrapper(export_onnx_path)\n", + "model.graph.node[8]" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "The ModelWrapper exposes a range of other useful functions as well. For instance, by convention the second input of the MatMul node will be a pre-initialized weight tensor, which we can view using the following:" + ] + }, + { + "cell_type": "code", + "execution_count": 10, + "metadata": {}, + "outputs": [ + { + "data": { + "text/plain": [ + "array([[-1., -1., 1., ..., -1., 1., -1.],\n", + " [ 1., 1., -1., ..., 1., -1., 1.],\n", + " [-1., -1., -1., ..., 1., -1., 1.],\n", + " ...,\n", + " [ 1., -1., -1., ..., -1., -1., 1.],\n", + " [ 1., -1., -1., ..., 1., 1., 1.],\n", + " [ 1., -1., 1., ..., 1., -1., 1.]], dtype=float32)" + ] + }, + "execution_count": 10, + "metadata": {}, + "output_type": "execute_result" + } + ], + "source": [ + "model.get_initializer(model.graph.node[8].input[1])" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "We can also examine the quantization annotations and shapes of various tensors using the convenience functions provided by ModelWrapper." + ] + }, + { + "cell_type": "code", + "execution_count": 11, + "metadata": {}, + "outputs": [ + { + "data": { + "text/plain": [ + "'BIPOLAR'" + ] + }, + "execution_count": 11, + "metadata": {}, + "output_type": "execute_result" + } + ], + "source": [ + "model.get_tensor_datatype(model.graph.node[8].input[1]).name" + ] + }, + { + "cell_type": "code", + "execution_count": 12, + "metadata": {}, + "outputs": [ + { + "data": { + "text/plain": [ + "[784, 1024]" + ] + }, + "execution_count": 12, + "metadata": {}, + "output_type": "execute_result" + } + ], + "source": [ + "model.get_tensor_shape(model.graph.node[8].input[1])" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "If we want to operate further on this model in FINN, it is a good idea to execute certain \"cleanup\" transformations on this graph. Here, we will run shape inference and constant folding on this graph, and visualize the resulting graph in Netron again." + ] + }, + { + "cell_type": "code", + "execution_count": 13, + "metadata": {}, + "outputs": [], + "source": [ + "from qonnx.transformation.fold_constants import FoldConstants\n", + "from qonnx.transformation.infer_shapes import InferShapes\n", + "model = model.transform(InferShapes())\n", + "model = model.transform(FoldConstants())\n", + "export_onnx_path_transformed = \"/tmp/LFCW1A1-finn-onnx-clean.onnx\"\n", + "model.save(export_onnx_path_transformed)" + ] + }, + { + "cell_type": "code", + "execution_count": 14, + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "Stopping http://0.0.0.0:8081\n", + "Serving '/tmp/LFCW1A1-finn-onnx-clean.onnx' at http://0.0.0.0:8081\n" + ] + }, + { + "data": { + "text/html": [ + "\n", + " \n", + " " + ], + "text/plain": [ + "" + ] + }, + "execution_count": 14, + "metadata": {}, + "output_type": "execute_result" + } + ], + "source": [ + "showInNetron(export_onnx_path_transformed)" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "We can see that the resulting graph has become smaller and simpler. Specifically, the input reshaping is now a single Reshape node instead of the Shape -> Gather -> Unsqueeze -> Concat -> Reshape sequence. We can now use the internal ONNX execution capabilities of FINN to ensure that we still get the same output from this model as we did with PyTorch." + ] + }, + { + "cell_type": "code", + "execution_count": 15, + "metadata": {}, + "outputs": [ + { + "data": { + "text/plain": [ + "array([[-1.3736125, -3.5715756, 0.1768887, -1.9529207, -2.1233053,\n", + " -3.9293835, -2.1914592, -3.9634604, -0.7772659, -1.9869976]],\n", + " dtype=float32)" + ] + }, + "execution_count": 15, + "metadata": {}, + "output_type": "execute_result" + } + ], + "source": [ + "import finn.core.onnx_exec as oxe\n", + "input_dict = {\"0\": nph.to_array(input_tensor)}\n", + "output_dict = oxe.execute_onnx(model, input_dict)\n", + "produced_finn = output_dict[list(output_dict.keys())[0]]\n", + "\n", + "produced_finn" + ] + }, + { + "cell_type": "code", + "execution_count": 16, + "metadata": {}, + "outputs": [ + { + "data": { + "text/plain": [ + "True" + ] + }, + "execution_count": 16, + "metadata": {}, + "output_type": "execute_result" + } + ], + "source": [ + "np.isclose(produced, produced_finn).all()" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "We have succesfully verified that the transformed and cleaned-up FINN graph still produces the same output, and can now use this model for further processing in FINN." + ] + } + ], + "metadata": { + "kernelspec": { + "display_name": "Python 3", + "language": "python", + "name": "python3" + }, + "language_info": { + "codemirror_mode": { + "name": "ipython", + "version": 3 + }, + "file_extension": ".py", + "mimetype": "text/x-python", + "name": "python", + "nbconvert_exporter": "python", + "pygments_lexer": "ipython3", + "version": "3.8.5" + } + }, + "nbformat": 4, + "nbformat_minor": 2 +} From 6d4e0f04b39bad87d99bcdb1557e90ed23d6d0b7 Mon Sep 17 00:00:00 2001 From: Hendrik Borras Date: Thu, 8 Sep 2022 12:26:21 +0200 Subject: [PATCH 003/665] Remove cell execution --- ...revitas_network_import_via_FINN-ONNX.ipynb | 623 +----------------- 1 file changed, 31 insertions(+), 592 deletions(-) diff --git a/notebooks/basics/1a_brevitas_network_import_via_FINN-ONNX.ipynb b/notebooks/basics/1a_brevitas_network_import_via_FINN-ONNX.ipynb index 9f28459f77..ed5375fd70 100644 --- a/notebooks/basics/1a_brevitas_network_import_via_FINN-ONNX.ipynb +++ b/notebooks/basics/1a_brevitas_network_import_via_FINN-ONNX.ipynb @@ -6,6 +6,8 @@ "source": [ "# Importing Brevitas networks into FINN with the FINN-ONNX interchange format\n", "\n", + "**Note: This notebook is very similar to the 1b notebook, in that it shows the same concepts for the FINN-ONNX ingestion as 1b does for QONNX.**\n", + "\n", "In this notebook we'll go through an example of how to import a Brevitas-trained QNN into FINN. The steps will be as follows:\n", "\n", "1. Load up the trained PyTorch model\n", @@ -17,7 +19,7 @@ }, { "cell_type": "code", - "execution_count": 1, + "execution_count": null, "metadata": {}, "outputs": [], "source": [ @@ -36,121 +38,9 @@ }, { "cell_type": "code", - "execution_count": 2, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "# MIT License\n", - "#\n", - "# Copyright (c) 2019 Xilinx\n", - "#\n", - "# Permission is hereby granted, free of charge, to any person obtaining a copy\n", - "# of this software and associated documentation files (the \"Software\"), to deal\n", - "# in the Software without restriction, including without limitation the rights\n", - "# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n", - "# copies of the Software, and to permit persons to whom the Software is\n", - "# furnished to do so, subject to the following conditions:\n", - "#\n", - "# The above copyright notice and this permission notice shall be included in all\n", - "# copies or substantial portions of the Software.\n", - "#\n", - "# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n", - "# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n", - "# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n", - "# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n", - "# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n", - "# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n", - "# SOFTWARE.\n", - "\n", - "import ast\n", - "from functools import reduce\n", - "from operator import mul\n", - "\n", - "from torch.nn import Module, ModuleList, BatchNorm1d, Dropout\n", - "import torch\n", - "\n", - "from brevitas.nn import QuantIdentity, QuantLinear\n", - "from .common import CommonWeightQuant, CommonActQuant\n", - "from .tensor_norm import TensorNorm\n", - "\n", - "DROPOUT = 0.2\n", - "\n", - "\n", - "class FC(Module):\n", - "\n", - " def __init__(\n", - " self,\n", - " num_classes,\n", - " weight_bit_width,\n", - " act_bit_width,\n", - " in_bit_width,\n", - " in_channels,\n", - " out_features,\n", - " in_features=(28, 28)):\n", - " super(FC, self).__init__()\n", - "\n", - " self.features = ModuleList()\n", - " self.features.append(QuantIdentity(act_quant=CommonActQuant, bit_width=in_bit_width))\n", - " self.features.append(Dropout(p=DROPOUT))\n", - " in_features = reduce(mul, in_features)\n", - " for out_features in out_features:\n", - " self.features.append(QuantLinear(\n", - " in_features=in_features,\n", - " out_features=out_features,\n", - " bias=False,\n", - " weight_bit_width=weight_bit_width,\n", - " weight_quant=CommonWeightQuant))\n", - " in_features = out_features\n", - " self.features.append(BatchNorm1d(num_features=in_features))\n", - " self.features.append(QuantIdentity(act_quant=CommonActQuant, bit_width=act_bit_width))\n", - " self.features.append(Dropout(p=DROPOUT))\n", - " self.features.append(QuantLinear(\n", - " in_features=in_features,\n", - " out_features=num_classes,\n", - " bias=False,\n", - " weight_bit_width=weight_bit_width,\n", - " weight_quant=CommonWeightQuant))\n", - " self.features.append(TensorNorm())\n", - "\n", - " for m in self.modules():\n", - " if isinstance(m, QuantLinear):\n", - " torch.nn.init.uniform_(m.weight.data, -1, 1)\n", - "\n", - " def clip_weights(self, min_val, max_val):\n", - " for mod in self.features:\n", - " if isinstance(mod, QuantLinear):\n", - " mod.weight.data.clamp_(min_val, max_val)\n", - " \n", - " def forward(self, x):\n", - " x = x.view(x.shape[0], -1)\n", - " x = 2.0 * x - torch.tensor([1.0], device=x.device)\n", - " for mod in self.features:\n", - " x = mod(x)\n", - " return x\n", - "\n", - "\n", - "def fc(cfg):\n", - " weight_bit_width = cfg.getint('QUANT', 'WEIGHT_BIT_WIDTH')\n", - " act_bit_width = cfg.getint('QUANT', 'ACT_BIT_WIDTH')\n", - " in_bit_width = cfg.getint('QUANT', 'IN_BIT_WIDTH')\n", - " num_classes = cfg.getint('MODEL', 'NUM_CLASSES')\n", - " in_channels = cfg.getint('MODEL', 'IN_CHANNELS')\n", - " out_features = ast.literal_eval(cfg.get('MODEL', 'OUT_FEATURES'))\n", - " net = FC(\n", - " weight_bit_width=weight_bit_width,\n", - " act_bit_width=act_bit_width,\n", - " in_bit_width=in_bit_width,\n", - " in_channels=in_channels,\n", - " out_features=out_features,\n", - " num_classes=num_classes)\n", - " return net\n", - "\n" - ] - } - ], + "outputs": [], "source": [ "from brevitas_examples import bnn_pynq\n", "showSrc(bnn_pynq.models.FC)" @@ -165,267 +55,9 @@ }, { "cell_type": "code", - "execution_count": 3, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "data": { - "text/plain": [ - "FC(\n", - " (features): ModuleList(\n", - " (0): QuantIdentity(\n", - " (input_quant): ActQuantProxyFromInjector(\n", - " (_zero_hw_sentinel): StatelessBuffer()\n", - " )\n", - " (act_quant): ActQuantProxyFromInjector(\n", - " (_zero_hw_sentinel): StatelessBuffer()\n", - " (fused_activation_quant_proxy): FusedActivationQuantProxy(\n", - " (activation_impl): Identity()\n", - " (tensor_quant): ClampedBinaryQuant(\n", - " (scaling_impl): ConstScaling(\n", - " (restrict_clamp_scaling): _RestrictClampValue(\n", - " (clamp_min_ste): Identity()\n", - " (restrict_value_impl): FloatRestrictValue()\n", - " )\n", - " (value): StatelessBuffer()\n", - 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" (clamp_min_ste): Identity()\n", - " (restrict_value_impl): FloatRestrictValue()\n", - " )\n", - " (value): StatelessBuffer()\n", - " )\n", - " (bit_width): BitWidthConst(\n", - " (bit_width): StatelessBuffer()\n", - " )\n", - " (zero_point): StatelessBuffer()\n", - " (delay_wrapper): DelayWrapper(\n", - " (delay_impl): _NoDelay()\n", - " )\n", - " (tensor_clamp_impl): TensorClamp()\n", - " )\n", - " )\n", - " )\n", - " )\n", - " (13): Dropout(p=0.2, inplace=False)\n", - " (14): QuantLinear(\n", - " in_features=1024, out_features=10, bias=False\n", - " (input_quant): ActQuantProxyFromInjector(\n", - " (_zero_hw_sentinel): StatelessBuffer()\n", - " )\n", - " (output_quant): ActQuantProxyFromInjector(\n", - " (_zero_hw_sentinel): StatelessBuffer()\n", - " )\n", - " (weight_quant): WeightQuantProxyFromInjector(\n", - " (_zero_hw_sentinel): StatelessBuffer()\n", - " (tensor_quant): BinaryQuant(\n", - " (scaling_impl): ConstScaling(\n", - " (restrict_clamp_scaling): _RestrictClampValue(\n", - " (clamp_min_ste): Identity()\n", - " (restrict_value_impl): FloatRestrictValue()\n", - " )\n", - " (value): StatelessBuffer()\n", - " )\n", - " (bit_width): BitWidthConst(\n", - " (bit_width): StatelessBuffer()\n", - " )\n", - " (zero_point): StatelessBuffer()\n", - " (delay_wrapper): DelayWrapper(\n", - " (delay_impl): _NoDelay()\n", - " )\n", - " )\n", - " )\n", - " (bias_quant): BiasQuantProxyFromInjector(\n", - " (_zero_hw_sentinel): StatelessBuffer()\n", - " )\n", - " )\n", - " (15): TensorNorm()\n", - " )\n", - ")" - ] - }, - "execution_count": 3, - "metadata": {}, - "output_type": "execute_result" - } - ], + "outputs": [], "source": [ "from finn.util.test import get_test_model\n", "lfc = get_test_model(netname = \"LFC\", wbits = 1, abits = 1, pretrained = True)\n", @@ -441,30 +73,9 @@ }, { "cell_type": "code", - "execution_count": 4, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "name": "stderr", - "output_type": "stream", - "text": [ - ":9: UserWarning: The given NumPy array is not writeable, and PyTorch does not support non-writeable tensors. This means you can write to the underlying (supposedly non-writeable) NumPy array using the tensor. You may want to copy the array to protect its data or make it writeable before converting it to a tensor. This type of warning will be suppressed for the rest of this program. (Triggered internally at /opt/conda/conda-bld/pytorch_1607370172916/work/torch/csrc/utils/tensor_numpy.cpp:141.)\n", - " input_tensor_pyt = torch.from_numpy(input_tensor_npy).float()\n" - ] - }, - { - "data": { - "image/png": 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- "text/plain": [ - "
" - ] - }, - "metadata": { - "needs_background": "light" - }, - "output_type": "display_data" - } - ], + "outputs": [], "source": [ "import torch\n", "import matplotlib.pyplot as plt\n", @@ -480,21 +91,9 @@ }, { "cell_type": "code", - "execution_count": 5, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "data": { - "text/plain": [ - "tensor([0.1020, 0.0113, 0.4806, 0.0571, 0.0482, 0.0079, 0.0450, 0.0076, 0.1851,\n", - " 0.0552])" - ] - }, - "execution_count": 5, - "metadata": {}, - "output_type": "execute_result" - } - ], + "outputs": [], "source": [ "from torch.nn.functional import softmax\n", "# do forward pass in PyTorch/Brevitas\n", @@ -505,22 +104,9 @@ }, { "cell_type": "code", - "execution_count": 6, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "data": { - "image/png": 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5ZcqUmuEjIqKOOlcNfQ04BLgSuAo4WNIxNY59KbCFpE0kTQT2BeYOO/YWPbN/A1xfN/GIiFg+6vQR7Az8hW0DSDoJmD/aTrYXS5oNnAtMAE6wPV/SUcA823OB2ZJ2BR4HHgDesZTvIyIillKdQrAA2Ai4pcxvWJaNyvY5DBuXyPZHe6YPq5dmREQ0ZdCgc9+jupxzEnCNpEvKqm2BS0baLyIiViyDzgg+31oWERExZgYNOnfR0LSk5wIvL7OX2L6n6cQiIqIdda4a2oeqKehNwD7AxZL2bjqxiIhoR53O4g8DLx86C5A0BbgAOLPJxCIioh11bihbaVhT0H0194uIiBVAnTOCH0o6lz89sD6PqoyIGEcGFgJJAr5M1VH8qrL4WNtnN51YRES0Y2AhsG1J59h+EXBWSzlFRESL6rT1Xy7p5aNvFhERK6I6fQTbAW+VdDPwCCCqk4UXN5lYRES0o04h+KvGs4iIiDEzaKyh5wAfAjanGoL608MeLRkREePAoD6Cb1E1BX0FWJPq6qGIiBhnBjUNrW/7w2X6XEmXt5FQRES0a7T7CNal6hwGmNA7b/v+hnOLiIgWDCoEawOX8adCADB0VmBg06aSioiI9gwahnp6i3lERMQYyeBxEREdl0IQEdFxKQQRER036IayZw/aMVcNRUSMD4OuGrqM6uogARsBD5TpdYBbgU2aTi4iIpo3YtOQ7U1sb0r1WMrX255sez3gdcB5bSUYERHNqtNHsL3tp55IZvsHwA7NpRQREW2qM/roHZKOBE4u828B7mgupYiIaFOdM4L9gCnA2VRPKZtSlkVExDgw6hlBuTroMElr2H6khZwiIqJFo54RSNpB0tXANWX+JZK+1nhmERHRijpNQ0dTPaXsPgDbvwZ2bDKpiIhoT607i23fNmzREw3kEhERY6DOVUO3SdoBsKRVgMMozUQREbHiq3NGcAhwKDAVuB3YGviHBnOKiIgW1Tkj2Mr2W3oXSHol8LNmUoqIiDbVOSP4Ss1lf0bSLEnXSVog6Yg+6w+XdLWk30j6b0kb1zluREQsP4NGH30F1VASUyQd3rNqLWDCaAeWNAE4BtgNWAhcKmmu7at7NvsVMNP2HyT9PfBZ4M1L/jYiImJpDTojmAisSVUsJvW8HgL2rnHsbYEFtm+0/RhwGrBn7wa2f2T7D2X2l8C0JUs/IiKW1aBnFl8EXCTpRNu3LMWxpwK9l50uBLYbsP27gB8sRZyIiFgGdfoIjpe0ztCMpHUlnbs8k5D0VmAm8LkR1h8kaZ6keYsWLVqeoSMiOq9OIZhs+8GhGdsPAM+psd/twIY989PKsqeRtCvwYWAP24/2O5DtY23PtD1zypQpNUJHRERddQrBk5I2GpopV/a4xn6XAltI2kTSRGBfYG7vBpJeCnyDqgjcUz/tiIhYXurcR/Bh4KeSLqJ6VOWrgYNG28n2YkmzgXOprjI6wfZ8SUcB82zPpWoKWhM4QxLArbb3WLq3EhERS6POMNQ/lLQNsH1Z9B7b99Y5eHmy2TnDln20Z3rXJcg1IiIaMGLTkKTnl3+3oXp4/R3ltVFZFhER48CgM4L3AQcCX+izzsDOjWQUEbGUjj7/t43HeO9uWzYeo22D7iM4sPy7U3vpRERE2wYNMbHXoB1tn7X804mIiLYNahp6ffn3OVRjDl1Y5ncCfk71IPuIiFjBDWoaeieApPOAGbbvLPPrAye2kl1ERDSuzg1lGw4VgeJuqquIIiJiHKhzQ9l/l7GFTi3zbwYuaC6liIhoU50bymZL+ltgx7LoWNtnN5tWRES0pc4ZAcDlwMO2L5C0uqRJth9uMrGIiGjHqH0Ekg4EzqQaHA6q5wx8t8GcIiKiRXU6iw8FXkn1ZDJsX0+9YagjImIFUKcQPFoeNQmApJWpNwx1RESsAOoUgoskfQhYTdJuwBnA95pNKyIi2lKnEHwAWARcCRxMNaz0kU0mFRER7Rl41ZCkCcB8288HjmsnpYiIaNPAMwLbTwDX9T6qMiIixpc69xGsC8yXdAnwyNDCPFIyImJ8qFMIPtJ4FhERMWYGPY9gVeAQYHOqjuI5the3lVhERLRjUB/BScBMqiKwO/0fWRkRESu4QU1DM2y/CEDSHOCSdlKKiIg2DTojeHxoIk1CERHj16AzgpdIeqhMi+rO4ofKtG2v1Xh2ERHRuEGPqpzQZiIRETE26gwxERER41gKQUREx6UQRER0XApBRETHpRBERHRcCkFERMelEEREdFwKQUREx6UQRER0XApBRETHNVoIJM2SdJ2kBZKO6LN+R0mXS1osae8mc4mIiP4aKwTlwffHUD3LYAawn6QZwza7FdgfOKWpPCIiYrA6j6pcWtsCC2zfCCDpNGBP4OqhDWzfXNY92WAeTzn6/N82HuO9u23ZeIyIiOWpyaahqcBtPfMLy7IlJukgSfMkzVu0aNFySS4iIiorRGex7WNtz7Q9c8qUKWOdTkTEuNJkIbgd2LBnflpZFhERzyBNFoJLgS0kbSJpIrAvMLfBeBERsRQaKwTlOcezgXOBa4DTbc+XdJSkPQAkvVzSQuBNwDckzW8qn4iI6K/Jq4awfQ5wzrBlH+2ZvpSqySgiIsbICtFZHBERzUkhiIjouBSCiIiOSyGIiOi4FIKIiI5LIYiI6LgUgoiIjkshiIjouBSCiIiOSyGIiOi4FIKIiI5LIYiI6LhGB52LyONBI575UggiIpaDFflHT5qGIiI6LoUgIqLj0jQU41rTp+vpn4jxIIUgYhxKAYwlkaahiIiOSyGIiOi4FIKIiI5LIYiI6LgUgoiIjkshiIjouBSCiIiOSyGIiOi4FIKIiI5LIYiI6LgUgoiIjkshiIjouBSCiIiOSyGIiOi4DEPdkhX5MXYRMb6lEEQ0JM8EiBVFo4VA0izg34AJwPG2PzNs/bOAbwEvA+4D3mz75iZziohm5ex3xdNYH4GkCcAxwO7ADGA/STOGbfYu4AHbmwNHA//aVD4REdFfk53F2wILbN9o+zHgNGDPYdvsCZxUps8EdpGkBnOKiIhhZLuZA0t7A7NsH1Dm3wZsZ3t2zzZXlW0Wlvkbyjb3DjvWQcBBZXYr4LpGku5vMnDvqFsldmIndmI/s2NvbHtKvxUrRGex7WOBY8citqR5tmcmdmIndmKPl9jDNdk0dDuwYc/8tLKs7zaSVgbWpuo0joiIljRZCC4FtpC0iaSJwL7A3GHbzAXeUab3Bi50U21VERHRV2NNQ7YXS5oNnEt1+egJtudLOgqYZ3suMAf4tqQFwP1UxeKZZkyapBI7sRM7sdvSWGdxRESsGDLWUEREx6UQRER0XArBCCTNknSdpAWSjmg59gmS7in3WbQZd0NJP5J0taT5kg5rMfaqki6R9OsS++Ntxe7JYYKkX0n6/hjEvlnSlZKukDSv5djrSDpT0rWSrpH0ipbiblXe79DrIUnvaSN2if/e8t/aVZJOlbRqi7EPK3Hnt/meR2Q7r2Evqs7tG4BNgYnAr4EZLcbfEdgGuKrl970+sE2ZngT8tq33DQhYs0yvAlwMbN/y+z8cOAX4fptxS+ybgcltxy2xTwIOKNMTgXXGIIcJwF1UNz21EW8qcBOwWpk/Hdi/pdgvBK4CVqe6YOcCYPOx+NsPvXJG0F+d4TEaY/t/qK6iapXtO21fXqYfBq6h+h+mjdi2/fsyu0p5tXYlg6RpwN8Ax7cV85lA0tpUPzzmANh+zPaDY5DKLsANtm9pMebKwGrlHqbVgTtaivsXwMW2/2B7MXARsFdLsftKIehvKnBbz/xCWvpCfKaQNB14KdUv87ZiTpB0BXAPcL7t1mIDXwL+CXiyxZi9DJwn6bIypEpbNgEWAd8szWLHS1qjxfhD9gVObSuY7duBzwO3AncCv7N9XkvhrwJeLWk9SasDf83Tb75tXQpB/BlJawLfAd5j+6G24tp+wvbWVHehbyvphW3ElfQ64B7bl7URbwSvsr0N1Wi9h0rasaW4K1M1Q/677ZcCjwBt94lNBPYAzmgx5rpUZ/mbABsAa0h6axuxbV9DNdLyecAPgSuAJ9qIPZIUgv7qDI8xLklahaoI/Ifts8Yih9I08SNgVkshXwnsIelmqmbAnSWd3FJs4KlfqNi+BzibqnmyDQuBhT1nX2dSFYY27Q5cbvvuFmPuCtxke5Htx4GzgB3aCm57ju2X2d4ReICqP27MpBD0V2d4jHGnDAE+B7jG9hdbjj1F0jplejVgN+DaNmLb/qDtabanU/2tL7Tdyq9DAElrSJo0NA38JVXzQeNs3wXcJmmrsmgX4Oo2YvfYjxabhYpbge0lrV7+u9+Fqk+sFZKeU/7diKp/4JS2YvezQow+2jaPMDxGW/ElnQq8FpgsaSHwMdtzWgj9SuBtwJWlrR7gQ7bPaSH2+sBJ5YFGKwGn2279Ms4x8lzg7PIojpWBU2z/sMX47wb+o/zouRF4Z1uBS+HbDTi4rZgAti+WdCZwObAY+BXtDvnwHUnrAY8Dh45RB/1TMsRERETHpWkoIqLjUggiIjouhSAiouNSCCIiOi6FICKi41IIIiI6LoUgIqLj/hdRB2LXFx7MKAAAAABJRU5ErkJggg==\n", - "text/plain": [ - "
" - ] - }, - "metadata": { - "needs_background": "light" - }, - "output_type": "display_data" - } - ], + "outputs": [], "source": [ "import numpy as np\n", "objects = [str(x) for x in range(10)]\n", @@ -549,7 +135,7 @@ }, { "cell_type": "code", - "execution_count": 7, + "execution_count": null, "metadata": {}, "outputs": [], "source": [ @@ -568,38 +154,9 @@ }, { "cell_type": "code", - "execution_count": 8, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "Serving '/tmp/LFCW1A1_finn-onnx.onnx' at http://0.0.0.0:8081\n" - ] - }, - { - "data": { - "text/html": [ - "\n", - " \n", - " " - ], - "text/plain": [ - "" - ] - }, - "execution_count": 8, - "metadata": {}, - "output_type": "execute_result" - } - ], + "outputs": [], "source": [ "showInNetron(export_onnx_path)" ] @@ -622,34 +179,9 @@ }, { "cell_type": "code", - "execution_count": 9, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "name": "stderr", - "output_type": "stream", - "text": [ - "/home/hendrik/Dropbox/a_local/Uni/fpga_synth_system_data/finn_deving/finn/deps/qonnx/src/qonnx/core/modelwrapper.py:93: UserWarning: Some old-style domain attributes were automatically converted to new-style,\n", - " i.e. domain=finn to domain=qonnx.custom_op.\n", - " warnings.warn(\n" - ] - }, - { - "data": { - "text/plain": [ - "input: \"37\"\n", - "input: \"38\"\n", - "output: \"39\"\n", - "name: \"MatMul_13\"\n", - "op_type: \"MatMul\"\n", - "domain: \"\"" - ] - }, - "execution_count": 9, - "metadata": {}, - "output_type": "execute_result" - } - ], + "outputs": [], "source": [ "from qonnx.core.modelwrapper import ModelWrapper\n", "model = ModelWrapper(export_onnx_path)\n", @@ -665,26 +197,9 @@ }, { "cell_type": "code", - "execution_count": 10, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "data": { - "text/plain": [ - "array([[-1., -1., 1., ..., -1., 1., -1.],\n", - " [ 1., 1., -1., ..., 1., -1., 1.],\n", - " [-1., -1., -1., ..., 1., -1., 1.],\n", - " ...,\n", - " [ 1., -1., -1., ..., -1., -1., 1.],\n", - " [ 1., -1., -1., ..., 1., 1., 1.],\n", - " [ 1., -1., 1., ..., 1., -1., 1.]], dtype=float32)" - ] - }, - "execution_count": 10, - "metadata": {}, - "output_type": "execute_result" - } - ], + "outputs": [], "source": [ "model.get_initializer(model.graph.node[8].input[1])" ] @@ -698,40 +213,18 @@ }, { "cell_type": "code", - "execution_count": 11, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "data": { - "text/plain": [ - "'BIPOLAR'" - ] - }, - "execution_count": 11, - "metadata": {}, - "output_type": "execute_result" - } - ], + "outputs": [], "source": [ "model.get_tensor_datatype(model.graph.node[8].input[1]).name" ] }, { "cell_type": "code", - "execution_count": 12, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "data": { - "text/plain": [ - "[784, 1024]" - ] - }, - "execution_count": 12, - "metadata": {}, - "output_type": "execute_result" - } - ], + "outputs": [], "source": [ "model.get_tensor_shape(model.graph.node[8].input[1])" ] @@ -745,7 +238,7 @@ }, { "cell_type": "code", - "execution_count": 13, + "execution_count": null, "metadata": {}, "outputs": [], "source": [ @@ -759,39 +252,9 @@ }, { "cell_type": "code", - "execution_count": 14, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "Stopping http://0.0.0.0:8081\n", - "Serving '/tmp/LFCW1A1-finn-onnx-clean.onnx' at http://0.0.0.0:8081\n" - ] - }, - { - "data": { - "text/html": [ - "\n", - " \n", - " " - ], - "text/plain": [ - "" - ] - }, - "execution_count": 14, - "metadata": {}, - "output_type": "execute_result" - } - ], + "outputs": [], "source": [ "showInNetron(export_onnx_path_transformed)" ] @@ -805,22 +268,9 @@ }, { "cell_type": "code", - "execution_count": 15, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "data": { - "text/plain": [ - "array([[-1.3736125, -3.5715756, 0.1768887, -1.9529207, -2.1233053,\n", - " -3.9293835, -2.1914592, -3.9634604, -0.7772659, -1.9869976]],\n", - " dtype=float32)" - ] - }, - "execution_count": 15, - "metadata": {}, - "output_type": "execute_result" - } - ], + "outputs": [], "source": [ "import finn.core.onnx_exec as oxe\n", "input_dict = {\"0\": nph.to_array(input_tensor)}\n", @@ -832,20 +282,9 @@ }, { "cell_type": "code", - "execution_count": 16, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "data": { - "text/plain": [ - "True" - ] - }, - "execution_count": 16, - "metadata": {}, - "output_type": "execute_result" - } - ], + "outputs": [], "source": [ "np.isclose(produced, produced_finn).all()" ] From 14801b8e98094b59174d4a206398ed8033076065 Mon Sep 17 00:00:00 2001 From: Hendrik Borras Date: Thu, 8 Sep 2022 12:27:19 +0200 Subject: [PATCH 004/665] Initial QONNX ingestion notebook --- ...1b_brevitas_network_import_via_QONNX.ipynb | 328 ++++++++++++++++++ 1 file changed, 328 insertions(+) create mode 100644 notebooks/basics/1b_brevitas_network_import_via_QONNX.ipynb diff --git a/notebooks/basics/1b_brevitas_network_import_via_QONNX.ipynb b/notebooks/basics/1b_brevitas_network_import_via_QONNX.ipynb new file mode 100644 index 0000000000..2d8447ad3a --- /dev/null +++ b/notebooks/basics/1b_brevitas_network_import_via_QONNX.ipynb @@ -0,0 +1,328 @@ +{ + "cells": [ + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "# Importing Brevitas networks into FINN with the QONNX interchange format\n", + "\n", + "**Note: This notebook is very similar to the 1a notebook, in that it shows the same concepts for the QONNX ingestion as 1a does for FINN-ONNX.**\n", + "\n", + "In this notebook we'll go through an example of how to import a Brevitas-trained QNN into FINN. The steps will be as follows:\n", + "\n", + "1. Load up the trained PyTorch model\n", + "2. Call Brevitas QONNX export and visualize with Netron\n", + "3. Import into FINN and converting QONNX to FINN-ONNX\n", + "\n", + "We'll use the following utility functions to print the source code for function calls (`showSrc()`) and to visualize a network using netron (`showInNetron()`) in the Jupyter notebook:" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": {}, + "outputs": [], + "source": [ + "import onnx\n", + "from finn.util.visualization import showSrc, showInNetron" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "## 1. Load up the trained PyTorch model\n", + "\n", + "The FINN Docker image comes with several [example Brevitas networks](https://github.com/Xilinx/brevitas/tree/master/src/brevitas_examples/bnn_pynq), and we'll use the LFC-w1a1 model as the example network here. This is a binarized fully connected network trained on the MNIST dataset. Let's start by looking at what the PyTorch network definition looks like:" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": {}, + "outputs": [], + "source": [ + "from brevitas_examples import bnn_pynq\n", + "showSrc(bnn_pynq.models.FC)" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "We can see that the network topology is constructed using a few helper functions that generate the quantized linear layers and quantized activations. The bitwidth of the layers is actually parametrized in the constructor, so let's instantiate a 1-bit weights and activations version of this network. We also have pretrained weights for this network, which we will load into the model." + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": {}, + "outputs": [], + "source": [ + "from finn.util.test import get_test_model\n", + "lfc = get_test_model(netname = \"LFC\", wbits = 1, abits = 1, pretrained = True)\n", + "lfc" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "We have now instantiated our trained PyTorch network. Let's try to run an example MNIST image through the network using PyTorch." + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": {}, + "outputs": [], + "source": [ + "import torch\n", + "import matplotlib.pyplot as plt\n", + "from pkgutil import get_data\n", + "import onnx\n", + "import onnx.numpy_helper as nph\n", + "raw_i = get_data(\"qonnx.data\", \"onnx/mnist-conv/test_data_set_0/input_0.pb\")\n", + "input_tensor = onnx.load_tensor_from_string(raw_i)\n", + "input_tensor_npy = nph.to_array(input_tensor)\n", + "input_tensor_pyt = torch.from_numpy(input_tensor_npy).float()\n", + "imgplot = plt.imshow(input_tensor_npy.reshape(28,28), cmap='gray')" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": {}, + "outputs": [], + "source": [ + "from torch.nn.functional import softmax\n", + "# do forward pass in PyTorch/Brevitas\n", + "produced = lfc.forward(input_tensor_pyt).detach()\n", + "probabilities = softmax(produced, dim=-1).flatten()\n", + "probabilities" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": {}, + "outputs": [], + "source": [ + "import numpy as np\n", + "objects = [str(x) for x in range(10)]\n", + "y_pos = np.arange(len(objects))\n", + "plt.bar(y_pos, probabilities, align='center', alpha=0.5)\n", + "plt.xticks(y_pos, objects)\n", + "plt.ylabel('Predicted Probability')\n", + "plt.title('LFC-w1a1 Predictions for Image')\n", + "plt.show()" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "## 2. Call Brevitas QONNX export and visualize with Netron\n", + "\n", + "Brevitas comes with built-in QONNX export functionality. This is similar to the regular ONNX export capabilities of PyTorch, with a few differences:\n", + "\n", + "1. Weight and activation quantization is represented as a 'fake-quantization' with Quant and BipolarQuant nodes.\n", + "2. Truncation operations as required by average pooling are represented with a Trunc node.\n", + "\n", + "One can read more about how QONNX works and why it was developed here: https://xilinx.github.io/finn//2021/11/03/qonnx-and-finn.html\n", + "\n", + "Additionally QONNX comes with a set of tools for working with the format. These are maintained together with the Fast Machinelearning collaboration as an open-source projet here: https://github.com/fastmachinelearning/qonnx\n", + "\n", + "It's actually quite straightforward to export QONNX from our Brevitas model as follows:" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": {}, + "outputs": [], + "source": [ + "from brevitas.export.onnx.generic.manager import BrevitasONNXManager\n", + "export_onnx_path = \"/tmp/LFCW1A1_qonnx.onnx\"\n", + "input_shape = (1, 1, 28, 28)\n", + "BrevitasONNXManager.export(lfc, input_shape, export_onnx_path);" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "Let's examine what the exported ONNX model looks like. For this, we will use the Netron visualizer:" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": {}, + "outputs": [], + "source": [ + "showInNetron(export_onnx_path)" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "When running this notebook in the FINN Docker container, you should be able to see an interactive visualization of the imported network above, and click on individual nodes to inspect their parameters. If you look at any of the MatMul nodes, you should be able to see that the weights are all {-1, +1} values." + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "## 3. Import into FINN and converting QONNX to FINN-ONNX\n", + "\n", + "Similarily to the 1a notebook we will first run a cleanup transformation on the exported QONNX model." + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": {}, + "outputs": [], + "source": [ + "from qonnx.util.cleanup import cleanup\n", + "\n", + "export_onnx_path_cleaned = \"/tmp/LFCW1A1-qonnx-clean.onnx\"\n", + "cleanup(export_onnx_path, out_file=export_onnx_path_cleaned)" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": {}, + "outputs": [], + "source": [ + "showInNetron(export_onnx_path_cleaned)" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "We will now import this QONNX model into FINN using the ModelWrapper. Here we can immediatley execute the model to verify correctness." + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": {}, + "outputs": [], + "source": [ + "from qonnx.core.modelwrapper import ModelWrapper\n", + "import qonnx.core.onnx_exec as oxe\n", + "model = ModelWrapper(export_onnx_path_cleaned)\n", + "input_dict = {\"0\": nph.to_array(input_tensor)}\n", + "output_dict = oxe.execute_onnx(model, input_dict)\n", + "produced_qonnx = output_dict[list(output_dict.keys())[0]]\n", + "\n", + "produced_qonnx" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": {}, + "outputs": [], + "source": [ + "np.isclose(produced, produced_finn).all()" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "Using the `QONNXtoFINN` transformation we can convert the model to the FINN internal FINN-ONNX representation. Notably all Quant and BipolarQuant nodes will have disappeared and are converted into MultiThreshold nodes." + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": {}, + "outputs": [], + "source": [ + "from finn.transformation.qonnx.convert_qonnx_to_finn import ConvertQONNXtoFINN\n", + "model = ModelWrapper(export_onnx_path_cleaned)\n", + "\n", + "model = model.transform(ConvertQONNXtoFINN())\n", + "\n", + "export_onnx_path_converted = \"/tmp/LFCW1A1-qonnx-converted.onnx\"\n", + "model.save(export_onnx_path_converted)" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": { + "scrolled": false + }, + "outputs": [], + "source": [ + "showInNetron(export_onnx_path_converted)" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "And once again we can execute the model with the FINN/QONNX execution engine." + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": {}, + "outputs": [], + "source": [ + "model = ModelWrapper(export_onnx_path_cleaned)\n", + "input_dict = {\"0\": nph.to_array(input_tensor)}\n", + "output_dict = oxe.execute_onnx(model, input_dict)\n", + "produced_finn = output_dict[list(output_dict.keys())[0]]\n", + "\n", + "produced_finn" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": {}, + "outputs": [], + "source": [ + "np.isclose(produced, produced_finn).all()" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "We have succesfully verified that the transformed and cleaned-up FINN graph still produces the same output, and can now use this model for further processing in FINN." + ] + } + ], + "metadata": { + "kernelspec": { + "display_name": "Python 3", + "language": "python", + "name": "python3" + }, + "language_info": { + "codemirror_mode": { + "name": "ipython", + "version": 3 + }, + "file_extension": ".py", + "mimetype": "text/x-python", + "name": "python", + "nbconvert_exporter": "python", + "pygments_lexer": "ipython3", + "version": "3.8.5" + } + }, + "nbformat": 4, + "nbformat_minor": 2 +} From c0cda8f78a2b1cc43e273d2b45e72148d6d073c6 Mon Sep 17 00:00:00 2001 From: Felix Jentzsch Date: Fri, 25 Nov 2022 19:20:00 +0100 Subject: [PATCH 005/665] Make SIMD support independent from PE --- .../fpgadataflow/vectorvectoractivation.py | 16 ++++---- tests/fpgadataflow/test_fpgadataflow_vvau.py | 39 +++++++++++-------- 2 files changed, 30 insertions(+), 25 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index da99da2e02..813b673b39 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -225,10 +225,10 @@ def get_output_datatype(self, ind=0): def get_instream_width(self, ind=0): i_bits = self.get_input_datatype().bitwidth() simd = self.get_nodeattr("SIMD") - if simd > 1: - pe = self.get_nodeattr("Channels") - else: - pe = self.get_nodeattr("PE") + #if simd > 1: + #pe = self.get_nodeattr("Channels") + #else: + pe = self.get_nodeattr("PE") in_width = i_bits * simd * pe return in_width @@ -242,10 +242,10 @@ def get_folded_input_shape(self, ind=0): dim_h, dim_w = self.get_nodeattr("Dim") ch = self.get_nodeattr("Channels") simd = self.get_nodeattr("SIMD") - if simd > 1: - pe = self.get_nodeattr("Channels") - else: - pe = self.get_nodeattr("PE") + #if simd > 1: + #pe = self.get_nodeattr("Channels") + #else: + pe = self.get_nodeattr("PE") sf = k_h * k_w // simd nf = ch // pe diff --git a/tests/fpgadataflow/test_fpgadataflow_vvau.py b/tests/fpgadataflow/test_fpgadataflow_vvau.py index c54284dee9..ea4be47334 100644 --- a/tests/fpgadataflow/test_fpgadataflow_vvau.py +++ b/tests/fpgadataflow/test_fpgadataflow_vvau.py @@ -27,7 +27,6 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import pytest - import numpy as np from onnx import TensorProto, helper from qonnx.core.datatype import DataType @@ -37,6 +36,8 @@ # from qonnx.custom_op.registry import getCustomOp from qonnx.transformation.general import GiveUniqueNodeNames from qonnx.util.basic import gen_finn_dt_tensor +from qonnx.transformation.infer_datatypes import InferDataTypes +from qonnx.transformation.infer_shapes import InferShapes import finn.core.onnx_exec as oxe @@ -47,6 +48,9 @@ from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.fpgadataflow.minimize_accumulator_width import ( + MinimizeAccumulatorWidth, +) def _infer_sparse_weight_tensor(W_conv, k_h, k_w, channels): @@ -150,6 +154,11 @@ def _make_single_vvau_modelwrapper( model.set_tensor_datatype("thresh", tdt) model.set_initializer("thresh", T) + # Minimize accumulator width to obtain realistic HLS reports + model = model.transform(MinimizeAccumulatorWidth()) + model = model.transform(InferShapes()) + model = model.transform(InferDataTypes()) + return model @@ -158,27 +167,27 @@ def prepare_inputs(input_tensor): # input datatype -@pytest.mark.parametrize("idt", [DataType["UINT4"], DataType["UINT8"]]) +@pytest.mark.parametrize("idt", [DataType["UINT4"]]) # weight datatype -@pytest.mark.parametrize("wdt", [DataType["INT4"]]) +@pytest.mark.parametrize("wdt", [DataType["UINT4"]]) # activation: None or DataType @pytest.mark.parametrize("act", [DataType["UINT4"], None]) # PE -@pytest.mark.parametrize("pe", [1, "channels"]) +@pytest.mark.parametrize("pe", [1,2,3,6]) # SIMD -@pytest.mark.parametrize("simd", [1]) +@pytest.mark.parametrize("simd", [1,9]) # Input image shape @pytest.mark.parametrize("dim_h", [10]) -@pytest.mark.parametrize("dim_w", [10, 1]) +@pytest.mark.parametrize("dim_w", [10]) # Kernel shape @pytest.mark.parametrize("k_h", [3]) -@pytest.mark.parametrize("k_w", [3, 1]) +@pytest.mark.parametrize("k_w", [3]) # Number of input and output channels -@pytest.mark.parametrize("channels", [3, 4]) +@pytest.mark.parametrize("channels", [6]) # memory mode -@pytest.mark.parametrize("mem_mode", ["const", "decoupled"]) +@pytest.mark.parametrize("mem_mode", ["const"]) # execution mode -@pytest.mark.parametrize("exec_mode", ["cppsim", "rtlsim"]) +@pytest.mark.parametrize("exec_mode", ["cppsim","rtlsim"]) @pytest.mark.fpgadataflow @pytest.mark.slow @pytest.mark.vivado @@ -194,6 +203,9 @@ def test_fpgadataflow_vvau( if channels % pe != 0: pytest.skip("Requirement Channels divisable by PE is violated.") + #if pe < channels and simd > 1: + # pytest.skip("Do not apply SIMD parallelism before max PE parallelism") + # Generate weights in expected shape for ONNX and HLS node W = gen_finn_dt_tensor(wdt, (channels, 1, k_h, k_w)) # shape: [channels, 1, k, k] W_onnx = _infer_sparse_weight_tensor( @@ -251,13 +263,6 @@ def test_fpgadataflow_vvau( "outp" ] - with open("vvau_test_expected.txt", "w") as f: - f.write("-------expected:\n") - f.write(str(y_expected)) - with open("vvau_test_produced.txt", "w") as f: - f.write("--------produced:\n") - f.write(str(y_produced)) - assert (y_produced == y_expected).all(), "incorrect result" # if exec_mode == "rtlsim": From 0fb57af5ca46657970309fa5a9599adee356d933 Mon Sep 17 00:00:00 2001 From: Felix Jentzsch Date: Thu, 1 Dec 2022 09:11:35 +0100 Subject: [PATCH 006/665] [RTL SWG] Rework parallel-output implementation style --- finn-rtllib/swg/swg_template_parallel.sv | 406 ++++++++++++++++++ .../convolutioninputgenerator_rtl.py | 284 +++++++++++- 2 files changed, 685 insertions(+), 5 deletions(-) create mode 100644 finn-rtllib/swg/swg_template_parallel.sv diff --git a/finn-rtllib/swg/swg_template_parallel.sv b/finn-rtllib/swg/swg_template_parallel.sv new file mode 100644 index 0000000000..432c374764 --- /dev/null +++ b/finn-rtllib/swg/swg_template_parallel.sv @@ -0,0 +1,406 @@ +/****************************************************************************** + * Copyright (C) 2022, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *****************************************************************************/ +module $TOP_MODULE_NAME$_controller #( + int unsigned LOOP_H_ITERATIONS = $LOOP_H_ITERATIONS$, + int unsigned LOOP_W_ITERATIONS = $LOOP_W_ITERATIONS$, + int unsigned LOOP_KH_ITERATIONS = $LOOP_KH_ITERATIONS$, + int unsigned LOOP_KW_ITERATIONS = $LOOP_KW_ITERATIONS$, + int unsigned LOOP_SIMD_ITERATIONS = $LOOP_SIMD_ITERATIONS$, + + int unsigned INCR_BITWIDTH = $INCR_BITWIDTH$, + + bit IS_DEPTHWISE = $IS_DEPTHWISE$ +)( + input logic clk, + input logic rst_n, + + input logic advance, + output logic [INCR_BITWIDTH-1:0] addr_incr, + output logic [INCR_BITWIDTH-1:0] tail_incr +); + + // state and counters + typedef enum logic [2:0] { + STATE_START, + STATE_LOOP_SIMD, + STATE_LOOP_KW, + STATE_LOOP_KH, + STATE_LOOP_W, + STATE_LOOP_H + } state_e; + state_e State = $INNERMOST_STATE$; + state_e state_next; + + logic signed [$clog2(LOOP_H_ITERATIONS +2)+1-1:0] Counter_loop_h = LOOP_H_ITERATIONS; + logic signed [$clog2(LOOP_W_ITERATIONS +2)+1-1:0] Counter_loop_w = LOOP_W_ITERATIONS; + logic signed [$clog2(LOOP_KH_ITERATIONS +2)+1-1:0] Counter_loop_kh = LOOP_KH_ITERATIONS; + logic signed [$clog2(LOOP_KW_ITERATIONS +2)+1-1:0] Counter_loop_kw = LOOP_KW_ITERATIONS; + logic signed [$clog2(LOOP_SIMD_ITERATIONS+2)+1-1:0] Counter_loop_simd = LOOP_SIMD_ITERATIONS; + + // combinational logic for addr_incr generation + always_comb begin : blkHead + unique case (State) + 0 : addr_incr = 0; + 1 : addr_incr = $HEAD_INCR_SIMD$; + 2 : addr_incr = $HEAD_INCR_KW$; + 3 : addr_incr = $HEAD_INCR_KH$; + 4 : addr_incr = $HEAD_INCR_W$; + 5 : addr_incr = $HEAD_INCR_H$; + endcase + end + + // combinational logic for tail_incr generation + uwire tail_incr_inner_condition = IS_DEPTHWISE? (Counter_loop_kh >= 0) : 0; + assign tail_incr = + tail_incr_inner_condition? 1 : + Counter_loop_w >= 0? $TAIL_INCR_W$ : + Counter_loop_h >= 0? $TAIL_INCR_H$ : + /* else */ $TAIL_INCR_LAST$; + + // combinational next state logic + always_comb begin : blkState + state_next = State; + if(State != $INNERMOST_STATE$) state_next = $INNERMOST_STATE$; + else begin + if(Counter_loop_simd < 0) begin + state_next = + (Counter_loop_kw >= 0)? STATE_LOOP_KW : + (Counter_loop_kh >= 0)? STATE_LOOP_KH : + (Counter_loop_w >= 0)? STATE_LOOP_W : + (Counter_loop_h >= 0)? STATE_LOOP_H : + /* else */ STATE_START; + end + end + end : blkState + + // sequential logic + always_ff @ (posedge clk) begin + if(!rst_n) begin + State <= $INNERMOST_STATE$; + Counter_loop_h <= LOOP_H_ITERATIONS; + Counter_loop_w <= LOOP_W_ITERATIONS; + Counter_loop_kh <= LOOP_KH_ITERATIONS; + Counter_loop_kw <= LOOP_KW_ITERATIONS; + Counter_loop_simd <= LOOP_SIMD_ITERATIONS; + end + else if(advance) begin + State <= state_next; + if (State == $INNERMOST_STATE$) begin + if(Counter_loop_simd >= 0) Counter_loop_simd <= Counter_loop_simd-1; + else begin + Counter_loop_simd <= LOOP_SIMD_ITERATIONS; + if(Counter_loop_kw >= 0) Counter_loop_kw <= Counter_loop_kw-1; + else begin + Counter_loop_kw <= LOOP_KW_ITERATIONS; + if(Counter_loop_kh >= 0) Counter_loop_kh <= Counter_loop_kh-1; + else begin + Counter_loop_kh <= LOOP_KH_ITERATIONS; + if(Counter_loop_w >= 0) Counter_loop_w <= Counter_loop_w-1; + else begin + Counter_loop_w <= LOOP_W_ITERATIONS; + if(Counter_loop_h >= 0) Counter_loop_h <= Counter_loop_h-1; + else Counter_loop_h <= LOOP_H_ITERATIONS; + end + end + end + end + end + end + end + +endmodule : $TOP_MODULE_NAME$_controller + +module $TOP_MODULE_NAME$_reg_buffer +#( + parameter WIDTH = 1, + parameter DEPTH = 1 +) +( + CLK, + shift_enable, + shift_in, + shift_out, + data_out +); + +input CLK, shift_enable; +input [WIDTH-1:0] shift_in; +output [WIDTH-1:0] shift_out; +output [WIDTH*DEPTH-1:0] data_out; + +reg [WIDTH-1:0] data [DEPTH-1:0]; + +assign shift_out = data[DEPTH-1]; + +for (genvar e=0; e0; i=i-1) + data[i] <= data[i-1]; + data[0] <= shift_in; + end +end +endmodule : $TOP_MODULE_NAME$_reg_buffer + +module $TOP_MODULE_NAME$_ram_buffer +#( + parameter WIDTH = 1, + parameter DEPTH = 1 +) +( + CLK, + RST, + shift_enable, + shift_in, + shift_out +); + +input CLK, RST, shift_enable; +input [WIDTH-1:0] shift_in; +output [WIDTH-1:0] shift_out; + +reg [WIDTH-1:0] out_reg; +assign shift_out = out_reg; + +integer addr_w, addr_r; //TODO: minimize width + simplify + +$RAM_STYLE$ reg [WIDTH-1:0] ram [DEPTH-1:0]; + +always @(posedge CLK) begin + if (RST == 1'b0) begin + addr_w <= 0; + addr_r <= 1; + end else begin + if (shift_enable) begin + ram[addr_w] <= shift_in; + out_reg <= ram[addr_r]; + + if (addr_w == DEPTH-1) + addr_w <= 0; + else + addr_w <= addr_w + 1; + + if (addr_r == DEPTH-1) + addr_r <= 0; + else + addr_r <= addr_r + 1; + end + end +end +endmodule : $TOP_MODULE_NAME$_ram_buffer + +module $TOP_MODULE_NAME$_wb +#( + parameter IN_WIDTH = 1, //bit-width*C*MMV_in + parameter OUT_ELEM_WIDTH = 1, //bit-width*C + parameter OUT_WIDTH = 1, //bit-width*C*MMV_out + parameter BUFFER_ELEM_TOTAL = 1 +) +( + CLK, + RST, + data_in, + shift_enable, + data_out +); + +input CLK, RST; +input [IN_WIDTH-1:0] data_in; +input shift_enable; +output [OUT_WIDTH-1:0] data_out; + +$GENERATE_REG_FIFOS$ + +$GENERATE_BRAM_FIFOS$ + +//Fixed interconnect between linear buffers +$GENERATE_BUFFER_CONNECTION$ + +//Fixed REG FIFO <-> output mapping +$GENERATE_OUTPUT_MAPPING$ + + +endmodule : $TOP_MODULE_NAME$_wb + +module $TOP_MODULE_NAME$_impl #( + int BIT_WIDTH, + int SIMD, + int MMV_IN, + int MMV_OUT, + int LAST_READ_ELEM = $LAST_READ_ELEM$, + int FIRST_WRITE_ELEM = $FIRST_WRITE_ELEM$, + int LAST_WRITE_ELEM = $LAST_WRITE_ELEM$, + int BUF_ELEM_TOTAL = $BUF_ELEM_TOTAL$, + int INCR_BITWIDTH = $INCR_BITWIDTH$ +)( + input logic ap_clk, + input logic ap_rst_n, + + input logic in0_V_V_TVALID, + output logic in0_V_V_TREADY, + input logic [BIT_WIDTH * SIMD * MMV_IN-1:0] in0_V_V_TDATA, + + output logic out_V_V_TVALID, + input logic out_V_V_TREADY, + output logic [BIT_WIDTH * SIMD * MMV_OUT-1:0] out_V_V_TDATA +); + // derived constants + localparam int unsigned BUF_IN_WIDTH = BIT_WIDTH * SIMD * MMV_IN; + localparam int unsigned BUF_OUT_ELEM_WIDTH = BIT_WIDTH * SIMD; + localparam int unsigned BUF_OUT_WIDTH = BIT_WIDTH * SIMD * MMV_OUT; + + //main buffer instantiation + uwire [BUF_IN_WIDTH -1:0] window_buffer_in; + uwire [BUF_OUT_WIDTH-1:0] window_buffer_out; + uwire window_buffer_shift_enable; + $TOP_MODULE_NAME$_wb + #( + .IN_WIDTH(BUF_IN_WIDTH), + .OUT_ELEM_WIDTH(BUF_OUT_ELEM_WIDTH), + .OUT_WIDTH(BUF_OUT_WIDTH), + .BUFFER_ELEM_TOTAL(BUF_ELEM_TOTAL) + ) + window_buffer_inst + ( + .CLK(ap_clk), + .RST(ap_rst_n), + .data_in(window_buffer_in), + .shift_enable(window_buffer_shift_enable), + .data_out(window_buffer_out) + ); + + //controller instantiation + uwire advance_controller; + uwire signed [INCR_BITWIDTH-1:0] addr_incr; + uwire [INCR_BITWIDTH-1:0] tail_incr; + $TOP_MODULE_NAME$_controller controller_inst ( + .clk(ap_clk), + .rst_n(ap_rst_n), + .advance(advance_controller), + .addr_incr(addr_incr), + .tail_incr(tail_incr) + ); + + // Counters/address registers + // Add a sign bit even to (most) unsigned counters and Window_buffer_read_addr_reg, + // so we can use automatic sign extension and simplify calculations w/ signed increment. + // Alternatively, we could manually sign-extend and shave off a bit here or there. + logic signed [$clog2(LAST_READ_ELEM+1)+1-1:0] Newest_buffered_elem = -1; + logic [$clog2(LAST_READ_ELEM+1)+1-1:0] Current_elem = FIRST_WRITE_ELEM; + logic [$clog2(LAST_READ_ELEM+1)+1-1:0] First_elem_next_window = 0; + + // Control signals/registers + logic Writing_done = 0; + logic write_done = 0; + + uwire write_ok = write_cmd && (out_V_V_TREADY || write_done); + uwire write_blocked = write_cmd && !out_V_V_TREADY && !write_done; + + uwire write_cmd = !($signed(Current_elem) > Newest_buffered_elem) && !Writing_done;; + + uwire reading_done = Newest_buffered_elem == LAST_READ_ELEM; + uwire read_cmd = + !reading_done && ( // if there is still an input element left to read + Writing_done || ( // if fetching is done (e.g. for skipped rows at FM end due to stride) + $signed(((Newest_buffered_elem - (BUF_ELEM_TOTAL - 1)))) < $signed(First_elem_next_window) && + $signed(((Newest_buffered_elem - (BUF_ELEM_TOTAL - 1)))) < $signed(Current_elem) + ) // (over-)write to buffer if oldest buffered element will no longer be needed + ); + uwire read_ok = read_cmd && in0_V_V_TVALID && !write_blocked; + + // includes waiting on W if W-only cycle: wait only on W no R/W to wait for + uwire advance = read_ok || (!read_cmd && write_ok) || (!read_cmd && !write_cmd); + + //assign buffer control + assign window_buffer_shift_enable = advance; + assign advance_controller = write_ok; + + //assign I/O ports + assign window_buffer_in = in0_V_V_TDATA; + assign out_V_V_TDATA = window_buffer_out; + assign in0_V_V_TREADY = ap_rst_n && read_ok; //only asserted if data is available and we can store it (allowed) + assign out_V_V_TVALID = ap_rst_n && write_cmd && !write_done; //only asserted if we have data available and it has not been read yet (don't wait for READY from sink) + + //write done logic + always_ff @(posedge ap_clk) begin + if (advance) begin + write_done <= 1'b0; //reset flag + end else if (write_ok) // successful W in this cycle, but R still outstanding + write_done <= 1'b1; //write can happen even if read is blocked, but only for the current cycle! + end + + //main process for advancing counters + always_ff @(posedge ap_clk) begin + if(!ap_rst_n) begin + Newest_buffered_elem <= -1; + Current_elem <= FIRST_WRITE_ELEM; + First_elem_next_window <= 0; + Writing_done <= 0; + end + else begin + if (read_ok) begin + Newest_buffered_elem <= Newest_buffered_elem+1; + + //check if this is the last read cycle (reading_done will be true afterwards) + if ((Newest_buffered_elem == LAST_READ_ELEM-1) && Writing_done) begin + //start processing of next FM if writing is done already (possible due to unused input elements at the tail end) + //todo: allow for read overlapping between feature maps (i.e., reading first elements from next FM while still writing last window of current FM) + Newest_buffered_elem <= -1; + Current_elem <= FIRST_WRITE_ELEM; + First_elem_next_window <= 0; + Writing_done <= 0; + end + end + + if (write_ok) begin + First_elem_next_window <= First_elem_next_window + tail_incr; + + //check if this is the last write cycle (Writing_done will be true afterwards) + if (Current_elem == LAST_WRITE_ELEM) begin + Writing_done <= 1; + + if (reading_done || (read_ok && (Newest_buffered_elem == LAST_READ_ELEM - 1))) begin + //start processing of next FM if reading is done already, or completes in the same cycle + Newest_buffered_elem <= -1; + Current_elem <= FIRST_WRITE_ELEM; + First_elem_next_window <= 0; + Writing_done <= 0; + end + end + else + Current_elem <= $signed(Current_elem) + addr_incr; + end + end + end + +endmodule : $TOP_MODULE_NAME$_impl diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py index 1afd23d3a1..1ae4022b79 100755 --- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py +++ b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py @@ -72,8 +72,8 @@ def get_nodeattr_types(self): "SIMD": ("i", True, 0), # additional parallelization parameter - not yet implemented "M": ("i", False, 1), - # alternative implementation style - not yet implemented - "parallel_window": ("i", False, 0, {0}), + # Enable parallel window output (requires full SIMD unfolding) + "parallel_window": ("i", False, 0, {0, 1}), "Stride": ("ints", True, []), # [H, W] = [Y, X] "Dilation": ("ints", True, []), # [H, W] = [Y, X] # FINN DataTypes for inputs, weights, outputs @@ -639,6 +639,281 @@ def prepare_codegen_default(self): return template_path, code_gen_dict + def prepare_codegen_parallel(self): + # Parallel implementation style for MMV_out = K: + # mix of shift-registers (for parallel read) and line buffers (BRAM or LUTRAM) + # compute a static schedule by analyzing access pattern (from im2col function) + template_path = ( + os.environ["FINN_ROOT"] + "/finn-rtllib/swg/swg_template_parallel.sv" + ) + code_gen_dict = {} + + ifm_ch = self.get_nodeattr("IFMChannels") + k = self.get_nodeattr("ConvKernelDim") + ifm_dim = self.get_nodeattr("IFMDim") + stride = self.get_nodeattr("Stride") + dilation = self.get_nodeattr("Dilation") + simd = self.get_nodeattr("SIMD") + M = self.get_nodeattr("M") + + k_h, k_w = k + h, w = ifm_dim + pad = [0, 0, 0, 0] # padding happens in separate padding node for now + stride_h, stride_w = stride + dilation_h, dilation_w = dilation + pad_h = pad[0] + pad[2] + pad_w = pad[1] + pad[3] + out_dim_h = im2col.compute_conv_output_dim(h, k_h, stride_h, pad_h, dilation_h) + out_dim_w = im2col.compute_conv_output_dim(w, k_w, stride_w, pad_w, dilation_w) + mmv_in = M * 1 + mmv_out = M * k_h * k_w + channel_factor = int(ifm_ch / simd) + + # compute minimal buffer length (assuming it holds 1 complete window) + buffer_min_size = ( + (k_h - 1) * dilation_h * w + (k_w - 1) * dilation_w + 1 + ) * channel_factor + + # buffer_actual_size = self.get_buffer_depth() # TODO: Move to this method + buffer_actual_size = buffer_min_size + 1 + code_gen_dict["$BUF_ELEM_TOTAL$"] = [str(buffer_actual_size)] + + # compute some intermediate values, e.g., kernel "width" = k_w incl. dilation + # or cols/rows that are skipped due to imperfect stride<->dim combination + kernel_width = (k_w - 1) * dilation_w + 1 + kernel_height = (k_h - 1) * dilation_h + 1 + skip_columns = w % (kernel_width + (out_dim_w - 1) * stride_w) + skip_rows = h % (kernel_height + (out_dim_h - 1) * stride_h) + + # compute address increment values for 5-loop nest #TODO: simplify + addr_incr_end_simd = 1 + addr_incr_end_window_elem = (dilation_w - 1) * channel_factor + 1 + addr_incr_end_window_row = ( + ((w - kernel_width) * channel_factor) # remaining line + + ((dilation_h - 1) * w * channel_factor) # skip lines + + 1 # wrap-around of minimally sized buffer + ) + addr_incr_end_window = -buffer_min_size + stride_w * channel_factor + 1 + addr_incr_end_row = ( + -buffer_min_size + + ((skip_columns + kernel_width) * channel_factor) # remaining line + + ((stride_h - 1) * w * channel_factor) # skip lines + + 1 + ) + + # set certain threshold indices to detect when reading/writing finishes + code_gen_dict["$LAST_READ_ELEM$"] = [str(h * w * channel_factor - 1)] + code_gen_dict["$LAST_WRITE_ELEM$"] = [ + str(((h - skip_rows - 1) * w + (w - skip_columns)) * channel_factor - 1) + ] + + # default controller loop structure: # iterations (counters) map directly + loop_h_iterations = out_dim_h + loop_w_iterations = out_dim_w # -> innermost loop + loop_kh_iterations = 1 # k_h + loop_kw_iterations = 1 # k_w + loop_simd_iterations = 1 # channel_factor + + if loop_w_iterations == 1: + code_gen_dict["$INNERMOST_STATE$"] = ["STATE_LOOP_H"] + loop_h_iterations -= 1 # -1 because state is initial state + else: + code_gen_dict["$INNERMOST_STATE$"] = ["STATE_LOOP_W"] + loop_w_iterations -= 1 # -1 because state is initial state + + tail_incr_w = addr_incr_end_window + buffer_min_size - 1 + tail_incr_h = addr_incr_end_row + buffer_min_size - 1 + tail_incr_last_window = buffer_min_size - 1 + code_gen_dict["$IS_DEPTHWISE$"] = ["0"] + + # overwrite new loop bounds: + addr_incr_end_simd = 1 + addr_incr_end_window_elem = 1 + addr_incr_end_window_row = 1 + addr_incr_end_window = tail_incr_w + addr_incr_end_row = tail_incr_h + + # add init value for CURRENT_ELEM counter = last elem of first window + code_gen_dict["$FIRST_WRITE_ELEM$"] = [str(buffer_min_size - 1)] + + cntr_bitwidth = math.ceil( + math.log2( + max( + loop_h_iterations - 2 + 1, + loop_w_iterations - 2 + 1, + loop_kh_iterations - 2 + 1, + loop_kw_iterations - 2 + 1, + loop_simd_iterations - 2 + 1, + ) + ) + ) + code_gen_dict["$CNTR_BITWIDTH$"] = [str(cntr_bitwidth)] + code_gen_dict["$LOOP_H_ITERATIONS$"] = [str(loop_h_iterations - 2)] + code_gen_dict["$LOOP_W_ITERATIONS$"] = [str(loop_w_iterations - 2)] + code_gen_dict["$LOOP_KH_ITERATIONS$"] = [str(loop_kh_iterations - 2)] + code_gen_dict["$LOOP_KW_ITERATIONS$"] = [str(loop_kw_iterations - 2)] + code_gen_dict["$LOOP_SIMD_ITERATIONS$"] = [str(loop_simd_iterations - 2)] + + incr_bitwidth = 1 + math.ceil( + math.log2( + max( + abs(addr_incr_end_simd) + 1, + abs(addr_incr_end_window_elem) + 1, + abs(addr_incr_end_window_row) + 1, + abs(addr_incr_end_window) + 1, + abs(addr_incr_end_row) + 1, + abs(tail_incr_w) + 1, + abs(tail_incr_h) + 1, + abs(tail_incr_last_window) + 1, + ) + ) + ) + code_gen_dict["$INCR_BITWIDTH$"] = [str(incr_bitwidth)] + code_gen_dict["$HEAD_INCR_SIMD$"] = [str(addr_incr_end_simd)] + code_gen_dict["$HEAD_INCR_KW$"] = [str(addr_incr_end_window_elem)] + code_gen_dict["$HEAD_INCR_KH$"] = [str(addr_incr_end_window_row)] + code_gen_dict["$HEAD_INCR_W$"] = [str(addr_incr_end_window)] + code_gen_dict["$HEAD_INCR_H$"] = [str(addr_incr_end_row)] + code_gen_dict["$TAIL_INCR_W$"] = [str(tail_incr_w)] + code_gen_dict["$TAIL_INCR_H$"] = [str(tail_incr_h)] + code_gen_dict["$TAIL_INCR_LAST$"] = [str(tail_incr_last_window)] + + code_gen_dict["$SIMD$"] = [str(simd)] + code_gen_dict["$MMV_IN$"] = [str(mmv_in)] + code_gen_dict["$MMV_OUT$"] = [str(mmv_out)] + + # prepare buffer partitioning into "reg_fifos" and "bram_fifos" + # use normalized ([H,W]=[1,W]) dimensions for 1D case + ( + ifm_ch, + [ifm_dim_h, ifm_dim_w], + [ofm_dim_h, ofm_dim_w], + [k_h, k_w], + [stride_h, stride_w], + [dilation_h, dilation_w], + ) = self.get_1d_conv_attrs_normalized() + + reg_fifos = [] + bram_fifos_depth = [] + + px_idx = 0 + for ky in range(k_h): + reg_fifo = [] + for kx in range(k_w): + reg_fifo.append(px_idx) + px_idx += 1 + if kx < (k_w - 1): + reg_fifo.extend([-1] * (dilation_w - 1)) + px_idx += dilation_w - 1 + reg_fifos.append(reg_fifo) + + if ky < (k_h - 1): + line_buffer_len = (w - kernel_width) + w * (dilation_h - 1) + bram_fifos_depth.append(line_buffer_len) + px_idx += line_buffer_len + + code_gen_dict["$GENERATE_REG_FIFOS$"] = [] + for i, reg_fifo in enumerate(reg_fifos): + code_gen_dict["$GENERATE_REG_FIFOS$"].append( + """ + wire [IN_WIDTH-1:0] reg_fifo_{id}_in; + wire [IN_WIDTH-1:0] reg_fifo_{id}_out; + wire [IN_WIDTH*{len}-1:0] reg_fifo_{id}; + {name}_reg_buffer + #( + .WIDTH(IN_WIDTH), + .DEPTH({len}) + ) + reg_buffer_inst_{id} + ( + .CLK(CLK), + .shift_enable(shift_enable), + .shift_in(reg_fifo_{id}_in), + .shift_out(reg_fifo_{id}_out), + .data_out(reg_fifo_{id}) + );""".format( + name=self.get_verilog_top_module_name(), + id=i, + len=len(reg_fifo), + ) + ) + + code_gen_dict["$GENERATE_BRAM_FIFOS$"] = [] + for i, bram_fifo_depth in enumerate(bram_fifos_depth): + code_gen_dict["$GENERATE_BRAM_FIFOS$"].append( + """ + wire [IN_WIDTH-1:0] bram_fifo_{id}_in; + wire [IN_WIDTH-1:0] bram_fifo_{id}_out; + {name}_ram_buffer + #( + .WIDTH(IN_WIDTH), + .DEPTH({len}) + ) + ram_buffer_inst_{id} + ( + .CLK(CLK), + .RST(RST), + .shift_enable(shift_enable), + .shift_in(bram_fifo_{id}_in), + .shift_out(bram_fifo_{id}_out) + );""".format( + name=self.get_verilog_top_module_name(), + id=i, + len=bram_fifo_depth, + ) + ) + + code_gen_dict["$GENERATE_OUTPUT_MAPPING$"] = [] + out_idx = mmv_out - 1 + for fifo_id, reg_fifo in enumerate(reg_fifos): + for fifo_idx, access_idx in enumerate(reg_fifo): + if access_idx != -1: + code_gen_dict["$GENERATE_OUTPUT_MAPPING$"].append( + """assign data_out[OUT_ELEM_WIDTH*{out_idx}+:OUT_ELEM_WIDTH] + = reg_fifo_{fifo_id}[{access_idx}*{mmv}*OUT_ELEM_WIDTH+ + OUT_ELEM_WIDTH*{mmv_idx}+:OUT_ELEM_WIDTH];""".format( + out_idx=out_idx, + fifo_id=fifo_id, + access_idx=len(reg_fifo) + - 1 + - int((max(reg_fifo) - access_idx) / M), + mmv_idx=(max(reg_fifo) - access_idx) % M, + mmv=M, + ) + ) + # reversal: out_idx=0 -> oldest buffer element -> highest access_idx + out_idx = out_idx - 1 + assert out_idx == -1, "ERROR: Not all output vector elements connected" + + code_gen_dict["$GENERATE_BUFFER_CONNECTION$"] = [] + for i in range(len(reg_fifos)): + if i == 0: + # first FIFO containing newest elements -> input comes from input reg + code_gen_dict["$GENERATE_BUFFER_CONNECTION$"].append( + """assign reg_fifo_{fifo_id}_in = data_in;""".format( + fifo_id=i, + ) + ) + else: + # other REG FIFOs -> input comes from connected BRAM FIFO (line buffer) + input_fifo_id = i - 1 + code_gen_dict["$GENERATE_BUFFER_CONNECTION$"].append( + """assign reg_fifo_{fifo_id}_in = bram_fifo_{input_fifo_id}_out; + """.format( + fifo_id=i, input_fifo_id=input_fifo_id + ) + ) + for i in range(len(bram_fifos_depth)): + input_fifo_id = i + code_gen_dict["$GENERATE_BUFFER_CONNECTION$"].append( + """assign bram_fifo_{fifo_id}_in = reg_fifo_{input_fifo_id}_out; + """.format( + fifo_id=i, input_fifo_id=input_fifo_id + ) + ) + + return template_path, code_gen_dict + def select_impl_style(self): simd = self.get_nodeattr("SIMD") M = self.get_nodeattr("M") @@ -685,9 +960,6 @@ def select_impl_style(self): else: impl_style = "default" - assert ( - impl_style == "default" - ), "ERROR: Parallel window mode not yet implemented" return impl_style def generate_hdl(self): @@ -696,6 +968,8 @@ def generate_hdl(self): # prepare code generation by filling out dictionaries if impl_style == "default": template_path, code_gen_dict = self.prepare_codegen_default() + elif impl_style == "parallel": + template_path, code_gen_dict = self.prepare_codegen_parallel() else: raise Exception("Requested impl. style not implemented") From d222db36ee8e740931def8302a7b8e099fe18fbf Mon Sep 17 00:00:00 2001 From: icolbert Date: Thu, 1 Dec 2022 08:01:06 -0800 Subject: [PATCH 007/665] Updating MVAU LUT estimation - Using accDataType rather than an estimate - Updated the estimate equation for case when accDataType is not specified - Adding logic check that thresholds are also using LUTRAM rather than BRAM --- .../fpgadataflow/matrixvectoractivation.py | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index df9d1f1e70..ed19b93bb2 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -350,13 +350,23 @@ def lut_estimation(self): # adder tree addertree_luts = (W + A) * (2 * Q - 1) # accumulator - acc_bits = W + A + np.ceil(math.log(MW, 2)) + acc_datatype = self.get_accumulator_datatype() + # if accDataType is not set, then it will default to INT32, which would + # be a large overestimate in most (if not all) cases. In this scenario, + # we would use the minimum accumulator as determined by the data types. + alpha = math.log(MW, 2) + W + A - 1 - int(idt.signed()) + phi = lambda x_: math.log(1 + pow(2, -x_), 2) + acc_bits = min( + acc_datatype.bitwidth(), + np.ceil(alpha + phi(alpha) + 1) + ) acc_luts = acc_bits # thresholds and threshold comparators thr_luts = 0 comp_luts = 0 noact = self.get_nodeattr("noActivation") - if noact == 0: + tmem_style = self.get_nodeattr("ram_style_thresholds") + if (noact == 0) and (tmem_style == "distributed"): odt = self.get_output_datatype() B = odt.bitwidth() thr_luts = (2**B - 1) * acc_bits * math.ceil(self.calc_tmem() / 64) @@ -405,6 +415,10 @@ def get_input_datatype(self, ind=0): else: raise Exception("Undefined input ind for this layer type") + def get_accumulator_datatype(self): + """Returns FINN DataType of accumulator""" + return DataType[self.get_nodeattr("accDataType")] + def get_weight_datatype(self): """Returns FINN DataType of weights.""" return DataType[self.get_nodeattr("weightDataType")] From aaf03f5738d2daada44851f39e2442db1d44f9a2 Mon Sep 17 00:00:00 2001 From: icolbert Date: Thu, 1 Dec 2022 08:01:25 -0800 Subject: [PATCH 008/665] Updating VVAU LUT estimation - Using accDataType rather than an estimate - Updated the estimate equation for case when accDataType is not specified - Adding logic check that thresholds are also using LUTRAM rather than BRAM --- .../fpgadataflow/vectorvectoractivation.py | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index a411d245a9..a0b9268957 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -216,6 +216,10 @@ def get_weight_datatype(self): """Returns FINN DataType of weights.""" return DataType[self.get_nodeattr("weightDataType")] + def get_accumulator_datatype(self): + """Returns FINN DataType of accumulator""" + return DataType[self.get_nodeattr("accDataType")] + def get_output_datatype(self, ind=0): """Returns FINN DataType of output.""" return DataType[self.get_nodeattr("outputDataType")] @@ -1172,14 +1176,25 @@ def lut_estimation(self): else: mult_luts = (2 * math.ceil((W + A) / 6) - 1) * (W + A) # accumulator + acc_datatype = self.get_accumulator_datatype() + acc_bits = acc_datatype.bitwidth() k_h, k_w = self.get_nodeattr("Kernel") - acc_bits = W + A + math.ceil(math.log(k_h * k_w, 2)) + # if accDataType is not set, then it will default to INT32, which would + # be a large overestimate in most (if not all) cases. In this scenario, + # we would use the minimum accumulator as determined by the data types. + alpha = math.log(k_h * k_w, 2) + W + A - 1 - int(idt.signed()) + phi = lambda x_: math.log(1 + pow(2, -x_), 2) + acc_bits = min( + acc_datatype.bitwidth(), + np.ceil(alpha + phi(alpha) + 1) + ) acc_luts = acc_bits # thresholds and threshold comparators thr_luts = 0 comp_luts = 0 noact = self.get_nodeattr("noActivation") - if noact == 0: + tmem_style = self.get_nodeattr("ram_style_thresholds") + if (noact == 0) and (tmem_style == "distributed"): odt = self.get_output_datatype() B = odt.bitwidth() thr_luts = (2**B - 1) * acc_bits * math.ceil(self.calc_tmem() / 64) From 48095e47dd0b6f471a02f52223f8e244a9d763ee Mon Sep 17 00:00:00 2001 From: icolbert Date: Thu, 1 Dec 2022 08:32:40 -0800 Subject: [PATCH 009/665] Updating qonnx URL and commit --- fetch-repos.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fetch-repos.sh b/fetch-repos.sh index b0f6400ed1..b7b616e166 100755 --- a/fetch-repos.sh +++ b/fetch-repos.sh @@ -27,7 +27,7 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -QONNX_COMMIT="f702b17cdb9d5e57f85f43a5d33890647e063de6" +QONNX_COMMIT="13d777a2aa0dc449dc3de7aa369c1e155d6ce2c2 " FINN_EXP_COMMIT="9cbd2787b5160e2b44e0e8164a0df1457dbd5366" BREVITAS_COMMIT="a5b71d6de1389d3e7db898fef72e014842670f03" PYVERILATOR_COMMIT="766e457465f5c0dd315490d7b9cc5d74f9a76f4f" @@ -38,7 +38,7 @@ AVNET_BDF_COMMIT="2d49cfc25766f07792c0b314489f21fe916b639b" XIL_BDF_COMMIT="8cf4bb674a919ac34e3d99d8d71a9e60af93d14e" EXP_BOARD_FILES_MD5="30eecc497c31050bd46d10ea20eba232" -QONNX_URL="https://github.com/fastmachinelearning/qonnx.git" +QONNX_URL="https://github.com/i-colbert/qonnx.git" FINN_EXP_URL="https://github.com/Xilinx/finn-experimental.git" BREVITAS_URL="https://github.com/Xilinx/brevitas.git" PYVERILATOR_URL="https://github.com/maltanar/pyverilator.git" From df8a70fda5cc7f1d4876c70f3cec2e34f59bcbd8 Mon Sep 17 00:00:00 2001 From: icolbert Date: Mon, 5 Dec 2022 12:45:16 -0800 Subject: [PATCH 010/665] Update vectorvectoractivation.py --- src/finn/custom_op/fpgadataflow/vectorvectoractivation.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index a0b9268957..d5216a8711 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -1193,8 +1193,8 @@ def lut_estimation(self): thr_luts = 0 comp_luts = 0 noact = self.get_nodeattr("noActivation") - tmem_style = self.get_nodeattr("ram_style_thresholds") - if (noact == 0) and (tmem_style == "distributed"): + # TODO - add 'ram_style_threshold' node attribute + if noact == 0: odt = self.get_output_datatype() B = odt.bitwidth() thr_luts = (2**B - 1) * acc_bits * math.ceil(self.calc_tmem() / 64) From 7654dea277cbafc2c0571b72f106cf77a1908dc9 Mon Sep 17 00:00:00 2001 From: icolbert Date: Fri, 6 Jan 2023 08:41:45 -0800 Subject: [PATCH 011/665] Adding new function attribute to MVAU and VVAU --- .../fpgadataflow/matrixvectoractivation.py | 14 ++++++++++++++ .../fpgadataflow/vectorvectoractivation.py | 14 ++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index ed19b93bb2..6244bbc8e7 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -650,6 +650,20 @@ def minimize_accumulator_width(self, model): self.set_nodeattr("outputDataType", adt.name) return DataType[self.get_nodeattr("accDataType")] + def minimize_weight_bit_width(self, model): + weights = model.get_initializer(self.onnx_node.input[1]) + w_min = weights.min() + w_max = weights.max() + if w_min < 0: + if abs(w_min) > w_max: + wdt = DataType.get_smallest_possible(w_min) + else: + wdt = DataType.get_smallest_possible(-w_max - 1) + else: + wdt = DataType.get_smallest_possible(w_max) + self.set_nodeattr("weightDataType", wdt.name) + return DataType[self.get_nodeattr("weightDataType")] + def get_hls_compatible_threshold_tensor(self, orig_thres_matrix): """Convert the original numpy weight matrix orig_weight_matrix into a form suitable for passing to the hlslib call: diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index d5216a8711..665ff71810 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -169,6 +169,20 @@ def minimize_accumulator_width(self, model): self.set_nodeattr("outputDataType", adt.name) return DataType[self.get_nodeattr("accDataType")] + def minimize_weight_bit_width(self, model): + weights = model.get_initializer(self.onnx_node.input[1]) + w_min = weights.min() + w_max = weights.max() + if w_min < 0: + if abs(w_min) > w_max: + wdt = DataType.get_smallest_possible(w_min) + else: + wdt = DataType.get_smallest_possible(-w_max - 1) + else: + wdt = DataType.get_smallest_possible(w_max) + self.set_nodeattr("weightDataType", wdt.name) + return DataType[self.get_nodeattr("weightDataType")] + def calc_wmem(self): """Calculates and returns WMEM.""" ch = self.get_nodeattr("Channels") From f353feffc71a7918c75b1b91e11e111dd7ced539 Mon Sep 17 00:00:00 2001 From: icolbert Date: Fri, 6 Jan 2023 13:36:28 -0800 Subject: [PATCH 012/665] Adding check for runtime_writeable_weights --- .../fpgadataflow/matrixvectoractivation.py | 23 +++++++++++-------- .../fpgadataflow/vectorvectoractivation.py | 23 +++++++++++-------- 2 files changed, 26 insertions(+), 20 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index 6244bbc8e7..a1dff7a0ad 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -651,17 +651,20 @@ def minimize_accumulator_width(self, model): return DataType[self.get_nodeattr("accDataType")] def minimize_weight_bit_width(self, model): - weights = model.get_initializer(self.onnx_node.input[1]) - w_min = weights.min() - w_max = weights.max() - if w_min < 0: - if abs(w_min) > w_max: - wdt = DataType.get_smallest_possible(w_min) + """Minimize the bit width based on the values of the weights""" + runtime_writable = self.get_nodeattr("runtime_writeable_weights") == 0 + if runtime_writable: + weights = model.get_initializer(self.onnx_node.input[1]) + w_min = weights.min() + w_max = weights.max() + if w_min < 0: + if abs(w_min) > w_max: + wdt = DataType.get_smallest_possible(w_min) + else: + wdt = DataType.get_smallest_possible(-w_max - 1) else: - wdt = DataType.get_smallest_possible(-w_max - 1) - else: - wdt = DataType.get_smallest_possible(w_max) - self.set_nodeattr("weightDataType", wdt.name) + wdt = DataType.get_smallest_possible(w_max) + self.set_nodeattr("weightDataType", wdt.name) return DataType[self.get_nodeattr("weightDataType")] def get_hls_compatible_threshold_tensor(self, orig_thres_matrix): diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index 665ff71810..5d97244e5b 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -170,17 +170,20 @@ def minimize_accumulator_width(self, model): return DataType[self.get_nodeattr("accDataType")] def minimize_weight_bit_width(self, model): - weights = model.get_initializer(self.onnx_node.input[1]) - w_min = weights.min() - w_max = weights.max() - if w_min < 0: - if abs(w_min) > w_max: - wdt = DataType.get_smallest_possible(w_min) + """Minimize the bit width based on the values of the weights""" + runtime_writable = self.get_nodeattr("runtime_writeable_weights") == 0 + if runtime_writable: + weights = model.get_initializer(self.onnx_node.input[1]) + w_min = weights.min() + w_max = weights.max() + if w_min < 0: + if abs(w_min) > w_max: + wdt = DataType.get_smallest_possible(w_min) + else: + wdt = DataType.get_smallest_possible(-w_max - 1) else: - wdt = DataType.get_smallest_possible(-w_max - 1) - else: - wdt = DataType.get_smallest_possible(w_max) - self.set_nodeattr("weightDataType", wdt.name) + wdt = DataType.get_smallest_possible(w_max) + self.set_nodeattr("weightDataType", wdt.name) return DataType[self.get_nodeattr("weightDataType")] def calc_wmem(self): From 9f8701643e491030fdcbc0bccb181ca1bfa2bc39 Mon Sep 17 00:00:00 2001 From: Felix Jentzsch Date: Tue, 10 Jan 2023 18:43:28 +0100 Subject: [PATCH 013/665] [VVAU] Fix BIPOLAR/TERNARY compatibility --- .../fpgadataflow/vectorvectoractivation.py | 42 ++++++++-- src/finn/util/data_packing.py | 2 +- tests/fpgadataflow/test_fpgadataflow_vvau.py | 83 ++++++++++++------- 3 files changed, 86 insertions(+), 41 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index 813b673b39..6d4b5fb9e6 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -225,9 +225,9 @@ def get_output_datatype(self, ind=0): def get_instream_width(self, ind=0): i_bits = self.get_input_datatype().bitwidth() simd = self.get_nodeattr("SIMD") - #if simd > 1: - #pe = self.get_nodeattr("Channels") - #else: + # if simd > 1: + # pe = self.get_nodeattr("Channels") + # else: pe = self.get_nodeattr("PE") in_width = i_bits * simd * pe return in_width @@ -242,9 +242,9 @@ def get_folded_input_shape(self, ind=0): dim_h, dim_w = self.get_nodeattr("Dim") ch = self.get_nodeattr("Channels") simd = self.get_nodeattr("SIMD") - #if simd > 1: - #pe = self.get_nodeattr("Channels") - #else: + # if simd > 1: + # pe = self.get_nodeattr("Channels") + # else: pe = self.get_nodeattr("PE") sf = k_h * k_w // simd nf = ch // pe @@ -351,6 +351,9 @@ def get_hls_compatible_weight_tensor(self, orig_weight_matrix): ), """Weights matrix doesn't have expected shape (channels, 1, kernel_size, kernel_size)""" ret = orig_weight_matrix + if self.get_weight_datatype() == DataType["BIPOLAR"]: + # convert bipolar to binary + ret = (ret + 1) / 2 ret = ret.reshape(ch, k_h * k_w) # distribute rows between PEs ret = interleave_matrix_outer_dim_from_partitions(ret, pe) @@ -649,6 +652,12 @@ def execute_node(self, context, graph): not float32 as expected.""" expected_inp_shape = self.get_folded_input_shape() reshaped_input = context[inputs].reshape(expected_inp_shape) + if self.get_input_datatype() == DataType["BIPOLAR"]: + # store bipolar activations as binary + reshaped_input = (reshaped_input + 1) / 2 + export_idt = DataType["BINARY"] + else: + export_idt = self.get_input_datatype() # make copy before saving the array reshaped_input = reshaped_input.copy() np.save( @@ -664,14 +673,20 @@ def execute_node(self, context, graph): super().exec_precompiled_singlenode_model() # load output npy file super().npy_to_dynamic_output(context) + # reinterpret binary output as bipolar where needed + if self.get_output_datatype() == DataType["BIPOLAR"]: + out = context[node.output[0]] + out = 2 * out - 1 + context[node.output[0]] = out assert ( context[node.output[0]].shape == self.get_normal_output_shape() ), "cppsim did not produce expected output shape" elif mode == "rtlsim": sim = self.get_rtlsim() nbits = self.get_instream_width() - idt = self.get_input_datatype() - inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), idt, nbits) + inp = npy_to_rtlsim_input( + "{}/input_0.npy".format(code_gen_dir), export_idt, nbits + ) super().reset_rtlsim(sim) super().toggle_clk(sim) @@ -756,6 +771,9 @@ def defines(self, var): def read_npy_data(self): code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") dtype = self.get_input_datatype() + if dtype == DataType["BIPOLAR"]: + # use binary for bipolar storage + dtype = DataType["BINARY"] elem_bits = dtype.bitwidth() packed_bits = self.get_instream_width() packed_hls_type = "ap_uint<%d>" % packed_bits @@ -826,6 +844,11 @@ def docompute(self): ) ] elif mem_mode == "decoupled" or mem_mode == "external": + simd = self.get_nodeattr("SIMD") + if simd > 1: + raise Exception( + "SIMD parallelism not supported for decoupled or external mode" + ) wdt = self.get_weight_datatype() if wdt == DataType["BIPOLAR"]: export_wdt = DataType["BINARY"] @@ -853,6 +876,9 @@ def docompute(self): def dataoutstrm(self): code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") dtype = self.get_output_datatype() + if dtype == DataType["BIPOLAR"]: + # use binary for bipolar storage + dtype = DataType["BINARY"] elem_bits = dtype.bitwidth() packed_bits = self.get_outstream_width() packed_hls_type = "ap_uint<%d>" % packed_bits diff --git a/src/finn/util/data_packing.py b/src/finn/util/data_packing.py index 65478d2540..f7ea2ff943 100644 --- a/src/finn/util/data_packing.py +++ b/src/finn/util/data_packing.py @@ -220,7 +220,7 @@ def unpack_innermost_dim_from_hex_string( if conv_dtype == DataType["BIPOLAR"]: ar_list = [2 * x - 1 for x in ar_list] # interpret values as signed values - elif conv_dtype.name.startswith("INT"): + elif dtype.signed(): mask = 2 ** (conv_dtype.bitwidth() - 1) ar_list = [-(x & mask) + (x & ~mask) for x in ar_list] diff --git a/tests/fpgadataflow/test_fpgadataflow_vvau.py b/tests/fpgadataflow/test_fpgadataflow_vvau.py index ea4be47334..a418de5728 100644 --- a/tests/fpgadataflow/test_fpgadataflow_vvau.py +++ b/tests/fpgadataflow/test_fpgadataflow_vvau.py @@ -27,30 +27,29 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import pytest + import numpy as np from onnx import TensorProto, helper from qonnx.core.datatype import DataType from qonnx.core.modelwrapper import ModelWrapper from qonnx.custom_op.general.multithreshold import multithreshold - -# from qonnx.custom_op.registry import getCustomOp +from qonnx.custom_op.registry import getCustomOp from qonnx.transformation.general import GiveUniqueNodeNames -from qonnx.util.basic import gen_finn_dt_tensor from qonnx.transformation.infer_datatypes import InferDataTypes from qonnx.transformation.infer_shapes import InferShapes +from qonnx.util.basic import gen_finn_dt_tensor import finn.core.onnx_exec as oxe - -# from finn.analysis.fpgadataflow.exp_cycles_per_layer import exp_cycles_per_layer +from finn.analysis.fpgadataflow.exp_cycles_per_layer import exp_cycles_per_layer from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP +from finn.transformation.fpgadataflow.minimize_accumulator_width import ( + MinimizeAccumulatorWidth, +) from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode -from finn.transformation.fpgadataflow.minimize_accumulator_width import ( - MinimizeAccumulatorWidth, -) def _infer_sparse_weight_tensor(W_conv, k_h, k_w, channels): @@ -110,7 +109,10 @@ def _make_single_vvau_modelwrapper( if T is not None: no_act = 0 node_inp_list = ["inp", "weights", "thresh"] - actval = odt.min() + if odt == DataType["BIPOLAR"]: + actval = 0 + else: + actval = odt.min() else: no_act = 1 node_inp_list = ["inp", "weights"] @@ -167,15 +169,15 @@ def prepare_inputs(input_tensor): # input datatype -@pytest.mark.parametrize("idt", [DataType["UINT4"]]) +@pytest.mark.parametrize("idt", [DataType["BIPOLAR"], DataType["UINT4"]]) # weight datatype -@pytest.mark.parametrize("wdt", [DataType["UINT4"]]) +@pytest.mark.parametrize("wdt", [DataType["BIPOLAR"], DataType["UINT4"]]) # activation: None or DataType -@pytest.mark.parametrize("act", [DataType["UINT4"], None]) +@pytest.mark.parametrize("act", [DataType["BIPOLAR"], DataType["UINT4"], None]) # PE -@pytest.mark.parametrize("pe", [1,2,3,6]) +@pytest.mark.parametrize("pe", [1, 3, 6]) # SIMD -@pytest.mark.parametrize("simd", [1,9]) +@pytest.mark.parametrize("simd", [1, 9]) # Input image shape @pytest.mark.parametrize("dim_h", [10]) @pytest.mark.parametrize("dim_w", [10]) @@ -187,7 +189,7 @@ def prepare_inputs(input_tensor): # memory mode @pytest.mark.parametrize("mem_mode", ["const"]) # execution mode -@pytest.mark.parametrize("exec_mode", ["cppsim","rtlsim"]) +@pytest.mark.parametrize("exec_mode", ["cppsim", "rtlsim"]) @pytest.mark.fpgadataflow @pytest.mark.slow @pytest.mark.vivado @@ -203,9 +205,6 @@ def test_fpgadataflow_vvau( if channels % pe != 0: pytest.skip("Requirement Channels divisable by PE is violated.") - #if pe < channels and simd > 1: - # pytest.skip("Do not apply SIMD parallelism before max PE parallelism") - # Generate weights in expected shape for ONNX and HLS node W = gen_finn_dt_tensor(wdt, (channels, 1, k_h, k_w)) # shape: [channels, 1, k, k] W_onnx = _infer_sparse_weight_tensor( @@ -221,14 +220,23 @@ def test_fpgadataflow_vvau( if act is None: T = None tdt = None - odt = DataType["INT32"] + if wdt == DataType["BIPOLAR"] and idt == DataType["BIPOLAR"]: + odt = DataType["UINT32"] + else: + odt = DataType["INT32"] else: odt = act - (min_v, max_v) = _calculate_dot_prod_range(idt, wdt, k_h * k_w * channels) + (min_v, max_v) = _calculate_dot_prod_range(idt, wdt, k_h * k_w) n_steps = act.get_num_possible_values() - 1 T = np.random.randint(min_v, max_v - 1, (channels, n_steps)).astype(np.float32) T = np.sort(T, axis=1) - tdt = DataType["INT32"] + if wdt == DataType["BIPOLAR"] and idt == DataType["BIPOLAR"]: + tdt = DataType["UINT32"] + # bias thresholds to be positive + T = np.ceil((T + (k_h * k_w)) / 2) + assert (T >= 0).all() + else: + tdt = DataType["INT32"] model = _make_single_vvau_modelwrapper( W, pe, simd, k_h, k_w, channels, dim_h, dim_w, wdt, idt, odt, T, tdt, mem_mode @@ -250,14 +258,25 @@ def test_fpgadataflow_vvau( input_dict = prepare_inputs(x_vvau) # Calculate output - y_expected = np.matmul(x, W_onnx) # Y is in [N, H, W, C] format + if wdt == DataType["BIPOLAR"] and idt == DataType["BIPOLAR"]: + # Simulate XNOR-popcount matrix multiplication, see + # qonnx.custom_op.general.xnorpopcount (not usable due to sparse W) + y_expected = np.matmul(x, W_onnx) + y_expected = (y_expected + (k_h * k_w)) / 2 + else: + y_expected = np.matmul(x, W_onnx) # Y is in [N, H, W, C] format + if T is not None: # Reshape Y, as multithreshold expects Y to be in [N, C, H, W] format y_expected = np.transpose(y_expected, (0, 3, 1, 2)) y_expected = multithreshold(y_expected, T) y_expected = np.transpose(y_expected, (0, 2, 3, 1)) - # signed offset - y_expected += act.min() + if act == DataType["BIPOLAR"]: + # binary to bipolar + y_expected = 2 * y_expected - 1 + else: + # signed offset + y_expected += act.min() y_produced = oxe.execute_onnx(model, input_dict, return_full_exec_context=False)[ "outp" @@ -265,11 +284,11 @@ def test_fpgadataflow_vvau( assert (y_produced == y_expected).all(), "incorrect result" - # if exec_mode == "rtlsim": - # node = model.get_nodes_by_op_type("VectorVectorActivation")[0] - # inst = getCustomOp(node) - # cycles_rtlsim = inst.get_nodeattr("cycles_rtlsim") - # exp_cycles_dict = model.analysis(exp_cycles_per_layer) - # exp_cycles = exp_cycles_dict[node.name] - # assert np.isclose(exp_cycles, cycles_rtlsim, atol=10) - # assert exp_cycles != 0 + if exec_mode == "rtlsim": + node = model.get_nodes_by_op_type("VectorVectorActivation")[0] + inst = getCustomOp(node) + cycles_rtlsim = inst.get_nodeattr("cycles_rtlsim") + exp_cycles_dict = model.analysis(exp_cycles_per_layer) + exp_cycles = exp_cycles_dict[node.name] + assert np.isclose(exp_cycles, cycles_rtlsim, atol=10) + assert exp_cycles != 0 From da8295794be7a970a78c22ff3efc49926962c548 Mon Sep 17 00:00:00 2001 From: icolbert Date: Mon, 16 Jan 2023 11:52:42 -0800 Subject: [PATCH 014/665] Fixing reproducibility issue with FINN_BUILD_DIR --- src/finn/util/basic.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/finn/util/basic.py b/src/finn/util/basic.py index 4aba87216c..a252d323dc 100644 --- a/src/finn/util/basic.py +++ b/src/finn/util/basic.py @@ -121,7 +121,7 @@ def make_build_dir(prefix=""): try: tmpdir = tempfile.mkdtemp(prefix=prefix) newdir = tmpdir.replace("/tmp", os.environ["FINN_BUILD_DIR"]) - os.makedirs(newdir) + os.makedirs(newdir, exist_ok=True) return newdir except KeyError: raise Exception( From 1add5a6785ae4e2bab7df0b1206e223daf586715 Mon Sep 17 00:00:00 2001 From: icolbert Date: Tue, 17 Jan 2023 09:14:02 -0800 Subject: [PATCH 015/665] Create minimize_weight_bit_width.py --- .../fpgadataflow/minimize_weight_bit_width.py | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 src/finn/transformation/fpgadataflow/minimize_weight_bit_width.py diff --git a/src/finn/transformation/fpgadataflow/minimize_weight_bit_width.py b/src/finn/transformation/fpgadataflow/minimize_weight_bit_width.py new file mode 100644 index 0000000000..de16c65912 --- /dev/null +++ b/src/finn/transformation/fpgadataflow/minimize_weight_bit_width.py @@ -0,0 +1,49 @@ +# Copyright (c) 2023, Xilinx +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from qonnx.custom_op.registry import getCustomOp +from qonnx.transformation.base import Transformation + +from finn.util.fpgadataflow import is_fpgadataflow_node + + +class MinimizeWeightBitWidth(Transformation): + """For relevant nodes, call the weight bit width minimization + functions to save on resources. May alter tensor weightDataType + if the node does not have runtime writeable weights.""" + + def __init__(self): + super().__init__() + + def apply(self, model): + for node in model.graph.node: + if is_fpgadataflow_node(node) is True: + inst = getCustomOp(node) + if hasattr(inst, "minimize_weight_bit_width"): + inst.minimize_weight_bit_width(model) + return (model, False) \ No newline at end of file From b4d66ed42bd258cda7b78ef5fa9eff2bc546081a Mon Sep 17 00:00:00 2001 From: icolbert Date: Tue, 17 Jan 2023 09:17:12 -0800 Subject: [PATCH 016/665] Fixing if-else logic to make more sense --- src/finn/custom_op/fpgadataflow/matrixvectoractivation.py | 3 +-- src/finn/custom_op/fpgadataflow/vectorvectoractivation.py | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index a1dff7a0ad..2ac9ad2867 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -652,8 +652,7 @@ def minimize_accumulator_width(self, model): def minimize_weight_bit_width(self, model): """Minimize the bit width based on the values of the weights""" - runtime_writable = self.get_nodeattr("runtime_writeable_weights") == 0 - if runtime_writable: + if not self.get_nodeattr("runtime_writeable_weights"): weights = model.get_initializer(self.onnx_node.input[1]) w_min = weights.min() w_max = weights.max() diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index 5d97244e5b..fd74a7b0c9 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -171,8 +171,7 @@ def minimize_accumulator_width(self, model): def minimize_weight_bit_width(self, model): """Minimize the bit width based on the values of the weights""" - runtime_writable = self.get_nodeattr("runtime_writeable_weights") == 0 - if runtime_writable: + if not self.get_nodeattr("runtime_writeable_weights"): weights = model.get_initializer(self.onnx_node.input[1]) w_min = weights.min() w_max = weights.max() From 74dafc8444b42d6a7cb2751f84a5a6d261557272 Mon Sep 17 00:00:00 2001 From: Felix Jentzsch Date: Wed, 18 Jan 2023 15:10:21 +0100 Subject: [PATCH 017/665] [VVAU] SIMD support for decoupled mode --- .../custom_op/fpgadataflow/vectorvectoractivation.py | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index 6d4b5fb9e6..72158ffcd6 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -473,7 +473,7 @@ def make_weight_file(self, weights, weight_file_mode, weight_file_name): weight_tensor_pe_flipped = np.flip(weight_tensor_unflipped, axis=-2) # reshape weight tensor (simd_flipped and pe_flipped) to desired shape pe = self.get_nodeattr("PE") - simd = 1 + simd = self.get_nodeattr("SIMD") # simd_flipped weight_tensor_simd_flipped = weight_tensor_simd_flipped.reshape( 1, -1, pe * simd @@ -844,11 +844,6 @@ def docompute(self): ) ] elif mem_mode == "decoupled" or mem_mode == "external": - simd = self.get_nodeattr("SIMD") - if simd > 1: - raise Exception( - "SIMD parallelism not supported for decoupled or external mode" - ) wdt = self.get_weight_datatype() if wdt == DataType["BIPOLAR"]: export_wdt = DataType["BINARY"] @@ -1249,9 +1244,10 @@ def get_weightstream_width(self): self.get_nodeattr("mem_mode") == "decoupled" or self.get_nodeattr("mem_mode") == "external" ): + simd = self.get_nodeattr("SIMD") pe = self.get_nodeattr("PE") wp = self.get_weight_datatype().bitwidth() - w_width = pe * wp + w_width = simd * pe * wp return w_width else: return 0 From 962a5585b5f03b4fd2ffbe128c0b4ab7179292c9 Mon Sep 17 00:00:00 2001 From: icolbert Date: Wed, 18 Jan 2023 08:31:19 -0800 Subject: [PATCH 018/665] Fixing headers to minimize_weight_bit_width.py --- .../transformation/fpgadataflow/minimize_weight_bit_width.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/finn/transformation/fpgadataflow/minimize_weight_bit_width.py b/src/finn/transformation/fpgadataflow/minimize_weight_bit_width.py index de16c65912..147f8281a7 100644 --- a/src/finn/transformation/fpgadataflow/minimize_weight_bit_width.py +++ b/src/finn/transformation/fpgadataflow/minimize_weight_bit_width.py @@ -1,4 +1,4 @@ -# Copyright (c) 2023, Xilinx +# Copyright (C) 2023, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without From 9ce9dfec374def40ec7ee2eae1acc738be5d4aa0 Mon Sep 17 00:00:00 2001 From: icolbert Date: Wed, 18 Jan 2023 09:03:17 -0800 Subject: [PATCH 019/665] Update basic.py --- src/finn/util/basic.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/finn/util/basic.py b/src/finn/util/basic.py index a252d323dc..4aba87216c 100644 --- a/src/finn/util/basic.py +++ b/src/finn/util/basic.py @@ -121,7 +121,7 @@ def make_build_dir(prefix=""): try: tmpdir = tempfile.mkdtemp(prefix=prefix) newdir = tmpdir.replace("/tmp", os.environ["FINN_BUILD_DIR"]) - os.makedirs(newdir, exist_ok=True) + os.makedirs(newdir) return newdir except KeyError: raise Exception( From fa5fa3879612310b40d2ebb4d336a7bcc82bd0a2 Mon Sep 17 00:00:00 2001 From: Rachit Garg Date: Sun, 22 Jan 2023 18:30:32 +0100 Subject: [PATCH 020/665] Add Ultra96-V2 --- src/finn/util/basic.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/finn/util/basic.py b/src/finn/util/basic.py index 4aba87216c..60f2446f59 100644 --- a/src/finn/util/basic.py +++ b/src/finn/util/basic.py @@ -34,6 +34,7 @@ # mapping from PYNQ board names to FPGA part names pynq_part_map = dict() pynq_part_map["Ultra96"] = "xczu3eg-sbva484-1-e" +pynq_part_map["Ultra96-V2"] = "xczu3eg-sbva484-1-i" pynq_part_map["Pynq-Z1"] = "xc7z020clg400-1" pynq_part_map["Pynq-Z2"] = "xc7z020clg400-1" pynq_part_map["ZCU102"] = "xczu9eg-ffvb1156-2-e" @@ -46,6 +47,7 @@ pynq_native_port_width["Pynq-Z1"] = 64 pynq_native_port_width["Pynq-Z2"] = 64 pynq_native_port_width["Ultra96"] = 128 +pynq_native_port_width["Ultra96-V2"] = 128 pynq_native_port_width["ZCU102"] = 128 pynq_native_port_width["ZCU104"] = 128 pynq_native_port_width["ZCU111"] = 128 From 6c0f869e36857546af5b3f24c833a89800ffd53a Mon Sep 17 00:00:00 2001 From: Rachit Garg Date: Sun, 22 Jan 2023 18:34:08 +0100 Subject: [PATCH 021/665] Added Ultra96-V2 --- src/finn/transformation/fpgadataflow/templates.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/finn/transformation/fpgadataflow/templates.py b/src/finn/transformation/fpgadataflow/templates.py index 78bcdea0d7..757b1382c3 100644 --- a/src/finn/transformation/fpgadataflow/templates.py +++ b/src/finn/transformation/fpgadataflow/templates.py @@ -120,6 +120,9 @@ } elseif {$BOARD == "Ultra96"} { set_property board_part avnet.com:ultra96v1:part0:1.2 [current_project] set ZYNQ_TYPE "zynq_us+" +} elseif {$BOARD == "Ultra96-V2"} { + set_property board_part avnet.com:ultra96v2:part0:1.2 [current_project] + set ZYNQ_TYPE "zynq_us+" } elseif {$BOARD == "Pynq-Z2"} { set ZYNQ_TYPE "zynq_7000" set_property board_part tul.com.tw:pynq-z2:part0:1.0 [current_project] From 61ac5b62e4da00837542d814c656798930deb6bf Mon Sep 17 00:00:00 2001 From: Felix Jentzsch Date: Thu, 26 Jan 2023 14:01:41 +0100 Subject: [PATCH 022/665] [VVAU] update resource estimates --- .../fpgadataflow/vectorvectoractivation.py | 61 +++++++++++++------ 1 file changed, 43 insertions(+), 18 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index 72158ffcd6..2e86d72d04 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -218,6 +218,10 @@ def get_weight_datatype(self): """Returns FINN DataType of weights.""" return DataType[self.get_nodeattr("weightDataType")] + def get_accumulator_datatype(self): + """Returns FINN DataType of accumulator""" + return DataType[self.get_nodeattr("accDataType")] + def get_output_datatype(self, ind=0): """Returns FINN DataType of output.""" return DataType[self.get_nodeattr("outputDataType")] @@ -1115,7 +1119,7 @@ def code_generation_ipi(self): def uram_estimation(self): P = self.get_nodeattr("PE") - Q = 1 + Q = self.get_nodeattr("SIMD") wdt = self.get_weight_datatype() W = wdt.bitwidth() omega = self.calc_wmem() @@ -1124,7 +1128,7 @@ def uram_estimation(self): mstyle = self.get_nodeattr("ram_style") if ( (mmode == "decoupled" and mstyle != "ultra") - or (mmode == "const" and self.calc_wmem() <= 128) + or (mmode == "const") or (mmode == "external") ): return 0 @@ -1136,9 +1140,11 @@ def bram_estimation(self): """Calculates resource estimation for BRAM""" # TODO add in/out FIFO contributions P = self.get_nodeattr("PE") + Q = self.get_nodeattr("SIMD") wdt = self.get_weight_datatype() W = wdt.bitwidth() omega = self.calc_wmem() + mem_width = Q * W * P # assuming SDP mode RAMB18s (see UG573 Table 1-10) # since this is HLS memory, not using the full width of a BRAM # assuming memories up to 128 deep get implemented in LUTs @@ -1146,23 +1152,24 @@ def bram_estimation(self): mstyle = self.get_nodeattr("ram_style") if ( (mmode == "decoupled" and mstyle in ["distributed", "ultra"]) + or (mstyle == "auto" and self.calc_wmem() <= 128) or (mmode == "const" and self.calc_wmem() <= 128) or (mmode == "external") ): return 0 - if W == 1: - return math.ceil(omega / 16384) * P - elif W == 2: - return math.ceil(omega / 8192) * P - elif W <= 4: - return (math.ceil(omega / 4096)) * (math.ceil(W / 4)) * P - elif W <= 9: - return (math.ceil(omega / 2048)) * (math.ceil(W / 8)) * P - elif W <= 18 or omega > 512: - return (math.ceil(omega / 1024)) * (math.ceil(W / 16)) * P + if mem_width == 1: + return math.ceil(omega / 16384) + elif mem_width == 2: + return math.ceil(omega / 8192) + elif mem_width <= 4: + return (math.ceil(omega / 4096)) * (math.ceil(mem_width / 4)) + elif mem_width <= 9: + return (math.ceil(omega / 2048)) * (math.ceil(mem_width / 8)) + elif mem_width <= 18 or omega > 512: + return (math.ceil(omega / 1024)) * (math.ceil(mem_width / 16)) else: - return (math.ceil(omega / 512)) * (math.ceil(W / 32)) * P + return (math.ceil(omega / 512)) * (math.ceil(mem_width / 32)) def bram_efficiency_estimation(self): P = self.get_nodeattr("PE") @@ -1186,6 +1193,7 @@ def lut_estimation(self): """ # TODO add in/out FIFO contributions P = self.get_nodeattr("PE") + Q = self.get_nodeattr("SIMD") wdt = self.get_weight_datatype() W = wdt.bitwidth() # determine tdt with input and weight data types @@ -1200,29 +1208,46 @@ def lut_estimation(self): if (mmode == "decoupled" and mstyle == "distributed") or ( mmode == "const" and self.calc_wmem() <= 128 ): - c2 = (P * W) * math.ceil(self.calc_wmem() / 64) + c2 = (P * Q * W) * math.ceil(self.calc_wmem() / 64) # multiplication res_type = self.get_nodeattr("resType") if res_type == "dsp": mult_luts = 0 else: - mult_luts = (2 * math.ceil((W + A) / 6) - 1) * (W + A) + mult_luts = Q * (2 * math.ceil((W + A) / 6) - 1) * (W + A) + # adder tree + addertree_luts = (W + A) * (2 * Q - 1) # accumulator + acc_datatype = self.get_accumulator_datatype() + acc_bits = acc_datatype.bitwidth() k_h, k_w = self.get_nodeattr("Kernel") - acc_bits = W + A + math.ceil(math.log(k_h * k_w, 2)) + # if accDataType is not set, then it will default to INT32, which would + # be a large overestimate in most (if not all) cases. In this scenario, + # we would use the minimum accumulator as determined by the data types. + alpha = math.log(k_h * k_w, 2) + W + A - 1 - int(idt.signed()) + + def phi(x_): + return math.log(1 + pow(2, -x_), 2) + + acc_bits = min(acc_datatype.bitwidth(), np.ceil(alpha + phi(alpha) + 1)) acc_luts = acc_bits # thresholds and threshold comparators thr_luts = 0 comp_luts = 0 noact = self.get_nodeattr("noActivation") + # TODO - add 'ram_style_threshold' node attribute if noact == 0: odt = self.get_output_datatype() B = odt.bitwidth() - thr_luts = (2**B - 1) * acc_bits * math.ceil(self.calc_tmem() / 64) + thr_luts = (2**B - 1) * acc_bits * self.calc_tmem() / 64 comp_luts = (2**B - 1) * acc_bits - return int(c0 + c1 * (P * (mult_luts + acc_luts + thr_luts + comp_luts)) + c2) + return int( + c0 + + c1 * (P * (mult_luts + addertree_luts + acc_luts + thr_luts + comp_luts)) + + c2 + ) def dsp_estimation(self): # multiplication From 7f4b20f62a964cfca9d04fca7ab08486b6da3998 Mon Sep 17 00:00:00 2001 From: Felix Jentzsch Date: Fri, 27 Jan 2023 17:54:08 +0100 Subject: [PATCH 023/665] [SWG] Adjust resource estimates, set_folding --- finn-rtllib/swg/swg_template_parallel.sv | 68 +++--- src/finn/builder/build_dataflow_steps.py | 1 + .../convolutioninputgenerator_rtl.py | 207 ++++++++++-------- .../fpgadataflow/set_folding.py | 42 +++- ...est_fpgadataflow_convinputgenerator_rtl.py | 8 +- 5 files changed, 192 insertions(+), 134 deletions(-) diff --git a/finn-rtllib/swg/swg_template_parallel.sv b/finn-rtllib/swg/swg_template_parallel.sv index 432c374764..767f9c6f85 100644 --- a/finn-rtllib/swg/swg_template_parallel.sv +++ b/finn-rtllib/swg/swg_template_parallel.sv @@ -192,7 +192,7 @@ output [WIDTH-1:0] shift_out; reg [WIDTH-1:0] out_reg; assign shift_out = out_reg; -integer addr_w, addr_r; //TODO: minimize width + simplify +integer addr_w, addr_r; $RAM_STYLE$ reg [WIDTH-1:0] ram [DEPTH-1:0]; @@ -221,9 +221,9 @@ endmodule : $TOP_MODULE_NAME$_ram_buffer module $TOP_MODULE_NAME$_wb #( - parameter IN_WIDTH = 1, //bit-width*C*MMV_in - parameter OUT_ELEM_WIDTH = 1, //bit-width*C - parameter OUT_WIDTH = 1, //bit-width*C*MMV_out + parameter IN_WIDTH = 1, // bit-width*C*MMV_in + parameter OUT_ELEM_WIDTH = 1, // bit-width*C + parameter OUT_WIDTH = 1, // bit-width*C*MMV_out parameter BUFFER_ELEM_TOTAL = 1 ) ( @@ -243,13 +243,12 @@ $GENERATE_REG_FIFOS$ $GENERATE_BRAM_FIFOS$ -//Fixed interconnect between linear buffers +// fixed interconnect between linear buffers $GENERATE_BUFFER_CONNECTION$ -//Fixed REG FIFO <-> output mapping +// fixed REG FIFO -> output mapping $GENERATE_OUTPUT_MAPPING$ - endmodule : $TOP_MODULE_NAME$_wb module $TOP_MODULE_NAME$_impl #( @@ -279,7 +278,7 @@ module $TOP_MODULE_NAME$_impl #( localparam int unsigned BUF_OUT_ELEM_WIDTH = BIT_WIDTH * SIMD; localparam int unsigned BUF_OUT_WIDTH = BIT_WIDTH * SIMD * MMV_OUT; - //main buffer instantiation + // main buffer instantiation uwire [BUF_IN_WIDTH -1:0] window_buffer_in; uwire [BUF_OUT_WIDTH-1:0] window_buffer_out; uwire window_buffer_shift_enable; @@ -299,7 +298,7 @@ module $TOP_MODULE_NAME$_impl #( .data_out(window_buffer_out) ); - //controller instantiation + // controller instantiation uwire advance_controller; uwire signed [INCR_BITWIDTH-1:0] addr_incr; uwire [INCR_BITWIDTH-1:0] tail_incr; @@ -311,27 +310,22 @@ module $TOP_MODULE_NAME$_impl #( .tail_incr(tail_incr) ); - // Counters/address registers - // Add a sign bit even to (most) unsigned counters and Window_buffer_read_addr_reg, - // so we can use automatic sign extension and simplify calculations w/ signed increment. - // Alternatively, we could manually sign-extend and shave off a bit here or there. + // counters/address registers logic signed [$clog2(LAST_READ_ELEM+1)+1-1:0] Newest_buffered_elem = -1; logic [$clog2(LAST_READ_ELEM+1)+1-1:0] Current_elem = FIRST_WRITE_ELEM; logic [$clog2(LAST_READ_ELEM+1)+1-1:0] First_elem_next_window = 0; - // Control signals/registers - logic Writing_done = 0; - logic write_done = 0; - - uwire write_ok = write_cmd && (out_V_V_TREADY || write_done); - uwire write_blocked = write_cmd && !out_V_V_TREADY && !write_done; - - uwire write_cmd = !($signed(Current_elem) > Newest_buffered_elem) && !Writing_done;; + // control registers/signals + logic Writing_done = 0; + logic Write_done = 0; + uwire write_ok = write_cmd && (out_V_V_TREADY || Write_done); + uwire write_blocked = write_cmd && !out_V_V_TREADY && !Write_done; + uwire write_cmd = !($signed(Current_elem) > Newest_buffered_elem) && !Writing_done;; uwire reading_done = Newest_buffered_elem == LAST_READ_ELEM; - uwire read_cmd = + uwire read_cmd = !reading_done && ( // if there is still an input element left to read - Writing_done || ( // if fetching is done (e.g. for skipped rows at FM end due to stride) + Writing_done || ( // if writing is done (e.g. for skipped rows at FM end due to stride) $signed(((Newest_buffered_elem - (BUF_ELEM_TOTAL - 1)))) < $signed(First_elem_next_window) && $signed(((Newest_buffered_elem - (BUF_ELEM_TOTAL - 1)))) < $signed(Current_elem) ) // (over-)write to buffer if oldest buffered element will no longer be needed @@ -339,27 +333,27 @@ module $TOP_MODULE_NAME$_impl #( uwire read_ok = read_cmd && in0_V_V_TVALID && !write_blocked; // includes waiting on W if W-only cycle: wait only on W no R/W to wait for - uwire advance = read_ok || (!read_cmd && write_ok) || (!read_cmd && !write_cmd); + uwire advance = read_ok || (!read_cmd && write_ok) || (!read_cmd && !write_cmd); - //assign buffer control + // assign buffer control assign window_buffer_shift_enable = advance; assign advance_controller = write_ok; - //assign I/O ports + // assign I/O ports assign window_buffer_in = in0_V_V_TDATA; assign out_V_V_TDATA = window_buffer_out; assign in0_V_V_TREADY = ap_rst_n && read_ok; //only asserted if data is available and we can store it (allowed) - assign out_V_V_TVALID = ap_rst_n && write_cmd && !write_done; //only asserted if we have data available and it has not been read yet (don't wait for READY from sink) + assign out_V_V_TVALID = ap_rst_n && write_cmd && !Write_done; //only asserted if we have data available and it has not been read yet (don't wait for READY from sink) - //write done logic + // write done logic always_ff @(posedge ap_clk) begin if (advance) begin - write_done <= 1'b0; //reset flag - end else if (write_ok) // successful W in this cycle, but R still outstanding - write_done <= 1'b1; //write can happen even if read is blocked, but only for the current cycle! + Write_done <= 1'b0; //reset flag + end else if (write_ok) //successful W in this cycle, but R still outstanding + Write_done <= 1'b1; //write can happen even if read is blocked, but only for the current cycle! end - //main process for advancing counters + // main process for advancing counters always_ff @(posedge ap_clk) begin if(!ap_rst_n) begin Newest_buffered_elem <= -1; @@ -371,10 +365,10 @@ module $TOP_MODULE_NAME$_impl #( if (read_ok) begin Newest_buffered_elem <= Newest_buffered_elem+1; - //check if this is the last read cycle (reading_done will be true afterwards) + // check if this is the last read cycle (reading_done will be true afterwards) if ((Newest_buffered_elem == LAST_READ_ELEM-1) && Writing_done) begin - //start processing of next FM if writing is done already (possible due to unused input elements at the tail end) - //todo: allow for read overlapping between feature maps (i.e., reading first elements from next FM while still writing last window of current FM) + // start processing of next FM if writing is done already (possible due to unused input elements at the tail end) + // todo: allow for read overlapping between feature maps (i.e., reading first elements from next FM while still writing last window of current FM) Newest_buffered_elem <= -1; Current_elem <= FIRST_WRITE_ELEM; First_elem_next_window <= 0; @@ -385,12 +379,12 @@ module $TOP_MODULE_NAME$_impl #( if (write_ok) begin First_elem_next_window <= First_elem_next_window + tail_incr; - //check if this is the last write cycle (Writing_done will be true afterwards) + // check if this is the last write cycle (Writing_done will be true afterwards) if (Current_elem == LAST_WRITE_ELEM) begin Writing_done <= 1; if (reading_done || (read_ok && (Newest_buffered_elem == LAST_READ_ELEM - 1))) begin - //start processing of next FM if reading is done already, or completes in the same cycle + // start processing of next FM if reading is done already, or completes in the same cycle Newest_buffered_elem <= -1; Current_elem <= FIRST_WRITE_ELEM; First_elem_next_window <= 0; diff --git a/src/finn/builder/build_dataflow_steps.py b/src/finn/builder/build_dataflow_steps.py index 956b4fd3be..9a6966ac9b 100644 --- a/src/finn/builder/build_dataflow_steps.py +++ b/src/finn/builder/build_dataflow_steps.py @@ -409,6 +409,7 @@ def step_target_fps_parallelization(model: ModelWrapper, cfg: DataflowBuildConfi hw_attrs = [ "PE", "SIMD", + "parallel_window", "ram_style", "resType", "mem_mode", diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py index 1ae4022b79..eae9ffd6bd 100755 --- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py +++ b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py @@ -81,7 +81,7 @@ def get_nodeattr_types(self): "outputDataType": ("s", True, ""), "depthwise": ("i", False, 0, {0, 1}), # Enable reprogrammable implementation to change FM dimensions, - # stride, or dilation during runtime + # stride, or dilation during runtime (requires parallel_window = 0) "dynamic_mode": ("i", False, 0, {0, 1}), # FPGA resource type for ConvolutionInputGenerator input buffer # auto -- let Vivado decide @@ -233,13 +233,13 @@ def get_buffer_depth(self): mmv_out = 1 channel_factor = int(ifm_ch / simd) + # compute minimal buffer length (assuming it holds 1 complete window) + buffer_min_size = ( + (k_h - 1) * dilation_h * w + (k_w - 1) * dilation_w + 1 + ) * channel_factor + impl_style = self.select_impl_style() if impl_style == "default": - # compute minimal buffer length (assuming it holds 1 complete window) - buffer_min_size = ( - (k_h - 1) * dilation_h * w + (k_w - 1) * dilation_w + 1 - ) * channel_factor - # add additional buffer space in case of stride > 1 # this minimizes cycle count as it allows an earlier pre-load of inputs buffer_depth = ( @@ -255,73 +255,89 @@ def get_buffer_depth(self): * channel_factor, ) ) - else: - buffer_depth = 0 - raise Exception("Requested impl. style not implemented") + elif impl_style == "parallel": + buffer_depth = buffer_min_size + 1 return buffer_depth def get_exp_cycles(self): - simd = self.get_nodeattr("SIMD") - ifm_ch = self.get_nodeattr("IFMChannels") - k = self.get_nodeattr("ConvKernelDim") - ifm_dim = self.get_nodeattr("IFMDim") - ofm_dim = self.get_nodeattr("OFMDim") - stride = self.get_nodeattr("Stride") - dilation = self.get_nodeattr("Dilation") - depthwise = self.get_nodeattr("depthwise") - ifm_dim_h, ifm_dim_w = ifm_dim - ofm_dim_h, ofm_dim_w = ofm_dim - k_h, k_w = k - stride_h, stride_w = stride - dilation_h, dilation_w = dilation - - channel_factor = int(ifm_ch / simd) + impl_style = self.select_impl_style() - if ifm_dim_h == 1 or ifm_dim_w == 1: - # 1D case - ( - ifm_ch, - [ifm_dim_h, ifm_dim_w], - [ofm_dim_h, ofm_dim_w], - [k_h, k_w], - [stride_h, stride_w], - [dilation_h, dilation_w], - ) = self.get_1d_conv_attrs_normalized() - - if depthwise: - exp_cycles = ( - +ofm_dim_w * k_w * channel_factor - + channel_factor * (k_w - 1) * (stride_w - 1) - - (k_w - 1) - + 2 - ) + if impl_style == "parallel": + exp_cycles = self.get_number_input_values() + 2 + elif impl_style == "default": + simd = self.get_nodeattr("SIMD") + ifm_ch = self.get_nodeattr("IFMChannels") + k = self.get_nodeattr("ConvKernelDim") + ifm_dim = self.get_nodeattr("IFMDim") + ofm_dim = self.get_nodeattr("OFMDim") + stride = self.get_nodeattr("Stride") + dilation = self.get_nodeattr("Dilation") + depthwise = self.get_nodeattr("depthwise") + ifm_dim_h, ifm_dim_w = ifm_dim + ofm_dim_h, ofm_dim_w = ofm_dim + k_h, k_w = k + stride_h, stride_w = stride + dilation_h, dilation_w = dilation + + channel_factor = int(ifm_ch / simd) + if ifm_dim_h == 1 or ifm_dim_w == 1: + # 1D case + ( + ifm_ch, + [ifm_dim_h, ifm_dim_w], + [ofm_dim_h, ofm_dim_w], + [k_h, k_w], + [stride_h, stride_w], + [dilation_h, dilation_w], + ) = self.get_1d_conv_attrs_normalized() + + if depthwise: + exp_cycles = ( + +ofm_dim_w * k_w * channel_factor + + channel_factor * (k_w - 1) * (stride_w - 1) + - (k_w - 1) + + 2 + ) + else: + exp_cycles = ofm_dim_w * k_w * channel_factor + 2 else: - exp_cycles = ofm_dim_w * k_w * channel_factor + 2 - else: - # 2D case - buffer_min_size = ( - (k_h - 1) * dilation_h * ifm_dim_w + (k_w - 1) * dilation_w + 1 - ) * channel_factor - cycles_write_block = ofm_dim_w * k_w * k_h * channel_factor - cycles_read_block = stride_w * ifm_dim_w * channel_factor - max_cycles = max(cycles_write_block, cycles_read_block) - if depthwise: - max_cycles += ofm_dim_w * (stride_w - 1) * (channel_factor - 1) - exp_cycles = buffer_min_size + ofm_dim_h * max_cycles # initial buffering - if depthwise: - exp_cycles += (stride_h - 1) * ifm_dim_w * channel_factor + # 2D case + buffer_min_size = ( + (k_h - 1) * dilation_h * ifm_dim_w + (k_w - 1) * dilation_w + 1 + ) * channel_factor + cycles_write_block = ofm_dim_w * k_w * k_h * channel_factor + cycles_read_block = stride_w * ifm_dim_w * channel_factor + max_cycles = max(cycles_write_block, cycles_read_block) + if depthwise: + max_cycles += ofm_dim_w * (stride_w - 1) * (channel_factor - 1) + exp_cycles = buffer_min_size + ofm_dim_h * max_cycles + if depthwise: + exp_cycles += (stride_h - 1) * ifm_dim_w * channel_factor return int(exp_cycles) def bram_estimation(self): simd = self.get_nodeattr("SIMD") ram_style = self.get_nodeattr("ram_style") + impl_style = self.select_impl_style() + [k_h, k_w] = self.get_nodeattr("ConvKernelDim") + [ifm_dim_h, ifm_dim_w] = self.get_nodeattr("IFMDim") + [dilation_h, dilation_w] = self.get_nodeattr("Dilation") - # NOTE: Actual BRAM usage might be lower in some cases. - # This does not account for the exact Vivado behavior yet. - buffer_width = simd * self.get_input_datatype().bitwidth() - buffer_depth = self.get_buffer_depth() if ram_style == "block" or ram_style == "auto": + buffer_width = simd * self.get_input_datatype().bitwidth() + if impl_style == "default": + buffer_depth = self.get_buffer_depth() + buffer_count = 1 + elif impl_style == "parallel": + if ifm_dim_h == 1 or ifm_dim_w == 1: + return 0 # 1D case (no line buffers needed) + kernel_width = (k_w - 1) * dilation_w + 1 + buffer_depth = (ifm_dim_w - kernel_width) + ifm_dim_w * (dilation_h - 1) + buffer_count = k_h - 1 + + # NOTE: Actual BRAM usage might be lower in some cases + # due to imperfect modeling of Vivado behavior if buffer_depth <= 512: ram_width = 36 elif buffer_depth <= 1024: @@ -356,7 +372,9 @@ def bram_estimation(self): remainder_cascade_width = math.ceil(buffer_width / remainder_width) cascade_savings = ram_cascade_width - remainder_cascade_width - return int(ram_cascade_depth * ram_cascade_width - cascade_savings) + return int( + (ram_cascade_depth * ram_cascade_width - cascade_savings) * buffer_count + ) else: return 0 @@ -374,15 +392,28 @@ def lut_estimation(self): def uram_estimation(self): simd = self.get_nodeattr("SIMD") ram_style = self.get_nodeattr("ram_style") - buffer_width = simd * self.get_input_datatype().bitwidth() - buffer_depth = self.get_buffer_depth() + impl_style = self.select_impl_style() + [k_h, k_w] = self.get_nodeattr("ConvKernelDim") + [ifm_dim_h, ifm_dim_w] = self.get_nodeattr("IFMDim") + [dilation_h, dilation_w] = self.get_nodeattr("Dilation") if ram_style == "ultra": + buffer_width = simd * self.get_input_datatype().bitwidth() + if impl_style == "default": + buffer_depth = self.get_buffer_depth() + buffer_count = 1 + elif impl_style == "parallel": + if ifm_dim_h == 1 or ifm_dim_w == 1: + return 0 # 1D case (no line buffers needed) + kernel_width = (k_w - 1) * dilation_w + 1 + buffer_depth = (ifm_dim_w - kernel_width) + ifm_dim_w * (dilation_h - 1) + buffer_count = k_h - 1 + ram_depth = 4096 ram_width = 72 ram_cascade_depth = math.ceil(buffer_depth / ram_depth) ram_cascade_width = math.ceil(buffer_width / ram_width) - return int(ram_cascade_depth * ram_cascade_width) + return int(ram_cascade_depth * ram_cascade_width * buffer_count) else: return 0 @@ -641,8 +672,7 @@ def prepare_codegen_default(self): def prepare_codegen_parallel(self): # Parallel implementation style for MMV_out = K: - # mix of shift-registers (for parallel read) and line buffers (BRAM or LUTRAM) - # compute a static schedule by analyzing access pattern (from im2col function) + # mix of shift-registers (for parallel read) and line buffers (BRAM/URAM/LUT) template_path = ( os.environ["FINN_ROOT"] + "/finn-rtllib/swg/swg_template_parallel.sv" ) @@ -674,8 +704,7 @@ def prepare_codegen_parallel(self): (k_h - 1) * dilation_h * w + (k_w - 1) * dilation_w + 1 ) * channel_factor - # buffer_actual_size = self.get_buffer_depth() # TODO: Move to this method - buffer_actual_size = buffer_min_size + 1 + buffer_actual_size = self.get_buffer_depth() code_gen_dict["$BUF_ELEM_TOTAL$"] = [str(buffer_actual_size)] # compute some intermediate values, e.g., kernel "width" = k_w incl. dilation @@ -685,34 +714,19 @@ def prepare_codegen_parallel(self): skip_columns = w % (kernel_width + (out_dim_w - 1) * stride_w) skip_rows = h % (kernel_height + (out_dim_h - 1) * stride_h) - # compute address increment values for 5-loop nest #TODO: simplify - addr_incr_end_simd = 1 - addr_incr_end_window_elem = (dilation_w - 1) * channel_factor + 1 - addr_incr_end_window_row = ( - ((w - kernel_width) * channel_factor) # remaining line - + ((dilation_h - 1) * w * channel_factor) # skip lines - + 1 # wrap-around of minimally sized buffer - ) - addr_incr_end_window = -buffer_min_size + stride_w * channel_factor + 1 - addr_incr_end_row = ( - -buffer_min_size - + ((skip_columns + kernel_width) * channel_factor) # remaining line - + ((stride_h - 1) * w * channel_factor) # skip lines - + 1 - ) - # set certain threshold indices to detect when reading/writing finishes code_gen_dict["$LAST_READ_ELEM$"] = [str(h * w * channel_factor - 1)] code_gen_dict["$LAST_WRITE_ELEM$"] = [ str(((h - skip_rows - 1) * w + (w - skip_columns)) * channel_factor - 1) ] - # default controller loop structure: # iterations (counters) map directly + # re-use default controller loop structure + code_gen_dict["$IS_DEPTHWISE$"] = ["0"] loop_h_iterations = out_dim_h - loop_w_iterations = out_dim_w # -> innermost loop - loop_kh_iterations = 1 # k_h - loop_kw_iterations = 1 # k_w - loop_simd_iterations = 1 # channel_factor + loop_w_iterations = out_dim_w # now the innermost loop + loop_kh_iterations = 1 + loop_kw_iterations = 1 + loop_simd_iterations = 1 if loop_w_iterations == 1: code_gen_dict["$INNERMOST_STATE$"] = ["STATE_LOOP_H"] @@ -721,12 +735,19 @@ def prepare_codegen_parallel(self): code_gen_dict["$INNERMOST_STATE$"] = ["STATE_LOOP_W"] loop_w_iterations -= 1 # -1 because state is initial state + # set head and tail address increment values + addr_incr_end_window = -buffer_min_size + stride_w * channel_factor + 1 + addr_incr_end_row = ( + -buffer_min_size + + ((skip_columns + kernel_width) * channel_factor) # remaining line + + ((stride_h - 1) * w * channel_factor) # skip lines + + 1 + ) + tail_incr_w = addr_incr_end_window + buffer_min_size - 1 tail_incr_h = addr_incr_end_row + buffer_min_size - 1 tail_incr_last_window = buffer_min_size - 1 - code_gen_dict["$IS_DEPTHWISE$"] = ["0"] - # overwrite new loop bounds: addr_incr_end_simd = 1 addr_incr_end_window_elem = 1 addr_incr_end_window_row = 1 @@ -970,6 +991,8 @@ def generate_hdl(self): template_path, code_gen_dict = self.prepare_codegen_default() elif impl_style == "parallel": template_path, code_gen_dict = self.prepare_codegen_parallel() + if self.get_nodeattr("dynamic_mode"): + raise Exception("Dynamic mode is not compatible with parallel_window") else: raise Exception("Requested impl. style not implemented") @@ -1109,6 +1132,8 @@ def get_dynamic_config(self, ifm_dim=None, stride=None, dilation=None): apply (e.g. component must be synthesized for largest buffer size).""" # NOTE: For better driver integration, this functionality could be packaged # as a standalone function in the future + if self.select_impl_style() != "default": + raise Exception("Impl. style is incompatible with dynamic mode") if ifm_dim is None: ifm_dim = self.get_nodeattr("IFMDim") diff --git a/src/finn/transformation/fpgadataflow/set_folding.py b/src/finn/transformation/fpgadataflow/set_folding.py index e24e24f1f8..48e5d9f9e1 100644 --- a/src/finn/transformation/fpgadataflow/set_folding.py +++ b/src/finn/transformation/fpgadataflow/set_folding.py @@ -73,6 +73,9 @@ class SetFolding(Transformation): * the producer of the node is expected to be a ConvolutionInputGenerator with depthwise=1, whose SIMD value will be set equal to the PE value of its consumer node + * the VVAU also supports SIMD ("input window") parallelism next to + PE ("channels"), but current ConvInpGen limitations require PE to be fully + unfolded before SIMD is increased """ def __init__( @@ -103,7 +106,9 @@ def apply(self, model): "Thresholding_Batch", ] # these ops use SIMD parallelism, up to a max value of NumChannels - # ConvolutionInputGenerator has a special case when depthwise=1 + # ConvolutionInputGenerator* has a special case when depthwise=1 + # ConvolutionInputGenerator_rtl supports additional parallelism by + # setting parallel_window=1 mode after maxing out SIMD simd_ops = [ "DownSampler", "FMPadding_Batch", @@ -151,15 +156,36 @@ def apply(self, model): max_pe = node_inst.get_nodeattr("Labels") self.optimize_attribute_val(node_inst, max_pe, "PE") elif op_type in depthwise_op_exceptions: + # init/reset SIMD of VVAU + if op_type == "VectorVectorActivation": + node_inst.set_nodeattr("SIMD", 1) max_pe = node_inst.get_nodeattr("Channels") self.optimize_attribute_val(node_inst, max_pe, "PE") + # increase SIMD for VVAU once PE is exhausted + pe = node_inst.get_nodeattr("PE") + cyc = node_inst.get_exp_cycles() + if ( + op_type == "VectorVectorActivation" + and pe == max_pe + and cyc > self.target_cycles_per_frame + ): + max_simd = np.prod(node_inst.get_nodeattr("Kernel")) + self.optimize_attribute_val(node_inst, max_simd, "SIMD") # also set the folding of the upsteam DW SWU # which must be identical to this node swu_node = model.find_producer(node.input[0]) if swu_node.op_type.startswith("ConvolutionInputGenerator"): swu_node_inst = getCustomOp(swu_node) - pe = node_inst.get_nodeattr("PE") swu_node_inst.set_nodeattr("SIMD", pe) + # enable parallel_window mode of RTL SWG if needed + if swu_node.op_type == "ConvolutionInputGenerator_rtl": + if ( + op_type == "VectorVectorActivation" + and node_inst.get_nodeattr("SIMD") > 1 + ): + swu_node_inst.set_nodeattr("parallel_window", 1) + else: + swu_node_inst.set_nodeattr("parallel_window", 0) else: if op_type == "VectorVectorActivation": ksize = np.prod(node_inst.get_nodeattr("Kernel")) @@ -176,7 +202,19 @@ def apply(self, model): depthwise = node_inst.get_nodeattr("depthwise") if depthwise == 0: max_simd = node_inst.get_nodeattr("IFMChannels") + # init/reset parallel_window mode of RTL SWG + if op_type == "ConvolutionInputGenerator_rtl": + node_inst.set_nodeattr("parallel_window", 0) self.optimize_attribute_val(node_inst, max_simd, "SIMD") + # enable parallel_window mode of RTL SWG if needed + simd = node_inst.get_nodeattr("SIMD") + cyc = node_inst.get_exp_cycles() + if ( + op_type == "ConvolutionInputGenerator_rtl" + and simd == max_simd + and cyc > self.target_cycles_per_frame + ): + node_inst.set_nodeattr("parallel_window", 1) else: # depthwise SWGs are handled separately continue diff --git a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py index 007360a5fd..a66038ef29 100755 --- a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py +++ b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py @@ -140,9 +140,9 @@ def prepare_inputs(input_tensor): # input datatype @pytest.mark.parametrize("idt", [DataType["UINT4"]]) # kernel size -@pytest.mark.parametrize("k", [[2, 2], [3, 3], [1, 3]]) +@pytest.mark.parametrize("k", [[3, 3], [1, 5]]) # input dimension -@pytest.mark.parametrize("ifm_dim", [[24, 24], [15, 6], [13, 13], [1, 14]]) +@pytest.mark.parametrize("ifm_dim", [[13, 13], [1, 21]]) # input channels @pytest.mark.parametrize("ifm_ch", [6]) # Stride @@ -152,9 +152,9 @@ def prepare_inputs(input_tensor): # depthwise @pytest.mark.parametrize("dw", [0, 1]) # input channel parallelism ("SIMD") -@pytest.mark.parametrize("simd", [1, 2, 3, 6]) +@pytest.mark.parametrize("simd", [1, 3, 6]) # parallel_window enable (MMV_out = M*K) -@pytest.mark.parametrize("parallel_window", [0]) +@pytest.mark.parametrize("parallel_window", [0, 1]) # in/out MMV ("M") @pytest.mark.parametrize("m", [1]) # Flip dimensions From ac1cb729fab0aaef398fd5a02f4549976bb414f6 Mon Sep 17 00:00:00 2001 From: Felix Jentzsch Date: Sun, 29 Jan 2023 17:00:04 +0100 Subject: [PATCH 024/665] [SWG] Add documentation --- docs/finn/img/rtl_swg_impl_styles.png | Bin 0 -> 103635 bytes docs/finn/internals.rst | 77 ++++++++++++++++++ .../convolutioninputgenerator_rtl.py | 34 ++++++-- .../fpgadataflow/convert_to_hls_layers.py | 14 +--- 4 files changed, 104 insertions(+), 21 deletions(-) create mode 100644 docs/finn/img/rtl_swg_impl_styles.png diff --git a/docs/finn/img/rtl_swg_impl_styles.png b/docs/finn/img/rtl_swg_impl_styles.png new file mode 100644 index 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b/docs/finn/internals.rst @@ -205,3 +205,80 @@ Disadvantages: How to set *mem_mode* --------------------- When the nodes in the network are converted to HLS layers, the *mem_mode* can be passed. More detailed information about the transformations that prepare the network and the transformation that performs the conversion to HLS layers can be found in chapter :ref:`nw_prep`. The *mem_mode* is passed as argument. Note that if no argument is passed, the default is *const*. + +RTL ConvolutionInputGenerator +============================= + +FINN implements convolution operations by pairing a ConvolutionInputGenerator (or "sliding window generator (SWG)") with an MVAU or VVAU (for depthwise convolution). +This RTL version is an alternative to the original `HLS implementation `_ and aims to improve on it in the following ways: + +* Support a wider range of hyperparameters without the fragmentation into 16+ separate HLS functions +* Support additional degrees of parallelism (i.e., across the output window or multiple input samples) that are difficult to implement in HLS +* Support additional features, such as dynamic feature map sizing +* Improve resource efficiency + +The component is implemented by generating (System-)Verilog code for each individual instance, realized via the template + replacement dictionary mechanism found in other FINN components. +Despite the HDL implementation, the component is managed by its own HLSCustomOp (!) named "ConvolutionInputGenerator_rtl". Naturally, HLS simulation & synthesis are not supported. + +The RTL SWG is currently disabled by default and can be enabled either in the corresponding HLS conversion transformation (:py:mod:`convert_to_hls_layers.InferConvInpGen(use_rtl_variant = True)`) or in the build configuration (:py:mod:`DataflowBuildConfig.force_rtl_conv_inp_gen = True`). + +Implementation styles +--------------------- +Depending on the amount of parallelism requested, one of two implementation styles is selected. The following table defines folding parameters (marked in bold text) and supported configurations. + +.. list-table:: Parallelism configurations + + * - **SIMD** + - **parallel_window** + - **M** + - MMV_in + - MMV_out + - Style + - Notes + * - < C + - 0 + - 1 + - 1 + - 1 + - default + - depthwise-aware + * - C + - 0 + - 1 + - 1 + - 1 + - default + - depthwise-agnostic + * - C + - 1 + - 1 + - 1 + - K + - parallel + - depthwise-agnostic + * - C + - 1 + - M + - M + - M*K + - parallel + - Currently unsupported + +(With C = #Channels, MMV_in = input samples (or "pixels") per cycle, MMV_out = output samples (or "pixels") per cycle, K = kernel_width * kernel_height.) + +The following diagram shows the operating principle of both styles, the "parallel" variant is pictured for a 2x2 kernel without dilation. + +.. image:: img/rtl_swg_impl_styles.png + :align: center + +The main difference lies in the buffer structure. If the output width is equal to the input width ("default mode"), an addressable circular buffer is used, which can be implemented either in LUTRAM, BRAM, or URAM resources. If parallel access to multiple window elements is required ("parallel mode"), the SWG generates a fixed structure of registers and line buffers to avoid memory port limitations and exploding multiplexing logic, while still featuring LUT-saving BRAM/URAM implementation for the line buffers. + +The "default" style also supports a dynamic mode, which provides an interface to change feature map dimensions, stride, or dilation at run-time. See `this pull request `_ description for more information. + +Folding +------- +The RTL SWG is supported by the basic automatic folding algorithm in FINN (:py:mod:`SetFolding()`). Consider the following implications: + +**MVAU:** Although it is recommended to unfold SIMD first, SIMD and PE can be set independently. Full (and balanced) parallelism is achieved by using the SWG in parallel window mode and setting MVAU SIMD and PE to their maximum values (SIMD = MW = C_in * K, PE = MH = C_out). + +**VVAU:** While the VVAU HLS component supports SIMD unfolding independently from PE, the RTL SWG requires full unfolding across the channel dimension (SIMD of the SWG = PE of the VVAU) before enabling window-parallelism. Unlike the MVAU, the VVAU can't accept datawidth-converted input from a fully-parallel SWG in this case due to the depthwise data layout. As a result, the VVAU should be unfolded by PE first (up to PE = C), followed by SIMD (up to SIMD = K). diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py index eae9ffd6bd..10eb604a6b 100755 --- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py +++ b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py @@ -188,6 +188,7 @@ def get_outstream_width(self, ind=0): return self.get_instream_width() def get_number_input_values(self): + """Function to get the number of expected input values.""" folded_ishape = self.get_folded_input_shape() num_input_elems = np.prod(folded_ishape[:-1]) return num_input_elems @@ -198,6 +199,7 @@ def get_number_output_values(self): return num_output_elems def get_1d_conv_attrs_normalized(self): + """Returns normalized spatial attributes, where H=1 for the 1D case.""" # normalize FM dimensions so that: # [H, W] = [Y, X] = [1, D] or [D, 1] are always mapped to [1, D]. # The dummy ('1') dimension is the Y-dimension. @@ -218,6 +220,8 @@ def get_1d_conv_attrs_normalized(self): return (ifm_ch, ifm_dim, ofm_dim, k, stride, dilation) def get_buffer_depth(self): + """Returns total depth of the internal buffer, depending on + implementation style.""" ifm_ch = self.get_nodeattr("IFMChannels") k = self.get_nodeattr("ConvKernelDim") ifm_dim = self.get_nodeattr("IFMDim") @@ -488,8 +492,8 @@ def execute_node(self, context, graph): shape doesn't match expected shape (1, ofm_dim_h, ofm_dim_w, k_h*k_w*ifm_ch).""" def prepare_codegen_default(self): - # Default implementation style for MMV_out = 1: addressable cyclic buffer - # Computing incremental addressing scheme directly.. + """Fills code generation dict for the default implementation style by computing + the incremental addressing scheme for the circular buffer.""" if self.get_nodeattr("dynamic_mode"): template_select = "/finn-rtllib/swg/swg_template_default_dynamic.sv" else: @@ -671,8 +675,10 @@ def prepare_codegen_default(self): return template_path, code_gen_dict def prepare_codegen_parallel(self): - # Parallel implementation style for MMV_out = K: - # mix of shift-registers (for parallel read) and line buffers (BRAM/URAM/LUT) + """Fills code generation dict for the parallel implementation style by computing + the loop controller configuration and partitioning the fixed buffer into + shift-registers (for parallel read access) and line buffers (for efficient + LUTRAM/BRAM/URAM implementation).""" template_path = ( os.environ["FINN_ROOT"] + "/finn-rtllib/swg/swg_template_parallel.sv" ) @@ -936,6 +942,7 @@ def prepare_codegen_parallel(self): return template_path, code_gen_dict def select_impl_style(self): + """Selects implementation style based on folding configuration.""" simd = self.get_nodeattr("SIMD") M = self.get_nodeattr("M") ifm_ch = self.get_nodeattr("IFMChannels") @@ -984,6 +991,8 @@ def select_impl_style(self): return impl_style def generate_hdl(self): + """Generates HDL code and wrapper for the IP, depending on required + implementation style.""" impl_style = self.select_impl_style() # prepare code generation by filling out dictionaries @@ -1186,44 +1195,53 @@ def get_dynamic_config(self, ifm_dim=None, stride=None, dilation=None): return config def code_generation_ipgen(self, model, fpgapart, clk): - """Normally: Generates C++ code and tcl script for IP generation. - Here: Generates (System-)Verilog code for IP generation.""" + """Generates (System-)Verilog code for IP generation (instead of HLS code).""" self.generate_hdl() def ipgen_singlenode_code(self): - """Normally: Builds the bash script for IP generation.""" + """Not implemented (RTL component).""" pass def code_generation_cppsim(self, model): - """Normally: Generates C++ code for simulation (cppsim).""" + """Not implemented (RTL component).""" pass def compile_singlenode_code(self): + """Not implemented (RTL component).""" pass def global_includes(self): + """Not implemented (RTL component).""" pass def defines(self, var): + """Not implemented (RTL component).""" pass def read_npy_data(self): + """Not implemented (RTL component).""" pass def strm_decl(self): + """Not implemented (RTL component).""" pass def docompute(self): + """Not implemented (RTL component).""" pass def dataoutstrm(self): + """Not implemented (RTL component).""" pass def save_as_npy(self): + """Not implemented (RTL component).""" pass def blackboxfunction(self): + """Not implemented (RTL component).""" pass def pragmas(self): + """Not implemented (RTL component).""" pass diff --git a/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py b/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py index 525af7ea92..d1f6eb4608 100644 --- a/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py +++ b/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py @@ -140,19 +140,7 @@ def apply(self, model): k_h > 1 and k_w == 1 and ifm_dim_w == 1 ) - # Ensure that RTL variant is not inserted for unsupported configuration - is_rtl_variant_compatible = True - if is_kernel_pointwise: - is_rtl_variant_compatible = False - if self.use_rtl_variant: - warnings.warn( - """%s : RTL ConvInpGen requested for unsupported - configuration. Falling back to HLS implementation.""" - % n.name - ) - - if self.use_rtl_variant and is_rtl_variant_compatible: - + if self.use_rtl_variant: ConvInpGen_node = helper.make_node( "ConvolutionInputGenerator_rtl", [ConvInpGen_input], From d19255d81892dea491b990e17aa5237bd1b82087 Mon Sep 17 00:00:00 2001 From: Yaman Umuroglu Date: Wed, 1 Feb 2023 11:32:17 +0100 Subject: [PATCH 025/665] [Build] calculate stable_throughput metric as part of step_measure_rtlsim_performance --- src/finn/builder/build_dataflow_steps.py | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/src/finn/builder/build_dataflow_steps.py b/src/finn/builder/build_dataflow_steps.py index b0f7b6ec6c..fb4d60c1eb 100644 --- a/src/finn/builder/build_dataflow_steps.py +++ b/src/finn/builder/build_dataflow_steps.py @@ -667,7 +667,6 @@ def step_measure_rtlsim_performance(model: ModelWrapper, cfg: DataflowBuildConfi ) rtlsim_bs = int(cfg.rtlsim_batch_size) if force_python_rtlsim: - # run with single input to get latency orig_rtlsim_trace_depth = get_rtlsim_trace_depth() assert rtlsim_bs > 0, "rtlsim batch size must be >0" if cfg.verify_save_rtlsim_waveforms: @@ -680,9 +679,11 @@ def step_measure_rtlsim_performance(model: ModelWrapper, cfg: DataflowBuildConfi rtlsim_model.set_metadata_prop( "extra_verilator_args", str(["-CFLAGS", "-O3"]) ) + # run with single input to get latency + rtlsim_latency_dict = throughput_test_rtlsim(rtlsim_model, 1) + # run with batch to get stable-state throughput rtlsim_perf_dict = throughput_test_rtlsim(rtlsim_model, rtlsim_bs) - rtlsim_latency = rtlsim_perf_dict["cycles"] - rtlsim_perf_dict["latency_cycles"] = rtlsim_latency + rtlsim_perf_dict["latency_cycles"] = rtlsim_latency_dict["cycles"] else: rtlsim_perf_dict = verilator_fifosim(model, rtlsim_bs) # keep keys consistent between the Python and C++-styles @@ -696,6 +697,19 @@ def step_measure_rtlsim_performance(model: ModelWrapper, cfg: DataflowBuildConfi for (key, val) in rtlsim_perf_dict.items(): if "max_count" in key: del rtlsim_perf_dict[key] + # estimate stable-state throughput based on latency+throughput + if rtlsim_bs == 1: + rtlsim_perf_dict["stable_throughput[images/s]"] = rtlsim_perf_dict[ + "throughput[images/s]" + ] + else: + total_cycles = rtlsim_perf_dict["cycles"] + latency_cycles = rtlsim_perf_dict["latency_cycles"] + stablestate_cycles = total_cycles - latency_cycles + clk_ns = float(model.get_metadata_prop("clk_ns")) + fclk_mhz = 1 / (clk_ns * 0.001) + runtime_s = (stablestate_cycles * clk_ns) * (10**-9) + rtlsim_perf_dict["stable_throughput[images/s]"] = rtlsim_bs / runtime_s with open(report_dir + "/rtlsim_performance.json", "w") as f: json.dump(rtlsim_perf_dict, f, indent=2) From a1519ef889d2c7df6b25567d9a647a2ae7f426f7 Mon Sep 17 00:00:00 2001 From: Yaman Umuroglu Date: Wed, 1 Feb 2023 11:32:48 +0100 Subject: [PATCH 026/665] [Test] add cnv testcase as part for FIFO sizing test --- tests/fpgadataflow/test_fifosizing.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/fpgadataflow/test_fifosizing.py b/tests/fpgadataflow/test_fifosizing.py index f4f2b8dbff..9399fbe394 100644 --- a/tests/fpgadataflow/test_fifosizing.py +++ b/tests/fpgadataflow/test_fifosizing.py @@ -55,7 +55,7 @@ def fetch_test_model(topology, wbits=2, abits=2): @pytest.mark.parametrize( "method", ["largefifo_rtlsim_python", "largefifo_rtlsim_cpp", "characterize"] ) -@pytest.mark.parametrize("topology", ["tfc"]) +@pytest.mark.parametrize("topology", ["tfc", "cnv"]) def test_fifosizing_linear(method, topology): force_python_rtlsim = "python" in method method_key = "largefifo_rtlsim" if "largefifo_rtlsim" in method else "characterize" @@ -68,7 +68,7 @@ def test_fifosizing_linear(method, topology): force_python_rtlsim=force_python_rtlsim, synth_clk_period_ns=10.0, board="Pynq-Z1", - rtlsim_batch_size=100, + rtlsim_batch_size=100 if topology == "tfc" else 2, shell_flow_type=build_cfg.ShellFlowType.VIVADO_ZYNQ, generate_outputs=[ build_cfg.DataflowOutputType.ESTIMATE_REPORTS, @@ -83,7 +83,7 @@ def test_fifosizing_linear(method, topology): with open(tmp_output_dir + "/report/rtlsim_performance.json") as f: sim_data = json.load(f) assert ( - float(sim_data["throughput[images/s]"]) + float(sim_data["stable_throughput[images/s]"]) / float(est_data["estimated_throughput_fps"]) > 0.9 ) From 423c32aaf42bd1bc050675ff5e7096892cd30ab1 Mon Sep 17 00:00:00 2001 From: Yaman Umuroglu Date: Wed, 1 Feb 2023 15:41:54 +0100 Subject: [PATCH 027/665] [DWC] always use hls mode during insertion for better compat --- src/finn/transformation/fpgadataflow/insert_dwc.py | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/insert_dwc.py b/src/finn/transformation/fpgadataflow/insert_dwc.py index 632d1f813b..cff8b60267 100644 --- a/src/finn/transformation/fpgadataflow/insert_dwc.py +++ b/src/finn/transformation/fpgadataflow/insert_dwc.py @@ -81,15 +81,11 @@ def apply(self, model): dwc_in_width = n0.get_outstream_width() # determine dwc outwidth dwc_out_width = n1.get_instream_width() - larger_width = max(dwc_in_width, dwc_out_width) - smaller_width = min(dwc_in_width, dwc_out_width) - both_8bit_aligned = (larger_width % 8 == 0) and ( - smaller_width % 8 == 0 - ) - if both_8bit_aligned: - impl_style = "vivado" - else: - impl_style = "hls" + # use hls mode by default since it supports more configs + # vivado mode can be manually enabled by user, but does not + # support e.g. node-by-node rtlsim neded for + # characterization-based FIFO sizing + impl_style = "hls" # determine shape for dwc dwc_shape = n0.get_normal_output_shape() From 8a2a9b558f8c4a0705c0ce300bf69b605861d7ae Mon Sep 17 00:00:00 2001 From: Felix Jentzsch Date: Fri, 3 Feb 2023 18:44:01 +0100 Subject: [PATCH 028/665] Fix top module setting in CreateStitchedIP --- src/finn/transformation/fpgadataflow/create_stitched_ip.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/finn/transformation/fpgadataflow/create_stitched_ip.py b/src/finn/transformation/fpgadataflow/create_stitched_ip.py index 8e2c69bad4..d1cb3c4af9 100644 --- a/src/finn/transformation/fpgadataflow/create_stitched_ip.py +++ b/src/finn/transformation/fpgadataflow/create_stitched_ip.py @@ -412,7 +412,7 @@ def apply(self, model): wrapper_filename = "%s/hdl/%s_wrapper.v" % (bd_base, block_name) tcl.append("add_files -norecurse %s" % wrapper_filename) model.set_metadata_prop("wrapper_filename", wrapper_filename) - tcl.append("set_property top finn_design_wrapper [current_fileset]") + tcl.append("set_property top %s_wrapper [current_fileset]" % block_name) # synthesize to DCP and export stub, DCP and constraints if self.vitis: tcl.append( From f752ba21e0badeb81372dc74c8ee52eb581ca1fb Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 13 Feb 2023 15:19:11 +0000 Subject: [PATCH 029/665] [Deps] Update finn-experimental version --- fetch-repos.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fetch-repos.sh b/fetch-repos.sh index 5b060f5bc8..dd62cad9eb 100755 --- a/fetch-repos.sh +++ b/fetch-repos.sh @@ -28,7 +28,7 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. QONNX_COMMIT="dd35a8ff49d7225a07ffceeebe25a6361df48349" -FINN_EXP_COMMIT="9cbd2787b5160e2b44e0e8164a0df1457dbd5366" +FINN_EXP_COMMIT="72fac31ab732130cba5cf05555544ee5a5ecb773" BREVITAS_COMMIT="a5b71d6de1389d3e7db898fef72e014842670f03" PYVERILATOR_COMMIT="766e457465f5c0dd315490d7b9cc5d74f9a76f4f" CNPY_COMMIT="4e8810b1a8637695171ed346ce68f6984e585ef4" From a66a2405c013a748f03b970974e87056d774a966 Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 13 Feb 2023 15:25:39 +0000 Subject: [PATCH 030/665] [Deps] Update finn experimental version --- fetch-repos.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fetch-repos.sh b/fetch-repos.sh index dd62cad9eb..4f3b821f76 100755 --- a/fetch-repos.sh +++ b/fetch-repos.sh @@ -28,7 +28,7 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. QONNX_COMMIT="dd35a8ff49d7225a07ffceeebe25a6361df48349" -FINN_EXP_COMMIT="72fac31ab732130cba5cf05555544ee5a5ecb773" +FINN_EXP_COMMIT="53049bf5025dbc0a11dc19355325b1a02c3947c0" BREVITAS_COMMIT="a5b71d6de1389d3e7db898fef72e014842670f03" PYVERILATOR_COMMIT="766e457465f5c0dd315490d7b9cc5d74f9a76f4f" CNPY_COMMIT="4e8810b1a8637695171ed346ce68f6984e585ef4" From 54e612fcf6ea7e1dcd621531a4bb3b6e1aa42098 Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 13 Feb 2023 15:53:43 +0000 Subject: [PATCH 031/665] [Deps] Update finn-experimental version (domain name update) --- fetch-repos.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fetch-repos.sh b/fetch-repos.sh index 4f3b821f76..89a18896af 100755 --- a/fetch-repos.sh +++ b/fetch-repos.sh @@ -28,7 +28,7 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. QONNX_COMMIT="dd35a8ff49d7225a07ffceeebe25a6361df48349" -FINN_EXP_COMMIT="53049bf5025dbc0a11dc19355325b1a02c3947c0" +FINN_EXP_COMMIT="448bd6f5ee1dbf9e2f9cda014e2f875bc6d49ae0" BREVITAS_COMMIT="a5b71d6de1389d3e7db898fef72e014842670f03" PYVERILATOR_COMMIT="766e457465f5c0dd315490d7b9cc5d74f9a76f4f" CNPY_COMMIT="4e8810b1a8637695171ed346ce68f6984e585ef4" From b703e74b0dd0339e850c0229ac5781bb9b882e3c Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 13 Feb 2023 18:47:22 +0000 Subject: [PATCH 032/665] Update finn-experimental commit --- fetch-repos.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fetch-repos.sh b/fetch-repos.sh index 89a18896af..e6aa50940c 100755 --- a/fetch-repos.sh +++ b/fetch-repos.sh @@ -28,7 +28,7 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. QONNX_COMMIT="dd35a8ff49d7225a07ffceeebe25a6361df48349" -FINN_EXP_COMMIT="448bd6f5ee1dbf9e2f9cda014e2f875bc6d49ae0" +FINN_EXP_COMMIT="8e6cccda16a5adeaac8451f9236e2a24766e0a27" BREVITAS_COMMIT="a5b71d6de1389d3e7db898fef72e014842670f03" PYVERILATOR_COMMIT="766e457465f5c0dd315490d7b9cc5d74f9a76f4f" CNPY_COMMIT="4e8810b1a8637695171ed346ce68f6984e585ef4" From 93b96f814303ef75146c2f8112d651dbd1b35c6b Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 14 Feb 2023 11:36:30 +0000 Subject: [PATCH 033/665] [Deps] Update finn-hlslib commit --- fetch-repos.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fetch-repos.sh b/fetch-repos.sh index 5b060f5bc8..dd23c33e1b 100755 --- a/fetch-repos.sh +++ b/fetch-repos.sh @@ -32,7 +32,7 @@ FINN_EXP_COMMIT="9cbd2787b5160e2b44e0e8164a0df1457dbd5366" BREVITAS_COMMIT="a5b71d6de1389d3e7db898fef72e014842670f03" PYVERILATOR_COMMIT="766e457465f5c0dd315490d7b9cc5d74f9a76f4f" CNPY_COMMIT="4e8810b1a8637695171ed346ce68f6984e585ef4" -HLSLIB_COMMIT="d27f6b6c5d8f1bb208db395659389603f63ad4be" +HLSLIB_COMMIT="4ddfa00b07275a3f1de1c13409e6acb489115fe2" OMX_COMMIT="d1065a788219ca0eb54d5e57600b1f9d7f67d4cc" AVNET_BDF_COMMIT="2d49cfc25766f07792c0b314489f21fe916b639b" XIL_BDF_COMMIT="8cf4bb674a919ac34e3d99d8d71a9e60af93d14e" From a31a13978ed0b4d176001d7d21c35d79893e32d6 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 15 Feb 2023 16:20:23 +0000 Subject: [PATCH 034/665] [Deps] Update qonnx commit --- fetch-repos.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fetch-repos.sh b/fetch-repos.sh index b7b616e166..9e06e196e2 100755 --- a/fetch-repos.sh +++ b/fetch-repos.sh @@ -27,7 +27,7 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -QONNX_COMMIT="13d777a2aa0dc449dc3de7aa369c1e155d6ce2c2 " +QONNX_COMMIT="383d511db8d540ff9efadf2d620db7caa44bf876" FINN_EXP_COMMIT="9cbd2787b5160e2b44e0e8164a0df1457dbd5366" BREVITAS_COMMIT="a5b71d6de1389d3e7db898fef72e014842670f03" PYVERILATOR_COMMIT="766e457465f5c0dd315490d7b9cc5d74f9a76f4f" @@ -38,7 +38,7 @@ AVNET_BDF_COMMIT="2d49cfc25766f07792c0b314489f21fe916b639b" XIL_BDF_COMMIT="8cf4bb674a919ac34e3d99d8d71a9e60af93d14e" EXP_BOARD_FILES_MD5="30eecc497c31050bd46d10ea20eba232" -QONNX_URL="https://github.com/i-colbert/qonnx.git" +QONNX_URL="https://github.com/fastmachinelearning/qonnx.git" FINN_EXP_URL="https://github.com/Xilinx/finn-experimental.git" BREVITAS_URL="https://github.com/Xilinx/brevitas.git" PYVERILATOR_URL="https://github.com/maltanar/pyverilator.git" From c62dc7638ab74bc38c95341de9a4d99a620f2b82 Mon Sep 17 00:00:00 2001 From: auphelia Date: Thu, 16 Feb 2023 15:40:09 +0000 Subject: [PATCH 035/665] [Docs] Add new transform to docs --- .../source_code/finn.transformation.fpgadataflow.rst | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/docs/finn/source_code/finn.transformation.fpgadataflow.rst b/docs/finn/source_code/finn.transformation.fpgadataflow.rst index 9f8ec07930..f7137ae347 100644 --- a/docs/finn/source_code/finn.transformation.fpgadataflow.rst +++ b/docs/finn/source_code/finn.transformation.fpgadataflow.rst @@ -173,6 +173,15 @@ finn.transformation.fpgadataflow.minimize\_accumulator\_width :show-inheritance: +finn.transformation.fpgadataflow.minimize\_weight\_bit\_width +-------------------------------------------------------------- + +.. automodule:: finn.transformation.fpgadataflow.minimize_weight_bit_width + :members: + :undoc-members: + :show-inheritance: + + finn.transformation.fpgadataflow.prepare\_cppsim ------------------------------------------------------- From dbf592687cef670ab49c96d16ddaf3e2fa2f09d2 Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 20 Feb 2023 15:24:11 +0000 Subject: [PATCH 036/665] [Notebooks] Update Brevitas import nbs --- ...a_brevitas_network_import_via_FINN-ONNX.ipynb | 2 +- .../1b_brevitas_network_import_via_QONNX.ipynb | 16 +++++++--------- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/notebooks/basics/1a_brevitas_network_import_via_FINN-ONNX.ipynb b/notebooks/basics/1a_brevitas_network_import_via_FINN-ONNX.ipynb index 2d751b43b6..429effca83 100644 --- a/notebooks/basics/1a_brevitas_network_import_via_FINN-ONNX.ipynb +++ b/notebooks/basics/1a_brevitas_network_import_via_FINN-ONNX.ipynb @@ -6,7 +6,7 @@ "source": [ "# Importing Brevitas networks into FINN with the FINN-ONNX interchange format\n", "\n", - "**Note: This notebook is very similar to the 1b notebook, in that it shows the same concepts for the FINN-ONNX ingestion as 1b does for QONNX.**\n", + "**Note: This notebook is very similar to the 1b notebook, in that it shows the same concepts for the FINN-ONNX ingestion as 1b does for QONNX. Section 1 is identical in both notebooks.**\n", "\n", "In this notebook we'll go through an example of how to import a Brevitas-trained QNN into FINN. The steps will be as follows:\n", "\n", diff --git a/notebooks/basics/1b_brevitas_network_import_via_QONNX.ipynb b/notebooks/basics/1b_brevitas_network_import_via_QONNX.ipynb index 2d8447ad3a..fba824dca2 100644 --- a/notebooks/basics/1b_brevitas_network_import_via_QONNX.ipynb +++ b/notebooks/basics/1b_brevitas_network_import_via_QONNX.ipynb @@ -6,7 +6,7 @@ "source": [ "# Importing Brevitas networks into FINN with the QONNX interchange format\n", "\n", - "**Note: This notebook is very similar to the 1a notebook, in that it shows the same concepts for the QONNX ingestion as 1a does for FINN-ONNX.**\n", + "**Note: This notebook is very similar to the 1a notebook, in that it shows the same concepts for the QONNX ingestion as 1a does for FINN-ONNX. Section 1 is identical in both notebooks.**\n", "\n", "In this notebook we'll go through an example of how to import a Brevitas-trained QNN into FINN. The steps will be as follows:\n", "\n", @@ -217,7 +217,7 @@ "from qonnx.core.modelwrapper import ModelWrapper\n", "import qonnx.core.onnx_exec as oxe\n", "model = ModelWrapper(export_onnx_path_cleaned)\n", - "input_dict = {\"0\": nph.to_array(input_tensor)}\n", + "input_dict = {\"global_in\": nph.to_array(input_tensor)}\n", "output_dict = oxe.execute_onnx(model, input_dict)\n", "produced_qonnx = output_dict[list(output_dict.keys())[0]]\n", "\n", @@ -230,7 +230,7 @@ "metadata": {}, "outputs": [], "source": [ - "np.isclose(produced, produced_finn).all()" + "np.isclose(produced, produced_qonnx).all()" ] }, { @@ -258,9 +258,7 @@ { "cell_type": "code", "execution_count": null, - "metadata": { - "scrolled": false - }, + "metadata": {}, "outputs": [], "source": [ "showInNetron(export_onnx_path_converted)" @@ -280,7 +278,7 @@ "outputs": [], "source": [ "model = ModelWrapper(export_onnx_path_cleaned)\n", - "input_dict = {\"0\": nph.to_array(input_tensor)}\n", + "input_dict = {\"global_in\": nph.to_array(input_tensor)}\n", "output_dict = oxe.execute_onnx(model, input_dict)\n", "produced_finn = output_dict[list(output_dict.keys())[0]]\n", "\n", @@ -293,7 +291,7 @@ "metadata": {}, "outputs": [], "source": [ - "np.isclose(produced, produced_finn).all()" + "np.isclose(produced_qonnx, produced_finn).all()" ] }, { @@ -306,7 +304,7 @@ ], "metadata": { "kernelspec": { - "display_name": "Python 3", + "display_name": "Python 3 (ipykernel)", "language": "python", "name": "python3" }, From 15a3552654a88bd0b3b59c68aaf2e3eacd67326d Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 21 Feb 2023 16:07:41 +0000 Subject: [PATCH 037/665] [Deps] Update brevitas commit to v0.8.0 --- fetch-repos.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fetch-repos.sh b/fetch-repos.sh index dd23c33e1b..f13037733e 100755 --- a/fetch-repos.sh +++ b/fetch-repos.sh @@ -29,7 +29,7 @@ QONNX_COMMIT="dd35a8ff49d7225a07ffceeebe25a6361df48349" FINN_EXP_COMMIT="9cbd2787b5160e2b44e0e8164a0df1457dbd5366" -BREVITAS_COMMIT="a5b71d6de1389d3e7db898fef72e014842670f03" +BREVITAS_COMMIT="c65f9c13dc124971f14739349531bbcda5c2a4aa" PYVERILATOR_COMMIT="766e457465f5c0dd315490d7b9cc5d74f9a76f4f" CNPY_COMMIT="4e8810b1a8637695171ed346ce68f6984e585ef4" HLSLIB_COMMIT="4ddfa00b07275a3f1de1c13409e6acb489115fe2" From 1b1ee9b3a3c129447d5f3615b989ecbcc7ffd01d Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 21 Feb 2023 16:13:00 +0000 Subject: [PATCH 038/665] [Tests] Update export fct in transformation tests --- .../streamline/test_sign_to_thres.py | 5 +++-- .../streamline/test_streamline_cnv.py | 5 +++-- .../streamline/test_streamline_fc.py | 5 +++-- .../test_batchnorm_to_affine_bnn_pynq.py | 7 ++++--- .../transformation/test_infer_data_layouts_cnv.py | 5 +++-- tests/transformation/test_infer_datatypes_lfc.py | 5 +++-- tests/transformation/test_qonnx_to_finn.py | 14 ++++++-------- 7 files changed, 25 insertions(+), 21 deletions(-) diff --git a/tests/transformation/streamline/test_sign_to_thres.py b/tests/transformation/streamline/test_sign_to_thres.py index 839680bd7a..72e400346d 100644 --- a/tests/transformation/streamline/test_sign_to_thres.py +++ b/tests/transformation/streamline/test_sign_to_thres.py @@ -28,10 +28,11 @@ import pytest -import brevitas.onnx as bo import onnx import onnx.numpy_helper as nph import os +import torch +from brevitas.export import export_finn_onnx from pkgutil import get_data from qonnx.core.modelwrapper import ModelWrapper from qonnx.transformation.fold_constants import FoldConstants @@ -47,7 +48,7 @@ @pytest.mark.streamline def test_sign_to_thres(): lfc = get_test_model_trained("LFC", 1, 1) - bo.export_finn_onnx(lfc, (1, 1, 28, 28), export_onnx_path) + export_finn_onnx(lfc, torch.randn(1, 1, 28, 28), export_onnx_path) model = ModelWrapper(export_onnx_path) model = model.transform(InferShapes()) model = model.transform(FoldConstants()) diff --git a/tests/transformation/streamline/test_streamline_cnv.py b/tests/transformation/streamline/test_streamline_cnv.py index 6a82925012..b7d6a825bb 100644 --- a/tests/transformation/streamline/test_streamline_cnv.py +++ b/tests/transformation/streamline/test_streamline_cnv.py @@ -30,8 +30,9 @@ import pytest -import brevitas.onnx as bo import numpy as np +import torch +from brevitas.export import export_finn_onnx from qonnx.core.modelwrapper import ModelWrapper from qonnx.transformation.fold_constants import FoldConstants from qonnx.transformation.general import ( @@ -63,7 +64,7 @@ def test_streamline_cnv(size, wbits, abits): nname = "%s_%dW%dA" % (size, wbits, abits) finn_onnx = export_onnx_path + "/%s.onnx" % nname fc = get_test_model_trained(size, wbits, abits) - bo.export_finn_onnx(fc, (1, 3, 32, 32), finn_onnx) + export_finn_onnx(fc, torch.randn(1, 3, 32, 32), finn_onnx) model = ModelWrapper(finn_onnx) model = model.transform(InferShapes()) model = model.transform(FoldConstants()) diff --git a/tests/transformation/streamline/test_streamline_fc.py b/tests/transformation/streamline/test_streamline_fc.py index 9000821435..6131c3b03e 100644 --- a/tests/transformation/streamline/test_streamline_fc.py +++ b/tests/transformation/streamline/test_streamline_fc.py @@ -28,10 +28,11 @@ import pytest -import brevitas.onnx as bo import numpy as np import onnx import onnx.numpy_helper as nph +import torch +from brevitas.export import export_finn_onnx from pkgutil import get_data from qonnx.core.modelwrapper import ModelWrapper from qonnx.transformation.fold_constants import FoldConstants @@ -66,7 +67,7 @@ def test_streamline_fc(size, wbits, abits): nname = "%s_%dW%dA" % (size, wbits, abits) finn_onnx = export_onnx_path + "/%s.onnx" % nname fc = get_test_model_trained(size, wbits, abits) - bo.export_finn_onnx(fc, (1, 1, 28, 28), finn_onnx) + export_finn_onnx(fc, torch.randn(1, 1, 28, 28), finn_onnx) model = ModelWrapper(finn_onnx) model = model.transform(InferShapes()) model = model.transform(FoldConstants()) diff --git a/tests/transformation/test_batchnorm_to_affine_bnn_pynq.py b/tests/transformation/test_batchnorm_to_affine_bnn_pynq.py index fd4e37807c..60e81ffe81 100644 --- a/tests/transformation/test_batchnorm_to_affine_bnn_pynq.py +++ b/tests/transformation/test_batchnorm_to_affine_bnn_pynq.py @@ -30,11 +30,12 @@ import pytest -import brevitas.onnx as bo import numpy as np import onnx import onnx.numpy_helper as nph import os +import torch +from brevitas.export import export_finn_onnx from pkgutil import get_data from qonnx.core.modelwrapper import ModelWrapper from qonnx.transformation.batchnorm_to_affine import BatchNormToAffine @@ -50,7 +51,7 @@ @pytest.mark.transform def test_batchnorm_to_affine_cnv_w1a1(): lfc = get_test_model_trained("CNV", 1, 1) - bo.export_finn_onnx(lfc, (1, 3, 32, 32), export_onnx_path) + export_finn_onnx(lfc, torch.randn(1, 3, 32, 32), export_onnx_path) model = ModelWrapper(export_onnx_path) model = model.transform(InferShapes()) model = model.transform(FoldConstants()) @@ -75,7 +76,7 @@ def test_batchnorm_to_affine_cnv_w1a1(): @pytest.mark.transform def test_batchnorm_to_affine_lfc_w1a1(): lfc = get_test_model_trained("LFC", 1, 1) - bo.export_finn_onnx(lfc, (1, 1, 28, 28), export_onnx_path) + export_finn_onnx(lfc, torch.randn(1, 1, 28, 28), export_onnx_path) model = ModelWrapper(export_onnx_path) model = model.transform(InferShapes()) model = model.transform(FoldConstants()) diff --git a/tests/transformation/test_infer_data_layouts_cnv.py b/tests/transformation/test_infer_data_layouts_cnv.py index 952ce306a4..71822a2903 100644 --- a/tests/transformation/test_infer_data_layouts_cnv.py +++ b/tests/transformation/test_infer_data_layouts_cnv.py @@ -28,9 +28,10 @@ import pytest -import brevitas.onnx as bo import os import qonnx.core.data_layout as DataLayout +import torch +from brevitas.export import export_finn_onnx from qonnx.core.modelwrapper import ModelWrapper from qonnx.transformation.bipolar_to_xnor import ConvertBipolarMatMulToXnorPopcount from qonnx.transformation.fold_constants import FoldConstants @@ -51,7 +52,7 @@ @pytest.mark.transform def test_infer_data_layouts_cnv(): cnv = get_test_model_trained("CNV", 1, 1) - bo.export_finn_onnx(cnv, (1, 3, 32, 32), export_onnx_path_cnv) + export_finn_onnx(cnv, torch.randn(1, 3, 32, 32), export_onnx_path_cnv) model = ModelWrapper(export_onnx_path_cnv) model = model.transform(InferShapes()) model = model.transform(FoldConstants()) diff --git a/tests/transformation/test_infer_datatypes_lfc.py b/tests/transformation/test_infer_datatypes_lfc.py index 9798005349..173532cb76 100644 --- a/tests/transformation/test_infer_datatypes_lfc.py +++ b/tests/transformation/test_infer_datatypes_lfc.py @@ -28,8 +28,9 @@ import pytest -import brevitas.onnx as bo import os +import torch +from brevitas.export import export_finn_onnx from qonnx.core.datatype import DataType from qonnx.core.modelwrapper import ModelWrapper from qonnx.transformation.fold_constants import FoldConstants @@ -45,7 +46,7 @@ @pytest.mark.transform def test_infer_datatypes_lfc(): lfc = get_test_model_trained("LFC", 1, 1) - bo.export_finn_onnx(lfc, (1, 1, 28, 28), export_onnx_path) + export_finn_onnx(lfc, torch.randn(1, 1, 28, 28), export_onnx_path) model = ModelWrapper(export_onnx_path) model = model.transform(InferShapes()) model = model.transform(FoldConstants()) diff --git a/tests/transformation/test_qonnx_to_finn.py b/tests/transformation/test_qonnx_to_finn.py index 7e438b4b8b..e5f1eefe12 100644 --- a/tests/transformation/test_qonnx_to_finn.py +++ b/tests/transformation/test_qonnx_to_finn.py @@ -31,12 +31,11 @@ import pytest -import brevitas.export.onnx.generic as b_onnx -import brevitas.onnx as bo import numpy as np import onnx import onnx.numpy_helper as nph import torch +from brevitas.export import export_finn_onnx, export_qonnx from pkgutil import get_data from qonnx.core.modelwrapper import ModelWrapper from qonnx.transformation.fold_constants import FoldConstants @@ -117,8 +116,10 @@ def test_QONNX_to_FINN(model_name, wbits, abits): torch_input_tensor = torch.from_numpy(input_tensor).float() brev_output = brev_model.forward(torch_input_tensor).detach().numpy() - # Get "clean" FINN model and it's output - _ = bo.export_finn_onnx(brev_model, in_shape, finn_base_path.format("raw")) + # Get "clean" FINN model and its output + _ = export_finn_onnx( + brev_model, torch.randn(in_shape), finn_base_path.format("raw") + ) model = ModelWrapper(finn_base_path.format("raw")) model = model.transform(GiveUniqueNodeNames()) model = model.transform(InferShapes()) @@ -137,10 +138,7 @@ def test_QONNX_to_FINN(model_name, wbits, abits): ).all(), "The output of the Brevitas model and the FINN model should match." # Get the equivalent QONNX model - b_onnx.function.DOMAIN_STRING = "qonnx.custom_op.general" - _ = b_onnx.manager.BrevitasONNXManager.export( - brev_model, in_shape, qonnx_base_path.format("raw") - ) + _ = export_qonnx(brev_model, torch.randn(in_shape), qonnx_base_path.format("raw")) cleanup(qonnx_base_path.format("raw"), out_file=qonnx_base_path.format("clean")) # Compare output From ae210a2d53b563a56447c387873bf29afa627bcd Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 21 Feb 2023 16:27:21 +0000 Subject: [PATCH 039/665] [Tests] Update export fct in conversion to hls layer tests --- tests/fpgadataflow/test_convert_to_hls_layers_cnv.py | 5 +++-- tests/fpgadataflow/test_convert_to_hls_layers_fc.py | 6 +++--- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/tests/fpgadataflow/test_convert_to_hls_layers_cnv.py b/tests/fpgadataflow/test_convert_to_hls_layers_cnv.py index 9997f28438..73721b6cc5 100644 --- a/tests/fpgadataflow/test_convert_to_hls_layers_cnv.py +++ b/tests/fpgadataflow/test_convert_to_hls_layers_cnv.py @@ -30,9 +30,10 @@ import pytest -import brevitas.onnx as bo import numpy as np import os +import torch +from brevitas.export import export_finn_onnx from qonnx.core.modelwrapper import ModelWrapper from qonnx.custom_op.registry import getCustomOp from qonnx.transformation.bipolar_to_xnor import ConvertBipolarMatMulToXnorPopcount @@ -61,7 +62,7 @@ @pytest.mark.parametrize("fused_activation", [True, False]) def test_convert_to_hls_layers_cnv_w1a1(fused_activation): cnv = get_test_model_trained("CNV", 1, 1) - bo.export_finn_onnx(cnv, (1, 3, 32, 32), export_onnx_path_cnv) + export_finn_onnx(cnv, torch.randn(1, 3, 32, 32), export_onnx_path_cnv) model = ModelWrapper(export_onnx_path_cnv) model = model.transform(InferShapes()) model = model.transform(FoldConstants()) diff --git a/tests/fpgadataflow/test_convert_to_hls_layers_fc.py b/tests/fpgadataflow/test_convert_to_hls_layers_fc.py index fd4e3679d7..5a45638ba1 100644 --- a/tests/fpgadataflow/test_convert_to_hls_layers_fc.py +++ b/tests/fpgadataflow/test_convert_to_hls_layers_fc.py @@ -28,12 +28,12 @@ import pytest -import brevitas.onnx as bo import numpy as np import onnx import onnx.numpy_helper as nph import os import torch +from brevitas.export import export_finn_onnx from pkgutil import get_data from qonnx.core.modelwrapper import ModelWrapper from qonnx.custom_op.registry import getCustomOp @@ -59,7 +59,7 @@ @pytest.mark.vivado def test_convert_to_hls_layers_tfc_w1a1(): tfc = get_test_model_trained("TFC", 1, 1) - bo.export_finn_onnx(tfc, (1, 1, 28, 28), export_onnx_path) + export_finn_onnx(tfc, torch.randn(1, 1, 28, 28), export_onnx_path) model = ModelWrapper(export_onnx_path) model = model.transform(InferShapes()) model = model.transform(FoldConstants()) @@ -130,7 +130,7 @@ def test_convert_to_hls_layers_tfc_w1a1(): @pytest.mark.vivado def test_convert_to_hls_layers_tfc_w1a2(): tfc = get_test_model_trained("TFC", 1, 2) - bo.export_finn_onnx(tfc, (1, 1, 28, 28), export_onnx_path) + export_finn_onnx(tfc, torch.randn(1, 1, 28, 28), export_onnx_path) model = ModelWrapper(export_onnx_path) model = model.transform(InferShapes()) model = model.transform(FoldConstants()) From c0410fda5ab99c60e89a4aa5d4924f0fc2d50a58 Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 21 Feb 2023 17:04:05 +0000 Subject: [PATCH 040/665] [Notebooks] Update export fct in Jupyter nbs --- .../basics/1a_brevitas_network_import_via_FINN-ONNX.ipynb | 4 ++-- .../basics/1b_brevitas_network_import_via_QONNX.ipynb | 4 ++-- .../end2end_example/bnn-pynq/cnv_end2end_example.ipynb | 7 ++++--- .../end2end_example/bnn-pynq/tfc_end2end_example.ipynb | 7 ++++--- .../cybersecurity/1-train-mlp-with-brevitas.ipynb | 4 ++-- 5 files changed, 14 insertions(+), 12 deletions(-) diff --git a/notebooks/basics/1a_brevitas_network_import_via_FINN-ONNX.ipynb b/notebooks/basics/1a_brevitas_network_import_via_FINN-ONNX.ipynb index 429effca83..756faf149d 100644 --- a/notebooks/basics/1a_brevitas_network_import_via_FINN-ONNX.ipynb +++ b/notebooks/basics/1a_brevitas_network_import_via_FINN-ONNX.ipynb @@ -139,10 +139,10 @@ "metadata": {}, "outputs": [], "source": [ - "import brevitas.onnx as bo\n", + "from brevitas.export import export_finn_onnx\n", "export_onnx_path = \"/tmp/LFCW1A1_finn-onnx.onnx\"\n", "input_shape = (1, 1, 28, 28)\n", - "bo.export_finn_onnx(lfc, input_shape, export_onnx_path);" + "export_finn_onnx(lfc, torch.randn(input_shape), export_onnx_path);" ] }, { diff --git a/notebooks/basics/1b_brevitas_network_import_via_QONNX.ipynb b/notebooks/basics/1b_brevitas_network_import_via_QONNX.ipynb index fba824dca2..58fa3fc7e1 100644 --- a/notebooks/basics/1b_brevitas_network_import_via_QONNX.ipynb +++ b/notebooks/basics/1b_brevitas_network_import_via_QONNX.ipynb @@ -142,10 +142,10 @@ "metadata": {}, "outputs": [], "source": [ - "from brevitas.export.onnx.generic.manager import BrevitasONNXManager\n", + "from brevitas.export import export_qonnx\n", "export_onnx_path = \"/tmp/LFCW1A1_qonnx.onnx\"\n", "input_shape = (1, 1, 28, 28)\n", - "BrevitasONNXManager.export(lfc, input_shape, export_onnx_path);" + "export_qonnx(lfc, torch.randn(input_shape), export_onnx_path);" ] }, { diff --git a/notebooks/end2end_example/bnn-pynq/cnv_end2end_example.ipynb b/notebooks/end2end_example/bnn-pynq/cnv_end2end_example.ipynb index 388accad3a..0018bb27ca 100644 --- a/notebooks/end2end_example/bnn-pynq/cnv_end2end_example.ipynb +++ b/notebooks/end2end_example/bnn-pynq/cnv_end2end_example.ipynb @@ -81,16 +81,17 @@ "metadata": {}, "outputs": [], "source": [ + "import torch\n", "import onnx\n", "from finn.util.test import get_test_model_trained\n", - "import brevitas.onnx as bo\n", + "from brevitas.export import export_finn_onnx\n", "from qonnx.core.modelwrapper import ModelWrapper\n", "from qonnx.transformation.infer_shapes import InferShapes\n", "from qonnx.transformation.fold_constants import FoldConstants\n", "from qonnx.transformation.general import GiveReadableTensorNames, GiveUniqueNodeNames, RemoveStaticGraphInputs\n", "\n", "cnv = get_test_model_trained(\"CNV\", 1, 1)\n", - "bo.export_finn_onnx(cnv, (1, 3, 32, 32), build_dir + \"/end2end_cnv_w1a1_export.onnx\")\n", + "export_finn_onnx(cnv, torch.randn(1, 3, 32, 32), build_dir + \"/end2end_cnv_w1a1_export.onnx\")\n", "model = ModelWrapper(build_dir + \"/end2end_cnv_w1a1_export.onnx\")\n", "model = model.transform(InferShapes())\n", "model = model.transform(FoldConstants())\n", @@ -148,7 +149,7 @@ "# preprocessing: torchvision's ToTensor divides uint8 inputs by 255\n", "totensor_pyt = ToTensor()\n", "chkpt_preproc_name = build_dir+\"/end2end_cnv_w1a1_preproc.onnx\"\n", - "bo.export_finn_onnx(totensor_pyt, ishape, chkpt_preproc_name)\n", + "export_finn_onnx(totensor_pyt, torch.randn(ishape), chkpt_preproc_name)\n", "\n", "# join preprocessing and core model\n", "pre_model = ModelWrapper(chkpt_preproc_name)\n", diff --git a/notebooks/end2end_example/bnn-pynq/tfc_end2end_example.ipynb b/notebooks/end2end_example/bnn-pynq/tfc_end2end_example.ipynb index eec17b2fa7..f99944e31f 100644 --- a/notebooks/end2end_example/bnn-pynq/tfc_end2end_example.ipynb +++ b/notebooks/end2end_example/bnn-pynq/tfc_end2end_example.ipynb @@ -81,12 +81,13 @@ "metadata": {}, "outputs": [], "source": [ + "import torch\n", "import onnx\n", "from finn.util.test import get_test_model_trained\n", - "import brevitas.onnx as bo\n", + "from brevitas.export import export_finn_onnx\n", "\n", "tfc = get_test_model_trained(\"TFC\", 1, 1)\n", - "bo.export_finn_onnx(tfc, (1, 1, 28, 28), build_dir+\"/tfc_w1_a1.onnx\"); # semicolon added to suppress log" + "export_finn_onnx(tfc, torch.randn(1, 1, 28, 28), build_dir+\"/tfc_w1_a1.onnx\"); # semicolon added to suppress log" ] }, { @@ -267,7 +268,7 @@ "# preprocessing: torchvision's ToTensor divides uint8 inputs by 255\n", "totensor_pyt = ToTensor()\n", "chkpt_preproc_name = build_dir+\"/tfc_w1_a1_preproc.onnx\"\n", - "bo.export_finn_onnx(totensor_pyt, ishape, chkpt_preproc_name)\n", + "export_finn_onnx(totensor_pyt, torch.randn(ishape), chkpt_preproc_name)\n", "\n", "# join preprocessing and core model\n", "pre_model = ModelWrapper(chkpt_preproc_name)\n", diff --git a/notebooks/end2end_example/cybersecurity/1-train-mlp-with-brevitas.ipynb b/notebooks/end2end_example/cybersecurity/1-train-mlp-with-brevitas.ipynb index 3d77586258..9bb9e6761e 100644 --- a/notebooks/end2end_example/cybersecurity/1-train-mlp-with-brevitas.ipynb +++ b/notebooks/end2end_example/cybersecurity/1-train-mlp-with-brevitas.ipynb @@ -677,7 +677,7 @@ "metadata": {}, "outputs": [], "source": [ - "import brevitas.onnx as bo\n", + "from brevitas.export import export_finn_onnx\n", "from brevitas.quant_tensor import QuantTensor\n", "\n", "ready_model_filename = \"cybsec-mlp-ready.onnx\"\n", @@ -696,7 +696,7 @@ "model_for_export.cpu()\n", "\n", "# Export to ONNX\n", - "bo.export_finn_onnx(\n", + "export_finn_onnx(\n", " model_for_export, export_path=ready_model_filename, input_t=input_qt\n", ")\n", "\n", From f60e4abe943dac75a03fb1824c4fb02e700cfb26 Mon Sep 17 00:00:00 2001 From: icolbert Date: Tue, 21 Feb 2023 09:14:54 -0800 Subject: [PATCH 041/665] Inline lambda function for data type bound --- src/finn/custom_op/fpgadataflow/matrixvectoractivation.py | 6 +++--- src/finn/custom_op/fpgadataflow/vectorvectoractivation.py | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index c440b3675c..6aa26af453 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -353,12 +353,12 @@ def lut_estimation(self): acc_datatype = self.get_accumulator_datatype() # if accDataType is not set, then it will default to INT32, which would # be a large overestimate in most (if not all) cases. In this scenario, - # we would use the minimum accumulator as determined by the data types. + # we would use the minimum accumulator as determined by the data types + # bound, derived in https://arxiv.org/abs/2301.13376 alpha = math.log(MW, 2) + W + A - 1 - int(idt.signed()) - phi = lambda x_: math.log(1 + pow(2, -x_), 2) acc_bits = min( acc_datatype.bitwidth(), - np.ceil(alpha + phi(alpha) + 1) + np.ceil(alpha + math.log(1 + pow(2, -alpha), 2) + 1) ) acc_luts = acc_bits # thresholds and threshold comparators diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index 377a62f79f..796225a712 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -1199,12 +1199,12 @@ def lut_estimation(self): k_h, k_w = self.get_nodeattr("Kernel") # if accDataType is not set, then it will default to INT32, which would # be a large overestimate in most (if not all) cases. In this scenario, - # we would use the minimum accumulator as determined by the data types. + # we would use the minimum accumulator as determined by the data types + # bound, derived in https://arxiv.org/abs/2301.13376 alpha = math.log(k_h * k_w, 2) + W + A - 1 - int(idt.signed()) - phi = lambda x_: math.log(1 + pow(2, -x_), 2) acc_bits = min( acc_datatype.bitwidth(), - np.ceil(alpha + phi(alpha) + 1) + np.ceil(alpha + math.log(1 + pow(2, -alpha), 2) + 1) ) acc_luts = acc_bits # thresholds and threshold comparators From 88b00a9fff71f859c187540bfb2384db0392df3e Mon Sep 17 00:00:00 2001 From: icolbert Date: Tue, 21 Feb 2023 09:52:58 -0800 Subject: [PATCH 042/665] Adding minimize_bit_width to the build config --- src/finn/builder/build_dataflow_config.py | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/finn/builder/build_dataflow_config.py b/src/finn/builder/build_dataflow_config.py index a38cb6e572..53576e50e7 100644 --- a/src/finn/builder/build_dataflow_config.py +++ b/src/finn/builder/build_dataflow_config.py @@ -233,6 +233,12 @@ class DataflowBuildConfig: #: flexibility, and makes it possible to have runtime-writable thresholds. standalone_thresholds: Optional[bool] = False + #: (Optional) Whether optimizations that minimize the bit width of the + #: weights and accumulator will be applied. Because this optimization relies + #: on the the values of the weights, it will only be applied if runtime- + #: writeable weights is not enabled. + minimize_bit_width: Optional[bool] = True + #: Target board, only needed for generating full bitfiles where the FINN #: design is integrated into a shell. #: e.g. "Pynq-Z1" or "U250" From 9c74af528dc1cdd0a238e1ae4caa730e06e4c479 Mon Sep 17 00:00:00 2001 From: icolbert Date: Tue, 21 Feb 2023 10:44:20 -0800 Subject: [PATCH 043/665] Creating and adding build step to default finn flows --- src/finn/builder/build_dataflow_config.py | 2 ++ src/finn/builder/build_dataflow_steps.py | 10 ++++++++++ 2 files changed, 12 insertions(+) diff --git a/src/finn/builder/build_dataflow_config.py b/src/finn/builder/build_dataflow_config.py index 53576e50e7..4c3e4ff899 100644 --- a/src/finn/builder/build_dataflow_config.py +++ b/src/finn/builder/build_dataflow_config.py @@ -119,6 +119,7 @@ class VerificationStepType(str, Enum): "step_create_dataflow_partition", "step_target_fps_parallelization", "step_apply_folding_config", + "step_minimize_bit_width", "step_generate_estimate_reports", "step_hls_codegen", "step_hls_ipgen", @@ -140,6 +141,7 @@ class VerificationStepType(str, Enum): "step_create_dataflow_partition", "step_target_fps_parallelization", "step_apply_folding_config", + "step_minimize_bit_width", "step_generate_estimate_reports", ] diff --git a/src/finn/builder/build_dataflow_steps.py b/src/finn/builder/build_dataflow_steps.py index 2ee898bc7d..16ac90296f 100644 --- a/src/finn/builder/build_dataflow_steps.py +++ b/src/finn/builder/build_dataflow_steps.py @@ -118,6 +118,8 @@ from finn.util.pyverilator import verilator_fifosim from finn.util.test import execute_parent +from finn.transformation.fpgadataflow.minimize_accumulator_width import MinimizeAccumulatorWidth +from finn.transformation.fpgadataflow.minimize_weight_bit_width import MinimizeWeightBitWidth def verify_step( model: ModelWrapper, @@ -477,6 +479,14 @@ def step_generate_estimate_reports(model: ModelWrapper, cfg: DataflowBuildConfig return model +def step_minimize_bit_width(model: ModelWrapper, cfg: DataflowBuildConfig): + """Tighten the weight and accumulator bit widths for each layer.""" + if cfg.minimize_bit_width: + model = model.transform(MinimizeWeightBitWidth()) + model = model.transform(MinimizeAccumulatorWidth()) + return model + + def step_hls_codegen(model: ModelWrapper, cfg: DataflowBuildConfig): "Generate Vivado HLS code to prepare HLSCustomOp nodes for IP generation." From 49055cf229f1b959ba38916d5c25cd3a7036d35e Mon Sep 17 00:00:00 2001 From: icolbert Date: Tue, 21 Feb 2023 11:13:36 -0800 Subject: [PATCH 044/665] Remove MinimizeAccumulatorWidth from convert_to_hls layers --- .../fpgadataflow/convert_to_hls_layers.py | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py b/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py index 7b8a1bf6b8..3029e09d48 100644 --- a/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py +++ b/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py @@ -40,10 +40,6 @@ from qonnx.util.basic import get_by_name from qonnx.util.onnx import nchw_to_nhwc -from finn.transformation.fpgadataflow.minimize_accumulator_width import ( - MinimizeAccumulatorWidth, -) - class InferConvInpGen(Transformation): """Convert Im2Col layers to ConvolutionInputGenerator layers.""" @@ -761,7 +757,6 @@ def apply(self, model): graph.node.remove(n) graph_modified = True if graph_modified: - model = model.transform(MinimizeAccumulatorWidth()) model = model.transform(InferShapes()) model = model.transform(InferDataTypes()) return (model, graph_modified) @@ -904,7 +899,6 @@ def apply(self, model): graph.node.remove(n) graph_modified = True if graph_modified: - model = model.transform(MinimizeAccumulatorWidth()) model = model.transform(InferShapes()) model = model.transform(InferDataTypes()) return (model, graph_modified) @@ -1057,7 +1051,6 @@ def apply(self, model): graph.node.remove(n) graph_modified = True if graph_modified: - model = model.transform(MinimizeAccumulatorWidth()) model = model.transform(InferShapes()) model = model.transform(InferDataTypes()) return (model, graph_modified) @@ -1135,7 +1128,7 @@ def apply(self, model): PE=pe, numSteps=thl_thres_shape[1], inputDataType=idt.name, - weightDataType=idt.name, # will be set by MinimizeAccumulatorWidth + weightDataType=idt.name, # can be tightened by MinimizeAccumulatorWidth outputDataType=odt.name, numInputVectors=list(thl_in_shape[:-1]), ActVal=actval, @@ -1148,7 +1141,6 @@ def apply(self, model): graph_modified = True if graph_modified: - model = model.transform(MinimizeAccumulatorWidth()) model = model.transform(InferShapes()) model = model.transform(InferDataTypes()) return (model, graph_modified) From c553deac9356c42a8eccb6ac810fafa3afda01e4 Mon Sep 17 00:00:00 2001 From: icolbert Date: Tue, 21 Feb 2023 15:51:04 -0800 Subject: [PATCH 045/665] Update minimize_accumulator_width to account for runtime-writeable weights --- .../fpgadataflow/matrixvectoractivation.py | 118 +++++++++--------- .../fpgadataflow/vectorvectoractivation.py | 117 ++++++++--------- 2 files changed, 121 insertions(+), 114 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index 6aa26af453..468e660117 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -589,69 +589,73 @@ def get_hls_compatible_weight_tensor(self, orig_weight_matrix): return ret def minimize_accumulator_width(self, model): - weights = model.get_initializer(self.onnx_node.input[1]) - # since in the calculation the values of the weight matrix are used, - # for the bipolar case they need to be converted to bipolar - if self.get_nodeattr("binaryXnorMode"): - weights = 2 * weights - 1 - if len(self.onnx_node.input) > 2: - thresholds = model.get_initializer(self.onnx_node.input[2]) - else: - thresholds = None - idt = self.get_input_datatype() - # calculate minimum and maximum values of accumulator - (acc_min, acc_max) = calculate_matvec_accumulator_range(weights, idt) - if thresholds is not None: - threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds) - # set threshold datatype (and accumulator datatype implicitly) - min_threshold = thresholds.min() - max_threshold = thresholds.max() - # clip threshold values - clip_upper = None - clip_lower = None - if max_threshold > acc_max + 1: - clip_upper = acc_max + 1 - if min_threshold < acc_min: - clip_lower = acc_min - if (clip_lower is not None) or (clip_upper is not None): - warnings.warn("Clipping some thresholds in %s" % self.onnx_node.name) - thresholds = np.clip(thresholds, clip_lower, clip_upper) - model.set_initializer(self.onnx_node.input[2], thresholds) + """Minimize the accumulator bit width according to the weight values, + input data types, and size of dot product""" + if not self.get_nodeattr("runtime_writeable_weights"): + weights = model.get_initializer(self.onnx_node.input[1]) + # since in the calculation the values of the weight matrix are used, + # for the bipolar case they need to be converted to bipolar + if self.get_nodeattr("binaryXnorMode"): + weights = 2 * weights - 1 + if len(self.onnx_node.input) > 2: + thresholds = model.get_initializer(self.onnx_node.input[2]) + else: + thresholds = None + idt = self.get_input_datatype() + # calculate minimum and maximum values of accumulator according to the + # weight values using the bounds derived in https://arxiv.org/abs/2301.13376 + (acc_min, acc_max) = calculate_matvec_accumulator_range(weights, idt) + if thresholds is not None: threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds) + # set threshold datatype (and accumulator datatype implicitly) min_threshold = thresholds.min() max_threshold = thresholds.max() - # get range required by threshold values - tdt_min = min(acc_min, min_threshold) - tdt_max = max(acc_max, max_threshold) - if tdt_min < 0: - if abs(tdt_min) > tdt_max: - tdt = DataType.get_smallest_possible(tdt_min) + # clip threshold values + clip_upper = None + clip_lower = None + if max_threshold > acc_max + 1: + clip_upper = acc_max + 1 + if min_threshold < acc_min: + clip_lower = acc_min + if (clip_lower is not None) or (clip_upper is not None): + warnings.warn("Clipping some thresholds in %s" % self.onnx_node.name) + thresholds = np.clip(thresholds, clip_lower, clip_upper) + model.set_initializer(self.onnx_node.input[2], thresholds) + threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds) + min_threshold = thresholds.min() + max_threshold = thresholds.max() + # get range required by threshold values + tdt_min = min(acc_min, min_threshold) + tdt_max = max(acc_max, max_threshold) + if tdt_min < 0: + if abs(tdt_min) > tdt_max: + tdt = DataType.get_smallest_possible(tdt_min) + else: + tdt = DataType.get_smallest_possible(-tdt_max - 1) else: - tdt = DataType.get_smallest_possible(-tdt_max - 1) + tdt = DataType.get_smallest_possible(tdt_max) + assert np.vectorize(tdt.allowed)( + threshold_tensor + ).all(), "Thresholds in %s can't be expressed with type %s" % ( + self.onnx_node.name, + str(tdt), + ) + self.set_nodeattr("accDataType", tdt.name) else: - tdt = DataType.get_smallest_possible(tdt_max) - assert np.vectorize(tdt.allowed)( - threshold_tensor - ).all(), "Thresholds in %s can't be expressed with type %s" % ( - self.onnx_node.name, - str(tdt), - ) - self.set_nodeattr("accDataType", tdt.name) - else: - if acc_min < 0: - if abs(acc_min) > acc_max: - adt = DataType.get_smallest_possible(acc_min) + if acc_min < 0: + if abs(acc_min) > acc_max: + adt = DataType.get_smallest_possible(acc_min) + else: + adt = DataType.get_smallest_possible(-acc_max - 1) else: - adt = DataType.get_smallest_possible(-acc_max - 1) - else: - adt = DataType.get_smallest_possible(acc_max) - # ensure a datatype divisible by 8-bits in case this is the last node - bw = roundup_to_integer_multiple(adt.bitwidth(), 8) - new_adt_name = adt.name.replace(str(adt.bitwidth()), str(bw)) - adt = DataType[new_adt_name] - self.set_nodeattr("accDataType", adt.name) - # for no-activation nodes, output dt = acc dt - self.set_nodeattr("outputDataType", adt.name) + adt = DataType.get_smallest_possible(acc_max) + # ensure a datatype divisible by 8-bits in case this is the last node + bw = roundup_to_integer_multiple(adt.bitwidth(), 8) + new_adt_name = adt.name.replace(str(adt.bitwidth()), str(bw)) + adt = DataType[new_adt_name] + self.set_nodeattr("accDataType", adt.name) + # for no-activation nodes, output dt = acc dt + self.set_nodeattr("outputDataType", adt.name) return DataType[self.get_nodeattr("accDataType")] def minimize_weight_bit_width(self, model): diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index 796225a712..f38abcc763 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -104,69 +104,72 @@ def get_nodeattr_types(self): return my_attrs def minimize_accumulator_width(self, model): - weights = model.get_initializer(self.onnx_node.input[1]) - k_h, k_w = self.get_nodeattr("Kernel") - fm = self.get_nodeattr("Channels") - # put weights into the shape expected by calculate_matvec_accumulator_range - weights = weights.reshape(fm, k_h * k_w).transpose() - if len(self.onnx_node.input) > 2: - thresholds = model.get_initializer(self.onnx_node.input[2]) - else: - thresholds = None - idt = self.get_input_datatype() - # calculate minimum and maximum values of accumulator - (acc_min, acc_max) = calculate_matvec_accumulator_range(weights, idt) - if thresholds is not None: - threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds) - # set threshold datatype (and accumulator datatype implicitly) - min_threshold = thresholds.min() - max_threshold = thresholds.max() - # clip threshold values - clip_upper = None - clip_lower = None - if max_threshold > acc_max + 1: - clip_upper = acc_max + 1 - if min_threshold < acc_min: - clip_lower = acc_min - if (clip_lower is not None) or (clip_upper is not None): - warnings.warn("Clipping some thresholds in %s" % self.onnx_node.name) - thresholds = np.clip(thresholds, clip_lower, clip_upper) - model.set_initializer(self.onnx_node.input[2], thresholds) + """Minimize the accumulator bit width according to the weight values, + input data types, and size of dot product""" + if not self.get_nodeattr("runtime_writeable_weights"): + weights = model.get_initializer(self.onnx_node.input[1]) + k_h, k_w = self.get_nodeattr("Kernel") + fm = self.get_nodeattr("Channels") + # put weights into the shape expected by calculate_matvec_accumulator_range + weights = weights.reshape(fm, k_h * k_w).transpose() + if len(self.onnx_node.input) > 2: + thresholds = model.get_initializer(self.onnx_node.input[2]) + else: + thresholds = None + idt = self.get_input_datatype() + # calculate minimum and maximum values of accumulator + (acc_min, acc_max) = calculate_matvec_accumulator_range(weights, idt) + if thresholds is not None: threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds) + # set threshold datatype (and accumulator datatype implicitly) min_threshold = thresholds.min() max_threshold = thresholds.max() - # get range required by threshold values - tdt_min = min(acc_min, min_threshold) - tdt_max = max(acc_max, max_threshold) - if tdt_min < 0: - if abs(tdt_min) > tdt_max: - tdt = DataType.get_smallest_possible(tdt_min) + # clip threshold values + clip_upper = None + clip_lower = None + if max_threshold > acc_max + 1: + clip_upper = acc_max + 1 + if min_threshold < acc_min: + clip_lower = acc_min + if (clip_lower is not None) or (clip_upper is not None): + warnings.warn("Clipping some thresholds in %s" % self.onnx_node.name) + thresholds = np.clip(thresholds, clip_lower, clip_upper) + model.set_initializer(self.onnx_node.input[2], thresholds) + threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds) + min_threshold = thresholds.min() + max_threshold = thresholds.max() + # get range required by threshold values + tdt_min = min(acc_min, min_threshold) + tdt_max = max(acc_max, max_threshold) + if tdt_min < 0: + if abs(tdt_min) > tdt_max: + tdt = DataType.get_smallest_possible(tdt_min) + else: + tdt = DataType.get_smallest_possible(-tdt_max - 1) else: - tdt = DataType.get_smallest_possible(-tdt_max - 1) + tdt = DataType.get_smallest_possible(tdt_max) + assert np.vectorize(tdt.allowed)( + threshold_tensor + ).all(), "Thresholds in %s can't be expressed with type %s" % ( + self.onnx_node.name, + str(tdt), + ) + self.set_nodeattr("accDataType", tdt.name) else: - tdt = DataType.get_smallest_possible(tdt_max) - assert np.vectorize(tdt.allowed)( - threshold_tensor - ).all(), "Thresholds in %s can't be expressed with type %s" % ( - self.onnx_node.name, - str(tdt), - ) - self.set_nodeattr("accDataType", tdt.name) - else: - if acc_min < 0: - if abs(acc_min) > acc_max: - adt = DataType.get_smallest_possible(acc_min) + if acc_min < 0: + if abs(acc_min) > acc_max: + adt = DataType.get_smallest_possible(acc_min) + else: + adt = DataType.get_smallest_possible(-acc_max - 1) else: - adt = DataType.get_smallest_possible(-acc_max - 1) - else: - adt = DataType.get_smallest_possible(acc_max) - # ensure a datatype divisible by 8-bits in case this is the last node - bw = roundup_to_integer_multiple(adt.bitwidth(), 8) - new_adt_name = adt.name.replace(str(adt.bitwidth()), str(bw)) - adt = DataType[new_adt_name] - self.set_nodeattr("accDataType", adt.name) - # for no-activation nodes, output dt = acc dt - self.set_nodeattr("outputDataType", adt.name) + adt = DataType.get_smallest_possible(acc_max) + # ensure a datatype divisible by 8-bits in case this is the last node + bw = roundup_to_integer_multiple(adt.bitwidth(), 8) + new_adt_name = adt.name.replace(str(adt.bitwidth()), str(bw)) + adt = DataType[new_adt_name] + self.set_nodeattr("accDataType", adt.name) + # for no-activation nodes, output dt = acc dt + self.set_nodeattr("outputDataType", adt.name) return DataType[self.get_nodeattr("accDataType")] def minimize_weight_bit_width(self, model): From 7c92c0f4f5f5f51b429fc3a0a9e1d3cc3d75a8ee Mon Sep 17 00:00:00 2001 From: icolbert Date: Tue, 21 Feb 2023 15:52:11 -0800 Subject: [PATCH 046/665] Updating comment on accumulator range calculation --- src/finn/custom_op/fpgadataflow/vectorvectoractivation.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index f38abcc763..232053b0fa 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -117,7 +117,8 @@ def minimize_accumulator_width(self, model): else: thresholds = None idt = self.get_input_datatype() - # calculate minimum and maximum values of accumulator + # calculate minimum and maximum values of accumulator according to the + # weight values using the bounds derived in https://arxiv.org/abs/2301.13376 (acc_min, acc_max) = calculate_matvec_accumulator_range(weights, idt) if thresholds is not None: threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds) From 205528b689894396fb0f709b1850ce74abf5c48a Mon Sep 17 00:00:00 2001 From: icolbert Date: Tue, 21 Feb 2023 15:59:45 -0800 Subject: [PATCH 047/665] Adding unit test --- tests/end2end/test_end2end_bnn_pynq.py | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index 858363d6d3..a627606f45 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -89,6 +89,8 @@ MakeMaxPoolNHWC, MoveScalarLinearPastInvariants, ) +from finn.transformation.fpgadataflow.minimize_accumulator_width import MinimizeAccumulatorWidth +from finn.transformation.fpgadataflow.minimize_weight_bit_width import MinimizeWeightBitWidth from finn.util.basic import get_finn_root from finn.util.gdrive import upload_to_end2end_dashboard from finn.util.pytorch import ToTensor @@ -511,11 +513,23 @@ def test_fold(self, topology, wbits, abits, QONNX_export): model = folding_fxn(model) model.save(get_checkpoint_name(topology, wbits, abits, QONNX_export, "fold")) + def test_minimize_bit_width(self, topology, wbits, abits, QONNX_export): + prev_chkpt_name = get_checkpoint_name( + topology, wbits, abits, QONNX_export, "fold" + ) + model = load_test_checkpoint_or_skip(prev_chkpt_name) + model = model.transform(MinimizeAccumulatorWidth()) + model = model.transform(MinimizeWeightBitWidth()) + curr_chkpt_name = get_checkpoint_name( + topology, wbits, abits, QONNX_export, "minimize_bit_width" + ) + model.save(curr_chkpt_name) + @pytest.mark.slow @pytest.mark.vivado def test_cppsim(self, topology, wbits, abits, QONNX_export): prev_chkpt_name = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "fold" + topology, wbits, abits, QONNX_export, "minimize_bit_width" ) model = load_test_checkpoint_or_skip(prev_chkpt_name) model = model.transform(PrepareCppSim()) From e7490079d1b5a4b1939ea8cfe0844497ce132f5e Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 22 Feb 2023 10:32:20 +0000 Subject: [PATCH 048/665] pre-commit cleanup --- src/finn/builder/build_dataflow_steps.py | 8 ++++++-- .../custom_op/fpgadataflow/matrixvectoractivation.py | 10 +++++++--- .../custom_op/fpgadataflow/vectorvectoractivation.py | 10 +++++++--- .../fpgadataflow/convert_to_hls_layers.py | 3 ++- .../fpgadataflow/minimize_weight_bit_width.py | 2 +- tests/end2end/test_end2end_bnn_pynq.py | 8 ++++++-- 6 files changed, 29 insertions(+), 12 deletions(-) diff --git a/src/finn/builder/build_dataflow_steps.py b/src/finn/builder/build_dataflow_steps.py index 16ac90296f..60290bbb98 100644 --- a/src/finn/builder/build_dataflow_steps.py +++ b/src/finn/builder/build_dataflow_steps.py @@ -89,6 +89,12 @@ from finn.transformation.fpgadataflow.insert_fifo import InsertFIFO from finn.transformation.fpgadataflow.make_pynq_driver import MakePYNQDriver from finn.transformation.fpgadataflow.make_zynq_proj import ZynqBuild +from finn.transformation.fpgadataflow.minimize_accumulator_width import ( + MinimizeAccumulatorWidth, +) +from finn.transformation.fpgadataflow.minimize_weight_bit_width import ( + MinimizeWeightBitWidth, +) from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim @@ -118,8 +124,6 @@ from finn.util.pyverilator import verilator_fifosim from finn.util.test import execute_parent -from finn.transformation.fpgadataflow.minimize_accumulator_width import MinimizeAccumulatorWidth -from finn.transformation.fpgadataflow.minimize_weight_bit_width import MinimizeWeightBitWidth def verify_step( model: ModelWrapper, diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index 468e660117..01d8c3b42b 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -358,7 +358,7 @@ def lut_estimation(self): alpha = math.log(MW, 2) + W + A - 1 - int(idt.signed()) acc_bits = min( acc_datatype.bitwidth(), - np.ceil(alpha + math.log(1 + pow(2, -alpha), 2) + 1) + np.ceil(alpha + math.log(1 + pow(2, -alpha), 2) + 1), ) acc_luts = acc_bits # thresholds and threshold comparators @@ -618,10 +618,14 @@ def minimize_accumulator_width(self, model): if min_threshold < acc_min: clip_lower = acc_min if (clip_lower is not None) or (clip_upper is not None): - warnings.warn("Clipping some thresholds in %s" % self.onnx_node.name) + warnings.warn( + "Clipping some thresholds in %s" % self.onnx_node.name + ) thresholds = np.clip(thresholds, clip_lower, clip_upper) model.set_initializer(self.onnx_node.input[2], thresholds) - threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds) + threshold_tensor = self.get_hls_compatible_threshold_tensor( + thresholds + ) min_threshold = thresholds.min() max_threshold = thresholds.max() # get range required by threshold values diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index 232053b0fa..fdf6a51c4c 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -133,10 +133,14 @@ def minimize_accumulator_width(self, model): if min_threshold < acc_min: clip_lower = acc_min if (clip_lower is not None) or (clip_upper is not None): - warnings.warn("Clipping some thresholds in %s" % self.onnx_node.name) + warnings.warn( + "Clipping some thresholds in %s" % self.onnx_node.name + ) thresholds = np.clip(thresholds, clip_lower, clip_upper) model.set_initializer(self.onnx_node.input[2], thresholds) - threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds) + threshold_tensor = self.get_hls_compatible_threshold_tensor( + thresholds + ) min_threshold = thresholds.min() max_threshold = thresholds.max() # get range required by threshold values @@ -1208,7 +1212,7 @@ def lut_estimation(self): alpha = math.log(k_h * k_w, 2) + W + A - 1 - int(idt.signed()) acc_bits = min( acc_datatype.bitwidth(), - np.ceil(alpha + math.log(1 + pow(2, -alpha), 2) + 1) + np.ceil(alpha + math.log(1 + pow(2, -alpha), 2) + 1), ) acc_luts = acc_bits # thresholds and threshold comparators diff --git a/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py b/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py index 3029e09d48..eaafebebf5 100644 --- a/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py +++ b/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py @@ -1128,7 +1128,8 @@ def apply(self, model): PE=pe, numSteps=thl_thres_shape[1], inputDataType=idt.name, - weightDataType=idt.name, # can be tightened by MinimizeAccumulatorWidth + # weightDataType can be tightened by MinimizeAccumulatorWidth + weightDataType=idt.name, outputDataType=odt.name, numInputVectors=list(thl_in_shape[:-1]), ActVal=actval, diff --git a/src/finn/transformation/fpgadataflow/minimize_weight_bit_width.py b/src/finn/transformation/fpgadataflow/minimize_weight_bit_width.py index 147f8281a7..32871cc44a 100644 --- a/src/finn/transformation/fpgadataflow/minimize_weight_bit_width.py +++ b/src/finn/transformation/fpgadataflow/minimize_weight_bit_width.py @@ -46,4 +46,4 @@ def apply(self, model): inst = getCustomOp(node) if hasattr(inst, "minimize_weight_bit_width"): inst.minimize_weight_bit_width(model) - return (model, False) \ No newline at end of file + return (model, False) diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index a627606f45..13635f88b0 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -78,6 +78,12 @@ from finn.transformation.fpgadataflow.insert_dwc import InsertDWC from finn.transformation.fpgadataflow.make_deployment import DeployToPYNQ from finn.transformation.fpgadataflow.make_pynq_driver import MakePYNQDriver +from finn.transformation.fpgadataflow.minimize_accumulator_width import ( + MinimizeAccumulatorWidth, +) +from finn.transformation.fpgadataflow.minimize_weight_bit_width import ( + MinimizeWeightBitWidth, +) from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode @@ -89,8 +95,6 @@ MakeMaxPoolNHWC, MoveScalarLinearPastInvariants, ) -from finn.transformation.fpgadataflow.minimize_accumulator_width import MinimizeAccumulatorWidth -from finn.transformation.fpgadataflow.minimize_weight_bit_width import MinimizeWeightBitWidth from finn.util.basic import get_finn_root from finn.util.gdrive import upload_to_end2end_dashboard from finn.util.pytorch import ToTensor From 8e84036e468d3abd0f08d8c84d353c16062c1a0e Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 22 Feb 2023 10:47:19 +0000 Subject: [PATCH 049/665] [Tests] Update export fct in end2end tests --- tests/end2end/test_end2end_bnn_pynq.py | 9 ++++----- tests/end2end/test_end2end_cybsec_mlp.py | 11 +++++------ tests/end2end/test_end2end_mobilenet_v1.py | 6 +++--- tests/fpgadataflow/test_fifosizing.py | 5 +++-- tests/fpgadataflow/test_split_large_fifos.py | 5 +++-- 5 files changed, 18 insertions(+), 18 deletions(-) diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index 858363d6d3..ccae0849fe 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -28,7 +28,6 @@ import pytest -import brevitas.onnx as bo import numpy as np # as of Feb'20 there is a bug that segfaults ONNX shape inference if we @@ -38,7 +37,7 @@ import subprocess import torch import warnings -from brevitas.export.onnx.generic.manager import BrevitasONNXManager +from brevitas.export import export_finn_onnx, export_qonnx from collections import OrderedDict from dataset_loading import cifar, mnist from datetime import datetime @@ -323,13 +322,13 @@ def test_export(self, topology, wbits, abits, QONNX_export): (model, ishape) = get_trained_network_and_ishape(topology, wbits, abits) chkpt_name = get_checkpoint_name(topology, wbits, abits, QONNX_export, "export") if QONNX_export: - BrevitasONNXManager.export(model, ishape, chkpt_name) + export_qonnx(model, torch.randn(ishape), chkpt_name) qonnx_cleanup(chkpt_name, out_file=chkpt_name) model = ModelWrapper(chkpt_name) model = model.transform(ConvertQONNXtoFINN()) model.save(chkpt_name) else: - bo.export_finn_onnx(model, ishape, chkpt_name) + export_finn_onnx(model, torch.randn(ishape), chkpt_name) nname = "%s_w%da%d" % (topology, wbits, abits) update_dashboard_data(topology, wbits, abits, "network", nname) dtstr = datetime.now().strftime("%Y-%m-%d %H:%M:%S") @@ -369,7 +368,7 @@ def test_add_pre_and_postproc(self, topology, wbits, abits, QONNX_export): chkpt_preproc_name = get_checkpoint_name( topology, wbits, abits, QONNX_export, "preproc" ) - bo.export_finn_onnx(totensor_pyt, ishape, chkpt_preproc_name) + export_finn_onnx(totensor_pyt, torch.randn(ishape), chkpt_preproc_name) assert os.path.isfile(chkpt_preproc_name) # join preprocessing and core model pre_model = ModelWrapper(chkpt_preproc_name) diff --git a/tests/end2end/test_end2end_cybsec_mlp.py b/tests/end2end/test_end2end_cybsec_mlp.py index 290afc3084..86942415b9 100644 --- a/tests/end2end/test_end2end_cybsec_mlp.py +++ b/tests/end2end/test_end2end_cybsec_mlp.py @@ -30,7 +30,6 @@ import pytest -import brevitas.onnx as bo import json import numpy as np import os @@ -40,7 +39,7 @@ import torch.nn as nn import wget from brevitas.core.quant import QuantType -from brevitas.export.onnx.generic.manager import BrevitasONNXManager +from brevitas.export import export_finn_onnx, export_qonnx from brevitas.nn import QuantIdentity, QuantLinear, QuantReLU from brevitas.quant_tensor import QuantTensor from qonnx.core.datatype import DataType @@ -133,10 +132,10 @@ def test_end2end_cybsec_mlp_export(QONNX_export): ) if QONNX_export: - # With the BrevitasONNXManager we need to manually set + # With the onnx export from Brevitas we need to manually set # the FINN DataType at the input - BrevitasONNXManager.export( - model_for_export, input_shape, export_path=export_onnx_path + export_qonnx( + model_for_export, torch.randn(input_shape), export_path=export_onnx_path ) model = ModelWrapper(export_onnx_path) model.set_tensor_datatype(model.graph.input[0].name, DataType["BIPOLAR"]) @@ -146,7 +145,7 @@ def test_end2end_cybsec_mlp_export(QONNX_export): model = model.transform(ConvertQONNXtoFINN()) model.save(export_onnx_path) else: - bo.export_finn_onnx( + export_finn_onnx( model_for_export, export_path=export_onnx_path, input_t=input_qt ) assert os.path.isfile(export_onnx_path) diff --git a/tests/end2end/test_end2end_mobilenet_v1.py b/tests/end2end/test_end2end_mobilenet_v1.py index 2f4df956ac..3a3c0fe237 100644 --- a/tests/end2end/test_end2end_mobilenet_v1.py +++ b/tests/end2end/test_end2end_mobilenet_v1.py @@ -27,11 +27,11 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import pytest -import brevitas.onnx as bo import numpy as np import os import time import torch +from brevitas.export import export_finn_onnx from PIL import Image from qonnx.core.datatype import DataType from qonnx.core.modelwrapper import ModelWrapper @@ -95,7 +95,7 @@ def test_end2end_mobilenet_export(): std = 0.226 ch = 3 preproc = NormalizePreProc(mean, std, ch) - bo.export_finn_onnx(preproc, (1, 3, 224, 224), preproc_onnx) + export_finn_onnx(preproc, torch.randn(1, 3, 224, 224), preproc_onnx) preproc_model = ModelWrapper(preproc_onnx) # set input finn datatype to UINT8 preproc_model.set_tensor_datatype( @@ -111,7 +111,7 @@ def test_end2end_mobilenet_export(): # export mobilenet finn_onnx = build_dir + "/end2end_mobilenet_export.onnx" mobilenet = get_test_model_trained("mobilenet", 4, 4) - bo.export_finn_onnx(mobilenet, (1, 3, 224, 224), finn_onnx) + export_finn_onnx(mobilenet, torch.randn(1, 3, 224, 224), finn_onnx) # calculate golden output with pytorch/brevitas and save as .npy # get single image as input and prepare image diff --git a/tests/fpgadataflow/test_fifosizing.py b/tests/fpgadataflow/test_fifosizing.py index 9399fbe394..922232c2c2 100644 --- a/tests/fpgadataflow/test_fifosizing.py +++ b/tests/fpgadataflow/test_fifosizing.py @@ -31,7 +31,8 @@ import json import shutil -from brevitas.export.onnx.generic.manager import BrevitasONNXManager +import torch +from brevitas.export import export_qonnx from qonnx.core.modelwrapper import ModelWrapper from qonnx.custom_op.registry import getCustomOp @@ -45,7 +46,7 @@ def fetch_test_model(topology, wbits=2, abits=2): tmp_output_dir = make_build_dir("build_fifosizing_%s_" % topology) (model, ishape) = get_trained_network_and_ishape(topology, wbits, abits) chkpt_name = tmp_output_dir + "/model.onnx" - BrevitasONNXManager.export(model, ishape, chkpt_name) + export_qonnx(model, torch.randn(ishape), chkpt_name) return tmp_output_dir diff --git a/tests/fpgadataflow/test_split_large_fifos.py b/tests/fpgadataflow/test_split_large_fifos.py index 85b4a2bfa8..0437d006cf 100644 --- a/tests/fpgadataflow/test_split_large_fifos.py +++ b/tests/fpgadataflow/test_split_large_fifos.py @@ -31,7 +31,8 @@ import json import shutil -from brevitas.export.onnx.generic.manager import BrevitasONNXManager +import torch +from brevitas.export import export_qonnx from qonnx.core.modelwrapper import ModelWrapper from qonnx.custom_op.registry import getCustomOp @@ -46,7 +47,7 @@ def fetch_test_model(topology, wbits=2, abits=2): tmp_output_dir = make_build_dir("build_fifosizing_%s_" % topology) (model, ishape) = get_trained_network_and_ishape(topology, wbits, abits) chkpt_name = tmp_output_dir + "/model.onnx" - BrevitasONNXManager.export(model, ishape, chkpt_name) + export_qonnx(model, torch.randn(ishape), chkpt_name) return tmp_output_dir From 285b9933410a0d2ef09315b69a33d3da5b11b893 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 22 Feb 2023 10:54:57 +0000 Subject: [PATCH 050/665] [Tests] Update export fct in brevitas export tests --- .../brevitas/test_brevitas_avg_pool_export.py | 9 ++- tests/brevitas/test_brevitas_cnv.py | 7 +-- tests/brevitas/test_brevitas_debug.py | 6 +- tests/brevitas/test_brevitas_fc.py | 7 +-- tests/brevitas/test_brevitas_mobilenet.py | 7 +-- ...revitas_non_scaled_quanthardtanh_export.py | 7 +-- tests/brevitas/test_brevitas_qconv2d.py | 7 +-- tests/brevitas/test_brevitas_qlinear.py | 7 +-- .../brevitas/test_brevitas_relu_act_export.py | 55 +++++++------------ .../test_brevitas_scaled_qhardtanh_export.py | 7 +-- .../test_brevitas_validate_mobilenet.py | 5 +- 11 files changed, 52 insertions(+), 72 deletions(-) diff --git a/tests/brevitas/test_brevitas_avg_pool_export.py b/tests/brevitas/test_brevitas_avg_pool_export.py index 669601ecb6..9c35910366 100644 --- a/tests/brevitas/test_brevitas_avg_pool_export.py +++ b/tests/brevitas/test_brevitas_avg_pool_export.py @@ -30,8 +30,7 @@ import numpy as np import os import torch -from brevitas.export import FINNManager -from brevitas.export.onnx.generic.manager import BrevitasONNXManager +from brevitas.export import export_finn_onnx, export_qonnx from brevitas.nn import QuantAvgPool2d from brevitas.quant_tensor import QuantTensor from qonnx.core.datatype import DataType @@ -97,14 +96,14 @@ def test_brevitas_avg_pool_export( # export if QONNX_export: - BrevitasONNXManager.export( + export_qonnx( quant_avgpool, export_path=export_onnx_path, input_t=input_quant_tensor, ) model = ModelWrapper(export_onnx_path) - # Statically set the additional inputs generated by the BrevitasONNXManager + # Statically set the additional inputs generated by the Brevitas ONNX export model.graph.input.remove(model.graph.input[3]) model.graph.input.remove(model.graph.input[2]) model.graph.input.remove(model.graph.input[1]) @@ -118,7 +117,7 @@ def test_brevitas_avg_pool_export( model = model.transform(ConvertQONNXtoFINN()) model.save(export_onnx_path) else: - FINNManager.export( + export_finn_onnx( quant_avgpool, export_path=export_onnx_path, input_t=input_quant_tensor ) model = ModelWrapper(export_onnx_path) diff --git a/tests/brevitas/test_brevitas_cnv.py b/tests/brevitas/test_brevitas_cnv.py index 62aab2e3c2..1a96815105 100644 --- a/tests/brevitas/test_brevitas_cnv.py +++ b/tests/brevitas/test_brevitas_cnv.py @@ -30,11 +30,10 @@ import pytest -import brevitas.onnx as bo import numpy as np import os import torch -from brevitas.export.onnx.generic.manager import BrevitasONNXManager +from brevitas.export import export_finn_onnx, export_qonnx from qonnx.core.modelwrapper import ModelWrapper from qonnx.transformation.fold_constants import FoldConstants from qonnx.transformation.general import GiveUniqueNodeNames, RemoveStaticGraphInputs @@ -58,13 +57,13 @@ def test_brevitas_cnv_export_exec(wbits, abits, QONNX_export): cnv = get_test_model_trained("CNV", wbits, abits) ishape = (1, 3, 32, 32) if QONNX_export: - BrevitasONNXManager.export(cnv, ishape, export_onnx_path) + export_qonnx(cnv, torch.randn(ishape), export_onnx_path) qonnx_cleanup(export_onnx_path, out_file=export_onnx_path) model = ModelWrapper(export_onnx_path) model = model.transform(ConvertQONNXtoFINN()) model.save(export_onnx_path) else: - bo.export_finn_onnx(cnv, ishape, export_onnx_path) + export_finn_onnx(cnv, torch.randn(ishape), export_onnx_path) model = ModelWrapper(export_onnx_path) model = model.transform(GiveUniqueNodeNames()) model = model.transform(InferShapes()) diff --git a/tests/brevitas/test_brevitas_debug.py b/tests/brevitas/test_brevitas_debug.py index 181d610fff..547c026e21 100644 --- a/tests/brevitas/test_brevitas_debug.py +++ b/tests/brevitas/test_brevitas_debug.py @@ -34,7 +34,7 @@ import onnx.numpy_helper as nph import os import torch -from brevitas.export.onnx.generic.manager import BrevitasONNXManager +from brevitas.export import export_finn_onnx, export_qonnx from pkgutil import get_data from qonnx.core.modelwrapper import ModelWrapper from qonnx.transformation.fold_constants import FoldConstants @@ -58,7 +58,7 @@ def test_brevitas_debug(QONNX_export, QONNX_FINN_conversion): ishape = (1, 1, 28, 28) if QONNX_export: dbg_hook = bo.enable_debug(fc, proxy_level=True) - BrevitasONNXManager.export(fc, ishape, finn_onnx) + export_qonnx(fc, torch.randn(ishape), finn_onnx) # DebugMarkers have the brevitas.onnx domain, so that needs adjusting model = ModelWrapper(finn_onnx) dbg_nodes = model.get_nodes_by_op_type("DebugMarker") @@ -72,7 +72,7 @@ def test_brevitas_debug(QONNX_export, QONNX_FINN_conversion): model.save(finn_onnx) else: dbg_hook = bo.enable_debug(fc) - bo.export_finn_onnx(fc, ishape, finn_onnx) + export_finn_onnx(fc, torch.randn(ishape), finn_onnx) model = ModelWrapper(finn_onnx) # DebugMarkers have the brevitas.onnx domain, so that needs adjusting # ToDo: We should probably have transformation pass, which does this diff --git a/tests/brevitas/test_brevitas_fc.py b/tests/brevitas/test_brevitas_fc.py index 211fdb629b..3aaa96f9a5 100644 --- a/tests/brevitas/test_brevitas_fc.py +++ b/tests/brevitas/test_brevitas_fc.py @@ -28,12 +28,11 @@ import pytest -import brevitas.onnx as bo import numpy as np import onnx import onnx.numpy_helper as nph import torch -from brevitas.export.onnx.generic.manager import BrevitasONNXManager +from brevitas.export import export_finn_onnx, export_qonnx from pkgutil import get_data from qonnx.core.modelwrapper import ModelWrapper from qonnx.transformation.fold_constants import FoldConstants @@ -68,13 +67,13 @@ def test_brevitas_fc_onnx_export_and_exec(size, wbits, abits, QONNX_export): fc = get_test_model_trained(size, wbits, abits) ishape = (1, 1, 28, 28) if QONNX_export: - BrevitasONNXManager.export(fc, ishape, finn_onnx) + export_qonnx(fc, torch.randn(ishape), finn_onnx) qonnx_cleanup(finn_onnx, out_file=finn_onnx) model = ModelWrapper(finn_onnx) model = model.transform(ConvertQONNXtoFINN()) model.save(finn_onnx) else: - bo.export_finn_onnx(fc, ishape, finn_onnx) + export_finn_onnx(fc, torch.randn(ishape), finn_onnx) model = ModelWrapper(finn_onnx) model = model.transform(InferShapes()) model = model.transform(FoldConstants()) diff --git a/tests/brevitas/test_brevitas_mobilenet.py b/tests/brevitas/test_brevitas_mobilenet.py index b1475b6f4e..c840524172 100644 --- a/tests/brevitas/test_brevitas_mobilenet.py +++ b/tests/brevitas/test_brevitas_mobilenet.py @@ -28,9 +28,9 @@ import pytest -import brevitas.onnx as bo import numpy as np import torch +from brevitas.export import export_finn_onnx from PIL import Image from qonnx.core.datatype import DataType from qonnx.core.modelwrapper import ModelWrapper @@ -54,7 +54,6 @@ @pytest.mark.brevitas_export -@pytest.mark.xfail def test_brevitas_mobilenet(): # get single image as input and prepare image img = Image.open(get_finn_root() + "/tests/brevitas/king_charles.jpg") @@ -76,7 +75,7 @@ def test_brevitas_mobilenet(): std = 0.226 ch = 3 preproc = NormalizePreProc(mean, std, ch) - bo.export_finn_onnx(preproc, (1, 3, 224, 224), preproc_onnx) + export_finn_onnx(preproc, torch.randn(1, 3, 224, 224), preproc_onnx) preproc_model = ModelWrapper(preproc_onnx) # set input finn datatype to UINT8 preproc_model.set_tensor_datatype( @@ -89,7 +88,7 @@ def test_brevitas_mobilenet(): finn_onnx = export_onnx_path + "/quant_mobilenet_v1_4b_exported.onnx" mobilenet = get_test_model_trained("mobilenet", 4, 4) - bo.export_finn_onnx(mobilenet, (1, 3, 224, 224), finn_onnx) + export_finn_onnx(mobilenet, torch.randn(1, 3, 224, 224), finn_onnx) # do forward pass in PyTorch/Brevitas input_tensor = preproc.forward(img_torch) diff --git a/tests/brevitas/test_brevitas_non_scaled_quanthardtanh_export.py b/tests/brevitas/test_brevitas_non_scaled_quanthardtanh_export.py index 5d70acb102..ad6a7e53de 100644 --- a/tests/brevitas/test_brevitas_non_scaled_quanthardtanh_export.py +++ b/tests/brevitas/test_brevitas_non_scaled_quanthardtanh_export.py @@ -28,7 +28,6 @@ import pytest -import brevitas.onnx as bo import numpy as np import onnx # noqa import os @@ -36,7 +35,7 @@ from brevitas.core.quant import QuantType from brevitas.core.restrict_val import RestrictValueType from brevitas.core.scaling import ScalingImplType -from brevitas.export.onnx.generic.manager import BrevitasONNXManager +from brevitas.export import export_finn_onnx, export_qonnx from brevitas.nn import QuantHardTanh from qonnx.core.modelwrapper import ModelWrapper from qonnx.transformation.infer_shapes import InferShapes @@ -78,13 +77,13 @@ def get_quant_type(bit_width): ) if QONNX_export: m_path = export_onnx_path - BrevitasONNXManager.export(b_act, ishape, m_path) + export_qonnx(b_act, torch.randn(ishape), m_path) qonnx_cleanup(m_path, out_file=m_path) model = ModelWrapper(m_path) model = model.transform(ConvertQONNXtoFINN()) model.save(m_path) else: - bo.export_finn_onnx(b_act, ishape, export_onnx_path) + export_finn_onnx(b_act, torch.randn(ishape), export_onnx_path) model = ModelWrapper(export_onnx_path) model = model.transform(InferShapes()) inp_tensor = np.random.uniform(low=min_val, high=max_val, size=ishape).astype( diff --git a/tests/brevitas/test_brevitas_qconv2d.py b/tests/brevitas/test_brevitas_qconv2d.py index 214c55e5fd..faeb3ff48e 100644 --- a/tests/brevitas/test_brevitas_qconv2d.py +++ b/tests/brevitas/test_brevitas_qconv2d.py @@ -28,7 +28,6 @@ import pytest -import brevitas.onnx as bo import numpy as np import os import torch @@ -36,7 +35,7 @@ from brevitas.core.restrict_val import RestrictValueType from brevitas.core.scaling import ScalingImplType from brevitas.core.stats import StatsOp -from brevitas.export.onnx.generic.manager import BrevitasONNXManager +from brevitas.export import export_finn_onnx, export_qonnx from brevitas.nn import QuantConv2d from qonnx.core.datatype import DataType from qonnx.core.modelwrapper import ModelWrapper @@ -96,13 +95,13 @@ def test_brevitas_QConv2d(dw, bias, in_channels, QONNX_export): b_conv.eval() if QONNX_export: m_path = export_onnx_path - BrevitasONNXManager.export(b_conv, ishape, m_path) + export_qonnx(b_conv, torch.randn(ishape), m_path) qonnx_cleanup(m_path, out_file=m_path) model = ModelWrapper(m_path) model = model.transform(ConvertQONNXtoFINN()) model.save(m_path) else: - bo.export_finn_onnx(b_conv, ishape, export_onnx_path) + export_finn_onnx(b_conv, torch.randn(ishape), export_onnx_path) model = ModelWrapper(export_onnx_path) model = model.transform(InferShapes()) inp_tensor = np.random.uniform(low=-1.0, high=1.0, size=ishape).astype(np.float32) diff --git a/tests/brevitas/test_brevitas_qlinear.py b/tests/brevitas/test_brevitas_qlinear.py index bcd75a5455..1ad52fb5df 100644 --- a/tests/brevitas/test_brevitas_qlinear.py +++ b/tests/brevitas/test_brevitas_qlinear.py @@ -28,12 +28,11 @@ import pytest -import brevitas.onnx as bo import numpy as np import os import torch from brevitas.core.quant import QuantType -from brevitas.export.onnx.generic.manager import BrevitasONNXManager +from brevitas.export import export_finn_onnx, export_qonnx from brevitas.nn import QuantLinear from qonnx.core.datatype import DataType from qonnx.core.modelwrapper import ModelWrapper @@ -75,13 +74,13 @@ def test_brevitas_qlinear( b_linear.eval() if QONNX_export: m_path = export_onnx_path - BrevitasONNXManager.export(b_linear, i_shape, m_path) + export_qonnx(b_linear, torch.randn(i_shape), m_path) qonnx_cleanup(m_path, out_file=m_path) model = ModelWrapper(m_path) model = model.transform(ConvertQONNXtoFINN()) model.save(m_path) else: - bo.export_finn_onnx(b_linear, i_shape, export_onnx_path) + export_finn_onnx(b_linear, torch.randn(i_shape), export_onnx_path) model = ModelWrapper(export_onnx_path) model = model.transform(InferShapes()) inp_tensor = gen_finn_dt_tensor(i_dtype, i_shape) diff --git a/tests/brevitas/test_brevitas_relu_act_export.py b/tests/brevitas/test_brevitas_relu_act_export.py index 3dc46ec31e..1900763bdd 100644 --- a/tests/brevitas/test_brevitas_relu_act_export.py +++ b/tests/brevitas/test_brevitas_relu_act_export.py @@ -28,7 +28,6 @@ import pytest -import brevitas.onnx as bo import numpy as np import onnx # noqa import os @@ -36,7 +35,7 @@ from brevitas.core.quant import QuantType from brevitas.core.restrict_val import RestrictValueType from brevitas.core.scaling import ScalingImplType -from brevitas.export.onnx.generic.manager import BrevitasONNXManager +from brevitas.export import export_finn_onnx, export_qonnx from brevitas.nn import QuantReLU from qonnx.core.modelwrapper import ModelWrapper from qonnx.transformation.infer_shapes import InferShapes @@ -51,18 +50,16 @@ @pytest.mark.brevitas_export @pytest.mark.parametrize("abits", [2, 4, 8]) -@pytest.mark.parametrize("max_val", [1.0, 1.5, 1 - 2 ** (-7)]) @pytest.mark.parametrize( "scaling_impl_type", [ScalingImplType.CONST, ScalingImplType.PARAMETER] ) @pytest.mark.parametrize("QONNX_export", [False, True]) -def test_brevitas_act_export_relu(abits, max_val, scaling_impl_type, QONNX_export): - min_val = -1.0 +def test_brevitas_act_export_relu(abits, scaling_impl_type, QONNX_export): ishape = (1, 15) b_act = QuantReLU( bit_width=abits, - max_val=max_val, + max_val=6.0, scaling_impl_type=scaling_impl_type, restrict_scaling_type=RestrictValueType.LOG_FP, quant_type=QuantType.INT, @@ -79,18 +76,16 @@ def test_brevitas_act_export_relu(abits, max_val, scaling_impl_type, QONNX_expor b_act.load_state_dict(checkpoint) if QONNX_export: m_path = export_onnx_path - BrevitasONNXManager.export(b_act, ishape, m_path) + export_qonnx(b_act, torch.randn(ishape), m_path) qonnx_cleanup(m_path, out_file=m_path) model = ModelWrapper(m_path) model = model.transform(ConvertQONNXtoFINN()) model.save(m_path) else: - bo.export_finn_onnx(b_act, ishape, export_onnx_path) + export_finn_onnx(b_act, torch.randn(ishape), export_onnx_path) model = ModelWrapper(export_onnx_path) model = model.transform(InferShapes()) - inp_tensor = np.random.uniform(low=min_val, high=max_val, size=ishape).astype( - np.float32 - ) + inp_tensor = np.random.uniform(low=-1.0, high=6.0, size=ishape).astype(np.float32) idict = {model.graph.input[0].name: inp_tensor} odict = oxe.execute_onnx(model, idict, True) produced = odict[model.graph.output[0].name] @@ -98,7 +93,7 @@ def test_brevitas_act_export_relu(abits, max_val, scaling_impl_type, QONNX_expor b_act.eval() expected = b_act.forward(inp_tensor).detach().numpy() if not np.isclose(produced, expected, atol=1e-3).all(): - print(abits, max_val, scaling_impl_type) + print(abits, scaling_impl_type) print("scale: ", b_act.quant_act_scale().type(torch.FloatTensor).detach()) if abits < 5: print( @@ -115,27 +110,25 @@ def test_brevitas_act_export_relu(abits, max_val, scaling_impl_type, QONNX_expor @pytest.mark.brevitas_export @pytest.mark.parametrize("abits", [2, 4, 8]) -@pytest.mark.parametrize("max_val", [1.0, 1.5, 1 - 2 ** (-7)]) -@pytest.mark.parametrize("scaling_per_channel", [True, False]) +@pytest.mark.parametrize("scaling_per_output_channel", [True, False]) @pytest.mark.parametrize("QONNX_export", [False, True]) def test_brevitas_act_export_relu_imagenet( - abits, max_val, scaling_per_channel, QONNX_export + abits, scaling_per_output_channel, QONNX_export ): out_channels = 32 ishape = (1, out_channels, 1, 1) - min_val = -1.0 b_act = QuantReLU( bit_width=abits, quant_type=QuantType.INT, scaling_impl_type=ScalingImplType.PARAMETER, - scaling_per_channel=scaling_per_channel, + scaling_per_output_channel=scaling_per_output_channel, restrict_scaling_type=RestrictValueType.LOG_FP, scaling_min_val=2e-16, max_val=6.0, return_quant_tensor=False, per_channel_broadcastable_shape=(1, out_channels, 1, 1), ) - if scaling_per_channel is True: + if scaling_per_output_channel is True: rand_tensor = (2) * torch.rand((1, out_channels, 1, 1)) else: rand_tensor = torch.tensor(1.2398) @@ -148,18 +141,16 @@ def test_brevitas_act_export_relu_imagenet( b_act.load_state_dict(checkpoint) if QONNX_export: m_path = export_onnx_path - BrevitasONNXManager.export(b_act, ishape, m_path) + export_qonnx(b_act, torch.randn(ishape), m_path) qonnx_cleanup(m_path, out_file=m_path) model = ModelWrapper(m_path) model = model.transform(ConvertQONNXtoFINN()) model.save(m_path) else: - bo.export_finn_onnx(b_act, ishape, export_onnx_path) + export_finn_onnx(b_act, torch.randn(ishape), export_onnx_path) model = ModelWrapper(export_onnx_path) model = model.transform(InferShapes()) - inp_tensor = np.random.uniform(low=min_val, high=max_val, size=ishape).astype( - np.float32 - ) + inp_tensor = np.random.uniform(low=-1.0, high=6.0, size=ishape).astype(np.float32) idict = {model.graph.input[0].name: inp_tensor} odict = oxe.execute_onnx(model, idict, True) produced = odict[model.graph.output[0].name] @@ -167,7 +158,7 @@ def test_brevitas_act_export_relu_imagenet( b_act.eval() expected = b_act.forward(inp_tensor).detach().numpy() if not np.isclose(produced, expected, atol=1e-3).all(): - print(abits, max_val) + print(abits) print("scale: ", b_act.quant_act_scale().type(torch.FloatTensor).detach()) if abits < 5: print( @@ -190,7 +181,7 @@ def __init__(self, abits): bit_width=abits, quant_type=QuantType.INT, scaling_impl_type=ScalingImplType.PARAMETER, - scaling_per_channel=True, + scaling_per_output_channel=True, restrict_scaling_type=RestrictValueType.LOG_FP, scaling_min_val=2e-16, max_val=6.0, @@ -208,15 +199,13 @@ def forward(self, x): @pytest.mark.brevitas_export @pytest.mark.parametrize("abits", [2, 4, 8]) -@pytest.mark.parametrize("max_val", [1.0, 1.5, 1 - 2 ** (-7)]) -@pytest.mark.parametrize("scaling_per_channel", [True]) +@pytest.mark.parametrize("scaling_per_output_channel", [True]) @pytest.mark.parametrize("QONNX_export", [True]) def test_brevitas_act_export_relu_forking( - abits, max_val, scaling_per_channel, QONNX_export + abits, scaling_per_output_channel, QONNX_export ): out_channels = 32 ishape = (1, out_channels, 1, 1) - min_val = -1.0 model_pyt = PyTorchTestModel(abits) rand_tensor = (2) * torch.rand((1, out_channels, 1, 1)) @@ -229,7 +218,7 @@ def test_brevitas_act_export_relu_forking( if QONNX_export: m_path = export_onnx_path - BrevitasONNXManager.export(model_pyt, ishape, m_path) + export_qonnx(model_pyt, torch.randn(ishape), m_path) qonnx_cleanup(m_path, out_file=m_path) model = ModelWrapper(m_path) model = model.transform(ConvertQONNXtoFINN()) @@ -237,9 +226,7 @@ def test_brevitas_act_export_relu_forking( model = ModelWrapper(export_onnx_path) model = model.transform(InferShapes()) - inp_tensor = np.random.uniform(low=min_val, high=max_val, size=ishape).astype( - np.float32 - ) + inp_tensor = np.random.uniform(low=-1.0, high=6.0, size=ishape).astype(np.float32) idict = {model.graph.input[0].name: inp_tensor} odict = oxe.execute_onnx(model, idict, True) produced = odict[model.graph.output[0].name] @@ -247,7 +234,7 @@ def test_brevitas_act_export_relu_forking( model_pyt.eval() expected = model_pyt.forward(inp_tensor).detach().numpy() if not np.isclose(produced, expected, atol=1e-3).all(): - print(abits, max_val) + print(abits) print("scale: ", model_pyt.quant_act_scale().type(torch.FloatTensor).detach()) if abits < 5: print( diff --git a/tests/brevitas/test_brevitas_scaled_qhardtanh_export.py b/tests/brevitas/test_brevitas_scaled_qhardtanh_export.py index 403d406105..d35cc8d2dd 100644 --- a/tests/brevitas/test_brevitas_scaled_qhardtanh_export.py +++ b/tests/brevitas/test_brevitas_scaled_qhardtanh_export.py @@ -28,7 +28,6 @@ import pytest -import brevitas.onnx as bo import numpy as np import onnx # noqa import os @@ -36,7 +35,7 @@ from brevitas.core.quant import QuantType from brevitas.core.restrict_val import RestrictValueType from brevitas.core.scaling import ScalingImplType -from brevitas.export.onnx.generic.manager import BrevitasONNXManager +from brevitas.export import export_finn_onnx, export_qonnx from brevitas.nn import QuantHardTanh from qonnx.core.modelwrapper import ModelWrapper from qonnx.transformation.infer_shapes import InferShapes @@ -91,13 +90,13 @@ def get_quant_type(bit_width): b_act.load_state_dict(checkpoint) if QONNX_export: m_path = export_onnx_path - BrevitasONNXManager.export(b_act, ishape, m_path) + export_qonnx(b_act, torch.randn(ishape), m_path) qonnx_cleanup(m_path, out_file=m_path) model = ModelWrapper(m_path) model = model.transform(ConvertQONNXtoFINN()) model.save(m_path) else: - bo.export_finn_onnx(b_act, ishape, export_onnx_path) + export_finn_onnx(b_act, torch.randn(ishape), export_onnx_path) model = ModelWrapper(export_onnx_path) model = model.transform(InferShapes()) inp_tensor = np.random.uniform(low=min_val, high=max_val, size=ishape).astype( diff --git a/tests/brevitas/test_brevitas_validate_mobilenet.py b/tests/brevitas/test_brevitas_validate_mobilenet.py index 55915838e8..20e8ddad50 100644 --- a/tests/brevitas/test_brevitas_validate_mobilenet.py +++ b/tests/brevitas/test_brevitas_validate_mobilenet.py @@ -35,6 +35,7 @@ import torch import torchvision.datasets as datasets import torchvision.transforms as transforms +from brevitas.export import export_finn_onnx from qonnx.core.modelwrapper import ModelWrapper from qonnx.transformation.fold_constants import FoldConstants from qonnx.transformation.general import ( @@ -113,7 +114,7 @@ def test_brevitas_compare_exported_mobilenet(): # export preprocessing preproc_onnx = export_onnx_path + "/quant_mobilenet_v1_4b_preproc.onnx" preproc = NormalizePreProc(mean, std, ch) - bo.export_finn_onnx(preproc, (1, 3, 224, 224), preproc_onnx) + export_finn_onnx(preproc, torch.randn(1, 3, 224, 224), preproc_onnx) preproc_model = ModelWrapper(preproc_onnx) preproc_model = preproc_model.transform(InferShapes()) preproc_model = preproc_model.transform(GiveUniqueNodeNames()) @@ -124,7 +125,7 @@ def test_brevitas_compare_exported_mobilenet(): mobilenet = get_test_model_trained("mobilenet", 4, 4) if debug_mode: dbg_hook = bo.enable_debug(mobilenet) - bo.export_finn_onnx(mobilenet, (1, 3, 224, 224), finn_onnx) + export_finn_onnx(mobilenet, torch.randn(1, 3, 224, 224), finn_onnx) model = ModelWrapper(finn_onnx) model = model.transform(InferShapes()) model = model.transform(FoldConstants()) From bfb966841221a427dae09f3252cdb5de55382335 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 22 Feb 2023 11:45:52 +0000 Subject: [PATCH 051/665] [Deps] Update finn-experimental --- fetch-repos.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fetch-repos.sh b/fetch-repos.sh index 6068d9fc4c..53d199d4d4 100755 --- a/fetch-repos.sh +++ b/fetch-repos.sh @@ -28,7 +28,7 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. QONNX_COMMIT="dd35a8ff49d7225a07ffceeebe25a6361df48349" -FINN_EXP_COMMIT="8e6cccda16a5adeaac8451f9236e2a24766e0a27" +FINN_EXP_COMMIT="0aa7e1c44b20cf085b6fe42cff360f0a832afd2c" BREVITAS_COMMIT="c65f9c13dc124971f14739349531bbcda5c2a4aa" PYVERILATOR_COMMIT="766e457465f5c0dd315490d7b9cc5d74f9a76f4f" CNPY_COMMIT="4e8810b1a8637695171ed346ce68f6984e585ef4" From 65822357a7dba4f917c852d5f08bdebc7dd22e9d Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 22 Feb 2023 12:12:28 +0000 Subject: [PATCH 052/665] [Deps] Update to qonnx v0.2.0 --- fetch-repos.sh | 2 +- src/finn/custom_op/fpgadataflow/addstreams_batch.py | 4 ++-- src/finn/custom_op/fpgadataflow/channelwise_op_batch.py | 4 ++-- src/finn/custom_op/fpgadataflow/checksum.py | 4 ++-- src/finn/custom_op/fpgadataflow/concat.py | 4 ++-- src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py | 4 ++-- .../custom_op/fpgadataflow/convolutioninputgenerator1d.py | 4 ++-- .../custom_op/fpgadataflow/convolutioninputgenerator_rtl.py | 4 ++-- src/finn/custom_op/fpgadataflow/downsampler.py | 4 ++-- src/finn/custom_op/fpgadataflow/duplicatestreams_batch.py | 4 ++-- src/finn/custom_op/fpgadataflow/eltwise.py | 4 ++-- src/finn/custom_op/fpgadataflow/fmpadding_batch.py | 4 ++-- src/finn/custom_op/fpgadataflow/fmpadding_rtl.py | 4 ++-- src/finn/custom_op/fpgadataflow/globalaccpool_batch.py | 4 ++-- src/finn/custom_op/fpgadataflow/hlscustomop.py | 4 ++-- src/finn/custom_op/fpgadataflow/iodma.py | 4 ++-- src/finn/custom_op/fpgadataflow/labelselect_batch.py | 4 ++-- src/finn/custom_op/fpgadataflow/lookup.py | 4 ++-- src/finn/custom_op/fpgadataflow/matrixvectoractivation.py | 4 ++-- src/finn/custom_op/fpgadataflow/streamingfifo.py | 4 ++-- src/finn/custom_op/fpgadataflow/thresholding_batch.py | 4 ++-- src/finn/custom_op/fpgadataflow/tlastmarker.py | 4 ++-- src/finn/custom_op/fpgadataflow/upsampler.py | 4 ++-- src/finn/custom_op/fpgadataflow/vectorvectoractivation.py | 4 ++-- 24 files changed, 47 insertions(+), 47 deletions(-) diff --git a/fetch-repos.sh b/fetch-repos.sh index f13037733e..9738ea153f 100755 --- a/fetch-repos.sh +++ b/fetch-repos.sh @@ -27,7 +27,7 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -QONNX_COMMIT="dd35a8ff49d7225a07ffceeebe25a6361df48349" +QONNX_COMMIT="d9ac34c638ccbdcd3b3f5cd236fe76d611b08f6a" FINN_EXP_COMMIT="9cbd2787b5160e2b44e0e8164a0df1457dbd5366" BREVITAS_COMMIT="c65f9c13dc124971f14739349531bbcda5c2a4aa" PYVERILATOR_COMMIT="766e457465f5c0dd315490d7b9cc5d74f9a76f4f" diff --git a/src/finn/custom_op/fpgadataflow/addstreams_batch.py b/src/finn/custom_op/fpgadataflow/addstreams_batch.py index cd0af6b3ab..af106d9c06 100644 --- a/src/finn/custom_op/fpgadataflow/addstreams_batch.py +++ b/src/finn/custom_op/fpgadataflow/addstreams_batch.py @@ -38,8 +38,8 @@ class AddStreams_Batch(HLSCustomOp): """Class that corresponds to finn-hlslib AddStreams_Batch function.""" - def __init__(self, onnx_node): - super().__init__(onnx_node) + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) def get_nodeattr_types(self): my_attrs = super().get_nodeattr_types() diff --git a/src/finn/custom_op/fpgadataflow/channelwise_op_batch.py b/src/finn/custom_op/fpgadataflow/channelwise_op_batch.py index 46adca680d..cde66f1ae2 100644 --- a/src/finn/custom_op/fpgadataflow/channelwise_op_batch.py +++ b/src/finn/custom_op/fpgadataflow/channelwise_op_batch.py @@ -85,8 +85,8 @@ class ChannelwiseOp_Batch(HLSCustomOp): including Add, Mul and multi-thresholding. """ - def __init__(self, onnx_node): - super().__init__(onnx_node) + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) self.decoupled_wrapper = templates.decoupled_wrapper def get_nodeattr_types(self): diff --git a/src/finn/custom_op/fpgadataflow/checksum.py b/src/finn/custom_op/fpgadataflow/checksum.py index c927c07df2..99646274fa 100644 --- a/src/finn/custom_op/fpgadataflow/checksum.py +++ b/src/finn/custom_op/fpgadataflow/checksum.py @@ -38,8 +38,8 @@ class CheckSum(HLSCustomOp): """Class that corresponds to custom_hls checksum function.""" - def __init__(self, onnx_node): - super().__init__(onnx_node) + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) def get_nodeattr_types(self): my_attrs = { diff --git a/src/finn/custom_op/fpgadataflow/concat.py b/src/finn/custom_op/fpgadataflow/concat.py index 4437bcd198..8b655b570d 100644 --- a/src/finn/custom_op/fpgadataflow/concat.py +++ b/src/finn/custom_op/fpgadataflow/concat.py @@ -39,8 +39,8 @@ class StreamingConcat(HLSCustomOp): """Streaming concatenation node with dynamically generated HLS. Only supports concatenating along the last axis.""" - def __init__(self, onnx_node): - super().__init__(onnx_node) + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) def get_nodeattr_types(self): my_attrs = { diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py index 1566445999..6cc9208bb8 100644 --- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py +++ b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py @@ -54,8 +54,8 @@ class ConvolutionInputGenerator(HLSCustomOp): attributes (e.g. depthwise or not, whether k % stride is 0) a different variant will be picked for the actual HLS implementation.""" - def __init__(self, onnx_node): - super().__init__(onnx_node) + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) def get_nodeattr_types(self): my_attrs = { diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator1d.py b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator1d.py index f1c84662cc..6e792ca585 100644 --- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator1d.py +++ b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator1d.py @@ -59,8 +59,8 @@ class ConvolutionInputGenerator1D(HLSCustomOp): attributes (e.g. depthwise or not, whether dilation is 0) a different variant will be picked for the actual HLS implementation.""" - def __init__(self, onnx_node): - super().__init__(onnx_node) + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) def get_nodeattr_types(self): my_attrs = { diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py index 1afd23d3a1..30861f0135 100755 --- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py +++ b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py @@ -60,8 +60,8 @@ class ConvolutionInputGenerator_rtl(HLSCustomOp): (sliding window) function variants. Generates an RTL ConvolutionInputGenerator implementation based on (System-)Verilog templates, defined in finn-rtllib/swg.""" - def __init__(self, onnx_node): - super().__init__(onnx_node) + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) def get_nodeattr_types(self): my_attrs = { diff --git a/src/finn/custom_op/fpgadataflow/downsampler.py b/src/finn/custom_op/fpgadataflow/downsampler.py index b7efaff440..255606ee7f 100644 --- a/src/finn/custom_op/fpgadataflow/downsampler.py +++ b/src/finn/custom_op/fpgadataflow/downsampler.py @@ -39,8 +39,8 @@ class DownSampler(HLSCustomOp): """Corresponds to finn-hlslib ConvolutionInputGenerator_*_kernel1 function. Basically performs a down sampling of the image removing rows and columns.""" - def __init__(self, onnx_node): - super().__init__(onnx_node) + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) def get_nodeattr_types(self): my_attrs = { diff --git a/src/finn/custom_op/fpgadataflow/duplicatestreams_batch.py b/src/finn/custom_op/fpgadataflow/duplicatestreams_batch.py index 93cde15ca7..312f5e7e4a 100644 --- a/src/finn/custom_op/fpgadataflow/duplicatestreams_batch.py +++ b/src/finn/custom_op/fpgadataflow/duplicatestreams_batch.py @@ -38,8 +38,8 @@ class DuplicateStreams_Batch(HLSCustomOp): """Class that corresponds to finn-hlslib function of the same name.""" - def __init__(self, onnx_node): - super().__init__(onnx_node) + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) def get_nodeattr_types(self): my_attrs = { diff --git a/src/finn/custom_op/fpgadataflow/eltwise.py b/src/finn/custom_op/fpgadataflow/eltwise.py index 68ed6546c7..c96f12f06b 100644 --- a/src/finn/custom_op/fpgadataflow/eltwise.py +++ b/src/finn/custom_op/fpgadataflow/eltwise.py @@ -38,8 +38,8 @@ class StreamingEltwise(HLSCustomOp): """Class that corresponds to finn-hlslib StreamingEltwise function.""" - def __init__(self, onnx_node): - super().__init__(onnx_node) + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) def get_nodeattr_types(self): diff --git a/src/finn/custom_op/fpgadataflow/fmpadding_batch.py b/src/finn/custom_op/fpgadataflow/fmpadding_batch.py index dfc55d283f..bdb5775c3e 100644 --- a/src/finn/custom_op/fpgadataflow/fmpadding_batch.py +++ b/src/finn/custom_op/fpgadataflow/fmpadding_batch.py @@ -39,8 +39,8 @@ class FMPadding_Batch(HLSCustomOp): """Corresponds to finn-hlslib FMPadding_Batch function. Pads input image by given amount.""" - def __init__(self, onnx_node): - super().__init__(onnx_node) + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) def get_nodeattr_types(self): my_attrs = { diff --git a/src/finn/custom_op/fpgadataflow/fmpadding_rtl.py b/src/finn/custom_op/fpgadataflow/fmpadding_rtl.py index 5650d21885..9c27503224 100644 --- a/src/finn/custom_op/fpgadataflow/fmpadding_rtl.py +++ b/src/finn/custom_op/fpgadataflow/fmpadding_rtl.py @@ -49,8 +49,8 @@ class FMPadding_rtl(HLSCustomOp): Supports adjusting the padding amount and spatial feature sizes at runtime.""" - def __init__(self, onnx_node): - super().__init__(onnx_node) + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) def get_nodeattr_types(self): my_attrs = { diff --git a/src/finn/custom_op/fpgadataflow/globalaccpool_batch.py b/src/finn/custom_op/fpgadataflow/globalaccpool_batch.py index e7fa5bc004..220856922c 100644 --- a/src/finn/custom_op/fpgadataflow/globalaccpool_batch.py +++ b/src/finn/custom_op/fpgadataflow/globalaccpool_batch.py @@ -38,8 +38,8 @@ class GlobalAccPool_Batch(HLSCustomOp): """Class that corresponds to finn-hlslib AccPool_Batch function.""" - def __init__(self, onnx_node): - super().__init__(onnx_node) + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) def get_nodeattr_types(self): my_attrs = { diff --git a/src/finn/custom_op/fpgadataflow/hlscustomop.py b/src/finn/custom_op/fpgadataflow/hlscustomop.py index d1326607aa..d5d0c9ea6e 100644 --- a/src/finn/custom_op/fpgadataflow/hlscustomop.py +++ b/src/finn/custom_op/fpgadataflow/hlscustomop.py @@ -59,8 +59,8 @@ class HLSCustomOp(CustomOp): custom node should have. Some as abstract methods, these have to be filled when writing a new fpgadataflow custom op node.""" - def __init__(self, onnx_node): - super().__init__(onnx_node) + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) self.code_gen_dict = {} diff --git a/src/finn/custom_op/fpgadataflow/iodma.py b/src/finn/custom_op/fpgadataflow/iodma.py index 65683079fc..8a756b630d 100644 --- a/src/finn/custom_op/fpgadataflow/iodma.py +++ b/src/finn/custom_op/fpgadataflow/iodma.py @@ -75,8 +75,8 @@ class IODMA(HLSCustomOp): """Class that corresponds to finn-hlslib DMA function(s).""" - def __init__(self, onnx_node): - super().__init__(onnx_node) + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) def get_nodeattr_types(self): my_attrs = { diff --git a/src/finn/custom_op/fpgadataflow/labelselect_batch.py b/src/finn/custom_op/fpgadataflow/labelselect_batch.py index 03f89bd7ec..492cd01073 100644 --- a/src/finn/custom_op/fpgadataflow/labelselect_batch.py +++ b/src/finn/custom_op/fpgadataflow/labelselect_batch.py @@ -39,8 +39,8 @@ class LabelSelect_Batch(HLSCustomOp): """Class that corresponds to finn-hlslib LabelSelect_Batch function.""" - def __init__(self, onnx_node): - super().__init__(onnx_node) + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) odt_name = self.get_nodeattr("outputDataType") if odt_name == "": # If not provided compute min size diff --git a/src/finn/custom_op/fpgadataflow/lookup.py b/src/finn/custom_op/fpgadataflow/lookup.py index fd3e2b5b1c..ed560ac962 100644 --- a/src/finn/custom_op/fpgadataflow/lookup.py +++ b/src/finn/custom_op/fpgadataflow/lookup.py @@ -44,8 +44,8 @@ class Lookup(HLSCustomOp): "Streaming elementwise HLS lookup, mapping indices to values." - def __init__(self, onnx_node): - super().__init__(onnx_node) + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) def get_nodeattr_types(self): my_attrs = { diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index 72128fda4c..27c44e3e65 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -60,8 +60,8 @@ class MatrixVectorActivation(HLSCustomOp): """Class that corresponds to finn-hls Matrix_Vector_Activate(_Stream)_Batch function.""" - def __init__(self, onnx_node): - super().__init__(onnx_node) + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) self.decoupled_wrapper = templates.decoupled_wrapper def get_nodeattr_types(self): diff --git a/src/finn/custom_op/fpgadataflow/streamingfifo.py b/src/finn/custom_op/fpgadataflow/streamingfifo.py index 522305327f..34b1940fa1 100644 --- a/src/finn/custom_op/fpgadataflow/streamingfifo.py +++ b/src/finn/custom_op/fpgadataflow/streamingfifo.py @@ -41,8 +41,8 @@ class StreamingFIFO(HLSCustomOp): - def __init__(self, onnx_node): - super().__init__(onnx_node) + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) self.strm_fifo_wrapper = templates.strm_fifo_wrapper def get_nodeattr_types(self): diff --git a/src/finn/custom_op/fpgadataflow/thresholding_batch.py b/src/finn/custom_op/fpgadataflow/thresholding_batch.py index d9745acf63..ce8c31ee9a 100644 --- a/src/finn/custom_op/fpgadataflow/thresholding_batch.py +++ b/src/finn/custom_op/fpgadataflow/thresholding_batch.py @@ -57,8 +57,8 @@ class Thresholding_Batch(HLSCustomOp): """Class that corresponds to finn-hls Thresholding_Batch function.""" - def __init__(self, onnx_node): - super().__init__(onnx_node) + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) self.decoupled_wrapper = templates.decoupled_wrapper def get_nodeattr_types(self): diff --git a/src/finn/custom_op/fpgadataflow/tlastmarker.py b/src/finn/custom_op/fpgadataflow/tlastmarker.py index 1bd32442a1..895a2eedab 100644 --- a/src/finn/custom_op/fpgadataflow/tlastmarker.py +++ b/src/finn/custom_op/fpgadataflow/tlastmarker.py @@ -37,8 +37,8 @@ class TLastMarker(HLSCustomOp): (needed by the FINN PYNQ shell) or at the beginning to remove the end-of-burst from DMA read.""" - def __init__(self, onnx_node): - super().__init__(onnx_node) + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) def get_nodeattr_types(self): my_attrs = { diff --git a/src/finn/custom_op/fpgadataflow/upsampler.py b/src/finn/custom_op/fpgadataflow/upsampler.py index a018fd35aa..b653b9386e 100644 --- a/src/finn/custom_op/fpgadataflow/upsampler.py +++ b/src/finn/custom_op/fpgadataflow/upsampler.py @@ -41,8 +41,8 @@ class UpsampleNearestNeighbour_Batch(HLSCustomOp): The layer expects square feature maps for the in and output. """ - def __init__(self, onnx_node): - super().__init__(onnx_node) + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) def get_nodeattr_types(self): my_attrs = { diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index d5e29ca22a..531dc75a5f 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -50,8 +50,8 @@ class VectorVectorActivation(HLSCustomOp): """Class that corresponds to finn-hlslib Vector_Vector_Activate_Batch function""" - def __init__(self, onnx_node): - super().__init__(onnx_node) + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) def get_nodeattr_types(self): my_attrs = { From 86ec96dce961cb0d15d2e24c6922a390271c4e57 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 22 Feb 2023 15:39:04 +0000 Subject: [PATCH 053/665] [Tests] Update res estimate test to match updated estimate fcts --- tests/fpgadataflow/test_fpgadataflow_res_estimate.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_res_estimate.py b/tests/fpgadataflow/test_fpgadataflow_res_estimate.py index b3cf7b4229..2ff7dd8b32 100644 --- a/tests/fpgadataflow/test_fpgadataflow_res_estimate.py +++ b/tests/fpgadataflow/test_fpgadataflow_res_estimate.py @@ -101,7 +101,7 @@ def test_res_estimate(): "MatrixVectorActivation_0": { "BRAM_18K": 0, "BRAM_efficiency": 1, - "LUT": 357, + "LUT": 317, "DSP": 0, "URAM_efficiency": 1, "URAM": 0, @@ -119,7 +119,7 @@ def test_res_estimate(): { "BRAM_18K": 0, "BRAM_efficiency": 1, - "LUT": 352, + "LUT": 313, "DSP": 1, "URAM": 0, "URAM_efficiency": 1, @@ -127,7 +127,7 @@ def test_res_estimate(): { "BRAM_18K": 0, "BRAM_efficiency": 1, - "LUT": 357, + "LUT": 317, "DSP": 0, "URAM": 0, "URAM_efficiency": 1, From 9249b668dd38cc8c59c10f6ccc022b79617a6390 Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Wed, 22 Feb 2023 15:41:01 +0000 Subject: [PATCH 054/665] remove unused dependency Signed-off-by: Fionn O'Donohoe --- requirements.txt | 1 - 1 file changed, 1 deletion(-) diff --git a/requirements.txt b/requirements.txt index 83aad07d72..6703c83d97 100644 --- a/requirements.txt +++ b/requirements.txt @@ -1,7 +1,6 @@ bitstring==3.1.7 clize==4.1.1 dataclasses-json==0.5.7 -docrep==0.2.7 gspread==3.6.0 numpy==1.22.0 onnx==1.13.0 From fd12de646969c58ceff2652fa72406d73b04a26a Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 22 Feb 2023 16:51:13 +0000 Subject: [PATCH 055/665] [Builder] Update lookup for builder steps --- src/finn/builder/build_dataflow_steps.py | 1 + 1 file changed, 1 insertion(+) diff --git a/src/finn/builder/build_dataflow_steps.py b/src/finn/builder/build_dataflow_steps.py index 857a1f6122..ba5a23f411 100644 --- a/src/finn/builder/build_dataflow_steps.py +++ b/src/finn/builder/build_dataflow_steps.py @@ -851,6 +851,7 @@ def step_deployment_package(model: ModelWrapper, cfg: DataflowBuildConfig): "step_create_dataflow_partition": step_create_dataflow_partition, "step_target_fps_parallelization": step_target_fps_parallelization, "step_apply_folding_config": step_apply_folding_config, + "step_minimize_bit_width": step_minimize_bit_width, "step_generate_estimate_reports": step_generate_estimate_reports, "step_hls_codegen": step_hls_codegen, "step_hls_ipgen": step_hls_ipgen, From 74ab5a3030f06163b576edc1c67ffef2b52e9073 Mon Sep 17 00:00:00 2001 From: auphelia Date: Thu, 23 Feb 2023 15:00:49 +0000 Subject: [PATCH 056/665] [Tests] Fix to validate top1 in bnn_pynq test --- tests/end2end/test_end2end_bnn_pynq.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index ccae0849fe..831c1a2f73 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -268,7 +268,7 @@ def measure_top1_accuracy(model_chkpt, dataset, parent_chkpt=None): raise Exception("Unrecognized dataset") # move from dataset_loader layout to ONNX layout: NHWC -> NCHW testx = testx.transpose(0, 3, 1, 2) - model = ModelWrapper(model_chkpt) + model = load_test_checkpoint_or_skip(model_chkpt) iname = model.graph.input[0].name oname = model.graph.output[0].name if parent_chkpt is None: From 3ebd6ee1a393769104dfa72d07543352a6bc4d6c Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 24 Feb 2023 15:50:54 +0000 Subject: [PATCH 057/665] Update finn-hlslib commit --- fetch-repos.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fetch-repos.sh b/fetch-repos.sh index 86a2176c75..1e01a058ff 100755 --- a/fetch-repos.sh +++ b/fetch-repos.sh @@ -32,7 +32,7 @@ FINN_EXP_COMMIT="0aa7e1c44b20cf085b6fe42cff360f0a832afd2c" BREVITAS_COMMIT="c65f9c13dc124971f14739349531bbcda5c2a4aa" PYVERILATOR_COMMIT="766e457465f5c0dd315490d7b9cc5d74f9a76f4f" CNPY_COMMIT="4e8810b1a8637695171ed346ce68f6984e585ef4" -HLSLIB_COMMIT="4ddfa00b07275a3f1de1c13409e6acb489115fe2" +HLSLIB_COMMIT="c17aa478ae574971d115afa9fa4d9c215857d1ac" OMX_COMMIT="d1065a788219ca0eb54d5e57600b1f9d7f67d4cc" AVNET_BDF_COMMIT="2d49cfc25766f07792c0b314489f21fe916b639b" XIL_BDF_COMMIT="8cf4bb674a919ac34e3d99d8d71a9e60af93d14e" From 0c239a5f9086601171d550819831a42bcbb74d97 Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 27 Feb 2023 12:02:55 +0000 Subject: [PATCH 058/665] [Tests] Re-enable decoupled tests for VVAU --- tests/fpgadataflow/test_fpgadataflow_vvau.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_vvau.py b/tests/fpgadataflow/test_fpgadataflow_vvau.py index bcbf4fb721..5ffbf81354 100644 --- a/tests/fpgadataflow/test_fpgadataflow_vvau.py +++ b/tests/fpgadataflow/test_fpgadataflow_vvau.py @@ -187,7 +187,7 @@ def prepare_inputs(input_tensor): # Number of input and output channels @pytest.mark.parametrize("channels", [6]) # memory mode -@pytest.mark.parametrize("mem_mode", ["const"]) +@pytest.mark.parametrize("mem_mode", ["const", "decoupled"]) # execution mode @pytest.mark.parametrize("exec_mode", ["cppsim", "rtlsim"]) @pytest.mark.fpgadataflow From 746d44d4d87649c44d52492751d6963c85a875b3 Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 27 Feb 2023 16:17:09 +0000 Subject: [PATCH 059/665] [CustomOp] Add assertion when pe or simd setting not valid --- .../fpgadataflow/vectorvectoractivation.py | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index 69275cfc5e..5d996e10d8 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -253,9 +253,6 @@ def get_output_datatype(self, ind=0): def get_instream_width(self, ind=0): i_bits = self.get_input_datatype().bitwidth() simd = self.get_nodeattr("SIMD") - # if simd > 1: - # pe = self.get_nodeattr("Channels") - # else: pe = self.get_nodeattr("PE") in_width = i_bits * simd * pe return in_width @@ -270,11 +267,13 @@ def get_folded_input_shape(self, ind=0): dim_h, dim_w = self.get_nodeattr("Dim") ch = self.get_nodeattr("Channels") simd = self.get_nodeattr("SIMD") - # if simd > 1: - # pe = self.get_nodeattr("Channels") - # else: pe = self.get_nodeattr("PE") - sf = k_h * k_w // simd + kernel_2 = k_h * k_w + assert ( + kernel_2 % simd == 0 + ), "Requirement kernel (k_h * k_w) divisable by SIMD is violated." + sf = kernel_2 // simd + assert ch % pe == 0, "Requirement Channels divisable by PE is violated." nf = ch // pe if ind == 0: From 9ccaed38b46d3e220d237a3394c78b62166d8e1e Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 27 Feb 2023 16:18:50 +0000 Subject: [PATCH 060/665] [Tests] Extend parameters for vvau testing --- tests/fpgadataflow/test_fpgadataflow_vvau.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_vvau.py b/tests/fpgadataflow/test_fpgadataflow_vvau.py index 5ffbf81354..be1ada59a1 100644 --- a/tests/fpgadataflow/test_fpgadataflow_vvau.py +++ b/tests/fpgadataflow/test_fpgadataflow_vvau.py @@ -180,12 +180,12 @@ def prepare_inputs(input_tensor): @pytest.mark.parametrize("simd", [1, 9]) # Input image shape @pytest.mark.parametrize("dim_h", [10]) -@pytest.mark.parametrize("dim_w", [10]) +@pytest.mark.parametrize("dim_w", [10, 1]) # Kernel shape @pytest.mark.parametrize("k_h", [3]) -@pytest.mark.parametrize("k_w", [3]) +@pytest.mark.parametrize("k_w", [3, 1]) # Number of input and output channels -@pytest.mark.parametrize("channels", [6]) +@pytest.mark.parametrize("channels", [3, 6]) # memory mode @pytest.mark.parametrize("mem_mode", ["const", "decoupled"]) # execution mode @@ -196,15 +196,15 @@ def prepare_inputs(input_tensor): def test_fpgadataflow_vvau( idt, wdt, act, pe, simd, dim_h, dim_w, k_h, k_w, channels, mem_mode, exec_mode ): - if pe == "channels": - pe = channels - if dim_w == 1 and k_w != 1: pytest.skip("1D image requires 1D kernel, skipping.") if channels % pe != 0: pytest.skip("Requirement Channels divisable by PE is violated.") + if (k_h * k_w) % simd != 0: + pytest.skip("Requirement kernel (k_h * k_w) divisable by SIMD is violated.") + # Generate weights in expected shape for ONNX and HLS node W = gen_finn_dt_tensor(wdt, (channels, 1, k_h, k_w)) # shape: [channels, 1, k, k] W_onnx = _infer_sparse_weight_tensor( From b8386edf55e631eb4416a83254c92c8f9c2b3174 Mon Sep 17 00:00:00 2001 From: icolbert Date: Mon, 27 Feb 2023 15:07:31 -0800 Subject: [PATCH 061/665] Update minimize_accumulator_width for MVAU If not runtime-writeable weights, then we can still minimize the accumulator bit width according to the data types. --- .../fpgadataflow/matrixvectoractivation.py | 142 ++++++++++-------- 1 file changed, 79 insertions(+), 63 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index 40f625093b..75aa587433 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -591,75 +591,91 @@ def get_hls_compatible_weight_tensor(self, orig_weight_matrix): def minimize_accumulator_width(self, model): """Minimize the accumulator bit width according to the weight values, input data types, and size of dot product""" - if not self.get_nodeattr("runtime_writeable_weights"): - weights = model.get_initializer(self.onnx_node.input[1]) - # since in the calculation the values of the weight matrix are used, - # for the bipolar case they need to be converted to bipolar - if self.get_nodeattr("binaryXnorMode"): - weights = 2 * weights - 1 - if len(self.onnx_node.input) > 2: - thresholds = model.get_initializer(self.onnx_node.input[2]) - else: - thresholds = None - idt = self.get_input_datatype() - # calculate minimum and maximum values of accumulator according to the - # weight values using the bounds derived in https://arxiv.org/abs/2301.13376 + weights = model.get_initializer(self.onnx_node.input[1]) + # since in the calculation the values of the weight matrix are used, + # for the bipolar case they need to be converted to bipolar + if self.get_nodeattr("binaryXnorMode"): + weights = 2 * weights - 1 + if len(self.onnx_node.input) > 2: + thresholds = model.get_initializer(self.onnx_node.input[2]) + else: + thresholds = None + idt = self.get_input_datatype() + # if runtime-writeable weights, then the values of the weights can + # change and we need to use the worst-case values from the datatypes + if self.get_nodeattr("runtime_writeable_weights"): + wdt = self.get_weight_datatype() + lower_worst = wdt.min() * np.ones_like(weights) + lower_range = calculate_matvec_accumulator_range(lower_worst, idt) + upper_worst = wdt.min() * np.ones_like(weights) + upper_range = calculate_matvec_accumulator_range(upper_worst, idt) + acc_min = min(min(lower_range), min(upper_range)) + acc_max = max(max(upper_range), max(upper_range)) + thresholds = None # range of thresholds are also runtime-writeable + # if not runtime-writeable weights, then we can calculate the min + # and max values of the accumulation range using knowledge of the + # weights and input data types since they are fixed + else: (acc_min, acc_max) = calculate_matvec_accumulator_range(weights, idt) - if thresholds is not None: - threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds) - # set threshold datatype (and accumulator datatype implicitly) + # if the thresholds can be used to determine range, then adjust the range + # according to the known values of the thresholds + if thresholds is not None: + threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds) + # set threshold datatype (and accumulator datatype implicitly) + min_threshold = thresholds.min() + max_threshold = thresholds.max() + # clip threshold values + clip_upper = None + clip_lower = None + if max_threshold > acc_max + 1: + clip_upper = acc_max + 1 + if min_threshold < acc_min: + clip_lower = acc_min + if (clip_lower is not None) or (clip_upper is not None): + warnings.warn( + "Clipping some thresholds in %s" % self.onnx_node.name + ) + thresholds = np.clip(thresholds, clip_lower, clip_upper) + model.set_initializer(self.onnx_node.input[2], thresholds) + threshold_tensor = self.get_hls_compatible_threshold_tensor( + thresholds + ) min_threshold = thresholds.min() max_threshold = thresholds.max() - # clip threshold values - clip_upper = None - clip_lower = None - if max_threshold > acc_max + 1: - clip_upper = acc_max + 1 - if min_threshold < acc_min: - clip_lower = acc_min - if (clip_lower is not None) or (clip_upper is not None): - warnings.warn( - "Clipping some thresholds in %s" % self.onnx_node.name - ) - thresholds = np.clip(thresholds, clip_lower, clip_upper) - model.set_initializer(self.onnx_node.input[2], thresholds) - threshold_tensor = self.get_hls_compatible_threshold_tensor( - thresholds - ) - min_threshold = thresholds.min() - max_threshold = thresholds.max() - # get range required by threshold values - tdt_min = min(acc_min, min_threshold) - tdt_max = max(acc_max, max_threshold) - if tdt_min < 0: - if abs(tdt_min) > tdt_max: - tdt = DataType.get_smallest_possible(tdt_min) - else: - tdt = DataType.get_smallest_possible(-tdt_max - 1) + # get range required by threshold values + tdt_min = min(acc_min, min_threshold) + tdt_max = max(acc_max, max_threshold) + if tdt_min < 0: + if abs(tdt_min) > tdt_max: + tdt = DataType.get_smallest_possible(tdt_min) else: - tdt = DataType.get_smallest_possible(tdt_max) - assert np.vectorize(tdt.allowed)( - threshold_tensor - ).all(), "Thresholds in %s can't be expressed with type %s" % ( - self.onnx_node.name, - str(tdt), - ) - self.set_nodeattr("accDataType", tdt.name) + tdt = DataType.get_smallest_possible(-tdt_max - 1) else: - if acc_min < 0: - if abs(acc_min) > acc_max: - adt = DataType.get_smallest_possible(acc_min) - else: - adt = DataType.get_smallest_possible(-acc_max - 1) + tdt = DataType.get_smallest_possible(tdt_max) + assert np.vectorize(tdt.allowed)( + threshold_tensor + ).all(), "Thresholds in %s can't be expressed with type %s" % ( + self.onnx_node.name, + str(tdt), + ) + adt = tdt # Set activation datatype to the threshold datatype + else: + if acc_min < 0: + if abs(acc_min) > acc_max: + adt = DataType.get_smallest_possible(acc_min) else: - adt = DataType.get_smallest_possible(acc_max) - # ensure a datatype divisible by 8-bits in case this is the last node - bw = roundup_to_integer_multiple(adt.bitwidth(), 8) - new_adt_name = adt.name.replace(str(adt.bitwidth()), str(bw)) - adt = DataType[new_adt_name] - self.set_nodeattr("accDataType", adt.name) - # for no-activation nodes, output dt = acc dt - self.set_nodeattr("outputDataType", adt.name) + adt = DataType.get_smallest_possible(-acc_max - 1) + else: + adt = DataType.get_smallest_possible(acc_max) + # if this is the last node in the graph, then ensure the datatype is + # divisibly by 8 bits + if model.find_direct_successors(self.onnx_node) is None: + bw = roundup_to_integer_multiple(adt.bitwidth(), 8) + new_adt_name = adt.name.replace(str(adt.bitwidth()), str(bw)) + adt = DataType[new_adt_name] + # for no-activation nodes, output dt = acc dt + self.set_nodeattr("outputDataType", adt.name) + self.set_nodeattr("accDataType", adt.name) return DataType[self.get_nodeattr("accDataType")] def minimize_weight_bit_width(self, model): From 7afc09862707074982f3e18da6e019c3614a9442 Mon Sep 17 00:00:00 2001 From: icolbert Date: Mon, 27 Feb 2023 15:09:37 -0800 Subject: [PATCH 062/665] Update minimize_accumulator_width for VVAU --- .../fpgadataflow/vectorvectoractivation.py | 146 ++++++++++-------- 1 file changed, 83 insertions(+), 63 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index 10ee30f89a..a580674836 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -106,75 +106,95 @@ def get_nodeattr_types(self): def minimize_accumulator_width(self, model): """Minimize the accumulator bit width according to the weight values, input data types, and size of dot product""" - if not self.get_nodeattr("runtime_writeable_weights"): - weights = model.get_initializer(self.onnx_node.input[1]) - k_h, k_w = self.get_nodeattr("Kernel") - fm = self.get_nodeattr("Channels") - # put weights into the shape expected by calculate_matvec_accumulator_range - weights = weights.reshape(fm, k_h * k_w).transpose() - if len(self.onnx_node.input) > 2: - thresholds = model.get_initializer(self.onnx_node.input[2]) - else: - thresholds = None - idt = self.get_input_datatype() - # calculate minimum and maximum values of accumulator according to the - # weight values using the bounds derived in https://arxiv.org/abs/2301.13376 + weights = model.get_initializer(self.onnx_node.input[1]) + k_h, k_w = self.get_nodeattr("Kernel") + fm = self.get_nodeattr("Channels") + # put weights into the shape expected by calculate_matvec_accumulator_range + weights = weights.reshape(fm, k_h * k_w).transpose() + # since in the calculation the values of the weight matrix are used, + # for the bipolar case they need to be converted to bipolar + if self.get_nodeattr("binaryXnorMode"): + weights = 2 * weights - 1 + if len(self.onnx_node.input) > 2: + thresholds = model.get_initializer(self.onnx_node.input[2]) + else: + thresholds = None + idt = self.get_input_datatype() + # if runtime-writeable weights, then the values of the weights can + # change and we need to use the worst-case values from the datatypes + if self.get_nodeattr("runtime_writeable_weights"): + wdt = self.get_weight_datatype() + lower_worst = wdt.min() * np.ones_like(weights) + lower_range = calculate_matvec_accumulator_range(lower_worst, idt) + upper_worst = wdt.min() * np.ones_like(weights) + upper_range = calculate_matvec_accumulator_range(upper_worst, idt) + acc_min = min(min(lower_range), min(upper_range)) + acc_max = max(max(upper_range), max(upper_range)) + thresholds = None # range of thresholds are also runtime-writeable + # if not runtime-writeable weights, then we can calculate the min + # and max values of the accumulation range using knowledge of the + # weights and input data types since they are fixed + else: (acc_min, acc_max) = calculate_matvec_accumulator_range(weights, idt) - if thresholds is not None: - threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds) - # set threshold datatype (and accumulator datatype implicitly) + # if the thresholds can be used to determine range, then adjust the range + # according to the known values of the thresholds + if thresholds is not None: + threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds) + # set threshold datatype (and accumulator datatype implicitly) + min_threshold = thresholds.min() + max_threshold = thresholds.max() + # clip threshold values + clip_upper = None + clip_lower = None + if max_threshold > acc_max + 1: + clip_upper = acc_max + 1 + if min_threshold < acc_min: + clip_lower = acc_min + if (clip_lower is not None) or (clip_upper is not None): + warnings.warn( + "Clipping some thresholds in %s" % self.onnx_node.name + ) + thresholds = np.clip(thresholds, clip_lower, clip_upper) + model.set_initializer(self.onnx_node.input[2], thresholds) + threshold_tensor = self.get_hls_compatible_threshold_tensor( + thresholds + ) min_threshold = thresholds.min() max_threshold = thresholds.max() - # clip threshold values - clip_upper = None - clip_lower = None - if max_threshold > acc_max + 1: - clip_upper = acc_max + 1 - if min_threshold < acc_min: - clip_lower = acc_min - if (clip_lower is not None) or (clip_upper is not None): - warnings.warn( - "Clipping some thresholds in %s" % self.onnx_node.name - ) - thresholds = np.clip(thresholds, clip_lower, clip_upper) - model.set_initializer(self.onnx_node.input[2], thresholds) - threshold_tensor = self.get_hls_compatible_threshold_tensor( - thresholds - ) - min_threshold = thresholds.min() - max_threshold = thresholds.max() - # get range required by threshold values - tdt_min = min(acc_min, min_threshold) - tdt_max = max(acc_max, max_threshold) - if tdt_min < 0: - if abs(tdt_min) > tdt_max: - tdt = DataType.get_smallest_possible(tdt_min) - else: - tdt = DataType.get_smallest_possible(-tdt_max - 1) + # get range required by threshold values + tdt_min = min(acc_min, min_threshold) + tdt_max = max(acc_max, max_threshold) + if tdt_min < 0: + if abs(tdt_min) > tdt_max: + tdt = DataType.get_smallest_possible(tdt_min) else: - tdt = DataType.get_smallest_possible(tdt_max) - assert np.vectorize(tdt.allowed)( - threshold_tensor - ).all(), "Thresholds in %s can't be expressed with type %s" % ( - self.onnx_node.name, - str(tdt), - ) - self.set_nodeattr("accDataType", tdt.name) + tdt = DataType.get_smallest_possible(-tdt_max - 1) else: - if acc_min < 0: - if abs(acc_min) > acc_max: - adt = DataType.get_smallest_possible(acc_min) - else: - adt = DataType.get_smallest_possible(-acc_max - 1) + tdt = DataType.get_smallest_possible(tdt_max) + assert np.vectorize(tdt.allowed)( + threshold_tensor + ).all(), "Thresholds in %s can't be expressed with type %s" % ( + self.onnx_node.name, + str(tdt), + ) + adt = tdt # Set activation datatype to the threshold datatype + else: + if acc_min < 0: + if abs(acc_min) > acc_max: + adt = DataType.get_smallest_possible(acc_min) else: - adt = DataType.get_smallest_possible(acc_max) - # ensure a datatype divisible by 8-bits in case this is the last node - bw = roundup_to_integer_multiple(adt.bitwidth(), 8) - new_adt_name = adt.name.replace(str(adt.bitwidth()), str(bw)) - adt = DataType[new_adt_name] - self.set_nodeattr("accDataType", adt.name) - # for no-activation nodes, output dt = acc dt - self.set_nodeattr("outputDataType", adt.name) + adt = DataType.get_smallest_possible(-acc_max - 1) + else: + adt = DataType.get_smallest_possible(acc_max) + # if this is the last node in the graph, then ensure the datatype is + # divisibly by 8 bits + if model.find_direct_successors(self.onnx_node) is None: + bw = roundup_to_integer_multiple(adt.bitwidth(), 8) + new_adt_name = adt.name.replace(str(adt.bitwidth()), str(bw)) + adt = DataType[new_adt_name] + # for no-activation nodes, output dt = acc dt + self.set_nodeattr("outputDataType", adt.name) + self.set_nodeattr("accDataType", adt.name) return DataType[self.get_nodeattr("accDataType")] def minimize_weight_bit_width(self, model): From 1185b60fd5d40cdef41d70a15b2f6ed7a1f9052b Mon Sep 17 00:00:00 2001 From: icolbert Date: Mon, 27 Feb 2023 16:35:23 -0800 Subject: [PATCH 063/665] Creating test for MinimizeWeightBitWidth --- .../streamline/test_minimize_bit_width.py | 148 ++++++++++++++++++ 1 file changed, 148 insertions(+) create mode 100644 tests/transformation/streamline/test_minimize_bit_width.py diff --git a/tests/transformation/streamline/test_minimize_bit_width.py b/tests/transformation/streamline/test_minimize_bit_width.py new file mode 100644 index 0000000000..51dbe9cc7f --- /dev/null +++ b/tests/transformation/streamline/test_minimize_bit_width.py @@ -0,0 +1,148 @@ +# Copyright (C) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import pytest +from typing import Optional +from onnx import TensorProto, helper +from qonnx.core.datatype import DataType, IntType +from qonnx.core.modelwrapper import ModelWrapper +from qonnx.custom_op.registry import getCustomOp +from qonnx.util.basic import gen_finn_dt_tensor + +from finn.custom_op.fpgadataflow.vectorvectoractivation import VectorVectorActivation +from finn.custom_op.fpgadataflow.matrixvectoractivation import MatrixVectorActivation +from finn.transformation.fpgadataflow.minimize_weight_bit_width import MinimizeWeightBitWidth + + +def make_unit_test_model(wdt: DataType, idt: DataType, tdt: Optional[DataType] = None): + """Creates a toy finn-onnx model for unit testing. The VVAU-MVAU pair is based + on the first pair of MobileNetV1""" + inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, [1, 32, 32, 288]) + outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, [1, 32, 32, 64]) + layer1 = helper.make_node( + "VectorVectorActivation", + ["inp", "params0", "thresh"] if tdt is not None else ["inp", "params0"], + ["hid"], + domain="finn.custom_op.fpgadataflow", + backend="fpgadataflow", + PE=1, + Channels=32, + Dim=(32, 32), + Kernel=(3,3), + inputDataType=idt.name, + outputDataType=idt.name, + weightDataType=wdt.name, + noActivation=tdt.min() if tdt is not None else 0, + ActVal=0 if tdt is not None else 1, + ) + layer2 = helper.make_node( + "MatrixVectorActivation", + ["hid", "params1", "thresh"] if tdt is not None else ["hid", "params1"], + ["outp"], + domain="finn.custom_op.fpgadataflow", + backend="fpgadataflow", + MW=32, # matrix_width (num_inputs) + MH=64, # matrix_height (num_outputs) + SIMD=1, + PE=1, + inputDataType=idt.name, + outputDataType=idt.name, + weightDataType=wdt.name, + noActivation=tdt.min() if tdt is not None else 0, + ActVal=0 if tdt is not None else 1, + binaryXnorMode=0 + ) + graph = helper.make_graph( + nodes=[layer1, layer2], name="fclayer_graph", inputs=[inp], outputs=[outp] + ) + + model = helper.make_model(graph, producer_name="fclayer-model") + model = ModelWrapper(model) + + model.set_tensor_datatype("inp", idt) + model.set_tensor_datatype("outp", idt) + model.set_tensor_datatype("hid", idt) + model.set_tensor_datatype("params0", wdt) + model.set_tensor_datatype("params1", wdt) + model.set_initializer("params0", + gen_finn_dt_tensor(wdt, (32, 1, 3, 3)) + ) + model.set_initializer("params1", + gen_finn_dt_tensor(wdt, (32, 64)) + ) + if tdt is not None: + model.set_tensor_datatype("thresh", tdt) + # model.set_initializer("thresh", thresholds) + return model + + +weight_data_types = [ + DataType['INT8'], + DataType['UINT8'], + DataType['INT7'], + DataType['UINT7'], + DataType['INT3'], + DataType['UINT3'], + DataType["BIPOLAR"], + DataType["TERNARY"], +] + +@pytest.mark.parametrize("wdt", weight_data_types) +@pytest.mark.parametrize("rww", [True, False]) +def test_minimize_weight_bit_width(wdt: DataType, rww: bool): + """Testing MinimizeWeightBitWidth for VVAU and MVAU. + + :param wdt: (DataType) The data type that we are testing for the weights + :param rww: (bool) Whether or not to use runtime-writeable weights""" + + # Create a w8a8 model + def_wdt = DataType['UINT8'] + model = make_unit_test_model(def_wdt, DataType['INT8']) + + # Create new weights for the model based on wdt + params0 = gen_finn_dt_tensor(wdt, (32, 1, 3, 3)) + params1 = gen_finn_dt_tensor(wdt, (32, 64)) + model.set_initializer("params0", params0) + model.set_initializer("params1", params1) + + # If runtime-writeable weights, specify as a node attribute + for node in model.graph.node: + inst = getCustomOp(node) + if isinstance(inst, (MatrixVectorActivation, VectorVectorActivation)): + inst.set_nodeattr("runtime_writeable_weights", int(rww)) + + # Apply the optimization + model = model.transform(MinimizeWeightBitWidth()) + + # Iterate through each node to make sure it functioned properly + for node in model.graph.node: + inst = getCustomOp(node) + if isinstance(inst, (MatrixVectorActivation, VectorVectorActivation)): + cur_wdt = DataType[inst.get_nodeattr("weightDataType")] + exp_wdt = def_wdt if rww else wdt + assert cur_wdt.bitwidth() == exp_wdt.bitwidth(), "Mismatched data types" From 68a6f3e166b11a4c541676c344f26fd7e0bfc72b Mon Sep 17 00:00:00 2001 From: icolbert Date: Mon, 27 Feb 2023 16:39:32 -0800 Subject: [PATCH 064/665] Removing bipolar weights for now --- tests/transformation/streamline/test_minimize_bit_width.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/transformation/streamline/test_minimize_bit_width.py b/tests/transformation/streamline/test_minimize_bit_width.py index 51dbe9cc7f..e25bf68d0d 100644 --- a/tests/transformation/streamline/test_minimize_bit_width.py +++ b/tests/transformation/streamline/test_minimize_bit_width.py @@ -108,7 +108,7 @@ def make_unit_test_model(wdt: DataType, idt: DataType, tdt: Optional[DataType] = DataType['UINT7'], DataType['INT3'], DataType['UINT3'], - DataType["BIPOLAR"], + # DataType["BIPOLAR"], # TODO - investigate bipolar weights DataType["TERNARY"], ] From 5fc807348074027306fa2189b4e0bb3f6ebd9397 Mon Sep 17 00:00:00 2001 From: icolbert Date: Mon, 27 Feb 2023 16:51:55 -0800 Subject: [PATCH 065/665] Adding test for MinimizeAccumulatorWidth --- .../streamline/test_minimize_bit_width.py | 54 +++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/tests/transformation/streamline/test_minimize_bit_width.py b/tests/transformation/streamline/test_minimize_bit_width.py index e25bf68d0d..658481cc6d 100644 --- a/tests/transformation/streamline/test_minimize_bit_width.py +++ b/tests/transformation/streamline/test_minimize_bit_width.py @@ -37,6 +37,7 @@ from finn.custom_op.fpgadataflow.vectorvectoractivation import VectorVectorActivation from finn.custom_op.fpgadataflow.matrixvectoractivation import MatrixVectorActivation from finn.transformation.fpgadataflow.minimize_weight_bit_width import MinimizeWeightBitWidth +from finn.transformation.fpgadataflow.minimize_accumulator_width import MinimizeAccumulatorWidth def make_unit_test_model(wdt: DataType, idt: DataType, tdt: Optional[DataType] = None): @@ -112,6 +113,17 @@ def make_unit_test_model(wdt: DataType, idt: DataType, tdt: Optional[DataType] = DataType["TERNARY"], ] + +input_data_types = [ + DataType['INT8'], + DataType['UINT8'], + DataType['INT3'], + DataType['UINT3'], + DataType["BIPOLAR"], + DataType["TERNARY"], +] + + @pytest.mark.parametrize("wdt", weight_data_types) @pytest.mark.parametrize("rww", [True, False]) def test_minimize_weight_bit_width(wdt: DataType, rww: bool): @@ -146,3 +158,45 @@ def test_minimize_weight_bit_width(wdt: DataType, rww: bool): cur_wdt = DataType[inst.get_nodeattr("weightDataType")] exp_wdt = def_wdt if rww else wdt assert cur_wdt.bitwidth() == exp_wdt.bitwidth(), "Mismatched data types" + + +@pytest.mark.parametrize("wdt", weight_data_types) +@pytest.mark.parametrize("adt", input_data_types) +@pytest.mark.parametrize("rww", [True, False]) +def test_minimize_weight_bit_width(wdt: DataType, idt:DataType, rww: bool): + """Testing MinimizeAccumulatorWidth for VVAU and MVAU. + + :param wdt: (DataType) The data type that we are testing for the weights + :param idt: (DataType) The data type that we are testing for the activations + :param rww: (bool) Whether or not to use runtime-writeable weights""" + + # Create uniform-precision model + # TODO: add thresholds (tdt) to unit tests + model = make_unit_test_model(wdt, idt) + def_adt = DataType["INT32"] + + # If runtime-writeable weights, specify as a node attribute + for node in model.graph.node: + inst = getCustomOp(node) + if isinstance(inst, (MatrixVectorActivation, VectorVectorActivation)): + inst.set_nodeattr("runtime_writeable_weights", int(rww)) + cur_adt = DataType[inst.get_nodeattr("accDataType")] + assert cur_adt.bitwidth() == def_adt.bitwidth(), "Default data type is incorrect" + + # Apply the optimization + model = model.transform(MinimizeAccumulatorWidth()) + + # Iterate through each node to make sure it functioned properly + for node in model.graph.node: + inst = getCustomOp(node) + if isinstance(inst, (MatrixVectorActivation, VectorVectorActivation)): + cur_adt = DataType[inst.get_nodeattr("accDataType")] + cur_odt = DataType[inst.get_nodeattr("accDataType")] + # TODO - figure out how to calculate expected accDataType + # exp_wdt = def_wdt if rww else wdt + # assert cur_adt.bitwidth() == exp_adt.bitwidth(), "Mismatched data types" + if model.find_direct_successors(inst.onnx_node) is None: + assert (cur_adt.bitwidth() % 8) == 0, "bit width of last node needs to be divisible by 8" + assert cur_adt.bitwidth() == cur_odt.bitwidth(), "outputDataType and accDataType should be equal" + else: + assert cur_adt.bitwidth() == idt.bitwidth(), "outputDataType should not be changed" \ No newline at end of file From 880f0f4f587c0fdf8e96890b730e09b2928871f4 Mon Sep 17 00:00:00 2001 From: icolbert Date: Mon, 27 Feb 2023 16:55:11 -0800 Subject: [PATCH 066/665] Fixing test_minimize_accumulator_width() --- .../transformation/streamline/test_minimize_bit_width.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tests/transformation/streamline/test_minimize_bit_width.py b/tests/transformation/streamline/test_minimize_bit_width.py index 658481cc6d..4995f45eba 100644 --- a/tests/transformation/streamline/test_minimize_bit_width.py +++ b/tests/transformation/streamline/test_minimize_bit_width.py @@ -161,9 +161,9 @@ def test_minimize_weight_bit_width(wdt: DataType, rww: bool): @pytest.mark.parametrize("wdt", weight_data_types) -@pytest.mark.parametrize("adt", input_data_types) +@pytest.mark.parametrize("idt", input_data_types) @pytest.mark.parametrize("rww", [True, False]) -def test_minimize_weight_bit_width(wdt: DataType, idt:DataType, rww: bool): +def test_minimize_accumulator_width(wdt: DataType, idt:DataType, rww: bool): """Testing MinimizeAccumulatorWidth for VVAU and MVAU. :param wdt: (DataType) The data type that we are testing for the weights @@ -191,7 +191,7 @@ def test_minimize_weight_bit_width(wdt: DataType, idt:DataType, rww: bool): inst = getCustomOp(node) if isinstance(inst, (MatrixVectorActivation, VectorVectorActivation)): cur_adt = DataType[inst.get_nodeattr("accDataType")] - cur_odt = DataType[inst.get_nodeattr("accDataType")] + cur_odt = DataType[inst.get_nodeattr("outputDataType")] # TODO - figure out how to calculate expected accDataType # exp_wdt = def_wdt if rww else wdt # assert cur_adt.bitwidth() == exp_adt.bitwidth(), "Mismatched data types" @@ -199,4 +199,4 @@ def test_minimize_weight_bit_width(wdt: DataType, idt:DataType, rww: bool): assert (cur_adt.bitwidth() % 8) == 0, "bit width of last node needs to be divisible by 8" assert cur_adt.bitwidth() == cur_odt.bitwidth(), "outputDataType and accDataType should be equal" else: - assert cur_adt.bitwidth() == idt.bitwidth(), "outputDataType should not be changed" \ No newline at end of file + assert cur_odt.bitwidth() == idt.bitwidth(), "outputDataType should not be changed" \ No newline at end of file From fc403fb8bc8673f7d0330ffad2c0d6123c38de74 Mon Sep 17 00:00:00 2001 From: icolbert Date: Mon, 27 Feb 2023 16:58:22 -0800 Subject: [PATCH 067/665] Fixing bug --- src/finn/custom_op/fpgadataflow/matrixvectoractivation.py | 2 +- src/finn/custom_op/fpgadataflow/vectorvectoractivation.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index 75aa587433..5f0fb2ede1 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -607,7 +607,7 @@ def minimize_accumulator_width(self, model): wdt = self.get_weight_datatype() lower_worst = wdt.min() * np.ones_like(weights) lower_range = calculate_matvec_accumulator_range(lower_worst, idt) - upper_worst = wdt.min() * np.ones_like(weights) + upper_worst = wdt.max() * np.ones_like(weights) upper_range = calculate_matvec_accumulator_range(upper_worst, idt) acc_min = min(min(lower_range), min(upper_range)) acc_max = max(max(upper_range), max(upper_range)) diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index a580674836..15cfdcfd37 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -126,7 +126,7 @@ def minimize_accumulator_width(self, model): wdt = self.get_weight_datatype() lower_worst = wdt.min() * np.ones_like(weights) lower_range = calculate_matvec_accumulator_range(lower_worst, idt) - upper_worst = wdt.min() * np.ones_like(weights) + upper_worst = wdt.max() * np.ones_like(weights) upper_range = calculate_matvec_accumulator_range(upper_worst, idt) acc_min = min(min(lower_range), min(upper_range)) acc_max = max(max(upper_range), max(upper_range)) From df856b45ff8d708d48f78b4c4bbc25a14b1e48e2 Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 28 Feb 2023 17:00:54 +0000 Subject: [PATCH 068/665] [Tests] Update ReLU export test --- .../brevitas/test_brevitas_relu_act_export.py | 180 ++---------------- 1 file changed, 13 insertions(+), 167 deletions(-) diff --git a/tests/brevitas/test_brevitas_relu_act_export.py b/tests/brevitas/test_brevitas_relu_act_export.py index 1900763bdd..6bff4ae800 100644 --- a/tests/brevitas/test_brevitas_relu_act_export.py +++ b/tests/brevitas/test_brevitas_relu_act_export.py @@ -33,14 +33,12 @@ import os import torch from brevitas.core.quant import QuantType -from brevitas.core.restrict_val import RestrictValueType from brevitas.core.scaling import ScalingImplType from brevitas.export import export_finn_onnx, export_qonnx from brevitas.nn import QuantReLU from qonnx.core.modelwrapper import ModelWrapper from qonnx.transformation.infer_shapes import InferShapes from qonnx.util.cleanup import cleanup as qonnx_cleanup -from torch import nn import finn.core.onnx_exec as oxe from finn.transformation.qonnx.convert_qonnx_to_finn import ConvertQONNXtoFINN @@ -50,95 +48,30 @@ @pytest.mark.brevitas_export @pytest.mark.parametrize("abits", [2, 4, 8]) +@pytest.mark.parametrize("ishape", [(1, 15), (1, 32, 1, 1)]) @pytest.mark.parametrize( - "scaling_impl_type", [ScalingImplType.CONST, ScalingImplType.PARAMETER] + "scaling_impl_type", [ScalingImplType.CONST] # , ScalingImplType.PARAMETER] ) +@pytest.mark.parametrize("scaling_per_output_channel", [True, False]) +@pytest.mark.parametrize("per_channel_broadcastable_shape", [None, (1, 32, 1, 1)]) @pytest.mark.parametrize("QONNX_export", [False, True]) -def test_brevitas_act_export_relu(abits, scaling_impl_type, QONNX_export): - ishape = (1, 15) +def test_brevitas_act_export_relu( + abits, + ishape, + scaling_impl_type, + scaling_per_output_channel, + per_channel_broadcastable_shape, + QONNX_export, +): b_act = QuantReLU( bit_width=abits, max_val=6.0, scaling_impl_type=scaling_impl_type, - restrict_scaling_type=RestrictValueType.LOG_FP, - quant_type=QuantType.INT, - ) - if scaling_impl_type == ScalingImplType.PARAMETER: - checkpoint = { - "act_quant_proxy.fused_activation_quant_proxy.tensor_quant.\ -scaling_impl.learned_value": torch.tensor( - 0.49 - ).type( - torch.FloatTensor - ) - } - b_act.load_state_dict(checkpoint) - if QONNX_export: - m_path = export_onnx_path - export_qonnx(b_act, torch.randn(ishape), m_path) - qonnx_cleanup(m_path, out_file=m_path) - model = ModelWrapper(m_path) - model = model.transform(ConvertQONNXtoFINN()) - model.save(m_path) - else: - export_finn_onnx(b_act, torch.randn(ishape), export_onnx_path) - model = ModelWrapper(export_onnx_path) - model = model.transform(InferShapes()) - inp_tensor = np.random.uniform(low=-1.0, high=6.0, size=ishape).astype(np.float32) - idict = {model.graph.input[0].name: inp_tensor} - odict = oxe.execute_onnx(model, idict, True) - produced = odict[model.graph.output[0].name] - inp_tensor = torch.from_numpy(inp_tensor).float() - b_act.eval() - expected = b_act.forward(inp_tensor).detach().numpy() - if not np.isclose(produced, expected, atol=1e-3).all(): - print(abits, scaling_impl_type) - print("scale: ", b_act.quant_act_scale().type(torch.FloatTensor).detach()) - if abits < 5: - print( - "thres:", - ", ".join(["{:8.4f}".format(x) for x in b_act.export_thres[0]]), - ) - print("input:", ", ".join(["{:8.4f}".format(x) for x in inp_tensor[0]])) - print("prod :", ", ".join(["{:8.4f}".format(x) for x in produced[0]])) - print("expec:", ", ".join(["{:8.4f}".format(x) for x in expected[0]])) - - assert np.isclose(produced, expected, atol=1e-3).all() - os.remove(export_onnx_path) - - -@pytest.mark.brevitas_export -@pytest.mark.parametrize("abits", [2, 4, 8]) -@pytest.mark.parametrize("scaling_per_output_channel", [True, False]) -@pytest.mark.parametrize("QONNX_export", [False, True]) -def test_brevitas_act_export_relu_imagenet( - abits, scaling_per_output_channel, QONNX_export -): - out_channels = 32 - ishape = (1, out_channels, 1, 1) - b_act = QuantReLU( - bit_width=abits, quant_type=QuantType.INT, - scaling_impl_type=ScalingImplType.PARAMETER, scaling_per_output_channel=scaling_per_output_channel, - restrict_scaling_type=RestrictValueType.LOG_FP, - scaling_min_val=2e-16, - max_val=6.0, - return_quant_tensor=False, - per_channel_broadcastable_shape=(1, out_channels, 1, 1), + per_channel_broadcastable_shape=per_channel_broadcastable_shape, ) - if scaling_per_output_channel is True: - rand_tensor = (2) * torch.rand((1, out_channels, 1, 1)) - else: - rand_tensor = torch.tensor(1.2398) - checkpoint = { - "act_quant_proxy.fused_activation_quant_proxy.tensor_quant.\ -scaling_impl.learned_value": rand_tensor.type( - torch.FloatTensor - ) - } - b_act.load_state_dict(checkpoint) if QONNX_export: m_path = export_onnx_path export_qonnx(b_act, torch.randn(ishape), m_path) @@ -157,93 +90,6 @@ def test_brevitas_act_export_relu_imagenet( inp_tensor = torch.from_numpy(inp_tensor).float() b_act.eval() expected = b_act.forward(inp_tensor).detach().numpy() - if not np.isclose(produced, expected, atol=1e-3).all(): - print(abits) - print("scale: ", b_act.quant_act_scale().type(torch.FloatTensor).detach()) - if abits < 5: - print( - "thres:", - ", ".join(["{:8.4f}".format(x) for x in b_act.export_thres[0]]), - ) - print("input:", ", ".join(["{:8.4f}".format(x) for x in inp_tensor[0]])) - print("prod :", ", ".join(["{:8.4f}".format(x) for x in produced[0]])) - print("expec:", ", ".join(["{:8.4f}".format(x) for x in expected[0]])) - - assert np.isclose(produced, expected, atol=1e-3).all() - os.remove(export_onnx_path) - - -class PyTorchTestModel(nn.Module): - def __init__(self, abits): - super(PyTorchTestModel, self).__init__() - out_channels = 32 - self.b_act = QuantReLU( - bit_width=abits, - quant_type=QuantType.INT, - scaling_impl_type=ScalingImplType.PARAMETER, - scaling_per_output_channel=True, - restrict_scaling_type=RestrictValueType.LOG_FP, - scaling_min_val=2e-16, - max_val=6.0, - return_quant_tensor=False, - per_channel_broadcastable_shape=(1, out_channels, 1, 1), - ) - - def forward(self, x): - act_out = self.b_act(x) - y0 = act_out * 2.0 - y1 = act_out * -1.0 - y = y0 + y1 - return y - - -@pytest.mark.brevitas_export -@pytest.mark.parametrize("abits", [2, 4, 8]) -@pytest.mark.parametrize("scaling_per_output_channel", [True]) -@pytest.mark.parametrize("QONNX_export", [True]) -def test_brevitas_act_export_relu_forking( - abits, scaling_per_output_channel, QONNX_export -): - out_channels = 32 - ishape = (1, out_channels, 1, 1) - model_pyt = PyTorchTestModel(abits) - - rand_tensor = (2) * torch.rand((1, out_channels, 1, 1)) - - checkpoint = { - "b_act.act_quant_proxy.fused_activation_quant_proxy." - "tensor_quant.scaling_impl.learned_value": rand_tensor.type(torch.FloatTensor) - } - model_pyt.load_state_dict(checkpoint) - - if QONNX_export: - m_path = export_onnx_path - export_qonnx(model_pyt, torch.randn(ishape), m_path) - qonnx_cleanup(m_path, out_file=m_path) - model = ModelWrapper(m_path) - model = model.transform(ConvertQONNXtoFINN()) - model.save(m_path) - - model = ModelWrapper(export_onnx_path) - model = model.transform(InferShapes()) - inp_tensor = np.random.uniform(low=-1.0, high=6.0, size=ishape).astype(np.float32) - idict = {model.graph.input[0].name: inp_tensor} - odict = oxe.execute_onnx(model, idict, True) - produced = odict[model.graph.output[0].name] - inp_tensor = torch.from_numpy(inp_tensor).float() - model_pyt.eval() - expected = model_pyt.forward(inp_tensor).detach().numpy() - if not np.isclose(produced, expected, atol=1e-3).all(): - print(abits) - print("scale: ", model_pyt.quant_act_scale().type(torch.FloatTensor).detach()) - if abits < 5: - print( - "thres:", - ", ".join(["{:8.4f}".format(x) for x in model_pyt.export_thres[0]]), - ) - print("input:", ", ".join(["{:8.4f}".format(x) for x in inp_tensor[0]])) - print("prod :", ", ".join(["{:8.4f}".format(x) for x in produced[0]])) - print("expec:", ", ".join(["{:8.4f}".format(x) for x in expected[0]])) assert np.isclose(produced, expected, atol=1e-3).all() os.remove(export_onnx_path) From 72798e10c1091d7139d8c725fb5e92199f447223 Mon Sep 17 00:00:00 2001 From: icolbert Date: Tue, 28 Feb 2023 15:48:52 -0800 Subject: [PATCH 069/665] Removing manual override of thresholds --- src/finn/custom_op/fpgadataflow/matrixvectoractivation.py | 1 - src/finn/custom_op/fpgadataflow/vectorvectoractivation.py | 1 - 2 files changed, 2 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index 5f0fb2ede1..39fd16d456 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -611,7 +611,6 @@ def minimize_accumulator_width(self, model): upper_range = calculate_matvec_accumulator_range(upper_worst, idt) acc_min = min(min(lower_range), min(upper_range)) acc_max = max(max(upper_range), max(upper_range)) - thresholds = None # range of thresholds are also runtime-writeable # if not runtime-writeable weights, then we can calculate the min # and max values of the accumulation range using knowledge of the # weights and input data types since they are fixed diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index 15cfdcfd37..8fac0942e9 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -130,7 +130,6 @@ def minimize_accumulator_width(self, model): upper_range = calculate_matvec_accumulator_range(upper_worst, idt) acc_min = min(min(lower_range), min(upper_range)) acc_max = max(max(upper_range), max(upper_range)) - thresholds = None # range of thresholds are also runtime-writeable # if not runtime-writeable weights, then we can calculate the min # and max values of the accumulation range using knowledge of the # weights and input data types since they are fixed From fcfeb026c1408f0c3203b181023b4ad150c3f171 Mon Sep 17 00:00:00 2001 From: icolbert Date: Tue, 28 Feb 2023 16:19:51 -0800 Subject: [PATCH 070/665] Updating checks in minimize_accumulator_width --- .../streamline/test_minimize_bit_width.py | 74 +++++++++++++++++-- 1 file changed, 68 insertions(+), 6 deletions(-) diff --git a/tests/transformation/streamline/test_minimize_bit_width.py b/tests/transformation/streamline/test_minimize_bit_width.py index 4995f45eba..221be75da7 100644 --- a/tests/transformation/streamline/test_minimize_bit_width.py +++ b/tests/transformation/streamline/test_minimize_bit_width.py @@ -27,12 +27,16 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import pytest -from typing import Optional +import numpy as np +from typing import Optional, Union from onnx import TensorProto, helper from qonnx.core.datatype import DataType, IntType from qonnx.core.modelwrapper import ModelWrapper from qonnx.custom_op.registry import getCustomOp -from qonnx.util.basic import gen_finn_dt_tensor +from qonnx.util.basic import ( + gen_finn_dt_tensor, + roundup_to_integer_multiple +) from finn.custom_op.fpgadataflow.vectorvectoractivation import VectorVectorActivation from finn.custom_op.fpgadataflow.matrixvectoractivation import MatrixVectorActivation @@ -109,7 +113,9 @@ def make_unit_test_model(wdt: DataType, idt: DataType, tdt: Optional[DataType] = DataType['UINT7'], DataType['INT3'], DataType['UINT3'], - # DataType["BIPOLAR"], # TODO - investigate bipolar weights + # TODO - current MinimizeWeightBitWidth sets {-1,1} to INT2, need to check + # for 0 in weights to minimize weight bit width to bipolar + # DataType["BIPOLAR"], DataType["TERNARY"], ] @@ -160,6 +166,57 @@ def test_minimize_weight_bit_width(wdt: DataType, rww: bool): assert cur_wdt.bitwidth() == exp_wdt.bitwidth(), "Mismatched data types" +def calculate_accumulator_bit_width( + inst: Union[MatrixVectorActivation, VectorVectorActivation], + model: ModelWrapper + ) -> Union[DataType, IntType]: + """Calculate the accumulator bit width use the closed-form expressions + derived in `Quantized Neural Networks for Low-Precision Accumulation + with Guaranteed Overflow Avoidance` (2023) by I.Colbert, A. Pappalardo, + J. Petri-Koenig + + :param inst: (HLSCustomOp) The instance of the MVAU or VVAU + :param model: (ModelWrapper) The instance of the whole model + """ + def phi(x: float) -> float: + return np.log2(1 + pow(2, -x)) + + weights = model.get_initializer(inst.onnx_node.input[1]) + # since in the calculation the values of the weight matrix are used, + # for the bipolar case they need to be converted to bipolar + if inst.get_nodeattr("binaryXnorMode"): + weights = 2 * weights - 1 + # modify the weights based on if the node is a VVAU or MVAU + if isinstance(inst, MatrixVectorActivation): + K = inst.get_nodeattr("MW") # matrix_width = num_inputs + elif isinstance(inst, VectorVectorActivation): + k_h, k_w = inst.get_nodeattr("Kernel") + K = k_h * k_w # size of kernels = num_inputs + fm = inst.get_nodeattr("Channels") + # put weights into the shape expected by calculate_matvec_accumulator_range + weights = weights.reshape(fm, k_h * k_w).transpose() + else: + raise Exception("Considering only MVAU and VVAU currently") + # collect attributes used to determine the accumulator bit width bound + wdt = inst.get_weight_datatype() + idt = inst.get_input_datatype() + rww = inst.get_nodeattr("runtime_writeable_weights") + # if runtime-writeable weights, then use the lower bound on the accumulator bit + # width as determined by the input and weight data types and size of dot product + if rww: + alpha = np.log2(K) + idt.bitwidth() + wdt.bitwidth() - 1. - float(idt.signed()) + P = np.ceil(alpha + phi(alpha) + 1.) + # if not runtime-writable weights, then use the tighter bound on the accumulator + # bit width as determined by the weight values themselves + else: + beta = np.log2(abs(weights).sum(axis=0).max()) + idt.bitwidth() - float(idt.signed()) + P = np.ceil(beta + phi(beta) + 1.) + # if the node is the last in the graph, then round up to the nearest 8 bits + if model.find_direct_successors(inst.onnx_node) is None: + P = roundup_to_integer_multiple(P, 8) + return DataType[f"INT{int(P)}"] + + @pytest.mark.parametrize("wdt", weight_data_types) @pytest.mark.parametrize("idt", input_data_types) @pytest.mark.parametrize("rww", [True, False]) @@ -169,6 +226,8 @@ def test_minimize_accumulator_width(wdt: DataType, idt:DataType, rww: bool): :param wdt: (DataType) The data type that we are testing for the weights :param idt: (DataType) The data type that we are testing for the activations :param rww: (bool) Whether or not to use runtime-writeable weights""" + if not wdt.signed(): + pytest.skip("Closed-form accumulator calculation is designed to consider only signed weights") # Create uniform-precision model # TODO: add thresholds (tdt) to unit tests @@ -192,9 +251,12 @@ def test_minimize_accumulator_width(wdt: DataType, idt:DataType, rww: bool): if isinstance(inst, (MatrixVectorActivation, VectorVectorActivation)): cur_adt = DataType[inst.get_nodeattr("accDataType")] cur_odt = DataType[inst.get_nodeattr("outputDataType")] - # TODO - figure out how to calculate expected accDataType - # exp_wdt = def_wdt if rww else wdt - # assert cur_adt.bitwidth() == exp_adt.bitwidth(), "Mismatched data types" + # Calculating expected accumulator bit width using a closed-form expression + # that is a slight over-approximation of the lower bound. The accumulator + # bit width minimization logic in the MVAU and VVAU is exact and should be + # less than or equal to this calculation + exp_adt = calculate_accumulator_bit_width(inst, model) + assert cur_adt.bitwidth() <= exp_adt.bitwidth(), "Mismatched accumulation data types" if model.find_direct_successors(inst.onnx_node) is None: assert (cur_adt.bitwidth() % 8) == 0, "bit width of last node needs to be divisible by 8" assert cur_adt.bitwidth() == cur_odt.bitwidth(), "outputDataType and accDataType should be equal" From 9a99b31141f372417914ed47b73d1ede1b287a02 Mon Sep 17 00:00:00 2001 From: icolbert Date: Tue, 28 Feb 2023 18:06:52 -0800 Subject: [PATCH 071/665] Adding threshold data types for accumulator width unit test --- .../streamline/test_minimize_bit_width.py | 37 +++++++++++++++---- 1 file changed, 29 insertions(+), 8 deletions(-) diff --git a/tests/transformation/streamline/test_minimize_bit_width.py b/tests/transformation/streamline/test_minimize_bit_width.py index 221be75da7..7cb866c6e8 100644 --- a/tests/transformation/streamline/test_minimize_bit_width.py +++ b/tests/transformation/streamline/test_minimize_bit_width.py @@ -51,7 +51,7 @@ def make_unit_test_model(wdt: DataType, idt: DataType, tdt: Optional[DataType] = outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, [1, 32, 32, 64]) layer1 = helper.make_node( "VectorVectorActivation", - ["inp", "params0", "thresh"] if tdt is not None else ["inp", "params0"], + ["inp", "params0", "thresh0"] if tdt is not None else ["inp", "params0"], ["hid"], domain="finn.custom_op.fpgadataflow", backend="fpgadataflow", @@ -67,7 +67,7 @@ def make_unit_test_model(wdt: DataType, idt: DataType, tdt: Optional[DataType] = ) layer2 = helper.make_node( "MatrixVectorActivation", - ["hid", "params1", "thresh"] if tdt is not None else ["hid", "params1"], + ["hid", "params1", "thresh1"] if tdt is not None else ["hid", "params1"], ["outp"], domain="finn.custom_op.fpgadataflow", backend="fpgadataflow", @@ -100,9 +100,21 @@ def make_unit_test_model(wdt: DataType, idt: DataType, tdt: Optional[DataType] = model.set_initializer("params1", gen_finn_dt_tensor(wdt, (32, 64)) ) + # if the threshold data type is specified, then we need to generate + # some dummy threshold values if tdt is not None: - model.set_tensor_datatype("thresh", tdt) - # model.set_initializer("thresh", thresholds) + model.set_tensor_datatype("thresh0", tdt) + model.set_tensor_datatype("thresh1", tdt) + # Create threshold tensors + n_steps: int = idt.get_num_possible_values() - 1 + thresholds: Optional[np.ndarray] = np.random.randint(tdt.min(), tdt.max() - 1, \ + (32, n_steps)).astype(np.float32) # generate thresholds for the activations + thresholds = np.sort(thresholds, axis=1) # provide non-decreasing thresholds + model.set_initializer("thresh0", thresholds) + thresholds: Optional[np.ndarray] = np.random.randint(tdt.min(), tdt.max() - 1, \ + (64, n_steps)).astype(np.float32) # generate thresholds for the activations + thresholds = np.sort(thresholds, axis=1) # provide non-decreasing thresholds + model.set_initializer("thresh1", thresholds) return model @@ -170,7 +182,7 @@ def calculate_accumulator_bit_width( inst: Union[MatrixVectorActivation, VectorVectorActivation], model: ModelWrapper ) -> Union[DataType, IntType]: - """Calculate the accumulator bit width use the closed-form expressions + """Calculate the accumulator bit width using the closed-form expressions derived in `Quantized Neural Networks for Low-Precision Accumulation with Guaranteed Overflow Avoidance` (2023) by I.Colbert, A. Pappalardo, J. Petri-Koenig @@ -217,21 +229,30 @@ def phi(x: float) -> float: return DataType[f"INT{int(P)}"] +thresh_data_types = [ + None, + DataType['INT32'], + DataType['INT24'], + DataType['INT16'], +] + + @pytest.mark.parametrize("wdt", weight_data_types) @pytest.mark.parametrize("idt", input_data_types) +@pytest.mark.parametrize("tdt", thresh_data_types) @pytest.mark.parametrize("rww", [True, False]) -def test_minimize_accumulator_width(wdt: DataType, idt:DataType, rww: bool): +def test_minimize_accumulator_width(wdt: DataType, idt: DataType, tdt: DataType, rww: bool): """Testing MinimizeAccumulatorWidth for VVAU and MVAU. :param wdt: (DataType) The data type that we are testing for the weights :param idt: (DataType) The data type that we are testing for the activations + :param tdt: (DataType) The data type that we are testing for the thresholds :param rww: (bool) Whether or not to use runtime-writeable weights""" if not wdt.signed(): pytest.skip("Closed-form accumulator calculation is designed to consider only signed weights") # Create uniform-precision model - # TODO: add thresholds (tdt) to unit tests - model = make_unit_test_model(wdt, idt) + model = make_unit_test_model(wdt, idt, tdt) def_adt = DataType["INT32"] # If runtime-writeable weights, specify as a node attribute From 168ccbc7b2d1a76406a48097f56a5420fedd40f9 Mon Sep 17 00:00:00 2001 From: icolbert Date: Tue, 28 Feb 2023 18:10:16 -0800 Subject: [PATCH 072/665] Fixing bug Switching noActivation and ActVal, which we incorrectly set when thresholds were specified. --- .../transformation/streamline/test_minimize_bit_width.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tests/transformation/streamline/test_minimize_bit_width.py b/tests/transformation/streamline/test_minimize_bit_width.py index 7cb866c6e8..73beaf5b0c 100644 --- a/tests/transformation/streamline/test_minimize_bit_width.py +++ b/tests/transformation/streamline/test_minimize_bit_width.py @@ -62,8 +62,8 @@ def make_unit_test_model(wdt: DataType, idt: DataType, tdt: Optional[DataType] = inputDataType=idt.name, outputDataType=idt.name, weightDataType=wdt.name, - noActivation=tdt.min() if tdt is not None else 0, - ActVal=0 if tdt is not None else 1, + ActVal=tdt.min() if tdt is not None else 0, + noActivation=0 if tdt is not None else 1, ) layer2 = helper.make_node( "MatrixVectorActivation", @@ -78,8 +78,8 @@ def make_unit_test_model(wdt: DataType, idt: DataType, tdt: Optional[DataType] = inputDataType=idt.name, outputDataType=idt.name, weightDataType=wdt.name, - noActivation=tdt.min() if tdt is not None else 0, - ActVal=0 if tdt is not None else 1, + ActVal=tdt.min() if tdt is not None else 0, + noActivation=0 if tdt is not None else 1, binaryXnorMode=0 ) graph = helper.make_graph( From c25ac04f1a63ee1d0bef6a9dff9bf1cc0cd7e0d2 Mon Sep 17 00:00:00 2001 From: icolbert Date: Tue, 28 Feb 2023 18:16:28 -0800 Subject: [PATCH 073/665] Handling weight data type test cases --- .../streamline/test_minimize_bit_width.py | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/tests/transformation/streamline/test_minimize_bit_width.py b/tests/transformation/streamline/test_minimize_bit_width.py index 73beaf5b0c..1b280de015 100644 --- a/tests/transformation/streamline/test_minimize_bit_width.py +++ b/tests/transformation/streamline/test_minimize_bit_width.py @@ -30,7 +30,7 @@ import numpy as np from typing import Optional, Union from onnx import TensorProto, helper -from qonnx.core.datatype import DataType, IntType +from qonnx.core.datatype import DataType, IntType, BipolarType from qonnx.core.modelwrapper import ModelWrapper from qonnx.custom_op.registry import getCustomOp from qonnx.util.basic import ( @@ -125,9 +125,7 @@ def make_unit_test_model(wdt: DataType, idt: DataType, tdt: Optional[DataType] = DataType['UINT7'], DataType['INT3'], DataType['UINT3'], - # TODO - current MinimizeWeightBitWidth sets {-1,1} to INT2, need to check - # for 0 in weights to minimize weight bit width to bipolar - # DataType["BIPOLAR"], + DataType["BIPOLAR"], DataType["TERNARY"], ] @@ -149,6 +147,10 @@ def test_minimize_weight_bit_width(wdt: DataType, rww: bool): :param wdt: (DataType) The data type that we are testing for the weights :param rww: (bool) Whether or not to use runtime-writeable weights""" + if isinstance(wdt, BipolarType): + # current MinimizeWeightBitWidth sets {-1,1} to INT2, need to check + # for 0 in weights to minimize weight bit width to bipolar + pytest.skip("Not well-supported for this optimization") # Create a w8a8 model def_wdt = DataType['UINT8'] @@ -248,7 +250,7 @@ def test_minimize_accumulator_width(wdt: DataType, idt: DataType, tdt: DataType, :param idt: (DataType) The data type that we are testing for the activations :param tdt: (DataType) The data type that we are testing for the thresholds :param rww: (bool) Whether or not to use runtime-writeable weights""" - if not wdt.signed(): + if (not wdt.signed()) or isinstance(wdt, BipolarType): pytest.skip("Closed-form accumulator calculation is designed to consider only signed weights") # Create uniform-precision model From 29fa600cf0992948aaaa4ad3b24f1bd874b7ca0e Mon Sep 17 00:00:00 2001 From: icolbert Date: Tue, 28 Feb 2023 18:30:51 -0800 Subject: [PATCH 074/665] pre-commit cleanup --- .../fpgadataflow/matrixvectoractivation.py | 10 +- .../fpgadataflow/vectorvectoractivation.py | 10 +- .../streamline/test_minimize_bit_width.py | 144 ++++++++++-------- 3 files changed, 89 insertions(+), 75 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index 39fd16d456..f5585db483 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -631,14 +631,10 @@ def minimize_accumulator_width(self, model): if min_threshold < acc_min: clip_lower = acc_min if (clip_lower is not None) or (clip_upper is not None): - warnings.warn( - "Clipping some thresholds in %s" % self.onnx_node.name - ) + warnings.warn("Clipping some thresholds in %s" % self.onnx_node.name) thresholds = np.clip(thresholds, clip_lower, clip_upper) model.set_initializer(self.onnx_node.input[2], thresholds) - threshold_tensor = self.get_hls_compatible_threshold_tensor( - thresholds - ) + threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds) min_threshold = thresholds.min() max_threshold = thresholds.max() # get range required by threshold values @@ -657,7 +653,7 @@ def minimize_accumulator_width(self, model): self.onnx_node.name, str(tdt), ) - adt = tdt # Set activation datatype to the threshold datatype + adt = tdt # Set activation datatype to the threshold datatype else: if acc_min < 0: if abs(acc_min) > acc_max: diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index 8fac0942e9..a9c59ebe31 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -150,14 +150,10 @@ def minimize_accumulator_width(self, model): if min_threshold < acc_min: clip_lower = acc_min if (clip_lower is not None) or (clip_upper is not None): - warnings.warn( - "Clipping some thresholds in %s" % self.onnx_node.name - ) + warnings.warn("Clipping some thresholds in %s" % self.onnx_node.name) thresholds = np.clip(thresholds, clip_lower, clip_upper) model.set_initializer(self.onnx_node.input[2], thresholds) - threshold_tensor = self.get_hls_compatible_threshold_tensor( - thresholds - ) + threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds) min_threshold = thresholds.min() max_threshold = thresholds.max() # get range required by threshold values @@ -176,7 +172,7 @@ def minimize_accumulator_width(self, model): self.onnx_node.name, str(tdt), ) - adt = tdt # Set activation datatype to the threshold datatype + adt = tdt # Set activation datatype to the threshold datatype else: if acc_min < 0: if abs(acc_min) > acc_max: diff --git a/tests/transformation/streamline/test_minimize_bit_width.py b/tests/transformation/streamline/test_minimize_bit_width.py index 1b280de015..866b64445b 100644 --- a/tests/transformation/streamline/test_minimize_bit_width.py +++ b/tests/transformation/streamline/test_minimize_bit_width.py @@ -27,21 +27,23 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import pytest + import numpy as np -from typing import Optional, Union from onnx import TensorProto, helper -from qonnx.core.datatype import DataType, IntType, BipolarType +from qonnx.core.datatype import BipolarType, DataType, IntType from qonnx.core.modelwrapper import ModelWrapper from qonnx.custom_op.registry import getCustomOp -from qonnx.util.basic import ( - gen_finn_dt_tensor, - roundup_to_integer_multiple -) +from qonnx.util.basic import gen_finn_dt_tensor, roundup_to_integer_multiple +from typing import Optional, Union -from finn.custom_op.fpgadataflow.vectorvectoractivation import VectorVectorActivation from finn.custom_op.fpgadataflow.matrixvectoractivation import MatrixVectorActivation -from finn.transformation.fpgadataflow.minimize_weight_bit_width import MinimizeWeightBitWidth -from finn.transformation.fpgadataflow.minimize_accumulator_width import MinimizeAccumulatorWidth +from finn.custom_op.fpgadataflow.vectorvectoractivation import VectorVectorActivation +from finn.transformation.fpgadataflow.minimize_accumulator_width import ( + MinimizeAccumulatorWidth, +) +from finn.transformation.fpgadataflow.minimize_weight_bit_width import ( + MinimizeWeightBitWidth, +) def make_unit_test_model(wdt: DataType, idt: DataType, tdt: Optional[DataType] = None): @@ -58,7 +60,7 @@ def make_unit_test_model(wdt: DataType, idt: DataType, tdt: Optional[DataType] = PE=1, Channels=32, Dim=(32, 32), - Kernel=(3,3), + Kernel=(3, 3), inputDataType=idt.name, outputDataType=idt.name, weightDataType=wdt.name, @@ -71,8 +73,8 @@ def make_unit_test_model(wdt: DataType, idt: DataType, tdt: Optional[DataType] = ["outp"], domain="finn.custom_op.fpgadataflow", backend="fpgadataflow", - MW=32, # matrix_width (num_inputs) - MH=64, # matrix_height (num_outputs) + MW=32, # matrix_width (num_inputs) + MH=64, # matrix_height (num_outputs) SIMD=1, PE=1, inputDataType=idt.name, @@ -80,7 +82,7 @@ def make_unit_test_model(wdt: DataType, idt: DataType, tdt: Optional[DataType] = weightDataType=wdt.name, ActVal=tdt.min() if tdt is not None else 0, noActivation=0 if tdt is not None else 1, - binaryXnorMode=0 + binaryXnorMode=0, ) graph = helper.make_graph( nodes=[layer1, layer2], name="fclayer_graph", inputs=[inp], outputs=[outp] @@ -94,12 +96,8 @@ def make_unit_test_model(wdt: DataType, idt: DataType, tdt: Optional[DataType] = model.set_tensor_datatype("hid", idt) model.set_tensor_datatype("params0", wdt) model.set_tensor_datatype("params1", wdt) - model.set_initializer("params0", - gen_finn_dt_tensor(wdt, (32, 1, 3, 3)) - ) - model.set_initializer("params1", - gen_finn_dt_tensor(wdt, (32, 64)) - ) + model.set_initializer("params0", gen_finn_dt_tensor(wdt, (32, 1, 3, 3))) + model.set_initializer("params1", gen_finn_dt_tensor(wdt, (32, 64))) # if the threshold data type is specified, then we need to generate # some dummy threshold values if tdt is not None: @@ -107,34 +105,40 @@ def make_unit_test_model(wdt: DataType, idt: DataType, tdt: Optional[DataType] = model.set_tensor_datatype("thresh1", tdt) # Create threshold tensors n_steps: int = idt.get_num_possible_values() - 1 - thresholds: Optional[np.ndarray] = np.random.randint(tdt.min(), tdt.max() - 1, \ - (32, n_steps)).astype(np.float32) # generate thresholds for the activations - thresholds = np.sort(thresholds, axis=1) # provide non-decreasing thresholds + thresholds: Optional[np.ndarray] = np.random.randint( + tdt.min(), tdt.max() - 1, (32, n_steps) + ).astype( + np.float32 + ) # generate thresholds for the activations + thresholds = np.sort(thresholds, axis=1) # provide non-decreasing thresholds model.set_initializer("thresh0", thresholds) - thresholds: Optional[np.ndarray] = np.random.randint(tdt.min(), tdt.max() - 1, \ - (64, n_steps)).astype(np.float32) # generate thresholds for the activations - thresholds = np.sort(thresholds, axis=1) # provide non-decreasing thresholds + thresholds: Optional[np.ndarray] = np.random.randint( + tdt.min(), tdt.max() - 1, (64, n_steps) + ).astype( + np.float32 + ) # generate thresholds for the activations + thresholds = np.sort(thresholds, axis=1) # provide non-decreasing thresholds model.set_initializer("thresh1", thresholds) return model weight_data_types = [ - DataType['INT8'], - DataType['UINT8'], - DataType['INT7'], - DataType['UINT7'], - DataType['INT3'], - DataType['UINT3'], + DataType["INT8"], + DataType["UINT8"], + DataType["INT7"], + DataType["UINT7"], + DataType["INT3"], + DataType["UINT3"], DataType["BIPOLAR"], DataType["TERNARY"], ] input_data_types = [ - DataType['INT8'], - DataType['UINT8'], - DataType['INT3'], - DataType['UINT3'], + DataType["INT8"], + DataType["UINT8"], + DataType["INT3"], + DataType["UINT3"], DataType["BIPOLAR"], DataType["TERNARY"], ] @@ -144,7 +148,7 @@ def make_unit_test_model(wdt: DataType, idt: DataType, tdt: Optional[DataType] = @pytest.mark.parametrize("rww", [True, False]) def test_minimize_weight_bit_width(wdt: DataType, rww: bool): """Testing MinimizeWeightBitWidth for VVAU and MVAU. - + :param wdt: (DataType) The data type that we are testing for the weights :param rww: (bool) Whether or not to use runtime-writeable weights""" if isinstance(wdt, BipolarType): @@ -153,9 +157,9 @@ def test_minimize_weight_bit_width(wdt: DataType, rww: bool): pytest.skip("Not well-supported for this optimization") # Create a w8a8 model - def_wdt = DataType['UINT8'] - model = make_unit_test_model(def_wdt, DataType['INT8']) - + def_wdt = DataType["UINT8"] + model = make_unit_test_model(def_wdt, DataType["INT8"]) + # Create new weights for the model based on wdt params0 = gen_finn_dt_tensor(wdt, (32, 1, 3, 3)) params1 = gen_finn_dt_tensor(wdt, (32, 64)) @@ -171,7 +175,7 @@ def test_minimize_weight_bit_width(wdt: DataType, rww: bool): # Apply the optimization model = model.transform(MinimizeWeightBitWidth()) - # Iterate through each node to make sure it functioned properly + # Iterate through each node to make sure it functioned properly for node in model.graph.node: inst = getCustomOp(node) if isinstance(inst, (MatrixVectorActivation, VectorVectorActivation)): @@ -181,9 +185,8 @@ def test_minimize_weight_bit_width(wdt: DataType, rww: bool): def calculate_accumulator_bit_width( - inst: Union[MatrixVectorActivation, VectorVectorActivation], - model: ModelWrapper - ) -> Union[DataType, IntType]: + inst: Union[MatrixVectorActivation, VectorVectorActivation], model: ModelWrapper +) -> Union[DataType, IntType]: """Calculate the accumulator bit width using the closed-form expressions derived in `Quantized Neural Networks for Low-Precision Accumulation with Guaranteed Overflow Avoidance` (2023) by I.Colbert, A. Pappalardo, @@ -192,6 +195,7 @@ def calculate_accumulator_bit_width( :param inst: (HLSCustomOp) The instance of the MVAU or VVAU :param model: (ModelWrapper) The instance of the whole model """ + def phi(x: float) -> float: return np.log2(1 + pow(2, -x)) @@ -202,10 +206,10 @@ def phi(x: float) -> float: weights = 2 * weights - 1 # modify the weights based on if the node is a VVAU or MVAU if isinstance(inst, MatrixVectorActivation): - K = inst.get_nodeattr("MW") # matrix_width = num_inputs + K = inst.get_nodeattr("MW") # matrix_width = num_inputs elif isinstance(inst, VectorVectorActivation): k_h, k_w = inst.get_nodeattr("Kernel") - K = k_h * k_w # size of kernels = num_inputs + K = k_h * k_w # size of kernels = num_inputs fm = inst.get_nodeattr("Channels") # put weights into the shape expected by calculate_matvec_accumulator_range weights = weights.reshape(fm, k_h * k_w).transpose() @@ -218,13 +222,17 @@ def phi(x: float) -> float: # if runtime-writeable weights, then use the lower bound on the accumulator bit # width as determined by the input and weight data types and size of dot product if rww: - alpha = np.log2(K) + idt.bitwidth() + wdt.bitwidth() - 1. - float(idt.signed()) - P = np.ceil(alpha + phi(alpha) + 1.) + alpha = np.log2(K) + idt.bitwidth() + wdt.bitwidth() - 1.0 - float(idt.signed()) + P = np.ceil(alpha + phi(alpha) + 1.0) # if not runtime-writable weights, then use the tighter bound on the accumulator # bit width as determined by the weight values themselves else: - beta = np.log2(abs(weights).sum(axis=0).max()) + idt.bitwidth() - float(idt.signed()) - P = np.ceil(beta + phi(beta) + 1.) + beta = ( + np.log2(abs(weights).sum(axis=0).max()) + + idt.bitwidth() + - float(idt.signed()) + ) + P = np.ceil(beta + phi(beta) + 1.0) # if the node is the last in the graph, then round up to the nearest 8 bits if model.find_direct_successors(inst.onnx_node) is None: P = roundup_to_integer_multiple(P, 8) @@ -233,9 +241,9 @@ def phi(x: float) -> float: thresh_data_types = [ None, - DataType['INT32'], - DataType['INT24'], - DataType['INT16'], + DataType["INT32"], + DataType["INT24"], + DataType["INT16"], ] @@ -243,15 +251,19 @@ def phi(x: float) -> float: @pytest.mark.parametrize("idt", input_data_types) @pytest.mark.parametrize("tdt", thresh_data_types) @pytest.mark.parametrize("rww", [True, False]) -def test_minimize_accumulator_width(wdt: DataType, idt: DataType, tdt: DataType, rww: bool): +def test_minimize_accumulator_width( + wdt: DataType, idt: DataType, tdt: DataType, rww: bool +): """Testing MinimizeAccumulatorWidth for VVAU and MVAU. - + :param wdt: (DataType) The data type that we are testing for the weights :param idt: (DataType) The data type that we are testing for the activations :param tdt: (DataType) The data type that we are testing for the thresholds :param rww: (bool) Whether or not to use runtime-writeable weights""" if (not wdt.signed()) or isinstance(wdt, BipolarType): - pytest.skip("Closed-form accumulator calculation is designed to consider only signed weights") + pytest.skip( + "Closed-form accumulator calculation is designed to consider signed weights" + ) # Create uniform-precision model model = make_unit_test_model(wdt, idt, tdt) @@ -263,12 +275,14 @@ def test_minimize_accumulator_width(wdt: DataType, idt: DataType, tdt: DataType, if isinstance(inst, (MatrixVectorActivation, VectorVectorActivation)): inst.set_nodeattr("runtime_writeable_weights", int(rww)) cur_adt = DataType[inst.get_nodeattr("accDataType")] - assert cur_adt.bitwidth() == def_adt.bitwidth(), "Default data type is incorrect" + assert ( + cur_adt.bitwidth() == def_adt.bitwidth() + ), "Default data type is incorrect" # Apply the optimization model = model.transform(MinimizeAccumulatorWidth()) - # Iterate through each node to make sure it functioned properly + # Iterate through each node to make sure it functioned properly for node in model.graph.node: inst = getCustomOp(node) if isinstance(inst, (MatrixVectorActivation, VectorVectorActivation)): @@ -279,9 +293,17 @@ def test_minimize_accumulator_width(wdt: DataType, idt: DataType, tdt: DataType, # bit width minimization logic in the MVAU and VVAU is exact and should be # less than or equal to this calculation exp_adt = calculate_accumulator_bit_width(inst, model) - assert cur_adt.bitwidth() <= exp_adt.bitwidth(), "Mismatched accumulation data types" + assert ( + cur_adt.bitwidth() <= exp_adt.bitwidth() + ), "Mismatched accumulation data types" if model.find_direct_successors(inst.onnx_node) is None: - assert (cur_adt.bitwidth() % 8) == 0, "bit width of last node needs to be divisible by 8" - assert cur_adt.bitwidth() == cur_odt.bitwidth(), "outputDataType and accDataType should be equal" + assert ( + cur_adt.bitwidth() % 8 + ) == 0, "bit width of last node needs to be divisible by 8" + assert ( + cur_adt.bitwidth() == cur_odt.bitwidth() + ), "outputDataType and accDataType should be equal" else: - assert cur_odt.bitwidth() == idt.bitwidth(), "outputDataType should not be changed" \ No newline at end of file + assert ( + cur_odt.bitwidth() == idt.bitwidth() + ), "outputDataType should not be changed" From 3a2d5e3fd2561adce3f16b143d0bf5c4450cd523 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 1 Mar 2023 09:51:36 +0000 Subject: [PATCH 075/665] [Tests] Update brevitas export test for relu --- .../brevitas/test_brevitas_relu_act_export.py | 53 ++++++++++++++----- 1 file changed, 40 insertions(+), 13 deletions(-) diff --git a/tests/brevitas/test_brevitas_relu_act_export.py b/tests/brevitas/test_brevitas_relu_act_export.py index 6bff4ae800..a4657d7924 100644 --- a/tests/brevitas/test_brevitas_relu_act_export.py +++ b/tests/brevitas/test_brevitas_relu_act_export.py @@ -32,7 +32,6 @@ import onnx # noqa import os import torch -from brevitas.core.quant import QuantType from brevitas.core.scaling import ScalingImplType from brevitas.export import export_finn_onnx, export_qonnx from brevitas.nn import QuantReLU @@ -49,28 +48,56 @@ @pytest.mark.brevitas_export @pytest.mark.parametrize("abits", [2, 4, 8]) @pytest.mark.parametrize("ishape", [(1, 15), (1, 32, 1, 1)]) -@pytest.mark.parametrize( - "scaling_impl_type", [ScalingImplType.CONST] # , ScalingImplType.PARAMETER] -) -@pytest.mark.parametrize("scaling_per_output_channel", [True, False]) -@pytest.mark.parametrize("per_channel_broadcastable_shape", [None, (1, 32, 1, 1)]) @pytest.mark.parametrize("QONNX_export", [False, True]) def test_brevitas_act_export_relu( abits, ishape, - scaling_impl_type, - scaling_per_output_channel, - per_channel_broadcastable_shape, QONNX_export, ): + b_act = QuantReLU( + bit_width=abits, + ) + if QONNX_export: + m_path = export_onnx_path + export_qonnx(b_act, torch.randn(ishape), m_path) + qonnx_cleanup(m_path, out_file=m_path) + model = ModelWrapper(m_path) + model = model.transform(ConvertQONNXtoFINN()) + model.save(m_path) + else: + export_finn_onnx(b_act, torch.randn(ishape), export_onnx_path) + model = ModelWrapper(export_onnx_path) + model = model.transform(InferShapes()) + inp_tensor = np.random.uniform(low=-1.0, high=6.0, size=ishape).astype(np.float32) + idict = {model.graph.input[0].name: inp_tensor} + odict = oxe.execute_onnx(model, idict, True) + produced = odict[model.graph.output[0].name] + inp_tensor = torch.from_numpy(inp_tensor).float() + b_act.eval() + expected = b_act.forward(inp_tensor).detach().numpy() + + assert np.isclose(produced, expected, atol=1e-3).all() + os.remove(export_onnx_path) + + +@pytest.mark.brevitas_export +@pytest.mark.parametrize("abits", [2, 4, 8]) +@pytest.mark.parametrize("ishape", [(1, 15, 4, 4), (1, 32, 1, 1)]) +@pytest.mark.parametrize("QONNX_export", [False, True]) +def test_brevitas_act_export_relu_channel( + abits, + ishape, + QONNX_export, +): + + ch = ishape[1] b_act = QuantReLU( bit_width=abits, max_val=6.0, - scaling_impl_type=scaling_impl_type, - quant_type=QuantType.INT, - scaling_per_output_channel=scaling_per_output_channel, - per_channel_broadcastable_shape=per_channel_broadcastable_shape, + scaling_impl_type=ScalingImplType.CONST, + scaling_per_output_channel=True, + per_channel_broadcastable_shape=(1, ch, 1, 1), ) if QONNX_export: m_path = export_onnx_path From 6b409baf091c1f3e131734a93dc66beafc444486 Mon Sep 17 00:00:00 2001 From: Felix Jentzsch Date: Thu, 2 Mar 2023 10:44:58 +0100 Subject: [PATCH 076/665] [Thres] remove workaround for vivado_hls bug for T[0][0]=0 case --- src/finn/custom_op/fpgadataflow/matrixvectoractivation.py | 7 ------- src/finn/custom_op/fpgadataflow/thresholding_batch.py | 7 ------- src/finn/custom_op/fpgadataflow/vectorvectoractivation.py | 7 ------- 3 files changed, 21 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index 40f625093b..d6285a6f69 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -709,13 +709,6 @@ def get_hls_compatible_threshold_tensor(self, orig_thres_matrix): # ensure all thresholds are integer assert (orig_thres_matrix.astype(np.int32) == orig_thres_matrix).all() ret = orig_thres_matrix - # workaround for vivado_hls threshold bug - if ret[0][0] == 0 and n_thres_steps == 1: - ret = np.copy(ret) - ret[0][0] = 1 - warnings.warn( - "Setting 0-valued first threshold to 1 to avoid vivado_hls bug" - ) # ensure channels = mh , duplicating if necessary if ret.shape[0] == 1: ret = np.tile(ret, (mh, 1)) diff --git a/src/finn/custom_op/fpgadataflow/thresholding_batch.py b/src/finn/custom_op/fpgadataflow/thresholding_batch.py index ce8c31ee9a..292f70941a 100644 --- a/src/finn/custom_op/fpgadataflow/thresholding_batch.py +++ b/src/finn/custom_op/fpgadataflow/thresholding_batch.py @@ -319,13 +319,6 @@ def get_hls_compatible_threshold_tensor(self, orig_thres_matrix): np.mod(orig_thres_matrix, 1), 0 ).all(), "Need int threshold tensor" ret = orig_thres_matrix - # workaround for vivado_hls threshold bug - if ret[0][0] == 0 and n_thres_steps == 1: - ret = np.copy(ret) - ret[0][0] = 1 - warnings.warn( - "Setting 0-valued first threshold to 1 to avoid vivado_hls bug" - ) # ensure channels = mh , duplicating if necessary if ret.shape[0] == 1: ret = np.tile(ret, (mh, 1)) diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index 5d996e10d8..a2dd3c75dc 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -418,13 +418,6 @@ def get_hls_compatible_threshold_tensor(self, orig_thres_matrix): # ensure all thresholds are integer assert (orig_thres_matrix.astype(np.int32) == orig_thres_matrix).all() ret = orig_thres_matrix - # workaround for vivado_hls threshold bug - if ret[0][0] == 0 and n_thres_steps == 1: - ret = np.copy(ret) - ret[0][0] = 1 - warnings.warn( - "Setting 0-valued first threshold to 1 to avoid vivado_hls bug" - ) # ensure channels = mh , duplicating if necessary if ret.shape[0] == 1: ret = np.tile(ret, (ch, 1)) From b8319a719cea0c6ccf073220c7839688d5d2f557 Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 3 Mar 2023 13:58:07 +0000 Subject: [PATCH 077/665] [Tests] Delete vivado_hls bug test from thresholding testing --- tests/fpgadataflow/test_fpgadataflow_thresholding.py | 4 ---- 1 file changed, 4 deletions(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_thresholding.py b/tests/fpgadataflow/test_fpgadataflow_thresholding.py index 96cd69c345..445afdf458 100644 --- a/tests/fpgadataflow/test_fpgadataflow_thresholding.py +++ b/tests/fpgadataflow/test_fpgadataflow_thresholding.py @@ -132,10 +132,6 @@ def test_fpgadataflow_thresholding(idt, act, nf, ich, exec_mode, mem_mode): odt = act n_steps = act.get_num_possible_values() - 1 T = np.random.randint(idt.min(), idt.max() + 1, (ich, n_steps)).astype(np.float32) - # make the vivado_hls threshold bug appear (incorrect rtlsim result when first - # threshold of first channel is zero, while using BIPOLAR output) - if act == DataType["BIPOLAR"]: - T[0][0] = 0 # provide non-decreasing thresholds T = np.sort(T, axis=1) From 7077e40af03cffdce4f8bcbc9d39d1628ec48f9a Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 3 Mar 2023 14:29:21 +0000 Subject: [PATCH 078/665] [Driver] Update loading of rt weights in driver base --- src/finn/qnn-data/templates/driver/driver_base.py | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/src/finn/qnn-data/templates/driver/driver_base.py b/src/finn/qnn-data/templates/driver/driver_base.py index 2096760580..5f6f00da13 100644 --- a/src/finn/qnn-data/templates/driver/driver_base.py +++ b/src/finn/qnn-data/templates/driver/driver_base.py @@ -189,14 +189,10 @@ def load_runtime_weights(self, flush_accel=True, verify=True): layer_ind = int(w_filename.split("_")[1]) rt_weight_dict[(sdp_ind, layer_ind)] = layer_w for sdp_ind, layer_ind in rt_weight_dict.keys(): - cand_if_name = "StreamingDataflowPartition_%d/s_axilite_%d" % ( - sdp_ind, - layer_ind, - ) + cand_if_name = "StreamingDataflowPartition_%d" % sdp_ind if cand_if_name in self.ip_dict.keys(): layer_mmio = getattr( - getattr(self, "StreamingDataflowPartition_%d" % sdp_ind), - "s_axilite_%d" % layer_ind, + self, "StreamingDataflowPartition_%d" % sdp_ind ).mmio layer_w = rt_weight_dict[(sdp_ind, layer_ind)] layer_mmio.write_mm(0, layer_w.tobytes()) From 2da2445fda6c63bd19ccedfae6d5614eca7ad241 Mon Sep 17 00:00:00 2001 From: Rachit Garg Date: Sat, 4 Mar 2023 19:55:04 +0100 Subject: [PATCH 079/665] Fixed Summary Typo Changed from "Summmmary" to "Summary" --- notebooks/end2end_example/bnn-pynq/cnv_end2end_example.ipynb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/notebooks/end2end_example/bnn-pynq/cnv_end2end_example.ipynb b/notebooks/end2end_example/bnn-pynq/cnv_end2end_example.ipynb index 388accad3a..f08bcf8488 100644 --- a/notebooks/end2end_example/bnn-pynq/cnv_end2end_example.ipynb +++ b/notebooks/end2end_example/bnn-pynq/cnv_end2end_example.ipynb @@ -240,7 +240,7 @@ "cell_type": "markdown", "metadata": {}, "source": [ - "We won't go into too much detail about what happens in each transformation and why they are called in the particular order they are (feel free to visualize the intermediate steps using Netron yourself if you are curious) but here is a brief summmmary:\n", + "We won't go into too much detail about what happens in each transformation and why they are called in the particular order they are (feel free to visualize the intermediate steps using Netron yourself if you are curious) but here is a brief summary:\n", "\n", "* `Streamline` moves floating point scaling and addition operations closer to the input of the nearest thresholding activation and absorbs them into thresholds\n", "* `LowerConvsToMatMul` converts ONNX `Conv` nodes into sequences of `Im2Col, MatMul` nodes as discussed above. `Im2Col` is a custom FINN ONNX high-level node type that implements the sliding window operator.\n", From 6f78fa76308d8fc657d257eabe8b5b159290368a Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 6 Mar 2023 10:26:20 +0000 Subject: [PATCH 080/665] [Docs] Modify docstring in set folding transform --- src/finn/transformation/fpgadataflow/set_folding.py | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/set_folding.py b/src/finn/transformation/fpgadataflow/set_folding.py index 4e79a3faa5..0a466afe13 100644 --- a/src/finn/transformation/fpgadataflow/set_folding.py +++ b/src/finn/transformation/fpgadataflow/set_folding.py @@ -71,12 +71,13 @@ class SetFolding(Transformation): When folding depthwise convolutions ("VVAU"/VectorVectorActivation) or spatial reduction ops (Pool_Batch): - * the producer of the node is expected to be a ConvolutionInputGenerator - with depthwise=1, whose SIMD value will be set equal to the PE value of - its consumer node - * the VVAU also supports SIMD ("input window") parallelism next to - PE ("channels"), but current ConvInpGen limitations require PE to be fully - unfolded before SIMD is increased + + * the producer of the node is expected to be a ConvolutionInputGenerator + with depthwise=1, whose SIMD value will be set equal to the PE value of + its consumer node + * the VVAU also supports SIMD ("input window") parallelism next to + PE ("channels"), but current ConvInpGen limitations require PE to be fully + unfolded before SIMD is increased """ def __init__( From e0f68c537d7f33c2767b8b9f37e524cbd29c2722 Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 6 Mar 2023 10:34:49 +0000 Subject: [PATCH 081/665] [Docs] Update internals.rst --- docs/finn/internals.rst | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/docs/finn/internals.rst b/docs/finn/internals.rst index 848d22afec..c0d1f65aab 100644 --- a/docs/finn/internals.rst +++ b/docs/finn/internals.rst @@ -213,10 +213,14 @@ FINN implements convolution operations by pairing a ConvolutionInputGenerator (o This RTL version is an alternative to the original `HLS implementation `_ and aims to improve on it in the following ways: * Support a wider range of hyperparameters without the fragmentation into 16+ separate HLS functions + * Support additional degrees of parallelism (i.e., across the output window or multiple input samples) that are difficult to implement in HLS + * Support additional features, such as dynamic feature map sizing + * Improve resource efficiency + The component is implemented by generating (System-)Verilog code for each individual instance, realized via the template + replacement dictionary mechanism found in other FINN components. Despite the HDL implementation, the component is managed by its own HLSCustomOp (!) named "ConvolutionInputGenerator_rtl". Naturally, HLS simulation & synthesis are not supported. @@ -277,7 +281,7 @@ The "default" style also supports a dynamic mode, which provides an interface to Folding ------- -The RTL SWG is supported by the basic automatic folding algorithm in FINN (:py:mod:`SetFolding()`). Consider the following implications: +The RTL SWG is supported by the basic automatic folding algorithm in FINN (:py:mod:`finn.transformation.fpgadataflow.set_folding.SetFolding`). Consider the following implications: **MVAU:** Although it is recommended to unfold SIMD first, SIMD and PE can be set independently. Full (and balanced) parallelism is achieved by using the SWG in parallel window mode and setting MVAU SIMD and PE to their maximum values (SIMD = MW = C_in * K, PE = MH = C_out). From 99bc34573339eba0bb5950fe92c91636cc8819ab Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 6 Mar 2023 10:44:58 +0000 Subject: [PATCH 082/665] [Docs] Update API links in internals section --- docs/finn/internals.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/finn/internals.rst b/docs/finn/internals.rst index c0d1f65aab..d0c4cd2065 100644 --- a/docs/finn/internals.rst +++ b/docs/finn/internals.rst @@ -224,7 +224,7 @@ This RTL version is an alternative to the original `HLS implementation Date: Tue, 7 Mar 2023 15:52:43 +0000 Subject: [PATCH 083/665] [Tests] Move minimize bit width test and add Jenkins marker --- .../streamline => fpgadataflow}/test_minimize_bit_width.py | 2 ++ 1 file changed, 2 insertions(+) rename tests/{transformation/streamline => fpgadataflow}/test_minimize_bit_width.py (99%) diff --git a/tests/transformation/streamline/test_minimize_bit_width.py b/tests/fpgadataflow/test_minimize_bit_width.py similarity index 99% rename from tests/transformation/streamline/test_minimize_bit_width.py rename to tests/fpgadataflow/test_minimize_bit_width.py index 866b64445b..7f6778fbf3 100644 --- a/tests/transformation/streamline/test_minimize_bit_width.py +++ b/tests/fpgadataflow/test_minimize_bit_width.py @@ -146,6 +146,7 @@ def make_unit_test_model(wdt: DataType, idt: DataType, tdt: Optional[DataType] = @pytest.mark.parametrize("wdt", weight_data_types) @pytest.mark.parametrize("rww", [True, False]) +@pytest.mark.fpgadataflow def test_minimize_weight_bit_width(wdt: DataType, rww: bool): """Testing MinimizeWeightBitWidth for VVAU and MVAU. @@ -251,6 +252,7 @@ def phi(x: float) -> float: @pytest.mark.parametrize("idt", input_data_types) @pytest.mark.parametrize("tdt", thresh_data_types) @pytest.mark.parametrize("rww", [True, False]) +@pytest.mark.fpgadataflow def test_minimize_accumulator_width( wdt: DataType, idt: DataType, tdt: DataType, rww: bool ): From 21b9c45a3cdf40a0cd15453e3a551116019dcc01 Mon Sep 17 00:00:00 2001 From: icolbert Date: Tue, 7 Mar 2023 08:05:53 -0800 Subject: [PATCH 084/665] Cleaning up weight data types for pytest options --- tests/fpgadataflow/test_minimize_bit_width.py | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/tests/fpgadataflow/test_minimize_bit_width.py b/tests/fpgadataflow/test_minimize_bit_width.py index 7f6778fbf3..dc4a076a18 100644 --- a/tests/fpgadataflow/test_minimize_bit_width.py +++ b/tests/fpgadataflow/test_minimize_bit_width.py @@ -129,7 +129,7 @@ def make_unit_test_model(wdt: DataType, idt: DataType, tdt: Optional[DataType] = DataType["UINT7"], DataType["INT3"], DataType["UINT3"], - DataType["BIPOLAR"], + # DataType["BIPOLAR"], # TODO - add support for bipolar weights DataType["TERNARY"], ] @@ -247,6 +247,15 @@ def phi(x: float) -> float: DataType["INT16"], ] +# Removing unsigned data types fro weights +weight_data_types = [ + DataType["INT8"], + DataType["INT7"], + DataType["INT3"], + # DataType["BIPOLAR"], # TODO - add support for bipolar weights + DataType["TERNARY"], +] + @pytest.mark.parametrize("wdt", weight_data_types) @pytest.mark.parametrize("idt", input_data_types) From 4907f627546c77a7ba296931e6c0dc468c9be81d Mon Sep 17 00:00:00 2001 From: auphelia Date: Thu, 9 Mar 2023 08:48:04 +0000 Subject: [PATCH 085/665] [Util] Fix interpretation of dtype to check for signed integer --- src/finn/util/data_packing.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/finn/util/data_packing.py b/src/finn/util/data_packing.py index 3602b1bdd5..a41fe882e5 100644 --- a/src/finn/util/data_packing.py +++ b/src/finn/util/data_packing.py @@ -220,7 +220,7 @@ def unpack_innermost_dim_from_hex_string( if conv_dtype == DataType["BIPOLAR"]: ar_list = [2 * x - 1 for x in ar_list] # interpret values as signed values - elif dtype.signed(): + elif conv_dtype.signed() and conv_dtype.is_integer(): mask = 2 ** (conv_dtype.bitwidth() - 1) ar_list = [-(x & mask) + (x & ~mask) for x in ar_list] From 1a2eaaac2fdbf7ee6b24b7458577dbc692659b63 Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 13 Mar 2023 10:05:38 +0000 Subject: [PATCH 086/665] [Tests] Remove minimize acc width for vvau tests --- tests/fpgadataflow/test_fpgadataflow_vvau.py | 5 ----- 1 file changed, 5 deletions(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_vvau.py b/tests/fpgadataflow/test_fpgadataflow_vvau.py index be1ada59a1..95501078d6 100644 --- a/tests/fpgadataflow/test_fpgadataflow_vvau.py +++ b/tests/fpgadataflow/test_fpgadataflow_vvau.py @@ -43,9 +43,6 @@ from finn.analysis.fpgadataflow.exp_cycles_per_layer import exp_cycles_per_layer from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP -from finn.transformation.fpgadataflow.minimize_accumulator_width import ( - MinimizeAccumulatorWidth, -) from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim @@ -156,8 +153,6 @@ def _make_single_vvau_modelwrapper( model.set_tensor_datatype("thresh", tdt) model.set_initializer("thresh", T) - # Minimize accumulator width to obtain realistic HLS reports - model = model.transform(MinimizeAccumulatorWidth()) model = model.transform(InferShapes()) model = model.transform(InferDataTypes()) From 6e31105f59b0cba618b1dc452035b98c5f19802b Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 14 Mar 2023 10:06:57 +0000 Subject: [PATCH 087/665] [Tests] Update resource estimates in cybsec test --- tests/end2end/test_end2end_cybsec_mlp.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/end2end/test_end2end_cybsec_mlp.py b/tests/end2end/test_end2end_cybsec_mlp.py index 86942415b9..d2a4d0287f 100644 --- a/tests/end2end/test_end2end_cybsec_mlp.py +++ b/tests/end2end/test_end2end_cybsec_mlp.py @@ -222,7 +222,7 @@ def test_end2end_cybsec_mlp_build(QONNX_export): assert est_cycles_dict["MatrixVectorActivation_1"] == 64 with open(est_res_report, "r") as f: est_res_dict = json.load(f) - assert est_res_dict["total"]["LUT"] == 11360.0 + assert est_res_dict["total"]["LUT"] == 7904.0 assert est_res_dict["total"]["BRAM_18K"] == 36.0 shutil.copytree(output_dir + "/deploy", get_checkpoint_name("build", QONNX_export)) From 40eb5c7d22189065589fb0e592c1cbee6e46f1e7 Mon Sep 17 00:00:00 2001 From: Felix Jentzsch Date: Tue, 14 Mar 2023 15:12:55 +0100 Subject: [PATCH 088/665] [SWG] Move common modules to static source file --- finn-rtllib/swg/swg_common.sv | 254 ++++++++++++++++ finn-rtllib/swg/swg_template_default.sv | 160 ++--------- .../swg/swg_template_default_dynamic.sv | 30 +- finn-rtllib/swg/swg_template_parallel.sv | 270 ++++-------------- .../convolutioninputgenerator_rtl.py | 29 +- 5 files changed, 345 insertions(+), 398 deletions(-) create mode 100644 finn-rtllib/swg/swg_common.sv diff --git a/finn-rtllib/swg/swg_common.sv b/finn-rtllib/swg/swg_common.sv new file mode 100644 index 0000000000..8dfb8f51a2 --- /dev/null +++ b/finn-rtllib/swg/swg_common.sv @@ -0,0 +1,254 @@ +/****************************************************************************** + * Copyright (C) 2022, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *****************************************************************************/ + +// loop controller used for both, "default" and "parallel", implementation styles +module swg_controller #( + int unsigned LOOP_H_ITERATIONS, + int unsigned LOOP_W_ITERATIONS, + int unsigned LOOP_KH_ITERATIONS, + int unsigned LOOP_KW_ITERATIONS, + int unsigned LOOP_SIMD_ITERATIONS, + + int unsigned INCR_BITWIDTH, + + bit IS_DEPTHWISE, + + int HEAD_INCR_SIMD, + int HEAD_INCR_KW, + int HEAD_INCR_KH, + int HEAD_INCR_W, + int HEAD_INCR_H, + int TAIL_INCR_W, + int TAIL_INCR_H, + int TAIL_INCR_LAST, + + parameter INNERMOST_STATE +)( + input logic clk, + input logic rst_n, + + input logic advance, + output logic [INCR_BITWIDTH-1:0] addr_incr, + output logic [INCR_BITWIDTH-1:0] tail_incr +); + + // state and counters + typedef enum logic [2:0] { + STATE_START, + STATE_LOOP_SIMD, + STATE_LOOP_KW, + STATE_LOOP_KH, + STATE_LOOP_W, + STATE_LOOP_H + } state_e; + state_e State = INNERMOST_STATE; + state_e state_next; + + logic signed [$clog2(LOOP_H_ITERATIONS +2)+1-1:0] Counter_loop_h = LOOP_H_ITERATIONS; + logic signed [$clog2(LOOP_W_ITERATIONS +2)+1-1:0] Counter_loop_w = LOOP_W_ITERATIONS; + logic signed [$clog2(LOOP_KH_ITERATIONS +2)+1-1:0] Counter_loop_kh = LOOP_KH_ITERATIONS; + logic signed [$clog2(LOOP_KW_ITERATIONS +2)+1-1:0] Counter_loop_kw = LOOP_KW_ITERATIONS; + logic signed [$clog2(LOOP_SIMD_ITERATIONS+2)+1-1:0] Counter_loop_simd = LOOP_SIMD_ITERATIONS; + + // combinational logic for addr_incr generation + always_comb begin : blkHead + unique case (State) + STATE_START : addr_incr = 0; + STATE_LOOP_SIMD : addr_incr = HEAD_INCR_SIMD; + STATE_LOOP_KW : addr_incr = HEAD_INCR_KW; + STATE_LOOP_KH : addr_incr = HEAD_INCR_KH; + STATE_LOOP_W : addr_incr = HEAD_INCR_W; + STATE_LOOP_H : addr_incr = HEAD_INCR_H; + endcase + end + + // combinational logic for tail_incr generation + uwire tail_incr_inner_condition = IS_DEPTHWISE? (Counter_loop_kh >= 0) : 0; + assign tail_incr = + tail_incr_inner_condition? 1 : + Counter_loop_w >= 0? TAIL_INCR_W : + Counter_loop_h >= 0? TAIL_INCR_H : + /* else */ TAIL_INCR_LAST; + + // combinational next state logic + always_comb begin : blkState + state_next = State; + if(State != INNERMOST_STATE) state_next = INNERMOST_STATE; + else begin + if(Counter_loop_simd < 0) begin + state_next = + (Counter_loop_kw >= 0)? STATE_LOOP_KW : + (Counter_loop_kh >= 0)? STATE_LOOP_KH : + (Counter_loop_w >= 0)? STATE_LOOP_W : + (Counter_loop_h >= 0)? STATE_LOOP_H : + /* else */ STATE_START; + end + end + end : blkState + + // sequential logic + always_ff @ (posedge clk) begin + if(!rst_n) begin + State <= INNERMOST_STATE; + Counter_loop_h <= LOOP_H_ITERATIONS; + Counter_loop_w <= LOOP_W_ITERATIONS; + Counter_loop_kh <= LOOP_KH_ITERATIONS; + Counter_loop_kw <= LOOP_KW_ITERATIONS; + Counter_loop_simd <= LOOP_SIMD_ITERATIONS; + end + else if(advance) begin + State <= state_next; + if (State == INNERMOST_STATE) begin + if(Counter_loop_simd >= 0) Counter_loop_simd <= Counter_loop_simd-1; + else begin + Counter_loop_simd <= LOOP_SIMD_ITERATIONS; + if(Counter_loop_kw >= 0) Counter_loop_kw <= Counter_loop_kw-1; + else begin + Counter_loop_kw <= LOOP_KW_ITERATIONS; + if(Counter_loop_kh >= 0) Counter_loop_kh <= Counter_loop_kh-1; + else begin + Counter_loop_kh <= LOOP_KH_ITERATIONS; + if(Counter_loop_w >= 0) Counter_loop_w <= Counter_loop_w-1; + else begin + Counter_loop_w <= LOOP_W_ITERATIONS; + if(Counter_loop_h >= 0) Counter_loop_h <= Counter_loop_h-1; + else Counter_loop_h <= LOOP_H_ITERATIONS; + end + end + end + end + end + end + end + +endmodule : swg_controller + +// buffer used in "default" implementation style +module swg_cyclic_buffer_addressable #( + int unsigned WIDTH, + int unsigned DEPTH, + parameter RAM_STYLE = "auto" +)( + input logic clk, + + input logic write_enable, + input logic [$clog2(DEPTH)-1:0] write_addr, + input logic [WIDTH-1:0] data_in, + + input logic read_enable, + input logic [$clog2(DEPTH)-1:0] read_addr, // absolute (!) read address of cyclic buffer + output logic [WIDTH-1:0] data_out +); + + (*ram_style=RAM_STYLE*) logic [WIDTH-1:0] Ram[DEPTH]; + logic [WIDTH-1:0] Out = 'x; + always_ff @(posedge clk) begin + if (read_enable) Out <= Ram[read_addr]; + if (write_enable) Ram[write_addr] <= data_in; + end + assign data_out = Out; + +endmodule : swg_cyclic_buffer_addressable + +// buffer used in "parallel" implementation style +module swg_reg_buffer +#( + int unsigned WIDTH = 1, + int unsigned DEPTH = 1 +) +( + input logic CLK, + input logic shift_enable, + input logic [WIDTH-1:0] shift_in, + output logic [WIDTH-1:0] shift_out, + output logic [WIDTH*DEPTH-1:0] data_out +); + +reg [WIDTH-1:0] data [DEPTH-1:0]; + +assign shift_out = data[DEPTH-1]; + +for (genvar e=0; e0; i=i-1) + data[i] <= data[i-1]; + data[0] <= shift_in; + end +end +endmodule : swg_reg_buffer + +// buffer used in "parallel" implementation style +module swg_ram_buffer +#( + int unsigned WIDTH, + int unsigned DEPTH, + parameter RAM_STYLE = "auto" +) +( + input logic CLK, + input logic RST, + input logic shift_enable, + input logic [WIDTH-1:0] shift_in, + output logic [WIDTH-1:0] shift_out +); + +reg [WIDTH-1:0] out_reg; +assign shift_out = out_reg; + +integer addr_w, addr_r; + +(*ram_style=RAM_STYLE*) reg [WIDTH-1:0] ram [DEPTH-1:0]; + +always @(posedge CLK) begin + if (RST == 1'b0) begin + addr_w <= 0; + addr_r <= 1; + end else begin + if (shift_enable) begin + ram[addr_w] <= shift_in; + out_reg <= ram[addr_r]; + + if (addr_w == DEPTH-1) + addr_w <= 0; + else + addr_w <= addr_w + 1; + + if (addr_r == DEPTH-1) + addr_r <= 0; + else + addr_r <= addr_r + 1; + end + end +end +endmodule : swg_ram_buffer diff --git a/finn-rtllib/swg/swg_template_default.sv b/finn-rtllib/swg/swg_template_default.sv index 06e65e9111..4970762172 100644 --- a/finn-rtllib/swg/swg_template_default.sv +++ b/finn-rtllib/swg/swg_template_default.sv @@ -28,141 +28,6 @@ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ -module $TOP_MODULE_NAME$_controller #( - int unsigned LOOP_H_ITERATIONS = $LOOP_H_ITERATIONS$, - int unsigned LOOP_W_ITERATIONS = $LOOP_W_ITERATIONS$, - int unsigned LOOP_KH_ITERATIONS = $LOOP_KH_ITERATIONS$, - int unsigned LOOP_KW_ITERATIONS = $LOOP_KW_ITERATIONS$, - int unsigned LOOP_SIMD_ITERATIONS = $LOOP_SIMD_ITERATIONS$, - - int unsigned INCR_BITWIDTH = $INCR_BITWIDTH$, - - bit IS_DEPTHWISE = $IS_DEPTHWISE$ -)( - input logic clk, - input logic rst_n, - - input logic advance, - output logic [INCR_BITWIDTH-1:0] addr_incr, - output logic [INCR_BITWIDTH-1:0] tail_incr -); - - // state and counters - typedef enum logic [2:0] { - STATE_START, - STATE_LOOP_SIMD, - STATE_LOOP_KW, - STATE_LOOP_KH, - STATE_LOOP_W, - STATE_LOOP_H - } state_e; - state_e State = $INNERMOST_STATE$; - state_e state_next; - - logic signed [$clog2(LOOP_H_ITERATIONS +2)+1-1:0] Counter_loop_h = LOOP_H_ITERATIONS; - logic signed [$clog2(LOOP_W_ITERATIONS +2)+1-1:0] Counter_loop_w = LOOP_W_ITERATIONS; - logic signed [$clog2(LOOP_KH_ITERATIONS +2)+1-1:0] Counter_loop_kh = LOOP_KH_ITERATIONS; - logic signed [$clog2(LOOP_KW_ITERATIONS +2)+1-1:0] Counter_loop_kw = LOOP_KW_ITERATIONS; - logic signed [$clog2(LOOP_SIMD_ITERATIONS+2)+1-1:0] Counter_loop_simd = LOOP_SIMD_ITERATIONS; - - // combinational logic for addr_incr generation - always_comb begin : blkHead - unique case (State) - 0 : addr_incr = 0; - 1 : addr_incr = $HEAD_INCR_SIMD$; - 2 : addr_incr = $HEAD_INCR_KW$; - 3 : addr_incr = $HEAD_INCR_KH$; - 4 : addr_incr = $HEAD_INCR_W$; - 5 : addr_incr = $HEAD_INCR_H$; - endcase - end - - // combinational logic for tail_incr generation - uwire tail_incr_inner_condition = IS_DEPTHWISE? (Counter_loop_kh >= 0) : 0; - assign tail_incr = - tail_incr_inner_condition? 1 : - Counter_loop_w >= 0? $TAIL_INCR_W$ : - Counter_loop_h >= 0? $TAIL_INCR_H$ : - /* else */ $TAIL_INCR_LAST$; - - // combinational next state logic - always_comb begin : blkState - state_next = State; - if(State != $INNERMOST_STATE$) state_next = $INNERMOST_STATE$; - else begin - if(Counter_loop_simd < 0) begin - state_next = - (Counter_loop_kw >= 0)? STATE_LOOP_KW : - (Counter_loop_kh >= 0)? STATE_LOOP_KH : - (Counter_loop_w >= 0)? STATE_LOOP_W : - (Counter_loop_h >= 0)? STATE_LOOP_H : - /* else */ STATE_START; - end - end - end : blkState - - // sequential logic - always_ff @ (posedge clk) begin - if(!rst_n) begin - State <= $INNERMOST_STATE$; - Counter_loop_h <= LOOP_H_ITERATIONS; - Counter_loop_w <= LOOP_W_ITERATIONS; - Counter_loop_kh <= LOOP_KH_ITERATIONS; - Counter_loop_kw <= LOOP_KW_ITERATIONS; - Counter_loop_simd <= LOOP_SIMD_ITERATIONS; - end - else if(advance) begin - State <= state_next; - if (State == $INNERMOST_STATE$) begin - if(Counter_loop_simd >= 0) Counter_loop_simd <= Counter_loop_simd-1; - else begin - Counter_loop_simd <= LOOP_SIMD_ITERATIONS; - if(Counter_loop_kw >= 0) Counter_loop_kw <= Counter_loop_kw-1; - else begin - Counter_loop_kw <= LOOP_KW_ITERATIONS; - if(Counter_loop_kh >= 0) Counter_loop_kh <= Counter_loop_kh-1; - else begin - Counter_loop_kh <= LOOP_KH_ITERATIONS; - if(Counter_loop_w >= 0) Counter_loop_w <= Counter_loop_w-1; - else begin - Counter_loop_w <= LOOP_W_ITERATIONS; - if(Counter_loop_h >= 0) Counter_loop_h <= Counter_loop_h-1; - else Counter_loop_h <= LOOP_H_ITERATIONS; - end - end - end - end - end - end - end - -endmodule : $TOP_MODULE_NAME$_controller - -module $TOP_MODULE_NAME$_cyclic_buffer_addressable #( - int unsigned WIDTH, - int unsigned DEPTH -)( - input logic clk, - - input logic write_enable, - input logic [$clog2(DEPTH)-1:0] write_addr, - input logic [WIDTH-1:0] data_in, - - input logic read_enable, - input logic [$clog2(DEPTH)-1:0] read_addr, // absolute (!) read address of cyclic buffer - output logic [WIDTH-1:0] data_out -); - - $RAM_STYLE$ logic [WIDTH-1:0] Ram[DEPTH]; - logic [WIDTH-1:0] Out = 'x; - always_ff @(posedge clk) begin - if (read_enable) Out <= Ram[read_addr]; - if (write_enable) Ram[write_addr] <= data_in; - end - assign data_out = Out; - -endmodule : $TOP_MODULE_NAME$_cyclic_buffer_addressable - module $TOP_MODULE_NAME$_impl #( int BIT_WIDTH, int SIMD, @@ -197,9 +62,10 @@ module $TOP_MODULE_NAME$_impl #( uwire window_buffer_read_enable; uwire [$clog2(BUF_ELEM_TOTAL)-1:0] window_buffer_write_addr; uwire [$clog2(BUF_ELEM_TOTAL)-1:0] window_buffer_read_addr; - $TOP_MODULE_NAME$_cyclic_buffer_addressable #( + swg_cyclic_buffer_addressable #( .WIDTH(BUF_IN_WIDTH), - .DEPTH(BUF_ELEM_TOTAL) + .DEPTH(BUF_ELEM_TOTAL), + .RAM_STYLE($RAM_STYLE$) ) window_buffer_inst ( .clk(ap_clk), @@ -216,7 +82,25 @@ module $TOP_MODULE_NAME$_impl #( uwire advance_controller; uwire signed [INCR_BITWIDTH-1:0] addr_incr; uwire [INCR_BITWIDTH-1:0] tail_incr; - $TOP_MODULE_NAME$_controller controller_inst ( + swg_controller #( + .LOOP_H_ITERATIONS($LOOP_H_ITERATIONS$), + .LOOP_W_ITERATIONS($LOOP_W_ITERATIONS$), + .LOOP_KH_ITERATIONS($LOOP_KH_ITERATIONS$), + .LOOP_KW_ITERATIONS($LOOP_KW_ITERATIONS$), + .LOOP_SIMD_ITERATIONS($LOOP_SIMD_ITERATIONS$), + .HEAD_INCR_SIMD($HEAD_INCR_SIMD$), + .HEAD_INCR_KW($HEAD_INCR_KW$), + .HEAD_INCR_KH($HEAD_INCR_KH$), + .HEAD_INCR_W($HEAD_INCR_W$), + .HEAD_INCR_H($HEAD_INCR_H$), + .TAIL_INCR_W($TAIL_INCR_W$), + .TAIL_INCR_H($TAIL_INCR_H$), + .TAIL_INCR_LAST($TAIL_INCR_LAST$), + .INCR_BITWIDTH($INCR_BITWIDTH$), + .IS_DEPTHWISE($IS_DEPTHWISE$), + .INNERMOST_STATE($INNERMOST_STATE$) + ) + controller_inst ( .clk(ap_clk), .rst_n(ap_rst_n), .advance(advance_controller), diff --git a/finn-rtllib/swg/swg_template_default_dynamic.sv b/finn-rtllib/swg/swg_template_default_dynamic.sv index eb53978b58..412f8689ba 100644 --- a/finn-rtllib/swg/swg_template_default_dynamic.sv +++ b/finn-rtllib/swg/swg_template_default_dynamic.sv @@ -152,31 +152,6 @@ module $TOP_MODULE_NAME$_controller #( endmodule : $TOP_MODULE_NAME$_controller -module $TOP_MODULE_NAME$_cyclic_buffer_addressable #( - int unsigned WIDTH, - int unsigned DEPTH -)( - input logic clk, - - input logic write_enable, - input logic [$clog2(DEPTH)-1:0] write_addr, - input logic [WIDTH-1:0] data_in, - - input logic read_enable, - input logic [$clog2(DEPTH)-1:0] read_addr, // absolute (!) read address of cyclic buffer - output logic [WIDTH-1:0] data_out -); - - $RAM_STYLE$ logic [WIDTH-1:0] Ram[DEPTH]; - logic [WIDTH-1:0] Out = 'x; - always_ff @(posedge clk) begin - if (read_enable) Out <= Ram[read_addr]; - if (write_enable) Ram[write_addr] <= data_in; - end - assign data_out = Out; - -endmodule : $TOP_MODULE_NAME$_cyclic_buffer_addressable - module $TOP_MODULE_NAME$_impl #( int BIT_WIDTH, int SIMD, @@ -242,9 +217,10 @@ module $TOP_MODULE_NAME$_impl #( uwire window_buffer_read_enable; uwire [$clog2(BUF_ELEM_TOTAL)-1:0] window_buffer_write_addr; uwire [$clog2(BUF_ELEM_TOTAL)-1:0] window_buffer_read_addr; - $TOP_MODULE_NAME$_cyclic_buffer_addressable #( + swg_cyclic_buffer_addressable #( .WIDTH(BUF_IN_WIDTH), - .DEPTH(BUF_ELEM_TOTAL) + .DEPTH(BUF_ELEM_TOTAL), + .RAM_STYLE($RAM_STYLE$) ) window_buffer_inst ( .clk(ap_clk), diff --git a/finn-rtllib/swg/swg_template_parallel.sv b/finn-rtllib/swg/swg_template_parallel.sv index 767f9c6f85..9fe0f2c5ab 100644 --- a/finn-rtllib/swg/swg_template_parallel.sv +++ b/finn-rtllib/swg/swg_template_parallel.sv @@ -28,217 +28,22 @@ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ -module $TOP_MODULE_NAME$_controller #( - int unsigned LOOP_H_ITERATIONS = $LOOP_H_ITERATIONS$, - int unsigned LOOP_W_ITERATIONS = $LOOP_W_ITERATIONS$, - int unsigned LOOP_KH_ITERATIONS = $LOOP_KH_ITERATIONS$, - int unsigned LOOP_KW_ITERATIONS = $LOOP_KW_ITERATIONS$, - int unsigned LOOP_SIMD_ITERATIONS = $LOOP_SIMD_ITERATIONS$, - - int unsigned INCR_BITWIDTH = $INCR_BITWIDTH$, - - bit IS_DEPTHWISE = $IS_DEPTHWISE$ -)( - input logic clk, - input logic rst_n, - - input logic advance, - output logic [INCR_BITWIDTH-1:0] addr_incr, - output logic [INCR_BITWIDTH-1:0] tail_incr -); - - // state and counters - typedef enum logic [2:0] { - STATE_START, - STATE_LOOP_SIMD, - STATE_LOOP_KW, - STATE_LOOP_KH, - STATE_LOOP_W, - STATE_LOOP_H - } state_e; - state_e State = $INNERMOST_STATE$; - state_e state_next; - - logic signed [$clog2(LOOP_H_ITERATIONS +2)+1-1:0] Counter_loop_h = LOOP_H_ITERATIONS; - logic signed [$clog2(LOOP_W_ITERATIONS +2)+1-1:0] Counter_loop_w = LOOP_W_ITERATIONS; - logic signed [$clog2(LOOP_KH_ITERATIONS +2)+1-1:0] Counter_loop_kh = LOOP_KH_ITERATIONS; - logic signed [$clog2(LOOP_KW_ITERATIONS +2)+1-1:0] Counter_loop_kw = LOOP_KW_ITERATIONS; - logic signed [$clog2(LOOP_SIMD_ITERATIONS+2)+1-1:0] Counter_loop_simd = LOOP_SIMD_ITERATIONS; - - // combinational logic for addr_incr generation - always_comb begin : blkHead - unique case (State) - 0 : addr_incr = 0; - 1 : addr_incr = $HEAD_INCR_SIMD$; - 2 : addr_incr = $HEAD_INCR_KW$; - 3 : addr_incr = $HEAD_INCR_KH$; - 4 : addr_incr = $HEAD_INCR_W$; - 5 : addr_incr = $HEAD_INCR_H$; - endcase - end - - // combinational logic for tail_incr generation - uwire tail_incr_inner_condition = IS_DEPTHWISE? (Counter_loop_kh >= 0) : 0; - assign tail_incr = - tail_incr_inner_condition? 1 : - Counter_loop_w >= 0? $TAIL_INCR_W$ : - Counter_loop_h >= 0? $TAIL_INCR_H$ : - /* else */ $TAIL_INCR_LAST$; - - // combinational next state logic - always_comb begin : blkState - state_next = State; - if(State != $INNERMOST_STATE$) state_next = $INNERMOST_STATE$; - else begin - if(Counter_loop_simd < 0) begin - state_next = - (Counter_loop_kw >= 0)? STATE_LOOP_KW : - (Counter_loop_kh >= 0)? STATE_LOOP_KH : - (Counter_loop_w >= 0)? STATE_LOOP_W : - (Counter_loop_h >= 0)? STATE_LOOP_H : - /* else */ STATE_START; - end - end - end : blkState - - // sequential logic - always_ff @ (posedge clk) begin - if(!rst_n) begin - State <= $INNERMOST_STATE$; - Counter_loop_h <= LOOP_H_ITERATIONS; - Counter_loop_w <= LOOP_W_ITERATIONS; - Counter_loop_kh <= LOOP_KH_ITERATIONS; - Counter_loop_kw <= LOOP_KW_ITERATIONS; - Counter_loop_simd <= LOOP_SIMD_ITERATIONS; - end - else if(advance) begin - State <= state_next; - if (State == $INNERMOST_STATE$) begin - if(Counter_loop_simd >= 0) Counter_loop_simd <= Counter_loop_simd-1; - else begin - Counter_loop_simd <= LOOP_SIMD_ITERATIONS; - if(Counter_loop_kw >= 0) Counter_loop_kw <= Counter_loop_kw-1; - else begin - Counter_loop_kw <= LOOP_KW_ITERATIONS; - if(Counter_loop_kh >= 0) Counter_loop_kh <= Counter_loop_kh-1; - else begin - Counter_loop_kh <= LOOP_KH_ITERATIONS; - if(Counter_loop_w >= 0) Counter_loop_w <= Counter_loop_w-1; - else begin - Counter_loop_w <= LOOP_W_ITERATIONS; - if(Counter_loop_h >= 0) Counter_loop_h <= Counter_loop_h-1; - else Counter_loop_h <= LOOP_H_ITERATIONS; - end - end - end - end - end - end - end - -endmodule : $TOP_MODULE_NAME$_controller - -module $TOP_MODULE_NAME$_reg_buffer -#( - parameter WIDTH = 1, - parameter DEPTH = 1 -) -( - CLK, - shift_enable, - shift_in, - shift_out, - data_out -); - -input CLK, shift_enable; -input [WIDTH-1:0] shift_in; -output [WIDTH-1:0] shift_out; -output [WIDTH*DEPTH-1:0] data_out; - -reg [WIDTH-1:0] data [DEPTH-1:0]; - -assign shift_out = data[DEPTH-1]; - -for (genvar e=0; e0; i=i-1) - data[i] <= data[i-1]; - data[0] <= shift_in; - end -end -endmodule : $TOP_MODULE_NAME$_reg_buffer - -module $TOP_MODULE_NAME$_ram_buffer -#( - parameter WIDTH = 1, - parameter DEPTH = 1 -) -( - CLK, - RST, - shift_enable, - shift_in, - shift_out -); - -input CLK, RST, shift_enable; -input [WIDTH-1:0] shift_in; -output [WIDTH-1:0] shift_out; - -reg [WIDTH-1:0] out_reg; -assign shift_out = out_reg; - -integer addr_w, addr_r; - -$RAM_STYLE$ reg [WIDTH-1:0] ram [DEPTH-1:0]; - -always @(posedge CLK) begin - if (RST == 1'b0) begin - addr_w <= 0; - addr_r <= 1; - end else begin - if (shift_enable) begin - ram[addr_w] <= shift_in; - out_reg <= ram[addr_r]; - - if (addr_w == DEPTH-1) - addr_w <= 0; - else - addr_w <= addr_w + 1; - - if (addr_r == DEPTH-1) - addr_r <= 0; - else - addr_r <= addr_r + 1; - end - end -end -endmodule : $TOP_MODULE_NAME$_ram_buffer module $TOP_MODULE_NAME$_wb #( - parameter IN_WIDTH = 1, // bit-width*C*MMV_in - parameter OUT_ELEM_WIDTH = 1, // bit-width*C - parameter OUT_WIDTH = 1, // bit-width*C*MMV_out - parameter BUFFER_ELEM_TOTAL = 1 + int unsigned IN_WIDTH = 1, // bit-width*C*MMV_in + int unsigned OUT_ELEM_WIDTH = 1, // bit-width*C + int unsigned OUT_WIDTH = 1, // bit-width*C*MMV_out + int unsigned BUFFER_ELEM_TOTAL = 1 ) ( - CLK, - RST, - data_in, - shift_enable, - data_out + input logic CLK, + input logic RST, + input logic shift_enable, + input logic [IN_WIDTH-1:0] data_in, + output logic [OUT_WIDTH-1:0] data_out ); -input CLK, RST; -input [IN_WIDTH-1:0] data_in; -input shift_enable; -output [OUT_WIDTH-1:0] data_out; - $GENERATE_REG_FIFOS$ $GENERATE_BRAM_FIFOS$ @@ -252,15 +57,15 @@ $GENERATE_OUTPUT_MAPPING$ endmodule : $TOP_MODULE_NAME$_wb module $TOP_MODULE_NAME$_impl #( - int BIT_WIDTH, - int SIMD, - int MMV_IN, - int MMV_OUT, - int LAST_READ_ELEM = $LAST_READ_ELEM$, - int FIRST_WRITE_ELEM = $FIRST_WRITE_ELEM$, - int LAST_WRITE_ELEM = $LAST_WRITE_ELEM$, - int BUF_ELEM_TOTAL = $BUF_ELEM_TOTAL$, - int INCR_BITWIDTH = $INCR_BITWIDTH$ + int unsigned BIT_WIDTH, + int unsigned SIMD, + int unsigned MMV_IN, + int unsigned MMV_OUT, + int unsigned LAST_READ_ELEM = $LAST_READ_ELEM$, + int unsigned FIRST_WRITE_ELEM = $FIRST_WRITE_ELEM$, + int unsigned LAST_WRITE_ELEM = $LAST_WRITE_ELEM$, + int unsigned BUF_ELEM_TOTAL = $BUF_ELEM_TOTAL$, + int unsigned INCR_BITWIDTH = $INCR_BITWIDTH$ )( input logic ap_clk, input logic ap_rst_n, @@ -302,7 +107,25 @@ module $TOP_MODULE_NAME$_impl #( uwire advance_controller; uwire signed [INCR_BITWIDTH-1:0] addr_incr; uwire [INCR_BITWIDTH-1:0] tail_incr; - $TOP_MODULE_NAME$_controller controller_inst ( + swg_controller #( + .LOOP_H_ITERATIONS($LOOP_H_ITERATIONS$), + .LOOP_W_ITERATIONS($LOOP_W_ITERATIONS$), + .LOOP_KH_ITERATIONS($LOOP_KH_ITERATIONS$), + .LOOP_KW_ITERATIONS($LOOP_KW_ITERATIONS$), + .LOOP_SIMD_ITERATIONS($LOOP_SIMD_ITERATIONS$), + .HEAD_INCR_SIMD($HEAD_INCR_SIMD$), + .HEAD_INCR_KW($HEAD_INCR_KW$), + .HEAD_INCR_KH($HEAD_INCR_KH$), + .HEAD_INCR_W($HEAD_INCR_W$), + .HEAD_INCR_H($HEAD_INCR_H$), + .TAIL_INCR_W($TAIL_INCR_W$), + .TAIL_INCR_H($TAIL_INCR_H$), + .TAIL_INCR_LAST($TAIL_INCR_LAST$), + .INCR_BITWIDTH($INCR_BITWIDTH$), + .IS_DEPTHWISE($IS_DEPTHWISE$), + .INNERMOST_STATE($INNERMOST_STATE$) + ) + controller_inst ( .clk(ap_clk), .rst_n(ap_rst_n), .advance(advance_controller), @@ -318,16 +141,16 @@ module $TOP_MODULE_NAME$_impl #( // control registers/signals logic Writing_done = 0; logic Write_done = 0; + uwire write_cmd = !($signed(Current_elem) > Newest_buffered_elem) && !Writing_done;; uwire write_ok = write_cmd && (out_V_V_TREADY || Write_done); uwire write_blocked = write_cmd && !out_V_V_TREADY && !Write_done; - uwire write_cmd = !($signed(Current_elem) > Newest_buffered_elem) && !Writing_done;; uwire reading_done = Newest_buffered_elem == LAST_READ_ELEM; uwire read_cmd = !reading_done && ( // if there is still an input element left to read Writing_done || ( // if writing is done (e.g. for skipped rows at FM end due to stride) - $signed(((Newest_buffered_elem - (BUF_ELEM_TOTAL - 1)))) < $signed(First_elem_next_window) && - $signed(((Newest_buffered_elem - (BUF_ELEM_TOTAL - 1)))) < $signed(Current_elem) + $signed(((Newest_buffered_elem - ($signed(BUF_ELEM_TOTAL) - 1)))) < $signed(First_elem_next_window) && + $signed(((Newest_buffered_elem - ($signed(BUF_ELEM_TOTAL) - 1)))) < $signed(Current_elem) ) // (over-)write to buffer if oldest buffered element will no longer be needed ); uwire read_ok = read_cmd && in0_V_V_TVALID && !write_blocked; @@ -347,10 +170,15 @@ module $TOP_MODULE_NAME$_impl #( // write done logic always_ff @(posedge ap_clk) begin - if (advance) begin - Write_done <= 1'b0; //reset flag - end else if (write_ok) //successful W in this cycle, but R still outstanding - Write_done <= 1'b1; //write can happen even if read is blocked, but only for the current cycle! + if(!ap_rst_n) begin + Write_done <= 1'b0; + end + else begin + if (advance) begin + Write_done <= 1'b0; //reset flag + end else if (write_ok) //successful W in this cycle, but R still outstanding + Write_done <= 1'b1; //write can happen even if read is blocked, but only for the current cycle! + end end // main process for advancing counters diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py index 7ed3de3c19..4a8ddfee90 100755 --- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py +++ b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py @@ -29,6 +29,7 @@ import math import numpy as np import os +import shutil from qonnx.core.datatype import DataType from qonnx.custom_op.general import im2col from qonnx.custom_op.general.im2col import compute_conv_output_dim @@ -616,13 +617,13 @@ def prepare_codegen_default(self): # skip innermost SIMD loop completely if loop_kw_iterations == 1: # skip innermost KW loop completely - code_gen_dict["$INNERMOST_STATE$"] = ["STATE_LOOP_KH"] + code_gen_dict["$INNERMOST_STATE$"] = [str(3)] # STATE_LOOP_KH loop_kh_iterations -= 1 # -1 because state is initial state else: - code_gen_dict["$INNERMOST_STATE$"] = ["STATE_LOOP_KW"] + code_gen_dict["$INNERMOST_STATE$"] = [str(2)] # STATE_LOOP_KW loop_kw_iterations -= 1 # -1 because state is initial state else: - code_gen_dict["$INNERMOST_STATE$"] = ["STATE_LOOP_SIMD"] + code_gen_dict["$INNERMOST_STATE$"] = [str(1)] # STATE_LOOP_SIMD loop_simd_iterations -= 1 # -1 because state is initial state cntr_bitwidth = math.ceil( @@ -735,10 +736,10 @@ def prepare_codegen_parallel(self): loop_simd_iterations = 1 if loop_w_iterations == 1: - code_gen_dict["$INNERMOST_STATE$"] = ["STATE_LOOP_H"] + code_gen_dict["$INNERMOST_STATE$"] = [str(5)] # STATE_LOOP_H loop_h_iterations -= 1 # -1 because state is initial state else: - code_gen_dict["$INNERMOST_STATE$"] = ["STATE_LOOP_W"] + code_gen_dict["$INNERMOST_STATE$"] = [str(4)] # STATE_LOOP_W loop_w_iterations -= 1 # -1 because state is initial state # set head and tail address increment values @@ -846,7 +847,7 @@ def prepare_codegen_parallel(self): wire [IN_WIDTH-1:0] reg_fifo_{id}_in; wire [IN_WIDTH-1:0] reg_fifo_{id}_out; wire [IN_WIDTH*{len}-1:0] reg_fifo_{id}; - {name}_reg_buffer + swg_reg_buffer #( .WIDTH(IN_WIDTH), .DEPTH({len}) @@ -871,10 +872,11 @@ def prepare_codegen_parallel(self): """ wire [IN_WIDTH-1:0] bram_fifo_{id}_in; wire [IN_WIDTH-1:0] bram_fifo_{id}_out; - {name}_ram_buffer + swg_ram_buffer #( .WIDTH(IN_WIDTH), - .DEPTH({len}) + .DEPTH({len}), + .RAM_STYLE("{ram_style}") ) ram_buffer_inst_{id} ( @@ -887,6 +889,7 @@ def prepare_codegen_parallel(self): name=self.get_verilog_top_module_name(), id=i, len=bram_fifo_depth, + ram_style=self.get_nodeattr("ram_style") ) ) @@ -1012,10 +1015,7 @@ def generate_hdl(self): self.set_nodeattr("gen_top_module", self.get_verilog_top_module_name()) code_gen_dict["$BIT_WIDTH$"] = [str(self.get_input_datatype().bitwidth())] ram_style = self.get_nodeattr("ram_style") - if ram_style == "auto": - code_gen_dict["$RAM_STYLE$"] = [""] - else: - code_gen_dict["$RAM_STYLE$"] = ['(* ram_style = "{}" *)'.format(ram_style)] + code_gen_dict["$RAM_STYLE$"] = ["\"{}\"".format(ram_style)] # apply code generation to templates code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") @@ -1062,6 +1062,9 @@ def generate_hdl(self): ) as f: f.write(template_axilite) + # Copy static source file for common core components + shutil.copy2(os.environ["FINN_ROOT"] + "/finn-rtllib/swg/swg_common.sv", code_gen_dir) + # set ipgen_path and ip_path so that HLS-Synth transformation # and stich_ip transformation do not complain self.set_nodeattr("ipgen_path", code_gen_dir) @@ -1081,6 +1084,7 @@ def prepare_rtlsim(self): verilog_files = [ self.get_nodeattr("gen_top_module") + "_wrapper.v", self.get_nodeattr("gen_top_module") + "_impl.sv", + "swg_common.sv" ] if self.get_nodeattr("dynamic_mode"): verilog_files.append(self.get_nodeattr("gen_top_module") + "_axilite.v") @@ -1104,6 +1108,7 @@ def code_generation_ipi(self): sourcefiles = [ self.get_nodeattr("gen_top_module") + "_wrapper.v", self.get_nodeattr("gen_top_module") + "_impl.sv", + "swg_common.sv" ] if self.get_nodeattr("dynamic_mode"): From f94e1cbdca5cfdf2f299d3d072b85fc36406d4df Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 15 Mar 2023 11:43:30 +0000 Subject: [PATCH 089/665] [CustomOp] pre-commit on rtl swg --- .../convolutioninputgenerator_rtl.py | 24 +++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py index 4a8ddfee90..5fe578e99c 100755 --- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py +++ b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py @@ -617,13 +617,13 @@ def prepare_codegen_default(self): # skip innermost SIMD loop completely if loop_kw_iterations == 1: # skip innermost KW loop completely - code_gen_dict["$INNERMOST_STATE$"] = [str(3)] # STATE_LOOP_KH + code_gen_dict["$INNERMOST_STATE$"] = [str(3)] # STATE_LOOP_KH loop_kh_iterations -= 1 # -1 because state is initial state else: - code_gen_dict["$INNERMOST_STATE$"] = [str(2)] # STATE_LOOP_KW + code_gen_dict["$INNERMOST_STATE$"] = [str(2)] # STATE_LOOP_KW loop_kw_iterations -= 1 # -1 because state is initial state else: - code_gen_dict["$INNERMOST_STATE$"] = [str(1)] # STATE_LOOP_SIMD + code_gen_dict["$INNERMOST_STATE$"] = [str(1)] # STATE_LOOP_SIMD loop_simd_iterations -= 1 # -1 because state is initial state cntr_bitwidth = math.ceil( @@ -736,10 +736,10 @@ def prepare_codegen_parallel(self): loop_simd_iterations = 1 if loop_w_iterations == 1: - code_gen_dict["$INNERMOST_STATE$"] = [str(5)] # STATE_LOOP_H + code_gen_dict["$INNERMOST_STATE$"] = [str(5)] # STATE_LOOP_H loop_h_iterations -= 1 # -1 because state is initial state else: - code_gen_dict["$INNERMOST_STATE$"] = [str(4)] # STATE_LOOP_W + code_gen_dict["$INNERMOST_STATE$"] = [str(4)] # STATE_LOOP_W loop_w_iterations -= 1 # -1 because state is initial state # set head and tail address increment values @@ -860,7 +860,6 @@ def prepare_codegen_parallel(self): .shift_out(reg_fifo_{id}_out), .data_out(reg_fifo_{id}) );""".format( - name=self.get_verilog_top_module_name(), id=i, len=len(reg_fifo), ) @@ -886,10 +885,9 @@ def prepare_codegen_parallel(self): .shift_in(bram_fifo_{id}_in), .shift_out(bram_fifo_{id}_out) );""".format( - name=self.get_verilog_top_module_name(), id=i, len=bram_fifo_depth, - ram_style=self.get_nodeattr("ram_style") + ram_style=self.get_nodeattr("ram_style"), ) ) @@ -1015,7 +1013,7 @@ def generate_hdl(self): self.set_nodeattr("gen_top_module", self.get_verilog_top_module_name()) code_gen_dict["$BIT_WIDTH$"] = [str(self.get_input_datatype().bitwidth())] ram_style = self.get_nodeattr("ram_style") - code_gen_dict["$RAM_STYLE$"] = ["\"{}\"".format(ram_style)] + code_gen_dict["$RAM_STYLE$"] = ['"{}"'.format(ram_style)] # apply code generation to templates code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") @@ -1063,7 +1061,9 @@ def generate_hdl(self): f.write(template_axilite) # Copy static source file for common core components - shutil.copy2(os.environ["FINN_ROOT"] + "/finn-rtllib/swg/swg_common.sv", code_gen_dir) + shutil.copy2( + os.environ["FINN_ROOT"] + "/finn-rtllib/swg/swg_common.sv", code_gen_dir + ) # set ipgen_path and ip_path so that HLS-Synth transformation # and stich_ip transformation do not complain @@ -1084,7 +1084,7 @@ def prepare_rtlsim(self): verilog_files = [ self.get_nodeattr("gen_top_module") + "_wrapper.v", self.get_nodeattr("gen_top_module") + "_impl.sv", - "swg_common.sv" + "swg_common.sv", ] if self.get_nodeattr("dynamic_mode"): verilog_files.append(self.get_nodeattr("gen_top_module") + "_axilite.v") @@ -1108,7 +1108,7 @@ def code_generation_ipi(self): sourcefiles = [ self.get_nodeattr("gen_top_module") + "_wrapper.v", self.get_nodeattr("gen_top_module") + "_impl.sv", - "swg_common.sv" + "swg_common.sv", ] if self.get_nodeattr("dynamic_mode"): From 71ea7485fa9cc00f84cc5a9f9afe41776f109e35 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 15 Mar 2023 16:59:44 +0000 Subject: [PATCH 090/665] [Builder] infer data types after bit width minimization --- src/finn/builder/build_dataflow_steps.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/finn/builder/build_dataflow_steps.py b/src/finn/builder/build_dataflow_steps.py index ba5a23f411..e43a29d632 100644 --- a/src/finn/builder/build_dataflow_steps.py +++ b/src/finn/builder/build_dataflow_steps.py @@ -488,6 +488,8 @@ def step_minimize_bit_width(model: ModelWrapper, cfg: DataflowBuildConfig): if cfg.minimize_bit_width: model = model.transform(MinimizeWeightBitWidth()) model = model.transform(MinimizeAccumulatorWidth()) + # make sure the changed datatypes are propagated through the network + model = model.transform(InferDataTypes()) return model From 24bd19072c4631c842d4142b695cf4819abecc6e Mon Sep 17 00:00:00 2001 From: Felix Jentzsch Date: Thu, 23 Mar 2023 15:30:23 +0100 Subject: [PATCH 091/665] [SWG] Incorporate minor comments on Verilog code --- finn-rtllib/swg/swg_common.sv | 55 ++++++++++--------- finn-rtllib/swg/swg_template_parallel.sv | 8 +-- .../convolutioninputgenerator_rtl.py | 6 +- 3 files changed, 35 insertions(+), 34 deletions(-) diff --git a/finn-rtllib/swg/swg_common.sv b/finn-rtllib/swg/swg_common.sv index 8dfb8f51a2..ff6778973c 100644 --- a/finn-rtllib/swg/swg_common.sv +++ b/finn-rtllib/swg/swg_common.sv @@ -185,25 +185,25 @@ module swg_reg_buffer int unsigned DEPTH = 1 ) ( - input logic CLK, + input logic clk, input logic shift_enable, input logic [WIDTH-1:0] shift_in, output logic [WIDTH-1:0] shift_out, output logic [WIDTH*DEPTH-1:0] data_out ); -reg [WIDTH-1:0] data [DEPTH-1:0]; +logic [WIDTH-1:0] Data [DEPTH-1:0]; -assign shift_out = data[DEPTH-1]; +assign shift_out = Data[DEPTH-1]; -for (genvar e=0; e0; i=i-1) - data[i] <= data[i-1]; - data[0] <= shift_in; + for (int i=DEPTH-1; i>0; i--) + Data[i] <= Data[i-1]; + Data[0] <= shift_in; end end endmodule : swg_reg_buffer @@ -216,38 +216,39 @@ module swg_ram_buffer parameter RAM_STYLE = "auto" ) ( - input logic CLK, - input logic RST, + input logic clk, + input logic rst_n, input logic shift_enable, input logic [WIDTH-1:0] shift_in, output logic [WIDTH-1:0] shift_out ); -reg [WIDTH-1:0] out_reg; -assign shift_out = out_reg; +logic [WIDTH-1:0] Out_reg; +assign shift_out = Out_reg; -integer addr_w, addr_r; +logic [$clog2(DEPTH)-1:0] Addr_w = 0; +logic [$clog2(DEPTH)-1:0] Addr_r = 0; -(*ram_style=RAM_STYLE*) reg [WIDTH-1:0] ram [DEPTH-1:0]; +(*ram_style=RAM_STYLE*) logic [WIDTH-1:0] Ram [DEPTH-1:0]; -always @(posedge CLK) begin - if (RST == 1'b0) begin - addr_w <= 0; - addr_r <= 1; +always_ff @(posedge clk) begin + if (rst_n == 1'b0) begin + Addr_w <= 0; + Addr_r <= 1; end else begin if (shift_enable) begin - ram[addr_w] <= shift_in; - out_reg <= ram[addr_r]; + Ram[Addr_w] <= shift_in; + Out_reg <= Ram[Addr_r]; - if (addr_w == DEPTH-1) - addr_w <= 0; + if (Addr_w == DEPTH-1) + Addr_w <= 0; else - addr_w <= addr_w + 1; + Addr_w <= Addr_w + 1; - if (addr_r == DEPTH-1) - addr_r <= 0; + if (Addr_r == DEPTH-1) + Addr_r <= 0; else - addr_r <= addr_r + 1; + Addr_r <= Addr_r + 1; end end end diff --git a/finn-rtllib/swg/swg_template_parallel.sv b/finn-rtllib/swg/swg_template_parallel.sv index 9fe0f2c5ab..b55a51e400 100644 --- a/finn-rtllib/swg/swg_template_parallel.sv +++ b/finn-rtllib/swg/swg_template_parallel.sv @@ -37,8 +37,8 @@ module $TOP_MODULE_NAME$_wb int unsigned BUFFER_ELEM_TOTAL = 1 ) ( - input logic CLK, - input logic RST, + input logic clk, + input logic rst_n, input logic shift_enable, input logic [IN_WIDTH-1:0] data_in, output logic [OUT_WIDTH-1:0] data_out @@ -96,8 +96,8 @@ module $TOP_MODULE_NAME$_impl #( ) window_buffer_inst ( - .CLK(ap_clk), - .RST(ap_rst_n), + .clk(ap_clk), + .rst_n(ap_rst_n), .data_in(window_buffer_in), .shift_enable(window_buffer_shift_enable), .data_out(window_buffer_out) diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py index 5fe578e99c..77a435640c 100755 --- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py +++ b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py @@ -854,7 +854,7 @@ def prepare_codegen_parallel(self): ) reg_buffer_inst_{id} ( - .CLK(CLK), + .clk(clk), .shift_enable(shift_enable), .shift_in(reg_fifo_{id}_in), .shift_out(reg_fifo_{id}_out), @@ -879,8 +879,8 @@ def prepare_codegen_parallel(self): ) ram_buffer_inst_{id} ( - .CLK(CLK), - .RST(RST), + .clk(clk), + .rst_n(rst_n), .shift_enable(shift_enable), .shift_in(bram_fifo_{id}_in), .shift_out(bram_fifo_{id}_out) From 12fac2e87ee1de47b75f882bf8ffc0851e91eaa3 Mon Sep 17 00:00:00 2001 From: Felix Jentzsch Date: Fri, 24 Mar 2023 10:54:56 +0100 Subject: [PATCH 092/665] Add support for RFSoC 4x2 board --- fetch-repos.sh | 7 ++++++- src/finn/transformation/fpgadataflow/templates.py | 3 +++ src/finn/util/basic.py | 2 ++ 3 files changed, 11 insertions(+), 1 deletion(-) diff --git a/fetch-repos.sh b/fetch-repos.sh index 1e01a058ff..03aa68c43b 100755 --- a/fetch-repos.sh +++ b/fetch-repos.sh @@ -36,8 +36,9 @@ HLSLIB_COMMIT="c17aa478ae574971d115afa9fa4d9c215857d1ac" OMX_COMMIT="d1065a788219ca0eb54d5e57600b1f9d7f67d4cc" AVNET_BDF_COMMIT="2d49cfc25766f07792c0b314489f21fe916b639b" XIL_BDF_COMMIT="8cf4bb674a919ac34e3d99d8d71a9e60af93d14e" +RFSOC4x2_BDF_COMMIT="13fb6f6c02c7dfd7e4b336b18b959ad5115db696" KV260_BDF_COMMIT="98e0d3efc901f0b974006bc4370c2a7ad8856c79" -EXP_BOARD_FILES_MD5="30eecc497c31050bd46d10ea20eba232" +EXP_BOARD_FILES_MD5="226ca927a16ea4ce579f1332675e9e9a" QONNX_URL="https://github.com/fastmachinelearning/qonnx.git" FINN_EXP_URL="https://github.com/Xilinx/finn-experimental.git" @@ -48,6 +49,7 @@ HLSLIB_URL="https://github.com/Xilinx/finn-hlslib.git" OMX_URL="https://github.com/maltanar/oh-my-xilinx.git" AVNET_BDF_URL="https://github.com/Avnet/bdf.git" XIL_BDF_URL="https://github.com/Xilinx/XilinxBoardStore.git" +RFSOC4x2_BDF_URL="https://github.com/RealDigitalOrg/RFSoC4x2-BSP.git" KV260_BDF_URL="https://github.com/Xilinx/XilinxBoardStore.git" QONNX_DIR="qonnx" @@ -59,6 +61,7 @@ HLSLIB_DIR="finn-hlslib" OMX_DIR="oh-my-xilinx" AVNET_BDF_DIR="avnet-bdf" XIL_BDF_DIR="xil-bdf" +RFSOC4x2_BDF_DIR="rfsoc4x2-bdf" KV260_SOM_BDF_DIR="kv260-som-bdf" # absolute path to this script, e.g. /home/user/bin/foo.sh @@ -107,6 +110,7 @@ fetch_board_files() { unzip -q pynq-z2.zip cp -r $SCRIPTPATH/deps/$AVNET_BDF_DIR/* $SCRIPTPATH/deps/board_files/ cp -r $SCRIPTPATH/deps/$XIL_BDF_DIR/boards/Xilinx/rfsoc2x2 $SCRIPTPATH/deps/board_files/; + cp -r $SCRIPTPATH/deps/$RFSOC4x2_BDF_DIR/board_files/rfsoc4x2 $SCRIPTPATH/deps/board_files/; cp -r $SCRIPTPATH/deps/$KV260_SOM_BDF_DIR/boards/Xilinx/kv260_som $SCRIPTPATH/deps/board_files/; cd $OLD_PWD } @@ -120,6 +124,7 @@ fetch_repo $HLSLIB_URL $HLSLIB_COMMIT $HLSLIB_DIR fetch_repo $OMX_URL $OMX_COMMIT $OMX_DIR fetch_repo $AVNET_BDF_URL $AVNET_BDF_COMMIT $AVNET_BDF_DIR fetch_repo $XIL_BDF_URL $XIL_BDF_COMMIT $XIL_BDF_DIR +fetch_repo $RFSOC4x2_BDF_URL $RFSOC4x2_BDF_COMMIT $RFSOC4x2_BDF_DIR fetch_repo $KV260_BDF_URL $KV260_BDF_COMMIT $KV260_SOM_BDF_DIR # download extra Pynq board files and extract if needed diff --git a/src/finn/transformation/fpgadataflow/templates.py b/src/finn/transformation/fpgadataflow/templates.py index f52bad0ffb..aed90d381a 100644 --- a/src/finn/transformation/fpgadataflow/templates.py +++ b/src/finn/transformation/fpgadataflow/templates.py @@ -117,6 +117,9 @@ } elseif {$BOARD == "RFSoC2x2"} { set_property board_part xilinx.com:rfsoc2x2:part0:1.1 [current_project] set ZYNQ_TYPE "zynq_us+" +} elseif {$BOARD == "RFSoC4x2"} { + set_property board_part realdigital.org:rfsoc4x2:part0:1.0 [current_project] + set ZYNQ_TYPE "zynq_us+" } elseif {$BOARD == "Ultra96"} { set_property board_part avnet.com:ultra96v1:part0:1.2 [current_project] set ZYNQ_TYPE "zynq_us+" diff --git a/src/finn/util/basic.py b/src/finn/util/basic.py index 3bc5b803db..28478848d0 100644 --- a/src/finn/util/basic.py +++ b/src/finn/util/basic.py @@ -40,6 +40,7 @@ pynq_part_map["ZCU104"] = "xczu7ev-ffvc1156-2-e" pynq_part_map["ZCU111"] = "xczu28dr-ffvg1517-2-e" pynq_part_map["RFSoC2x2"] = "xczu28dr-ffvg1517-2-e" +pynq_part_map["RFSoC4x2"] = "xczu48dr-ffvg1517-2-e" pynq_part_map["KV260_SOM"] = "xck26-sfvc784-2LV-c" @@ -52,6 +53,7 @@ pynq_native_port_width["ZCU104"] = 128 pynq_native_port_width["ZCU111"] = 128 pynq_native_port_width["RFSoC2x2"] = 128 +pynq_native_port_width["RFSoC4x2"] = 128 pynq_native_port_width["KV260_SOM"] = 128 # Alveo device and platform mappings From ad4678a4d460814444a6368a206b7ff5559876d0 Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Mon, 3 Apr 2023 15:35:47 +0100 Subject: [PATCH 093/665] [jenkins] add node label to Jenkinsfile Signed-off-by: Fionn O'Donohoe --- docker/jenkins/Jenkinsfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index e3e5b5f7f9..2e195d105e 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -1,4 +1,4 @@ -node { +node('finn-build') { def app stage('Clone repository') { /* Let's make sure we have the repository cloned to our workspace */ From a14bf7ea9e41c1dc5b21bf18bcb8e04105803b41 Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Tue, 4 Apr 2023 15:31:09 +0100 Subject: [PATCH 094/665] [jenkins] introduce basic declaritive pipeline Signed-off-by: Fionn O'Donohoe --- docker/jenkins/Jenkinsfile | 67 +++++++++++++------------------------- 1 file changed, 22 insertions(+), 45 deletions(-) diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index 2e195d105e..fee116da3a 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -1,46 +1,23 @@ -node('finn-build') { - def app - stage('Clone repository') { - /* Let's make sure we have the repository cloned to our workspace */ - checkout scm +pipeline { + agent { node { label 'finn-build' } } + environment { + FINN_XILINX_PATH="/proj/xbuilds/SWIP/2022.1_0420_0327/installs/lin64" + FINN_XILINX_VERSION="2022.1" + FINN_DOCKER_TAG="xilinx/finn:jenkins" + FINN_HOST_BUILD_DIR="/scratch/users/finn_ci" + PLATFORM_REPO_PATHS="/opt/xilinx/platforms" + } + stages { + stage('Quicktest') { + steps { + sh 'echo "Hello FINN"' + sh 'hostname' + sh 'whoami' + sh 'pwd' + sh 'docker login' + sh 'printenv | sort' + sh 'run-docker.sh quicktest' + } } - withEnv([ - "FINN_XILINX_PATH=/proj/xbuilds/SWIP/2022.1_0420_0327/installs/lin64", - "FINN_XILINX_VERSION=2022.1", - "FINN_DOCKER_TAG=xilinx/finn:jenkins", - "FINN_HOST_BUILD_DIR=/scratch/users/finn_ci", - "PLATFORM_REPO_PATHS=/opt/xilinx/platforms" - ]){ - parallel firstBranch: { - stage('Brevitas export') { - dir("${env.WORKSPACE}") { - sh("bash run-docker.sh python setup.py test --addopts -mbrevitas_export") - } - } - }, secondBranch: { - stage('Streamlining transformations') { - dir("${env.WORKSPACE}") { - sh("bash run-docker.sh python setup.py test --addopts -mstreamline") - } - } - }, thirdBranch: { - stage('Util functions') { - dir("${env.WORKSPACE}") { - sh("bash run-docker.sh python setup.py test --addopts -mutil") - } - } - }, fourthBranch: { - stage('General transformations') { - dir("${env.WORKSPACE}") { - sh("bash run-docker.sh python setup.py test --addopts -mtransform") - } - } - }, fifthBranch: { - stage('Fpgadataflow transformations and simulations') { - dir("${env.WORKSPACE}") { - sh("bash run-docker.sh python setup.py test --addopts -mfpgadataflow") - } - } - } - } -} + } +} \ No newline at end of file From 60033063c3ca57542120e8b49b1f2baf374ebfe3 Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Tue, 4 Apr 2023 16:08:35 +0100 Subject: [PATCH 095/665] [jenkins] move into the test dir before running quicktest Signed-off-by: Fionn O'Donohoe --- docker/jenkins/Jenkinsfile | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index fee116da3a..dfe8b42f58 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -10,13 +10,15 @@ pipeline { stages { stage('Quicktest') { steps { - sh 'echo "Hello FINN"' - sh 'hostname' - sh 'whoami' - sh 'pwd' - sh 'docker login' - sh 'printenv | sort' - sh 'run-docker.sh quicktest' + dir("finn") { + sh 'echo "Hello FINN"' + sh 'hostname' + sh 'whoami' + sh 'pwd' + sh 'docker login' + sh 'printenv | sort' + sh './run-docker.sh quicktest' + } } } } From da54e373e3be095804533648e39273366b42aef8 Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Tue, 4 Apr 2023 16:09:44 +0100 Subject: [PATCH 096/665] [jenkins] keep 30 builds in build history Signed-off-by: Fionn O'Donohoe --- docker/jenkins/Jenkinsfile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index dfe8b42f58..db0bf15815 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -1,4 +1,7 @@ pipeline { + options { + buildDiscarder(logRotator(numToKeepStr: '30', artifactNumToKeepStr: '30')) + } agent { node { label 'finn-build' } } environment { FINN_XILINX_PATH="/proj/xbuilds/SWIP/2022.1_0420_0327/installs/lin64" From da57f9bcdbfac83e8b2f9545a74582ccdb2c2d4c Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Tue, 4 Apr 2023 16:19:49 +0100 Subject: [PATCH 097/665] Revert "[jenkins] move into the test dir before running quicktest" This reverts commit 60033063c3ca57542120e8b49b1f2baf374ebfe3. --- docker/jenkins/Jenkinsfile | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index db0bf15815..1497c5f843 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -13,15 +13,13 @@ pipeline { stages { stage('Quicktest') { steps { - dir("finn") { - sh 'echo "Hello FINN"' - sh 'hostname' - sh 'whoami' - sh 'pwd' - sh 'docker login' - sh 'printenv | sort' - sh './run-docker.sh quicktest' - } + sh 'echo "Hello FINN"' + sh 'hostname' + sh 'whoami' + sh 'pwd' + sh 'docker login' + sh 'printenv | sort' + sh 'run-docker.sh quicktest' } } } From 0d3d69228b5d816a156e30acc11b9e1b48d220a0 Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Tue, 4 Apr 2023 16:22:24 +0100 Subject: [PATCH 098/665] [jenkins] the './' was necessary to run the test, not moving into a new directory Signed-off-by: Fionn O'Donohoe --- docker/jenkins/Jenkinsfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index 1497c5f843..2107524169 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -19,7 +19,7 @@ pipeline { sh 'pwd' sh 'docker login' sh 'printenv | sort' - sh 'run-docker.sh quicktest' + sh './run-docker.sh quicktest' } } } From c6ee5a6f0b29fde7acf426cd54bdf0d3cd03a596 Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 4 Apr 2023 17:30:56 +0100 Subject: [PATCH 099/665] [Deps] Update qonnx commit version --- fetch-repos.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fetch-repos.sh b/fetch-repos.sh index 1e01a058ff..e039ca9144 100755 --- a/fetch-repos.sh +++ b/fetch-repos.sh @@ -27,7 +27,7 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -QONNX_COMMIT="d9ac34c638ccbdcd3b3f5cd236fe76d611b08f6a" +QONNX_COMMIT="20a34289cf2297d2b2bbbe75d6ac152ece86e3b4" FINN_EXP_COMMIT="0aa7e1c44b20cf085b6fe42cff360f0a832afd2c" BREVITAS_COMMIT="c65f9c13dc124971f14739349531bbcda5c2a4aa" PYVERILATOR_COMMIT="766e457465f5c0dd315490d7b9cc5d74f9a76f4f" From 90cc515938ed18eba01ffd15d33dc9b24a2b6efe Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 4 Apr 2023 17:33:21 +0100 Subject: [PATCH 100/665] [QONNX conversion] Update infer quant avg pool 2d --- .../qonnx/infer_quant_avg_pool_2d.py | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/src/finn/transformation/qonnx/infer_quant_avg_pool_2d.py b/src/finn/transformation/qonnx/infer_quant_avg_pool_2d.py index 5a3f176f1f..bd3ff15645 100644 --- a/src/finn/transformation/qonnx/infer_quant_avg_pool_2d.py +++ b/src/finn/transformation/qonnx/infer_quant_avg_pool_2d.py @@ -46,7 +46,7 @@ def _get_signed_from_upstream(model, trunc_node): # Check if the input of this node already has a FINN datatype signed = None inp_dt = model.get_tensor_datatype(node.input[0]) - if inp_dt is not None and inp_dt is not DataType["FLOAT32"]: + if inp_dt is not None and inp_dt != "FLOAT32": signed = inp_dt.signed() # Go further up the graph, since the datatype inference works top down # these nodes should either be sign preserving ops or they already have a @@ -67,23 +67,27 @@ def _get_signed_from_upstream(model, trunc_node): ) next_node = next_node[0] out_dt = model.get_tensor_datatype(next_node.output[0]) - if out_dt is not None and out_dt is not DataType["FLOAT32"]: + if out_dt is not None and out_dt != "FLOAT32": signed = out_dt.signed() break # Special cases where the node has an internal or intrinsic datatype. if next_node.op_type == "MultiThreshold": - mt_inst = getCustomOp(next_node) + mt_inst = getCustomOp( + next_node, onnx_opset_version=9, brevitas_exception=True + ) out_dt = DataType[mt_inst.get_nodeattr("out_dtype")] - if out_dt is not None and out_dt is not DataType["FLOAT32"]: + if out_dt is not None and out_dt != "FLOAT32": signed = out_dt.signed() break if next_node.op_type == "BipolarQuant": signed = True break if next_node.op_type == "Quant": - q_inst = getCustomOp(next_node) + q_inst = getCustomOp( + next_node, onnx_opset_version=9, brevitas_exception=True + ) out_dt = q_inst.get_integer_datatype(model) - if out_dt is not None and out_dt is not DataType["FLOAT32"]: + if out_dt is not None and out_dt != "FLOAT32": signed = out_dt.signed() break From 744a43dc5db11df8d44eaf3ae7e08c21ac67d7de Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 5 Apr 2023 14:17:11 +0100 Subject: [PATCH 101/665] [Transform] Update check for dt in infer quant avg pool --- .../qonnx/infer_quant_avg_pool_2d.py | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/src/finn/transformation/qonnx/infer_quant_avg_pool_2d.py b/src/finn/transformation/qonnx/infer_quant_avg_pool_2d.py index bd3ff15645..d2aaee59a4 100644 --- a/src/finn/transformation/qonnx/infer_quant_avg_pool_2d.py +++ b/src/finn/transformation/qonnx/infer_quant_avg_pool_2d.py @@ -46,7 +46,7 @@ def _get_signed_from_upstream(model, trunc_node): # Check if the input of this node already has a FINN datatype signed = None inp_dt = model.get_tensor_datatype(node.input[0]) - if inp_dt is not None and inp_dt != "FLOAT32": + if inp_dt is not None and inp_dt != DataType["FLOAT32"]: signed = inp_dt.signed() # Go further up the graph, since the datatype inference works top down # these nodes should either be sign preserving ops or they already have a @@ -67,27 +67,23 @@ def _get_signed_from_upstream(model, trunc_node): ) next_node = next_node[0] out_dt = model.get_tensor_datatype(next_node.output[0]) - if out_dt is not None and out_dt != "FLOAT32": + if out_dt is not None and out_dt != DataType["FLOAT32"]: signed = out_dt.signed() break # Special cases where the node has an internal or intrinsic datatype. if next_node.op_type == "MultiThreshold": - mt_inst = getCustomOp( - next_node, onnx_opset_version=9, brevitas_exception=True - ) + mt_inst = getCustomOp(next_node, onnx_opset_version=9) out_dt = DataType[mt_inst.get_nodeattr("out_dtype")] - if out_dt is not None and out_dt != "FLOAT32": + if out_dt is not None and out_dt != DataType["FLOAT32"]: signed = out_dt.signed() break if next_node.op_type == "BipolarQuant": signed = True break if next_node.op_type == "Quant": - q_inst = getCustomOp( - next_node, onnx_opset_version=9, brevitas_exception=True - ) + q_inst = getCustomOp(next_node, onnx_opset_version=9) out_dt = q_inst.get_integer_datatype(model) - if out_dt is not None and out_dt != "FLOAT32": + if out_dt is not None and out_dt != DataType["FLOAT32"]: signed = out_dt.signed() break From 2d42124deb1a679f0e749df8633090ec43443db7 Mon Sep 17 00:00:00 2001 From: Felix Jentzsch Date: Wed, 5 Apr 2023 16:25:29 +0200 Subject: [PATCH 102/665] [SWG] Minor fixes --- src/finn/builder/build_dataflow_steps.py | 1 + .../fpgadataflow/convolutioninputgenerator_rtl.py | 8 ++++---- tests/fpgadataflow/test_convert_to_hls_conv_layer.py | 5 +---- .../test_fpgadataflow_convinputgenerator_rtl.py | 11 ++++++----- 4 files changed, 12 insertions(+), 13 deletions(-) diff --git a/src/finn/builder/build_dataflow_steps.py b/src/finn/builder/build_dataflow_steps.py index b4a0374fb8..a22b5adc98 100644 --- a/src/finn/builder/build_dataflow_steps.py +++ b/src/finn/builder/build_dataflow_steps.py @@ -589,6 +589,7 @@ def step_set_fifo_depths(model: ModelWrapper, cfg: DataflowBuildConfig): hw_attrs = [ "PE", "SIMD", + "parallel_window", "ram_style", "depth", "impl_style", diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py index 77a435640c..173a157841 100755 --- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py +++ b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py @@ -564,13 +564,13 @@ def prepare_codegen_default(self): ) addr_incr_end_simd = -buffer_min_size + (channel_factor + 1) - # sanity check + # sanity check for wrap logic assert not ( abs(addr_incr_end_window) > buffer_actual_size - ), "ERROR: W increment > buffer size, wrap logic doesn't account for this" + ), "ERROR: W increment > buffer size, try setting parallel_window=1" assert not ( abs(addr_incr_end_row) > buffer_actual_size - ), "ERROR: H increment > buffer size, wrap logic doesn't account for this" + ), "ERROR: H increment > buffer size, try setting parallel_window=1" # set certain threshold indices to detect when reading/writing finishes code_gen_dict["$LAST_READ_ELEM$"] = [str(h * w * channel_factor - 1)] @@ -753,7 +753,7 @@ def prepare_codegen_parallel(self): tail_incr_w = addr_incr_end_window + buffer_min_size - 1 tail_incr_h = addr_incr_end_row + buffer_min_size - 1 - tail_incr_last_window = buffer_min_size - 1 + tail_incr_last_window = stride_w addr_incr_end_simd = 1 addr_incr_end_window_elem = 1 diff --git a/tests/fpgadataflow/test_convert_to_hls_conv_layer.py b/tests/fpgadataflow/test_convert_to_hls_conv_layer.py index de31ef0f12..7b2793712d 100644 --- a/tests/fpgadataflow/test_convert_to_hls_conv_layer.py +++ b/tests/fpgadataflow/test_convert_to_hls_conv_layer.py @@ -73,9 +73,6 @@ def test_convert_to_hls_conv_layer(conv_config, depthwise, use_rtl_swg, exec_mod if use_rtl_swg and exec_mode == "cppsim": pytest.skip("cppsim not supported for RTL SWG") - if use_rtl_swg and kernel_size == 1: - pytest.skip("1x1 kernel not supported by current RTL SWG") - if depthwise is True: group = out_chn = in_chn conv_param_shape = [out_chn, 1, kernel_size, kernel_size] @@ -164,7 +161,7 @@ def test_convert_to_hls_conv_layer(conv_config, depthwise, use_rtl_swg, exec_mod inp_dict = {model.graph.input[0].name: x} assert oxe.compare_execution(model, new_model, inp_dict) - if kernel_size == 1 and stride > 1 and pad == 0: + if not use_rtl_swg and kernel_size == 1 and stride > 1 and pad == 0: assert new_model.graph.node[1].op_type == "DownSampler" if exec_mode == "rtlsim": node = new_model.get_nodes_by_op_type("DownSampler")[0] diff --git a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py index 6775498610..2f3ad0a23d 100755 --- a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py +++ b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py @@ -198,12 +198,13 @@ def test_fpgadataflow_slidingwindow_rtl( pytest.skip( "Illegal convolution configuration: kernel or stride > FM dimension" ) - if (k_h == 1 and (stride_h != 1 or dilation_h != 1)) or ( - k_w == 1 and (stride_w != 1 or dilation_w != 1) - ): + if (k_h == 1 and dilation_h != 1) or (k_w == 1 and dilation_w != 1): pytest.skip( - """Illegal convolution configuration: - stride or dilation defined for unitary kernel dim""" + "Illegal convolution configuration: dilation for unitary kernel dim" + ) + if (stride_h > k_h) or (stride_w > k_w) and not parallel_window: + pytest.skip( + "Not all combinations for stride > k edge case supported in default mode" ) if k_h == 1 and k_w == 1 and simd != ifm_ch: pytest.skip("1x1 Kernel only supported in parallel mode (SIMD=C)") From b056303b65cac8a5afa872c7822ea5b9313617be Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 5 Apr 2023 16:54:38 +0100 Subject: [PATCH 103/665] [Tests] Update avg pool export testing and disable unsigned testing temporarily --- .../brevitas/test_brevitas_avg_pool_export.py | 87 +++++++------------ 1 file changed, 31 insertions(+), 56 deletions(-) diff --git a/tests/brevitas/test_brevitas_avg_pool_export.py b/tests/brevitas/test_brevitas_avg_pool_export.py index 9c35910366..9550031b32 100644 --- a/tests/brevitas/test_brevitas_avg_pool_export.py +++ b/tests/brevitas/test_brevitas_avg_pool_export.py @@ -30,9 +30,8 @@ import numpy as np import os import torch -from brevitas.export import export_finn_onnx, export_qonnx -from brevitas.nn import QuantAvgPool2d -from brevitas.quant_tensor import QuantTensor +from brevitas.export import export_qonnx +from brevitas.nn import QuantAvgPool2d, QuantIdentity, QuantReLU from qonnx.core.datatype import DataType from qonnx.core.modelwrapper import ModelWrapper from qonnx.transformation.infer_datatypes import InferDataTypes @@ -47,10 +46,9 @@ @pytest.mark.brevitas_export -@pytest.mark.parametrize("QONNX_export", [False, True]) @pytest.mark.parametrize("kernel_size", [2, 3]) @pytest.mark.parametrize("stride", [1, 2]) -@pytest.mark.parametrize("signed", [True, False]) +@pytest.mark.parametrize("signed", [True]) # TODO: Add unsigned test case @pytest.mark.parametrize("bit_width", [2, 4]) @pytest.mark.parametrize("input_bit_width", [4, 8, 16]) @pytest.mark.parametrize("channels", [2, 4]) @@ -63,79 +61,56 @@ def test_brevitas_avg_pool_export( input_bit_width, channels, idim, - QONNX_export, ): - export_onnx_path = base_export_onnx_path.replace( - ".onnx", f"test_QONNX-{QONNX_export}.onnx" - ) + export_onnx_path = base_export_onnx_path.replace(".onnx", "test_QONNX.onnx") + if signed: + quant_node = QuantIdentity( + bit_width=input_bit_width, + return_quant_tensor=True, + ) + else: + quant_node = QuantReLU( + bit_width=input_bit_width, + return_quant_tensor=True, + ) quant_avgpool = QuantAvgPool2d( kernel_size=kernel_size, stride=stride, bit_width=bit_width, return_quant_tensor=False, + float_to_int_impl_type="FLOOR", ) - quant_avgpool.eval() + model_brevitas = torch.nn.Sequential(quant_node, quant_avgpool) + model_brevitas.eval() # determine input - prefix = "INT" if signed else "UINT" - dt_name = prefix + str(input_bit_width) - dtype = DataType[dt_name] input_shape = (1, channels, idim, idim) - input_array = gen_finn_dt_tensor(dtype, input_shape) - # Brevitas QuantAvgPool layers need QuantTensors to export correctly - # which requires setting up a QuantTensor instance with the scale - # factor, zero point, bitwidth and signedness - scale_array = np.ones((1, channels, 1, 1)).astype(np.float32) - scale_array *= 0.5 - input_tensor = torch.from_numpy(input_array * scale_array).float() - scale_tensor = torch.from_numpy(scale_array).float() - zp = torch.tensor(0.0) - input_quant_tensor = QuantTensor( - input_tensor, scale_tensor, zp, input_bit_width, signed, training=False - ) + input_array = gen_finn_dt_tensor(DataType["FLOAT32"], input_shape) - # export - if QONNX_export: - export_qonnx( - quant_avgpool, - export_path=export_onnx_path, - input_t=input_quant_tensor, - ) - model = ModelWrapper(export_onnx_path) + input_tensor = torch.from_numpy(input_array).float() - # Statically set the additional inputs generated by the Brevitas ONNX export - model.graph.input.remove(model.graph.input[3]) - model.graph.input.remove(model.graph.input[2]) - model.graph.input.remove(model.graph.input[1]) - model.set_initializer("1", scale_array) - model.set_initializer("2", np.array(0.0).astype(np.float32)) - model.set_initializer("3", np.array(input_bit_width).astype(np.float32)) - model.save(export_onnx_path) + # export + export_qonnx( + model_brevitas, + export_path=export_onnx_path, + input_t=input_tensor, + ) + model = ModelWrapper(export_onnx_path) + model.save(export_onnx_path) - qonnx_cleanup(export_onnx_path, out_file=export_onnx_path) - model = ModelWrapper(export_onnx_path) - model = model.transform(ConvertQONNXtoFINN()) - model.save(export_onnx_path) - else: - export_finn_onnx( - quant_avgpool, export_path=export_onnx_path, input_t=input_quant_tensor - ) + qonnx_cleanup(export_onnx_path, out_file=export_onnx_path) model = ModelWrapper(export_onnx_path) + model = model.transform(ConvertQONNXtoFINN()) model = model.transform(InferShapes()) model = model.transform(InferDataTypes()) # reference brevitas output - ref_output_array = quant_avgpool(input_quant_tensor).detach().numpy() + ref_output_array = model_brevitas(input_tensor).detach().numpy() # finn output - if QONNX_export: - # Manually apply the Quant tensor scaling for QONNX - idict = {model.graph.input[0].name: input_array * scale_array} - else: - idict = {model.graph.input[0].name: input_array} + idict = {model.graph.input[0].name: input_array} odict = oxe.execute_onnx(model, idict, True) finn_output = odict[model.graph.output[0].name] # compare outputs assert np.isclose(ref_output_array, finn_output).all() # cleanup - # assert False os.remove(export_onnx_path) From 76a8f6338987f991ee0fe1901b4beb4758d5d469 Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 7 Apr 2023 14:49:48 +0100 Subject: [PATCH 104/665] [Docs/Tests] Remove unused images and replacing mobilenet test image --- docs/img/finn-examples-header.png | Bin 26332 -> 0 bytes docs/img/imagenet.jpg | Bin 296033 -> 0 bytes tests/brevitas/king_charles.jpg | Bin 11954 -> 61443 bytes 3 files changed, 0 insertions(+), 0 deletions(-) delete mode 100644 docs/img/finn-examples-header.png delete mode 100644 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zUiDfEO{8}dc5#=g7dBsil82q#_qOkmzGR$_uqrb$5XF+q8ZBY|>f!Awn9vj&Zi z@wwyJY=1DA>+!jc3#V^Ke~mZnznX8-P^tIMgNJszSpPK}p!ly;fTVfD=q`q5eDDQ~ z?>}InH#EFEr>BI%IwEl>`I(|Zu*QA^Ctl>7OXG)%KIwnz#!djEbQXhQC1$9I>ySp}JtZFX zjd8Hx*_6rsqzd$-JMV+%Ur`{x0{oYlGXO$CmySiZ;h01|ELb6vt^fO%G8(nnCfJYh zMjH7}{HJlxjg%pw&yC5oRrlqho=VSMJ(>CLTM~0DXrbn4xM0gM z`}FEUCUpzFyAWfcx66P+pL^bYEFyinZRxh;0hd~cMZy@DYJ0J`%erhlM&4%z3!)cLo+7a~QIZLidT19|n% zHA03iP~&o+Ls$Q7*ibKuPo(y|Fy_!hS`F5`=AoPv6N_xh<9dMn7J7Cag~2gXbPcF1 z8SA^0w?<|!C;uSamV9kb6{r%=7Bv{;3?lltBYSUm5qiS+5A<7~#faxOWvCzb-+8?x z`MuUYBqQV>00N&$l7l#g-Dn$*XLraqMKSML|g zNh4{1Uvn_<(HfNU!S-PQA4NTzK>dTVnDpfgjGdY;4v~_SPTvPfH_zx7?vNX{S v91&Xvo0AB;q-1C477vsX^&=8pG>B;%;v&$KJ|_YbIAE*FNW Date: Fri, 7 Apr 2023 15:14:58 +0100 Subject: [PATCH 106/665] [Tests] Run pre-commit on changed files --- tests/brevitas/test_brevitas_mobilenet.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tests/brevitas/test_brevitas_mobilenet.py b/tests/brevitas/test_brevitas_mobilenet.py index 25276eac76..c7f0f4ebf9 100644 --- a/tests/brevitas/test_brevitas_mobilenet.py +++ b/tests/brevitas/test_brevitas_mobilenet.py @@ -120,4 +120,6 @@ def test_brevitas_mobilenet(): produced = odict[model.graph.output[0].name] produced_prob = odict["TopK_0_out0"] * a0 assert (produced.flatten() == expected_top5).all() - assert np.isclose(produced_prob.flatten(), expected_top5_prob, atol=2.2*1e-1).all() + assert np.isclose( + produced_prob.flatten(), expected_top5_prob, atol=2.2 * 1e-1 + ).all() From 11b046cd4e654e762dfa6e618016d26ae1d1143b Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 7 Apr 2023 16:20:57 +0100 Subject: [PATCH 107/665] [Tests] Mark mobilenet export test as xfail --- tests/brevitas/test_brevitas_mobilenet.py | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/brevitas/test_brevitas_mobilenet.py b/tests/brevitas/test_brevitas_mobilenet.py index c7f0f4ebf9..b469b197fa 100644 --- a/tests/brevitas/test_brevitas_mobilenet.py +++ b/tests/brevitas/test_brevitas_mobilenet.py @@ -54,6 +54,7 @@ @pytest.mark.brevitas_export +@pytest.mark.xfail def test_brevitas_mobilenet(): # get single image as input and prepare image img = Image.open(get_finn_root() + "/tests/brevitas/king_charles.jpg") From 30501464601528ea2ff14c4b94b6d55a44a3ae2f Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Tue, 11 Apr 2023 14:46:51 +0100 Subject: [PATCH 108/665] [notebooks] add pytests for testing all jupyter notebooks Signed-off-by: Fionn O'Donohoe --- .../advanced/0_custom_analysis_pass.ipynb | 6 +- .../1_custom_transformation_pass.ipynb | 5 +- .../1-train-mlp-with-brevitas.ipynb | 5 +- .../2-import-into-finn-and-verify.ipynb | 7 +- .../3-build-accelerator-with-finn.ipynb | 6 +- tests/notebooks/test_jupyter_notebooks.py | 83 +++++++++++++++++++ 6 files changed, 100 insertions(+), 12 deletions(-) create mode 100644 tests/notebooks/test_jupyter_notebooks.py diff --git a/notebooks/advanced/0_custom_analysis_pass.ipynb b/notebooks/advanced/0_custom_analysis_pass.ipynb index f8444520c3..0454010284 100644 --- a/notebooks/advanced/0_custom_analysis_pass.ipynb +++ b/notebooks/advanced/0_custom_analysis_pass.ipynb @@ -52,7 +52,9 @@ "metadata": {}, "outputs": [], "source": [ - "showInNetron(\"../LFCW1A1.onnx\")" + "import os\n", + "print(os.getcwd())\n", + "showInNetron(os.environ['FINN_ROOT'] + \"/notebooks/LFCW1A1.onnx\")" ] }, { @@ -69,7 +71,7 @@ "outputs": [], "source": [ "from qonnx.core.modelwrapper import ModelWrapper\n", - "model = ModelWrapper('../LFCW1A1.onnx')" + "model = ModelWrapper(os.environ['FINN_ROOT'] + \"/notebooks/LFCW1A1.onnx\")" ] }, { diff --git a/notebooks/advanced/1_custom_transformation_pass.ipynb b/notebooks/advanced/1_custom_transformation_pass.ipynb index 391e852a71..8cdbabc34d 100644 --- a/notebooks/advanced/1_custom_transformation_pass.ipynb +++ b/notebooks/advanced/1_custom_transformation_pass.ipynb @@ -110,8 +110,9 @@ "metadata": {}, "outputs": [], "source": [ + "import os\n", "import onnx\n", - "onnx_model = onnx.load('../LFCW1A1.onnx')\n", + "onnx_model = onnx.load(os.environ['FINN_ROOT'] + \"/notebooks/LFCW1A1.onnx\")\n", "from qonnx.core.modelwrapper import ModelWrapper\n", "onnx_model = ModelWrapper(onnx_model)" ] @@ -122,7 +123,7 @@ "metadata": {}, "outputs": [], "source": [ - "showInNetron('../LFCW1A1.onnx')" + "showInNetron(os.environ['FINN_ROOT'] + \"/notebooks/LFCW1A1.onnx\")" ] }, { diff --git a/notebooks/end2end_example/cybersecurity/1-train-mlp-with-brevitas.ipynb b/notebooks/end2end_example/cybersecurity/1-train-mlp-with-brevitas.ipynb index 9bb9e6761e..b99e9f16b2 100644 --- a/notebooks/end2end_example/cybersecurity/1-train-mlp-with-brevitas.ipynb +++ b/notebooks/end2end_example/cybersecurity/1-train-mlp-with-brevitas.ipynb @@ -483,13 +483,14 @@ "metadata": {}, "outputs": [], "source": [ + "import os\n", "import torch\n", "\n", "# Make sure the model is on CPU before loading a pretrained state_dict\n", "model = model.cpu()\n", "\n", "# Load pretrained weights\n", - "trained_state_dict = torch.load(\"state_dict.pth\")[\"models_state_dict\"][0]\n", + "trained_state_dict = torch.load(os.environ['FINN_ROOT'] + \"/notebooks/end2end_example/cybersecurity/state_dict.pth\")[\"models_state_dict\"][0]\n", "\n", "model.load_state_dict(trained_state_dict, strict=False)" ] @@ -680,7 +681,7 @@ "from brevitas.export import export_finn_onnx\n", "from brevitas.quant_tensor import QuantTensor\n", "\n", - "ready_model_filename = \"cybsec-mlp-ready.onnx\"\n", + "ready_model_filename = os.environ['FINN_ROOT'] + \"/notebooks/end2end_example/cybersecurity/cybsec-mlp-ready.onnx\"\n", "input_shape = (1, 600)\n", "\n", "# create a QuantTensor instance to mark input as bipolar during export\n", diff --git a/notebooks/end2end_example/cybersecurity/2-import-into-finn-and-verify.ipynb b/notebooks/end2end_example/cybersecurity/2-import-into-finn-and-verify.ipynb index e4848a1f40..0efaf62e7f 100644 --- a/notebooks/end2end_example/cybersecurity/2-import-into-finn-and-verify.ipynb +++ b/notebooks/end2end_example/cybersecurity/2-import-into-finn-and-verify.ipynb @@ -62,9 +62,10 @@ "metadata": {}, "outputs": [], "source": [ + "import os\n", "from qonnx.core.modelwrapper import ModelWrapper\n", "\n", - "ready_model_filename = \"cybsec-mlp-ready.onnx\"\n", + "ready_model_filename = os.environ['FINN_ROOT'] + \"/notebooks/end2end_example/cybersecurity/cybsec-mlp-ready.onnx\"\n", "model_for_sim = ModelWrapper(ready_model_filename)" ] }, @@ -151,7 +152,7 @@ "model_for_sim = model_for_sim.transform(InferDataTypes())\n", "model_for_sim = model_for_sim.transform(RemoveStaticGraphInputs())\n", "\n", - "verif_model_filename = \"cybsec-mlp-verification.onnx\"\n", + "verif_model_filename = os.environ['FINN_ROOT'] + \"/notebooks/end2end_example/cybersecurity/cybsec-mlp-verification.onnx\"\n", "model_for_sim.save(verif_model_filename)" ] }, @@ -258,7 +259,7 @@ "\n", "# replace this with your trained network checkpoint if you're not\n", "# using the pretrained weights\n", - "trained_state_dict = torch.load(\"state_dict.pth\")[\"models_state_dict\"][0]\n", + "trained_state_dict = torch.load(os.environ['FINN_ROOT'] + \"/notebooks/end2end_example/cybersecurity/state_dict.pth\")[\"models_state_dict\"][0]\n", "# Uncomment the following line if you previously chose to train the network yourself\n", "#trained_state_dict = torch.load(\"state_dict_self-trained.pth\")\n", "\n", diff --git a/notebooks/end2end_example/cybersecurity/3-build-accelerator-with-finn.ipynb b/notebooks/end2end_example/cybersecurity/3-build-accelerator-with-finn.ipynb index a18cafd604..1c93e4f58b 100644 --- a/notebooks/end2end_example/cybersecurity/3-build-accelerator-with-finn.ipynb +++ b/notebooks/end2end_example/cybersecurity/3-build-accelerator-with-finn.ipynb @@ -115,7 +115,7 @@ "import os\n", "import shutil\n", "\n", - "model_file = \"cybsec-mlp-ready.onnx\"\n", + "model_file = os.environ['FINN_ROOT'] + \"/notebooks/end2end_example/cybersecurity/cybsec-mlp-ready.onnx\"\n", "\n", "estimates_output_dir = \"output_estimates_only\"\n", "\n", @@ -272,7 +272,7 @@ "import os\n", "import shutil\n", "\n", - "model_file = \"cybsec-mlp-ready.onnx\"\n", + "model_file = os.environ['FINN_ROOT'] + \"/notebooks/end2end_example/cybersecurity/cybsec-mlp-ready.onnx\"\n", "\n", "rtlsim_output_dir = \"output_ipstitch_ooc_rtlsim\"\n", "\n", @@ -412,7 +412,7 @@ "import os\n", "import shutil\n", "\n", - "model_file = \"cybsec-mlp-ready.onnx\"\n", + "model_file = os.environ['FINN_ROOT'] + \"/notebooks/end2end_example/cybersecurity/cybsec-mlp-ready.onnx\"\n", "\n", "final_output_dir = \"output_final\"\n", "\n", diff --git a/tests/notebooks/test_jupyter_notebooks.py b/tests/notebooks/test_jupyter_notebooks.py new file mode 100644 index 0000000000..3de586f1fd --- /dev/null +++ b/tests/notebooks/test_jupyter_notebooks.py @@ -0,0 +1,83 @@ +import pytest + +import nbformat +from nbconvert.preprocessors import ExecutePreprocessor + +from finn.util.basic import get_finn_root + +notebook_basic_dir = get_finn_root() + "/notebooks/basics/" +notebook_advanced_dir = get_finn_root() + "/notebooks/advanced/" +notebook_cyber_dir = get_finn_root() + "/notebooks/end2end_example/cybersecurity/" +notebook_bnn_dir = get_finn_root() + "/notebooks/end2end_example/bnn-pynq/" + +basics_notebooks = [ + pytest.param( + notebook_basic_dir + "0_how_to_work_with_onnx.ipynb", + marks=pytest.mark.notebooks_basic, + ), + pytest.param( + notebook_basic_dir + "1a_brevitas_network_import_via_FINN-ONNX.ipynb", + marks=pytest.mark.notebooks_basic, + ), + pytest.param( + notebook_basic_dir + "1b_brevitas_network_import_via_QONNX.ipynb", + marks=pytest.mark.notebooks_basic, + ), +] + +advanced_notebooks = [ + pytest.param( + notebook_advanced_dir + "0_custom_analysis_pass.ipynb", + marks=pytest.mark.notebooks_advanced, + ), + pytest.param( + notebook_advanced_dir + "1_custom_transformation_pass.ipynb", + marks=pytest.mark.notebooks_advanced, + ), + pytest.param( + notebook_advanced_dir + "2_custom_op.ipynb", + marks=pytest.mark.notebooks_advanced, + ), +] + +cyber_notebooks = [ + pytest.param( + notebook_cyber_dir + "1-train-mlp-with-brevitas.ipynb", + marks=pytest.mark.notebooks_cyber, + ), + pytest.param( + notebook_cyber_dir + "2-import-into-finn-and-verify.ipynb", + marks=pytest.mark.notebooks_cyber, + ), + pytest.param( + notebook_cyber_dir + "3-build-accelerator-with-finn.ipynb", + marks=pytest.mark.notebooks_cyber, + ), +] + +bnn_notebooks = [ + pytest.param( + notebook_bnn_dir + "cnv_end2end_example.ipynb", marks=pytest.mark.notebooks_bnn + ), + pytest.param( + notebook_bnn_dir + "tfc_end2end_example.ipynb", marks=pytest.mark.notebooks_bnn + ), + pytest.param( + notebook_bnn_dir + "tfc_end2end_verification.ipynb", + marks=pytest.mark.notebooks_bnn, + ), +] + + +@pytest.mark.notebooks +@pytest.mark.parametrize( + "notebook", basics_notebooks + advanced_notebooks + cyber_notebooks + bnn_notebooks +) +def test_notebook_exec(notebook): + with open(notebook) as f: + nb = nbformat.read(f, as_version=4) + ep = ExecutePreprocessor(timeout=600, kernel_name="python3") + try: + assert ep.preprocess(nb) is not None, f"Got empty notebook for {notebook}" + except Exception: + assert False, f"Failed executing {notebook}" From 16d1e63e0ff0b016faa3c4aa0239740716de7180 Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Tue, 18 Apr 2023 12:23:09 +0100 Subject: [PATCH 109/665] [notebooks] increase notebook timeout to 1 hour Signed-off-by: Fionn O'Donohoe --- tests/notebooks/test_jupyter_notebooks.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/tests/notebooks/test_jupyter_notebooks.py b/tests/notebooks/test_jupyter_notebooks.py index 3de586f1fd..d8669d7e7e 100644 --- a/tests/notebooks/test_jupyter_notebooks.py +++ b/tests/notebooks/test_jupyter_notebooks.py @@ -5,6 +5,7 @@ from finn.util.basic import get_finn_root +notebook_timeout_seconds = 3600 notebook_basic_dir = get_finn_root() + "/notebooks/basics/" notebook_advanced_dir = get_finn_root() + "/notebooks/advanced/" notebook_cyber_dir = get_finn_root() + "/notebooks/end2end_example/cybersecurity/" @@ -76,7 +77,9 @@ def test_notebook_exec(notebook): with open(notebook) as f: nb = nbformat.read(f, as_version=4) - ep = ExecutePreprocessor(timeout=600, kernel_name="python3") + ep = ExecutePreprocessor( + timeout=notebook_timeout_seconds, kernel_name="python3" + ) try: assert ep.preprocess(nb) is not None, f"Got empty notebook for {notebook}" except Exception: From 10f07ab573bc3847917984c2ec871d9b0544e36c Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Tue, 18 Apr 2023 13:37:36 +0100 Subject: [PATCH 110/665] [notebooks] tidy up paths to ONNX files by reusing variables Signed-off-by: Fionn O'Donohoe --- .../cybersecurity/1-train-mlp-with-brevitas.ipynb | 8 +++++--- .../cybersecurity/2-import-into-finn-and-verify.ipynb | 8 +++++--- .../cybersecurity/3-build-accelerator-with-finn.ipynb | 7 ++++--- 3 files changed, 14 insertions(+), 9 deletions(-) diff --git a/notebooks/end2end_example/cybersecurity/1-train-mlp-with-brevitas.ipynb b/notebooks/end2end_example/cybersecurity/1-train-mlp-with-brevitas.ipynb index b99e9f16b2..7bfedf4bbb 100644 --- a/notebooks/end2end_example/cybersecurity/1-train-mlp-with-brevitas.ipynb +++ b/notebooks/end2end_example/cybersecurity/1-train-mlp-with-brevitas.ipynb @@ -63,7 +63,9 @@ "outputs": [], "source": [ "import onnx\n", - "import torch" + "import torch\n", + "\n", + "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/end2end_example/cybersecurity\"" ] }, { @@ -490,7 +492,7 @@ "model = model.cpu()\n", "\n", "# Load pretrained weights\n", - "trained_state_dict = torch.load(os.environ['FINN_ROOT'] + \"/notebooks/end2end_example/cybersecurity/state_dict.pth\")[\"models_state_dict\"][0]\n", + "trained_state_dict = torch.load(model_dir + \"/state_dict.pth\")[\"models_state_dict\"][0]\n", "\n", "model.load_state_dict(trained_state_dict, strict=False)" ] @@ -681,7 +683,7 @@ "from brevitas.export import export_finn_onnx\n", "from brevitas.quant_tensor import QuantTensor\n", "\n", - "ready_model_filename = os.environ['FINN_ROOT'] + \"/notebooks/end2end_example/cybersecurity/cybsec-mlp-ready.onnx\"\n", + "ready_model_filename = model_dir + \"/cybsec-mlp-ready.onnx\"\n", "input_shape = (1, 600)\n", "\n", "# create a QuantTensor instance to mark input as bipolar during export\n", diff --git a/notebooks/end2end_example/cybersecurity/2-import-into-finn-and-verify.ipynb b/notebooks/end2end_example/cybersecurity/2-import-into-finn-and-verify.ipynb index 0efaf62e7f..5546ea3d09 100644 --- a/notebooks/end2end_example/cybersecurity/2-import-into-finn-and-verify.ipynb +++ b/notebooks/end2end_example/cybersecurity/2-import-into-finn-and-verify.ipynb @@ -65,7 +65,8 @@ "import os\n", "from qonnx.core.modelwrapper import ModelWrapper\n", "\n", - "ready_model_filename = os.environ['FINN_ROOT'] + \"/notebooks/end2end_example/cybersecurity/cybsec-mlp-ready.onnx\"\n", + "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/end2end_example/cybersecurity\"\n", + "ready_model_filename = model_dir + \"/cybsec-mlp-ready.onnx\"\n", "model_for_sim = ModelWrapper(ready_model_filename)" ] }, @@ -152,7 +153,7 @@ "model_for_sim = model_for_sim.transform(InferDataTypes())\n", "model_for_sim = model_for_sim.transform(RemoveStaticGraphInputs())\n", "\n", - "verif_model_filename = os.environ['FINN_ROOT'] + \"/notebooks/end2end_example/cybersecurity/cybsec-mlp-verification.onnx\"\n", + "verif_model_filename = model_dir + \"/cybsec-mlp-verification.onnx\"\n", "model_for_sim.save(verif_model_filename)" ] }, @@ -259,7 +260,8 @@ "\n", "# replace this with your trained network checkpoint if you're not\n", "# using the pretrained weights\n", - "trained_state_dict = torch.load(os.environ['FINN_ROOT'] + \"/notebooks/end2end_example/cybersecurity/state_dict.pth\")[\"models_state_dict\"][0]\n", + "trained_state_dict = torch.load(model_dir + \"/state_dict.pth\")[\"models_state_dict\"][0]\n", + "\n", "# Uncomment the following line if you previously chose to train the network yourself\n", "#trained_state_dict = torch.load(\"state_dict_self-trained.pth\")\n", "\n", diff --git a/notebooks/end2end_example/cybersecurity/3-build-accelerator-with-finn.ipynb b/notebooks/end2end_example/cybersecurity/3-build-accelerator-with-finn.ipynb index 1c93e4f58b..8bd6993e53 100644 --- a/notebooks/end2end_example/cybersecurity/3-build-accelerator-with-finn.ipynb +++ b/notebooks/end2end_example/cybersecurity/3-build-accelerator-with-finn.ipynb @@ -115,7 +115,8 @@ "import os\n", "import shutil\n", "\n", - "model_file = os.environ['FINN_ROOT'] + \"/notebooks/end2end_example/cybersecurity/cybsec-mlp-ready.onnx\"\n", + "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/end2end_example/cybersecurity\"\n", + "model_file = model_dir + \"/cybsec-mlp-ready.onnx\"\n", "\n", "estimates_output_dir = \"output_estimates_only\"\n", "\n", @@ -272,7 +273,7 @@ "import os\n", "import shutil\n", "\n", - "model_file = os.environ['FINN_ROOT'] + \"/notebooks/end2end_example/cybersecurity/cybsec-mlp-ready.onnx\"\n", + "model_file = model_dir + \"/cybsec-mlp-ready.onnx\"\n", "\n", "rtlsim_output_dir = \"output_ipstitch_ooc_rtlsim\"\n", "\n", @@ -412,7 +413,7 @@ "import os\n", "import shutil\n", "\n", - "model_file = os.environ['FINN_ROOT'] + \"/notebooks/end2end_example/cybersecurity/cybsec-mlp-ready.onnx\"\n", + "model_file = model_dir + \"/cybsec-mlp-ready.onnx\"\n", "\n", "final_output_dir = \"output_final\"\n", "\n", From e52e49e6909cf435536d79d7265e0b3fcb2a6b0e Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Tue, 18 Apr 2023 13:39:11 +0100 Subject: [PATCH 111/665] [notebooks] add assertion checks to aid with CI Signed-off-by: Fionn O'Donohoe --- .../bnn-pynq/tfc_end2end_verification.ipynb | 30 ++++++++++--------- .../2-import-into-finn-and-verify.ipynb | 7 +++-- .../3-build-accelerator-with-finn.ipynb | 20 +++++++++++++ 3 files changed, 40 insertions(+), 17 deletions(-) diff --git a/notebooks/end2end_example/bnn-pynq/tfc_end2end_verification.ipynb b/notebooks/end2end_example/bnn-pynq/tfc_end2end_verification.ipynb index 6c3b796509..2f6cde6e5b 100644 --- a/notebooks/end2end_example/bnn-pynq/tfc_end2end_verification.ipynb +++ b/notebooks/end2end_example/bnn-pynq/tfc_end2end_verification.ipynb @@ -121,12 +121,11 @@ "output_dict = oxe.execute_onnx(model_for_sim, input_dict, return_full_exec_context=False)\n", "output_pysim = output_dict[list(output_dict.keys())[0]]\n", "\n", - "\n", - "\n", - "if np.isclose(output_pysim, np.where(output_golden[0]==np.amax(output_golden[0])), atol=1e-3).all():\n", + "try:\n", + " assert np.isclose(output_pysim, np.where(output_golden[0]==np.amax(output_golden[0])), atol=1e-3).all()\n", " print(\"Results are the same!\")\n", - "else:\n", - " print(\"The results are not the same!\")" + "except AssertionError:\n", + " assert False, \"The results are not the same!\"" ] }, { @@ -268,10 +267,11 @@ "output_dict = oxe.execute_onnx(parent_model, input_dict)\n", "output_cppsim = output_dict[list(output_dict.keys())[0]]\n", "\n", - "if np.isclose(output_cppsim, np.where(output_golden[0]==np.amax(output_golden[0])), atol=1e-3).all():\n", + "try:\n", + " assert np.isclose(output_cppsim, np.where(output_golden[0]==np.amax(output_golden[0])), atol=1e-3).all()\n", " print(\"Results are the same!\")\n", - "else:\n", - " print(\"The results are not the same!\")" + "except AssertionError:\n", + " assert False, \"The results are not the same!\"" ] }, { @@ -356,10 +356,11 @@ "output_dict = oxe.execute_onnx(model_for_rtlsim, input_dict)\n", "output_rtlsim = output_dict[list(output_dict.keys())[0]]\n", "\n", - "if np.isclose(output_rtlsim, np.where(output_golden[0]==np.amax(output_golden[0])), atol=1e-3).all():\n", + "try:\n", + " assert np.isclose(output_rtlsim, np.where(output_golden[0]==np.amax(output_golden[0])), atol=1e-3).all()\n", " print(\"Results are the same!\")\n", - "else:\n", - " print(\"The results are not the same!\")" + "except AssertionError:\n", + " assert False, \"The results are not the same!\"" ] }, { @@ -430,10 +431,11 @@ "metadata": {}, "outputs": [], "source": [ - "if np.isclose(output_rtlsim, np.where(output_golden[0]==np.amax(output_golden[0])), atol=1e-3).all():\n", + "try:\n", + " assert np.isclose(output_rtlsim, np.where(output_golden[0]==np.amax(output_golden[0])), atol=1e-3).all()\n", " print(\"Results are the same!\")\n", - "else:\n", - " print(\"The results are not the same!\")" + "except AssertionError:\n", + " assert False, \"The results are not the same!\"" ] } ], diff --git a/notebooks/end2end_example/cybersecurity/2-import-into-finn-and-verify.ipynb b/notebooks/end2end_example/cybersecurity/2-import-into-finn-and-verify.ipynb index 5546ea3d09..5f4924b309 100644 --- a/notebooks/end2end_example/cybersecurity/2-import-into-finn-and-verify.ipynb +++ b/notebooks/end2end_example/cybersecurity/2-import-into-finn-and-verify.ipynb @@ -368,10 +368,11 @@ "metadata": {}, "outputs": [], "source": [ - "if ok == n_verification_inputs:\n", + "try:\n", + " assert ok == n_verification_inputs\n", " print(\"Verification succeeded. Brevitas and FINN-ONNX execution outputs are identical\")\n", - "else:\n", - " print(\"Verification failed. Brevitas and FINN-ONNX execution outputs are NOT identical\")" + "except AssertionError:\n", + " assert False, \"Verification failed. Brevitas and FINN-ONNX execution outputs are NOT identical\"" ] }, { diff --git a/notebooks/end2end_example/cybersecurity/3-build-accelerator-with-finn.ipynb b/notebooks/end2end_example/cybersecurity/3-build-accelerator-with-finn.ipynb index 8bd6993e53..80f3cd3819 100644 --- a/notebooks/end2end_example/cybersecurity/3-build-accelerator-with-finn.ipynb +++ b/notebooks/end2end_example/cybersecurity/3-build-accelerator-with-finn.ipynb @@ -149,6 +149,15 @@ "build.build_dataflow_cfg(model_file, cfg_estimates)" ] }, + { + "cell_type": "code", + "execution_count": null, + "metadata": {}, + "outputs": [], + "source": [ + "assert os.path.exists(estimates_output_dir + \"/report/estimate_network_performance.json\")" + ] + }, { "cell_type": "markdown", "metadata": {}, @@ -306,6 +315,17 @@ "build.build_dataflow_cfg(model_file, cfg_stitched_ip)" ] }, + { + "cell_type": "code", + "execution_count": null, + "metadata": {}, + "outputs": [], + "source": [ + "assert os.path.exists(rtlsim_output_dir + \"/report/ooc_synth_and_timing.json\")\n", + "assert os.path.exists(rtlsim_output_dir + \"/report/rtlsim_performance.json\")\n", + "assert os.path.exists(rtlsim_output_dir + \"/final_hw_config.json\")" + ] + }, { "cell_type": "markdown", "metadata": {}, From 79368dd1f2072d4ac3b0b85dcb2853811b13cfc6 Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Tue, 18 Apr 2023 13:44:16 +0100 Subject: [PATCH 112/665] [notebooks] add test markers to setup.cfg for Jupyter notebooks to prevent warnings during pytest runs Signed-off-by: Fionn O'Donohoe --- setup.cfg | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/setup.cfg b/setup.cfg index 1893aa4231..c0d893d5b6 100644 --- a/setup.cfg +++ b/setup.cfg @@ -127,6 +127,11 @@ markers = transform: mark tests that test transformations (before hls layers) fpgadataflow: mark tests related to hls layers end2end: mark tests that run the end2end flow + notebooks_basic: mark tests that execute all 'basic' Jupyter notebooks + notebooks_advanced: mark tests that execute all 'advanced' Jupyter notebooks + notebooks_cyber: mark tests that execute all 'cyber' Jupyter notebooks + notebooks_bnn: mark tests that execute all 'bnn' Jupyter notebooks + notebooks: mark tests that execute all Jupyter notebooks norecursedirs = dist build From 77dc1d4817d7e1b2bef36adfcc78b4ce8aa7dabe Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Tue, 18 Apr 2023 13:55:43 +0100 Subject: [PATCH 113/665] [notebooks] tidy up paths to ONNX files by reusing variables - advanced notebooks Signed-off-by: Fionn O'Donohoe --- notebooks/advanced/0_custom_analysis_pass.ipynb | 6 +++--- notebooks/advanced/1_custom_transformation_pass.ipynb | 6 ++++-- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/notebooks/advanced/0_custom_analysis_pass.ipynb b/notebooks/advanced/0_custom_analysis_pass.ipynb index 0454010284..f915b11fa0 100644 --- a/notebooks/advanced/0_custom_analysis_pass.ipynb +++ b/notebooks/advanced/0_custom_analysis_pass.ipynb @@ -53,8 +53,8 @@ "outputs": [], "source": [ "import os\n", - "print(os.getcwd())\n", - "showInNetron(os.environ['FINN_ROOT'] + \"/notebooks/LFCW1A1.onnx\")" + "notebook_dir = os.environ['FINN_ROOT'] + \"/notebooks\"\n", + "showInNetron(notebook_dir + \"/LFCW1A1.onnx\")" ] }, { @@ -71,7 +71,7 @@ "outputs": [], "source": [ "from qonnx.core.modelwrapper import ModelWrapper\n", - "model = ModelWrapper(os.environ['FINN_ROOT'] + \"/notebooks/LFCW1A1.onnx\")" + "model = ModelWrapper(notebook_dir + \"/LFCW1A1.onnx\")" ] }, { diff --git a/notebooks/advanced/1_custom_transformation_pass.ipynb b/notebooks/advanced/1_custom_transformation_pass.ipynb index 8cdbabc34d..7e4989c902 100644 --- a/notebooks/advanced/1_custom_transformation_pass.ipynb +++ b/notebooks/advanced/1_custom_transformation_pass.ipynb @@ -111,8 +111,10 @@ "outputs": [], "source": [ "import os\n", + "notebook_dir = os.environ['FINN_ROOT'] + \"/notebooks\"\n", + "\n", "import onnx\n", - "onnx_model = onnx.load(os.environ['FINN_ROOT'] + \"/notebooks/LFCW1A1.onnx\")\n", + "onnx_model = onnx.load(notebook_dir + \"/LFCW1A1.onnx\")\n", "from qonnx.core.modelwrapper import ModelWrapper\n", "onnx_model = ModelWrapper(onnx_model)" ] @@ -123,7 +125,7 @@ "metadata": {}, "outputs": [], "source": [ - "showInNetron(os.environ['FINN_ROOT'] + \"/notebooks/LFCW1A1.onnx\")" + "showInNetron(notebook_dir + \"/LFCW1A1.onnx\")" ] }, { From e9c89ffb712cea51b5bfa94aba0bf0a03c000b40 Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Tue, 18 Apr 2023 15:07:11 +0100 Subject: [PATCH 114/665] [notebooks] reduce notebooks markers to only 1 Signed-off-by: Fionn O'Donohoe --- setup.cfg | 4 -- tests/notebooks/test_jupyter_notebooks.py | 58 +++++------------------ 2 files changed, 12 insertions(+), 50 deletions(-) diff --git a/setup.cfg b/setup.cfg index c0d893d5b6..63dec2b8b2 100644 --- a/setup.cfg +++ b/setup.cfg @@ -127,10 +127,6 @@ markers = transform: mark tests that test transformations (before hls layers) fpgadataflow: mark tests related to hls layers end2end: mark tests that run the end2end flow - notebooks_basic: mark tests that execute all 'basic' Jupyter notebooks - notebooks_advanced: mark tests that execute all 'advanced' Jupyter notebooks - notebooks_cyber: mark tests that execute all 'cyber' Jupyter notebooks - notebooks_bnn: mark tests that execute all 'bnn' Jupyter notebooks notebooks: mark tests that execute all Jupyter notebooks norecursedirs = dist diff --git a/tests/notebooks/test_jupyter_notebooks.py b/tests/notebooks/test_jupyter_notebooks.py index d8669d7e7e..819b4ccde0 100644 --- a/tests/notebooks/test_jupyter_notebooks.py +++ b/tests/notebooks/test_jupyter_notebooks.py @@ -12,61 +12,27 @@ notebook_bnn_dir = get_finn_root() + "/notebooks/end2end_example/bnn-pynq/" basics_notebooks = [ - pytest.param( - notebook_basic_dir + "0_how_to_work_with_onnx.ipynb", - marks=pytest.mark.notebooks_basic, - ), - pytest.param( - notebook_basic_dir + "1a_brevitas_network_import_via_FINN-ONNX.ipynb", - marks=pytest.mark.notebooks_basic, - ), - pytest.param( - notebook_basic_dir + "1b_brevitas_network_import_via_QONNX.ipynb", - marks=pytest.mark.notebooks_basic, - ), + pytest.param(notebook_basic_dir + "0_how_to_work_with_onnx.ipynb"), + pytest.param(notebook_basic_dir + "1a_brevitas_network_import_via_FINN-ONNX.ipynb"), + pytest.param(notebook_basic_dir + "1b_brevitas_network_import_via_QONNX.ipynb"), ] advanced_notebooks = [ - pytest.param( - notebook_advanced_dir + "0_custom_analysis_pass.ipynb", - marks=pytest.mark.notebooks_advanced, - ), - pytest.param( - notebook_advanced_dir + "1_custom_transformation_pass.ipynb", - marks=pytest.mark.notebooks_advanced, - ), - pytest.param( - notebook_advanced_dir + "2_custom_op.ipynb", - marks=pytest.mark.notebooks_advanced, - ), + pytest.param(notebook_advanced_dir + "0_custom_analysis_pass.ipynb"), + pytest.param(notebook_advanced_dir + "1_custom_transformation_pass.ipynb"), + pytest.param(notebook_advanced_dir + "2_custom_op.ipynb"), ] cyber_notebooks = [ - pytest.param( - notebook_cyber_dir + "1-train-mlp-with-brevitas.ipynb", - marks=pytest.mark.notebooks_cyber, - ), - pytest.param( - notebook_cyber_dir + "2-import-into-finn-and-verify.ipynb", - marks=pytest.mark.notebooks_cyber, - ), - pytest.param( - notebook_cyber_dir + "3-build-accelerator-with-finn.ipynb", - marks=pytest.mark.notebooks_cyber, - ), + pytest.param(notebook_cyber_dir + "1-train-mlp-with-brevitas.ipynb"), + pytest.param(notebook_cyber_dir + "2-import-into-finn-and-verify.ipynb"), + pytest.param(notebook_cyber_dir + "3-build-accelerator-with-finn.ipynb"), ] bnn_notebooks = [ - pytest.param( - notebook_bnn_dir + "cnv_end2end_example.ipynb", marks=pytest.mark.notebooks_bnn - ), - pytest.param( - notebook_bnn_dir + "tfc_end2end_example.ipynb", marks=pytest.mark.notebooks_bnn - ), - pytest.param( - notebook_bnn_dir + "tfc_end2end_verification.ipynb", - marks=pytest.mark.notebooks_bnn, - ), + pytest.param(notebook_bnn_dir + "cnv_end2end_example.ipynb"), + pytest.param(notebook_bnn_dir + "tfc_end2end_example.ipynb"), + pytest.param(notebook_bnn_dir + "tfc_end2end_verification.ipynb"), ] From 63918e7165c8230411564425e6a918fc7a42bdcc Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Tue, 18 Apr 2023 15:09:25 +0100 Subject: [PATCH 115/665] [notebooks] remove notebooks from being tested during quicktest test suite Signed-off-by: Fionn O'Donohoe --- docker/quicktest.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docker/quicktest.sh b/docker/quicktest.sh index b4ad37232f..466fcfb09d 100755 --- a/docker/quicktest.sh +++ b/docker/quicktest.sh @@ -6,7 +6,7 @@ cd $FINN_ROOT # check if command line argument is empty or not present if [ -z $1 ]; then echo "Running quicktest: not (vivado or slow or board) with pytest-xdist" - python setup.py test --addopts "-m 'not (vivado or slow or vitis or board)' --dist=loadfile -n $PYTEST_PARALLEL" + python setup.py test --addopts "-m 'not (vivado or slow or vitis or board or notebooks)' --dist=loadfile -n $PYTEST_PARALLEL" elif [ $1 = "main" ]; then echo "Running main test suite: not (rtlsim or end2end) with pytest-xdist" python setup.py test --addopts "-k 'not (rtlsim or end2end)' --dist=loadfile -n $PYTEST_PARALLEL" From 9ee018ff47b25e153e54c20a0c46d5961910434e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thomas=20B=2E=20Preu=C3=9Fer?= Date: Tue, 18 Apr 2023 20:42:46 +0100 Subject: [PATCH 116/665] Streamlined memstream module tested with random interleaved parameter readback. --- finn-rtllib/memstream/component.xml | 1707 --- finn-rtllib/memstream/gui/memstream_v1_0.gtcl | 2 - finn-rtllib/memstream/hdl/Q_srl.v | 308 - finn-rtllib/memstream/hdl/memstream.sv | 176 + finn-rtllib/memstream/hdl/memstream.v | 327 - finn-rtllib/memstream/hdl/memstream_axi.sv | 136 + .../memstream/hdl/memstream_multiblock.v | 474 - .../memstream/hdl/memstream_singleblock.v | 246 - finn-rtllib/memstream/hdl/mux.v | 44 - finn-rtllib/memstream/hdl/ramb18_sdp.v | 96 - .../memstream/hdl/ramb18_wf_dualport.v | 111 - finn-rtllib/memstream/sim/gen_memblocks.sh | 39 - finn-rtllib/memstream/sim/golden.dat | 9216 ----------------- finn-rtllib/memstream/sim/memstream_tb.sv | 212 + finn-rtllib/memstream/sim/tb_memstream.v | 369 - .../memstream/sim/tb_memstream_writes.v | 486 - finn-rtllib/memstream/sim/test.sh | 32 - finn-rtllib/memstream/xgui/memstream_v1_0.tcl | 394 - 18 files changed, 524 insertions(+), 13851 deletions(-) delete mode 100644 finn-rtllib/memstream/component.xml delete mode 100644 finn-rtllib/memstream/gui/memstream_v1_0.gtcl delete mode 100644 finn-rtllib/memstream/hdl/Q_srl.v create mode 100644 finn-rtllib/memstream/hdl/memstream.sv delete mode 100644 finn-rtllib/memstream/hdl/memstream.v create mode 100644 finn-rtllib/memstream/hdl/memstream_axi.sv delete mode 100644 finn-rtllib/memstream/hdl/memstream_multiblock.v delete mode 100644 finn-rtllib/memstream/hdl/memstream_singleblock.v delete mode 100644 finn-rtllib/memstream/hdl/mux.v delete mode 100644 finn-rtllib/memstream/hdl/ramb18_sdp.v delete mode 100644 finn-rtllib/memstream/hdl/ramb18_wf_dualport.v delete mode 100644 finn-rtllib/memstream/sim/gen_memblocks.sh delete mode 100644 finn-rtllib/memstream/sim/golden.dat create mode 100644 finn-rtllib/memstream/sim/memstream_tb.sv delete mode 100644 finn-rtllib/memstream/sim/tb_memstream.v delete mode 100644 finn-rtllib/memstream/sim/tb_memstream_writes.v delete mode 100755 finn-rtllib/memstream/sim/test.sh delete mode 100644 finn-rtllib/memstream/xgui/memstream_v1_0.tcl diff --git a/finn-rtllib/memstream/component.xml b/finn-rtllib/memstream/component.xml deleted file mode 100644 index 63a8540a76..0000000000 --- a/finn-rtllib/memstream/component.xml +++ /dev/null @@ -1,1707 +0,0 @@ - - - xilinx.com - user - memstream - 1.0 - - - m_axis_0 - - - - - - - TDATA - - - m_axis_0_tdata - - - - - TVALID - - - m_axis_0_tvalid - - - - - TREADY - - - m_axis_0_tready - - - - - - m_axis_1 - - - - - - - TDATA - - - m_axis_1_tdata - - - - - TVALID - - - m_axis_1_tvalid - - - - - TREADY - - - m_axis_1_tready - - - - - - - true - - - - - - m_axis_2 - - - - - - - TDATA - - - m_axis_2_tdata - - - - - TVALID - - - m_axis_2_tvalid - - - - - TREADY - - - m_axis_2_tready - - - - - - - true - - - - - - m_axis_3 - - - - - - - TDATA - - - m_axis_3_tdata - - - - - TVALID - - - m_axis_3_tvalid - - - - - TREADY - - - m_axis_3_tready - - - - - - - true - - - - - - m_axis_4 - - - - - - - TDATA - - - m_axis_4_tdata - - - - - TVALID - - - m_axis_4_tvalid - - - - - TREADY - - - m_axis_4_tready - - - - - - - true - - - - - - m_axis_5 - - - - - - - TDATA - - - m_axis_5_tdata - - - - - TVALID - - - m_axis_5_tvalid - - - - - TREADY - - - m_axis_5_tready - - - - - - - true - - - - - - s_axilite - - - - - - - - - AWADDR - - - awaddr - - - - - AWPROT - - - awprot - - - - - AWVALID - - - awvalid - - - - - AWREADY - - - awready - - - - - WDATA - - - wdata - - - - - WSTRB - - - wstrb - - - - - WVALID - - - wvalid - - - - - WREADY - - - wready - - - - - BRESP - - - bresp - - - - - BVALID - - - bvalid - - - - - BREADY - - - bready - - - - - ARADDR - - - araddr - - - - - ARPROT - - - arprot - - - - - ARVALID - - - arvalid - - - - - ARREADY - - - arready - - - - - RDATA - - - rdata - - - - - RRESP - - - rresp - - - - - RVALID - - - rvalid - - - - - RREADY - - - rready - - - - - - - true - - - - - - aresetn - - - - - - - RST - - - aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - aclk - - - - - - - CLK - - - aclk - - - - - - ASSOCIATED_BUSIF - m_axis_0:m_axis_1:m_axis_2:m_axis_3:m_axis_4:m_axis_5:s_axilite - - - ASSOCIATED_RESET - aresetn - - - - - - - interface_aximm - - reg0 - 0 - 65536 - 32 - register - - - - - - - xilinx_anylanguagesynthesis - Synthesis - :vivado.xilinx.com:synthesis - Verilog - memstream - - xilinx_anylanguagesynthesis_view_fileset - - - - viewChecksum - 1fc5a310 - - - - - xilinx_anylanguagebehavioralsimulation - Simulation - :vivado.xilinx.com:simulation - Verilog - memstream - - xilinx_anylanguagebehavioralsimulation_view_fileset - - - - viewChecksum - d02d9990 - - - - - xilinx_xpgui - UI Layout - :vivado.xilinx.com:xgui.ui - - xilinx_xpgui_view_fileset - - - - viewChecksum - f960907f - - - - - xilinx_utilityxitfiles - Utility XIT/TTCL - :vivado.xilinx.com:xit.util - - xilinx_utilityxitfiles_view_fileset - - - - viewChecksum - d2aad2c5 - - - - - - - aclk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - aresetn - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - awready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - awvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - awaddr - - in - - 15 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - awprot - - in - - 2 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - wready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - wvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - wdata - - in - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - wstrb - - in - - 3 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 1 - - - - - bready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - bvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - 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std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 1 - - - - - m_axis_5_tvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m_axis_5_tdata - - out - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - - CONFIG_EN - Config En - true - - - NSTREAMS - Nstreams - 6 - - - MEM_DEPTH - Mem Depth - 13824 - - - MEM_WIDTH - Mem Width - 32 - - - MEM_INIT - Mem Init - ./ - - - RAM_STYLE - Ram Style - auto - - - STRM0_WIDTH - Strm0 Width - 32 - - - STRM1_WIDTH - Strm1 Width - 32 - - - STRM2_WIDTH - Strm2 Width - 32 - - - STRM3_WIDTH - Strm3 Width - 32 - - - STRM4_WIDTH - Strm4 Width - 32 - - - STRM5_WIDTH - Strm5 Width - 32 - - - STRM0_DEPTH - Strm0 Depth - 2304 - - - STRM1_DEPTH - Strm1 Depth - 2304 - - - STRM2_DEPTH - Strm2 Depth - 2304 - - - STRM3_DEPTH - Strm3 Depth - 2304 - - - STRM4_DEPTH - Strm4 Depth - 2304 - - - STRM5_DEPTH - Strm5 Depth - 2304 - - - STRM0_OFFSET - Strm0 Offset - 0 - - - STRM1_OFFSET - Strm1 Offset - 2304 - - - STRM2_OFFSET - Strm2 Offset - 4608 - - - STRM3_OFFSET - Strm3 Offset - 6912 - - - STRM4_OFFSET - Strm4 Offset - 9216 - - - STRM5_OFFSET - Strm5 Offset - 11520 - - - AXILITE_ADDR_WIDTH - Axilite Addr Width - 16 - - - - - - choice_list_9d8b0d81 - ACTIVE_HIGH - ACTIVE_LOW - - - choice_list_e2bd1cd0 - auto - distributed - block - ultra - - - - - xilinx_anylanguagesynthesis_view_fileset - - hdl/axilite_if.v - verilogSource - - - hdl/memstream.v - verilogSource - - - hdl/memstream_multiblock.v - verilogSource - - - hdl/memstream_singleblock.v - verilogSource - - - hdl/mux.v - verilogSource - - - hdl/ramb18_sdp.v - verilogSource - - - hdl/ramb18_wf_dualport.v - verilogSource - CHECKSUM_9425c051 - - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - hdl/memstream.v - verilogSource - USED_IN_ipstatic - xil_defaultlib - - - hdl/axilite_if.v - verilogSource - USED_IN_ipstatic - xil_defaultlib - - - hdl/memstream_singleblock.v - verilogSource - USED_IN_ipstatic - xil_defaultlib - - - hdl/mux.v - verilogSource - USED_IN_ipstatic - xil_defaultlib - - - hdl/ramb18_wf_dualport.v - verilogSource - USED_IN_ipstatic - xil_defaultlib - - - hdl/memstream_multiblock.v - verilogSource - USED_IN_ipstatic - xil_defaultlib - - - hdl/ramb18_sdp.v - verilogSource - USED_IN_ipstatic - xil_defaultlib - - - - xilinx_xpgui_view_fileset - - xgui/memstream_v1_0.tcl - tclSource - CHECKSUM_f960907f - XGUI_VERSION_2 - - - - xilinx_utilityxitfiles_view_fileset - - gui/memstream_v1_0.gtcl - GTCL - - - - memstream_v1_0 - - - CONFIG_EN - Config En - true - - - NSTREAMS - Nstreams - 6 - - - MEM_DEPTH - Mem Depth - 13824 - - - MEM_WIDTH - Mem Width - 32 - - - MEM_INIT - Mem Init - ./ - - - RAM_STYLE - Ram Style - auto - - - STRM0_WIDTH - Strm0 Width - 32 - - - STRM1_WIDTH - Strm1 Width - 32 - - - STRM2_WIDTH - Strm2 Width - 32 - - - STRM3_WIDTH - Strm3 Width - 32 - - - STRM4_WIDTH - Strm4 Width - 32 - - - STRM5_WIDTH - Strm5 Width - 32 - - - STRM0_DEPTH - Strm0 Depth - 2304 - - - STRM1_DEPTH - Strm1 Depth - 2304 - - - STRM2_DEPTH - Strm2 Depth - 2304 - - - STRM3_DEPTH - Strm3 Depth - 2304 - - - STRM4_DEPTH - Strm4 Depth - 2304 - - - STRM5_DEPTH - Strm5 Depth - 2304 - - - STRM0_OFFSET - Strm0 Offset - 0 - - - STRM1_OFFSET - Strm1 Offset - 2304 - - - STRM2_OFFSET - Strm2 Offset - 4608 - - - STRM3_OFFSET - Strm3 Offset - 6912 - - - STRM4_OFFSET - Strm4 Offset - 9216 - - - STRM5_OFFSET - Strm5 Offset - 11520 - - - AXILITE_ADDR_WIDTH - Axilite Addr Width - 16 - - - - false - - - - - - Component_Name - memstream_v1_0 - - - - - - aartix7 - akintex7 - artix7 - artix7l - azynq - kintex7 - kintex7l - kintexu - kintexuplus - qkintex7 - qkintex7l - qvirtex7 - qzynq - qzynqplus - versal - versalprime - virtex7 - virtexu - virtexuplus - virtexuplusHBM - virtexupluse58g - zynq - zynquplus - - - /UserIP - - memstream_v1_0 - package_project - 5 - 2020-10-09T15:31:57Z - - - 2020.1 - - - - - - - - - diff --git a/finn-rtllib/memstream/gui/memstream_v1_0.gtcl b/finn-rtllib/memstream/gui/memstream_v1_0.gtcl deleted file mode 100644 index a68b85e1f5..0000000000 --- a/finn-rtllib/memstream/gui/memstream_v1_0.gtcl +++ /dev/null @@ -1,2 +0,0 @@ -# This file is automatically written. Do not modify. -proc gen_USERPARAMETER_AXILITE_ADDR_WIDTH_VALUE {MEM_DEPTH MEM_WIDTH } {expr 2+ceil(log($MEM_DEPTH*pow(2,ceil(log(($MEM_WIDTH+31)/32)/log(2))))/log(2))} diff --git a/finn-rtllib/memstream/hdl/Q_srl.v b/finn-rtllib/memstream/hdl/Q_srl.v deleted file mode 100644 index 11cef604e0..0000000000 --- a/finn-rtllib/memstream/hdl/Q_srl.v +++ /dev/null @@ -1,308 +0,0 @@ -// original source: -// https://github.com/nachiket/tdfc/blob/master/verilog/queues/Q_srl_oreg3_prefull_SIMPLE.v - - -// Copyright (c) 1999 The Regents of the University of California -// Copyright (c) 2010 The Regents of the University of Pennsylvania -// Copyright (c) 2011 Department of Electrical and Electronic Engineering, Imperial College London -// Copyright (c) 2020 Xilinx -// -// Permission to use, copy, modify, and distribute this software and -// its documentation for any purpose, without fee, and without a -// written agreement is hereby granted, provided that the above copyright -// notice and this paragraph and the following two paragraphs appear in -// all copies. -// -// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR -// DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING -// LOST PROFITS, ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, -// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF -// SUCH DAMAGE. -// -// THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY -// AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS ON -// AN "AS IS" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO -// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. -// - -// Q_srl_oreg3_prefull_SIMPLE.v -// -// - In-page queue with parameterizable depth, bit width -// - Stream I/O is triple (data, valid, back-pressure), -// with EOS concatenated into the data -// - Flow control for input & output is combinationally decoupled -// - 2 <= depth <= 256 -// * (depth >= 2) is required to decouple I/O flow control, -// where empty => no produce, full => no consume, -// and depth 1 would ping-pong between the two at half rate -// * (depth <= 256) can be modified -// by changing ''synthesis loop_limit X'' below -// and changing ''addrwidth'' or its log computation -// - 1 <= width -// - Queue storage is in SRL16E, up to depth 16 per LUT per bit-slice, -// plus output register (for fast output) -// - Queue addressing is done by ''addr'' up-down counter -// - Queue fullness is checked by comparator (addr==depth) -// - Queue fullness is pre-computed for next cycle -// - Queue input back-pressure is pre-computed for next cycle -// - Queue output valid (state!=state__empty) is pre-computed for next cycle -// (necessary since SRL data output reg requires non-boolean state) -// - FSM has 3 states (empty, one, more) -// - When empty, continue to emit most recently emitted value (for debugging) -// -// - Queue slots used = / (state==state_empty) ? 0 -// | (state==state_one) ? 1 -// \ (state==state_more) ? addr+2 -// - Queue slots used <= depth -// - Queue slots remaining = depth - used -// = / (state==state_empty) ? depth -// | (state==state_one) ? depth-1 -// \ (state==state_more) ? depth-2-addr -// -// - Synplify 7.1 / 8.0 -// - Eylon Caspi, 9/11/03, 8/18/04, 3/29/05 - - -`ifdef Q_srl -`else -`define Q_srl - - -module Q_srl (clock, reset, i_d, i_v, i_r, o_d, o_v, o_r, count, maxcount); - - parameter depth = 16; // - greatest #items in queue (2 <= depth <= 256) - parameter width = 16; // - width of data (i_d, o_d) - - parameter addrwidth = $clog2(depth); - - input clock; - input reset; - - input [width-1:0] i_d; // - input stream data (concat data + eos) - input i_v; // - input stream valid - output i_r; // - input stream ready - wire i_b; // - input stream back-pressure - - output [width-1:0] o_d; // - output stream data (concat data + eos) - output o_v; // - output stream valid - input o_r; // - output stream ready - wire o_b; // - output stream back-pressure - - output [addrwidth:0] count; // - output number of elems in queue - output [addrwidth:0] maxcount; // - maximum observed count since reset - - reg [addrwidth:0] maxcount_reg; // - maximum count seen until now - reg [addrwidth-1:0] addr, addr_, a_; // - SRL16 address - // for data output - reg shift_en_; // - SRL16 shift enable - reg [width-1:0] srl [depth-2:0]; // - SRL16 memory - reg shift_en_o_; // - SRLO shift enable - reg [width-1:0] srlo_, srlo // - SRLO output reg - /* synthesis syn_allow_retiming=0 */ ; - - parameter state_empty = 2'd0; // - state empty : o_v=0 o_d=UNDEFINED - parameter state_one = 2'd1; // - state one : o_v=1 o_d=srlo - parameter state_more = 2'd2; // - state more : o_v=1 o_d=srlo - // #items in srl = addr+2 - - reg [1:0] state, state_; // - state register - - wire addr_full_; // - true iff addr==depth-2 on NEXT cycle - reg addr_full; // - true iff addr==depth-2 - wire addr_zero_; // - true iff addr==0 - wire o_v_reg_; // - true iff state_empty on NEXT cycle - reg o_v_reg // - true iff state_empty - /* synthesis syn_allow_retiming=0 */ ; - wire i_b_reg_; // - true iff !full on NEXT cycle - reg i_b_reg // - true iff !full - /* synthesis syn_allow_retiming=0 */ ; - - assign addr_full_ = (state_==state_more) && (addr_==depth-2); - // - queue full - assign addr_zero_ = (addr==0); // - queue contains 2 (or 1,0) - assign o_v_reg_ = (state_!=state_empty); // - output valid if non-empty - assign i_b_reg_ = addr_full_; // - input bp if full - assign o_d = srlo; // - output data from queue - assign o_v = o_v_reg; // - output valid if non-empty - assign i_b = i_b_reg; // - input bp if full - assign maxcount = maxcount_reg; - - assign i_r = !i_b; - assign o_b = !o_r; - - assign count = (state==state_more ? addr+2 : (state==state_one ? 1 : 0)); - - // - ''always'' block with both FFs and SRL16 does not work, - // since FFs need reset but SRL16 does not - - always @(posedge clock) begin // - seq always: FFs - if (reset) begin - state <= state_empty; - addr <= 0; - addr_full <= 0; - o_v_reg <= 0; - - i_b_reg <= 0; - maxcount_reg <= 0; - - end - else begin - state <= state_; - addr <= addr_; - addr_full <= addr_full_; - o_v_reg <= o_v_reg_; - i_b_reg <= i_b_reg_; - maxcount_reg <= (count > maxcount_reg ? count : maxcount_reg); - end - end // always @ (posedge clock) - - always @(posedge clock) begin // - seq always: srlo - // - infer enabled output reg at end of shift chain - // - input first element from i_d, all subsequent elements from SRL16 - if (reset) begin - srlo <= 0; - end - else begin - if (shift_en_o_) begin - srlo <= srlo_; - end - end - end // always @ (posedge clock) - - always @(posedge clock) begin // - seq always: srl - // - infer enabled SRL16E from shifting srl array - // - no reset capability; srl[] contents undefined on reset - if (shift_en_) begin - // synthesis loop_limit 256 - for (a_=depth-2; a_>0; a_=a_-1) begin - srl[a_] = srl[a_-1]; - end - srl[0] <= i_d; - end - end // always @ (posedge clock or negedge reset) - - always @* begin // - combi always - srlo_ <= 'bx; - shift_en_o_ <= 1'bx; - shift_en_ <= 1'bx; - addr_ <= 'bx; - state_ <= 2'bx; - case (state) - - state_empty: begin // - (empty, will not produce) - if (i_v) begin // - empty & i_v => consume - srlo_ <= i_d; - shift_en_o_ <= 1; - shift_en_ <= 1'bx; - addr_ <= 0; - state_ <= state_one; - end - else begin // - empty & !i_v => idle - srlo_ <= 'bx; - shift_en_o_ <= 0; - shift_en_ <= 1'bx; - addr_ <= 0; - state_ <= state_empty; - end - end - - state_one: begin // - (contains one) - if (i_v && o_b) begin // - one & i_v & o_b => consume - srlo_ <= 'bx; - shift_en_o_ <= 0; - shift_en_ <= 1; - addr_ <= 0; - state_ <= state_more; - end - else if (i_v && !o_b) begin // - one & i_v & !o_b => cons+prod - srlo_ <= i_d; - shift_en_o_ <= 1; - shift_en_ <= 1; - addr_ <= 0; - state_ <= state_one; - end - else if (!i_v && o_b) begin // - one & !i_v & o_b => idle - srlo_ <= 'bx; - shift_en_o_ <= 0; - shift_en_ <= 1'bx; - addr_ <= 0; - state_ <= state_one; - end - else if (!i_v && !o_b) begin // - one & !i_v & !o_b => produce - srlo_ <= 'bx; - shift_en_o_ <= 0; - shift_en_ <= 1'bx; - addr_ <= 0; - state_ <= state_empty; - end - end // case: state_one - - state_more: begin // - (contains more than one) - if (addr_full || (depth==2)) begin - // - (full, will not consume) - // - (full here if depth==2) - if (o_b) begin // - full & o_b => idle - srlo_ <= 'bx; - shift_en_o_ <= 0; - shift_en_ <= 0; - addr_ <= addr; - state_ <= state_more; - end - else begin // - full & !o_b => produce - srlo_ <= srl[addr]; - shift_en_o_ <= 1; - shift_en_ <= 0; -// addr_ <= addr-1; -// state_ <= state_more; - addr_ <= addr_zero_ ? 0 : addr-1; - state_ <= addr_zero_ ? state_one : state_more; - end - end - else begin // - (mid: neither empty nor full) - if (i_v && o_b) begin // - mid & i_v & o_b => consume - srlo_ <= 'bx; - shift_en_o_ <= 0; - shift_en_ <= 1; - addr_ <= addr+1; - state_ <= state_more; - end - else if (i_v && !o_b) begin // - mid & i_v & !o_b => cons+prod - srlo_ <= srl[addr]; - shift_en_o_ <= 1; - shift_en_ <= 1; - addr_ <= addr; - state_ <= state_more; - end - else if (!i_v && o_b) begin // - mid & !i_v & o_b => idle - srlo_ <= 'bx; - shift_en_o_ <= 0; - shift_en_ <= 0; - addr_ <= addr; - state_ <= state_more; - end - else if (!i_v && !o_b) begin // - mid & !i_v & !o_b => produce - srlo_ <= srl[addr]; - shift_en_o_ <= 1; - shift_en_ <= 0; - addr_ <= addr_zero_ ? 0 : addr-1; - state_ <= addr_zero_ ? state_one : state_more; - end - end // else: !if(addr_full) - end // case: state_more - - default: begin - srlo_ <= 'bx; - shift_en_o_ <= 1'bx; - shift_en_ <= 1'bx; - addr_ <= 'bx; - state_ <= 2'bx; - end // case: default - - endcase // case(state) - end // always @ * - -endmodule // Q_srl - - -`endif // `ifdef Q_srl diff --git a/finn-rtllib/memstream/hdl/memstream.sv b/finn-rtllib/memstream/hdl/memstream.sv new file mode 100644 index 0000000000..9cbef493a3 --- /dev/null +++ b/finn-rtllib/memstream/hdl/memstream.sv @@ -0,0 +1,176 @@ +/** + * Copyright (c) 2023, Xilinx + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of FINN nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * @author Thomas B. Preußer + */ + +module memstream #( + int unsigned DEPTH, + int unsigned WIDTH, + + parameter INIT_FILE = "", + parameter RAM_STYLE = "auto" +)( + input logic clk, + input logic rst, + + // Configuration and readback interface - compatible with ap_memory + input logic config_ce, + input logic config_we, + input logic [31 :0] config_address, + input logic [WIDTH-1:0] config_d0, + + output logic config_rack, + output logic [WIDTH-1:0] config_q0, + + // Continuous output stream + input logic ordy, + output logic ovld, + output logic [WIDTH-1:0] odat +); + + typedef logic [$clog2(DEPTH)-1:0] addr_t; + typedef logic [WIDTH -1:0] data_t; + + uwire en; // Pipeline enable + uwire rollback; // Rollback stream reads if backpressure would block read back + + // Counter with pre-computed last indication for val == DEPTH-1 + typedef struct { + addr_t val; + logic lst; + } ptr_t; + + // Counter history to facilitate pipeline rollback + ptr_t Ptr[3] = '{ + 0: '{ val: 0, lst: DEPTH<2 }, + default: '{ default: 'x } + }; + + //----------------------------------------------------------------------- + // Stage #0: Address & Op + logic Wr1 = 0; // Write + logic Rb1 = 0; // Read back + logic Rs1 = 0; // Read stream + data_t Data1 = 'x; + if(1) begin : blkStage1 + // Increment for wrapping DEPTH-1 back to zero + localparam int unsigned WRAP_INC = 2**$bits(addr_t) - DEPTH + 1; + + uwire ptr_t ptr_eff = rollback? Ptr[2] : Ptr[0]; + uwire ptr_t ptr_nxt; + assign ptr_nxt.val = ptr_eff.val + (config_ce? 0 : !ptr_eff.lst? 1 : WRAP_INC); + assign ptr_nxt.lst = + DEPTH < 2? 1 : + config_ce? ptr_eff.lst : + ptr_eff.lst? 0 : + /* else */ ptr_eff.val == DEPTH-2; + + always_ff @(posedge clk) begin + if(rst) Ptr[0] <= '{ val: 0, lst: DEPTH<2 }; + else if(en) Ptr[0] <= ptr_nxt; + end + + // Issue next Memory Operation + always_ff @(posedge clk) begin + if(rst) begin + Wr1 <= 0; + Rb1 <= 0; + Rs1 <= 0; + Ptr[1] <= '{ default : 'x }; + Data1 <= 'x; + end + else if(en) begin + Wr1 <= 0; + Rb1 <= 0; + Rs1 <= 0; + if(config_ce) begin + if(config_we) Wr1 <= 1; + else Rb1 <= 1; + Ptr[1] <= '{ val: config_address, lst: 'x }; + Data1 <= config_d0; + end + else begin + Rs1 <= 1; + Ptr[1] <= ptr_eff; + Data1 <= 'x; + end + end + end + end : blkStage1 + + //----------------------------------------------------------------------- + // Stage #2: Memory Access + logic Rb2 = 0; + logic Rs2 = 0; + data_t Data2 = 'x; + if(1) begin : blkStage2 + (* RAM_STYLE = RAM_STYLE *) + data_t Mem[DEPTH]; + + // Optional Memory Initialization + if(INIT_FILE != "") initial $readmemh(INIT_FILE, Mem); + + // Execute Memory Operation + uwire addr_t addr = Ptr[1].val; + always_ff @(posedge clk) begin + if(en) begin + if(Wr1) Mem[addr] <= Data1; + Data2 <= Mem[addr]; + end + end + + // Copy Output Designation + always_ff @(posedge clk) begin + if(rst) begin + Rb2 <= 0; + Rs2 <= 0; + Ptr[2] <= '{ default: 'x }; + end + else if(en) begin + Rb2 <= Rb1; + Rs2 <= Rs1 && !rollback; + Ptr[2] <= Ptr[1]; + end + end + end : blkStage2 + + //----------------------------------------------------------------------- + // Output Interfaces + assign config_rack = Rb2; + assign config_q0 = Data2; + + assign ovld = Rs2; + assign odat = Data2; + + uwire backpressure = Rs2 && !ordy; + assign rollback = backpressure && (Rb1 || config_ce); + assign en = !backpressure || Rb1 || config_ce; + +endmodule : memstream diff --git a/finn-rtllib/memstream/hdl/memstream.v b/finn-rtllib/memstream/hdl/memstream.v deleted file mode 100644 index 2cd955f8d1..0000000000 --- a/finn-rtllib/memstream/hdl/memstream.v +++ /dev/null @@ -1,327 +0,0 @@ -/* - Copyright (c) 2020, Xilinx - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - * Neither the name of FINN nor the names of its - contributors may be used to endorse or promote products derived from - this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -module memstream -#( -//parameters to enable/disable axi-mm, set number of streams, set readmemh for memory, set per-stream offsets in memory, set per-stream widths - parameter CONFIG_EN = 1, - parameter NSTREAMS = 6,//1 up to 6 - - parameter MEM_DEPTH = 13824, - parameter MEM_WIDTH = 32, - parameter MEM_INIT = "./", - parameter RAM_STYLE = "auto", - - //widths per stream - parameter STRM0_WIDTH = 32, - parameter STRM1_WIDTH = 32, - parameter STRM2_WIDTH = 32, - parameter STRM3_WIDTH = 32, - parameter STRM4_WIDTH = 32, - parameter STRM5_WIDTH = 32, - - //depths per stream - parameter STRM0_DEPTH = 2304, - parameter STRM1_DEPTH = 2304, - parameter STRM2_DEPTH = 2304, - parameter STRM3_DEPTH = 2304, - parameter STRM4_DEPTH = 2304, - parameter STRM5_DEPTH = 2304, - - //offsets for each stream - parameter STRM0_OFFSET = 0, - parameter STRM1_OFFSET = 2304, - parameter STRM2_OFFSET = 4608, - parameter STRM3_OFFSET = 6912, - parameter STRM4_OFFSET = 9216, - parameter STRM5_OFFSET = 11520, - - parameter AXILITE_ADDR_WIDTH = 2+$clog2(MEM_DEPTH*(1<<$clog2((MEM_WIDTH+31)/32))) -) - -( - input aclk, - input aresetn, - - output awready, - input awvalid, - input [AXILITE_ADDR_WIDTH-1:0] awaddr, - input [2:0] awprot, - //write data - output wready, - input wvalid, - input [31:0] wdata, - input [3:0] wstrb, - //burst response - input bready, - output bvalid, - output [1:0] bresp, - - //Read channels - //read address - output arready, - input arvalid, - input [AXILITE_ADDR_WIDTH-1:0] araddr, - input [2:0] arprot, - //read data - input rready, - output rvalid, - output [1:0] rresp, - output [31:0] rdata, - - //multiple output AXI Streams, TDATA width rounded to multiple of 8 bits - input m_axis_0_afull, - input m_axis_0_tready, - output m_axis_0_tvalid, - output [((STRM0_WIDTH+7)/8)*8-1:0] m_axis_0_tdata, - - input m_axis_1_afull, - input m_axis_1_tready, - output m_axis_1_tvalid, - output [((STRM1_WIDTH+7)/8)*8-1:0] m_axis_1_tdata, - - input m_axis_2_afull, - input m_axis_2_tready, - output m_axis_2_tvalid, - output [((STRM2_WIDTH+7)/8)*8-1:0] m_axis_2_tdata, - - input m_axis_3_afull, - input m_axis_3_tready, - output m_axis_3_tvalid, - output [((STRM3_WIDTH+7)/8)*8-1:0] m_axis_3_tdata, - - input m_axis_4_afull, - input m_axis_4_tready, - output m_axis_4_tvalid, - output [((STRM4_WIDTH+7)/8)*8-1:0] m_axis_4_tdata, - - input m_axis_5_afull, - input m_axis_5_tready, - output m_axis_5_tvalid, - output [((STRM5_WIDTH+7)/8)*8-1:0] m_axis_5_tdata - - -); - -wire [31:0] config_address; -wire config_ce; -wire config_we; -wire config_rack; -wire [MEM_WIDTH-1:0] config_d0; -wire [MEM_WIDTH-1:0] config_q0; - -generate -if(NSTREAMS <= 2) begin: singleblock - - -memstream_singleblock -#( - .CONFIG_EN(CONFIG_EN), - .NSTREAMS(NSTREAMS), - .MEM_DEPTH(MEM_DEPTH), - .MEM_WIDTH(MEM_WIDTH), - .MEM_INIT(MEM_INIT), - .RAM_STYLE(RAM_STYLE), - - //widths per stream - .STRM0_WIDTH(STRM0_WIDTH), - .STRM1_WIDTH(STRM1_WIDTH), - - //depths per stream - .STRM0_DEPTH(STRM0_DEPTH), - .STRM1_DEPTH(STRM1_DEPTH), - - //offsets for each stream - .STRM0_OFFSET(STRM0_OFFSET), - .STRM1_OFFSET(STRM1_OFFSET) -) -mem -( - .aclk(aclk), - .aresetn(aresetn), - - .config_address(config_address), - .config_ce(config_ce), - .config_we(config_we), - .config_d0(config_d0), - .config_q0(config_q0), - .config_rack(config_rack), - - .m_axis_0_tready(m_axis_0_tready), - .m_axis_0_tvalid(m_axis_0_tvalid), - .m_axis_0_tdata(m_axis_0_tdata), - - .m_axis_1_tready(m_axis_1_tready), - .m_axis_1_tvalid(m_axis_1_tvalid), - .m_axis_1_tdata(m_axis_1_tdata) -); - -assign m_axis_2_tvalid = 0; -assign m_axis_2_tdata = 0; -assign m_axis_3_tvalid = 0; -assign m_axis_3_tdata = 0; -assign m_axis_4_tvalid = 0; -assign m_axis_4_tdata = 0; -assign m_axis_5_tvalid = 0; -assign m_axis_5_tdata = 0; - -end else begin: multiblock - - -memstream_multiblock -#( - .CONFIG_EN(CONFIG_EN), - .NSTREAMS(NSTREAMS), - .MEM_DEPTH(MEM_DEPTH), - .MEM_WIDTH(MEM_WIDTH), - .MEM_INIT(MEM_INIT), - .RAM_STYLE(RAM_STYLE), - - //widths per stream - .STRM0_WIDTH(STRM0_WIDTH), - .STRM1_WIDTH(STRM1_WIDTH), - .STRM2_WIDTH(STRM2_WIDTH), - .STRM3_WIDTH(STRM3_WIDTH), - .STRM4_WIDTH(STRM4_WIDTH), - .STRM5_WIDTH(STRM5_WIDTH), - - //depths per stream - .STRM0_DEPTH(STRM0_DEPTH), - .STRM1_DEPTH(STRM1_DEPTH), - .STRM2_DEPTH(STRM2_DEPTH), - .STRM3_DEPTH(STRM3_DEPTH), - .STRM4_DEPTH(STRM4_DEPTH), - .STRM5_DEPTH(STRM5_DEPTH), - - //offsets for each stream - .STRM0_OFFSET(STRM0_OFFSET), - .STRM1_OFFSET(STRM1_OFFSET), - .STRM2_OFFSET(STRM2_OFFSET), - .STRM3_OFFSET(STRM3_OFFSET), - .STRM4_OFFSET(STRM4_OFFSET), - .STRM5_OFFSET(STRM5_OFFSET) -) -mem -( - .aclk(aclk), - .aresetn(aresetn), - - .config_address(config_address), - .config_ce(config_ce), - .config_we(config_we), - .config_d0(config_d0), - .config_q0(config_q0), - - .m_axis_0_afull(m_axis_0_afull), - .m_axis_0_tready(m_axis_0_tready), - .m_axis_0_tvalid(m_axis_0_tvalid), - .m_axis_0_tdata(m_axis_0_tdata), - - .m_axis_1_afull(m_axis_1_afull), - .m_axis_1_tready(m_axis_1_tready), - .m_axis_1_tvalid(m_axis_1_tvalid), - .m_axis_1_tdata(m_axis_1_tdata), - - .m_axis_2_afull(m_axis_2_afull), - .m_axis_2_tready(m_axis_2_tready), - .m_axis_2_tvalid(m_axis_2_tvalid), - .m_axis_2_tdata(m_axis_2_tdata), - - .m_axis_3_afull(m_axis_3_afull), - .m_axis_3_tready(m_axis_3_tready), - .m_axis_3_tvalid(m_axis_3_tvalid), - .m_axis_3_tdata(m_axis_3_tdata), - - .m_axis_4_afull(m_axis_4_afull), - .m_axis_4_tready(m_axis_4_tready), - .m_axis_4_tvalid(m_axis_4_tvalid), - .m_axis_4_tdata(m_axis_4_tdata), - - .m_axis_5_afull(m_axis_5_afull), - .m_axis_5_tready(m_axis_5_tready), - .m_axis_5_tvalid(m_axis_5_tvalid), - .m_axis_5_tdata(m_axis_5_tdata) - -); - - -end -endgenerate - -axi4lite_if -#( - .ADDR_WIDTH(AXILITE_ADDR_WIDTH), - .DATA_WIDTH(32), - .IP_DATA_WIDTH(MEM_WIDTH) -) -config_if -( - //system signals - .aclk(aclk), - .aresetn(aresetn), - - //Write channels - //write address - .awready(awready), - .awvalid(awvalid), - .awaddr(awaddr), - .awprot(awprot), - //write data - .wready(wready), - .wvalid(wvalid), - .wdata(wdata), - .wstrb(wstrb), - //burst response - .bready(bready), - .bvalid(bvalid), - .bresp(bresp), - - //Read channels - //read address - .arready(arready), - .arvalid(arvalid), - .araddr(araddr), - .arprot(arprot), - //read data - .rready(rready), - .rvalid(rvalid), - .rresp(rresp), - .rdata(rdata), - - //IP-side interface - .ip_en(config_ce), - .ip_wen(config_we), - .ip_addr(config_address), - .ip_wdata(config_d0), - .ip_rack(config_rack), - .ip_rdata(config_q0) -); - -endmodule diff --git a/finn-rtllib/memstream/hdl/memstream_axi.sv b/finn-rtllib/memstream/hdl/memstream_axi.sv new file mode 100644 index 0000000000..620d9ec1de --- /dev/null +++ b/finn-rtllib/memstream/hdl/memstream_axi.sv @@ -0,0 +1,136 @@ +/** + * Copyright (c) 2023, Xilinx + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of FINN nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * @author Thomas B. Preußer + */ + +module memstream_axi #( + int unsigned DEPTH, + int unsigned WIDTH, + + parameter INIT_FILE = "", + parameter RAM_STYLE = "auto", + + localparam int unsigned AXILITE_ADDR_WIDTH = $clog2(DEPTH * (2**$clog2((WIDTH+31)/32))) + 2 +)( + // Global Control + input logic clk, + input logic rst, + + // AXI-lite Write + output logic awready, + input logic awvalid, + input logic [2:0] awprot, + input logic [AXILITE_ADDR_WIDTH-1:0] awaddr, + + output logic wready, + input logic wvalid, + input logic [31:0] wdata, + input logic [ 3:0] wstrb, + + input logic bready, + output logic bvalid, + output logic [1:0] bresp, + + // AXI-lite Read + output loigc arready, + input loigc arvalid, + input loigc [2:0] arprot, + input loigc [AXILITE_ADDR_WIDTH-1:0] araddr, + + input loigc rready, + output loigc rvalid, + output logic [ 1:0] rresp, + output loigc [31:0] rdata, + + // Continuous output stream + input logic m_axis_0_tready, + output logic m_axis_0_tvalid, + output logic [((WIDTH+7)/8)*8-1:0] m_axis_0_tdata +); + + //----------------------------------------------------------------------- + // AXI-lite to ap_memory Adapter + uwire [31:0] config_address; + uwire config_ce; + uwire config_we; + uwire config_rack; + uwire [WIDTH-1:0] config_d0; + uwire [WIDTH-1:0] config_q0; + axi4lite_if #( + .ADDR_WIDTH(AXILITE_ADDR_WIDTH), + .DATA_WIDTH(32), + .IP_DATA_WIDTH(WIDTH) + ) config_if ( + .aclk(clk), .aresetn(!rst), + + // Write Channels + .awready, .awvalid, .awaddr, .awprot, + .wready, .wvalid, .wdata, .wstrb, + .bready, .bvalid, .bresp, + + // Read Channels + .arready, .arvalid, .araddr, .arprot, + .rready, .rvalid, .rresp, .rdata, + + // IP-side Interface + .ip_en(config_ce), + .ip_wen(config_we), + .ip_addr(config_address), + .ip_wdata(config_d0), + .ip_rack(config_rack), + .ip_rdata(config_q0) + ); + + //----------------------------------------------------------------------- + // Streaming Memory Backend + memstream #( + .DEPTH(DEPTH), + .WIDTH(WIDTH), + .INIT_FILE(INIT_FILE), + .RAM_STYLE(RAM_STYLE) + ) mem ( + .clk, .rst, + + .config_address, + .config_ce, + .config_we, + .config_d0, + .config_q0, + .config_rack, + + .ordy(m_axis_0_tready), + .ovld(m_axis_0_tvalid), + .odat(m_axis_0_tdata[WIDTH-1:0]) + ); + if($bits(m_axis_0_tdata) > WIDTH) begin + assign m_axis_0_tdata[$left(m_axis_0_tdata):WIDTH] <= '0; + end + +endmodule : memstream_axi diff --git a/finn-rtllib/memstream/hdl/memstream_multiblock.v b/finn-rtllib/memstream/hdl/memstream_multiblock.v deleted file mode 100644 index 4e6167132d..0000000000 --- a/finn-rtllib/memstream/hdl/memstream_multiblock.v +++ /dev/null @@ -1,474 +0,0 @@ -/* - Copyright (c) 2020, Xilinx - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - * Neither the name of FINN nor the names of its - contributors may be used to endorse or promote products derived from - this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -module memstream_multiblock -#( -//parameters to enable/disable axi-mm, set number of streams, set readmemh for memory, set per-stream offsets in memory, set per-stream widths - parameter CONFIG_EN = 1, - parameter NSTREAMS = 6,//1 up to 6 - - parameter MEM_DEPTH = 13824, - parameter MEM_WIDTH = 32, - parameter MEM_INIT = "./", - parameter RAM_STYLE = "auto", - - //widths per stream - parameter STRM0_WIDTH = 32, - parameter STRM1_WIDTH = 32, - parameter STRM2_WIDTH = 32, - parameter STRM3_WIDTH = 32, - parameter STRM4_WIDTH = 32, - parameter STRM5_WIDTH = 32, - - //depths per stream - parameter STRM0_DEPTH = 2304, - parameter STRM1_DEPTH = 2304, - parameter STRM2_DEPTH = 2304, - parameter STRM3_DEPTH = 2304, - parameter STRM4_DEPTH = 2304, - parameter STRM5_DEPTH = 2304, - - //offsets for each stream - parameter STRM0_OFFSET = 0, - parameter STRM1_OFFSET = 2304, - parameter STRM2_OFFSET = 4608, - parameter STRM3_OFFSET = 6912, - parameter STRM4_OFFSET = 9216, - parameter STRM5_OFFSET = 11520 -) - -( - input aclk, - input aresetn, - - //optional configuration interface compatible with ap_memory - input [31:0] config_address, - input config_ce, - input config_we, - input [31:0] config_d0, - output [31:0] config_q0, - output config_rack, - - //multiple output AXI Streams, TDATA width rounded to multiple of 8 bits - input m_axis_0_afull, - input m_axis_0_tready, - output m_axis_0_tvalid, - output [((STRM0_WIDTH+7)/8)*8-1:0] m_axis_0_tdata, - - input m_axis_1_afull, - input m_axis_1_tready, - output m_axis_1_tvalid, - output [((STRM1_WIDTH+7)/8)*8-1:0] m_axis_1_tdata, - - input m_axis_2_afull, - input m_axis_2_tready, - output m_axis_2_tvalid, - output [((STRM2_WIDTH+7)/8)*8-1:0] m_axis_2_tdata, - - input m_axis_3_afull, - input m_axis_3_tready, - output m_axis_3_tvalid, - output [((STRM3_WIDTH+7)/8)*8-1:0] m_axis_3_tdata, - - input m_axis_4_afull, - input m_axis_4_tready, - output m_axis_4_tvalid, - output [((STRM4_WIDTH+7)/8)*8-1:0] m_axis_4_tdata, - - input m_axis_5_afull, - input m_axis_5_tready, - output m_axis_5_tvalid, - output [((STRM5_WIDTH+7)/8)*8-1:0] m_axis_5_tdata - - -); - -//calculate number of RAMB18 blocks we need depth-wise -localparam NMEMBLOCKS = (MEM_DEPTH+1023) / 1024; //ceil(MEM_DEPTH/1024) - -//calculate width of address for each block -localparam BLOCKADRWIDTH = NMEMBLOCKS > 1 ? 10 : $clog2(MEM_DEPTH); - -//determine whether a stream needs to multiplex between memory blocks -localparam STRM0_MUX = ((STRM0_OFFSET/1024) != ((STRM0_OFFSET+STRM0_DEPTH)/1024)); -localparam STRM1_MUX = ((STRM1_OFFSET/1024) != ((STRM1_OFFSET+STRM1_DEPTH)/1024)); -localparam STRM2_MUX = ((STRM2_OFFSET/1024) != ((STRM2_OFFSET+STRM2_DEPTH)/1024)); -localparam STRM3_MUX = ((STRM3_OFFSET/1024) != ((STRM3_OFFSET+STRM3_DEPTH)/1024)); -localparam STRM4_MUX = ((STRM4_OFFSET/1024) != ((STRM4_OFFSET+STRM4_DEPTH)/1024)); -localparam STRM5_MUX = ((STRM5_OFFSET/1024) != ((STRM5_OFFSET+STRM5_DEPTH)/1024)); - -//determine what the base block of each stream is -localparam STRM0_BLOCK = (STRM0_OFFSET/1024); -localparam STRM1_BLOCK = (STRM1_OFFSET/1024); -localparam STRM2_BLOCK = (STRM2_OFFSET/1024); -localparam STRM3_BLOCK = (STRM3_OFFSET/1024); -localparam STRM4_BLOCK = (STRM4_OFFSET/1024); -localparam STRM5_BLOCK = (STRM5_OFFSET/1024); - -//determine what the end block of each stream is -localparam STRM0_END_BLOCK = ((STRM0_OFFSET+STRM0_DEPTH-1)/1024); -localparam STRM1_END_BLOCK = ((STRM1_OFFSET+STRM1_DEPTH-1)/1024); -localparam STRM2_END_BLOCK = ((STRM2_OFFSET+STRM2_DEPTH-1)/1024); -localparam STRM3_END_BLOCK = ((STRM3_OFFSET+STRM3_DEPTH-1)/1024); -localparam STRM4_END_BLOCK = ((STRM4_OFFSET+STRM4_DEPTH-1)/1024); -localparam STRM5_END_BLOCK = ((STRM5_OFFSET+STRM5_DEPTH-1)/1024); - -//determine the number of blocks spanned by each stream -localparam STRM0_NBLOCKS = STRM0_END_BLOCK - STRM0_BLOCK + 1; -localparam STRM1_NBLOCKS = STRM1_END_BLOCK - STRM1_BLOCK + 1; -localparam STRM2_NBLOCKS = STRM2_END_BLOCK - STRM2_BLOCK + 1; -localparam STRM3_NBLOCKS = STRM3_END_BLOCK - STRM3_BLOCK + 1; -localparam STRM4_NBLOCKS = STRM4_END_BLOCK - STRM4_BLOCK + 1; -localparam STRM5_NBLOCKS = STRM5_END_BLOCK - STRM5_BLOCK + 1; - -//TODO: check that memory width is equal to the widest stream -//TODO: check that the stream depths and offsets make sense, and that the memory depth is sufficient (or calculate depth here?) -initial begin - if((NSTREAMS < 1) | (NSTREAMS > 6)) begin - $display("Invalid setting for NSTREAMS, please set in range [1,6]"); - $finish(); - end -end - -//invert reset -wire rst; -assign rst = ~aresetn; - -//WARNING: pipeline depth is larger than the number of streams per port so we have in-flight writes that may see not-ready when they get executed -//solution: use prog-full to make sure we have an equal number of free slots in the stream to the read pipeline depth - -reg [$clog2(MEM_DEPTH)-1:0] strm0_addr = STRM0_OFFSET; -reg [$clog2(MEM_DEPTH)-1:0] strm1_addr = STRM1_OFFSET; -reg [$clog2(MEM_DEPTH)-1:0] strm2_addr = STRM2_OFFSET; -reg [$clog2(MEM_DEPTH)-1:0] strm3_addr = STRM3_OFFSET; -reg [$clog2(MEM_DEPTH)-1:0] strm4_addr = STRM4_OFFSET; -reg [$clog2(MEM_DEPTH)-1:0] strm5_addr = STRM5_OFFSET; - -reg strm0_incr_en; -reg strm1_incr_en; -reg strm2_incr_en; -reg strm3_incr_en; -reg strm4_incr_en; -reg strm5_incr_en; - -wire strm0_rst; -wire strm1_rst; -wire strm2_rst; -wire strm3_rst; -wire strm4_rst; -wire strm5_rst; - -reg strm0_ready; -reg strm1_ready; -reg strm2_ready; -reg strm3_ready; -reg strm4_ready; -reg strm5_ready; - -//arbiter: work on one stream at a time -//multiplex each port between (up to) half of the streams -reg [1:0] current_stream_porta = 0; -reg [1:0] current_stream_portb = 0; - -always @(posedge aclk) begin - if(rst) - current_stream_porta <= 0; - else case(current_stream_porta) - 0: current_stream_porta <= strm2_ready ? 1 : strm4_ready ? 2 : 0; - 1: current_stream_porta <= strm4_ready ? 2 : strm0_ready ? 0 : 1; - 2: current_stream_porta <= strm0_ready ? 0 : strm2_ready ? 1 : 2; - endcase - if(rst) - current_stream_portb <= 0; - else case(current_stream_portb) - 0: current_stream_portb <= strm3_ready ? 1 : strm5_ready ? 2 : 0; - 1: current_stream_portb <= strm5_ready ? 2 : strm1_ready ? 0 : 1; - 2: current_stream_portb <= strm1_ready ? 0 : strm3_ready ? 1 : 2; - endcase -end - -always @(posedge aclk) begin - if(rst) begin - strm0_incr_en <= 0; - strm1_incr_en <= 0; - strm2_incr_en <= 0; - strm3_incr_en <= 0; - strm4_incr_en <= 0; - strm5_incr_en <= 0; - end else begin - strm0_incr_en <= (current_stream_porta == 0) & strm0_ready; - strm1_incr_en <= (current_stream_portb == 0) & strm1_ready; - strm2_incr_en <= (current_stream_porta == 1) & strm2_ready; - strm3_incr_en <= (current_stream_portb == 1) & strm3_ready; - strm4_incr_en <= (current_stream_porta == 2) & strm4_ready; - strm5_incr_en <= (current_stream_portb == 2) & strm5_ready; - end -end - -assign strm0_rst = strm0_incr_en & (strm0_addr == (STRM0_OFFSET + STRM0_DEPTH-1)); -assign strm1_rst = strm1_incr_en & (strm1_addr == (STRM1_OFFSET + STRM1_DEPTH-1)); -assign strm2_rst = strm2_incr_en & (strm2_addr == (STRM2_OFFSET + STRM2_DEPTH-1)); -assign strm3_rst = strm3_incr_en & (strm3_addr == (STRM3_OFFSET + STRM3_DEPTH-1)); -assign strm4_rst = strm4_incr_en & (strm4_addr == (STRM4_OFFSET + STRM4_DEPTH-1)); -assign strm5_rst = strm5_incr_en & (strm5_addr == (STRM5_OFFSET + STRM5_DEPTH-1)); - -always @(posedge aclk) begin - strm0_ready <= ~m_axis_0_afull; - strm1_ready <= ~m_axis_1_afull & (NSTREAMS >= 2); - strm2_ready <= ~m_axis_2_afull & (NSTREAMS >= 3); - strm3_ready <= ~m_axis_3_afull & (NSTREAMS >= 4); - strm4_ready <= ~m_axis_4_afull & (NSTREAMS >= 5); - strm5_ready <= ~m_axis_5_afull & (NSTREAMS >= 6); -end - -//one address counter per stream; more LUTs but keeps routing short and local -always @(posedge aclk) begin - if(strm0_rst | rst) - strm0_addr <= STRM0_OFFSET; - else if(strm0_incr_en) - strm0_addr <= strm0_addr + 1; - if(strm1_rst | rst) - strm1_addr <= STRM1_OFFSET; - else if(strm1_incr_en) - strm1_addr <= strm1_addr + 1; - if(strm2_rst | rst) - strm2_addr <= STRM2_OFFSET; - else if(strm2_incr_en) - strm2_addr <= strm2_addr + 1; - if(strm3_rst | rst) - strm3_addr <= STRM3_OFFSET; - else if(strm3_incr_en) - strm3_addr <= strm3_addr + 1; - if(strm4_rst | rst) - strm4_addr <= STRM4_OFFSET; - else if(strm4_incr_en) - strm4_addr <= strm4_addr + 1; - if(strm5_rst | rst) - strm5_addr <= STRM5_OFFSET; - else if(strm5_incr_en) - strm5_addr <= strm5_addr + 1; -end - -reg [$clog2(MEM_DEPTH)-1:0] addra; -wire [MEM_WIDTH*NMEMBLOCKS-1:0] rdqa; - -reg [$clog2(MEM_DEPTH)-1:0] addrb; -wire [MEM_WIDTH*NMEMBLOCKS-1:0] rdqb; - -wire [NMEMBLOCKS-1:0] we; - -reg [1:0] addr_select_porta; -reg [1:0] addr_select_portb; - -//multiplex addresses of various streams into address ports of memory -always @(posedge aclk) begin - addr_select_porta <= current_stream_porta; - case(addr_select_porta) - 0: addra <= strm0_addr; - 1: addra <= strm2_addr; - 2: addra <= strm4_addr; - endcase - addr_select_portb <= current_stream_portb; - case(addr_select_portb) - 0: addrb <= strm1_addr; - 1: addrb <= strm3_addr; - 2: addrb <= strm5_addr; - endcase -end - -genvar g; -generate for(g=0; g 1) begin: multiblock - -wire [MEM_WIDTH-1:0] rdqmux[5:0]; - -reg [$clog2(MEM_DEPTH)-BLOCKADRWIDTH-1:0] rdblocka[2:0]; -reg [$clog2(MEM_DEPTH)-BLOCKADRWIDTH-1:0] rdblockb[2:0]; - -always @(posedge aclk) begin - rdblocka[0] <= addra[$clog2(MEM_DEPTH)-1:BLOCKADRWIDTH]; - rdblockb[0] <= addrb[$clog2(MEM_DEPTH)-1:BLOCKADRWIDTH]; - for(i=0; i<2; i=i+1) begin - rdblocka[i+1] <= rdblocka[i]; - rdblockb[i+1] <= rdblockb[i]; - end -end - -if(NSTREAMS >= 1) begin: en_strm0 - if(STRM0_MUX == 1) begin: mux0 - mux #(STRM0_NBLOCKS, MEM_WIDTH) m(rdqa[(STRM0_BLOCK+STRM0_NBLOCKS)*MEM_WIDTH-1:STRM0_BLOCK*MEM_WIDTH],rdqmux[0],rdblocka[1] - STRM0_BLOCK); - end else begin: nomux0 - assign rdqmux[0] = rdqa[(STRM0_BLOCK+1)*MEM_WIDTH-1:STRM0_BLOCK*MEM_WIDTH]; - end - assign m_axis_0_tdata = rdqmux[0][STRM0_WIDTH-1:0]; -end - -if(NSTREAMS >= 2) begin: en_strm1 - if(STRM1_MUX == 1) begin: mux1 - mux #(STRM1_NBLOCKS, MEM_WIDTH) m(rdqb[(STRM1_BLOCK+STRM1_NBLOCKS)*MEM_WIDTH-1:STRM1_BLOCK*MEM_WIDTH],rdqmux[1],rdblockb[1] - STRM1_BLOCK); - end else begin: nomux1 - assign rdqmux[1] = rdqb[(STRM1_BLOCK+1)*MEM_WIDTH-1:STRM1_BLOCK*MEM_WIDTH]; - end - assign m_axis_1_tdata = rdqmux[1][STRM1_WIDTH-1:0]; -end - -if(NSTREAMS >= 3) begin: en_strm2 - if(STRM2_MUX == 1) begin: mux2 - mux #(STRM2_NBLOCKS, MEM_WIDTH) m(rdqa[(STRM2_BLOCK+STRM2_NBLOCKS)*MEM_WIDTH-1:STRM2_BLOCK*MEM_WIDTH],rdqmux[2],rdblocka[1] - STRM2_BLOCK); - end else begin: nomux2 - assign rdqmux[2] = rdqa[(STRM2_BLOCK+1)*MEM_WIDTH-1:STRM2_BLOCK*MEM_WIDTH]; - end - assign m_axis_2_tdata = rdqmux[2][STRM2_WIDTH-1:0]; -end - -if(NSTREAMS >= 4) begin: en_strm3 - if(STRM3_MUX == 1) begin: mux3 - mux #(STRM3_NBLOCKS, MEM_WIDTH) m(rdqb[(STRM3_BLOCK+STRM3_NBLOCKS)*MEM_WIDTH-1:STRM3_BLOCK*MEM_WIDTH],rdqmux[3],rdblockb[1] - STRM3_BLOCK); - end else begin: nomux3 - assign rdqmux[3] = rdqb[(STRM3_BLOCK+1)*MEM_WIDTH-1:STRM3_BLOCK*MEM_WIDTH]; - end - assign m_axis_3_tdata = rdqmux[3][STRM3_WIDTH-1:0]; -end - -if(NSTREAMS >= 5) begin: en_strm4 - if(STRM4_MUX == 1) begin: mux4 - mux #(STRM4_NBLOCKS, MEM_WIDTH) m(rdqa[(STRM4_BLOCK+STRM4_NBLOCKS)*MEM_WIDTH-1:STRM4_BLOCK*MEM_WIDTH],rdqmux[4],rdblocka[1] - STRM4_BLOCK); - end else begin: nomux4 - assign rdqmux[4] = rdqa[(STRM4_BLOCK+1)*MEM_WIDTH-1:STRM4_BLOCK*MEM_WIDTH]; - end - assign m_axis_4_tdata = rdqmux[4][STRM4_WIDTH-1:0]; -end - -if(NSTREAMS >= 6) begin: en_strm5 - if(STRM5_MUX == 1) begin: mux5 - mux #(STRM5_NBLOCKS, MEM_WIDTH) m(rdqb[(STRM5_BLOCK+STRM5_NBLOCKS)*MEM_WIDTH-1:STRM5_BLOCK*MEM_WIDTH],rdqmux[5],rdblockb[1] - STRM5_BLOCK); - end else begin: nomux5 - assign rdqmux[5] = rdqb[(STRM5_BLOCK+1)*MEM_WIDTH-1:STRM5_BLOCK*MEM_WIDTH]; - end - assign m_axis_5_tdata = rdqmux[5][STRM5_WIDTH-1:0]; -end - -end else begin: singleblock - -if(NSTREAMS >= 1) begin: en_strm0_direct - assign m_axis_0_tdata = rdqa[STRM0_WIDTH-1:0]; -end -if(NSTREAMS >= 2) begin: en_strm1_direct - assign m_axis_1_tdata = rdqb[STRM1_WIDTH-1:0]; -end -if(NSTREAMS >= 3) begin: en_strm2_direct - assign m_axis_2_tdata = rdqa[STRM2_WIDTH-1:0]; -end -if(NSTREAMS >= 4) begin: en_strm3_direct - assign m_axis_3_tdata = rdqb[STRM3_WIDTH-1:0]; -end -if(NSTREAMS >= 5) begin: en_strm4_direct - assign m_axis_4_tdata = rdqa[STRM4_WIDTH-1:0]; -end -if(NSTREAMS >= 6) begin: en_strm5_direct - assign m_axis_5_tdata = rdqb[STRM5_WIDTH-1:0]; -end - -end -endgenerate - -//output to AXI Streams -reg tvalid_pipe0[2:0]; -reg tvalid_pipe1[2:0]; -reg tvalid_pipe2[2:0]; -reg tvalid_pipe3[2:0]; -reg tvalid_pipe4[2:0]; -reg tvalid_pipe5[2:0]; - -assign m_axis_0_tvalid = tvalid_pipe0[2]; -assign m_axis_1_tvalid = tvalid_pipe1[2]; -assign m_axis_2_tvalid = tvalid_pipe2[2]; -assign m_axis_3_tvalid = tvalid_pipe3[2]; -assign m_axis_4_tvalid = tvalid_pipe4[2]; -assign m_axis_5_tvalid = tvalid_pipe5[2]; - - -always @(posedge aclk) begin - tvalid_pipe0[0] <= strm0_incr_en; - tvalid_pipe1[0] <= strm1_incr_en; - tvalid_pipe2[0] <= strm2_incr_en; - tvalid_pipe3[0] <= strm3_incr_en; - tvalid_pipe4[0] <= strm4_incr_en; - tvalid_pipe5[0] <= strm5_incr_en; - for(i=0; i<2; i=i+1) begin: srl - tvalid_pipe0[i+1] <= tvalid_pipe0[i]; - tvalid_pipe1[i+1] <= tvalid_pipe1[i]; - tvalid_pipe2[i+1] <= tvalid_pipe2[i]; - tvalid_pipe3[i+1] <= tvalid_pipe3[i]; - tvalid_pipe4[i+1] <= tvalid_pipe4[i]; - tvalid_pipe5[i+1] <= tvalid_pipe5[i]; - end -end - -//dummy read, for now -assign config_q0 = 0; -assign config_rack = config_ce & ~config_we; - -endmodule diff --git a/finn-rtllib/memstream/hdl/memstream_singleblock.v b/finn-rtllib/memstream/hdl/memstream_singleblock.v deleted file mode 100644 index c9b8770aaa..0000000000 --- a/finn-rtllib/memstream/hdl/memstream_singleblock.v +++ /dev/null @@ -1,246 +0,0 @@ -/* - Copyright (c) 2020, Xilinx - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - * Neither the name of FINN nor the names of its - contributors may be used to endorse or promote products derived from - this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -/* - Implements a lightweight streamer for up to 2 streams in a single block of memory -*/ - -module memstream_singleblock -#( - parameter CONFIG_EN = 1, - parameter NSTREAMS = 2,//1 up to 2 - - parameter MEM_DEPTH = 512, - parameter MEM_WIDTH = 32, - parameter MEM_INIT = "./", - parameter RAM_STYLE = "auto", - - //widths per stream - parameter STRM0_WIDTH = 32, - parameter STRM1_WIDTH = 32, - - //depths per stream - parameter STRM0_DEPTH = 256, - parameter STRM1_DEPTH = 256, - - //offsets for each stream - parameter STRM0_OFFSET = 0, - parameter STRM1_OFFSET = 256 -) - -( - input aclk, - input aresetn, - - //optional configuration interface compatible with ap_memory - input [31:0] config_address, - input config_ce, - input config_we, - input [MEM_WIDTH-1:0] config_d0, - output [MEM_WIDTH-1:0] config_q0, - output config_rack, - - //multiple output AXI Streams, TDATA width rounded to multiple of 8 bits - input m_axis_0_tready, - output m_axis_0_tvalid, - output [((STRM0_WIDTH+7)/8)*8-1:0] m_axis_0_tdata, - - input m_axis_1_tready, - output m_axis_1_tvalid, - output [((STRM1_WIDTH+7)/8)*8-1:0] m_axis_1_tdata - -); - - -//TODO: check that memory width is equal to the widest stream -//TODO: check that the stream depths and offsets make sense, and that the memory depth is sufficient (or calculate depth here?) -initial begin - if((NSTREAMS < 1) | (NSTREAMS > 2)) begin - $display("Invalid setting for NSTREAMS, please set in range [1,2]"); - $finish(); - end -end - -//invert reset -wire rst; -assign rst = ~aresetn; - -wire strm0_incr_en; -wire strm1_incr_en; - -assign strm0_incr_en = m_axis_0_tready | ~m_axis_0_tvalid; -assign strm1_incr_en = m_axis_1_tready | ~m_axis_1_tvalid; - -reg rack_shift[1:0]; - -generate -if(MEM_DEPTH > 1) begin: use_ram - -//calculate width of memory address, with a minimum of 1 bit -localparam BLOCKADRWIDTH = $clog2(MEM_DEPTH); - -reg [BLOCKADRWIDTH-1:0] strm0_addr = STRM0_OFFSET; -wire strm0_rst; -assign strm0_rst = strm0_incr_en & (strm0_addr == (STRM0_OFFSET + STRM0_DEPTH-1)); - -//one address counter per stream; more LUTs but keeps routing short and local -always @(posedge aclk) begin - if(strm0_rst | rst) - strm0_addr <= STRM0_OFFSET; - else if(strm0_incr_en) - strm0_addr <= strm0_addr + 1; -end - -if(NSTREAMS == 1) begin: sdp - -ramb18_sdp -#( - .ID(0), - .DWIDTH(MEM_WIDTH), - .AWIDTH(BLOCKADRWIDTH), - .DEPTH(MEM_DEPTH), - .MEM_INIT(MEM_INIT), - .RAM_STYLE(RAM_STYLE) -) -ram -( - .clk(aclk), - - .ena(config_ce), - .wea(config_we), - .addra(config_address[BLOCKADRWIDTH-1:0]), - .wdataa(config_d0), - - .enb(strm0_incr_en | config_ce), - .enqb(strm0_incr_en | rack_shift[0]), - .addrb(config_ce ? config_address[BLOCKADRWIDTH-1:0] : strm0_addr), - .rdqb(m_axis_0_tdata) -); - - -end else begin: tdp - -reg [BLOCKADRWIDTH-1:0] strm1_addr = STRM1_OFFSET; -wire strm1_rst; -assign strm1_rst = strm1_incr_en & (strm1_addr == (STRM1_OFFSET + STRM1_DEPTH-1)); - -always @(posedge aclk) begin - if(strm1_rst | rst) - strm1_addr <= STRM1_OFFSET; - else if(strm1_incr_en) - strm1_addr <= strm1_addr + 1; -end - -ramb18_wf_dualport -#( - .ID(0), - .DWIDTH(MEM_WIDTH), - .AWIDTH(BLOCKADRWIDTH), - .DEPTH(MEM_DEPTH), - .MEM_INIT(MEM_INIT), - .RAM_STYLE(RAM_STYLE) -) -ram -( - .clk(aclk), - - .wea(config_we), - .ena(strm0_incr_en | config_ce), - .enqa(strm0_incr_en | config_ce_r), - .addra(config_we ? config_address[BLOCKADRWIDTH-1:0] : strm0_addr), - .wdataa(config_d0), - .rdqa(m_axis_0_tdata), - - .web(1'b0), - .enb(strm1_incr_en), - .enqb(strm1_incr_en), - .addrb(strm1_addr), - .wdatab('d0), - .rdqb(m_axis_1_tdata) -); - -end - -end else begin: bypass - -reg [MEM_WIDTH-1:0] singleval[0:0]; -initial begin - `ifdef SYNTHESIS - $readmemh({MEM_INIT,"memblock_synth_0.dat"}, singleval, 0, 0); - `else - $readmemh({MEM_INIT,"memblock_sim_0.dat"}, singleval, 0, 0); - `endif -end - -always @(posedge aclk) - if(config_ce & config_we) - singleval[0] <= config_d0; - -assign m_axis_0_tdata = singleval[0]; -assign m_axis_1_tdata = singleval[0]; - -end -endgenerate - -//signal valid after 2 tready cycles after initialization -//then stay valid -reg [1:0] tvalid_pipe0 = 2'd0; -reg [1:0] tvalid_pipe1 = 2'd0; - -assign m_axis_0_tvalid = tvalid_pipe0[1]; -assign m_axis_1_tvalid = tvalid_pipe1[1]; - -always @(posedge aclk) begin - if(rst) begin - tvalid_pipe0 <= 0; - end else if(strm0_incr_en) begin - tvalid_pipe0[0] <= 1; - tvalid_pipe0[1] <= tvalid_pipe0[0]; - end -end - -always @(posedge aclk) begin - if(rst) begin - tvalid_pipe1 <= 0; - end else if(strm1_incr_en) begin - tvalid_pipe1[0] <= 1; - tvalid_pipe1[1] <= tvalid_pipe1[0]; - end -end - -always @(posedge aclk) begin - rack_shift[0] <= config_ce & ~config_we; - rack_shift[1] <= rack_shift[0]; -end - -assign config_rack = rack_shift[1]; -assign config_q0 = m_axis_0_tdata; - -endmodule diff --git a/finn-rtllib/memstream/hdl/mux.v b/finn-rtllib/memstream/hdl/mux.v deleted file mode 100644 index f7087f9735..0000000000 --- a/finn-rtllib/memstream/hdl/mux.v +++ /dev/null @@ -1,44 +0,0 @@ -/* - Copyright (c) 2020, Xilinx - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - * Neither the name of FINN nor the names of its - contributors may be used to endorse or promote products derived from - this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -module mux -#( - parameter NINPUTS = 1, - parameter WIDTH = 16 -) -( - input [NINPUTS*WIDTH-1:0] in, - output [WIDTH-1:0] out, - input [$clog2(NINPUTS)-1:0] sel -); - -assign out = in >> (sel*WIDTH); - -endmodule diff --git a/finn-rtllib/memstream/hdl/ramb18_sdp.v b/finn-rtllib/memstream/hdl/ramb18_sdp.v deleted file mode 100644 index 8d2fbf9a98..0000000000 --- a/finn-rtllib/memstream/hdl/ramb18_sdp.v +++ /dev/null @@ -1,96 +0,0 @@ -/* - Copyright (c) 2020, Xilinx - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - * Neither the name of FINN nor the names of its - contributors may be used to endorse or promote products derived from - this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -module ramb18_sdp -#( - parameter ID = 0, - parameter DWIDTH = 18, - parameter AWIDTH = 10, - parameter DEPTH = 2**AWIDTH, - parameter MEM_INIT = "", - parameter RAM_STYLE = "auto" -) -( - input clk, - - input ena, - input wea, - input [AWIDTH-1:0] addra, - input [DWIDTH-1:0] wdataa, - - input enb, - input enqb, - input [AWIDTH-1:0] addrb, - output reg [DWIDTH-1:0] rdqb -); - -(* ram_style = RAM_STYLE *) reg [DWIDTH-1:0] mem[0:DEPTH-1]; -reg [DWIDTH-1:0] rdatab; - -`ifdef SYNTHESIS -reg [7:0] idx = ID; -`else -reg [15:0] idx; -`endif - -//initialize memory -initial begin - //note the hacky way of adding a filename memblock_ID.dat to the path provided in MEM_INIT - //ID can go up to 99 - if (ID < 0 && ID > 99) begin - $display("ID out of range [0-99]"); - $finish(); - end - //MEM_INIT path must be terminated by / - `ifdef SYNTHESIS - if (ID < 10) - $readmemh({MEM_INIT,"memblock_synth_",idx+8'd48,".dat"}, mem, 0, DEPTH-1); - else - $readmemh({MEM_INIT,"memblock_synth_",(idx/10)+8'd48,(idx%10)+8'd48,".dat"}, mem, 0, DEPTH-1); - `else - $sformat(idx,"%0d",ID); - if (ID < 10) - $readmemh({MEM_INIT,"memblock_sim_",idx[7:0],".dat"}, mem, 0, DEPTH-1); - else - $readmemh({MEM_INIT,"memblock_sim_",idx,".dat"}, mem, 0, DEPTH-1); - `endif -end - -//memory ports, with output pipeline register -always @(posedge clk) begin - if(wea) - mem[addra] <= wdataa; - if(enb) - rdatab <= mem[addrb]; - if(enqb) - rdqb <= rdatab; -end - -endmodule diff --git a/finn-rtllib/memstream/hdl/ramb18_wf_dualport.v b/finn-rtllib/memstream/hdl/ramb18_wf_dualport.v deleted file mode 100644 index c7850106ae..0000000000 --- a/finn-rtllib/memstream/hdl/ramb18_wf_dualport.v +++ /dev/null @@ -1,111 +0,0 @@ -/* - Copyright (c) 2020, Xilinx - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - * Neither the name of FINN nor the names of its - contributors may be used to endorse or promote products derived from - this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -module ramb18_wf_dualport -#( - parameter ID = 0, - parameter DWIDTH = 18, - parameter AWIDTH = 10, - parameter DEPTH = 2**AWIDTH, - parameter MEM_INIT = "", - parameter RAM_STYLE = "auto" -) -( - input clk, - - input wea, - input ena, - input enqa, - input [AWIDTH-1:0] addra, - input [DWIDTH-1:0] wdataa, - output reg [DWIDTH-1:0] rdqa, - - input web, - input enb, - input enqb, - input [AWIDTH-1:0] addrb, - input [DWIDTH-1:0] wdatab, - output reg [DWIDTH-1:0] rdqb -); - -(* ram_style = RAM_STYLE *) reg [DWIDTH-1:0] mem[0:DEPTH-1]; -reg [DWIDTH-1:0] rdataa; -reg [DWIDTH-1:0] rdatab; - -`ifdef SYNTHESIS -reg [7:0] idx = ID; -`else -reg [15:0] idx; -`endif - -//initialize memory -initial begin - //note the hacky way of adding a filename memblock_ID.dat to the path provided in MEM_INIT - //ID can go up to 99 - if (ID < 0 && ID > 99) begin - $display("ID out of range [0-99]"); - $finish(); - end - //MEM_INIT path must be terminated by / - `ifdef SYNTHESIS - if (ID < 10) - $readmemh({MEM_INIT,"memblock_",idx+8'd48,".dat"}, mem, 0, DEPTH-1); - else - $readmemh({MEM_INIT,"memblock_",(idx/10)+8'd48,(idx%10)+8'd48,".dat"}, mem, 0, DEPTH-1); - `else - $sformat(idx,"%0d",ID); - if (ID < 10) - $readmemh({MEM_INIT,"memblock_",idx[7:0],".dat"}, mem, 0, DEPTH-1); - else - $readmemh({MEM_INIT,"memblock_",idx,".dat"}, mem, 0, DEPTH-1); - `endif -end - -//memory ports, with output pipeline register -always @(posedge clk) begin - if(ena) begin - if(wea) - mem[addra] <= wdataa; - rdataa <= mem[addra]; - end - if(enqa) - rdqa <= rdataa; -end -always @(posedge clk) begin - if(enb) begin - if(web) - mem[addrb] <= wdatab; - rdatab <= mem[addrb]; - end - if(enqb) - rdqb <= rdatab; -end - -endmodule diff --git a/finn-rtllib/memstream/sim/gen_memblocks.sh b/finn-rtllib/memstream/sim/gen_memblocks.sh deleted file mode 100644 index b6e6b656ad..0000000000 --- a/finn-rtllib/memstream/sim/gen_memblocks.sh +++ /dev/null @@ -1,39 +0,0 @@ -#!/bin/bash - -# Copyright (c) 2020, Xilinx -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# * Redistributions of source code must retain the above copyright notice, this -# list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# * Neither the name of FINN nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -NLINES=`cat $1 | wc -l` -NBLOCKS=$(( ($NLINES + 1023) / 1024 )) -rm memblock_*.dat - -for (( i=0; i<$NBLOCKS; i++ )) -do - START=$(( 1 + $i * 1024 )) - tail -n +$START $1 | head -n 1024 >> memblock_$i.dat -done diff --git a/finn-rtllib/memstream/sim/golden.dat b/finn-rtllib/memstream/sim/golden.dat deleted file mode 100644 index 1466271bca..0000000000 --- a/finn-rtllib/memstream/sim/golden.dat +++ /dev/null @@ -1,9216 +0,0 @@ -AFB2B66A -BB100CFF -1ED93E9B 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b/finn-rtllib/memstream/sim/memstream_tb.sv new file mode 100644 index 0000000000..4b2e850415 --- /dev/null +++ b/finn-rtllib/memstream/sim/memstream_tb.sv @@ -0,0 +1,212 @@ +/** + * Copyright (c) 2023, Xilinx + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of FINN nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * @author Thomas B. Preußer + */ + +module memstream_tb; + localparam int unsigned DEPTH = 256; + localparam int unsigned DATA_WIDTH = 32; + + // Global Control + logic clk = 0; + always #5ns clk = !clk; + logic rst; + + // Configuration Interface + logic [31:0] config_address; + logic config_ce; + logic config_we; + logic [DATA_WIDTH-1:0] config_d0; + uwire config_rack; + uwire [DATA_WIDTH-1:0] config_q0; + + // Streamed Output + logic ordy; + uwire ovld; + uwire [DATA_WIDTH-1:0] odat; + + initial begin + config_address = 'x; + config_ce = 0; + config_we = 0; + config_d0 = 'x; + + ordy = 0; + + rst = 1; + repeat(16) @(posedge clk); + rst <= 0; + + // Write Parameters + config_ce <= 1; + config_we <= 1; + for(int unsigned i = 0; i < DEPTH; i++) begin + config_address <= i; + config_d0 <= i; + @(posedge clk); + end + config_address <= 'x; + config_ce <= 0; + config_we <= 0; + config_d0 <= 'x; + + rst <= 1; + @(posedge clk); + rst <= 0; + + // One Round of Stream Read + ordy <= 1; + for(int unsigned i = 0; i < DEPTH; i++) begin + @(posedge clk iff ovld); + assert(odat == i) else begin + $error("Unexpected output: %0d instead of %0d", odat, i); + $stop; + end + end + ordy <= 0; + + // Full Parameter Readback + if(1) begin + automatic logic [DATA_WIDTH-1:0] Q[$] = {}; + + config_ce <= 1; + for(int unsigned i = 0; i < DEPTH; i++) begin + config_address <= i; + @(posedge clk); + Q.push_back(i); + + if(config_rack) begin + automatic logic [DATA_WIDTH-1:0] exp = Q.pop_front(); + assert(config_q0 == exp) else begin + $error("Readback mismatch: %0d instead of %0d", config_q0, exp); + $stop; + end + end + end + config_address <= 'x; + config_ce <= 0; + + while(Q.size) begin + automatic logic [DATA_WIDTH-1:0] exp = Q.pop_front(); + + @(posedge clk iff config_rack); + assert(config_q0 == exp) else begin + $error("Readback mismatch: %0d instead of %0d", config_q0, exp); + $stop; + end + end + end + + repeat(6) @(posedge clk); + + // Another Round of Stream Read + ordy <= 1; + for(int unsigned i = 0; i < DEPTH; i++) begin + @(posedge clk iff ovld); + assert(odat == i) else begin + $error("Unexpected output: %0d instead of %0d", odat, i); + $stop; + end + end + ordy <= 0; + + // A Round of Stream Read with intermittent Read Backs + if(1) begin + automatic logic [DATA_WIDTH-1:0] Q[$] = {}; + + for(int unsigned i = 0; i < DEPTH; i++) begin + do begin + // Randomly delayed Readiness + if($urandom()%5 != 0) ordy <= 1; + + // Issue and Check Random Read Backs + if($urandom()%9 == 0) begin + automatic int unsigned addr = $urandom() % DEPTH; + config_ce <= 1; + config_address <= addr; + Q.push_back(addr); + end + @(posedge clk); + config_ce <= 0; + config_address <= 'x; + + if(config_rack) begin + automatic logic [DATA_WIDTH-1:0] exp = Q.pop_front(); + assert(config_q0 == exp) else begin + $error("Readback mismatch: %0d instead of %0d", config_q0, exp); + $stop; + end + end + + end while(!ovld || !ordy); + ordy <= 0; + + assert(odat == i) else begin + $error("Unexpected output: %0d instead of %0d", odat, i); + $stop; + end + end + + while(Q.size) begin + automatic logic [DATA_WIDTH-1:0] exp = Q.pop_front(); + + @(posedge clk iff config_rack); + assert(config_q0 == exp) else begin + $error("Readback mismatch: %0d instead of %0d", config_q0, exp); + $stop; + end + end + end + ordy <= 0; + + repeat(2) @(posedge clk); + $display("Test completed."); + $finish; + end + + memstream #( + .DEPTH(DEPTH), + .WIDTH(DATA_WIDTH) + ) dut ( + .clk, .rst, + + .config_address, + .config_ce, + .config_we, + .config_d0, + .config_q0, + .config_rack, + + .ordy, + .ovld, + .odat + ); + +endmodule : memstream_tb diff --git a/finn-rtllib/memstream/sim/tb_memstream.v b/finn-rtllib/memstream/sim/tb_memstream.v deleted file mode 100644 index ad3efad5bd..0000000000 --- a/finn-rtllib/memstream/sim/tb_memstream.v +++ /dev/null @@ -1,369 +0,0 @@ -/* - Copyright (c) 2020, Xilinx - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - * Neither the name of FINN nor the names of its - contributors may be used to endorse or promote products derived from - this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -`timescale 1ns/10ps - -module tb_memstream; - -//parameters to enable/disable axi-mm, set number of streams, set readmemh for memory, set per-stream offsets in memory, set per-stream widths -parameter CONFIG_EN = 1; -parameter NSTREAMS = 4;//1 up to 6 - -parameter MEM_DEPTH = 9216; -parameter MEM_WIDTH = 32; -parameter MEM_INIT = "./"; -parameter MEM_CHECK = "golden.dat"; - -//widths per stream -parameter STRM0_WIDTH = 32; -parameter STRM1_WIDTH = 32; -parameter STRM2_WIDTH = 32; -parameter STRM3_WIDTH = 32; -parameter STRM4_WIDTH = 1; -parameter STRM5_WIDTH = 1; - -//depths per stream -parameter STRM0_DEPTH = 2304; -parameter STRM1_DEPTH = 2304; -parameter STRM2_DEPTH = 2304; -parameter STRM3_DEPTH = 2304; -parameter STRM4_DEPTH = 1; -parameter STRM5_DEPTH = 1; - -//offsets for each stream -parameter STRM0_OFFSET = 0; -parameter STRM1_OFFSET = 2304; -parameter STRM2_OFFSET = 4608; -parameter STRM3_OFFSET = 6912; -parameter STRM4_OFFSET = 0; -parameter STRM5_OFFSET = 0; - - -reg clk; -reg rst; - -reg [31:0] config_address = 0; -reg config_ce = 0; -reg config_we = 0; -reg [31:0] config_d0 = 0; -wire [31:0] config_q0; - -//multiple wire AXI Streams -reg m_axis_0_afull; -reg m_axis_0_tready; -wire m_axis_0_tvalid; -wire [STRM0_WIDTH-1:0] m_axis_0_tdata; - -reg m_axis_1_afull; -reg m_axis_1_tready; -wire m_axis_1_tvalid; -wire [STRM1_WIDTH-1:0] m_axis_1_tdata; - -reg m_axis_2_afull; -reg m_axis_2_tready; -wire m_axis_2_tvalid; -wire [STRM2_WIDTH-1:0] m_axis_2_tdata; - -reg m_axis_3_afull; -reg m_axis_3_tready; -wire m_axis_3_tvalid; -wire [STRM3_WIDTH-1:0] m_axis_3_tdata; - -reg m_axis_4_afull; -reg m_axis_4_tready; -wire m_axis_4_tvalid; -wire [STRM4_WIDTH-1:0] m_axis_4_tdata; - -reg m_axis_5_afull; -reg m_axis_5_tready; -wire m_axis_5_tvalid; -wire [STRM5_WIDTH-1:0] m_axis_5_tdata; - -reg [MEM_WIDTH-1:0] golden[MEM_DEPTH-1:0]; -integer ptr0, ptr1, ptr2, ptr3, ptr4, ptr5; -integer done = 0; -reg [5:0] rng; - -//clock -initial begin - clk = 0; - forever #5 clk = ~clk; -end - -initial begin - rst = 1; - config_ce = 0; - m_axis_0_afull = 0; - m_axis_1_afull = 0; - m_axis_2_afull = 0; - m_axis_3_afull = 0; - m_axis_4_afull = 0; - m_axis_5_afull = 0; - m_axis_0_tready = 1; - m_axis_1_tready = 1; - m_axis_2_tready = 1; - m_axis_3_tready = 1; - m_axis_4_tready = 1; - m_axis_5_tready = 1; - repeat(100) @(negedge clk); - rst = 0; - #100 - fork - begin - $display("Starting to generate random AFULL"); - while(~done) begin - rng = $random; - m_axis_0_afull = rng[0]; - m_axis_1_afull = rng[1]; - m_axis_2_afull = rng[2]; - m_axis_3_afull = rng[3]; - m_axis_4_afull = rng[4]; - m_axis_5_afull = rng[5]; - @(negedge clk); - end - end - join -end - - -//DUT -memstream -#( - CONFIG_EN, - NSTREAMS, - MEM_DEPTH, - MEM_WIDTH, - MEM_INIT, - - //widths per stream - STRM0_WIDTH, - STRM1_WIDTH, - STRM2_WIDTH, - STRM3_WIDTH, - STRM4_WIDTH, - STRM5_WIDTH, - - //depths per stream - STRM0_DEPTH, - STRM1_DEPTH, - STRM2_DEPTH, - STRM3_DEPTH, - STRM4_DEPTH, - STRM5_DEPTH, - - //offsets for each stream - STRM0_OFFSET, - STRM1_OFFSET, - STRM2_OFFSET, - STRM3_OFFSET, - STRM4_OFFSET, - STRM5_OFFSET -) -dut -( - clk, - ~rst, - - //optional AXI-Lite interface - config_address, - config_ce, - config_we, - config_d0, - config_q0, - - //multiple output AXI Streams - m_axis_0_afull, - m_axis_0_tready, - m_axis_0_tvalid, - m_axis_0_tdata, - - m_axis_1_afull, - m_axis_1_tready, - m_axis_1_tvalid, - m_axis_1_tdata, - - m_axis_2_afull, - m_axis_2_tready, - m_axis_2_tvalid, - m_axis_2_tdata, - - m_axis_3_afull, - m_axis_3_tready, - m_axis_3_tvalid, - m_axis_3_tdata, - - m_axis_4_afull, - m_axis_4_tready, - m_axis_4_tvalid, - m_axis_4_tdata, - - m_axis_5_afull, - m_axis_5_tready, - m_axis_5_tvalid, - m_axis_5_tdata - - -); - -//stream checkers -initial begin - ptr0 = STRM0_OFFSET; - ptr1 = STRM1_OFFSET; - ptr2 = STRM2_OFFSET; - ptr3 = STRM3_OFFSET; - ptr4 = STRM4_OFFSET; - ptr5 = STRM5_OFFSET; - fork - //check stream 0 - begin - $display("Starting stream 0 checker"); - while(~done & (NSTREAMS > 0)) begin - @(negedge clk); - if(m_axis_0_tvalid) begin - if(m_axis_0_tdata != golden[ptr0]) begin - $display("Mismatch on stream 0"); - $stop(); - end - //increment pointer - ptr0 = ptr0 + 1; - //rewind pointer if it's reached end - if(ptr0 == (STRM0_OFFSET + STRM0_DEPTH)) - ptr0 = STRM0_OFFSET; - end - end - end - //check stream 1 - begin - $display("Starting stream 1 checker"); - while(~done & (NSTREAMS > 1)) begin - @(negedge clk); - if(m_axis_1_tvalid) begin - if(m_axis_1_tdata != golden[ptr1]) begin - $display("Mismatch on stream 1"); - $stop(); - end - //increment pointer - ptr1 = ptr1 + 1; - //rewind pointer if it's reached end - if(ptr1 == (STRM1_OFFSET + STRM1_DEPTH)) - ptr1 = STRM1_OFFSET; - end - end - end - - //check stream 2 - begin - $display("Starting stream 2 checker"); - while(~done & (NSTREAMS > 2)) begin - @(negedge clk); - if(m_axis_2_tvalid) begin - if(m_axis_2_tdata != golden[ptr2]) begin - $display("Mismatch on stream 2"); - $stop(); - end - //increment pointer - ptr2 = ptr2 + 1; - //rewind pointer if it's reached end - if(ptr2 == (STRM2_OFFSET + STRM2_DEPTH)) - ptr2 = STRM2_OFFSET; - end - end - end - //check stream 3 - begin - $display("Starting stream 3 checker"); - while(~done & (NSTREAMS > 3)) begin - @(negedge clk); - if(m_axis_3_tvalid) begin - if(m_axis_3_tdata != golden[ptr3]) begin - $display("Mismatch on stream 3"); - $stop(); - end - //increment pointer - ptr3 = ptr3 + 1; - //rewind pointer if it's reached end - if(ptr3 == (STRM3_OFFSET + STRM3_DEPTH)) - ptr3 = STRM3_OFFSET; - end - end - end - //check stream 4 - begin - $display("Starting stream 4 checker"); - while(~done & (NSTREAMS > 4)) begin - @(negedge clk); - if(m_axis_4_tvalid) begin - if(m_axis_4_tdata != golden[ptr4]) begin - $display("Mismatch on stream 4"); - $stop(); - end - //increment pointer - ptr4 = ptr4 + 1; - //rewind pointer if it's reached end - if(ptr4 == (STRM4_OFFSET + STRM4_DEPTH)) - ptr4 = STRM4_OFFSET; - end - end - end - //check stream 5 - begin - $display("Starting stream 5 checker"); - while(~done & (NSTREAMS > 5)) begin - @(negedge clk); - if(m_axis_5_tvalid) begin - if(m_axis_5_tdata != golden[ptr5]) begin - $display("Mismatch on stream 5"); - $stop(); - end - //increment pointer - ptr5 = ptr5 + 1; - //rewind pointer if it's reached end - if(ptr5 == (STRM5_OFFSET + STRM5_DEPTH)) - ptr5 = STRM5_OFFSET; - end - end - end - join -end - -initial begin - done = 0; - $readmemh(MEM_CHECK,golden); -// $dumpfile("wave.vcd"); -// $dumpvars(0,tb_memstream); - @(negedge rst); - #10000000 - $display("Test done!"); - done = 1; - #1000 - $finish(); -end - -endmodule diff --git a/finn-rtllib/memstream/sim/tb_memstream_writes.v b/finn-rtllib/memstream/sim/tb_memstream_writes.v deleted file mode 100644 index c66807454b..0000000000 --- a/finn-rtllib/memstream/sim/tb_memstream_writes.v +++ /dev/null @@ -1,486 +0,0 @@ -/* - Copyright (c) 2020, Xilinx - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - * Neither the name of FINN nor the names of its - contributors may be used to endorse or promote products derived from - this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -`timescale 1ns/10ps - -module tb_memstream_writes; - -//parameters to enable/disable axi-mm, set number of streams, set readmemh for memory, set per-stream offsets in memory, set per-stream widths -parameter CONFIG_EN = 1; -parameter NSTREAMS = 2;//1 up to 6 - -parameter MEM_DEPTH = 40; -parameter MEM_WIDTH = 70; - -//widths per stream -parameter STRM0_WIDTH = 70; -parameter STRM1_WIDTH = 32; -parameter STRM2_WIDTH = 32; -parameter STRM3_WIDTH = 32; -parameter STRM4_WIDTH = 1; -parameter STRM5_WIDTH = 1; - -//depths per stream -parameter STRM0_DEPTH = 20; -parameter STRM1_DEPTH = 20; -parameter STRM2_DEPTH = 2304; -parameter STRM3_DEPTH = 2304; -parameter STRM4_DEPTH = 1; -parameter STRM5_DEPTH = 1; - -//offsets for each stream -parameter STRM0_OFFSET = 0; -parameter STRM1_OFFSET = 20; -parameter STRM2_OFFSET = 4608; -parameter STRM3_OFFSET = 6912; -parameter STRM4_OFFSET = 0; -parameter STRM5_OFFSET = 0; - - -reg clk; -reg rst; - -wire awready; -reg awvalid; -reg [31:0] awaddr; -reg [2:0] awprot; -//write data -wire wready; -reg wvalid; -reg [31:0] wdata; -reg [3:0] wstrb; -//burst response -reg bready; -wire bvalid; -wire [1:0] bresp; - -//Read channels -//read address -wire arready; -reg arvalid; -reg [31:0] araddr; -reg [2:0] arprot; -//read data -reg rready; -wire rvalid; -wire [1:0] rresp; -wire [31:0] rdata; - -//multiple wire AXI Streams -reg m_axis_0_afull; -reg m_axis_0_tready; -wire m_axis_0_tvalid; -wire [STRM0_WIDTH-1:0] m_axis_0_tdata; - -reg m_axis_1_afull; -reg m_axis_1_tready; -wire m_axis_1_tvalid; -wire [STRM1_WIDTH-1:0] m_axis_1_tdata; - -reg m_axis_2_afull; -reg m_axis_2_tready; -wire m_axis_2_tvalid; -wire [STRM2_WIDTH-1:0] m_axis_2_tdata; - -reg m_axis_3_afull; -reg m_axis_3_tready; -wire m_axis_3_tvalid; -wire [STRM3_WIDTH-1:0] m_axis_3_tdata; - -reg m_axis_4_afull; -reg m_axis_4_tready; -wire m_axis_4_tvalid; -wire [STRM4_WIDTH-1:0] m_axis_4_tdata; - -reg m_axis_5_afull; -reg m_axis_5_tready; -wire m_axis_5_tvalid; -wire [STRM5_WIDTH-1:0] m_axis_5_tdata; - -reg [MEM_WIDTH-1:0] golden[MEM_DEPTH-1:0]; -reg [MEM_WIDTH-1:0] gword; -integer ptr0, ptr1, ptr2, ptr3, ptr4, ptr5; -integer done = 0; -integer i, j; -reg [5:0] rng; - -parameter NFOLDS_PER_WORD = (MEM_WIDTH+31)/32; - -task axi_write; - input [MEM_WIDTH-1:0] data; - input [31:0] adr; - begin - for(j=0; j<(1<<$clog2(NFOLDS_PER_WORD)); j=j+1) begin - @(negedge clk); - awvalid = 1; - wvalid = 1; - wdata = data>>(j*32); - awaddr = (adr*(1<<$clog2(NFOLDS_PER_WORD))+j)*4; - fork - begin - @(posedge awready); - @(posedge clk) awvalid = 0; - end - begin - @(posedge wready); - @(posedge clk) wvalid = 0; - end - join - @(posedge clk); - end - end -endtask - -task axi_read; - input [31:0] adr; - output [MEM_WIDTH-1:0] data; - begin - data = 0; - for(j=0; j 0)) begin - @(negedge clk); - if(m_axis_0_tvalid & m_axis_0_tready) begin - if(m_axis_0_tdata != golden[ptr0]) begin - $display("Mismatch on stream 0"); - $stop(); - end - //increment pointer - ptr0 = ptr0 + 1; - //rewind pointer if it's reached end - if(ptr0 == (STRM0_OFFSET + STRM0_DEPTH)) - ptr0 = STRM0_OFFSET; - end - end - end - //check stream 1 - begin - $display("Starting stream 1 checker"); - while(~done & (NSTREAMS > 1)) begin - @(negedge clk); - if(m_axis_1_tvalid & m_axis_1_tready) begin - if(m_axis_1_tdata != golden[ptr1]) begin - $display("Mismatch on stream 1"); - $stop(); - end - //increment pointer - ptr1 = ptr1 + 1; - //rewind pointer if it's reached end - if(ptr1 == (STRM1_OFFSET + STRM1_DEPTH)) - ptr1 = STRM1_OFFSET; - end - end - end - //check stream 2 - begin - $display("Starting stream 2 checker"); - while(~done & (NSTREAMS > 2)) begin - @(negedge clk); - if(m_axis_2_tvalid & m_axis_2_tready) begin - if(m_axis_2_tdata != golden[ptr2]) begin - $display("Mismatch on stream 2"); - $stop(); - end - //increment pointer - ptr2 = ptr2 + 1; - //rewind pointer if it's reached end - if(ptr2 == (STRM2_OFFSET + STRM2_DEPTH)) - ptr2 = STRM2_OFFSET; - end - end - end - //check stream 3 - begin - $display("Starting stream 3 checker"); - while(~done & (NSTREAMS > 3)) begin - @(negedge clk); - if(m_axis_3_tvalid & m_axis_3_tready) begin - if(m_axis_3_tdata != golden[ptr3]) begin - $display("Mismatch on stream 3"); - $stop(); - end - //increment pointer - ptr3 = ptr3 + 1; - //rewind pointer if it's reached end - if(ptr3 == (STRM3_OFFSET + STRM3_DEPTH)) - ptr3 = STRM3_OFFSET; - end - end - end - //check stream 4 - begin - $display("Starting stream 4 checker"); - while(~done & (NSTREAMS > 4)) begin - @(negedge clk); - if(m_axis_4_tvalid & m_axis_4_tready) begin - if(m_axis_4_tdata != golden[ptr4]) begin - $display("Mismatch on stream 4"); - $stop(); - end - //increment pointer - ptr4 = ptr4 + 1; - //rewind pointer if it's reached end - if(ptr4 == (STRM4_OFFSET + STRM4_DEPTH)) - ptr4 = STRM4_OFFSET; - end - end - end - //check stream 5 - begin - $display("Starting stream 5 checker"); - while(~done & (NSTREAMS > 5)) begin - @(negedge clk); - if(m_axis_5_tvalid & m_axis_5_tready) begin - if(m_axis_5_tdata != golden[ptr5]) begin - $display("Mismatch on stream 5"); - $stop(); - end - //increment pointer - ptr5 = ptr5 + 1; - //rewind pointer if it's reached end - if(ptr5 == (STRM5_OFFSET + STRM5_DEPTH)) - ptr5 = STRM5_OFFSET; - end - end - end - join -end - -initial begin - done = 0; - @(negedge rst); - $dumpfile("wave.vcd"); - $dumpvars(0,tb_memstream_writes); - #50000 - $display("Test done!"); - done = 1; - #1000 - $finish(); -end - -endmodule diff --git a/finn-rtllib/memstream/sim/test.sh b/finn-rtllib/memstream/sim/test.sh deleted file mode 100755 index 7cb0497d26..0000000000 --- a/finn-rtllib/memstream/sim/test.sh +++ /dev/null @@ -1,32 +0,0 @@ -#!/bin/bash - -# Copyright (c) 2020, Xilinx -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# * Redistributions of source code must retain the above copyright notice, this -# list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# * Neither the name of FINN nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -iverilog ../hdl/*.v tb_memstream_writes.v -o sim -./sim diff --git a/finn-rtllib/memstream/xgui/memstream_v1_0.tcl b/finn-rtllib/memstream/xgui/memstream_v1_0.tcl deleted file mode 100644 index 87565bc561..0000000000 --- a/finn-rtllib/memstream/xgui/memstream_v1_0.tcl +++ /dev/null @@ -1,394 +0,0 @@ - -# Loading additional proc with user specified bodies to compute parameter values. -source [file join [file dirname [file dirname [info script]]] gui/memstream_v1_0.gtcl] - -# Definitional proc to organize widgets for parameters. -proc init_gui { IPINST } { - ipgui::add_param $IPINST -name "Component_Name" - #Adding Page - set Page_0 [ipgui::add_page $IPINST -name "Page 0"] - ipgui::add_param $IPINST -name "AXILITE_ADDR_WIDTH" -parent ${Page_0} - ipgui::add_param $IPINST -name "CONFIG_EN" -parent ${Page_0} - ipgui::add_param $IPINST -name "MEM_DEPTH" -parent ${Page_0} - ipgui::add_param $IPINST -name "MEM_INIT" -parent ${Page_0} - ipgui::add_param $IPINST -name "MEM_WIDTH" -parent ${Page_0} - ipgui::add_param $IPINST -name "NSTREAMS" -parent ${Page_0} - ipgui::add_param $IPINST -name "RAM_STYLE" -parent ${Page_0} -widget comboBox - ipgui::add_param $IPINST -name "STRM0_DEPTH" -parent ${Page_0} - ipgui::add_param $IPINST -name "STRM0_OFFSET" -parent ${Page_0} - ipgui::add_param $IPINST -name "STRM0_WIDTH" -parent ${Page_0} - ipgui::add_param $IPINST -name "STRM1_DEPTH" -parent ${Page_0} - ipgui::add_param $IPINST -name "STRM1_OFFSET" -parent ${Page_0} - ipgui::add_param $IPINST -name "STRM1_WIDTH" -parent ${Page_0} - ipgui::add_param $IPINST -name "STRM2_DEPTH" -parent ${Page_0} - ipgui::add_param $IPINST -name "STRM2_OFFSET" -parent ${Page_0} - ipgui::add_param $IPINST -name "STRM2_WIDTH" -parent ${Page_0} - ipgui::add_param $IPINST -name "STRM3_DEPTH" -parent ${Page_0} - ipgui::add_param $IPINST -name "STRM3_OFFSET" -parent ${Page_0} - ipgui::add_param $IPINST -name "STRM3_WIDTH" -parent ${Page_0} - ipgui::add_param $IPINST -name "STRM4_DEPTH" -parent ${Page_0} - ipgui::add_param $IPINST -name "STRM4_OFFSET" -parent ${Page_0} - ipgui::add_param $IPINST -name "STRM4_WIDTH" -parent ${Page_0} - ipgui::add_param $IPINST -name "STRM5_DEPTH" -parent ${Page_0} - ipgui::add_param $IPINST -name "STRM5_OFFSET" -parent ${Page_0} - ipgui::add_param $IPINST -name "STRM5_WIDTH" -parent ${Page_0} - - -} - -proc update_PARAM_VALUE.AXILITE_ADDR_WIDTH { PARAM_VALUE.AXILITE_ADDR_WIDTH PARAM_VALUE.MEM_DEPTH PARAM_VALUE.MEM_WIDTH } { - # Procedure called to update AXILITE_ADDR_WIDTH when any of the dependent parameters in the arguments change - set AXILITE_ADDR_WIDTH ${PARAM_VALUE.AXILITE_ADDR_WIDTH} - set MEM_DEPTH ${PARAM_VALUE.MEM_DEPTH} - set MEM_WIDTH ${PARAM_VALUE.MEM_WIDTH} - set values(MEM_DEPTH) [get_property value $MEM_DEPTH] - set values(MEM_WIDTH) [get_property value $MEM_WIDTH] - set_property value [gen_USERPARAMETER_AXILITE_ADDR_WIDTH_VALUE $values(MEM_DEPTH) $values(MEM_WIDTH)] $AXILITE_ADDR_WIDTH -} - -proc validate_PARAM_VALUE.AXILITE_ADDR_WIDTH { PARAM_VALUE.AXILITE_ADDR_WIDTH } { - # Procedure called to validate AXILITE_ADDR_WIDTH - return true -} - -proc update_PARAM_VALUE.CONFIG_EN { PARAM_VALUE.CONFIG_EN } { - # Procedure called to update CONFIG_EN when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.CONFIG_EN { PARAM_VALUE.CONFIG_EN } { - # Procedure called to validate CONFIG_EN - return true -} - -proc update_PARAM_VALUE.MEM_DEPTH { PARAM_VALUE.MEM_DEPTH } { - # Procedure called to update MEM_DEPTH when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.MEM_DEPTH { PARAM_VALUE.MEM_DEPTH } { - # Procedure called to validate MEM_DEPTH - return true -} - -proc update_PARAM_VALUE.MEM_INIT { PARAM_VALUE.MEM_INIT } { - # Procedure called to update MEM_INIT when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.MEM_INIT { PARAM_VALUE.MEM_INIT } { - # Procedure called to validate MEM_INIT - return true -} - -proc update_PARAM_VALUE.MEM_WIDTH { PARAM_VALUE.MEM_WIDTH } { - # Procedure called to update MEM_WIDTH when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.MEM_WIDTH { PARAM_VALUE.MEM_WIDTH } { - # Procedure called to validate MEM_WIDTH - return true -} - -proc update_PARAM_VALUE.NSTREAMS { PARAM_VALUE.NSTREAMS } { - # Procedure called to update NSTREAMS when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.NSTREAMS { PARAM_VALUE.NSTREAMS } { - # Procedure called to validate NSTREAMS - return true -} - -proc update_PARAM_VALUE.RAM_STYLE { PARAM_VALUE.RAM_STYLE } { - # Procedure called to update RAM_STYLE when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.RAM_STYLE { PARAM_VALUE.RAM_STYLE } { - # Procedure called to validate RAM_STYLE - return true -} - -proc update_PARAM_VALUE.STRM0_DEPTH { PARAM_VALUE.STRM0_DEPTH } { - # Procedure called to update STRM0_DEPTH when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.STRM0_DEPTH { PARAM_VALUE.STRM0_DEPTH } { - # Procedure called to validate STRM0_DEPTH - return true -} - -proc update_PARAM_VALUE.STRM0_OFFSET { PARAM_VALUE.STRM0_OFFSET } { - # Procedure called to update STRM0_OFFSET when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.STRM0_OFFSET { PARAM_VALUE.STRM0_OFFSET } { - # Procedure called to validate STRM0_OFFSET - return true -} - -proc update_PARAM_VALUE.STRM0_WIDTH { PARAM_VALUE.STRM0_WIDTH } { - # Procedure called to update STRM0_WIDTH when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.STRM0_WIDTH { PARAM_VALUE.STRM0_WIDTH } { - # Procedure called to validate STRM0_WIDTH - return true -} - -proc update_PARAM_VALUE.STRM1_DEPTH { PARAM_VALUE.STRM1_DEPTH } { - # Procedure called to update STRM1_DEPTH when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.STRM1_DEPTH { PARAM_VALUE.STRM1_DEPTH } { - # Procedure called to validate STRM1_DEPTH - return true -} - -proc update_PARAM_VALUE.STRM1_OFFSET { PARAM_VALUE.STRM1_OFFSET } { - # Procedure called to update STRM1_OFFSET when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.STRM1_OFFSET { PARAM_VALUE.STRM1_OFFSET } { - # Procedure called to validate STRM1_OFFSET - return true -} - -proc update_PARAM_VALUE.STRM1_WIDTH { PARAM_VALUE.STRM1_WIDTH } { - # Procedure called to update STRM1_WIDTH when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.STRM1_WIDTH { PARAM_VALUE.STRM1_WIDTH } { - # Procedure called to validate STRM1_WIDTH - return true -} - -proc update_PARAM_VALUE.STRM2_DEPTH { PARAM_VALUE.STRM2_DEPTH } { - # Procedure called to update STRM2_DEPTH when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.STRM2_DEPTH { PARAM_VALUE.STRM2_DEPTH } { - # Procedure called to validate STRM2_DEPTH - return true -} - -proc update_PARAM_VALUE.STRM2_OFFSET { PARAM_VALUE.STRM2_OFFSET } { - # Procedure called to update STRM2_OFFSET when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.STRM2_OFFSET { PARAM_VALUE.STRM2_OFFSET } { - # Procedure called to validate STRM2_OFFSET - return true -} - -proc update_PARAM_VALUE.STRM2_WIDTH { PARAM_VALUE.STRM2_WIDTH } { - # Procedure called to update STRM2_WIDTH when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.STRM2_WIDTH { PARAM_VALUE.STRM2_WIDTH } { - # Procedure called to validate STRM2_WIDTH - return true -} - -proc update_PARAM_VALUE.STRM3_DEPTH { PARAM_VALUE.STRM3_DEPTH } { - # Procedure called to update STRM3_DEPTH when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.STRM3_DEPTH { PARAM_VALUE.STRM3_DEPTH } { - # Procedure called to validate STRM3_DEPTH - return true -} - -proc update_PARAM_VALUE.STRM3_OFFSET { PARAM_VALUE.STRM3_OFFSET } { - # Procedure called to update STRM3_OFFSET when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.STRM3_OFFSET { PARAM_VALUE.STRM3_OFFSET } { - # Procedure called to validate STRM3_OFFSET - return true -} - -proc update_PARAM_VALUE.STRM3_WIDTH { PARAM_VALUE.STRM3_WIDTH } { - # Procedure called to update STRM3_WIDTH when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.STRM3_WIDTH { PARAM_VALUE.STRM3_WIDTH } { - # Procedure called to validate STRM3_WIDTH - return true -} - -proc update_PARAM_VALUE.STRM4_DEPTH { PARAM_VALUE.STRM4_DEPTH } { - # Procedure called to update STRM4_DEPTH when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.STRM4_DEPTH { PARAM_VALUE.STRM4_DEPTH } { - # Procedure called to validate STRM4_DEPTH - return true -} - -proc update_PARAM_VALUE.STRM4_OFFSET { PARAM_VALUE.STRM4_OFFSET } { - # Procedure called to update STRM4_OFFSET when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.STRM4_OFFSET { PARAM_VALUE.STRM4_OFFSET } { - # Procedure called to validate STRM4_OFFSET - return true -} - -proc update_PARAM_VALUE.STRM4_WIDTH { PARAM_VALUE.STRM4_WIDTH } { - # Procedure called to update STRM4_WIDTH when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.STRM4_WIDTH { PARAM_VALUE.STRM4_WIDTH } { - # Procedure called to validate STRM4_WIDTH - return true -} - -proc update_PARAM_VALUE.STRM5_DEPTH { PARAM_VALUE.STRM5_DEPTH } { - # Procedure called to update STRM5_DEPTH when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.STRM5_DEPTH { PARAM_VALUE.STRM5_DEPTH } { - # Procedure called to validate STRM5_DEPTH - return true -} - -proc update_PARAM_VALUE.STRM5_OFFSET { PARAM_VALUE.STRM5_OFFSET } { - # Procedure called to update STRM5_OFFSET when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.STRM5_OFFSET { PARAM_VALUE.STRM5_OFFSET } { - # Procedure called to validate STRM5_OFFSET - return true -} - -proc update_PARAM_VALUE.STRM5_WIDTH { PARAM_VALUE.STRM5_WIDTH } { - # Procedure called to update STRM5_WIDTH when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.STRM5_WIDTH { PARAM_VALUE.STRM5_WIDTH } { - # Procedure called to validate STRM5_WIDTH - return true -} - - -proc update_MODELPARAM_VALUE.CONFIG_EN { MODELPARAM_VALUE.CONFIG_EN PARAM_VALUE.CONFIG_EN } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.CONFIG_EN}] ${MODELPARAM_VALUE.CONFIG_EN} -} - -proc update_MODELPARAM_VALUE.NSTREAMS { MODELPARAM_VALUE.NSTREAMS PARAM_VALUE.NSTREAMS } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.NSTREAMS}] ${MODELPARAM_VALUE.NSTREAMS} -} - -proc update_MODELPARAM_VALUE.MEM_DEPTH { MODELPARAM_VALUE.MEM_DEPTH PARAM_VALUE.MEM_DEPTH } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.MEM_DEPTH}] ${MODELPARAM_VALUE.MEM_DEPTH} -} - -proc update_MODELPARAM_VALUE.MEM_WIDTH { MODELPARAM_VALUE.MEM_WIDTH PARAM_VALUE.MEM_WIDTH } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.MEM_WIDTH}] ${MODELPARAM_VALUE.MEM_WIDTH} -} - -proc update_MODELPARAM_VALUE.MEM_INIT { MODELPARAM_VALUE.MEM_INIT PARAM_VALUE.MEM_INIT } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.MEM_INIT}] ${MODELPARAM_VALUE.MEM_INIT} -} - -proc update_MODELPARAM_VALUE.RAM_STYLE { MODELPARAM_VALUE.RAM_STYLE PARAM_VALUE.RAM_STYLE } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.RAM_STYLE}] ${MODELPARAM_VALUE.RAM_STYLE} -} - -proc update_MODELPARAM_VALUE.STRM0_WIDTH { MODELPARAM_VALUE.STRM0_WIDTH PARAM_VALUE.STRM0_WIDTH } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.STRM0_WIDTH}] ${MODELPARAM_VALUE.STRM0_WIDTH} -} - -proc update_MODELPARAM_VALUE.STRM1_WIDTH { MODELPARAM_VALUE.STRM1_WIDTH PARAM_VALUE.STRM1_WIDTH } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.STRM1_WIDTH}] ${MODELPARAM_VALUE.STRM1_WIDTH} -} - -proc update_MODELPARAM_VALUE.STRM2_WIDTH { MODELPARAM_VALUE.STRM2_WIDTH PARAM_VALUE.STRM2_WIDTH } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.STRM2_WIDTH}] ${MODELPARAM_VALUE.STRM2_WIDTH} -} - -proc update_MODELPARAM_VALUE.STRM3_WIDTH { MODELPARAM_VALUE.STRM3_WIDTH PARAM_VALUE.STRM3_WIDTH } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.STRM3_WIDTH}] ${MODELPARAM_VALUE.STRM3_WIDTH} -} - -proc update_MODELPARAM_VALUE.STRM4_WIDTH { MODELPARAM_VALUE.STRM4_WIDTH PARAM_VALUE.STRM4_WIDTH } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.STRM4_WIDTH}] ${MODELPARAM_VALUE.STRM4_WIDTH} -} - -proc update_MODELPARAM_VALUE.STRM5_WIDTH { MODELPARAM_VALUE.STRM5_WIDTH PARAM_VALUE.STRM5_WIDTH } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.STRM5_WIDTH}] ${MODELPARAM_VALUE.STRM5_WIDTH} -} - -proc update_MODELPARAM_VALUE.STRM0_DEPTH { MODELPARAM_VALUE.STRM0_DEPTH PARAM_VALUE.STRM0_DEPTH } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.STRM0_DEPTH}] ${MODELPARAM_VALUE.STRM0_DEPTH} -} - -proc update_MODELPARAM_VALUE.STRM1_DEPTH { MODELPARAM_VALUE.STRM1_DEPTH PARAM_VALUE.STRM1_DEPTH } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.STRM1_DEPTH}] ${MODELPARAM_VALUE.STRM1_DEPTH} -} - -proc update_MODELPARAM_VALUE.STRM2_DEPTH { MODELPARAM_VALUE.STRM2_DEPTH PARAM_VALUE.STRM2_DEPTH } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.STRM2_DEPTH}] ${MODELPARAM_VALUE.STRM2_DEPTH} -} - -proc update_MODELPARAM_VALUE.STRM3_DEPTH { MODELPARAM_VALUE.STRM3_DEPTH PARAM_VALUE.STRM3_DEPTH } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.STRM3_DEPTH}] ${MODELPARAM_VALUE.STRM3_DEPTH} -} - -proc update_MODELPARAM_VALUE.STRM4_DEPTH { MODELPARAM_VALUE.STRM4_DEPTH PARAM_VALUE.STRM4_DEPTH } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.STRM4_DEPTH}] ${MODELPARAM_VALUE.STRM4_DEPTH} -} - -proc update_MODELPARAM_VALUE.STRM5_DEPTH { MODELPARAM_VALUE.STRM5_DEPTH PARAM_VALUE.STRM5_DEPTH } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.STRM5_DEPTH}] ${MODELPARAM_VALUE.STRM5_DEPTH} -} - -proc update_MODELPARAM_VALUE.STRM0_OFFSET { MODELPARAM_VALUE.STRM0_OFFSET PARAM_VALUE.STRM0_OFFSET } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.STRM0_OFFSET}] ${MODELPARAM_VALUE.STRM0_OFFSET} -} - -proc update_MODELPARAM_VALUE.STRM1_OFFSET { MODELPARAM_VALUE.STRM1_OFFSET PARAM_VALUE.STRM1_OFFSET } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.STRM1_OFFSET}] ${MODELPARAM_VALUE.STRM1_OFFSET} -} - -proc update_MODELPARAM_VALUE.STRM2_OFFSET { MODELPARAM_VALUE.STRM2_OFFSET PARAM_VALUE.STRM2_OFFSET } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.STRM2_OFFSET}] ${MODELPARAM_VALUE.STRM2_OFFSET} -} - -proc update_MODELPARAM_VALUE.STRM3_OFFSET { MODELPARAM_VALUE.STRM3_OFFSET PARAM_VALUE.STRM3_OFFSET } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.STRM3_OFFSET}] ${MODELPARAM_VALUE.STRM3_OFFSET} -} - -proc update_MODELPARAM_VALUE.STRM4_OFFSET { MODELPARAM_VALUE.STRM4_OFFSET PARAM_VALUE.STRM4_OFFSET } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.STRM4_OFFSET}] ${MODELPARAM_VALUE.STRM4_OFFSET} -} - -proc update_MODELPARAM_VALUE.STRM5_OFFSET { MODELPARAM_VALUE.STRM5_OFFSET PARAM_VALUE.STRM5_OFFSET } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.STRM5_OFFSET}] ${MODELPARAM_VALUE.STRM5_OFFSET} -} - -proc update_MODELPARAM_VALUE.AXILITE_ADDR_WIDTH { MODELPARAM_VALUE.AXILITE_ADDR_WIDTH PARAM_VALUE.AXILITE_ADDR_WIDTH } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.AXILITE_ADDR_WIDTH}] ${MODELPARAM_VALUE.AXILITE_ADDR_WIDTH} -} From 39e4c313918ff85d1d2fb6105b10bef0424d29ae Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thomas=20B=2E=20Preu=C3=9Fer?= Date: Tue, 18 Apr 2023 20:55:34 +0100 Subject: [PATCH 117/665] Adding FINN instantiation template for revised memstream module. --- finn-rtllib/memstream/hdl/memstream_axi.sv | 14 +-- .../memstream/hdl/memstream_axi_wrapper.v | 116 ++++++++++++++++++ 2 files changed, 123 insertions(+), 7 deletions(-) create mode 100644 finn-rtllib/memstream/hdl/memstream_axi_wrapper.v diff --git a/finn-rtllib/memstream/hdl/memstream_axi.sv b/finn-rtllib/memstream/hdl/memstream_axi.sv index 620d9ec1de..ee64bdd057 100644 --- a/finn-rtllib/memstream/hdl/memstream_axi.sv +++ b/finn-rtllib/memstream/hdl/memstream_axi.sv @@ -59,15 +59,15 @@ module memstream_axi #( output logic [1:0] bresp, // AXI-lite Read - output loigc arready, - input loigc arvalid, - input loigc [2:0] arprot, - input loigc [AXILITE_ADDR_WIDTH-1:0] araddr, + output logic arready, + input logic arvalid, + input logic [2:0] arprot, + input logic [AXILITE_ADDR_WIDTH-1:0] araddr, - input loigc rready, - output loigc rvalid, + input logic rready, + output logic rvalid, output logic [ 1:0] rresp, - output loigc [31:0] rdata, + output logic [31:0] rdata, // Continuous output stream input logic m_axis_0_tready, diff --git a/finn-rtllib/memstream/hdl/memstream_axi_wrapper.v b/finn-rtllib/memstream/hdl/memstream_axi_wrapper.v new file mode 100644 index 0000000000..2982dd8672 --- /dev/null +++ b/finn-rtllib/memstream/hdl/memstream_axi_wrapper.v @@ -0,0 +1,116 @@ +/** + * Copyright (c) 2023, Xilinx + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of FINN nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * @author Thomas B. Preußer + */ + +module memstream_axi_wrapper #( + parameter DEPTH = $DEPTH$, + parameter WIDTH = $WIDTH$, + + parameter INIT_FILE = $INIT_FILE$, + parameter RAM_STYLE = $RAM_STYLE$, + + localparam AXILITE_ADDR_WIDTH = $clog2(DEPTH * (2**$clog2((WIDTH+31)/32))) + 2 +)( + // Global Control + (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF m_axis_0" *) + input ap_clk, + (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF m_axis_0" *) + input ap_rst_n, + + // AXI-lite Write + output awready, + input awvalid, + input [2:0] awprot, + input [AXILITE_ADDR_WIDTH-1:0] awaddr, + + output wready, + input wvalid, + input [31:0] wdata, + input [ 3:0] wstrb, + + input bready, + output bvalid, + output [1:0] bresp, + + // AXI-lite Read + output arready, + input arvalid, + input [2:0] arprot, + input [AXILITE_ADDR_WIDTH-1:0] araddr, + + input rready, + output rvalid, + output [ 1:0] rresp, + output [31:0] rdata, + + // Continuous output stream + input m_axis_0_tready, + output m_axis_0_tvalid, + output [((WIDTH+7)/8)*8-1:0] m_axis_0_tdata +); + + memstream_axi #( + .DEPTH(DEPTH), .WIDTH(WIDTH), + .INIT_FILE(INIT_FILE), + .RAM_STYLE(RAM_STYLE) + ) core ( + .clk(ap_clk), .rst(!ap_rst_n), + + // AXI-lite Write + .awready(awready), + .awvalid(awvalid), + .awprot(awprot), + .awaddr(awaddr), + .wready(wready), + .wvalid(wvalid), + .wdata(wdata), + .wstrb(wstrb), + .bready(bready), + .bvalid(bvalid), + .bresp(bresp), + + // AXI-lite Read + .arready(arready), + .arvalid(arvalid), + .arprot(arprot), + .araddr(araddr), + .rready(rready), + .rvalid(rvalid), + .rresp(rresp), + .rdata(rdata), + + // Continuous output stream + .m_axis_0_tready(m_axis_0_tready), + .m_axis_0_tvalid(m_axis_0_tvalid), + .m_axis_0_tdata(m_axis_0_tdata) + ); + +endmodule : memstream_axi_wrapper From aa1ea2e95f9023d70e09ad2f9966a68cf4416a16 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 19 Apr 2023 16:31:09 +0100 Subject: [PATCH 118/665] [Tests] Run linting on rtl swg test --- tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py index 2f3ad0a23d..e8236c0c6b 100755 --- a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py +++ b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py @@ -204,7 +204,7 @@ def test_fpgadataflow_slidingwindow_rtl( ) if (stride_h > k_h) or (stride_w > k_w) and not parallel_window: pytest.skip( - "Not all combinations for stride > k edge case supported in default mode" + "Not all combinations for stride > k edge case supported in default mode" ) if k_h == 1 and k_w == 1 and simd != ifm_ch: pytest.skip("1x1 Kernel only supported in parallel mode (SIMD=C)") From 1155ac40183efc6da784d22ce9da395e7c36a3ed Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thomas=20B=2E=20Preu=C3=9Fer?= Date: Fri, 21 Apr 2023 15:16:24 +0100 Subject: [PATCH 119/665] Prepare for memstream instantiation as an IP core. --- finn-rtllib/memstream/component.xml | 835 ++++++++++++++++++ finn-rtllib/memstream/hdl/memstream_axi.sv | 2 +- .../memstream/hdl/memstream_axi_wrapper.v | 18 +- finn-rtllib/memstream/xgui/memstream_v1_0.tcl | 76 ++ .../fpgadataflow/matrixvectoractivation.py | 42 +- 5 files changed, 932 insertions(+), 41 deletions(-) create mode 100644 finn-rtllib/memstream/component.xml create mode 100644 finn-rtllib/memstream/xgui/memstream_v1_0.tcl diff --git a/finn-rtllib/memstream/component.xml b/finn-rtllib/memstream/component.xml new file mode 100644 index 0000000000..191454ed61 --- /dev/null +++ b/finn-rtllib/memstream/component.xml @@ -0,0 +1,835 @@ + + + amd.com + FINN + memstream + 1.0 + + + m_axis_0 + + + + + + + TDATA + + + m_axis_0_tdata + + + + + TVALID + + + m_axis_0_tvalid + + + + + TREADY + + + m_axis_0_tready + + + + + + aximm + + + + + + + + + AWADDR + + + awaddr + + + + + AWPROT + + + awprot + + + + + AWVALID + + + awvalid + + + + + AWREADY + + + awready + + + + + WDATA + + + wdata + + + + + WSTRB + + + wstrb + + + + + WVALID + + + wvalid + + + + + WREADY + + + wready + + + + + BRESP + + + bresp + + + + + BVALID + + + bvalid + + + + + BREADY + + + bready + + + + + ARADDR + + + araddr + + + + + ARPROT + + + arprot + + + + + ARVALID + + + arvalid + + + + + ARREADY + + + arready + + + + + RDATA + + + rdata + + + + + RRESP + + + rresp + + + + + RVALID + + + rvalid + + + + + RREADY + + + rready + + + + + + ap_rst_n + + + + + + + RST + + + ap_rst_n + + + + + + POLARITY + ACTIVE_LOW + + + ASSOCIATED_BUSIF + m_axis_0 + + + + + ap_clk + + + + + + + CLK + + + ap_clk + + + + + + ASSOCIATED_RESET + ap_rst_n + + + ASSOCIATED_BUSIF + m_axis_0:interface_aximm + + + + + + + interface_aximm + interface_aximm + + reg0 + reg0 + 0x0 + 4096 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + SystemVerilog + memstream_axi_wrapper + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + e498d456 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 91d40e29 + + + + + + + ap_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + + + + + + ap_rst_n + + in + + + std_logic + xilinx_anylanguagesynthesis + + + + + + awready + + out + + + std_logic + xilinx_anylanguagesynthesis + + + + + + awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + + + + 0 + + + + + awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + + + + 0 + + + + + awaddr + + in + + 10 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + + + + 0 + + + + + wready + + out + + + std_logic + xilinx_anylanguagesynthesis + + + + + + wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + + + + 0 + + + + + wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + + + + 0 + + + + + wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + + + + 1 + + + + + bready + + in + + + std_logic + xilinx_anylanguagesynthesis + + + + 0 + + + + + bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + + + + + + bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + + + + + + arready + + out + + + std_logic + xilinx_anylanguagesynthesis + + + + + + arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + + + + 0 + + + + + arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + + + + 0 + + + + + araddr + + in + + 10 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + + + + 0 + + + + + rready + + in + + + std_logic + xilinx_anylanguagesynthesis + + + + 0 + + + + + rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + + + + + + rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + + + + + + rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + + + + + + m_axis_0_tready + + in + + + std_logic + xilinx_anylanguagesynthesis + + + + 1 + + + + + m_axis_0_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + + + + + + m_axis_0_tdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + + + + + + + + DEPTH + Depth + 512 + + + WIDTH + Width + 32 + + + INIT_FILE + Init File + + + + RAM_STYLE + Ram Style + auto + + + AXILITE_ADDR_WIDTH + Axilite Addr Width + 11 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + hdl/axilite_if.v + verilogSource + + + hdl/memstream.sv + systemVerilogSource + + + hdl/memstream_axi.sv + systemVerilogSource + + + hdl/memstream_axi_wrapper.v + verilogSource + CHECKSUM_0ce7d8fc + + + + xilinx_xpgui_view_fileset + + xgui/memstream_v1_0.tcl + tclSource + CHECKSUM_91d40e29 + XGUI_VERSION_2 + + + + memstream + + + DEPTH + Depth + 512 + + + + required + + + + + + WIDTH + Width + 32 + + + + required + + + + + + INIT_FILE + Init File + + + + RAM_STYLE + Ram Style + auto + + + Component_Name + memstream_axi_wrapper_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /UserIP + + memstream + level_0 + package_project + AMD + 1 + + user.org:user:memstream_axi_wrapper:1.0 + + 2023-04-21T12:20:38Z + + + + + + 2022.1 + + + + + + + + + + + + + + diff --git a/finn-rtllib/memstream/hdl/memstream_axi.sv b/finn-rtllib/memstream/hdl/memstream_axi.sv index ee64bdd057..136bcb1d7e 100644 --- a/finn-rtllib/memstream/hdl/memstream_axi.sv +++ b/finn-rtllib/memstream/hdl/memstream_axi.sv @@ -130,7 +130,7 @@ module memstream_axi #( .odat(m_axis_0_tdata[WIDTH-1:0]) ); if($bits(m_axis_0_tdata) > WIDTH) begin - assign m_axis_0_tdata[$left(m_axis_0_tdata):WIDTH] <= '0; + assign m_axis_0_tdata[$left(m_axis_0_tdata):WIDTH] = '0; end endmodule : memstream_axi diff --git a/finn-rtllib/memstream/hdl/memstream_axi_wrapper.v b/finn-rtllib/memstream/hdl/memstream_axi_wrapper.v index 2982dd8672..69d6b64dec 100644 --- a/finn-rtllib/memstream/hdl/memstream_axi_wrapper.v +++ b/finn-rtllib/memstream/hdl/memstream_axi_wrapper.v @@ -31,13 +31,13 @@ */ module memstream_axi_wrapper #( - parameter DEPTH = $DEPTH$, - parameter WIDTH = $WIDTH$, + parameter DEPTH = 512, + parameter WIDTH = 32, - parameter INIT_FILE = $INIT_FILE$, - parameter RAM_STYLE = $RAM_STYLE$, + parameter INIT_FILE = "", + parameter RAM_STYLE = "auto", - localparam AXILITE_ADDR_WIDTH = $clog2(DEPTH * (2**$clog2((WIDTH+31)/32))) + 2 + parameter AXILITE_ADDR_WIDTH = $clog2(DEPTH * (2**$clog2((WIDTH+31)/32))) + 2 )( // Global Control (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF m_axis_0" *) @@ -77,9 +77,15 @@ module memstream_axi_wrapper #( output [((WIDTH+7)/8)*8-1:0] m_axis_0_tdata ); + localparam INIT_FILTERED = +`ifdef SYNTHESIS + RAM_STYLE == "ultra"? "" : +`endif + INIT_FILE; + memstream_axi #( .DEPTH(DEPTH), .WIDTH(WIDTH), - .INIT_FILE(INIT_FILE), + .INIT_FILE(INIT_FILTERED), .RAM_STYLE(RAM_STYLE) ) core ( .clk(ap_clk), .rst(!ap_rst_n), diff --git a/finn-rtllib/memstream/xgui/memstream_v1_0.tcl b/finn-rtllib/memstream/xgui/memstream_v1_0.tcl new file mode 100644 index 0000000000..7feac1fbe3 --- /dev/null +++ b/finn-rtllib/memstream/xgui/memstream_v1_0.tcl @@ -0,0 +1,76 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DEPTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "INIT_FILE" -parent ${Page_0} + ipgui::add_param $IPINST -name "RAM_STYLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "WIDTH" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.DEPTH { PARAM_VALUE.DEPTH } { + # Procedure called to update DEPTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEPTH { PARAM_VALUE.DEPTH } { + # Procedure called to validate DEPTH + return true +} + +proc update_PARAM_VALUE.INIT_FILE { PARAM_VALUE.INIT_FILE } { + # Procedure called to update INIT_FILE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.INIT_FILE { PARAM_VALUE.INIT_FILE } { + # Procedure called to validate INIT_FILE + return true +} + +proc update_PARAM_VALUE.RAM_STYLE { PARAM_VALUE.RAM_STYLE } { + # Procedure called to update RAM_STYLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.RAM_STYLE { PARAM_VALUE.RAM_STYLE } { + # Procedure called to validate RAM_STYLE + return true +} + +proc update_PARAM_VALUE.WIDTH { PARAM_VALUE.WIDTH } { + # Procedure called to update WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.WIDTH { PARAM_VALUE.WIDTH } { + # Procedure called to validate WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.DEPTH { MODELPARAM_VALUE.DEPTH PARAM_VALUE.DEPTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEPTH}] ${MODELPARAM_VALUE.DEPTH} +} + +proc update_MODELPARAM_VALUE.WIDTH { MODELPARAM_VALUE.WIDTH PARAM_VALUE.WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.WIDTH}] ${MODELPARAM_VALUE.WIDTH} +} + +proc update_MODELPARAM_VALUE.INIT_FILE { MODELPARAM_VALUE.INIT_FILE PARAM_VALUE.INIT_FILE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.INIT_FILE}] ${MODELPARAM_VALUE.INIT_FILE} +} + +proc update_MODELPARAM_VALUE.RAM_STYLE { MODELPARAM_VALUE.RAM_STYLE PARAM_VALUE.RAM_STYLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.RAM_STYLE}] ${MODELPARAM_VALUE.RAM_STYLE} +} + +proc update_MODELPARAM_VALUE.AXILITE_ADDR_WIDTH { MODELPARAM_VALUE.AXILITE_ADDR_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + # WARNING: There is no corresponding user parameter named "AXILITE_ADDR_WIDTH". Setting updated value from the model parameter. +set_property value 11 ${MODELPARAM_VALUE.AXILITE_ADDR_WIDTH} +} + diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index aa987384dd..68ef4cb6fb 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -867,29 +867,9 @@ def generate_params(self, model, path): self.make_weight_file(weights, "decoupled_npy", weight_filename_sim) if mem_mode == "decoupled": # also save weights as Verilog .dat file - # note that we provide two different .dat files, one for synth - # and one for synthesis. this is because URAM-based weights always - # need zero weights for synthesis, otherwise they get inferred - # as BRAM - weight_filename_rtl_synth = "{}/memblock_synth_0.dat".format( - code_gen_dir - ) - weight_filename_rtl_sim = "{}/memblock_sim_0.dat".format(code_gen_dir) - # sim weights are always the true weights - self.make_weight_file( - weights, "decoupled_verilog_dat", weight_filename_rtl_sim - ) - ram_style = self.get_nodeattr("ram_style") - if ram_style == "ultra": - # UltraRAM must have no memory initializer, or only zeroes - # otherwise BRAM will be inferred instead of URAM - # as a workaround we provide a zero-weight init here - synth_weights = np.zeros_like(weights, dtype=np.float32) - else: - synth_weights = weights - self.make_weight_file( - synth_weights, "decoupled_verilog_dat", weight_filename_rtl_synth - ) + # This file will be ignored when synthesizing UltraScale memory. + weight_filename_rtl = "{}/memblock.dat".format(code_gen_dir) + self.make_weight_file(weights, "decoupled_verilog_dat", weight_filename_rtl) else: raise Exception( """Please set mem_mode to "const", "decoupled", or "external", @@ -1387,24 +1367,18 @@ def code_generation_ipi(self): ) cmd.append( "set_property -dict [list " - "CONFIG.NSTREAMS {1} " - "CONFIG.MEM_DEPTH {%d} " - "CONFIG.MEM_WIDTH {%d} " - "CONFIG.MEM_INIT {%s} " + "CONFIG.DEPTH {%d} " + "CONFIG.WIDTH {%d} " + "CONFIG.INIT_FILE {%s} " "CONFIG.RAM_STYLE {%s} " - "CONFIG.STRM0_DEPTH {%d} " - "CONFIG.STRM0_WIDTH {%d} " - "CONFIG.STRM0_OFFSET {0} " "] [get_bd_cells /%s/%s]" % ( self.calc_wmem(), self.get_weightstream_width_padded(), - self.get_nodeattr("code_gen_dir_ipgen") + "/", + self.get_nodeattr("code_gen_dir_ipgen") + "/memblock.dat", self.get_nodeattr("ram_style"), - self.calc_wmem(), - self.get_weightstream_width_padded(), node_name, - strm_inst, + strm_inst ) ) cmd.append( From c179c0cdc03351339287a984ef771e513ee4cce9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thomas=20B=2E=20Preu=C3=9Fer?= Date: Fri, 21 Apr 2023 16:20:43 +0100 Subject: [PATCH 120/665] Renaming configuration interface to s_axilite. --- finn-rtllib/memstream/component.xml | 26 +++++++++++++++----------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/finn-rtllib/memstream/component.xml b/finn-rtllib/memstream/component.xml index 191454ed61..2705f61908 100644 --- a/finn-rtllib/memstream/component.xml +++ b/finn-rtllib/memstream/component.xml @@ -38,7 +38,7 @@ - aximm + s_axilite @@ -247,7 +247,11 @@ ASSOCIATED_BUSIF - m_axis_0:interface_aximm + m_axis_0:s_axilite + + + FREQ_TOLERANCE_HZ + -1 @@ -280,7 +284,7 @@ viewChecksum - e498d456 + 4d23c8e5 @@ -689,7 +693,7 @@ AXILITE_ADDR_WIDTH Axilite Addr Width - 11 + 11 @@ -718,7 +722,7 @@ hdl/memstream_axi_wrapper.v verilogSource - CHECKSUM_0ce7d8fc + CHECKSUM_a3b36ea4 @@ -808,22 +812,22 @@ level_0 package_project AMD - 1 + 2 user.org:user:memstream_axi_wrapper:1.0 - 2023-04-21T12:20:38Z + 2023-04-21T15:18:55Z 2022.1 - + - - - + + + From 763d876eba9240b52d92125772e6972342c0b5c5 Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 21 Apr 2023 16:36:13 +0100 Subject: [PATCH 121/665] [finn-rtllib] Re-instantiate FIFO rtl implementation --- finn-rtllib/memstream/hdl/Q_srl.v | 308 ++++++++++++++++++++++++++++++ 1 file changed, 308 insertions(+) create mode 100644 finn-rtllib/memstream/hdl/Q_srl.v diff --git a/finn-rtllib/memstream/hdl/Q_srl.v b/finn-rtllib/memstream/hdl/Q_srl.v new file mode 100644 index 0000000000..11cef604e0 --- /dev/null +++ b/finn-rtllib/memstream/hdl/Q_srl.v @@ -0,0 +1,308 @@ +// original source: +// https://github.com/nachiket/tdfc/blob/master/verilog/queues/Q_srl_oreg3_prefull_SIMPLE.v + + +// Copyright (c) 1999 The Regents of the University of California +// Copyright (c) 2010 The Regents of the University of Pennsylvania +// Copyright (c) 2011 Department of Electrical and Electronic Engineering, Imperial College London +// Copyright (c) 2020 Xilinx +// +// Permission to use, copy, modify, and distribute this software and +// its documentation for any purpose, without fee, and without a +// written agreement is hereby granted, provided that the above copyright +// notice and this paragraph and the following two paragraphs appear in +// all copies. +// +// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR +// DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING +// LOST PROFITS, ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, +// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF +// SUCH DAMAGE. +// +// THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY +// AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS ON +// AN "AS IS" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO +// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. +// + +// Q_srl_oreg3_prefull_SIMPLE.v +// +// - In-page queue with parameterizable depth, bit width +// - Stream I/O is triple (data, valid, back-pressure), +// with EOS concatenated into the data +// - Flow control for input & output is combinationally decoupled +// - 2 <= depth <= 256 +// * (depth >= 2) is required to decouple I/O flow control, +// where empty => no produce, full => no consume, +// and depth 1 would ping-pong between the two at half rate +// * (depth <= 256) can be modified +// by changing ''synthesis loop_limit X'' below +// and changing ''addrwidth'' or its log computation +// - 1 <= width +// - Queue storage is in SRL16E, up to depth 16 per LUT per bit-slice, +// plus output register (for fast output) +// - Queue addressing is done by ''addr'' up-down counter +// - Queue fullness is checked by comparator (addr==depth) +// - Queue fullness is pre-computed for next cycle +// - Queue input back-pressure is pre-computed for next cycle +// - Queue output valid (state!=state__empty) is pre-computed for next cycle +// (necessary since SRL data output reg requires non-boolean state) +// - FSM has 3 states (empty, one, more) +// - When empty, continue to emit most recently emitted value (for debugging) +// +// - Queue slots used = / (state==state_empty) ? 0 +// | (state==state_one) ? 1 +// \ (state==state_more) ? addr+2 +// - Queue slots used <= depth +// - Queue slots remaining = depth - used +// = / (state==state_empty) ? depth +// | (state==state_one) ? depth-1 +// \ (state==state_more) ? depth-2-addr +// +// - Synplify 7.1 / 8.0 +// - Eylon Caspi, 9/11/03, 8/18/04, 3/29/05 + + +`ifdef Q_srl +`else +`define Q_srl + + +module Q_srl (clock, reset, i_d, i_v, i_r, o_d, o_v, o_r, count, maxcount); + + parameter depth = 16; // - greatest #items in queue (2 <= depth <= 256) + parameter width = 16; // - width of data (i_d, o_d) + + parameter addrwidth = $clog2(depth); + + input clock; + input reset; + + input [width-1:0] i_d; // - input stream data (concat data + eos) + input i_v; // - input stream valid + output i_r; // - input stream ready + wire i_b; // - input stream back-pressure + + output [width-1:0] o_d; // - output stream data (concat data + eos) + output o_v; // - output stream valid + input o_r; // - output stream ready + wire o_b; // - output stream back-pressure + + output [addrwidth:0] count; // - output number of elems in queue + output [addrwidth:0] maxcount; // - maximum observed count since reset + + reg [addrwidth:0] maxcount_reg; // - maximum count seen until now + reg [addrwidth-1:0] addr, addr_, a_; // - SRL16 address + // for data output + reg shift_en_; // - SRL16 shift enable + reg [width-1:0] srl [depth-2:0]; // - SRL16 memory + reg shift_en_o_; // - SRLO shift enable + reg [width-1:0] srlo_, srlo // - SRLO output reg + /* synthesis syn_allow_retiming=0 */ ; + + parameter state_empty = 2'd0; // - state empty : o_v=0 o_d=UNDEFINED + parameter state_one = 2'd1; // - state one : o_v=1 o_d=srlo + parameter state_more = 2'd2; // - state more : o_v=1 o_d=srlo + // #items in srl = addr+2 + + reg [1:0] state, state_; // - state register + + wire addr_full_; // - true iff addr==depth-2 on NEXT cycle + reg addr_full; // - true iff addr==depth-2 + wire addr_zero_; // - true iff addr==0 + wire o_v_reg_; // - true iff state_empty on NEXT cycle + reg o_v_reg // - true iff state_empty + /* synthesis syn_allow_retiming=0 */ ; + wire i_b_reg_; // - true iff !full on NEXT cycle + reg i_b_reg // - true iff !full + /* synthesis syn_allow_retiming=0 */ ; + + assign addr_full_ = (state_==state_more) && (addr_==depth-2); + // - queue full + assign addr_zero_ = (addr==0); // - queue contains 2 (or 1,0) + assign o_v_reg_ = (state_!=state_empty); // - output valid if non-empty + assign i_b_reg_ = addr_full_; // - input bp if full + assign o_d = srlo; // - output data from queue + assign o_v = o_v_reg; // - output valid if non-empty + assign i_b = i_b_reg; // - input bp if full + assign maxcount = maxcount_reg; + + assign i_r = !i_b; + assign o_b = !o_r; + + assign count = (state==state_more ? addr+2 : (state==state_one ? 1 : 0)); + + // - ''always'' block with both FFs and SRL16 does not work, + // since FFs need reset but SRL16 does not + + always @(posedge clock) begin // - seq always: FFs + if (reset) begin + state <= state_empty; + addr <= 0; + addr_full <= 0; + o_v_reg <= 0; + + i_b_reg <= 0; + maxcount_reg <= 0; + + end + else begin + state <= state_; + addr <= addr_; + addr_full <= addr_full_; + o_v_reg <= o_v_reg_; + i_b_reg <= i_b_reg_; + maxcount_reg <= (count > maxcount_reg ? count : maxcount_reg); + end + end // always @ (posedge clock) + + always @(posedge clock) begin // - seq always: srlo + // - infer enabled output reg at end of shift chain + // - input first element from i_d, all subsequent elements from SRL16 + if (reset) begin + srlo <= 0; + end + else begin + if (shift_en_o_) begin + srlo <= srlo_; + end + end + end // always @ (posedge clock) + + always @(posedge clock) begin // - seq always: srl + // - infer enabled SRL16E from shifting srl array + // - no reset capability; srl[] contents undefined on reset + if (shift_en_) begin + // synthesis loop_limit 256 + for (a_=depth-2; a_>0; a_=a_-1) begin + srl[a_] = srl[a_-1]; + end + srl[0] <= i_d; + end + end // always @ (posedge clock or negedge reset) + + always @* begin // - combi always + srlo_ <= 'bx; + shift_en_o_ <= 1'bx; + shift_en_ <= 1'bx; + addr_ <= 'bx; + state_ <= 2'bx; + case (state) + + state_empty: begin // - (empty, will not produce) + if (i_v) begin // - empty & i_v => consume + srlo_ <= i_d; + shift_en_o_ <= 1; + shift_en_ <= 1'bx; + addr_ <= 0; + state_ <= state_one; + end + else begin // - empty & !i_v => idle + srlo_ <= 'bx; + shift_en_o_ <= 0; + shift_en_ <= 1'bx; + addr_ <= 0; + state_ <= state_empty; + end + end + + state_one: begin // - (contains one) + if (i_v && o_b) begin // - one & i_v & o_b => consume + srlo_ <= 'bx; + shift_en_o_ <= 0; + shift_en_ <= 1; + addr_ <= 0; + state_ <= state_more; + end + else if (i_v && !o_b) begin // - one & i_v & !o_b => cons+prod + srlo_ <= i_d; + shift_en_o_ <= 1; + shift_en_ <= 1; + addr_ <= 0; + state_ <= state_one; + end + else if (!i_v && o_b) begin // - one & !i_v & o_b => idle + srlo_ <= 'bx; + shift_en_o_ <= 0; + shift_en_ <= 1'bx; + addr_ <= 0; + state_ <= state_one; + end + else if (!i_v && !o_b) begin // - one & !i_v & !o_b => produce + srlo_ <= 'bx; + shift_en_o_ <= 0; + shift_en_ <= 1'bx; + addr_ <= 0; + state_ <= state_empty; + end + end // case: state_one + + state_more: begin // - (contains more than one) + if (addr_full || (depth==2)) begin + // - (full, will not consume) + // - (full here if depth==2) + if (o_b) begin // - full & o_b => idle + srlo_ <= 'bx; + shift_en_o_ <= 0; + shift_en_ <= 0; + addr_ <= addr; + state_ <= state_more; + end + else begin // - full & !o_b => produce + srlo_ <= srl[addr]; + shift_en_o_ <= 1; + shift_en_ <= 0; +// addr_ <= addr-1; +// state_ <= state_more; + addr_ <= addr_zero_ ? 0 : addr-1; + state_ <= addr_zero_ ? state_one : state_more; + end + end + else begin // - (mid: neither empty nor full) + if (i_v && o_b) begin // - mid & i_v & o_b => consume + srlo_ <= 'bx; + shift_en_o_ <= 0; + shift_en_ <= 1; + addr_ <= addr+1; + state_ <= state_more; + end + else if (i_v && !o_b) begin // - mid & i_v & !o_b => cons+prod + srlo_ <= srl[addr]; + shift_en_o_ <= 1; + shift_en_ <= 1; + addr_ <= addr; + state_ <= state_more; + end + else if (!i_v && o_b) begin // - mid & !i_v & o_b => idle + srlo_ <= 'bx; + shift_en_o_ <= 0; + shift_en_ <= 0; + addr_ <= addr; + state_ <= state_more; + end + else if (!i_v && !o_b) begin // - mid & !i_v & !o_b => produce + srlo_ <= srl[addr]; + shift_en_o_ <= 1; + shift_en_ <= 0; + addr_ <= addr_zero_ ? 0 : addr-1; + state_ <= addr_zero_ ? state_one : state_more; + end + end // else: !if(addr_full) + end // case: state_more + + default: begin + srlo_ <= 'bx; + shift_en_o_ <= 1'bx; + shift_en_ <= 1'bx; + addr_ <= 'bx; + state_ <= 2'bx; + end // case: default + + endcase // case(state) + end // always @ * + +endmodule // Q_srl + + +`endif // `ifdef Q_srl From eb31a30ce4a4a8d0b3b6b670ac40ca9524732063 Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 21 Apr 2023 16:46:58 +0100 Subject: [PATCH 122/665] [CustomOp] Update Thresholding node to use new memstream implementation --- .../fpgadataflow/thresholding_batch.py | 45 +++++-------------- 1 file changed, 10 insertions(+), 35 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/thresholding_batch.py b/src/finn/custom_op/fpgadataflow/thresholding_batch.py index 292f70941a..eab50c2cbc 100644 --- a/src/finn/custom_op/fpgadataflow/thresholding_batch.py +++ b/src/finn/custom_op/fpgadataflow/thresholding_batch.py @@ -45,8 +45,6 @@ rtlsim_output_to_npy, ) -from . import templates - # ONNX i/o tensor shape assumptions for Thresholding: # input 0 is the input tensor, shape (..., NumChannels) # input 1 is the threshold tensor, shape (NumChannels, n_thres) @@ -59,7 +57,6 @@ class Thresholding_Batch(HLSCustomOp): def __init__(self, onnx_node, **kwargs): super().__init__(onnx_node, **kwargs) - self.decoupled_wrapper = templates.decoupled_wrapper def get_nodeattr_types(self): my_attrs = { @@ -457,26 +454,10 @@ def generate_params(self, model, path): weight_filename_sim = "{}/thresholds.npy".format(code_gen_dir) self.make_weight_file(thresholds, "decoupled_npy", weight_filename_sim) # also save weights as Verilog .dat file - # note that we provide two different .dat files, one for synth - # and one for synthesis. this is because URAM-based weights always - # need zero weights for synthesis, otherwise they get inferred - # as BRAM - weight_filename_rtl_synth = "{}/memblock_synth_0.dat".format(code_gen_dir) - weight_filename_rtl_sim = "{}/memblock_sim_0.dat".format(code_gen_dir) - # sim weights are always the true weights + # This file will be ignored when synthesizing UltraScale memory. + weight_filename_rtl = "{}/memblock.dat".format(code_gen_dir) self.make_weight_file( - thresholds, "decoupled_verilog_dat", weight_filename_rtl_sim - ) - ram_style = self.get_nodeattr("ram_style") - if ram_style == "ultra": - # UltraRAM must have no memory initializer, or only zeroes - # otherwise BRAM will be inferred instead of URAM - # as a workaround we provide a zero-weight init here - synth_thresholds = np.zeros_like(thresholds, dtype=np.float32) - else: - synth_thresholds = thresholds - self.make_weight_file( - synth_thresholds, "decoupled_verilog_dat", weight_filename_rtl_synth + thresholds, "decoupled_verilog_dat", weight_filename_rtl ) else: raise Exception("Unrecognized mem_mode") @@ -843,7 +824,7 @@ def code_generation_ipi(self): % (self.get_nodeattr("ip_vlnv"), node_name, node_name) ) # instantiate a streamer and connect it to the HLS IP - strm_vlnv = "xilinx.com:user:memstream:1.0" + strm_vlnv = "amd.com:FINN:memstream:1.0" strm_inst = node_name + "_wstrm" cmd.append( "create_bd_cell -type ip -vlnv %s /%s/%s" @@ -851,22 +832,16 @@ def code_generation_ipi(self): ) cmd.append( "set_property -dict [list " - "CONFIG.NSTREAMS {1} " - "CONFIG.MEM_DEPTH {%d} " - "CONFIG.MEM_WIDTH {%d} " - "CONFIG.MEM_INIT {%s} " + "CONFIG.DEPTH {%d} " + "CONFIG.WIDTH {%d} " + "CONFIG.INIT_FILE {%s} " "CONFIG.RAM_STYLE {%s} " - "CONFIG.STRM0_DEPTH {%d} " - "CONFIG.STRM0_WIDTH {%d} " - "CONFIG.STRM0_OFFSET {0} " "] [get_bd_cells /%s/%s]" % ( self.calc_tmem(), self.get_weightstream_width_padded(), - self.get_nodeattr("code_gen_dir_ipgen") + "/", + self.get_nodeattr("code_gen_dir_ipgen") + "/memblock.dat", self.get_nodeattr("ram_style"), - self.calc_tmem(), - self.get_weightstream_width_padded(), node_name, strm_inst, ) @@ -877,11 +852,11 @@ def code_generation_ipi(self): % (node_name, strm_inst, node_name, node_name, sname) ) cmd.append( - "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/aresetn]" + "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/ap_rst_n]" % (node_name, rst_name, node_name, strm_inst) ) cmd.append( - "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/aclk]" + "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/ap_clk]" % (node_name, clk_name, node_name, strm_inst) ) cmd.append( From 232e9147723e09389b5fa1c345bf6098a4fc0efa Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 21 Apr 2023 17:01:21 +0100 Subject: [PATCH 123/665] [CustomOp] Delete old decoupled wrapper and linting on MVAU --- .../custom_op/fpgadataflow/matrixvectoractivation.py | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index 68ef4cb6fb..d59b6826c2 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -46,8 +46,6 @@ rtlsim_output_to_npy, ) -from . import templates - # ONNX i/o tensor shape assumptions for MatrixVectorActivation: # input 0 is the input tensor, shape (.., i_size) = (..., MW) # input 1 is the weight tensor, shape (i_size, o_size) = (MW, MH) @@ -62,7 +60,6 @@ class MatrixVectorActivation(HLSCustomOp): def __init__(self, onnx_node, **kwargs): super().__init__(onnx_node, **kwargs) - self.decoupled_wrapper = templates.decoupled_wrapper def get_nodeattr_types(self): my_attrs = { @@ -869,7 +866,9 @@ def generate_params(self, model, path): # also save weights as Verilog .dat file # This file will be ignored when synthesizing UltraScale memory. weight_filename_rtl = "{}/memblock.dat".format(code_gen_dir) - self.make_weight_file(weights, "decoupled_verilog_dat", weight_filename_rtl) + self.make_weight_file( + weights, "decoupled_verilog_dat", weight_filename_rtl + ) else: raise Exception( """Please set mem_mode to "const", "decoupled", or "external", @@ -1378,7 +1377,7 @@ def code_generation_ipi(self): self.get_nodeattr("code_gen_dir_ipgen") + "/memblock.dat", self.get_nodeattr("ram_style"), node_name, - strm_inst + strm_inst, ) ) cmd.append( From a2e8e92892260184a48438fbdd252e17cfe373fd Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 21 Apr 2023 17:18:40 +0100 Subject: [PATCH 124/665] [CustomOp] Update custom ops to use new memstream component --- .../fpgadataflow/channelwise_op_batch.py | 3 - .../fpgadataflow/matrixvectoractivation.py | 2 +- src/finn/custom_op/fpgadataflow/templates.py | 101 ------------------ .../fpgadataflow/vectorvectoractivation.py | 40 ++----- 4 files changed, 9 insertions(+), 137 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/channelwise_op_batch.py b/src/finn/custom_op/fpgadataflow/channelwise_op_batch.py index cde66f1ae2..7791647abf 100644 --- a/src/finn/custom_op/fpgadataflow/channelwise_op_batch.py +++ b/src/finn/custom_op/fpgadataflow/channelwise_op_batch.py @@ -39,8 +39,6 @@ rtlsim_output_to_npy, ) -from . import templates - # ONNX i/o tensor shape assumptions for channelwise ops: # input 0 is the input tensor, shape (..., NumChannels) # input 1 is the channelwise parameter tensor, shape (NumChannels, params_per_channel) @@ -87,7 +85,6 @@ class ChannelwiseOp_Batch(HLSCustomOp): def __init__(self, onnx_node, **kwargs): super().__init__(onnx_node, **kwargs) - self.decoupled_wrapper = templates.decoupled_wrapper def get_nodeattr_types(self): my_attrs = { diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index d59b6826c2..9abc933847 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -1358,7 +1358,7 @@ def code_generation_ipi(self): % (self.get_nodeattr("ip_vlnv"), node_name, node_name) ) # instantiate a streamer and connect it to the HLS IP - strm_vlnv = "xilinx.com:user:memstream:1.0" + strm_vlnv = "amd.com:FINN:memstream:1.0" strm_inst = node_name + "_wstrm" cmd.append( "create_bd_cell -type ip -vlnv %s /%s/%s" diff --git a/src/finn/custom_op/fpgadataflow/templates.py b/src/finn/custom_op/fpgadataflow/templates.py index c7bbc3f139..4e03e6daf9 100644 --- a/src/finn/custom_op/fpgadataflow/templates.py +++ b/src/finn/custom_op/fpgadataflow/templates.py @@ -109,107 +109,6 @@ exit 0 """ -# verilog wrapper for decoupled mem mode -decoupled_wrapper = """ -module $TOPNAME$( -ap_clk, -ap_rst_n, -in0_$HLS_SNAME$_TDATA, -in0_$HLS_SNAME$_TVALID, -in0_$HLS_SNAME$_TREADY, -out_$HLS_SNAME$_TDATA, -out_$HLS_SNAME$_TVALID, -out_$HLS_SNAME$_TREADY -); - -input ap_clk; -input ap_rst_n; -input $IN_RANGE$ in0_$HLS_SNAME$_TDATA; -input in0_$HLS_SNAME$_TVALID; -output in0_$HLS_SNAME$_TREADY; -output $OUT_RANGE$ out_$HLS_SNAME$_TDATA; -output out_$HLS_SNAME$_TVALID; -input out_$HLS_SNAME$_TREADY; - -reg [31:0] config_address = 0; -reg config_ce = 0; -reg config_we = 0; -reg [31:0] config_d0 = 0; -wire [31:0] config_q0; - -//multiple wire AXI Streams -wire m_axis_0_afull; -// FIFO count to generate programmable full -wire [5:0] fifo_0_count; -wire m_axis_0_tready; -wire m_axis_0_tvalid; -wire $WEIGHT_RANGE$ m_axis_0_tdata; - -//memstream component - -memstream -#( -//parameters to enable/disable axi-mm, set number of streams, set readmemh for -// memory, set per-stream offsets in memory, set per-stream widths -.CONFIG_EN(1), -.NSTREAMS(1), -.MEM_DEPTH($MEM_DEPTH$), -.MEM_WIDTH($WEIGHT_WIDTH$), -.MEM_INIT("./"), -.RAM_STYLE("$RAM_STYLE$"), - -//widths per stream -.STRM0_WIDTH($WEIGHT_WIDTH$), - -//depths per stream -.STRM0_DEPTH($WSTREAM_DEPTH$), - -//offsets for each stream -.STRM0_OFFSET(0) -) -mem -( -.aclk(ap_clk), -.aresetn(ap_rst_n), - -//optional configuration interface compatible with ap_memory -.config_address(config_address), -.config_ce(config_ce), -.config_we(config_we), -.config_d0(config_d0), -.config_q0(config_q0), - -//multiple output AXI Streams, TDATA width rounded to multiple of 8 bits -.m_axis_0_afull(m_axis_0_afull), -.m_axis_0_tready(m_axis_0_tready), -.m_axis_0_tvalid(m_axis_0_tvalid), -.m_axis_0_tdata(m_axis_0_tdata) - - -); - - -//MVA_Stream_Unit - -$LAYER_NAME$ -MVA_Stream_U -( -.ap_clk(ap_clk), //input -.ap_rst_n(ap_rst_n), //input -.in0_$HLS_SNAME$_TDATA(in0_$HLS_SNAME$_TDATA), //$IN_RANGE$ input -.in0_$HLS_SNAME$_TVALID(in0_$HLS_SNAME$_TVALID), //input -.in0_$HLS_SNAME$_TREADY(in0_$HLS_SNAME$_TREADY), //output -.weights_$HLS_SNAME$_TDATA(m_axis_0_tdata), //$WEIGHT_RANGE$ input -.weights_$HLS_SNAME$_TVALID(m_axis_0_tvalid), //input -.weights_$HLS_SNAME$_TREADY(m_axis_0_tready), //output -.out_$HLS_SNAME$_TDATA(out_$HLS_SNAME$_TDATA), //$OUT_RANGE$ output -.out_$HLS_SNAME$_TVALID(out_$HLS_SNAME$_TVALID), //output -.out_$HLS_SNAME$_TREADY(out_$HLS_SNAME$_TREADY) //input -); - -endmodule -""" - ip_package_tcl = """ ## IP Info set Vendor "xilinx.com" diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index da79933f26..afbaad5759 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -580,28 +580,10 @@ def generate_params(self, model, path): self.make_weight_file(weights, "decoupled_npy", weight_filename_sim) if mem_mode == "decoupled": # also save weights as Verilog .dat file - # note that we provide two different .dat files, one for synth - # and one for synthesis. this is because URAM-based weights always - # need zero weights for synthesis, otherwise they get inferred - # as BRAM - weight_filename_rtl_synth = "{}/memblock_synth_0.dat".format( - code_gen_dir - ) - weight_filename_rtl_sim = "{}/memblock_sim_0.dat".format(code_gen_dir) - # sim weights are always the true weights - self.make_weight_file( - weights, "decoupled_verilog_dat", weight_filename_rtl_sim - ) - ram_style = self.get_nodeattr("ram_style") - if ram_style == "ultra": - # UltraRAM must have no memory initializer, or only zeroes - # otherwise BRAM will be inferred instead of URAM - # as a workaround we provide a zero-weight init here - synth_weights = np.zeros_like(weights, dtype=np.float32) - else: - synth_weights = weights + # This file will be ignored when synthesizing UltraScale memory. + weight_filename_rtl = "{}/memblock.dat".format(code_gen_dir) self.make_weight_file( - synth_weights, "decoupled_verilog_dat", weight_filename_rtl_synth + weights, "decoupled_verilog_dat", weight_filename_rtl ) else: raise Exception( @@ -1068,7 +1050,7 @@ def code_generation_ipi(self): % (self.get_nodeattr("ip_vlnv"), node_name, node_name) ) # instantiate a streamer and connect it to the HLS IP - strm_vlnv = "xilinx.com:user:memstream:1.0" + strm_vlnv = "amd.com:FINN:memstream:1.0" strm_inst = node_name + "_wstrm" cmd.append( "create_bd_cell -type ip -vlnv %s /%s/%s" @@ -1076,22 +1058,16 @@ def code_generation_ipi(self): ) cmd.append( "set_property -dict [list " - "CONFIG.NSTREAMS {1} " - "CONFIG.MEM_DEPTH {%d} " - "CONFIG.MEM_WIDTH {%d} " - "CONFIG.MEM_INIT {%s} " + "CONFIG.DEPTH {%d} " + "CONFIG.WIDTH {%d} " + "CONFIG.INIT_FILE {%s} " "CONFIG.RAM_STYLE {%s} " - "CONFIG.STRM0_DEPTH {%d} " - "CONFIG.STRM0_WIDTH {%d} " - "CONFIG.STRM0_OFFSET {0} " "] [get_bd_cells /%s/%s]" % ( self.calc_wmem(), self.get_weightstream_width_padded(), - self.get_nodeattr("code_gen_dir_ipgen") + "/", + self.get_nodeattr("code_gen_dir_ipgen") + "/memblock.dat", self.get_nodeattr("ram_style"), - self.calc_wmem(), - self.get_weightstream_width_padded(), node_name, strm_inst, ) From 91ae41aea2b0fe12aab9b2ad734716de0f934d72 Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 24 Apr 2023 10:43:54 +0100 Subject: [PATCH 125/665] [Docs] Move rtd required packages from Dockerfile to requirements.txt --- docker/Dockerfile.finn | 2 -- requirements.txt | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/docker/Dockerfile.finn b/docker/Dockerfile.finn index dbafba2476..f823d3c42b 100644 --- a/docker/Dockerfile.finn +++ b/docker/Dockerfile.finn @@ -88,8 +88,6 @@ RUN pip install jupyter==1.0.0 --ignore-installed RUN pip install markupsafe==2.0.1 RUN pip install matplotlib==3.3.1 --ignore-installed RUN pip install pytest-dependency==0.5.1 -RUN pip install sphinx==5.0.2 -RUN pip install sphinx_rtd_theme==0.5.0 RUN pip install pytest-xdist[setproctitle]==2.4.0 RUN pip install pytest-parallel==0.1.0 RUN pip install "netron>=5.0.0" diff --git a/requirements.txt b/requirements.txt index 6703c83d97..3cf829a171 100644 --- a/requirements.txt +++ b/requirements.txt @@ -13,6 +13,8 @@ pyscaffold==3.2.1 scipy==1.5.2 setupext-janitor>=1.1.2 sigtools==2.0.3 +sphinx==5.0.2 +sphinx_rtd_theme==0.5.0 toposort==1.5 vcdvcd==1.0.5 wget==3.2 From f494b60989447709ab88b313bdaf304d9680b8c3 Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 24 Apr 2023 11:37:55 +0100 Subject: [PATCH 126/665] [Docs] Add sphinx and rtd theme installs to setup.cfg --- setup.cfg | 2 ++ 1 file changed, 2 insertions(+) diff --git a/setup.cfg b/setup.cfg index 1893aa4231..144a6a38d5 100644 --- a/setup.cfg +++ b/setup.cfg @@ -81,6 +81,8 @@ docs = pytest netron vcdvcd + sphinx==5.0.2 + sphinx_rtd_theme==0.5.0 torchvision torch qonnx@git+https://github.com/fastmachinelearning/qonnx@main#egg=qonnx From cd8c6817b26bc319ff9c84fc9a92856e194255dc Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 24 Apr 2023 13:42:37 +0100 Subject: [PATCH 127/665] [rtllib] linting on tcl script --- finn-rtllib/memstream/xgui/memstream_v1_0.tcl | 1 - 1 file changed, 1 deletion(-) diff --git a/finn-rtllib/memstream/xgui/memstream_v1_0.tcl b/finn-rtllib/memstream/xgui/memstream_v1_0.tcl index 7feac1fbe3..4ad14af637 100644 --- a/finn-rtllib/memstream/xgui/memstream_v1_0.tcl +++ b/finn-rtllib/memstream/xgui/memstream_v1_0.tcl @@ -73,4 +73,3 @@ proc update_MODELPARAM_VALUE.AXILITE_ADDR_WIDTH { MODELPARAM_VALUE.AXILITE_ADDR_ # WARNING: There is no corresponding user parameter named "AXILITE_ADDR_WIDTH". Setting updated value from the model parameter. set_property value 11 ${MODELPARAM_VALUE.AXILITE_ADDR_WIDTH} } - From 44aed57b775223be77d8b281315094b8f33b9869 Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 24 Apr 2023 13:43:43 +0100 Subject: [PATCH 128/665] [CustomOp] update rst and clk signal connection for updated memstrm --- src/finn/custom_op/fpgadataflow/matrixvectoractivation.py | 4 ++-- src/finn/custom_op/fpgadataflow/vectorvectoractivation.py | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index 9abc933847..fd41e1f9ad 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -1386,11 +1386,11 @@ def code_generation_ipi(self): % (node_name, strm_inst, node_name, node_name, sname) ) cmd.append( - "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/aresetn]" + "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/ap_rst_n]" % (node_name, rst_name, node_name, strm_inst) ) cmd.append( - "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/aclk]" + "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/ap_clk]" % (node_name, clk_name, node_name, strm_inst) ) cmd.append( diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index afbaad5759..a7aaa186df 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -1078,11 +1078,11 @@ def code_generation_ipi(self): % (node_name, strm_inst, node_name, node_name, sname) ) cmd.append( - "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/aresetn]" + "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/ap_rst_n]" % (node_name, rst_name, node_name, strm_inst) ) cmd.append( - "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/aclk]" + "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/ap_clk]" % (node_name, clk_name, node_name, strm_inst) ) cmd.append( From 876bd89c97730e08d7dbd4f47004fd988fc35054 Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Wed, 26 Apr 2023 13:08:23 +0100 Subject: [PATCH 129/665] [notebooks] import os library to use os.environ[] Signed-off-by: Fionn O'Donohoe --- .../cybersecurity/1-train-mlp-with-brevitas.ipynb | 1 + 1 file changed, 1 insertion(+) diff --git a/notebooks/end2end_example/cybersecurity/1-train-mlp-with-brevitas.ipynb b/notebooks/end2end_example/cybersecurity/1-train-mlp-with-brevitas.ipynb index 7bfedf4bbb..0f90b8ee78 100644 --- a/notebooks/end2end_example/cybersecurity/1-train-mlp-with-brevitas.ipynb +++ b/notebooks/end2end_example/cybersecurity/1-train-mlp-with-brevitas.ipynb @@ -62,6 +62,7 @@ "metadata": {}, "outputs": [], "source": [ + "import os\n", "import onnx\n", "import torch\n", "\n", From 19dafd217e6e1d6541a1eb5147865872502fa5c9 Mon Sep 17 00:00:00 2001 From: Yaman Umuroglu Date: Wed, 3 May 2023 23:17:01 +0200 Subject: [PATCH 130/665] [SWG] move enum def to top, use enum values for codegen --- finn-rtllib/swg/swg_common.sv | 20 +++++++++++-------- .../swg/swg_template_default_dynamic.sv | 20 +++++++++++-------- .../convolutioninputgenerator_rtl.py | 10 +++++----- 3 files changed, 29 insertions(+), 21 deletions(-) diff --git a/finn-rtllib/swg/swg_common.sv b/finn-rtllib/swg/swg_common.sv index ff6778973c..d953078abe 100644 --- a/finn-rtllib/swg/swg_common.sv +++ b/finn-rtllib/swg/swg_common.sv @@ -29,6 +29,18 @@ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ +`ifndef FINN_SWG_ENUM_DEFINED +`define FINN_SWG_ENUM_DEFINED +typedef enum logic [2:0] { + STATE_START, + STATE_LOOP_SIMD, + STATE_LOOP_KW, + STATE_LOOP_KH, + STATE_LOOP_W, + STATE_LOOP_H +} state_e; +`endif + // loop controller used for both, "default" and "parallel", implementation styles module swg_controller #( int unsigned LOOP_H_ITERATIONS, @@ -61,14 +73,6 @@ module swg_controller #( ); // state and counters - typedef enum logic [2:0] { - STATE_START, - STATE_LOOP_SIMD, - STATE_LOOP_KW, - STATE_LOOP_KH, - STATE_LOOP_W, - STATE_LOOP_H - } state_e; state_e State = INNERMOST_STATE; state_e state_next; diff --git a/finn-rtllib/swg/swg_template_default_dynamic.sv b/finn-rtllib/swg/swg_template_default_dynamic.sv index 412f8689ba..c1647ef699 100644 --- a/finn-rtllib/swg/swg_template_default_dynamic.sv +++ b/finn-rtllib/swg/swg_template_default_dynamic.sv @@ -1,3 +1,15 @@ +`ifndef FINN_SWG_ENUM_DEFINED +`define FINN_SWG_ENUM_DEFINED +typedef enum logic [2:0] { + STATE_START, + STATE_LOOP_SIMD, + STATE_LOOP_KW, + STATE_LOOP_KH, + STATE_LOOP_W, + STATE_LOOP_H +} state_e; +`endif + module $TOP_MODULE_NAME$_controller #( int unsigned CNTR_BITWIDTH, int unsigned INCR_BITWIDTH, @@ -62,14 +74,6 @@ module $TOP_MODULE_NAME$_controller #( end // state and counters - typedef enum logic [2:0] { - STATE_START, - STATE_LOOP_SIMD, - STATE_LOOP_KW, - STATE_LOOP_KH, - STATE_LOOP_W, - STATE_LOOP_H - } state_e; state_e State = $INNERMOST_STATE$; state_e state_next; diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py index 173a157841..a1a32ba6af 100755 --- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py +++ b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py @@ -617,13 +617,13 @@ def prepare_codegen_default(self): # skip innermost SIMD loop completely if loop_kw_iterations == 1: # skip innermost KW loop completely - code_gen_dict["$INNERMOST_STATE$"] = [str(3)] # STATE_LOOP_KH + code_gen_dict["$INNERMOST_STATE$"] = ["STATE_LOOP_KH"] loop_kh_iterations -= 1 # -1 because state is initial state else: - code_gen_dict["$INNERMOST_STATE$"] = [str(2)] # STATE_LOOP_KW + code_gen_dict["$INNERMOST_STATE$"] = ["STATE_LOOP_KW"] loop_kw_iterations -= 1 # -1 because state is initial state else: - code_gen_dict["$INNERMOST_STATE$"] = [str(1)] # STATE_LOOP_SIMD + code_gen_dict["$INNERMOST_STATE$"] = ["STATE_LOOP_SIMD"] loop_simd_iterations -= 1 # -1 because state is initial state cntr_bitwidth = math.ceil( @@ -736,10 +736,10 @@ def prepare_codegen_parallel(self): loop_simd_iterations = 1 if loop_w_iterations == 1: - code_gen_dict["$INNERMOST_STATE$"] = [str(5)] # STATE_LOOP_H + code_gen_dict["$INNERMOST_STATE$"] = ["STATE_LOOP_H"] loop_h_iterations -= 1 # -1 because state is initial state else: - code_gen_dict["$INNERMOST_STATE$"] = [str(4)] # STATE_LOOP_W + code_gen_dict["$INNERMOST_STATE$"] = ["STATE_LOOP_W"] loop_w_iterations -= 1 # -1 because state is initial state # set head and tail address increment values From 40ce6b8b6a583e86e12873ba6da0d8348aa15f7f Mon Sep 17 00:00:00 2001 From: Yaman Umuroglu Date: Thu, 4 May 2023 10:01:37 +0100 Subject: [PATCH 131/665] [Test] add synth to one DSWG testcase to trigger (fixed) error --- .../test_fpgadataflow_convinputgenerator_rtl_dynamic.py | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py index 7f7bf649a9..e586984b31 100644 --- a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py +++ b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py @@ -189,6 +189,10 @@ def write_swg_config(sim): "ofm": 64, "depthwise": True, "pad_mode": "SAME_UPPER", + # run synthesis for one configuration + # this helped expose a bug in enum decls previously + # (which config the synth runs on does not matter) + "do_synth": True, } cfg1 = { "idims": [(32, 16), (16, 8)], @@ -198,6 +202,7 @@ def write_swg_config(sim): "ofm": 8, "depthwise": False, "pad_mode": "SAME_UPPER", + "do_synth": False, } cfg2 = { "idims": [(64, 128), (2, 4)], @@ -207,6 +212,7 @@ def write_swg_config(sim): "ofm": 64, "depthwise": True, "pad_mode": "SAME_UPPER", + "do_synth": False, } @@ -215,6 +221,7 @@ def write_swg_config(sim): @pytest.mark.vivado @pytest.mark.fpgadataflow def test_fpgadataflow_conv_dynamic(cfg): + do_synth = cfg["do_synth"] pad_mode = cfg["pad_mode"] depthwise = cfg["depthwise"] idims = cfg["idims"] @@ -292,7 +299,7 @@ def test_fpgadataflow_conv_dynamic(cfg): model = model.transform(GiveReadableTensorNames()) model = model.transform(PrepareIP("xc7z020clg400-1", 5)) model = model.transform(HLSSynthIP()) - model = model.transform(CreateStitchedIP("xc7z020clg400-1", 5)) + model = model.transform(CreateStitchedIP("xc7z020clg400-1", 5, vitis=do_synth)) model.set_metadata_prop("exec_mode", "rtlsim") # loop through experiment configurations From 06ab3eccd0d010c3d3cbe968accc6ec8a6181c2d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thomas=20B=2E=20Preu=C3=9Fer?= Date: Fri, 5 May 2023 13:50:58 +0100 Subject: [PATCH 132/665] Have IPI recompute AXI-lite address width according to user-defined memory layout. --- finn-rtllib/memstream/component.xml | 149 +++++++++++------- finn-rtllib/memstream/gui/memstream_v1_0.gtcl | 2 + finn-rtllib/memstream/xgui/memstream_v1_0.tcl | 27 +++- 3 files changed, 119 insertions(+), 59 deletions(-) create mode 100644 finn-rtllib/memstream/gui/memstream_v1_0.gtcl diff --git a/finn-rtllib/memstream/component.xml b/finn-rtllib/memstream/component.xml index 2705f61908..7b9eff239f 100644 --- a/finn-rtllib/memstream/component.xml +++ b/finn-rtllib/memstream/component.xml @@ -249,10 +249,6 @@ ASSOCIATED_BUSIF m_axis_0:s_axilite - - FREQ_TOLERANCE_HZ - -1 - @@ -288,6 +284,31 @@ + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + SystemVerilog + memstream_axi_wrapper + + + viewChecksum + c6fe43e9 + + + + + xilinx_implementation + Implementation + :vivado.xilinx.com:implementation + memstream_axi_wrapper + + + viewChecksum + cd434062 + + + xilinx_xpgui UI Layout @@ -298,7 +319,21 @@ viewChecksum - 91d40e29 + 32cad48d + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + abaee39b @@ -312,6 +347,7 @@ std_logic xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -324,6 +360,7 @@ std_logic xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -336,6 +373,7 @@ std_logic xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -348,6 +386,7 @@ std_logic xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -367,6 +406,7 @@ std_logic_vector xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -386,6 +426,7 @@ std_logic_vector xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -401,6 +442,7 @@ std_logic xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -413,6 +455,7 @@ std_logic xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -432,6 +475,7 @@ std_logic_vector xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -451,6 +495,7 @@ std_logic_vector xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -466,6 +511,7 @@ std_logic xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -481,6 +527,7 @@ std_logic xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -497,6 +544,7 @@ std_logic_vector xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -509,6 +557,7 @@ std_logic xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -521,6 +570,7 @@ std_logic xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -540,6 +590,7 @@ std_logic_vector xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -559,6 +610,7 @@ std_logic_vector xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -574,6 +626,7 @@ std_logic xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -589,6 +642,7 @@ std_logic xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -605,6 +659,7 @@ std_logic_vector xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -621,6 +676,7 @@ std_logic_vector xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -633,6 +689,7 @@ std_logic xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -648,6 +705,7 @@ std_logic xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -664,6 +722,7 @@ std_logic_vector xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -693,7 +752,7 @@ AXILITE_ADDR_WIDTH Axilite Addr Width - 11 + 11 @@ -730,10 +789,17 @@ xgui/memstream_v1_0.tcl tclSource - CHECKSUM_91d40e29 + CHECKSUM_32cad48d XGUI_VERSION_2 + + xilinx_utilityxitfiles_view_fileset + + gui/memstream_v1_0.gtcl + GTCL + + memstream @@ -741,25 +807,11 @@ DEPTH Depth 512 - - - - required - - - WIDTH Width 32 - - - - required - - - INIT_FILE @@ -771,6 +823,18 @@ Ram Style auto + + AXILITE_ADDR_WIDTH + Axilite Addr Width + 11 + + + + false + + + + Component_Name memstream_axi_wrapper_v1_0 @@ -778,57 +842,30 @@ - - virtex7 - qvirtex7 - versal - kintex7 - kintex7l - qkintex7 - qkintex7l - akintex7 - artix7 - artix7l - aartix7 - qartix7 - zynq - qzynq - azynq - spartan7 - aspartan7 - virtexu - zynquplus - virtexuplus - virtexuplusHBM - virtexuplus58g - kintexuplus - artixuplus - kintexu - /UserIP memstream - level_0 + level_1 package_project AMD - 2 + 1 user.org:user:memstream_axi_wrapper:1.0 - 2023-04-21T15:18:55Z + 2023-05-05T12:43:17Z 2022.1 - + - - - - + + + + diff --git a/finn-rtllib/memstream/gui/memstream_v1_0.gtcl b/finn-rtllib/memstream/gui/memstream_v1_0.gtcl new file mode 100644 index 0000000000..00fcee6045 --- /dev/null +++ b/finn-rtllib/memstream/gui/memstream_v1_0.gtcl @@ -0,0 +1,2 @@ +# This file is automatically written. Do not modify. +proc gen_USERPARAMETER_AXILITE_ADDR_WIDTH_VALUE {DEPTH WIDTH } {expr 2 + log($DEPTH*pow(2, log(($WIDTH+31)/32)/log(2)))/log(2)} diff --git a/finn-rtllib/memstream/xgui/memstream_v1_0.tcl b/finn-rtllib/memstream/xgui/memstream_v1_0.tcl index 4ad14af637..1943a50399 100644 --- a/finn-rtllib/memstream/xgui/memstream_v1_0.tcl +++ b/finn-rtllib/memstream/xgui/memstream_v1_0.tcl @@ -1,8 +1,13 @@ + +# Loading additional proc with user specified bodies to compute parameter values. +source [file join [file dirname [file dirname [info script]]] gui/memstream_v1_0.gtcl] + # Definitional proc to organize widgets for parameters. proc init_gui { IPINST } { ipgui::add_param $IPINST -name "Component_Name" #Adding Page set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "AXILITE_ADDR_WIDTH" -parent ${Page_0} ipgui::add_param $IPINST -name "DEPTH" -parent ${Page_0} ipgui::add_param $IPINST -name "INIT_FILE" -parent ${Page_0} ipgui::add_param $IPINST -name "RAM_STYLE" -parent ${Page_0} @@ -11,6 +16,22 @@ proc init_gui { IPINST } { } +proc update_PARAM_VALUE.AXILITE_ADDR_WIDTH { PARAM_VALUE.AXILITE_ADDR_WIDTH PARAM_VALUE.DEPTH PARAM_VALUE.WIDTH } { + # Procedure called to update AXILITE_ADDR_WIDTH when any of the dependent parameters in the arguments change + + set AXILITE_ADDR_WIDTH ${PARAM_VALUE.AXILITE_ADDR_WIDTH} + set DEPTH ${PARAM_VALUE.DEPTH} + set WIDTH ${PARAM_VALUE.WIDTH} + set values(DEPTH) [get_property value $DEPTH] + set values(WIDTH) [get_property value $WIDTH] + set_property value [gen_USERPARAMETER_AXILITE_ADDR_WIDTH_VALUE $values(DEPTH) $values(WIDTH)] $AXILITE_ADDR_WIDTH +} + +proc validate_PARAM_VALUE.AXILITE_ADDR_WIDTH { PARAM_VALUE.AXILITE_ADDR_WIDTH } { + # Procedure called to validate AXILITE_ADDR_WIDTH + return true +} + proc update_PARAM_VALUE.DEPTH { PARAM_VALUE.DEPTH } { # Procedure called to update DEPTH when any of the dependent parameters in the arguments change } @@ -68,8 +89,8 @@ proc update_MODELPARAM_VALUE.RAM_STYLE { MODELPARAM_VALUE.RAM_STYLE PARAM_VALUE. set_property value [get_property value ${PARAM_VALUE.RAM_STYLE}] ${MODELPARAM_VALUE.RAM_STYLE} } -proc update_MODELPARAM_VALUE.AXILITE_ADDR_WIDTH { MODELPARAM_VALUE.AXILITE_ADDR_WIDTH } { +proc update_MODELPARAM_VALUE.AXILITE_ADDR_WIDTH { MODELPARAM_VALUE.AXILITE_ADDR_WIDTH PARAM_VALUE.AXILITE_ADDR_WIDTH } { # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - # WARNING: There is no corresponding user parameter named "AXILITE_ADDR_WIDTH". Setting updated value from the model parameter. -set_property value 11 ${MODELPARAM_VALUE.AXILITE_ADDR_WIDTH} + set_property value [get_property value ${PARAM_VALUE.AXILITE_ADDR_WIDTH}] ${MODELPARAM_VALUE.AXILITE_ADDR_WIDTH} } + From 96277dba0bde072be12eeccc9b4186d50ed9f242 Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 5 May 2023 13:55:10 +0100 Subject: [PATCH 133/665] [rtllib] Linting of updated tcl script --- finn-rtllib/memstream/xgui/memstream_v1_0.tcl | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/finn-rtllib/memstream/xgui/memstream_v1_0.tcl b/finn-rtllib/memstream/xgui/memstream_v1_0.tcl index 1943a50399..60cb44c99e 100644 --- a/finn-rtllib/memstream/xgui/memstream_v1_0.tcl +++ b/finn-rtllib/memstream/xgui/memstream_v1_0.tcl @@ -18,7 +18,7 @@ proc init_gui { IPINST } { proc update_PARAM_VALUE.AXILITE_ADDR_WIDTH { PARAM_VALUE.AXILITE_ADDR_WIDTH PARAM_VALUE.DEPTH PARAM_VALUE.WIDTH } { # Procedure called to update AXILITE_ADDR_WIDTH when any of the dependent parameters in the arguments change - + set AXILITE_ADDR_WIDTH ${PARAM_VALUE.AXILITE_ADDR_WIDTH} set DEPTH ${PARAM_VALUE.DEPTH} set WIDTH ${PARAM_VALUE.WIDTH} @@ -93,4 +93,3 @@ proc update_MODELPARAM_VALUE.AXILITE_ADDR_WIDTH { MODELPARAM_VALUE.AXILITE_ADDR_ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value set_property value [get_property value ${PARAM_VALUE.AXILITE_ADDR_WIDTH}] ${MODELPARAM_VALUE.AXILITE_ADDR_WIDTH} } - From 0bb289ca20ab33989f434191fb3083a991f6244a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thomas=20B=2E=20Preu=C3=9Fer?= Date: Tue, 9 May 2023 11:26:40 +0100 Subject: [PATCH 134/665] Yet another fix of the address width expression for IP integrator. --- finn-rtllib/memstream/component.xml | 20 +++++++++++-------- finn-rtllib/memstream/gui/memstream_v1_0.gtcl | 2 +- 2 files changed, 13 insertions(+), 9 deletions(-) diff --git a/finn-rtllib/memstream/component.xml b/finn-rtllib/memstream/component.xml index 7b9eff239f..76f71cf878 100644 --- a/finn-rtllib/memstream/component.xml +++ b/finn-rtllib/memstream/component.xml @@ -249,6 +249,10 @@ ASSOCIATED_BUSIF m_axis_0:s_axilite + + FREQ_TOLERANCE_HZ + -1 + @@ -333,7 +337,7 @@ viewChecksum - abaee39b + 923e7b90 @@ -849,23 +853,23 @@ level_1 package_project AMD - 1 + 2 user.org:user:memstream_axi_wrapper:1.0 - 2023-05-05T12:43:17Z + 2023-05-09T10:21:56Z 2022.1 - + - - - - + + + + diff --git a/finn-rtllib/memstream/gui/memstream_v1_0.gtcl b/finn-rtllib/memstream/gui/memstream_v1_0.gtcl index 00fcee6045..271f9df453 100644 --- a/finn-rtllib/memstream/gui/memstream_v1_0.gtcl +++ b/finn-rtllib/memstream/gui/memstream_v1_0.gtcl @@ -1,2 +1,2 @@ # This file is automatically written. Do not modify. -proc gen_USERPARAMETER_AXILITE_ADDR_WIDTH_VALUE {DEPTH WIDTH } {expr 2 + log($DEPTH*pow(2, log(($WIDTH+31)/32)/log(2)))/log(2)} +proc gen_USERPARAMETER_AXILITE_ADDR_WIDTH_VALUE {DEPTH WIDTH } {expr 2 + ceil(log($DEPTH*pow(2, ceil(log(($WIDTH+31)/32)/log(2))))/log(2))} From 573c147065e40d1b334ec4d8f92c75380d97ead1 Mon Sep 17 00:00:00 2001 From: auphelia Date: Thu, 11 May 2023 15:25:13 +0100 Subject: [PATCH 135/665] [Jenkins] Update tool versions for CI --- docker/jenkins/Jenkinsfile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index e3e5b5f7f9..2954877c2a 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -5,8 +5,8 @@ node { checkout scm } withEnv([ - "FINN_XILINX_PATH=/proj/xbuilds/SWIP/2022.1_0420_0327/installs/lin64", - "FINN_XILINX_VERSION=2022.1", + "FINN_XILINX_PATH=/proj/xbuilds/SWIP/2022.2_1014_8888/installs/lin64", + "FINN_XILINX_VERSION=2022.2", "FINN_DOCKER_TAG=xilinx/finn:jenkins", "FINN_HOST_BUILD_DIR=/scratch/users/finn_ci", "PLATFORM_REPO_PATHS=/opt/xilinx/platforms" From d75e1fd2c4823458714c54e8bbedfb7bf36ef2d6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thomas=20B=2E=20Preu=C3=9Fer?= Date: Mon, 15 May 2023 17:42:27 +0100 Subject: [PATCH 136/665] Revised packaging with XCI cleanup and address map generation. --- .../fpgadataflow/create_stitched_ip.py | 95 +++++++++++++++---- 1 file changed, 79 insertions(+), 16 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/create_stitched_ip.py b/src/finn/transformation/fpgadataflow/create_stitched_ip.py index d1cb3c4af9..03212a9f15 100644 --- a/src/finn/transformation/fpgadataflow/create_stitched_ip.py +++ b/src/finn/transformation/fpgadataflow/create_stitched_ip.py @@ -385,6 +385,8 @@ def apply(self, model): "create_project %s %s -part %s" % (prjname, vivado_stitch_proj_dir, self.fpgapart) ) + # no warnings on long module names + tcl.append("set_msg_config -id {[BD 41-1753]} -suppress"); # add all the generated IP dirs to ip_repo_paths ip_dirs_str = " ".join(ip_dirs) tcl.append("set_property ip_repo_paths [%s] [current_project]" % ip_dirs_str) @@ -397,8 +399,7 @@ def apply(self, model): fclk_mhz = 1 / (self.clk_ns * 0.001) fclk_hz = fclk_mhz * 1000000 model.set_metadata_prop("clk_ns", str(self.clk_ns)) - tcl.append("set_property CONFIG.FREQ_HZ %f [get_bd_ports /ap_clk]" % fclk_hz) - tcl.append("regenerate_bd_layout") + tcl.append("set_property CONFIG.FREQ_HZ %d [get_bd_ports /ap_clk]" % round(fclk_hz)) tcl.append("validate_bd_design") tcl.append("save_bd_design") # create wrapper hdl (for rtlsim later on) @@ -450,6 +451,8 @@ def apply(self, model): ) % (vivado_stitch_proj_dir, block_vendor, block_library, block_name) ) + # Allow user to customize clock in deployment of stitched IP + tcl.append("set_property ipi_drc {ignore_freq_hz true} [ipx::current_core]"); # in some cases, the IP packager seems to infer an aperture of 64K or 4G, # preventing address assignment of the DDR_LOW and/or DDR_HIGH segments # the following is a hotfix to remove this aperture during IODMA packaging @@ -544,20 +547,80 @@ def apply(self, model): # add a rudimentary driver mdd to get correct ranges in xparameters.h later on example_data_dir = pk.resource_filename("finn.qnn-data", "mdd-data/") copytree(example_data_dir, vivado_stitch_proj_dir + "/data") - tcl.append("file copy -force data ip/") - tcl.append("ipx::add_file_group -type software_driver {} [ipx::current_core]") - tcl.append( - "set_property type mdd [ipx::add_file data/finn_design.mdd " - "[ipx::get_file_groups xilinx_softwaredriver -of_objects " - "[ipx::current_core]]]" - ) - tcl.append( - "set_property type tclSource [ipx::add_file data/finn_design.tcl " - "[ipx::get_file_groups xilinx_softwaredriver -of_objects " - "[ipx::current_core]]]" - ) - tcl.append("ipx::update_checksums [ipx::find_open_core %s]" % block_vlnv) - tcl.append("ipx::save_core [ipx::find_open_core %s]" % block_vlnv) + + ##### + # Core Cleanup Operations + tcl.append(""" +set core [ipx::current_core] + +# Add rudimentary driver +file copy -force data ip/ +set file_group [ipx::add_file_group -type software_driver {} $core] +set_property type mdd [ipx::add_file data/finn_design.mdd $file_group] +set_property type tclSource [ipx::add_file data/finn_design.tcl $file_group] + +# Remove all XCI references to subcores +set impl_files [ipx::get_file_groups xilinx_implementation -of $core] +foreach xci [ipx::get_files -of $impl_files {*.xci}] { + ipx::remove_file [get_property NAME $xci] $impl_files +} + +# Construct a single flat memory map for each AXI-lite interface port +foreach port [get_bd_intf_ports -filter {CONFIG.PROTOCOL==AXI4LITE}] { + set pin $port + set awidth "" + while { $awidth == "" } { + set pins [get_bd_intf_pins -of [get_bd_intf_nets -boundary_type lower -of $pin]] + set kill [lsearch $pins $pin] + if { $kill >= 0 } { set pins [lreplace $pins $kill $kill] } + if { [llength $pins] != 1 } { break } + set pin [lindex $pins 0] + set awidth [get_property CONFIG.ADDR_WIDTH $pin] + } + if { $awidth == "" } { + puts "CRITICAL WARNING: Unable to construct address map for $port." + } { + set range [expr 2**$awidth] + puts "INFO: Building address map for $port 0+:$range" + set name [get_property NAME $port] + set_property range $range [ipx::add_address_block Reg0 [ipx::add_memory_map $name $core]] + set_property slave_memory_map_ref $name [ipx::get_bus_interfaces $name -of $core] + } +} + +# Finalize and Save +ipx::update_checksums $core +ipx::save_core $core + +# Remove stale subcore references from component.xml +file rename -force ip/component.xml ip/component.bak +set ifile [open ip/component.bak r] +set ofile [open ip/component.xml w] +set buf [list] +set kill 0 +while { [eof $ifile] != 1 } { + gets $ifile line + if { [string match {**} $line] == 1 } { + foreach l $buf { puts $ofile $l } + set buf [list $line] + } elseif { [llength $buf] > 0 } { + lappend buf $line + + if { [string match {**} $line] == 1 } { + if { $kill == 0 } { foreach l $buf { puts $ofile $l } } + set buf [list] + set kill 0 + } elseif { [string match {**} $line] == 1 } { + set kill 1 + } + } else { + puts $ofile $line + } +} +close $ifile +close $ofile +"""); + # export list of used Verilog files (for rtlsim later on) tcl.append( "set all_v_files [get_files -filter {USED_IN_SYNTHESIS == 1 " From 5e940096e7299ac18675e8cb9e744250c8c4816f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thomas=20B=2E=20Preu=C3=9Fer?= Date: Tue, 16 May 2023 08:45:28 +0100 Subject: [PATCH 137/665] Linting. --- .../fpgadataflow/create_stitched_ip.py | 85 ++++++++++--------- 1 file changed, 45 insertions(+), 40 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/create_stitched_ip.py b/src/finn/transformation/fpgadataflow/create_stitched_ip.py index 03212a9f15..ef1afb95ca 100644 --- a/src/finn/transformation/fpgadataflow/create_stitched_ip.py +++ b/src/finn/transformation/fpgadataflow/create_stitched_ip.py @@ -386,7 +386,7 @@ def apply(self, model): % (prjname, vivado_stitch_proj_dir, self.fpgapart) ) # no warnings on long module names - tcl.append("set_msg_config -id {[BD 41-1753]} -suppress"); + tcl.append("set_msg_config -id {[BD 41-1753]} -suppress") # add all the generated IP dirs to ip_repo_paths ip_dirs_str = " ".join(ip_dirs) tcl.append("set_property ip_repo_paths [%s] [current_project]" % ip_dirs_str) @@ -399,7 +399,9 @@ def apply(self, model): fclk_mhz = 1 / (self.clk_ns * 0.001) fclk_hz = fclk_mhz * 1000000 model.set_metadata_prop("clk_ns", str(self.clk_ns)) - tcl.append("set_property CONFIG.FREQ_HZ %d [get_bd_ports /ap_clk]" % round(fclk_hz)) + tcl.append( + "set_property CONFIG.FREQ_HZ %d [get_bd_ports /ap_clk]" % round(fclk_hz) + ) tcl.append("validate_bd_design") tcl.append("save_bd_design") # create wrapper hdl (for rtlsim later on) @@ -452,7 +454,7 @@ def apply(self, model): % (vivado_stitch_proj_dir, block_vendor, block_library, block_name) ) # Allow user to customize clock in deployment of stitched IP - tcl.append("set_property ipi_drc {ignore_freq_hz true} [ipx::current_core]"); + tcl.append("set_property ipi_drc {ignore_freq_hz true} [ipx::current_core]") # in some cases, the IP packager seems to infer an aperture of 64K or 4G, # preventing address assignment of the DDR_LOW and/or DDR_HIGH segments # the following is a hotfix to remove this aperture during IODMA packaging @@ -550,7 +552,8 @@ def apply(self, model): ##### # Core Cleanup Operations - tcl.append(""" + tcl.append( + """ set core [ipx::current_core] # Add rudimentary driver @@ -567,25 +570,26 @@ def apply(self, model): # Construct a single flat memory map for each AXI-lite interface port foreach port [get_bd_intf_ports -filter {CONFIG.PROTOCOL==AXI4LITE}] { - set pin $port - set awidth "" - while { $awidth == "" } { - set pins [get_bd_intf_pins -of [get_bd_intf_nets -boundary_type lower -of $pin]] - set kill [lsearch $pins $pin] - if { $kill >= 0 } { set pins [lreplace $pins $kill $kill] } - if { [llength $pins] != 1 } { break } - set pin [lindex $pins 0] - set awidth [get_property CONFIG.ADDR_WIDTH $pin] - } - if { $awidth == "" } { - puts "CRITICAL WARNING: Unable to construct address map for $port." - } { - set range [expr 2**$awidth] - puts "INFO: Building address map for $port 0+:$range" - set name [get_property NAME $port] - set_property range $range [ipx::add_address_block Reg0 [ipx::add_memory_map $name $core]] - set_property slave_memory_map_ref $name [ipx::get_bus_interfaces $name -of $core] - } + set pin $port + set awidth "" + while { $awidth == "" } { + set pins [get_bd_intf_pins -of [get_bd_intf_nets -boundary_type lower -of $pin]] + set kill [lsearch $pins $pin] + if { $kill >= 0 } { set pins [lreplace $pins $kill $kill] } + if { [llength $pins] != 1 } { break } + set pin [lindex $pins 0] + set awidth [get_property CONFIG.ADDR_WIDTH $pin] + } + if { $awidth == "" } { + puts "CRITICAL WARNING: Unable to construct address map for $port." + } { + set range [expr 2**$awidth] + puts "INFO: Building address map for $port: 0+:$range" + set name [get_property NAME $port] + set addr_block [ipx::add_address_block Reg0 [ipx::add_memory_map $name $core]] + set_property range $range $addr_block + set_property slave_memory_map_ref $name [ipx::get_bus_interfaces $name -of $core] + } } # Finalize and Save @@ -599,27 +603,28 @@ def apply(self, model): set buf [list] set kill 0 while { [eof $ifile] != 1 } { - gets $ifile line - if { [string match {**} $line] == 1 } { - foreach l $buf { puts $ofile $l } - set buf [list $line] - } elseif { [llength $buf] > 0 } { - lappend buf $line + gets $ifile line + if { [string match {**} $line] == 1 } { + foreach l $buf { puts $ofile $l } + set buf [list $line] + } elseif { [llength $buf] > 0 } { + lappend buf $line - if { [string match {**} $line] == 1 } { - if { $kill == 0 } { foreach l $buf { puts $ofile $l } } - set buf [list] - set kill 0 - } elseif { [string match {**} $line] == 1 } { - set kill 1 - } - } else { - puts $ofile $line - } + if { [string match {**} $line] == 1 } { + if { $kill == 0 } { foreach l $buf { puts $ofile $l } } + set buf [list] + set kill 0 + } elseif { [string match {**} $line] == 1 } { + set kill 1 + } + } else { + puts $ofile $line + } } close $ifile close $ofile -"""); +""" + ) # export list of used Verilog files (for rtlsim later on) tcl.append( From f15c00d8e1dd94e0a2dc8724317f73b9aa29574c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thomas=20B=2E=20Preu=C3=9Fer?= Date: Tue, 16 May 2023 15:54:41 +0100 Subject: [PATCH 138/665] Polish interface attributes. Use all-lower-case finn library name like other modules. --- finn-rtllib/memstream/component.xml | 20 ++++++++----------- .../memstream/hdl/memstream_axi_wrapper.v | 5 +++-- finn-rtllib/memstream/xgui/memstream_v1_0.tcl | 2 -- .../fpgadataflow/matrixvectoractivation.py | 2 +- .../fpgadataflow/thresholding_batch.py | 2 +- .../fpgadataflow/vectorvectoractivation.py | 2 +- 6 files changed, 14 insertions(+), 19 deletions(-) diff --git a/finn-rtllib/memstream/component.xml b/finn-rtllib/memstream/component.xml index 76f71cf878..7965c9ae61 100644 --- a/finn-rtllib/memstream/component.xml +++ b/finn-rtllib/memstream/component.xml @@ -1,7 +1,7 @@ amd.com - FINN + finn memstream 1.0 @@ -219,10 +219,6 @@ POLARITY ACTIVE_LOW - - ASSOCIATED_BUSIF - m_axis_0 - @@ -284,7 +280,7 @@ viewChecksum - 4d23c8e5 + 4c694b82 @@ -785,7 +781,7 @@ hdl/memstream_axi_wrapper.v verilogSource - CHECKSUM_a3b36ea4 + CHECKSUM_1dcfa744 @@ -853,20 +849,20 @@ level_1 package_project AMD - 2 + 3 user.org:user:memstream_axi_wrapper:1.0 - 2023-05-09T10:21:56Z + 2023-05-16T13:58:39Z - 2022.1 - + 2022.2 + - + diff --git a/finn-rtllib/memstream/hdl/memstream_axi_wrapper.v b/finn-rtllib/memstream/hdl/memstream_axi_wrapper.v index 69d6b64dec..2d032ca159 100644 --- a/finn-rtllib/memstream/hdl/memstream_axi_wrapper.v +++ b/finn-rtllib/memstream/hdl/memstream_axi_wrapper.v @@ -40,9 +40,10 @@ module memstream_axi_wrapper #( parameter AXILITE_ADDR_WIDTH = $clog2(DEPTH * (2**$clog2((WIDTH+31)/32))) + 2 )( // Global Control - (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF m_axis_0" *) + (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF m_axis_0, ASSOCIATED_RESET ap_rst_n" *) + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *) input ap_clk, - (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF m_axis_0" *) + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_HIGH" *) input ap_rst_n, // AXI-lite Write diff --git a/finn-rtllib/memstream/xgui/memstream_v1_0.tcl b/finn-rtllib/memstream/xgui/memstream_v1_0.tcl index 60cb44c99e..e802d81c79 100644 --- a/finn-rtllib/memstream/xgui/memstream_v1_0.tcl +++ b/finn-rtllib/memstream/xgui/memstream_v1_0.tcl @@ -12,8 +12,6 @@ proc init_gui { IPINST } { ipgui::add_param $IPINST -name "INIT_FILE" -parent ${Page_0} ipgui::add_param $IPINST -name "RAM_STYLE" -parent ${Page_0} ipgui::add_param $IPINST -name "WIDTH" -parent ${Page_0} - - } proc update_PARAM_VALUE.AXILITE_ADDR_WIDTH { PARAM_VALUE.AXILITE_ADDR_WIDTH PARAM_VALUE.DEPTH PARAM_VALUE.WIDTH } { diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index fd41e1f9ad..899bce98d2 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -1358,7 +1358,7 @@ def code_generation_ipi(self): % (self.get_nodeattr("ip_vlnv"), node_name, node_name) ) # instantiate a streamer and connect it to the HLS IP - strm_vlnv = "amd.com:FINN:memstream:1.0" + strm_vlnv = "amd.com:finn:memstream:1.0" strm_inst = node_name + "_wstrm" cmd.append( "create_bd_cell -type ip -vlnv %s /%s/%s" diff --git a/src/finn/custom_op/fpgadataflow/thresholding_batch.py b/src/finn/custom_op/fpgadataflow/thresholding_batch.py index eab50c2cbc..12e635b3d6 100644 --- a/src/finn/custom_op/fpgadataflow/thresholding_batch.py +++ b/src/finn/custom_op/fpgadataflow/thresholding_batch.py @@ -824,7 +824,7 @@ def code_generation_ipi(self): % (self.get_nodeattr("ip_vlnv"), node_name, node_name) ) # instantiate a streamer and connect it to the HLS IP - strm_vlnv = "amd.com:FINN:memstream:1.0" + strm_vlnv = "amd.com:finn:memstream:1.0" strm_inst = node_name + "_wstrm" cmd.append( "create_bd_cell -type ip -vlnv %s /%s/%s" diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index a7aaa186df..ede572f1a4 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -1050,7 +1050,7 @@ def code_generation_ipi(self): % (self.get_nodeattr("ip_vlnv"), node_name, node_name) ) # instantiate a streamer and connect it to the HLS IP - strm_vlnv = "amd.com:FINN:memstream:1.0" + strm_vlnv = "amd.com:finn:memstream:1.0" strm_inst = node_name + "_wstrm" cmd.append( "create_bd_cell -type ip -vlnv %s /%s/%s" From ff78c24d2f993cf800e1ba73abac1ef0ac82423b Mon Sep 17 00:00:00 2001 From: Hugo LE BLEVEC Date: Tue, 16 May 2023 17:38:34 +0200 Subject: [PATCH 139/665] [PixelPadding] Created custom_op and unit test, which is passing both rtlsim and cppsim --- src/finn/custom_op/fpgadataflow/__init__.py | 2 + .../custom_op/fpgadataflow/fmpadding_pixel.py | 335 ++++++++++++++++++ .../test_fpgadataflow_pixelpadding.py | 169 +++++++++ 3 files changed, 506 insertions(+) create mode 100644 src/finn/custom_op/fpgadataflow/fmpadding_pixel.py create mode 100644 tests/fpgadataflow/test_fpgadataflow_pixelpadding.py diff --git a/src/finn/custom_op/fpgadataflow/__init__.py b/src/finn/custom_op/fpgadataflow/__init__.py index 56d4230a3a..bdcdcd9796 100644 --- a/src/finn/custom_op/fpgadataflow/__init__.py +++ b/src/finn/custom_op/fpgadataflow/__init__.py @@ -43,6 +43,7 @@ from finn.custom_op.fpgadataflow.duplicatestreams_batch import DuplicateStreams_Batch from finn.custom_op.fpgadataflow.eltwise import StreamingEltwise from finn.custom_op.fpgadataflow.fmpadding_batch import FMPadding_Batch +from finn.custom_op.fpgadataflow.fmpadding_pixel import FMPadding_Pixel from finn.custom_op.fpgadataflow.fmpadding_rtl import FMPadding_rtl from finn.custom_op.fpgadataflow.globalaccpool_batch import GlobalAccPool_Batch from finn.custom_op.fpgadataflow.iodma import IODMA @@ -79,6 +80,7 @@ custom_op["GlobalAccPool_Batch"] = GlobalAccPool_Batch custom_op["Pool_Batch"] = Pool_Batch custom_op["FMPadding_Batch"] = FMPadding_Batch +custom_op["FMPadding_Pixel"] = FMPadding_Pixel custom_op["Thresholding_Batch"] = Thresholding_Batch custom_op["AddStreams_Batch"] = AddStreams_Batch custom_op["LabelSelect_Batch"] = LabelSelect_Batch diff --git a/src/finn/custom_op/fpgadataflow/fmpadding_pixel.py b/src/finn/custom_op/fpgadataflow/fmpadding_pixel.py new file mode 100644 index 0000000000..caa7f199c4 --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/fmpadding_pixel.py @@ -0,0 +1,335 @@ +import numpy as np +import os +import warnings +from qonnx.core.datatype import DataType + +from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp +from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy + + +class FMPadding_Pixel(HLSCustomOp): + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) + + def get_nodeattr_types(self): + my_attrs = { + # spatial size of input images + "ImgDim": ("ints", True, []), + # stride to apply, can be non-square + "Stride": ("ints", True, []), + # number of channels in input image + "NumChannels": ("i", True, 0), + # SIMD Input parallelism + "SIMD": ("i", False, 1), + # FINN input datatype + "inputDataType": ("s", True, ""), + # shape describing input vecs per execution + "numInputVectors": ("i", False, 1), + } + my_attrs.update(super().get_nodeattr_types()) + return my_attrs + + def get_padded_odim(self): + "Return the padded spatial size of the output." + idim_h, idim_w = self.get_nodeattr("ImgDim") + stride_h, stride_w = self.get_nodeattr("Stride") + odim_h = idim_h + (idim_h - 1) * (stride_h - 1) + odim_w = idim_w + (idim_w - 1) * (stride_w - 1) + return [odim_h, odim_w] + + def get_exp_cycles(self): + odim_h, odim_w = self.get_padded_odim() + channels = self.get_nodeattr("NumChannels") + simd = self.get_nodeattr("SIMD") + exp_cycles = (channels / simd) * odim_h * odim_w + return int(exp_cycles) + + def get_normal_input_shape(self, ind=0): + idim_h, idim_w = self.get_nodeattr("ImgDim") + num_ch = self.get_nodeattr("NumChannels") + ishape = (1, idim_h, idim_w, num_ch) + return ishape + + def get_normal_output_shape(self, ind=0): + odim_h, odim_w = self.get_padded_odim() + num_ch = self.get_nodeattr("NumChannels") + oshape = (1, odim_h, odim_w, num_ch) + return oshape + + def get_folded_input_shape(self, ind=0): + normal_ishape = list(self.get_normal_input_shape()) + ifm_ch = self.get_nodeattr("NumChannels") + simd = self.get_nodeattr("SIMD") + assert ifm_ch % simd == 0, "SIMD must divide input channels" + fold = int(normal_ishape[-1] / simd) + folded_ishape = normal_ishape[:-1] + [fold, simd] + return tuple(folded_ishape) + + def get_folded_output_shape(self, ind=0): + normal_oshape = list(self.get_normal_output_shape()) + ifm_ch = self.get_nodeattr("NumChannels") + simd = self.get_nodeattr("SIMD") + assert ifm_ch % simd == 0, "SIMD must divide input channels" + fold = int(normal_oshape[-1] / simd) + folded_oshape = normal_oshape[:-1] + [fold, simd] + return tuple(folded_oshape) + + def make_shape_compatible_op(self, model): + exp_ishape = self.get_normal_input_shape() + oshape = self.get_normal_output_shape() + ishape = tuple(model.get_tensor_shape(self.onnx_node.input[0])) + assert ishape == exp_ishape, "Unexpect input shape for FMPadding_Pixel." + return super().make_const_shape_op(oshape) + + def infer_node_datatype(self, model): + node = self.onnx_node + idt = model.get_tensor_datatype(node.input[0]) + if idt != self.get_input_datatype(): + warn_str = "inputDataType changing for %s: %s -> %s " % ( + node.name, + str(self.get_input_datatype()), + str(idt), + ) + warnings.warn(warn_str) + self.set_nodeattr("inputDataType", idt.name) + model.set_tensor_datatype(node.output[0], idt) + + def verify_node(self): + pass + + def get_input_datatype(self, ind=0): + """Returns FINN DataType of input.""" + ret = DataType[self.get_nodeattr("inputDataType")] + # the hlslib op always pads with zeros, so ensure that the DataType + # is able to represent zeros + assert ret.allowed(0), "FMPadding_Pixel DataType must support zero" + return ret + + def get_output_datatype(self, ind=0): + """Returns FINN DataType of output. (Same as input datatype)""" + return self.get_input_datatype() + + def get_instream_width(self, ind=0): + ibits = self.get_input_datatype().bitwidth() + simd = self.get_nodeattr("SIMD") + return ibits * simd + + def get_outstream_width(self, ind=0): + obits = self.get_output_datatype().bitwidth() + simd = self.get_nodeattr("SIMD") + return obits * simd + + def get_number_output_values(self): + folded_oshape = self.get_folded_output_shape() + return np.prod(folded_oshape[:-1]) + + def global_includes(self): + self.code_gen_dict["$GLOBALS$"] = ['#include "streamtools.h"'] + + def defines(self, var): + odim_h, odim_w = self.get_padded_odim() + stride_h, stride_w = self.get_nodeattr("Stride") + is_square_img = odim_h == odim_w + is_square_stride = stride_h == stride_w + if is_square_img and is_square_stride: + self.code_gen_dict["$DEFINES$"] = [ + """ + #define OutputDim {}\n + #define Stride {}\n + #define NumChannels {}\n + #define SIMD {}\n + """.format( + odim_h, + stride_h, + self.get_nodeattr("NumChannels"), + self.get_nodeattr("SIMD"), + ) + ] + else: + self.code_gen_dict["$DEFINES$"] = [ + """ + #define OutputDim_x {}\n + #define OutputDim_y {}\n + #define Stride_x {}\n + #define Stride_y {}\n + #define NumChannels {}\n + #define SIMD {}\n + """.format( + odim_w, + odim_h, + stride_w, + stride_h, + self.get_nodeattr("NumChannels"), + self.get_nodeattr("SIMD"), + ) + ] + + def read_npy_data(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_input_datatype() + if dtype == DataType["BIPOLAR"]: + # use binary for bipolar storage + dtype = DataType["BINARY"] + elem_bits = dtype.bitwidth() + packed_bits = self.get_instream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "float" + npy_in = "%s/input_0.npy" % code_gen_dir + self.code_gen_dict["$READNPYDATA$"] = [] + self.code_gen_dict["$READNPYDATA$"].append( + 'npy2apintstream<%s, %s, %d, %s>("%s", in0);' + % (packed_hls_type, elem_hls_type, elem_bits, npy_type, npy_in) + ) + + def strm_decl(self): + self.code_gen_dict["$STREAMDECLARATIONS$"] = [] + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> in0 ("in0");'.format(self.get_instream_width()) + ) + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> out ("out");'.format(self.get_outstream_width()) + ) + + def docompute(self): + in_t = self.get_input_datatype().get_hls_datatype_str() + odim_h, odim_w = self.get_padded_odim() + stride_h, stride_w = self.get_nodeattr("Stride") + is_square_img = odim_h == odim_w + is_square_stride = stride_h == stride_w + + if is_square_img and is_square_stride: + hls_call = "FMPadding_Pixel" + self.code_gen_dict["$DOCOMPUTE$"] = [ + """{} (in0, out);""".format( + hls_call, in_t + ) + ] + else: + hls_call = "FMPadding_Pixel_Nonsquare" + self.code_gen_dict["$DOCOMPUTE$"] = [ + """{} (in0, out);""".format( + hls_call, in_t + ) + ] + + def dataoutstrm(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_output_datatype() + if dtype == DataType["BIPOLAR"]: + # use binary for bipolar storage + dtype = DataType["BINARY"] + elem_bits = dtype.bitwidth() + packed_bits = self.get_outstream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "float" + npy_out = "%s/output.npy" % code_gen_dir + oshape = self.get_folded_output_shape() + oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") + + self.code_gen_dict["$DATAOUTSTREAM$"] = [ + 'apintstream2npy<%s, %s, %d, %s>(out, %s, "%s");' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + oshape_cpp_str, + npy_out, + ) + ] + + def save_as_npy(self): + self.code_gen_dict["$SAVEASCNPY$"] = [] + + def blackboxfunction(self): + packed_bits = self.get_instream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ + "void %s(hls::stream<%s > &in0, hls::stream<%s > &out)" + % (self.onnx_node.name, packed_hls_type, packed_hls_type) + ] + + def pragmas(self): + self.code_gen_dict["$PRAGMAS$"] = [ + "#pragma HLS INTERFACE axis port=in0 name=in0_" + self.hls_sname() + ] + self.code_gen_dict["$PRAGMAS$"].append( + "#pragma HLS INTERFACE axis port=out name=out_" + self.hls_sname() + ) + self.code_gen_dict["$PRAGMAS$"].append( + "#pragma HLS INTERFACE ap_ctrl_none port=return" + ) + + def execute_node(self, context, graph): + mode = self.get_nodeattr("exec_mode") + node = self.onnx_node + exp_ishape = self.get_normal_input_shape() + exp_oshape = self.get_normal_output_shape() + folded_ishape = self.get_folded_input_shape() + + if mode == "cppsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + elif mode == "rtlsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + + inp = context[node.input[0]] + assert str(inp.dtype) == "float32", "Input datatype is not float32" + assert ( + inp.shape == exp_ishape + ), """Input shape doesn't + match expected shape (1, ImgDim_h, ImgDim_w, NumChannels).""" + export_idt = self.get_input_datatype() + + reshaped_input = inp.reshape(folded_ishape) + np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input) + + if mode == "cppsim": + # execute the precompiled model + super().exec_precompiled_singlenode_model() + # load output npy file + super().npy_to_dynamic_output(context) + assert ( + context[node.output[0]].shape == exp_oshape + ), "cppsim did not produce expected output shape" + elif mode == "rtlsim": + sim = self.get_rtlsim() + nbits = self.get_instream_width() + rtlsim_inp = npy_to_rtlsim_input( + "{}/input_0.npy".format(code_gen_dir), export_idt, nbits + ) + super().reset_rtlsim(sim) + super().toggle_clk(sim) + rtlsim_output = self.rtlsim(sim, rtlsim_inp) + odt = export_idt + target_bits = odt.bitwidth() + packed_bits = self.get_outstream_width() + out_npy_path = "{}/output.npy".format(code_gen_dir) + out_shape = self.get_folded_output_shape() + rtlsim_output_to_npy( + rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits + ) + # load and reshape output + output = np.load(out_npy_path) + output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) + context[node.output[0]] = output + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + assert ( + context[node.output[0]].shape == exp_oshape + ), """Output shape doesn't match expected shape + (1, OutputDim_H, OutputDim_W, NumChannels).""" diff --git a/tests/fpgadataflow/test_fpgadataflow_pixelpadding.py b/tests/fpgadataflow/test_fpgadataflow_pixelpadding.py new file mode 100644 index 0000000000..95f102e442 --- /dev/null +++ b/tests/fpgadataflow/test_fpgadataflow_pixelpadding.py @@ -0,0 +1,169 @@ +# Copyright (c) 2020, Xilinx +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import pytest + +import numpy as np +import os +from onnx import TensorProto, helper +from qonnx.core.datatype import DataType +from qonnx.core.modelwrapper import ModelWrapper +from qonnx.custom_op.registry import getCustomOp +from qonnx.transformation.general import GiveUniqueNodeNames +from qonnx.transformation.infer_shapes import InferShapes +from qonnx.util.basic import gen_finn_dt_tensor, qonnx_make_model + +import finn.core.onnx_exec as oxe +from finn.analysis.fpgadataflow.exp_cycles_per_layer import exp_cycles_per_layer +from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim +from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP +from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim +from finn.transformation.fpgadataflow.prepare_ip import PrepareIP +from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim +from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.util.basic import pynq_part_map + +test_pynq_board = os.getenv("PYNQ_BOARD", default="Pynq-Z1") +test_fpga_part = pynq_part_map[test_pynq_board] +target_clk_ns = 10 + + +def make_single_pixelpadding_modelwrapper(optype, idim, stride, num_ch, simd, idt): + idim_h, idim_w = idim + stride_h, stride_w = stride + + odim_h = idim_h + (idim_h - 1) * (stride_h - 1) + odim_w = idim_w + (idim_w - 1) * (stride_w - 1) + + assert ( + odim_h > idim_h or odim_w > idim_w + ), "Output dim should be greater than input dim" + + inp = helper.make_tensor_value_info( + "inp", TensorProto.FLOAT, [1, idim_h, idim_w, num_ch] + ) + outp = helper.make_tensor_value_info( + "outp", TensorProto.FLOAT, [1, odim_h, odim_w, num_ch] + ) + + FMPadding_Pixel = helper.make_node( + optype, + ["inp"], + ["outp"], + domain="finn.custom_op.fpgadataflow", + backend="fpgadataflow", + ImgDim=idim, + Stride=stride, + NumChannels=num_ch, + inputDataType=str(idt.name), + numInputVectors=1, + SIMD=simd, + ) + + graph = helper.make_graph( + nodes=[FMPadding_Pixel], name="pixelpadding_graph", inputs=[inp], outputs=[outp] + ) + + model = qonnx_make_model(graph, producer_name="pixelpadding-model") + model = ModelWrapper(model) + + model.set_tensor_datatype("inp", idt) + model.set_tensor_datatype("outp", idt) + + return model + + +# input image dimension +@pytest.mark.parametrize("idim", [[8, 8], [10, 8]]) +# number of rows and number of cols to add +@pytest.mark.parametrize("stride", [[2, 2], [2, 3]]) +# number of channels +@pytest.mark.parametrize("num_ch", [2, 4]) +# Input parallelism +@pytest.mark.parametrize("simd", [1, 2]) +# FINN input datatype +@pytest.mark.parametrize("idt", [DataType["INT2"], DataType["INT4"]]) +# execution mode +@pytest.mark.parametrize("mode", ["cppsim", "rtlsim"]) +# # implementation style +# @pytest.mark.parametrize("impl_style", ["rtl", "hls"]) +@pytest.mark.fpgadataflow +@pytest.mark.slow +@pytest.mark.vivado +def test_fpgadataflow_pixelpadding(idim, stride, num_ch, simd, idt, mode): + # if impl_style == "rtl" and mode == "cppsim": + # pytest.skip("rtl implstyle has no cppsim, skipping") + if num_ch % simd != 0: + pytest.skip(" num_ch % simd != 0, skipping") + + idim_h, idim_w = idim + stride_h, stride_w = stride + + # generate input data + x = gen_finn_dt_tensor(idt, [1, idim_h, idim_w, num_ch]) + input_dict = {"inp": x} + odim_h = idim_h + (idim_h - 1) * (stride_h - 1) + odim_w = idim_w + (idim_w - 1) * (stride_w - 1) + + optype = "FMPadding_Pixel" + + model = make_single_pixelpadding_modelwrapper( + optype, idim, stride, num_ch, simd, idt + ) + model = model.transform(InferShapes()) + model = model.transform(SetExecMode(mode)) + model = model.transform(GiveUniqueNodeNames()) + if mode == "cppsim": + model = model.transform(PrepareCppSim()) + model = model.transform(CompileCppSim()) + elif mode == "rtlsim": + model = model.transform(PrepareIP(test_fpga_part, target_clk_ns)) + model = model.transform(HLSSynthIP()) + model = model.transform(PrepareRTLSim()) + + y_produced = oxe.execute_onnx(model, input_dict)["outp"] + expected_oshape = (1, odim_h, odim_w, num_ch) + assert y_produced.shape == expected_oshape + + y_expected = np.zeros(expected_oshape) + for i in range(x.shape[1]): + for j in range(x.shape[2]): + ih = i * stride_h + iw = j * stride_w + y_expected[0, ih, iw, :] = x[0, i, j, :] + + assert (y_produced == y_expected).all() + + if mode == "rtlsim": + node = model.get_nodes_by_op_type(optype)[0] + inst = getCustomOp(node) + cycles_rtlsim = inst.get_nodeattr("cycles_rtlsim") + exp_cycles_dict = model.analysis(exp_cycles_per_layer) + exp_cycles = exp_cycles_dict[node.name] + assert np.isclose(exp_cycles, cycles_rtlsim, atol=10) + assert exp_cycles != 0 From e5f4a2c5b54e058e52c42eeb9f0af456e34da40f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thomas=20B=2E=20Preu=C3=9Fer?= Date: Tue, 23 May 2023 21:02:02 +0100 Subject: [PATCH 140/665] Add missing simulation fileset. --- finn-rtllib/memstream/component.xml | 40 +++++++++++++++++++++++++---- 1 file changed, 35 insertions(+), 5 deletions(-) diff --git a/finn-rtllib/memstream/component.xml b/finn-rtllib/memstream/component.xml index 7965c9ae61..8ee591e187 100644 --- a/finn-rtllib/memstream/component.xml +++ b/finn-rtllib/memstream/component.xml @@ -290,10 +290,13 @@ :vivado.xilinx.com:simulation SystemVerilog memstream_axi_wrapper + + xilinx_anylanguagebehavioralsimulation_view_fileset + viewChecksum - c6fe43e9 + 4728d76a @@ -319,7 +322,7 @@ viewChecksum - 32cad48d + 6c92393d @@ -784,6 +787,33 @@ CHECKSUM_1dcfa744 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + hdl/memstream.sv + systemVerilogSource + USED_IN_ipstatic + xil_defaultlib + + + hdl/memstream_axi.sv + systemVerilogSource + USED_IN_ipstatic + xil_defaultlib + + + hdl/axilite_if.v + verilogSource + USED_IN_ipstatic + xil_defaultlib + + + hdl/memstream_axi_wrapper.v + verilogSource + USED_IN_ipstatic + xil_defaultlib + + xilinx_xpgui_view_fileset @@ -849,11 +879,11 @@ level_1 package_project AMD - 3 + 4 user.org:user:memstream_axi_wrapper:1.0 - 2023-05-16T13:58:39Z + 2023-05-23T19:59:11Z @@ -862,7 +892,7 @@ 2022.2 - + From 30a0058fb50b5e2525687a28c2df7cae848ba3e0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thomas=20B=2E=20Preu=C3=9Fer?= Date: Wed, 24 May 2023 07:40:59 +0100 Subject: [PATCH 141/665] Revised control interface attributes. --- finn-rtllib/axi_info/component.xml | 27 ++++++--- finn-rtllib/axi_info/hdl/axi_info_top.sv | 3 + finn-rtllib/memstream/component.xml | 12 ++-- .../memstream/hdl/memstream_axi_wrapper.v | 2 +- finn-rtllib/swg/swg_template_wrapper.v | 55 +++++++++---------- .../swg/swg_template_wrapper_dynamic.v | 45 ++++++++++++--- 6 files changed, 90 insertions(+), 54 deletions(-) diff --git a/finn-rtllib/axi_info/component.xml b/finn-rtllib/axi_info/component.xml index d22637534f..c7632e2915 100644 --- a/finn-rtllib/axi_info/component.xml +++ b/finn-rtllib/axi_info/component.xml @@ -197,6 +197,10 @@ ASSOCIATED_BUSIF s_axi + + FREQ_TOLERANCE_HZ + -1 + @@ -228,7 +232,7 @@ viewChecksum - 7d682dfc + c9da9874 @@ -244,7 +248,7 @@ viewChecksum - 7d682dfc + c9da9874 @@ -258,7 +262,7 @@ viewChecksum - e11f9727 + 1e654f67 @@ -607,7 +611,7 @@ hdl/axi_info_top.sv systemVerilogSource - CHECKSUM_ec9ff0da + CHECKSUM_db6ccc10 @@ -692,17 +696,22 @@ axi_info_top_v1_0 package_project - 5 - 2022-05-30T14:16:13Z + 6 + 2023-05-24T06:36:33Z - 2022.1 - + 2022.2 + - + + + + + + diff --git a/finn-rtllib/axi_info/hdl/axi_info_top.sv b/finn-rtllib/axi_info/hdl/axi_info_top.sv index ab2cfc8bed..74aebe3ec7 100644 --- a/finn-rtllib/axi_info/hdl/axi_info_top.sv +++ b/finn-rtllib/axi_info/hdl/axi_info_top.sv @@ -38,7 +38,10 @@ module axi_info_top #( bit [31:0] CHECKSUM_COUNT )( //- Global Control ------------------ + (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET ap_rst_n" *) + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *) input logic ap_clk, + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) input logic ap_rst_n, //- AXI Lite ------------------------ diff --git a/finn-rtllib/memstream/component.xml b/finn-rtllib/memstream/component.xml index 8ee591e187..722da1d803 100644 --- a/finn-rtllib/memstream/component.xml +++ b/finn-rtllib/memstream/component.xml @@ -280,7 +280,7 @@ viewChecksum - 4c694b82 + 04464096 @@ -296,7 +296,7 @@ viewChecksum - 4728d76a + 9e058959 @@ -784,7 +784,7 @@ hdl/memstream_axi_wrapper.v verilogSource - CHECKSUM_1dcfa744 + CHECKSUM_7caabca7 @@ -879,11 +879,11 @@ level_1 package_project AMD - 4 + 5 user.org:user:memstream_axi_wrapper:1.0 - 2023-05-23T19:59:11Z + 2023-05-24T06:34:57Z @@ -892,7 +892,7 @@ 2022.2 - + diff --git a/finn-rtllib/memstream/hdl/memstream_axi_wrapper.v b/finn-rtllib/memstream/hdl/memstream_axi_wrapper.v index 2d032ca159..13f5c82d6e 100644 --- a/finn-rtllib/memstream/hdl/memstream_axi_wrapper.v +++ b/finn-rtllib/memstream/hdl/memstream_axi_wrapper.v @@ -43,7 +43,7 @@ module memstream_axi_wrapper #( (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF m_axis_0, ASSOCIATED_RESET ap_rst_n" *) (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *) input ap_clk, - (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_HIGH" *) + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) input ap_rst_n, // AXI-lite Write diff --git a/finn-rtllib/swg/swg_template_wrapper.v b/finn-rtllib/swg/swg_template_wrapper.v index 0cc3579a25..11fa0a88cb 100644 --- a/finn-rtllib/swg/swg_template_wrapper.v +++ b/finn-rtllib/swg/swg_template_wrapper.v @@ -28,19 +28,19 @@ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ -`timescale 1 ns / 1 ps module $TOP_MODULE_NAME$ ( -(* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out_V" *) -input ap_clk, -(* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out_V" *) -input ap_rst_n, -input [BUF_IN_WIDTH-1:0] in0_V_TDATA, -input in0_V_TVALID, -output in0_V_TREADY, -output [BUF_OUT_WIDTH-1:0] out_V_TDATA, -output out_V_TVALID, -input out_V_TREADY + (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out_V, ASSOCIATED_RESET ap_rst_n" *) + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *) + input ap_clk, + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) + input ap_rst_n, + input [BUF_IN_WIDTH-1:0] in0_V_TDATA, + input in0_V_TVALID, + output in0_V_TREADY, + output [BUF_OUT_WIDTH-1:0] out_V_TDATA, + output out_V_TVALID, + input out_V_TREADY ); // top-level parameters (set via code-generation) @@ -53,23 +53,20 @@ parameter MMV_OUT = $MMV_OUT$; parameter BUF_IN_WIDTH = BIT_WIDTH * SIMD * MMV_IN; parameter BUF_OUT_WIDTH = BIT_WIDTH * SIMD * MMV_OUT; -$TOP_MODULE_NAME$_impl -#( - .BIT_WIDTH(BIT_WIDTH), - .SIMD(SIMD), - .MMV_IN(MMV_IN), - .MMV_OUT(MMV_OUT) -) -impl -( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .in0_V_V_TDATA(in0_V_TDATA), - .in0_V_V_TVALID(in0_V_TVALID), - .in0_V_V_TREADY(in0_V_TREADY), - .out_V_V_TDATA(out_V_TDATA), - .out_V_V_TVALID(out_V_TVALID), - .out_V_V_TREADY(out_V_TREADY) +$TOP_MODULE_NAME$_impl #( + .BIT_WIDTH(BIT_WIDTH), + .SIMD(SIMD), + .MMV_IN(MMV_IN), + .MMV_OUT(MMV_OUT) +) impl ( + .ap_clk(ap_clk), + .ap_rst_n(ap_rst_n), + .in0_V_V_TDATA(in0_V_TDATA), + .in0_V_V_TVALID(in0_V_TVALID), + .in0_V_V_TREADY(in0_V_TREADY), + .out_V_V_TDATA(out_V_TDATA), + .out_V_V_TVALID(out_V_TVALID), + .out_V_V_TREADY(out_V_TREADY) ); -endmodule //TOP_MODULE_NAME +endmodule : $TOP_MODULE_NAME$ diff --git a/finn-rtllib/swg/swg_template_wrapper_dynamic.v b/finn-rtllib/swg/swg_template_wrapper_dynamic.v index ca870ace11..5c09e7c1b4 100644 --- a/finn-rtllib/swg/swg_template_wrapper_dynamic.v +++ b/finn-rtllib/swg/swg_template_wrapper_dynamic.v @@ -1,4 +1,33 @@ -`timescale 1 ns / 1 ps +/****************************************************************************** + * Copyright (C) 2022, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *****************************************************************************/ module $TOP_MODULE_NAME$ #( // top-level parameters (set via code-generation) @@ -18,9 +47,10 @@ module $TOP_MODULE_NAME$ #( parameter integer C_s_axilite_ADDR_WIDTH = 6 ) ( - (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out_V:s_axilite" *) + (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out_V:s_axilite, ASSOCIATED_RESET ap_rst_n" *) + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *) input ap_clk, - (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out_V:s_axilite" *) + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) input ap_rst_n, input [BUF_IN_WIDTH-1:0] in0_V_TDATA, input in0_V_TVALID, @@ -113,17 +143,14 @@ $TOP_MODULE_NAME$_axilite # ( .cfg_reg15(cfg_last_write) ); -$TOP_MODULE_NAME$_impl -#( +$TOP_MODULE_NAME$_impl #( .BIT_WIDTH(BIT_WIDTH), .SIMD(SIMD), .MMV_IN(MMV_IN), .MMV_OUT(MMV_OUT), .CNTR_BITWIDTH(CNTR_BITWIDTH), .INCR_BITWIDTH(INCR_BITWIDTH) -) -impl -( +) impl ( .ap_clk(ap_clk), .ap_rst_n(ap_rst_n), .in0_V_V_TDATA(in0_V_TDATA), @@ -151,4 +178,4 @@ impl .cfg_last_write(cfg_last_write) ); -endmodule //TOP_MODULE_NAME +endmodule : $TOP_MODULE_NAME$ From 9f6d7b2700e0364c6a4a6a36bbfb234281df03f9 Mon Sep 17 00:00:00 2001 From: Felix Jentzsch Date: Wed, 24 May 2023 10:03:04 +0200 Subject: [PATCH 142/665] Pin IPython dependency --- requirements.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/requirements.txt b/requirements.txt index 3cf829a171..5bb4f4abc9 100644 --- a/requirements.txt +++ b/requirements.txt @@ -18,3 +18,4 @@ sphinx_rtd_theme==0.5.0 toposort==1.5 vcdvcd==1.0.5 wget==3.2 +ipython==8.12.2 From 4443eeb823a0bbc35ec016d1a92574264f3981fe Mon Sep 17 00:00:00 2001 From: Felix Jentzsch Date: Thu, 25 May 2023 12:47:27 +0200 Subject: [PATCH 143/665] Update base image to Ubuntu 22.04 --- docker/Dockerfile.finn | 31 +++++++++++++++++++------------ docker/finn_entrypoint.sh | 5 +++-- fetch-repos.sh | 4 ++-- requirements.txt | 14 ++++++-------- run-docker.sh | 5 ++++- 5 files changed, 34 insertions(+), 25 deletions(-) diff --git a/docker/Dockerfile.finn b/docker/Dockerfile.finn index f823d3c42b..d69ccc9725 100644 --- a/docker/Dockerfile.finn +++ b/docker/Dockerfile.finn @@ -26,10 +26,10 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -FROM pytorch/pytorch:1.7.1-cuda11.0-cudnn8-runtime +FROM ubuntu:jammy-20230126 LABEL maintainer="Yaman Umuroglu " -ARG XRT_DEB_VERSION="xrt_202210.2.13.466_18.04-amd64-xrt" +ARG XRT_DEB_VERSION="xrt_202220.2.14.354_22.04-amd64-xrt" WORKDIR /workspace @@ -57,12 +57,15 @@ RUN apt-get update && \ unzip \ zip \ locales \ - lsb-core + lsb-core \ + python3 \ + python-is-python3 \ + python3-pip RUN echo "StrictHostKeyChecking no" >> /etc/ssh/ssh_config RUN locale-gen "en_US.UTF-8" # install Verilator from source to get the right version -RUN apt-get install -y git perl python3 make autoconf g++ flex bison ccache libgoogle-perftools-dev numactl perl-doc libfl2 libfl-dev zlibc zlib1g zlib1g-dev +RUN apt-get install -y git perl make autoconf g++ flex bison ccache libgoogle-perftools-dev numactl perl-doc libfl2 libfl-dev zlib1g zlib1g-dev RUN git clone https://github.com/verilator/verilator RUN cd verilator && \ git checkout v4.224 && \ @@ -81,19 +84,23 @@ RUN rm /tmp/$XRT_DEB_VERSION.deb COPY requirements.txt . RUN pip install -r requirements.txt RUN rm requirements.txt + +# install PyTorch +RUN pip install torch==1.13.1 torchvision==0.14.1 torchaudio==0.13.1 --extra-index-url https://download.pytorch.org/whl/cu116 + # extra Python package dependencies (for testing and interaction) -RUN pip install pygments==2.4.1 -RUN pip install ipykernel==5.5.5 +RUN pip install pygments==2.14.0 +RUN pip install ipykernel==6.21.2 RUN pip install jupyter==1.0.0 --ignore-installed RUN pip install markupsafe==2.0.1 -RUN pip install matplotlib==3.3.1 --ignore-installed +RUN pip install matplotlib==3.7.0 --ignore-installed RUN pip install pytest-dependency==0.5.1 -RUN pip install pytest-xdist[setproctitle]==2.4.0 -RUN pip install pytest-parallel==0.1.0 +RUN pip install pytest-xdist[setproctitle]==3.2.0 +RUN pip install pytest-parallel==0.1.1 RUN pip install "netron>=5.0.0" -RUN pip install pandas==1.1.5 -RUN pip install scikit-learn==0.24.1 -RUN pip install tqdm==4.31.1 +RUN pip install pandas==1.5.3 +RUN pip install scikit-learn==1.2.1 +RUN pip install tqdm==4.64.1 RUN pip install -e git+https://github.com/fbcotter/dataset_loading.git@0.0.4#egg=dataset_loading # extra dependencies from other FINN deps diff --git a/docker/finn_entrypoint.sh b/docker/finn_entrypoint.sh index b5c702111a..4e0266ca6b 100644 --- a/docker/finn_entrypoint.sh +++ b/docker/finn_entrypoint.sh @@ -54,8 +54,9 @@ recho () { echo -e "${RED}ERROR: $1${NC}" } -# qonnx -pip install --user -e ${FINN_ROOT}/deps/qonnx +# qonnx (using workaround for https://github.com/pypa/pip/issues/7953) +# to be fixed in future Ubuntu versions (https://bugs.launchpad.net/ubuntu/+source/setuptools/+bug/1994016) +pip install --no-build-isolation --no-warn-script-location -e ${FINN_ROOT}/deps/qonnx # finn-experimental pip install --user -e ${FINN_ROOT}/deps/finn-experimental # brevitas diff --git a/fetch-repos.sh b/fetch-repos.sh index e039ca9144..189693dd17 100755 --- a/fetch-repos.sh +++ b/fetch-repos.sh @@ -27,7 +27,7 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -QONNX_COMMIT="20a34289cf2297d2b2bbbe75d6ac152ece86e3b4" +QONNX_COMMIT="0c980ef410c7c99b33c5b96486233f5a723ca1bc" FINN_EXP_COMMIT="0aa7e1c44b20cf085b6fe42cff360f0a832afd2c" BREVITAS_COMMIT="c65f9c13dc124971f14739349531bbcda5c2a4aa" PYVERILATOR_COMMIT="766e457465f5c0dd315490d7b9cc5d74f9a76f4f" @@ -39,7 +39,7 @@ XIL_BDF_COMMIT="8cf4bb674a919ac34e3d99d8d71a9e60af93d14e" KV260_BDF_COMMIT="98e0d3efc901f0b974006bc4370c2a7ad8856c79" EXP_BOARD_FILES_MD5="30eecc497c31050bd46d10ea20eba232" -QONNX_URL="https://github.com/fastmachinelearning/qonnx.git" +QONNX_URL="https://github.com/iksnagreb/qonnx.git" FINN_EXP_URL="https://github.com/Xilinx/finn-experimental.git" BREVITAS_URL="https://github.com/Xilinx/brevitas.git" PYVERILATOR_URL="https://github.com/maltanar/pyverilator.git" diff --git a/requirements.txt b/requirements.txt index 3cf829a171..a9e691fea2 100644 --- a/requirements.txt +++ b/requirements.txt @@ -2,19 +2,17 @@ bitstring==3.1.7 clize==4.1.1 dataclasses-json==0.5.7 gspread==3.6.0 -numpy==1.22.0 +numpy==1.24.1 onnx==1.13.0 onnxoptimizer -onnxruntime==1.11.1 -pre-commit==2.9.2 +onnxruntime==1.15.0 +pre-commit==3.3.2 protobuf==3.20.3 psutil==5.9.4 -pyscaffold==3.2.1 -scipy==1.5.2 +pyscaffold==4.4 +scipy==1.10.1 setupext-janitor>=1.1.2 sigtools==2.0.3 -sphinx==5.0.2 -sphinx_rtd_theme==0.5.0 -toposort==1.5 +toposort==1.7.0 vcdvcd==1.0.5 wget==3.2 diff --git a/run-docker.sh b/run-docker.sh index 381be35293..c24dcec724 100755 --- a/run-docker.sh +++ b/run-docker.sh @@ -86,7 +86,7 @@ SCRIPTPATH=$(dirname "$SCRIPT") : ${ALVEO_BOARD="U250"} : ${ALVEO_TARGET_DIR="/tmp"} : ${PLATFORM_REPO_PATHS="/opt/xilinx/platforms"} -: ${XRT_DEB_VERSION="xrt_202210.2.13.466_18.04-amd64-xrt"} +: ${XRT_DEB_VERSION="xrt_202220.2.14.354_22.04-amd64-xrt"} : ${FINN_HOST_BUILD_DIR="/tmp/$DOCKER_INST_NAME"} : ${FINN_DOCKER_TAG="xilinx/finn:$(git describe --always --tags --dirty).$XRT_DEB_VERSION"} : ${FINN_DOCKER_PREBUILT="0"} @@ -201,6 +201,9 @@ DOCKER_EXEC+="-e PYNQ_PASSWORD=$PYNQ_PASSWORD " DOCKER_EXEC+="-e PYNQ_TARGET_DIR=$PYNQ_TARGET_DIR " DOCKER_EXEC+="-e OHMYXILINX=$OHMYXILINX " DOCKER_EXEC+="-e NUM_DEFAULT_WORKERS=$NUM_DEFAULT_WORKERS " +# Workaround for FlexLM issue, see: +# https://community.flexera.com/t5/InstallAnywhere-Forum/Issues-when-running-Xilinx-tools-or-Other-vendor-tools-in-docker/m-p/245820#M10647 +DOCKER_EXEC+="-e LD_PRELOAD=/lib/x86_64-linux-gnu/libudev.so.1 " if [ "$FINN_DOCKER_RUN_AS_ROOT" = "0" ];then DOCKER_EXEC+="-v /etc/group:/etc/group:ro " DOCKER_EXEC+="-v /etc/passwd:/etc/passwd:ro " From a2a0ffedfad96a64fe102d7c9d3c4c01a3288121 Mon Sep 17 00:00:00 2001 From: Felix Jentzsch Date: Thu, 25 May 2023 17:33:52 +0200 Subject: [PATCH 144/665] Update pre-commit config --- .pre-commit-config.yaml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index 126a4ac4b2..42a18b2737 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -29,11 +29,11 @@ exclude: '^docs/conf.py' default_language_version: - python: python3.8 + python: python3.10 repos: - repo: https://github.com/pre-commit/pre-commit-hooks - rev: v4.2.0 + rev: v4.4.0 hooks: - id: trailing-whitespace exclude: '\.dat$' @@ -56,13 +56,13 @@ repos: - id: isort - repo: https://github.com/psf/black - rev: 22.3.0 + rev: 23.3.0 hooks: - id: black language_version: python3 - repo: https://github.com/PyCQA/flake8 - rev: 3.9.2 + rev: 6.0.0 hooks: - id: flake8 # black-compatible flake-8 config From b1b0db5f55e4430e7c4a5a5de022cbf4e75e2128 Mon Sep 17 00:00:00 2001 From: Felix Jentzsch Date: Thu, 25 May 2023 17:46:52 +0200 Subject: [PATCH 145/665] Fix linting --- requirements.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/requirements.txt b/requirements.txt index 5bb4f4abc9..223138932e 100644 --- a/requirements.txt +++ b/requirements.txt @@ -2,6 +2,7 @@ bitstring==3.1.7 clize==4.1.1 dataclasses-json==0.5.7 gspread==3.6.0 +ipython==8.12.2 numpy==1.22.0 onnx==1.13.0 onnxoptimizer @@ -18,4 +19,3 @@ sphinx_rtd_theme==0.5.0 toposort==1.5 vcdvcd==1.0.5 wget==3.2 -ipython==8.12.2 From 161cc20e25a71806d438290f3dca88a87e1213d2 Mon Sep 17 00:00:00 2001 From: Felix Jentzsch Date: Fri, 26 May 2023 11:22:46 +0200 Subject: [PATCH 146/665] Update Brevitas, apply workarounds to fix quicktest --- fetch-repos.sh | 2 +- setup.cfg | 8 ++++---- tests/brevitas/test_brevitas_avg_pool_export.py | 4 ++-- tests/end2end/test_end2end_cybsec_mlp.py | 2 +- tests/transformation/streamline/test_streamline_cnv.py | 2 ++ tests/transformation/streamline/test_streamline_fc.py | 2 ++ tests/transformation/test_infer_data_layouts_cnv.py | 3 ++- 7 files changed, 14 insertions(+), 9 deletions(-) diff --git a/fetch-repos.sh b/fetch-repos.sh index 189693dd17..ddae4020ed 100755 --- a/fetch-repos.sh +++ b/fetch-repos.sh @@ -29,7 +29,7 @@ QONNX_COMMIT="0c980ef410c7c99b33c5b96486233f5a723ca1bc" FINN_EXP_COMMIT="0aa7e1c44b20cf085b6fe42cff360f0a832afd2c" -BREVITAS_COMMIT="c65f9c13dc124971f14739349531bbcda5c2a4aa" +BREVITAS_COMMIT="d30ba0d6b3db4a333072624fa3d10827a686488d" PYVERILATOR_COMMIT="766e457465f5c0dd315490d7b9cc5d74f9a76f4f" CNPY_COMMIT="4e8810b1a8637695171ed346ce68f6984e585ef4" HLSLIB_COMMIT="c17aa478ae574971d115afa9fa4d9c215857d1ac" diff --git a/setup.cfg b/setup.cfg index 50a91498ce..fb070a436e 100644 --- a/setup.cfg +++ b/setup.cfg @@ -34,12 +34,12 @@ name = finn description = A Framework for Fast, Scalable Quantized Neural Network Inference author = Yaman Umuroglu -author-email = yamanu@xilinx.com +author_email = yamanu@xilinx.com license = new-bsd -long-description = file: README.md -long-description-content-type = text/markdown +long_description = file: README.md +long_description_content_type = text/markdown url = https://xilinx.github.io/finn/ -project-urls = +project_urls = Documentation = https://finn.readthedocs.io/ # Change if running only on Windows, Mac or Linux (comma-separated) platforms = any diff --git a/tests/brevitas/test_brevitas_avg_pool_export.py b/tests/brevitas/test_brevitas_avg_pool_export.py index 9550031b32..898f1fb732 100644 --- a/tests/brevitas/test_brevitas_avg_pool_export.py +++ b/tests/brevitas/test_brevitas_avg_pool_export.py @@ -31,7 +31,7 @@ import os import torch from brevitas.export import export_qonnx -from brevitas.nn import QuantAvgPool2d, QuantIdentity, QuantReLU +from brevitas.nn import TruncAvgPool2d, QuantIdentity, QuantReLU from qonnx.core.datatype import DataType from qonnx.core.modelwrapper import ModelWrapper from qonnx.transformation.infer_datatypes import InferDataTypes @@ -73,7 +73,7 @@ def test_brevitas_avg_pool_export( bit_width=input_bit_width, return_quant_tensor=True, ) - quant_avgpool = QuantAvgPool2d( + quant_avgpool = TruncAvgPool2d( kernel_size=kernel_size, stride=stride, bit_width=bit_width, diff --git a/tests/end2end/test_end2end_cybsec_mlp.py b/tests/end2end/test_end2end_cybsec_mlp.py index d2a4d0287f..1ab2d01228 100644 --- a/tests/end2end/test_end2end_cybsec_mlp.py +++ b/tests/end2end/test_end2end_cybsec_mlp.py @@ -146,7 +146,7 @@ def test_end2end_cybsec_mlp_export(QONNX_export): model.save(export_onnx_path) else: export_finn_onnx( - model_for_export, export_path=export_onnx_path, input_t=input_qt + model_for_export, export_path=export_onnx_path, input_t=input_qt, input_names=["onnx::Mul_0"] ) assert os.path.isfile(export_onnx_path) # fix input datatype diff --git a/tests/transformation/streamline/test_streamline_cnv.py b/tests/transformation/streamline/test_streamline_cnv.py index b7d6a825bb..c5d8e2517f 100644 --- a/tests/transformation/streamline/test_streamline_cnv.py +++ b/tests/transformation/streamline/test_streamline_cnv.py @@ -38,6 +38,7 @@ from qonnx.transformation.general import ( GiveReadableTensorNames, GiveUniqueNodeNames, + GiveUniqueParameterTensors, RemoveStaticGraphInputs, RemoveUnusedTensors, ) @@ -69,6 +70,7 @@ def test_streamline_cnv(size, wbits, abits): model = model.transform(InferShapes()) model = model.transform(FoldConstants()) model = model.transform(GiveUniqueNodeNames()) + model = model.transform(GiveUniqueParameterTensors()) model = model.transform(GiveReadableTensorNames()) model = model.transform(RemoveStaticGraphInputs()) # load one of the test vectors diff --git a/tests/transformation/streamline/test_streamline_fc.py b/tests/transformation/streamline/test_streamline_fc.py index 6131c3b03e..07c3a0f3cb 100644 --- a/tests/transformation/streamline/test_streamline_fc.py +++ b/tests/transformation/streamline/test_streamline_fc.py @@ -39,6 +39,7 @@ from qonnx.transformation.general import ( GiveReadableTensorNames, GiveUniqueNodeNames, + GiveUniqueParameterTensors, RemoveStaticGraphInputs, RemoveUnusedTensors, ) @@ -72,6 +73,7 @@ def test_streamline_fc(size, wbits, abits): model = model.transform(InferShapes()) model = model.transform(FoldConstants()) model = model.transform(GiveUniqueNodeNames()) + model = model.transform(GiveUniqueParameterTensors()) model = model.transform(GiveReadableTensorNames()) model = model.transform(RemoveStaticGraphInputs()) # load one of the test vectors diff --git a/tests/transformation/test_infer_data_layouts_cnv.py b/tests/transformation/test_infer_data_layouts_cnv.py index 71822a2903..245980f958 100644 --- a/tests/transformation/test_infer_data_layouts_cnv.py +++ b/tests/transformation/test_infer_data_layouts_cnv.py @@ -35,7 +35,7 @@ from qonnx.core.modelwrapper import ModelWrapper from qonnx.transformation.bipolar_to_xnor import ConvertBipolarMatMulToXnorPopcount from qonnx.transformation.fold_constants import FoldConstants -from qonnx.transformation.general import GiveReadableTensorNames, GiveUniqueNodeNames +from qonnx.transformation.general import GiveReadableTensorNames, GiveUniqueNodeNames, GiveUniqueParameterTensors from qonnx.transformation.infer_data_layouts import InferDataLayouts from qonnx.transformation.infer_shapes import InferShapes from qonnx.transformation.lower_convs_to_matmul import LowerConvsToMatMul @@ -57,6 +57,7 @@ def test_infer_data_layouts_cnv(): model = model.transform(InferShapes()) model = model.transform(FoldConstants()) model = model.transform(GiveUniqueNodeNames()) + model = model.transform(GiveUniqueParameterTensors()) model = model.transform(GiveReadableTensorNames()) model = model.transform(Streamline()) model = model.transform(InferDataLayouts()) From a78cdb2859c2e8b5150ce07e41a907b93cba2bc4 Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 29 May 2023 13:36:43 +0100 Subject: [PATCH 147/665] [CustomOp] Update naming of interfaces for code generation --- .../fpgadataflow/addstreams_batch.py | 55 +++++++++--- .../fpgadataflow/channelwise_op_batch.py | 36 +++++--- src/finn/custom_op/fpgadataflow/checksum.py | 35 +++++--- src/finn/custom_op/fpgadataflow/concat.py | 46 +++++++--- .../fpgadataflow/convolutioninputgenerator.py | 40 ++++++--- .../convolutioninputgenerator1d.py | 58 +++++++----- .../custom_op/fpgadataflow/downsampler.py | 39 +++++--- .../fpgadataflow/duplicatestreams_batch.py | 41 ++++++--- src/finn/custom_op/fpgadataflow/eltwise.py | 55 +++++++++--- .../custom_op/fpgadataflow/fmpadding_batch.py | 44 +++++++--- .../fpgadataflow/globalaccpool_batch.py | 36 +++++--- src/finn/custom_op/fpgadataflow/iodma.py | 88 ++++++++++++++----- .../fpgadataflow/labelselect_batch.py | 36 +++++--- src/finn/custom_op/fpgadataflow/lookup.py | 49 +++++++---- .../fpgadataflow/matrixvectoractivation.py | 70 ++++++++++----- src/finn/custom_op/fpgadataflow/pool_batch.py | 40 ++++++--- .../streamingdatawidthconverter_batch.py | 46 +++++++--- .../fpgadataflow/streamingmaxpool_batch.py | 47 +++++++--- .../fpgadataflow/thresholding_batch.py | 68 +++++++++----- src/finn/custom_op/fpgadataflow/upsampler.py | 42 ++++++--- .../fpgadataflow/vectorvectoractivation.py | 70 ++++++++++----- 21 files changed, 739 insertions(+), 302 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/addstreams_batch.py b/src/finn/custom_op/fpgadataflow/addstreams_batch.py index af106d9c06..8fbdf9c452 100644 --- a/src/finn/custom_op/fpgadataflow/addstreams_batch.py +++ b/src/finn/custom_op/fpgadataflow/addstreams_batch.py @@ -268,37 +268,60 @@ def read_npy_data(self): self.code_gen_dict["$READNPYDATA$"] = [] npy_in = "%s/input_0.npy" % code_gen_dir self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0);' - % (packed_hls_type, elem_hls_type, elem_bits, npy_type, npy_in) + 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) ) npy_in = "%s/input_1.npy" % code_gen_dir self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in1);' - % (packed_hls_type, elem_hls_type, elem_bits, npy_type, npy_in) + 'npy2apintstream<%s, %s, %d, %s>("%s", in1_%s);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) ) def strm_decl(self): self.code_gen_dict["$STREAMDECLARATIONS$"] = [] self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0 ("in0");'.format(self.get_instream_width()) + 'hls::stream> in0_{} ("in0_{}");'.format( + self.get_instream_width(), self.hls_sname(), self.hls_sname() + ) ) self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in1 ("in1");'.format(self.get_instream_width()) + 'hls::stream> in1_{} ("in1_{}");'.format( + self.get_instream_width(), self.hls_sname(), self.hls_sname() + ) ) self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out ("out");'.format(self.get_outstream_width()) + 'hls::stream> out_{} ("out_{}");'.format( + self.get_outstream_width(), self.hls_sname(), self.hls_sname() + ) ) def docompute(self): node = self.onnx_node self.code_gen_dict["$DOCOMPUTE$"] = [ - """{}<{}, {}, {}, {}, {}> (in0, in1, out, 1);""".format( + """{}<{}, {}, {}, {}, {}> (in0_{}, in1_{}, out_{}, 1);""".format( node.op_type, self.get_nodeattr("PE"), self.get_input_datatype().get_hls_datatype_str(), self.get_input_datatype().get_hls_datatype_str(), self.get_output_datatype().get_hls_datatype_str(), self.get_number_output_values(), + self.hls_sname(), + self.hls_sname(), + self.hls_sname(), ) ] @@ -315,12 +338,13 @@ def dataoutstrm(self): oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out, %s, "%s");' + 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' % ( packed_hls_type, elem_hls_type, elem_bits, npy_type, + self.hls_sname(), oshape_cpp_str, npy_out, ) @@ -331,24 +355,27 @@ def save_as_npy(self): def blackboxfunction(self): self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - """void {}(hls::stream> &in0, hls::stream> &in1, - hls::stream> &out)""".format( + """void {}(hls::stream> &in0_{}, hls::stream> &in1_{}, + hls::stream> &out_{})""".format( self.onnx_node.name, self.get_nodeattr("PE") * self.get_input_datatype().bitwidth(), + self.hls_sname(), self.get_nodeattr("PE") * self.get_input_datatype().bitwidth(), + self.hls_sname(), self.get_nodeattr("PE") * self.get_output_datatype().bitwidth(), + self.hls_sname(), ) ] def pragmas(self): self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0 name=in0_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() ] self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=in1 name=in1_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=in1_" + self.hls_sname() ) self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out name=out_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() ) self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE ap_ctrl_none port=return" diff --git a/src/finn/custom_op/fpgadataflow/channelwise_op_batch.py b/src/finn/custom_op/fpgadataflow/channelwise_op_batch.py index 7791647abf..71fc37b184 100644 --- a/src/finn/custom_op/fpgadataflow/channelwise_op_batch.py +++ b/src/finn/custom_op/fpgadataflow/channelwise_op_batch.py @@ -486,17 +486,28 @@ def read_npy_data(self): self.code_gen_dict["$READNPYDATA$"] = [] # note: the innermost dim is reversed for the input self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0, false);' - % (packed_hls_type, elem_hls_type, elem_bits, npy_type, npy_in) + 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s, false);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) ) def strm_decl(self): self.code_gen_dict["$STREAMDECLARATIONS$"] = [] self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0 ("in0");'.format(self.get_instream_width()) + 'hls::stream> in0_{} ("in0_{}");'.format( + self.get_instream_width(), self.hls_sname(), self.hls_sname() + ) ) self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out ("out");'.format(self.get_outstream_width()) + 'hls::stream> out_{} ("out_{}");'.format( + self.get_outstream_width(), self.hls_sname(), self.hls_sname() + ) ) def docompute(self): @@ -512,10 +523,12 @@ def docompute(self): raise Exception("""Unexpeted input shape""") self.code_gen_dict["$DOCOMPUTE$"] = [ """Thresholding_Batch<{}, NumChannels1, PE1, {}, {}> - (in0, out, threshs, numReps);""".format( + (in0_{}, out_{}, threshs, numReps);""".format( spatial_dim, tmpl_args["TSrcI"], tmpl_args["TDstI"], + self.hls_sname(), + self.hls_sname(), ) ] @@ -536,12 +549,13 @@ def dataoutstrm(self): # note: the innermost dim is not reversed for the output self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out, %s, "%s", false);' + 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s", false);' % ( packed_hls_type, elem_hls_type, elem_bits, npy_type, + self.hls_sname(), shape_cpp_str, npy_out, ) @@ -552,21 +566,23 @@ def save_as_npy(self): def blackboxfunction(self): self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - """void {}(hls::stream> &in0, - hls::stream> &out + """void {}(hls::stream> &in0_{}, + hls::stream> &out_{} )""".format( self.onnx_node.name, self.get_instream_width(), + self.hls_sname(), self.get_outstream_width(), + self.hls_sname(), ) ] def pragmas(self): self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0 name=in0_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() ] self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out name=out_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() ) self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE ap_ctrl_none port=return" diff --git a/src/finn/custom_op/fpgadataflow/checksum.py b/src/finn/custom_op/fpgadataflow/checksum.py index 99646274fa..c9d16c0011 100644 --- a/src/finn/custom_op/fpgadataflow/checksum.py +++ b/src/finn/custom_op/fpgadataflow/checksum.py @@ -241,17 +241,28 @@ def read_npy_data(self): self.code_gen_dict["$READNPYDATA$"] = [] # note: the innermost dim is reversed for the input self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0, false);' - % (packed_hls_type, elem_hls_type, elem_bits, npy_type, npy_in) + 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s, false);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) ) def strm_decl(self): self.code_gen_dict["$STREAMDECLARATIONS$"] = [] self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0 ("in0");'.format(self.get_instream_width()) + 'hls::stream> in0_{} ("in0_{}");'.format( + self.get_instream_width(), self.hls_sname(), self.hls_sname() + ) ) self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out ("out");'.format(self.get_outstream_width()) + 'hls::stream> out_{} ("out_{}");'.format( + self.get_outstream_width(), self.hls_sname(), self.hls_sname() + ) ) self.code_gen_dict["$STREAMDECLARATIONS$"].append("ap_uint<32> chk;") # set drain = false for cppsim @@ -259,7 +270,8 @@ def strm_decl(self): def docompute(self): self.code_gen_dict["$DOCOMPUTE$"] = [ - """checksum(in0, out, chk, drain);""" + """checksum(in0_%s, out_%s, chk, drain);""" + % (self.hls_sname(), self.hls_sname()) ] def dataoutstrm(self): @@ -279,12 +291,13 @@ def dataoutstrm(self): # note: the innermost dim is not reversed for the output self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out, %s, "%s", false);' + 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s", false);' % ( packed_hls_type, elem_hls_type, elem_bits, npy_type, + self.hls_sname(), shape_cpp_str, npy_out, ), @@ -299,18 +312,18 @@ def save_as_npy(self): def blackboxfunction(self): self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - """using T = ap_uint;\n void {}(hls::stream &in0, - hls::stream &out, ap_uint<32> &chk, ap_uint<1> &drain)""".format( - self.onnx_node.name + """using T = ap_uint;\n void {}(hls::stream &in0_{}, + hls::stream &out_{}, ap_uint<32> &chk, ap_uint<1> &drain)""".format( + self.onnx_node.name, self.hls_sname(), self.hls_sname() ) ] def pragmas(self): self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS interface axis port=in0 name=in0_" + self.hls_sname() + "#pragma HLS interface axis port=in0_" + self.hls_sname() ] self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS interface axis port=out name=out_" + self.hls_sname() + "#pragma HLS interface axis port=out_" + self.hls_sname() ) self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS interface s_axilite port=chk bundle=checksum" diff --git a/src/finn/custom_op/fpgadataflow/concat.py b/src/finn/custom_op/fpgadataflow/concat.py index 8b655b570d..c43e88d59d 100644 --- a/src/finn/custom_op/fpgadataflow/concat.py +++ b/src/finn/custom_op/fpgadataflow/concat.py @@ -278,8 +278,16 @@ def read_npy_data(self): packed_hls_type = "ap_uint<%d>" % packed_bits npy_in = "%s/input_%d.npy" % (code_gen_dir, i) self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in%d);' - % (packed_hls_type, elem_hls_type, elem_bits, npy_type, npy_in, i) + 'npy2apintstream<%s, %s, %d, %s>("%s", in%d_%s);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + i, + self.hls_sname(), + ) ) def strm_decl(self): @@ -288,21 +296,28 @@ def strm_decl(self): for i in range(n_inputs): packed_bits = self.get_instream_width(i) packed_hls_type = "ap_uint<%d>" % packed_bits - stream_name = "in%d" % i + stream_name = "in%d_%s" % (i, self.hls_sname()) self.code_gen_dict["$STREAMDECLARATIONS$"].append( 'hls::stream<%s> %s ("%s");' % (packed_hls_type, stream_name, stream_name) ) self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out ("out");'.format(self.get_outstream_width()) + 'hls::stream> out_{} ("out_{}");'.format( + self.get_outstream_width(), self.hls_sname(), self.hls_sname() + ) ) def docompute(self): self.code_gen_dict["$DOCOMPUTE$"] = [] n_inputs = self.get_n_inputs() - in_stream_names = ["in%d" % x for x in range(n_inputs)] - in_stream_names = ",".join(in_stream_names) - comp_call = "StreamingConcat(%s, out, NumReps);" % (in_stream_names) + in_streams = [] + for i in range(n_inputs): + in_streams.append("in%d_%s" % (i, self.hls_sname())) + in_stream_names = ",".join(in_streams) + comp_call = "StreamingConcat(%s, out_%s, NumReps);" % ( + in_stream_names, + self.hls_sname(), + ) self.code_gen_dict["$DOCOMPUTE$"] = [comp_call] def dataoutstrm(self): @@ -318,12 +333,13 @@ def dataoutstrm(self): oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out, %s, "%s");' + 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' % ( packed_hls_type, elem_hls_type, elem_bits, npy_type, + self.hls_sname(), oshape_cpp_str, npy_out, ) @@ -337,10 +353,15 @@ def blackboxfunction(self): in_streams = [] for i in range(n_inputs): iwidth = self.get_instream_width(i) - in_streams.append("hls::stream> &in%d" % (iwidth, i)) + in_streams.append( + "hls::stream> &in%d_%s" % (iwidth, i, self.hls_sname()) + ) in_streams = ",".join(in_streams) total_width = self.get_input_datatype().bitwidth() * self.get_total_elems() - out_stream = "hls::stream> &out" % (total_width) + out_stream = "hls::stream> &out_%s" % ( + total_width, + self.hls_sname(), + ) blackbox_hls = "void %s(%s, %s)" % (self.onnx_node.name, in_streams, out_stream) self.code_gen_dict["$BLACKBOXFUNCTION$"] = [blackbox_hls] @@ -349,12 +370,11 @@ def pragmas(self): pragmas = [] for i in range(n_inputs): pragmas.append( - "#pragma HLS INTERFACE axis port=in%d name=in%d_%s" - % (i, i, self.hls_sname()) + "#pragma HLS INTERFACE axis port=in%d_%s" % (i, self.hls_sname()) ) self.code_gen_dict["$PRAGMAS$"] = pragmas self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out name=out_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() ) self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE ap_ctrl_none port=return" diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py index 6cc9208bb8..c80f79a8c9 100644 --- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py +++ b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py @@ -401,17 +401,28 @@ def read_npy_data(self): npy_in = "%s/input_0.npy" % code_gen_dir self.code_gen_dict["$READNPYDATA$"] = [] self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0);' - % (packed_hls_type, elem_hls_type, elem_bits, npy_type, npy_in) + 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) ) def strm_decl(self): self.code_gen_dict["$STREAMDECLARATIONS$"] = [] self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0 ("in0");'.format(self.get_instream_width()) + 'hls::stream> in0_{} ("in0_{}");'.format( + self.get_instream_width(), self.hls_sname(), self.hls_sname() + ) ) self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out ("out");'.format(self.get_outstream_width()) + 'hls::stream> out_{} ("out_{}");'.format( + self.get_outstream_width(), self.hls_sname(), self.hls_sname() + ) ) def docompute(self): @@ -436,15 +447,15 @@ def docompute(self): if self.get_nodeattr("depthwise") == 1: self.code_gen_dict["$DOCOMPUTE$"] = [ """{}_dws (in0, out, numReps, {});""".format( - hls_call, hls_ram_style + OFMDim1, SIMD1, Stride1> (in0_{}, out_{}, numReps, {});""".format( + hls_call, self.hls_sname(), self.hls_sname(), hls_ram_style ) ] else: self.code_gen_dict["$DOCOMPUTE$"] = [ """{} (in0, out, numReps, {});""".format( - hls_call, hls_ram_style + OFMDim1, SIMD1, Stride1> (in0_{}, out_{}, numReps, {});""".format( + hls_call, self.hls_sname(), self.hls_sname(), hls_ram_style ) ] @@ -464,12 +475,13 @@ def dataoutstrm(self): oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out, %s, "%s");' + 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' % ( packed_hls_type, elem_hls_type, elem_bits, npy_type, + self.hls_sname(), oshape_cpp_str, npy_out, ) @@ -480,18 +492,18 @@ def save_as_npy(self): def blackboxfunction(self): self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - """void {}(hls::stream> &in0, - hls::stream> &out)""".format( - self.onnx_node.name + """void {}(hls::stream> &in0_{}, + hls::stream> &out_{})""".format( + self.onnx_node.name, self.hls_sname(), self.hls_sname() ) ] def pragmas(self): self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0 name=in0_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() ] self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out name=out_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() ) self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE ap_ctrl_none port=return" diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator1d.py b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator1d.py index 6e792ca585..43e8df17b4 100644 --- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator1d.py +++ b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator1d.py @@ -601,17 +601,28 @@ def read_npy_data(self): npy_in = "%s/input_0.npy" % code_gen_dir self.code_gen_dict["$READNPYDATA$"] = [] self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0);' - % (packed_hls_type, elem_hls_type, elem_bits, npy_type, npy_in) + 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) ) def strm_decl(self): self.code_gen_dict["$STREAMDECLARATIONS$"] = [] self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0 ("in0");'.format(self.get_instream_width()) + 'hls::stream> in0_{} ("in0_{}");'.format( + self.get_instream_width(), self.hls_sname(), self.hls_sname() + ) ) self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out ("out");'.format(self.get_outstream_width()) + 'hls::stream> out_{} ("out_{}");'.format( + self.get_outstream_width(), self.hls_sname(), self.hls_sname() + ) ) def docompute(self): @@ -630,40 +641,40 @@ def docompute(self): self.code_gen_dict["$DOCOMPUTE$"] = [ """{} - (in0, out, numReps, {});""".format( - swu_variant, hls_ram_style + (in0_{}, out_{}, numReps, {});""".format( + swu_variant, self.hls_sname(), self.hls_sname(), hls_ram_style ) ] if swu_variant == "ConvolutionInputGenerator_1D": self.code_gen_dict["$DOCOMPUTE$"] = [ """{} - (in0, out, numReps, {});""".format( - swu_variant, hls_ram_style + (in0_{}, out_{}, numReps, {});""".format( + swu_variant, self.hls_sname(), self.hls_sname(), hls_ram_style ) ] if swu_variant == "ConvolutionInputGenerator_1D_dws": self.code_gen_dict["$DOCOMPUTE$"] = [ """{} - (in0, out, numReps, {});""".format( - swu_variant, hls_ram_style + (in0_{}, out_{}, numReps, {});""".format( + swu_variant, self.hls_sname(), self.hls_sname(), hls_ram_style ) ] if swu_variant == "ConvolutionInputGenerator_1D_dws_stride": self.code_gen_dict["$DOCOMPUTE$"] = [ """{} - (in0, out, numReps, {});""".format( - swu_variant, hls_ram_style + (in0_{}, out_{}, numReps, {});""".format( + swu_variant, self.hls_sname(), self.hls_sname(), hls_ram_style ) ] if swu_variant == "ConvolutionInputGenerator_1D_dws_naive": self.code_gen_dict["$DOCOMPUTE$"] = [ """{} - (in0, out, numReps, {});""".format( - swu_variant, hls_ram_style + (in0_{}, out_{}, numReps, {});""".format( + swu_variant, self.hls_sname(), self.hls_sname(), hls_ram_style ) ] @@ -690,12 +701,13 @@ def dataoutstrm(self): multi_pixel_out = 1 self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out, %s, "%s", true, 1, %d);' + 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s", true, 1, %d);' % ( packed_hls_type, elem_hls_type, elem_bits, npy_type, + self.hls_sname(), oshape_cpp_str, npy_out, multi_pixel_out, @@ -708,26 +720,26 @@ def save_as_npy(self): def blackboxfunction(self): if self.use_parallel_window_output(): self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - """void {}(hls::stream> &in0, + """void {}(hls::stream> &in0_{}, hls::stream> - &out)""".format( - self.onnx_node.name + &out_{})""".format( + self.onnx_node.name, self.hls_sname(), self.hls_sname() ) ] else: self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - """void {}(hls::stream> &in0, - hls::stream> &out)""".format( - self.onnx_node.name + """void {}(hls::stream> &in0_{}, + hls::stream> &out_{})""".format( + self.onnx_node.name, self.hls_sname(), self.hls_sname() ) ] def pragmas(self): self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0 name=in0_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() ] self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out name=out_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() ) self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE ap_ctrl_none port=return" diff --git a/src/finn/custom_op/fpgadataflow/downsampler.py b/src/finn/custom_op/fpgadataflow/downsampler.py index 255606ee7f..d42a076c30 100644 --- a/src/finn/custom_op/fpgadataflow/downsampler.py +++ b/src/finn/custom_op/fpgadataflow/downsampler.py @@ -212,24 +212,36 @@ def read_npy_data(self): npy_in = "%s/input_0.npy" % code_gen_dir self.code_gen_dict["$READNPYDATA$"] = [] self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0);' - % (packed_hls_type, elem_hls_type, elem_bits, npy_type, npy_in) + 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) ) def strm_decl(self): self.code_gen_dict["$STREAMDECLARATIONS$"] = [] self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0 ("in0");'.format(self.get_instream_width()) + 'hls::stream> in0_{} ("in0_{}");'.format( + self.get_instream_width(), self.hls_sname(), self.hls_sname() + ) ) self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out ("out");'.format(self.get_outstream_width()) + 'hls::stream> out_{} ("out_{}");'.format( + self.get_outstream_width(), self.hls_sname(), self.hls_sname() + ) ) def docompute(self): dim_var = "1D" if (self.get_nodeattr("is1D") == 1) else "2D" + sname = self.hls_sname() self.code_gen_dict["$DOCOMPUTE$"] = [ f"""ConvolutionInputGenerator_{dim_var}_kernel1 (in0, out, numReps);""" + IFMDim, SIMD,Stride> (in0_{sname}, out_{sname}, numReps);""" ] def dataoutstrm(self): @@ -248,12 +260,13 @@ def dataoutstrm(self): oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out, %s, "%s");' + 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' % ( packed_hls_type, elem_hls_type, elem_bits, npy_type, + self.hls_sname(), oshape_cpp_str, npy_out, ) @@ -266,16 +279,22 @@ def blackboxfunction(self): packed_bits = self.get_instream_width() packed_hls_type = "ap_uint<%d>" % packed_bits self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - "void %s(hls::stream<%s > &in0, hls::stream<%s > &out)" - % (self.onnx_node.name, packed_hls_type, packed_hls_type) + "void %s(hls::stream<%s > &in0_%s, hls::stream<%s > &out_%s)" + % ( + self.onnx_node.name, + packed_hls_type, + self.hls_sname(), + packed_hls_type, + self.hls_sname(), + ) ] def pragmas(self): self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0 name=in0_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() ] self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out name=out_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() ) self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE ap_ctrl_none port=return" diff --git a/src/finn/custom_op/fpgadataflow/duplicatestreams_batch.py b/src/finn/custom_op/fpgadataflow/duplicatestreams_batch.py index 312f5e7e4a..0d5d806dc5 100644 --- a/src/finn/custom_op/fpgadataflow/duplicatestreams_batch.py +++ b/src/finn/custom_op/fpgadataflow/duplicatestreams_batch.py @@ -309,18 +309,27 @@ def read_npy_data(self): npy_in = "%s/input_0.npy" % code_gen_dir self.code_gen_dict["$READNPYDATA$"] = [] self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0);' - % (packed_hls_type, elem_hls_type, elem_bits, npy_type, npy_in) + 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) ) def strm_decl(self): n_outputs = self.get_num_output_streams() self.code_gen_dict["$STREAMDECLARATIONS$"] = [] self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0 ("in0");'.format(self.get_instream_width()) + 'hls::stream> in0_{} ("in0_{}");'.format( + self.get_instream_width(), self.hls_sname(), self.hls_sname() + ) ) for i in range(n_outputs): - out_name = "out%d" % i + out_name = "out%d_%s" % (i, self.hls_sname()) self.code_gen_dict["$STREAMDECLARATIONS$"].append( 'hls::stream> %s ("%s");' % (self.get_outstream_width(), out_name, out_name) @@ -328,8 +337,13 @@ def strm_decl(self): def docompute(self): n_outputs = self.get_num_output_streams() - ostreams = ["out%d" % x for x in range(n_outputs)] - dc = "DuplicateStreamsCustom(in0, %s);" % (",".join(ostreams)) + ostreams = [] + for i in range(n_outputs): + ostreams.append("out%d_%s" % (i, self.hls_sname())) + dc = "DuplicateStreamsCustom(in0_%s, %s);" % ( + self.hls_sname(), + ",".join(ostreams), + ) self.code_gen_dict["$DOCOMPUTE$"] = [dc] def dataoutstrm(self): @@ -346,7 +360,7 @@ def dataoutstrm(self): outstrm_code = [] for i in range(n_outputs): - out_name = "out%d" % i + out_name = "out%d_%s" % (i, self.hls_sname()) npy_out = "%s/output%d.npy" % (code_gen_dir, i) outstrm_code.append( 'apintstream2npy<%s, %s, %d, %s>(%s, %s, "%s");' @@ -371,10 +385,14 @@ def blackboxfunction(self): inp_streams = [] o_stream_w = self.get_outstream_width() i_stream_w = self.get_instream_width() - in_stream = "hls::stream > &in0" % (i_stream_w) + in_stream = "hls::stream > &in0_%s" % (i_stream_w, self.hls_sname()) inp_streams.append(in_stream) for i in range(n_outputs): - out_stream = "hls::stream > &out%d" % (o_stream_w, i) + out_stream = "hls::stream > &out%d_%s" % ( + o_stream_w, + i, + self.hls_sname(), + ) inp_streams.append(out_stream) self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ @@ -387,12 +405,11 @@ def blackboxfunction(self): def pragmas(self): n_outputs = self.get_num_output_streams() self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0 name=in0_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() ] for i in range(n_outputs): self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out%d name=out%d_%s" - % (i, i, self.hls_sname()) + "#pragma HLS INTERFACE axis port=out%d_%s" % (i, self.hls_sname()) ) self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE ap_ctrl_none port=return" diff --git a/src/finn/custom_op/fpgadataflow/eltwise.py b/src/finn/custom_op/fpgadataflow/eltwise.py index c96f12f06b..348e314792 100644 --- a/src/finn/custom_op/fpgadataflow/eltwise.py +++ b/src/finn/custom_op/fpgadataflow/eltwise.py @@ -354,25 +354,45 @@ def read_npy_data(self): self.code_gen_dict["$READNPYDATA$"] = [] npy_in = "%s/input_0.npy" % code_gen_dir self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0);' - % (packed_hls_type_0, elem_hls_type_0, elem_bits_0, npy_type, npy_in) + 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' + % ( + packed_hls_type_0, + elem_hls_type_0, + elem_bits_0, + npy_type, + npy_in, + self.hls_sname(), + ) ) npy_in = "%s/input_1.npy" % code_gen_dir self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in1);' - % (packed_hls_type_1, elem_hls_type_1, elem_bits_1, npy_type, npy_in) + 'npy2apintstream<%s, %s, %d, %s>("%s", in1_%s);' + % ( + packed_hls_type_1, + elem_hls_type_1, + elem_bits_1, + npy_type, + npy_in, + self.hls_sname(), + ) ) def strm_decl(self): self.code_gen_dict["$STREAMDECLARATIONS$"] = [] self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0 ("in0");'.format(self.get_instream_width(0)) + 'hls::stream> in0_{} ("in0_{}");'.format( + self.get_instream_width(0), self.hls_sname(), self.hls_sname() + ) ) self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in1 ("in1");'.format(self.get_instream_width(1)) + 'hls::stream> in1_{} ("in1_{}");'.format( + self.get_instream_width(1), self.hls_sname(), self.hls_sname() + ) ) self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out ("out");'.format(self.get_outstream_width()) + 'hls::stream> out_{} ("out_{}");'.format( + self.get_outstream_width(), self.hls_sname(), self.hls_sname() + ) ) def docompute(self): @@ -394,7 +414,7 @@ def docompute(self): out_hls_type, ) self.code_gen_dict["$DOCOMPUTE$"] = [ - """{}<{}, {}, {}, {}, {}, {}>(in0, in1, out, {});""".format( + """{}<{}, {}, {}, {}, {}, {}>(in0_{}, in1_{}, out_{}, {});""".format( "StreamingEltwise", self.get_nodeattr("NumChannels"), self.get_nodeattr("PE"), @@ -402,6 +422,9 @@ def docompute(self): slice_in0, slice_in1, slice_out, + self.hls_sname(), + self.hls_sname(), + self.hls_sname(), eltwise_op_str, ) ] @@ -419,12 +442,13 @@ def dataoutstrm(self): oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out, %s, "%s");' + 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' % ( packed_hls_type, elem_hls_type, elem_bits, npy_type, + self.hls_sname(), oshape_cpp_str, npy_out, ) @@ -435,24 +459,27 @@ def save_as_npy(self): def blackboxfunction(self): self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - """void {}(hls::stream> &in0, hls::stream> &in1, - hls::stream> &out)""".format( + """void {}(hls::stream> &in0_{}, hls::stream> &in1_{}, + hls::stream> &out_{})""".format( self.onnx_node.name, self.get_nodeattr("PE") * self.get_input_datatype(0).bitwidth(), + self.hls_sname(), self.get_nodeattr("PE") * self.get_input_datatype(1).bitwidth(), + self.hls_sname(), self.get_nodeattr("PE") * self.get_output_datatype().bitwidth(), + self.hls_sname(), ) ] def pragmas(self): self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0 name=in0_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() ] self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=in1 name=in1_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=in1_" + self.hls_sname() ) self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out name=out_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() ) self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE ap_ctrl_none port=return" diff --git a/src/finn/custom_op/fpgadataflow/fmpadding_batch.py b/src/finn/custom_op/fpgadataflow/fmpadding_batch.py index bdb5775c3e..ea9028d925 100644 --- a/src/finn/custom_op/fpgadataflow/fmpadding_batch.py +++ b/src/finn/custom_op/fpgadataflow/fmpadding_batch.py @@ -228,17 +228,28 @@ def read_npy_data(self): npy_in = "%s/input_0.npy" % code_gen_dir self.code_gen_dict["$READNPYDATA$"] = [] self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0);' - % (packed_hls_type, elem_hls_type, elem_bits, npy_type, npy_in) + 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) ) def strm_decl(self): self.code_gen_dict["$STREAMDECLARATIONS$"] = [] self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0 ("in0");'.format(self.get_instream_width()) + 'hls::stream> in0_{} ("in0_{}");'.format( + self.get_instream_width(), self.hls_sname(), self.hls_sname() + ) ) self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out ("out");'.format(self.get_outstream_width()) + 'hls::stream> out_{} ("out_{}");'.format( + self.get_outstream_width(), self.hls_sname(), self.hls_sname() + ) ) def docompute(self): @@ -256,8 +267,8 @@ def docompute(self): hls_call = node.op_type self.code_gen_dict["$DOCOMPUTE$"] = [ """{} (in0, out, numReps);""".format( - hls_call, in_t + {}> (in0_{}, out_{}, numReps);""".format( + hls_call, in_t, self.hls_sname(), self.hls_sname() ) ] else: @@ -265,8 +276,8 @@ def docompute(self): self.code_gen_dict["$DOCOMPUTE$"] = [ """{} (in0, out, numReps);""".format( - hls_call, in_t + SIMD1, {}> (in0_{}, out_{}, numReps);""".format( + hls_call, in_t, self.hls_sname(), self.hls_sname() ) ] @@ -286,12 +297,13 @@ def dataoutstrm(self): oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out, %s, "%s");' + 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' % ( packed_hls_type, elem_hls_type, elem_bits, npy_type, + self.hls_sname(), oshape_cpp_str, npy_out, ) @@ -304,16 +316,22 @@ def blackboxfunction(self): packed_bits = self.get_instream_width() packed_hls_type = "ap_uint<%d>" % packed_bits self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - "void %s(hls::stream<%s > &in0, hls::stream<%s > &out)" - % (self.onnx_node.name, packed_hls_type, packed_hls_type) + "void %s(hls::stream<%s > &in0_%s, hls::stream<%s > &out_%s)" + % ( + self.onnx_node.name, + packed_hls_type, + self.hls_sname(), + packed_hls_type, + self.hls_sname(), + ) ] def pragmas(self): self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0 name=in0_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() ] self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out name=out_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() ) self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE ap_ctrl_none port=return" diff --git a/src/finn/custom_op/fpgadataflow/globalaccpool_batch.py b/src/finn/custom_op/fpgadataflow/globalaccpool_batch.py index 220856922c..e518507034 100644 --- a/src/finn/custom_op/fpgadataflow/globalaccpool_batch.py +++ b/src/finn/custom_op/fpgadataflow/globalaccpool_batch.py @@ -267,27 +267,40 @@ def read_npy_data(self): npy_in = "%s/input_0.npy" % code_gen_dir self.code_gen_dict["$READNPYDATA$"] = [] self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0);' - % (packed_hls_type, elem_hls_type, elem_bits, npy_type, npy_in) + 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) ) def strm_decl(self): self.code_gen_dict["$STREAMDECLARATIONS$"] = [] self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0 ("in0");'.format(self.get_instream_width()) + 'hls::stream> in0_{} ("in0_{}");'.format( + self.get_instream_width(), self.hls_sname(), self.hls_sname() + ) ) self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out ("out");'.format(self.get_outstream_width()) + 'hls::stream> out_{} ("out_{}");'.format( + self.get_outstream_width(), self.hls_sname(), self.hls_sname() + ) ) def docompute(self): self.code_gen_dict["$DOCOMPUTE$"] = [ - """AccPool_Batch<{}, {}, {}, {}, {}> (in0, out, 1);""".format( + """AccPool_Batch<{}, {}, {}, {}, {}> (in0_{}, out_{}, 1);""".format( self.get_normal_input_shape()[1], self.get_nodeattr("NumChannels"), self.get_input_datatype().get_hls_datatype_str(), self.get_nodeattr("PE"), self.get_output_datatype().get_hls_datatype_str(), + self.hls_sname(), + self.hls_sname(), ) ] @@ -304,12 +317,13 @@ def dataoutstrm(self): oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out, %s, "%s");' + 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' % ( packed_hls_type, elem_hls_type, elem_bits, npy_type, + self.hls_sname(), oshape_cpp_str, npy_out, ) @@ -320,20 +334,22 @@ def save_as_npy(self): def blackboxfunction(self): self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - """void {}(hls::stream> &in0, - hls::stream> &out)""".format( + """void {}(hls::stream> &in0_{}, + hls::stream> &out_{})""".format( self.onnx_node.name, self.get_instream_width(), + self.hls_sname(), self.get_outstream_width(), + self.hls_sname(), ) ] def pragmas(self): self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0 name=in0_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() ] self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out name=out_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() ) self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE ap_ctrl_none port=return" diff --git a/src/finn/custom_op/fpgadataflow/iodma.py b/src/finn/custom_op/fpgadataflow/iodma.py index 8a756b630d..4b4ad28def 100644 --- a/src/finn/custom_op/fpgadataflow/iodma.py +++ b/src/finn/custom_op/fpgadataflow/iodma.py @@ -47,7 +47,7 @@ # Interfaces # - AXI-MM name specified by intfName unless this is set to "" (empty, the default) -# in which case output AXI-MM are named "out" and input AXI-MM are named "in0" +# in which case output AXI-MM are named "out_V" and input AXI-MM are named "in0_V" # - AXI-MM interface width (in bits) is specified by intfWidth # - AXI-Stream interface width (in bits) is specified by streamWidth # - If inftWidth and streamWidth are not equal, the DMA core performs @@ -254,15 +254,24 @@ def docompute(self): # DWCs depend on AXI MM and out interface width if strmw == intfw: # case 0: AXI MM width = out width, no DWCs needed - self.code_gen_dict["$DOCOMPUTE$"] = [dma_inst_template % ("in0", "out")] + self.code_gen_dict["$DOCOMPUTE$"] = [ + dma_inst_template + % ("in0_" + self.hls_sname(), "out_" + self.hls_sname()) + ] elif (strmw % intfw == 0) or (intfw % strmw == 0): # case 1: AXI MM width divisible by out width or vice versa # single DWC + single extra stream needed self.code_gen_dict["$DOCOMPUTE$"] = [ "hls::stream > dma2dwc;" % intfw, - dma_inst_template % ("in0", "dma2dwc"), + dma_inst_template % ("in0_" + self.hls_sname(), "dma2dwc"), dwc_inst_template - % (intfw, strmw, total_bits // intfw, "dma2dwc", "out"), + % ( + intfw, + strmw, + total_bits // intfw, + "dma2dwc", + "out_" + self.hls_sname(), + ), ] else: # case 2: AXI MM width not divisible by out width or vice versa @@ -271,26 +280,41 @@ def docompute(self): self.code_gen_dict["$DOCOMPUTE$"] = [ "hls::stream > dma2lcm;" % intfw, "hls::stream > lcm2out;" % width_lcm, - dma_inst_template % ("in0", "dma2lcm"), + dma_inst_template % ("in0_" + self.hls_sname(), "dma2lcm"), dwc_inst_template % (intfw, width_lcm, total_bits // intfw, "dma2lcm", "lcm2out"), dwc_inst_template - % (width_lcm, strmw, total_bits // width_lcm, "lcm2out", "out"), + % ( + width_lcm, + strmw, + total_bits // width_lcm, + "lcm2out", + "out_" + self.hls_sname(), + ), ] elif direction == "out": # in0 -> (DWCs) -> IODMA -> AXI MM # DWCs depend on AXI MM and out interface width if strmw == intfw: # case 0: in width = AXI MM width, no DWCs needed - self.code_gen_dict["$DOCOMPUTE$"] = [dma_inst_template % ("in0", "out")] + self.code_gen_dict["$DOCOMPUTE$"] = [ + dma_inst_template + % ("in0_" + self.hls_sname(), "out_" + self.hls_sname()) + ] elif (strmw % intfw == 0) or (intfw % strmw == 0): # case 1: AXI MM width divisible by in width or vice versa # single DWC + single extra stream needed self.code_gen_dict["$DOCOMPUTE$"] = [ "hls::stream > dwc2dma;" % intfw, dwc_inst_template - % (strmw, intfw, total_bits // strmw, "in0", "dwc2dma"), - dma_inst_template % ("dwc2dma", "out"), + % ( + strmw, + intfw, + total_bits // strmw, + "in0_" + self.hls_sname(), + "dwc2dma", + ), + dma_inst_template % ("dwc2dma", "out_" + self.hls_sname()), ] else: # case 2: AXI MM width not divisible by out width or vice versa @@ -300,10 +324,16 @@ def docompute(self): "hls::stream > in2lcm;" % width_lcm, "hls::stream > lcm2dma;" % intfw, dwc_inst_template - % (strmw, width_lcm, total_bits // strmw, "in0", "in2lcm"), + % ( + strmw, + width_lcm, + total_bits // strmw, + "in0_" + self.hls_sname(), + "in2lcm", + ), dwc_inst_template % (width_lcm, intfw, total_bits // width_lcm, "in2lcm", "lcm2dma"), - dma_inst_template % ("lcm2dma", "out"), + dma_inst_template % ("lcm2dma", "out_" + self.hls_sname()), ] else: raise Exception("Unknown IODMA direction: %s" % direction) @@ -316,13 +346,25 @@ def blackboxfunction(self): direction = self.get_nodeattr("direction") if direction == "in": self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - "void %s(%s *in0, hls::stream<%s > &out, unsigned int numReps)" - % (self.onnx_node.name, packed_hls_type_in, packed_hls_type_out) + "void %s(%s *in0_%s, hls::stream<%s > &out_%s, unsigned int numReps)" + % ( + self.onnx_node.name, + packed_hls_type_in, + self.hls_sname(), + packed_hls_type_out, + self.hls_sname(), + ) ] elif direction == "out": self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - "void %s(hls::stream<%s > &in0, %s *out, unsigned int numReps)" - % (self.onnx_node.name, packed_hls_type_in, packed_hls_type_out) + "void %s(hls::stream<%s > &in0_%s, %s *out_%s, unsigned int numReps)" + % ( + self.onnx_node.name, + packed_hls_type_in, + self.hls_sname(), + packed_hls_type_out, + self.hls_sname(), + ) ] else: raise ValueError("Invalid IODMA direction, please set to in or out") @@ -339,32 +381,36 @@ def pragmas(self): if direction == "in": if intfname == "": self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE m_axi offset=slave port=in0" + "#pragma HLS INTERFACE m_axi offset=slave port=in0_" + + self.hls_sname() ) else: self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE m_axi offset=slave port=%s" % (intfname) ) self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE s_axilite port=in0 bundle=control" + "#pragma HLS INTERFACE s_axilite port=in0_%s bundle=control" + % (self.hls_sname()) ) self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out name=out_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() ) elif direction == "out": self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=in0 name=in0_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() ) if intfname == "": self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE m_axi offset=slave port=out" + "#pragma HLS INTERFACE m_axi offset=slave port=out_" + + self.hls_sname() ) else: self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE m_axi offset=slave port=%s" % (intfname) ) self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE s_axilite port=out bundle=control" + "#pragma HLS INTERFACE s_axilite port=out_%s bundle=control" + % (self.hls_sname()) ) else: raise ValueError("Invalid IODMA direction, please set to in or out") diff --git a/src/finn/custom_op/fpgadataflow/labelselect_batch.py b/src/finn/custom_op/fpgadataflow/labelselect_batch.py index 492cd01073..12a88dacd4 100644 --- a/src/finn/custom_op/fpgadataflow/labelselect_batch.py +++ b/src/finn/custom_op/fpgadataflow/labelselect_batch.py @@ -275,29 +275,42 @@ def read_npy_data(self): # Also notice that StreamingDataWidthConverter_Batch performs LE packing self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0,false);' - % (packed_hls_type, elem_hls_type, elem_bits, npy_type, npy_in) + 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s, false);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) ) def strm_decl(self): self.code_gen_dict["$STREAMDECLARATIONS$"] = [] self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0 ("in0");'.format(self.get_instream_width()) + 'hls::stream> in0_{} ("in0_{}");'.format( + self.get_instream_width(), self.hls_sname(), self.hls_sname() + ) ) self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out ("out");'.format(self.get_outstream_width()) + 'hls::stream> out_{} ("out_{}");'.format( + self.get_outstream_width(), self.hls_sname(), self.hls_sname() + ) ) def docompute(self): node = self.onnx_node self.code_gen_dict["$DOCOMPUTE$"] = [ - """{}<{}, {}, {}, {}, {} > (in0, out, 1);""".format( + """{}<{}, {}, {}, {}, {} > (in0_{}, out_{}, 1);""".format( node.op_type, self.get_nodeattr("Labels"), self.get_nodeattr("PE"), self.get_nodeattr("K"), self.get_input_datatype().get_hls_datatype_str(), self.get_output_datatype().get_hls_datatype_str(), + self.hls_sname(), + self.hls_sname(), ) ] @@ -314,12 +327,13 @@ def dataoutstrm(self): oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out, %s, "%s");' + 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' % ( packed_hls_type, elem_hls_type, elem_bits, npy_type, + self.hls_sname(), oshape_cpp_str, npy_out, ) @@ -330,21 +344,23 @@ def save_as_npy(self): def blackboxfunction(self): self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - """void {}(hls::stream> &in0, - hls::stream > &out)""".format( + """void {}(hls::stream> &in0_{}, + hls::stream > &out_{})""".format( self.onnx_node.name, self.get_nodeattr("PE"), self.get_input_datatype().bitwidth(), + self.hls_sname(), self.get_output_datatype().bitwidth(), + self.hls_sname(), ) ] def pragmas(self): self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0 name=in0_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() ] self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out name=out_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() ) self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE ap_ctrl_none port=return" diff --git a/src/finn/custom_op/fpgadataflow/lookup.py b/src/finn/custom_op/fpgadataflow/lookup.py index ed560ac962..ecf630ef7f 100644 --- a/src/finn/custom_op/fpgadataflow/lookup.py +++ b/src/finn/custom_op/fpgadataflow/lookup.py @@ -206,8 +206,15 @@ def read_npy_data(self): npy_in = "%s/input_0.npy" % code_gen_dir self.code_gen_dict["$READNPYDATA$"] = [] self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0);' - % (packed_hls_type, elem_hls_type, elem_bits, npy_type, npy_in) + 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) ) def dataoutstrm(self): @@ -226,12 +233,13 @@ def dataoutstrm(self): oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out, %s, "%s", %s);' + 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s", %s);' % ( packed_hls_type, elem_hls_type, elem_bits, npy_type, + self.hls_sname(), oshape_cpp_str, npy_out, "false", @@ -244,10 +252,14 @@ def save_as_npy(self): def strm_decl(self): self.code_gen_dict["$STREAMDECLARATIONS$"] = [] self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0 ("in0");'.format(self.get_instream_width()) + 'hls::stream> in0_{} ("in0_{}");'.format( + self.get_instream_width(), self.hls_sname(), self.hls_sname() + ) ) self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out ("out");'.format(self.get_outstream_width()) + 'hls::stream> out_{} ("out_{}");'.format( + self.get_outstream_width(), self.hls_sname(), self.hls_sname() + ) ) def docompute(self): @@ -255,12 +267,14 @@ def docompute(self): if mem_mode == "const": self.code_gen_dict["$DOCOMPUTE$"] = [ """StreamingLookup(in0, out, embeddings);""" + InputType, EmbeddingType >(in0_%s, out_%s, embeddings);""" + % (self.hls_sname(), self.hls_sname()) ] elif mem_mode == "external": self.code_gen_dict["$DOCOMPUTE$"] = [ - """StreamingLookup_ext(in0, out, mem, size, oob_count, + """StreamingLookup_ext(in0_%s, out_%s, mem, size, oob_count, oob_irq);""" + % (self.hls_sname(), self.hls_sname()) ] def blackboxfunction(self): @@ -271,26 +285,29 @@ def blackboxfunction(self): packed_output_hls_type = "ap_uint<%d>" % obits if mem_mode == "const": self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - "void %s(hls::stream<%s > &in0, hls::stream<%s > &out)" - % (self.onnx_node.name, packed_input_hls_type, packed_output_hls_type) + "void %s(hls::stream<%s > &in0_%s, hls::stream<%s > &out_%s)" + % ( + self.onnx_node.name, + packed_input_hls_type, + self.hls_sname(), + packed_output_hls_type, + self.hls_sname(), + ) ] elif mem_mode == "external": self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ "void " + self.onnx_node.name - + "(hls::stream &in0, hls::stream &out, " + + "(hls::stream &in0_%s, hls::stream &out_%s, " + % (self.hls_sname(), self.hls_sname()) + "T_DST const *const mem, unsigned const size, " + "unsigned &oob_count, bool &oob_irq)" ] def pragmas(self): mem_mode = self.get_nodeattr("mem_mode") - my_pragmas = [ - "#pragma HLS INTERFACE axis port=in0 name=in0_" + self.hls_sname() - ] - my_pragmas.append( - "#pragma HLS INTERFACE axis port=out name=out_" + self.hls_sname() - ) + my_pragmas = ["#pragma HLS INTERFACE axis port=in0_" + self.hls_sname()] + my_pragmas.append("#pragma HLS INTERFACE axis port=out_" + self.hls_sname()) my_pragmas.append("#pragma HLS INTERFACE ap_ctrl_none port=return") if mem_mode == "const": my_pragmas.append( diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index 899bce98d2..fae2d86d88 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -1097,8 +1097,15 @@ def read_npy_data(self): self.code_gen_dict["$READNPYDATA$"] = [] # note: the innermost dim is reversed for the input self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0, false);' - % (packed_hls_type, elem_hls_type, elem_bits, npy_type, npy_in) + 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s, false);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) ) mem_mode = self.get_nodeattr("mem_mode") @@ -1112,24 +1119,35 @@ def read_npy_data(self): npy_in = "%s/weights.npy" % code_gen_dir self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", weights, false, numReps);' - % (packed_hls_type, elem_hls_type, elem_bits, npy_type, npy_in) + 'npy2apintstream<%s, %s, %d, %s>("%s", weights_%s, false, numReps);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) ) def strm_decl(self): mem_mode = self.get_nodeattr("mem_mode") self.code_gen_dict["$STREAMDECLARATIONS$"] = [] self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0 ("in0");'.format(self.get_instream_width()) + 'hls::stream> in0_{} ("in0_{}");'.format( + self.get_instream_width(), self.hls_sname(), self.hls_sname() + ) ) self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out ("out");'.format(self.get_outstream_width()) + 'hls::stream> out_{} ("out_{}");'.format( + self.get_outstream_width(), self.hls_sname(), self.hls_sname() + ) ) if mem_mode == "decoupled" or mem_mode == "external": self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> weights ("weights");'.format( - self.get_weightstream_width() + 'hls::stream> weights_{} ("weights_{}");'.format( + self.get_weightstream_width(), self.hls_sname(), self.hls_sname() ) ) @@ -1149,10 +1167,12 @@ def docompute(self): if mem_mode == "const": self.code_gen_dict["$DOCOMPUTE$"] = [ """Matrix_Vector_Activate_Batch - (in0, out, weights, {}, numReps, {});""".format( + (in0_{}, out_{}, weights, {}, numReps, {});""".format( tmpl_args["TSrcI"], tmpl_args["TDstI"], tmpl_args["TWeightI"], + self.hls_sname(), + self.hls_sname(), threshs, map_to_hls_mult_style[self.get_nodeattr("resType")], ) @@ -1166,11 +1186,14 @@ def docompute(self): wdtype_hls_str = export_wdt.get_hls_datatype_str() self.code_gen_dict["$DOCOMPUTE$"] = [ """Matrix_Vector_Activate_Stream_Batch - (in0, out, weights, {}, numReps, {});""".format( + (in0_{}, out_{}, weights_{}, {}, numReps, {});""".format( tmpl_args["TSrcI"], tmpl_args["TDstI"], tmpl_args["TWeightI"], wdtype_hls_str, + self.hls_sname(), + self.hls_sname(), + self.hls_sname(), threshs, map_to_hls_mult_style[self.get_nodeattr("resType")], ) @@ -1199,12 +1222,13 @@ def dataoutstrm(self): # note: the innermost dim is not reversed for the output self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out, %s, "%s", false);' + 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s", false);' % ( packed_hls_type, elem_hls_type, elem_bits, npy_type, + self.hls_sname(), shape_cpp_str, npy_out, ) @@ -1217,25 +1241,30 @@ def blackboxfunction(self): mem_mode = self.get_nodeattr("mem_mode") if mem_mode == "const": self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - """void {}(hls::stream> &in0, - hls::stream> &out + """void {}(hls::stream> &in0_{}, + hls::stream> &out_{} )""".format( self.onnx_node.name, self.get_instream_width(), + self.hls_sname(), self.get_outstream_width(), + self.hls_sname(), ) ] elif mem_mode == "decoupled" or mem_mode == "external": self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ """void {}( - hls::stream> &in0, - hls::stream> &weights, - hls::stream> &out + hls::stream> &in0_{}, + hls::stream> &weights_{}, + hls::stream> &out_{} )""".format( self.onnx_node.name, self.get_instream_width(), + self.hls_sname(), self.get_weightstream_width(), + self.hls_sname(), self.get_outstream_width(), + self.hls_sname(), ) ] @@ -1249,10 +1278,10 @@ def pragmas(self): mem_mode = self.get_nodeattr("mem_mode") ram_style_thresholds = self.get_nodeattr("ram_style_thresholds") self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0 name=in0_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() ] self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out name=out_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() ) self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE ap_ctrl_none port=return" @@ -1270,11 +1299,10 @@ def pragmas(self): ) elif mem_mode == "decoupled" or mem_mode == "external": self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=weights name=weights_" - + self.hls_sname() + "#pragma HLS INTERFACE axis port=weights_" + self.hls_sname() ) self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS stream depth=8 variable=weights" + "#pragma HLS stream depth=8 variable=weights_" + self.hls_sname() ) else: diff --git a/src/finn/custom_op/fpgadataflow/pool_batch.py b/src/finn/custom_op/fpgadataflow/pool_batch.py index 813f13e504..8ccfce7820 100644 --- a/src/finn/custom_op/fpgadataflow/pool_batch.py +++ b/src/finn/custom_op/fpgadataflow/pool_batch.py @@ -239,17 +239,28 @@ def read_npy_data(self): npy_in = "%s/input_0.npy" % code_gen_dir self.code_gen_dict["$READNPYDATA$"] = [] self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0,false);' - % (packed_hls_type, elem_hls_type, elem_bits, npy_type, npy_in) + 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s, false);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) ) def strm_decl(self): self.code_gen_dict["$STREAMDECLARATIONS$"] = [] self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0 ("in0");'.format(self.get_instream_width()) + 'hls::stream> in0_{} ("in0_{}");'.format( + self.get_instream_width(), self.hls_sname(), self.hls_sname() + ) ) self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out ("out");'.format(self.get_outstream_width()) + 'hls::stream> out_{} ("out_{}");'.format( + self.get_outstream_width(), self.hls_sname(), self.hls_sname() + ) ) def docompute(self): @@ -281,8 +292,8 @@ def docompute(self): self.code_gen_dict["$DOCOMPUTE$"] += [ """Pool_batch, Slice< {} > > - (in0,out, pool_fxn, OFMDimTotal*numReps);""".format( - i_hls_dt, o_hls_dt + (in0_{}, out_{}, pool_fxn, OFMDimTotal*numReps);""".format( + i_hls_dt, o_hls_dt, self.hls_sname(), self.hls_sname() ) ] @@ -302,12 +313,13 @@ def dataoutstrm(self): oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out, %s, "%s",false);' + 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s", false);' % ( packed_hls_type, elem_hls_type, elem_bits, npy_type, + self.hls_sname(), oshape_cpp_str, npy_out, ) @@ -323,16 +335,22 @@ def blackboxfunction(self): packed_obits = self.get_outstream_width() packed_out_hls_type = "ap_uint<%d>" % packed_obits self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - "void %s(hls::stream<%s > &in0, hls::stream<%s > &out)" - % (self.onnx_node.name, packed_in_hls_type, packed_out_hls_type) + "void %s(hls::stream<%s > &in0_%s, hls::stream<%s > &out_%s)" + % ( + self.onnx_node.name, + packed_in_hls_type, + self.hls_sname(), + packed_out_hls_type, + self.hls_sname(), + ) ] def pragmas(self): self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0 name=in0_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() ] self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out name=out_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() ) self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE ap_ctrl_none port=return" diff --git a/src/finn/custom_op/fpgadataflow/streamingdatawidthconverter_batch.py b/src/finn/custom_op/fpgadataflow/streamingdatawidthconverter_batch.py index a80d2bbefa..dc905658b1 100644 --- a/src/finn/custom_op/fpgadataflow/streamingdatawidthconverter_batch.py +++ b/src/finn/custom_op/fpgadataflow/streamingdatawidthconverter_batch.py @@ -236,14 +236,23 @@ def read_npy_data(self): npy_in = "%s/input_0.npy" % code_gen_dir self.code_gen_dict["$READNPYDATA$"] = [] self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0);' - % (packed_hls_type, elem_hls_type, elem_bits, npy_type, npy_in) + 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) ) def strm_decl(self): self.code_gen_dict["$STREAMDECLARATIONS$"] = [] self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0 ("in0");'.format(self.get_instream_width()) + 'hls::stream> in0_{} ("in0_{}");'.format( + self.get_instream_width(), self.hls_sname(), self.hls_sname() + ) ) if self.needs_lcm(): self.code_gen_dict["$STREAMDECLARATIONS$"].append( @@ -252,7 +261,9 @@ def strm_decl(self): ) ) self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out ("out");'.format(self.get_outstream_width()) + 'hls::stream> out_{} ("out_{}");'.format( + self.get_outstream_width(), self.hls_sname(), self.hls_sname() + ) ) def docompute(self): @@ -263,13 +274,15 @@ def docompute(self): 'hls::stream> intermediate ("intermediate");'.format( self.get_iowidth_lcm() ), - "%s(in0, intermediate, numReps);" % (op), - "%s(intermediate, out, numReps);" - % (op), + "%s(in0_%s, intermediate, numReps);" + % (op, self.hls_sname()), + "%s(intermediate, out_%s, numReps);" + % (op, self.hls_sname()), ] else: self.code_gen_dict["$DOCOMPUTE$"] = [ - "%s(in0, out, numReps);" % (op) + "%s(in0_%s, out_%s, numReps);" + % (op, self.hls_sname(), self.hls_sname()) ] def dataoutstrm(self): @@ -288,12 +301,13 @@ def dataoutstrm(self): oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out, %s, "%s");' + 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' % ( packed_hls_type, elem_hls_type, elem_bits, npy_type, + self.hls_sname(), oshape_cpp_str, npy_out, ) @@ -308,16 +322,22 @@ def blackboxfunction(self): out_packed_bits = self.get_outstream_width() out_packed_hls_type = "ap_uint<%d>" % out_packed_bits self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - "void %s(hls::stream<%s > &in0, hls::stream<%s > &out)" - % (self.onnx_node.name, in_packed_hls_type, out_packed_hls_type) + "void %s(hls::stream<%s > &in0_%s, hls::stream<%s > &out_%s)" + % ( + self.onnx_node.name, + in_packed_hls_type, + self.hls_sname(), + out_packed_hls_type, + self.hls_sname(), + ) ] def pragmas(self): self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0 name=in0_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() ] self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out name=out_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() ) self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE ap_ctrl_none port=return" diff --git a/src/finn/custom_op/fpgadataflow/streamingmaxpool_batch.py b/src/finn/custom_op/fpgadataflow/streamingmaxpool_batch.py index a0e60931ed..78f4095cbe 100755 --- a/src/finn/custom_op/fpgadataflow/streamingmaxpool_batch.py +++ b/src/finn/custom_op/fpgadataflow/streamingmaxpool_batch.py @@ -254,17 +254,28 @@ def read_npy_data(self): npy_in = "%s/input_0.npy" % code_gen_dir self.code_gen_dict["$READNPYDATA$"] = [] self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0);' - % (packed_hls_type, elem_hls_type, elem_bits, npy_type, npy_in) + 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) ) def strm_decl(self): self.code_gen_dict["$STREAMDECLARATIONS$"] = [] self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0 ("in0");'.format(self.get_instream_width()) + 'hls::stream> in0_{} ("in0_{}");'.format( + self.get_instream_width(), self.hls_sname(), self.hls_sname() + ) ) self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out ("out");'.format(self.get_outstream_width()) + 'hls::stream> out_{} ("out_{}");'.format( + self.get_outstream_width(), self.hls_sname(), self.hls_sname() + ) ) def docompute(self): @@ -275,7 +286,8 @@ def docompute(self): else: op = "StreamingMaxPool" self.code_gen_dict["$DOCOMPUTE$"] = [ - "%s(in0, out);" % (op) + "%s(in0_%s, out_%s);" + % (op, self.hls_sname(), self.hls_sname()) ] else: dtype = self.get_input_datatype() @@ -285,14 +297,14 @@ def docompute(self): op = "StreamingMaxPool_Precision_1d" self.code_gen_dict["$DOCOMPUTE$"] = [ """%s(in0, out);""" - % (op, dtype_hls, minval_str) + OutputSize, %s, %s>(in0_%s, out_%s);""" + % (op, dtype_hls, minval_str, self.hls_sname(), self.hls_sname()) ] else: op = "StreamingMaxPool_Precision" self.code_gen_dict["$DOCOMPUTE$"] = [ - "%s(in0, out);" - % (op, dtype_hls, minval_str) + "%s(in0_%s, out_%s);" + % (op, dtype_hls, minval_str, self.hls_sname(), self.hls_sname()) ] def dataoutstrm(self): @@ -311,12 +323,13 @@ def dataoutstrm(self): oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out, %s, "%s");' + 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' % ( packed_hls_type, elem_hls_type, elem_bits, npy_type, + self.hls_sname(), oshape_cpp_str, npy_out, ) @@ -329,16 +342,22 @@ def blackboxfunction(self): packed_bits = self.get_instream_width() packed_hls_type = "ap_uint<%d>" % packed_bits self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - "void %s(hls::stream<%s > &in0, hls::stream<%s > &out)" - % (self.onnx_node.name, packed_hls_type, packed_hls_type) + "void %s(hls::stream<%s > &in0_%s, hls::stream<%s > &out_%s)" + % ( + self.onnx_node.name, + packed_hls_type, + self.hls_sname(), + packed_hls_type, + self.hls_sname(), + ) ] def pragmas(self): self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0 name=in0_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() ] self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out name=out_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() ) self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE ap_ctrl_none port=return" diff --git a/src/finn/custom_op/fpgadataflow/thresholding_batch.py b/src/finn/custom_op/fpgadataflow/thresholding_batch.py index 12e635b3d6..fc5aa61d66 100644 --- a/src/finn/custom_op/fpgadataflow/thresholding_batch.py +++ b/src/finn/custom_op/fpgadataflow/thresholding_batch.py @@ -613,8 +613,15 @@ def read_npy_data(self): self.code_gen_dict["$READNPYDATA$"] = [] # note: the innermost dim is reversed for the input self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0, false);' - % (packed_hls_type, elem_hls_type, elem_bits, npy_type, npy_in) + 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s, false);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) ) mem_mode = self.get_nodeattr("mem_mode") if mem_mode == "decoupled": @@ -627,23 +634,34 @@ def read_npy_data(self): npy_in = "%s/thresholds.npy" % code_gen_dir self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", weights, false, ImgDim1);' - % (packed_hls_type, elem_hls_type, elem_bits, npy_type, npy_in) + 'npy2apintstream<%s, %s, %d, %s>("%s", weights_%s, false, ImgDim1);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) ) def strm_decl(self): self.code_gen_dict["$STREAMDECLARATIONS$"] = [] self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0 ("in0");'.format(self.get_instream_width()) + 'hls::stream> in0_{} ("in0_{}");'.format( + self.get_instream_width(), self.hls_sname(), self.hls_sname() + ) ) self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out ("out");'.format(self.get_outstream_width()) + 'hls::stream> out_{} ("out_{}");'.format( + self.get_outstream_width(), self.hls_sname(), self.hls_sname() + ) ) mem_mode = self.get_nodeattr("mem_mode") if mem_mode == "decoupled": self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> weights ("weights");'.format( - self.get_weightstream_width() + 'hls::stream> weights_{} ("weights_{}");'.format( + self.get_weightstream_width(), self.hls_sname(), self.hls_sname() ) ) @@ -654,10 +672,12 @@ def docompute(self): if mem_mode == "const": self.code_gen_dict["$DOCOMPUTE$"] = [ """{} - (in0, out, threshs, numReps);""".format( + (in0_{}, out_{}, threshs, numReps);""".format( node.op_type, tmpl_args["TSrcI"], tmpl_args["TDstI"], + self.hls_sname(), + self.hls_sname(), ) ] elif mem_mode == "decoupled": @@ -666,10 +686,13 @@ def docompute(self): # - for synth the unit runs continuously anyway (ap_ctrl_none) self.code_gen_dict["$DOCOMPUTE$"] = [ """{} - (in0, out, weights, numReps);""".format( + (in0_{}, out_{}, weights_{}, numReps);""".format( "Thresholding_Stream_Batch", tmpl_args["TSrcI"], tmpl_args["TDstI"], + self.hls_sname(), + self.hls_sname(), + self.hls_sname(), ) ] else: @@ -692,12 +715,13 @@ def dataoutstrm(self): # note: the innermost dim is not reversed for the output self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out, %s, "%s", false);' + 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s", false);' % ( packed_hls_type, elem_hls_type, elem_bits, npy_type, + self.hls_sname(), shape_cpp_str, npy_out, ) @@ -709,24 +733,29 @@ def save_as_npy(self): def blackboxfunction(self): if self.get_nodeattr("mem_mode") == "const": self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - """void {}(hls::stream> &in0, - hls::stream> &out + """void {}(hls::stream> &in0_{}, + hls::stream> &out_{} )""".format( self.onnx_node.name, self.get_instream_width(), + self.hls_sname(), self.get_outstream_width(), + self.hls_sname(), ) ] elif self.get_nodeattr("mem_mode") == "decoupled": self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - """void {}(hls::stream> &in0, - hls::stream> &weights, - hls::stream> &out + """void {}(hls::stream> &in0_{}, + hls::stream> &weights_{}, + hls::stream> &out_{} )""".format( self.onnx_node.name, self.get_instream_width(), + self.hls_sname(), self.get_weightstream_width(), + self.hls_sname(), self.get_outstream_width(), + self.hls_sname(), ) ] else: @@ -734,10 +763,10 @@ def blackboxfunction(self): def pragmas(self): self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0 name=in0_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() ] self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out name=out_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() ) self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE ap_ctrl_none port=return" @@ -789,8 +818,7 @@ def pragmas(self): ) elif self.get_nodeattr("mem_mode") == "decoupled": self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=weights name=weights_" - + self.hls_sname() + "#pragma HLS INTERFACE axis port=weights_" + self.hls_sname() ) def code_generation_ipi(self): diff --git a/src/finn/custom_op/fpgadataflow/upsampler.py b/src/finn/custom_op/fpgadataflow/upsampler.py index b653b9386e..ab5a734e7c 100644 --- a/src/finn/custom_op/fpgadataflow/upsampler.py +++ b/src/finn/custom_op/fpgadataflow/upsampler.py @@ -187,17 +187,28 @@ def read_npy_data(self): npy_in = "%s/input_0.npy" % code_gen_dir self.code_gen_dict["$READNPYDATA$"] = [] self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0);' - % (packed_hls_type, elem_hls_type, elem_bits, npy_type, npy_in) + 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) ) def strm_decl(self): self.code_gen_dict["$STREAMDECLARATIONS$"] = [] self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0 ("in0");'.format(self.get_instream_width()) + 'hls::stream> in0_{} ("in0_{}");'.format( + self.get_instream_width(), self.hls_sname(), self.hls_sname() + ) ) self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out ("out");'.format(self.get_outstream_width()) + 'hls::stream> out_{} ("out_{}");'.format( + self.get_outstream_width(), self.hls_sname(), self.hls_sname() + ) ) def docompute(self): @@ -206,13 +217,15 @@ def docompute(self): if is_2d: self.code_gen_dict["$DOCOMPUTE$"] = [ """UpsampleNearestNeighbour_Batch > (in0, out, numReps);""" + ap_uint > (in0_%s, out_%s, numReps);""" + % (self.hls_sname(), self.hls_sname()) ] else: assert batch == 1, "1D upsampler currently needs numReps=1" self.code_gen_dict["$DOCOMPUTE$"] = [ """UpsampleNearestNeighbour_1D > (in0, out);""" + ap_uint > (in0_%s, out_%s);""" + % (self.hls_sname(), self.hls_sname()) ] def dataoutstrm(self): @@ -231,12 +244,13 @@ def dataoutstrm(self): oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out, %s, "%s");' + 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' % ( packed_hls_type, elem_hls_type, elem_bits, npy_type, + self.hls_sname(), oshape_cpp_str, npy_out, ) @@ -249,16 +263,22 @@ def blackboxfunction(self): packed_bits = self.get_instream_width() packed_hls_type = "ap_uint<%d>" % packed_bits self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - "void %s(hls::stream<%s > &in0, hls::stream<%s > &out)" - % (self.onnx_node.name, packed_hls_type, packed_hls_type) + "void %s(hls::stream<%s > &in0_%s, hls::stream<%s > &out_%s)" + % ( + self.onnx_node.name, + packed_hls_type, + self.hls_sname(), + packed_hls_type, + self.hls_sname(), + ) ] def pragmas(self): self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0 name=in0_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() ] self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out name=out_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() ) self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE ap_ctrl_none port=return" diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index ede572f1a4..64fb5dcbe1 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -802,8 +802,15 @@ def read_npy_data(self): self.code_gen_dict["$READNPYDATA$"] = [] # note: the innermost dim is reversed for the input self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0, false);' - % (packed_hls_type, elem_hls_type, elem_bits, npy_type, npy_in) + 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s, false);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) ) mem_mode = self.get_nodeattr("mem_mode") @@ -817,23 +824,34 @@ def read_npy_data(self): npy_in = "%s/weights.npy" % code_gen_dir self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", weights, false, numReps);' - % (packed_hls_type, elem_hls_type, elem_bits, npy_type, npy_in) + 'npy2apintstream<%s, %s, %d, %s>("%s", weights_%s, false, numReps);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) ) def strm_decl(self): mem_mode = self.get_nodeattr("mem_mode") self.code_gen_dict["$STREAMDECLARATIONS$"] = [] self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0 ("in0");'.format(self.get_instream_width()) + 'hls::stream> in0_{} ("in0_{}");'.format( + self.get_instream_width(), self.hls_sname(), self.hls_sname() + ) ) self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out ("out");'.format(self.get_outstream_width()) + 'hls::stream> out_{} ("out_{}");'.format( + self.get_outstream_width(), self.hls_sname(), self.hls_sname() + ) ) if mem_mode == "decoupled" or mem_mode == "external": self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> weights ("weights");'.format( - self.get_weightstream_width() + 'hls::stream> weights_{} ("weights_{}");'.format( + self.get_weightstream_width(), self.hls_sname(), self.hls_sname() ) ) @@ -854,10 +872,12 @@ def docompute(self): if mem_mode == "const": self.code_gen_dict["$DOCOMPUTE$"] = [ """Vector_Vector_Activate_Batch - (in0, out, weights, {}, numReps, {});""".format( + (in0_{}, out_{}, weights, {}, numReps, {});""".format( tmpl_args["TSrcI"], tmpl_args["TDstI"], tmpl_args["TWeightI"], + self.hls_sname(), + self.hls_sname(), threshs, map_to_hls_mult_style[self.get_nodeattr("resType")], ) @@ -871,12 +891,15 @@ def docompute(self): wdtype_hls_str = export_wdt.get_hls_datatype_str() self.code_gen_dict["$DOCOMPUTE$"] = [ """{} - (in0, out, weights, {}, numReps, {});""".format( + (in0_{}, out_{}, weights_{}, {}, numReps, {});""".format( "Vector_Vector_Activate_Stream_Batch", tmpl_args["TSrcI"], tmpl_args["TDstI"], tmpl_args["TWeightI"], wdtype_hls_str, + self.hls_sname(), + self.hls_sname(), + self.hls_sname(), threshs, map_to_hls_mult_style[self.get_nodeattr("resType")], ) @@ -904,12 +927,13 @@ def dataoutstrm(self): # note: the innermost dim is not reversed for the output self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out, %s, "%s", false);' + 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s", false);' % ( packed_hls_type, elem_hls_type, elem_bits, npy_type, + self.hls_sname(), shape_cpp_str, npy_out, ) @@ -922,25 +946,30 @@ def blackboxfunction(self): mem_mode = self.get_nodeattr("mem_mode") if mem_mode == "const": self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - """void {}(hls::stream> &in0, - hls::stream> &out + """void {}(hls::stream> &in0_{}, + hls::stream> &out_{} )""".format( self.onnx_node.name, self.get_instream_width(), + self.hls_sname(), self.get_outstream_width(), + self.hls_sname(), ) ] elif mem_mode == "decoupled" or mem_mode == "external": self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ """void {}( - hls::stream> &in0, - hls::stream> &weights, - hls::stream> &out + hls::stream> &in0_{}, + hls::stream> &weights_{}, + hls::stream> &out_{} )""".format( self.onnx_node.name, self.get_instream_width(), + self.hls_sname(), self.get_weightstream_width(), + self.hls_sname(), self.get_outstream_width(), + self.hls_sname(), ) ] else: @@ -952,10 +981,10 @@ def blackboxfunction(self): def pragmas(self): mem_mode = self.get_nodeattr("mem_mode") self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0 name=in0_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() ] self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out name=out_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() ) self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE ap_ctrl_none port=return" @@ -973,11 +1002,10 @@ def pragmas(self): ) elif mem_mode == "decoupled" or mem_mode == "external": self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=weights name=weights_" - + self.hls_sname() + "#pragma HLS INTERFACE axis port=weights_" + self.hls_sname() ) self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS stream depth=8 variable=weights" + "#pragma HLS stream depth=8 variable=weights_" + self.hls_sname() ) else: raise Exception( From 7070653b608d2b8eeba196f2434b5cafa4fb1911 Mon Sep 17 00:00:00 2001 From: shashwat1198 Date: Mon, 29 May 2023 13:44:48 +0100 Subject: [PATCH 148/665] Draft PR for folding tutorial --- notebooks/advanced/Folding-Tutorial.ipynb | 2334 +++++++++++++++++++++ notebooks/advanced/finn-hw-arch.png | Bin 0 -> 110452 bytes 2 files changed, 2334 insertions(+) create mode 100644 notebooks/advanced/Folding-Tutorial.ipynb create mode 100644 notebooks/advanced/finn-hw-arch.png diff --git a/notebooks/advanced/Folding-Tutorial.ipynb b/notebooks/advanced/Folding-Tutorial.ipynb new file mode 100644 index 0000000000..409595d0d8 --- /dev/null +++ b/notebooks/advanced/Folding-Tutorial.ipynb @@ -0,0 +1,2334 @@ +{ + "cells": [ + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "# FINN - Folding\n", + "--------------------------------------\n", + "**Note: To run this notebook, you first need to run the build flow in the 3rd cybersecurity notebook as we utilize one of the intermediate models generated in that process in this notebook.** \n", + "\n", + "This notebook describes the use of FINN parallelization parameters (PE & SIMD) to efficiently streamline models so as to extract the maximum performance out of them.\n", + "\n", + "We'll use the utility function `showInNetron()` to visualize and interact with our network in the Jupyter Notebook and `showSrc()` to show source code of FINN library calls." + ] + }, + { + "cell_type": "code", + "execution_count": 1, + "metadata": {}, + "outputs": [], + "source": [ + "from finn.util.visualization import showInNetron, showSrc" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "Note: The build_flow in the cybsec_mlp notebook comprises a transformation step `step_target_fps_parallelization` that automatically sets custom parallelization parameters needed to achieve a given `target_fps` by invoking the `SetFolding` transformation.\n", + "\n", + "More details of the above step can be found here: https://github.com/Xilinx/finn/blob/main/src/finn/builder/build_dataflow_steps.py#L394\n", + "\n", + "This notebook shows the manual version of this step and explains how these attributes can improve performance and what are their effects on resource utilization for developers who need to maximize the performance of their network. \n", + "\n", + "* input : the 'step_convert_to_hls.onnx' file (we pick has gone through a series of transformation passes) to be analyzed in terms of clock cycles and resource utilization per layer\n", + "* analyze the estimated execution clock cycles and the resource utilization of each layer in the network" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "### FINN-style Dataflow Architectures \n", + "\n", + "We start with a quick recap of FINN-style dataflow architectures. The key idea in such architectures is to parallelize across layers as well as within layers by dedicating a proportionate amount of compute resources to each layer, as illustrated in the figure below taken from the [FINN-R paper](https://arxiv.org/pdf/1809.04570.pdf):\n", + "\n", + "![](finn-hw-arch.png)\n", + "\n", + "In practice, the compute arrays are instantiated by function calls to optimized Vitis HLS building blocks from the [finn-hlslib](https://github.com/Xilinx/finn-hlslib) library. As these function calls can only handle certain patterns/cases, we need to transform the network into an appropriate form so that we can replace network layers with these function calls, which is the goal of the network preparation process." + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "# Part-1 : Loading the ONNX model.\n", + "\n", + "The 'onnx' file needs to go through multiple transformations before it can be fed into our estimation functions.\n", + "\n", + "The 'onnx' file loaded here is taken from the cybersecurity end2end example notebook. The build_step in the notebook comprises several series of transformations that take place before the onnx file is used for bitstream generation.\n", + "We pick the onnx file `step_convert_to_hls` to which the necessary transformations have been applied for this notebook (Network layers mapped to necessary FINN-HLS blocks. In this case, the `MatrixVectorActivation` Units). \n", + "\n", + "More information on these transformations can be found in the tfc_end2end_example notebook.\n", + "\n", + "To interact with the 'onnx' file we use the `ModelWrapper()` helper function. This function gives access to different model attributes and allows us to apply custom tranformations to it.\n", + "In the below cell, we load our onnx file and view the cybersecurity MLP network in netron." + ] + }, + { + "cell_type": "code", + "execution_count": 2, + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "Serving './step_convert_to_hls_folding.onnx' at http://0.0.0.0:5901\n" + ] + }, + { + "data": { + "text/html": [ + "\n", + " \n", + " " + ], + "text/plain": [ + "" + ] + }, + "execution_count": 2, + "metadata": {}, + "output_type": "execute_result" + } + ], + "source": [ + "from qonnx.core.modelwrapper import ModelWrapper\n", + "model = ModelWrapper(\"./step_convert_to_hls.onnx\")\n", + "\n", + "showInNetron(\"./step_convert_to_hls.onnx\",localhost_url='xirxlabs53')" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "# Part 2 : Parallelisation Attributes : PE & SIMD" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "**PE & SIMD represent the amount of time-multiplexity to which we expose each of our network layers. \n", + "These parallelization attributes are subject to certain constraints and should be selected accordingly.**\n", + "\n", + "We see how they work through an example of a multiplication computation (Matrix-Vector) in the `MatrixVectorActivation` layer looks like.\n", + "\n", + "From the below block diagram, we observe that `SIMD` represents the parallelism within a single dot-product computation (the number of multiplications is a single clock cycle), while `PE` refers to how many such (Matrix-Vector?) dot-products execute in parallel.\n", + "\n", + "If `PE` & `SIMD` are set to 2 & 4 for a given layer that means, that within a dot-product 4 multiplications will happen in parallel and 2 such dot-products will execute in parallel.\n", + "\n", + "The base case of `PE` & `SIMD` both set as 1 suggest that there will be no parallelization therefore the resource utilization would be low (resources can be resued for differnt multiplication operations) when compared to settings where network layers have higher `PE` & `SIMD` values." + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "

\n", + "Question in the third line of the above cell.\n", + "
" + ] + }, + { + "attachments": { + "MVA-1.png": { + "image/png": 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fGps+Ka9Px1LDdO3NW+k3xR2BDfXrSaQgxO/ixTN432/oqMrXnM+htbl9Ul6fjkV5iboKu5V+cy4B9et7wwPpVzWfW7wFdLO6uihOPnSllcZ6c977jRXfX+Gt9Pua8XMX1K/vZw+kX879ppqDo99Ucr3Iu5V+/xn/+MokBtSvx0b9yr2Hc781Nn0acfbpWGqYrr15K/3+msMD0hJOmPr10Khfue9QvzU2fVJen46lhunam7fS71frT9HLJKhfz+aB9Mu5X7m3N5doJx9yJvuajwAvpX5LZrfS76jl1+DKA4ysUL8eygPpl3O/kW6u2kX9qjD1NehW+pUV2k5KzpVLIrXygZMRKGe7eOPZGZJL79AqNNauNpej3xi9m++jflWXIGWkieVg0e6g8Qz8jtyUDDxHOVPrr5QuVhf1RDee/evFg+WL9xonHwoO9k/qt0TRtJKiOiwHi3bHimfgYkzJwHOUd+n6C6SL1UU9lX7T7zRqemOklFG/JTXqt0TRtJKiOiwHi3bHimfgYkzJwHOUY1V/gXSxuqgn0u+v+Wjq31cto35L3NRviaJpJUV1WA4W7Y4Vz8DFmJKB5yhl6S+QLlYX9UT6HYl3Go1et8t/L4fOP/pyv0Lz9vU1Ouyw/z7++nor9n3ZZfRZFsRWKnmx4mIf9VuyoX5LFE0rKarDcrBod6x4Bi7GlAw8RylLf4F0sbqoJ9Lvnzl7OLfH+ftRPKN7Xvz4187/SvnUmHH5i2Jz47+gal+KZbiVDfytup+J+vXo3R/Ub4miaSVFdVgOFu2OFc/AxZiSgecoZ2r9BdLF6qKeSL8DY0qhVjr6u/0h6/lqtTNm6P1b6Nf9aM37IWo/CfpduB/FHtuioRsNx5Y3+wPTsf21fdRvCYT6LVE0raSoDsvBot2x4hm4GFMy8BzlWNVfIF2sLuqZ9Ds0X5EOvjFTb+XZpHgGy27xY6OmZmJWh+hvsziMfos9n8uF2QjjX6tt6vfATfdC/ao4pagOy8Gi3UHjGbgYUzLwHKUs/ZXSxeqinkm/69jvG3wZc5j1fTUL59Qw+WB/sdzTHgzmZnrQ7/ywx/6ebvx3crdmR/0eIClfqF8VqBTVYTlYtDtoPAMXY0oGnqOUpb9Sulhd1DPpN3KwBScAACAASURBVPr1mVk5JfH5MXVTCjtv1rXZbg6zD5+Lj5+T0a/veBM7ZP58CctnMRj+Wmz+Ub++k6r/oH5VqFJUh+Vg0e6g8QxcjCkZeI5yptZfKV2sLuqZ9BudcP0z/qO241sgjH6328Psw7fZBv2G0a/9nVwzc8PicvEl+42Z/Yr3VxybGAyih1INeJ516ld1rVNUh+Vg0e6g8QxcjCkZeI5yrOqvlC5WF/VM+o2b8cfO1v68H6dyi7lfO/q1P0XuJ4WnZhT0u/L83R8T90thq3FYJr5kZQfOvxz9lpBUK9SvClOK6rAcLNodNJ6BizElA89RytJfKV2sLuqZ9Ls3sd8W31v/2mX3c/hcrhz9Dj787MPnYmf7mRvdzv2f/hIMNpHJ33f3BNl36rcgpP2T+lWRSlEdloNFu4PGM3AxpmTgOUpZ+iuli9VFPZN+7e0M0Q/Mvn42TsCLuf8MLtz5sB0Usw9LO84N+l15/u6PTW3Kwu76Gy/sNzU4+i0Z6VaoXxWnFNVhOVi0O2g8AxdjSgaeo5yp9VdKF6uLeir92o/F/HTCeX//+17Z23l3rvQ4+n3z9z5M7ZA56Lec+x0Mz01e/HI59XtOt3HPnxk3lndVCD0asnYQcq5cUqvCbfKBkxEoZ7uin5ifRZ3uQHOUY1XfiC5WF/VU+rUfjc2/RsflOOFrue63xs3nHu98cKvv9ktZ9kE9Qb8rz98FG/d85tVmePhvs7Kfpq33n/tPp/iTekPKySs/eitxQMIqs/JXctqVc+WSyBFTvxEoZ7tQlboK0BylLP2x6WJ1UU+l38Fs4WYZyuWfxbmd21sYiqWY2z2Ofv3sg5t7KPVbjn7tjb92ouHkzgf7NeVyiX29I7TiX6nfEkfOj/6UlSSsQKKs1S/nyiW1Ktwm9RuBcrYLVamrAM1RytIfmy5WF/Vc+h3MCklOisV9q7iwree69Q8Eruj3z977sHbfyjgb/c7909Ne3v7sf/6Pl3AbhP2C8nhM/Xqgqj/8B5aqyMsGQaKsNS3nyiW1Ktwm9RuBcrYLVamrAM1RztT6Y9PF6qKeTL97O2Bd/Vav8NZMwvMbPvx8bkW/g7Upfkoj6DeMfr/93EO1mnKdc78lCt3K942egv9SfqtRd5zVKFmyckk1/7COfHSFxIamsBws2rWBZ+BiTMnAc5RjVQ9WF6uLejL92m8Sn8jXPnBrbMavbrJ2NDeLk2+92X1LM/a/wRf0u9rv959/7ysjK4P69X1U/8fN5mHKrzvqjzVEypKVS0Ju5RXRFxIbmsBysGjXBp6BizElA89RytKD1cXqop5Lv7+L88c+uPngxWY3tBO3bi64cueDvZfMFjk1B/2Wk7tT8dO1d37rzXdS9R8p72F15U2Bk9hd4E0JxzJZsnLJMbtcQ04diQ0NYDlYtGsDz8DFmJKB5yhl6cHqYnVRz6XfykRv6KJ2/OvuObPLvJixrU4+2NkHP99wot/FZh4eRXmspFx73NGve9S8XUbFY5HtPxeKbf9n2FdiOKy8fQl3+h0D18Xfescd11r7iD4AT9W6LFm5JFIxoi8kNjSF5WDRrg08AxdjSgaeo5yp9WB1sbqop9LvuxnHR62j3/dZvCT05Au/3uxf3BnnUfwlZf+emqz8bLn790JY3DM6I8to0T7CHJsw9x6poMtdUz+vlNSCLFm5JNIQoi8kNjSF5WDRrg08AxdjSgaeoxyrerC6WF1Ub/S7Pt6Oi629FTcshC7X9Lo6/6paU3iHZfep34l72vzQTtaMnTGHpth2+7bRQe7ePsO+za2zG33rwslD+Euj/brLkpVLIrUi+kJiQ1NYDhbt2sAzcDGmZOA5Sll6sLpYXVRv9Gtv2EpepqG/Nb/aX60o7/Ftjuy89B71Owmjxe/i6fND/y2VJlT2iyyt+g3PlWuqp5uy9/SfXpUlK5dETgLRFxIbmsJysGjXBp6BizElA89RytKD1cXqovqj38O9uPjLQr4NIfTD4lU3LXua09HWPeq3uAnEAbFatVM1rfq1Py0dfcjRCdOd+T7Zvt7GfpE8+StLVi6JnBiiLyQ2NIXlYNGuDTwDF2NKBp4zB3qhLpZzv6EXhtftIty3G/bc7PU+9eu+k+0W+4h6+zFlTb/78Oj5l5diGn0/XNjHIrdMPszMIjpvUTTU7Z+r8uek0HZkycolkTYQfSGxoSksB4t2baBfbkjLuUYrU+DzX13snY1+lRMIoWdVXotvRlR2SKvFM3Gk0qvuv0f9lpMP9qlu7ivXG7OsmnN5nDsqfqXJvW1aR7/T9AnY7Av2ZRatX0+MNyJLVi6J1IQID4kNTWE5WLRr4xpivE4rOqUWXHWxujFybyYfrqDf3flNv6GjXvv1HvV7nHwofgavNvpdTsaTcfH/xuH8ds8qahv92l8xle5Zu8IlWZlNWuuyZOWSyPkgwutedXgLeIZ7TsprhETTLjwDb0Wn1OIodbG6qGfS78TNWPZjuU/9+smHzy/7pT93z8DQLMKPfXjfnpL9m0ys2lr0a78GEyY0TrOvs/W5McOk8a8sWbkkckqX0G9lzuc4+3NYs7++crZP3qGLfqvclzS3PwmDLvaZ29UqWtNn9jEt2xm62B+rgVLsDzwe4t9bFxvbGvP+rot6X2o/uIp0n8vtUk8gRJrU5uZ8yT/SbNaue9Rv5d4UO651+i2X8JvQFSZr/2FG4+TDp/0Ib1VJuf7qn33O/vx1VnGA7hhkyb6VTLhCAu0Epk+j35HqZ4B077/cqHvU7+FrF4vx9NXP+donzo/eDssZj2XxdcHY6Pf1xy+rufV5+7Phzmq+6I7Pn9N3SOTvkVh7fdKveKvQwn2bfiEW1wq00WN3m/dhWVTu/A772l4XplpDW/Rw+PExMeMPdJkYmwgsC7M5RK9bl4nZtMas17qo9epp9HurJxvG3r/3qd/lYG//C0tt7vd1Yx89X/y/G3yZ8Z97+Lz9jO7zmFFkVh+MbBa3nHxwx/O3nW6GpYqG4eSaX5v0O25OrZZeYvKhWl99HZubxaJdW3gGPiubkoHnKGdqPWBdrC7qieZ+//XiL5riLXKP+j3e+VCcQ02/J3c+2GmFcqkLdlmMfv2f9vmfs6K2u/qT+vWXi/qVey31W2PzWvmh4lrR1TfvUb/HOx8KXDX9ftp5iMOz5/8Gy8OHcnZ6YVjX7wnsH3d/xN0t1K+/ZNSv3HOp3xob6rcGBNyc1O5SsPqtzyuc1Rib+z0Jekn/6tlJPdfdoH497yT9LnjjWaWz9uOf5Nq7FyoHXq5qc/s04uzTsZQgW1bOR79b+/T5wyLkturXzh9uhdwe76Z+/cVJ0i/v+612bOq3SuNa6/ep39NpBHvTVrksBHCNN575HP/tDCG7t7upX39prqRfeLxsP3oDc5RTBf6sdbG6qCf66K1PyuvTsWgld/7RW2lfI+u35ZkP9gdFpFztcd0gjvr10K+kX3i8zDsfwPeEdgIhVq02t0/K69OxxJhecd84+bljVzzIWlPUrwdC/db6RWWTo98KDLfaJ+X16VhqmK69ebMfG8o4UerXw6N+5T5E/dbY9El5fboLo4bp2psp7+FrH2O9PerXE0m5dOisLD6P6w4NbUUpS3/WulhdFOd+PdJr/9GPDzyvfdbR9rY3fORk9IAUO6lfDylJv/BMLp94puiReSHa+dtYK9rcPo1++/QF6BjTK+7r02XRnjb160lRv3KH4ei3xqZP7/NZ+u+M1c7q7jfv8R8C1K/vdtSv/O6jfmts+qRf+f1bO+jH37zHfwjIl08uiVzJp3zkDnhHLj6P60Bz7jfS3eRd2gmEWA3a3D7p1z4KLHYqkX2j1+3y38uhYPTlfp3h7evL/tbPYXn5+nK31tp9bhk1PFD+82sW6gnJfXi9x38IyJKVSyKsn1K/nPut9oR+/NtPq9DqkYd1bW6f9DuYtP0GZXF2v/a3gt0yL34UZ+c/prJPbByXT1uwzwxzPyBqX4pluI0b+M9HHOoJ6Prw+mUiv5XRhwNrOAZZsnJJpDrqNwLlbBc/ejtDcukdWoXG2tXm9kq/ut+de7cPtJ6vVjtjht6/hX7XVrTvBxJ7+8zyQr8L9+hq90j0YeyLZqOxGa5W9inUcTnHuF5pHySsKx1TWzPyMcslkTqp3wiUs13U7xmSS+/QKjTWrja3V/rV9amNmfph7mxSPCxzt3A/sjY1k/JHeuxvVR70u/JsPpf2wf0Rxa59TX9DX0GM4s32QcK62VGeNiwfs1xyWoPfekr9cu632hM4+VClcbX1bSnQhia/jDnM1r6ahXNqmHwofmrYZc7N9KBfNwZ2i/0V+PNniP2aiXfysn93XPTpJ/gKgu1/ypKVSyK1PqV+Ofdb7QnUb5XG1dbfNY8ZnxlzmOP9/Ji6KQX786n2T/szrpvD7MPn4uPnZPRri3/MxGZ9lj9p+2nFGx7ruB/17tO3lzt85o4sWbkk0rWo3wiUs126fyiepqE5ytvEfCO6WF0Uv/V2et2utfVSDmwbWvwrftH9GBFGv9sweP4226DfMPodjPwP+JSfxfm5YT/V/BKbFD5WfqM16lcFPuUeWywHi3YHjWe4f669qs73GIRn4K0oZekPSheri6J+j9f5qmvr2m9HRBv/sR+k/bz7aQNfXsz92tHvyI9w3TTwKOh3Vdbgf5Zidfi5n/F4YksW5u/bPp938VPeMVFG33qF+lVdgRTVYTlYtDtoPMOKkXO/1evNyYcqjeutv5pNuwr31r922f18FQdWjn4HH3724XOxs3MNxZ0P5eh3sDmb/N3b+WAzWVsB79obvR4D3xL1qwKeojosB4t2B41n4OPSlAw8RzlW9VdKF6uL4uhX1fkvH7QfmvnX6Lgch7gnbX39+B+VWMz9nG2482E7KGYflnYIHfS7KvM2Zw+xsVMdZmVbsDeyuVsnerVQv6rLkaI6LAeLdgeNZ+BiTMnAc5Sy9FdKF6uLon5Vnb+DoNnCj2zDH//EJv6+V/Z2Xj9sPY5+38zEJkzNX6nf4+h3eDb6tfotxtpLnyY2dYsC6ldFPUV1WA4W7Q4az8DFmJKB5yhl6a+ULlYXRf2qOn8XQV/u6xPGTIolfI8i2tJ+a/xUcXnng7sJ4n3w4m6fOBv92pkG++nGajM8/LdZDdzkg6/Yfph3mMeItnOLndSvinqK6rAcLNodNJ5hxci53+r15txvlcY11z/tl4dXjTLczmfhgOZ+hvc4+vWzD27uodRvOfq1N/7aR0Kc3vlQ/k7bwpRVhqpv/Er9qi5AiuqwHCzaHTSegY9LUzLwHOVY1V8pXawuiqNfVefvIsh+d6JFhYVtfdtbM7WvFf3+2Xsf1u5bGWej37n/asXL25/9z/9hg+zNEr4aOwvRt7vPqF9V50pRHZaDRbuDxjNwMaZk4DlKWforpYvVRVG/qs7fQdC/9nkAe7dCkOWH92dFv9aoxbetg37D6Pfbzz3UDjh82+3VDGslN9+kflWXIEV1WA4W7Q4az8DFmJKB5yhl6a+ULlYXRf2qOn8HQYVQGyt+GZvxq7slYjQ3i5Nvvdl9SzP2d7AH/a72+/3n3/vK+HFyrd6Xib/l4e/8U7la4PU3n1i/iL6Q2HARsRws2rWBZ1gxcu43XB73yrnfKo3rrf+rPDRSbNXdHbHY7Ib2Ezp/Z0R19Gs/RfPPgQj69Z/juT+msXvY/i3MbvszMWve9yvS1hfIXy2WSyK1I/pCYkNTWA4W7drAM/BxaUoGnqMcq3qwulhdFPUb+uqVX+dnd4fFDuDF3XNml3nxEV1Vv3b2wc83nOh3sZkLt1D4JwcvVr2zr719YxE7817vkyUrl0ROCNEXEhuawnKwaNcGnoGLMSUDz1HK0oPVxeqiqN/QV6/7am8FO/5iRWPTo9/3WWw825gUK3x7/71IPbG6M/ZRvyp4KarDcrBod9B4Bi7GlAw8RylLf6V0sboo6lfV+S8e9N6/Jz9e/Bx1FVK/Kk4pqsNysGh30HiGFSPnfqvXm3O/VRpXWw+PLLtag71tiPpVXZoU1WE5WLQ7aDwDH5emZOA5yrGqv1K6WF1Ub0a/6+PjD7C1t+KW2PY+3Ktfu5jCz91rP8H7jKB+VdctRXVYDhbtDhrPwMWYkoHnKGXpr5QuVhfVG/3a3yxLXtw3EtqXXul32Lsv/7YD7CaC+lVxTVEdloNFu4PGM3AxpmTgOUpZ+iuli9VF9Ue/h2cf4C+L2I2ukS7dK/0a08ePwSLUOt9F/aoQp6gOy8Gi3UHjGVaMnPutXm/O/VZpXGvdfmX4Wk31vR3qV3WFUlSH5WDR7qDxDHxcmpKB5yjHqv5K6WJ1Ub0Z/eomEGI99R5/6XhmNrFTecZ91K/qqqeoDsvBot1B4xm4GFMy8BylLP2V0sXqoqhfVee/dNA/zS9tXrrRftZH/aquS4rqsBws2h30NX6F7TqtrM2v6iq4IF0s9VsD2qe539fiG2u1I3zKTepXddlxOaKjU7yFJP32cu7X/xSt6jq4xw5qVE391nD2Sb99OpYapmtvUr8q4kmqg+5uxFvAM9wPtMi/6xIHgWfgreiUWhyfLlY3RubkQ/yad7yX+i0BU78liqaVFNVhOVi0O1Y8AxdjSgaeo1NqcX10sboo6repz3dWRv2WaKnfEkXTSorqsBws2h0rnoGLMSUDz1HK0l8gXawuivpt6vOdlVG/JVrqt0TRtJKiOiwHi3bHit/Di4sxJQPPUcrSXyBdrC6K+m3q852VUb8lWuq3RNG0gssRHZ3iLeAZuBhTMvAcpSz9BdLF6qKo36Y+31kZ9VuipX5LFE0rKSNNLAeLdsdK/cpXjPqtsemT8vp0LDVM196kflXEU1SH5WDR7qDxDHxcmpKB5yhl6a+ULlYXxdGvqvNfOoj6LYlSvyWKphVJdfsXeZmbpVx4VqKLfqs8j9D+Ykt1s1Iir67NUi6MlMxmO7OdoQua82GWhybeW5eN2bbGvL/rot6XygfWNHWN/DLtF4djLWlz+6S8Ph1LjOkV9z2afpOf28fEJyQwpX6v6JrQFPUbSDzcb71d2yENjwi0P8baUFov0kWPh8dlYSbHDeXawlRraE/6+FiYzQe6oDnH+HXrMjEfrTHrtS5qvaJ+SxNcb4X6LVk/2uh3XJ5Z6wryNV9p8qGpESwHi3bt4hn4rGxKBp6jnKn1sHWxuijO/Tb1387KqN8SLfVbomhaSVEdloNFu2PFM3AxpmTgOUpZ+guki9VFUb9Nfb6zMuq3REv9liiaVlJUh+Vg0e5Y8QxcjCkZeI5Slv4C6WJ1UdRvU5/vrIz6LdFSvyWKphX8rlxUj7hMU44Jf4AOnkH9NvWkSJn27oVI6kCb2yfl9elYYkyvuI/6VcHG5XgF/UJPVCtOE5cpntGtfnXPMtNFPc/od98n5fXpWFTv/u6CqF8V2yT9Qs/WxceyKceEyxTP6Fa/umkFXdTz6HewNT+qjn6NIOq3pEz9liiaVlJUh+Vg0e5Y8QxcjCkZeI5Slv4C6WJ1UU+k3x+zberfVy2jfkvc1G+JomkFH5uiesRlmnJM+FgWz6B+m3pSpEw7fxtJVc/9IndZxtq55D7qt6RJ/ZYomlZwOV5Bv08596sb1+qinmj0m/K3aNMbIqeM+i3pUb8liqaVJP1y7rcJaaVMKUufoYvVRT2RfjdmVgF+21Xqt+RP/ZYomlaS9AuNTvEW8Ax8WiAlA89RytJfIF2sLuqJ9GvMS1P/vmoZ9Vvipn5LFE0rKfOsmB6xaHesKceE/xsUz6B+m3pSpOwKc79fBvg2fuQQL7qL+i1xUr8liqYVXI6c+23ieVqmHKv6JF2sLup5Rr9LMz9Ffsst6rekT/2WKJpWkvTLud8mpJUypSx9hi5WF/U8+rVPk67wvvEq9VteAOq3RNG0kqRfzv02Ia2UKWXpM3Sxuqin0e9+Yr4qvG+8Sv2WF4D6LVE0raTMs2LKxqLdsaYcEz6Ti2dw7repJ0XKup/7fTUfkXZvtYv6LclTvyWKphVcjpz7beJ5WqYcq/okXawu6mlGv7s+zT0MqN+y+1O/JYqmlST9cu63CWmlTClLn6GL1UU9i35fzWRfwX3rVeq3vALUb4miaSVJv5z7bUJaKVPK0mfoYnVRT6Lf2aRXg1+Ofo9dn/o9smhYS5lnxZSNRbtDTTkmfCYXz+Dcb0NHihV1PPf7O+nTXWcWAEe/ZS+gfksUTSu4HDn328TztEw5VvVJulhd1KOOfj9H5TJ7nRoz7dPUA/Vb6fxPrF9EqUhsoIuNTrFo10bKMeFjWTyDo9/QA5SvFx/9Lk9+73ux7Zd9Ofo99gvq98iiYS1FdVgOFu0OFc/AxZiSgecox6r++uhidVGPOvpdTsrlY7r9a+jXNyni5EOJnfotUTSt4GNTVI+4TFOOCR/L4hnUb1NPipRdfPQbaaNPu6jf8mpQvyWKphVcjlfQL3RnRXF2uEzxDOq3qSdFyl7NupyrBVfetmYaqbHfu6jf8vpQvyWKppUk/fK+3yaklTLlVIHP0MXqonoz+TA5mazFNqjfSk+6t1XqV3XFkvQLjU7xFvAMfFyakoHnKGX5wPot52rRlQVHv6o3cE+Dnlm/wOg0ZZ4V0yMW7XpTyjHhUwl4BvULvtc59wsCe5zwZ9YvMDrF5ci5X/2b5OlHv+kTCDnq1l+gy0Zy7rfkSf2WKJpWkvQLjK5TxrIpx4SPZfEMjn6belKkLEehObmRQ7nKLuq3xLw3ply/l5U38ZdT5JLIuSH6QmJDU1gOFu3awDNwMaZk4Dkc/YY+A79SvzCyXiUY07PvxLTTkSUrl0RqReZOkdjQFKZHLNq1kXJM+FgWz6B+Qw9QvuYoNCdXeXgXD+Po94h0Ynr3rZjjwcXXZMnKJZGaEOEhsaEpLAeLdm3gGbgYUzLwHI5+Q5+BX6lfGFmvEjZm1qvjURyMLFm5JFItoi8kNjSFjU6xaNdGyjHhY1k8g/oNPUD5mqPQnFzl4V08jKPfI9Kp+T5u3MeaLFm5JHJmiL6Q2NAUloNFuzbwDFyMKRl4Dke/oc/Ar9QvjKxXCat+PYpZw0aWrFwSqRcZbyKxoSlMj1i0a+Ma49LrtLIBfghSF6sU+r9efGkhR6E5uaGjXvuVo98j8a1ZHTfuY02WrFwSOTNEeEhsaArLwaJdG9RvIH3+Sv2eM+nNHur3eCn+mfVx4z7WZMnKJZEzQ4TXverwFvCMwUCppQotPANvRTeiLQ5KF6uL6s0zH/i1i0qPe6pV+72Le7vzTJasXBK5ptRvBMrZLur3DMmld+RMIOTkXvo8tPVx9FshNTS/la17WJUlK5dEzguZz00ZaWI5WLQ7HTwDH5emZOA5yrGqv4a6WF0UR7+Rt0X3u6jfCuOV+als3cOqLFm5JHJeHP1GoJztus7oV3/zo+5GSer37EL2Zwf1W7kWMzO5s9kHWbJySeWEwyr1G0g0vV5Hv19Nh3BSphOrLoqj3xO019qgfqukN/d265ksWbmkesKHdeo3AuVs173qVzWe5o1nZ9f7Cjuo3yrkVzN8qW73fl2WrFwSOSnO/UagnO26V/2qxtPU79n1vsIO6rcKeb8z87uafpAlK5dUT/iwztFvBMrZLur3DMmld+TcvZCTe+nz0NZH/Z6Q+lqY+T2Nf2XJyiUnJ1xsUL8RKGe7qN/PMya6Heq3VI5Cc3J1p3H5KOr3lOnvwox/fis/snpa3LctWbJySeQcqN8IlLNd19GvaqbWH9vV73x4+VidQdHs+J3804TZmByF5uQqD+/iYdRvDelod/rrqrXinm3+DXfCEWH6BX6NQrrHdv8iL2vzKheeleii3yp/R67NsrKlW/0w37rAQ9Rs9mGWM3RBc4bm+9DEe+syNMvWmPd3XdT7sv2ZD38fJulr+XZIY5T+zVFoTq7wJup8N/V7hvh3tRsef2X1rPhOdryd/i3CLRJoJDBt1e/fxlWwgvu/s6/WvzkKzcmFT+pCCdTvhUD2rZrr6/f4V9bZmjGLs33yDl30eHhc7IzRcUO5ZsCcj4+F2XygC5pzjF+3Lguza41Zr3VR61Wbft3Y1y0rsKcX9lX6N0ehObngOV0snPq9GMp+VYRNPgC/dCxNPjSdPpaDRbt28Qz868ApGXiO8ksSHrYuVhfV/rWLt2GhX9C/wb66Z2nnKDQnt6nzdllG/XZJ94Z1U78t8PEP0vCMR9LvIMm/mH350VtLp2XxnRCgflsuFC5TPOOh9Dv4O4x/F6sWtMdi0L7U7xEd1+6ZAPXbcvVwmeIZj6VffPyL2pf6bem0LL4TAtRvy4XCZYpnpOj38vf9qmpUfekYHP/C9qV+Wzoti++EAKbfC9z328QF+2gMi3bt4hm4GFMy8BzlB2Ueti5WF9X+0ZtvEpr/xe1L/XrK/OPuCWD65Z0Pigt+ndGv6gE5/mh1YtVFKfWLzP8m2Jf6VXRDhtwBAeq35SLhMsUzHm70Oxi8+S9fKO7/TbEv9dvSaVl8JwSo35YLhcsUz3hA/Zafv7Xc/5BkX+q3pdOy+E4IYPrl3K/islK/HpJq/JtmX+pX0Q0ZcgcEMP1y7ldxSa+jX9V9Cv5otU88U9WouvOhgBQ+f2sY/ybal/pVdEOG3AEB6rflIuEyxTMecfLBYg33n5mffRxyqn2p3zhP7r03AtRvyxXDZYpnPKh+j/5dRSEn25f6jfLkzrsjAOr3W32CKffYYjlYtDtwPAMXY0oGnqO8TcxfLV2sLkp749mhm5Tzv7Hxb7p9qd8DX77cOQFIv4i+kNjAEMvBol0beAYuxpQMPEcpSw9WF6uLAvVb3v8Qef5Zhn2p3/CO4et9E6B+W64fPpWAZzyufo/zD/Xxb459qd+WTsviOyFA/bZcKFymeEaKflX3Kfhzu9WdDwXY4+dvJ6Cz7Ev9nrDkRm8JLJfLwxv1e7mMzNxSvy2XDpcpnpGi335/6bgCtfTvB8UOEQAAIABJREFUqrIzz77UbwUlV3tMwH7tc1sc3tqY9fmBUr/nTE724DLFMx5av5X5hxJspn2p35IkV3pNgPqtXB5+9FaBUVvt5qM338jZ+DfXvtRv7eJxs6cEqN/KhaF+KzBqqx3qtz7+zbYv9Vu7eNzsKQHqt3JhqN8KjNpql/odFD8+b/viyraab1/qt3bxuNlTAtRv5cI8kn7v5c6HAv/x+xeXsC/1W+nUXO0xAeq3cnEeSb93c+dDwb/073xhu6RbIrfhVC5V82rOj8Xn5DYfVXel/KH57th2WrPt55u5X8a884H6lftap5MPttnSv969efa1o9/1KHF525qpTKGnJdRvTy9M22EdOnvxwhvP/rXxOivHbyPDMx77xrMD0vL+B98Xc8a+A6vfyUnHxjao37Nezh3dEDjpmNQv9St1s65Hv/b5k+H3h2yfzLOv02/ysuDoV+oD3H9pArarr37ff+3/H5x84OSD3L261+/x+Tu59uVHb/J1ZEmfCFj98ltv4YI8kn7v684HfwXKO87MT7giia85H5/l5CYebnYa536zEd6mAuq3wv2R9Htndz7Yq/Bbma/N9G+OQnNyK33pqqvU71VxX64x6rfCkvqtwKitdj75cBz72j6ZOf7NUWhObo3Z1Tap36uhvmxD1G+F59q8V7Z0q/h9DHjGM9z5cGrf4vtvuisQicpRaE5u5FCusov6vQrmyzdC/VaYXkOMuErdAaJHNjZvlfNqXtXFdjz6Le27DPc/5Mw/5Cg0J7cZdHel1G93bDut+Wb6TRlpYjlYtKOMSi4t5xqt6JRa9CxdbLf6Le37XX/+TnGM4J85Cs3JBQ/zYuHbzMmaix0IK8II7Nbr1yLjZ72LDDg6e95v9xLCW8AzBgOllipXBc/AW9EptTgoXawuCv2ttwOWin0r9/9GumMFY9NqjkJzcpuOqcsy6rdLujesm/ptgY/LFM94dP2e2PcS/s1RaE5uS1/prPgn3D3aWQus+CYEqN8W7LhM8YwH12/Nvhfwb45Cc3Jb+kpnxdRvZ2hvWzH128Iflyme8dj6PbNvvn9zFJqT29JXOiuem8MMYmctsOKbEKB+W7DjMsUzHlq/EftWnn+WNv+bo9Cc3Ja+0lkx/ilzZ4fCii9JgPptoYnLFM94ZP1G7Zs7/s1RaE5uS1/prHhoRp3VzYpvSID6bYG/MfqnKxRV4RlOv1gryvsU/AHpYnVR8J0Pgn2tf4f2nki3pIx/cxSak9vSV7oq/jRm31XdrPeWBKjfFvr4WBbPeNzRr2jfvPFvjkJzclv6SlfFM7PpqmrWe1MC1G8LflymeMbD6rfBvln+zVFoTm5LX+mqeGnmXVXNem9KgPptwY/LFM94VP022jfHvzkKzclt6StdFU9540NXaG9cL/XbcgFwmeIZD6rfFvtm+DdHoTm5LX2lo2I79fvXUdWs9rYEqN8W/rhM8YzH1G+rfdP9m6PQnNyWvtJR8dJEfiWso7ZY7VUJUL8tuNF7EpxKsbsY3AGgOcr7FPy56WJ1UcCdDwr7Jvs3R6E5uS19pZvi/YZzD92QvX2t1G/LNcDHsnjGI45+VfZN9W+OQnNyW/pKN8VbM+RtZ92gvXmt1G/LJcBlimc8oH6V9k30b45Cc3Jb+konxZYk/vvcnRwJK704AavfF/WyNq/q2J35F439G8nLh/mWC89KdNFfs+PyYZbHDeXa0LwqI4uw9/ehWb6jC5ozMa+HJr5bl4lZtsZ8f+uivre6n2lX2zfNvzkKzcm9+NuvvUJ7YVbtUYy4TwJvxVeP+CcJqAhMVfoF7Jvk3xyF5uRe5T3+V/nrfrk2vOf3KtRv04jV70S9GLPIjh0P5cWYptJ6ni5683FcFqa6ddzftIbmrNcLY59xDy5ozjF+3roYM22Nmc91UfOVRr+QfVP8m6PQnNyrvEeXJ38PTrZXaZSN3IQA535bsOMzuXhGt3O/Q9XvwumiVHc+gPZN8G+OQnNyW/rKZYpfy3HG5mO+/LxMpayllwSo35bLgssUz+hWv7pbynRRGv3C9sX9m6PQnNyWvsJiEsAIUL8tvHCZ4hkPpd8E+8L+zVFoTm5LX2ExCWAEqN8WXrhM8YxH0u/X4jB1+d0C9rT4L/z+vGqqM0ehObmnx8wtEsgkQP22AES/j+ZU+szfetvbD/Hcgtm3HP+Ov1quhy/OUWhOrubYGEMCNQL70VttT9iE9Iv8UDsSGw4Gy8GiXRt4Bj4uTcnAc5QztR6sLlYXpZj7LfyL2vfg37HuVx1yFJqTGzoqX0kAICBLVi6JVI/oC4kNTWE5WLRrA8/AxZiSgecoZenB6mJ1UQr9DgZ2/Ivb1/tXad9BjkJzckNH5SsJAARkycolkeoRfSGxoSksB4t2beAZuBhTMvAcpSw9WF2sLkql38Eqxb7Wv1Pd2HdA/YZ3DF/vgYAsWbkkcl6IvpDY0BSWg0W7NvAMXIwpGXiOUpYerC5WF6XTb7ienb3mjGBzcjs7IVb8yARkycolER6IvpDY0BSWg0W7NvAMXIwpGXiOUpYerC5WF0X9hr7KVxLQEpAlK5dE6kb0hcSGprAcLNq1gWc4MaL3MeAZeCtKWXqwulhdFPUb+ipfSUBLQJasXBKpG9EXEhuawnKwaNcGnoGPS1My8BylLD1YXawuivoNfZWvJKAlIEtWLonUjegLiQ1NYTlYtGsDz8DFmJKB5yhl6cHqYnVR1G/oq3wlAS0BWbJySaRuRF9IbGgKy8GiXRt4Bi7GlAw8RylLD1YXq4uifkNf5SsJaAnIkpVLInUj+kJiQ1NYDhbt2sAzcDGmZOA5Sll6sLpYXRT1G/oqX0lAS0CWrFwSqRvRFxIbmsJysGjXBp6BizElA89RytKD1cXqoqjf0Ff5SgJaArJk5ZJI3Yi+kNjQFJaDRbs28AwnRt75EK6Pff2nedx6Jb6b1VezrvwkBLaq/Lmkbg6ctT4jAVmyckmEE6IvJDY0heVg0a4NPAMfl6Zk4DnKsaoHq4vVRfVGv5PiwT5Jf05Df+MrCVyDgCxZuSRyXIi+kNjQFJaDRbs28AxcjCkZeI5Slh6sLlYX1R/9qn/1qhJofyprsVj0Yvweujxfn4CALFm5JIIF0RcSG5rCcrBo1waegYsxJQPPUcrSg9XF6qJ6o9/0ESy/dBzebny9EgFZsnJJ5NAQfSGxoSksB4t2beAZuBhTMvAcpSw9WF2sLor6DX2VrySgJSBLVi6J1I3oC4kNTWE5WLRrA8/AxZiSgecoZenB6mJ1UdRv6Kt8JQEtAVmyckmkbkRfSGxoCsvBol0beIYTI+98CNfHvvblzgdOPlQuClf7TUCWrFwSOSNEX0hsaArLwaJdG3gGPi5NycBzlGNVD1YXq4uifkNf5SsJaAnIkpVLInUj+kJiQ1NYDhbt2sAzcDGmZOA5Sll6sLpYXRT1G/oqX0lAS0CWrFwSqRvRFxIbmsJysGjXBp6BizElA89RytKD1cXqoqjf0Ff5SgJaArJk5ZJI3Yi+kNjQFJaDRbs2PuB5XFyMKRl4zsT8BWitr7pY6rcVJANIIImALFm5JNIQIjwkNjSF5WDRro2NUf2MeTgc/4rn4Bn4kU3M58lRNm3oYqnfJoYsI4F0ArJk5ZJIa4jwUkaaWA4W7U4nRYxDo/39xwAMzxgM0JyFeQnNtb7qYnVjZE4+tOJmAAnUCMiSlUtqVbhNRL8pqsNysGh3/HjGYKAcFbrqDwuegbeiU2pxQLpY3RiZ+g1Xma8koCUgS1YuidR9//pF7+HFxZiSgefolFpcQl2sLor6jbwtuIsEGgnIkpVLIhXev37xuV98LItnUL+Rzta0K+e5DTm5TcfEMhIQCMiSlUsiVWH6xUea2DfMsGh3Opx8iFzUwy6OfmU2LCGBHAKyZOWSSHuYfvGRJqZHLNqdDp6Bj0tTMvAcpSz9NdTF6qI4+RB5W3AXCTQSkCUrl0QqpH4jUM52cfLhDMmld+RMIOTkXvo8WN9TEJAlK5dEwFC/EShnu6jfMySX3pGj0JzcS58H63sKArJk5ZIImPvXLz4fjcsUz+DkQ6SzNe3KUWhObtMxsYwEBAKyZOWSSFX3r198PhqXKZ5B/UY6W9OuHIXm5DYdE8tIQCAgS1YuiVSF6RcfaWL3MmDR7nT40Vvkoh528aM3mQ1LSCCHgCxZuSTSHqZffKSJ6RGLdqeDZ+Dj0pQMPEcpS38NdbG6KN75EHlbcBcJNBKQJSuXRCqkfiNQznZx8uEMyaV35Ewg5ORe+jxY31MQkCUrl0TAUL8RKGe7qN8zJJfekaPQnNxLnwfrewoCsmTlkgiY+9cvPh+NyxTP4ORDpLM17cpRaE5u0zGxjAQEArJk5ZJIVfevX3w+GpcpnkH9Rjpb064chebkNh0Ty0hAICBLVi6JVIXpFx9pYvcyYNHudPjRW+SiHnbxozeZDUtIIIeALFm5JNIepl98pInpEYt2p4Nn4OPSlAw8RylLfw11sboo3vkQeVtwFwk0EpAlK5dEKqR+I1DOdnHy4QzJpXfkTCDk5F76PFjfUxCQJWtLXtTLzvxTx27MbzT2byQvG/NPLjwr0UV/zY7L0LweN5RrY/NPGVmEvb+Pzes7ukzAnIX5PjTx3boszGtrzPe3Lup7a6Y9eMfkKDQntwenzkO4PwJN+jVcSEBNYEr93t/bn0d8WwKN+p2oF2MW2bHjobwY01Raz9NFbz6Oy8JUt477m9YMmLNeG7Nbo8sCzDEmtDBvXYyZtsbM57qo+Yr6ve1bma3fH4Em/Y71p4N8dIXEhiPAcrBo1waegX8o5n61+C2ckPoVnS+uf1C29y3F/yxiXVm8vNjvo4qApqP+R/024WEZCZwToH49k+voF1WpOzQ0p67f80t+3KOL1UXxzocjV66RgI4A9es5Ub9yd6F+ZTYsIYEcAtSvp0f9yp2I+pXZsIQEcghcTL8z9VHg30lzc7P6+tFod+BY/cWpotMC+ESCawdtRSlLfwq6WF0UJx+KXsE/SUBP4GL61X+TLWWkieVg0Q4WnoGLMSUDz1HK0vcQXawuivrVv+kYSQIFAerXc6B+5TcE9SuzYQkJ5BCgfj096lfuRNSvzIYlJJBDgPr19KhfuRNRvzIblpBADgHq19OjfuVORP3KbFhCAjkELqZf/Z0JKXcZYDlYtMOHZ+AfiqVk4DlKWfo+o4vVRfGjt5y3IXOfk8DF9Ms7H9o7EHoTmasRzVHK0h+sLlYXRf22X39GkMApAerX8+Dkw2m3qG5Rv1UaXCeByxGgfj1L6lfuUtSvzIYlJJBDgPr19KhfuRPdmX7X0DPwq8H9eGC8fCFY8nAEqF9/SalfuWffmX4n6gfEnwf24fc65AvBkocjcDH98s6H9r6BfozmakRzlLL0B6uL1UX15qM35Ln8p8/pn/TiicXt3YgRD0PgYvrlnQ/tfQJVqasRzVHK0h+sLlYX1Rv9po9g+Vtv7V2YERclQP16nJx8kHsV9SuzYQkJ5BCgfj096lfuRNSvzIYlJJBDgPr19KhfuRNRvzIblpBADgHq19OjfuVORP3KbFhCAjkELqZf3vnQfhnQj9FcjWiOUpb+YHWxuih+9NZ+/RlBAqcELqbf+77z4Ro/AY+r1F0qVL/G7E+vcMOWLpb6bUDIIhLIIED9enio5FwSnoNn4K0Yo+8NuljqV0+UkSSAELiBfodmhByhj8VysGjXQIoYJ+YFPA88YzBAc3RKLQ5cF6sbI3PyAewMDCeBwQ30m6I6LAeLdr0AzxgMlKPCSifDM/BWdEotDkoXq4uifisXmqskoCJA/XpM1K/cW6hfmQ1LSCCHwMX0q7/zIUV1WA4W7fDhGfi4NCUDz1HK0vcZXawuiqPfnLchc5+TwMX0q7/zIUV1WA4W7S48noGLMSUDz1HK0vd2Xawuivp9ToHwrHMIUL+eHvUrdyLqV2bDEhLIIUD9enrUr9yJqF+ZDUtIIIcA9evpUb9yJ6J+ZTYsIYEcAtSvp0f9yp2I+pXZsIQEcghcTL+886H9MvC+33ZGmRE5j0zPyc08bKY/J4GL6Zd3PrR3IOq3nVFmRI5Cc3IzD5vpz0mA+vXXnZMPcvfn5IPMhiUkkEOA+vX0qF+5E1G/MhuWkEAOAerX06N+5U5E/cpsWEICOQSoX0+P+pU7EfUrs2EJCeQQuJh+eedD+2XgR2/tjDIjcj4+y8nNPGymPyeBC+kX+bWIlJEmloNFuwuPZ+BPY0jJwHOUY1Xf23Wxuig+8+E5BcKzziFwIf0i+kJiw6lhOVi0awPPwMWYkoHnKGXpwepidVHUb+irfCUBLQHq15OifuUOQ/3KbFhCAjkEqF9Pj/qVOxH1K7NhCQnkEGjU74t6GZuv7Ni/kbyMza9ceFaii/6aHZex+XfcUK4tzK8ysgh7f1+Y73d0QXOMCS18ty7GtIbYAF3U99ZMczrihXJzPj7Lyb3Q4bOa5yLQpF/DhQTUBKbU73Opg2ebT6BRvxP1YsxiMZlo/p9MpNjxUF6MaSqt5+miNx/HxZjq1nF/0xqas14bs4YXNOcYP29djGkNsQG6qPmK+s1/O7KG5yLQpN+xHgUyd4rEhiPAcrBo1waegd+TkJKB5yhnaj1YXawuinc+hL7KVxLQEqB+PSnqV+4w1K/MhiUkkEOA+vX0qF+5E1G/MhuWkEAOAerX06N+5U5E/cpsWEICOQSoX0+P+pU7EfUrs2EJCeQQoH49PepX7kTUr8yGJSSQQ4D69fSoX7kTUb8yG5aQQA4B6tfTo37lTkT9ymxYQgI5BKhfT4/6lTsR9SuzYQkJ5BCgfj096lfuRNSvzIYlJJBDgPr19KhfuRNRvzIblpBADgHq19OjfuVORP3KbFhCAjkEqF9Pj/qVO9Gd6XcNPQW0GtyPR2bKF4IlD0eA+vWXlPqVe/ad6dc+US956cMTi+ULwZKHI0D9+ktK/co9+870izyZ9PRJpZNePDJTvhAseTgC1K+/pNSv3LPvTL/pI1j+2oXcCVjSCQHq12OlfuXeRf3KbFhCAjkEqF9Pj/qVOxH1K7NhCQnkEKB+PT3qV+5E1K/MhiUkkEOA+vX0qF+5E1G/MhuWkEAOAerX06N+5U5E/cpsWEICOQSoX0+P+pU7EfUrs2EJCeQQoH49vYV5gSniOXgG/EvHL2ahPhFlLPWrJspAEoAIUL8eV5oYPyHUTqVoBpyjVKo/cGUs9QteZoaTgJLADfSbpjpkdIq3gGcMBkotVS4EngG3olSqPyhdrC5qMPjXi++M5Xx1Iie3cpW5SgJaAtSvJ0X9ih2G+hXRsIAE8ghQv54f9St2I+pXRMMCEsgjQP16ftSv2I2oXxENC0ggjwD16/lRv2I3on5FNCwggTwC1K/nR/2K3Yj6FdGwgATyCFC/nh/1K3Yj6ldEwwISyCNA/Xp+1K/YjahfEQ0LSCCPAPXr+VG/YjeifkU0LCCBPALUr+dH/YrdiPoV0bCABPIIUL+eH/UrdiPqV0TDAhLII0D9en7Ur9iNqF8RDQtIII/AhfQ7MX/q40hRHZaDRbsDxzPgpzHYVvjMB3UnSQ3MeW5DTm7q8TLvqQlcTL/6Z3mlqA7LwaLd9cczUmRK/Xb+XstRaE5u5yfGBh6RwIX0i+gLiQ3IsRws2rWBZ1C/4docXvnEsxoQbpJAGwHq1xOifsWOwrlfEQ0LSCCPAPXr+VG/YjeifkU0LCCBPALUr+dH/YrdiPoV0bCABPIIUL+eH/UrdiPqV0TDAhLII0D9en7Ur9iNqF8RDQtIII8A9ev5Ub9iN6J+RTQsIIE8Ao36fVEvC/OWHfs3kpeFmcmFZyW66K/ZcVmY3+OGcs0YZeAh7P3dmHd4AXO+zSI08d22vJpFW4gt10V9f2/5U5t5b0VmPx+BJv0aLiSgJjClfp9PHzzjPAKN+p2oF2PUoRMpdjyUF2PksvMSXfTm47gYU9067m9aM6ap9LxsvTZmDS9ozjF+3rZMjWkLseW6qPl8Rf3mvRWZ/XwEmvQ71uNA5k6R2HAEWA4W7drAM+7kW297TzD+53FWN14+GLj9xyhflfgHv/UmomEBCcQJUL+ey8PqN37Vi706seqiBgPqt4k1y0ggQoD69VCo30jfKHZRvyIaFpBAHgHq1/OjfsVuRP2KaFhAAnkEqF/Pj/oVuxH1K6JhAQnkEaB+PT/qV+xG1K+IhgUkkEeA+vX8qF+xG1G/IhoWkEAeAerX86N+xW5E/YpoWEACeQSoX8+P+hW7EfUromEBCeQRoH49P+pX7EbUr4iGBSSQR4D69fyoX7EbUb8iGhaQQB4B6tfzo37FbkT9imhYQAJ5BKhfz4/6FbsR9SuiYQEJ5BGgfj0/6lfsRtSviIYFJJBHgPr1/KhfsRvdm37X2EPwK9H9eGC8eCFY8HgEqF9/TalfsWvfm37t86STl6lIgQUk0AEB6tdDpX7FvnVv+m16av/5k/mreya9eGC8eCFY8HgEqF9/TalfsWvfm37TR7Cv1K/YC1jQCQHq12OlfsXeRf2KaFhAAnkEqF/Pj/oVuxH1K6JhAQnkEaB+Pb+F+YQ5GoOm4BnwL8r9mYn6qHSx1K8aKANJACNA/XpeVxCjbecKrbyZoboD6GKpXzVQBpIARuAm+sVHmtjoFIt2wBLEuIdz8Az7W8NgK/L1PO8XuljdGJk/tXnOl3tIoIWA/BaUSyJVInOnoFB8a1gOFu0awDPUP8B+pKUdRx4z9D/zHnKQq6aL1Y2Rqd9wBfhKAmoC8ltQLolUTv1GoNR33at+x/UTiW7zh+ajWLiTBGQCsmTlkkht1G8ESn0X9VsncvntnHt3c3Ivfyas8QkIyJKVSyJYqN8IlPou6rdO5PLbOQrNyb38mbDGJyAgS1YuiWChfiNQ6ruo3zqRy2/nKDQn9/JnwhqfgIAsWbkkgoX6jUCp76J+60Quv52j0Jzcy58Ja3wCArJk5ZIIFuo3AqW+i/qtE7n8do5Cc3Ivfyas8QkIyJKVSyJYqN8IlPou6rdO5PLbOQrNyb38mbDGJyAgS1YuiWAxZh/ZG9+VcI8teF8u3gKe8UT3/fLGs3hH5l4SyCQgS1YuiTSJ6AuJDU1hOVi0awPPoH7DtTm88r7fGhBukkAbAVmyckmkTkRfSGxoCsvBol0beAb1G67N4ZX6rQHhJgm0EZAlK5dE6kT0hcSGprAcLNq1gWdQv+HaHF6p3xoQbpJAGwFZsnJJpE5EX0hsaArLwaJdG3gG9RuuzeGV+q0B4SYJtBGQJSuXROpE9IXEhqawHCzatYFnUL/h2hxeqd8aEG6SQBsBWbJySaRORF9IbGgKy8GiXRt4BvUbrs3hlfqtAeEmCbQRkCUrl0TqRPSFxIamsBws2rWBZ1C/4docXqnfGhBukkAbAVmytmSkXoxRh46Q2FCrMTNgwaJdxUjGe7F8m8VhTfuCZ7y/t+R815elmdR3idu6WF3U9/e2F78TnPPViZzctvcZy0kgQqBJv4YLCagJTKnfyPuLu0iggUCjfifqxRh16ESKHQ/lxRi57LxEF735OC7GHNe1a2jOem3MGl7AnN0xft62TM2iLcSW66Lm8xX12/A+YxEJRAg06Vf3ZVNfKTJ3isSGI8ZysGjXBp6RNPer/xXicOLocyK0Pw3k6pevfWhdH8UfG6oy4zoJqAjIb0G5JFIxoi8kNjSF5WDRrg08I0m/i3A+6ldcv/q/NHVXWBdF/aovKQNJIBCQ31xyScitvCL6QmJDE1gOFu3awDOo33BtDq+886EGhJsk0EZAlqxcEqkT0RcSG5rCcrBo1waeQf2Ga3N4pX5rQLhJAm0EZMnKJZE6EX0hsaEpLAeLdm3gGdRvuDaHV+q3BoSbJNBGQJasXBKpE9EXEhuawnKwaNcGnkH9hmtzeKV+a0C4SQJtBGTJyiWROhF9IbGhKSwHi3Zt4BnUb7g2h1fqtwaEmyTQRkCWrFwSqRPRFxIbmsJysGjXBp5B/YZrc3ilfmtAuEkCbQRkycolkToRfSGxoSksB4t2beAZ1G+4NodX6rcGhJsk0EZAlqxcEqkT0RcSG5rCcrBo1waeQf2Ga3N4pX5rQLhJAm0EZMnKJZE6EX0hsaEpLAeLdm3gGdRvuDaHV+q3BoSbJNBGQJasXBKpE9EXEhuawnKwaNcGnkH9hmtzeKV+a0C4SQJtBGTJyiWROhF9IbGhKSwHi3Zt4BnUb7g2h1fqtwaEmyTQRkCWrFwSqRPRFxIbmsJysGjXBp5B/YZrc3ilfmtAuEkCbQRkycolkToRfSGxoSksB4t2beAZ1G+4NodX6rcGhJsk0EZAlqxcEqkT0RcSG5rCcrBo1waeQf2Ga3N4pX5rQLhJAm0EZMnKJZE6EX0hsaEpLAeLdm3gGdRvuDaHV+q3BoSbJNBGQJasXBKpE9EXEhuawnKwaNcGnkH9hmtzeKV+a0C4SQJtBGTJyiWROhF9IbGhKSwHi3Zt4BnUb7g2h9e+6Hen/eXTs7ifXvxcUg0rNx+ZgCxZuSTCA9EXEhuawnKwaNcGnkH9hmtzeO2Lfu1vCSYv09o5cZMEOiUgS1YuiRwQoi8kNjSF5WDRrg08g/oN1+bw2hf9jrU/lXoWN+Tot3ZNudkxAVmycknkkBB9IbGhKSwHi3Zt4BnUb7g2h9e+6Dd9BPtK/dauKTc7JiBLVi6JHBKiLyQ2NIXlYNGuDTyD+g3X5vBK/daAcJME2gjIkpVLInUi+kJiQ1NYDhbt2sAzqN9wbQ6v1G8NCDdJoI2ALFm5JFInoi8kNjSF5WDRrg08g/oN1+bwSv3WgHCTBNoIyJKVSyJ1IvpCYkNTWA4WbdvYm0VoSf36AufgGQNY8l9moz4DXay2H1C/avAMJIGCgPzmkksi7BDhIbGhKSwHi7ZtXEOM12lFp9QCqy5W2w+o39BZ+UoCSgLym0suiVQNCC/rNZmcAAARtElEQVRlpInlYNHubFL0+2fGERBNu/CMwQDN0Sm1OEpdrC5qMKB+m649y0ggQkCWrFwSqQbQb4rqsBws2p0NnjEYQHw8MjwDb0UrS3dAulhdFPXrLzH/IAGEgKwEuSRSP/UbgVLfBRE9JKM5Wlm66nWxuijqt361uU0CrQTkt7dcEqmU+o1Aqe+CiB6S0RytLF31ulhdFPVbv9rcJoFWAvLbWy6JVEr9RqDUd0FED8lozgy480EXS/3WryO3SeBCBOS3t1xy3vSe+j2HcrYHIRqS0RytLF39ulhdFEe/4YrxlQTUBOS3t1xyXvmLmZzvFPakfMyF5WDR7jDxDPxDsZQMPEcrS3fWuljdGJn6dUS5kABEQJasXHLeAKIvJDa0hOVg0a4NPAMXY0oGnqNTasFVF6uLon5DX+UrCagJyJK1JfuRcpmZhTJyNGqI/ZoJy69ZCCWx3ero3/DE7W+zCKvq11czUccWgTbjG12WYM7WjMsmXpfNy48ZNwf40p+FJmq5XJmdutd1F5jz1LKc3O7OiDU/MIEm/Q7fkp9bzcQ7ILC48DEOe/A+yVFoTm4PTp2HcH8EmvQ7/htqF2O0kcOhHLs5ewL2YcfGGKkotl8bvVuHxZiwpn7dmYU6tgi0GXN0mYI562r8qnmZm0lzgC/VRa1WU+Cei+7eJzkKzcnt7oxY8wMTaNSv+ryRuVMkNhwAloNFuzbwDHxWNiUDz9HO1Lqz1n2opq2RXzp2TLmQAECA+nWwHke/OqUWHUQnVm2N1C/wtmMoCTgC1K+j8Dj61SnVnbP2xjNtjdRvQZV/koCaAPXrUFG/coehfmU2LCGBLALUr8NH/cqdiPqV2bCEBLIIUL8O33PqVzerS/1mvcGYTAIyAerXsXlO/erEqovit97k9xhLSEAgQP06MI+jX92ItugMOrFqa+RHb8JbjLtJQCJA/Toyj6NfnVKL3qCL1UVx9Cu9w7ifBEQC1K9DQ/2KHUT5XDTqVybIEhIQCFC/Dgz1K3QPu5ujX5kNS0ggiwD16/A9p351s7rUb9YbjMkkIBOgfh2b59SvTqy6KE4+yO8xlpCAQID6dWAeR7+6EW3RGXRi1dbIOx+Etxh3k4BEgPp1ZB5HvzqlFr1BF6uL4uhXeodxPwmIBKhfh4b6FTsIP3qT0bCEBPIIUL+OH/Ur9yKOfmU2LCGBLALUr8P3nPrVzepSv1lvMCaTgEyA+nVsnlO/OrHqojj3K7/HWEICAgHq14F5HP3qRrRFZ9CJVVsj73wQ3mLcTQISAerXkXkc/eqUWvQGXawuiqNf6R3G/SQgEqB+HRrqV+wgvPNBRsMSEsgjQP06ftSv3Is4+pXZsIQEsghQvw7fc+pXN6tL/Wa9wZhMAjIB6texeU796sSqi+Lcr/weYwkJCASoXwfmcfSrG9EWnUEnVm2NvPNBeItxNwlIBKhfR+Zx9KtTatEbdLG6qP6MfnfvqcuPmUpvE+4ngS4IUL+OKvUr96170+/EpC/Ur9wPWNIBAerXQaV+5a51b/odf6QuQ45+5W7Aki4IUL+O6nPqVzere2/6TR/BvlK/XSiGdcoEqF/H5jn1qxOrLqo/c7/Ur/xuZ0nPCFC/7oI8jn51I9qiE+rEqq2Rdz707K3Nw+k/AerXXaPH0a9OqUW/1MXqojj67f97nUfYOwLUr7sk1K/cMalfmQ1LSCCLAPXr8MkUZLh4Dp6BH9mv2cmHXCvRxVK/NWzcJIFLEZCVYEtG2mVmFtrQkRj7NROXX7MQy84LlNG/x9vzX83kuKFcg3O+l2byjS5oztZsDk28LtuWHzNsC7HlP2asiFout724byDn7oWc3Eu9H1nPUxFo0m/67evMfBwCC+WpTKnfpzIHT/YCBBr1O1QvxqhDh1LsRr5dfmOMXHhWoozerctlZxblunYFzpmvzWKOLmjOzkxCE6u2ZWrGbSG2XBe1WvXjK7s5I9ic3Au8FVnF8xFo0u9YjUOu5bwKJDZkYzlYtGsDzxioH0MeziEl45iz99W0/+nnc4uwY8PCmm7uVxfFOx8EyNxNAjIBWTxyyXltXcWGlpD6U2SK1V8clfYjqXAOR5Ue97Svoa1oZela1sXqoqjf9mvJCBKoEZDFI5fUqrCbXcWGlpD6saMpWsDqL3JQMVK/4Wp2+ZozgZCT2+U5se6HJSCLRy45h9FVbGgJqf9a+tV+Gyycw2CAZ+DK1o5V3VHpYnVRHP0erzPXSEBJQBabXHJedVexoSWk/mvpl6PfcHWKV37p+JQHt0iglYAsNrnkvNKuYkNLSP2PpV90xKwdqzqyulhdFEe/oa/ylQTUBGSxySXnlXcVG1pC6n8s/aJjbK0sHVldrC6K+g19la8koCYgi00uOa+8q9jQElI/9Ruotb3qxKqLon7baLOcBM4IyGKTS84q4Z0P50gie9CRrKsCzdHK0tWti9VFUb+OKBcSgAjIkpVLzhvoKja0hNR/rdEvOivLOx/C1ezyNefmsZzcLs+JdT8sAVlscsk5jK5iQ0tI/dfSLzouxUey7uzRVrRjVVe3LlYXxdGvI8qFBCACstjkkvMGuooNLSH1P5Z+0TG2VpaOrC5WF0X9hr7KVxJQE5DFJpecV95VbGgJqf+x9MvRb+gDutecCYScXN3RMYoETgjIYpNLTirwG13FhpaQ+qnfQK3tVTeu1UVx9NtGm+UkcEZAFptcclYJ73w4RxLZg45kXRVojlaWrm5drC6K+nVEuZAARECWrFxy3kBXsaElpP5rjX7RWVne+RCuZpevORMIObldnhPrflgCstjkknMYXcWGlpD6r6VfdFyKj2Td2aOtaMeqrm5drC6Ko19HlAsJqAi8/CvCSrHtv2sP6S5LFPV1FRuaRup/LP2iY2ytLB1ZXawuivoNfZWvJNBOYP3hBXwQ2345/KnlIMrrKjYcElL/Y+mXo9/QB3SvORMIObm6o2MUCRQEZvbn06yAvdisfM3ir0YGUV5XseGQkPqp30Ct7VU3rtVFcfTbRpvlJFAhMLW/YLt7t2Lbvw7tr9nWB7+d3c2AqbQ4YCwHi3Yt4Bn4rGxKBp6jlaU7a12sLor6dUS5kICSwK//AfEPM7E/PWzM4qWehiipq9hwTEj9KTLF6i+OCp2V5Z0P4Wp2+ZozgZCT2+U5se5HJOCGv+VyNviFRoSIvpDYgB3LwaJdG3gGPi5NycBztGNVd9a6WF0UR7+OKBcS0BIohr+FgM8Hv5CSEH0hseFUsBws2rWBZ+BiTMnAR8xaWbqz1sXqoqhfR5QLCagJrMux7/nML6YkRF9IbDgVLAeLdm3gGSkyRe9icEeG5mhl6erWxeqiqF9HlAsJqAkch7+RwS+kJERfSGw4FSwHi3Zt4Bm4GFMy8BytLN1Z62J1UdSvI8qFBPQEyuHv+cwvpiREX0hsOBUsB4t2beAZuBhTMvAcrSzdWetidVHUryPKhQT0BMLwNzb4hZSE6AuJDaeC5WDRrg08A5+VTcmgfkMP0L7m3L2Qk6s9PsaRQEngMPyNDX4hJSH6QmLDgWI5WLRrA8/AxZiSgedox6rurHWxuiiOfh1RLiQAECiGv9HBL6QkRF9IbDgVLAeLdm3gGbgYUzLwEbNWlu6sdbG6KOrXEeVCAggBP/yNDn4hJSH6QmLDqWA5WLRrA89IkSl6F4M7MjRHK0tXty5WF0X9OqJcSAAh8G7vPYsPfiElIfpCYsOpYDlYtGsDz8DFmJKB52hl6c5aF6uLon4dUS4kABHYRZ72UFSAKKmr2HAqSP0pMsXqL44KHZfiKnXtoK1oZenq1sXqoqhfR5QLCUAE3qXBLzQiRPSFxIZTwXKwaNcGnoHPyqZkUL+hB2hfc+5eyMnVHh/jSKBKYB2f+cWUhOgLiQ0HiuVg0a4NPAMXY0oGnqMdq7qz1sXqovoz+t29py4/ZuqwcCGBqxGY1Z/zG1pGlNRVbMqxpMgUOf5wTOi0AK5S1xL6XDWtLF3dulhdVH/0e/wmPb5G/bp+waUHBBAldRUbMCD1P5Z+UclrZenI6mJ1UX3R7/s6Z9mGDsdXErgtAUR5XcUGAkj91G+g1vaqE6suqi/6bTtnlpPAXRBAlNdVbACF1E/9Bmptrzqx6qKo3zbaLCcBgIBV3ki7/HYUG9pH6h+NsGjXBp4xGv0zm3B4ylc8A2/l23woj2Y00sXqokajJT+4At5dDCWBRgJv+CcXzHhqAvzgqvENxUIS0BP4G0/Ui/2pzk5iQ6VI/ZMJFu3awDNScq7RCtKGLlYX5Siu9J2LkSRAApci8DfcqavC5nGLarEcLNq1gBx/OFH0noS0G8/QVmbDeTjA1lddrHbut7U5BpAACdyaAC5H9MO0lBZwKqgYr6Nf/DzaMqjfNkIsJ4G7IZAy0sRysOhUcF9DdK4Tz7DKhltJPR8pTzdGlrK5nwRIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgAS6I/C1XC7/XPV/dmW5d2tul19xG1xIgARI4CoEvryJrtJUTxqZGWO+3bEs7YqZubWVMWP3+uTLF/8KevIewNO/KoGv+cdV2+tDY/uFMT/uQOZOv1u39mGM/lfcXcJjLu+bVwr4MS8tz6p/BL6sgP7177C6PqK1MTvXxsTp1/2o8d6+Lrtu9R7q35khBXwPF4rHePcEnHzN8w1+B4OtPW87ynOTEMYs7Nqvff26++t5gRP4Z0FQwBcAySpIoJHAyP/Tu5gEbQx8vEJn25m3sB0HH9Y49euv884CoYAfr8vzjHpFYDS3E6B2ecbBb5hrmNoZB+tfO/lr/ybi1K/vn274axeOgHv1buXBPBSBkf2kv1j8HQAPdW6ak7FjvPnAfQL3Zech7OSvnQTm1G8Bzg9/KWBNL2IMCSQQeCvlazYJ6TdP+Xw5XT7hI/qx4zs34Tt287+L/ZvVjZ2M4GIJHIa/FDB7Awl0QKAiX3v/1ffJ4r6GcLJsa8tPfVnVlnl9ma5ry0dt2Qxry6S2FLMk1gfSgv8d4hzz92PMyg98Z9/WwRmkX94fadkcMXMKIqNXMJUEzgn8tNrs+Pbr6dqi5md/E9n5mTbs+bRn9s/+M/vVT/tu7b8G3O1nqYv7JO9Bl+FvKhTmkQAJnBH4O/Hv+nSwWhvKrlb1wW5tMLzdnoyV7cbr9/fp///qI8NZbfka1ZbTmYWXF3xu4eykz3bYr1m4GZg3/823qRWx//LFWZhux6w2nr/vzXHlbxJ+C0PXAxhFAloCVQH7z/vtja92cX8Wa37zsf8oZr/drMXITjxY4XDq93DBX47/OtrYfxxwIQESuCyBl3IEvHjSLxvY2V67+G8eD92a++4FF0fgx+FwC+XLDkEC3RB4+fFfuH3a213/vGH89639QHjdDeb7q/XvMPilfO/v2vGI74fAy7YQ8JMOf/2Y98VdLj8Qzpn6vZ9rrjjSH//3EuWrQMUQEsggUAj4Sb/t5ca8xR0TfiDMD/iLjuQHv5RvxruKqSSgJPDpRsDPOfz9t1uvD190m9sbkzn1W3QZO/ilfJXvHoaRQCaB/Xb8pMPfTHCPmf6yoHwf88ryrPpJ4HNrb37lQgKOwCtvNWNHIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIIGuCPwH9j3d4Kg1fY0AAAAASUVORK5CYII=" + } + }, + "cell_type": "markdown", + "metadata": {}, + "source": [ + "![MVA-1.png](attachment:MVA-1.png)" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "Based on the above block diagram we find that `PE` & `SIMD` parallelization attributes are subject to the following constraints. \n", + "If `W` is the width of the input and `H` is the height of the output in a Matrix-Vector Computation then:\n", + "\n", + " W % SIMD == 0\n", + " H % PE == 0\n", + " \n", + "For the above example, H = 12 and W = 12. The demonstrated PE & SIMD values adhere to the above constraints.\n", + "\n", + "We also define a term referred to as total folding which is defined as :\n", + "\n", + " Total folding = (H/PE) x (W/SIMD)\n", + "\n", + "The goal of adjusting these parameters is to get an almost balanced pipeline i.e. equalling the rate of producers and consumers in the generated dataflow architecture.\n", + "This can be achieved (or almost achieved) by keeping the `total folding` parameter approximately constant across all layers.\n", + "\n", + "We now explore how these parameters affect the estimated clock cycles and the resource utilization of the generated dataflow architectures.\n", + "We start with a naive case where `PE` & `SIMD` values across all layers are 1 and observe the above-mentioned numbers.\n", + "We define the utility functions (`exp_cycles_per_layer()`) and (`res_estimation()`) to estimate the number of clock cycles and resource utilization of each network layer." + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "
\n", + "Should this line be added (The `exp_cycles_per_layer` formula is equal to the total folding in this case as the number of input vectors is 1 and the mmv value is also 1).\n", + "
" + ] + }, + { + "cell_type": "code", + "execution_count": 3, + "metadata": {}, + "outputs": [], + "source": [ + "from finn.analysis.fpgadataflow.exp_cycles_per_layer import exp_cycles_per_layer\n", + "from finn.analysis.fpgadataflow.res_estimation import res_estimation" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "We now individually extract the `MatrixVectorActivation` blocks from the onnx file and set the config values manually (although this can be done automatically by Vivado tools also as mentioned in the introduction).\n", + "\n", + "In the first step, we set the `PE` & `SIMD` values for all the layers to be '1' to establish a baseline and measure the estimated clock cycles and resource utilization for each of the individual layers.\n", + "\n", + "We utilize from (`getCustomOp()`) as the helper function to set different properties of the node. The (`set_nodeattr()`) function within this function call helps us set these values." + ] + }, + { + "cell_type": "code", + "execution_count": 4, + "metadata": {}, + "outputs": [], + "source": [ + "from qonnx.custom_op.registry import getCustomOp\n", + "fc_layers = model.get_nodes_by_op_type(\"MatrixVectorActivation\")\n", + "# (PE, SIMD, in_fifo_depth, out_fifo_depth, ramstyle) for each layer\n", + "config = [\n", + " (1, 1, [16], [64], \"block\"),\n", + " (1, 1, [64], [64], \"auto\"),#8,8\n", + " (1, 1, [64], [64], \"auto\"),#8,8\n", + " (1, 1, [64], [1], \"distributed\"),\n", + "]\n", + "for fcl, (pe, simd, ififo, ofifo, ramstyle) in zip(fc_layers, config):\n", + " fcl_inst = getCustomOp(fcl)\n", + " fcl_inst.set_nodeattr(\"PE\", pe)\n", + " fcl_inst.set_nodeattr(\"SIMD\", simd)\n", + " fcl_inst.set_nodeattr(\"inFIFODepths\", ififo)\n", + " fcl_inst.set_nodeattr(\"outFIFODepths\", ofifo)\n", + " fcl_inst.set_nodeattr(\"ram_style\", ramstyle)" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "After setting these parameters, we save the model and view it using `Netron`\n", + ". We can observe the values we set in the above step by clicking on any of the nodes and observing their properties." + ] + }, + { + "cell_type": "code", + "execution_count": 10, + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "Stopping http://0.0.0.0:5901\n", + "Serving './cybsec_PE_SIMD_not_modified.onnx' at http://0.0.0.0:5901\n" + ] + }, + { + "data": { + "text/html": [ + "\n", + " \n", + " " + ], + "text/plain": [ + "" + ] + }, + "execution_count": 10, + "metadata": {}, + "output_type": "execute_result" + } + ], + "source": [ + "model.save(\"./cybsec_PE_SIMD_not_modified.onnx\")\n", + "showInNetron(\"./cybsec_PE_SIMD_not_modified.onnx\",localhost_url='xirxlabs53')" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "We pass our model to the `exp_cycles_per_layer()` and `res_estimation()` functions which iteratively go through all the layers in the graph and measure the expected execution clock cycles and resource utilization for each of them and return a dictionary with calculated values." + ] + }, + { + "cell_type": "code", + "execution_count": 6, + "metadata": {}, + "outputs": [], + "source": [ + "cycles_dict = []\n", + "cycles_dict = exp_cycles_per_layer(model)" + ] + }, + { + "cell_type": "code", + "execution_count": 7, + "metadata": {}, + "outputs": [ + { + "data": { + "image/png": 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tuq62b98+GWP06quv6tVXX82xz/Hjx1WxYkW9/vrr6ty5s+655x7VrVtXbdu2Vc+ePVWvXr08bVO6/JCV8+fPX/M7yMzM1OHDh1WnTh2rPacnzuZk79692rVr1w1/e1Lufuf79++XpFz9DipVqpQt8JUoUUJbt27NVe1Xj9ms5c+cOSPp8nFLTEzUJ598ok8++STHdVy5f9fSvHlz63LktWvXqnz58mrQoIHq16+vtWvX6qGHHtK6dev0xBNPWMv8+eefqlChgjw9Pe3WlXV5eNa4ynK972v8+PE6d+6cli1bdkvv6Lxw4YLGjx+vmTNn6siRI3b3/l35RygfHx916tRJs2fP1htvvCHp8iWZFStWtEL/zRzb3P4mAdwZhDsABULZsmUVFxenFStWaNmyZVq2bJlmzpypXr166Ysvvrjp9V7rLMe12rP+w2j//v1q3bq1atWqpQ8++EB+fn5yc3PT0qVLNXHixGwPRMlJZmamHnroIY0YMSLH+ffcc08u9+Lv49FHH9WXX36pDz/80O4hJ/mhV69eeu+997R48WJ1795ds2fPVseOHW8Ysm8k67t86aWXFBoammOfrFd2tGjRQvv379c333yjH374QZ999pkmTpyoGTNmqH///rdUR27k9gxJZmamAgIC9MEHH+Q4P+uPG/nxO7/ajcbWrS6fVdPTTz99zftScxO277//fqWnpys2NlZr16617slr3ry51q5dq927d+vEiRNW+8243vcVGhqq5cuXa8KECWrVqlW2M6K5NWTIEM2cOVNDhw5VcHCwvL29ZbPZ1K1bt2zfX69evTR//nytX79eAQEB+vbbb/Xcc89ZT7e8mWPLWTugYCHcASgw3Nzc1KlTJ3Xq1EmZmZl67rnn9PHHH+vVV19VjRo1rnlZ3e3w3XffKTU1Vd9++63dmYQrL2fLcq26qlevrnPnzikkJOS626pcubKio6N17tw5u7N3N3rC5JXb2b59e676XrnNa21j9+7dKl26tIoXL66iRYvKy8sr1+sfMmSIatSooTFjxsjb21ujRo3Kt/rr1q2re++9V7NmzVKlSpV06NAhffTRRze1ritlXRJZuHDhG35XklSyZEn16dNHffr0sR62MW7cuDyHuzJlyqhYsWLX/A5cXFyynWHOrerVq2vLli1q3br1dcdNbn/nWZdJbt++PU/vprwdypQpI09PT2VkZNzw+7revjdp0kRubm5au3at1q5dq+HDh0u6HOA//fRTRUdHW5+zVK5cWT/++KPOnj1rd/Zu9+7d1vzcatq0qQYOHKiOHTvq8ccf16JFi1SoUN7/s2zBggUKCwvT+++/b7VdvHgxx6fttm3bVmXKlNGsWbMUFBSk8+fPq2fPntb8vBxbAAUT99wBKBBOnTpl99nFxcX6C3HWo9uz3umVl1cE3KysswdXX+I0c+bMbH2LFy+eY01PPPGEYmNjtWLFimzzEhMTrfv72rdvr0uXLtk9fj4jIyNbcLmWrl27asuWLVq0aFG2edc6W1K+fHkFBgbqiy++sKt9+/bt+uGHH9S+fXtJl7+HLl266LvvvtNvv/2Wq/W/+uqreumllzR69OhrPlL/Zuvv2bOnfvjhB02aNEmlSpXK9vTFmzkWZcuWVatWrfTxxx/r2LFj2eZnvaNOyv479fDwUI0aNbK9XiA3XF1d1aZNG33zzTd2j61PSEjQ7Nmzdf/998vLyyvP65Uu//aOHDmiTz/9NNu8CxcuWE/azO3vvE2bNvL09NT48eN18eJFu3m5PSOXX1xdXdW1a1ctXLgwxyB/5fd1vX8zihQposaNG+urr77SoUOH7M7cXbhwQZMnT1b16tVVvnx5a5n27dsrIyNDU6ZMsVvXxIkTZbPZcvU00CuFhIRozpw5Wr58uXr27HnTZ0qv/g4++ugjZWRkZOtbqFAhde/eXfPmzVNkZKQCAgLszsTl5dgCKJg4cwfgjli2bJn11+0r3XfffapWrZr69++v06dP68EHH1SlSpX0559/6qOPPlJgYKB1P0tgYKBcXV317rvvKikpSe7u7tb7ufJbmzZtrDOJzz77rM6dO6dPP/1UZcuWzRYAGjZsqOnTp+vNN99UjRo1VLZsWT344IMaPny4vv32W3Xs2FG9e/dWw4YNlZKSom3btmnBggU6ePCgSpcurU6dOqlZs2YaNWqUDh48KH9/f3399de5emiLdPndaQsWLNDjjz+uvn37qmHDhjp9+rS+/fZbzZgxQ/Xr189xuffee0/t2rVTcHCw+vXrZ70KwdvbW+PGjbP6vf322/rhhx/UsmVL67H6x44d0/z587Vu3bocX8z93nvvKSkpSeHh4fL09LR7wMat1P/UU09pxIgRWrRokQYNGmT3sJxbORZTp07V/fffr4CAAA0YMEDVqlVTQkKCYmNj9ddff2nLli2SJH9/f7Vq1UoNGzZUyZIl9dtvv2nBggUaPHjwNffvet58801FRUXp/vvv13PPPadChQrp448/Vmpqaq7fDZeTnj17at68eRo4cKBWrVqlZs2aKSMjQ7t379a8efO0YsUKNWrUKNe/cy8vL02cOFH9+/dX48aN9dRTT6lEiRLasmWLzp8/f0uXTt+Md955R6tWrVJQUJAGDBggf39/nT59Wps2bdKPP/6o06dPS7p8xtHHx0czZsyQp6enihcvrqCgIOs+sebNm+udd96Rt7e3AgICJF0O+zVr1tSePXvUu3dvu+126tRJDzzwgF5++WUdPHhQ9evX1w8//KBvvvlGQ4cOve4rP66lS5cu1iXoXl5e+vjjj/O0fMeOHfXf//5X3t7e8vf3V2xsrH788Ufr3uGr9erVS5MnT9aqVaus185cKbfHFkABdWcfzgngn+Z6r0LQFY8oX7BggWnTpo0pW7ascXNzM3fddZd59tlnzbFjx+zW9+mnn5pq1aoZV1dXu9ciXOtVCPPnz8+xnqsf6z927FgjyZw4ccJq+/bbb029evVMkSJFTJUqVcy7775rPv/8cyPJHDhwwOoXHx9vOnToYDw9PY0kuzrOnj1rRo8ebWrUqGHc3NxM6dKlzX333Wf+/e9/272i4dSpU6Znz57Gy8vLeHt7m549e5rNmzfn6lUIWcsPHjzYVKxY0bi5uZlKlSqZsLAw63HmOT3+3xhjfvzxR9OsWTNTtGhR4+XlZTp16mR27tyZbf1//vmn6dWrlylTpoxxd3c31apVM+Hh4SY1NfWaxzUjI8N0797dFCpUyCxevPiW6r9S+/btjSSzfv36fD0W+/fvN7169TK+vr6mcOHCpmLFiqZjx45mwYIFVp8333zTNGnSxPj4+JiiRYuaWrVqmbfeesvuu8zJtV6FYIwxmzZtMqGhocbDw8MUK1bMPPDAA9n27Vq/2+tJS0sz7777rqlTp45xd3c3JUqUMA0bNjSvvfaaSUpKsvrl9nee1fe+++6zfi9NmjQxX331lTW/ZcuWpk6dOtlqCQsLy/aqkZxIMuHh4dnaK1eubPe4fmOMSUhIMOHh4cbPz88ULlzY+Pr6mtatW5tPPvnErt8333xj/P39TaFChbJ970uWLDGSsr0apX///kaS+c9//pOtlrNnz5phw4aZChUqmMKFC5u7777bvPfee3avhLjevlzrtzBt2jQjybz00ks5Hpsr13vlqxDOnDlj+vTpY0qXLm08PDxMaGio2b17d47HLEudOnWMi4uL+euvv3Kcn5tje61/YwE4ls2YO3w9BQAAt+CRRx7Rtm3btG/fPkeXAvwt3XvvvSpZsqR1XyEA58E9dwCAv41jx45pyZIldg+BAJB7v/32m+Li4tSrVy9HlwLgNuDMHQCgwDtw4IB++uknffbZZ9qwYYP279+f6/foAbj8sKSNGzfq/fff18mTJ/XHH3/c9OsXABRcnLkDABR4MTEx6tmzpw4cOKAvvviCYAfk0YIFC9SnTx+lp6frq6++ItgBToozdwAAAADgBDhzBwAAAABOgHAHAAAAAE6gwLzE/J133tHo0aP1wgsvaNKkSZKkixcv6sUXX9ScOXOUmpqq0NBQTZs2TeXKlbOWO3TokAYNGqRVq1bJw8NDYWFhGj9+vAoV+t+urV69WhEREdqxY4f8/Pz0yiuvZHsx6dSpU/Xee+8pPj5e9evX10cffaQmTZrkuv7MzEwdPXpUnp6estlst3QsAAAAAPx9GWN09uxZVahQQS4ud/B8mgPfsWf59ddfTZUqVUy9evXMCy+8YLUPHDjQ+Pn5mejoaPPbb7+Zpk2bmvvuu8+af+nSJVO3bl0TEhJiNm/ebJYuXWpKly5tRo8ebfX5448/TLFixUxERITZuXOn+eijj4yrq6tZvny51WfOnDnGzc3NfP7552bHjh1mwIABxsfHxyQkJOR6Hw4fPnzdFzUzMTExMTExMTExMf2zpsOHD99aUMojhz9Q5dy5c2rQoIGmTZumN998U4GBgZo0aZKSkpJUpkwZzZ49W4899pgkaffu3apdu7ZiY2PVtGlTLVu2TB07dtTRo0ets3kzZszQyJEjdeLECbm5uWnkyJFasmSJtm/fbm2zW7duSkxM1PLlyyVJQUFBaty4saZMmSLp8lk4Pz8/DRkyRKNGjcrVfiQlJcnHx0eHDx+Wl5dXfh4iAAAAAH8jycnJ8vPzU2Jiory9ve/Ydh1+WWZ4eLg6dOigkJAQvfnmm1b7xo0blZ6erpCQEKutVq1auuuuu6xwFxsbq4CAALvLNENDQzVo0CDt2LFD9957r2JjY+3WkdVn6NChkqS0tDRt3LhRo0ePtua7uLgoJCREsbGx16w7NTVVqamp1uezZ89Kkry8vAh3AAAAAO747VoODXdz5szRpk2btGHDhmzz4uPj5ebmJh8fH7v2cuXKKT4+3upzZbDLmp8173p9kpOTdeHCBZ05c0YZGRk59tm9e/c1ax8/frxee+213O0oAAAAANxmDnta5uHDh/XCCy9o1qxZf8sXaY4ePVpJSUnWdPjwYUeXBAAAAOAfzGHhbuPGjTp+/LgaNGigQoUKqVChQoqJidHkyZNVqFAhlStXTmlpaUpMTLRbLiEhQb6+vpIkX19fJSQkZJufNe96fby8vFS0aFGVLl1arq6uOfbJWkdO3N3drUswuRQTAAAAgKM5LNy1bt1a27ZtU1xcnDU1atRIPXr0sP534cKFFR0dbS2zZ88eHTp0SMHBwZKk4OBgbdu2TcePH7f6REVFycvLS/7+/lafK9eR1SdrHW5ubmrYsKFdn8zMTEVHR1t9AAAAAKCgc9g9d56enqpbt65dW/HixVWqVCmrvV+/foqIiFDJkiXl5eWlIUOGKDg4WE2bNpUktWnTRv7+/urZs6cmTJig+Ph4vfLKKwoPD5e7u7skaeDAgZoyZYpGjBihvn37auXKlZo3b56WLFlibTciIkJhYWFq1KiRmjRpokmTJiklJUV9+vS5Q0cDAAAAAG6Nw5+WeT0TJ06Ui4uLunbtavcS8yyurq76/vvvNWjQIAUHB6t48eIKCwvT66+/bvWpWrWqlixZomHDhunDDz9UpUqV9Nlnnyk0NNTq8+STT+rEiRMaM2aM4uPjFRgYqOXLl2d7yAoAAAAAFFQOf8+ds0hOTpa3t7eSkpK4/w4AAAD4B3NUNnDYPXcAAAAAgPxDuAMAAAAAJ0C4AwAAAAAnQLgDAAAAACdAuAMAAAAAJ0C4AwAAAAAnQLgDAAAAACdAuAMAAAAAJ1DI0QXg9rDZHF2BYxnj6AoAAACAO4szdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBBwa7qZPn6569erJy8tLXl5eCg4O1rJly6z5rVq1ks1ms5sGDhxot45Dhw6pQ4cOKlasmMqWLavhw4fr0qVLdn1Wr16tBg0ayN3dXTVq1FBkZGS2WqZOnaoqVaqoSJEiCgoK0q+//npb9hkAAAAAbgeHhrtKlSrpnXfe0caNG/Xbb7/pwQcfVOfOnbVjxw6rz4ABA3Ts2DFrmjBhgjUvIyNDHTp0UFpamtavX68vvvhCkZGRGjNmjNXnwIED6tChgx544AHFxcVp6NCh6t+/v1asWGH1mTt3riIiIjR27Fht2rRJ9evXV2hoqI4fP35nDgQAAAAA3CKbMcY4uogrlSxZUu+995769eunVq1aKTAwUJMmTcqx77Jly9SxY0cdPXpU5cqVkyTNmDFDI0eO1IkTJ+Tm5qaRI0dqyZIl2r59u7Vct27dlJiYqOXLl0uSgoKC1LhxY02ZMkWSlJmZKT8/Pw0ZMkSjRo3KcdupqalKTU21PicnJ8vPz09JSUny8vLKj0NxS2w2R1fgWAXrVw0AAIB/kuTkZHl7e9/xbFBg7rnLyMjQnDlzlJKSouDgYKt91qxZKl26tOrWravRo0fr/Pnz1rzY2FgFBARYwU6SQkNDlZycbJ39i42NVUhIiN22QkNDFRsbK0lKS0vTxo0b7fq4uLgoJCTE6pOT8ePHy9vb25r8/Pxu7QAAAAAAwC0o5OgCtm3bpuDgYF28eFEeHh5atGiR/P39JUlPPfWUKleurAoVKmjr1q0aOXKk9uzZo6+//lqSFB8fbxfsJFmf4+Pjr9snOTlZFy5c0JkzZ5SRkZFjn927d1+z7tGjRysiIsL6nHXmDgAAAAAcweHhrmbNmoqLi1NSUpIWLFigsLAwxcTEyN/fX88884zVLyAgQOXLl1fr1q21f/9+Va9e3YFVS+7u7nJ3d3doDQAAAACQxeGXZbq5ualGjRpq2LChxo8fr/r16+vDDz/MsW9QUJAkad++fZIkX19fJSQk2PXJ+uzr63vdPl5eXipatKhKly4tV1fXHPtkrQMAAAAACjqHh7urZWZm2j2o5EpxcXGSpPLly0uSgoODtW3bNrunWkZFRcnLy8u6tDM4OFjR0dF264mKirLu63Nzc1PDhg3t+mRmZio6Otru3j8AAAAAKMgcelnm6NGj1a5dO9111106e/asZs+erdWrV2vFihXav3+/Zs+erfbt26tUqVLaunWrhg0bphYtWqhevXqSpDZt2sjf3189e/bUhAkTFB8fr1deeUXh4eHWJZMDBw7UlClTNGLECPXt21crV67UvHnztGTJEquOiIgIhYWFqVGjRmrSpIkmTZqklJQU9enTxyHHBQAAAADyyqHh7vjx4+rVq5eOHTsmb29v1atXTytWrNBDDz2kw4cP68cff7SClp+fn7p27apXXnnFWt7V1VXff/+9Bg0apODgYBUvXlxhYWF6/fXXrT5Vq1bVkiVLNGzYMH344YeqVKmSPvvsM4WGhlp9nnzySZ04cUJjxoxRfHy8AgMDtXz58mwPWQEAAACAgqrAvefu78pR77K4Ft5z5+gKAAAA8E/1j3/PHQAAAADg5hHuAAAAAMAJEO4AAAAAwAkQ7gAAAADACRDuAAAAAMAJEO4AAAAAwAkQ7gAAAADACRDuAAAAAMAJEO4AAAAAwAkQ7gAAAADACRDuAAAAAMAJEO4AAAAAwAkQ7gAAAADACRDuAAAAAMAJEO4AAAAAwAkQ7gAAAADACRDuAAAAAMAJEO4AAAAAwAkQ7gAAAADACRDuAAAAAMAJEO4AAAAAwAkQ7gAAAADACRDuAAAAAMAJEO4AAAAAwAkQ7gAAAADACRDuAAAAAMAJEO4AAAAAwAkQ7gAAAADACRDuAAAAAMAJEO4AAAAAwAkQ7gAAAADACRDuAAAAAMAJEO4AAAAAwAkQ7gAAAADACRDuAAAAAMAJEO4AAAAAwAk4NNxNnz5d9erVk5eXl7y8vBQcHKxly5ZZ8y9evKjw8HCVKlVKHh4e6tq1qxISEuzWcejQIXXo0EHFihVT2bJlNXz4cF26dMmuz+rVq9WgQQO5u7urRo0aioyMzFbL1KlTVaVKFRUpUkRBQUH69ddfb8s+AwAAAMDt4NBwV6lSJb3zzjvauHGjfvvtNz344IPq3LmzduzYIUkaNmyYvvvuO82fP18xMTE6evSoHn30UWv5jIwMdejQQWlpaVq/fr2++OILRUZGasyYMVafAwcOqEOHDnrggQcUFxenoUOHqn///lqxYoXVZ+7cuYqIiNDYsWO1adMm1a9fX6GhoTp+/PidOxgAAAAAcAtsxhjj6CKuVLJkSb333nt67LHHVKZMGc2ePVuPPfaYJGn37t2qXbu2YmNj1bRpUy1btkwdO3bU0aNHVa5cOUnSjBkzNHLkSJ04cUJubm4aOXKklixZou3bt1vb6NatmxITE7V8+XJJUlBQkBo3bqwpU6ZIkjIzM+Xn56chQ4Zo1KhRuao7OTlZ3t7eSkpKkpeXV34ekptiszm6AscqWL9qAAAA/JM4KhsUmHvuMjIyNGfOHKWkpCg4OFgbN25Uenq6QkJCrD61atXSXXfdpdjYWElSbGysAgICrGAnSaGhoUpOTrbO/sXGxtqtI6tP1jrS0tK0ceNGuz4uLi4KCQmx+uQkNTVVycnJdhMAAAAAOIrDw922bdvk4eEhd3d3DRw4UIsWLZK/v7/i4+Pl5uYmHx8fu/7lypVTfHy8JCk+Pt4u2GXNz5p3vT7Jycm6cOGCTp48qYyMjBz7ZK0jJ+PHj5e3t7c1+fn53dT+AwAAAEB+cHi4q1mzpuLi4vTLL79o0KBBCgsL086dOx1d1g2NHj1aSUlJ1nT48GFHlwQAAADgH6yQowtwc3NTjRo1JEkNGzbUhg0b9OGHH+rJJ59UWlqaEhMT7c7eJSQkyNfXV5Lk6+ub7amWWU/TvLLP1U/YTEhIkJeXl4oWLSpXV1e5urrm2CdrHTlxd3eXu7v7ze00AAAAAOQzh5+5u1pmZqZSU1PVsGFDFS5cWNHR0da8PXv26NChQwoODpYkBQcHa9u2bXZPtYyKipKXl5f8/f2tPleuI6tP1jrc3NzUsGFDuz6ZmZmKjo62+gAAAABAQefQM3ejR49Wu3btdNddd+ns2bOaPXu2Vq9erRUrVsjb21v9+vVTRESESpYsKS8vLw0ZMkTBwcFq2rSpJKlNmzby9/dXz549NWHCBMXHx+uVV15ReHi4dVZt4MCBmjJlikaMGKG+fftq5cqVmjdvnpYsWWLVERERobCwMDVq1EhNmjTRpEmTlJKSoj59+jjkuAAAAABAXjk03B0/fly9evXSsWPH5O3trXr16mnFihV66KGHJEkTJ06Ui4uLunbtqtTUVIWGhmratGnW8q6urvr+++81aNAgBQcHq3jx4goLC9Prr79u9alataqWLFmiYcOG6cMPP1SlSpX02WefKTQ01Orz5JNP6sSJExozZozi4+MVGBio5cuXZ3vICgAAAAAUVAXuPXd/V7znrmDhVw0AAABH+ce/5w4AAAAAcPMIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQcGu7Gjx+vxo0by9PTU2XLllWXLl20Z88euz6tWrWSzWazmwYOHGjX59ChQ+rQoYOKFSumsmXLavjw4bp06ZJdn9WrV6tBgwZyd3dXjRo1FBkZma2eqVOnqkqVKipSpIiCgoL066+/5vs+AwAAAMDt4NBwFxMTo/DwcP3888+KiopSenq62rRpo5SUFLt+AwYM0LFjx6xpwoQJ1ryMjAx16NBBaWlpWr9+vb744gtFRkZqzJgxVp8DBw6oQ4cOeuCBBxQXF6ehQ4eqf//+WrFihdVn7ty5ioiI0NixY7Vp0ybVr19foaGhOn78+O0/EAAAAABwi2zGGOPoIrKcOHFCZcuWVUxMjFq0aCHp8pm7wMBATZo0Kcdlli1bpo4dO+ro0aMqV66cJGnGjBkaOXKkTpw4ITc3N40cOVJLlizR9u3breW6deumxMRELV++XJIUFBSkxo0ba8qUKZKkzMxM+fn5aciQIRo1atQNa09OTpa3t7eSkpLk5eV1K4chX9hsjq7AsQrOrxoAAAD/NI7KBgXqnrukpCRJUsmSJe3aZ82apdKlS6tu3boaPXq0zp8/b82LjY1VQECAFewkKTQ0VMnJydqxY4fVJyQkxG6doaGhio2NlSSlpaVp48aNdn1cXFwUEhJi9blaamqqkpOT7SYAAAAAcJRCji4gS2ZmpoYOHapmzZqpbt26VvtTTz2lypUrq0KFCtq6datGjhypPXv26Ouvv5YkxcfH2wU7Sdbn+Pj46/ZJTk7WhQsXdObMGWVkZOTYZ/fu3TnWO378eL322mu3ttMAAAAAkE8KTLgLDw/X9u3btW7dOrv2Z555xvrfAQEBKl++vFq3bq39+/erevXqd7pMy+jRoxUREWF9Tk5Olp+fn8PqAQAAAPDPViDC3eDBg/X9999rzZo1qlSp0nX7BgUFSZL27dun6tWry9fXN9tTLRMSEiRJvr6+1v/Naruyj5eXl4oWLSpXV1e5urrm2CdrHVdzd3eXu7t77ncSAAAAAG4jh95zZ4zR4MGDtWjRIq1cuVJVq1a94TJxcXGSpPLly0uSgoODtW3bNrunWkZFRcnLy0v+/v5Wn+joaLv1REVFKTg4WJLk5uamhg0b2vXJzMxUdHS01QcAAAAACjKHnrkLDw/X7Nmz9c0338jT09O6R87b21tFixbV/v37NXv2bLVv316lSpXS1q1bNWzYMLVo0UL16tWTJLVp00b+/v7q2bOnJkyYoPj4eL3yyisKDw+3zqwNHDhQU6ZM0YgRI9S3b1+tXLlS8+bN05IlS6xaIiIiFBYWpkaNGqlJkyaaNGmSUlJS1KdPnzt/YAAAAAAgj/L8KoRNmzapcOHCCggIkCR98803mjlzpvz9/TVu3Di5ubnlfuPXeF7/zJkz1bt3bx0+fFhPP/20tm/frpSUFPn5+emRRx7RK6+8YvdI0T///FODBg3S6tWrVbx4cYWFhemdd95RoUL/y66rV6/WsGHDtHPnTlWqVEmvvvqqevfubbfdKVOm6L333lN8fLwCAwM1efJk6zLQG+FVCAULr0IAAACAozgqG+Q53DVu3FijRo1S165d9ccff6hOnTp65JFHtGHDBnXo0OGa76NzdoS7goVwBwAAAEf527zn7vfff1dgYKAkaf78+WrRooVmz56tyMhILVy4ML/rAwAAAADkQp7DnTFGmZmZkqQff/xR7du3lyT5+fnp5MmT+VsdAAAAACBX8hzuGjVqpDfffFP//e9/FRMTow4dOkiSDhw4kO0l4AAAAACAOyPP4W7SpEnatGmTBg8erJdfflk1atSQJC1YsED33XdfvhcIAAAAALixPD9Q5VouXrwoV1dXFS5cOD9W97fDA1UKFh6oAgAAAEf52zxQRZISExP12WefafTo0Tp9+rQkaefOnXYvEgcAAAAA3Dl5fon51q1b1bp1a/n4+OjgwYMaMGCASpYsqa+//lqHDh3Sl19+eTvqBAAAAABcR57P3EVERKhPnz7au3evihQpYrW3b99ea9asydfiAAAAAAC5k+dwt2HDBj377LPZ2itWrKj4+Ph8KQoAAAAAkDd5Dnfu7u5KTk7O1v7777+rTJky+VIUAAAAACBv8hzuHn74Yb3++utKT0+XJNlsNh06dEgjR45U165d871AAAAAAMCN5Tncvf/++zp37pzKli2rCxcuqGXLlqpRo4Y8PT311ltv3Y4aAQAAAAA3kOenZXp7eysqKkrr1q3T1q1bde7cOTVo0EAhISG3oz4AAAAAQC7k20vM/+l4iXnBwq8aAAAAjuKobJCrM3eTJ0/O9Qqff/75my4GAAAAAHBzcnXmrmrVqrlbmc2mP/7445aL+jvizF3Bwpk7AAAAOEqBPnN34MCB210HAAAAAOAW5PlpmQAAAACAgifP4a5r16569913s7VPmDBBjz/+eL4UBQAAAADImzyHuzVr1qh9+/bZ2tu1a6c1a9bkS1EAAAAAgLzJc7g7d+6c3NzcsrUXLlxYycnJ+VIUAAAAACBv8hzuAgICNHfu3Gztc+bMkb+/f74UBQAAAADIm1w9LfNKr776qh599FHt379fDz74oCQpOjpaX331lebPn5/vBQIAAAAAbizP4a5Tp05avHix3n77bS1YsEBFixZVvXr19OOPP6ply5a3o0YAAAAAwA3k6iXmuDFeYl6w8KsGAACAozgqG+T5nruwsDCeigkAAAAABUyew11SUpJCQkJ099136+2339aRI0duR10AAAAAgDzIc7hbvHixjhw5okGDBmnu3LmqUqWK2rVrpwULFig9Pf121AgAAAAAuIE8hztJKlOmjCIiIrRlyxb98ssvqlGjhnr27KkKFSpo2LBh2rt3b37XCQAAAAC4jpsKd1mOHTumqKgoRUVFydXVVe3bt9e2bdvk7++viRMn5leNAAAAAIAbyHO4S09P18KFC9WxY0dVrlxZ8+fP19ChQ3X06FF98cUX+vHHHzVv3jy9/vrrt6NeAAAAAEAO8vyeu/LlyyszM1Pdu3fXr7/+qsDAwGx9HnjgAfn4+ORDeQAAAACA3MhzuJs4caIef/xxFSlS5Jp9fHx8dODAgVsqDAAAAACQe7m+LDMjI0Nbt27VY489li3YnT9/Xlu3blVmZma+FwgAAAAAuLFch7v//ve/6tu3r9zc3LLNc3NzU9++fTV79ux8LQ4AAAAAkDu5Dnf/+c9/9NJLL8nV1TXbvEKFCmnEiBH65JNP8rU4AAAAAEDu5Drc7dmzR02bNr3m/MaNG2vXrl35UhQAAAAAIG9yHe5SUlKUnJx8zflnz57V+fPn87Tx8ePHq3HjxvL09FTZsmXVpUsX7dmzx67PxYsXFR4erlKlSsnDw0Ndu3ZVQkKCXZ9Dhw6pQ4cOKlasmMqWLavhw4fr0qVLdn1Wr16tBg0ayN3dXTVq1FBkZGS2eqZOnaoqVaqoSJEiCgoK0q+//pqn/QEAAAAAR8l1uLv77ru1fv36a85ft26d7r777jxtPCYmRuHh4fr5558VFRWl9PR0tWnTRikpKVafYcOG6bvvvtP8+fMVExOjo0eP6tFHH7XmZ2RkqEOHDkpLS9P69ev1xRdfKDIyUmPGjLH6HDhwQB06dNADDzyguLg4DR06VP3799eKFSusPnPnzlVERITGjh2rTZs2qX79+goNDdXx48fztE8AAAAA4BAml959911TqlQps2XLlmzz4uLiTKlSpcy7776b29Xl6Pjx40aSiYmJMcYYk5iYaAoXLmzmz59v9dm1a5eRZGJjY40xxixdutS4uLiY+Ph4q8/06dONl5eXSU1NNcYYM2LECFOnTh27bT355JMmNDTU+tykSRMTHh5ufc7IyDAVKlQw48ePz1XtSUlJRpJJSkrK417fHtI/ewIAAAAcxVHZINdn7oYNG6aAgAA1bNhQ7dq107BhwzRs2DC1a9dOjRo1Ut26dTVs2LBbCppJSUmSpJIlS0qSNm7cqPT0dIWEhFh9atWqpbvuukuxsbGSpNjYWAUEBKhcuXJWn9DQUCUnJ2vHjh1WnyvXkdUnax1paWnauHGjXR8XFxeFhIRYfa6Wmpqq5ORkuwkAAAAAHCXX4a5w4cL64Ycf9NZbb+nYsWP65JNP9PHHH+vYsWN666239MMPP6hw4cI3XUhmZqaGDh2qZs2aqW7dupKk+Ph4ubm5ycfHx65vuXLlFB8fb/W5Mthlzc+ad70+ycnJunDhgk6ePKmMjIwc+2St42rjx4+Xt7e3Nfn5+d3cjgMAAABAPiiUl86FCxfWiBEjNGLEiHwvJDw8XNu3b9e6devyfd23w+jRoxUREWF9Tk5OJuABAAAAcJg8hbvbZfDgwfr++++1Zs0aVapUyWr39fVVWlqaEhMT7c7eJSQkyNfX1+pz9VMts56meWWfq5+wmZCQIC8vLxUtWlSurq5ydXXNsU/WOq7m7u4ud3f3m9thAAAAAMhnub4s83Ywxmjw4MFatGiRVq5cqapVq9rNb9iwoQoXLqzo6Girbc+ePTp06JCCg4MlScHBwdq2bZvdUy2joqLk5eUlf39/q8+V68jqk7UONzc3NWzY0K5PZmamoqOjrT4AAAAAUJA59MxdeHi4Zs+erW+++Uaenp7W/W3e3t4qWrSovL291a9fP0VERKhkyZLy8vLSkCFDFBwcbL1QvU2bNvL391fPnj01YcIExcfH65VXXlF4eLh1Zm3gwIGaMmWKRowYob59+2rlypWaN2+elixZYtUSERGhsLAwNWrUSE2aNNGkSZOUkpKiPn363PkDAwAAAAB5ZDPGGIdt3GbLsX3mzJnq3bu3pMsvMX/xxRf11VdfKTU1VaGhoZo2bZrd5ZJ//vmnBg0apNWrV6t48eIKCwvTO++8o0KF/pddV69erWHDhmnnzp2qVKmSXn31VWsbWaZMmaL33ntP8fHxCgwM1OTJkxUUFJSrfUlOTpa3t7eSkpLk5eWVtwNxG1zj0P5jOO5XDQAAgH86R2WDPIe77du3W0+zvNrixYvVpUuX/Kjrb4dwV7AQ7gAAAOAojsoGeb7nLjQ0VAcOHMjWvnDhQvXo0SNfigIAAAAA5E2ew13//v0VEhJi9/63uXPnqlevXoqMjMzP2gAAAAAAuZTnB6q89tprOn36tEJCQrRmzRotX75c/fv313//+1917dr1dtQIAAAAALiBm3pa5kcffaQePXqoadOmOnLkiL766it17tw5v2sDAAAAAORSrsLdt99+m63t0Ucf1dq1a9W9e3fZbDarz8MPP5y/FQIAAAAAbihXT8t0ccndrXk2m00ZGRm3XNTfEU/LLFh4WiYAAAAcxVHZIFdn7jIzM293HQAAAACAW5Dnp2UCAAAAAAqePIe7559/XpMnT87WPmXKFA0dOjQ/agIAAAAA5FGew93ChQvVrFmzbO333XefFixYkC9FAQAAAADyJs/h7tSpU/L29s7W7uXlpZMnT+ZLUQAAAACAvMlzuKtRo4aWL1+erX3ZsmWqVq1avhQFAAAAAMibPL/EPCIiQoMHD9aJEyf04IMPSpKio6P1/vvva9KkSfldHwAAAAAgF/Ic7vr27avU1FS99dZbeuONNyRJVapU0fTp09WrV698LxAAAAAAcGO5eon5tZw4cUJFixaVh4dHftb0t8RLzAsWXmIOAAAARynQLzHPyYkTJ7Rnzx5JUq1atVS6dOl8KwoAAAAAkDd5fqBKSkqK+vbtq/Lly6tFixZq0aKFypcvr379+un8+fO3o0YAAAAAwA3kOdxFREQoJiZG3333nRITE5WYmKhvvvlGMTExevHFF29HjQAAAACAG8jzPXelS5fWggUL1KpVK7v2VatW6YknntCJEyfys76/De65K1i45w4AAACO4qhskOczd+fPn1e5cuWytZctW5bLMgEAAADAQfIc7oKDgzV27FhdvHjRartw4YJee+01BQcH52txAAAAAIDcyfPTMj/88EOFhoaqUqVKql+/viRpy5YtKlKkiFasWJHvBQIAAAAAbuym3nN3/vx5zZo1S7t375Yk1a5dWz169FDRokXzvcC/C+65K1i45w4AAACO8rd6z12xYsU0YMCA/K4FAAAAAHCTchXuvv3221yv8OGHH77pYgAAAAAANydX4a5Lly65WpnNZlNGRsat1AMAAAAAuAm5CneZmZm3uw4AAAAAwC3I86sQAAAAAAAFT67D3cqVK+Xv76/k5ORs85KSklSnTh2tWbMmX4sDAAAAAOROrsPdpEmTNGDAgBwf5ent7a1nn31WEydOzNfiAAAAAAC5k+twt2XLFrVt2/aa89u0aaONGzfmS1EAAAAAgLzJdbhLSEhQ4cKFrzm/UKFCOnHiRL4UBQAAAADIm1yHu4oVK2r79u3XnL9161aVL18+X4oCAAAAAORNrsNd+/bt9eqrr+rixYvZ5l24cEFjx45Vx44d87U4AAAAAEDu2IwxJjcdExIS1KBBA7m6umrw4MGqWbOmJGn37t2aOnWqMjIytGnTJpUrV+62FlxQJScny9vbW0lJSTk+dOZOs9kcXYFj5e5XDQAAAOQ/R2WDXL3EXJLKlSun9evXa9CgQRo9erSyMqHNZlNoaKimTp36jw12AAAAAOBouQ53klS5cmUtXbpUZ86c0b59+2SM0d13360SJUrcrvoAAAAAALmQ63vurlSiRAk1btxYTZo0uaVgt2bNGnXq1EkVKlSQzWbT4sWL7eb37t1bNpvNbrr6dQynT59Wjx495OXlJR8fH/Xr10/nzp2z67N161Y1b95cRYoUkZ+fnyZMmJCtlvnz56tWrVoqUqSIAgICtHTp0pveLwAAAAC4024q3OWXlJQU1a9fX1OnTr1mn7Zt2+rYsWPW9NVXX9nN79Gjh3bs2KGoqCh9//33WrNmjZ555hlrfnJystq0aaPKlStr48aNeu+99zRu3Dh98sknVp/169ere/fu6tevnzZv3qwuXbqoS5cu1306KAAAAAAUJLl+oMrtZrPZtGjRInXp0sVq6927txITE7Od0cuya9cu+fv7a8OGDWrUqJEkafny5Wrfvr3++usvVahQQdOnT9fLL7+s+Ph4ubm5SZJGjRqlxYsXa/fu3ZKkJ598UikpKfr++++tdTdt2lSBgYGaMWNGjttOTU1Vamqq9Tk5OVl+fn48UKWAKBi/agAAAPwTOeqBKg49c5cbq1evVtmyZVWzZk0NGjRIp06dsubFxsbKx8fHCnaSFBISIhcXF/3yyy9WnxYtWljBTpJCQ0O1Z88enTlzxuoTEhJit93Q0FDFxsZes67x48fL29vbmvz8/PJlfwEAAADgZhTocNe2bVt9+eWXio6O1rvvvquYmBi1a9dOGRkZkqT4+HiVLVvWbplChQqpZMmSio+Pt/pc/RTPrM836pM1PyejR49WUlKSNR0+fPjWdhYAAAAAbkGenpZ5p3Xr1s363wEBAapXr56qV6+u1atXq3Xr1g6sTHJ3d5e7u7tDawAAAACALAX6zN3VqlWrptKlS2vfvn2SJF9fXx0/ftyuz6VLl3T69Gn5+vpafRISEuz6ZH2+UZ+s+QAAAABQ0P2twt1ff/2lU6dOqXz58pKk4OBgJSYmauPGjVaflStXKjMzU0FBQVafNWvWKD093eoTFRWlmjVrWq9xCA4OVnR0tN22oqKiFBwcfLt3CQAAAADyhUPD3blz5xQXF6e4uDhJ0oEDBxQXF6dDhw7p3LlzGj58uH7++WcdPHhQ0dHR6ty5s2rUqKHQ0FBJUu3atdW2bVsNGDBAv/76q3766ScNHjxY3bp1U4UKFSRJTz31lNzc3NSvXz/t2LFDc+fO1YcffqiIiAirjhdeeEHLly/X+++/r927d2vcuHH67bffNHjw4Dt+TAAAAADgZjj0VQirV6/WAw88kK09LCxM06dPV5cuXbR582YlJiaqQoUKatOmjd544w27h5+cPn1agwcP1nfffScXFxd17dpVkydPloeHh9Vn69atCg8P14YNG1S6dGkNGTJEI0eOtNvm/Pnz9corr+jgwYO6++67NWHCBLVv3z7X++Kox51eC69CcHQFAAAA+KdyVDYoMO+5+7sj3BUs/KoBAADgKLznDgAAAABw0wh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQcGu7WrFmjTp06qUKFCrLZbFq8eLHdfGOMxowZo/Lly6to0aIKCQnR3r177fqcPn1aPXr0kJeXl3x8fNSvXz+dO3fOrs/WrVvVvHlzFSlSRH5+fpowYUK2WubPn69atWqpSJEiCggI0NKlS/N9fwEAAADgdnFouEtJSVH9+vU1derUHOdPmDBBkydP1owZM/TLL7+oePHiCg0N1cWLF60+PXr00I4dOxQVFaXvv/9ea9as0TPPPGPNT05OVps2bVS5cmVt3LhR7733nsaNG6dPPvnE6rN+/Xp1795d/fr10+bNm9WlSxd16dJF27dvv307DwAAAAD5yGaMMY4uQpJsNpsWLVqkLl26SLp81q5ChQp68cUX9dJLL0mSkpKSVK5cOUVGRqpbt27atWuX/P39tWHDBjVq1EiStHz5crVv315//fWXKlSooOnTp+vll19WfHy83NzcJEmjRo3S4sWLtXv3bknSk08+qZSUFH3//fdWPU2bNlVgYKBmzJiRq/qTk5Pl7e2tpKQkeXl55ddhuWk2m6MrcKyC8asGAADAP5GjskGBvefuwIEDio+PV0hIiNXm7e2toKAgxcbGSpJiY2Pl4+NjBTtJCgkJkYuLi3755RerT4sWLaxgJ0mhoaHas2ePzpw5Y/W5cjtZfbK2k5PU1FQlJyfbTQAAAADgKAU23MXHx0uSypUrZ9derlw5a158fLzKli1rN79QoUIqWbKkXZ+c1nHlNq7VJ2t+TsaPHy9vb29r8vPzy+suAgAAAEC+KbDhrqAbPXq0kpKSrOnw4cOOLgkAAADAP1iBDXe+vr6SpISEBLv2hIQEa56vr6+OHz9uN//SpUs6ffq0XZ+c1nHlNq7VJ2t+Ttzd3eXl5WU3AQAAAICjFNhwV7VqVfn6+io6OtpqS05O1i+//KLg4GBJUnBwsBITE7Vx40arz8qVK5WZmamgoCCrz5o1a5Senm71iYqKUs2aNVWiRAmrz5XbyeqTtR0AAAAAKOgcGu7OnTunuLg4xcXFSbr8EJW4uDgdOnRINptNQ4cO1Ztvvqlvv/1W27ZtU69evVShQgXriZq1a9dW27ZtNWDAAP3666/66aefNHjwYHXr1k0VKlSQJD311FNyc3NTv379tGPHDs2dO1cffvihIiIirDpeeOEFLV++XO+//752796tcePG6bffftPgwYPv9CEBAAAAgJvi0FchrF69Wg888EC29rCwMEVGRsoYo7Fjx+qTTz5RYmKi7r//fk2bNk333HOP1ff06dMaPHiwvvvuO7m4uKhr166aPHmyPDw8rD5bt25VeHi4NmzYoNKlS2vIkCEaOXKk3Tbnz5+vV155RQcPHtTdd9+tCRMmqH379rneF16FULDwKgQAAAA4iqOyQYF5z93fHeGuYOFXDQAAAEfhPXcAAAAAgJtGuAMAAAAAJ0C4AwAAAAAnQLgDAAAAACdAuAMAAAAAJ0C4AwAAAAAnQLgDAAAAACdAuAMAAAAAJ0C4AwAAAAAnQLgDAAAAACdAuAMAAAAAJ0C4AwAAAAAnQLgDAAAAACdAuAMAAAAAJ0C4AwAAAAAnQLgDAAAAACdAuAMAAAAAJ0C4AwAAAAAnQLgDAAAAACdAuAMAAAAAJ0C4AwAAAAAnQLgDAAAAACdAuAMAAAAAJ0C4AwAAAAAnQLgDAAAAACdAuAMAAAAAJ0C4AwAAAAAnQLgDAAAAACdAuAMAAAAAJ0C4AwAAAAAnQLgDAAAAACdAuAMAAAAAJ0C4AwAAAAAnQLgDAAAAACdAuAMAAAAAJ0C4AwAAAAAnQLgDAAAAACdQoMPduHHjZLPZ7KZatWpZ8y9evKjw8HCVKlVKHh4e6tq1qxISEuzWcejQIXXo0EHFihVT2bJlNXz4cF26dMmuz+rVq9WgQQO5u7urRo0aioyMvBO7BwAAAAD5pkCHO0mqU6eOjh07Zk3r1q2z5g0bNkzfffed5s+fr5iYGB09elSPPvqoNT8jI0MdOnRQWlqa1q9fry+++EKRkZEaM2aM1efAgQPq0KGDHnjgAcXFxWno0KHq37+/VqxYcUf3EwAAAABuhc0YYxxdxLWMGzdOixcvVlxcXLZ5SUlJKlOmjGbPnq3HHntMkrR7927Vrl1bsbGxatq0qZYtW6aOHTvq6NGjKleunCRpxowZGjlypE6cOCE3NzeNHDlSS5Ys0fbt2611d+vWTYmJiVq+fHmua01OTpa3t7eSkpLk5eV1azueD2w2R1fgWAX3Vw0AAABn56hsUODP3O3du1cVKlRQtWrV1KNHDx06dEiStHHjRqWnpyskJMTqW6tWLd11112KjY2VJMXGxiogIMAKdpIUGhqq5ORk7dixw+pz5Tqy+mSt41pSU1OVnJxsNwEAAACAoxTocBcUFKTIyEgtX75c06dP14EDB9S8eXOdPXtW8fHxcnNzk4+Pj90y5cqVU3x8vCQpPj7eLthlzc+ad70+ycnJunDhwjVrGz9+vLy9va3Jz8/vVncXAAAAAG5aIUcXcD3t2rWz/ne9evUUFBSkypUra968eSpatKgDK5NGjx6tiIgI63NycjIBDwAAAIDDFOgzd1fz8fHRPffco3379snX11dpaWlKTEy065OQkCBfX19Jkq+vb7anZ2Z9vlEfLy+v6wZId3d3eXl52U0AAAAA4Ch/q3B37tw57d+/X+XLl1fDhg1VuHBhRUdHW/P37NmjQ4cOKTg4WJIUHBysbdu26fjx41afqKgoeXl5yd/f3+pz5Tqy+mStAwAAAAD+Dgp0uHvppZcUExOjgwcPav369XrkkUfk6uqq7t27y9vbW/369VNERIRWrVqljRs3qk+fPgoODlbTpk0lSW3atJG/v7969uypLVu2aMWKFXrllVcUHh4ud3d3SdLAgQP1xx9/aMSIEdq9e7emTZumefPmadiwYY7cdQAAAADIkwJ9z91ff/2l7t2769SpUypTpozuv/9+/fzzzypTpowkaeLEiXJxcVHXrl2Vmpqq0NBQTZs2zVre1dVV33//vQYNGqTg4GAVL15cYWFhev31160+VatW1ZIlSzRs2DB9+OGHqlSpkj777DOFhobe8f0FAAAAgJtVoN9z93fCe+4KFn7VAAAAcBTecwcAAAAAuGkF+rJMAChIOCPu6ArgbBhTjq4AgLPhzB0AAAAAOAHCHQAAAAA4AcIdAAAAADgBwh0AAAAAOAHCHQAAAAA4AcIdAAAAADgBwh0AAAAAOAHCHQAAAAA4AcIdAAAAADgBwh0AAAAAOAHCHQAAAAA4AcIdAAAAADgBwh0AAAAAOAHCHQAAAAA4AcIdAAAAADgBwh0AAAAAOAHCHQAAAAA4AcIdAAAAADgBwh0AAAAAOAHCHQAAAAA4AcIdAAAAADgBwh0AAAAAOAHCHQAAAAA4AcIdAAAAADgBwh0AAAAAOAHCHQAAAAA4AcIdAAAAADgBwh0AAAAAOAHCHQAAAAA4AcIdAAAAADgBwh0AAAAAOAHCHQAAAAA4AcIdAAAAADgBwh0AAAAAOAHCHQAAAAA4AcLdVaZOnaoqVaqoSJEiCgoK0q+//urokgAAAADghgh3V5g7d64iIiI0duxYbdq0SfXr11doaKiOHz/u6NIAAAAA4LoId1f44IMPNGDAAPXp00f+/v6aMWOGihUrps8//9zRpQEAAADAdRVydAEFRVpamjZu3KjRo0dbbS4uLgoJCVFsbGy2/qmpqUpNTbU+JyUlSZKSk5Nvf7G4Ib4GIP8xroD8xZjC7eDt7egKHOv//pPc4bIygTHmjm6XcPd/Tp48qYyMDJUrV86uvVy5ctq9e3e2/uPHj9drr72Wrd3Pz++21Yjc+6f/wwbcDowrIH8xpoD8V9DG1dmzZ+V9B4si3N2k0aNHKyIiwvqcmZmp06dPq1SpUrLZbA6szPGSk5Pl5+enw4cPy8vLy9HlAE6BcQXkL8YUkP8YV/9jjNHZs2dVoUKFO7pdwt3/KV26tFxdXZWQkGDXnpCQIF9f32z93d3d5e7ubtfm4+NzO0v82/Hy8vrHD2wgvzGugPzFmALyH+Pqsjt5xi4LD1T5P25ubmrYsKGio6OttszMTEVHRys4ONiBlQEAAADAjXHm7goREREKCwtTo0aN1KRJE02aNEkpKSnq06ePo0sDAAAAgOsi3F3hySef1IkTJzRmzBjFx8crMDBQy5cvz/aQFVyfu7u7xo4dm+2yVQA3j3EF5C/GFJD/GFeOZzN3+vmcAAAAAIB8xz13AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3DlalShVNmjTJ0WX87Rw8eFA2m01xcXG3fVt8R38vfF83hzGF6+E7uzmMK1wL39fNYUzlgoEJCwszksyzzz6bbd5zzz1nJJmwsLBcrevAgQNGktm8eXOu+h8/ftykpKTkqm/Hjh1NaGhojvPWrFljJJktW7bkal3XsmrVKiPJnDlz5pbWc7Xz58+bEiVKmFKlSpmLFy/madmwsDDTuXNnu7ZLly6ZY8eOmfT09HyrcebMmcbb2ztbe16+o/wyZcoUU7lyZePu7m6aNGlifvnllzu6/VvFmPofxpR3tvY7PaZiYmJMx44dTfny5Y0ks2jRoju27fzEuPofxpV3tvY7Pa7efvtt06hRI+Ph4WHKlCljOnfubHbv3n3Htp8fGFP/w5jyztZ+p8fUtGnTTEBAgPH09DSenp6madOmZunSpXleD2fu/o+fn5/mzJmjCxcuWG0XL17U7Nmzddddd+X79tLS0iRJZcqUUbFixXK1TL9+/RQVFaW//vor27yZM2eqUaNGqlevXr7WebOMMbp06ZL1eeHChapTp45q1aqlxYsX3/L6XV1d5evrq0KFbv/bPPLyHeWHuXPnKiIiQmPHjtWmTZtUv359hYaG6vjx43eshvzAmMpfjKmbl5KSovr162vq1Kl3bJu3C+MqfzGubl5MTIzCw8P1888/KyoqSunp6WrTpo1SUlLuWA35gTGVvxhTN69SpUp65513tHHjRv3222968MEH1blzZ+3YsSNvK8rn0Pm3lPWXgbp165r/9//+n9U+a9YsU69ePdO5c2frLzfLli0zzZo1M97e3qZkyZKmQ4cOZt++fdYykuymli1b2m3jzTffNOXLlzdVqlQxxhhTuXJlM3HiRGPM5b+aFC5c2KxZs8Za37vvvmvKlClj4uPjTXp6uilXrpx544037Oo/e/as8fDwMNOnTzfGGLN27Vpz//33myJFiphKlSqZIUOGmHPnzln9L168aEaMGGEqVapk3NzcTPXq1c1nn31m/dXpyilrvy9evGiGDBliypQpY9zd3U2zZs3Mr7/+aq0z6y8+S5cuNQ0aNDCFCxc2q1atsua3atXKzJgxw0yfPt089NBD2b6D7du3mw4dOhhPT0/j4eFh7r//frNv3z4zduzYbDWtWrXK7i9kGRkZpmLFimbatGl269y0aZOx2Wzm4MGDxhhj3n//fVO3bl1TrFgxU6lSJTNo0CBz9uxZu/qvnMaOHZvtOzLGmD///NM8/PDDpnjx4sbT09M8/vjjJj4+3po/duxYU79+ffPll1+aypUrGy8vL/Pkk0+a5OTkbPudkyZNmpjw8HDrc0ZGhqlQoYIZP358rpYvCBhTjKmCNKaupL/5mTvGFeOqII4rYy6f5ZBkYmJibmp5R2BMMaYK8pgyxpgSJUqYzz77LE/LEO7M/wbeBx98YFq3bm21t27d2kycONFucC9YsMAsXLjQ7N2712zevNl06tTJBAQEmIyMDGOMMb/++quRZH788Udz7Ngxc+rUKWsbHh4epmfPnmb79u1m+/btxpjsP5zhw4ebypUrm8TERLNp0ybj5uZmvvnmG7v51atXN5mZmVbb559/booWLWoSExPNvn37TPHixc3EiRPN77//bn766Sdz7733mt69e1v9n3jiCePn52e+/vprs3//fvPjjz+aOXPmmEuXLpmFCxcaSWbPnj3m2LFjJjEx0RhjzPPPP28qVKhgli5danbs2GHCwsJMiRIlrP3LGhz16tUzP/zwg9m3b581b9++fcbd3d2cPn3anDp1yhQpUsQacMYY89dff5mSJUuaRx991GzYsMHs2bPHfP7552b37t3m7Nmz5oknnjBt27Y1x44dM8eOHTOpqanZLn946aWXzP3332/3vb744ot2bRMnTjQrV640Bw4cMNHR0aZmzZpm0KBBxhhjUlNTzaRJk4yXl5e1nayBf+V3lJGRYQIDA839999vfvvtN/Pzzz+bhg0bWv+IG3N5cHt4eJhHH33UbNu2zaxZs8b4+vqaf/3rX9f8DWZJTU01rq6u2f7js1evXubhhx++4fIFBWOKMVVQxtTVnCHcMa4YVwVtXBljzN69e40ks23btpta3hEYU4ypgjqmLl26ZL766ivj5uZmduzYkadlCXfmf4P7+PHjxt3d3Rw8eNAcPHjQFClSxJw4ccJucF/txIkTdv+YXeua67CwMFOuXDmTmppq13714E5NTTWBgYHmiSeeMP7+/mbAgAF2/Xft2mX99SJL8+bNzdNPP22MMaZfv37mmWeesVtm7dq1xsXFxVy4cMHs2bPHSDJRUVE57k9O11yfO3fOFC5c2MyaNctqS0tLMxUqVDATJkywW27x4sXZ1vmvf/3LdOnSxfrcuXNn668ixhgzevRoU7VqVZOWlpZjTTldc331cd68ebOx2Wzmzz//NMYY6685WX/Nysn8+fNNqVKlrM/Xuub6yu/ohx9+MK6urubQoUPW/B07dhhJ1l+yxo4da4oVK2b3l5rhw4eboKCga9aS5ciRI0aSWb9+vV378OHDTZMmTW64fEHBmPofxpR3tn53ckxdzRnCHeOKcVXQxlVGRobp0KGDadasWZ6XdSTG1P8wpryz9XPEmNq6daspXry4cXV1Nd7e3mbJkiW5XjYL99xdoUyZMurQoYMiIyM1c+ZMdejQQaVLl7brs3fvXnXv3l3VqlWTl5eXqlSpIkk6dOjQDdcfEBAgNze36/Zxc3PTrFmztHDhQl28eFETJ060m1+rVi3dd999+vzzzyVJ+/bt09q1a9WvXz9J0pYtWxQZGSkPDw9rCg0NVWZmpg4cOKC4uDi5urqqZcuWuT0s2r9/v9LT09WsWTOrrXDhwmrSpIl27dpl17dRo0Z2nzMyMvTFF1/o6aefttqefvppRUZGKjMzU5IUFxen5s2bq3Dhwrmu6WqBgYGqXbu2Zs+eLenyvQDHjx/X448/bvX58ccf1bp1a1WsWFGenp7q2bOnTp06pfPnz+d6O7t27ZKfn5/8/PysNn9/f/n4+NgdiypVqsjT09P6XL58+b/dPXP5gTGVM8bU/zCm8o5xlTPG1f/c6XEVHh6u7du3a86cOXletiBgTOWMMfU/d2pM1axZU3Fxcfrll180aNAghYWFaefOnbleXuJVCNn07dtXkZGR+uKLL9S3b99s8zt16qTTp0/r008/1S+//KJffvlF0v9ukL2e4sWL56qG9evXS5JOnz6t06dPZ5vfr18/LVy4UGfPntXMmTNVvXp1a7CeO3dOzz77rOLi4qxpy5Yt2rt3r6pXr66iRYvmqoabdfU+rlixQkeOHNGTTz6pQoUKqVChQurWrZv+/PNPRUdHS1K+1dSjRw9rcM+ePVtt27ZVqVKlJF1+dG7Hjh1Vr149LVy4UBs3brQerpCb7y6vrv6HymazWf+YXU/p0qXl6uqqhIQEu/aEhAT5+vrma413CmPq1jCmLrvZMeWsGFe3hnF1WX6Mq8GDB+v777/XqlWrVKlSpfws745iTN0axtRltzqm3NzcVKNGDTVs2FDjx49X/fr19eGHH+apBsLdVdq2bau0tDSlp6crNDTUbt6pU6e0Z88evfLKK2rdurVq166tM2fO2PXJ+stMRkbGTW1///79GjZsmD799FMFBQUpLCws24/iiSeekIuLi2bPnq0vv/xSffv2lc1mkyQ1aNBAO3fuVI0aNbJNbm5uCggIUGZmpmJiYnLcfk71V69eXW5ubvrpp5+stvT0dG3YsEH+/v7X3Z///Oc/6tatm90/NnFxcerWrZv+85//SJLq1auntWvXKj09/Zo15eZ4PvXUU9q+fbs2btyoBQsWqEePHta8jRs3KjMzU++//76aNm2qe+65R0ePHs3zdmrXrq3Dhw/r8OHDVtvOnTuVmJh4w2ORG25ubmrYsKH1D58kZWZmKjo6WsHBwbe8fkdgTDGmrud2jylnxbhiXF3PnRhXxhgNHjxYixYt0sqVK1W1atV8Wa+jMKYYU9fjqP9flZmZqdTU1LwtlOcLOZ3Q1df0JiUlmaSkJOtz1jXXGRkZplSpUubpp582e/fuNdHR0aZx48Z293Ckp6ebokWLmjfffNPEx8dbN6TmdN2wMfbX8166dMk0bdrUdO3a1RhjzNGjR02pUqWs65qv1K9fP1OiRAnj6upqjhw5YrVv2bLFFC1a1ISHh5vNmzeb33//3SxevNju6Yu9e/c2fn5+ZtGiReaPP/4wq1atMnPnzjXGXL651WazmcjISHP8+HHrptIXXnjBVKhQwSxbtszuhtrTp08bY3K+Vvv48eOmcOHCZtmyZdnqX7p0qXF3dzenTp0yJ0+eNKVKlbJuqP3999/Nl19+ab0v56233jJ33XWX2b17tzlx4oRJS0u75rXtzZo1M/Xr1zeenp7m/PnzVntcXJyRZCZNmmT2799vvvzyS1OxYkW7mn/66SfrZugTJ05Y7za58jvKzMw0gYGBpnnz5mbjxo3ml19+yfGG2vr169vVNXHiRFO5cuVsxyEnc+bMMe7u7iYyMtLs3LnTPPPMM8bHx8fuiUwFHWOKMWVMwRlTZ8+eNZs3bzabN282kswHH3xgNm/ebN2j8XfBuGJcGVNwxtWgQYOMt7e3Wb16tfUgimPHjtntT0HHmGJMGVNwxtSoUaNMTEyMOXDggNm6dasZNWqUsdls5ocffsjV8lkId+baAy/LlTfURkVFmdq1axt3d3dTr149s3r16mw36H/66afGz8/PuLi4ZHsU7tWu/OG89tprpnz58ubkyZPW/IULFxo3NzcTFxdnt9z69euNJNO+ffts6/z111/NQw89ZDw8PEzx4sVNvXr1zFtvvWXNv3Dhghk2bJgpX768cXNzMzVq1DCff/65Nf/11183vr6+xmazWft94cIFM2TIEFO6dOnrPgr3ysH973//2/j4+OR4o2xqaqrx8fExH374oTHm8j9Kbdq0McWKFTOenp6mefPmZv/+/caYy/9IZO2PcngU7pWmTZtmJJlevXpl2+YHH3xgypcvb4oWLWpCQ0PNl19+ma3mgQMHmlKlSuXLo3CvlJfBbYwxH330kbnrrruMm5ubadKkifn5559zvWxBwJhiTGUpCGMqp0ddS7l/OXFBwbhiXGUpCOMqpzElycycOTNXyxcEjCnGVJaCMKb69u1rKleubNzc3EyZMmVM69at8xzsjDHGZowxeTvXBwAAAAAoaLjnDgAAAACcAOEOuIMOHTpk95jiq6fcPFIZwP8wpoD8x7gC8tedHFNclgncQZcuXdLBgwevOb9KlSoqVKjQnSsI+JtjTAH5j3EF5K87OaYIdwAAAADgBLgsEwAAAACcAOEOAAAAAJwA4Q4AAAAAnADhDgAAAACcAOEOAIBb1KpVKw0dOtTRZQAA/uEIdwAAh+ndu7dsNpveeecdu/bFixfLZrPlaV1VqlTRpEmT8rG62+fgwYOy2WyKi4tzdCkAACdCuAMAOFSRIkX07rvv6syZM44uJc/S0tIcXUK+Sk9Pd3QJAIBbQLgDADhUSEiIfH19NX78+Ov2W7dunZo3b66iRYvKz89Pzz//vFJSUiRdvizyzz//1LBhw2Sz2WSz2WSMUZkyZbRgwQJrHYGBgSpfvrzdOt3d3XX+/HlJ0qFDh9S5c2d5eHjIy8tLTzzxhBISEqz+48aNU2BgoD777DNVrVpVRYoUybHWJUuWyNvbW7NmzbqpY7J//3517txZ5cqVk4eHhxo3bqwff/zRmv/666+rbt262ZYLDAzUq6++an3+7LPPVLt2bRUpUkS1atXStGnTrHlZZw/nzp2rli1bqkiRIpo1a5b+/PNPderUSSVKlFDx4sVVp04dLV269Kb2AwBwZxHuAAAO5erqqrffflsfffSR/vrrrxz77N+/X23btlXXrl21detWzZ07V+vWrdPgwYMlSV9//bUqVaqk119/XceOHdOxY8dks9nUokULrV69WpJ05swZ7dq1SxcuXNDu3bslSTExMWrcuLGKFSumzMxMde7cWadPn1ZMTIyioqL0xx9/6Mknn7SrZd++fVq4cKG+/vrrHC+rnD17trp3765Zs2apR48eN3VMzp07p/bt2ys6OlqbN29W27Zt1alTJx06dEiS1LdvX+3atUsbNmywltm8ebO2bt2qPn36SJJmzZqlMWPG6K233tKuXbv09ttv69VXX9UXX3xht61Ro0bphRde0K5duxQaGqrw8HClpqZqzZo12rZtm9599115eHjc1H4AAO6sQo4uAACARx55RIGBgRo7dqz+85//ZJs/fvx49ejRw3poyd13363JkyerZcuWmj59ukqWLClXV1d5enrK19fXWq5Vq1b6+OOPJUlr1qzRvffeK19fX61evVq1atXS6tWr1bJlS0lSdHS0tm3bpgMHDsjPz0+S9OWXX6pOnTrasGGDGjduLOnypZhffvmlypQpk63OqVOn6uWXX9Z3331nrfdm1K9fX/Xr17c+v/HGG1q0aJG+/fZbDR48WJUqVVJoaKhmzpxp1TVz5ky1bNlS1apVkySNHTtW77//vh599FFJUtWqVbVz5059/PHHCgsLs9Y9dOhQq490+exl165dFRAQIEnW+gAABR9n7gAABcK7776rL774Qrt27co2b8uWLYqMjJSHh4c1hYaGKjMzUwcOHLjmOlu2bKmdO3fqxIkTiomJUatWrdSqVSutXr1a6enpWr9+vVq1aiVJ2rVrl/z8/KxgJ0n+/v7y8fGxq6ly5co5BrsFCxZo2LBhioqKuqVgJ10+c/fSSy+pdu3a8vHxkYeHh3bt2mWduZOkAQMG6KuvvtLFixeVlpam2bNnq2/fvpKklJQU7d+/X/369bM7Zm+++ab2799vt61GjRrZfX7++ef15ptvqlmzZho7dqy2bt16S/sCALhzCHcAgAKhRYsWCg0N1ejRo7PNO3funJ599lnFxcVZ05YtW7R3715Vr179musMCAhQyZIlFRMTYxfuYmJitGHDBqWnp+u+++7LU53FixfPsf3ee+9VmTJl9Pnnn8sYk6d1Xu2ll17SokWL9Pbbb2vt2rWKi4tTQECA3QNcOnXqJHd3dy1atEjfffed0tPT9dhjj0m6fLwk6dNPP7U7Ztu3b9fPP/983f3p37+//vjjD/Xs2VPbtm1To0aN9NFHH93S/gAA7gwuywQAFBjvvPOOAgMDVbNmTbv2Bg0aaOfOnapRo8Y1l3Vzc1NGRoZdm81mU/PmzfXNN99ox44duv/++1WsWDGlpqbq448/VqNGjaxwU7t2bR0+fFiHDx+2zt7t3LlTiYmJ8vf3v2Ht1atX1/vvv69WrVrJ1dVVU6ZMyevuW3766Sf17t1bjzzyiKTLYe3gwYN2fQoVKqSwsDDNnDlTbm5u6tatm4oWLSpJKleunCpUqKA//vjjpu778/Pz08CBAzVw4ECNHj1an376qYYMGXLT+wMAuDMIdwCAAiMgIEA9evTQ5MmT7dpHjhyppk2bavDgwerfv7+KFy+unTt3KioqygpRVapU0Zo1a9StWze5u7urdOnSki7fd/fiiy+qUaNG1oNBWrRooVmzZmn48OHWNkJCQqztT5o0SZcuXdJzzz2nli1bZrt08VruuecerVq1Sq1atVKhQoVu+N69PXv2ZGurU6eO7r77bn399dfq1KmTbDabXn31VWVmZmbr279/f9WuXVvS5UB4pddee03PP/+8vL291bZtW6Wmpuq3337TmTNnFBERcc2ahg4dqnbt2umee+7RmTNntGrVKmsbAICCjcsyAQAFyuuvv54tyNSrV08xMTH6/fff1bx5c917770aM2aMKlSoYLfcwYMHVb16dbt74lq2bKmMjAzr3jrpcuC7us1ms+mbb75RiRIl1KJFC4WEhKhatWqaO3dunuqvWbOmVq5cqa+++kovvvjidft269ZN9957r92UkJCgDz74QCVKlNB9992nTp06KTQ0VA0aNMi2/N1336377rtPtWrVUlBQkN28/v3767PPPtPMmTMVEBCgli1bKjIyUlWrVr1uTRkZGQoPD1ft2rXVtm1b3XPPPXavUAAAFFw2c6s3BgAAAIcwxujuu+/Wc889d92zcQCAfwYuywQA4G/oxIkTmjNnjuLj46132wEA/tkIdwAA/A2VLVtWpUuX1ieffKISJUo4uhwAQAFAuAMA4G+IuyoAAFfjgSoAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBP4/da6Cud3tvjMAAAAASUVORK5CYII=", + "text/plain": [ + "
" + ] + }, + "metadata": {}, + "output_type": "display_data" + } + ], + "source": [ + "import matplotlib.pyplot as plt\n", + "\n", + "layers = list(cycles_dict.keys())\n", + "cycles = list(cycles_dict.values())\n", + "fig = plt.figure(figsize = (10, 5))\n", + "plt.bar(layers, cycles, color ='blue', width = 0.3)\n", + "plt.xlabel(\"Network Layers\")\n", + "plt.ylabel(\"Clock Cycles\")\n", + "plt.title(\"Estimated clock cycles for each network layer\")\n", + "plt.show()" + ] + }, + { + "cell_type": "code", + "execution_count": 8, + "metadata": {}, + "outputs": [], + "source": [ + "res_dict = []\n", + "res_dict = res_estimation(model)" + ] + }, + { + "cell_type": "code", + "execution_count": 9, + "metadata": {}, + "outputs": [ + { + "data": { + "image/png": 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etHz5cg0cOFArV67U+fPnncYnJCRY67qW3bt3a/PmzcqfP3+G/Wk3YDhw4IAKFCggLy8vp/6HH374BnuXvbLrFvj58uVT3bp1NWXKFA0dOlTS5dMYXV1d1aJFC2tc2jVCo0aN0r59+5SSkmL1ZeYUs8zYvXu3EhISFBAQkGF/2nsQGRmpli1bavDgwRo2bJjq1KmjJ598Us8++6zc3d2zpZYhQ4aoefPmKl26tMqXL6+GDRuqXbt2CgsLkyTt2bNHxhi99dZbeuutt65Zb6FChXTgwAFVrVo1Xf+tfGYOHDhwzXWUKVNGv/76q1Obq6urChcufMP1Hj9+XKdPn9aYMWM0ZsyYDMekvQ+SNGHCBH388cfasWOHU0i+8q6ue/fuVcGCBeXv73/D7V/9O0CS8uTJk+4aw8wunydPHkmylk8L2tc79TghIcFaLiMuLi6KiIjQsmXLJF0OZrVq1VLNmjWVkpKiVatWKTAwUCdPnnQKZtf6HKSd4n3gwAGVL1/eas/ozrhp2rVrJ1dXV23fvl1BQUHXHHcjBw8e1IABA/Tjjz+me42v/INW/fr1VaBAAU2cOFF169ZVamqqvvvuOzVv3lze3t6Sbu61vd4+AsgaghnwgAoICNCmTZs0b948zZ07V3PnztW4cePUvn17TZgw4abX6+LikqV28/+vSdi7d6/q1q2rMmXK6JNPPlFwcLDc3Nw0Z84cDRs2LFM3WUhNTVX9+vX16quvZthfunTpTO7FrXN3d3e6+P5KaaHzyqMkt6p169bq2LGjNm3apPDwcE2ZMkV169a1rquRLl/k/9Zbb6lTp04aOnSo/P39lSNHDvXs2fOGr6/D4cjw+pErw510+T0ICAjQxIkTM1xPWmhO+x64VatW6aefftK8efPUqVMnffzxx1q1alW60JwZV9dSu3Zt7d27Vz/88IN++eUXffXVVxo2bJg+//xzdenSxdrnPn36KCoqKsN1ZuXrJW63K494Xk/afj333HPX/Ad2Wjj99ttv1aFDBz355JPq27evAgIC5OLiotjYWO3du/em6rzRXL/V5dP278MPP3S6Bu5Kmfn81KxZU++8844uXLigZcuW6Y033pCfn5/Kly+vZcuWWdeuXhnMsup61yC2aNFC33zzjUaMGKHY2NibWn9KSop1fdprr72mMmXKyNPTU3/99Zc6dOjgNK9dXFz07LPP6ssvv9SoUaO0fPlyHT582Onurzfz2mbmOksAmUMwAx5gbm5uatasmZo1a6bU1FS9+OKL+uKLL/TWW2+pVKlSd/RLjX/66SclJSXpxx9/dPqLeUZ3h7tWXSVLltTZs2dv+D1RRYsW1cKFC3X27Fmnf2Rk9W5oN9rGtdaX1n6zpy5l5Mknn1S3bt2s0xl37dql/v37O42ZNm2aHnvsMY0dO9ap/fTp004BLiN58uTJ8FS0tKM+aUqWLKkFCxaoRo0amfoHW7Vq1VStWjW98847mjRpktq2bavJkyerS5cu163l6jtoXrx4UUeOHEk31t/fXx07dlTHjh119uxZ1a5dW4MGDVKXLl1UokQJSVLOnDkz9ZnJ6JTIW/nMpL3/O3fu1OOPP55uvTf7+cifP7+8vb2VkpJyw/2aNm2aSpQooRkzZjjNq6tPWSxZsqTmzZunkydPZuqo2e2Udpqkj4/PDffver/DatWqpYsXL+q7777TX3/9ZQWw2rVrW8GsdOnSVkCTrj2vd+zYYfVn1ksvvaRSpUppwIAB8vX1Vb9+/TK9bJotW7Zo165dmjBhgtq3b2+1X+sU9fbt2+vjjz/WTz/9pLlz5yp//vxOf5TIymsLIPtxjRnwgDpx4oTT8xw5clh/RU+7jX3a99HcidvIp/2V/Mq/qickJGjcuHHpxnp6emZYU6tWrbRy5UrNmzcvXd/p06et69kaN26s5ORkp1vxp6Sk6LPPPrvV3bA0btxYq1at0vr169PVMXHiRIWHh9/S6UtX8/PzU1RUlKZMmaLJkyfLzc1NTz75pNMYFxeXdEctpk6dmu7W7BkpWbKkduzYoePHj1ttv/32W7pbaLdq1UopKSnWKZVXSk5Ott63U6dOpasl7S/0V3+NQka1pF0blGbMmDHpjphd/Rn38vJSqVKlrPUHBASoTp06+uKLLzIMdVfua9r7uWbNGqf+ax0ZzIzKlSsrICBAn3/+udM+z507V9u3b1eTJk1uar0uLi5q2bKlpk+frt9//z1d/5X7ldG8W716tVauXOm0TMuWLWWMyfBrGTJ7JCy7VKpUSSVLltRHH32ks2fPpuu/cv+u9zusatWqypkzp95//335+/urXLlyki4HtlWrVikuLi7d0bLGjRtrzZo1Tq/PuXPnNGbMGBUrVkwhISFZ2pe33npLffr0Uf/+/dN9NUhmZPT+GWOsrz25WlhYmMLCwvTVV19p+vTpat26tVxd//c3+qy8tgCyH0fMgPvU3Llzrb/iXql69eoqUaKEunTpopMnT+rxxx9X4cKFdeDAAX322WcKDw+3rpcIDw+Xi4uL3n//fSUkJMjd3d36nrHs1qBBA+sIXrdu3XT27Fl9+eWXCggISPeP5kqVKmn06NF6++23VapUKQUEBOjxxx9X37599eOPP6pp06bq0KGDKlWqpHPnzmnLli2aNm2a9u/fr3z58qlZs2aqUaOG+vXrp/379yskJEQzZszI1A1GrjR9+vQMX+Po6Gj169dPU6dOVe3atdWtWzeVKVNGhw8f1vjx43XkyJEMA+eteuaZZ/Tcc89p1KhRioqKSvdlxk2bNtWQIUPUsWNHVa9eXVu2bNHEiROtI0fX06lTJ33yySeKiopS586ddezYMX3++ecqV66c03czRUZGqlu3boqNjdWmTZvUoEED5cyZU7t379bUqVM1YsQIPfXUU5owYYJGjRqlf/3rXypZsqTOnDmjL7/8Uj4+PmrcuPF1a+nSpYteeOEFtWzZUvXr19dvv/2mefPmpTvqFxISojp16qhSpUry9/fXunXrNG3aNPXo0cMaM3LkSNWsWVOhoaHq2rWrSpQooaNHj2rlypX6888/re94e/XVV/Wf//xHDRs21CuvvGLdLr9o0aLavHnzDV+/jKSFgo4dOyoyMlJt2rSxbpdfrFgx9erV66bWK12+5fzixYtVtWpVde3aVSEhITp58qQ2bNigBQsW6OTJk5IufyZmzJihf/3rX2rSpIn27dunzz//XCEhIU7/MH/sscfUrl07ffrpp9q9e7caNmyo1NRULVu2TI899pjTa3q75ciRQ1999ZUaNWqkcuXKqWPHjipUqJD++usvLV68WD4+Pvrpp58kXf5dIV3+yoLWrVsrZ86catasmTw9PZU7d25VqlRJq1atsr7DTLp8xOzcuXM6d+5cumDWr18/fffdd2rUqJFefvll+fv7a8KECdq3b5+mT5+eqVNNr/bhhx8qISFBMTEx8vb2ztIXy5cpU0YlS5ZUnz599Ndff8nHx0fTp0+/7vV87du3V58+fSQp3bay8toCuA3u9G0gAdxe17tdvq64LfK0adNMgwYNTEBAgHFzczNFihQx3bp1M0eOHHFa35dffmlKlChhXFxcnG7TfK3b5V99C/mMbhNuzP9utXz8+HGr7ccffzRhYWHGw8PDFCtWzLz//vvm66+/Tne76/j4eNOkSRPj7e1tJDnVcebMGdO/f39TqlQp4+bmZvLly2eqV69uPvroI6fb+J84ccK0a9fO+Pj4GF9fX9OuXTuzcePGLN0u/1qPtFtp//nnn6ZLly6mUKFCxtXV1fj7+5umTZuaVatWXXf9Wb1dfprExESTK1cuI8l8++236fovXLhg/u///s8UKFDA5MqVy9SoUcOsXLky3XuZ0e3yjTHm22+/NSVKlDBubm4mPDzczJs3L93t8tOMGTPGVKpUyeTKlct4e3ub0NBQ8+qrr5rDhw8bYy7fprtNmzamSJEixt3d3QQEBJimTZuadevW3XA/U1JSzGuvvWby5ctncufObaKiosyePXvS3S7/7bffNlWqVDF+fn4mV65cpkyZMuadd95x+hwYY8zevXtN+/btTVBQkMmZM6cpVKiQadq0qZk2bZrTuM2bN5vIyEjj4eFhChUqZIYOHWrGjh1707fLT/P999+bihUrGnd3d+Pv72/atm1r/vzzT6cx0dHRxtPT84avzZWOHj1qYmJiTHBwsMmZM6cJCgoydevWNWPGjLHGpKammnfffdcULVrUuLu7m4oVK5rZs2dn+L4mJyebDz/80JQpU8a4ubmZ/Pnzm0aNGpn169dbY3SNr4m4+r3JyLV+h1zr87hx40bTokULkzdvXuPu7m6KFi1qWrVqZRYuXOg0bujQoaZQoUImR44c6d6rvn37Gknm/fffd1qmVKlSRpLZu3dvujr37t1rnnrqKePn52c8PDxMlSpVzOzZszO1L8Zk/FlISUkxbdq0Ma6urmbWrFk3fI2uvF3+tm3bTL169YyXl5fJly+f6dq1q/UVBRn9Ljty5IhxcXExpUuXvuZ2MvPaZvQ7HMCtcRjDtwECAAA8CP7++28VKFBAAwYMuObdSAHYg2vMAAAAHhDjx49XSkqK2rVrZ3cpAK7CNWYAAAD3uUWLFmnbtm1655139OSTT6pYsWJ2lwTgKpzKCAAAcJ+rU6eOVqxYoRo1aujbb79VoUKF7C4JwFUIZgAAAABgM64xAwAAAACbEcwAAAAAwGbc/ENSamqqDh8+LG9vb+sLJgEAAAA8eIwxOnPmjAoWLHhTXxx/swhmkg4fPqzg4GC7ywAAAABwlzh06JAKFy58x7ZHMJPk7e0t6fKL7+PjY3M1AAAAAOySmJio4OBgKyPcKQQzyTp90cfHh2AGAAAA4I5f4sTNPwAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbOZqdwFIzzHYYXcJtjIDjd0lAAAAAHcUR8wAAAAAwGZ3TTB777335HA41LNnT6vtwoULiomJUd68eeXl5aWWLVvq6NGjTssdPHhQTZo0Ue7cuRUQEKC+ffsqOTn5DlcPAAAAADfvrghma9eu1RdffKGwsDCn9l69eumnn37S1KlTFRcXp8OHD6tFixZWf0pKipo0aaKLFy9qxYoVmjBhgsaPH68BAwbc6V0AAAAAgJtmezA7e/as2rZtqy+//FJ58uSx2hMSEjR27Fh98sknevzxx1WpUiWNGzdOK1as0KpVqyRJv/zyi7Zt26Zvv/1W4eHhatSokYYOHaqRI0fq4sWL19xmUlKSEhMTnR4AAAAAYBfbg1lMTIyaNGmievXqObWvX79ely5dcmovU6aMihQpopUrV0qSVq5cqdDQUAUGBlpjoqKilJiYqK1bt15zm7GxsfL19bUewcHB2bxXAAAAAJB5tgazyZMna8OGDYqNjU3XFx8fLzc3N/n5+Tm1BwYGKj4+3hpzZShL60/ru5b+/fsrISHBehw6dOgW9wQAAAAAbp5tt8s/dOiQXnnlFc2fP18eHh53dNvu7u5yd3e/o9sEAAAAgGux7YjZ+vXrdezYMT3yyCNydXWVq6ur4uLi9Omnn8rV1VWBgYG6ePGiTp8+7bTc0aNHFRQUJEkKCgpKd5fGtOdpYwAAAADgbmdbMKtbt662bNmiTZs2WY/KlSurbdu21s85c+bUwoULrWV27typgwcPKiIiQpIUERGhLVu26NixY9aY+fPny8fHRyEhIXd8nwAAAADgZth2KqO3t7fKly/v1Obp6am8efNa7Z07d1bv3r3l7+8vHx8fvfTSS4qIiFC1atUkSQ0aNFBISIjatWunDz74QPHx8XrzzTcVExPDqYoAAAAA7hm2BbPMGDZsmHLkyKGWLVsqKSlJUVFRGjVqlNXv4uKi2bNnq3v37oqIiJCnp6eio6M1ZMgQG6sGAAAAgKxxGGOM3UXYLTExUb6+vkpISJCPj4/d5cgx2GF3CbYyAx/4jyQAAABsYlc2sP17zAAAAADgQUcwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAm93V32MGANmBr6DgKyiQ/ZhXzCsA2YsjZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANrM1mI0ePVphYWHy8fGRj4+PIiIiNHfuXKu/Tp06cjgcTo8XXnjBaR0HDx5UkyZNlDt3bgUEBKhv375KTk6+07sCAAAAADfN1c6NFy5cWO+9954eeughGWM0YcIENW/eXBs3blS5cuUkSV27dtWQIUOsZXLnzm39nJKSoiZNmigoKEgrVqzQkSNH1L59e+XMmVPvvvvuHd8fAAAAALgZtgazZs2aOT1/5513NHr0aK1atcoKZrlz51ZQUFCGy//yyy/atm2bFixYoMDAQIWHh2vo0KF67bXXNGjQILm5uWW4XFJSkpKSkqzniYmJ2bRHAAAAAJB1d801ZikpKZo8ebLOnTuniIgIq33ixInKly+fypcvr/79++v8+fNW38qVKxUaGqrAwECrLSoqSomJidq6des1txUbGytfX1/rERwcfHt2CgAAAAAywdYjZpK0ZcsWRURE6MKFC/Ly8tLMmTMVEhIiSXr22WdVtGhRFSxYUJs3b9Zrr72mnTt3asaMGZKk+Ph4p1AmyXoeHx9/zW32799fvXv3tp4nJiYSzgAAAADYxvZg9vDDD2vTpk1KSEjQtGnTFB0drbi4OIWEhOj555+3xoWGhqpAgQKqW7eu9u7dq5IlS970Nt3d3eXu7p4d5QMAAADALbP9VEY3NzeVKlVKlSpVUmxsrCpUqKARI0ZkOLZq1aqSpD179kiSgoKCdPToUacxac+vdV0aAAAAANxtbA9mV0tNTXW6MceVNm3aJEkqUKCAJCkiIkJbtmzRsWPHrDHz58+Xj4+PdTokAAAAANztbD2VsX///mrUqJGKFCmiM2fOaNKkSVqyZInmzZunvXv3atKkSWrcuLHy5s2rzZs3q1evXqpdu7bCwsIkSQ0aNFBISIjatWunDz74QPHx8XrzzTcVExPDqYoAAAAA7hm2BrNjx46pffv2OnLkiHx9fRUWFqZ58+apfv36OnTokBYsWKDhw4fr3LlzCg4OVsuWLfXmm29ay7u4uGj27Nnq3r27IiIi5OnpqejoaKfvPQMAAACAu52twWzs2LHX7AsODlZcXNwN11G0aFHNmTMnO8sCAAAA7ijHYIfdJdjKDDR2l2C7u+4aMwAAAAB40BDMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGa2BrPRo0crLCxMPj4+8vHxUUREhObOnWv1X7hwQTExMcqbN6+8vLzUsmVLHT161GkdBw8eVJMmTZQ7d24FBASob9++Sk5OvtO7AgAAAAA3zdZgVrhwYb333ntav3691q1bp8cff1zNmzfX1q1bJUm9evXSTz/9pKlTpyouLk6HDx9WixYtrOVTUlLUpEkTXbx4UStWrNCECRM0fvx4DRgwwK5dAgAAAIAscxhjjN1FXMnf318ffvihnnrqKeXPn1+TJk3SU089JUnasWOHypYtq5UrV6patWqaO3eumjZtqsOHDyswMFCS9Pnnn+u1117T8ePH5ebmlqltJiYmytfXVwkJCfLx8blt+5ZZjsEOu0uwlRl4V30kcR9gTjGnkP2YV8wrZC/m1N0zp+zKBnfNNWYpKSmaPHmyzp07p4iICK1fv16XLl1SvXr1rDFlypRRkSJFtHLlSknSypUrFRoaaoUySYqKilJiYqJ11C0jSUlJSkxMdHoAAAAAgF1sD2ZbtmyRl5eX3N3d9cILL2jmzJkKCQlRfHy83Nzc5Ofn5zQ+MDBQ8fHxkqT4+HinUJbWn9Z3LbGxsfL19bUewcHB2btTAAAAAJAFtgezhx9+WJs2bdLq1avVvXt3RUdHa9u2bbd1m/3791dCQoL1OHTo0G3dHgAAAABcj6vdBbi5ualUqVKSpEqVKmnt2rUaMWKEnnnmGV28eFGnT592Omp29OhRBQUFSZKCgoK0Zs0ap/Wl3bUxbUxG3N3d5e7uns17AgAAAAA3x/YjZldLTU1VUlKSKlWqpJw5c2rhwoVW386dO3Xw4EFFRERIkiIiIrRlyxYdO3bMGjN//nz5+PgoJCTkjtcOAAAAADfD1iNm/fv3V6NGjVSkSBGdOXNGkyZN0pIlSzRv3jz5+vqqc+fO6t27t/z9/eXj46OXXnpJERERqlatmiSpQYMGCgkJUbt27fTBBx8oPj5eb775pmJiYjgiBgAAAOCeYWswO3bsmNq3b68jR47I19dXYWFhmjdvnurXry9JGjZsmHLkyKGWLVsqKSlJUVFRGjVqlLW8i4uLZs+ere7duysiIkKenp6Kjo7WkCFD7NolAAAAAMgyW4PZ2LFjr9vv4eGhkSNHauTIkdccU7RoUc2ZMye7SwMAAACAO+auu8YMAAAAAB40BDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAm7nezEK7d+/W4sWLdezYMaWmpjr1DRgwIFsKAwAAAIAHRZaD2Zdffqnu3bsrX758CgoKksPhsPocDgfBDAAAAACyKMvB7O2339Y777yj11577XbUAwAAAAAPnCxfY3bq1Ck9/fTTt6MWAAAAAHggZTmYPf300/rll19uRy0AAAAA8EDK8qmMpUqV0ltvvaVVq1YpNDRUOXPmdOp/+eWXs604AAAAAHgQZDmYjRkzRl5eXoqLi1NcXJxTn8PhIJgBAAAAQBZlOZjt27fvdtQBAAAAAA+sW/qCaWOMjDHZVQsAAAAAPJBuKph98803Cg0NVa5cuZQrVy6FhYXpP//5T3bXBgAAAAAPhCwHs08++UTdu3dX48aNNWXKFE2ZMkUNGzbUCy+8oGHDhmVpXbGxsXr00Ufl7e2tgIAAPfnkk9q5c6fTmDp16sjhcDg9XnjhBacxBw8eVJMmTZQ7d24FBASob9++Sk5OzuquAQAAAIAtsnyN2WeffabRo0erffv2VtsTTzyhcuXKadCgQerVq1em1xUXF6eYmBg9+uijSk5O1uuvv64GDRpo27Zt8vT0tMZ17dpVQ4YMsZ7nzp3b+jklJUVNmjRRUFCQVqxYoSNHjqh9+/bKmTOn3n333azuHgAAAADccVkOZkeOHFH16tXTtVevXl1HjhzJ0rp+/vlnp+fjx49XQECA1q9fr9q1a1vtuXPnVlBQUIbr+OWXX7Rt2zYtWLBAgYGBCg8P19ChQ/Xaa69p0KBBcnNzy1JNAAAAAHCnZflUxlKlSmnKlCnp2r///ns99NBDt1RMQkKCJMnf39+pfeLEicqXL5/Kly+v/v376/z581bfypUrFRoaqsDAQKstKipKiYmJ2rp1a4bbSUpKUmJiotMDAAAAAOyS5SNmgwcP1jPPPKOlS5eqRo0akqTly5dr4cKFGQa2zEpNTVXPnj1Vo0YNlS9f3mp/9tlnVbRoURUsWFCbN2/Wa6+9pp07d2rGjBmSpPj4eKdQJsl6Hh8fn+G2YmNjNXjw4JuuFQAAAACyU5aDWcuWLbV69WoNGzZMs2bNkiSVLVtWa9asUcWKFW+6kJiYGP3+++/69ddfndqff/556+fQ0FAVKFBAdevW1d69e1WyZMmb2lb//v3Vu3dv63liYqKCg4NvrnAAAAAAuEVZDmaSVKlSJX377bfZVkSPHj00e/ZsLV26VIULF77u2KpVq0qS9uzZo5IlSyooKEhr1qxxGnP06FFJuuZ1ae7u7nJ3d8+GygEAAADg1mXqGrMrr8G6+tqsW7lWyxijHj16aObMmVq0aJGKFy9+w2U2bdokSSpQoIAkKSIiQlu2bNGxY8esMfPnz5ePj49CQkKyVA8AAAAA2CFTR8zy5MmjI0eOKCAgQH5+fnI4HOnGGGPkcDiUkpKS6Y3HxMRo0qRJ+uGHH+Tt7W1dE+br66tcuXJp7969mjRpkho3bqy8efNq8+bN6tWrl2rXrq2wsDBJUoMGDRQSEqJ27drpgw8+UHx8vN58803FxMRwVAwAAADAPSFTwWzRokXWnRIXL16cbRsfPXq0pMtfIn2lcePGqUOHDnJzc9OCBQs0fPhwnTt3TsHBwWrZsqXefPNNa6yLi4tmz56t7t27KyIiQp6enoqOjnb63jMAAAAAuJtlKphFRkZaPxcvXlzBwcHpjpoZY3To0KEsbdwYc93+4OBgxcXF3XA9RYsW1Zw5c7K0bQAAAAC4W2T5e8yKFy+u48ePp2s/efJkpq4RAwAAAAA4y3IwS7uW7Gpnz56Vh4dHthQFAAAAAA+STN8uP+17vxwOh9566y3lzp3b6ktJSdHq1asVHh6e7QUCAAAAwP0u08Fs48aNki4fMduyZYvc3NysPjc3N1WoUEF9+vTJ/goBAAAA4D6X6WCWdjfGjh07asSIEfLx8bltRQEAAADAgyTTwSzNuHHjbkcdAAAAAPDAynIwk6R169ZpypQpOnjwoC5evOjUN2PGjGwpDAAAAAAeFFm+K+PkyZNVvXp1bd++XTNnztSlS5e0detWLVq0SL6+vrejRgAAAAC4r2U5mL377rsaNmyYfvrpJ7m5uWnEiBHasWOHWrVqpSJFityOGgEAAADgvpblYLZ37141adJE0uW7MZ47d04Oh0O9evXSmDFjsr1AAAAAALjfZTmY5cmTR2fOnJEkFSpUSL///rsk6fTp0zp//nz2VgcAAAAAD4As3/yjdu3amj9/vkJDQ/X000/rlVde0aJFizR//nzVrVv3dtQIAAAAAPe1LAezf//737pw4YIk6Y033lDOnDm1YsUKtWzZUm+++Wa2FwgAAAAA97ssBzN/f3/r5xw5cqhfv37ZWhAAAAAAPGiyfI3Zhg0btGXLFuv5Dz/8oCeffFKvv/56uu80AwAAAADcWJaDWbdu3bRr1y5J0h9//KFnnnlGuXPn1tSpU/Xqq69me4EAAAAAcL/LcjDbtWuXwsPDJUlTp05VZGSkJk2apPHjx2v69OnZXR8AAAAA3PeyHMyMMUpNTZUkLViwQI0bN5YkBQcH6++//87e6gAAAADgAZDlYFa5cmW9/fbb+s9//qO4uDjry6b37dunwMDAbC8QAAAAAO53WQ5mw4cP14YNG9SjRw+98cYbKlWqlCRp2rRpql69erYXCAAAAAD3uyzfLj8sLMzproxpPvzwQ7m4uGRLUQAAAADwIMlyMLsWDw+P7FoVAAAAADxQMhXM/P39tWvXLuXLl0958uSRw+G45tiTJ09mW3EAAAAA8CDIVDAbNmyYvL29JV2+xgwAAAAAkH0yFcyio6Mz/BkAAAAAcOsyFcwSExMzvUIfH5+bLgYAAAAAHkSZCmZ+fn7Xva5MuvzF0w6HQykpKdlSGAAAAAA8KDIVzBYvXny76wAAAACAB1amgllkZOTtrgMAAAAAHliZCmabN29W+fLllSNHDm3evPm6Y8PCwrKlMAAAAAB4UGQqmIWHhys+Pl4BAQEKDw+Xw+GQMSbdOK4xAwAAAICsy1Qw27dvn/Lnz2/9DAAAAADIPpkKZkWLFrV+PnDggKpXry5XV+dFk5OTtWLFCqexAAAAAIAby5HVBR577DGdPHkyXXtCQoIee+yxbCkKAAAAAB4kWQ5mad9XdrUTJ07I09MzS+uKjY3Vo48+Km9vbwUEBOjJJ5/Uzp07ncZcuHBBMTExyps3r7y8vNSyZUsdPXrUaczBgwfVpEkT5c6dWwEBAerbt6+Sk5OzumsAAAAAYItMncooSS1atJB0+QYfHTp0kLu7u9WXkpKizZs3q3r16lnaeFxcnGJiYvToo48qOTlZr7/+uho0aKBt27ZZIa9Xr17673//q6lTp8rX11c9evRQixYttHz5cmvbTZo0UVBQkFasWKEjR46offv2ypkzp959990s1QMAAAAAdsh0MPP19ZV0+YiZt7e3cuXKZfW5ubmpWrVq6tq1a5Y2/vPPPzs9Hz9+vAICArR+/XrVrl1bCQkJGjt2rCZNmqTHH39ckjRu3DiVLVtWq1atUrVq1fTLL79o27ZtWrBggQIDAxUeHq6hQ4fqtdde06BBg+Tm5palmgAAAADgTst0MBs3bpwkqVixYurTp0+WT1vMjISEBEmSv7+/JGn9+vW6dOmS6tWrZ40pU6aMihQpopUrV6patWpauXKlQkNDFRgYaI2JiopS9+7dtXXrVlWsWDHddpKSkpSUlGQ9T0xMzPZ9AQAAAIDMyvI1ZgMHDrwtoSw1NVU9e/ZUjRo1VL58eUlSfHy83Nzc5Ofn5zQ2MDBQ8fHx1pgrQ1laf1pfRmJjY+Xr62s9goODs3lvAAAAACDzMh3M8uTJI39//3SP4sWLKyoqSvPnz7+lQmJiYvT7779r8uTJt7SezOjfv78SEhKsx6FDh277NgEAAADgWjJ9KuPw4cMzbD99+rTWr1+vpk2batq0aWrWrFmWi+jRo4dmz56tpUuXqnDhwlZ7UFCQLl68qNOnTzsdNTt69KiCgoKsMWvWrHFaX9pdG9PGXM3d3d3p5iUAAAAAYKdMB7Po6Ojr9oeHhys2NjZLwcwYo5deekkzZ87UkiVLVLx4caf+SpUqKWfOnFq4cKFatmwpSdq5c6cOHjyoiIgISVJERITeeecdHTt2TAEBAZKk+fPny8fHRyEhIZmuBQAAAADskuVrzK6ladOm2rFjR5aWiYmJ0bfffqtJkybJ29tb8fHxio+P1z///CPp8p0gO3furN69e2vx4sVav369OnbsqIiICFWrVk2S1KBBA4WEhKhdu3b67bffNG/ePL355puKiYnhqBgAAACAe0Kmj5jdSFJSUpZvTT969GhJUp06dZzax40bpw4dOkiShg0bphw5cqhly5ZKSkpSVFSURo0aZY11cXHR7Nmz1b17d0VERMjT01PR0dEaMmTILe0PAAAAANwp2RbMxo4dq/Dw8CwtY4y54RgPDw+NHDlSI0eOvOaYokWLas6cOVnaNgAAAADcLTIdzHr37p1he0JCgjZs2KBdu3Zp6dKl2VYYAAAAADwoMh3MNm7cmGG7j4+P6tevrxkzZqS7eQcAAAAA4MYyHcwWL158O+sAAAAAgAdWtt2VEQAAAABwcwhmAAAAAGAzghkAAAAA2IxgBgAAAAA2y3Qw69Spk86cOXM7awEAAACAB1Kmg9mECRP0zz//3M5aAAAAAOCBlOlgZoy5nXUAAAAAwAMr099jJklnzpyRh4fHdcf4+PjcUkEAAAAA8KDJUjArXbr0NfuMMXI4HEpJSbnlogAAAADgQZKlYDZt2jT5+/vfrloAAAAA4IGUpWBWo0YNBQQE3K5aAAAAAOCBxPeYAQAAAIDNMh3MihYtKhcXl9tZCwAAAAA8kDJ9KuO+fftuZx0AAAAA8MDKdDDLkyePHA5HunZfX1+VLl1affr0Uf369bO1OAAAAAB4EGQ6mA0bNizDYHb69GmtX79eTZs21bRp09SsWbNsLRAAAAAA7neZDmYdOnS4bn94eLhiY2MJZgAAAACQRdl2V8amTZtqx44d2bU6AAAAAHhgZFswS0pKkpubW3atDgAAAAAeGNkWzMaOHavw8PDsWh0AAAAAPDAyfY1Z7969M2xPSEjQhg0btGvXLi1dujTbCgMAAACAB0Wmg9nGjRszbPfx8VH9+vU1Y8YMFS9ePNsKAwAAAIAHRaaD2eLFi6/b/+eff+r555/XmDFjbrkoAAAAAHiQZNs1ZidOnNDYsWOza3UAAAAA8MDItmAGAAAAALg5BDMAAAAAsBnBDAAAAABslumbf7Ro0eK6/adPn77VWgAAAADggZTpYObr63vD/vbt299yQQAAAADwoMl0MBs3btztrAMAAAAAHlhcYwYAAAAANrM1mC1dulTNmjVTwYIF5XA4NGvWLKf+Dh06yOFwOD0aNmzoNObkyZNq27atfHx85Ofnp86dO+vs2bN3cC8AAAAA4NbYGszOnTunChUqaOTIkdcc07BhQx05csR6fPfdd079bdu21datWzV//nzNnj1bS5cu1fPPP3+7SwcAAACAbJPpa8xuh0aNGqlRo0bXHePu7q6goKAM+7Zv366ff/5Za9euVeXKlSVJn332mRo3bqyPPvpIBQsWzPaaAQAAACC73fXXmC1ZskQBAQF6+OGH1b17d504ccLqW7lypfz8/KxQJkn16tVTjhw5tHr16muuMykpSYmJiU4PAAAAALDLXR3MGjZsqG+++UYLFy7U+++/r7i4ODVq1EgpKSmSpPj4eAUEBDgt4+rqKn9/f8XHx19zvbGxsfL19bUewcHBt3U/AAAAAOB6bD2V8UZat25t/RwaGqqwsDCVLFlSS5YsUd26dW96vf3791fv3r2t54mJiYQzAAAAALa5q4+YXa1EiRLKly+f9uzZI0kKCgrSsWPHnMYkJyfr5MmT17wuTbp83ZqPj4/TAwAAAADsck8Fsz///FMnTpxQgQIFJEkRERE6ffq01q9fb41ZtGiRUlNTVbVqVbvKBAAAAIAssfVUxrNnz1pHvyRp37592rRpk/z9/eXv76/BgwerZcuWCgoK0t69e/Xqq6+qVKlSioqKkiSVLVtWDRs2VNeuXfX555/r0qVL6tGjh1q3bs0dGQEAAADcM2w9YrZu3TpVrFhRFStWlCT17t1bFStW1IABA+Ti4qLNmzfriSeeUOnSpdW5c2dVqlRJy5Ytk7u7u7WOiRMnqkyZMqpbt64aN26smjVrasyYMXbtEgAAAABkma1HzOrUqSNjzDX7582bd8N1+Pv7a9KkSdlZFgAAAADcUffUNWYAAAAAcD8imAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDNbg9nSpUvVrFkzFSxYUA6HQ7NmzXLqN8ZowIABKlCggHLlyqV69epp9+7dTmNOnjyptm3bysfHR35+furcubPOnj17B/cCAAAAAG6NrcHs3LlzqlChgkaOHJlh/wcffKBPP/1Un3/+uVavXi1PT09FRUXpwoUL1pi2bdtq69atmj9/vmbPnq2lS5fq+eefv1O7AAAAAAC3zNXOjTdq1EiNGjXKsM8Yo+HDh+vNN99U8+bNJUnffPONAgMDNWvWLLVu3Vrbt2/Xzz//rLVr16py5cqSpM8++0yNGzfWRx99pIIFC2a47qSkJCUlJVnPExMTs3nPAAAAACDz7tprzPbt26f4+HjVq1fPavP19VXVqlW1cuVKSdLKlSvl5+dnhTJJqlevnnLkyKHVq1dfc92xsbHy9fW1HsHBwbdvRwAAAADgBu7aYBYfHy9JCgwMdGoPDAy0+uLj4xUQEODU7+rqKn9/f2tMRvr376+EhATrcejQoWyuHgAAAAAyz9ZTGe3i7u4ud3d3u8sAAAAAAEl38RGzoKAgSdLRo0ed2o8ePWr1BQUF6dixY079ycnJOnnypDUGAAAAAO52d20wK168uIKCgrRw4UKrLTExUatXr1ZERIQkKSIiQqdPn9b69eutMYsWLVJqaqqqVq16x2sGAAAAgJth66mMZ8+e1Z49e6zn+/bt06ZNm+Tv768iRYqoZ8+eevvtt/XQQw+pePHieuutt1SwYEE9+eSTkqSyZcuqYcOG6tq1qz7//HNdunRJPXr0UOvWra95R0YAAAAAuNvYGszWrVunxx57zHreu3dvSVJ0dLTGjx+vV199VefOndPzzz+v06dPq2bNmvr555/l4eFhLTNx4kT16NFDdevWVY4cOdSyZUt9+umnd3xfAAAAAOBm2RrM6tSpI2PMNfsdDoeGDBmiIUOGXHOMv7+/Jk2adDvKAwAAAIA74q69xgwAAAAAHhQEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALDZXR3MBg0aJIfD4fQoU6aM1X/hwgXFxMQob9688vLyUsuWLXX06FEbKwYAAACArLurg5kklStXTkeOHLEev/76q9XXq1cv/fTTT5o6dari4uJ0+PBhtWjRwsZqAQAAACDrXO0u4EZcXV0VFBSUrj0hIUFjx47VpEmT9Pjjj0uSxo0bp7Jly2rVqlWqVq3aNdeZlJSkpKQk63liYmL2Fw4AAAAAmXTXHzHbvXu3ChYsqBIlSqht27Y6ePCgJGn9+vW6dOmS6tWrZ40tU6aMihQpopUrV153nbGxsfL19bUewcHBt3UfAAAAAOB67upgVrVqVY0fP14///yzRo8erX379qlWrVo6c+aM4uPj5ebmJj8/P6dlAgMDFR8ff9319u/fXwkJCdbj0KFDt3EvAAAAAOD67upTGRs1amT9HBYWpqpVq6po0aKaMmWKcuXKddPrdXd3l7u7e3aUCAAAAAC37K4+YnY1Pz8/lS5dWnv27FFQUJAuXryo06dPO405evRohtekAQAAAMDd6p4KZmfPntXevXtVoEABVapUSTlz5tTChQut/p07d+rgwYOKiIiwsUoAAAAAyJq7+lTGPn36qFmzZipatKgOHz6sgQMHysXFRW3atJGvr686d+6s3r17y9/fXz4+PnrppZcUERFx3TsyAgAAAMDd5q4OZn/++afatGmjEydOKH/+/KpZs6ZWrVql/PnzS5KGDRumHDlyqGXLlkpKSlJUVJRGjRplc9UAAAAAkDV3dTCbPHnydfs9PDw0cuRIjRw58g5VBAAAAADZ7566xgwAAAAA7kcEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALDZfRPMRo4cqWLFisnDw0NVq1bVmjVr7C4JAAAAADLlvghm33//vXr37q2BAwdqw4YNqlChgqKionTs2DG7SwMAAACAG7ovgtknn3yirl27qmPHjgoJCdHnn3+u3Llz6+uvv7a7NAAAAAC4IVe7C7hVFy9e1Pr169W/f3+rLUeOHKpXr55WrlyZ4TJJSUlKSkqynickJEiSEhMTb2+xmXXB7gLsdde8D7h/MKfsLgH3I+aV3SXgfsOcsrsES1otxpg7ut17Ppj9/fffSklJUWBgoFN7YGCgduzYkeEysbGxGjx4cLr24ODg21Ijssb3PV+7SwDuK8wpIPsxr4DsdTfOqTNnzsjX987Vdc8Hs5vRv39/9e7d23qempqqkydPKm/evHI4HDZWZr/ExEQFBwfr0KFD8vHxsbsc4J7HnAKyH/MKyF7MKWfGGJ05c0YFCxa8o9u954NZvnz55OLioqNHjzq1Hz16VEFBQRku4+7uLnd3d6c2Pz+/21XiPcnHx4eJCWQj5hSQ/ZhXQPZiTv3PnTxSluaev/mHm5ubKlWqpIULF1ptqampWrhwoSIiImysDAAAAAAy554/YiZJvXv3VnR0tCpXrqwqVapo+PDhOnfunDp27Gh3aQAAAABwQ/dFMHvmmWd0/PhxDRgwQPHx8QoPD9fPP/+c7oYguDF3d3cNHDgw3ameAG4OcwrIfswrIHsxp+4ODnOn7wMJAAAAAHByz19jBgAAAAD3OoIZAAAAANiMYAYAAAAANiOY3aRixYpp+PDhdpdxz9m/f78cDoc2bdp027fFe3Tv4T27OcwrXAvv181hTuF6eM9uDvMqE8w9LDo62kgy3bp1S9f34osvGkkmOjo6U+vat2+fkWQ2btyYqfHHjh0z586dy9TYpk2bmqioqAz7li5daiSZ3377LVPrupbFixcbSebUqVO3tJ6rnT9/3uTJk8fkzZvXXLhwIUvLRkdHm+bNmzu1JScnmyNHjphLly5lW43jxo0zvr6+6dqz8h5ll3//+9+maNGixt3d3VSpUsWsXr36jm4/OzCv/od55Zuu/U7Pq7i4ONO0aVNToEABI8nMnDnzjm07uzCn/oc55Zuu/U7PqXfffddUrlzZeHl5mfz585vmzZubHTt23LHtZxfm1f8wr3zTtd/peTVq1CgTGhpqvL29jbe3t6lWrZqZM2dOltdzzx8xCw4O1uTJk/XPP/9YbRcuXNCkSZNUpEiRbN/exYsXJUn58+dX7ty5M7VM586dNX/+fP3555/p+saNG6fKlSsrLCwsW+u8WcYYJScnW8+nT5+ucuXKqUyZMpo1a9Ytr9/FxUVBQUFydb3939SQlfcoO3z//ffq3bu3Bg4cqA0bNqhChQqKiorSsWPH7lgN2YV5lb2YVzfv3LlzqlChgkaOHHnHtnk7MKeyF3Pq5sXFxSkmJkarVq3S/PnzdenSJTVo0EDnzp27YzVkF+ZV9mJe3bzChQvrvffe0/r167Vu3To9/vjjat68ubZu3Zq1FWVzYLyj0tJ4+fLlzbfffmu1T5w40YSFhZnmzZtbfy2ZO3euqVGjhvH19TX+/v6mSZMmZs+ePdYykpwekZGRTtt4++23TYECBUyxYsWMMcYULVrUDBs2zBhz+S8VOXPmNEuXLrXW9/7775v8+fOb+Ph4c+nSJRMYGGiGDh3qVP+ZM2eMl5eXGT16tDHGmGXLlpmaNWsaDw8PU7hwYfPSSy+Zs2fPWuMvXLhgXn31VVO4cGHj5uZmSpYsab766ivrLz1XPtL2+8KFC+all14y+fPnN+7u7qZGjRpmzZo11jrT/soyZ84c88gjj5icOXOaxYsXW/116tQxn3/+uRk9erSpX79+uvfg999/N02aNDHe3t7Gy8vL1KxZ0+zZs8cMHDgwXU2LFy92+qtUSkqKKVSokBk1apTTOjds2GAcDofZv3+/McaYjz/+2JQvX97kzp3bFC5c2HTv3t2cOXPGqf4rHwMHDkz3HhljzIEDB8wTTzxhPD09jbe3t3n66adNfHy81T9w4EBToUIF880335iiRYsaHx8f88wzz5jExMR0+52RKlWqmJiYGOt5SkqKKViwoImNjc3U8ncL5hXz6m6aV1fSPXzEjDnFnLob55Qxl48sSDJxcXE3tbxdmFfMq7t5XhljTJ48ecxXX32VpWXui2D2ySefmLp161rtdevWNcOGDXOalNOmTTPTp083u3fvNhs3bjTNmjUzoaGhJiUlxRhjzJo1a4wks2DBAnPkyBFz4sQJaxteXl6mXbt25vfffze///67MSb9G963b19TtGhRc/r0abNhwwbj5uZmfvjhB6f+kiVLmtTUVKvt66+/Nrly5TKnT582e/bsMZ6enmbYsGFm165dZvny5aZixYqmQ4cO1vhWrVqZ4OBgM2PGDLN3716zYMECM3nyZJOcnGymT59uJJmdO3eaI0eOmNOnTxtjjHn55ZdNwYIFzZw5c8zWrVtNdHS0yZMnj7V/aR/qsLAw88svv5g9e/ZYfXv27DHu7u7m5MmT5sSJE8bDw8OaKMYY8+effxp/f3/TokULs3btWrNz507z9ddfmx07dpgzZ86YVq1amYYNG5ojR46YI0eOmKSkpHSnC/Tp08fUrFnT6X39v//7P6e2YcOGmUWLFpl9+/aZhQsXmocffth0797dGGNMUlKSGT58uPHx8bG2kzZhr3yPUlJSTHh4uKlZs6ZZt26dWbVqlalUqZL1y9eYy5PSy8vLtGjRwmzZssUsXbrUBAUFmddff/2an8E0SUlJxsXFJd0/Gtu3b2+eeOKJGy5/N2FeMa/ulnl1tXs9mDGnmFN325wyxpjdu3cbSWbLli03tbxdmFfMq7t1XiUnJ5vvvvvOuLm5ma1bt2Zp2fsimB07dsy4u7ub/fv3m/379xsPDw9z/Phxp0l5tePHjzv9IrrW+cXR0dEmMDDQJCUlObVfPSmTkpJMeHi4adWqlQkJCTFdu3Z1Gr99+3brLwZpatWqZZ577jljjDGdO3c2zz//vNMyy5YtMzly5DD//POP2blzp5Fk5s+fn+H+ZHR+8dmzZ03OnDnNxIkTrbaLFy+aggULmg8++MBpuVmzZqVb5+uvv26efPJJ63nz5s2tv0QYY0z//v1N8eLFzcWLFzOsKaPzi69+nTdu3GgcDoc5cOCAMcZYf0FJ+wtSRqZOnWry5s1rPb/W+cVXvke//PKLcXFxMQcPHrT6t27daiRZfz0aOHCgyZ07t9NfR/r27WuqVq16zVrS/PXXX0aSWbFihVN73759TZUqVW64/N2EefU/zCvfdOPu5Ly62r0ezJhTzKm7bU6lpKSYJk2amBo1amR5Wbsxr/6HeeWbbpwd82rz5s3G09PTuLi4GF9fX/Pf//4308umueevMZMun0fapEkTjR8/XuPGjVOTJk2UL18+pzG7d+9WmzZtVKJECfn4+KhYsWKSpIMHD95w/aGhoXJzc7vuGDc3N02cOFHTp0/XhQsXNGzYMKf+MmXKqHr16vr6668lSXv27NGyZcvUuXNnSdJvv/2m8ePHy8vLy3pERUUpNTVV+/bt06ZNm+Ti4qLIyMjMvizau3evLl26pBo1alhtOXPmVJUqVbR9+3ansZUrV3Z6npKSogkTJui5556z2p577jmNHz9eqampkqRNmzapVq1aypkzZ6Zrulp4eLjKli2rSZMmSbp87vuxY8f09NNPW2MWLFigunXrqlChQvL29la7du104sQJnT9/PtPb2b59u4KDgxUcHGy1hYSEyM/Pz+m1KFasmLy9va3nBQoUuCevEcsOzKuMMa/+h3mVNcypjDGn/udOz6mYmBj9/vvvmjx5cpaXvVswrzLGvPqfOzWvHn74YW3atEmrV69W9+7dFR0drW3btmV6eek+ul1+p06dNH78eE2YMEGdOnVK19+sWTOdPHlSX375pVavXq3Vq1dL+t+FnNfj6emZqRpWrFghSTp58qROnjyZrr9z586aPn26zpw5o3HjxqlkyZLWJDt79qy6deumTZs2WY/ffvtNu3fvVsmSJZUrV65M1XCzrt7HefPm6a+//tIzzzwjV1dXubq6qnXr1jpw4IAWLlwoSdlWU9u2ba1JOWnSJDVs2FB58+aVdPnWqk2bNlVYWJimT5+u9evXWzcByMx7l1VX/4JxOBzWL6HryZcvn1xcXHT06FGn9qNHjyooKChba7yTmFe3hnl12c3Oq/sRc+rWMKcuy4451aNHD82ePVuLFy9W4cKFs7O8O455dWuYV5fd6rxyc3NTqVKlVKlSJcXGxqpChQoaMWJElmq4b4JZw4YNdfHiRV26dElRUVFOfSdOnNDOnTv15ptvqm7duipbtqxOnTrlNCbtryEpKSk3tf29e/eqV69e+vLLL1W1alVFR0enezNbtWqlHDlyaNKkSfrmm2/UqVMnORwOSdIjjzyibdu2qVSpUukebm5uCg0NVWpqquLi4jLcfkb1lyxZUm5ublq+fLnVdunSJa1du1YhISHX3Z+xY8eqdevWTr8kNm3apNatW2vs2LGSpLCwMC1btkyXLl26Zk2ZeT2fffZZ/f7771q/fr2mTZumtm3bWn3r169XamqqPv74Y1WrVk2lS5fW4cOHs7ydsmXL6tChQzp06JDVtm3bNp0+ffqGr0VmuLm5qVKlStYvLElKTU3VwoULFRERccvrtwvzinl1Pbd7Xt2PmFPMqeu5E3PKGKMePXpo5syZWrRokYoXL54t67UT84p5dT12/b8qNTVVSUlJWVsoyyc/3kWuPn81ISHBJCQkWM/Tzi9OSUkxefPmNc8995zZvXu3WbhwoXn00Uedrle4dOmSyZUrl3n77bdNfHy8deFkRufIGuN87mpycrKpVq2aadmypTHGmMOHD5u8efNa5/BeqXPnziZPnjzGxcXF/PXXX1b7b7/9ZnLlymViYmLMxo0bza5du8ysWbOc7vLXoUMHExwcbGbOnGn++OMPs3jxYvP9998bYy5fhOlwOMz48ePNsWPHrIsfX3nlFVOwYEEzd+5cpws/T548aYzJ+LzkY8eOmZw5c5q5c+emq3/OnDnG3d3dnDhxwvz9998mb9681oWfu3btMt988431fSjvvPOOKVKkiNmxY4c5fvy4uXjx4jXP465Ro4apUKGC8fb2NufPn7faN23aZCSZ4cOHm71795pvvvnGFCpUyKnm5cuXWxftHj9+3Preiivfo9TUVBMeHm5q1apl1q9fb1avXp3hhZ8VKlRwqmvYsGGmaNGi6V6HjEyePNm4u7ub8ePHm23btpnnn3/e+Pn5Od31517AvGJeGXP3zKszZ86YjRs3mo0bNxpJ5pNPPjEbN260rkm4FzCnmFPG3D1zqnv37sbX19csWbLEumHCkSNHnPbnXsC8Yl4Zc/fMq379+pm4uDizb98+s3nzZtOvXz/jcDjML7/8kqnl09xXwexqV174OX/+fFO2bFnj7u5uwsLCzJIlS9JdSP7ll1+a4OBgkyNHjnS3Sr3alW/44MGDTYECBczff/9t9U+fPt24ubmZTZs2OS23YsUKI8k0btw43TrXrFlj6tevb7y8vIynp6cJCwsz77zzjtX/zz//mF69epkCBQoYNzc3U6pUKfP1119b/UOGDDFBQUHG4XBY+/3PP/+Yl156yeTLl++6t0q9clJ+9NFHxs/PL8MLOpOSkoyfn58ZMWKEMebyL5MGDRqY3LlzG29vb1OrVi2zd+9eY8zlyZ22P8rgVqlXGjVqlJFk2rdvn26bn3zyiSlQoIDJlSuXiYqKMt988026ml944QWTN2/ebLlV6pWyMimNMeazzz4zRYoUMW5ubqZKlSpm1apVmV72bsG8Yl6luRvmVUa3Q5Yy/8WxdwPmFHMqzd0wpzKaT5LMuHHjMrX83YJ5xbxKczfMq06dOpmiRYsaNzc3kz9/flO3bt0shzJjjHEYY0zWjrEBAAAAALLTfXONGQAAAADcqwhmQCYcPHjQ6Ta2Vz8yc8tdAM6YV0D2Yk4B2e9OzitOZQQyITk5Wfv3779mf7FixeTq6nrnCgLuA8wrIHsxp4DsdyfnFcEMAAAAAGzGqYwAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAIAHWp06ddSzZ0+7ywAAPOAIZgCAm9KhQwc5HA699957Tu2zZs2Sw+HI0rqKFSum4cOHZ2N1t8/+/fvlcDi0adMmu0sBANxHCGYAgJvm4eGh999/X6dOnbK7lCy7ePGi3SVkq0uXLtldAgDgFhDMAAA3rV69egoKClJsbOx1x/3666+qVauWcuXKpeDgYL388ss6d+6cpMunEh44cEC9evWSw+GQw+GQMUb58+fXtGnTrHWEh4erQIECTut0d3fX+fPnJUkHDx5U8+bN5eXlJR8fH7Vq1UpHjx61xg8aNEjh4eH66quvVLx4cXl4eGRY63//+1/5+vpq4sSJN/Wa7N27V82bN1dgYKC8vLz06KOPasGCBVb/kCFDVL58+XTLhYeH66233rKef/XVVypbtqw8PDxUpkwZjRo1yupLO2r3/fffKzIyUh4eHpo4caIOHDigZs2aKU+ePPL09FS5cuU0Z86cm9oPAMCdRTADANw0FxcXvfvuu/rss8/0559/Zjhm7969atiwoVq2bKnNmzfr+++/16+//qoePXpIkmbMmKHChQtryJAhOnLkiI4cOSKHw6HatWtryZIlkqRTp05p+/bt+ueff7Rjxw5JUlxcnB599FHlzp1bqampat68uU6ePKm4uDjNnz9ff/zxh5555hmnWvbs2aPp06drxowZGZ6KOGnSJLVp00YTJ05U27Ztb+o1OXv2rBo3bqyFCxdq48aNatiwoZo1a6aDBw9Kkjp16qTt27dr7dq11jIbN27U5s2b1bFjR0nSxIkTNWDAAL3zzjvavn273n33Xb311luaMGGC07b69eunV155Rdu3b1dUVJRiYmKUlJSkpUuXasuWLXr//ffl5eV1U/sBALizXO0uAABwb/vXv/6l8PBwDRw4UGPHjk3XHxsbq7Zt21o32HjooYf06aefKjIyUqNHj5a/v79cXFzk7e2toKAga7k6deroiy++kCQtXbpUFStWVFBQkJYsWaIyZcpoyZIlioyMlCQtXLhQW7Zs0b59+xQcHCxJ+uabb1SuXDmtXbtWjz76qKTLpy9+8803yp8/f7o6R44cqTfeeEM//fSTtd6bUaFCBVWoUMF6PnToUM2cOVM//vijevToocKFCysqKkrjxo2z6ho3bpwiIyNVokQJSdLAgQP18ccfq0WLFpKk4sWLa9u2bfriiy8UHR1trbtnz57WGOnyUcOWLVsqNDRUkqz1AQDufhwxAwDcsvfff18TJkzQ9u3b0/X99ttvGj9+vLy8vKxHVFSUUlNTtW/fvmuuMzIyUtu2bdPx48cVFxenOnXqqE6dOlqyZIkuXbqkFStWqE6dOpKk7du3Kzg42AplkhQSEiI/Pz+nmooWLZphKJs2bZp69eql+fPn31Ioky4fMevTp4/Kli0rPz8/eXl5afv27dYRM0nq2rWrvvvuO124cEEXL17UpEmT1KlTJ0nSuXPntHfvXnXu3NnpNXv77be1d+9ep21VrlzZ6fnLL7+st99+WzVq1NDAgQO1efPmW9oXAMCdQzADANyy2rVrKyoqSv3790/Xd/bsWXXr1k2bNm2yHr/99pt2796tkiVLXnOdoaGh8vf3V1xcnFMwi4uL09q1a3Xp0iVVr149S3V6enpm2F6xYkXlz59fX3/9tYwxWVrn1fr06aOZM2fq3Xff1bJly7Rp0yaFhoY63WykWbNmcnd318yZM/XTTz/p0qVLeuqppyRdfr0k6csvv3R6zX7//XetWrXquvvTpUsX/fHHH2rXrp22bNmiypUr67PPPrul/QEA3BmcyggAyBbvvfeewsPD9fDDDzu1P/LII9q2bZtKlSp1zWXd3NyUkpLi1OZwOFSrVi398MMP2rp1q2rWrKncuXMrKSlJX3zxhSpXrmwFk7Jly+rQoUM6dOiQddRs27ZtOn36tEJCQm5Ye8mSJfXxxx+rTp06cnFx0b///e+s7r5l+fLl6tChg/71r39Juhy09u/f7zTG1dVV0dHRGjdunNzc3NS6dWvlypVLkhQYGKiCBQvqjz/+uKnr3IKDg/XCCy/ohRdeUP/+/fXll1/qpZdeuun9AQDcGQQzAEC2CA0NVdu2bfXpp586tb/22muqVq2aevTooS5dusjT01Pbtm3T/PnzrQBUrFgxLV26VK1bt5a7u7vy5csn6fJ1Zv/3f/+nypUrWzexqF27tiZOnKi+ffta26hXr561/eHDhys5OVkvvviiIiMj053udy2lS5fW4sWLVadOHbm6ut7we9V27tyZrq1cuXJ66KGHNGPGDDVr1kwOh0NvvfWWUlNT043t0qWLypYtK+lymLvS4MGD9fLLL8vX11cNGzZUUlKS1q1bp1OnTql3797XrKlnz55q1KiRSpcurVOnTmnx4sXWNgAAdzdOZQQAZJshQ4akCyFhYWGKi4vTrl27VKtWLVWsWFEDBgxQwYIFnZbbv3+/SpYs6XQNWGRkpFJSUqxryaTLYe3qNofDoR9++EF58uRR7dq1Va9ePZUoUULff/99lup/+OGHtWjRIn333Xf6v//7v+uObd26tSpWrOj0OHr0qD755BPlyZNH1atXV7NmzRQVFaVHHnkk3fIPPfSQqlevrjJlyqhq1apOfV26dNFXX32lcePGKTQ0VJGRkRo/fryKFy9+3ZpSUlIUExOjsmXLqmHDhipdurTTbfYBAHcvh7nVk+kBAECWGWP00EMP6cUXX7zuUTAAwIOBUxkBALjDjh8/rsmTJys+Pt767jIAwIONYAYAwB0WEBCgfPnyacyYMcqTJ4/d5QAA7gIEMwAA7jCuIgAAXI2bfwAAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANvt/0FgPyPFgHAkAAAAASUVORK5CYII=", + "text/plain": [ + "
" + ] + }, + "metadata": {}, + "output_type": "display_data" + } + ], + "source": [ + "layers = list(res_dict.keys())\n", + "utilisation = list(res_dict.values())\n", + "lut_values = [] #Initializing a list to store LUT values.\n", + "for i in range(len(layers)):\n", + " x = list(utilisation[i].values()) #Extracting the resource utilisation for each layer as a list.\n", + " lut_values.append(x[2]) #Extracting the LUT values of resource utilisation from each layer and appending to the list\n", + " \n", + "#Plotting the bar graph of each network layer with their corresponding LUT resource utilisation\n", + "fig = plt.figure(figsize = (10, 5))\n", + "plt.bar(layers, lut_values, color ='green', width = 0.3)\n", + "plt.xlabel(\"Network Layers\")\n", + "plt.ylabel(\"LUT Utilisation\")\n", + "plt.title(\"Estimated LUT values used for each network layer\")\n", + "plt.show()" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "Note, from the above result we observe that the bottleneck in the execution of the model on hardware would come from the execution of the first layer which takes estimated 38400 clock cycles to execute one set of its inputs.\n", + "No matter how quickly the layers execute the (throughput or latency?) will be defined by the first layer's execution latency.\n", + "\n", + "So our goal to adjust the folding parameters would be to expand the computation of the first layer to reduce its latency at the expense an of increase in resource utilization." + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "
\n", + "Question in the first line of the above cell.\n", + "
" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "# QuickNote : StreamingDataWidthConverter Layer" + ] + }, + { + "cell_type": "code", + "execution_count": 37, + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "Instream Width = 1 Outstream Width = 2\n", + "Instream Width = 2 Outstream Width = 2\n", + "Instream Width = 2 Outstream Width = 2\n", + "Instream Width = 2 Outstream Width = 1\n" + ] + } + ], + "source": [ + "fc_layers = model.get_nodes_by_op_type(\"MatrixVectorActivation\")\n", + "for fcl in fc_layers:\n", + " fcl_inst = getCustomOp(fcl)\n", + " print('Instream Width =',(fcl_inst.get_instream_width()),'Outstream Width =',int(fcl_inst.get_outstream_width()))" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "We can also view the `instream_width` and `outstream_width` of each layer using the `get_instream_width()` and `get_outstream_width()` helper functions. These widths are of particular importance as for a (balanced pipeline?) these width's should be the same.\n", + "\n", + "For example, the outwidth of a given layer of the network should match the inwidth of the next layer for the (pipeline to be stable?). If they are not the same then the FINN compiler adds an extra `streamingdatawidthconverter` (which increases the overall resource utilization of the design slightly) layer to make sure these widths match.\n", + "\n", + "Note, that if these widths are the same then even if we call the `InsertDWC()` transformation on our model (responsible for adding the above layer), the datawidth conversion layers will not be a part of our model as shown in the below cells. " + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "
\n", + "Question in the first and the second line of the above cell.\n", + "
" + ] + }, + { + "cell_type": "code", + "execution_count": 11, + "metadata": {}, + "outputs": [], + "source": [ + "from finn.transformation.fpgadataflow.insert_dwc import InsertDWC\n", + "model = model.transform(InsertDWC())" + ] + }, + { + "cell_type": "code", + "execution_count": 12, + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "Stopping http://0.0.0.0:5901\n", + "Serving './cybsec_DWC_not_inserted.onnx' at http://0.0.0.0:5901\n" + ] + }, + { + "data": { + "text/html": [ + "\n", + " \n", + " " + ], + "text/plain": [ + "" + ] + }, + "execution_count": 12, + "metadata": {}, + "output_type": "execute_result" + } + ], + "source": [ + "model.save(\"./cybsec_DWC_not_inserted.onnx\")\n", + "showInNetron(\"./cybsec_DWC_not_inserted.onnx\",localhost_url='xirxlabs53')#localhost_url='xirxlabs60'" + ] + }, + { + "cell_type": "code", + "execution_count": 13, + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "class MatrixVectorActivation(HLSCustomOp):\n", + " \"\"\"Class that corresponds to finn-hls Matrix_Vector_Activate(_Stream)_Batch\n", + " function.\"\"\"\n", + "\n", + " def __init__(self, onnx_node):\n", + " super().__init__(onnx_node)\n", + " self.decoupled_wrapper = templates.decoupled_wrapper\n", + "\n", + " def get_nodeattr_types(self):\n", + " my_attrs = {\n", + " \"PE\": (\"i\", True, 0),\n", + " \"SIMD\": (\"i\", True, 0),\n", + " \"MW\": (\"i\", True, 0),\n", + " \"MH\": (\"i\", True, 0),\n", + " \"resType\": (\"s\", False, \"lut\", {\"auto\", \"lut\", \"dsp\"}),\n", + " \"ActVal\": (\"i\", False, 0),\n", + " # FINN DataTypes for inputs, weights, outputs\n", + " \"inputDataType\": (\"s\", True, \"\"),\n", + " \"weightDataType\": (\"s\", True, \"\"),\n", + " \"outputDataType\": (\"s\", True, \"\"),\n", + " # FINN DataType for accumulator -- auto-computed and updated\n", + " \"accDataType\": (\"s\", False, \"INT32\"),\n", + " # use xnor-popcount for binary weights/inputs, thus treating them\n", + " # as bipolar\n", + " \"binaryXnorMode\": (\"i\", False, 0, {0, 1}),\n", + " # no-activation mode (produce accumulators)\n", + " \"noActivation\": (\"i\", False, 0, {0, 1}),\n", + " # number of input vectors, examples:\n", + " # [1] is a single vector (like a FC layer with batch=1)\n", + " # [4] is four vectors (like a FC layer with batch=4)\n", + " # [1, 4, 4] is four * four vectors (like a conv layer with batch=1)\n", + " \"numInputVectors\": (\"ints\", False, [1]),\n", + " # memory mode for the FC weights\n", + " # const -- embedded weights, default, long compile/synth times\n", + " # decoupled -- streaming weights with weight streamer packaged inside IP\n", + " # external -- streaming weights with external streamer\n", + " \"mem_mode\": (\"s\", False, \"const\", {\"const\", \"decoupled\", \"external\"}),\n", + " # FPGA resource type for memories in decoupled mode\n", + " # auto -- let Vivado decide\n", + " # block -- use BRAM\n", + " # distributed -- use LUTRAM\n", + " # ultra -- use UltraRAM (URAM), must have runtime_writeable_weights=1\n", + " # see also https://www.xilinx.com/support/answers/38070.html\n", + " \"ram_style\": (\n", + " \"s\",\n", + " False,\n", + " \"auto\",\n", + " {\"auto\", \"block\", \"distributed\", \"ultra\"},\n", + " ),\n", + " # FPGA resource type for threshold memories (if noActivation is False)\n", + " # auto -- let Vivado decide\n", + " # block -- use BRAM\n", + " # distributed -- use LUTRAM\n", + " \"ram_style_thresholds\": (\n", + " \"s\",\n", + " False,\n", + " \"auto\",\n", + " {\"auto\", \"block\", \"distributed\"},\n", + " ),\n", + " # (mem_mode = decoupled only) whether weights will be writable through\n", + " # an AXI-lite interface during runtime\n", + " # 1 for enabled, 0 for disabled.\n", + " # see finn-rtllib/memstream/doc/README for more about the memory\n", + " # address map used for writable weights\n", + " # IMPORTANT: After using AXI lite to either read or write the weights,\n", + " # always \"flush\" the accelerator by first passing a dummy input\n", + " # vector through the accelerator. This will get rid of any old\n", + " # weight data from the weight FIFOs.\n", + " \"runtime_writeable_weights\": (\"i\", False, 0, {0, 1}),\n", + " }\n", + " my_attrs.update(super().get_nodeattr_types())\n", + " return my_attrs\n", + "\n", + " def calc_wmem(self):\n", + " \"\"\"Calculates and returns WMEM.\"\"\"\n", + " mw = self.get_nodeattr(\"MW\")\n", + " mh = self.get_nodeattr(\"MH\")\n", + " pe = self.get_nodeattr(\"PE\")\n", + " simd = self.get_nodeattr(\"SIMD\")\n", + " assert mh % pe == 0, \"Requirement MH divisable by PE is violated.\"\n", + " assert mw % simd == 0, \"Requirement MW divisable by SIMD is violated.\"\n", + " wmem = mw * mh // (pe * simd)\n", + " return wmem\n", + "\n", + " def calc_tmem(self):\n", + " \"\"\"Calculates and returns TMEM.\"\"\"\n", + " if self.get_nodeattr(\"noActivation\") == 1:\n", + " return 0\n", + " else:\n", + " mh = self.get_nodeattr(\"MH\")\n", + " pe = self.get_nodeattr(\"PE\")\n", + " return mh // pe\n", + "\n", + " def make_shape_compatible_op(self, model):\n", + " oshape = self.get_normal_output_shape()\n", + " return super().make_const_shape_op(oshape)\n", + "\n", + " def infer_node_datatype(self, model):\n", + " node = self.onnx_node\n", + " idt = model.get_tensor_datatype(node.input[0])\n", + " if idt != self.get_input_datatype():\n", + " warn_str = \"inputDataType changing for %s: %s -> %s \" % (\n", + " node.name,\n", + " str(self.get_input_datatype()),\n", + " str(idt),\n", + " )\n", + " warnings.warn(warn_str)\n", + " self.set_nodeattr(\"inputDataType\", idt.name)\n", + " # set output datatype from property\n", + " odt = self.get_output_datatype()\n", + " model.set_tensor_datatype(node.output[0], odt)\n", + "\n", + " def verify_node(self):\n", + " info_messages = []\n", + " # verify that \"backend\" is set to \"fpgadataflow\"\n", + " backend_value = self.get_nodeattr(\"backend\")\n", + " if backend_value == \"fpgadataflow\":\n", + " info_messages.append(\"Attribute backend is set correctly\")\n", + " else:\n", + " info_messages.append('Attribute backend should be set to \"fpgadataflow\"')\n", + "\n", + " # verify that all necessary attributes exist\n", + " # TODO collect automatically from get_nodeattr_types\n", + " try:\n", + " self.get_nodeattr(\"code_gen_dir_cppsim\")\n", + " self.get_nodeattr(\"executable_path\")\n", + " self.get_nodeattr(\"resType\")\n", + " self.get_nodeattr(\"MW\")\n", + " self.get_nodeattr(\"MH\")\n", + " self.get_nodeattr(\"SIMD\")\n", + " self.get_nodeattr(\"PE\")\n", + " self.get_nodeattr(\"inputDataType\")\n", + " self.get_nodeattr(\"weightDataType\")\n", + " self.get_nodeattr(\"outputDataType\")\n", + " info_messages.append(\"All necessary attributes exist\")\n", + " except Exception:\n", + " info_messages.append(\n", + " \"\"\"The required MatrixVectorActivation attributes do not exist.\"\"\"\n", + " )\n", + "\n", + " # verify the number of inputs depending on noActivation value\n", + " # check noActivation value to determine the number of inputs\n", + " no_act = self.get_nodeattr(\"noActivation\")\n", + "\n", + " if no_act == 1:\n", + " if len(self.onnx_node.input) == 2:\n", + " info_messages.append(\"The number of inputs is correct\")\n", + " else:\n", + " info_messages.append(\n", + " \"\"\"MatrixVectorActivation needs in no\n", + " activation mode 2 inputs (data input and weights)\"\"\"\n", + " )\n", + " elif no_act == 0:\n", + " if len(self.onnx_node.input) == 3:\n", + " info_messages.append(\"The number of inputs is correct\")\n", + " else:\n", + " info_messages.append(\n", + " \"\"\"MatrixVectorActivation needs 3 inputs\n", + " (data input and weights and threshold values)\"\"\"\n", + " )\n", + " else:\n", + " info_messages.append(\n", + " \"\"\"noActivation attribute contains {} should\n", + " be 0 or 1\"\"\".format(\n", + " no_act\n", + " )\n", + " )\n", + "\n", + " return info_messages\n", + "\n", + " def uram_estimation(self):\n", + " P = self.get_nodeattr(\"PE\")\n", + " Q = self.get_nodeattr(\"SIMD\")\n", + " wdt = self.get_weight_datatype()\n", + " W = wdt.bitwidth()\n", + " D_in = self.get_nodeattr(\"MW\")\n", + " D_out = self.get_nodeattr(\"MH\")\n", + " omega = (D_in * D_out) / (Q * P)\n", + " mem_width = Q * W * P\n", + " mmode = self.get_nodeattr(\"mem_mode\")\n", + " mstyle = self.get_nodeattr(\"ram_style\")\n", + " if (\n", + " (mmode == \"decoupled\" and mstyle != \"ultra\")\n", + " or (mmode == \"const\" and self.calc_wmem() <= 128)\n", + " or (mmode == \"external\")\n", + " ):\n", + " return 0\n", + " width_multiplier = math.ceil(mem_width / 72)\n", + " depth_multiplier = math.ceil(omega / 4096)\n", + " return width_multiplier * depth_multiplier\n", + "\n", + " def bram_estimation(self):\n", + " \"\"\"Calculates resource estimation for BRAM based on:\n", + " - FINN-R: An End-to-End Deep-Learning Framework for Fast\n", + " Exploration of Quantized Neural Networks\n", + " - M. Blott, T. B. Preusser, N. J. Fraser, G. Gambardella, K. O'Brien,\n", + " Y. Umuroglu, M. Leeser and K. Vissers\n", + " - 12. Sep 2018\n", + " \"\"\"\n", + " # TODO add in/out FIFO contributions\n", + " P = self.get_nodeattr(\"PE\")\n", + " Q = self.get_nodeattr(\"SIMD\")\n", + " wdt = self.get_weight_datatype()\n", + " W = wdt.bitwidth()\n", + " D_in = self.get_nodeattr(\"MW\")\n", + " D_out = self.get_nodeattr(\"MH\")\n", + " omega = (D_in * D_out) / (Q * P)\n", + " mem_width = Q * W * P\n", + " mmode = self.get_nodeattr(\"mem_mode\")\n", + " mstyle = self.get_nodeattr(\"ram_style\")\n", + " if (\n", + " (mmode == \"decoupled\" and mstyle in [\"distributed\", \"ultra\"])\n", + " or (mmode == \"const\" and self.calc_wmem() <= 128)\n", + " or (mmode == \"external\")\n", + " ):\n", + " return 0\n", + " # assuming SDP mode RAMB18s (see UG573 Table 1-10)\n", + " # assuming decoupled (RTL) memory, which is more efficient than const (HLS)\n", + " if mem_width == 1:\n", + " return math.ceil(omega / 16384)\n", + " elif mem_width == 2:\n", + " return math.ceil(omega / 8192)\n", + " elif mem_width <= 4:\n", + " return (math.ceil(omega / 4096)) * (math.ceil(mem_width / 4))\n", + " elif mem_width <= 9:\n", + " return (math.ceil(omega / 2048)) * (math.ceil(mem_width / 9))\n", + " elif mem_width <= 18 or omega > 512:\n", + " return (math.ceil(omega / 1024)) * (math.ceil(mem_width / 18))\n", + " else:\n", + " return (math.ceil(omega / 512)) * (math.ceil(mem_width / 36))\n", + "\n", + " def bram_efficiency_estimation(self):\n", + " wdt = self.get_weight_datatype()\n", + " W = wdt.bitwidth()\n", + " D_in = self.get_nodeattr(\"MW\")\n", + " D_out = self.get_nodeattr(\"MH\")\n", + " bram16_est = self.bram_estimation()\n", + " if bram16_est == 0:\n", + " return 1\n", + " wbits = W * D_in * D_out\n", + " bram16_est_capacity = bram16_est * 36 * 512\n", + " return wbits / bram16_est_capacity\n", + "\n", + " def uram_efficiency_estimation(self):\n", + " \"\"\"Function for URAM efficiency estimation: actual parameter storage\n", + " needed divided by the allocated URAM storage (from estimation)\"\"\"\n", + " wdt = self.get_weight_datatype()\n", + " W = wdt.bitwidth()\n", + " D_in = self.get_nodeattr(\"MW\")\n", + " D_out = self.get_nodeattr(\"MH\")\n", + " uram_est = self.uram_estimation()\n", + " if uram_est == 0:\n", + " return 1\n", + " wbits = W * D_in * D_out\n", + " uram_est_capacity = uram_est * 72 * 4096\n", + " return wbits / uram_est_capacity\n", + "\n", + " def lut_estimation(self):\n", + " \"\"\"Calculates resource estimations for LUTs based on:\n", + " - FINN-R: An End-to-End Deep-Learning Framework for Fast\n", + " Exploration of Quantized Neural Networks\n", + " - M. Blott, T. B. Preusser, N. J. Fraser, G. Gambardella, K. O'Brien,\n", + " Y. Umuroglu, M. Leeser and K. Vissers\n", + " - 12. Sep 2018\n", + " \"\"\"\n", + " # TODO add in/out FIFO contributions\n", + " P = self.get_nodeattr(\"PE\")\n", + " Q = self.get_nodeattr(\"SIMD\")\n", + " MW = self.get_nodeattr(\"MW\")\n", + " wdt = self.get_weight_datatype()\n", + " W = wdt.bitwidth()\n", + " # determine tdt with input and weight data types\n", + " idt = self.get_input_datatype()\n", + " A = idt.bitwidth()\n", + " # parameters from experiments in paper mentioned above\n", + " c0 = 300\n", + " c1 = 1.1\n", + " c2 = 0\n", + " mmode = self.get_nodeattr(\"mem_mode\")\n", + " mstyle = self.get_nodeattr(\"ram_style\")\n", + " if (mmode == \"decoupled\" and mstyle == \"distributed\") or (\n", + " mmode == \"const\" and self.calc_wmem() <= 128\n", + " ):\n", + " c2 = (P * Q * W) * math.ceil(self.calc_wmem() / 64)\n", + "\n", + " # multiplication\n", + " res_type = self.get_nodeattr(\"resType\")\n", + " if res_type == \"dsp\":\n", + " mult_luts = 0\n", + " else:\n", + " mult_luts = Q * (2 * math.ceil((W + A) / 6) - 1) * (W + A)\n", + " # adder tree\n", + " addertree_luts = (W + A) * (2 * Q - 1)\n", + " # accumulator\n", + " acc_bits = W + A + np.ceil(math.log(MW, 2))\n", + " acc_luts = acc_bits\n", + " # thresholds and threshold comparators\n", + " thr_luts = 0\n", + " comp_luts = 0\n", + " noact = self.get_nodeattr(\"noActivation\")\n", + " if noact == 0:\n", + " odt = self.get_output_datatype()\n", + " B = odt.bitwidth()\n", + " thr_luts = (2**B - 1) * acc_bits * math.ceil(self.calc_tmem() / 64)\n", + " comp_luts = (2**B - 1) * acc_bits\n", + "\n", + " return int(\n", + " c0\n", + " + c1 * (P * (mult_luts + addertree_luts + acc_luts + thr_luts + comp_luts))\n", + " + c2\n", + " )\n", + "\n", + " def dsp_estimation(self):\n", + " # multiplication\n", + " P = self.get_nodeattr(\"PE\")\n", + " res_type = self.get_nodeattr(\"resType\")\n", + " Q = self.get_nodeattr(\"SIMD\")\n", + " wdt = self.get_weight_datatype()\n", + " W = wdt.bitwidth()\n", + " idt = self.get_input_datatype()\n", + " A = idt.bitwidth()\n", + " if res_type == \"dsp\":\n", + " mult_dsp = P * Q * np.ceil((W + A) / 48) # TODO: more accurate modelling\n", + " else:\n", + " mult_dsp = 0\n", + " return int(mult_dsp)\n", + "\n", + " def get_exp_cycles(self):\n", + " pe = self.get_nodeattr(\"PE\")\n", + " simd = self.get_nodeattr(\"SIMD\")\n", + " num_inp_vec = self.get_nodeattr(\"numInputVectors\")\n", + " mh = self.get_nodeattr(\"MH\")\n", + " mw = self.get_nodeattr(\"MW\")\n", + " # since mmv != 1 is not supported yet, we set mmv for now to 1\n", + " mmv = 1\n", + " exp_cycles = (mh / pe) * (mw / simd) * np.prod(num_inp_vec) / mmv\n", + " return int(exp_cycles)\n", + "\n", + " def get_input_datatype(self, ind=0):\n", + " \"\"\"Returns FINN DataType of input.\"\"\"\n", + " # when performing FIFO insertion on an FC layer with ext weights, the ind\n", + " # parameter can be > 0 (referring to the weights) so handle that here\n", + " if ind == 0:\n", + " return DataType[self.get_nodeattr(\"inputDataType\")]\n", + " elif ind == 1:\n", + " return DataType[self.get_nodeattr(\"weightDataType\")]\n", + " else:\n", + " raise Exception(\"Undefined input ind for this layer type\")\n", + "\n", + " def get_weight_datatype(self):\n", + " \"\"\"Returns FINN DataType of weights.\"\"\"\n", + " return DataType[self.get_nodeattr(\"weightDataType\")]\n", + "\n", + " def get_output_datatype(self, ind=0):\n", + " \"\"\"Returns FINN DataType of output.\"\"\"\n", + " return DataType[self.get_nodeattr(\"outputDataType\")]\n", + "\n", + " def get_instream_width(self, ind=0):\n", + " i_bits = self.get_input_datatype().bitwidth()\n", + " in_width = i_bits * self.get_nodeattr(\"SIMD\")\n", + " return in_width\n", + "\n", + " def get_outstream_width(self, ind=0):\n", + " o_bits = self.get_output_datatype().bitwidth()\n", + " out_width = o_bits * self.get_nodeattr(\"PE\")\n", + " return out_width\n", + "\n", + " def get_weightstream_width(self):\n", + " \"\"\"Returns weight stream width. Used only in decoupled mode.\"\"\"\n", + " if (\n", + " self.get_nodeattr(\"mem_mode\") == \"decoupled\"\n", + " or self.get_nodeattr(\"mem_mode\") == \"external\"\n", + " ):\n", + " pe = self.get_nodeattr(\"PE\")\n", + " simd = self.get_nodeattr(\"SIMD\")\n", + " wp = self.get_weight_datatype().bitwidth()\n", + " w_width = pe * simd * wp\n", + " return w_width\n", + " else:\n", + " return 0\n", + "\n", + " def get_weightstream_width_padded(self):\n", + " \"\"\"Returns weight stream width padded to a multiple of 8. This is required\n", + " by the AXI Stream spec. Used in decoupled mode.\"\"\"\n", + " weight_width = self.get_weightstream_width()\n", + " return roundup_to_integer_multiple(weight_width, 8)\n", + "\n", + " def get_ap_int_max_w(self):\n", + " # base class impl (max of inp/out stream widths)\n", + " max_of_io = super().get_ap_int_max_w()\n", + " # decoupled mode weight stream\n", + " weightstream = self.get_weightstream_width()\n", + " # single PE weight entry\n", + " weight_bits = self.get_weight_datatype().bitwidth()\n", + " simd = self.get_nodeattr(\"SIMD\")\n", + " single_pe_w = simd * weight_bits\n", + " return max([weightstream, max_of_io, single_pe_w])\n", + "\n", + " def get_folded_input_shape(self, ind=0):\n", + " mw = self.get_nodeattr(\"MW\")\n", + " mh = self.get_nodeattr(\"MH\")\n", + " simd = self.get_nodeattr(\"SIMD\")\n", + " pe = self.get_nodeattr(\"PE\")\n", + " sf = mw // simd\n", + " nf = mh // pe\n", + " vecs = list(self.get_nodeattr(\"numInputVectors\"))\n", + "\n", + " if ind == 0:\n", + " # calculate shape of input 0\n", + " folded_input_shape = tuple(vecs + [sf, simd])\n", + " elif ind == 1 and self.get_nodeattr(\"mem_mode\") == \"external\":\n", + " # calculate shape of input 1 (weights)\n", + " folded_input_shape = tuple(vecs + [sf * nf, simd * pe])\n", + " else:\n", + " raise Exception(\"Undefined input shape for requested input\")\n", + "\n", + " return folded_input_shape\n", + "\n", + " def get_folded_output_shape(self, ind=0):\n", + " mh = self.get_nodeattr(\"MH\")\n", + " pe = self.get_nodeattr(\"PE\")\n", + " nf = mh // pe\n", + " vecs = list(self.get_nodeattr(\"numInputVectors\"))\n", + " folded_output_shape = tuple(vecs + [nf, pe])\n", + " return folded_output_shape\n", + "\n", + " def get_normal_input_shape(self, ind=0):\n", + " mw = self.get_nodeattr(\"MW\")\n", + " vecs = list(self.get_nodeattr(\"numInputVectors\"))\n", + " normal_input_shape = tuple(vecs + [mw])\n", + " return normal_input_shape\n", + "\n", + " def get_normal_output_shape(self, ind=0):\n", + " mh = self.get_nodeattr(\"MH\")\n", + " vecs = list(self.get_nodeattr(\"numInputVectors\"))\n", + " normal_output_shape = tuple(vecs + [mh])\n", + " return normal_output_shape\n", + "\n", + " def get_number_output_values(self):\n", + " nf = np.prod(self.get_folded_output_shape()[:-1])\n", + " return nf\n", + "\n", + " def get_template_param_values(self):\n", + " \"\"\"Returns the template parameter values according to input, output and weight\n", + " data types.\"\"\"\n", + " ret = dict()\n", + " inp_hls_str = self.get_input_datatype().get_hls_datatype_str()\n", + " out_hls_str = self.get_output_datatype().get_hls_datatype_str()\n", + " inp_is_binary = self.get_input_datatype() == DataType[\"BINARY\"]\n", + " # out_is_binary = self.get_output_datatype() == DataType[\"BINARY\"]\n", + " wt_is_binary = self.get_weight_datatype() == DataType[\"BINARY\"]\n", + " bin_xnor_mode = self.get_nodeattr(\"binaryXnorMode\") == 1\n", + " if (inp_is_binary or wt_is_binary) and (not bin_xnor_mode):\n", + " raise Exception(\"True binary (non-bipolar) inputs not yet supported\")\n", + " inp_is_bipolar = self.get_input_datatype() == DataType[\"BIPOLAR\"]\n", + " # out_is_bipolar = self.get_output_datatype() == DataType[\"BIPOLAR\"]\n", + " wt_is_bipolar = self.get_weight_datatype() == DataType[\"BIPOLAR\"]\n", + " # reinterpret inp/wt as bipolar if bin_xnor_mode is iset\n", + " inp_is_bipolar = inp_is_bipolar or (inp_is_binary and bin_xnor_mode)\n", + " wt_is_bipolar = wt_is_bipolar or (wt_is_binary and bin_xnor_mode)\n", + " # fill in TSrcI and TWeightI\n", + " # TODO check these with Giulio\n", + " # TODO handle non-bipolar binary inputs\n", + " if inp_is_bipolar and wt_is_bipolar:\n", + " ret[\"TSrcI\"] = \"Recast\"\n", + " ret[\"TWeightI\"] = \"Identity\"\n", + " elif (not inp_is_bipolar) and wt_is_bipolar:\n", + " ret[\"TSrcI\"] = \"Slice<%s>\" % inp_hls_str\n", + " ret[\"TWeightI\"] = \"Recast\"\n", + " elif inp_is_bipolar and (not wt_is_bipolar):\n", + " ret[\"TSrcI\"] = \"Recast\"\n", + " ret[\"TWeightI\"] = \"Identity\"\n", + " elif (not inp_is_bipolar) and (not wt_is_bipolar):\n", + " ret[\"TSrcI\"] = \"Slice<%s>\" % inp_hls_str\n", + " ret[\"TWeightI\"] = \"Identity\"\n", + "\n", + " # fill in TDstI\n", + " ret[\"TDstI\"] = \"Slice<%s>\" % out_hls_str\n", + "\n", + " return ret\n", + "\n", + " def get_hls_compatible_weight_tensor(self, orig_weight_matrix):\n", + " \"\"\"Convert the original numpy weight matrix orig_weight_matrix into\n", + " a form suitable for passing to the hlslib call:\n", + " * ensure MH % PE == 0 and MW % SIMD == 0\n", + " * for bipolar {-1,+1} weights, convert to binary {0, 1}\n", + " * interleave rows between PEs\n", + " * reshape into (1, PE, WMEM, SIMD) and return\n", + " \"\"\"\n", + " mw = self.get_nodeattr(\"MW\")\n", + " mh = self.get_nodeattr(\"MH\")\n", + " pe = self.get_nodeattr(\"PE\")\n", + " simd = self.get_nodeattr(\"SIMD\")\n", + " wmem = self.calc_wmem()\n", + " assert orig_weight_matrix.shape == (\n", + " mw,\n", + " mh,\n", + " ), \"\"\"Weights matrix doesn't\n", + " have expected shape (mw, mh)\"\"\"\n", + " assert mw % simd == 0, \"Requirement MH divisable by SIMD is violated.\"\n", + " assert mh % pe == 0, \"Requirement MH divisable by PE is violated.\"\n", + " # start by transposing the original weight matrix, since ONNX and\n", + " # finn-hlslib use different assumptions\n", + " # ONNX uses (in_features, out_features) and matmul(x, W)\n", + " # finn-hlslib uses (out_features, in_features) and matmul(W, x)\n", + " ret = orig_weight_matrix.T\n", + " if self.get_weight_datatype() == DataType[\"BIPOLAR\"]:\n", + " # convert bipolar to binary\n", + " ret = (ret + 1) / 2\n", + " # interleave rows between PEs and reshape\n", + " # distribute rows between PEs\n", + " ret = interleave_matrix_outer_dim_from_partitions(ret, pe)\n", + " # create SIMD as innermost dimension and add a dummy outer dim\n", + " ret = ret.reshape(1, pe, wmem, simd)\n", + " # reverse the SIMD dimension\n", + " ret = np.flip(ret, axis=-1)\n", + " return ret\n", + "\n", + " def minimize_accumulator_width(self, model):\n", + " weights = model.get_initializer(self.onnx_node.input[1])\n", + " # since in the calculation the values of the weight matrix are used,\n", + " # for the bipolar case they need to be converted to bipolar\n", + " if self.get_nodeattr(\"binaryXnorMode\"):\n", + " weights = 2 * weights - 1\n", + " if len(self.onnx_node.input) > 2:\n", + " thresholds = model.get_initializer(self.onnx_node.input[2])\n", + " else:\n", + " thresholds = None\n", + " idt = self.get_input_datatype()\n", + " # calculate minimum and maximum values of accumulator\n", + " (acc_min, acc_max) = calculate_matvec_accumulator_range(weights, idt)\n", + " if thresholds is not None:\n", + " threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds)\n", + " # set threshold datatype (and accumulator datatype implicitly)\n", + " min_threshold = thresholds.min()\n", + " max_threshold = thresholds.max()\n", + " # clip threshold values\n", + " clip_upper = None\n", + " clip_lower = None\n", + " if max_threshold > acc_max + 1:\n", + " clip_upper = acc_max + 1\n", + " if min_threshold < acc_min:\n", + " clip_lower = acc_min\n", + " if (clip_lower is not None) or (clip_upper is not None):\n", + " warnings.warn(\"Clipping some thresholds in %s\" % self.onnx_node.name)\n", + " thresholds = np.clip(thresholds, clip_lower, clip_upper)\n", + " model.set_initializer(self.onnx_node.input[2], thresholds)\n", + " threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds)\n", + " min_threshold = thresholds.min()\n", + " max_threshold = thresholds.max()\n", + " # get range required by threshold values\n", + " tdt_min = min(acc_min, min_threshold)\n", + " tdt_max = max(acc_max, max_threshold)\n", + " if tdt_min < 0:\n", + " if abs(tdt_min) > tdt_max:\n", + " tdt = DataType.get_smallest_possible(tdt_min)\n", + " else:\n", + " tdt = DataType.get_smallest_possible(-tdt_max - 1)\n", + " else:\n", + " tdt = DataType.get_smallest_possible(tdt_max)\n", + " assert np.vectorize(tdt.allowed)(\n", + " threshold_tensor\n", + " ).all(), \"Thresholds in %s can't be expressed with type %s\" % (\n", + " self.onnx_node.name,\n", + " str(tdt),\n", + " )\n", + " self.set_nodeattr(\"accDataType\", tdt.name)\n", + " else:\n", + " if acc_min < 0:\n", + " if abs(acc_min) > acc_max:\n", + " adt = DataType.get_smallest_possible(acc_min)\n", + " else:\n", + " adt = DataType.get_smallest_possible(-acc_max - 1)\n", + " else:\n", + " adt = DataType.get_smallest_possible(acc_max)\n", + " # ensure a datatype divisible by 8-bits in case this is the last node\n", + " bw = roundup_to_integer_multiple(adt.bitwidth(), 8)\n", + " new_adt_name = adt.name.replace(str(adt.bitwidth()), str(bw))\n", + " adt = DataType[new_adt_name]\n", + " self.set_nodeattr(\"accDataType\", adt.name)\n", + " # for no-activation nodes, output dt = acc dt\n", + " self.set_nodeattr(\"outputDataType\", adt.name)\n", + " return DataType[self.get_nodeattr(\"accDataType\")]\n", + "\n", + " def get_hls_compatible_threshold_tensor(self, orig_thres_matrix):\n", + " \"\"\"Convert the original numpy weight matrix orig_weight_matrix into\n", + " a form suitable for passing to the hlslib call:\n", + " * ensure MH % PE == 0\n", + " * for bipolar weights&inputs, ensure thresholds are positive\n", + " * interleave rows between PEs\n", + " * reshape into (PE, TMEM, n_thres_steps) and return\n", + " \"\"\"\n", + " mh = self.get_nodeattr(\"MH\")\n", + " pe = self.get_nodeattr(\"PE\")\n", + " tmem = mh // pe\n", + " assert mh % pe == 0, \"Requirement MH divisable by PE is violated.\"\n", + " assert (\n", + " orig_thres_matrix.ndim == 2\n", + " ), \"\"\"Threshold matrix dimension is\n", + " not as expected (2).\"\"\"\n", + " n_thres_steps = orig_thres_matrix.shape[1]\n", + " inp_is_bipolar = self.get_input_datatype() == DataType[\"BIPOLAR\"]\n", + " wt_is_bipolar = self.get_weight_datatype() == DataType[\"BIPOLAR\"]\n", + " # reinterpret inp/wt as bipolar if bin_xnor_mode is iset\n", + " inp_is_binary = self.get_input_datatype() == DataType[\"BINARY\"]\n", + " wt_is_binary = self.get_weight_datatype() == DataType[\"BINARY\"]\n", + " bin_xnor_mode = self.get_nodeattr(\"binaryXnorMode\") == 1\n", + " inp_is_bipolar = inp_is_bipolar or (inp_is_binary and bin_xnor_mode)\n", + " wt_is_bipolar = wt_is_bipolar or (wt_is_binary and bin_xnor_mode)\n", + " if inp_is_bipolar and wt_is_bipolar:\n", + " # ensure all thresholds are nonnegative\n", + " assert (orig_thres_matrix >= 0).all()\n", + " # ensure all thresholds are integer\n", + " assert (orig_thres_matrix.astype(np.int32) == orig_thres_matrix).all()\n", + " ret = orig_thres_matrix\n", + " # workaround for vivado_hls threshold bug\n", + " if ret[0][0] == 0 and n_thres_steps == 1:\n", + " ret = np.copy(ret)\n", + " ret[0][0] = 1\n", + " warnings.warn(\n", + " \"Setting 0-valued first threshold to 1 to avoid vivado_hls bug\"\n", + " )\n", + " # ensure channels = mh , duplicating if necessary\n", + " if ret.shape[0] == 1:\n", + " ret = np.tile(ret, (mh, 1))\n", + " assert (\n", + " ret.shape[0] == mh\n", + " ), \"Channels of threshold matrix are not as expected (mh)\"\n", + " # distribute rows between PEs\n", + " ret = interleave_matrix_outer_dim_from_partitions(ret, pe)\n", + " assert (\n", + " ret.shape[0] == pe\n", + " ), \"\"\"First dimension after distribution of the\n", + " rows between PEs is not as expected (pe)\"\"\"\n", + " assert (\n", + " ret.shape[1] == tmem\n", + " ), \"\"\"Second dimension after distribution of the\n", + " rows between PEs is not as expected (tmem)\"\"\"\n", + " assert (\n", + " ret.shape[2] == n_thres_steps\n", + " ), \"\"\"Third dimension after distribution of the\n", + " rows between PEs is not as expected (n_thres_steps)\"\"\"\n", + " return ret.reshape(1, pe, tmem, n_thres_steps)\n", + "\n", + " def make_weight_file(self, weights, weight_file_mode, weight_file_name):\n", + " \"\"\"Produce a file containing given weights in appropriate format for this\n", + " layer. This file can be used for either synthesis or run-time reconfig\n", + " of weights.\n", + "\n", + " Arguments:\n", + "\n", + " * weights : numpy array with weights to be put into the file\n", + " * weight_file_mode : one of {hls_header, decoupled_verilog_dat,\n", + " decoupled_runtime}\n", + " * weight_file_name : filename for the weight file to be generated\n", + "\n", + " \"\"\"\n", + " # convert weights into hlslib-compatible format\n", + " weight_tensor = self.get_hls_compatible_weight_tensor(weights)\n", + " export_wdt = self.get_weight_datatype()\n", + " # we have converted bipolar weights to binary for export,\n", + " # so use it as such for weight generation\n", + " if self.get_weight_datatype() == DataType[\"BIPOLAR\"]:\n", + " export_wdt = DataType[\"BINARY\"]\n", + " if weight_file_mode == \"hls_header\":\n", + " weight_hls_code = numpy_to_hls_code(\n", + " weight_tensor, export_wdt, \"weights\", True, True\n", + " )\n", + " # write weights into C++ header file as dictated by finn-hlslib\n", + " f_weights = open(weight_file_name, \"w\")\n", + " if export_wdt.bitwidth() != 1:\n", + " f_weights.write(\n", + " \"const FixedPointWeights<{},{},{},{}> weights = \".format(\n", + " self.get_nodeattr(\"SIMD\"),\n", + " export_wdt.get_hls_datatype_str(),\n", + " self.get_nodeattr(\"PE\"),\n", + " self.calc_wmem(),\n", + " )\n", + " )\n", + " else:\n", + " f_weights.write(\n", + " \"const BinaryWeights<{},{},{}> weights = \".format(\n", + " self.get_nodeattr(\"SIMD\"),\n", + " self.get_nodeattr(\"PE\"),\n", + " self.calc_wmem(),\n", + " )\n", + " )\n", + " f_weights.write(weight_hls_code)\n", + " f_weights.close()\n", + " elif \"decoupled\" in weight_file_mode:\n", + " # create a weight stream for various flavors of decoupled mode:\n", + " # transpose weight tensor from (1, PE, WMEM, SIMD) to (1, WMEM, PE, SIMD)\n", + " weight_tensor_unflipped = np.transpose(weight_tensor, (0, 2, 1, 3))\n", + " # reverse SIMD flip for saving weights in .npy\n", + " weight_tensor_simd_flipped = np.flip(weight_tensor_unflipped, axis=-1)\n", + " # PE flip for saving weights in .dat\n", + " weight_tensor_pe_flipped = np.flip(weight_tensor_unflipped, axis=-2)\n", + " # reshape weight tensor (simd_flipped and pe_flipped) to desired shape\n", + " pe = self.get_nodeattr(\"PE\")\n", + " simd = self.get_nodeattr(\"SIMD\")\n", + " # simd_flipped\n", + " weight_tensor_simd_flipped = weight_tensor_simd_flipped.reshape(\n", + " 1, -1, pe * simd\n", + " )\n", + " weight_tensor_simd_flipped = weight_tensor_simd_flipped.copy()\n", + " # flipped\n", + " weight_tensor_pe_flipped = weight_tensor_pe_flipped.reshape(\n", + " 1, -1, pe * simd\n", + " )\n", + " weight_tensor_pe_flipped = weight_tensor_pe_flipped.copy()\n", + " if weight_file_mode == \"decoupled_npy\":\n", + " # save weight stream into npy for cppsim\n", + " np.save(weight_file_name, weight_tensor_simd_flipped)\n", + " elif weight_file_mode == \"decoupled_verilog_dat\":\n", + " # convert weight values into hexstring\n", + " weight_width = self.get_weightstream_width()\n", + " # pad to nearest 4 bits to get hex strings\n", + " weight_width_padded = roundup_to_integer_multiple(weight_width, 4)\n", + " weight_tensor_pe_flipped = pack_innermost_dim_as_hex_string(\n", + " weight_tensor_pe_flipped, export_wdt, weight_width_padded, prefix=\"\"\n", + " )\n", + " # add zeroes to pad out file to 1024 entries\n", + " weight_stream = weight_tensor_pe_flipped.flatten()\n", + " weight_stream = weight_stream.copy()\n", + " with open(weight_file_name, \"w\") as f:\n", + " for val in weight_stream:\n", + " f.write(val + \"\\n\")\n", + " elif weight_file_mode == \"decoupled_runtime\":\n", + " # memstream axi-lite interface will map each mem line to\n", + " # one or multiple 32-bit words\n", + " weight_width = self.get_weightstream_width()\n", + " words_per_memwidth = 2 ** math.ceil(math.log2(weight_width / 32))\n", + " if words_per_memwidth < 1:\n", + " words_per_memwidth = 1\n", + " weight_width_padded = words_per_memwidth * 32\n", + " # first, pack and ensure padding to 32 bits\n", + " weight_tensor_pe_flipped = pack_innermost_dim_as_hex_string(\n", + " weight_tensor_pe_flipped, export_wdt, weight_width_padded, prefix=\"\"\n", + " )\n", + " weight_stream = weight_tensor_pe_flipped.flatten()\n", + " weight_stream = weight_stream.copy()\n", + " with open(weight_file_name, \"w\") as f:\n", + " for val in weight_stream:\n", + " # split into groups of 8 hex digits (= 32 bits)\n", + " words_32b = textwrap.wrap(val, 8)\n", + " words_32b.reverse()\n", + " for word_32b in words_32b:\n", + " f.write(word_32b + \"\\n\")\n", + " else:\n", + " raise Exception(\"Unknown weight_file_mode\")\n", + "\n", + " else:\n", + " raise Exception(\"Unknown weight_file_mode\")\n", + "\n", + " def generate_params(self, model, path):\n", + " mem_mode = self.get_nodeattr(\"mem_mode\")\n", + " code_gen_dir = path\n", + " # weights, if not external\n", + " weights = model.get_initializer(self.onnx_node.input[1])\n", + " if mem_mode == \"const\":\n", + " # save hlslib-compatible weights in params.h\n", + " weight_filename = \"{}/params.h\".format(code_gen_dir)\n", + " self.make_weight_file(weights, \"hls_header\", weight_filename)\n", + " elif mem_mode == \"decoupled\" or mem_mode == \"external\":\n", + " weight_filename_sim = \"{}/weights.npy\".format(code_gen_dir)\n", + " # save decoupled weights for cppsim\n", + " self.make_weight_file(weights, \"decoupled_npy\", weight_filename_sim)\n", + " if mem_mode == \"decoupled\":\n", + " # also save weights as Verilog .dat file\n", + " # note that we provide two different .dat files, one for synth\n", + " # and one for synthesis. this is because URAM-based weights always\n", + " # need zero weights for synthesis, otherwise they get inferred\n", + " # as BRAM\n", + " weight_filename_rtl_synth = \"{}/memblock_synth_0.dat\".format(\n", + " code_gen_dir\n", + " )\n", + " weight_filename_rtl_sim = \"{}/memblock_sim_0.dat\".format(code_gen_dir)\n", + " # sim weights are always the true weights\n", + " self.make_weight_file(\n", + " weights, \"decoupled_verilog_dat\", weight_filename_rtl_sim\n", + " )\n", + " ram_style = self.get_nodeattr(\"ram_style\")\n", + " if ram_style == \"ultra\":\n", + " # UltraRAM must have no memory initializer, or only zeroes\n", + " # otherwise BRAM will be inferred instead of URAM\n", + " # as a workaround we provide a zero-weight init here\n", + " synth_weights = np.zeros_like(weights, dtype=np.float32)\n", + " else:\n", + " synth_weights = weights\n", + " self.make_weight_file(\n", + " synth_weights, \"decoupled_verilog_dat\", weight_filename_rtl_synth\n", + " )\n", + " else:\n", + " raise Exception(\n", + " \"\"\"Please set mem_mode to \"const\", \"decoupled\", or \"external\",\n", + " currently no other parameter value is supported!\"\"\"\n", + " )\n", + "\n", + " # save thresholds in thresh.h\n", + " if len(self.onnx_node.input) > 2:\n", + " thresholds = model.get_initializer(self.onnx_node.input[2])\n", + " if thresholds is not None:\n", + " threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds)\n", + " # use UINT32 threshold export for bipolar times bipolar\n", + " inp_is_bipolar = self.get_input_datatype() == DataType[\"BIPOLAR\"]\n", + " wt_is_bipolar = self.get_weight_datatype() == DataType[\"BIPOLAR\"]\n", + " # reinterpret inp/wt as bipolar if bin_xnor_mode is iset\n", + " inp_is_binary = self.get_input_datatype() == DataType[\"BINARY\"]\n", + " wt_is_binary = self.get_weight_datatype() == DataType[\"BINARY\"]\n", + " bin_xnor_mode = self.get_nodeattr(\"binaryXnorMode\") == 1\n", + " inp_is_bipolar = inp_is_bipolar or (inp_is_binary and bin_xnor_mode)\n", + " wt_is_bipolar = wt_is_bipolar or (wt_is_binary and bin_xnor_mode)\n", + " # get computed threshold datatype from attribute\n", + " tdt = DataType[self.get_nodeattr(\"accDataType\")]\n", + "\n", + " assert np.vectorize(tdt.allowed)(\n", + " threshold_tensor\n", + " ).all(), \"Thresholds in %s can't be expressed with type %s\" % (\n", + " self.onnx_node.name,\n", + " str(tdt),\n", + " )\n", + " thresholds_hls_code = numpy_to_hls_code(\n", + " threshold_tensor, tdt, \"thresholds\", False, True\n", + " )\n", + " # write thresholds into thresh.h\n", + " f_thresh = open(\"{}/thresh.h\".format(code_gen_dir), \"w\")\n", + " tdt_hls = tdt.get_hls_datatype_str()\n", + " # use binary to export bipolar activations\n", + " export_odt = self.get_output_datatype()\n", + " if self.get_output_datatype() == DataType[\"BIPOLAR\"]:\n", + " export_odt = DataType[\"BINARY\"]\n", + " odt_hls = export_odt.get_hls_datatype_str()\n", + " f_thresh.write(\n", + " \"static ThresholdsActivation<{},{},{},{},{},{},{}> threshs \\\n", + " = \".format(\n", + " self.calc_tmem(),\n", + " self.get_nodeattr(\"PE\"),\n", + " threshold_tensor.shape[-1],\n", + " tdt_hls,\n", + " odt_hls,\n", + " self.get_nodeattr(\"ActVal\"),\n", + " \"comp::less_equal<%s, %s>\" % (tdt_hls, tdt_hls),\n", + " )\n", + " )\n", + " f_thresh.write(thresholds_hls_code)\n", + " f_thresh.close()\n", + "\n", + " def execute_node(self, context, graph):\n", + " mode = self.get_nodeattr(\"exec_mode\")\n", + " mem_mode = self.get_nodeattr(\"mem_mode\")\n", + " node = self.onnx_node\n", + "\n", + " # TODO ensure codegen dir exists\n", + " if mode == \"cppsim\":\n", + " code_gen_dir = self.get_nodeattr(\"code_gen_dir_cppsim\")\n", + " elif mode == \"rtlsim\":\n", + " code_gen_dir = self.get_nodeattr(\"code_gen_dir_ipgen\")\n", + " else:\n", + " raise Exception(\n", + " \"\"\"Invalid value for attribute exec_mode! Is currently set to: {}\n", + " has to be set to one of the following value (\"cppsim\", \"rtlsim\")\"\"\".format(\n", + " mode\n", + " )\n", + " )\n", + "\n", + " # create a npy file fore each input of the node (in_ind is input index)\n", + " in_ind = 0\n", + " for inputs in node.input:\n", + " # it is assumed that the first input of the node is the data input\n", + " # the second input are the weights\n", + " # the third input are the thresholds\n", + " if in_ind == 0:\n", + " assert (\n", + " str(context[inputs].dtype) == \"float32\"\n", + " ), \"\"\"Input datatype is\n", + " not float32 as expected.\"\"\"\n", + " expected_inp_shape = self.get_folded_input_shape()\n", + " reshaped_input = context[inputs].reshape(expected_inp_shape)\n", + " if self.get_input_datatype() == DataType[\"BIPOLAR\"]:\n", + " # store bipolar activations as binary\n", + " reshaped_input = (reshaped_input + 1) / 2\n", + " export_idt = DataType[\"BINARY\"]\n", + " else:\n", + " export_idt = self.get_input_datatype()\n", + " # make copy before saving the array\n", + " reshaped_input = reshaped_input.copy()\n", + " np.save(\n", + " os.path.join(code_gen_dir, \"input_{}.npy\".format(in_ind)),\n", + " reshaped_input,\n", + " )\n", + " elif in_ind > 2:\n", + " raise Exception(\"Unexpected input found for MatrixVectorActivation\")\n", + " in_ind += 1\n", + "\n", + " if mode == \"cppsim\":\n", + " # execute the precompiled model\n", + " super().exec_precompiled_singlenode_model()\n", + " # load output npy file\n", + " super().npy_to_dynamic_output(context)\n", + " # reinterpret binary output as bipolar where needed\n", + " if self.get_output_datatype() == DataType[\"BIPOLAR\"]:\n", + " out = context[node.output[0]]\n", + " out = 2 * out - 1\n", + " context[node.output[0]] = out\n", + " assert (\n", + " context[node.output[0]].shape == self.get_normal_output_shape()\n", + " ), \"cppsim did not produce expected output shape\"\n", + " elif mode == \"rtlsim\":\n", + " sim = self.get_rtlsim()\n", + " nbits = self.get_instream_width()\n", + " inp = npy_to_rtlsim_input(\n", + " \"{}/input_0.npy\".format(code_gen_dir), export_idt, nbits\n", + " )\n", + " super().reset_rtlsim(sim)\n", + " super().toggle_clk(sim)\n", + " if mem_mode == \"external\" or mem_mode == \"decoupled\":\n", + " wnbits = self.get_weightstream_width()\n", + " export_wdt = self.get_weight_datatype()\n", + " # we have converted bipolar weights to binary for export,\n", + " # so use it as such for weight generation\n", + " if self.get_weight_datatype() == DataType[\"BIPOLAR\"]:\n", + " export_wdt = DataType[\"BINARY\"]\n", + " wei = npy_to_rtlsim_input(\n", + " \"{}/weights.npy\".format(code_gen_dir), export_wdt, wnbits\n", + " )\n", + " num_w_reps = np.prod(self.get_nodeattr(\"numInputVectors\"))\n", + " io_dict = {\n", + " \"inputs\": {\"in0\": inp, \"weights\": wei * num_w_reps},\n", + " \"outputs\": {\"out\": []},\n", + " }\n", + " self.rtlsim_multi_io(sim, io_dict)\n", + " output = io_dict[\"outputs\"][\"out\"]\n", + " else:\n", + " output = self.rtlsim(sim, inp)\n", + " odt = self.get_output_datatype()\n", + " target_bits = odt.bitwidth()\n", + " packed_bits = self.get_outstream_width()\n", + " out_npy_path = \"{}/output.npy\".format(code_gen_dir)\n", + " out_shape = self.get_folded_output_shape()\n", + " rtlsim_output_to_npy(\n", + " output, out_npy_path, odt, out_shape, packed_bits, target_bits\n", + " )\n", + "\n", + " # load and reshape output\n", + " output = np.load(out_npy_path)\n", + " oshape = self.get_normal_output_shape()\n", + " output = np.asarray([output], dtype=np.float32).reshape(*oshape)\n", + " context[node.output[0]] = output\n", + " else:\n", + " raise Exception(\n", + " \"\"\"Invalid value for attribute exec_mode! Is currently set to: {}\n", + " has to be set to one of the following value (\"cppsim\", \"rtlsim\")\"\"\".format(\n", + " mode\n", + " )\n", + " )\n", + "\n", + " def global_includes(self):\n", + " self.code_gen_dict[\"$GLOBALS$\"] = ['#include \"weights.hpp\"']\n", + " self.code_gen_dict[\"$GLOBALS$\"] += ['#include \"activations.hpp\"']\n", + "\n", + " mem_mode = self.get_nodeattr(\"mem_mode\")\n", + " if mem_mode not in [\"const\", \"decoupled\", \"external\"]:\n", + " raise Exception(\n", + " \"\"\"Please set mem_mode to \"const\", \"decoupled\", or \"external\",\n", + " currently no other parameter value is supported!\"\"\"\n", + " )\n", + " self.code_gen_dict[\"$GLOBALS$\"] += ['#include \"mvau.hpp\"']\n", + " if self.calc_tmem() != 0:\n", + " # TODO find a better way of checking for no pregenerated thresholds\n", + " self.code_gen_dict[\"$GLOBALS$\"] += ['#include \"thresh.h\"']\n", + "\n", + " def defines(self, var):\n", + " # Only ipgen mode: Make sure that SIMD parameter satisfies minimum requirements.\n", + " if var == \"ipgen\":\n", + " SIMD = self.get_nodeattr(\"SIMD\")\n", + " MW = self.get_nodeattr(\"MW\")\n", + " condition = SIMD >= (MW / 1024)\n", + " msg = (\n", + " f\"HLS synthesis of MatrixVectorActivation requires: \"\n", + " f\"SIMD >= MW / 1024. This is not fulfilled with: SIMD={SIMD} \"\n", + " f\"and MW={MW} for node: {self.onnx_node.name}.\"\n", + " )\n", + " assert condition, msg\n", + " mem_mode = self.get_nodeattr(\"mem_mode\")\n", + " numInputVectors = list(self.get_nodeattr(\"numInputVectors\"))\n", + " numReps = np.prod(numInputVectors)\n", + " self.code_gen_dict[\"$DEFINES$\"] = [\n", + " \"\"\"#define MW1 {}\\n #define MH1 {}\\n\n", + " #define SIMD1 {}\\n #define PE1 {}\\n #define WMEM1 {}\\n\n", + " #define TMEM1 {}\\n #define numReps {}\"\"\".format(\n", + " self.get_nodeattr(\"MW\"),\n", + " self.get_nodeattr(\"MH\"),\n", + " self.get_nodeattr(\"SIMD\"),\n", + " self.get_nodeattr(\"PE\"),\n", + " self.calc_wmem(),\n", + " self.calc_tmem(),\n", + " numReps,\n", + " )\n", + " ]\n", + " if mem_mode == \"decoupled\" or mem_mode == \"external\":\n", + " wdt = self.get_weight_datatype()\n", + " self.code_gen_dict[\"$DEFINES$\"].append(\n", + " \"#define WP1 {}\\n\".format(wdt.bitwidth())\n", + " )\n", + "\n", + " def read_npy_data(self):\n", + " code_gen_dir = self.get_nodeattr(\"code_gen_dir_cppsim\")\n", + " dtype = self.get_input_datatype()\n", + " if dtype == DataType[\"BIPOLAR\"]:\n", + " # use binary for bipolar storage\n", + " dtype = DataType[\"BINARY\"]\n", + " elem_bits = dtype.bitwidth()\n", + " packed_bits = self.get_instream_width()\n", + " packed_hls_type = \"ap_uint<%d>\" % packed_bits\n", + " elem_hls_type = dtype.get_hls_datatype_str()\n", + " npy_type = \"float\"\n", + " npy_in = \"%s/input_0.npy\" % code_gen_dir\n", + " self.code_gen_dict[\"$READNPYDATA$\"] = []\n", + " # note: the innermost dim is reversed for the input\n", + " self.code_gen_dict[\"$READNPYDATA$\"].append(\n", + " 'npy2apintstream<%s, %s, %d, %s>(\"%s\", in0, false);'\n", + " % (packed_hls_type, elem_hls_type, elem_bits, npy_type, npy_in)\n", + " )\n", + "\n", + " mem_mode = self.get_nodeattr(\"mem_mode\")\n", + " if mem_mode == \"decoupled\" or mem_mode == \"external\":\n", + " wdt = self.get_weight_datatype()\n", + " elem_bits = wdt.bitwidth()\n", + " packed_bits = self.get_weightstream_width()\n", + " packed_hls_type = \"ap_uint<%d>\" % packed_bits\n", + " elem_hls_type = wdt.get_hls_datatype_str()\n", + " npy_type = \"float\"\n", + " npy_in = \"%s/weights.npy\" % code_gen_dir\n", + "\n", + " self.code_gen_dict[\"$READNPYDATA$\"].append(\n", + " 'npy2apintstream<%s, %s, %d, %s>(\"%s\", weights, false, numReps);'\n", + " % (packed_hls_type, elem_hls_type, elem_bits, npy_type, npy_in)\n", + " )\n", + "\n", + " def strm_decl(self):\n", + " mem_mode = self.get_nodeattr(\"mem_mode\")\n", + " self.code_gen_dict[\"$STREAMDECLARATIONS$\"] = []\n", + " self.code_gen_dict[\"$STREAMDECLARATIONS$\"].append(\n", + " 'hls::stream> in0 (\"in0\");'.format(self.get_instream_width())\n", + " )\n", + " self.code_gen_dict[\"$STREAMDECLARATIONS$\"].append(\n", + " 'hls::stream> out (\"out\");'.format(self.get_outstream_width())\n", + " )\n", + "\n", + " if mem_mode == \"decoupled\" or mem_mode == \"external\":\n", + " self.code_gen_dict[\"$STREAMDECLARATIONS$\"].append(\n", + " 'hls::stream> weights (\"weights\");'.format(\n", + " self.get_weightstream_width()\n", + " )\n", + " )\n", + "\n", + " def docompute(self):\n", + " mem_mode = self.get_nodeattr(\"mem_mode\")\n", + " map_to_hls_mult_style = {\n", + " \"auto\": \"ap_resource_dflt()\",\n", + " \"lut\": \"ap_resource_lut()\",\n", + " \"dsp\": \"ap_resource_dsp()\",\n", + " }\n", + " tmpl_args = self.get_template_param_values()\n", + " if self.calc_tmem() == 0:\n", + " odtype_hls_str = self.get_output_datatype().get_hls_datatype_str()\n", + " threshs = \"PassThroughActivation<%s>()\" % odtype_hls_str\n", + " else:\n", + " threshs = \"threshs\"\n", + " if mem_mode == \"const\":\n", + " self.code_gen_dict[\"$DOCOMPUTE$\"] = [\n", + " \"\"\"Matrix_Vector_Activate_Batch\n", + " (in0, out, weights, {}, numReps, {});\"\"\".format(\n", + " tmpl_args[\"TSrcI\"],\n", + " tmpl_args[\"TDstI\"],\n", + " tmpl_args[\"TWeightI\"],\n", + " threshs,\n", + " map_to_hls_mult_style[self.get_nodeattr(\"resType\")],\n", + " )\n", + " ]\n", + " elif mem_mode == \"decoupled\" or mem_mode == \"external\":\n", + " wdt = self.get_weight_datatype()\n", + " if wdt == DataType[\"BIPOLAR\"]:\n", + " export_wdt = DataType[\"BINARY\"]\n", + " else:\n", + " export_wdt = wdt\n", + " wdtype_hls_str = export_wdt.get_hls_datatype_str()\n", + " self.code_gen_dict[\"$DOCOMPUTE$\"] = [\n", + " \"\"\"Matrix_Vector_Activate_Stream_Batch\n", + " (in0, out, weights, {}, numReps, {});\"\"\".format(\n", + " tmpl_args[\"TSrcI\"],\n", + " tmpl_args[\"TDstI\"],\n", + " tmpl_args[\"TWeightI\"],\n", + " wdtype_hls_str,\n", + " threshs,\n", + " map_to_hls_mult_style[self.get_nodeattr(\"resType\")],\n", + " )\n", + " ]\n", + "\n", + " else:\n", + " raise Exception(\n", + " \"\"\"Please set mem_mode to \"const\", \"decoupled\", or \"external\",\n", + " currently no other parameter value is supported!\"\"\"\n", + " )\n", + "\n", + " def dataoutstrm(self):\n", + " code_gen_dir = self.get_nodeattr(\"code_gen_dir_cppsim\")\n", + " dtype = self.get_output_datatype()\n", + " if dtype == DataType[\"BIPOLAR\"]:\n", + " # use binary for bipolar storage\n", + " dtype = DataType[\"BINARY\"]\n", + " elem_bits = dtype.bitwidth()\n", + " packed_bits = self.get_outstream_width()\n", + " packed_hls_type = \"ap_uint<%d>\" % packed_bits\n", + " elem_hls_type = dtype.get_hls_datatype_str()\n", + " npy_type = \"float\"\n", + " npy_out = \"%s/output.npy\" % code_gen_dir\n", + " shape = self.get_folded_output_shape()\n", + " shape_cpp_str = str(shape).replace(\"(\", \"{\").replace(\")\", \"}\")\n", + "\n", + " # note: the innermost dim is not reversed for the output\n", + " self.code_gen_dict[\"$DATAOUTSTREAM$\"] = [\n", + " 'apintstream2npy<%s, %s, %d, %s>(out, %s, \"%s\", false);'\n", + " % (\n", + " packed_hls_type,\n", + " elem_hls_type,\n", + " elem_bits,\n", + " npy_type,\n", + " shape_cpp_str,\n", + " npy_out,\n", + " )\n", + " ]\n", + "\n", + " def save_as_npy(self):\n", + " self.code_gen_dict[\"$SAVEASCNPY$\"] = []\n", + "\n", + " def blackboxfunction(self):\n", + " mem_mode = self.get_nodeattr(\"mem_mode\")\n", + " if mem_mode == \"const\":\n", + " self.code_gen_dict[\"$BLACKBOXFUNCTION$\"] = [\n", + " \"\"\"void {}(hls::stream> &in0,\n", + " hls::stream> &out\n", + " )\"\"\".format(\n", + " self.onnx_node.name,\n", + " self.get_instream_width(),\n", + " self.get_outstream_width(),\n", + " )\n", + " ]\n", + " elif mem_mode == \"decoupled\" or mem_mode == \"external\":\n", + " self.code_gen_dict[\"$BLACKBOXFUNCTION$\"] = [\n", + " \"\"\"void {}(\n", + " hls::stream> &in0,\n", + " hls::stream> &weights,\n", + " hls::stream> &out\n", + " )\"\"\".format(\n", + " self.onnx_node.name,\n", + " self.get_instream_width(),\n", + " self.get_weightstream_width(),\n", + " self.get_outstream_width(),\n", + " )\n", + " ]\n", + "\n", + " else:\n", + " raise Exception(\n", + " \"\"\"Please set mem_mode to \"const\" or \"decoupled\", currently no other\n", + " parameter value is supported!\"\"\"\n", + " )\n", + "\n", + " def pragmas(self):\n", + " mem_mode = self.get_nodeattr(\"mem_mode\")\n", + " ram_style_thresholds = self.get_nodeattr(\"ram_style_thresholds\")\n", + " self.code_gen_dict[\"$PRAGMAS$\"] = [\n", + " \"#pragma HLS INTERFACE axis port=in0 name=in0_\" + self.hls_sname()\n", + " ]\n", + " self.code_gen_dict[\"$PRAGMAS$\"].append(\n", + " \"#pragma HLS INTERFACE axis port=out name=out_\" + self.hls_sname()\n", + " )\n", + " self.code_gen_dict[\"$PRAGMAS$\"].append(\n", + " \"#pragma HLS INTERFACE ap_ctrl_none port=return\"\n", + " )\n", + "\n", + " if mem_mode == \"const\":\n", + " self.code_gen_dict[\"$PRAGMAS$\"].append('#include \"params.h\"')\n", + " # the weight tensor is ap_uint [PE][WMEM]\n", + " # partition for parallel access along the PE dimension (dim 1)\n", + " self.code_gen_dict[\"$PRAGMAS$\"].append(\n", + " (\n", + " \"#pragma HLS ARRAY_PARTITION variable=weights.m_weights \"\n", + " \"complete dim=1\"\n", + " )\n", + " )\n", + " elif mem_mode == \"decoupled\" or mem_mode == \"external\":\n", + " self.code_gen_dict[\"$PRAGMAS$\"].append(\n", + " \"#pragma HLS INTERFACE axis port=weights name=weights_\"\n", + " + self.hls_sname()\n", + " )\n", + " self.code_gen_dict[\"$PRAGMAS$\"].append(\n", + " \"#pragma HLS stream depth=8 variable=weights\"\n", + " )\n", + "\n", + " else:\n", + " raise Exception(\n", + " \"\"\"Please set mem_mode to \"const\", \"decoupled\", or external,\n", + " currently no other parameter value is supported!\"\"\"\n", + " )\n", + "\n", + " # the threshold tensor is acc_type [PE][TMEM][N_THRES]\n", + " # partition for parallel access along PE and N_THRES\n", + " # dimensions (dims 1 and 3)\n", + " if self.calc_tmem() != 0:\n", + " # TODO find a better way of checking for no pregenerated thresholds\n", + " self.code_gen_dict[\"$PRAGMAS$\"].append(\n", + " (\n", + " \"#pragma HLS ARRAY_PARTITION variable=threshs.m_thresholds \"\n", + " \"complete dim=1\"\n", + " )\n", + " )\n", + " self.code_gen_dict[\"$PRAGMAS$\"].append(\n", + " (\n", + " \"#pragma HLS ARRAY_PARTITION variable=threshs.m_thresholds \"\n", + " \"complete dim=3\"\n", + " )\n", + " )\n", + " # add resource pragma for thresholds if set\n", + " if ram_style_thresholds == \"distributed\":\n", + " self.code_gen_dict[\"$PRAGMAS$\"].append(\n", + " (\n", + " \"#pragma HLS RESOURCE variable=threshs.m_thresholds \"\n", + " \"core=ROM_2P_LUTRAM\"\n", + " )\n", + " )\n", + " elif ram_style_thresholds == \"block\":\n", + " self.code_gen_dict[\"$PRAGMAS$\"].append(\n", + " (\n", + " \"#pragma HLS RESOURCE variable=threshs.m_thresholds \"\n", + " \"core=ROM_2P_BRAM\"\n", + " )\n", + " )\n", + " elif ram_style_thresholds == \"auto\":\n", + " # no pragma needed\n", + " pass\n", + " else:\n", + " raise Exception(\n", + " \"Unrecognized ram_style_thresholds value:\" + ram_style_thresholds\n", + " )\n", + "\n", + " def code_generation_ipi(self):\n", + " cmd = []\n", + " # add streamer if needed\n", + " mem_mode = self.get_nodeattr(\"mem_mode\")\n", + " if mem_mode == \"decoupled\":\n", + " runtime_writable = self.get_nodeattr(\"runtime_writeable_weights\") == 1\n", + " if self.get_nodeattr(\"ram_style\") == \"ultra\":\n", + " assert (\n", + " runtime_writable == 1\n", + " ), \"Layer with URAM weights must have runtime_writeable_weights=1\"\n", + " node_name = self.onnx_node.name\n", + " sname = self.hls_sname()\n", + " # create a hierarchy for this layer, with the same port names\n", + " clk_name = self.get_verilog_top_module_intf_names()[\"clk\"][0]\n", + " rst_name = self.get_verilog_top_module_intf_names()[\"rst\"][0]\n", + " dout_name = self.get_verilog_top_module_intf_names()[\"m_axis\"][0][0]\n", + " din_name = self.get_verilog_top_module_intf_names()[\"s_axis\"][0][0]\n", + " cmd.append(\"create_bd_cell -type hier %s\" % node_name)\n", + " cmd.append(\"create_bd_pin -dir I -type clk /%s/%s\" % (node_name, clk_name))\n", + " cmd.append(\"create_bd_pin -dir I -type rst /%s/%s\" % (node_name, rst_name))\n", + " cmd.append(\n", + " \"create_bd_intf_pin -mode Master \"\n", + " \"-vlnv xilinx.com:interface:axis_rtl:1.0 /%s/%s\"\n", + " % (node_name, dout_name)\n", + " )\n", + " cmd.append(\n", + " \"create_bd_intf_pin -mode Slave \"\n", + " \"-vlnv xilinx.com:interface:axis_rtl:1.0 /%s/%s\" % (node_name, din_name)\n", + " )\n", + " # instantiate the hls ip\n", + " cmd.append(\n", + " \"create_bd_cell -type ip -vlnv %s /%s/%s\"\n", + " % (self.get_nodeattr(\"ip_vlnv\"), node_name, node_name)\n", + " )\n", + " # instantiate a streamer and connect it to the HLS IP\n", + " strm_vlnv = \"xilinx.com:user:memstream:1.0\"\n", + " strm_inst = node_name + \"_wstrm\"\n", + " cmd.append(\n", + " \"create_bd_cell -type ip -vlnv %s /%s/%s\"\n", + " % (strm_vlnv, node_name, strm_inst)\n", + " )\n", + " cmd.append(\n", + " \"set_property -dict [list \"\n", + " \"CONFIG.NSTREAMS {1} \"\n", + " \"CONFIG.MEM_DEPTH {%d} \"\n", + " \"CONFIG.MEM_WIDTH {%d} \"\n", + " \"CONFIG.MEM_INIT {%s} \"\n", + " \"CONFIG.RAM_STYLE {%s} \"\n", + " \"CONFIG.STRM0_DEPTH {%d} \"\n", + " \"CONFIG.STRM0_WIDTH {%d} \"\n", + " \"CONFIG.STRM0_OFFSET {0} \"\n", + " \"] [get_bd_cells /%s/%s]\"\n", + " % (\n", + " self.calc_wmem(),\n", + " self.get_weightstream_width_padded(),\n", + " self.get_nodeattr(\"code_gen_dir_ipgen\") + \"/\",\n", + " self.get_nodeattr(\"ram_style\"),\n", + " self.calc_wmem(),\n", + " self.get_weightstream_width_padded(),\n", + " node_name,\n", + " strm_inst,\n", + " )\n", + " )\n", + " cmd.append(\n", + " \"connect_bd_intf_net [get_bd_intf_pins %s/%s/m_axis_0] \"\n", + " \"[get_bd_intf_pins %s/%s/weights_%s]\"\n", + " % (node_name, strm_inst, node_name, node_name, sname)\n", + " )\n", + " cmd.append(\n", + " \"connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/aresetn]\"\n", + " % (node_name, rst_name, node_name, strm_inst)\n", + " )\n", + " cmd.append(\n", + " \"connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/aclk]\"\n", + " % (node_name, clk_name, node_name, strm_inst)\n", + " )\n", + " cmd.append(\n", + " \"connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/%s]\"\n", + " % (node_name, rst_name, node_name, node_name, rst_name)\n", + " )\n", + " cmd.append(\n", + " \"connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/%s]\"\n", + " % (node_name, clk_name, node_name, node_name, clk_name)\n", + " )\n", + " cmd.append(\n", + " \"connect_bd_intf_net [get_bd_intf_pins %s/%s] \"\n", + " \"[get_bd_intf_pins %s/%s/%s]\"\n", + " % (node_name, din_name, node_name, node_name, din_name)\n", + " )\n", + " cmd.append(\n", + " \"connect_bd_intf_net [get_bd_intf_pins %s/%s] \"\n", + " \"[get_bd_intf_pins %s/%s/%s]\"\n", + " % (node_name, dout_name, node_name, node_name, dout_name)\n", + " )\n", + " if runtime_writable:\n", + " # expose axi lite interface for writeable weights\n", + " axilite_name = self.get_verilog_top_module_intf_names()[\"axilite\"][0]\n", + " cmd.append(\n", + " \"create_bd_intf_pin -mode Slave \"\n", + " \"-vlnv xilinx.com:interface:aximm_rtl:1.0 /%s/%s\"\n", + " % (node_name, axilite_name)\n", + " )\n", + " cmd.append(\n", + " \"connect_bd_intf_net [get_bd_intf_pins %s/%s] \"\n", + " \"[get_bd_intf_pins %s/%s/%s]\"\n", + " % (node_name, axilite_name, node_name, strm_inst, axilite_name)\n", + " )\n", + " # TODO calculate and pass in segment size here\n", + " cmd.append(\"assign_bd_address\")\n", + " cmd.append(\"save_bd_design\")\n", + " elif mem_mode == \"const\" or mem_mode == \"external\":\n", + " # base class impl sufficient for const/external modes\n", + " return super().code_generation_ipi()\n", + " else:\n", + " raise Exception(\"Unrecognized mem_mode for MatrixVectorActivation\")\n", + " return cmd\n", + "\n", + " def get_verilog_top_module_intf_names(self):\n", + " intf_names = super().get_verilog_top_module_intf_names()\n", + " mem_mode = self.get_nodeattr(\"mem_mode\")\n", + " sname = self.hls_sname()\n", + " if mem_mode == \"external\":\n", + " intf_names[\"s_axis\"].append(\n", + " (\"weights_\" + sname, self.get_weightstream_width_padded())\n", + " )\n", + " if mem_mode == \"decoupled\":\n", + " # only expose axilite interface if attribute is set\n", + " runtime_writable = self.get_nodeattr(\"runtime_writeable_weights\") == 1\n", + " if runtime_writable:\n", + " intf_names[\"axilite\"] = [\"s_axilite\"]\n", + " return intf_names\n", + "\n", + " def get_op_and_param_counts(self):\n", + " in_features = self.get_nodeattr(\"MW\")\n", + " out_features = self.get_nodeattr(\"MH\")\n", + " weight_bits = self.get_weight_datatype().bitwidth()\n", + " inp_bits = self.get_input_datatype().bitwidth()\n", + " num_inp_vec = self.get_nodeattr(\"numInputVectors\")\n", + " num_repetitions = int(np.prod(num_inp_vec))\n", + " mac_count = in_features * out_features * num_repetitions\n", + " # cannonicalize op type: highest bitwidth operand first s.t.\n", + " # e.g. mac_8bx4b and mac_4bx8b don't appear as two different op types\n", + " bw1 = min(inp_bits, weight_bits)\n", + " bw2 = max(inp_bits, weight_bits)\n", + " mac_op_type = \"op_mac_%dbx%db\" % (bw1, bw2)\n", + " weight_param_type = \"param_weight_%db\" % (weight_bits)\n", + " weight_count = in_features * out_features\n", + " ret_dict = {mac_op_type: mac_count, weight_param_type: weight_count}\n", + " if self.get_nodeattr(\"noActivation\") == 0:\n", + " tdt = DataType[self.get_nodeattr(\"accDataType\")]\n", + " thres_bits = tdt.bitwidth()\n", + " thres_param_type = \"param_threshold_%db\" % (thres_bits)\n", + " thres_count = out_features\n", + " ret_dict[thres_param_type] = thres_count\n", + " return ret_dict\n", + "\n", + " def derive_characteristic_fxns(self, period):\n", + " n_inps = np.prod(self.get_folded_input_shape()[:-1])\n", + " io_dict = {\n", + " \"inputs\": {\n", + " \"in0\": [0 for i in range(n_inps)],\n", + " },\n", + " \"outputs\": {\"out\": []},\n", + " }\n", + " mem_mode = self.get_nodeattr(\"mem_mode\")\n", + " if mem_mode in [\"decoupled\", \"external\"]:\n", + " n_weight_inps = self.calc_wmem()\n", + " num_w_reps = np.prod(self.get_nodeattr(\"numInputVectors\"))\n", + " io_dict[\"inputs\"][\"weights\"] = [\n", + " 0 for i in range(num_w_reps * n_weight_inps)\n", + " ]\n", + " super().derive_characteristic_fxns(period, override_rtlsim_dict=io_dict)\n", + "\n" + ] + } + ], + "source": [ + "#To view the source code of the matrix vector activation function\n", + "from finn.custom_op.fpgadataflow.matrixvectoractivation import MatrixVectorActivation\n", + "showSrc(MatrixVectorActivation)" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "## Modify Parameters\n", + "\n", + "We now modify the parallelization attributes of the first network layer to reduce its overall latency." + ] + }, + { + "cell_type": "code", + "execution_count": 14, + "metadata": {}, + "outputs": [], + "source": [ + "fc_layers = model.get_nodes_by_op_type(\"MatrixVectorActivation\") \n", + "# (PE, SIMD, in_fifo_depth, out_fifo_depth, ramstyle) for each layer\n", + "config = [\n", + " (2, 5, [16], [64], \"block\"),\n", + " (1, 1, [64], [64], \"auto\"),#8,8\n", + " (1, 1, [64], [64], \"auto\"),#8,8\n", + " (1, 1, [64], [1], \"distributed\"),\n", + "]\n", + "for fcl, (pe, simd, ififo, ofifo, ramstyle) in zip(fc_layers, config):\n", + " fcl_inst = getCustomOp(fcl)\n", + " fcl_inst.set_nodeattr(\"PE\", pe)\n", + " fcl_inst.set_nodeattr(\"SIMD\", simd)\n", + " fcl_inst.set_nodeattr(\"inFIFODepths\", ififo)\n", + " fcl_inst.set_nodeattr(\"outFIFODepths\", ofifo)\n", + " fcl_inst.set_nodeattr(\"ram_style\", ramstyle)\n", + " num_inp_vec = fcl_inst.get_nodeattr(\"numInputVectors\")" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "We again save the model and view it. On expanding the first `MatrixVectorActivation` we can view the updated `PE` & `SIMD` parameters for that layer." + ] + }, + { + "cell_type": "code", + "execution_count": 16, + "metadata": { + "scrolled": true + }, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "Stopping http://0.0.0.0:5901\n", + "Serving './cybsec_PE_SIMD_modified.onnx' at http://0.0.0.0:5901\n" + ] + }, + { + "data": { + "text/html": [ + "\n", + " \n", + " " + ], + "text/plain": [ + "" + ] + }, + "execution_count": 16, + "metadata": {}, + "output_type": "execute_result" + } + ], + "source": [ + "model.save(\"./cybsec_PE_SIMD_modified.onnx\")\n", + "showInNetron(\"./cybsec_PE_SIMD_modified.onnx\",localhost_url='xirxlabs53')" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "From the above total folding formula, we have reduced the total folding of our layer from `600 x 64` to `120 x 32`. Hence, resulting in an estimated `10x` decrease in the execution latency of our layer. \n", + "This can be observed in the new estimated clock cycles." + ] + }, + { + "cell_type": "code", + "execution_count": 17, + "metadata": { + "scrolled": true + }, + "outputs": [], + "source": [ + "cycles_dict_updated = []\n", + "cycles_dict_updated = exp_cycles_per_layer(model)" + ] + }, + { + "cell_type": "code", + "execution_count": 18, + "metadata": {}, + "outputs": [ + { + "data": { + "image/png": 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xYsWsayFzuqyr7d27V8YYvfLKK3rllVey7XPs2DFVrFhR48aNU+fOnXXPPfeodu3aateunXr27Kk6derkap3S5ZuYnDt37pqfQUZGhg4dOqRatWpZ7dndsTU7e/bs0c6dO2/43ZNy9j3ft2+fJOXoexAYGJgl0JUqVUpbtmzJUe1Xj9nM+U+dOiXp8n5LSkrSJ598ok8++STbZVy5fdfSvHlz63ThNWvWqEKFCqpfv77q1q2rNWvW6KGHHtLatWv1+OOPW/P88ccfCggIkLe3t8OyMk/fzhxXma73eY0fP15nzpzR4sWLb+oZlefPn9f48eM1bdo0HT582OHauyv/yOTr66tOnTpp5syZevXVVyVdPmWyYsWKVqjPy77N6XcSwK1DeANQ4MqXL6/4+HgtXbpUixcv1uLFizVt2jT16tVL06dPz/Nyr3WU4lrtmb/47Nu3T61bt1aNGjX07rvvKigoSB4eHvr+++81ceLELDccyU5GRoYeeughvfjii9lOv+eee3K4Fa7jkUce0RdffKH33nvP4SYi+aFXr156++23tXDhQnXv3l0zZ85Ux44dbxiibyTzs3zhhRcUHh6ebZ/MR1q0aNFC+/bt09dff60ffvhBn332mSZOnKiPPvpI/fr1u6k6ciKnRzgyMjIUGhqqd999N9vpmX+8yI/v+dVuNLZudv7Mmp588slrXheakzDdrFkzpaWlKS4uTmvWrLGuiWvevLnWrFmjXbt26fjx41Z7Xlzv8woPD9eSJUs0YcIEtWrVKssRzZwaPHiwpk2bpiFDhigsLMx6CHy3bt2yfH69evXS3LlztW7dOoWGhuqbb77RwIEDrbtD5mXfctQNKHwIbwBuCQ8PD3Xq1EmdOnVSRkaGBg4cqI8//livvPKKgoODr3naW0H49ttvlZqaqm+++cbhSMCVp5tlulZd1apV05kzZ9SmTZvrrqtSpUpavny5zpw543D07UZ3aLxyPdu2bctR3yvXea117Nq1S2XLllXJkiVVvHhx2e32HC9/8ODBCg4O1qhRo+Tj46OXXnop3+qvXbu27r33Xs2YMUOBgYE6ePCg3n///Twt60qZpywWLVr0hp+VJJUuXVpPPfWUnnrqKetmFmPGjMl1eCtXrpxKlChxzc+gSJEiWY4Q51S1atW0efNmtW7d+rrjJqff88zTGLdt25arZzMWhHLlysnb21vp6ek3/Lyut+2NGjWSh4eH1qxZozVr1mj48OGSLgf0Tz/9VMuXL7feZ6pUqZKWLVum06dPOxx927VrlzU9p5o0aaL+/furY8eOeuyxx7RgwQK5u+f+V6558+YpMjJS77zzjtV24cKFbO9W265dO5UrV04zZsxQ48aNde7cOfXs2dOanpt9C6Dw4po3AAXuxIkTDu+LFCli/YU389bmmc+0ys0t9PMq86//V5+CNG3atCx9S5YsmW1Njz/+uOLi4rR06dIs05KSkqzr6zp06KBLly453J49PT09SzC5lq5du2rz5s1asGBBlmnXOtpRoUIF1atXT9OnT3eofdu2bfrhhx/UoUMHSZc/hy5duujbb7/Vr7/+mqPlv/LKK3rhhRc0cuTIa95yPq/19+zZUz/88IMmTZqkMmXKZLl7YV72Rfny5dWqVSt9/PHHOnr0aJbpmc9ok7J+T728vBQcHJzl9vs54ebmprZt2+rrr792uK17YmKiZs6cqWbNmslut+d6udLl797hw4f16aefZpl2/vx5606VOf2et23bVt7e3ho/frwuXLjgMC2nR9Tyi5ubm7p27ar58+dnG9Sv/Lyu9zOjWLFiuu+++/Tll1/q4MGDDkfezp8/r8mTJ6tatWqqUKGCNU+HDh2Unp6uDz74wGFZEydOlM1my9HdNK/Upk0bzZo1S0uWLFHPnj3zfKTz6s/g/fffV3p6epa+7u7u6t69u+bMmaPo6GiFhoY6HEnLzb4FUHhx5A3ATVu8eLH11+kr3X///apatar69eunkydP6sEHH1RgYKD++OMPvf/++6pXr551PUm9evXk5uamt956S8nJyfL09LSeT5Xf2rZtax0JfPbZZ3XmzBl9+umnKl++fJZf8Bs0aKCpU6fqtddeU3BwsMqXL68HH3xQw4cP1zfffKOOHTuqd+/eatCggc6ePautW7dq3rx5OnDggMqWLatOnTqpadOmeumll3TgwAGFhIToq6++ytFNUaTLzw6bN2+eHnvsMfXp00cNGjTQyZMn9c033+ijjz5S3bp1s53v7bffVvv27RUWFqa+fftajwrw8fHRmDFjrH5vvPGGfvjhB7Vs2dK67fzRo0c1d+5crV27NtsHT7/99ttKTk5WVFSUvL29HW5gcTP1P/HEE3rxxRe1YMECDRgwwOFmNDezLz788EM1a9ZMoaGhevrpp1W1alUlJiYqLi5Of/75pzZv3ixJCgkJUatWrdSgQQOVLl1av/76q+bNm6dBgwZdc/uu57XXXlNMTIyaNWumgQMHyt3dXR9//LFSU1Nz/Gy07PTs2VNz5sxR//79tXLlSjVt2lTp6enatWuX5syZo6VLl6phw4Y5/p7b7XZNnDhR/fr103333acnnnhCpUqV0ubNm3Xu3LmbOrU5L958802tXLlSjRs31tNPP62QkBCdPHlSGzdu1LJly3Ty5ElJl48Y+vr66qOPPpK3t7dKliypxo0bW9dpNW/eXG+++aZ8fHwUGhoq6XKYr169unbv3q3evXs7rLdTp0564IEH9K9//UsHDhxQ3bp19cMPP+jrr7/WkCFDrvtIjGvp0qWLdYq43W7Xxx9/nKv5O3bsqP/+97/y8fFRSEiI4uLitGzZMuva3av16tVLkydP1sqVK63Hslwpp/sWQCF2a29uCeB2cr1HBeiKW3jPmzfPtG3b1pQvX954eHiYu+66yzz77LPm6NGjDsv79NNPTdWqVY2bm5vDYwOu9aiAuXPnZlvP1be9Hz16tJFkjh8/brV98803pk6dOqZYsWKmcuXK5q233jKff/65kWT2799v9UtISDARERHG29vbSHKo4/Tp02bkyJEmODjYeHh4mLJly5r777/f/Pvf/3Z4hMGJEydMz549jd1uNz4+PqZnz55m06ZNOXpUQOb8gwYNMhUrVjQeHh4mMDDQREZGWrf7zu72+MYYs2zZMtO0aVNTvHhxY7fbTadOncyOHTuyLP+PP/4wvXr1MuXKlTOenp6matWqJioqyqSmpl5zv6anp5vu3bsbd3d3s3Dhwpuq/0odOnQwksy6devydV/s27fP9OrVy/j7+5uiRYuaihUrmo4dO5p58+ZZfV577TXTqFEj4+vra4oXL25q1KhhXn/9dYfPMjvXelSAMcZs3LjRhIeHGy8vL1OiRAnzwAMPZNm2a31vr+fixYvmrbfeMrVq1TKenp6mVKlSpkGDBmbs2LEmOTnZ6pfT73lm3/vvv9/6vjRq1Mh8+eWX1vSWLVuaWrVqZaklMjIyy6M4siPJREVFZWmvVKmSw+3sjTEmMTHRREVFmaCgIFO0aFHj7+9vWrdubT755BOHfl9//bUJCQkx7u7uWT73RYsWGUlZHh3Sr18/I8n85z//yVLL6dOnzdChQ01AQIApWrSoufvuu83bb7/t8MiE623Ltb4LU6ZMMZLMCy+8kO2+uXK5Vz4q4NSpU+app54yZcuWNV5eXiY8PNzs2rUr232WqVatWqZIkSLmzz//zHZ6TvbttX7GAnA+mzG3+JwIAACu4W9/+5u2bt2qvXv3OrsUwCXde++9Kl26tHVdH4DbC9e8AQAKhaNHj2rRokUON1kAkHO//vqr4uPj1atXL2eXAqCAcOQNAOBU+/fv148//qjPPvtM69ev1759+3L8HDkAl29GtGHDBr3zzjv666+/9Pvvv+f58QQACjeOvAEAnCo2NlY9e/bU/v37NX36dIIbkEvz5s3TU089pbS0NH355ZcEN+A2xpE3AAAAAHABHHkDAAAAABdAeAMAAAAAF8BDunMgIyNDR44ckbe3t2w2m7PLAQAAAOAkxhidPn1aAQEBKlLk1h4LI7zlwJEjRxQUFOTsMgAAAAAUEocOHVJgYOAtXSfhLQe8vb0lXf6A7Ha7k6sBAAAA4CwpKSkKCgqyMsKtRHjLgcxTJe12O+ENAAAAgFMup+KGJQAAAADgAghvAAAAAOACCG8AAAAA4AIIbwAAAADgAghvAAAAAOACCG8AAAAA4AIIbwAAAADgAghvAAAAAOACCG8AAAAA4AIIbwAAAADgAghvAAAAAOACCG8AAAAA4AIIbwAAAADgAghvAAAAAOACCG8AAAAA4ALcnV0AABQGNpuzK3AuY5xdAW5HjCtnVwDgdsORNwAAAABwAYQ3AAAAAHABhDcAAAAAcAGENwAAAABwAYUmvL355puy2WwaMmSI1XbhwgVFRUWpTJky8vLyUteuXZWYmOgw38GDBxUREaESJUqofPnyGj58uC5duuTQZ9WqVapfv748PT0VHBys6OjoW7BFAAAAAJB/CkV4W79+vT7++GPVqVPHoX3o0KH69ttvNXfuXMXGxurIkSN65JFHrOnp6emKiIjQxYsXtW7dOk2fPl3R0dEaNWqU1Wf//v2KiIjQAw88oPj4eA0ZMkT9+vXT0qVLb9n2AQAAAMDNshnj3BvZnjlzRvXr19eUKVP02muvqV69epo0aZKSk5NVrlw5zZw5U48++qgkadeuXapZs6bi4uLUpEkTLV68WB07dtSRI0fk5+cnSfroo480YsQIHT9+XB4eHhoxYoQWLVqkbdu2Wevs1q2bkpKStGTJkhzVmJKSIh8fHyUnJ8tut+f/TgDgdNzS3NkV4HbEuHJ2BQAKgjOzgdOPvEVFRSkiIkJt2rRxaN+wYYPS0tIc2mvUqKG77rpLcXFxkqS4uDiFhoZawU2SwsPDlZKSou3bt1t9rl52eHi4tYzspKamKiUlxeEFAAAAAM7k1Id0z5o1Sxs3btT69euzTEtISJCHh4d8fX0d2v38/JSQkGD1uTK4ZU7PnHa9PikpKTp//ryKFy+eZd3jx4/X2LFj87xdAAAAAJDfnHbk7dChQ/rHP/6hGTNmqFixYs4qI1sjR45UcnKy9Tp06JCzSwIAAABwh3NaeNuwYYOOHTum+vXry93dXe7u7oqNjdXkyZPl7u4uPz8/Xbx4UUlJSQ7zJSYmyt/fX5Lk7++f5e6Tme9v1Mdut2d71E2SPD09ZbfbHV4AAAAA4ExOC2+tW7fW1q1bFR8fb70aNmyoHj16WP9ftGhRLV++3Jpn9+7dOnjwoMLCwiRJYWFh2rp1q44dO2b1iYmJkd1uV0hIiNXnymVk9slcBgAAAAC4Aqdd8+bt7a3atWs7tJUsWVJlypSx2vv27athw4apdOnSstvtGjx4sMLCwtSkSRNJUtu2bRUSEqKePXtqwoQJSkhI0Msvv6yoqCh5enpKkvr3768PPvhAL774ovr06aMVK1Zozpw5WrRo0a3dYAAAAAC4CU69YcmNTJw4UUWKFFHXrl2Vmpqq8PBwTZkyxZru5uam7777TgMGDFBYWJhKliypyMhIjRs3zupTpUoVLVq0SEOHDtV7772nwMBAffbZZwoPD3fGJgEAAABAnjj9OW+ugOe8Abc/nkfl7ApwO2JcObsCAAXhjn7OGwAAAADgxghvAAAAAOACCG8AAAAA4AIIbwAAAADgAghvAAAAAOACCG8AAAAA4AIIbwAAAADgAgr1Q7pxbTw7x9kVAAAAALcWR94AAAAAwAUQ3gAAAADABRDeAAAAAMAFEN4AAAAAwAUQ3gAAAADABRDeAAAAAMAFEN4AAAAAwAUQ3gAAAADABRDeAAAAAMAFEN4AAAAAwAUQ3gAAAADABRDeAAAAAMAFEN4AAAAAwAUQ3gAAAADABRDeAAAAAMAFEN4AAAAAwAUQ3gAAAADABRDeAAAAAMAFEN4AAAAAwAUQ3gAAAADABRDeAAAAAMAFEN4AAAAAwAUQ3gAAAADABRDeAAAAAMAFEN4AAAAAwAUQ3gAAAADABTg1vE2dOlV16tSR3W6X3W5XWFiYFi9ebE1v1aqVbDabw6t///4Oyzh48KAiIiJUokQJlS9fXsOHD9elS5cc+qxatUr169eXp6engoODFR0dfSs2DwAAAADyjbszVx4YGKg333xTd999t4wxmj59ujp37qxNmzapVq1akqSnn35a48aNs+YpUaKE9f/p6emKiIiQv7+/1q1bp6NHj6pXr14qWrSo3njjDUnS/v37FRERof79+2vGjBlavny5+vXrpwoVKig8PPzWbjAAAAAA5JHNGGOcXcSVSpcurbffflt9+/ZVq1atVK9ePU2aNCnbvosXL1bHjh115MgR+fn5SZI++ugjjRgxQsePH5eHh4dGjBihRYsWadu2bdZ83bp1U1JSkpYsWZLtclNTU5Wammq9T0lJUVBQkJKTk2W32/NvY2+CzebsCpyrcH1rcTtgTDm7AtyOGFfOrgBAQUhJSZGPj49TskGhueYtPT1ds2bN0tmzZxUWFma1z5gxQ2XLllXt2rU1cuRInTt3zpoWFxen0NBQK7hJUnh4uFJSUrR9+3arT5s2bRzWFR4erri4uGvWMn78ePn4+FivoKCg/NpMAAAAAMgTp542KUlbt25VWFiYLly4IC8vLy1YsEAhISGSpCeeeEKVKlVSQECAtmzZohEjRmj37t366quvJEkJCQkOwU2S9T4hIeG6fVJSUnT+/HkVL148S00jR47UsGHDrPeZR94AAAAAwFmcHt6qV6+u+Ph4JScna968eYqMjFRsbKxCQkL0zDPPWP1CQ0NVoUIFtW7dWvv27VO1atUKrCZPT095enoW2PIBAAAAILecftqkh4eHgoOD1aBBA40fP15169bVe++9l23fxo0bS5L27t0rSfL391diYqJDn8z3/v7+1+1jt9uzPeoGAAAAAIWR08Pb1TIyMhxuFnKl+Ph4SVKFChUkSWFhYdq6dauOHTtm9YmJiZHdbrdOvQwLC9Py5csdlhMTE+NwXR0AAAAAFHZOPW1y5MiRat++ve666y6dPn1aM2fO1KpVq7R06VLt27dPM2fOVIcOHVSmTBlt2bJFQ4cOVYsWLVSnTh1JUtu2bRUSEqKePXtqwoQJSkhI0Msvv6yoqCjrtMf+/fvrgw8+0Isvvqg+ffpoxYoVmjNnjhYtWuTMTQcAAACAXHFqeDt27Jh69eqlo0ePysfHR3Xq1NHSpUv10EMP6dChQ1q2bJkmTZqks2fPKigoSF27dtXLL79sze/m5qbvvvtOAwYMUFhYmEqWLKnIyEiH58JVqVJFixYt0tChQ/Xee+8pMDBQn332Gc94AwAAAOBSCt1z3gojZz7L4Vp4do6zK8DthjHl7ApwO2JcObsCAAWB57wBAAAAAK6L8AYAAAAALoDwBgAAAAAugPAGAAAAAC6A8AYAAAAALoDwBgAAAAAugPAGAAAAAC6A8AYAAAAALoDwBgAAAAAugPAGAAAAAC6A8AYAAAAALoDwBgAAAAAugPAGAAAAAC6A8AYAAAAALoDwBgAAAAAugPAGAAAAAC6A8AYAAAAALoDwBgAAAAAugPAGAAAAAC6A8AYAAAAALoDwBgAAAAAugPAGAAAAAC6A8AYAAAAALoDwBgAAAAAugPAGAAAAAC6A8AYAAAAALoDwBgAAAAAugPAGAAAAAC6A8AYAAAAALoDwBgAAAAAugPAGAAAAAC6A8AYAAAAALoDwBgAAAAAuwKnhberUqapTp47sdrvsdrvCwsK0ePFia/qFCxcUFRWlMmXKyMvLS127dlViYqLDMg4ePKiIiAiVKFFC5cuX1/Dhw3Xp0iWHPqtWrVL9+vXl6emp4OBgRUdH34rNAwAAAIB849TwFhgYqDfffFMbNmzQr7/+qgcffFCdO3fW9u3bJUlDhw7Vt99+q7lz5yo2NlZHjhzRI488Ys2fnp6uiIgIXbx4UevWrdP06dMVHR2tUaNGWX3279+viIgIPfDAA4qPj9eQIUPUr18/LV269JZvLwAAAADklc0YY5xdxJVKly6tt99+W48++qjKlSunmTNn6tFHH5Uk7dq1SzVr1lRcXJyaNGmixYsXq2PHjjpy5Ij8/PwkSR999JFGjBih48ePy8PDQyNGjNCiRYu0bds2ax3dunVTUlKSlixZkqOaUlJS5OPjo+TkZNnt9vzf6Dyw2ZxdgXMVrm8tbgeMKWdXgNsR48rZFQAoCM7MBoXmmrf09HTNmjVLZ8+eVVhYmDZs2KC0tDS1adPG6lOjRg3dddddiouLkyTFxcUpNDTUCm6SFB4erpSUFOvoXVxcnMMyMvtkLiM7qampSklJcXgBAAAAgDM5Pbxt3bpVXl5e8vT0VP/+/bVgwQKFhIQoISFBHh4e8vX1dejv5+enhIQESVJCQoJDcMucnjnten1SUlJ0/vz5bGsaP368fHx8rFdQUFB+bCoAAAAA5JnTw1v16tUVHx+vn3/+WQMGDFBkZKR27Njh1JpGjhyp5ORk63Xo0CGn1gMAAAAA7s4uwMPDQ8HBwZKkBg0aaP369Xrvvff097//XRcvXlRSUpLD0bfExET5+/tLkvz9/fXLL784LC/zbpRX9rn6DpWJiYmy2+0qXrx4tjV5enrK09MzX7YPAAAAAPKD04+8XS0jI0Opqalq0KCBihYtquXLl1vTdu/erYMHDyosLEySFBYWpq1bt+rYsWNWn5iYGNntdoWEhFh9rlxGZp/MZQAAAACAK3DqkbeRI0eqffv2uuuuu3T69GnNnDlTq1at0tKlS+Xj46O+fftq2LBhKl26tOx2uwYPHqywsDA1adJEktS2bVuFhISoZ8+emjBhghISEvTyyy8rKirKOnLWv39/ffDBB3rxxRfVp08frVixQnPmzNGiRYucuekAAAAAkCtODW/Hjh1Tr169dPToUfn4+KhOnTpaunSpHnroIUnSxIkTVaRIEXXt2lWpqakKDw/XlClTrPnd3Nz03XffacCAAQoLC1PJkiUVGRmpcePGWX2qVKmiRYsWaejQoXrvvfcUGBiozz77TOHh4bd8ewEAAAAgrwrdc94KI57zVvjwrUV+Y0w5uwLcjhhXzq4AQEHgOW8AAAAAgOsivAEAAACACyC8AQAAAIALILwBAAAAgAsgvAEAAACACyC8AQAAAIALILwBAAAAgAsgvAEAAACACyC8AQAAAIALILwBAAAAgAsgvAEAAACACyC8AQAAAIALILwBAAAAgAsgvAEAAACACyC8AQAAAIALILwBAAAAgAsgvAEAAACACyC8AQAAAIALILwBAAAAgAsgvAEAAACACyC8AQAAAIALILwBAAAAgAsgvAEAAACACyC8AQAAAIALILwBAAAAgAsgvAEAAACACyC8AQAAAIALILwBAAAAgAvIdXjbuHGjtm7dar3/+uuv1aVLF/3zn//UxYsX87U4AAAAAMBluQ5vzz77rH777TdJ0u+//65u3bqpRIkSmjt3rl588cV8LxAAAAAAkIfw9ttvv6levXqSpLlz56pFixaaOXOmoqOjNX/+/PyuDwAAAACgPIQ3Y4wyMjIkScuWLVOHDh0kSUFBQfrrr7/ytzoAAAAAgKQ8hLeGDRvqtdde03//+1/FxsYqIiJCkrR//375+fnle4EAAAAAgDyEt0mTJmnjxo0aNGiQ/vWvfyk4OFiSNG/ePN1///35XiAAAAAAIA/hrU6dOtq6dauSk5M1evRoq/3tt9/W9OnTc7Ws8ePH67777pO3t7fKly+vLl26aPfu3Q59WrVqJZvN5vDq37+/Q5+DBw8qIiJCJUqUUPny5TV8+HBdunTJoc+qVatUv359eXp6Kjg4WNHR0bnbcAAAAABwojw95y0pKUmfffaZRo4cqZMnT0qSduzYoWPHjuVqObGxsYqKitJPP/2kmJgYpaWlqW3btjp79qxDv6efflpHjx61XhMmTLCmpaenKyIiQhcvXtS6des0ffp0RUdHa9SoUVaf/fv3KyIiQg888IDi4+M1ZMgQ9evXT0uXLs3L5gMAAADALWczxpjczLBlyxa1bt1avr6+OnDggHbv3q2qVavq5Zdf1sGDB/XFF1/kuZjjx4+rfPnyio2NVYsWLSRdPvJWr149TZo0Kdt5Fi9erI4dO+rIkSPWNXcfffSRRowYoePHj8vDw0MjRozQokWLtG3bNmu+bt26KSkpSUuWLLlhXSkpKfLx8VFycrLsdnuety8/2WzOrsC5cvetBW6MMeXsCnA7Ylw5uwIABcGZ2SDXR96GDRump556Snv27FGxYsWs9g4dOmj16tU3VUxycrIkqXTp0g7tM2bMUNmyZVW7dm2NHDlS586ds6bFxcUpNDTU4WYp4eHhSklJ0fbt260+bdq0cVhmeHi44uLisq0jNTVVKSkpDi8AAAAAcCb33M6wfv16ffzxx1naK1asqISEhDwXkpGRoSFDhqhp06aqXbu21f7EE0+oUqVKCggI0JYtWzRixAjt3r1bX331lSQpISEhy10uM99n1nOtPikpKTp//ryKFy/uMG38+PEaO3ZsnrcFAAAAAPJbrsObp6dntkeifvvtN5UrVy7PhURFRWnbtm1au3atQ/szzzxj/X9oaKgqVKig1q1ba9++fapWrVqe13c9I0eO1LBhw6z3KSkpCgoKKpB1AQAAAEBO5Pq0yYcffljjxo1TWlqaJMlms+ngwYMaMWKEunbtmqciBg0apO+++04rV65UYGDgdfs2btxYkrR3715Jkr+/vxITEx36ZL739/e/bh+73Z7lqJt0OaDa7XaHFwAAAAA4U67D2zvvvKMzZ86ofPnyOn/+vFq2bKng4GB5e3vr9ddfz9WyjDEaNGiQFixYoBUrVqhKlSo3nCc+Pl6SVKFCBUlSWFiYtm7d6nCny5iYGNntdoWEhFh9li9f7rCcmJgYhYWF5apeAAAAAHCWXN9tMtPatWu1ZcsWnTlzRvXr189yQ5CcGDhwoGbOnKmvv/5a1atXt9p9fHxUvHhx7du3TzNnzlSHDh1UpkwZbdmyRUOHDlVgYKBiY2MlXX5UQL169RQQEKAJEyYoISFBPXv2VL9+/fTGG29IuvyogNq1aysqKkp9+vTRihUr9Nxzz2nRokUKDw+/YZ3cbbLw4Q5eyG+MKWdXgNsR48rZFQAoCM7MBnkOb/my8mv8VJ82bZp69+6tQ4cO6cknn9S2bdt09uxZBQUF6W9/+5tefvllhx31xx9/aMCAAVq1apVKliypyMhIvfnmm3J3/98lfatWrdLQoUO1Y8cOBQYG6pVXXlHv3r1zVCfhrfDhH0TkN8aUsyvA7Yhx5ewKABSEQh/eJk+enOMFPvfcczdVUGFEeCt8+AcR+Y0x5ewKcDtiXDm7AgAFodCHt5xciyZdPpL2+++/33RRhQ3hrfDhH0TkN8aUsyvA7Yhx5ewKABQEZ2aDHD0qYP/+/QVdBwAAAADgOnJ9t0kAAAAAwK2X6/DWtWtXvfXWW1naJ0yYoMceeyxfigIAAAAAOMp1eFu9erU6dOiQpb19+/ZavXp1vhQFAAAAAHCU6/B25swZeXh4ZGkvWrSoUlJS8qUoAAAAAICjXIe30NBQzZ49O0v7rFmzFBISki9FAQAAAAAc5ehuk1d65ZVX9Mgjj2jfvn168MEHJUnLly/Xl19+qblz5+Z7gQAAAACAPIS3Tp06aeHChXrjjTc0b948FS9eXHXq1NGyZcvUsmXLgqgRAAAAAO54OXpI952Oh3QXPnxrkd8YU86uALcjxpWzKwBQEJyZDXJ9zVtkZCR3lQQAAACAWyzX4S05OVlt2rTR3XffrTfeeEOHDx8uiLoAAAAAAFfIdXhbuHChDh8+rAEDBmj27NmqXLmy2rdvr3nz5iktLa0gagQAAACAO16uw5sklStXTsOGDdPmzZv1888/Kzg4WD179lRAQICGDh2qPXv25HedAAAAAHBHy1N4y3T06FHFxMQoJiZGbm5u6tChg7Zu3aqQkBBNnDgxv2oEAAAAgDtersNbWlqa5s+fr44dO6pSpUqaO3euhgwZoiNHjmj69OlatmyZ5syZo3HjxhVEvQAAAABwR8r1c94qVKigjIwMde/eXb/88ovq1auXpc8DDzwgX1/ffCgPAAAAACDlIbxNnDhRjz32mIoVK3bNPr6+vtq/f/9NFQYAAAAA+J8cnzaZnp6uLVu26NFHH80S3M6dO6ctW7YoIyMj3wsEAAAAAOQivP33v/9Vnz595OHhkWWah4eH+vTpo5kzZ+ZrcQAAAACAy3Ic3v7zn//ohRdekJubW5Zp7u7uevHFF/XJJ5/ka3EAAAAAgMtyHN52796tJk2aXHP6fffdp507d+ZLUQAAAAAARzkOb2fPnlVKSso1p58+fVrnzp3Ll6IAAAAAAI5yHN7uvvturVu37prT165dq7vvvjtfigIAAAAAOMpxeHviiSf08ssva8uWLVmmbd68WaNGjdITTzyRr8UBAAAAAC6zGWNMTjqmpaWpbdu2Wrt2rdq0aaMaNWpIknbt2qVly5apadOmiomJUdGiRQu0YGdISUmRj4+PkpOTZbfbnV2OJMlmc3YFzpWzby2Qc4wpZ1eA2xHjytkVACgIzswGOQ5v0uUAN3HiRM2cOVN79uyRMUb33HOPnnjiCQ0ZMiTbxwjcDghvhQ//ICK/MaacXQFuR4wrZ1cAoCC4THi7UxHeCh++tchvjClnV4DbEePK2RUAKAjOzAY5vuYNAAAAAOA8hDcAAAAAcAGENwAAAABwAYQ3AAAAAHABuQ5v27Ztu+a0hQsX3kwtAAAAAIBryHV4Cw8P1/79+7O0z58/Xz169MiXogAAAAAAjnId3vr166c2bdooISHBaps9e7Z69eql6OjoXC1r/Pjxuu++++Tt7a3y5curS5cu2r17t0OfCxcuKCoqSmXKlJGXl5e6du2qxMREhz4HDx5URESESpQoofLly2v48OG6dOmSQ59Vq1apfv368vT0VHBwcK5rBQAAAABnynV4Gzt2rDp06KA2bdro5MmTmjlzpp566il98cUXeuyxx3K1rNjYWEVFRemnn35STEyM0tLS1LZtW509e9bqM3ToUH377beaO3euYmNjdeTIET3yyCPW9PT0dEVEROjixYtat26dpk+frujoaI0aNcrqs3//fkVEROiBBx5QfHy8hgwZon79+mnp0qW53XwAAAAAcIo8P6S7R48eWr9+vQ4fPqyZM2eqc+fON13M8ePHVb58ecXGxqpFixZKTk5WuXLlNHPmTD366KOSpF27dqlmzZqKi4tTkyZNtHjxYnXs2FFHjhyRn5+fJOmjjz7SiBEjdPz4cXl4eGjEiBFatGiRw/V63bp1U1JSkpYsWXLDunhId+HDg0+R3xhTzq4AtyPGlbMrAFAQnJkN3HPS6ZtvvsnS9sgjj2jNmjXq3r27bDab1efhhx/OczHJycmSpNKlS0uSNmzYoLS0NLVp08bqU6NGDd11111WeIuLi1NoaKgV3KTL1+UNGDBA27dv17333qu4uDiHZWT2GTJkSLZ1pKamKjU11XqfkpKS520CAAAAgPyQo/DWpUuXa077/PPP9fnnn0uSbDab0tPT81RIRkaGhgwZoqZNm6p27dqSpISEBHl4eMjX19ehr5+fn3XNXUJCgkNwy5yeOe16fVJSUnT+/HkVL17cYdr48eM1duzYPG0HAAAAABSEHF3zlpGRkaNXXoObJEVFRWnbtm2aNWtWnpeRX0aOHKnk5GTrdejQIWeXBAAAAOAOl6MjbwVt0KBB+u6777R69WoFBgZa7f7+/rp48aKSkpIcjr4lJibK39/f6vPLL784LC/zbpRX9rn6DpWJiYmy2+1ZjrpJkqenpzw9PfNl2wAAAAAgP+T6bpPPPfecJk+enKX9gw8+uOY1ZNdijNGgQYO0YMECrVixQlWqVHGY3qBBAxUtWlTLly+32nbv3q2DBw8qLCxMkhQWFqatW7fq2LFjVp+YmBjZ7XaFhIRYfa5cRmafzGUAAAAAQGGX6/A2f/58NW3aNEv7/fffr3nz5uVqWVFRUfq///s/zZw5U97e3kpISFBCQoLOnz8vSfLx8VHfvn01bNgwrVy5Uhs2bNBTTz2lsLAwNWnSRJLUtm1bhYSEqGfPntq8ebOWLl2ql19+WVFRUdbRs/79++v333/Xiy++qF27dmnKlCmaM2eOhg4dmtvNBwAAAACnyPWjAooVK6Zt27YpODjYoX3v3r2qXbu2Lly4kPOVX+MewtOmTVPv3r0lXX5I9/PPP68vv/xSqampCg8P15QpU6xTIiXpjz/+0IABA7Rq1SqVLFlSkZGRevPNN+Xu/r+zQletWqWhQ4dqx44dCgwM1CuvvGKt40Z4VEDhw+2Xkd8YU86uALcjxpWzKwBQEJyZDXId3mrXrq3+/ftr0KBBDu3vv/++pk6dqh07duRrgYUB4a3w4R9E5DfGlLMrwO2IceXsCgAUhEL/nLcrDRs2TIMGDdLx48f14IMPSpKWL1+ud955R5MmTcrv+gAAAAAAykN469Onj1JTU/X666/r1VdflSRVrlxZU6dOVa9evfK9QAAAAABAHk6bvNLx48dVvHhxeXl55WdNhQ6nTRY+nIqC/MaYcnYFuB0xrpxdAYCC4FKnTWY6fvy4du/eLUmqUaOGypYtm29FAQAAAAAc5fpRAWfPnlWfPn1UoUIFtWjRQi1atFCFChXUt29fnTt3riBqBAAAAIA7Xq7D27BhwxQbG6tvv/1WSUlJSkpK0tdff63Y2Fg9//zzBVEjAAAAANzxcn3NW9myZTVv3jy1atXKoX3lypV6/PHHdfz48fysr1DgmrfCh+sIkN8YU86uALcjxpWzKwBQEJyZDXJ95O3cuXPy8/PL0l6+fHlOmwQAAACAApLr8BYWFqbRo0frwoULVtv58+c1duxYhYWF5WtxAAAAAIDLcn23yffee0/h4eEKDAxU3bp1JUmbN29WsWLFtHTp0nwvEAAAAACQh/BWu3Zt7dmzRzNmzNCuXbskSd27d1ePHj1UvHjxfC8QAAAAAJDH57yVKFFCTz/9dH7XAgAAAAC4hhyFt2+++SbHC3z44YfzXAwAAAAAIHs5Cm9dunTJ0cJsNpvS09Nvph4AAAAAQDZyFN4yMjIKug4AAAAAwHXk+lEBAAAAAIBbL8fhbcWKFQoJCVFKSkqWacnJyapVq5ZWr16dr8UBAAAAAC7LcXibNGmSnn76adnt9izTfHx89Oyzz2rixIn5WhwAAAAA4LIch7fNmzerXbt215zetm1bbdiwIV+KAgAAAAA4ynF4S0xMVNGiRa853d3dXcePH8+XogAAAAAAjnIc3ipWrKht27Zdc/qWLVtUoUKFfCkKAAAAAOAox+GtQ4cOeuWVV3ThwoUs086fP6/Ro0erY8eO+VocAAAAAOAymzHG5KRjYmKi6tevLzc3Nw0aNEjVq1eXJO3atUsffvih0tPTtXHjRvn5+RVowc6QkpIiHx8fJScnZ3vDFmew2ZxdgXPl7FsL5BxjytkV4HbEuHJ2BQAKgjOzQY4e0i1Jfn5+WrdunQYMGKCRI0cqM/PZbDaFh4frww8/vC2DGwAAAAAUBjkOb5JUqVIlff/99zp16pT27t0rY4zuvvtulSpVqqDqAwAAAAAol+EtU6lSpXTffffldy0AAAAAgGvI8Q1LAAAAAADOQ3gDAAAAABdAeAMAAAAAF0B4AwAAAAAXQHgDAAAAABdAeAMAAAAAF0B4AwAAAAAXQHgDAAAAABfg1PC2evVqderUSQEBAbLZbFq4cKHD9N69e8tmszm82rVr59Dn5MmT6tGjh+x2u3x9fdW3b1+dOXPGoc+WLVvUvHlzFStWTEFBQZowYUJBbxoAAAAA5CunhrezZ8+qbt26+vDDD6/Zp127djp69Kj1+vLLLx2m9+jRQ9u3b1dMTIy+++47rV69Ws8884w1PSUlRW3btlWlSpW0YcMGvf322xozZow++eSTAtsuAAAAAMhv7s5cefv27dW+ffvr9vH09JS/v3+203bu3KklS5Zo/fr1atiwoSTp/fffV4cOHfTvf/9bAQEBmjFjhi5evKjPP/9cHh4eqlWrluLj4/Xuu+86hLwrpaamKjU11XqfkpKSxy0EAAAAgPxR6K95W7VqlcqXL6/q1atrwIABOnHihDUtLi5Ovr6+VnCTpDZt2qhIkSL6+eefrT4tWrSQh4eH1Sc8PFy7d+/WqVOnsl3n+PHj5ePjY72CgoIKaOsAAAAAIGcKdXhr166dvvjiCy1fvlxvvfWWYmNj1b59e6Wnp0uSEhISVL58eYd53N3dVbp0aSUkJFh9/Pz8HPpkvs/sc7WRI0cqOTnZeh06dCi/Nw0AAAAAcsWpp03eSLdu3az/Dw0NVZ06dVStWjWtWrVKrVu3LrD1enp6ytPTs8CWDwAAAAC5VaiPvF2tatWqKlu2rPbu3StJ8vf317Fjxxz6XLp0SSdPnrSuk/P391diYqJDn8z317qWDgAAAAAKG5cKb3/++adOnDihChUqSJLCwsKUlJSkDRs2WH1WrFihjIwMNW7c2OqzevVqpaWlWX1iYmJUvXp1lSpV6tZuAAAAAADkkVPD25kzZxQfH6/4+HhJ0v79+xUfH6+DBw/qzJkzGj58uH766ScdOHBAy5cvV+fOnRUcHKzw8HBJUs2aNdWuXTs9/fTT+uWXX/Tjjz9q0KBB6tatmwICAiRJTzzxhDw8PNS3b19t375ds2fP1nvvvadhw4Y5a7MBAAAAINdsxhjjrJWvWrVKDzzwQJb2yMhITZ06VV26dNGmTZuUlJSkgIAAtW3bVq+++qrDDUhOnjypQYMG6dtvv1WRIkXUtWtXTZ48WV5eXlafLVu2KCoqSuvXr1fZsmU1ePBgjRgxIsd1pqSkyMfHR8nJybLb7Te30fnEZnN2Bc7lvG8tbleMKWdXgNsR48rZFQAoCM7MBk4Nb66C8Fb48K1FfmNMObsC3I4YV86uAEBBcGY2cKlr3gAAAADgTkV4AwAAAAAXQHgDAAAAABdAeAMAAAAAF0B4AwAAAAAXQHgDAAAAABdAeAMAAAAAF0B4AwAAAAAXQHgDAAAAABdAeAMAAAAAF0B4AwAAAAAXQHgDAAAAABdAeAMAAAAAF0B4AwAAAAAXQHgDAAAAABdAeAMAAAAAF0B4AwAAAAAXQHgDAAAAABdAeAMAAAAAF0B4AwAAAAAXQHgDAAAAABdAeAMAAAAAF0B4AwAAAAAXQHgDAAAAABdAeAMAAAAAF0B4AwAAAAAXQHgDAAAAABdAeAMAAAAAF0B4AwAAAAAXQHgDAAAAABdAeAMAAAAAF0B4AwAAAAAXQHgDAAAAABfg1PC2evVqderUSQEBAbLZbFq4cKHDdGOMRo0apQoVKqh48eJq06aN9uzZ49Dn5MmT6tGjh+x2u3x9fdW3b1+dOXPGoc+WLVvUvHlzFStWTEFBQZowYUJBbxoAAAAA5CunhrezZ8+qbt26+vDDD7OdPmHCBE2ePFkfffSRfv75Z5UsWVLh4eG6cOGC1adHjx7avn27YmJi9N1332n16tV65plnrOkpKSlq27atKlWqpA0bNujtt9/WmDFj9MknnxT49gEAAABAfrEZY4yzi5Akm82mBQsWqEuXLpIuH3ULCAjQ888/rxdeeEGSlJycLD8/P0VHR6tbt27auXOnQkJCtH79ejVs2FCStGTJEnXo0EF//vmnAgICNHXqVP3rX/9SQkKCPDw8JEkvvfSSFi5cqF27duWotpSUFPn4+Cg5OVl2uz3/Nz4PbDZnV+BcheNbi9sJY8rZFeB2xLhydgUACoIzs0GhveZt//79SkhIUJs2baw2Hx8fNW7cWHFxcZKkuLg4+fr6WsFNktq0aaMiRYro559/tvq0aNHCCm6SFB4ert27d+vUqVPZrjs1NVUpKSkOLwAAAABwpkIb3hISEiRJfn5+Du1+fn7WtISEBJUvX95huru7u0qXLu3QJ7tlXLmOq40fP14+Pj7WKygo6OY3CAAAAABuQqENb840cuRIJScnW69Dhw45uyQAAAAAd7hCG978/f0lSYmJiQ7tiYmJ1jR/f38dO3bMYfqlS5d08uRJhz7ZLePKdVzN09NTdrvd4QUAAAAAzlRow1uVKlXk7++v5cuXW20pKSn6+eefFRYWJkkKCwtTUlKSNmzYYPVZsWKFMjIy1LhxY6vP6tWrlZaWZvWJiYlR9erVVapUqVu0NQAAAABwc5wa3s6cOaP4+HjFx8dLunyTkvj4eB08eFA2m01DhgzRa6+9pm+++UZbt25Vr169FBAQYN2RsmbNmmrXrp2efvpp/fLLL/rxxx81aNAgdevWTQEBAZKkJ554Qh4eHurbt6+2b9+u2bNn67333tOwYcOctNUAAAAAkHtOfVTAqlWr9MADD2Rpj4yMVHR0tIwxGj16tD755BMlJSWpWbNmmjJliu655x6r78mTJzVo0CB9++23KlKkiLp27arJkyfLy8vL6rNlyxZFRUVp/fr1Klu2rAYPHqwRI0bkuE4eFVD4cPtl5DfGlLMrwO2IceXsCgAUBGdmg0LznLfCjPBW+PCtRX5jTDm7AtyOGFfOrgBAQeA5bwAAAACA6yK8AQAAAIALILwBAAAAgAsgvAEAAACACyC8AQAAAIALILwBAAAAgAsgvAEAAACACyC8AQAAAIALILwBAAAAgAsgvAEAAACACyC8AQAAAIALILwBAAAAgAsgvAEAAACACyC8AQAAAIALILwBAAAAgAsgvAEAAACACyC8AQAAAIALILwBAAAAgAsgvAEAAACACyC8AQAAAIALILwBAAAAgAsgvAEAAACACyC8AQAAAIALILwBAAAAgAsgvAEAAACACyC8AQAAAIALILwBAAAAgAsgvAEAAACACyC8AQAAAIALILwBAAAAgAsgvAEAAACACyC8AQAAAIALILwBAAAAgAsgvAEAAACACyjU4W3MmDGy2WwOrxo1aljTL1y4oKioKJUpU0ZeXl7q2rWrEhMTHZZx8OBBRUREqESJEipfvryGDx+uS5cu3epNAQAAAICb4u7sAm6kVq1aWrZsmfXe3f1/JQ8dOlSLFi3S3Llz5ePjo0GDBumRRx7Rjz/+KElKT09XRESE/P39tW7dOh09elS9evVS0aJF9cYbb9zybQEAAACAvCr04c3d3V3+/v5Z2pOTk/Wf//xHM2fO1IMPPihJmjZtmmrWrKmffvpJTZo00Q8//KAdO3Zo2bJl8vPzU7169fTqq69qxIgRGjNmjDw8PG715gAAAABAnhTq0yYlac+ePQoICFDVqlXVo0cPHTx4UJK0YcMGpaWlqU2bNlbfGjVq6K677lJcXJwkKS4uTqGhofLz87P6hIeHKyUlRdu3b7/mOlNTU5WSkuLwAgAAAABnKtThrXHjxoqOjtaSJUs0depU7d+/X82bN9fp06eVkJAgDw8P+fr6Oszj5+enhIQESVJCQoJDcMucnjntWsaPHy8fHx/rFRQUlL8bBgAAAAC5VKhPm2zfvr31/3Xq1FHjxo1VqVIlzZkzR8WLFy+w9Y4cOVLDhg2z3qekpBDgAAAAADhVoT7ydjVfX1/dc8892rt3r/z9/XXx4kUlJSU59ElMTLSukfP3989y98nM99ldR5fJ09NTdrvd4QUAAAAAzuRS4e3MmTPat2+fKlSooAYNGqho0aJavny5NX337t06ePCgwsLCJElhYWHaunWrjh07ZvWJiYmR3W5XSEjILa8fAAAAAPKqUJ82+cILL6hTp06qVKmSjhw5otGjR8vNzU3du3eXj4+P+vbtq2HDhql06dKy2+0aPHiwwsLC1KRJE0lS27ZtFRISop49e2rChAlKSEjQyy+/rKioKHl6ejp56wAAAAAg5wp1ePvzzz/VvXt3nThxQuXKlVOzZs30008/qVy5cpKkiRMnqkiRIuratatSU1MVHh6uKVOmWPO7ubnpu+++04ABAxQWFqaSJUsqMjJS48aNc9YmAQAAAECe2IwxxtlFFHYpKSny8fFRcnJyobn+zWZzdgXOxbcW+Y0x5ewKcDtiXDm7AgAFwZnZwKWueQMAAACAOxXhDQAAAABcAOENAAAAAFwA4Q0AAAAAXADhDQAAAABcAOENAAAAAFwA4Q0AAAAAXADhDQAAAABcAOENAAAAAFwA4Q0AAAAAXADhDQAAAABcAOENAAAAAFwA4Q0AAAAAXADhDQAAAABcAOENAAAAAFwA4Q0AAAAAXADhDQAAAABcAOENAAAAAFwA4Q0AAAAAXADhDQAAAABcAOENAAAAAFwA4Q0AAAAAXADhDQAAAABcAOENAAAAAFwA4Q0AAAAAXADhDQAAAABcAOENAAAAAFwA4Q0AAAAAXADhDQAAAABcAOENAAAAAFwA4Q0AAAAAXADhDQAAAABcgLuzCwAAAABwYzabsytwLmOcXYHzceQNAAAAAFzAHRXePvzwQ1WuXFnFihVT48aN9csvvzi7JAAAAADIkTsmvM2ePVvDhg3T6NGjtXHjRtWtW1fh4eE6duyYs0sDAAAAgBu6Y8Lbu+++q6efflpPPfWUQkJC9NFHH6lEiRL6/PPPnV0aAAAAANzQHXHDkosXL2rDhg0aOXKk1VakSBG1adNGcXFxWfqnpqYqNTXVep+cnCxJSklJKfhikSN8FED+YkwB+Y9xBeSvwjKmMjOBccIdVO6I8PbXX38pPT1dfn5+Du1+fn7atWtXlv7jx4/X2LFjs7QHBQUVWI3IHR8fZ1cA3F4YU0D+Y1wB+auwjanTp0/L5xYXdUeEt9waOXKkhg0bZr3PyMjQyZMnVaZMGdnu9Hu06vJfG4KCgnTo0CHZ7XZnlwO4PMYUkP8YV0D+Ykz9jzFGp0+fVkBAwC1f9x0R3sqWLSs3NzclJiY6tCcmJsrf3z9Lf09PT3l6ejq0+fr6FmSJLslut9/xgxfIT4wpIP8xroD8xZi67FYfcct0R9ywxMPDQw0aNNDy5cuttoyMDC1fvlxhYWFOrAwAAAAAcuaOOPImScOGDVNkZKQaNmyoRo0aadKkSTp79qyeeuopZ5cGAAAAADd0x4S3v//97zp+/LhGjRqlhIQE1atXT0uWLMlyExPcmKenp0aPHp3l1FIAecOYAvIf4wrIX4ypwsFmnHGPSwAAAABArtwR17wBAAAAgKsjvAEAAACACyC8AQAAAIALILwVoMqVK2vSpEnOLsPlHDhwQDabTfHx8QW+Lj4j18NnljeMK1wLn1feMKZwPXxmecO4ygFzm4uMjDSSzLPPPptl2sCBA40kExkZmaNl7d+/30gymzZtylH/Y8eOmbNnz+aob8eOHU14eHi201avXm0kmc2bN+doWdeycuVKI8mcOnXqppZztXPnzplSpUqZMmXKmAsXLuRq3sjISNO5c2eHtkuXLpmjR4+atLS0fKtx2rRpxsfHJ0t7bj6j/PLBBx+YSpUqGU9PT9OoUSPz888/39L15wfG1f8wrnyytN/qcRUbG2s6duxoKlSoYCSZBQsW3LJ15xfG1P8wpnyytN/qMfXGG2+Yhg0bGi8vL1OuXDnTuXNns2vXrlu2/vzCuPofxpVPlvZbPa6mTJliQkNDjbe3t/H29jZNmjQx33//fa6Xc0cceQsKCtKsWbN0/vx5q+3ChQuaOXOm7rrrrnxf38WLFyVJ5cqVU4kSJXI0T9++fRUTE6M///wzy7Rp06apYcOGqlOnTr7WmVfGGF26dMl6P3/+fNWqVUs1atTQwoULb3r5bm5u8vf3l7t7wT/JIjefUX6YPXu2hg0bptGjR2vjxo2qW7euwsPDdezYsVtWQ35hXOUvxlXenT17VnXr1tWHH354y9ZZEBhT+YsxlXexsbGKiorSTz/9pJiYGKWlpalt27Y6e/bsLashvzCu8hfjKu8CAwP15ptvasOGDfr111/14IMPqnPnztq+fXvuFpTPobLQyUz1tWvXNv/3f/9ntc+YMcPUqVPHdO7c2fqry+LFi03Tpk2Nj4+PKV26tImIiDB79+615pHk8GrZsqXDOl577TVToUIFU7lyZWOMMZUqVTITJ040xlz+i0fRokXN6tWrreW99dZbply5ciYhIcGkpaUZPz8/8+qrrzrUf/r0aePl5WWmTp1qjDFmzZo1plmzZqZYsWImMDDQDB482Jw5c8bqf+HCBfPiiy+awMBA4+HhYapVq2Y+++wz6y9GV74yt/vChQtm8ODBply5csbT09M0bdrU/PLLL9YyM/9a8/3335v69eubokWLmpUrV1rTW7VqZT766CMzdepU89BDD2X5DLZt22YiIiKMt7e38fLyMs2aNTN79+41o0ePzlLTypUrHf66lZ6ebipWrGimTJnisMyNGzcam81mDhw4YIwx5p133jG1a9c2JUqUMIGBgWbAgAHm9OnTDvVf+Ro9enSWz8gYY/744w/z8MMPm5IlSxpvb2/z2GOPmYSEBGv66NGjTd26dc0XX3xhKlWqZOx2u/n73/9uUlJSsmx3dho1amSioqKs9+np6SYgIMCMHz8+R/MXFowrxlVhGldXkgsfeWNMMaYK45gy5vIRCkkmNjY2T/M7C+OKcVWYx5UxxpQqVcp89tlnuZrnjglv7777rmndurXV3rp1azNx4kSHgTtv3jwzf/58s2fPHrNp0ybTqVMnExoaatLT040xxvzyyy9Gklm2bJk5evSoOXHihLUOLy8v07NnT7Nt2zazbds2Y0zWL8Xw4cNNpUqVTFJSktm4caPx8PAwX3/9tcP0atWqmYyMDKvt888/N8WLFzdJSUlm7969pmTJkmbixInmt99+Mz/++KO59957Te/eva3+jz/+uAkKCjJfffWV2bdvn1m2bJmZNWuWuXTpkpk/f76RZHbv3m2OHj1qkpKSjDHGPPfccyYgIMB8//33Zvv27SYyMtKUKlXK2r7ML36dOnXMDz/8YPbu3WtN27t3r/H09DQnT540J06cMMWKFbMGkzHG/Pnnn6Z06dLmkUceMevXrze7d+82n3/+udm1a5c5ffq0efzxx027du3M0aNHzdGjR01qamqWUxNeeOEF06xZM4fP9fnnn3domzhxolmxYoXZv3+/Wb58ualevboZMGCAMcaY1NRUM2nSJGO32631ZA7qKz+j9PR0U69ePdOsWTPz66+/mp9++sk0aNDA+gFtzOWB6+XlZR555BGzdetWs3r1auPv72/++c9/XvM7mCk1NdW4ubll+cWyV69e5uGHH77h/IUJ44pxVVjG1dVcPbwxphhThW1MGWPMnj17jCSzdevWPM3vLIwrxlVhHVeXLl0yX375pfHw8DDbt2/P1bx3THg7duyY8fT0NAcOHDAHDhwwxYoVM8ePH3cYuFc7fvy4ww+ra53vHBkZafz8/ExqaqpD+9UDNzU11dSrV888/vjjJiQkxDz99NMO/Xfu3Gn95SFT8+bNzZNPPmmMMaZv377mmWeecZhnzZo1pkiRIub8+fNm9+7dRpKJiYnJdnuyO9/5zJkzpmjRombGjBlW28WLF01AQICZMGGCw3wLFy7Mssx//vOfpkuXLtb7zp07W3/RMMaYkSNHmipVqpiLFy9mW1N25ztfvZ83bdpkbDab+eOPP4wxxvpLTOZforIzd+5cU6ZMGev9tc53vvIz+uGHH4ybm5s5ePCgNX379u1GkvVXqNGjR5sSJUo4/JVl+PDhpnHjxtesJdPhw4eNJLNu3TqH9uHDh5tGjRrdcP7ChHH1P4wrnyz9buW4upqrhzfGFGOqsI2p9PR0ExERYZo2bZrreZ2NcfU/jCufLP2cMa62bNliSpYsadzc3IyPj49ZtGhRjufNdEdc8yZdPq81IiJC0dHRmjZtmiIiIlS2bFmHPnv27FH37t1VtWpV2e12Va5cWZJ08ODBGy4/NDRUHh4e1+3j4eGhGTNmaP78+bpw4YImTpzoML1GjRq6//779fnnn0uS9u7dqzVr1qhv376SpM2bNys6OlpeXl7WKzw8XBkZGdq/f7/i4+Pl5uamli1b5nS3aN++fUpLS1PTpk2ttqJFi6pRo0bauXOnQ9+GDRs6vE9PT9f06dP15JNPWm1PPvmkoqOjlZGRIUmKj49X8+bNVbRo0RzXdLV69eqpZs2amjlzpqTL5+IfO3ZMjz32mNVn2bJlat26tSpWrChvb2/17NlTJ06c0Llz53K8np07dyooKEhBQUFWW0hIiHx9fR32ReXKleXt7W29r1Chgktes5YfGFfZY1z9D+MqdxhT2WNM/c+tHlNRUVHatm2bZs2alet5CwvGVfYYV/9zq8ZV9erVFR8fr59//lkDBgxQZGSkduzYkeP5pTvsUQF9+vRRdHS0pk+frj59+mSZ3qlTJ508eVKffvqpfv75Z/3888+S/nfx6fWULFkyRzWsW7dOknTy5EmdPHkyy/S+fftq/vz5On36tKZNm6Zq1apZA/HMmTN69tlnFR8fb702b96sPXv2qFq1aipevHiOasirq7dx6dKlOnz4sP7+97/L3d1d7u7u6tatm/744w8tX75ckvKtph49elgDd+bMmWrXrp3KlCkj6fJtZTt27Kg6depo/vz52rBhg3Xjgpx8drl19Q8hm81m/aC6nrJly8rNzU2JiYkO7YmJifL398/XGm8lxtXNYVxdltdxdTtiTN0cxtRl+TGmBg0apO+++04rV65UYGBgfpZ3yzGubg7j6rKbHVceHh4KDg5WgwYNNH78eNWtW1fvvfdermq4o8Jbu3btdPHiRaWlpSk8PNxh2okTJ7R79269/PLLat26tWrWrKlTp0459Mn8q0p6enqe1r9v3z4NHTpUn376qRo3bqzIyMgsH/jjjz+uIkWKaObMmfriiy/Up08f2Ww2SVL9+vW1Y8cOBQcHZ3l5eHgoNDRUGRkZio2NzXb92dVfrVo1eXh46Mcff7Ta0tLStH79eoWEhFx3e/7zn/+oW7duDj9I4uPj1a1bN/3nP/+RJNWpU0dr1qxRWlraNWvKyf584okntG3bNm3YsEHz5s1Tjx49rGkbNmxQRkaG3nnnHTVp0kT33HOPjhw5kuv11KxZU4cOHdKhQ4esth07digpKemG+yInPDw81KBBA+uHmiRlZGRo+fLlCgsLu+nlOwvjinF1PQU9rm5HjCnG1PXcijFljNGgQYO0YMECrVixQlWqVMmX5ToT44pxdT3O+rcqIyNDqampuZsp1ydaupirz6dNTk42ycnJ1vvM853T09NNmTJlzJNPPmn27Nljli9fbu677z6H6yfS0tJM8eLFzWuvvWYSEhKsiz2zO2fXGMdzaS9dumSaNGliunbtaowx5siRI6ZMmTLWOcVX6tu3rylVqpRxc3Mzhw8ftto3b95sihcvbqKiosymTZvMb7/9ZhYuXOhw98LevXuboKAgs2DBAvP777+blStXmtmzZxtjLl84arPZTHR0tDl27Jh1weY//vEPExAQYBYvXuxwserJkyeNMdmfJ33s2DFTtGhRs3jx4iz1f//998bT09OcOHHC/PXXX6ZMmTLWxaq//fab+eKLL6znxbz++uvmrrvuMrt27TLHjx83Fy9evOZ55U2bNjV169Y13t7e5ty5c1Z7fHy8kWQmTZpk9u3bZ7744gtTsWJFh5p//PFH60Lj48ePW8/1uPIzysjIMPXq1TPNmzc3GzZsMD///HO2F6vWrVvXoa6JEyeaSpUqZdkP2Zk1a5bx9PQ00dHRZseOHeaZZ54xvr6+DnczcgWMK8aVMYVnXJ0+fdps2rTJbNq0yUgy7777rtm0aZN1jYQrYEwxpowpPGNqwIABxsfHx6xatcq6ycPRo0cdtscVMK4YV8YUnnH10ksvmdjYWLN//36zZcsW89JLLxmbzWZ++OGHHM2f6Y4Lb1e78mLVmJgYU7NmTePp6Wnq1KljVq1aleXi908//dQEBQWZIkWKZLlN7NWu/FKMHTvWVKhQwfz111/W9Pnz5xsPDw8THx/vMN+6deuMJNOhQ4csy/zll1/MQw89ZLy8vEzJkiVNnTp1zOuvv25NP3/+vBk6dKipUKGC8fDwMMHBwebzzz+3po8bN874+/sbm81mbff58+fN4MGDTdmyZa97m9grB+6///1v4+vrm+1FqKmpqcbX19e89957xpjLP3Datm1rSpQoYby9vU3z5s3Nvn37jDGXfwBkbo+yuU3slaZMmWIkmV69emVZ57vvvmsqVKhgihcvbsLDw80XX3yRpeb+/fubMmXK5MttYq+Um4FrjDHvv/++ueuuu4yHh4dp1KiR+emnn3I8b2HBuGJcZSoM4yq7W0FLOX/4bmHAmGJMZSoMYyq78STJTJs2LUfzFxaMK8ZVpsIwrvr06WMqVapkPDw8TLly5Uzr1q1zHdyMMcZmjDG5O1YHAAAAALjV7qhr3gAAAADAVRHegHxy8OBBh1v4Xv3Kye2GAThiXAH5izEF5L9bOa44bRLIJ5cuXdKBAweuOb1y5cpyd3e/dQUBtwHGFZC/GFNA/ruV44rwBgAAAAAugNMmAQAAAMAFEN4AAAAAwAUQ3gAAAADABRDeAAAAAMAFEN4AALiBVq1aaciQIc4uAwBwhyO8AQAKTO/evWWz2fTmm286tC9cuFA2my1Xy6pcubImTZqUj9UVnAMHDshmsyk+Pt7ZpQAAbiOENwBAgSpWrJjeeustnTp1ytml5NrFixedXUK+SktLc3YJAICbQHgDABSoNm3ayN/fX+PHj79uv7Vr16p58+YqXry4goKC9Nxzz+ns2bOSLp+2+Mcff2jo0KGy2Wyy2WwyxqhcuXKaN2+etYx69eqpQoUKDsv09PTUuXPnJEkHDx5U586d5eXlJbvdrscff1yJiYlW/zFjxqhevXr67LPPVKVKFRUrVizbWhctWiQfHx/NmDEjT/tk37596ty5s/z8/OTl5aX77rtPy5Yts6aPGzdOtWvXzjJfvXr19Morr1jvP/vsM9WsWVPFihVTjRo1NGXKFGta5tG/2bNnq2XLlipWrJhmzJihP/74Q506dVKpUqVUsmRJ1apVS99//32etgMAcGsR3gAABcrNzU1vvPGG3n//ff3555/Z9tm3b5/atWunrl27asuWLZo9e7bWrl2rQYMGSZK++uorBQYGaty4cTp69KiOHj0qm82mFi1aaNWqVZKkU6dOaefOnTp//rx27dolSYqNjdV9992nEiVKKCMjQ507d9bJkycVGxurmJgY/f777/r73//uUMvevXs1f/58ffXVV9me9jhz5kx1795dM2bMUI8ePfK0T86cOaMOHTpo+fLl2rRpk9q1a6dOnTrp4MGDkqQ+ffpo586dWr9+vTXPpk2btGXLFj311FOSpBkzZmjUqFF6/fXXtXPnTr3xxht65ZVXNH36dId1vfTSS/rHP/6hnTt3Kjw8XFFRUUpNTdXq1au1detWvfXWW/Ly8srTdgAAbi13ZxcAALj9/e1vf1O9evU0evRo/ec//8kyffz48erRo4d1U5C7775bkydPVsuWLTV16lSVLl1abm5u8vb2lr+/vzVfq1at9PHHH0uSVq9erXvvvVf+/v5atWqVatSooVWrVqlly5aSpOXLl2vr1q3av3+/goKCJElffPGFatWqpfXr1+u+++6TdPlUyS+++ELlypXLUueHH36of/3rX/r222+t5eZF3bp1VbduXev9q6++qgULFuibb77RoEGDFBgYqPDwcE2bNs2qa9q0aWrZsqWqVq0qSRo9erTeeecdPfLII5KkKlWqaMeOHfr4448VGRlpLXvIkCFWH+ny0ceuXbsqNDRUkqzlAQAKP468AQBuibfeekvTp0/Xzp07s0zbvHmzoqOj5eXlZb3Cw8OVkZGh/fv3X3OZLVu21I4dO3T8+HHFxsaqVatWatWqlVatWqW0tDStW7dOrVq1kiTt3LlTQUFBVnCTpJCQEPn6+jrUVKlSpWyD27x58zR06FDFxMTcVHCTLh95e+GFF1SzZk35+vrKy8tLO3futI68SdLTTz+tL7/8UhcuXNDFixc1c+ZM9enTR5J09uxZ7du3T3379nXYZ6+99pr27dvnsK6GDRs6vH/uuef02muvqWnTpho9erS2bNlyU9sCALh1CG8AgFuiRYsWCg8P18iRI7NMO3PmjJ599lnFx8dbr82bN2vPnj2qVq3aNZcZGhqq0qVLKzY21iG8xcbGav369UpLS9P999+fqzpLliyZbfu9996rcuXK6fPPP5cxJlfLvNoLL7ygBQsW6I033tCaNWsUHx+v0NBQhxukdOrUSZ6enlqwYIG+/fZbpaWl6dFHH5V0eX9J0qeffuqwz7Zt26affvrputvTr18//f777+rZs6e2bt2qhg0b6v3337+p7QEA3BqcNgkAuGXefPNN1atXT9WrV3dor1+/vnbs2KHg4OBrzuvh4aH09HSHNpvNpubNm+vrr7/W9u3b1axZM5UoUUKpqan6+OOP1bBhQyu81KxZU4cOHdKhQ4eso287duxQUlKSQkJCblh7tWrV9M4776hVq1Zyc3PTBx98kNvNt/z444/q3bu3/va3v0m6HMYOHDjg0Mfd3V2RkZGaNm2aPDw81K1bNxUvXlyS5Ofnp4CAAP3+++95uu4uKChI/fv3V//+/TVy5Eh9+umnGjx4cJ63BwBwaxDeAAC3TGhoqHr06KHJkyc7tI8YMUJNmjTRoEGD1K9fP5UsWVI7duxQTEyMFZIqV66s1atXq1u3bvL09FTZsmUlXb7u7fnnn1fDhg2tG2+0aNFCM2bM0PDhw611tGnTxlr/pEmTdOnSJQ0cOFAtW7bMcmrhtdxzzz1auXKlWrVqJXd39xs+d2737t1Z2mrVqqW7775bX331lTp16iSbzaZXXnlFGRkZWfr269dPNWvWlHQ58F1p7Nixeu655+Tj46N27dopNTVVv/76q06dOqVhw4Zds6YhQ4aoffv2uueee3Tq1CmtXLnSWgcAoHDjtEkAwC01bty4LEGlTp06io2N1W+//abmzZvr3nvv1ahRoxQQEOAw34EDB1StWjWHa9Jatmyp9PR069o26XKgu7rNZrPp66+/VqlSpdSiRQu1adNGVatW1ezZs3NVf/Xq1bVixQp9+eWXev7556/bt1u3brr33nsdXomJiXr33XdVqlQp3X///erUqZPCw8NVv379LPPffffduv/++1WjRg01btzYYVq/fv302Wefadq0aQoNDVXLli0VHR2tKlWqXLem9PR0RUVFqWbNmmrXrp3uueceh0cMAAAKL5u52RP3AQBAgTDG6O6779bAgQOvezQNAHBn4LRJAAAKoePHj2vWrFlKSEiwnu0GALizEd4AACiEypcvr7Jly+qTTz5RqVKlnF0OAKAQILwBAFAIcVUDAOBq3LAEAAAAAFwA4Q0AAAAAXADhDQAAAABcAOENAAAAAFwA4Q0AAAAAXADhDQAAAABcAOENAAAAAFwA4Q0AAAAAXMD/A+rVYcrBq9R7AAAAAElFTkSuQmCC", + "text/plain": [ + "
" + ] + }, + "metadata": {}, + "output_type": "display_data" + } + ], + "source": [ + "layers_updated = list(cycles_dict_updated.keys())\n", + "cycles_updated = list(cycles_dict_updated.values())\n", + "fig = plt.figure(figsize = (10, 5))\n", + "plt.bar(layers_updated, cycles_updated, color ='blue', width = 0.3)\n", + "plt.xlabel(\"Network Layers\")\n", + "plt.ylabel(\"Clock Cycles\")\n", + "plt.title(\"Estimated clock cycles for each network layer\")\n", + "plt.show()" + ] + }, + { + "cell_type": "code", + "execution_count": 19, + "metadata": {}, + "outputs": [], + "source": [ + "res_dict_updated = []\n", + "res_dict_updated = res_estimation(model)" + ] + }, + { + "cell_type": "code", + "execution_count": 20, + "metadata": {}, + "outputs": [ + { + "data": { + "image/png": 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m1atXa+TIkVq7dq3Onj3rND41NdVa15Xs3btXP/74o0qUKJFrf/YNGA4dOqSSJUvK19fXqf+uu+66xt4VrIK6BX7x4sXVtGlTffLJJxo7dqyki6cxurm5qX379ta47GuEJk+erAMHDigzM9Pqy8spZnmxd+9epaamKjg4ONf+7PcgJiZGHTp00OjRozVhwgQ1adJEDz/8sP72t7/J09OzQGoZM2aM2rVrpypVqujuu+9Wy5Yt1a1bN9WoUUOStG/fPhljNHz4cA0fPvyK9ZYuXVqHDh1SvXr1cvTfyGfm0KFDV1xH1apV9f333zu1ubm5qUyZMtdc7++//66TJ09q6tSpmjp1aq5jst8HSZo5c6Zef/117dq1yykkX3pX1/3796tUqVIKCgq65vYv/xkgSUWLFs1xjWFely9atKgkWctnB+2rnXqcmppqLZcbV1dXRUdHa9WqVZIuBrPGjRurUaNGyszM1Lp16xQSEqKUlBSnYHalz0H2Kd6HDh3S3XffbbXndmfcbN26dZObm5t27typ0NDQK467lsOHD2vEiBH6/PPPc7zGl/5Bq3nz5ipZsqRmzZqlpk2bKisrSx999JHatWsnPz8/Sdf32l5tHwHkD8EMKKSCg4O1bds2ff3111q8eLEWL16shIQEde/eXTNnzrzu9bq6uuar3fz/axL279+vpk2bqmrVqnrjjTcUFhYmDw8Pffnll5owYUKebrKQlZWl5s2b6/nnn8+1v0qVKnncixvn6enpdPH9pbJD56VHSW5U586d1bNnT23btk1RUVH65JNP1LRpU+u6GuniRf7Dhw9Xr169NHbsWAUFBcnFxUUDBgy45uvrcDhyvX7k0nAnXXwPgoODNWvWrFzXkx2as78Hbt26dfriiy/09ddfq1evXnr99de1bt26HKE5Ly6v5b777tP+/fv12Wef6ZtvvtF7772nCRMm6J133lGfPn2sfR48eLBiY2NzXWd+vl7iZrv0iOfVZO/X448/fsVfsLPD6YcffqgePXro4Ycf1pAhQxQcHCxXV1eNHz9e+/fvv646rzXXb3T57P375z//6XQN3KXy8vlp1KiRXn75ZZ07d06rVq3SP/7xDwUGBuruu+/WqlWrrGtXLw1m+XW1axDbt2+vDz74QG+++abGjx9/XevPzMy0rk974YUXVLVqVfn4+OjXX39Vjx49nOa1q6ur/va3v2natGmaPHmyVq9erd9++83p7q/X89rm5TpLAHlDMAMKMQ8PD7Vt21Zt27ZVVlaWnn76ab377rsaPny4KlWqdEu/1PiLL75Qenq6Pv/8c6e/mOd2d7gr1VWxYkWdPn36mt8TVa5cOS1dulSnT592+iUjv3dDu9Y2rrS+7PbrPXUpNw8//LD69u1rnc64Z88eDRs2zGnMvHnzdP/992v69OlO7SdPnnQKcLkpWrRorqeiZR/1yVaxYkV9++23atiwYZ5+Yatfv77q16+vl19+WbNnz1bXrl01Z84c9enT56q1XH4HzfPnz+vo0aM5xgYFBalnz57q2bOnTp8+rfvuu0+jRo1Snz59VKFCBUmSu7t7nj4zuZ0SeSOfmez3f/fu3XrggQdyrPd6Px8lSpSQn5+fMjMzr7lf8+bNU4UKFbRgwQKneXX5KYsVK1bU119/rZSUlDwdNbuZsk+T9Pf3v+b+Xe1nWOPGjXX+/Hl99NFH+vXXX60Adt9991nBrEqVKlZAk648r3ft2mX159UzzzyjSpUqacSIEQoICNDQoUPzvGy27du3a8+ePZo5c6a6d+9utV/pFPXu3bvr9ddf1xdffKHFixerRIkSTn+UyM9rC6DgcY0ZUEgdP37c6bmLi4v1V/Ts29hnfx/NrbiNfPZfyS/9q3pqaqoSEhJyjPXx8cm1pk6dOmnt2rX6+uuvc/SdPHnSup7twQcfVEZGhtOt+DMzM/X222/f6G5YHnzwQa1bt06bN2/OUcesWbMUFRV1Q6cvXS4wMFCxsbH65JNPNGfOHHl4eOjhhx92GuPq6prjqMXcuXNz3Jo9NxUrVtSuXbv0+++/W20//PBDjltod+rUSZmZmdYplZfKyMiw3rcTJ07kqCX7L/SXf41CbrVkXxuUberUqTmOmF3+Gff19VWlSpWs9QcHB6tJkyZ69913cw11l+5r9vu5YcMGp/4rHRnMizp16ig4OFjvvPOO0z4vXrxYO3fuVOvWra9rva6ururQoYPmz5+vn376KUf/pfuV27xbv3691q5d67RMhw4dZIzJ9WsZ8nokrKDUrl1bFStW1L/+9S+dPn06R/+l+3e1n2H16tWTu7u7Xn31VQUFBal69eqSLga2devWacWKFTmOlj344IPasGGD0+tz5swZTZ06VeXLl1dERES+9mX48OEaPHiwhg0bluOrQfIit/fPGGN97cnlatSooRo1aui9997T/Pnz1blzZ7m5/e9v9Pl5bQEUPI6YAXeoxYsXW3/FvVSDBg1UoUIF9enTRykpKXrggQdUpkwZHTp0SG+//baioqKs6yWioqLk6uqqV199VampqfL09LS+Z6ygtWjRwjqC17dvX50+fVrTpk1TcHBwjl+aa9eurSlTpuill15SpUqVFBwcrAceeEBDhgzR559/rjZt2qhHjx6qXbu2zpw5o+3bt2vevHk6ePCgihcvrrZt26phw4YaOnSoDh48qIiICC1YsCBPNxi51Pz583N9jePi4jR06FDNnTtX9913n/r27auqVavqt99+04wZM3T06NFcA+eNeuyxx/T4449r8uTJio2NzfFlxm3atNGYMWPUs2dPNWjQQNu3b9esWbOsI0dX06tXL73xxhuKjY1V7969dezYMb3zzjuqXr2603czxcTEqG/fvho/fry2bdumFi1ayN3dXXv37tXcuXP15ptv6tFHH9XMmTM1efJkPfLII6pYsaJOnTqladOmyd/fXw8++OBVa+nTp4+eeuopdejQQc2bN9cPP/ygr7/+OsdRv4iICDVp0kS1a9dWUFCQNm3apHnz5ql///7WmEmTJqlRo0aKjIzUE088oQoVKig5OVlr167VL7/8Yn3H2/PPP6///Oc/atmypZ577jnrdvnlypXTjz/+eM3XLzfZoaBnz56KiYlRly5drNvlly9fXgMHDryu9UoXbzm/fPly1atXT0888YQiIiKUkpKiLVu26Ntvv1VKSoqki5+JBQsW6JFHHlHr1q114MABvfPOO4qIiHD6xfz+++9Xt27d9NZbb2nv3r1q2bKlsrKytGrVKt1///1Or+nN5uLiovfee0+tWrVS9erV1bNnT5UuXVq//vqrli9fLn9/f33xxReSLv6skC5+ZUHnzp3l7u6utm3bysfHR0WKFFHt2rW1bt066zvMpItHzM6cOaMzZ87kCGZDhw7VRx99pFatWunZZ59VUFCQZs6cqQMHDmj+/Pl5OtX0cv/85z+Vmpqq+Ph4+fn55euL5atWraqKFStq8ODB+vXXX+Xv76/58+df9Xq+7t27a/DgwZKUY1v5eW0B3AS3+jaQAG6uq90uX5fcFnnevHmmRYsWJjg42Hh4eJiyZcuavn37mqNHjzqtb9q0aaZChQrG1dXV6TbNV7pd/uW3kM/tNuHG/O9Wy7///rvV9vnnn5saNWoYLy8vU758efPqq6+a999/P8ftrpOSkkzr1q2Nn5+fkeRUx6lTp8ywYcNMpUqVjIeHhylevLhp0KCB+de//uV0G//jx4+bbt26GX9/fxMQEGC6detmtm7dmq/b5V/pkX0r7V9++cX06dPHlC5d2ri5uZmgoCDTpk0bs27duquuP7+3y8+WlpZmvL29jSTz4Ycf5ug/d+6c+fvf/25KlixpvL29TcOGDc3atWtzvJe53S7fGGM+/PBDU6FCBePh4WGioqLM119/neN2+dmmTp1qateubby9vY2fn5+JjIw0zz//vPntt9+MMRdv092lSxdTtmxZ4+npaYKDg02bNm3Mpk2brrmfmZmZ5oUXXjDFixc3RYoUMbGxsWbfvn05bpf/0ksvmbp165rAwEDj7e1tqlatal5++WWnz4Exxuzfv990797dhIaGGnd3d1O6dGnTpk0bM2/ePKdxP/74o4mJiTFeXl6mdOnSZuzYsWb69OnXfbv8bB9//LGpVauW8fT0NEFBQaZr167ml19+cRoTFxdnfHx8rvnaXCo5OdnEx8ebsLAw4+7ubkJDQ03Tpk3N1KlTrTFZWVlm3Lhxply5csbT09PUqlXLLFq0KNf3NSMjw/zzn/80VatWNR4eHqZEiRKmVatWZvPmzdYYXeFrIi5/b3JzpZ8hV/o8bt261bRv394UK1bMeHp6mnLlyplOnTqZpUuXOo0bO3asKV26tHFxccnxXg0ZMsRIMq+++qrTMpUqVTKSzP79+3PUuX//fvPoo4+awMBA4+XlZerWrWsWLVqUp30xJvfPQmZmpunSpYtxc3MzCxcuvOZrdOnt8hMTE02zZs2Mr6+vKV68uHniiSesryjI7WfZ0aNHjaurq6lSpcoVt5OX1za3n+EAbozDGL4NEAAAoDD4448/VLJkSY0YMeKKdyMFYA+uMQMAACgkZsyYoczMTHXr1s3uUgBchmvMAAAA7nDLli1TYmKiXn75ZT388MMqX7683SUBuAynMgIAANzhmjRpojVr1qhhw4b68MMPVbp0abtLAnAZghkAAAAA2IxrzAAAAADAZgQzAAAAALAZN/+QlJWVpd9++01+fn7WF0wCAAAAKHyMMTp16pRKlSp1XV8cf70IZpJ+++03hYWF2V0GAAAAgNvEkSNHVKZMmVu2PYKZJD8/P0kXX3x/f3+bqwEAAABgl7S0NIWFhVkZ4VYhmEnW6Yv+/v4EMwAAAAC3/BInbv4BAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM1sD2a//vqrHn/8cRUrVkze3t6KjIzUpk2brH5jjEaMGKGSJUvK29tbzZo10969e53WkZKSoq5du8rf31+BgYHq3bu3Tp8+fat3BQAAAACui63B7MSJE2rYsKHc3d21ePFiJSYm6vXXX1fRokWtMa+99preeustvfPOO1q/fr18fHwUGxurc+fOWWO6du2qHTt2aMmSJVq0aJFWrlypJ5980o5dAgAAAIB8cxhjjF0bHzp0qFavXq1Vq1bl2m+MUalSpfT3v/9dgwcPliSlpqYqJCREM2bMUOfOnbVz505FRERo48aNqlOnjiTpq6++0oMPPqhffvlFpUqVumYdaWlpCggIUGpqKl8wDQAAABRidmUDW4+Yff7556pTp446duyo4OBg1apVS9OmTbP6Dxw4oKSkJDVr1sxqCwgIUL169bR27VpJ0tq1axUYGGiFMklq1qyZXFxctH79+ly3m56errS0NKcHAAAAANjF1mD2888/a8qUKapcubK+/vpr9evXT88++6xmzpwpSUpKSpIkhYSEOC0XEhJi9SUlJSk4ONip383NTUFBQdaYy40fP14BAQHWIywsrKB3DQAAAADyzNZglpWVpXvuuUfjxo1TrVq19OSTT+qJJ57QO++8c1O3O2zYMKWmplqPI0eO3NTtAQAAAMDV2BrMSpYsqYiICKe2atWq6fDhw5Kk0NBQSVJycrLTmOTkZKsvNDRUx44dc+rPyMhQSkqKNeZynp6e8vf3d3oAAAAAgF1sDWYNGzbU7t27ndr27NmjcuXKSZLCw8MVGhqqpUuXWv1paWlav369oqOjJUnR0dE6efKkNm/ebI1ZtmyZsrKyVK9evVuwFwAAAABwY9zs3PjAgQPVoEEDjRs3Tp06ddKGDRs0depUTZ06VZLkcDg0YMAAvfTSS6pcubLCw8M1fPhwlSpVSg8//LCki0fYWrZsaZ0CeeHCBfXv31+dO3fO0x0ZAQAAAMButt4uX5IWLVqkYcOGae/evQoPD9egQYP0xBNPWP3GGI0cOVJTp07VyZMn1ahRI02ePFlVqlSxxqSkpKh///764osv5OLiog4dOuitt96Sr69vnmq43W6X7xjtsLsEW5mRtn4kAQAAUIjZlQ1sD2a3A4LZ7YVgBgAAALsUyu8xAwAAAAAQzAAAAADAdgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALCZrcFs1KhRcjgcTo+qVata/efOnVN8fLyKFSsmX19fdejQQcnJyU7rOHz4sFq3bq0iRYooODhYQ4YMUUZGxq3eFQAAAAC4bm52F1C9enV9++231nM3t/+VNHDgQP33v//V3LlzFRAQoP79+6t9+/ZavXq1JCkzM1OtW7dWaGio1qxZo6NHj6p79+5yd3fXuHHjbvm+AAAAAMD1sD2Yubm5KTQ0NEd7amqqpk+frtmzZ+uBBx6QJCUkJKhatWpat26d6tevr2+++UaJiYn69ttvFRISoqioKI0dO1YvvPCCRo0aJQ8Pj1u9OwAAAACQb7ZfY7Z3716VKlVKFSpUUNeuXXX48GFJ0ubNm3XhwgU1a9bMGlu1alWVLVtWa9eulSStXbtWkZGRCgkJscbExsYqLS1NO3bsuOI209PTlZaW5vQAAAAAALvYGszq1aunGTNm6KuvvtKUKVN04MABNW7cWKdOnVJSUpI8PDwUGBjotExISIiSkpIkSUlJSU6hLLs/u+9Kxo8fr4CAAOsRFhZWsDsGAAAAAPlg66mMrVq1sv5do0YN1atXT+XKldMnn3wib2/vm7bdYcOGadCgQdbztLQ0whkAAAAA29h+KuOlAgMDVaVKFe3bt0+hoaE6f/68Tp486TQmOTnZuiYtNDQ0x10as5/ndt1aNk9PT/n7+zs9AAAAAMAut1UwO336tPbv36+SJUuqdu3acnd319KlS63+3bt36/Dhw4qOjpYkRUdHa/v27Tp27Jg1ZsmSJfL391dERMQtrx8AAAAAroetpzIOHjxYbdu2Vbly5fTbb79p5MiRcnV1VZcuXRQQEKDevXtr0KBBCgoKkr+/v5555hlFR0erfv36kqQWLVooIiJC3bp102uvvaakpCS9+OKLio+Pl6enp527BgAAAAB5Zmsw++WXX9SlSxcdP35cJUqUUKNGjbRu3TqVKFFCkjRhwgS5uLioQ4cOSk9PV2xsrCZPnmwt7+rqqkWLFqlfv36Kjo6Wj4+P4uLiNGbMGLt2CQAAAADyzWGMMXYXYbe0tDQFBAQoNTX1trjezDHaYXcJtjIjC/1HEgAAADaxKxvcVteYAQAAAEBhRDADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZrdNMHvllVfkcDg0YMAAq+3cuXOKj49XsWLF5Ovrqw4dOig5OdlpucOHD6t169YqUqSIgoODNWTIEGVkZNzi6gEAAADg+t0WwWzjxo169913VaNGDaf2gQMH6osvvtDcuXO1YsUK/fbbb2rfvr3Vn5mZqdatW+v8+fNas2aNZs6cqRkzZmjEiBG3ehcAAAAA4LrZHsxOnz6trl27atq0aSpatKjVnpqaqunTp+uNN97QAw88oNq1ayshIUFr1qzRunXrJEnffPONEhMT9eGHHyoqKkqtWrXS2LFjNWnSJJ0/f96uXQIAAACAfLE9mMXHx6t169Zq1qyZU/vmzZt14cIFp/aqVauqbNmyWrt2rSRp7dq1ioyMVEhIiDUmNjZWaWlp2rFjxxW3mZ6errS0NKcHAAAAANjFzc6Nz5kzR1u2bNHGjRtz9CUlJcnDw0OBgYFO7SEhIUpKSrLGXBrKsvuz+65k/PjxGj169A1WDwAAAAAFw7YjZkeOHNFzzz2nWbNmycvL65Zue9iwYUpNTbUeR44cuaXbBwAAAIBL2RbMNm/erGPHjumee+6Rm5ub3NzctGLFCr311ltyc3NTSEiIzp8/r5MnTzotl5ycrNDQUElSaGhojrs0Zj/PHpMbT09P+fv7Oz0AAAAAwC62BbOmTZtq+/bt2rZtm/WoU6eOunbtav3b3d1dS5cutZbZvXu3Dh8+rOjoaElSdHS0tm/frmPHjlljlixZIn9/f0VERNzyfQIAAACA62HbNWZ+fn66++67ndp8fHxUrFgxq713794aNGiQgoKC5O/vr2eeeUbR0dGqX7++JKlFixaKiIhQt27d9NprrykpKUkvvvii4uPj5enpecv3CQAAAACuh603/7iWCRMmyMXFRR06dFB6erpiY2M1efJkq9/V1VWLFi1Sv379FB0dLR8fH8XFxWnMmDE2Vg0AAAAA+eMwxhi7i7BbWlqaAgIClJqaeltcb+YY7bC7BFuZkYX+IwkAAACb2JUNbP8eMwAAAAAo7K7rVMa9e/dq+fLlOnbsmLKyspz6RowYUSCFAQAAAEBhke9gNm3aNPXr10/FixdXaGioHI7/nXbncDgIZgBuO5wezOnBKHjMK+YVgIKV72D20ksv6eWXX9YLL7xwM+oBAAAAgEIn39eYnThxQh07drwZtQAAAABAoZTvYNaxY0d98803N6MWAAAAACiU8n0qY6VKlTR8+HCtW7dOkZGRcnd3d+p/9tlnC6w4AAAAACgM8h3Mpk6dKl9fX61YsUIrVqxw6nM4HAQzAAAAAMinfAezAwcO3Iw6AAAAAKDQuqEvmDbGyBhuFwsAAAAAN+K6gtkHH3ygyMhIeXt7y9vbWzVq1NB//vOfgq4NAAAAAAqFfJ/K+MYbb2j48OHq37+/GjZsKEn6/vvv9dRTT+mPP/7QwIEDC7xIAAAAALiT5TuYvf3225oyZYq6d+9utT300EOqXr26Ro0aRTADAAAAgHzK96mMR48eVYMGDXK0N2jQQEePHi2QogAAAACgMMl3MKtUqZI++eSTHO0ff/yxKleuXCBFAQAAAEBhku9TGUePHq3HHntMK1eutK4xW716tZYuXZprYAMAAAAAXF2+j5h16NBB69evV/HixbVw4UItXLhQxYsX14YNG/TII4/cjBoBAAAA4I6W7yNmklS7dm19+OGHBV0LAAAAABRKeQpmaWlp8vf3t/59NdnjAAAAAAB5k6dgVrRoUR09elTBwcEKDAyUw+HIMcYYI4fDoczMzAIvEgAAAADuZHkKZsuWLVNQUJAkafny5Te1IAAAAAAobPIUzGJiYqx/h4eHKywsLMdRM2OMjhw5UrDVAQAAAEAhkO+7MoaHh+v333/P0Z6SkqLw8PACKQoAAAAACpN8B7Psa8kud/r0aXl5eRVIUQAAAABQmOT5dvmDBg2SJDkcDg0fPlxFihSx+jIzM7V+/XpFRUUVeIEAAAAAcKfLczDbunWrpItHzLZv3y4PDw+rz8PDQzVr1tTgwYMLvkIAAAAAuMPlOZhl342xZ8+eevPNN/m+MgAAAAAoIHkOZtkSEhJuRh0AAAAAUGjlO5hJ0qZNm/TJJ5/o8OHDOn/+vFPfggULCqQwAAAAoLBwjM55c73CxIw0dpdgu3zflXHOnDlq0KCBdu7cqU8//VQXLlzQjh07tGzZMgUEBNyMGgEAAADgjpbvYDZu3DhNmDBBX3zxhTw8PPTmm29q165d6tSpk8qWLXszagQAAACAO1q+g9n+/fvVunVrSRfvxnjmzBk5HA4NHDhQU6dOLfACAQAAAOBOl+9gVrRoUZ06dUqSVLp0af3000+SpJMnT+rs2bMFWx0AAAAAFAL5vvnHfffdpyVLligyMlIdO3bUc889p2XLlmnJkiVq2rTpzagRAAAAAO5o+Q5m//73v3Xu3DlJ0j/+8Q+5u7trzZo16tChg1588cUCLxAAAAAA7nT5DmZBQUHWv11cXDR06NACLQgAAAAACpt8X2O2ZcsWbd++3Xr+2Wef6eGHH9b//d//5fhOMwAAAADAteU7mPXt21d79uyRJP3888967LHHVKRIEc2dO1fPP/98gRcIAAAAAHe6fAezPXv2KCoqSpI0d+5cxcTEaPbs2ZoxY4bmz59f0PUBAAAAwB0v38HMGKOsrCxJ0rfffqsHH3xQkhQWFqY//vijYKsDAAAAgEIg38GsTp06eumll/Sf//xHK1assL5s+sCBAwoJCSnwAgEAAADgTpfvYDZx4kRt2bJF/fv31z/+8Q9VqlRJkjRv3jw1aNCgwAsEAAAAgDtdvm+XX6NGDae7Mmb75z//KVdX1wIpCgAAAAAKk3wHsyvx8vIqqFUBAAAAQKGSp2AWFBSkPXv2qHjx4ipatKgcDscVx6akpBRYcQAAAABQGOQpmE2YMEF+fn6SLl5jBgAAAAAoOHkKZnFxcbn+GwAAAABw4/IUzNLS0vK8Qn9//+suBgAAAAAKozwFs8DAwKteVyZd/OJph8OhzMzMAikMAAAAAAqLPAWz5cuX3+w6AAAAAKDQylMwi4mJudl1AAAAAECh5ZKXQT/++KOysrKsf1/tkR9TpkxRjRo15O/vL39/f0VHR2vx4sVW/7lz5xQfH69ixYrJ19dXHTp0UHJystM6Dh8+rNatW6tIkSIKDg7WkCFDlJGRka86AAAAAMBOeTpiFhUVpaSkJAUHBysqKkoOh0PGmBzj8nuNWZkyZfTKK6+ocuXKMsZo5syZateunbZu3arq1atr4MCB+u9//6u5c+cqICBA/fv3V/v27bV69WpJUmZmplq3bq3Q0FCtWbNGR48eVffu3eXu7q5x48bluQ4AAAAAsFOegtmBAwdUokQJ698FpW3btk7PX375ZU2ZMkXr1q1TmTJlNH36dM2ePVsPPPCAJCkhIUHVqlXTunXrVL9+fX3zzTdKTEzUt99+q5CQEEVFRWns2LF64YUXNGrUKHl4eBRYrQAAAABws+TpVMZy5cpZd2U8dOiQSpcurXLlyjk9SpcurUOHDl13IZmZmZozZ47OnDmj6Ohobd68WRcuXFCzZs2sMVWrVlXZsmW1du1aSdLatWsVGRmpkJAQa0xsbKzS0tK0Y8eOK24rPT1daWlpTg8AAAAAsEuegtml7r//fqWkpORoT01N1f3335/vArZv3y5fX195enrqqaee0qeffqqIiAglJSXJw8NDgYGBTuNDQkKUlJQkSUpKSnIKZdn92X1XMn78eAUEBFiPsLCwfNcNAAAAAAUl38Es+/vKLnf8+HH5+Pjku4C77rpL27Zt0/r169WvXz/FxcUpMTEx3+vJj2HDhik1NdV6HDly5KZuDwAAAACuJk/XmElS+/btJV28wUePHj3k6elp9WVmZurHH39UgwYN8l2Ah4eHKlWqJEmqXbu2Nm7cqDfffFOPPfaYzp8/r5MnTzodNUtOTlZoaKgkKTQ0VBs2bHBaX/ZdG7PH5MbT09OpfgAAAACwU56PmGWf9meMkZ+fn9OpgKGhoXryySf14Ycf3nBBWVlZSk9PV+3ateXu7q6lS5dafbt379bhw4cVHR0tSYqOjtb27dt17Ngxa8ySJUvk7++viIiIG64FAAAAAG6FPB8xS0hIkCSVL19egwcPvq7TFi83bNgwtWrVSmXLltWpU6c0e/Zsfffdd/r6668VEBCg3r17a9CgQQoKCpK/v7+eeeYZRUdHq379+pKkFi1aKCIiQt26ddNrr72mpKQkvfjii4qPj+eIGAAAAIC/jDwHs2wjR44ssI0fO3ZM3bt319GjRxUQEKAaNWro66+/VvPmzSVJEyZMkIuLizp06KD09HTFxsZq8uTJ1vKurq5atGiR+vXrp+joaPn4+CguLk5jxowpsBoBAAAA4GbLczArWrRorjf9CAgIUJUqVTR48GArUOXV9OnTr9rv5eWlSZMmadKkSVccU65cOX355Zf52i4AAAAA3E7yHMwmTpyYa/vJkye1efNmtWnTRvPmzcvxpdEAAAAAgKvLczCLi4u7an9UVJTGjx9PMAMAAACAfMr395hdSZs2bbRr166CWh0AAAAAFBoFFszS09Pl4eFRUKsDAAAAgEKjwILZ9OnTFRUVVVCrAwAAAIBCI8/XmA0aNCjX9tTUVG3ZskV79uzRypUrC6wwAAAAACgs8hzMtm7dmmu7v7+/mjdvrgULFig8PLzACgMAAACAwiLPwWz58uU3sw4AAAAAKLQK7BozAAAAAMD1IZgBAAAAgM0IZgAAAABgM4IZAAAAANgsz8GsV69eOnXq1M2sBQAAAAAKpTwHs5kzZ+rPP/+8mbUAAAAAQKGU52BmjLmZdQAAAABAoZXn7zGTpFOnTsnLy+uqY/z9/W+oIAAAAAAobPIVzKpUqXLFPmOMHA6HMjMzb7goAAAAAChM8hXM5s2bp6CgoJtVCwAAAAAUSvkKZg0bNlRwcPDNqgUAAAAACiW+xwwAAAAAbJbnYFauXDm5urrezFoAAAAAoFDK86mMBw4cuJl1AAAAAEChledgVrRoUTkcjhztAQEBqlKligYPHqzmzZsXaHEAAAAAUBjkOZhNmDAh12B28uRJbd68WW3atNG8efPUtm3bAi0QAAAAAO50eQ5mPXr0uGp/VFSUxo8fTzADAAAAgHwqsLsytmnTRrt27Sqo1QEAAABAoVFgwSw9PV0eHh4FtToAAAAAKDQKLJhNnz5dUVFRBbU6AAAAACg08nyN2aBBg3JtT01N1ZYtW7Rnzx6tXLmywAoDAAAAgMIiz8Fs69atubb7+/urefPmWrBggcLDwwusMAAAAAAoLPIczJYvX37V/l9++UVPPvmkpk6desNFAQAAAEBhUmDXmB0/flzTp08vqNUBAAAAQKFRYMEMAAAAAHB9CGYAAAAAYDOCGQAAAADYLM83/2jfvv1V+0+ePHmjtQAAAABAoZTnYBYQEHDN/u7du99wQQAAAABQ2OQ5mCUkJNzMOgAAAACg0OIaMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwma3BbPz48br33nvl5+en4OBgPfzww9q9e7fTmHPnzik+Pl7FihWTr6+vOnTooOTkZKcxhw8fVuvWrVWkSBEFBwdryJAhysjIuJW7AgAAAADXzdZgtmLFCsXHx2vdunVasmSJLly4oBYtWujMmTPWmIEDB+qLL77Q3LlztWLFCv32229q37691Z+ZmanWrVvr/PnzWrNmjWbOnKkZM2ZoxIgRduwSAAAAAOSbm50b/+qrr5yez5gxQ8HBwdq8ebPuu+8+paamavr06Zo9e7YeeOABSVJCQoKqVaumdevWqX79+vrmm2+UmJiob7/9ViEhIYqKitLYsWP1wgsvaNSoUfLw8LBj1wAAAAAgz26ra8xSU1MlSUFBQZKkzZs368KFC2rWrJk1pmrVqipbtqzWrl0rSVq7dq0iIyMVEhJijYmNjVVaWpp27NiR63bS09OVlpbm9AAAAAAAu9w2wSwrK0sDBgxQw4YNdffdd0uSkpKS5OHhocDAQKexISEhSkpKssZcGsqy+7P7cjN+/HgFBARYj7CwsALeGwAAAADIu9smmMXHx+unn37SnDlzbvq2hg0bptTUVOtx5MiRm75NAAAAALgSW68xy9a/f38tWrRIK1euVJkyZaz20NBQnT9/XidPnnQ6apacnKzQ0FBrzIYNG5zWl33Xxuwxl/P09JSnp2cB7wUAAAAAXB9bj5gZY9S/f399+umnWrZsmcLDw536a9euLXd3dy1dutRq2717tw4fPqzo6GhJUnR0tLZv365jx45ZY5YsWSJ/f39FRETcmh0BAAAAgBtg6xGz+Ph4zZ49W5999pn8/Pysa8ICAgLk7e2tgIAA9e7dW4MGDVJQUJD8/f31zDPPKDo6WvXr15cktWjRQhEREerWrZtee+01JSUl6cUXX1R8fDxHxQAAAAD8JdgazKZMmSJJatKkiVN7QkKCevToIUmaMGGCXFxc1KFDB6Wnpys2NlaTJ0+2xrq6umrRokXq16+foqOj5ePjo7i4OI0ZM+ZW7QYAAAAA3BBbg5kx5ppjvLy8NGnSJE2aNOmKY8qVK6cvv/yyIEsDAAAAgFvmtrkrIwAAAAAUVgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbGZrMFu5cqXatm2rUqVKyeFwaOHChU79xhiNGDFCJUuWlLe3t5o1a6a9e/c6jUlJSVHXrl3l7++vwMBA9e7dW6dPn76FewEAAAAAN8bWYHbmzBnVrFlTkyZNyrX/tdde01tvvaV33nlH69evl4+Pj2JjY3Xu3DlrTNeuXbVjxw4tWbJEixYt0sqVK/Xkk0/eql0AAAAAgBvmZufGW7VqpVatWuXaZ4zRxIkT9eKLL6pdu3aSpA8++EAhISFauHChOnfurJ07d+qrr77Sxo0bVadOHUnS22+/rQcffFD/+te/VKpUqVu2LwAAAABwvW7ba8wOHDigpKQkNWvWzGoLCAhQvXr1tHbtWknS2rVrFRgYaIUySWrWrJlcXFy0fv36K647PT1daWlpTg8AAAAAsMttG8ySkpIkSSEhIU7tISEhVl9SUpKCg4Od+t3c3BQUFGSNyc348eMVEBBgPcLCwgq4egAAAADIu9s2mN1Mw4YNU2pqqvU4cuSI3SUBAAAAKMRu22AWGhoqSUpOTnZqT05OtvpCQ0N17Ngxp/6MjAylpKRYY3Lj6ekpf39/pwcAAAAA2OW2DWbh4eEKDQ3V0qVLrba0tDStX79e0dHRkqTo6GidPHlSmzdvtsYsW7ZMWVlZqlev3i2vGQAAAACuh613ZTx9+rT27dtnPT9w4IC2bdumoKAglS1bVgMGDNBLL72kypUrKzw8XMOHD1epUqX08MMPS5KqVaumli1b6oknntA777yjCxcuqH///urcuTN3ZAQAAADwl2FrMNu0aZPuv/9+6/mgQYMkSXFxcZoxY4aef/55nTlzRk8++aROnjypRo0a6auvvpKXl5e1zKxZs9S/f381bdpULi4u6tChg956661bvi8AAAAAcL1sDWZNmjSRMeaK/Q6HQ2PGjNGYMWOuOCYoKEizZ8++GeUBAAAAwC1x215jBgAAAACFBcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAm90xwWzSpEkqX768vLy8VK9ePW3YsMHukgAAAAAgT+6IYPbxxx9r0KBBGjlypLZs2aKaNWsqNjZWx44ds7s0AAAAALimOyKYvfHGG3riiSfUs2dPRURE6J133lGRIkX0/vvv210aAAAAAFyTm90F3Kjz589r8+bNGjZsmNXm4uKiZs2aae3atbkuk56ervT0dOt5amqqJCktLe3mFptX5+wuwF63zfuAOwdzyu4ScCdiXtldAu40zCm7S7Bk12KMuaXb/csHsz/++EOZmZkKCQlxag8JCdGuXbtyXWb8+PEaPXp0jvawsLCbUiPyJ+CVALtLAO4ozCmg4DGvgIJ1O86pU6dOKSDg1tX1lw9m12PYsGEaNGiQ9TwrK0spKSkqVqyYHA6HjZXZLy0tTWFhYTpy5Ij8/f3tLgf4y2NOAQWPeQUULOaUM2OMTp06pVKlSt3S7f7lg1nx4sXl6uqq5ORkp/bk5GSFhobmuoynp6c8PT2d2gIDA29WiX9J/v7+TEygADGngILHvAIKFnPqf27lkbJsf/mbf3h4eKh27dpaunSp1ZaVlaWlS5cqOjraxsoAAAAAIG/+8kfMJGnQoEGKi4tTnTp1VLduXU2cOFFnzpxRz5497S4NAAAAAK7pjghmjz32mH7//XeNGDFCSUlJioqK0ldffZXjhiC4Nk9PT40cOTLHqZ4Arg9zCih4zCugYDGnbg8Oc6vvAwkAAAAAcPKXv8YMAAAAAP7qCGYAAAAAYDOCGQAAAADYjGB2ncqXL6+JEyfaXcZfzsGDB+VwOLRt27abvi3eo78e3rPrw7zClfB+XR/mFK6G9+z6MK/ywPyFxcXFGUmmb9++OfqefvppI8nExcXlaV0HDhwwkszWrVvzNP7YsWPmzJkzeRrbpk0bExsbm2vfypUrjSTzww8/5GldV7J8+XIjyZw4ceKG1nO5s2fPmqJFi5pixYqZc+fO5WvZuLg4065dO6e2jIwMc/ToUXPhwoUCqzEhIcEEBATkaM/Pe1RQ/v3vf5ty5coZT09PU7duXbN+/fpbuv2CwLz6H+ZVQI72Wz2vVqxYYdq0aWNKlixpJJlPP/30lm27oDCn/oc5FZCj/VbPqXHjxpk6deoYX19fU6JECdOuXTuza9euW7b9gsK8+h/mVUCO9ls9ryZPnmwiIyONn5+f8fPzM/Xr1zdffvllvtfzlz9iFhYWpjlz5ujPP/+02s6dO6fZs2erbNmyBb698+fPS5JKlCihIkWK5GmZ3r17a8mSJfrll19y9CUkJKhOnTqqUaNGgdZ5vYwxysjIsJ7Pnz9f1atXV9WqVbVw4cIbXr+rq6tCQ0Pl5nbzv6khP+9RQfj44481aNAgjRw5Ulu2bFHNmjUVGxurY8eO3bIaCgrzqmAxr67fmTNnVLNmTU2aNOmWbfNmYE4VLObU9VuxYoXi4+O1bt06LVmyRBcuXFCLFi105syZW1ZDQWFeFSzm1fUrU6aMXnnlFW3evFmbNm3SAw88oHbt2mnHjh35W1EBB8ZbKjuN33333ebDDz+02mfNmmVq1Khh2rVrZ/21ZPHixaZhw4YmICDABAUFmdatW5t9+/ZZy0hyesTExDht46WXXjIlS5Y05cuXN8YYU65cOTNhwgRjzMW/VLi7u5uVK1da63v11VdNiRIlTFJSkrlw4YIJCQkxY8eOdar/1KlTxtfX10yZMsUYY8yqVatMo0aNjJeXlylTpox55plnzOnTp63x586dM88//7wpU6aM8fDwMBUrVjTvvfee9ZeeSx/Z+33u3DnzzDPPmBIlShhPT0/TsGFDs2HDBmud2X9l+fLLL80999xj3N3dzfLly63+Jk2amHfeecdMmTLFNG/ePMd78NNPP5nWrVsbPz8/4+vraxo1amT27dtnRo4cmaOm5cuXO/1VKjMz05QuXdpMnjzZaZ1btmwxDofDHDx40BhjzOuvv27uvvtuU6RIEVOmTBnTr18/c+rUKaf6L32MHDkyx3tkjDGHDh0yDz30kPHx8TF+fn6mY8eOJikpyeofOXKkqVmzpvnggw9MuXLljL+/v3nsscdMWlpajv3OTd26dU18fLz1PDMz05QqVcqMHz8+T8vfLphXzKvbaV5dSn/hI2bMKebU7TinjLl4ZEGSWbFixXUtbxfmFfPqdp5XxhhTtGhR89577+VrmTsimL3xxhumadOmVnvTpk3NhAkTnCblvHnzzPz5883evXvN1q1bTdu2bU1kZKTJzMw0xhizYcMGI8l8++235ujRo+b48ePWNnx9fU23bt3MTz/9ZH766SdjTM43fMiQIaZcuXLm5MmTZsuWLcbDw8N89tlnTv0VK1Y0WVlZVtv7779vvL29zcmTJ82+ffuMj4+PmTBhgtmzZ49ZvXq1qVWrlunRo4c1vlOnTiYsLMwsWLDA7N+/33z77bdmzpw5JiMjw8yfP99IMrt37zZHjx41J0+eNMYY8+yzz5pSpUqZL7/80uzYscPExcWZokWLWvuX/aGuUaOG+eabb8y+ffusvn379hlPT0+TkpJijh8/bry8vKyJYowxv/zyiwkKCjLt27c3GzduNLt37zbvv/++2bVrlzl16pTp1KmTadmypTl69Kg5evSoSU9Pz3G6wODBg02jRo2c3te///3vTm0TJkwwy5YtMwcOHDBLly41d911l+nXr58xxpj09HQzceJE4+/vb20ne8Je+h5lZmaaqKgo06hRI7Np0yazbt06U7t2beuHrzEXJ6Wvr69p37692b59u1m5cqUJDQ01//d//3fFz2C29PR04+rqmuOXxu7du5uHHnromsvfTphXzKvbZV5d7q8ezJhTzKnbbU4ZY8zevXuNJLN9+/brWt4uzCvm1e06rzIyMsxHH31kPDw8zI4dO/K17B0RzI4dO2Y8PT3NwYMHzcGDB42Xl5f5/fffnSbl5X7//XenH0RXOr84Li7OhISEmPT0dKf2yydlenq6iYqKMp06dTIRERHmiSeecBq/c+dO6y8G2Ro3bmwef/xxY4wxvXv3Nk8++aTTMqtWrTIuLi7mzz//NLt37zaSzJIlS3Ldn9zOLz59+rRxd3c3s2bNstrOnz9vSpUqZV577TWn5RYuXJhjnf/3f/9nHn74Yet5u3btrL9EGGPMsGHDTHh4uDl//nyuNeV2fvHlr/PWrVuNw+Ewhw4dMsYY6y8o2X9Bys3cuXNNsWLFrOdXOr/40vfom2++Ma6urubw4cNW/44dO4wk669HI0eONEWKFHH668iQIUNMvXr1rlhLtl9//dVIMmvWrHFqHzJkiKlbt+41l7+dMK/+h3kVkGPcrZxXl/urBzPmFHPqdptTmZmZpnXr1qZhw4b5XtZuzKv/YV4F5Bhnx7z68ccfjY+Pj3F1dTUBAQHmv//9b56XzfaXv8ZMungeaevWrTVjxgwlJCSodevWKl68uNOYvXv3qkuXLqpQoYL8/f1Vvnx5SdLhw4evuf7IyEh5eHhcdYyHh4dmzZql+fPn69y5c5owYYJTf9WqVdWgQQO9//77kqR9+/Zp1apV6t27tyTphx9+0IwZM+Tr62s9YmNjlZWVpQMHDmjbtm1ydXVVTExMXl8W7d+/XxcuXFDDhg2tNnd3d9WtW1c7d+50GlunTh2n55mZmZo5c6Yef/xxq+3xxx/XjBkzlJWVJUnatm2bGjduLHd39zzXdLmoqChVq1ZNs2fPlnTx3Pdjx46pY8eO1phvv/1WTZs2VenSpeXn56du3brp+PHjOnv2bJ63s3PnToWFhSksLMxqi4iIUGBgoNNrUb58efn5+VnPS5Ys+Ze8RqwgMK9yx7z6H+ZV/jCncsec+p9bPafi4+P1008/ac6cOfle9nbBvMod8+p/btW8uuuuu7Rt2zatX79e/fr1U1xcnBITE/O8vHQH3S6/V69emjFjhmbOnKlevXrl6G/btq1SUlI0bdo0rV+/XuvXr5f0vws5r8bHxydPNaxZs0aSlJKSopSUlBz9vXv31vz583Xq1CklJCSoYsWK1iQ7ffq0+vbtq23btlmPH374QXv37lXFihXl7e2dpxqu1+X7+PXXX+vXX3/VY489Jjc3N7m5ualz5846dOiQli5dKkkFVlPXrl2tSTl79my1bNlSxYoVk3Tx1qpt2rRRjRo1NH/+fG3evNm6CUBe3rv8uvwHjMPhsH4IXU3x4sXl6uqq5ORkp/bk5GSFhoYWaI23EvPqxjCvLrreeXUnYk7dGObURQUxp/r3769FixZp+fLlKlOmTEGWd8sxr24M8+qiG51XHh4eqlSpkmrXrq3x48erZs2aevPNN/NVwx0TzFq2bKnz58/rwoULio2Ndeo7fvy4du/erRdffFFNmzZVtWrVdOLECacx2X8NyczMvK7t79+/XwMHDtS0adNUr149xcXF5XgzO3XqJBcXF82ePVsffPCBevXqJYfDIUm65557lJiYqEqVKuV4eHh4KDIyUllZWVqxYkWu28+t/ooVK8rDw0OrV6+22i5cuKCNGzcqIiLiqvszffp0de7c2emHxLZt29S5c2dNnz5dklSjRg2tWrVKFy5cuGJNeXk9//a3v+mnn37S5s2bNW/ePHXt2tXq27x5s7KysvT666+rfv36qlKlin777bd8b6datWo6cuSIjhw5YrUlJibq5MmT13wt8sLDw0O1a9e2fmBJUlZWlpYuXaro6OgbXr9dmFfMq6u52fPqTsScYk5dza2YU8YY9e/fX59++qmWLVum8PDwAlmvnZhXzKursev/VVlZWUpPT8/fQvk++fE2cvn5q6mpqSY1NdV6nn1+cWZmpilWrJh5/PHHzd69e83SpUvNvffe63S9woULF4y3t7d56aWXTFJSknXhZG7nyBrjfO5qRkaGqV+/vunQoYMxxpjffvvNFCtWzDqH91K9e/c2RYsWNa6urubXX3+12n/44Qfj7e1t4uPjzdatW82ePXvMwoULne7y16NHDxMWFmY+/fRT8/PPP5vly5ebjz/+2Bhz8SJMh8NhZsyYYY4dO2Zd/Pjcc8+ZUqVKmcWLFztd+JmSkmKMyf285GPHjhl3d3ezePHiHPV/+eWXxtPT0xw/ftz88ccfplixYtaFn3v27DEffPCB9X0oL7/8silbtqzZtWuX+f3338358+eveB53w4YNTc2aNY2fn585e/as1b5t2zYjyUycONHs37/ffPDBB6Z06dJONa9evdq6aPf333+3vrfi0vcoKyvLREVFmcaNG5vNmzeb9evX53rhZ82aNZ3qmjBhgilXrlyO1yE3c+bMMZ6enmbGjBkmMTHRPPnkkyYwMNDprj9/Bcwr5pUxt8+8OnXqlNm6davZunWrkWTeeOMNs3XrVuuahL8C5hRzypjbZ07169fPBAQEmO+++866YcLRo0ed9uevgHnFvDLm9plXQ4cONStWrDAHDhwwP/74oxk6dKhxOBzmm2++ydPy2e6oYHa5Sy/8XLJkialWrZrx9PQ0NWrUMN99912OC8mnTZtmwsLCjIuLS45bpV7u0jd89OjRpmTJkuaPP/6w+ufPn288PDzMtm3bnJZbs2aNkWQefPDBHOvcsGGDad68ufH19TU+Pj6mRo0a5uWXX7b6//zzTzNw4EBTsmRJ4+HhYSpVqmTef/99q3/MmDEmNDTUOBwOa7///PNP88wzz5jixYtf9Vapl07Kf/3rXyYwMDDXCzrT09NNYGCgefPNN40xF3+YtGjRwhQpUsT4+fmZxo0bm/379xtjLk7u7P1RLrdKvdTkyZONJNO9e/cc23zjjTdMyZIljbe3t4mNjTUffPBBjpqfeuopU6xYsQK5Veql8jMpjTHm7bffNmXLljUeHh6mbt26Zt26dXle9nbBvGJeZbsd5lVut0OW8v7FsbcD5hRzKtvtMKdym0+STEJCQp6Wv10wr5hX2W6HedWrVy9Trlw54+HhYUqUKGGaNm2a71BmjDEOY4zJ3zE2AAAAAEBBumOuMQMAAACAvyqCGZAHhw8fdrqN7eWPvNxyF4Az5hVQsJhTQMG7lfOKUxmBPMjIyNDBgwev2F++fHm5ubnduoKAOwDzCihYzCmg4N3KeUUwAwAAAACbcSojAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQCgUGvSpIkGDBhgdxkAgEKOYAYAuC49evSQw+HQK6+84tS+cOFCORyOfK2rfPnymjhxYgFWd/McPHhQDodD27Zts7sUAMAdhGAGALhuXl5eevXVV3XixAm7S8m38+fP211Cgbpw4YLdJQAAbgDBDABw3Zo1a6bQ0FCNHz/+quO+//57NW7cWN7e3goLC9Ozzz6rM2fOSLp4KuGhQ4c0cOBAORwOORwOGWNUokQJzZs3z1pHVFSUSpYs6bROT09PnT17VpJ0+PBhtWvXTr6+vvL391enTp2UnJxsjR81apSioqL03nvvKTw8XF5eXrnW+t///lcBAQGaNWvWdb0m+/fvV7t27RQSEiJfX1/de++9+vbbb63+MWPG6O67786xXFRUlIYPH249f++991StWjV5eXmpatWqmjx5stWXfdTu448/VkxMjLy8vDRr1iwdOnRIbdu2VdGiReXj46Pq1avryy+/vK79AADcWgQzAMB1c3V11bhx4/T222/rl19+yXXM/v371bJlS3Xo0EE//vijPv74Y33//ffq37+/JGnBggUqU6aMxowZo6NHj+ro0aNyOBy677779N1330mSTpw4oZ07d+rPP//Url27JEkrVqzQvffeqyJFiigrK0vt2rVTSkqKVqxYoSVLlujnn3/WY4895lTLvn37NH/+fC1YsCDXUxFnz56tLl26aNasWeratet1vSanT5/Wgw8+qKVLl2rr1q1q2bKl2rZtq8OHD0uSevXqpZ07d2rjxo3WMlu3btWPP/6onj17SpJmzZqlESNG6OWXX9bOnTs1btw4DR8+XDNnznTa1tChQ/Xcc89p586dio2NVXx8vNLT07Vy5Upt375dr776qnx9fa9rPwAAt5ab3QUAAP7aHnnkEUVFRWnkyJGaPn16jv7x48era9eu1g02KleurLfeeksxMTGaMmWKgoKC5OrqKj8/P4WGhlrLNWnSRO+++64kaeXKlapVq5ZCQ0P13XffqWrVqvruu+8UExMjSVq6dKm2b9+uAwcOKCwsTJL0wQcfqHr16tq4caPuvfdeSRdPX/zggw9UokSJHHVOmjRJ//jHP/TFF19Y670eNWvWVM2aNa3nY8eO1aeffqrPP/9c/fv3V5kyZRQbG6uEhASrroSEBMXExKhChQqSpJEjR+r1119X+/btJUnh4eFKTEzUu+++q7i4OGvdAwYMsMZIF48adujQQZGRkZJkrQ8AcPvjiBkA4Ia9+uqrmjlzpnbu3Jmj74cfftCMGTPk6+trPWJjY5WVlaUDBw5ccZ0xMTFKTEzU77//rhUrVqhJkyZq0qSJvvvuO124cEFr1qxRkyZNJEk7d+5UWFiYFcokKSIiQoGBgU41lStXLtdQNm/ePA0cOFBLliy5oVAmXTxiNnjwYFWrVk2BgYHy9fXVzp07rSNmkvTEE0/oo48+0rlz53T+/HnNnj1bvXr1kiSdOXNG+/fvV+/evZ1es5deekn79+932ladOnWcnj/77LN66aWX1LBhQ40cOVI//vjjDe0LAODWIZgBAG7Yfffdp9jYWA0bNixH3+nTp9W3b19t27bNevzwww/au3evKlaseMV1RkZGKigoSCtWrHAKZitWrNDGjRt14cIFNWjQIF91+vj45Npeq1YtlShRQu+//76MMfla5+UGDx6sTz/9VOPGjdOqVau0bds2RUZGOt1spG3btvL09NSnn36qL774QhcuXNCjjz4q6eLrJUnTpk1zes1++uknrVu37qr706dPH/3888/q1q2btm/frjp16ujtt9++of0BANwanMoIACgQr7zyiqKionTXXXc5td9zzz1KTExUpUqVrrish4eHMjMzndocDocaN26szz77TDt27FCjRo1UpEgRpaen691331WdOnW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" + ] + }, + "metadata": {}, + "output_type": "display_data" + } + ], + "source": [ + "layers_updated = list(res_dict_updated.keys())\n", + "utilisation_updated = list(res_dict_updated.values())\n", + "lut_values_updated = [] #Initializing a list to store LUT values.\n", + "for i in range(len(layers_updated)):\n", + " x = list(utilisation_updated[i].values()) #Extracting the resource utilisation for each layer.\n", + " lut_values_updated.append(x[2]) #Extracting the LUT values of resource utilisation from each layer and appending to the list\n", + "\n", + "#Plotting the bar graph of each network layer with their corresponding LUT resource utilisation\n", + "fig = plt.figure(figsize = (10, 5))\n", + "plt.bar(layers_updated, lut_values_updated, color ='green', width = 0.3)\n", + "plt.xlabel(\"Network Layers\")\n", + "plt.ylabel(\"LUT Utilisation\")\n", + "plt.title(\"Estimated LUT values used for each network layer\")\n", + "plt.show()" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "From these numbers, we see that the first layer has been removed as the bottleneck and that the entire network can now perform one inference in ~4096 clock cycles (when the pipeline is full) as compared to the earlier configuration where it took ~38400 execution cycles.\n", + "\n", + "This decrease in execution latency of the network though comes at a cost of a 45% increase in LUT resource utilization for layer 1 of the network.\n", + "\n", + "We now observe the `instream_width` and `outstream_width` of our network with the updated folding parameters and then apply the `InsertDWC()` transform to it in case there is a mismatch in these widths due to the updates. " + ] + }, + { + "cell_type": "code", + "execution_count": 21, + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "Instream Width = 5 Outstream Width = 4\n", + "Instream Width = 2 Outstream Width = 2\n", + "Instream Width = 2 Outstream Width = 2\n", + "Instream Width = 2 Outstream Width = 1\n" + ] + } + ], + "source": [ + "fc_layers = model.get_nodes_by_op_type(\"MatrixVectorActivation\")\n", + "for fcl in fc_layers:\n", + " fcl_inst = getCustomOp(fcl)\n", + " print('Instream Width =',(fcl_inst.get_instream_width()),'Outstream Width =',int(fcl_inst.get_outstream_width()))" + ] + }, + { + "cell_type": "code", + "execution_count": 22, + "metadata": {}, + "outputs": [], + "source": [ + "model = model.transform(InsertDWC())" + ] + }, + { + "cell_type": "code", + "execution_count": 24, + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "Stopping http://0.0.0.0:5901\n", + "Serving './cybsec_DWC_inserted.onnx' at http://0.0.0.0:5901\n" + ] + }, + { + "data": { + "text/html": [ + "\n", + " \n", + " " + ], + "text/plain": [ + "" + ] + }, + "execution_count": 24, + "metadata": {}, + "output_type": "execute_result" + } + ], + "source": [ + "model.save(\"./cybsec_DWC_inserted.onnx\")\n", + "showInNetron(\"./cybsec_DWC_inserted.onnx\",localhost_url='xirxlabs53')" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "Because there is a mismatch in the `outstream_width` (4) of layer 1 and the `inputstream_width` (2) of layer 2 the FINN compiler inserts the `StreamingDataWidthConverter` layer to remedy this when we call that transformation for our network above.\n", + "\n", + "On expanding this layer in the netron we see that the `inWidth` of this layer is 4 and the `outWidth` is 2.\n", + "\n", + "Note, we do not see this insertion where these widths match. They are only mismatched for the first two layers and hence we see that the data width converter is being inserted there." + ] + }, + { + "cell_type": "code", + "execution_count": 25, + "metadata": {}, + "outputs": [], + "source": [ + "res_dict_DWC = []\n", + "res_dict_DWC = res_estimation(model)" + ] + }, + { + "cell_type": "code", + "execution_count": 26, + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "['MatrixVectorActivation_0', '', 'MatrixVectorActivation_1', 'MatrixVectorActivation_2', 'MatrixVectorActivation_3']\n" + ] + }, + { + "data": { + "image/png": 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Vc3rv7+8vSQoNDc3SnpGRoaSkJOs031WrVmns2LFas2aNzp8/7zR+UlKSNa9r2bt3r3799VeVLFky2+GZN047dOiQSpUqJR8fH6fhd9xxxw3WLm/l1aP2SpQooebNm+uLL77Qiy++KOnS6fyurq7q2LGjNV7mNdiTJ0/WgQMHlJ6ebg3LyanWObF3714lJSUpKCgo2+GZn0F0dLQ6deqkcePGaeLEiWrWrJkeeOAB/eMf/5CHh0ee1PLCCy+oQ4cOqlq1qu688061bt1aPXr0UM2aNSVJ+/btkzFGo0eP1ujRo69Zb5kyZXTo0CHVr18/y/Bb+c4cOnTomvOoVq2afv75Z6c2V1dXlS1b9obzPXnypBITEzVlyhRNmTIl23EyPwdJmjFjhl5//XXt2rXL6ceXK5/ysX//fpUuXVqBgYE3XP7VfwMkqVixYlnu4ZDT6YsVKyZJ1vSZP+Bc7xKcpKQka7rsuLi4KCoqSitXrpR0KfA3adJEjRs3Vnp6utauXavg4GAlJCQ4Bf5rfQ8yL3U6dOiQ7rzzTqs9uyelZOrRo4dcXV21c+dOhYSEXHO8Gzl8+LDGjBmjr7/+Oss2vvKH0pYtW6pUqVKaOXOmmjdvroyMDH322Wfq0KGDfH19Jd3ctr3eOgJAXiLwA0AuBAUFaevWrfr++++1aNEiLVq0SNOmTVPPnj01Y8aMm56vi4tLrtrN/7/mc//+/WrevLmqVaumN954Q6GhoXJ3d9e3336riRMn5ujmaBkZGWrZsqWeeeaZbIdXrVo1h2tx6zw8PJxumnWlzB8zrjyqe6u6du2q3r17a+vWrYqMjNQXX3yh5s2bW9ctS5duzjV69Gj16dNHL774ogIDA1WkSBENGTLkhtvX4XBke33ulT8aSJc+g6CgIM2cOTPb+WT+GONwODR37lytXbtW33zzjb7//nv16dNHr7/+utauXZvlx5icuLqWpk2bav/+/frqq6/0ww8/6MMPP9TEiRP1/vvvq1+/ftY6Dx8+XDExMdnOMzePsbzdrjxD43oy1+uRRx65ZnDL/NHj008/Va9evfTAAw9oxIgRCgoKkouLiyZMmKD9+/ffVJ036uu3On3m+v3rX/9yusfAlXLy/WncuLFefvllXbhwQStXrtQ///lPBQQE6M4779TKlSute4NcGfhz63r3eOjYsaM++eQTvfnmm5owYcJNzT89Pd26/v/ZZ59VtWrV5O3trT/++EO9evVy6tcuLi76xz/+oalTp2ry5MlatWqVjh075vQ0kJvZtjm5jwUA5AUCPwDkkru7u9q3b6/27dsrIyNDTzzxhD744AONHj1alStXzrMj0DnxzTffKCUlRV9//bXTEb7s7hZ+rboqVaqks2fP3vA55+XLl9eSJUt09uxZp/95ze3dsW+0jGvNL7P9Zk/hzc4DDzyg/v37W6f179mzR6NGjXIaZ+7cubrnnnv00UcfObUnJiY6/TCQnWLFimV7SnbmUepMlSpV0o8//qhGjRrlKAg0aNBADRo00Msvv6xZs2ape/fumj17tvr163fdWq5+osLFixd1/PjxLOMGBgaqd+/e6t27t86ePaumTZvq+eefV79+/VSxYkVJkpubW46+M9ldGnAr35nMz3/37t269957s8z3Zr8fJUuWlK+vr9LT02+4XnPnzlXFihU1f/58p3519an7lSpV0vfff6+EhIQcHeW/nTIvF/Dz87vh+l3vb1iTJk108eJFffbZZ/rjjz+sYN+0aVMr8FetWtUK/tK1+/WuXbus4Tk1ePBgVa5cWWPGjJG/v79GjhyZ42kzbdu2TXv27NGMGTPUs2dPq/1al2r17NlTr7/+ur755hstWrRIJUuWdPqxKzfbFgDyG9fwA0AunDp1yul9kSJFrKN+mY/Ly3yecn48ri7zqN6VRwGTkpI0bdq0LON6e3tnW1OXLl20Zs0aff/991mGJSYmWvcLuO+++5SWlub0yL/09HS9/fbbt7oalvvuu09r167Vpk2bstQxc+ZMRUZG3tJpvFcLCAhQTEyMvvjiC82ePVvu7u564IEHnMZxcXHJcpR1zpw5WR4Bl51KlSpp165dOnnypNX2yy+/ZHlUV5cuXZSenm5dWnCltLQ063M7ffp0lloyjyhe/bjG7GrJvPY605QpU7Ic4b/6O+7j46PKlStb8w8KClKzZs30wQcfZPtjwZXrmvl5rl+/3mn4tc5kyIm6desqKChI77//vtM6L1q0SDt37lTbtm1var4uLi7q1KmT5s2bp99++y3L8CvXK7t+t27dOq1Zs8Zpmk6dOskYk+3jH3N65D6v1KlTR5UqVdK///1vnT17NsvwK9fven/D6tevLzc3N7366qsKDAxUjRo1JF36IWDt2rVavnx5lqP79913n9avX++0fc6dO6cpU6aoQoUKCg8Pz9W6jB49WsOHD9eoUaOyPII0J7L7/Iwx1uNVr1azZk3VrFlTH374oebNm6euXbvK1fXyMbPcbFsAyG8c4QeAKyxatMg66nSlhg0bqmLFiurXr58SEhJ07733qmzZsjp06JDefvttRUZGWtejRkZGysXFRa+++qqSkpLk4eGhe++995rXZ9+KVq1aWWcc9O/fX2fPntXUqVMVFBSUJYzVqVNH7733nl566SVVrlxZQUFBuvfeezVixAh9/fXXateunXr16qU6dero3Llz2rZtm+bOnauDBw+qRIkSat++vRo1aqSRI0fq4MGDCg8P1/z583N0Y8ArzZs3L9ttHBsbq5EjR2rOnDlq2rSp+vfvr2rVqunYsWOaPn26jh8/nu0PGbfq4Ycf1iOPPKLJkycrJibG6ZFuktSuXTu98MIL6t27txo2bKht27Zp5syZ1pHu6+nTp4/eeOMNxcTEqG/fvjpx4oTef/991ahRw+nZ4tHR0erfv78mTJigrVu3qlWrVnJzc9PevXs1Z84cvfnmm3rooYc0Y8YMTZ48WQ8++KAqVaqkM2fOaOrUqfLz89N999133Vr69eunxx9/XJ06dVLLli31yy+/6Pvvv89ylkJ4eLiaNWumOnXqKDAwUBs3btTcuXM1aNAga5x3331XjRs3VkREhB599FFVrFhR8fHxWrNmjY4ePapffvlFkvTMM8/oP//5j1q3bq2nnnrKeixf+fLl9euvv95w+2UnM2z27t1b0dHR6tatm/VYvgoVKmjo0KE3NV/p0qPtli1bpvr16+vRRx9VeHi4EhIStHnzZv34449KSEiQdOk7MX/+fD344INq27atDhw4oPfff1/h4eFOge+ee+5Rjx499NZbb2nv3r1q3bq1MjIytHLlSt1zzz1O2/R2K1KkiD788EO1adNGNWrUUO/evVWmTBn98ccfWrZsmfz8/PTNN99IuvS3Qrr0aMSuXbvKzc1N7du3l7e3t4oWLao6depo7dq1at++vXU2QNOmTXXu3DmdO3cuS+AfOXKkPvvsM7Vp00ZPPvmkAgMDNWPGDB04cEDz5s3L0SUXV/vXv/6lpKQkDRw4UL6+vk6n2N9ItWrVVKlSJQ0fPlx//PGH/Pz8NG/evOveL6Fnz54aPny4JGVZVm62LQDku/x+LAAAFEbXeyyfrnj80ty5c02rVq1MUFCQcXd3N+XKlTP9+/c3x48fd5rf1KlTTcWKFY2Li4vT46Cu9Vi+qx9Vl93jyIy5/EinkydPWm1ff/21qVmzpvH09DQVKlQwr776qvn444+zPFYrLi7OtG3b1vj6+hpJTnWcOXPGjBo1ylSuXNm4u7ubEiVKmIYNG5p///vfTo8LPHXqlOnRo4fx8/Mz/v7+pkePHmbLli25eizftV6Zj+w6evSo6devnylTpoxxdXU1gYGBpl27dmbt2rXXnX9uH8uXKTk52Xh5eRlJ5tNPP80y/MKFC+bpp582pUqVMl5eXqZRo0ZmzZo1WT7L7B7LZ4wxn376qalYsaJxd3c3kZGR5vvvv8/yWL5MU6ZMMXXq1DFeXl7G19fXREREmGeeecYcO3bMGHPpcWDdunUz5cqVMx4eHiYoKMi0a9fObNy48YbrmZ6ebp599llTokQJU7RoURMTE2P27duX5bF8L730kqlXr54JCAgwXl5eplq1aubll192+h4YY8z+/ftNz549TUhIiHFzczNlypQx7dq1M3PnznUa79dffzXR0dHG09PTlClTxrz44ovmo48+uunH8mX6/PPPTe3atY2Hh4cJDAw03bt3N0ePHnUaJzY21nh7e99w21wpPj7eDBw40ISGhho3NzcTEhJimjdvbqZMmWKNk5GRYcaPH2/Kly9vPDw8TO3atc3ChQuz/VzT0tLMv/71L1OtWjXj7u5uSpYsadq0aWM2bdpkjaNrPI7y6s8mO9f6G3Kt7+OWLVtMx44dTfHixY2Hh4cpX7686dKli1myZInTeC+++KIpU6aMKVKkSJbPasSIEUaSefXVV52mqVy5spFk9u/fn6XO/fv3m4ceesgEBAQYT09PU69ePbNw4cIcrYsx2X8X0tPTTbdu3Yyrq6v58ssvb7iNrnws344dO0yLFi2Mj4+PKVGihHn00UetRyFm97fs+PHjxsXFxVStWvWay8nJts3ubzgA3E4OY/L5nDIAAADgb+TPP/9UqVKlNGbMmGs+nQIACiOu4QcAAACuY/r06UpPT1ePHj0KuhQAyBWu4QcAAACysXTpUu3YsUMvv/yyHnjgAVWoUKGgSwKAXOGUfgAAACAbzZo10+rVq9WoUSN9+umnKlOmTEGXBAC5QuAHAAAAAMCGuIYfAAAAAAAbIvADAAAAAGBD3LRPUkZGho4dOyZfX185HI6CLgcAAAAAYHPGGJ05c0alS5dWkSK351g8gV/SsWPHFBoaWtBlAAAAAAD+xxw5ckRly5a9LfMm8Evy9fWVdGlD+/n5FXA1AAAAAAC7S05OVmhoqJVHbwcCv2Sdxu/n50fgBwAAAADkm9t5WTk37QMAAAAAwIYI/AAAAAAA2BCBHwAAAAAAGyLwAwAAAABgQwR+AAAAAABsiMAPAAAAAIANFXjg/+OPP/TII4+oePHi8vLyUkREhDZu3GgNN8ZozJgxKlWqlLy8vNSiRQvt3bvXaR4JCQnq3r27/Pz8FBAQoL59++rs2bP5vSoAAAAAABQaBRr4T58+rUaNGsnNzU2LFi3Sjh079Prrr6tYsWLWOK+99preeustvf/++1q3bp28vb0VExOjCxcuWON0795d27dv1+LFi7Vw4UKtWLFCjz32WEGsEgAAAAAAhYLDGGMKauEjR47UqlWrtHLlymyHG2NUunRpPf300xo+fLgkKSkpScHBwZo+fbq6du2qnTt3Kjw8XBs2bFDdunUlSd99953uu+8+HT16VKVLl75hHcnJyfL391dSUpL8/PzybgUBAAAAAMhGfuTQAj3C//XXX6tu3brq3LmzgoKCVLt2bU2dOtUafuDAAcXFxalFixZWm7+/v+rXr681a9ZIktasWaOAgAAr7EtSixYtVKRIEa1bty7b5aakpCg5OdnpBQAAAACAnRRo4P/999/13nvvqUqVKvr+++81YMAAPfnkk5oxY4YkKS4uTpIUHBzsNF1wcLA1LC4uTkFBQU7DXV1dFRgYaI1ztQkTJsjf3996hYaG5vWqAQAAAABQoAo08GdkZOiuu+7S+PHjVbt2bT322GN69NFH9f7779/W5Y4aNUpJSUnW68iRI7d1eQAAAAAA5LcCDfylSpVSeHi4U1v16tV1+PBhSVJISIgkKT4+3mmc+Ph4a1hISIhOnDjhNDwtLU0JCQnWOFfz8PCQn5+f0wsAAAAAADsp0MDfqFEj7d6926ltz549Kl++vCQpLCxMISEhWrJkiTU8OTlZ69atU1RUlCQpKipKiYmJ2rRpkzXO0qVLlZGRofr16+fDWgAAAAAAUPi4FuTChw4dqoYNG2r8+PHq0qWL1q9frylTpmjKlCmSJIfDoSFDhuill15SlSpVFBYWptGjR6t06dJ64IEHJF06I6B169bWpQCpqakaNGiQunbtmqM79AMAAAAAYEcF+lg+SVq4cKFGjRqlvXv3KiwsTMOGDdOjjz5qDTfGaOzYsZoyZYoSExPVuHFjTZ48WVWrVrXGSUhI0KBBg/TNN9+oSJEi6tSpk9566y35+PjkqIa/1WP5HI6CriD/FOxXEwAAAABum/zIoQUe+AsDAn8hxVcTAAAAgE3lRw4t0Gv4AQAAAADA7UHgBwAAAADAhgj8AAAAAADYEIEfAAAAAAAbIvADAAAAAGBDBH4AAAAAAGyIwA8AAAAAgA0R+AEAAAAAsCECPwAAAAAANkTgBwAAAADAhgj8AAAAAADYEIEfAAAAAAAbIvADAAAAAGBDBH4AAAAAAGyIwA8AAAAAgA0R+AEAAAAAsCECPwAAAAAANkTgBwAAAADAhgj8AAAAAADYEIEfAAAAAAAbIvADAAAAAGBDBH4AAAAAAGyIwA8AAAAAgA0R+AEAAAAAsCECPwAAAAAANkTgBwAAAADAhgj8AAAAAADYEIEfAAAAAAAbIvADAAAAAGBDBH4AAAAAAGyIwA8AAAAAgA0R+AEAAAAAsCECPwAAAAAANkTgBwAAAADAhgj8AAAAAADYEIEfAAAAAAAbIvADAAAAAGBDBH4AAAAAAGyIwA8AAAAAgA0R+AEAAAAAsCECPwAAAAAANkTgBwAAAADAhgj8AAAAAADYEIEfAAAAAAAbIvADAAAAAGBDBH4AAAAAAGyIwA8AAAAAgA0R+AEAAAAAsCECPwAAAAAANkTgBwAAAADAhgj8AAAAAADYUIEG/ueff14Oh8PpVa1aNWv4hQsXNHDgQBUvXlw+Pj7q1KmT4uPjneZx+PBhtW3bVkWLFlVQUJBGjBihtLS0/F4VAAAAAAAKFdeCLqBGjRr68ccfrfeurpdLGjp0qP773/9qzpw58vf316BBg9SxY0etWrVKkpSenq62bdsqJCREq1ev1vHjx9WzZ0+5ublp/Pjx+b4uAAAAAAAUFgUe+F1dXRUSEpKlPSkpSR999JFmzZqle++9V5I0bdo0Va9eXWvXrlWDBg30ww8/aMeOHfrxxx8VHBysyMhIvfjii3r22Wf1/PPPy93dPb9XBwAAAACAQqHAr+Hfu3evSpcurYoVK6p79+46fPiwJGnTpk1KTU1VixYtrHGrVaumcuXKac2aNZKkNWvWKCIiQsHBwdY4MTExSk5O1vbt26+5zJSUFCUnJzu9AAAAAACwkwIN/PXr19f06dP13Xff6b333tOBAwfUpEkTnTlzRnFxcXJ3d1dAQIDTNMHBwYqLi5MkxcXFOYX9zOGZw65lwoQJ8vf3t16hoaF5u2IAAAAAABSwAj2lv02bNta/a9asqfr166t8+fL64osv5OXldduWO2rUKA0bNsx6n5ycTOgHAAAAANhKgZ/Sf6WAgABVrVpV+/btU0hIiC5evKjExESnceLj461r/kNCQrLctT/zfXb3Bcjk4eEhPz8/pxcAAAAAAHZSqAL/2bNntX//fpUqVUp16tSRm5ublixZYg3fvXu3Dh8+rKioKElSVFSUtm3bphMnTljjLF68WH5+fgoPD8/3+gEAAAAAKCwK9JT+4cOHq3379ipfvryOHTumsWPHysXFRd26dZO/v7/69u2rYcOGKTAwUH5+fho8eLCioqLUoEEDSVKrVq0UHh6uHj166LXXXlNcXJyee+45DRw4UB4eHgW5agAAAAAAFKgCDfxHjx5Vt27ddOrUKZUsWVKNGzfW2rVrVbJkSUnSxIkTVaRIEXXq1EkpKSmKiYnR5MmTreldXFy0cOFCDRgwQFFRUfL29lZsbKxeeOGFglolAAAAAAAKBYcxxhR0EQUtOTlZ/v7+SkpKKvzX8zscBV1B/uGrCQAAAMCm8iOHFqpr+AEAAAAAQN4g8AMAAAAAYEMEfgAAAAAAbIjADwAAAACADRH4AQAAAACwIQI/AAAAAAA2ROAHAAAAAMCGCPwAAAAAANgQgR8AAAAAABsi8AMAAAAAYEMEfgAAAAAAbIjADwAAAACADRH4AQAAAACwIQI/AAAAAAA2ROAHAAAAAMCGCPwAAAAAANgQgR8AAAAAABsi8AMAAAAAYEMEfgAAAAAAbIjADwAAAACADRH4AQAAAACwIQI/AAAAAAA2ROAHAAAAAMCGCPwAAAAAANgQgR8AAAAAABsi8AMAAAAAYEMEfgAAAAAAbIjADwAAAACADRH4AQAAAACwIQI/AAAAAAA2ROAHAAAAAMCGCPwAAAAAANgQgR8AAAAAABsi8AMAAAAAYEMEfgAAAAAAbIjADwAAAACADRH4AQAAAACwIQI/AAAAAAA2ROAHAAAAAMCGCPwAAAAAANgQgR8AAAAAABsi8AMAAAAAYEMEfgAAAAAAbIjADwAAAACADRH4AQAAAACwIQI/AAAAAAA2ROAHAAAAAMCGCPwAAAAAANgQgR8AAAAAABsi8AMAAAAAYEMEfgAAAAAAbKjQBP5XXnlFDodDQ4YMsdouXLiggQMHqnjx4vLx8VGnTp0UHx/vNN3hw4fVtm1bFS1aVEFBQRoxYoTS0tLyuXoAAAAAAAqXQhH4N2zYoA8++EA1a9Z0ah86dKi++eYbzZkzR8uXL9exY8fUsWNHa3h6erratm2rixcvavXq1ZoxY4amT5+uMWPG5PcqAAAAAABQqBR44D979qy6d++uqVOnqlixYlZ7UlKSPvroI73xxhu69957VadOHU2bNk2rV6/W2rVrJUk//PCDduzYoU8//VSRkZFq06aNXnzxRb377ru6ePFiQa0SAAAAAAAFrsAD/8CBA9W2bVu1aNHCqX3Tpk1KTU11aq9WrZrKlSunNWvWSJLWrFmjiIgIBQcHW+PExMQoOTlZ27dvv+YyU1JSlJyc7PQCAAAAAMBOXAty4bNnz9bmzZu1YcOGLMPi4uLk7u6ugIAAp/bg4GDFxcVZ41wZ9jOHZw67lgkTJmjcuHG3WD0AAAAAAIVXgR3hP3LkiJ566inNnDlTnp6e+brsUaNGKSkpyXodOXIkX5cPAAAAAMDtVmCBf9OmTTpx4oTuuusuubq6ytXVVcuXL9dbb70lV1dXBQcH6+LFi0pMTHSaLj4+XiEhIZKkkJCQLHftz3yfOU52PDw85Ofn5/QCAAAAAMBOCizwN2/eXNu2bdPWrVutV926ddW9e3fr325ublqyZIk1ze7du3X48GFFRUVJkqKiorRt2zadOHHCGmfx4sXy8/NTeHh4vq8TAAAAAACFRYFdw+/r66s777zTqc3b21vFixe32vv27athw4YpMDBQfn5+Gjx4sKKiotSgQQNJUqtWrRQeHq4ePXrotddeU1xcnJ577jkNHDhQHh4e+b5OAAAAAAAUFgV6074bmThxoooUKaJOnTopJSVFMTExmjx5sjXcxcVFCxcu1IABAxQVFSVvb2/FxsbqhRdeKMCqAQAAAAAoeA5jjCnoIgpacnKy/P39lZSUVPiv53c4CrqC/MNXEwAAAIBN5UcOLbBr+AEAAAAAwO1zU6f07927V8uWLdOJEyeUkZHhNGzMmDF5UhgAAAAAALh5uQ78U6dO1YABA1SiRAmFhITIccUp5g6Hg8APAEBB4bIvwBl9AsD/uFwH/pdeekkvv/yynn322dtRDwAAAAAAyAO5vob/9OnT6ty58+2oBQAAAAAA5JFcB/7OnTvrhx9+uB21AAAAAACAPJLrU/orV66s0aNHa+3atYqIiJCbm5vT8CeffDLPigMAAAAAADfHYUzu7vARFhZ27Zk5HPr9999vuaj8lh/PP8wz3HwGAHAt7CMAZ/QJAIVYfuTQXB/hP3DgwO2oAwAAAAAA5KFcX8N/JWOMcnmCAAAAAAAAyAc3Ffg/+eQTRUREyMvLS15eXqpZs6b+85//5HVtAAAAAADgJuX6lP433nhDo0eP1qBBg9SoUSNJ0s8//6zHH39cf/75p4YOHZrnRQIAAAAAgNy5qZv2jRs3Tj179nRqnzFjhp5//vm/5TX+3LSvkOJyEQDIHfYRgDP6BIBCLD9yaK5P6T9+/LgaNmyYpb1hw4Y6fvx4nhQFAAAAAABuTa4Df+XKlfXFF19kaf/8889VpUqVPCkKAAAAAADcmlxfwz9u3Dg9/PDDWrFihXUN/6pVq7RkyZJsfwgAAAAAAAD5L9dH+Dt16qR169apRIkS+vLLL/Xll1+qRIkSWr9+vR588MHbUSMAAAAAAMilXN+0z464aV8hxVcTAHKHfQTgjD4BoBDLjxyao1P6k5OTrQKSk5OvO26hD8wAAAAAAPwPyFHgL1asmI4fP66goCAFBATIkc2vpcYYORwOpaen53mRAAAAAAAgd3IU+JcuXarAwEBJ0rJly25rQQAAAAAA4NblKPBHR0db/w4LC1NoaGiWo/zGGB05ciRvqwMAAAAAADcl13fpDwsL08mTJ7O0JyQkKCwsLE+KAgAAAAAAtybXgT/zWv2rnT17Vp6ennlSFAAAAAAAuDU5OqVfkoYNGyZJcjgcGj16tIoWLWoNS09P17p16xQZGZnnBQIAAAAAgNzLceDfsmWLpEtH+Ldt2yZ3d3drmLu7u2rVqqXhw4fnfYUAAAAAACDXchz4M+/O37t3b7355pvy8/O7bUUBAAAAAIBbk+PAn2natGm3ow4AAAAAAJCHch34JWnjxo364osvdPjwYV28eNFp2Pz58/OkMAAAAABAHsnmxuu2ZUxBV1Bo5Pou/bNnz1bDhg21c+dOLViwQKmpqdq+fbuWLl0qf3//21EjAAAAAADIpVwH/vHjx2vixIn65ptv5O7urjfffFO7du1Sly5dVK5cudtRIwAAAAAAyKVcB/79+/erbdu2ki7dnf/cuXNyOBwaOnSopkyZkucFAgAAAACA3Mt14C9WrJjOnDkjSSpTpox+++03SVJiYqLOnz+ft9UBAAAAAICbkuub9jVt2lSLFy9WRESEOnfurKeeekpLly7V4sWL1bx589tRIwAAAAAAyKVcB/533nlHFy5ckCT985//lJubm1avXq1OnTrpueeey/MCAQAAAABA7jmM4ZkFycnJ8vf3V1JSkvz8/Aq6nOvjcRoAgGthHwE4o08Al9EfCp38yKG5voZ/8+bN2rZtm/X+q6++0gMPPKD/+7//08WLF/O0OAAAAAAAcHNyHfj79++vPXv2SJJ+//13PfzwwypatKjmzJmjZ555Js8LBAAAAAAAuZfrwL9nzx5FRkZKkubMmaPo6GjNmjVL06dP17x58/K6PgAAAAAAcBNyHfiNMcrIyJAk/fjjj7rvvvskSaGhofrzzz/ztjoAAAAAAHBTch3469atq5deekn/+c9/tHz5crVt21aSdODAAQUHB+d5gQAAAAAAIPdyHfgnTZqkzZs3a9CgQfrnP/+pypUrS5Lmzp2rhg0b5nmBAAAAAAAg9/LssXwXLlyQi4uL3Nzc8mJ2+YrH8hVSf5PHaQBAocE+AnBGnwAuoz8UOvmRQ13zakaenp55NSsAAAAAAHCLchT4AwMDtWfPHpUoUULFihWT4zq/DiUkJORZcQAAAAAA4ObkKPBPnDhRvr6+ki5dww8AAAAAAAq3PLuG/++Ma/gLKb6aAJA77CMAZ/QJ4DL6Q6FTaK7hT05OzvEMC31gBgAAAADgf0COAn9AQMB1r9uXJGOMHA6H0tPT86QwAAAAAABw83IU+JctW3a76wAAAAAAAHkoR4E/Ojr6dtcBAAAAAADyUJGcjPTrr78qIyPD+vf1Xrnx3nvvqWbNmvLz85Ofn5+ioqK0aNEia/iFCxc0cOBAFS9eXD4+PurUqZPi4+Od5nH48GG1bdtWRYsWVVBQkEaMGKG0tLRc1QEAAAAAgN3k6Ah/ZGSk4uLiFBQUpMjISDkcDmV3c//cXsNftmxZvfLKK6pSpYqMMZoxY4Y6dOigLVu2qEaNGho6dKj++9//as6cOfL399egQYPUsWNHrVq1SpKUnp6utm3bKiQkRKtXr9bx48fVs2dPubm5afz48TmuAwAAAAAAu8nRY/kOHTqkcuXKyeFw6NChQ9cdt3z58rdUUGBgoP71r3/poYceUsmSJTVr1iw99NBDkqRdu3apevXqWrNmjRo0aKBFixapXbt2OnbsmIKDgyVJ77//vp599lmdPHlS7u7uOVomj+UrpP4mj9MAgEKDfQTgjD4BXEZ/KHTyI4fm6JT+8uXLW3fpP3TokMqUKaPy5cs7vcqUKXPDHwOuJz09XbNnz9a5c+cUFRWlTZs2KTU1VS1atLDGqVatmsqVK6c1a9ZIktasWaOIiAgr7EtSTEyMkpOTtX379msuKyUlRcnJyU4vAAAAAADsJEeB/0r33HOPEhISsrQnJSXpnnvuyXUB27Ztk4+Pjzw8PPT4449rwYIFCg8PV1xcnNzd3RUQEOA0fnBwsOLi4iRJcXFxTmE/c3jmsGuZMGGC/P39rVdoaGiu6wYAAAAAoDDLdeA3xlhH+6906tQpeXt757qAO+64Q1u3btW6des0YMAAxcbGaseOHbmeT26MGjVKSUlJ1uvIkSO3dXkAAAAAAOS3HN20T5I6duwo6dKN+Xr16iUPDw9rWHp6un799Vc1bNgw1wW4u7urcuXKkqQ6depow4YNevPNN/Xwww/r4sWLSkxMdDrKHx8fr5CQEElSSEiI1q9f7zS/zLv4Z46THQ8PD6f6AQAAAACwmxwf4c88/d0YI19fX6dT4kNCQvTYY4/p008/veWCMjIylJKSojp16sjNzU1Lliyxhu3evVuHDx9WVFSUJCkqKkrbtm3TiRMnrHEWL14sPz8/hYeH33ItAAAAAAD8XeX4CP+0adMkSRUqVNDw4cNv6vT9q40aNUpt2rRRuXLldObMGc2aNUs//fSTvv/+e/n7+6tv374aNmyYAgMD5efnp8GDBysqKkoNGjSQJLVq1Urh4eHq0aOHXnvtNcXFxem5557TwIEDOYIPAAAAAPifluPAn2ns2LF5tvATJ06oZ8+eOn78uPz9/VWzZk19//33atmypSRp4sSJKlKkiDp16qSUlBTFxMRo8uTJ1vQuLi5auHChBgwYoKioKHl7eys2NlYvvPBCntUIAAAAAMDfkcOYnD2ksFixYtnerM/f319Vq1bV8OHDraD+d5Mfzz/MMzw/EwBwLewjAGf0CeAy+kOhkx85NMdH+CdNmpRte2JiojZt2qR27dpp7ty5at++fV7VBgAAAAAAblKOA39sbOx1h0dGRmrChAkEfgAAAAAACoEc36X/Rtq1a6ddu3bl1ewAAAAAAMAtyLPAn5KSInd397yaHQAAAAAAuAV5Fvg/+ugjRUZG5tXsAAAAAADALcjxNfzDhg3Ltj0pKUmbN2/Wnj17tGLFijwrDAAAAAAA3LwcB/4tW7Zk2+7n56eWLVtq/vz5CgsLy7PCAAAAAADAzctx4F+2bNntrAMAAAAAAOShPLuGHwAAAAAAFB4EfgAAAAAAbIjADwAAAACADRH4AQAAAACwoRwH/j59+ujMmTO3sxYAAAAAAJBHchz4Z8yYob/++ut21gIAAAAAAPJIjgO/MeZ21gEAAAAAAPKQa25GPnPmjDw9Pa87jp+f3y0VBAAAAAAAbl2uAn/VqlWvOcwYI4fDofT09FsuCgAAAAAA3JpcBf65c+cqMDDwdtUCAAAAAADySK4Cf6NGjRQUFHS7agEAAAAAAHkkxzftAwAAAAAAfx85Dvzly5eXi4vL7awFAAAAAADkkRyf0n/gwIHbWQcAAAAAAMhDOQ78xYoVk8PhyNLu7++vqlWravjw4WrZsmWeFgcAAAAAAG5OjgP/xIkTsw38iYmJ2rRpk9q1a6e5c+eqffv2eVogAAAAAADIvRwH/l69el13eGRkpCZMmEDgBwAAAACgEMizu/S3a9dOu3btyqvZAQAAAACAW5BngT8lJUXu7u55NTsAAAAAAHAL8izwf/TRR4qMjMyr2QEAAAAAgFuQ42v4hw0blm17UlKSNm/erD179mjFihV5VhgAAAAAALh5OQ78W7Zsybbdz89PLVu21Pz58xUWFpZnhQEAAAAAgJuX48C/bNmy6w4/evSoHnvsMU2ZMuWWiwIAAAAAALcmz67hP3XqlD766KO8mh0AAAAAALgFeRb4AQAAAABA4UHgBwAAAADAhgj8AAAAAADYUI5v2texY8frDk9MTLzVWgAAAAAAQB7JceD39/e/4fCePXveckEAAAAAAODW5TjwT5s27XbWAQAAAAAA8hDX8AMAAAAAYEMEfgAAAAAAbIjADwAAAACADRH4AQAAAACwIQI/AAAAAAA2ROAHAAAAAMCGCPwAAAAAANgQgR8AAAAAABsi8AMAAAAAYEMEfgAAAAAAbIjADwAAAACADRH4AQAAAACwIQI/AAAAAAA2VKCBf8KECbr77rvl6+uroKAgPfDAA9q9e7fTOBcuXNDAgQNVvHhx+fj4qFOnToqPj3ca5/Dhw2rbtq2KFi2qoKAgjRgxQmlpafm5KgAAAAAAFCoFGviXL1+ugQMHau3atVq8eLFSU1PVqlUrnTt3zhpn6NCh+uabbzRnzhwtX75cx44dU8eOHa3h6enpatu2rS5evKjVq1drxowZmj59usaMGVMQqwQAAAAAQKHgMMaYgi4i08mTJxUUFKTly5eradOmSkpKUsmSJTVr1iw99NBDkqRdu3apevXqWrNmjRo0aKBFixapXbt2OnbsmIKDgyVJ77//vp599lmdPHlS7u7uN1xucnKy/P39lZSUJD8/v9u6jrfM4SjoCvJP4flqAsDfA/sIwBl9AriM/lDo5EcOLVTX8CclJUmSAgMDJUmbNm1SamqqWrRoYY1TrVo1lStXTmvWrJEkrVmzRhEREVbYl6SYmBglJydr+/bt2S4nJSVFycnJTi8AAAAAAOyk0AT+jIwMDRkyRI0aNdKdd94pSYqLi5O7u7sCAgKcxg0ODlZcXJw1zpVhP3N45rDsTJgwQf7+/tYrNDQ0j9cGAAAAAICCVWgC/8CBA/Xbb79p9uzZt31Zo0aNUlJSkvU6cuTIbV8mAAAAAAD5ybWgC5CkQYMGaeHChVqxYoXKli1rtYeEhOjixYtKTEx0OsofHx+vkJAQa5z169c7zS/zLv6Z41zNw8NDHh4eebwWAAAAAAAUHgV6hN8Yo0GDBmnBggVaunSpwsLCnIbXqVNHbm5uWrJkidW2e/duHT58WFFRUZKkqKgobdu2TSdOnLDGWbx4sfz8/BQeHp4/KwIAAAAAQCFToEf4Bw4cqFmzZumrr76Sr6+vdc29v7+/vLy85O/vr759+2rYsGEKDAyUn5+fBg8erKioKDVo0ECS1KpVK4WHh6tHjx567bXXFBcXp+eee04DBw7kKD4AAAAA4H9WgT6Wz3GNR0NMmzZNvXr1kiRduHBBTz/9tD777DOlpKQoJiZGkydPdjpd/9ChQxowYIB++ukneXt7KzY2Vq+88opcXXP2ewaP5Suk/iaP0wCAQoN9BOCMPgFcRn8odPIjhxZo4C8sCPyFFF9NAMgd9hGAM/oEcBn9odDJjxxaaO7SDwAAAAAA8g6BHwAAAAAAGyLwAwAAAABgQwR+AAAAAABsiMAPAAAAAIANEfgBAAAAALAhAj8AAAAAADZE4AcAAAAAwIYI/AAAAAAA2BCBHwAAAAAAGyLwAwAAAABgQwR+AAAAAABsiMAPAAAAAIANEfgBAAAAALAhAj8AAAAAADZE4AcAAAAAwIYI/AAAAAAA2BCBHwAAAAAAGyLwAwAAAABgQwR+AAAAAABsiMAPAAAAAIANEfgBAAAAALAhAj8AAAAAADZE4AcAAAAAwIYI/AAAAAAA2BCBHwAAAAAAGyLwAwAAAABgQwR+AAAAAABsiMAPAAAAAIANEfgBAAAAALAhAj8AAAAAADZE4AcAAAAAwIYI/AAAAAAA2BCBHwAAAAAAGyLwAwAAAABgQwR+AAAAAABsiMAPAAAAAIANEfgBAAAAALAhAj8AAAAAADZE4AcAAAAAwIYI/AAAAAAA2BCBHwAAAAAAGyLwAwAAAABgQwR+AAAAAABsiMAPAAAAAIANEfgBAAAAALAhAj8AAAAAADZE4AcAAAAAwIYI/AAAAAAA2BCBHwAAAAAAGyLwAwAAAABgQwUa+FesWKH27durdOnScjgc+vLLL52GG2M0ZswYlSpVSl5eXmrRooX27t3rNE5CQoK6d+8uPz8/BQQEqG/fvjp79mw+rgUAAAAAAIVPgQb+c+fOqVatWnr33XezHf7aa6/prbfe0vvvv69169bJ29tbMTExunDhgjVO9+7dtX37di1evFgLFy7UihUr9Nhjj+XXKgAAAAAAUCg5jDGmoIuQJIfDoQULFuiBBx6QdOnofunSpfX0009r+PDhkqSkpCQFBwdr+vTp6tq1q3bu3Knw8HBt2LBBdevWlSR99913uu+++3T06FGVLl06R8tOTk6Wv7+/kpKS5Ofnd1vWL884HAVdQf4pHF9NAPj7YB8BOKNPAJfRHwqd/MihhfYa/gMHDiguLk4tWrSw2vz9/VW/fn2tWbNGkrRmzRoFBARYYV+SWrRooSJFimjdunXXnHdKSoqSk5OdXgAAAAAA2EmhDfxxcXGSpODgYKf24OBga1hcXJyCgoKchru6uiowMNAaJzsTJkyQv7+/9QoNDc3j6gEAAAAAKFiFNvDfTqNGjVJSUpL1OnLkSEGXBAAAAABAniq0gT8kJESSFB8f79QeHx9vDQsJCdGJEyechqelpSkhIcEaJzseHh7y8/NzegEAAAAAYCeFNvCHhYUpJCRES5YssdqSk5O1bt06RUVFSZKioqKUmJioTZs2WeMsXbpUGRkZql+/fr7XDAAAAABAYeFakAs/e/as9u3bZ70/cOCAtm7dqsDAQJUrV05DhgzRSy+9pCpVqigsLEyjR49W6dKlrTv5V69eXa1bt9ajjz6q999/X6mpqRo0aJC6du2a4zv0AwAAAABgRwUa+Ddu3Kh77rnHej9s2DBJUmxsrKZPn65nnnlG586d02OPPabExEQ1btxY3333nTw9Pa1pZs6cqUGDBql58+YqUqSIOnXqpLfeeivf1wUAAAAAgMLEYczf5CGFt1F+PP8wz/D8TADAtbCPAJzRJ4DL6A+FTn7k0EJ7DT8AAAAAALh5BH4AAAAAAGyIwA8AAAAAgA0R+AEAAAAAsCECPwAAAAAANkTgBwAAAADAhgj8AAAAAADYEIEfAAAAAAAbIvADAAAAAGBDBH4AAAAAAGyIwA8AAAAAgA0R+AEAAAAAsCECPwAAAAAANkTgBwAAAADAhgj8AAAAAADYEIEfAAAAAAAbIvADAAAAAGBDBH4AAAAAAGyIwA8AAAAAgA0R+AEAAAAAsCECPwAAAAAANkTgBwAAAADAhgj8AAAAAADYEIEfAAAAAAAbIvADAAAAAGBDBH4AAAAAAGyIwA8AAAAAgA0R+AEAAAAAsCECPwAAAAAANkTgBwAAAADAhgj8AAAAAADYEIEfAAAAAAAbIvADAAAAAGBDBH4AAAAAAGyIwA8AAAAAgA0R+AEAAAAAsCECPwAAAAAANkTgBwAAAADAhgj8AAAAAADYEIEfAAAAAAAbIvADAAAAAGBDBH4AAAAAAGyIwA8AAAAAgA0R+AEAAAAAsCECPwAAAAAANkTgBwAAAADAhgj8AAAAAADYEIEfAAAAAAAbIvADAAAAAGBDBH4AAAAAAGyIwA8AAAAAgA3ZJvC/++67qlChgjw9PVW/fn2tX7++oEsCAAAAAKDA2CLwf/755xo2bJjGjh2rzZs3q1atWoqJidGJEycKujQAAAAAAAqEwxhjCrqIW1W/fn3dfffdeueddyRJGRkZCg0N1eDBgzVy5MgbTp+cnCx/f38lJSXJz8/vdpd7axyOgq4g//z9v5rID/QJ4DL6A+CMPgFcRn8odPIjh7relrnmo4sXL2rTpk0aNWqU1VakSBG1aNFCa9asyXaalJQUpaSkWO+TkpIkXdrgKET4PABn9AngMvoD4Iw+AVz2N+kPmfnzdh6D/9sH/j///FPp6ekKDg52ag8ODtauXbuynWbChAkaN25clvbQ0NDbUiNukr9/QVcAFC70CeAy+gPgjD4BXPY36w9nzpyR/22q+W8f+G/GqFGjNGzYMOt9RkaGEhISVLx4cTn+l051yYHk5GSFhobqyJEjhf9yByAf0CcAZ/QJ4DL6A+CMPnF9xhidOXNGpUuXvm3L+NsH/hIlSsjFxUXx8fFO7fHx8QoJCcl2Gg8PD3l4eDi1BQQE3K4SbcHPz49OClyBPgE4o08Al9EfAGf0iWu7XUf2M/3t79Lv7u6uOnXqaMmSJVZbRkaGlixZoqioqAKsDAAAAACAgvO3P8IvScOGDVNsbKzq1q2revXqadKkSTp37px69+5d0KUBAAAAAFAgbBH4H374YZ08eVJjxoxRXFycIiMj9d1332W5kR9yz8PDQ2PHjs1yCQTwv4o+ATijTwCX0R8AZ/SJgucwt/MZAAAAAAAAoED87a/hBwAAAAAAWRH4AQAAAACwIQI/AAAAAAA2RODPQxUqVNCkSZMKuoy/nYMHD8rhcGjr1q23fVl8RgAKCn9/bg77CPtie98c+oQ9sa1vDv0hB4zNxMbGGkmmf//+WYY98cQTRpKJjY3N0bwOHDhgJJktW7bkaPwTJ06Yc+fO5Wjcdu3amZiYmGyHrVixwkgyv/zyS47mdS3Lli0zkszp06dvaT5XO3/+vClWrJgpXry4uXDhQq6mjY2NNR06dHBqS0tLM8ePHzepqal5VuO0adOMv79/lvbcfEZ55Z133jHly5c3Hh4epl69embdunX5unwAl7GPuIx9hH+W9vzeRyxfvty0a9fOlCpVykgyCxYsyLdlZ6JPXEaf8M/Snt99Yvz48aZu3brGx8fHlCxZ0nTo0MHs2rUr35ZPf7iM/uCfpT2/+8PkyZNNRESE8fX1Nb6+vqZBgwbm22+/zfV8bHmEPzQ0VLNnz9Zff/1ltV24cEGzZs1SuXLl8nx5Fy9elCSVLFlSRYsWzdE0ffv21eLFi3X06NEsw6ZNm6a6deuqZs2aeVrnzTLGKC0tzXo/b9481ahRQ9WqVdOXX355y/N3cXFRSEiIXF1v/1Mic/MZ5YXPP/9cw4YN09ixY7V582bVqlVLMTExOnHiRL7VAMAZ+4i8xT7i5p07d061atXSu+++m2/LzA59Im/RJ27e8uXLNXDgQK1du1aLFy9WamqqWrVqpXPnzuVbDfSHvEV/uHlly5bVK6+8ok2bNmnjxo2699571aFDB23fvj13M8rjHyIKXOYvP3feeaf59NNPrfaZM2eamjVrmg4dOli/zC1atMg0atTI+Pv7m8DAQNO2bVuzb98+axpJTq/o6GinZbz00kumVKlSpkKFCsYYY8qXL28mTpxojLn0q5ibm5tZsWKFNb9XX33VlCxZ0sTFxZnU1FQTHBxsXnzxRaf6z5w5Y3x8fMx7771njDFm5cqVpnHjxsbT09OULVvWDB482Jw9e9Ya/8KFC+aZZ54xZcuWNe7u7qZSpUrmww8/tH5VvPKVud4XLlwwgwcPNiVLljQeHh6mUaNGZv369dY8M3/R+/bbb81dd91l3NzczLJly6zhzZo1M++//7557733TMuWLbN8Br/99ptp27at8fX1NT4+PqZx48Zm3759ZuzYsVlqWrZsmdMvoOnp6aZMmTJm8uTJTvPcvHmzcTgc5uDBg8YYY15//XVz5513mqJFi5qyZcuaAQMGmDNnzjjVf+Vr7NixWT4jY4w5dOiQuf/++423t7fx9fU1nTt3NnFxcdbwsWPHmlq1aplPPvnElC9f3vj5+ZmHH37YJCcnZ1nv7NSrV88MHDjQep+enm5Kly5tJkyYkKPpAeQt9hHsIwrTPuJKKsAj/PQJ+kRh7BPGXDqiKsksX778pqbPLfoD/aEw9wdjjClWrJj58MMPczWNbQP/G2+8YZo3b261N2/e3EycONGpo86dO9fMmzfP7N2712zZssW0b9/eREREmPT0dGOMMevXrzeSzI8//miOHz9uTp06ZS3Dx8fH9OjRw/z222/mt99+M8Zk/RKMGDHClC9f3iQmJprNmzcbd3d389VXXzkNr1SpksnIyLDaPv74Y+Pl5WUSExPNvn37jLe3t5k4caLZs2ePWbVqlaldu7bp1auXNX6XLl1MaGiomT9/vtm/f7/58ccfzezZs01aWpqZN2+ekWR2795tjh8/bhITE40xxjz55JOmdOnS5ttvvzXbt283sbGxplixYtb6ZX7Ra9asaX744Qezb98+a9i+ffuMh4eHSUhIMKdOnTKenp5W5zHGmKNHj5rAwEDTsWNHs2HDBrN7927z8ccfm127dpkzZ86YLl26mNatW5vjx4+b48ePm5SUlCynPA0fPtw0btzY6XN9+umnndomTpxoli5dag4cOGCWLFli7rjjDjNgwABjjDEpKSlm0qRJxs/Pz1pOZie+8jNKT083kZGRpnHjxmbjxo1m7dq1pk6dOtYfZGMudVQfHx/TsWNHs23bNrNixQoTEhJi/u///u+a38FMKSkpxsXFJcv/wPXs2dPcf//9N5weQN5jH8E+orDsI65W0IGfPkGfKGx9whhj9u7daySZbdu23dT0uUV/oD8U1v6QlpZmPvvsM+Pu7m62b9+eq2ltG/hPnDhhPDw8zMGDB83BgweNp6enOXnypFNHvdrJkyed/qhc69qb2NhYExwcbFJSUpzar+6oKSkpJjIy0nTp0sWEh4ebRx991Gn8nTt3Wr9OZWrSpIl55JFHjDHG9O3b1zz22GNO06xcudIUKVLE/PXXX2b37t1Gklm8eHG265PdtTdnz541bm5uZubMmVbbxYsXTenSpc1rr73mNN2XX36ZZZ7/93//Zx544AHrfYcOHaxfvYwxZtSoUSYsLMxcvHgx25qyu/bm6u28ZcsW43A4zKFDh4wxxvq1LvPXyuzMmTPHFC9e3Hp/rWtvrvyMfvjhB+Pi4mIOHz5sDd++fbuRZP1SOXbsWFO0aFGnX+JGjBhh6tevf81aMv3xxx9Gklm9erVT+4gRI0y9evVuOD2AvMc+4jL2Ef5ZxsvPfcTVCjrw0yfoE4WtT6Snp5u2bduaRo0a5Xram0V/uIz+4J9lvILoD7/++qvx9vY2Li4uxt/f3/z3v//N8bSZbHkNv3TpGou2bdtq+vTpmjZtmtq2basSJUo4jbN3715169ZNFStWlJ+fnypUqCBJOnz48A3nHxERIXd39+uO4+7urpkzZ2revHm6cOGCJk6c6DS8WrVqatiwoT7++GNJ0r59+7Ry5Ur17dtXkvTLL79o+vTp8vHxsV4xMTHKyMjQgQMHtHXrVrm4uCg6Ojqnm0X79+9XamqqGjVqZLW5ubmpXr162rlzp9O4devWdXqfnp6uGTNm6JFHHrHaHnnkEU2fPl0ZGRmSpK1bt6pJkyZyc3PLcU1Xi4yMVPXq1TVr1ixJl67nOnHihDp37myN8+OPP6p58+YqU6aMfH191aNHD506dUrnz5/P8XJ27typ0NBQhYaGWm3h4eEKCAhw2hYVKlSQr6+v9b5UqVJcgw/8zbGPyB77iMv+1/YR9Ins0Scuy+8+MXDgQP3222+aPXt2rqe9VfSH7NEfLsuv/nDHHXdo69atWrdunQYMGKDY2Fjt2LEjx9NLNn8sX58+fTR9+nTNmDFDffr0yTK8ffv2SkhI0NSpU7Vu3TqtW7dO0uWbZ1yPt7d3jmpYvXq1JCkhIUEJCQlZhvft21fz5s3TmTNnNG3aNFWqVMnqeGfPnlX//v21detW6/XLL79o7969qlSpkry8vHJUw826eh2///57/fHHH3r44Yfl6uoqV1dXde3aVYcOHdKSJUskKc9q6t69u9VRZ82apdatW6t48eKSLj1+o127dqpZs6bmzZunTZs2WTc8yslnl1tX/9FxOBzWH6brKVGihFxcXBQfH+/UHh8fr5CQkDytEUDusY+4NewjLrnZfURhRJ+4NfSJS/KiTwwaNEgLFy7UsmXLVLZs2bwsL8foD7eG/nDJrfYHd3d3Va5cWXXq1NGECRNUq1Ytvfnmm7mqwdaBv3Xr1rp48aJSU1MVExPjNOzUqVPavXu3nnvuOTVv3lzVq1fX6dOnncbJ/OUtPT39ppa/f/9+DR06VFOnTlX9+vUVGxub5QPu0qWLihQpolmzZumTTz5Rnz595HA4JEl33XWXduzYocqVK2d5ubu7KyIiQhkZGVq+fHm2y8+u/kqVKsnd3V2rVq2y2lJTU7VhwwaFh4dfd30++ugjde3a1ekPx9atW9W1a1d99NFHkqSaNWtq5cqVSk1NvWZNOdme//jHP/Tbb79p06ZNmjt3rrp3724N27RpkzIyMvT666+rQYMGqlq1qo4dO5br5VSvXl1HjhzRkSNHrLYdO3YoMTHxhtsiJ9zd3VWnTh3rj5gkZWRkaMmSJYqKirrl+QO4Newj2Edcz+3eRxRG9An6xPXkR58wxmjQoEFasGCBli5dqrCwsDyZ782gP9Afrqeg9hEZGRlKSUnJ3US5vgigkLv62o6kpCSTlJRkvc+89iY9Pd0UL17cPPLII2bv3r1myZIl5u6773a6hi41NdV4eXmZl156ycTFxVk3q8ju+hFjnK/rSEtLMw0aNDCdOnUyxhhz7NgxU7x4cev6liv17dvXFCtWzLi4uJg//vjDav/ll1+Ml5eXGThwoNmyZYvZs2eP+fLLL53u+t6rVy8TGhpqFixYYH7//XezbNky8/nnnxtjLt34wuFwmOnTp5sTJ05YN5x46qmnTOnSpc2iRYucbraRkJBgjMn+mp0TJ04YNzc3s2jRoiz1f/vtt8bDw8OcOnXK/Pnnn6Z48eLWzTb27NljPvnkE+sZqi+//LIpV66c2bVrlzl58qS5ePHiNa9xatSokalVq5bx9fU158+ft9q3bt1qJJlJkyaZ/fv3m08++cSUKVPGqeZVq1ZZN0o5efKk9czMKz+jjIwMExkZaZo0aWI2bdpk1q1bl+3NNmrVquVU18SJE0358uWzbIfszJ4923h4eJjp06ebHTt2mMcee8wEBAQ43cETQP5hH8E+wpjCs484c+aM2bJli9myZYuRZN544w2zZcsW69rT/ECfoE8YU3j6xIABA4y/v7/56aefrBumHT9+3Gl9bif6A/3BmMLTH0aOHGmWL19uDhw4YH799VczcuRI43A4zA8//JCj6TPZPvBf7cqbbSxevNhUr17deHh4mJo1a5qffvopy01zpk6dakJDQ02RIkWyPE7jald+CcaNG2dKlSpl/vzzT2v4vHnzjLu7u9m6davTdKtXrzaSzH333ZdlnuvXrzctW7Y0Pj4+xtvb29SsWdO8/PLL1vC//vrLDB061JQqVcq4u7ubypUrm48//tga/sILL5iQkBDjcDis9f7rr7/M4MGDTYkSJa77OI0rO+q///1vExAQkO1NNFJSUkxAQIB58803jTGX/sC0atXKFC1a1Pj6+pomTZqY/fv3G2MudfjM9VE2j9O40uTJk40k07NnzyzLfOONN0ypUqWMl5eXiYmJMZ988kmWmh9//HFTvHjxPHmcxpVy01GNMebtt9825cqVM+7u7qZevXpm7dq1OZ4WQN5iH8E+IlNh2Edk9/gnXfH4q/xAn6BPZCoMfSK7/iDJTJs2LUfT3yr6A/0hU2HoD3369DHly5c37u7upmTJkqZ58+a5DvvGGOMwxpjcnRMAAAAAAAAKO1tfww8AAAAAwP8qAj9wkw4fPuz0qJOrXzl5LAsAwJ7YRwDO6BPAZfnZHzilH7hJaWlpOnjw4DWHV6hQQa6urvlXEACg0GAfATijTwCX5Wd/IPADAAAAAGBDnNIPAAAAAIANEfgBAAAAALAhAj8AAAAAADZE4AcAAAAAwIYI/AAAIFeaNWumIUOGFHQZAADgBgj8AADkk169esnhcOiVV15xav/yyy/lcDhyNa8KFSpo0qRJeVjd7XPw4EE5HA5t3bq1oEsBAOB/CoEfAIB85OnpqVdffVWnT58u6FJy7eLFiwVdQp5KTU0t6BIAALitCPwAAOSjFi1aKCQkRBMmTLjueD///LOaNGkiLy8vhYaG6sknn9S5c+ckXTql/tChQxo6dKgcDoccDoeMMSpZsqTmzp1rzSMyMlKlSpVymqeHh4fOnz8vSTp8+LA6dOggHx8f+fn5qUuXLoqPj7fGf/755xUZGakPP/xQYWFh8vT0zLbW//73v/L399fMmTNvapvs379fHTp0UHBwsHx8fHT33Xfrxx9/tIa/8MILuvPOO7NMFxkZqdGjR1vvP/zwQ1WvXl2enp6qVq2aJk+ebA3LPMvg888/V3R0tDw9PTVz5kwdOnRI7du3V7FixeTt7a0aNWro22+/van1AACgsCHwAwCQj1xcXDR+/Hi9/fbbOnr0aLbj7N+/X61bt1anTp3066+/6vPPP9fPP/+sQYMGSZLmz5+vsmXL6oUXXtDx48d1/PhxORwONW3aVD/99JMk6fTp09q5c6f++usv7dq1S5K0fPly3X333SpatKgyMjLUoUMHJSQkaPny5Vq8eLF+//13Pfzww0617Nu3T/PmzdP8+fOzPSV/1qxZ6tatm2bOnKnu3bvf1DY5e/as7rvvPi1ZskRbtmxR69at1b59ex0+fFiS1KdPH+3cuVMbNmywptmyZYt+/fVX9e7dW5I0c+ZMjRkzRi+//LJ27typ8ePHa/To0ZoxY4bTskaOHKmnnnpKO3fuVExMjAYOHKiUlBStWLFC27Zt06uvviofH5+bWg8AAAob14IuAACA/zUPPvigIiMjNXbsWH300UdZhk+YMEHdu3e3boxXpUoVvfXWW4qOjtZ7772nwMBAubi4yNfXVyEhIdZ0zZo10wcffCBJWrFihWrXrq2QkBD99NNPqlatmn766SdFR0dLkpYsWaJ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+ "text/plain": [ + "
" + ] + }, + "metadata": {}, + "output_type": "display_data" + } + ], + "source": [ + "layers_DWC = list(res_dict_DWC.keys())\n", + "print(layers_DWC)\n", + "utilisation_DWC = list(res_dict_DWC.values())\n", + "lut_values_DWC = [] #Initializing a list to store LUT values.\n", + "for i in range(len(layers_DWC)):\n", + " x = list(utilisation_DWC[i].values()) #Extracting the resource utilisation for each layer.\n", + " lut_values_DWC.append(x[2]) #Extracting the LUT values of resource utilisation from each layer and appending to the list\n", + "\n", + "#Plotting the bar graph of each network layer with their corresponding LUT resource utilisation\n", + "fig = plt.figure(figsize = (12, 5))\n", + "plt.bar(layers_DWC, lut_values_DWC, color ='red', width = 0.3)\n", + "plt.xlabel(\"Network Layers\")\n", + "plt.ylabel(\"LUT Utilisation\")\n", + "plt.title(\"Estimated LUT values used for each network layer\")\n", + "plt.show()" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "The `StreamingDataWidthConverter` layer does not consume a large number of LUT resources as shown in the above graph." + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "
\n", + "Question: The name of the 'StreamingDataWidthConverter' layer is not coming in the graph.\n", + "
" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "# Additional Information : Constraints table\n", + "\n", + "The below table exposes the constraints associated with each layer. A developer working with these layers has to be mindful of not violating them when setting the PE & SIMD values manually." + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": {}, + "outputs": [], + "source": [ + "+------------------------------------+------------+----------------------------------------------------------------+\n", + "| Layers | Attributes | Assertions |\n", + "+====================================+============+================================================================+\n", + "| addstreams_batch | PE | inp_channels % PE == 0 |\n", + "| channelwise_op_batch | PE | channels % PE == 0 |\n", + "| checksum | ~ | ~ |\n", + "| concat | ~ | ~ |\n", + "| convolutioninputgenerator | SIMD | inp_feature_map_channels % SIMD == 0 |\n", + "| convolutioninputgenerator1d | SIMD | inp_feature_map_channels % SIMD == 0 |\n", + "| convolutioninputgenerator_rtl | SIMD | inp_feature_map_channels % SIMD == 0 |\n", + "| downsampler | SIMD | inp_feature_map_channels % SIMD == 0 |\n", + "| duplicatestreams_batch | PE | channels % PE == 0 |\n", + "| eltwise | PE | inp_channels % PE == 0 |\n", + "| fmpadding_batch | SIMD | inp_feature_map_channels % SIMD == 0 |\n", + "| fmpadding_rtl | SIMD | inp_feature_map_channels % SIMD == 0 |\n", + "| globalaccpool_batch | PE | channels % PE == 0 |\n", + "| hlscustomop | ~ | ~ |\n", + "| iodma | ~ | ~ |\n", + "| labelselect_batch | PE | num_labels % PE == 0 |\n", + "| lookup | ~ | ~ |\n", + "| matrixvectoractivation | PE & SIMD | matrix_height % PE == 0 & matrix_width % SIMD == 0 |\n", + "| pool_batch | PE | input_feature_map_channels % PE == 0 |\n", + "| streamingdataflowpartition | ~ | ~ |\n", + "| streamingdatawidthconverter_batch | ~ | ~ |\n", + "| streamingfifo | ~ | ~ |\n", + "| streamingmaxpool_batch | ~ | ~ |\n", + "| templates | ~ | ~ |\n", + "| thresholding_batch | PE | matrix_height % PE == 0 |\n", + "| tlastmarker | ~ | ~ |\n", + "| upsampler | ~ | ~ |\n", + "| vectorvectoractivation | PE & SIMD | kernel_height * kernel_width % SIMD == 0 & channels % PE == 0 |\n", + "+------------------------------------+------------+----------------------------------------------------------------+" + ] + } + ], + "metadata": { + "kernelspec": { + "display_name": "Python 3 (ipykernel)", + "language": "python", + "name": "python3" + }, + "language_info": { + "codemirror_mode": { + "name": "ipython", + "version": 3 + }, + "file_extension": ".py", + "mimetype": "text/x-python", + "name": "python", + "nbconvert_exporter": "python", + "pygments_lexer": "ipython3", + "version": "3.8.5" + } + }, + "nbformat": 4, + "nbformat_minor": 2 +} diff --git a/notebooks/advanced/finn-hw-arch.png b/notebooks/advanced/finn-hw-arch.png new file mode 100644 index 0000000000000000000000000000000000000000..e5631ab97d0d6bdce91aea4b916a7c7a2780560d GIT binary patch literal 110452 zcmdqJ^;?_G^9EYn-5rV*Z*jNa?(W6iDeh3*-HW?xAXq65#ogWA?WCXgd;W)WogZ># zpXA9ryEFIf&d$!A2qgtc6huPAPoF-aNK1*SeEI}s@aYreCwNHkCnVDJso*yV7Zpj- zPc;+7N8k%+3lVvdPoL`JkY0^pz}E7!U$OhoO6!D$YR z7PdTDkI-Jwd1AZ@1~it)sr^6?t_ZanvKllLI*yo{a1js#LZk=?jI)o&MM~NK(Y*wu z6gRws5l`Q^@%J%x@NjqcaDQlRWNZ9*frAVbCP#;dhNSp3hyH(UQOF7k=>OUw&}sni zm;bv5p)Bm*jsM!1N+=Zn*QUxR6#buoKw&9ij*$O^1;z(h!~eg6A^!g(cxW={LyPob z^|9lcWFzxFS8!Tv2)gvePPyph`>qP^6(;8osJz{2a zUN7nK-&}^m`{b%Q=dY#S`x8b+shtE%f0yMm;R9d!z#tKV0^Q62OIE|P@P~%~j-Kx~ zy<2dcmeH5n_5*r}HNE(BHaNs8qJj&<)~t2d)~y#8o?6JCixtJ}chX2-+o~&SZ*E>v zA$Qi;%BBtnxG?>tQTQrkD?zvS?_#9AEjWM3SLQD>+U!DniQE8*8IYlC*G<=e7c!N8 zP|YNn4r1>4R?$E{o_?Io`>QVpm96LGr0r93L178kN|ysoBE_s%sakW z^ni==)6;j9?I}`6cT@q~8yoAN{wK9w!=TgegOfPhwXGgfH!^iy_Qyx()tbbi8 z={F2avu2#FgR*FfafmV=J`h?GwuuaIXjvJR34NEhegqyO1KHyOiC<)`7ZWT#Q@5RA zoUi%gQu#Cn-y#!^G(bYXN6LI2_HlI&x-Pr0hnZW{u+SS7wk8E$fjf)Qd|HBvHzvR>4Tyu2eRf9 z2gmPjMc+=v_yn)Jx7BY-{kVg{SO65tnz0Wqj^F-LY{|GLzqE_9)*$B`@r@SnNwNp! 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buT`dm;Z>s*_pG<;|8i1O`&gE`<(>Zlk_qm? literal 0 HcmV?d00001 From 19097bdcf2ba5e8d02271e011dc1d676e9409486 Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 29 May 2023 15:53:28 +0100 Subject: [PATCH 149/665] [TlastMarker] Update interface naming for code gen --- .../custom_op/fpgadataflow/tlastmarker.py | 45 ++++++++++++------- 1 file changed, 28 insertions(+), 17 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/tlastmarker.py b/src/finn/custom_op/fpgadataflow/tlastmarker.py index 895a2eedab..6eaf03ab16 100644 --- a/src/finn/custom_op/fpgadataflow/tlastmarker.py +++ b/src/finn/custom_op/fpgadataflow/tlastmarker.py @@ -130,9 +130,11 @@ def docompute(self): self.code_gen_dict["$DOCOMPUTE$"] = [ "for(unsigned int i=0; i &in0, - hls::stream &out, unsigned int numIters)""" - % self.onnx_node.name + """void %s(hls::stream &in0_%s, + hls::stream &out_%s, unsigned int numIters)""" + % (self.onnx_node.name, self.hls_sname(), self.hls_sname()) ] else: self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - """void %s(hls::stream &in0, hls::stream &out)""" - % self.onnx_node.name + """void %s(hls::stream &in0_%s, + hls::stream &out_%s)""" + % (self.onnx_node.name, self.hls_sname(), self.hls_sname()) ] def pragmas(self): self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0 name=in0_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() ] self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out name=out_" + self.hls_sname() + "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() ) dyn_iters = self.get_nodeattr("DynIters") @@ -239,10 +248,12 @@ def get_outstream_width(self, ind=0): def strm_decl(self): self.code_gen_dict["$STREAMDECLARATIONS$"] = [] self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream in0 ("in0");' + 'hls::stream in0_%s ("in0_%s");' + % (self.hls_sname(), self.hls_sname()) ) self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream out ("out");' + 'hls::stream out_%s ("out_%s");' + % (self.hls_sname(), self.hls_sname()) ) def get_verilog_top_module_intf_names(self): From aae59b1e6448c3274c36daa5667f943ee0d56a9a Mon Sep 17 00:00:00 2001 From: Felix Jentzsch Date: Thu, 1 Jun 2023 11:18:40 +0200 Subject: [PATCH 150/665] [Zynq build] update PS IP version --- src/finn/transformation/fpgadataflow/templates.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/finn/transformation/fpgadataflow/templates.py b/src/finn/transformation/fpgadataflow/templates.py index f52bad0ffb..bc34f61a8b 100644 --- a/src/finn/transformation/fpgadataflow/templates.py +++ b/src/finn/transformation/fpgadataflow/templates.py @@ -135,7 +135,7 @@ create_bd_design "top" if {$ZYNQ_TYPE == "zynq_us+"} { - create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.4 zynq_ps + create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.5 zynq_ps apply_bd_automation -rule xilinx.com:bd_rule:zynq_ultra_ps_e -config {apply_board_preset "1" } [get_bd_cells zynq_ps] #activate one slave port, deactivate the second master port set_property -dict [list CONFIG.PSU__USE__S_AXI_GP2 {1}] [get_bd_cells zynq_ps] From 1679e01ee4526a220664b04a8c77cbf9ef13e3a1 Mon Sep 17 00:00:00 2001 From: Felix Jentzsch Date: Thu, 1 Jun 2023 13:51:12 +0200 Subject: [PATCH 151/665] Minor fixes and workarounds for version updates --- src/finn/analysis/fpgadataflow/post_synth_res.py | 2 +- tests/end2end/test_end2end_bnn_pynq.py | 6 +++--- tests/fpgadataflow/test_convert_to_hls_layers_cnv.py | 3 ++- tests/fpgadataflow/test_convert_to_hls_layers_fc.py | 4 +++- 4 files changed, 9 insertions(+), 6 deletions(-) diff --git a/src/finn/analysis/fpgadataflow/post_synth_res.py b/src/finn/analysis/fpgadataflow/post_synth_res.py index 8b9c5d2a04..1202120529 100644 --- a/src/finn/analysis/fpgadataflow/post_synth_res.py +++ b/src/finn/analysis/fpgadataflow/post_synth_res.py @@ -85,7 +85,7 @@ def get_instance_stats(inst_name): row = root.findall(".//*[@contents='%s']/.." % inst_name) if row != []: node_dict = {} - row = row[0].getchildren() + row = list(row[0]) for (restype, ind) in restype_to_ind.items(): node_dict[restype] = int(row[ind].attrib["contents"]) return node_dict diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index 62b76d2f13..4c68a018db 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -328,13 +328,13 @@ def test_export(self, topology, wbits, abits, QONNX_export): (model, ishape) = get_trained_network_and_ishape(topology, wbits, abits) chkpt_name = get_checkpoint_name(topology, wbits, abits, QONNX_export, "export") if QONNX_export: - export_qonnx(model, torch.randn(ishape), chkpt_name) + export_qonnx(model, torch.randn(ishape), chkpt_name, opset_version=13) qonnx_cleanup(chkpt_name, out_file=chkpt_name) model = ModelWrapper(chkpt_name) model = model.transform(ConvertQONNXtoFINN()) model.save(chkpt_name) else: - export_finn_onnx(model, torch.randn(ishape), chkpt_name) + export_finn_onnx(model, torch.randn(ishape), chkpt_name, opset_version=13) nname = "%s_w%da%d" % (topology, wbits, abits) update_dashboard_data(topology, wbits, abits, "network", nname) dtstr = datetime.now().strftime("%Y-%m-%d %H:%M:%S") @@ -374,7 +374,7 @@ def test_add_pre_and_postproc(self, topology, wbits, abits, QONNX_export): chkpt_preproc_name = get_checkpoint_name( topology, wbits, abits, QONNX_export, "preproc" ) - export_finn_onnx(totensor_pyt, torch.randn(ishape), chkpt_preproc_name) + export_finn_onnx(totensor_pyt, torch.randn(ishape), chkpt_preproc_name, opset_version=13) assert os.path.isfile(chkpt_preproc_name) # join preprocessing and core model pre_model = ModelWrapper(chkpt_preproc_name) diff --git a/tests/fpgadataflow/test_convert_to_hls_layers_cnv.py b/tests/fpgadataflow/test_convert_to_hls_layers_cnv.py index 73721b6cc5..001c353c8e 100644 --- a/tests/fpgadataflow/test_convert_to_hls_layers_cnv.py +++ b/tests/fpgadataflow/test_convert_to_hls_layers_cnv.py @@ -38,7 +38,7 @@ from qonnx.custom_op.registry import getCustomOp from qonnx.transformation.bipolar_to_xnor import ConvertBipolarMatMulToXnorPopcount from qonnx.transformation.fold_constants import FoldConstants -from qonnx.transformation.general import GiveReadableTensorNames, GiveUniqueNodeNames +from qonnx.transformation.general import GiveReadableTensorNames, GiveUniqueNodeNames, GiveUniqueParameterTensors from qonnx.transformation.infer_data_layouts import InferDataLayouts from qonnx.transformation.infer_shapes import InferShapes from qonnx.transformation.lower_convs_to_matmul import LowerConvsToMatMul @@ -67,6 +67,7 @@ def test_convert_to_hls_layers_cnv_w1a1(fused_activation): model = model.transform(InferShapes()) model = model.transform(FoldConstants()) model = model.transform(GiveUniqueNodeNames()) + model = model.transform(GiveUniqueParameterTensors()) model = model.transform(GiveReadableTensorNames()) model = model.transform(Streamline()) model = model.transform(LowerConvsToMatMul()) diff --git a/tests/fpgadataflow/test_convert_to_hls_layers_fc.py b/tests/fpgadataflow/test_convert_to_hls_layers_fc.py index 5a45638ba1..0fa7155ac5 100644 --- a/tests/fpgadataflow/test_convert_to_hls_layers_fc.py +++ b/tests/fpgadataflow/test_convert_to_hls_layers_fc.py @@ -39,7 +39,7 @@ from qonnx.custom_op.registry import getCustomOp from qonnx.transformation.bipolar_to_xnor import ConvertBipolarMatMulToXnorPopcount from qonnx.transformation.fold_constants import FoldConstants -from qonnx.transformation.general import GiveReadableTensorNames, GiveUniqueNodeNames +from qonnx.transformation.general import GiveReadableTensorNames, GiveUniqueNodeNames, GiveUniqueParameterTensors from qonnx.transformation.infer_shapes import InferShapes import finn.core.onnx_exec as oxe @@ -64,6 +64,7 @@ def test_convert_to_hls_layers_tfc_w1a1(): model = model.transform(InferShapes()) model = model.transform(FoldConstants()) model = model.transform(GiveUniqueNodeNames()) + model = model.transform(GiveUniqueParameterTensors()) model = model.transform(GiveReadableTensorNames()) model = model.transform(Streamline()) model = model.transform(ConvertBipolarMatMulToXnorPopcount()) @@ -135,6 +136,7 @@ def test_convert_to_hls_layers_tfc_w1a2(): model = model.transform(InferShapes()) model = model.transform(FoldConstants()) model = model.transform(GiveUniqueNodeNames()) + model = model.transform(GiveUniqueParameterTensors()) model = model.transform(GiveReadableTensorNames()) model = model.transform(Streamline()) from finn.transformation.fpgadataflow.convert_to_hls_layers import ( From dff63d3ef91b68f4cde5bb328ee75c3ee516e3fb Mon Sep 17 00:00:00 2001 From: Hugo LE BLEVEC Date: Mon, 5 Jun 2023 14:06:49 +0200 Subject: [PATCH 152/665] Updating headers --- .../custom_op/fpgadataflow/fmpadding_pixel.py | 29 +++++++++++++++++++ .../test_fpgadataflow_pixelpadding.py | 4 +-- 2 files changed, 31 insertions(+), 2 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/fmpadding_pixel.py b/src/finn/custom_op/fpgadataflow/fmpadding_pixel.py index caa7f199c4..d56b8d2943 100644 --- a/src/finn/custom_op/fpgadataflow/fmpadding_pixel.py +++ b/src/finn/custom_op/fpgadataflow/fmpadding_pixel.py @@ -1,3 +1,32 @@ +# Copyright (c) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of Xilinx nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + import numpy as np import os import warnings diff --git a/tests/fpgadataflow/test_fpgadataflow_pixelpadding.py b/tests/fpgadataflow/test_fpgadataflow_pixelpadding.py index 95f102e442..8d58adeeab 100644 --- a/tests/fpgadataflow/test_fpgadataflow_pixelpadding.py +++ b/tests/fpgadataflow/test_fpgadataflow_pixelpadding.py @@ -1,4 +1,4 @@ -# Copyright (c) 2020, Xilinx +# Copyright (c) 2023, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -11,7 +11,7 @@ # this list of conditions and the following disclaimer in the documentation # and/or other materials provided with the distribution. # -# * Neither the name of FINN nor the names of its +# * Neither the name of Xilinx nor the names of its # contributors may be used to endorse or promote products derived from # this software without specific prior written permission. # From 3d0b918195b5b5f04b38e2b067ddd797b317a8d7 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 7 Jun 2023 16:22:43 +0100 Subject: [PATCH 153/665] [CI] Update tool version in Jenkinsfile --- docker/jenkins/Jenkinsfile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index 2954877c2a..d8fea0124c 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -5,8 +5,8 @@ node { checkout scm } withEnv([ - "FINN_XILINX_PATH=/proj/xbuilds/SWIP/2022.2_1014_8888/installs/lin64", - "FINN_XILINX_VERSION=2022.2", + "FINN_XILINX_PATH=/proj/xbuilds/SWIP/2023.1_0507_1903/installs/lin64", + "FINN_XILINX_VERSION=2023.1", "FINN_DOCKER_TAG=xilinx/finn:jenkins", "FINN_HOST_BUILD_DIR=/scratch/users/finn_ci", "PLATFORM_REPO_PATHS=/opt/xilinx/platforms" From 1c36cdbbe7ac9c8d18414cacb27149f45c03c890 Mon Sep 17 00:00:00 2001 From: Felix Jentzsch Date: Thu, 8 Jun 2023 13:13:04 +0200 Subject: [PATCH 154/665] [Zynq build] Retrieve auxiliary IP versions from catalog --- src/finn/transformation/fpgadataflow/templates.py | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/templates.py b/src/finn/transformation/fpgadataflow/templates.py index bc34f61a8b..5ffb5e4f46 100644 --- a/src/finn/transformation/fpgadataflow/templates.py +++ b/src/finn/transformation/fpgadataflow/templates.py @@ -135,7 +135,8 @@ create_bd_design "top" if {$ZYNQ_TYPE == "zynq_us+"} { - create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.5 zynq_ps + set zynq_ps_vlnv [get_property VLNV [get_ipdefs "xilinx.com:ip:zynq_ultra_ps_e:*"]] + create_bd_cell -type ip -vlnv $zynq_ps_vlnv zynq_ps apply_bd_automation -rule xilinx.com:bd_rule:zynq_ultra_ps_e -config {apply_board_preset "1" } [get_bd_cells zynq_ps] #activate one slave port, deactivate the second master port set_property -dict [list CONFIG.PSU__USE__S_AXI_GP2 {1}] [get_bd_cells zynq_ps] @@ -144,7 +145,8 @@ set_property -dict [list CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0}] [get_bd_cells zynq_ps] set_property -dict [list CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ [expr int($FREQ_MHZ)]] [get_bd_cells zynq_ps] } elseif {$ZYNQ_TYPE == "zynq_7000"} { - create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 zynq_ps + set zynq_ps_vlnv [get_property VLNV [get_ipdefs "xilinx.com:ip:processing_system7:*"]] + create_bd_cell -type ip -vlnv $zynq_ps_vlnv zynq_ps apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" apply_board_preset "1" Master "Disable" Slave "Disable" } [get_bd_cells zynq_ps] set_property -dict [list CONFIG.PCW_USE_S_AXI_HP0 {1}] [get_bd_cells zynq_ps] set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ [expr int($FREQ_MHZ)]] [get_bd_cells zynq_ps] @@ -153,8 +155,10 @@ } #instantiate axi interconnect, axi smartconnect -create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 -create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 +set interconnect_vlnv [get_property VLNV [get_ipdefs -all "xilinx.com:ip:axi_interconnect:*" -filter design_tool_contexts=~*IPI*]] +set smartconnect_vlnv [get_property VLNV [get_ipdefs "xilinx.com:ip:smartconnect:*"]] +create_bd_cell -type ip -vlnv $interconnect_vlnv axi_interconnect_0 +create_bd_cell -type ip -vlnv $smartconnect_vlnv smartconnect_0 #set number of axilite interfaces, and number of axi master interfaces set_property -dict [list CONFIG.NUM_SI $NUM_AXIMM] [get_bd_cells smartconnect_0] set_property -dict [list CONFIG.NUM_MI $NUM_AXILITE] [get_bd_cells axi_interconnect_0] From 8cb04e65ed38b64f968cc28f44d95f12af346df9 Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 9 Jun 2023 18:18:40 +0100 Subject: [PATCH 155/665] [Tests] Add node naming to cppsim tests --- tests/fpgadataflow/test_fpgadataflow_concat.py | 1 + tests/fpgadataflow/test_fpgadataflow_lookup.py | 1 + 2 files changed, 2 insertions(+) diff --git a/tests/fpgadataflow/test_fpgadataflow_concat.py b/tests/fpgadataflow/test_fpgadataflow_concat.py index 5fff286e54..2b2069a72b 100644 --- a/tests/fpgadataflow/test_fpgadataflow_concat.py +++ b/tests/fpgadataflow/test_fpgadataflow_concat.py @@ -95,6 +95,7 @@ def test_fpgadataflow_concat(exec_mode, idt): assert model.graph.node[0].op_type == "StreamingConcat" assert model.graph.node[0].domain == "finn.custom_op.fpgadataflow" if exec_mode == "cppsim": + model = model.transform(GiveUniqueNodeNames()) model = model.transform(PrepareCppSim()) model = model.transform(CompileCppSim()) model = model.transform(SetExecMode("cppsim")) diff --git a/tests/fpgadataflow/test_fpgadataflow_lookup.py b/tests/fpgadataflow/test_fpgadataflow_lookup.py index da4204c81a..3164f2b4a6 100644 --- a/tests/fpgadataflow/test_fpgadataflow_lookup.py +++ b/tests/fpgadataflow/test_fpgadataflow_lookup.py @@ -122,6 +122,7 @@ def test_fpgadataflow_lookup(edt, embedding_cfg, exec_mode): assert model.graph.node[0].input[1] == ename assert model.graph.node[0].output[0] == oname if exec_mode == "cppsim": + model = model.transform(GiveUniqueNodeNames()) model = model.transform(PrepareCppSim()) model = model.transform(CompileCppSim()) model = model.transform(SetExecMode("cppsim")) From c4c6f8b1eb89284f0ecd5c7d24e57f27cd260fe5 Mon Sep 17 00:00:00 2001 From: Hugo LE BLEVEC Date: Mon, 12 Jun 2023 10:34:58 +0200 Subject: [PATCH 156/665] [Deconvolution] Creating fpgadataflow test with full deconv (pixel padding + conv) --- .../fpgadataflow/test_fpgadataflow_deconv.py | 306 ++++++++++++++++++ 1 file changed, 306 insertions(+) create mode 100644 tests/fpgadataflow/test_fpgadataflow_deconv.py diff --git a/tests/fpgadataflow/test_fpgadataflow_deconv.py b/tests/fpgadataflow/test_fpgadataflow_deconv.py new file mode 100644 index 0000000000..07d1d30b16 --- /dev/null +++ b/tests/fpgadataflow/test_fpgadataflow_deconv.py @@ -0,0 +1,306 @@ +# Copyright (c) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of Xilinx nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import pytest + +import numpy as np +import os +from onnx import TensorProto, helper +from qonnx.core.datatype import DataType +from qonnx.core.modelwrapper import ModelWrapper +from qonnx.custom_op.registry import getCustomOp +from qonnx.transformation.general import GiveUniqueNodeNames +from qonnx.transformation.infer_datatypes import InferDataTypes +from qonnx.transformation.infer_shapes import InferShapes +from qonnx.transformation.lower_convs_to_matmul import LowerConvsToMatMul +from qonnx.util.basic import gen_finn_dt_tensor, qonnx_make_model + +import finn.core.onnx_exec as oxe +from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim +from finn.transformation.fpgadataflow.convert_to_hls_layers import ( + InferConvInpGen, + InferQuantizedMatrixVectorActivation, +) +from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP +from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP +from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim +from finn.transformation.fpgadataflow.prepare_ip import PrepareIP +from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim +from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.streamline.absorb import AbsorbConsecutiveTransposes +from finn.util.basic import pynq_part_map + +test_pynq_board = os.getenv("PYNQ_BOARD", default="Pynq-Z1") +test_fpga_part = pynq_part_map[test_pynq_board] +target_clk_ns = 10 + + +def convolution_2d( + x: np.ndarray, + weight: np.ndarray, + in_channels: int, + out_channels: int, + kernel_size: int = 3, + padding: int = 0, + stride: int = 1, +) -> np.ndarray: + Ic, Ih, Iw = x[0, :].shape + assert Ic == in_channels + Oh = 1 + (Ih - kernel_size + 2 * padding) // stride + Ow = 1 + (Iw - kernel_size + 2 * padding) // stride + output = np.zeros((1, out_channels, Oh, Ow)) + for oh in range(Oh): + for ow in range(Ow): + for oc in range(out_channels): + for ic in range(in_channels): + for kh in range(kernel_size): + for kw in range(kernel_size): + ih = stride * oh + kh - padding + iw = stride * ow + kw - padding + if ih >= 0 and ih < Ih and iw >= 0 and iw < Iw: + output[0, oc, oh, ow] += ( + weight[oc, ic, kh, kw] * x[0, ic, ih, iw] + ) + return output + + +def fractionally_strided_convolution( + x: np.ndarray, + weight: np.ndarray, + in_channels: int, + out_channels: int, + kernel_size: int = 3, + padding: int = 0, + stride: np.ndarray = np.array([1, 1]), +) -> np.ndarray: + x_ = np.zeros( + ( + 1, + x.shape[1], + x.shape[2] + (x.shape[2] - 1) * (stride[0] - 1), + x.shape[3] + (x.shape[3] - 1) * (stride[1] - 1), + ) + ) + # adding the zeros into the input space for the fractional strides + for i in range(x.shape[2]): + for j in range(x.shape[3]): + ih = i * stride[0] + iw = j * stride[1] + x_[0, :, ih, iw] = x[0, :, i, j] + padding = kernel_size - padding - 1 + stride = 1 + # weight = np.rot90(weight, 2, [2,3]) + # weight = np.moveaxis(weight, 0, 1) + output = convolution_2d( + x_, + weight=weight, + in_channels=in_channels, + out_channels=out_channels, + kernel_size=kernel_size, + stride=stride, + padding=padding, + ) + return output + + +def set_up_reference_model(idt, wdt, k, idim, ifm_ch, ofm_ch, stride, padding, simd): + + idim_h, idim_w = idim + stride_h, stride_w = stride + odim_h = (idim_h - 1) * stride_h - 2 * padding + (k - 1) + 1 + odim_w = (idim_w - 1) * stride_w - 2 * padding + (k - 1) + 1 + + odt = DataType["INT32"] + + padded_odim_h = idim_h + (idim_h - 1) * (stride_h - 1) + padded_odim_w = idim_w + (idim_w - 1) * (stride_w - 1) + conv_padding = k - padding - 1 + + inp = helper.make_tensor_value_info( + "inp", TensorProto.FLOAT, [1, idim_h, idim_w, ifm_ch] + ) + outp = helper.make_tensor_value_info( + "outp", TensorProto.FLOAT, [1, ofm_ch, odim_h, odim_w] + ) + out_pad = helper.make_tensor_value_info( + "out_pad", TensorProto.FLOAT, [1, padded_odim_h, padded_odim_w, ifm_ch] + ) + out_pad_trans = helper.make_tensor_value_info( + "out_pad_trans", TensorProto.FLOAT, [1, ifm_ch, padded_odim_h, padded_odim_w] + ) + W = helper.make_tensor_value_info("W", TensorProto.FLOAT, [ofm_ch, ifm_ch, k, k]) + + FMPadding_Pixel = helper.make_node( + "FMPadding_Pixel", + [inp], + [out_pad], + domain="finn.custom_op.fpgadataflow", + backend="fpgadataflow", + ImgDim=idim, + Stride=stride, + NumChannels=ifm_ch, + inputDataType=str(idt.name), + numInputVectors=1, + SIMD=simd, + ) + Transpose = helper.make_node( + "Transpose", ["out_pad"], ["out_pad_trans"], perm=[0, 3, 1, 2] + ) + + Conv = helper.make_node( + "Conv", + [out_pad_trans, W], + [outp], + dilations=(1, 1), + group=1, + kernel_shape=(k, k), + pads=(conv_padding, conv_padding, conv_padding, conv_padding), + strides=(1, 1), + ) + + node_list = [FMPadding_Pixel, Transpose, Conv] + value_info = [W] + + graph = helper.make_graph( + nodes=node_list, + name="deconv_graph", + inputs=[inp], + outputs=[outp], + value_info=value_info, + ) + model = qonnx_make_model(graph, producer_name="deconv-model") + model = ModelWrapper(model) + + # initialize model + model.set_tensor_datatype("inp", idt) + model.set_tensor_datatype(model.graph.output[0].name, odt) + model.set_tensor_datatype("W", wdt) + + w_tensor = gen_finn_dt_tensor(wdt, [ofm_ch, ifm_ch, k, k]) + model.set_initializer("W", w_tensor) + + model = model.transform(InferShapes()) + + return model + + +# input image dimension +@pytest.mark.parametrize("idim", [[8, 8], [10, 8]]) +# number of rows and number of cols to add +@pytest.mark.parametrize("stride", [[2, 2], [2, 3]]) +# number of channels +@pytest.mark.parametrize("ifm_ch", [2, 4]) +# number of channels +@pytest.mark.parametrize("ofm_ch", [2, 4]) +# Input parallelism +@pytest.mark.parametrize("simd", [1, 2]) +# PE +@pytest.mark.parametrize("pe", [1, 2]) +# kernel size +@pytest.mark.parametrize("k", [2, 4]) +# padding +@pytest.mark.parametrize("padding", [0, 1]) +# execution mode +@pytest.mark.parametrize("mode", ["cppsim", "rtlsim"]) +# @pytest.mark.parametrize("mode", ["stitched_ip_rtlsim"]) +@pytest.mark.fpgadataflow +@pytest.mark.slow +@pytest.mark.vivado +def test_fpgadataflow_deconv(idim, stride, ifm_ch, ofm_ch, simd, pe, k, padding, mode): + idt = wdt = DataType["INT4"] + idim_h, idim_w = idim + stride_h, stride_w = stride + + if idim_h == idim_w and stride_h == stride_w: + convinpgen_rtl = False + else: + convinpgen_rtl = True + + if convinpgen_rtl and mode == "cppsim": + pytest.skip("ConvolutionInputGenerator_rtl has no cppsim, skipping") + + model = set_up_reference_model( + idt, wdt, k, idim, ifm_ch, ofm_ch, stride, padding, simd + ) + + odim_h = (idim_h - 1) * stride_h - 2 * padding + (k - 1) + 1 + odim_w = (idim_w - 1) * stride_w - 2 * padding + (k - 1) + 1 + + input_tensor = gen_finn_dt_tensor(idt, [1, idim_h, idim_w, ifm_ch]) + weight_tensor = model.get_initializer("W") + input_dict = {"inp": input_tensor} + + model = model.transform(LowerConvsToMatMul()) + model = model.transform(InferDataTypes()) + model = model.transform(InferConvInpGen(use_rtl_variant=convinpgen_rtl)) + model = model.transform(InferQuantizedMatrixVectorActivation()) + model = model.transform(AbsorbConsecutiveTransposes()) + model = model.transform(InferShapes()) + if mode == "stitched_ip_rtlsim": + model = model.transform(SetExecMode("rtlsim")) + else: + model = model.transform(SetExecMode(mode)) + model = model.transform(GiveUniqueNodeNames()) + + for n in model.graph.node: + if n.op_type == "ConvolutionInputGenerator" and not convinpgen_rtl: + convinputgen_node = getCustomOp(n) + convinputgen_node.set_nodeattr("SIMD", simd) + elif n.op_type == "MatrixVectorActivation": + mvau_node = getCustomOp(n) + mvau_node.set_nodeattr("PE", pe) + mvau_node.set_nodeattr("SIMD", simd) + + if mode == "cppsim": + model = model.transform(PrepareCppSim()) + model = model.transform(CompileCppSim()) + elif mode == "rtlsim": + model = model.transform(PrepareIP(test_fpga_part, target_clk_ns)) + model = model.transform(HLSSynthIP()) + model = model.transform(PrepareRTLSim()) + elif mode == "stitched_ip_rtlsim": + model = model.transform(PrepareIP(test_fpga_part, target_clk_ns)) + model = model.transform(HLSSynthIP()) + model = model.transform( + CreateStitchedIP(test_fpga_part, target_clk_ns, vitis=False) + ) + + y_produced = oxe.execute_onnx(model, input_dict)["outp"] + expected_oshape = (1, ofm_ch, odim_h, odim_w) + assert y_produced.shape == expected_oshape + + y_expected = fractionally_strided_convolution( + input_tensor.transpose(0, 3, 1, 2), + weight_tensor, + ifm_ch, + ofm_ch, + k, + padding, + stride, + ) + assert (y_produced == y_expected).all() From 488dc9fd6ce39bd50bb8053cef7baba67fddf2a7 Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Mon, 12 Jun 2023 15:22:28 +0100 Subject: [PATCH 157/665] remove mention of remote_exec and remote_pynq options Signed-off-by: Fionn O'Donohoe --- src/finn/core/onnx_exec.py | 11 +- src/finn/core/remote_exec.py | 119 ------------------ .../fpgadataflow/make_deployment.py | 1 - .../fpgadataflow/template_driver.py | 2 +- .../test_fpgadataflow_ipstitch.py | 1 - 5 files changed, 3 insertions(+), 131 deletions(-) delete mode 100644 src/finn/core/remote_exec.py diff --git a/src/finn/core/onnx_exec.py b/src/finn/core/onnx_exec.py index 2695113661..daecb59743 100644 --- a/src/finn/core/onnx_exec.py +++ b/src/finn/core/onnx_exec.py @@ -31,7 +31,6 @@ import qonnx.analysis.topology as ta from qonnx.core.onnx_exec import execute_onnx as execute_onnx_base -from finn.core.remote_exec import remote_exec from finn.core.rtlsim_exec import rtlsim_exec @@ -51,7 +50,6 @@ def execute_onnx( # check if model has an execution mode set # if None, execute model node using the QONNX-provided execute_onnx impl - # if set to "remote_pynq" execute model on PYNQ board # if set to "rtlsim" execute model using pyverilator model_exec_mode = model.get_metadata_prop("exec_mode") if (model_exec_mode is None) or (model_exec_mode == ""): @@ -91,22 +89,17 @@ def execute_onnx( # check if model has an execution mode set # if None, execute model node by node using execute_node() - # if set to "remote_pynq" execute model on PYNQ board # if set to "rtlsim" execute model using pyverilator model_exec_mode = model.get_metadata_prop("exec_mode") if (model_exec_mode is None) or (model_exec_mode == ""): return execute_onnx_base() - elif model_exec_mode == "remote_pynq": - # use remote exec metadata built into model to execute on a remote PYNQ - remote_exec(model, execution_context) elif model_exec_mode == "rtlsim": # use stitched IP for rtlsim rtlsim_exec(model, execution_context) else: raise Exception( - """Metadata property "exec_mode" is set to an unknown value. - Can be left unset or has to be set to "remote_pynq" for remote execution - on PYNQ board or "rtlsim" for execution using pyverilator!""" + """Metadata property "exec_mode" is set to an unknown value. Can be left + unset or has to be set to "rtlsim" for execution using pyverilator!""" ) if return_full_exec_context: diff --git a/src/finn/core/remote_exec.py b/src/finn/core/remote_exec.py deleted file mode 100644 index f487b48f86..0000000000 --- a/src/finn/core/remote_exec.py +++ /dev/null @@ -1,119 +0,0 @@ -# Copyright (c) 2020 Xilinx, Inc. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# * Redistributions of source code must retain the above copyright notice, this -# list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# * Neither the name of Xilinx nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -import numpy as np -import os -import subprocess -import warnings - - -def remote_exec(model, execution_context): - """Executes the given model remotely on the pynq board. The metadata properties - related to the pynq board have to be set. The execution context contains the - input values.""" - # TODO fix for multi input-output - pynq_ip = model.get_metadata_prop("pynq_ip") - pynq_port = int(model.get_metadata_prop("pynq_port")) - pynq_username = model.get_metadata_prop("pynq_username") - pynq_password = model.get_metadata_prop("pynq_password") - pynq_target_dir = model.get_metadata_prop("pynq_target_dir") - deployment_dir = model.get_metadata_prop("pynq_deploy_dir") - platform = model.get_metadata_prop("platform") - assert platform in ["alveo", "zynq-iodma"] - bitfile = model.get_metadata_prop("bitfile") - bitfile = os.path.basename(bitfile) - if pynq_password == "": - if "zynq" in platform: - raise Exception("PYNQ board remote exec needs password for sudo") - else: - local_prefix = "" # assume we are using an ssh key - warnings.warn("Empty password, make sure you've set up an ssh key") - else: - local_prefix = "sshpass -p %s " % pynq_password - - if platform == "alveo": - # Alveo can run without sudo - remote_prefix = "" - elif "zynq" in platform: - # PYNQ Zynq boards need to execute with sudo - remote_prefix = "echo %s | sudo -S " % pynq_password - - inp = execution_context[model.graph.input[0].name] - # make copy of array before saving it - inp = inp.copy() - batchsize = inp.shape[0] - np.save(os.path.join(deployment_dir, "input.npy"), inp) - # extracting last folder of absolute path (deployment_dir) - deployment_folder = os.path.basename(os.path.normpath(deployment_dir)) - # copy input to PYNQ board - cmd = local_prefix + "scp -P{} -r {}/input.npy {}@{}:{}/{}".format( - pynq_port, - deployment_dir, - pynq_username, - pynq_ip, - pynq_target_dir, - deployment_folder, - ) - bash_command = ["/bin/bash", "-c", cmd] - process_scp_in = subprocess.Popen(bash_command, stdout=subprocess.PIPE) - process_scp_in.communicate() - - # use platform attribute for correct remote execution - if platform == "alveo": - remote_cmd = "bash -ic 'bash alveo_run.sh execute %d' \"" % batchsize - else: - remote_cmd = ( - "python3.6 driver.py --exec_mode=execute --batchsize={} " - "--bitfile={} --inputfile=input.npy --outputfile=output.npy " - '--platform={} "' - ).format(batchsize, bitfile, platform) - cmd = ( - local_prefix + 'ssh {}@{} -p {} "cd {}/{}; ' + remote_prefix + remote_cmd - ).format(pynq_username, pynq_ip, pynq_port, pynq_target_dir, deployment_folder) - bash_command = ["/bin/bash", "-c", cmd] - process_exec_accel = subprocess.Popen(bash_command, stdout=subprocess.PIPE) - process_exec_accel.communicate() - # remove stale output file from local dir, if any - try: - os.remove("{}/output.npy".format(deployment_dir)) - except FileNotFoundError: - pass - # copy generated output to local - cmd = local_prefix + "scp -P{} {}@{}:{}/{}/output.npy {}".format( - pynq_port, - pynq_username, - pynq_ip, - pynq_target_dir, - deployment_folder, - deployment_dir, - ) - bash_command = ["/bin/bash", "-c", cmd] - process_scp_out = subprocess.Popen(bash_command, stdout=subprocess.PIPE) - process_scp_out.communicate() - outp = np.load("{}/output.npy".format(deployment_dir)) - execution_context[model.graph.output[0].name] = outp diff --git a/src/finn/transformation/fpgadataflow/make_deployment.py b/src/finn/transformation/fpgadataflow/make_deployment.py index d4684dc83c..aa83b600cb 100644 --- a/src/finn/transformation/fpgadataflow/make_deployment.py +++ b/src/finn/transformation/fpgadataflow/make_deployment.py @@ -96,7 +96,6 @@ def apply(self, model): pynq_driver_dir = model.get_metadata_prop("pynq_driver_dir") copy_tree(pynq_driver_dir, deployment_dir) model.set_metadata_prop("pynq_deploy_dir", deployment_dir) - model.set_metadata_prop("exec_mode", "remote_pynq") # create target directory on PYNQ board cmd = 'ssh {}@{} -p {} "mkdir -p {}"'.format( diff --git a/src/finn/transformation/fpgadataflow/template_driver.py b/src/finn/transformation/fpgadataflow/template_driver.py index 05ee6ad920..158825191e 100644 --- a/src/finn/transformation/fpgadataflow/template_driver.py +++ b/src/finn/transformation/fpgadataflow/template_driver.py @@ -135,5 +135,5 @@ file.close() print("Results written to nw_metrics.txt") else: - raise Exception("Exec mode has to be set to remote_pynq or throughput_test") + raise Exception("Exec mode has to be set to execute or throughput_test") """ diff --git a/tests/fpgadataflow/test_fpgadataflow_ipstitch.py b/tests/fpgadataflow/test_fpgadataflow_ipstitch.py index b220338e69..7e4069f5c4 100644 --- a/tests/fpgadataflow/test_fpgadataflow_ipstitch.py +++ b/tests/fpgadataflow/test_fpgadataflow_ipstitch.py @@ -206,7 +206,6 @@ def test_fpgadataflow_ipstitch_gen_model(mem_mode): assert sdp_node.__class__.__name__ == "StreamingDataflowPartition" assert os.path.isfile(sdp_node.get_nodeattr("model")) model = load_test_checkpoint_or_skip(sdp_node.get_nodeattr("model")) - model.set_metadata_prop("exec_mode", "remote_pynq") model = model.transform(InsertTLastMarker()) model = model.transform(GiveUniqueNodeNames()) model = model.transform(PrepareIP(test_fpga_part, 5)) From 63ee3261f205a72d93183356b758031a2d6e8296 Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Mon, 12 Jun 2023 15:25:58 +0100 Subject: [PATCH 158/665] remove DeployToPYNQ() class and any test affected by the removal Signed-off-by: Fionn O'Donohoe --- src/finn/core/throughput_test.py | 79 ----------- .../fpgadataflow/make_deployment.py | 115 ---------------- src/finn/util/gdrive.py | 65 --------- tests/end2end/test_end2end_bnn_pynq.py | 123 +----------------- 4 files changed, 1 insertion(+), 381 deletions(-) delete mode 100644 src/finn/transformation/fpgadataflow/make_deployment.py delete mode 100644 src/finn/util/gdrive.py diff --git a/src/finn/core/throughput_test.py b/src/finn/core/throughput_test.py index 3533fd1339..08633be33b 100644 --- a/src/finn/core/throughput_test.py +++ b/src/finn/core/throughput_test.py @@ -28,90 +28,11 @@ import numpy as np import os -import subprocess -import warnings from qonnx.util.basic import gen_finn_dt_tensor from finn.core.rtlsim_exec import rtlsim_exec -def throughput_test_remote(model, batchsize=1000, timeout=None): - """Runs the throughput test for the given model remotely on the pynq board. - The metadata properties related to the pynq board have to be set. - Additionally a timeout for the SSH communication can be set. - Returns a dictionary with results of the throughput test. Returns None - if the test fails.""" - - pynq_ip = model.get_metadata_prop("pynq_ip") - pynq_port = int(model.get_metadata_prop("pynq_port")) - pynq_username = model.get_metadata_prop("pynq_username") - pynq_password = model.get_metadata_prop("pynq_password") - pynq_target_dir = model.get_metadata_prop("pynq_target_dir") - deployment_dir = model.get_metadata_prop("pynq_deploy_dir") - # extracting last folder of absolute path (deployment_dir) - deployment_folder = os.path.basename(os.path.normpath(deployment_dir)) - platform = model.get_metadata_prop("platform") - assert platform in ["alveo", "zynq-iodma"] - bitfile = model.get_metadata_prop("bitfile") - bitfile = os.path.basename(bitfile) - if pynq_password == "": - if "zynq" in platform: - raise Exception("PYNQ board remote exec needs password for sudo") - else: - local_prefix = "" # assume we are using an ssh key - warnings.warn("Empty password, make sure you've set up an ssh key") - else: - local_prefix = "sshpass -p %s " % pynq_password - - if platform == "alveo": - # Alveo can run without sudo but needs correct environment - remote_prefix = "conda activate finn-pynq-alveo; " - elif "zynq" in platform: - # PYNQ Zynq boards need to execute with sudo - remote_prefix = "echo %s | sudo -S " % pynq_password - - # use platform attribute for correct remote execution - if platform == "alveo": - remote_cmd = "bash -ic 'bash alveo_run.sh throughput_test %d' \"" % batchsize - else: - remote_cmd = ( - "python3.6 driver.py --exec_mode=throughput_test --batchsize={} " - "--bitfile={} --inputfile=input.npy --outputfile=output.npy " - '--platform={} "' - ).format(batchsize, bitfile, platform) - cmd = ( - local_prefix + 'ssh {}@{} -p {} "cd {}/{}; ' + remote_prefix + remote_cmd - ).format(pynq_username, pynq_ip, pynq_port, pynq_target_dir, deployment_folder) - bash_command = ["/bin/bash", "-c", cmd] - process_throughput_test = subprocess.Popen(bash_command, stdout=subprocess.PIPE) - process_throughput_test.communicate(timeout=timeout) - - # remove any pre-existing metrics file - try: - os.remove("{}/nw_metrics.txt".format(deployment_dir)) - except FileNotFoundError: - pass - - cmd = local_prefix + "scp -P{} {}@{}:{}/{}/nw_metrics.txt {}".format( - pynq_port, - pynq_username, - pynq_ip, - pynq_target_dir, - deployment_folder, - deployment_dir, - ) - bash_command = ["/bin/bash", "-c", cmd] - process_compile = subprocess.Popen(bash_command, stdout=subprocess.PIPE) - process_compile.communicate(timeout=timeout) - - try: - with open("{}/nw_metrics.txt".format(deployment_dir), "r") as file: - res = eval(file.read()) - return res - except FileNotFoundError: - return None - - def throughput_test_rtlsim(model, batchsize=100): """Runs a throughput test for the given IP-stitched model. When combined with tracing, useful to determine bottlenecks and required FIFO sizes.""" diff --git a/src/finn/transformation/fpgadataflow/make_deployment.py b/src/finn/transformation/fpgadataflow/make_deployment.py deleted file mode 100644 index aa83b600cb..0000000000 --- a/src/finn/transformation/fpgadataflow/make_deployment.py +++ /dev/null @@ -1,115 +0,0 @@ -# Copyright (c) 2020, Xilinx -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# * Redistributions of source code must retain the above copyright notice, this -# list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# * Neither the name of FINN nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -import os -import subprocess -from distutils.dir_util import copy_tree -from qonnx.transformation.base import Transformation -from shutil import copy - -import finn.transformation.fpgadataflow.templates as templates -from finn.util.basic import make_build_dir - - -class DeployToPYNQ(Transformation): - """Collects all necessary files for deployment and copies them to the PYNQ board. - Expects information about PYNQ board to make scp possible: - - IP address of board, username and password for board and target directory where - the files are stored on the board""" - - def __init__(self, ip, port, username, password, target_dir): - super().__init__() - self.ip = ip - self.port = port - self.username = username - self.password = password - self.target_dir = target_dir - - def apply(self, model): - # set metadata properties accordingly to user input specifications - model.set_metadata_prop("pynq_ip", self.ip) - model.set_metadata_prop("pynq_port", str(self.port)) - model.set_metadata_prop("pynq_username", self.username) - model.set_metadata_prop("pynq_password", self.password) - model.set_metadata_prop("pynq_target_dir", self.target_dir) - - # create directory for deployment files - deployment_dir = make_build_dir(prefix="pynq_deployment_") - model.set_metadata_prop("pynq_deployment_dir", deployment_dir) - - # get and copy necessary files - # .bit and .hwh file - bitfile = model.get_metadata_prop("bitfile") - hwh_file = model.get_metadata_prop("hw_handoff") - deploy_files = [bitfile, hwh_file] - - for dfile in deploy_files: - if dfile is not None: - copy(dfile, deployment_dir) - - # helper script for Alveo - platform = model.get_metadata_prop("platform") - if platform == "alveo": - alveo_run_sh = templates.alveo_run_sh_template - fill_dict = { - "$REMOTE_DEPLOY_DIR$": self.target_dir - + "/" - + os.path.basename(deployment_dir), - "$CONDA_ENV_NAME$": "finn-pynq-alveo", - "$REMOTE_XRT$": os.environ["XILINX_XRT"], - "$REMOTE_PLATFORM_REPO_PATHS$": os.environ["PLATFORM_REPO_PATHS"], - "$BITFILE$": os.path.basename(bitfile), - } - for key, value in fill_dict.items(): - alveo_run_sh = alveo_run_sh.replace(key, value) - alveo_run_sh_path = deployment_dir + "/alveo_run.sh" - with open(alveo_run_sh_path, "w") as f: - f.write(alveo_run_sh) - - # driver.py and python libraries - pynq_driver_dir = model.get_metadata_prop("pynq_driver_dir") - copy_tree(pynq_driver_dir, deployment_dir) - model.set_metadata_prop("pynq_deploy_dir", deployment_dir) - - # create target directory on PYNQ board - cmd = 'ssh {}@{} -p {} "mkdir -p {}"'.format( - self.username, self.ip, self.port, self.target_dir - ) - bash_command = ["/bin/bash", "-c", cmd] - process_compile = subprocess.Popen(bash_command, stdout=subprocess.PIPE) - process_compile.communicate() - # copy directory to PYNQ board using scp - cmd = "scp -P{} -r {} {}@{}:{}".format( - self.port, deployment_dir, self.username, self.ip, self.target_dir - ) - bash_command = ["/bin/bash", "-c", cmd] - process_compile = subprocess.Popen(bash_command, stdout=subprocess.PIPE) - process_compile.communicate() - - return (model, False) diff --git a/src/finn/util/gdrive.py b/src/finn/util/gdrive.py deleted file mode 100644 index d525437300..0000000000 --- a/src/finn/util/gdrive.py +++ /dev/null @@ -1,65 +0,0 @@ -# Copyright (c) 2020, Xilinx -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# * Redistributions of source code must retain the above copyright notice, this -# list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# * Neither the name of FINN nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -import gspread -import os -import warnings -from datetime import datetime - -from finn.util.basic import get_finn_root - - -def upload_to_end2end_dashboard(data_dict): - gdrive_key = get_finn_root() + "/gdrive-key/service_account.json" - if not os.path.isfile(gdrive_key): - warnings.warn("Google Drive key not found, skipping dashboard upload") - return - gc = gspread.service_account(filename=gdrive_key) - spreadsheet = gc.open("finn-end2end-dashboard") - worksheet = spreadsheet.get_worksheet(0) - keys = list(data_dict.keys()) - vals = list(data_dict.values()) - # check against existing header - existing_keys = worksheet.row_values(1) - if not set(existing_keys).issuperset(set(keys)): - # create new worksheet - dtstr = datetime.now().strftime("%Y-%m-%d %H:%M:%S") - worksheet = spreadsheet.add_worksheet( - title="Dashboard " + dtstr, rows=10, cols=len(keys), index=0 - ) - # create header row with keys - worksheet.update("A1:1", [keys]) - # freeze and make header bold - worksheet.freeze(rows=1) - worksheet.format("A1:1", {"textFormat": {"bold": True}}) - # insert values into new row at appropriate positions - worksheet.insert_row([], index=2) - for i in range(len(keys)): - colind = existing_keys.index(keys[i]) - col_letter = chr(ord("A") + colind) - worksheet.update("%s2" % col_letter, vals[i]) diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index 62b76d2f13..89b434b577 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -59,13 +59,12 @@ from qonnx.transformation.lower_convs_to_matmul import LowerConvsToMatMul from qonnx.transformation.merge_onnx_models import MergeONNXModels from qonnx.util.cleanup import cleanup as qonnx_cleanup -from scipy.stats import linregress import finn.transformation.fpgadataflow.convert_to_hls_layers as to_hls import finn.transformation.streamline.absorb as absorb from finn.analysis.fpgadataflow.dataflow_performance import dataflow_performance from finn.core.onnx_exec import execute_onnx -from finn.core.throughput_test import throughput_test_remote, throughput_test_rtlsim +from finn.core.throughput_test import throughput_test_rtlsim from finn.transformation.fpgadataflow.annotate_cycles import AnnotateCycles from finn.transformation.fpgadataflow.annotate_resources import AnnotateResources from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim @@ -75,7 +74,6 @@ from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP from finn.transformation.fpgadataflow.insert_dwc import InsertDWC -from finn.transformation.fpgadataflow.make_deployment import DeployToPYNQ from finn.transformation.fpgadataflow.make_pynq_driver import MakePYNQDriver from finn.transformation.fpgadataflow.minimize_accumulator_width import ( MinimizeAccumulatorWidth, @@ -95,7 +93,6 @@ MoveScalarLinearPastInvariants, ) from finn.util.basic import get_finn_root -from finn.util.gdrive import upload_to_end2end_dashboard from finn.util.pytorch import ToTensor from finn.util.test import ( execute_parent, @@ -715,121 +712,3 @@ def test_make_pynq_driver(self, topology, wbits, abits, QONNX_export, kind): model.save( get_checkpoint_name(topology, wbits, abits, QONNX_export, "driver_" + kind) ) - - @pytest.mark.parametrize("kind", ["zynq", "alveo"]) - def test_deploy(self, topology, wbits, abits, QONNX_export, kind): - prev_chkpt_name = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "driver_" + kind - ) - model = load_test_checkpoint_or_skip(prev_chkpt_name) - cfg = get_build_env(kind, target_clk_ns) - if cfg["ip"] == "": - pytest.skip("PYNQ board IP address not specified") - model = model.transform( - DeployToPYNQ( - cfg["ip"], - cfg["port"], - cfg["username"], - cfg["password"], - cfg["target_dir"], - ) - ) - # save the model to be able to link it to the parent - model.save( - get_checkpoint_name(topology, wbits, abits, QONNX_export, "deploy_" + kind) - ) - - @pytest.mark.parametrize("kind", ["zynq", "alveo"]) - def test_run_on_hw(self, topology, wbits, abits, QONNX_export, kind): - prev_chkpt_name = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "deploy_" + kind - ) - model = load_test_checkpoint_or_skip(prev_chkpt_name) # NOQA - cfg = get_build_env(kind, target_clk_ns) - if cfg["ip"] == "": - pytest.skip("PYNQ board IP address not specified") - (input_tensor_npy, output_tensor_npy) = get_golden_io_pair( - topology, wbits, abits, return_topk=1 - ) - parent_model = load_test_checkpoint_or_skip( - get_checkpoint_name(topology, wbits, abits, QONNX_export, "dataflow_parent") - ) - iname = parent_model.graph.input[0].name - oname = parent_model.graph.output[0].name - sdp_node = parent_model.get_nodes_by_op_type("StreamingDataflowPartition")[0] - sdp_node = getCustomOp(sdp_node) - sdp_node.set_nodeattr("model", prev_chkpt_name) - ret = execute_onnx(parent_model, {iname: input_tensor_npy}, True) - y = ret[oname] - assert np.isclose(y, output_tensor_npy).all() - - @pytest.mark.parametrize("kind", ["zynq", "alveo"]) - def test_throughput_hw(self, topology, wbits, abits, QONNX_export, kind): - prev_chkpt_name = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "deploy_" + kind - ) - end2end_example = "%s_w%da%d_%s" % (topology, wbits, abits, kind) - model = load_test_checkpoint_or_skip(prev_chkpt_name) # NOQA - cfg = get_build_env(kind, target_clk_ns) - if cfg["ip"] == "": - pytest.skip("PYNQ board IP address not specified") - ret = dict() - # try a range of batch sizes, some may fail due to insufficient DMA - # buffers - bsize_range_in = [8**i for i in range(5)] - bsize_range = [] - for bsize in bsize_range_in: - res = throughput_test_remote(model, bsize) - if res is not None: - ret[bsize] = res - bsize_range.append(bsize) - else: - # assume we reached largest possible N - break - y = [ret[key]["runtime[ms]"] for key in bsize_range] - lrret = linregress(bsize_range, y) - ret_str = "" - ret_str += "\n" + "%s Throughput Test Results" % end2end_example - ret_str += "\n" + "-----------------------------" - ret_str += "\n" + "From linear regression:" - ret_str += "\n" + "Invocation overhead: %f ms" % lrret.intercept - ret_str += "\n" + "Time per sample: %f ms" % lrret.slope - ret_str += "\n" + "Raw data:" - - ret_str += "\n" + "{:<8} {:<16} {:<16} {:<16} {:<16} {:<16}".format( - "N", "runtime[ms]", "fclk[mhz]", "fps", "DRAM rd[MB/s]", "DRAM wr[MB/s]" - ) - for k in bsize_range: - v = ret[k] - ret_str += "\n" + "{:<8} {:<16} {:<16} {:<16} {:<16} {:<16}".format( - k, - np.round(v["runtime[ms]"], 4), - v["fclk[mhz]"], - np.round(v["throughput[images/s]"], 2), - np.round(v["DRAM_in_bandwidth[MB/s]"], 2), - np.round(v["DRAM_out_bandwidth[MB/s]"], 2), - ) - ret_str += "\n" + "-----------------------------" - warnings.warn(ret_str) - largest_bsize = bsize_range[-1] - update_dashboard_data( - topology, wbits, abits, "fclk[mhz]", ret[largest_bsize]["fclk[mhz]"] - ) - update_dashboard_data( - topology, - wbits, - abits, - "throughput[images/s]", - ret[largest_bsize]["throughput[images/s]"], - ) - - def test_upload_results_to_dashboard(self, topology, wbits, abits, QONNX_export): - # ToDo: Extend the dashboard to also upload QONNX exported models? - if QONNX_export: - pytest.skip("Dashboard data upload is disabled for QONNX exported models.") - else: - dashboard_data = get_dashboard_data(topology, wbits, abits) - if len(dashboard_data.keys()) > 0: - upload_to_end2end_dashboard(dashboard_data) - else: - pytest.skip("No data to upload to dashboard") From fc2fa437186cf0e07c6a271b8753ec747ab300b4 Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Mon, 12 Jun 2023 15:28:20 +0100 Subject: [PATCH 159/665] remove standalone board access tests Signed-off-by: Fionn O'Donohoe --- tests/end2end/test_end2end_access_board.py | 56 ------------------ tests/end2end/test_end2end_cybsec_mlp.py | 61 -------------------- tests/end2end/test_ext_weights.py | 66 ---------------------- 3 files changed, 183 deletions(-) delete mode 100644 tests/end2end/test_end2end_access_board.py diff --git a/tests/end2end/test_end2end_access_board.py b/tests/end2end/test_end2end_access_board.py deleted file mode 100644 index ba3c49195b..0000000000 --- a/tests/end2end/test_end2end_access_board.py +++ /dev/null @@ -1,56 +0,0 @@ -# Copyright (c) 2021, Xilinx -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# * Redistributions of source code must retain the above copyright notice, this -# list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# * Neither the name of FINN nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -import pytest - -import subprocess - -from finn.util.test import get_build_env - - -@pytest.mark.board -@pytest.mark.end2end -def test_end2end_access_board(): - build_env = get_build_env("zynq", 5) - if build_env["ip"] == "": - pytest.skip("PYNQ board IP address not specified") - remote_cmd_base = [ - "ssh", - "-o", - "PreferredAuthentications=publickey", - "-o", - "PasswordAuthentication=no", - "%s@%s" % (build_env["username"], build_env["ip"]), - ] - test_text = "BoardIsAccessible" - touch_cmd = remote_cmd_base + ["echo %s" % test_text] - verif_res = subprocess.run( - touch_cmd, stdout=subprocess.PIPE, universal_newlines=True - ) - assert verif_res.returncode == 0 - assert verif_res.stdout.split("\n")[0] == test_text diff --git a/tests/end2end/test_end2end_cybsec_mlp.py b/tests/end2end/test_end2end_cybsec_mlp.py index d2a4d0287f..5e402bdeb4 100644 --- a/tests/end2end/test_end2end_cybsec_mlp.py +++ b/tests/end2end/test_end2end_cybsec_mlp.py @@ -34,10 +34,8 @@ import numpy as np import os import shutil -import subprocess import torch import torch.nn as nn -import wget from brevitas.core.quant import QuantType from brevitas.export import export_finn_onnx, export_qonnx from brevitas.nn import QuantIdentity, QuantLinear, QuantReLU @@ -225,62 +223,3 @@ def test_end2end_cybsec_mlp_build(QONNX_export): assert est_res_dict["total"]["LUT"] == 7904.0 assert est_res_dict["total"]["BRAM_18K"] == 36.0 shutil.copytree(output_dir + "/deploy", get_checkpoint_name("build", QONNX_export)) - - -@pytest.mark.end2end -@pytest.mark.xfail -@pytest.mark.parametrize("QONNX_export", [False, True]) -def test_end2end_cybsec_mlp_run_on_hw(QONNX_export): - build_env = get_build_env(build_kind, target_clk_ns) - assets_dir = pk.resource_filename("finn.qnn-data", "cybsec-mlp/") - deploy_dir = get_checkpoint_name("build", QONNX_export) - if not os.path.isdir(deploy_dir): - pytest.skip(deploy_dir + " not found from previous test step, skipping") - driver_dir = deploy_dir + "/driver" - assert os.path.isdir(driver_dir) - # put all assets into driver dir - shutil.copy(assets_dir + "/validate-unsw-nb15.py", driver_dir) - # put a copy of binarized dataset into driver dir - dataset_url = ( - "https://zenodo.org/record/4519767/files/unsw_nb15_binarized.npz?download=1" - ) - dataset_local = driver_dir + "/unsw_nb15_binarized.npz" - if not os.path.isfile(dataset_local): - wget.download(dataset_url, out=dataset_local) - assert os.path.isfile(dataset_local) - # create a shell script for running validation: 10 batches x 10 imgs - with open(driver_dir + "/validate.sh", "w") as f: - f.write( - """#!/bin/bash -cd %s/driver -echo %s | sudo -S python3.6 validate-unsw-nb15.py --batchsize=10 --limit_batches=10 - """ - % ( - build_env["target_dir"] + "/end2end_cybsecmlp_build", - build_env["password"], - ) - ) - # set up rsync command - remote_target = "%s@%s:%s" % ( - build_env["username"], - build_env["ip"], - build_env["target_dir"], - ) - rsync_res = subprocess.run(["rsync", "-avz", deploy_dir, remote_target]) - assert rsync_res.returncode == 0 - remote_verif_cmd = [ - "ssh", - "%s@%s" % (build_env["username"], build_env["ip"]), - "sh", - build_env["target_dir"] + "/end2end_cybsecmlp_build/driver/validate.sh", - ] - verif_res = subprocess.run( - remote_verif_cmd, - stdout=subprocess.PIPE, - universal_newlines=True, - input=build_env["password"], - ) - assert verif_res.returncode == 0 - log_output = verif_res.stdout.split("\n") - assert log_output[-3] == "batch 10 / 10 : total OK 93 NOK 7" - assert log_output[-2] == "Final accuracy: 93.000000" diff --git a/tests/end2end/test_ext_weights.py b/tests/end2end/test_ext_weights.py index 0a92c74a38..bef2e0ffa7 100644 --- a/tests/end2end/test_ext_weights.py +++ b/tests/end2end/test_ext_weights.py @@ -110,69 +110,3 @@ def test_end2end_ext_weights_build(): if os.path.isdir(get_checkpoint_name("build")): shutil.rmtree(get_checkpoint_name("build")) shutil.copytree(output_dir + "/deploy", get_checkpoint_name("build")) - - -@pytest.mark.board -@pytest.mark.end2end -@pytest.mark.xfail -def test_end2end_ext_weights_dataset(): - # make sure we have local copies of mnist dataset files - subprocess.check_output(["mkdir", "-p", mnist_local]) - for f in mnist_files: - if not os.path.isfile(mnist_local + "/" + f): - wget.download(mnist_url + "/" + f, out=mnist_local + "/" + f) - assert os.path.isfile(mnist_local + "/" + f) - # rsync to board - build_env = get_build_env(build_kind, target_clk_ns) - mnist_target = "%s@%s:%s" % (build_env["username"], build_env["ip"], "/tmp/") - - rsync_dataset_cmd = ["rsync", "-rv", mnist_local + "/", mnist_target] - subprocess.check_output(rsync_dataset_cmd) - - -@pytest.mark.end2end -@pytest.mark.xfail -def test_end2end_ext_weights_run_on_hw(): - build_env = get_build_env(build_kind, target_clk_ns) - deploy_dir = get_checkpoint_name("build") - if not os.path.isdir(deploy_dir): - pytest.skip(deploy_dir + " not found from previous test step, skipping") - driver_dir = deploy_dir + "/driver" - assert os.path.isdir(driver_dir) - # create a shell script for running validation: 10 batches x 10 imgs - with open(driver_dir + "/validate.sh", "w") as f: - f.write( - """#!/bin/bash -cd %s/driver -echo %s | sudo -S python3.6 validate.py --dataset mnist --bitfile %s - """ - % ( - build_env["target_dir"] + "/end2end_ext_weights_build", - build_env["password"], - "../bitfile/finn-accel.bit", - ) - ) - # set up rsync command - remote_target = "%s@%s:%s" % ( - build_env["username"], - build_env["ip"], - build_env["target_dir"], - ) - rsync_res = subprocess.run(["rsync", "-avz", deploy_dir, remote_target]) - assert rsync_res.returncode == 0 - remote_verif_cmd = [ - "ssh", - "%s@%s" % (build_env["username"], build_env["ip"]), - "sh", - build_env["target_dir"] + "/end2end_ext_weights_build/driver/validate.sh", - ] - verif_res = subprocess.run( - remote_verif_cmd, - stdout=subprocess.PIPE, - universal_newlines=True, - input=build_env["password"], - ) - assert verif_res.returncode == 0 - log_output = verif_res.stdout.split("\n") - assert log_output[-3] == "batch 100 / 100 : total OK 9296 NOK 704" - assert log_output[-2] == "Final accuracy: 92.960000" From e40e59dd2b890cae4126d8b4457ff831e90fe6e0 Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Mon, 12 Jun 2023 15:29:12 +0100 Subject: [PATCH 160/665] remove now unused template: alveo_run_sh_template Signed-off-by: Fionn O'Donohoe --- .../transformation/fpgadataflow/templates.py | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/templates.py b/src/finn/transformation/fpgadataflow/templates.py index f52bad0ffb..ce1545b5be 100644 --- a/src/finn/transformation/fpgadataflow/templates.py +++ b/src/finn/transformation/fpgadataflow/templates.py @@ -242,22 +242,6 @@ close_project """ -alveo_run_sh_template = """#!/bin/bash - -if [ "$#" -ne 2 ]; then - echo "Usage: alveo_run.sh " - exit -1 -fi - -cd $REMOTE_DEPLOY_DIR$ -eval "$(conda shell.bash hook)" -conda activate $CONDA_ENV_NAME$ -source $REMOTE_XRT$/setup.sh -export PLATFORM_REPO_PATHS=$REMOTE_PLATFORM_REPO_PATHS$ -python3.6 driver.py --exec_mode=$1 --batchsize=$2 --bitfile=$BITFILE$ \ - --inputfile=input.npy --outputfile=output.npy --platform=alveo -""" - vitis_gen_xml_report_tcl_template = """ open_project $VITIS_PROJ_PATH$/_x/link/vivado/vpl/prj/prj.xpr open_run impl_1 From bcc7ace9d2b522c214fcce619ee82a05fc881ae2 Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Mon, 12 Jun 2023 15:29:43 +0100 Subject: [PATCH 161/665] remove unused build environment parameters Signed-off-by: Fionn O'Donohoe --- src/finn/util/test.py | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/src/finn/util/test.py b/src/finn/util/test.py index bd8bde2820..4250079ef3 100644 --- a/src/finn/util/test.py +++ b/src/finn/util/test.py @@ -114,25 +114,14 @@ def get_build_env(kind, target_clk_ns): if kind == "zynq": ret["board"] = os.getenv("PYNQ_BOARD", default="Pynq-Z1") ret["part"] = pynq_part_map[ret["board"]] - ret["ip"] = os.getenv("PYNQ_IP", "") - ret["username"] = os.getenv("PYNQ_USERNAME", "xilinx") - ret["password"] = os.getenv("PYNQ_PASSWORD", "xilinx") - ret["port"] = os.getenv("PYNQ_PORT", 22) - ret["target_dir"] = os.getenv("PYNQ_TARGET_DIR", "/home/xilinx/finn") ret["build_fxn"] = ZynqBuild(ret["board"], target_clk_ns) elif kind == "alveo": ret["board"] = os.getenv("ALVEO_BOARD", default="U250") ret["part"] = alveo_part_map[ret["board"]] - ret["platform"] = alveo_default_platform[ret["board"]] - ret["ip"] = os.getenv("ALVEO_IP", "") - ret["username"] = os.getenv("ALVEO_USERNAME", "") - ret["password"] = os.getenv("ALVEO_PASSWORD", "") - ret["port"] = os.getenv("ALVEO_PORT", 22) - ret["target_dir"] = os.getenv("ALVEO_TARGET_DIR", "/tmp/finn_alveo_deploy") ret["build_fxn"] = VitisBuild( ret["part"], target_clk_ns, - ret["platform"], + alveo_default_platform[ret["board"]], strategy=VitisOptStrategy.BUILD_SPEED, ) else: From 9ddc555ea851549ba90ac6074e6e33741a2bf96f Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Mon, 12 Jun 2023 15:30:58 +0100 Subject: [PATCH 162/665] update RST files based on remote_exec removal Signed-off-by: Fionn O'Donohoe --- docs/finn/getting_started.rst | 3 --- docs/finn/source_code/finn.core.rst | 8 -------- 2 files changed, 11 deletions(-) diff --git a/docs/finn/getting_started.rst b/docs/finn/getting_started.rst index 9b3111b70e..c575ca7e3b 100644 --- a/docs/finn/getting_started.rst +++ b/docs/finn/getting_started.rst @@ -107,9 +107,6 @@ These are summarized below: * (optional) ``LOCALHOST_URL`` (default localhost) sets the base URL for accessing e.g. Netron from inside the container. Useful when running FINN remotely. * (optional) ``NETRON_PORT`` (default 8081) changes the port for Netron inside Docker * (optional) ``PYNQ_BOARD`` or ``ALVEO_BOARD`` specifies the type of PYNQ/Alveo board used (see "supported hardware" below) for the test suite -* (optional) ``PYNQ_IP`` and ``PYNQ_PORT`` (or ``ALVEO_IP`` and ``ALVEO_PORT``) specify ip address and port number to access the PYNQ board / Alveo target -* (optional) ``PYNQ_USERNAME`` and ``PYNQ_PASSWORD`` (or ``ALVEO_USERNAME`` and ``ALVEO_PASSWORD``) specify the PYNQ board / Alveo host access credentials for the test suite. For PYNQ, password is always needed to run as sudo. For Alveo, you can leave the password empty and place your ssh private key in the ``finn/ssh_keys`` folder to use keypair authentication. -* (optional) ``PYNQ_TARGET_DIR`` (or ``ALVEO_TARGET_DIR``) specifies the target dir on the PYNQ board / Alveo host for the test suite * (optional) ``IMAGENET_VAL_PATH`` specifies the path to the ImageNet validation directory for tests. * (optional) ``FINN_DOCKER_PREBUILT`` (default 0) if set to 1 then skip Docker image building and use the image tagged with ``FINN_DOCKER_TAG``. * (optional) ``FINN_DOCKER_TAG`` (autogenerated) specifies the Docker image tag to use. diff --git a/docs/finn/source_code/finn.core.rst b/docs/finn/source_code/finn.core.rst index afa1ecffa0..28cb47eaf7 100644 --- a/docs/finn/source_code/finn.core.rst +++ b/docs/finn/source_code/finn.core.rst @@ -54,14 +54,6 @@ finn.core.onnx\_exec :undoc-members: :show-inheritance: -finn.core.remote\_exec ------------------------------ - -.. automodule:: finn.core.remote_exec - :members: - :undoc-members: - :show-inheritance: - finn.core.rtlsim\_exec ----------------------------- From f593d53762d7f2a3687dd9b525a0a5dbd8b8bf19 Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Mon, 12 Jun 2023 15:36:39 +0100 Subject: [PATCH 163/665] update RST files based on gdrive removal Signed-off-by: Fionn O'Donohoe --- docs/finn/source_code/finn.util.rst | 8 -------- 1 file changed, 8 deletions(-) diff --git a/docs/finn/source_code/finn.util.rst b/docs/finn/source_code/finn.util.rst index 7ba3b252ab..aebd0604f4 100644 --- a/docs/finn/source_code/finn.util.rst +++ b/docs/finn/source_code/finn.util.rst @@ -99,14 +99,6 @@ finn.util.fpgadataflow :undoc-members: :show-inheritance: -finn.util.gdrive ------------------------------ - -.. automodule:: finn.util.gdrive - :members: - :undoc-members: - :show-inheritance: - finn.util.hls --------------- From 4ccff628d5cadc8441f3fce6fa018b461cb5bd2d Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Wed, 14 Jun 2023 15:15:37 +0100 Subject: [PATCH 164/665] remove update_dashboard util functions as uploading results was previously removed Signed-off-by: Fionn O'Donohoe --- tests/end2end/test_end2end_bnn_pynq.py | 38 -------------------------- 1 file changed, 38 deletions(-) diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index 89b434b577..27aaa1986d 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -34,13 +34,10 @@ # import pytorch before onnx, so we make sure to import onnx first import onnx # NOQA import os -import subprocess import torch import warnings from brevitas.export import export_finn_onnx, export_qonnx -from collections import OrderedDict from dataset_loading import cifar, mnist -from datetime import datetime from qonnx.core.datatype import DataType from qonnx.core.modelwrapper import ModelWrapper from qonnx.custom_op.registry import getCustomOp @@ -119,24 +116,6 @@ def get_checkpoint_name(topology, wbits, abits, QONNX_export, step): ) -def get_dashboard_data(topology, wbits, abits): - stats_file = build_dir + "/end2end_%s_w%da%d.txt" % (topology, wbits, abits) - stats_dict = OrderedDict() - if os.path.isfile(stats_file): - with open(stats_file, "r") as f: - stats_dict_txt = f.read() - stats_dict = eval(stats_dict_txt) - return stats_dict - - -def update_dashboard_data(topology, wbits, abits, key, val): - stats_dict = get_dashboard_data(topology, wbits, abits) - stats_dict[key] = val - stats_file = build_dir + "/end2end_%s_w%da%d.txt" % (topology, wbits, abits) - with open(stats_file, "w") as f: - f.write(str(stats_dict)) - - def fold_tfc(model): fc_layers = model.get_nodes_by_op_type("MatrixVectorActivation") # (PE, SIMD, ramstyle) for each layer @@ -332,15 +311,6 @@ def test_export(self, topology, wbits, abits, QONNX_export): model.save(chkpt_name) else: export_finn_onnx(model, torch.randn(ishape), chkpt_name) - nname = "%s_w%da%d" % (topology, wbits, abits) - update_dashboard_data(topology, wbits, abits, "network", nname) - dtstr = datetime.now().strftime("%Y-%m-%d %H:%M:%S") - update_dashboard_data(topology, wbits, abits, "datetime", dtstr) - finn_commit = subprocess.check_output( - ["git", "rev-parse", "HEAD"], cwd=get_finn_root() - ) - finn_commit = finn_commit.decode("utf-8").strip() - update_dashboard_data(topology, wbits, abits, "finn-commit", finn_commit) assert os.path.isfile(chkpt_name) def test_import_and_tidy(self, topology, wbits, abits, QONNX_export): @@ -641,10 +611,6 @@ def test_throughput_rtlsim(self, topology, wbits, abits, QONNX_export, kind): ret = throughput_test_rtlsim(model, batchsize=batchsize) res_cycles = ret["cycles"] est_cycles = latency + cycles_per_sample_est * batchsize - # warnings.warn("Estimated & rtlsim performance: " + str(perf)) - # for (k, v) in perf.items(): - # update_dashboard_data(topology, wbits, abits, k, v) - update_dashboard_data(topology, wbits, abits, "cycles_rtlsim", latency) assert (abs(res_cycles - est_cycles) / res_cycles) < 0.15 @pytest.mark.slow @@ -688,10 +654,6 @@ def test_build(self, topology, wbits, abits, QONNX_export, kind): cfg = get_build_env(kind, target_clk_ns) model = model.transform(cfg["build_fxn"]) model = model.transform(AnnotateResources("synth")) - synth_dct = eval(model.get_metadata_prop("res_total_top_synth")) - for (k, v) in synth_dct.items(): - update_dashboard_data(topology, wbits, abits, k, v) - update_dashboard_data(topology, wbits, abits, "board", cfg["board"]) model.save( get_checkpoint_name(topology, wbits, abits, QONNX_export, "build_" + kind) ) From fb09f04651340110fbcc01b3707842d0445cb9ad Mon Sep 17 00:00:00 2001 From: auphelia Date: Thu, 15 Jun 2023 09:54:50 +0100 Subject: [PATCH 165/665] [QONNX conversion] Add handling for ConvTranspose --- src/finn/transformation/qonnx/fold_quant_weights.py | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/finn/transformation/qonnx/fold_quant_weights.py b/src/finn/transformation/qonnx/fold_quant_weights.py index e8339ae244..06189ce418 100644 --- a/src/finn/transformation/qonnx/fold_quant_weights.py +++ b/src/finn/transformation/qonnx/fold_quant_weights.py @@ -102,7 +102,14 @@ def apply(self, model): model.set_initializer(node_out, q_node_output) else: # Check next operator type - mul_like_nodes = ["Mul", "Div", "Conv", "MatMul", "Gather"] + mul_like_nodes = [ + "Mul", + "Div", + "Conv", + "MatMul", + "Gather", + "ConvTranspose", + ] add_like_nodes = ["Add", "Sub"] all_supported_ops = mul_like_nodes.copy() all_supported_ops.extend(add_like_nodes) From 983cdc33cb0520cfd1de190450e8e8385dbadf42 Mon Sep 17 00:00:00 2001 From: auphelia Date: Thu, 15 Jun 2023 10:08:35 +0100 Subject: [PATCH 166/665] [Tests] Add Brevitas export test for deconv --- tests/brevitas/test_brevitas_deconv.py | 83 ++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 tests/brevitas/test_brevitas_deconv.py diff --git a/tests/brevitas/test_brevitas_deconv.py b/tests/brevitas/test_brevitas_deconv.py new file mode 100644 index 0000000000..75b740ec56 --- /dev/null +++ b/tests/brevitas/test_brevitas_deconv.py @@ -0,0 +1,83 @@ +# Copyright (c) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of Xilinx nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +import pytest + +import brevitas.nn as qnn +import numpy as np +import os +import torch +from brevitas.export import export_qonnx +from qonnx.core.modelwrapper import ModelWrapper +from qonnx.transformation.infer_shapes import InferShapes +from qonnx.util.cleanup import cleanup_model as qonnx_cleanup + +import finn.core.onnx_exec as oxe +from finn.transformation.qonnx.convert_qonnx_to_finn import ConvertQONNXtoFINN + +export_path = "test_brevitas_deconv.onnx" + + +@pytest.mark.brevitas_export +@pytest.mark.parametrize("ifm_ch", [3]) +@pytest.mark.parametrize("ofm_ch", [5]) +@pytest.mark.parametrize("mh", [4]) +@pytest.mark.parametrize("mw", [4]) +@pytest.mark.parametrize("padding", [1]) +@pytest.mark.parametrize("stride", [2]) +@pytest.mark.parametrize("kw", [4]) +@pytest.mark.parametrize("bias", [False]) +def test_brevitas_QTransposeConv(ifm_ch, ofm_ch, mh, mw, padding, stride, kw, bias): + kh = kw + oh = stride * (mh - 1) - (2 * padding) + kh + assert oh % mh == 0, "Needs to be evenly divisible." + ishape = (1, ifm_ch, mh, mw) # NCHW + inp = torch.randn(ishape) + b_deconv = qnn.QuantConvTranspose2d( + in_channels=ifm_ch, + out_channels=ofm_ch, + kernel_size=kw, + stride=stride, + padding=padding, + bias=bias, + ) + # outp = el(inp) # expects NCHW data format + export_qonnx( + b_deconv.cpu(), input_t=inp.cpu(), export_path=export_path, opset_version=11 + ) + model = ModelWrapper(export_path) + qonnx_cleanup(model) + model = model.transform(ConvertQONNXtoFINN()) + model = model.transform(InferShapes()) + inp_tensor = np.random.uniform(low=-1.0, high=1.0, size=ishape).astype(np.float32) + idict = {model.graph.input[0].name: inp_tensor} + odict = oxe.execute_onnx(model, idict, True) + produced = odict[model.graph.output[0].name] + inp_tensor = torch.from_numpy(inp_tensor).float() + expected = b_deconv.forward(inp_tensor).detach().numpy() + assert np.isclose(produced, expected, atol=1e-3).all() + os.remove(export_path) From 96efcda45cc7e58848db8cedd4af805924282294 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 21 Jun 2023 13:21:47 +0100 Subject: [PATCH 167/665] [SELU] Add selu to MT transformation + test case --- .../qonnx/qonnx_activation_handlers.py | 126 +++++++++++++----- .../brevitas/test_brevitas_selu_act_export.py | 68 ++++++++++ 2 files changed, 163 insertions(+), 31 deletions(-) create mode 100644 tests/brevitas/test_brevitas_selu_act_export.py diff --git a/src/finn/transformation/qonnx/qonnx_activation_handlers.py b/src/finn/transformation/qonnx/qonnx_activation_handlers.py index 9819086d82..5a5834a1c6 100644 --- a/src/finn/transformation/qonnx/qonnx_activation_handlers.py +++ b/src/finn/transformation/qonnx/qonnx_activation_handlers.py @@ -286,6 +286,7 @@ class QuantReluHandler(QuantActBaseHandler): def valid_predecessor_op_types(self): return [ "Relu", + "Selu", ] def _check_compatibility(self): @@ -293,16 +294,19 @@ def _check_compatibility(self): q_inst = getCustomOp(self._q_node) narrow = q_inst.get_nodeattr("narrow") signed = q_inst.get_nodeattr("signed") - if signed or narrow: - raise ValueError( - "FINN only supports unsigned and non-narrow Quant nodes " - "for Relu activations." - ) if not self._model.get_initializer(self._q_node.input[2]) == 0: raise ValueError( "Only Quant nodes with zero-point == 0 " "are currently supported for ReLu activations." ) + act_node = self._model.find_direct_predecessors(self._q_node) + act_node = act_node[0] + if act_node.op_type == "Relu": + if signed or narrow: + raise ValueError( + "FINN only supports unsigned and non-narrow Quant nodes " + "for Relu activations." + ) elif self._q_node.op_type == "BipolarQuant": return else: @@ -312,7 +316,31 @@ def _calculate_act_bias(self): # No bias allowed for Relu activations, see: https://github.com/Xilinx/ # brevitas/blob/a5bfd6dc5e030f0047ac1ee47932b60e8e873e17/src/brevitas/ # export/onnx/finn/handler/act.py#L48 - bias = np.array([0.0], dtype=np_default_dtype) + act_node = self._model.find_direct_predecessors(self._q_node) + act_node = act_node[0] + if act_node.op_type == "Relu": + bias = np.array([0.0], dtype=np_default_dtype) + elif act_node.op_type == "Selu": + # Gather parameters + q_inst = getCustomOp(self._q_node) + if self._q_node.op_type == "Quant": + bit_width = self._model.get_initializer(self._q_node.input[3]) + narrow = q_inst.get_nodeattr("narrow") + elif self._q_node.op_type == "BipolarQuant": + bit_width = 1.0 + else: + raise RuntimeError("Got an unexpected quantizer node type") + # Calculate bias, see: https://github.com/Xilinx/brevitas/blob/ + # a5bfd6dc5e030f0047ac1ee47932b60e8e873e17/src/brevitas/export/ + # onnx/finn/handler/act.py#L64 + if bit_width == 1.0: + bias = np.array([-0.5], dtype=np_default_dtype) + else: + if narrow: + min_non_scaled_val = -(2 ** (bit_width - 1) - 1) + else: + min_non_scaled_val = -(2 ** (bit_width - 1)) + bias = np.array([min_non_scaled_val], dtype=np_default_dtype) return bias def _calculate_thresholds(self): @@ -326,30 +354,66 @@ def _calculate_thresholds(self): quant_scale = self._model.get_initializer(self._q_node.input[1]).astype( np.float32 ) - # q_inst = getCustomOp(self._q_node) - # narrow = q_inst.get_nodeattr("narrow") + act_node = self._model.find_direct_predecessors(self._q_node) + act_node = act_node[0] + if act_node.op_type == "Relu": - # Calculate thersholds, see: https://github.com/Xilinx/brevitas/blob/ - # a5bfd6dc5e030f0047ac1ee47932b60e8e873e17/src/brevitas/export/ - # onnx/finn/handler/act.py#L21 - num_distinct_values = 2**bit_width - num_thresholds = int(num_distinct_values - 1) - flat_scale = quant_scale.flatten().astype(np.float32) - num_scale_channels = flat_scale.shape[0] - step = np.abs(flat_scale).astype(np.float32) - min_threshold = step / 2 - thresholds = np.empty( - (num_scale_channels, num_thresholds), dtype=np_default_dtype - ) - for c in range(num_scale_channels): - for t in range(num_thresholds): - thresholds[c][t] = min_threshold[c] + step[c] * t + # Calculate thersholds, see: https://github.com/Xilinx/brevitas/blob/ + # a5bfd6dc5e030f0047ac1ee47932b60e8e873e17/src/brevitas/export/ + # onnx/finn/handler/act.py#L21 + num_distinct_values = 2**bit_width + num_thresholds = int(num_distinct_values - 1) + flat_scale = quant_scale.flatten().astype(np.float32) + num_scale_channels = flat_scale.shape[0] + step = np.abs(flat_scale).astype(np.float32) + min_threshold = step / 2 + thresholds = np.empty( + (num_scale_channels, num_thresholds), dtype=np_default_dtype + ) + for c in range(num_scale_channels): + for t in range(num_thresholds): + thresholds[c][t] = min_threshold[c] + step[c] * t + + # ToDo: The index 1 needs to be changed to -1 for the channels last format + num_output_channels = self._model.get_tensor_shape(self._q_node.output[0])[ + 1 + ] + final_shape = (num_output_channels, num_thresholds) + if thresholds.shape != final_shape: + thresholds = np.broadcast_to(thresholds, final_shape) + elif act_node.op_type == "Selu": + q_inst = getCustomOp(self._q_node) + narrow = q_inst.get_nodeattr("narrow") + if narrow: + num_distinct_values = 2**bit_width - 1 + else: + num_distinct_values = 2**bit_width - # ToDo: The index 1 needs to be changed to -1 for the channels last format - num_output_channels = self._model.get_tensor_shape(self._q_node.output[0])[1] - final_shape = (num_output_channels, num_thresholds) - if thresholds.shape != final_shape: - thresholds = np.broadcast_to(thresholds, final_shape) + num_thresholds = int(num_distinct_values - 1) + flat_scale = quant_scale.flatten().astype(np.float32) + num_scale_channels = flat_scale.shape[0] + scale = np.abs(flat_scale).astype(np.float32) + half_scale = scale / 2 + # alpha and lambda + # from https://pytorch.org/docs/stable/generated/torch.nn.SELU.html + alpha = 1.6732632423543772848170429916717 + selu_scale = 1.0507009873554804934193349852946 + thresholds = np.empty( + (num_scale_channels, num_thresholds), dtype=np_default_dtype + ) + for c in range(num_scale_channels): + for t in range(num_thresholds): + step = -1.0 + half_scale + scale[c] * t + if step <= 0: + thresholds[c][t] = np.log(step / (alpha * selu_scale) + 1) + else: + thresholds[c][t] = step / selu_scale + num_output_channels = self._model.get_tensor_shape(self._q_node.output[0])[ + 1 + ] + final_shape = (num_output_channels, num_thresholds) + if thresholds.shape != final_shape: + thresholds = np.broadcast_to(thresholds, final_shape) return thresholds @@ -371,10 +435,10 @@ def _remove_activation_node(self, multi_threshold_node): "the Quant node must exist." ) act_node = act_node[0] - if not act_node.op_type == "Relu": + if act_node.op_type not in self.valid_predecessor_op_types(): raise RuntimeError( - "The predecesor of the Quant node must be Relu for handling " - "of Relu activations." + "The predecesor of the Quant node must be Relu or Selu for handling " + "of activations." ) # Reroute upstream tensor diff --git a/tests/brevitas/test_brevitas_selu_act_export.py b/tests/brevitas/test_brevitas_selu_act_export.py new file mode 100644 index 0000000000..2f1422e4cd --- /dev/null +++ b/tests/brevitas/test_brevitas_selu_act_export.py @@ -0,0 +1,68 @@ +# Copyright (c) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of Xilinx nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import pytest + +import numpy as np +import onnx # noqa +import os +import torch +from brevitas.export import export_qonnx +from brevitas.nn import QuantIdentity +from qonnx.core.modelwrapper import ModelWrapper +from qonnx.util.cleanup import cleanup as qonnx_cleanup + +import finn.core.onnx_exec as oxe +from finn.transformation.qonnx.convert_qonnx_to_finn import ConvertQONNXtoFINN + + +@pytest.mark.brevitas_export +@pytest.mark.parametrize("abits", [2, 4, 8]) +@pytest.mark.parametrize("ishape", [(1, 15), (1, 32, 1, 1)]) +@pytest.mark.parametrize("narrow", [True, False]) +def test_brevitas_act_export_selu(abits, ishape, narrow): + export_path = "test_brevitas_selu_act_export_%s.onnx" % str(abits) + b_act = torch.nn.Sequential( + torch.nn.SELU(), QuantIdentity(bit_width=abits, narrow=narrow) + ) + + export_qonnx(b_act, torch.randn(ishape), export_path, opset_version=11) + qonnx_cleanup(export_path, out_file=export_path) + model = ModelWrapper(export_path) + model = model.transform(ConvertQONNXtoFINN()) + + inp_tensor = np.random.uniform(low=-1.0, high=6.0, size=ishape).astype(np.float32) + idict = {model.graph.input[0].name: inp_tensor} + odict = oxe.execute_onnx(model, idict, True) + produced = odict[model.graph.output[0].name] + inp_tensor = torch.from_numpy(inp_tensor).float() + b_act.eval() + expected = b_act.forward(inp_tensor).detach().numpy() + + assert np.isclose(produced, expected, atol=1e-3).all() + os.remove(export_path) From b30a70f68687ef21107028eff799ae12c31d39c8 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 21 Jun 2023 16:12:57 +0100 Subject: [PATCH 168/665] [SELU] Cleanup qonnx handler and SELU export test --- .../qonnx/qonnx_activation_handlers.py | 19 ++++++------------- .../brevitas/test_brevitas_selu_act_export.py | 8 +++++++- 2 files changed, 13 insertions(+), 14 deletions(-) diff --git a/src/finn/transformation/qonnx/qonnx_activation_handlers.py b/src/finn/transformation/qonnx/qonnx_activation_handlers.py index 5a5834a1c6..bbe5e1a0e3 100644 --- a/src/finn/transformation/qonnx/qonnx_activation_handlers.py +++ b/src/finn/transformation/qonnx/qonnx_activation_handlers.py @@ -374,13 +374,6 @@ def _calculate_thresholds(self): for t in range(num_thresholds): thresholds[c][t] = min_threshold[c] + step[c] * t - # ToDo: The index 1 needs to be changed to -1 for the channels last format - num_output_channels = self._model.get_tensor_shape(self._q_node.output[0])[ - 1 - ] - final_shape = (num_output_channels, num_thresholds) - if thresholds.shape != final_shape: - thresholds = np.broadcast_to(thresholds, final_shape) elif act_node.op_type == "Selu": q_inst = getCustomOp(self._q_node) narrow = q_inst.get_nodeattr("narrow") @@ -408,12 +401,12 @@ def _calculate_thresholds(self): thresholds[c][t] = np.log(step / (alpha * selu_scale) + 1) else: thresholds[c][t] = step / selu_scale - num_output_channels = self._model.get_tensor_shape(self._q_node.output[0])[ - 1 - ] - final_shape = (num_output_channels, num_thresholds) - if thresholds.shape != final_shape: - thresholds = np.broadcast_to(thresholds, final_shape) + + # ToDo: The index 1 needs to be changed to -1 for the channels last format + num_output_channels = self._model.get_tensor_shape(self._q_node.output[0])[1] + final_shape = (num_output_channels, num_thresholds) + if thresholds.shape != final_shape: + thresholds = np.broadcast_to(thresholds, final_shape) return thresholds diff --git a/tests/brevitas/test_brevitas_selu_act_export.py b/tests/brevitas/test_brevitas_selu_act_export.py index 2f1422e4cd..3f4807c5d7 100644 --- a/tests/brevitas/test_brevitas_selu_act_export.py +++ b/tests/brevitas/test_brevitas_selu_act_export.py @@ -35,6 +35,7 @@ from brevitas.export import export_qonnx from brevitas.nn import QuantIdentity from qonnx.core.modelwrapper import ModelWrapper +from qonnx.util.basic import get_preferred_onnx_opset from qonnx.util.cleanup import cleanup as qonnx_cleanup import finn.core.onnx_exec as oxe @@ -51,7 +52,12 @@ def test_brevitas_act_export_selu(abits, ishape, narrow): torch.nn.SELU(), QuantIdentity(bit_width=abits, narrow=narrow) ) - export_qonnx(b_act, torch.randn(ishape), export_path, opset_version=11) + export_qonnx( + b_act, + torch.randn(ishape), + export_path, + opset_version=get_preferred_onnx_opset(), + ) qonnx_cleanup(export_path, out_file=export_path) model = ModelWrapper(export_path) model = model.transform(ConvertQONNXtoFINN()) From 175e7c60fcfad810162bc4d478831be55750bec2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thomas=20B=2E=20Preu=C3=9Fer?= Date: Fri, 23 Jun 2023 12:39:46 +0100 Subject: [PATCH 169/665] Trying a package for replacing the global ifdef'ed declaration. --- finn-rtllib/swg/swg_common.sv | 18 ++------ finn-rtllib/swg/swg_pkg.sv | 41 ++++++++++++++++++ finn-rtllib/swg/swg_template_axilite.v | 38 +++++++++++++--- finn-rtllib/swg/swg_template_default.sv | 2 +- .../swg/swg_template_default_dynamic.sv | 43 ++++++++++++++----- finn-rtllib/swg/swg_template_parallel.sv | 2 +- 6 files changed, 111 insertions(+), 33 deletions(-) create mode 100644 finn-rtllib/swg/swg_pkg.sv diff --git a/finn-rtllib/swg/swg_common.sv b/finn-rtllib/swg/swg_common.sv index d953078abe..f2cdc333ca 100644 --- a/finn-rtllib/swg/swg_common.sv +++ b/finn-rtllib/swg/swg_common.sv @@ -1,5 +1,5 @@ /****************************************************************************** - * Copyright (C) 2022, Advanced Micro Devices, Inc. + * Copyright (C) 2022-2023, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -29,20 +29,10 @@ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ -`ifndef FINN_SWG_ENUM_DEFINED -`define FINN_SWG_ENUM_DEFINED -typedef enum logic [2:0] { - STATE_START, - STATE_LOOP_SIMD, - STATE_LOOP_KW, - STATE_LOOP_KH, - STATE_LOOP_W, - STATE_LOOP_H -} state_e; -`endif // loop controller used for both, "default" and "parallel", implementation styles -module swg_controller #( +module swg_controller +import swg::*; #( int unsigned LOOP_H_ITERATIONS, int unsigned LOOP_W_ITERATIONS, int unsigned LOOP_KH_ITERATIONS, @@ -62,7 +52,7 @@ module swg_controller #( int TAIL_INCR_H, int TAIL_INCR_LAST, - parameter INNERMOST_STATE + state_e INNERMOST_STATE )( input logic clk, input logic rst_n, diff --git a/finn-rtllib/swg/swg_pkg.sv b/finn-rtllib/swg/swg_pkg.sv new file mode 100644 index 0000000000..1200310aca --- /dev/null +++ b/finn-rtllib/swg/swg_pkg.sv @@ -0,0 +1,41 @@ +/****************************************************************************** + * Copyright (C) 2023, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *****************************************************************************/ + +package swg; + typedef enum logic [2:0] { + STATE_START, + STATE_LOOP_SIMD, + STATE_LOOP_KW, + STATE_LOOP_KH, + STATE_LOOP_W, + STATE_LOOP_H + } state_e; +endpackage : swg diff --git a/finn-rtllib/swg/swg_template_axilite.v b/finn-rtllib/swg/swg_template_axilite.v index 9479c7f80d..1f39e4440e 100644 --- a/finn-rtllib/swg/swg_template_axilite.v +++ b/finn-rtllib/swg/swg_template_axilite.v @@ -1,8 +1,35 @@ +/****************************************************************************** + * Copyright (C) 2022-2023, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *****************************************************************************/ -`timescale 1 ns / 1 ps - -module $TOP_MODULE_NAME$_axilite # -( +module $TOP_MODULE_NAME$_axilite #( // Users to add parameters here // User parameters ends @@ -12,8 +39,7 @@ module $TOP_MODULE_NAME$_axilite # parameter integer C_S_AXI_DATA_WIDTH = 32, // Width of S_AXI address bus parameter integer C_S_AXI_ADDR_WIDTH = 6 -) -( +)( // Users to add ports here output wire [C_S_AXI_DATA_WIDTH-1:0] cfg_reg0, output wire [C_S_AXI_DATA_WIDTH-1:0] cfg_reg1, diff --git a/finn-rtllib/swg/swg_template_default.sv b/finn-rtllib/swg/swg_template_default.sv index 4970762172..78a8d0a3b9 100644 --- a/finn-rtllib/swg/swg_template_default.sv +++ b/finn-rtllib/swg/swg_template_default.sv @@ -98,7 +98,7 @@ module $TOP_MODULE_NAME$_impl #( .TAIL_INCR_LAST($TAIL_INCR_LAST$), .INCR_BITWIDTH($INCR_BITWIDTH$), .IS_DEPTHWISE($IS_DEPTHWISE$), - .INNERMOST_STATE($INNERMOST_STATE$) + .INNERMOST_STATE(swg::$INNERMOST_STATE$) ) controller_inst ( .clk(ap_clk), diff --git a/finn-rtllib/swg/swg_template_default_dynamic.sv b/finn-rtllib/swg/swg_template_default_dynamic.sv index c1647ef699..5a6fdda170 100644 --- a/finn-rtllib/swg/swg_template_default_dynamic.sv +++ b/finn-rtllib/swg/swg_template_default_dynamic.sv @@ -1,14 +1,33 @@ -`ifndef FINN_SWG_ENUM_DEFINED -`define FINN_SWG_ENUM_DEFINED -typedef enum logic [2:0] { - STATE_START, - STATE_LOOP_SIMD, - STATE_LOOP_KW, - STATE_LOOP_KH, - STATE_LOOP_W, - STATE_LOOP_H -} state_e; -`endif +/****************************************************************************** + * Copyright (C) 2022-2023, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *****************************************************************************/ module $TOP_MODULE_NAME$_controller #( int unsigned CNTR_BITWIDTH, @@ -39,6 +58,8 @@ module $TOP_MODULE_NAME$_controller #( input logic [INCR_BITWIDTH-1:0] cfg_incr_tail_last ); + import swg::*; + // (dynamic) configuration registers logic [CNTR_BITWIDTH-1:0] Cfg_cntr_simd = $LOOP_SIMD_ITERATIONS$; logic [CNTR_BITWIDTH-1:0] Cfg_cntr_kw = $LOOP_KW_ITERATIONS$; diff --git a/finn-rtllib/swg/swg_template_parallel.sv b/finn-rtllib/swg/swg_template_parallel.sv index b55a51e400..83a525ff36 100644 --- a/finn-rtllib/swg/swg_template_parallel.sv +++ b/finn-rtllib/swg/swg_template_parallel.sv @@ -123,7 +123,7 @@ module $TOP_MODULE_NAME$_impl #( .TAIL_INCR_LAST($TAIL_INCR_LAST$), .INCR_BITWIDTH($INCR_BITWIDTH$), .IS_DEPTHWISE($IS_DEPTHWISE$), - .INNERMOST_STATE($INNERMOST_STATE$) + .INNERMOST_STATE(swg::$INNERMOST_STATE$) ) controller_inst ( .clk(ap_clk), From a0b2141f762cd6929ff95dac0995bfb17e1203cd Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 23 Jun 2023 17:53:15 +0100 Subject: [PATCH 170/665] [Tranform] Enable rtlsim to utilize swg package --- .../custom_op/fpgadataflow/convolutioninputgenerator_rtl.py | 5 +++++ src/finn/util/pyverilator.py | 6 +++++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py index a1a32ba6af..c54c4ac1c9 100755 --- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py +++ b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py @@ -1064,6 +1064,9 @@ def generate_hdl(self): shutil.copy2( os.environ["FINN_ROOT"] + "/finn-rtllib/swg/swg_common.sv", code_gen_dir ) + shutil.copy2( + os.environ["FINN_ROOT"] + "/finn-rtllib/swg/swg_pkg.sv", code_gen_dir + ) # set ipgen_path and ip_path so that HLS-Synth transformation # and stich_ip transformation do not complain @@ -1082,6 +1085,7 @@ def prepare_rtlsim(self): code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") verilog_paths = [code_gen_dir] verilog_files = [ + "swg_pkg.sv", self.get_nodeattr("gen_top_module") + "_wrapper.v", self.get_nodeattr("gen_top_module") + "_impl.sv", "swg_common.sv", @@ -1106,6 +1110,7 @@ def code_generation_ipi(self): code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") sourcefiles = [ + "swg_pkg.sv", self.get_nodeattr("gen_top_module") + "_wrapper.v", self.get_nodeattr("gen_top_module") + "_impl.sv", "swg_common.sv", diff --git a/src/finn/util/pyverilator.py b/src/finn/util/pyverilator.py index 8d18858569..7452394524 100644 --- a/src/finn/util/pyverilator.py +++ b/src/finn/util/pyverilator.py @@ -118,6 +118,8 @@ def file_to_basename(x): if not remove_entry: filtered_verilog_files.append(vfile) remove_entry = True + elif "swg_pkg" in vfile: + continue else: filtered_verilog_files.append(vfile) @@ -315,8 +317,10 @@ def file_to_basename(x): xpm_cdc = f"{vivado_path}/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" xpm_fifo = f"{vivado_path}/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" + swg_pkg = os.environ["FINN_ROOT"] + "/finn-rtllib/swg/swg_pkg.sv" + sim = PyVerilator.build( - [top_module_file_name, xpm_fifo, xpm_memory, xpm_cdc], + [swg_pkg, top_module_file_name, xpm_fifo, xpm_memory, xpm_cdc], verilog_path=[vivado_stitch_proj_dir, verilog_header_dir], build_dir=build_dir, trace_depth=get_rtlsim_trace_depth(), From b238b7b989d19b44dc275aff59c9b105f2f402aa Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 26 Jun 2023 18:01:44 +0100 Subject: [PATCH 171/665] [notebooks] Updating first part of folding notebook --- ...Folding-Tutorial.ipynb => 3_folding.ipynb} | 357 +++++++++--------- notebooks/advanced/finn-dataflow.png | Bin 0 -> 164258 bytes notebooks/advanced/finn-folding-mvau.png | Bin 0 -> 29710 bytes notebooks/advanced/finn-folding.png | Bin 0 -> 84958 bytes notebooks/advanced/finn-hw-arch.png | Bin 110452 -> 0 bytes 5 files changed, 176 insertions(+), 181 deletions(-) rename notebooks/advanced/{Folding-Tutorial.ipynb => 3_folding.ipynb} (63%) create mode 100755 notebooks/advanced/finn-dataflow.png create mode 100755 notebooks/advanced/finn-folding-mvau.png create mode 100755 notebooks/advanced/finn-folding.png delete mode 100644 notebooks/advanced/finn-hw-arch.png diff --git a/notebooks/advanced/Folding-Tutorial.ipynb b/notebooks/advanced/3_folding.ipynb similarity index 63% rename from notebooks/advanced/Folding-Tutorial.ipynb rename to notebooks/advanced/3_folding.ipynb index 409595d0d8..b1baf69cab 100644 --- a/notebooks/advanced/Folding-Tutorial.ipynb +++ b/notebooks/advanced/3_folding.ipynb @@ -26,14 +26,20 @@ "cell_type": "markdown", "metadata": {}, "source": [ - "Note: The build_flow in the cybsec_mlp notebook comprises a transformation step `step_target_fps_parallelization` that automatically sets custom parallelization parameters needed to achieve a given `target_fps` by invoking the `SetFolding` transformation.\n", - "\n", - "More details of the above step can be found here: https://github.com/Xilinx/finn/blob/main/src/finn/builder/build_dataflow_steps.py#L394\n", + "Note: The build_flow in the cybsec_mlp notebook comprises a transformation step `step_target_fps_parallelization` that automatically sets custom parallelization parameters needed to achieve a given `target_fps` by invoking the [`SetFolding` transformation](https://github.com/Xilinx/finn/blob/main/src/finn/transformation/fpgadataflow/set_folding.py#L46).\n", "\n", + "More details of the above step can be found [here](https://github.com/Xilinx/finn/blob/main/src/finn/builder/build_dataflow_steps.py#L394)." + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ "This notebook shows the manual version of this step and explains how these attributes can improve performance and what are their effects on resource utilization for developers who need to maximize the performance of their network. \n", "\n", - "* input : the 'step_convert_to_hls.onnx' file (we pick has gone through a series of transformation passes) to be analyzed in terms of clock cycles and resource utilization per layer\n", - "* analyze the estimated execution clock cycles and the resource utilization of each layer in the network" + "For that we will use the `step_convert_to_hls.onnx` file as starting point. This intermediate model from the cybersecurity example is the model representation after the high-level ONNX layers are converted to HLS layers. Each node in the graph now corresponds to an HLS C++ function call and the parallelization parameters can be set using the node attributes.\n", + "\n", + "We will take this model to show how to set the folding factors manually and analyze the estimated execution clock cycles and the resource utilization of each layer in the network." ] }, { @@ -42,11 +48,15 @@ "source": [ "### FINN-style Dataflow Architectures \n", "\n", - "We start with a quick recap of FINN-style dataflow architectures. The key idea in such architectures is to parallelize across layers as well as within layers by dedicating a proportionate amount of compute resources to each layer, as illustrated in the figure below taken from the [FINN-R paper](https://arxiv.org/pdf/1809.04570.pdf):\n", + "We start with a quick recap of FINN-style dataflow architectures. The key idea in such architectures is to parallelize across layers as well as within layers by dedicating a proportionate amount of compute resources to each layer, as illustrated in the figure below.\n", + "\n", + "![](finn-dataflow.png)\n", "\n", - "![](finn-hw-arch.png)\n", + "In practice, the layers are instantiated by function calls to optimized Vitis HLS building blocks from the [finn-hlslib](https://github.com/Xilinx/finn-hlslib) library.\n", "\n", - "In practice, the compute arrays are instantiated by function calls to optimized Vitis HLS building blocks from the [finn-hlslib](https://github.com/Xilinx/finn-hlslib) library. As these function calls can only handle certain patterns/cases, we need to transform the network into an appropriate form so that we can replace network layers with these function calls, which is the goal of the network preparation process." + "Since each layer will be instantiated, we can flexibly set the parallelization of each layer and thus control resources and throughput of our network, as visualized in the imaged below:\n", + "\n", + "![](finn-folding.png)" ] }, { @@ -55,15 +65,14 @@ "source": [ "# Part-1 : Loading the ONNX model.\n", "\n", - "The 'onnx' file needs to go through multiple transformations before it can be fed into our estimation functions.\n", + "As discussed above, the network needs to go through a few preparation steps before it can be fed into our estimation functions.\n", "\n", - "The 'onnx' file loaded here is taken from the cybersecurity end2end example notebook. The build_step in the notebook comprises several series of transformations that take place before the onnx file is used for bitstream generation.\n", - "We pick the onnx file `step_convert_to_hls` to which the necessary transformations have been applied for this notebook (Network layers mapped to necessary FINN-HLS blocks. In this case, the `MatrixVectorActivation` Units). \n", + "The `.onnx` file loaded here is taken from the cybersecurity end2end example notebook. \n", + "We pick the onnx file `step_convert_to_hls.onnx` to which the necessary transformations have been applied for this notebook (Network layers mapped to necessary FINN-HLS blocks. In this case, the `MatrixVectorActivation` Units). \n", "\n", - "More information on these transformations can be found in the tfc_end2end_example notebook.\n", + "To interact with the `.onnx` file we use the `ModelWrapper()`. This wrapper simplifies the access to different model attributes and allows us to apply custom transformations on the model.\n", "\n", - "To interact with the 'onnx' file we use the `ModelWrapper()` helper function. This function gives access to different model attributes and allows us to apply custom tranformations to it.\n", - "In the below cell, we load our onnx file and view the cybersecurity MLP network in netron." + "In the below cell, we load our onnx file and view the cybersecurity MLP network in Netron." ] }, { @@ -75,7 +84,7 @@ "name": "stdout", "output_type": "stream", "text": [ - "Serving './step_convert_to_hls_folding.onnx' at http://0.0.0.0:5901\n" + "Serving 'step_convert_to_hls.onnx' at http://0.0.0.0:5920\n" ] }, { @@ -85,7 +94,7 @@ " " + "" ] }, "execution_count": 2, @@ -103,152 +112,63 @@ ], "source": [ "from qonnx.core.modelwrapper import ModelWrapper\n", - "model = ModelWrapper(\"./step_convert_to_hls.onnx\")\n", + "model = ModelWrapper(\"../end2end_example/cybersecurity/output_estimates_only/intermediate_models/step_convert_to_hls.onnx\")\n", + "model.save(\"step_convert_to_hls.onnx\")\n", "\n", - "showInNetron(\"./step_convert_to_hls.onnx\",localhost_url='xirxlabs53')" + "showInNetron(\"step_convert_to_hls.onnx\")" ] }, { "cell_type": "markdown", "metadata": {}, "source": [ - "# Part 2 : Parallelisation Attributes : PE & SIMD" + "# Part 2 : Parallelization Parameters: PE & SIMD" ] }, { "cell_type": "markdown", "metadata": {}, "source": [ - "**PE & SIMD represent the amount of time-multiplexity to which we expose each of our network layers. \n", - "These parallelization attributes are subject to certain constraints and should be selected accordingly.**\n", + "The computational parallelism can be varied by setting the folding factors or also called parallelization parameters **PE** and **SIMD** of each layer. These parallelization attributes are subject to certain constraints and should be selected accordingly.\n", "\n", - "We see how they work through an example of a multiplication computation (Matrix-Vector) in the `MatrixVectorActivation` layer looks like.\n", + "To see more details about how this is implemented in the `MatrixVectorActivation` layer (MVAU), please have a look at [this documentation](https://github.com/Xilinx/finn/blob/github-pages/docs/finn-sheduling-and-folding.pptx). A schematic of the folding in an MVAU for a fully-connected layer is shown below:\n", "\n", - "From the below block diagram, we observe that `SIMD` represents the parallelism within a single dot-product computation (the number of multiplications is a single clock cycle), while `PE` refers to how many such (Matrix-Vector?) dot-products execute in parallel.\n", - "\n", - "If `PE` & `SIMD` are set to 2 & 4 for a given layer that means, that within a dot-product 4 multiplications will happen in parallel and 2 such dot-products will execute in parallel.\n", - "\n", - "The base case of `PE` & `SIMD` both set as 1 suggest that there will be no parallelization therefore the resource utilization would be low (resources can be resued for differnt multiplication operations) when compared to settings where network layers have higher `PE` & `SIMD` values." - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "
    \n", - "Question in the third line of the above cell.\n", - "
    " + "![](finn-folding-mvau.png)" ] }, { - "attachments": { - "MVA-1.png": { - "image/png": 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fGps+Ka9Px1LDdO3NW+k3xR2BDfXrSaQgxO/ixTN432/oqMrXnM+htbl9Ul6fjkV5iboKu5V+cy4B9et7wwPpVzWfW7wFdLO6uihOPnSllcZ6c977jRXfX+Gt9Pua8XMX1K/vZw+kX879ppqDo99Ucr3Iu5V+/xn/+MokBtSvx0b9yr2Hc781Nn0acfbpWGqYrr15K/3+msMD0hJOmPr10Khfue9QvzU2fVJen46lhunam7fS71frT9HLJKhfz+aB9Mu5X7m3N5doJx9yJvuajwAvpX5LZrfS76jl1+DKA4ysUL8eygPpl3O/kW6u2kX9qjD1NehW+pUV2k5KzpVLIrXygZMRKGe7eOPZGZJL79AqNNauNpej3xi9m++jflWXIGWkieVg0e6g8Qz8jtyUDDxHOVPrr5QuVhf1RDee/evFg+WL9xonHwoO9k/qt0TRtJKiOiwHi3bHimfgYkzJwHOUd+n6C6SL1UU9lX7T7zRqemOklFG/JTXqt0TRtJKiOiwHi3bHimfgYkzJwHOUY1V/gXSxuqgn0u+v+Wjq31cto35L3NRviaJpJUV1WA4W7Y4Vz8DFmJKB5yhl6S+QLlYX9UT6HYl3Go1et8t/L4fOP/pyv0Lz9vU1Ouyw/z7++nor9n3ZZfRZFsRWKnmx4mIf9VuyoX5LFE0rKarDcrBod6x4Bi7GlAw8RylLf4F0sbqoJ9Lvnzl7OLfH+ftRPKN7Xvz4187/SvnUmHH5i2Jz47+gal+KZbiVDfytup+J+vXo3R/Ub4miaSVFdVgOFu2OFc/AxZiSgecoZ2r9BdLF6qKeSL8DY0qhVjr6u/0h6/lqtTNm6P1b6Nf9aM37IWo/CfpduB/FHtuioRsNx5Y3+wPTsf21fdRvCYT6LVE0raSoDsvBot2x4hm4GFMy8BzlWNVfIF2sLuqZ9Ds0X5EOvjFTb+XZpHgGy27xY6OmZmJWh+hvsziMfos9n8uF2QjjX6tt6vfATfdC/ao4pagOy8Gi3UHjGbgYUzLwHKUs/ZXSxeqinkm/69jvG3wZc5j1fTUL59Qw+WB/sdzTHgzmZnrQ7/ywx/6ebvx3crdmR/0eIClfqF8VqBTVYTlYtDtoPAMXY0oGnqOUpb9Sulhd1DPpN3KwBScAACAASURBVPr1mVk5JfH5MXVTCjtv1rXZbg6zD5+Lj5+T0a/veBM7ZP58CctnMRj+Wmz+Ub++k6r/oH5VqFJUh+Vg0e6g8QxcjCkZeI5yptZfKV2sLuqZ9BudcP0z/qO241sgjH6328Psw7fZBv2G0a/9nVwzc8PicvEl+42Z/Yr3VxybGAyih1INeJ516ld1rVNUh+Vg0e6g8QxcjCkZeI5yrOqvlC5WF/VM+o2b8cfO1v68H6dyi7lfO/q1P0XuJ4WnZhT0u/L83R8T90thq3FYJr5kZQfOvxz9lpBUK9SvClOK6rAcLNodNJ6BizElA89RytJfKV2sLuqZ9Ls3sd8W31v/2mX3c/hcrhz9Dj787MPnYmf7mRvdzv2f/hIMNpHJ33f3BNl36rcgpP2T+lWRSlEdloNFu4PGM3AxpmTgOUpZ+iuli9VFPZN+7e0M0Q/Mvn42TsCLuf8MLtz5sB0Usw9LO84N+l15/u6PTW3Kwu76Gy/sNzU4+i0Z6VaoXxWnFNVhOVi0O2g8AxdjSgaeo5yp9VdKF6uLeir92o/F/HTCeX//+17Z23l3rvQ4+n3z9z5M7ZA56Lec+x0Mz01e/HI59XtOt3HPnxk3lndVCD0asnYQcq5cUqvCbfKBkxEoZ7uin5ifRZ3uQHOUY1XfiC5WF/VU+rUfjc2/RsflOOFrue63xs3nHu98cKvv9ktZ9kE9Qb8rz98FG/d85tVmePhvs7Kfpq33n/tPp/iTekPKySs/eitxQMIqs/JXctqVc+WSyBFTvxEoZ7tQlboK0BylLP2x6WJ1UU+l38Fs4WYZyuWfxbmd21sYiqWY2z2Ofv3sg5t7KPVbjn7tjb92ouHkzgf7NeVyiX29I7TiX6nfEkfOj/6UlSSsQKKs1S/nyiW1Ktwm9RuBcrYLVamrAM1RytIfmy5WF/Vc+h3MCklOisV9q7iwree69Q8Eruj3z977sHbfyjgb/c7909Ne3v7sf/6Pl3AbhP2C8nhM/Xqgqj/8B5aqyMsGQaKsNS3nyiW1Ktwm9RuBcrYLVamrAM1RztT6Y9PF6qKeTL97O2Bd/Vav8NZMwvMbPvx8bkW/g7Upfkoj6DeMfr/93EO1mnKdc78lCt3K942egv9SfqtRd5zVKFmyckk1/7COfHSFxIamsBws2rWBZ+BiTMnAc5RjVQ9WF6uLejL92m8Sn8jXPnBrbMavbrJ2NDeLk2+92X1LM/a/wRf0u9rv959/7ysjK4P69X1U/8fN5mHKrzvqjzVEypKVS0Ju5RXRFxIbmsBysGjXBp6BizElA89RytKD1cXqop5Lv7+L88c+uPngxWY3tBO3bi64cueDvZfMFjk1B/2Wk7tT8dO1d37rzXdS9R8p72F15U2Bk9hd4E0JxzJZsnLJMbtcQ04diQ0NYDlYtGsDz8DFmJKB5yhl6cHqYnVRz6XfykRv6KJ2/OvuObPLvJixrU4+2NkHP99wot/FZh4eRXmspFx73NGve9S8XUbFY5HtPxeKbf9n2FdiOKy8fQl3+h0D18Xfescd11r7iD4AT9W6LFm5JFIxoi8kNjSF5WDRrg08AxdjSgaeo5yp9WB1sbqop9LvuxnHR62j3/dZvCT05Au/3uxf3BnnUfwlZf+emqz8bLn790JY3DM6I8to0T7CHJsw9x6poMtdUz+vlNSCLFm5JNIQoi8kNjSF5WDRrg08AxdjSgaeoxyrerC6WF1Ub/S7Pt6Oi629FTcshC7X9Lo6/6paU3iHZfep34l72vzQTtaMnTGHpth2+7bRQe7ePsO+za2zG33rwslD+Euj/brLkpVLIrUi+kJiQ1NYDhbt2sAzcDGmZOA5Sll6sLpYXVRv9Gtv2EpepqG/Nb/aX60o7/Ftjuy89B71Owmjxe/i6fND/y2VJlT2iyyt+g3PlWuqp5uy9/SfXpUlK5dETgLRFxIbmsJysGjXBp6BizElA89RytKD1cXqovqj38O9uPjLQr4NIfTD4lU3LXua09HWPeq3uAnEAbFatVM1rfq1Py0dfcjRCdOd+T7Zvt7GfpE8+StLVi6JnBiiLyQ2NIXlYNGuDTwDF2NKBp4zB3qhLpZzv6EXhtftIty3G/bc7PU+9eu+k+0W+4h6+zFlTb/78Oj5l5diGn0/XNjHIrdMPszMIjpvUTTU7Z+r8uek0HZkycolkTYQfSGxoSksB4t2baBfbkjLuUYrU+DzX13snY1+lRMIoWdVXotvRlR2SKvFM3Gk0qvuv0f9lpMP9qlu7ivXG7OsmnN5nDsqfqXJvW1aR7/T9AnY7Av2ZRatX0+MNyJLVi6J1IQID4kNTWE5WLRr4xpivE4rOqUWXHWxujFybyYfrqDf3flNv6GjXvv1HvV7nHwofgavNvpdTsaTcfH/xuH8ds8qahv92l8xle5Zu8IlWZlNWuuyZOWSyPkgwutedXgLeIZ7TsprhETTLjwDb0Wn1OIodbG6qGfS78TNWPZjuU/9+smHzy/7pT93z8DQLMKPfXjfnpL9m0ys2lr0a78GEyY0TrOvs/W5McOk8a8sWbkkckqX0G9lzuc4+3NYs7++crZP3qGLfqvclzS3PwmDLvaZ29UqWtNn9jEt2xm62B+rgVLsDzwe4t9bFxvbGvP+rot6X2o/uIp0n8vtUk8gRJrU5uZ8yT/SbNaue9Rv5d4UO651+i2X8JvQFSZr/2FG4+TDp/0Ib1VJuf7qn33O/vx1VnGA7hhkyb6VTLhCAu0Epk+j35HqZ4B077/cqHvU7+FrF4vx9NXP+donzo/eDssZj2XxdcHY6Pf1xy+rufV5+7Phzmq+6I7Pn9N3SOTvkVh7fdKveKvQwn2bfiEW1wq00WN3m/dhWVTu/A772l4XplpDW/Rw+PExMeMPdJkYmwgsC7M5RK9bl4nZtMas17qo9epp9HurJxvG3r/3qd/lYG//C0tt7vd1Yx89X/y/G3yZ8Z97+Lz9jO7zmFFkVh+MbBa3nHxwx/O3nW6GpYqG4eSaX5v0O25OrZZeYvKhWl99HZubxaJdW3gGPiubkoHnKGdqPWBdrC7qieZ+//XiL5riLXKP+j3e+VCcQ02/J3c+2GmFcqkLdlmMfv2f9vmfs6K2u/qT+vWXi/qVey31W2PzWvmh4lrR1TfvUb/HOx8KXDX9ftp5iMOz5/8Gy8OHcnZ6YVjX7wnsH3d/xN0t1K+/ZNSv3HOp3xob6rcGBNyc1O5SsPqtzyuc1Rib+z0Jekn/6tlJPdfdoH497yT9LnjjWaWz9uOf5Nq7FyoHXq5qc/s04uzTsZQgW1bOR79b+/T5wyLkturXzh9uhdwe76Z+/cVJ0i/v+612bOq3SuNa6/ep39NpBHvTVrksBHCNN575HP/tDCG7t7upX39prqRfeLxsP3oDc5RTBf6sdbG6qCf66K1PyuvTsWgld/7RW2lfI+u35ZkP9gdFpFztcd0gjvr10K+kX3i8zDsfwPeEdgIhVq02t0/K69OxxJhecd84+bljVzzIWlPUrwdC/db6RWWTo98KDLfaJ+X16VhqmK69ebMfG8o4UerXw6N+5T5E/dbY9El5fboLo4bp2psp7+FrH2O9PerXE0m5dOisLD6P6w4NbUUpS3/WulhdFOd+PdJr/9GPDzyvfdbR9rY3fORk9IAUO6lfDylJv/BMLp94puiReSHa+dtYK9rcPo1++/QF6BjTK+7r02XRnjb160lRv3KH4ei3xqZP7/NZ+u+M1c7q7jfv8R8C1K/vdtSv/O6jfmts+qRf+f1bO+jH37zHfwjIl08uiVzJp3zkDnhHLj6P60Bz7jfS3eRd2gmEWA3a3D7p1z4KLHYqkX2j1+3y38uhYPTlfp3h7evL/tbPYXn5+nK31tp9bhk1PFD+82sW6gnJfXi9x38IyJKVSyKsn1K/nPut9oR+/NtPq9DqkYd1bW6f9DuYtP0GZXF2v/a3gt0yL34UZ+c/prJPbByXT1uwzwxzPyBqX4pluI0b+M9HHOoJ6Prw+mUiv5XRhwNrOAZZsnJJpDrqNwLlbBc/ejtDcukdWoXG2tXm9kq/ut+de7cPtJ6vVjtjht6/hX7XVrTvBxJ7+8zyQr8L9+hq90j0YeyLZqOxGa5W9inUcTnHuF5pHySsKx1TWzPyMcslkTqp3wiUs13U7xmSS+/QKjTWrja3V/rV9amNmfph7mxSPCxzt3A/sjY1k/JHeuxvVR70u/JsPpf2wf0Rxa59TX9DX0GM4s32QcK62VGeNiwfs1xyWoPfekr9cu632hM4+VClcbX1bSnQhia/jDnM1r6ahXNqmHwofmrYZc7N9KBfNwZ2i/0V+PNniP2aiXfysn93XPTpJ/gKgu1/ypKVSyK1PqV+Ofdb7QnUb5XG1dbfNY8ZnxlzmOP9/Ji6KQX786n2T/szrpvD7MPn4uPnZPRri3/MxGZ9lj9p+2nFGx7ruB/17tO3lzt85o4sWbkk0rWo3wiUs126fyiepqE5ytvEfCO6WF0Uv/V2et2utfVSDmwbWvwrftH9GBFGv9sweP4226DfMPodjPwP+JSfxfm5YT/V/BKbFD5WfqM16lcFPuUeWywHi3YHjWe4f669qs73GIRn4K0oZekPSheri6J+j9f5qmvr2m9HRBv/sR+k/bz7aQNfXsz92tHvyI9w3TTwKOh3Vdbgf5Zidfi5n/F4YksW5u/bPp938VPeMVFG33qF+lVdgRTVYTlYtDtoPMOKkXO/1evNyYcqjeutv5pNuwr31r922f18FQdWjn4HH3724XOxs3MNxZ0P5eh3sDmb/N3b+WAzWVsB79obvR4D3xL1qwKeojosB4t2B41n4OPSlAw8RzlW9VdKF6uL4uhX1fkvH7QfmvnX6Lgch7gnbX39+B+VWMz9nG2482E7KGYflnYIHfS7KvM2Zw+xsVMdZmVbsDeyuVsnerVQv6rLkaI6LAeLdgeNZ+BiTMnAc5Sy9FdKF6uLon5Vnb+DoNnCj2zDH//EJv6+V/Z2Xj9sPY5+38zEJkzNX6nf4+h3eDb6tfotxtpLnyY2dYsC6ldFPUV1WA4W7Q4az8DFmJKB5yhl6a+ULlYXRf2qOn8XQV/u6xPGTIolfI8i2tJ+a/xUcXnng7sJ4n3w4m6fOBv92pkG++nGajM8/LdZDdzkg6/Yfph3mMeItnOLndSvinqK6rAcLNodNJ5hxci53+r15txvlcY11z/tl4dXjTLczmfhgOZ+hvc4+vWzD27uodRvOfq1N/7aR0Kc3vlQ/k7bwpRVhqpv/Er9qi5AiuqwHCzaHTSegY9LUzLwHOVY1V8pXawuiqNfVefvIsh+d6JFhYVtfdtbM7WvFf3+2Xsf1u5bGWej37n/asXL25/9z/9hg+zNEr4aOwvRt7vPqF9V50pRHZaDRbuDxjNwMaZk4DlKWforpYvVRVG/qs7fQdC/9nkAe7dCkOWH92dFv9aoxbetg37D6Pfbzz3UDjh82+3VDGslN9+kflWXIEV1WA4W7Q4az8DFmJKB5yhl6a+ULlYXRf2qOn8HQYVQGyt+GZvxq7slYjQ3i5Nvvdl9SzP2d7AH/a72+/3n3/vK+HFyrd6Xib/l4e/8U7la4PU3n1i/iL6Q2HARsRws2rWBZ1gxcu43XB73yrnfKo3rrf+rPDRSbNXdHbHY7Ib2Ezp/Z0R19Gs/RfPPgQj69Z/juT+msXvY/i3MbvszMWve9yvS1hfIXy2WSyK1I/pCYkNTWA4W7drAM/BxaUoGnqMcq3qwulhdFPUb+uqVX+dnd4fFDuDF3XNml3nxEV1Vv3b2wc83nOh3sZkLt1D4JwcvVr2zr719YxE7817vkyUrl0ROCNEXEhuawnKwaNcGnoGLMSUDz1HK0oPVxeqiqN/QV6/7am8FO/5iRWPTo9/3WWw825gUK3x7/71IPbG6M/ZRvyp4KarDcrBod9B4Bi7GlAw8RylLf6V0sboo6lfV+S8e9N6/Jz9e/Bx1FVK/Kk4pqsNysGh30HiGFSPnfqvXm3O/VRpXWw+PLLtag71tiPpVXZoU1WE5WLQ7aDwDH5emZOA5yrGqv1K6WF1Ub0a/6+PjD7C1t+KW2PY+3Ktfu5jCz91rP8H7jKB+VdctRXVYDhbtDhrPwMWYkoHnKGXpr5QuVhfVG/3a3yxLXtw3EtqXXul32Lsv/7YD7CaC+lVxTVEdloNFu4PGM3AxpmTgOUpZ+iuli9VF9Ue/h2cf4C+L2I2ukS7dK/0a08ePwSLUOt9F/aoQp6gOy8Gi3UHjGVaMnPutXm/O/VZpXGvdfmX4Wk31vR3qV3WFUlSH5WDR7qDxDHxcmpKB5yjHqv5K6WJ1Ub0Z/eomEGI99R5/6XhmNrFTecZ91K/qqqeoDsvBot1B4xm4GFMy8BylLP2V0sXqoqhfVee/dNA/zS9tXrrRftZH/aquS4rqsBws2h30NX6F7TqtrM2v6iq4IF0s9VsD2qe539fiG2u1I3zKTepXddlxOaKjU7yFJP32cu7X/xSt6jq4xw5qVE391nD2Sb99OpYapmtvUr8q4kmqg+5uxFvAM9wPtMi/6xIHgWfgreiUWhyfLlY3RubkQ/yad7yX+i0BU78liqaVFNVhOVi0O1Y8AxdjSgaeo1NqcX10sboo6repz3dWRv2WaKnfEkXTSorqsBws2h0rnoGLMSUDz1HK0l8gXawuivpt6vOdlVG/JVrqt0TRtJKiOiwHi3bHit/Di4sxJQPPUcrSXyBdrC6K+m3q852VUb8lWuq3RNG0gssRHZ3iLeAZuBhTMvAcpSz9BdLF6qKo36Y+31kZ9VuipX5LFE0rKSNNLAeLdsdK/cpXjPqtsemT8vp0LDVM196kflXEU1SH5WDR7qDxDHxcmpKB5yhl6a+ULlYXxdGvqvNfOoj6LYlSvyWKphVJdfsXeZmbpVx4VqKLfqs8j9D+Ykt1s1Iir67NUi6MlMxmO7OdoQua82GWhybeW5eN2bbGvL/rot6XygfWNHWN/DLtF4djLWlz+6S8Ph1LjOkV9z2afpOf28fEJyQwpX6v6JrQFPUbSDzcb71d2yENjwi0P8baUFov0kWPh8dlYSbHDeXawlRraE/6+FiYzQe6oDnH+HXrMjEfrTHrtS5qvaJ+SxNcb4X6LVk/2uh3XJ5Z6wryNV9p8qGpESwHi3bt4hn4rGxKBp6jnKn1sHWxuijO/Tb1387KqN8SLfVbomhaSVEdloNFu2PFM3AxpmTgOUpZ+guki9VFUb9Nfb6zMuq3REv9liiaVlJUh+Vg0e5Y8QxcjCkZeI5Slv4C6WJ1UdRvU5/vrIz6LdFSvyWKphX8rlxUj7hMU44Jf4AOnkH9NvWkSJn27oVI6kCb2yfl9elYYkyvuI/6VcHG5XgF/UJPVCtOE5cpntGtfnXPMtNFPc/od98n5fXpWFTv/u6CqF8V2yT9Qs/WxceyKceEyxTP6Fa/umkFXdTz6HewNT+qjn6NIOq3pEz9liiaVlJUh+Vg0e5Y8QxcjCkZeI5Slv4C6WJ1UU+k3x+zberfVy2jfkvc1G+JomkFH5uiesRlmnJM+FgWz6B+m3pSpEw7fxtJVc/9IndZxtq55D7qt6RJ/ZYomlZwOV5Bv08596sb1+qinmj0m/K3aNMbIqeM+i3pUb8liqaVJP1y7rcJaaVMKUufoYvVRT2RfjdmVgF+21Xqt+RP/ZYomlaS9AuNTvEW8Ax8WiAlA89RytJfIF2sLuqJ9GvMS1P/vmoZ9Vvipn5LFE0rKfOsmB6xaHesKceE/xsUz6B+m3pSpOwKc79fBvg2fuQQL7qL+i1xUr8liqYVXI6c+23ieVqmHKv6JF2sLup5Rr9LMz9Ffsst6rekT/2WKJpWkvTLud8mpJUypSx9hi5WF/U8+rVPk67wvvEq9VteAOq3RNG0kqRfzv02Ia2UKWXpM3Sxuqin0e9+Yr4qvG+8Sv2WF4D6LVE0raTMs2LKxqLdsaYcEz6Ti2dw7repJ0XKup/7fTUfkXZvtYv6LclTvyWKphVcjpz7beJ5WqYcq/okXawu6mlGv7s+zT0MqN+y+1O/JYqmlST9cu63CWmlTClLn6GL1UU9i35fzWRfwX3rVeq3vALUb4miaSVJv5z7bUJaKVPK0mfoYnVRT6Lf2aRXg1+Ofo9dn/o9smhYS5lnxZSNRbtDTTkmfCYXz+Dcb0NHihV1PPf7O+nTXWcWAEe/ZS+gfksUTSu4HDn328TztEw5VvVJulhd1KOOfj9H5TJ7nRoz7dPUA/Vb6fxPrF9EqUhsoIuNTrFo10bKMeFjWTyDo9/QA5SvFx/9Lk9+73ux7Zd9Ofo99gvq98iiYS1FdVgOFu0OFc/AxZiSgecox6r++uhidVGPOvpdTsrlY7r9a+jXNyni5EOJnfotUTSt4GNTVI+4TFOOCR/L4hnUb1NPipRdfPQbaaNPu6jf8mpQvyWKphVcjlfQL3RnRXF2uEzxDOq3qSdFyl7NupyrBVfetmYaqbHfu6jf8vpQvyWKppUk/fK+3yaklTLlVIHP0MXqonoz+TA5mazFNqjfSk+6t1XqV3XFkvQLjU7xFvAMfFyakoHnKGX5wPot52rRlQVHv6o3cE+Dnlm/wOg0ZZ4V0yMW7XpTyjHhUwl4BvULvtc59wsCe5zwZ9YvMDrF5ci5X/2b5OlHv+kTCDnq1l+gy0Zy7rfkSf2WKJpWkvQLjK5TxrIpx4SPZfEMjn6belKkLEehObmRQ7nKLuq3xLw3ply/l5U38ZdT5JLIuSH6QmJDU1gOFu3awDNwMaZk4Dkc/YY+A79SvzCyXiUY07PvxLTTkSUrl0RqReZOkdjQFKZHLNq1kXJM+FgWz6B+Qw9QvuYoNCdXeXgXD+Po94h0Ynr3rZjjwcXXZMnKJZGaEOEhsaEpLAeLdm3gGbgYUzLwHI5+Q5+BX6lfGFmvEjZm1qvjURyMLFm5JFItoi8kNjSFjU6xaNdGyjHhY1k8g/oNPUD5mqPQnFzl4V08jKPfI9Kp+T5u3MeaLFm5JHJmiL6Q2NAUloNFuzbwDFyMKRl4Dke/oc/Ar9QvjKxXCat+PYpZw0aWrFwSqRcZbyKxoSlMj1i0a+Ma49LrtLIBfghSF6sU+r9efGkhR6E5uaGjXvuVo98j8a1ZHTfuY02WrFwSOTNEeEhsaArLwaJdG9RvIH3+Sv2eM+nNHur3eCn+mfVx4z7WZMnKJZEzQ4TXverwFvCMwUCppQotPANvRTeiLQ5KF6uL6s0zH/i1i0qPe6pV+72Le7vzTJasXBK5ptRvBMrZLur3DMmld+RMIOTkXvo8tPVx9FshNTS/la17WJUlK5dEzguZz00ZaWI5WLQ7HTwDH5emZOA5yrGqv4a6WF0UR7+Rt0X3u6jfCuOV+als3cOqLFm5JHJeHP1GoJztus7oV3/zo+5GSer37EL2Zwf1W7kWMzO5s9kHWbJySeWEwyr1G0g0vV5Hv19Nh3BSphOrLoqj3xO019qgfqukN/d265ksWbmkesKHdeo3AuVs173qVzWe5o1nZ9f7Cjuo3yrkVzN8qW73fl2WrFwSOSnO/UagnO26V/2qxtPU79n1vsIO6rcKeb8z87uafpAlK5dUT/iwztFvBMrZLur3DMmld+TcvZCTe+nz0NZH/Z6Q+lqY+T2Nf2XJyiUnJ1xsUL8RKGe7qN/PMya6Heq3VI5Cc3J1p3H5KOr3lOnvwox/fis/snpa3LctWbJySeQcqN8IlLNd19GvaqbWH9vV73x4+VidQdHs+J3804TZmByF5uQqD+/iYdRvDelod/rrqrXinm3+DXfCEWH6BX6NQrrHdv8iL2vzKheeleii3yp/R67NsrKlW/0w37rAQ9Rs9mGWM3RBc4bm+9DEe+syNMvWmPd3XdT7sv2ZD38fJulr+XZIY5T+zVFoTq7wJup8N/V7hvh3tRsef2X1rPhOdryd/i3CLRJoJDBt1e/fxlWwgvu/s6/WvzkKzcmFT+pCCdTvhUD2rZrr6/f4V9bZmjGLs33yDl30eHhc7IzRcUO5ZsCcj4+F2XygC5pzjF+3Lguza41Zr3VR61Wbft3Y1y0rsKcX9lX6N0ehObngOV0snPq9GMp+VYRNPgC/dCxNPjSdPpaDRbt28Qz868ApGXiO8ksSHrYuVhfV/rWLt2GhX9C/wb66Z2nnKDQnt6nzdllG/XZJ94Z1U78t8PEP0vCMR9LvIMm/mH350VtLp2XxnRCgflsuFC5TPOOh9Dv4O4x/F6sWtMdi0L7U7xEd1+6ZAPXbcvVwmeIZj6VffPyL2pf6bem0LL4TAtRvy4XCZYpnpOj38vf9qmpUfekYHP/C9qV+Wzoti++EAKbfC9z328QF+2gMi3bt4hm4GFMy8BzlB2Ueti5WF9X+0ZtvEpr/xe1L/XrK/OPuCWD65Z0Pigt+ndGv6gE5/mh1YtVFKfWLzP8m2Jf6VXRDhtwBAeq35SLhMsUzHm70Oxi8+S9fKO7/TbEv9dvSaVl8JwSo35YLhcsUz3hA/Zafv7Xc/5BkX+q3pdOy+E4IYPrl3K/islK/HpJq/JtmX+pX0Q0ZcgcEMP1y7ldxSa+jX9V9Cv5otU88U9WouvOhgBQ+f2sY/ybal/pVdEOG3AEB6rflIuEyxTMecfLBYg33n5mffRxyqn2p3zhP7r03AtRvyxXDZYpnPKh+j/5dRSEn25f6jfLkzrsjAOr3W32CKffYYjlYtDtwPAMXY0oGnqO8TcxfLV2sLkp749mhm5Tzv7Hxb7p9qd8DX77cOQFIv4i+kNjAEMvBol0beAYuxpQMPEcpSw9WF6uLAvVb3v8Qef5Zhn2p3/CO4et9E6B+W64fPpWAZzyufo/zD/Xxb459qd+WTsviOyFA/bZcKFymeEaKflX3Kfhzu9WdDwXY4+dvJ6Cz7Ev9nrDkRm8JLJfLwxv1e7mMzNxSvy2XDpcpnpGi335/6bgCtfTvB8UOEQAAIABJREFUqrIzz77UbwUlV3tMwH7tc1sc3tqY9fmBUr/nTE724DLFMx5av5X5hxJspn2p35IkV3pNgPqtXB5+9FaBUVvt5qM338jZ+DfXvtRv7eJxs6cEqN/KhaF+KzBqqx3qtz7+zbYv9Vu7eNzsKQHqt3JhqN8KjNpql/odFD8+b/viyraab1/qt3bxuNlTAtRv5cI8kn7v5c6HAv/x+xeXsC/1W+nUXO0xAeq3cnEeSb93c+dDwb/073xhu6RbIrfhVC5V82rOj8Xn5DYfVXel/KH57th2WrPt55u5X8a884H6lftap5MPttnSv969efa1o9/1KHF525qpTKGnJdRvTy9M22EdOnvxwhvP/rXxOivHbyPDMx77xrMD0vL+B98Xc8a+A6vfyUnHxjao37Nezh3dEDjpmNQv9St1s65Hv/b5k+H3h2yfzLOv02/ysuDoV+oD3H9pArarr37ff+3/H5x84OSD3L261+/x+Tu59uVHb/J1ZEmfCFj98ltv4YI8kn7v684HfwXKO87MT7giia85H5/l5CYebnYa536zEd6mAuq3wv2R9Htndz7Yq/Bbma/N9G+OQnNyK33pqqvU71VxX64x6rfCkvqtwKitdj75cBz72j6ZOf7NUWhObo3Z1Tap36uhvmxD1G+F59q8V7Z0q/h9DHjGM9z5cGrf4vtvuisQicpRaE5u5FCusov6vQrmyzdC/VaYXkOMuErdAaJHNjZvlfNqXtXFdjz6Le27DPc/5Mw/5Cg0J7cZdHel1G93bDut+Wb6TRlpYjlYtKOMSi4t5xqt6JRa9CxdbLf6Le37XX/+TnGM4J85Cs3JBQ/zYuHbzMmaix0IK8II7Nbr1yLjZ72LDDg6e95v9xLCW8AzBgOllipXBc/AW9EptTgoXawuCv2ttwOWin0r9/9GumMFY9NqjkJzcpuOqcsy6rdLujesm/ptgY/LFM94dP2e2PcS/s1RaE5uS1/prPgn3D3aWQus+CYEqN8W7LhM8YwH12/Nvhfwb45Cc3Jb+kpnxdRvZ2hvWzH128Iflyme8dj6PbNvvn9zFJqT29JXOiuem8MMYmctsOKbEKB+W7DjMsUzHlq/EftWnn+WNv+bo9Cc3Ja+0lkx/ilzZ4fCii9JgPptoYnLFM94ZP1G7Zs7/s1RaE5uS1/prHhoRp3VzYpvSID6bYG/MfqnKxRV4RlOv1gryvsU/AHpYnVR8J0Pgn2tf4f2nki3pIx/cxSak9vSV7oq/jRm31XdrPeWBKjfFvr4WBbPeNzRr2jfvPFvjkJzclv6SlfFM7PpqmrWe1MC1G8LflymeMbD6rfBvln+zVFoTm5LX+mqeGnmXVXNem9KgPptwY/LFM94VP022jfHvzkKzclt6StdFU9540NXaG9cL/XbcgFwmeIZD6rfFvtm+DdHoTm5LX2lo2I79fvXUdWs9rYEqN8W/rhM8YzH1G+rfdP9m6PQnNyWvtJR8dJEfiWso7ZY7VUJUL8tuNF7EpxKsbsY3AGgOcr7FPy56WJ1UcCdDwr7Jvs3R6E5uS19pZvi/YZzD92QvX2t1G/LNcDHsnjGI45+VfZN9W+OQnNyW/pKN8VbM+RtZ92gvXmt1G/LJcBlimc8oH6V9k30b45Cc3Jb+konxZYk/vvcnRwJK704AavfF/WyNq/q2J35F439G8nLh/mWC89KdNFfs+PyYZbHDeXa0LwqI4uw9/ehWb6jC5ozMa+HJr5bl4lZtsZ8f+uivre6n2lX2zfNvzkKzcm9+NuvvUJ7YVbtUYy4TwJvxVeP+CcJqAhMVfoF7Jvk3xyF5uRe5T3+V/nrfrk2vOf3KtRv04jV70S9GLPIjh0P5cWYptJ6ni5683FcFqa6ddzftIbmrNcLY59xDy5ozjF+3roYM22Nmc91UfOVRr+QfVP8m6PQnNyrvEeXJ38PTrZXaZSN3IQA535bsOMzuXhGt3O/Q9XvwumiVHc+gPZN8G+OQnNyW/rKZYpfy3HG5mO+/LxMpayllwSo35bLgssUz+hWv7pbynRRGv3C9sX9m6PQnNyWvsJiEsAIUL8tvHCZ4hkPpd8E+8L+zVFoTm5LX2ExCWAEqN8WXrhM8YxH0u/X4jB1+d0C9rT4L/z+vGqqM0ehObmnx8wtEsgkQP22AES/j+ZU+szfetvbD/Hcgtm3HP+Ov1quhy/OUWhOrubYGEMCNQL70VttT9iE9Iv8UDsSGw4Gy8GiXRt4Bj4uTcnAc5QztR6sLlYXpZj7LfyL2vfg37HuVx1yFJqTGzoqX0kAICBLVi6JVI/oC4kNTWE5WLRrA8/AxZiSgecoZenB6mJ1UQr9DgZ2/Ivb1/tXad9BjkJzckNH5SsJAARkycolkeoRfSGxoSksB4t2beAZuBhTMvAcpSw9WF2sLkql38Eqxb7Wv1Pd2HdA/YZ3DF/vgYAsWbkkcl6IvpDY0BSWg0W7NvAMXIwpGXiOUpYerC5WF6XTb7ienb3mjGBzcjs7IVb8yARkycolER6IvpDY0BSWg0W7NvAMXIwpGXiOUpYerC5WF0X9hr7KVxLQEpAlK5dE6kb0hcSGprAcLNq1gWc4MaL3MeAZeCtKWXqwulhdFPUb+ipfSUBLQJasXBKpG9EXEhuawnKwaNcGnoGPS1My8BylLD1YXawuivoNfZWvJKAlIEtWLonUjegLiQ1NYTlYtGsDz8DFmJKB5yhl6cHqYnVR1G/oq3wlAS0BWbJySaRuRF9IbGgKy8GiXRt4Bi7GlAw8RylLD1YXq4uifkNf5SsJaAnIkpVLInUj+kJiQ1NYDhbt2sAzcDGmZOA5Sll6sLpYXRT1G/oqX0lAS0CWrFwSqRvRFxIbmsJysGjXBp6BizElA89RytKD1cXqoqjf0Ff5SgJaArJk5ZJI3Yi+kNjQFJaDRbs28AwnRt75EK6Pff2nedx6Jb6b1VezrvwkBLaq/Lmkbg6ctT4jAVmyckmEE6IvJDY0heVg0a4NPAMfl6Zk4DnKsaoHq4vVRfVGv5PiwT5Jf05Df+MrCVyDgCxZuSRyXIi+kNjQFJaDRbs28AxcjCkZeI5Slh6sLlYX1R/9qn/1qhJofyprsVj0Yvweujxfn4CALFm5JIIF0RcSG5rCcrBo1waegYsxJQPPUcrSg9XF6qJ6o9/0ESy/dBzebny9EgFZsnJJ5NAQfSGxoSksB4t2beAZuBhTMvAcpSw9WF2sLor6DX2VrySgJSBLVi6J1I3oC4kNTWE5WLRrA8/AxZiSgecoZenB6mJ1UdRv6Kt8JQEtAVmyckmkbkRfSGxoCsvBol0beIYTI+98CNfHvvblzgdOPlQuClf7TUCWrFwSOSNEX0hsaArLwaJdG3gGPi5NycBzlGNVD1YXq4uifkNf5SsJaAnIkpVLInUj+kJiQ1NYDhbt2sAzcDGmZOA5Sll6sLpYXRT1G/oqX0lAS0CWrFwSqRvRFxIbmsJysGjXBp6BizElA89RytKD1cXqoqjf0Ff5SgJaArJk5ZJI3Yi+kNjQFJaDRbs2PuB5XFyMKRl4zsT8BWitr7pY6rcVJANIIImALFm5JNIQIjwkNjSF5WDRro2NUf2MeTgc/4rn4Bn4kU3M58lRNm3oYqnfJoYsI4F0ArJk5ZJIa4jwUkaaWA4W7U4nRYxDo/39xwAMzxgM0JyFeQnNtb7qYnVjZE4+tOJmAAnUCMiSlUtqVbhNRL8pqsNysGh3/HjGYKAcFbrqDwuegbeiU2pxQLpY3RiZ+g1Xma8koCUgS1YuidR9//pF7+HFxZiSgefolFpcQl2sLor6jbwtuIsEGgnIkpVLIhXev37xuV98LItnUL+Rzta0K+e5DTm5TcfEMhIQCMiSlUsiVWH6xUea2DfMsGh3Opx8iFzUwy6OfmU2LCGBHAKyZOWSSHuYfvGRJqZHLNqdDp6Bj0tTMvAcpSz9NdTF6qI4+RB5W3AXCTQSkCUrl0QqpH4jUM52cfLhDMmld+RMIOTkXvo8WN9TEJAlK5dEwFC/EShnu6jfMySX3pGj0JzcS58H63sKArJk5ZIImPvXLz4fjcsUz+DkQ6SzNe3KUWhObtMxsYwEBAKyZOWSSFX3r198PhqXKZ5B/UY6W9OuHIXm5DYdE8tIQCAgS1YuiVSF6RcfaWL3MmDR7nT40Vvkoh528aM3mQ1LSCCHgCxZuSTSHqZffKSJ6RGLdqeDZ+Dj0pQMPEcpS38NdbG6KN75EHlbcBcJNBKQJSuXRCqkfiNQznZx8uEMyaV35Ewg5ORe+jxY31MQkCUrl0TAUL8RKGe7qN8zJJfekaPQnNxLnwfrewoCsmTlkgiY+9cvPh+NyxTP4ORDpLM17cpRaE5u0zGxjAQEArJk5ZJIVfevX3w+GpcpnkH9Rjpb064chebkNh0Ty0hAICBLVi6JVIXpFx9pYvcyYNHudPjRW+SiHnbxozeZDUtIIIeALFm5JNIepl98pInpEYt2p4Nn4OPSlAw8RylLfw11sboo3vkQeVtwFwk0EpAlK5dEKqR+I1DOdnHy4QzJpXfkTCDk5F76PFjfUxCQJWtLXtTLzvxTx27MbzT2byQvG/NPLjwr0UV/zY7L0LweN5RrY/NPGVmEvb+Pzes7ukzAnIX5PjTx3boszGtrzPe3Lup7a6Y9eMfkKDQntwenzkO4PwJN+jVcSEBNYEr93t/bn0d8WwKN+p2oF2MW2bHjobwY01Raz9NFbz6Oy8JUt477m9YMmLNeG7Nbo8sCzDEmtDBvXYyZtsbM57qo+Yr6ve1bma3fH4Em/Y71p4N8dIXEhiPAcrBo1waegX8o5n61+C2ckPoVnS+uf1C29y3F/yxiXVm8vNjvo4qApqP+R/024WEZCZwToH49k+voF1WpOzQ0p67f80t+3KOL1UXxzocjV66RgI4A9es5Ub9yd6F+ZTYsIYEcAtSvp0f9yp2I+pXZsIQEcghcTL8z9VHg30lzc7P6+tFod+BY/cWpotMC+ESCawdtRSlLfwq6WF0UJx+KXsE/SUBP4GL61X+TLWWkieVg0Q4WnoGLMSUDz1HK0vcQXawuivrVv+kYSQIFAerXc6B+5TcE9SuzYQkJ5BCgfj096lfuRNSvzIYlJJBDgPr19KhfuRNRvzIblpBADgHq19OjfuVORP3KbFhCAjkELqZf/Z0JKXcZYDlYtMOHZ+AfiqVk4DlKWfo+o4vVRfGjt5y3IXOfk8DF9Ms7H9o7EHoTmasRzVHK0h+sLlYXRf22X39GkMApAerX8+Dkw2m3qG5Rv1UaXCeByxGgfj1L6lfuUtSvzIYlJJBDgPr19KhfuRPdmX7X0DPwq8H9eGC8fCFY8nAEqF9/SalfuWffmX4n6gfEnwf24fc65AvBkocjcDH98s6H9r6BfozmakRzlLL0B6uL1UX15qM35Ln8p8/pn/TiicXt3YgRD0PgYvrlnQ/tfQJVqasRzVHK0h+sLlYX1Rv9po9g+Vtv7V2YERclQP16nJx8kHsV9SuzYQkJ5BCgfj096lfuRNSvzIYlJJBDgPr19KhfuRNRvzIblpBADgHq19OjfuVORP3KbFhCAjkELqZf3vnQfhnQj9FcjWiOUpb+YHWxuih+9NZ+/RlBAqcELqbf+77z4Ro/AY+r1F0qVL/G7E+vcMOWLpb6bUDIIhLIIED9enio5FwSnoNn4K0Yo+8NuljqV0+UkSSAELiBfodmhByhj8VysGjXQIoYJ+YFPA88YzBAc3RKLQ5cF6sbI3PyAewMDCeBwQ30m6I6LAeLdr0AzxgMlKPCSifDM/BWdEotDkoXq4uifisXmqskoCJA/XpM1K/cW6hfmQ1LSCCHwMX0q7/zIUV1WA4W7fDhGfi4NCUDz1HK0vcZXawuiqPfnLchc5+TwMX0q7/zIUV1WA4W7S48noGLMSUDz1HK0vd2Xawuivp9ToHwrHMIUL+eHvUrdyLqV2bDEhLIIUD9enrUr9yJqF+ZDUtIIIcA9evpUb9yJ6J+ZTYsIYEcAtSvp0f9yp2I+pXZsIQEcghcTL+886H9MvC+33ZGmRE5j0zPyc08bKY/J4GL6Zd3PrR3IOq3nVFmRI5Cc3IzD5vpz0mA+vXXnZMPcvfn5IPMhiUkkEOA+vX0qF+5E1G/MhuWkEAOAerX06N+5U5E/cpsWEICOQSoX0+P+pU7EfUrs2EJCeQQuJh+eedD+2XgR2/tjDIjcj4+y8nNPGymPyeBC+kX+bWIlJEmloNFuwuPZ+BPY0jJwHOUY1Xf23Wxuig+8+E5BcKzziFwIf0i+kJiw6lhOVi0awPPwMWYkoHnKGXpwepidVHUb+irfCUBLQHq15OifuUOQ/3KbFhCAjkEqF9Pj/qVOxH1K7NhCQnkEGjU74t6GZuv7Ni/kbyMza9ceFaii/6aHZex+XfcUK4tzK8ysgh7f1+Y73d0QXOMCS18ty7GtIbYAF3U99ZMczrihXJzPj7Lyb3Q4bOa5yLQpF/DhQTUBKbU73Opg2ebT6BRvxP1YsxiMZlo/p9MpNjxUF6MaSqt5+miNx/HxZjq1nF/0xqas14bs4YXNOcYP29djGkNsQG6qPmK+s1/O7KG5yLQpN+xHgUyd4rEhiPAcrBo1waegd+TkJKB5yhnaj1YXawuinc+hL7KVxLQEqB+PSnqV+4w1K/MhiUkkEOA+vX0qF+5E1G/MhuWkEAOAerX06N+5U5E/cpsWEICOQSoX0+P+pU7EfUrs2EJCeQQoH49PepX7kTUr8yGJSSQQ4D69fSoX7kTUb8yG5aQQA4B6tfTo37lTkT9ymxYQgI5BKhfT4/6lTsR9SuzYQkJ5BCgfj096lfuRNSvzIYlJJBDgPr19KhfuRNRvzIblpBADgHq19OjfuVORP3KbFhCAjkEqF9Pj/qVO9Gd6XcNPQW0GtyPR2bKF4IlD0eA+vWXlPqVe/ad6dc+US956cMTi+ULwZKHI0D9+ktK/co9+870izyZ9PRJpZNePDJTvhAseTgC1K+/pNSv3LPvTL/pI1j+2oXcCVjSCQHq12OlfuXeRf3KbFhCAjkEqF9Pj/qVOxH1K7NhCQnkEKB+PT3qV+5E1K/MhiUkkEOA+vX0qF+5E1G/MhuWkEAOAerX06N+5U5E/cpsWEICOQSoX0+P+pU7EfUrs2EJCeQQoH49vYV5gSniOXgG/EvHL2ahPhFlLPWrJspAEoAIUL8eV5oYPyHUTqVoBpyjVKo/cGUs9QteZoaTgJLADfSbpjpkdIq3gGcMBkotVS4EngG3olSqPyhdrC5qMPjXi++M5Xx1Iie3cpW5SgJaAtSvJ0X9ih2G+hXRsIAE8ghQv54f9St2I+pXRMMCEsgjQP16ftSv2I2oXxENC0ggjwD16/lRv2I3on5FNCwggTwC1K/nR/2K3Yj6FdGwgATyCFC/nh/1K3Yj6ldEwwISyCNA/Xp+1K/YjahfEQ0LSCCPAPXr+VG/YjeifkU0LCCBPALUr+dH/YrdiPoV0bCABPIIUL+eH/UrdiPqV0TDAhLII0D9en7Ur9iNqF8RDQtIII/AhfQ7MX/q40hRHZaDRbsDxzPgpzHYVvjMB3UnSQ3MeW5DTm7q8TLvqQlcTL/6Z3mlqA7LwaLd9cczUmRK/Xb+XstRaE5u5yfGBh6RwIX0i+gLiQ3IsRws2rWBZ1C/4docXvnEsxoQbpJAGwHq1xOifsWOwrlfEQ0LSCCPAPXr+VG/YjeifkU0LCCBPALUr+dH/YrdiPoV0bCABPIIUL+eH/UrdiPqV0TDAhLII0D9en7Ur9iNqF8RDQtIII8A9ev5Ub9iN6J+RTQsIIE8Ao36fVEvC/OWHfs3kpeFmcmFZyW66K/ZcVmY3+OGcs0YZeAh7P3dmHd4AXO+zSI08d22vJpFW4gt10V9f2/5U5t5b0VmPx+BJv0aLiSgJjClfp9PHzzjPAKN+p2oF2PUoRMpdjyUF2PksvMSXfTm47gYU9067m9aM6ap9LxsvTZmDS9ozjF+3rZMjWkLseW6qPl8Rf3mvRWZ/XwEmvQ71uNA5k6R2HAEWA4W7drAM+7kW297TzD+53FWN14+GLj9xyhflfgHv/UmomEBCcQJUL+ey8PqN37Vi706seqiBgPqt4k1y0ggQoD69VCo30jfKHZRvyIaFpBAHgHq1/OjfsVuRP2KaFhAAnkEqF/Pj/oVuxH1K6JhAQnkEaB+PT/qV+xG1K+IhgUkkEeA+vX8qF+xG1G/IhoWkEAeAerX86N+xW5E/YpoWEACeQSoX8+P+hW7EfUromEBCeQRoH49P+pX7EbUr4iGBSSQR4D69fyoX7EbUb8iGhaQQB4B6tfzo37FbkT9imhYQAJ5BKhfz4/6FbsR9SuiYQEJ5BGgfj0/6lfsRtSviIYFJJBHgPr1/KhfsRvdm37X2EPwK9H9eGC8eCFY8HgEqF9/TalfsWvfm37t86STl6lIgQUk0AEB6tdDpX7FvnVv+m16av/5k/mreya9eGC8eCFY8HgEqF9/TalfsWvfm37TR7Cv1K/YC1jQCQHq12OlfsXeRf2KaFhAAnkEqF/Pj/oVuxH1K6JhAQnkEaB+Pb+F+YQ5GoOm4BnwL8r9mYn6qHSx1K8aKANJACNA/XpeVxCjbecKrbyZoboD6GKpXzVQBpIARuAm+sVHmtjoFIt2wBLEuIdz8Az7W8NgK/L1PO8XuljdGJk/tXnOl3tIoIWA/BaUSyJVInOnoFB8a1gOFu0awDPUP8B+pKUdRx4z9D/zHnKQq6aL1Y2Rqd9wBfhKAmoC8ltQLolUTv1GoNR33at+x/UTiW7zh+ajWLiTBGQCsmTlkkht1G8ESn0X9VsncvntnHt3c3Ivfyas8QkIyJKVSyJYqN8IlPou6rdO5PLbOQrNyb38mbDGJyAgS1YuiWChfiNQ6ruo3zqRy2/nKDQn9/JnwhqfgIAsWbkkgoX6jUCp76J+60Quv52j0Jzcy58Ja3wCArJk5ZIIFuo3AqW+i/qtE7n8do5Cc3Ivfyas8QkIyJKVSyJYqN8IlPou6rdO5PLbOQrNyb38mbDGJyAgS1YuiWAxZh/ZG9+VcI8teF8u3gKe8UT3/fLGs3hH5l4SyCQgS1YuiTSJ6AuJDU1hOVi0awPPoH7DtTm88r7fGhBukkAbAVmyckmkTkRfSGxoCsvBol0beAb1G67N4ZX6rQHhJgm0EZAlK5dE6kT0hcSGprAcLNq1gWdQv+HaHF6p3xoQbpJAGwFZsnJJpE5EX0hsaArLwaJdG3gG9RuuzeGV+q0B4SYJtBGQJSuXROpE9IXEhqawHCzatYFnUL/h2hxeqd8aEG6SQBsBWbJySaRORF9IbGgKy8GiXRt4BvUbrs3hlfqtAeEmCbQRkCUrl0TqRPSFxIamsBws2rWBZ1C/4docXqnfGhBukkAbAVmytmSkXoxRh46Q2FCrMTNgwaJdxUjGe7F8m8VhTfuCZ7y/t+R815elmdR3idu6WF3U9/e2F78TnPPViZzctvcZy0kgQqBJv4YLCagJTKnfyPuLu0iggUCjfifqxRh16ESKHQ/lxRi57LxEF735OC7GHNe1a2jOem3MGl7AnN0xft62TM2iLcSW66Lm8xX12/A+YxEJRAg06Vf3ZVNfKTJ3isSGI8ZysGjXBp6RNPer/xXicOLocyK0Pw3k6pevfWhdH8UfG6oy4zoJqAjIb0G5JFIxoi8kNjSF5WDRrg08I0m/i3A+6ldcv/q/NHVXWBdF/aovKQNJIBCQ31xyScitvCL6QmJDE1gOFu3awDOo33BtDq+886EGhJsk0EZAlqxcEqkT0RcSG5rCcrBo1waeQf2Ga3N4pX5rQLhJAm0EZMnKJZE6EX0hsaEpLAeLdm3gGdRvuDaHV+q3BoSbJNBGQJasXBKpE9EXEhuawnKwaNcGnkH9hmtzeKV+a0C4SQJtBGTJyiWROhF9IbGhKSwHi3Zt4BnUb7g2h1fqtwaEmyTQRkCWrFwSqRPRFxIbmsJysGjXBp5B/YZrc3ilfmtAuEkCbQRkycolkToRfSGxoSksB4t2beAZ1G+4NodX6rcGhJsk0EZAlqxcEqkT0RcSG5rCcrBo1waeQf2Ga3N4pX5rQLhJAm0EZMnKJZE6EX0hsaEpLAeLdm3gGdRvuDaHV+q3BoSbJNBGQJasXBKpE9EXEhuawnKwaNcGnkH9hmtzeKV+a0C4SQJtBGTJyiWROhF9IbGhKSwHi3Zt4BnUb7g2h1fqtwaEmyTQRkCWrFwSqRPRFxIbmsJysGjXBp5B/YZrc3ilfmtAuEkCbQRkycolkToRfSGxoSksB4t2beAZ1G+4NodX6rcGhJsk0EZAlqxcEqkT0RcSG5rCcrBo1waeQf2Ga3N4pX5rQLhJAm0EZMnKJZE6EX0hsaEpLAeLdm3gGdRvuDaHV+q3BoSbJNBGQJasXBKpE9EXEhuawnKwaNcGnkH9hmtzeKV+a0C4SQJtBGTJyiWROhF9IbGhKSwHi3Zt4BnUb7g2h9e+6Hen/eXTs7ifXvxcUg0rNx+ZgCxZuSTCA9EXEhuawnKwaNcGnkH9hmtzeO2Lfu1vCSYv09o5cZMEOiUgS1YuiRwQoi8kNjSF5WDRrg08g/oN1+bw2hf9jrU/lXoWN+Tot3ZNudkxAVmycknkkBB9IbGhKSwHi3Zt4BnUb7g2h9e+6Dd9BPtK/dauKTc7JiBLVi6JHBKiLyQ2NIXlYNGuDTyD+g3X5vBK/daAcJME2gjIkpVLInUi+kJiQ1NYDhbt2sAzqN9wbQ6v1G8NCDdJoI2ALFm5JFInoi8kNjSF5WDRrg08g/oN1+bwSv3WgHCTBNoIyJKVSyJ1IvpCYkNTWA4WbdvYm0VoSf36AufgGQNY8l9moz4DXay2H1C/avAMJIGCgPzmkksi7BDhIbGhKSwHi7ZtXEOM12lFp9QCqy5W2w+o39BZ+UoCSgLym0suiVQNCC/rNZmcAAARtElEQVRlpInlYNHubFL0+2fGERBNu/CMwQDN0Sm1OEpdrC5qMKB+m649y0ggQkCWrFwSqQbQb4rqsBws2p0NnjEYQHw8MjwDb0UrS3dAulhdFPXrLzH/IAGEgKwEuSRSP/UbgVLfBRE9JKM5Wlm66nWxuijqt361uU0CrQTkt7dcEqmU+o1Aqe+CiB6S0RytLF31ulhdFPVbv9rcJoFWAvLbWy6JVEr9RqDUd0FED8lozgy480EXS/3WryO3SeBCBOS3t1xy3vSe+j2HcrYHIRqS0RytLF39ulhdFEe/4YrxlQTUBOS3t1xyXvmLmZzvFPakfMyF5WDR7jDxDPxDsZQMPEcrS3fWuljdGJn6dUS5kABEQJasXHLeAKIvJDa0hOVg0a4NPAMXY0oGnqNTasFVF6uLon5DX+UrCagJyJK1JfuRcpmZhTJyNGqI/ZoJy69ZCCWx3ero3/DE7W+zCKvq11czUccWgTbjG12WYM7WjMsmXpfNy48ZNwf40p+FJmq5XJmdutd1F5jz1LKc3O7OiDU/MIEm/Q7fkp9bzcQ7ILC48DEOe/A+yVFoTm4PTp2HcH8EmvQ7/htqF2O0kcOhHLs5ewL2YcfGGKkotl8bvVuHxZiwpn7dmYU6tgi0GXN0mYI562r8qnmZm0lzgC/VRa1WU+Cei+7eJzkKzcnt7oxY8wMTaNSv+ryRuVMkNhwAloNFuzbwDHxWNiUDz9HO1Lqz1n2opq2RXzp2TLmQAECA+nWwHke/OqUWHUQnVm2N1C/wtmMoCTgC1K+j8Dj61SnVnbP2xjNtjdRvQZV/koCaAPXrUFG/coehfmU2LCGBLALUr8NH/cqdiPqV2bCEBLIIUL8O33PqVzerS/1mvcGYTAIyAerXsXlO/erEqovit97k9xhLSEAgQP06MI+jX92ItugMOrFqa+RHb8JbjLtJQCJA/Toyj6NfnVKL3qCL1UVx9Cu9w7ifBEQC1K9DQ/2KHUT5XDTqVybIEhIQCFC/Dgz1K3QPu5ujX5kNS0ggiwD16/A9p351s7rUb9YbjMkkIBOgfh2b59SvTqy6KE4+yO8xlpCAQID6dWAeR7+6EW3RGXRi1dbIOx+Etxh3k4BEgPp1ZB5HvzqlFr1BF6uL4uhXeodxPwmIBKhfh4b6FTsIP3qT0bCEBPIIUL+OH/Ur9yKOfmU2LCGBLALUr8P3nPrVzepSv1lvMCaTgEyA+nVsnlO/OrHqojj3K7/HWEICAgHq14F5HP3qRrRFZ9CJVVsj73wQ3mLcTQISAerXkXkc/eqUWvQGXawuiqNf6R3G/SQgEqB+HRrqV+wgvPNBRsMSEsgjQP06ftSv3Is4+pXZsIQEsghQvw7fc+pXN6tL/Wa9wZhMAjIB6texeU796sSqi+Lcr/weYwkJCASoXwfmcfSrG9EWnUEnVm2NvPNBeItxNwlIBKhfR+Zx9KtTatEbdLG6qP6MfnfvqcuPmUpvE+4ngS4IUL+OKvUr96170+/EpC/Ur9wPWNIBAerXQaV+5a51b/odf6QuQ45+5W7Aki4IUL+O6nPqVzere2/6TR/BvlK/XSiGdcoEqF/H5jn1qxOrLqo/c7/Ur/xuZ0nPCFC/7oI8jn51I9qiE+rEqq2Rdz707K3Nw+k/AerXXaPH0a9OqUW/1MXqojj67f97nUfYOwLUr7sk1K/cMalfmQ1LSCCLAPXr8MkUZLh4Dp6BH9mv2cmHXCvRxVK/NWzcJIFLEZCVYEtG2mVmFtrQkRj7NROXX7MQy84LlNG/x9vzX83kuKFcg3O+l2byjS5oztZsDk28LtuWHzNsC7HlP2asiFout724byDn7oWc3Eu9H1nPUxFo0m/67evMfBwCC+WpTKnfpzIHT/YCBBr1O1QvxqhDh1LsRr5dfmOMXHhWoozerctlZxblunYFzpmvzWKOLmjOzkxCE6u2ZWrGbSG2XBe1WvXjK7s5I9ic3Au8FVnF8xFo0u9YjUOu5bwKJDZkYzlYtGsDzxioH0MeziEl45iz99W0/+nnc4uwY8PCmm7uVxfFOx8EyNxNAjIBWTxyyXltXcWGlpD6U2SK1V8clfYjqXAOR5Ue97Svoa1oZela1sXqoqjf9mvJCBKoEZDFI5fUqrCbXcWGlpD6saMpWsDqL3JQMVK/4Wp2+ZozgZCT2+U5se6HJSCLRy45h9FVbGgJqf9a+tV+Gyycw2CAZ+DK1o5V3VHpYnVRHP0erzPXSEBJQBabXHJedVexoSWk/mvpl6PfcHWKV37p+JQHt0iglYAsNrnkvNKuYkNLSP2PpV90xKwdqzqyulhdFEe/oa/ylQTUBGSxySXnlXcVG1pC6n8s/aJjbK0sHVldrC6K+g19la8koCYgi00uOa+8q9jQElI/9Ruotb3qxKqLon7baLOcBM4IyGKTS84q4Z0P50gie9CRrKsCzdHK0tWti9VFUb+OKBcSgAjIkpVLzhvoKja0hNR/rdEvOivLOx/C1ezyNefmsZzcLs+JdT8sAVlscsk5jK5iQ0tI/dfSLzouxUey7uzRVrRjVVe3LlYXxdGvI8qFBCACstjkkvMGuooNLSH1P5Z+0TG2VpaOrC5WF0X9hr7KVxJQE5DFJpecV95VbGgJqf+x9MvRb+gDutecCYScXN3RMYoETgjIYpNLTirwG13FhpaQ+qnfQK3tVTeu1UVx9NtGm+UkcEZAFptcclYJ73w4RxLZg45kXRVojlaWrm5drC6K+nVEuZAARECWrFxy3kBXsaElpP5rjX7RWVne+RCuZpevORMIObldnhPrflgCstjkknMYXcWGlpD6r6VfdFyKj2Td2aOtaMeqrm5drC6Ko19HlAsJqAi8/CvCSrHtv2sP6S5LFPV1FRuaRup/LP2iY2ytLB1ZXawuivoNfZWvJNBOYP3hBXwQ2345/KnlIMrrKjYcElL/Y+mXo9/QB3SvORMIObm6o2MUCRQEZvbn06yAvdisfM3ir0YGUV5XseGQkPqp30Ct7VU3rtVFcfTbRpvlJFAhMLW/YLt7t2Lbvw7tr9nWB7+d3c2AqbQ4YCwHi3Yt4Bn4rGxKBp6jlaU7a12sLor6dUS5kICSwK//AfEPM7E/PWzM4qWehiipq9hwTEj9KTLF6i+OCp2V5Z0P4Wp2+ZozgZCT2+U5se5HJOCGv+VyNviFRoSIvpDYgB3LwaJdG3gGPi5NycBztGNVd9a6WF0UR7+OKBcS0BIohr+FgM8Hv5CSEH0hseFUsBws2rWBZ+BiTMnAR8xaWbqz1sXqoqhfR5QLCagJrMux7/nML6YkRF9IbDgVLAeLdm3gGSkyRe9icEeG5mhl6erWxeqiqF9HlAsJqAkch7+RwS+kJERfSGw4FSwHi3Zt4Bm4GFMy8BytLN1Z62J1UdSvI8qFBPQEyuHv+cwvpiREX0hsOBUsB4t2beAZuBhTMvAcrSzdWetidVHUryPKhQT0BMLwNzb4hZSE6AuJDaeC5WDRrg08A5+VTcmgfkMP0L7m3L2Qk6s9PsaRQEngMPyNDX4hJSH6QmLDgWI5WLRrA8/AxZiSgedox6rurHWxuiiOfh1RLiQAECiGv9HBL6QkRF9IbDgVLAeLdm3gGbgYUzLwEbNWlu6sdbG6KOrXEeVCAggBP/yNDn4hJSH6QmLDqWA5WLRrA89IkSl6F4M7MjRHK0tXty5WF0X9OqJcSAAh8G7vPYsPfiElIfpCYsOpYDlYtGsDz8DFmJKB52hl6c5aF6uLon4dUS4kABHYRZ72UFSAKKmr2HAqSP0pMsXqL44KHZfiKnXtoK1oZenq1sXqoqhfR5QLCUAE3qXBLzQiRPSFxIZTwXKwaNcGnoHPyqZkUL+hB2hfc+5eyMnVHh/jSKBKYB2f+cWUhOgLiQ0HiuVg0a4NPAMXY0oGnqMdq7qz1sXqovoz+t29py4/ZuqwcCGBqxGY1Z/zG1pGlNRVbMqxpMgUOf5wTOi0AK5S1xL6XDWtLF3dulhdVH/0e/wmPb5G/bp+waUHBBAldRUbMCD1P5Z+UclrZenI6mJ1UX3R7/s6Z9mGDsdXErgtAUR5XcUGAkj91G+g1vaqE6suqi/6bTtnlpPAXRBAlNdVbACF1E/9Bmptrzqx6qKo3zbaLCcBgIBV3ki7/HYUG9pH6h+NsGjXBp4xGv0zm3B4ylc8A2/l23woj2Y00sXqokajJT+4At5dDCWBRgJv+CcXzHhqAvzgqvENxUIS0BP4G0/Ui/2pzk5iQ6VI/ZMJFu3awDNScq7RCtKGLlYX5Siu9J2LkSRAApci8DfcqavC5nGLarEcLNq1gBx/OFH0noS0G8/QVmbDeTjA1lddrHbut7U5BpAACdyaAC5H9MO0lBZwKqgYr6Nf/DzaMqjfNkIsJ4G7IZAy0sRysOhUcF9DdK4Tz7DKhltJPR8pTzdGlrK5nwRIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgARIgAS6I/C1XC7/XPV/dmW5d2tul19xG1xIgARI4CoEvryJrtJUTxqZGWO+3bEs7YqZubWVMWP3+uTLF/8KevIewNO/KoGv+cdV2+tDY/uFMT/uQOZOv1u39mGM/lfcXcJjLu+bVwr4MS8tz6p/BL6sgP7177C6PqK1MTvXxsTp1/2o8d6+Lrtu9R7q35khBXwPF4rHePcEnHzN8w1+B4OtPW87ynOTEMYs7Nqvff26++t5gRP4Z0FQwBcAySpIoJHAyP/Tu5gEbQx8vEJn25m3sB0HH9Y49euv884CoYAfr8vzjHpFYDS3E6B2ecbBb5hrmNoZB+tfO/lr/ybi1K/vn274axeOgHv1buXBPBSBkf2kv1j8HQAPdW6ak7FjvPnAfQL3Zech7OSvnQTm1G8Bzg9/KWBNL2IMCSQQeCvlazYJ6TdP+Xw5XT7hI/qx4zs34Tt287+L/ZvVjZ2M4GIJHIa/FDB7Awl0QKAiX3v/1ffJ4r6GcLJsa8tPfVnVlnl9ma5ry0dt2Qxry6S2FLMk1gfSgv8d4hzz92PMyg98Z9/WwRmkX94fadkcMXMKIqNXMJUEzgn8tNrs+Pbr6dqi5md/E9n5mTbs+bRn9s/+M/vVT/tu7b8G3O1nqYv7JO9Bl+FvKhTmkQAJnBH4O/Hv+nSwWhvKrlb1wW5tMLzdnoyV7cbr9/fp///qI8NZbfka1ZbTmYWXF3xu4eykz3bYr1m4GZg3/823qRWx//LFWZhux6w2nr/vzXHlbxJ+C0PXAxhFAloCVQH7z/vtja92cX8Wa37zsf8oZr/drMXITjxY4XDq93DBX47/OtrYfxxwIQESuCyBl3IEvHjSLxvY2V67+G8eD92a++4FF0fgx+FwC+XLDkEC3RB4+fFfuH3a213/vGH89639QHjdDeb7q/XvMPilfO/v2vGI74fAy7YQ8JMOf/2Y98VdLj8Qzpn6vZ9rrjjSH//3EuWrQMUQEsggUAj4Sb/t5ca8xR0TfiDMD/iLjuQHv5RvxruKqSSgJPDpRsDPOfz9t1uvD190m9sbkzn1W3QZO/ilfJXvHoaRQCaB/Xb8pMPfTHCPmf6yoHwf88ryrPpJ4HNrb37lQgKOwCtvNWNHIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIAESIIGuCPwH9j3d4Kg1fY0AAAAASUVORK5CYII=" - } - }, "cell_type": "markdown", "metadata": {}, "source": [ - "![MVA-1.png](attachment:MVA-1.png)" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "Based on the above block diagram we find that `PE` & `SIMD` parallelization attributes are subject to the following constraints. \n", - "If `W` is the width of the input and `H` is the height of the output in a Matrix-Vector Computation then:\n", + "In the case of the MVAU, `PE` & `SIMD` are subject to the following constraints: \n", + "\n", + "If `MW` is the number of input features and `MH` the number of output features:\n", "\n", - " W % SIMD == 0\n", - " H % PE == 0\n", + " MW % SIMD == 0\n", + " MH % PE == 0\n", " \n", - "For the above example, H = 12 and W = 12. The demonstrated PE & SIMD values adhere to the above constraints.\n", + "Total folding in the case of the MVAU is defined as:\n", "\n", - "We also define a term referred to as total folding which is defined as :\n", + " Total folding = (MH/PE) x (MW/SIMD)\n", "\n", - " Total folding = (H/PE) x (W/SIMD)\n", + "In a streaming dataflow architecture like it is in FINN designs the throughput is determined by the slowest layer. So, the goal of adjusting these parameters is to get an almost balanced pipeline i.e. equalizing the throughput rate of layers in the generated dataflow architecture.\n", "\n", - "The goal of adjusting these parameters is to get an almost balanced pipeline i.e. equalling the rate of producers and consumers in the generated dataflow architecture.\n", - "This can be achieved (or almost achieved) by keeping the `total folding` parameter approximately constant across all layers.\n", + "The FINN compiler provides analysis passes to facilitate the exploration of the folding factors of each layer. In this notebook we will show how to use these functions and explore how the parallelization parameters affect the clock cycles and the resource utilization of the generated dataflow architecture.\n", "\n", - "We now explore how these parameters affect the estimated clock cycles and the resource utilization of the generated dataflow architectures.\n", - "We start with a naive case where `PE` & `SIMD` values across all layers are 1 and observe the above-mentioned numbers.\n", - "We define the utility functions (`exp_cycles_per_layer()`) and (`res_estimation()`) to estimate the number of clock cycles and resource utilization of each network layer." - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "
    \n", - "Should this line be added (The `exp_cycles_per_layer` formula is equal to the total folding in this case as the number of input vectors is 1 and the mmv value is also 1).\n", - "
    " + "We start with a naive case where `PE` & `SIMD` values across all layers are 1, this is the starting point of our exploration and is also the state the network is in after the conversion to HLS layers. If you take a look at the model using Netron and click on one of the MVAU layers, you can see that `PE` and `SIMD` are both set to 1 by default." ] }, { "cell_type": "code", "execution_count": 3, "metadata": {}, - "outputs": [], - "source": [ - "from finn.analysis.fpgadataflow.exp_cycles_per_layer import exp_cycles_per_layer\n", - "from finn.analysis.fpgadataflow.res_estimation import res_estimation" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "We now individually extract the `MatrixVectorActivation` blocks from the onnx file and set the config values manually (although this can be done automatically by Vivado tools also as mentioned in the introduction).\n", - "\n", - "In the first step, we set the `PE` & `SIMD` values for all the layers to be '1' to establish a baseline and measure the estimated clock cycles and resource utilization for each of the individual layers.\n", - "\n", - "We utilize from (`getCustomOp()`) as the helper function to set different properties of the node. The (`set_nodeattr()`) function within this function call helps us set these values." - ] - }, - { - "cell_type": "code", - "execution_count": 4, - "metadata": {}, - "outputs": [], - "source": [ - "from qonnx.custom_op.registry import getCustomOp\n", - "fc_layers = model.get_nodes_by_op_type(\"MatrixVectorActivation\")\n", - "# (PE, SIMD, in_fifo_depth, out_fifo_depth, ramstyle) for each layer\n", - "config = [\n", - " (1, 1, [16], [64], \"block\"),\n", - " (1, 1, [64], [64], \"auto\"),#8,8\n", - " (1, 1, [64], [64], \"auto\"),#8,8\n", - " (1, 1, [64], [1], \"distributed\"),\n", - "]\n", - "for fcl, (pe, simd, ififo, ofifo, ramstyle) in zip(fc_layers, config):\n", - " fcl_inst = getCustomOp(fcl)\n", - " fcl_inst.set_nodeattr(\"PE\", pe)\n", - " fcl_inst.set_nodeattr(\"SIMD\", simd)\n", - " fcl_inst.set_nodeattr(\"inFIFODepths\", ififo)\n", - " fcl_inst.set_nodeattr(\"outFIFODepths\", ofifo)\n", - " fcl_inst.set_nodeattr(\"ram_style\", ramstyle)" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "After setting these parameters, we save the model and view it using `Netron`\n", - ". We can observe the values we set in the above step by clicking on any of the nodes and observing their properties." - ] - }, - { - "cell_type": "code", - "execution_count": 10, - "metadata": {}, "outputs": [ { "name": "stdout", "output_type": "stream", "text": [ - "Stopping http://0.0.0.0:5901\n", - "Serving './cybsec_PE_SIMD_not_modified.onnx' at http://0.0.0.0:5901\n" + "Stopping http://0.0.0.0:5920\n", + "Serving 'step_convert_to_hls.onnx' at http://0.0.0.0:5920\n" ] }, { @@ -258,7 +178,7 @@ " " + "" ] }, - "execution_count": 10, + "execution_count": 3, "metadata": {}, "output_type": "execute_result" } ], "source": [ - "model.save(\"./cybsec_PE_SIMD_not_modified.onnx\")\n", - "showInNetron(\"./cybsec_PE_SIMD_not_modified.onnx\",localhost_url='xirxlabs53')" + "showInNetron(\"step_convert_to_hls.onnx\")" ] }, { "cell_type": "markdown", "metadata": {}, "source": [ - "We pass our model to the `exp_cycles_per_layer()` and `res_estimation()` functions which iteratively go through all the layers in the graph and measure the expected execution clock cycles and resource utilization for each of them and return a dictionary with calculated values." + "We import the analysis passes (`exp_cycles_per_layer()`) and (`res_estimation()`) to estimate the number of clock cycles and resource utilization of each network layer." ] }, { "cell_type": "code", - "execution_count": 6, + "execution_count": 4, "metadata": {}, "outputs": [], "source": [ - "cycles_dict = []\n", - "cycles_dict = exp_cycles_per_layer(model)" + "from finn.analysis.fpgadataflow.exp_cycles_per_layer import exp_cycles_per_layer\n", + "from finn.analysis.fpgadataflow.res_estimation import res_estimation" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "Analysis passes in FINN return information about the model in form of a dictionary, you can learn more about analysis passes in general in this Jupyter notebook: [0_custom_analysis_pass.ipynb](0_custom_analysis_pass.ipynb).\n", + "\n", + "We start by calling the analysis pass `exp_cycles_per_layer()`, which returns a dictionary with the layer names as keys and the expected cycles as values. Afterwards, we plot the result in a block diagram." + ] + }, + { + "cell_type": "code", + "execution_count": 5, + "metadata": {}, + "outputs": [ + { + "data": { + "text/plain": [ + "{'MatrixVectorActivation_0': 38400,\n", + " 'MatrixVectorActivation_1': 4096,\n", + " 'MatrixVectorActivation_2': 4096,\n", + " 'MatrixVectorActivation_3': 64}" + ] + }, + "execution_count": 5, + "metadata": {}, + "output_type": "execute_result" + } + ], + "source": [ + "cycles_dict = model.analysis(exp_cycles_per_layer)\n", + "cycles_dict" ] }, { @@ -303,7 +255,7 @@ "outputs": [ { "data": { - "image/png": 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tuq62b98+GWP06quv6tVXX82xz/Hjx1WxYkW9/vrr6ty5s+655x7VrVtXbdu2Vc+ePVWvXr08bVO6/JCV8+fPX/M7yMzM1OHDh1WnTh2rPacnzuZk79692rVr1w1/e1Lufuf79++XpFz9DipVqpQt8JUoUUJbt27NVe1Xj9ms5c+cOSPp8nFLTEzUJ598ok8++STHdVy5f9fSvHlz63LktWvXqnz58mrQoIHq16+vtWvX6qGHHtK6dev0xBNPWMv8+eefqlChgjw9Pe3WlXV5eNa4ynK972v8+PE6d+6cli1bdkvv6Lxw4YLGjx+vmTNn6siRI3b3/l35RygfHx916tRJs2fP1htvvCHp8iWZFStWtEL/zRzb3P4mAdwZhDsABULZsmUVFxenFStWaNmyZVq2bJlmzpypXr166Ysvvrjp9V7rLMe12rP+w2j//v1q3bq1atWqpQ8++EB+fn5yc3PT0qVLNXHixGwPRMlJZmamHnroIY0YMSLH+ffcc08u9+Lv49FHH9WXX36pDz/80O4hJ/mhV69eeu+997R48WJ1795ds2fPVseOHW8Ysm8k67t86aWXFBoammOfrFd2tGjRQvv379c333yjH374QZ999pkmTpyoGTNmqH///rdUR27k9gxJZmamAgIC9MEHH+Q4P+uPG/nxO7/ajcbWrS6fVdPTTz99zftScxO277//fqWnpys2NlZr16617slr3ry51q5dq927d+vEiRNW+8243vcVGhqq5cuXa8KECWrVqlW2M6K5NWTIEM2cOVNDhw5VcHCwvL29ZbPZ1K1bt2zfX69evTR//nytX79eAQEB+vbbb/Xcc89ZT7e8mWPLWTugYCHcASgw3Nzc1KlTJ3Xq1EmZmZl67rnn9PHHH+vVV19VjRo1rnlZ3e3w3XffKTU1Vd9++63dmYQrL2fLcq26qlevrnPnzikkJOS626pcubKio6N17tw5u7N3N3rC5JXb2b59e676XrnNa21j9+7dKl26tIoXL66iRYvKy8sr1+sfMmSIatSooTFjxsjb21ujRo3Kt/rr1q2re++9V7NmzVKlSpV06NAhffTRRze1ritlXRJZuHDhG35XklSyZEn16dNHffr0sR62MW7cuDyHuzJlyqhYsWLX/A5cXFyynWHOrerVq2vLli1q3br1dcdNbn/nWZdJbt++PU/vprwdypQpI09PT2VkZNzw+7revjdp0kRubm5au3at1q5dq+HDh0u6HOA//fRTRUdHW5+zVK5cWT/++KPOnj1rd/Zu9+7d1vzcatq0qQYOHKiOHTvq8ccf16JFi1SoUN7/s2zBggUKCwvT+++/b7VdvHgxx6fttm3bVmXKlNGsWbMUFBSk8+fPq2fPntb8vBxbAAUT99wBKBBOnTpl99nFxcX6C3HWo9uz3umVl1cE3KysswdXX+I0c+bMbH2LFy+eY01PPPGEYmNjtWLFimzzEhMTrfv72rdvr0uXLtk9fj4jIyNbcLmWrl27asuWLVq0aFG2edc6W1K+fHkFBgbqiy++sKt9+/bt+uGHH9S+fXtJl7+HLl266LvvvtNvv/2Wq/W/+uqreumllzR69OhrPlL/Zuvv2bOnfvjhB02aNEmlSpXK9vTFmzkWZcuWVatWrfTxxx/r2LFj2eZnvaNOyv479fDwUI0aNbK9XiA3XF1d1aZNG33zzTd2j61PSEjQ7Nmzdf/998vLyyvP65Uu//aOHDmiTz/9NNu8CxcuWE/azO3vvE2bNvL09NT48eN18eJFu3m5PSOXX1xdXdW1a1ctXLgwxyB/5fd1vX8zihQposaNG+urr77SoUOH7M7cXbhwQZMnT1b16tVVvnx5a5n27dsrIyNDU6ZMsVvXxIkTZbPZcvU00CuFhIRozpw5Wr58uXr27HnTZ0qv/g4++ugjZWRkZOtbqFAhde/eXfPmzVNkZKQCAgLszsTl5dgCKJg4cwfgjli2bJn11+0r3XfffapWrZr69++v06dP68EHH1SlSpX0559/6qOPPlJgYKB1P0tgYKBcXV317rvvKikpSe7u7tb7ufJbmzZtrDOJzz77rM6dO6dPP/1UZcuWzRYAGjZsqOnTp+vNN99UjRo1VLZsWT344IMaPny4vv32W3Xs2FG9e/dWw4YNlZKSom3btmnBggU6ePCgSpcurU6dOqlZs2YaNWqUDh48KH9/f3399de5emiLdPndaQsWLNDjjz+uvn37qmHDhjp9+rS+/fZbzZgxQ/Xr189xuffee0/t2rVTcHCw+vXrZ70KwdvbW+PGjbP6vf322/rhhx/UsmVL67H6x44d0/z587Vu3bocX8z93nvvKSkpSeHh4fL09LR7wMat1P/UU09pxIgRWrRokQYNGmT3sJxbORZTp07V/fffr4CAAA0YMEDVqlVTQkKCYmNj9ddff2nLli2SJH9/f7Vq1UoNGzZUyZIl9dtvv2nBggUaPHjwNffvet58801FRUXp/vvv13PPPadChQrp448/Vmpqaq7fDZeTnj17at68eRo4cKBWrVqlZs2aKSMjQ7t379a8efO0YsUKNWrUKNe/cy8vL02cOFH9+/dX48aN9dRTT6lEiRLasmWLzp8/f0uXTt+Md955R6tWrVJQUJAGDBggf39/nT59Wps2bdKPP/6o06dPS7p8xtHHx0czZsyQp6enihcvrqCgIOs+sebNm+udd96Rt7e3AgICJF0O+zVr1tSePXvUu3dvu+126tRJDzzwgF5++WUdPHhQ9evX1w8//KBvvvlGQ4cOve4rP66lS5cu1iXoXl5e+vjjj/O0fMeOHfXf//5X3t7e8vf3V2xsrH788Ufr3uGr9erVS5MnT9aqVaus185cKbfHFkABdWcfzgngn+Z6r0LQFY8oX7BggWnTpo0pW7ascXNzM3fddZd59tlnzbFjx+zW9+mnn5pq1aoZV1dXu9ciXOtVCPPnz8+xnqsf6z927FgjyZw4ccJq+/bbb029evVMkSJFTJUqVcy7775rPv/8cyPJHDhwwOoXHx9vOnToYDw9PY0kuzrOnj1rRo8ebWrUqGHc3NxM6dKlzX333Wf+/e9/272i4dSpU6Znz57Gy8vLeHt7m549e5rNmzfn6lUIWcsPHjzYVKxY0bi5uZlKlSqZsLAw63HmOT3+3xhjfvzxR9OsWTNTtGhR4+XlZTp16mR27tyZbf1//vmn6dWrlylTpoxxd3c31apVM+Hh4SY1NfWaxzUjI8N0797dFCpUyCxevPiW6r9S+/btjSSzfv36fD0W+/fvN7169TK+vr6mcOHCpmLFiqZjx45mwYIFVp8333zTNGnSxPj4+JiiRYuaWrVqmbfeesvuu8zJtV6FYIwxmzZtMqGhocbDw8MUK1bMPPDAA9n27Vq/2+tJS0sz7777rqlTp45xd3c3JUqUMA0bNjSvvfaaSUpKsvrl9nee1fe+++6zfi9NmjQxX331lTW/ZcuWpk6dOtlqCQsLy/aqkZxIMuHh4dnaK1eubPe4fmOMSUhIMOHh4cbPz88ULlzY+Pr6mtatW5tPPvnErt8333xj/P39TaFChbJ970uWLDGSsr0apX///kaS+c9//pOtlrNnz5phw4aZChUqmMKFC5u7777bvPfee3avhLjevlzrtzBt2jQjybz00ks5Hpsr13vlqxDOnDlj+vTpY0qXLm08PDxMaGio2b17d47HLEudOnWMi4uL+euvv3Kcn5tje61/YwE4ls2YO3w9BQAAt+CRRx7Rtm3btG/fPkeXAvwt3XvvvSpZsqR1XyEA58E9dwCAv41jx45pyZIldg+BAJB7v/32m+Li4tSrVy9HlwLgNuDMHQCgwDtw4IB++uknffbZZ9qwYYP279+f6/foAbj8sKSNGzfq/fff18mTJ/XHH3/c9OsXABRcnLkDABR4MTEx6tmzpw4cOKAvvviCYAfk0YIFC9SnTx+lp6frq6++ItgBToozdwAAAADgBDhzBwAAAABOgHAHAAAAAE6gwLzE/J133tHo0aP1wgsvaNKkSZKkixcv6sUXX9ScOXOUmpqq0NBQTZs2TeXKlbOWO3TokAYNGqRVq1bJw8NDYWFhGj9+vAoV+t+urV69WhEREdqxY4f8/Pz0yiuvZHsx6dSpU/Xee+8pPj5e9evX10cffaQmTZrkuv7MzEwdPXpUnp6estlst3QsAAAAAPx9GWN09uxZVahQQS4ud/B8mgPfsWf59ddfTZUqVUy9evXMCy+8YLUPHDjQ+Pn5mejoaPPbb7+Zpk2bmvvuu8+af+nSJVO3bl0TEhJiNm/ebJYuXWpKly5tRo8ebfX5448/TLFixUxERITZuXOn+eijj4yrq6tZvny51WfOnDnGzc3NfP7552bHjh1mwIABxsfHxyQkJOR6Hw4fPnzdFzUzMTExMTExMTExMf2zpsOHD99aUMojhz9Q5dy5c2rQoIGmTZumN998U4GBgZo0aZKSkpJUpkwZzZ49W4899pgkaffu3apdu7ZiY2PVtGlTLVu2TB07dtTRo0ets3kzZszQyJEjdeLECbm5uWnkyJFasmSJtm/fbm2zW7duSkxM1PLlyyVJQUFBaty4saZMmSLp8lk4Pz8/DRkyRKNGjcrVfiQlJcnHx0eHDx+Wl5dXfh4iAAAAAH8jycnJ8vPzU2Jiory9ve/Ydh1+WWZ4eLg6dOigkJAQvfnmm1b7xo0blZ6erpCQEKutVq1auuuuu6xwFxsbq4CAALvLNENDQzVo0CDt2LFD9957r2JjY+3WkdVn6NChkqS0tDRt3LhRo0ePtua7uLgoJCREsbGx16w7NTVVqamp1uezZ89Kkry8vAh3AAAAAO747VoODXdz5szRpk2btGHDhmzz4uPj5ebmJh8fH7v2cuXKKT4+3upzZbDLmp8173p9kpOTdeHCBZ05c0YZGRk59tm9e/c1ax8/frxee+213O0oAAAAANxmDnta5uHDh/XCCy9o1qxZf8sXaY4ePVpJSUnWdPjwYUeXBAAAAOAfzGHhbuPGjTp+/LgaNGigQoUKqVChQoqJidHkyZNVqFAhlStXTmlpaUpMTLRbLiEhQb6+vpIkX19fJSQkZJufNe96fby8vFS0aFGVLl1arq6uOfbJWkdO3N3drUswuRQTAAAAgKM5LNy1bt1a27ZtU1xcnDU1atRIPXr0sP534cKFFR0dbS2zZ88eHTp0SMHBwZKk4OBgbdu2TcePH7f6REVFycvLS/7+/lafK9eR1SdrHW5ubmrYsKFdn8zMTEVHR1t9AAAAAKCgc9g9d56enqpbt65dW/HixVWqVCmrvV+/foqIiFDJkiXl5eWlIUOGKDg4WE2bNpUktWnTRv7+/urZs6cmTJig+Ph4vfLKKwoPD5e7u7skaeDAgZoyZYpGjBihvn37auXKlZo3b56WLFlibTciIkJhYWFq1KiRmjRpokmTJiklJUV9+vS5Q0cDAAAAAG6Nw5+WeT0TJ06Ui4uLunbtavcS8yyurq76/vvvNWjQIAUHB6t48eIKCwvT66+/bvWpWrWqlixZomHDhunDDz9UpUqV9Nlnnyk0NNTq8+STT+rEiRMaM2aM4uPjFRgYqOXLl2d7yAoAAAAAFFQOf8+ds0hOTpa3t7eSkpK4/w4AAAD4B3NUNnDYPXcAAAAAgPxDuAMAAAAAJ0C4AwAAAAAnQLgDAAAAACdAuAMAAAAAJ0C4AwAAAAAnQLgDAAAAACdAuAMAAAAAJ1DI0QXg9rDZHF2BYxnj6AoAAACAO4szdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBBwa7qZPn6569erJy8tLXl5eCg4O1rJly6z5rVq1ks1ms5sGDhxot45Dhw6pQ4cOKlasmMqWLavhw4fr0qVLdn1Wr16tBg0ayN3dXTVq1FBkZGS2WqZOnaoqVaqoSJEiCgoK0q+//npb9hkAAAAAbgeHhrtKlSrpnXfe0caNG/Xbb7/pwQcfVOfOnbVjxw6rz4ABA3Ts2DFrmjBhgjUvIyNDHTp0UFpamtavX68vvvhCkZGRGjNmjNXnwIED6tChgx544AHFxcVp6NCh6t+/v1asWGH1mTt3riIiIjR27Fht2rRJ9evXV2hoqI4fP35nDgQAAAAA3CKbMcY4uogrlSxZUu+995769eunVq1aKTAwUJMmTcqx77Jly9SxY0cdPXpU5cqVkyTNmDFDI0eO1IkTJ+Tm5qaRI0dqyZIl2r59u7Vct27dlJiYqOXLl0uSgoKC1LhxY02ZMkWSlJmZKT8/Pw0ZMkSjRo3KcdupqalKTU21PicnJ8vPz09JSUny8vLKj0NxS2w2R1fgWAXrVw0AAIB/kuTkZHl7e9/xbFBg7rnLyMjQnDlzlJKSouDgYKt91qxZKl26tOrWravRo0fr/Pnz1rzY2FgFBARYwU6SQkNDlZycbJ39i42NVUhIiN22QkNDFRsbK0lKS0vTxo0b7fq4uLgoJCTE6pOT8ePHy9vb25r8/Pxu7QAAAAAAwC0o5OgCtm3bpuDgYF28eFEeHh5atGiR/P39JUlPPfWUKleurAoVKmjr1q0aOXKk9uzZo6+//lqSFB8fbxfsJFmf4+Pjr9snOTlZFy5c0JkzZ5SRkZFjn927d1+z7tGjRysiIsL6nHXmDgAAAAAcweHhrmbNmoqLi1NSUpIWLFigsLAwxcTEyN/fX88884zVLyAgQOXLl1fr1q21f/9+Va9e3YFVS+7u7nJ3d3doDQAAAACQxeGXZbq5ualGjRpq2LChxo8fr/r16+vDDz/MsW9QUJAkad++fZIkX19fJSQk2PXJ+uzr63vdPl5eXipatKhKly4tV1fXHPtkrQMAAAAACjqHh7urZWZm2j2o5EpxcXGSpPLly0uSgoODtW3bNrunWkZFRcnLy8u6tDM4OFjR0dF264mKirLu63Nzc1PDhg3t+mRmZio6Otru3j8AAAAAKMgcelnm6NGj1a5dO9111106e/asZs+erdWrV2vFihXav3+/Zs+erfbt26tUqVLaunWrhg0bphYtWqhevXqSpDZt2sjf3189e/bUhAkTFB8fr1deeUXh4eHWJZMDBw7UlClTNGLECPXt21crV67UvHnztGTJEquOiIgIhYWFqVGjRmrSpIkmTZqklJQU9enTxyHHBQAAAADyyqHh7vjx4+rVq5eOHTsmb29v1atXTytWrNBDDz2kw4cP68cff7SClp+fn7p27apXXnnFWt7V1VXff/+9Bg0apODgYBUvXlxhYWF6/fXXrT5Vq1bVkiVLNGzYMH344YeqVKmSPvvsM4WGhlp9nnzySZ04cUJjxoxRfHy8AgMDtXz58mwPWQEAAACAgqrAvefu78pR77K4Ft5z5+gKAAAA8E/1j3/PHQAAAADg5hHuAAAAAMAJEO4AAAAAwAkQ7gAAAADACRDuAAAAAMAJEO4AAAAAwAkQ7gAAAADACRDuAAAAAMAJEO4AAAAAwAkQ7gAAAADACRDuAAAAAMAJEO4AAAAAwAkQ7gAAAADACRDuAAAAAMAJEO4AAAAAwAkQ7gAAAADACRDuAAAAAMAJEO4AAAAAwAkQ7gAAAADACRDuAAAAAMAJEO4AAAAAwAkQ7gAAAADACRDuAAAAAMAJEO4AAAAAwAkQ7gAAAADACRDuAAAAAMAJEO4AAAAAwAkQ7gAAAADACRDuAAAAAMAJEO4AAAAAwAkQ7gAAAADACRDuAAAAAMAJEO4AAAAAwAkQ7gAAAADACRDuAAAAAMAJEO4AAAAAwAk4NNxNnz5d9erVk5eXl7y8vBQcHKxly5ZZ8y9evKjw8HCVKlVKHh4e6tq1qxISEuzWcejQIXXo0EHFihVT2bJlNXz4cF26dMmuz+rVq9WgQQO5u7urRo0aioyMzFbL1KlTVaVKFRUpUkRBQUH69ddfb8s+AwAAAMDt4NBwV6lSJb3zzjvauHGjfvvtNz344IPq3LmzduzYIUkaNmyYvvvuO82fP18xMTE6evSoHn30UWv5jIwMdejQQWlpaVq/fr2++OILRUZGasyYMVafAwcOqEOHDnrggQcUFxenoUOHqn///lqxYoXVZ+7cuYqIiNDYsWO1adMm1a9fX6GhoTp+/PidOxgAAAAAcAtsxhjj6CKuVLJkSb333nt67LHHVKZMGc2ePVuPPfaYJGn37t2qXbu2YmNj1bRpUy1btkwdO3bU0aNHVa5cOUnSjBkzNHLkSJ04cUJubm4aOXKklixZou3bt1vb6NatmxITE7V8+XJJUlBQkBo3bqwpU6ZIkjIzM+Xn56chQ4Zo1KhRuao7OTlZ3t7eSkpKkpeXV34ekptiszm6AscqWL9qAAAA/JM4KhsUmHvuMjIyNGfOHKWkpCg4OFgbN25Uenq6QkJCrD61atXSXXfdpdjYWElSbGysAgICrGAnSaGhoUpOTrbO/sXGxtqtI6tP1jrS0tK0ceNGuz4uLi4KCQmx+uQkNTVVycnJdhMAAAAAOIrDw922bdvk4eEhd3d3DRw4UIsWLZK/v7/i4+Pl5uYmHx8fu/7lypVTfHy8JCk+Pt4u2GXNz5p3vT7Jycm6cOGCTp48qYyMjBz7ZK0jJ+PHj5e3t7c1+fn53dT+AwAAAEB+cHi4q1mzpuLi4vTLL79o0KBBCgsL086dOx1d1g2NHj1aSUlJ1nT48GFHlwQAAADgH6yQowtwc3NTjRo1JEkNGzbUhg0b9OGHH+rJJ59UWlqaEhMT7c7eJSQkyNfXV5Lk6+ub7amWWU/TvLLP1U/YTEhIkJeXl4oWLSpXV1e5urrm2CdrHTlxd3eXu7v7ze00AAAAAOQzh5+5u1pmZqZSU1PVsGFDFS5cWNHR0da8PXv26NChQwoODpYkBQcHa9u2bXZPtYyKipKXl5f8/f2tPleuI6tP1jrc3NzUsGFDuz6ZmZmKjo62+gAAAABAQefQM3ejR49Wu3btdNddd+ns2bOaPXu2Vq9erRUrVsjb21v9+vVTRESESpYsKS8vLw0ZMkTBwcFq2rSpJKlNmzby9/dXz549NWHCBMXHx+uVV15ReHi4dVZt4MCBmjJlikaMGKG+fftq5cqVmjdvnpYsWWLVERERobCwMDVq1EhNmjTRpEmTlJKSoj59+jjkuAAAAABAXjk03B0/fly9evXSsWPH5O3trXr16mnFihV66KGHJEkTJ06Ui4uLunbtqtTUVIWGhmratGnW8q6urvr+++81aNAgBQcHq3jx4goLC9Prr79u9alataqWLFmiYcOG6cMPP1SlSpX02WefKTQ01Orz5JNP6sSJExozZozi4+MVGBio5cuXZ3vICgAAAAAUVAXuPXd/V7znrmDhVw0AAABH+ce/5w4AAAAAcPMIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQcGu7Gjx+vxo0by9PTU2XLllWXLl20Z88euz6tWrWSzWazmwYOHGjX59ChQ+rQoYOKFSumsmXLavjw4bp06ZJdn9WrV6tBgwZyd3dXjRo1FBkZma2eqVOnqkqVKipSpIiCgoL066+/5vs+AwAAAMDt4NBwFxMTo/DwcP3888+KiopSenq62rRpo5SUFLt+AwYM0LFjx6xpwoQJ1ryMjAx16NBBaWlpWr9+vb744gtFRkZqzJgxVp8DBw6oQ4cOeuCBBxQXF6ehQ4eqf//+WrFihdVn7ty5ioiI0NixY7Vp0ybVr19foaGhOn78+O0/EAAAAABwi2zGGOPoIrKcOHFCZcuWVUxMjFq0aCHp8pm7wMBATZo0Kcdlli1bpo4dO+ro0aMqV66cJGnGjBkaOXKkTpw4ITc3N40cOVJLlizR9u3breW6deumxMRELV++XJIUFBSkxo0ba8qUKZKkzMxM+fn5aciQIRo1atQNa09OTpa3t7eSkpLk5eV1K4chX9hsjq7AsQrOrxoAAAD/NI7KBgXqnrukpCRJUsmSJe3aZ82apdKlS6tu3boaPXq0zp8/b82LjY1VQECAFewkKTQ0VMnJydqxY4fVJyQkxG6doaGhio2NlSSlpaVp48aNdn1cXFwUEhJi9blaamqqkpOT7SYAAAAAcJRCji4gS2ZmpoYOHapmzZqpbt26VvtTTz2lypUrq0KFCtq6datGjhypPXv26Ouvv5YkxcfH2wU7Sdbn+Pj46/ZJTk7WhQsXdObMGWVkZOTYZ/fu3TnWO378eL322mu3ttMAAAAAkE8KTLgLDw/X9u3btW7dOrv2Z555xvrfAQEBKl++vFq3bq39+/erevXqd7pMy+jRoxUREWF9Tk5Olp+fn8PqAQAAAPDPViDC3eDBg/X9999rzZo1qlSp0nX7BgUFSZL27dun6tWry9fXN9tTLRMSEiRJvr6+1v/Naruyj5eXl4oWLSpXV1e5urrm2CdrHVdzd3eXu7t77ncSAAAAAG4jh95zZ4zR4MGDtWjRIq1cuVJVq1a94TJxcXGSpPLly0uSgoODtW3bNrunWkZFRcnLy0v+/v5Wn+joaLv1REVFKTg4WJLk5uamhg0b2vXJzMxUdHS01QcAAAAACjKHnrkLDw/X7Nmz9c0338jT09O6R87b21tFixbV/v37NXv2bLVv316lSpXS1q1bNWzYMLVo0UL16tWTJLVp00b+/v7q2bOnJkyYoPj4eL3yyisKDw+3zqwNHDhQU6ZM0YgRI9S3b1+tXLlS8+bN05IlS6xaIiIiFBYWpkaNGqlJkyaaNGmSUlJS1KdPnzt/YAAAAAAgj/L8KoRNmzapcOHCCggIkCR98803mjlzpvz9/TVu3Di5ubnlfuPXeF7/zJkz1bt3bx0+fFhPP/20tm/frpSUFPn5+emRRx7RK6+8YvdI0T///FODBg3S6tWrVbx4cYWFhemdd95RoUL/y66rV6/WsGHDtHPnTlWqVEmvvvqqevfubbfdKVOm6L333lN8fLwCAwM1efJk6zLQG+FVCAULr0IAAACAozgqG+Q53DVu3FijRo1S165d9ccff6hOnTp65JFHtGHDBnXo0OGa76NzdoS7goVwBwAAAEf527zn7vfff1dgYKAkaf78+WrRooVmz56tyMhILVy4ML/rAwAAAADkQp7DnTFGmZmZkqQff/xR7du3lyT5+fnp5MmT+VsdAAAAACBX8hzuGjVqpDfffFP//e9/FRMTow4dOkiSDhw4kO0l4AAAAACAOyPP4W7SpEnatGmTBg8erJdfflk1atSQJC1YsED33XdfvhcIAAAAALixPD9Q5VouXrwoV1dXFS5cOD9W97fDA1UKFh6oAgAAAEf52zxQRZISExP12WefafTo0Tp9+rQkaefOnXYvEgcAAAAA3Dl5fon51q1b1bp1a/n4+OjgwYMaMGCASpYsqa+//lqHDh3Sl19+eTvqBAAAAABcR57P3EVERKhPnz7au3evihQpYrW3b99ea9asydfiAAAAAAC5k+dwt2HDBj377LPZ2itWrKj4+Ph8KQoAAAAAkDd5Dnfu7u5KTk7O1v7777+rTJky+VIUAAAAACBv8hzuHn74Yb3++utKT0+XJNlsNh06dEgjR45U165d871AAAAAAMCN5Tncvf/++zp37pzKli2rCxcuqGXLlqpRo4Y8PT311ltv3Y4aAQAAAAA3kOenZXp7eysqKkrr1q3T1q1bde7cOTVo0EAhISG3oz4AAAAAQC7k20vM/+l4iXnBwq8aAAAAjuKobJCrM3eTJ0/O9Qqff/75my4GAAAAAHBzcnXmrmrVqrlbmc2mP/7445aL+jvizF3Bwpk7AAAAOEqBPnN34MCB210HAAAAAOAW5PlpmQAAAACAgifP4a5r16569913s7VPmDBBjz/+eL4UBQAAAADImzyHuzVr1qh9+/bZ2tu1a6c1a9bkS1EAAAAAgLzJc7g7d+6c3NzcsrUXLlxYycnJ+VIUAAAAACBv8hzuAgICNHfu3Gztc+bMkb+/f74UBQAAAADIm1w9LfNKr776qh599FHt379fDz74oCQpOjpaX331lebPn5/vBQIAAAAAbizP4a5Tp05avHix3n77bS1YsEBFixZVvXr19OOPP6ply5a3o0YAAAAAwA3k6iXmuDFeYl6w8KsGAACAozgqG+T5nruwsDCeigkAAAAABUyew11SUpJCQkJ099136+2339aRI0duR10AAAAAgDzIc7hbvHixjhw5okGDBmnu3LmqUqWK2rVrpwULFig9Pf121AgAAAAAuIE8hztJKlOmjCIiIrRlyxb98ssvqlGjhnr27KkKFSpo2LBh2rt3b37XCQAAAAC4jpsKd1mOHTumqKgoRUVFydXVVe3bt9e2bdvk7++viRMn5leNAAAAAIAbyHO4S09P18KFC9WxY0dVrlxZ8+fP19ChQ3X06FF98cUX+vHHHzVv3jy9/vrrt6NeAAAAAEAO8vyeu/LlyyszM1Pdu3fXr7/+qsDAwGx9HnjgAfn4+ORDeQAAAACA3MhzuJs4caIef/xxFSlS5Jp9fHx8dODAgVsqDAAAAACQe7m+LDMjI0Nbt27VY489li3YnT9/Xlu3blVmZma+FwgAAAAAuLFch7v//ve/6tu3r9zc3LLNc3NzU9++fTV79ux8LQ4AAAAAkDu5Dnf/+c9/9NJLL8nV1TXbvEKFCmnEiBH65JNP8rU4AAAAAEDu5Drc7dmzR02bNr3m/MaNG2vXrl35UhQAAAAAIG9yHe5SUlKUnJx8zflnz57V+fPn87Tx8ePHq3HjxvL09FTZsmXVpUsX7dmzx67PxYsXFR4erlKlSsnDw0Ndu3ZVQkKCXZ9Dhw6pQ4cOKlasmMqWLavhw4fr0qVLdn1Wr16tBg0ayN3dXTVq1FBkZGS2eqZOnaoqVaqoSJEiCgoK0q+//pqn/QEAAAAAR8l1uLv77ru1fv36a85ft26d7r777jxtPCYmRuHh4fr5558VFRWl9PR0tWnTRikpKVafYcOG6bvvvtP8+fMVExOjo0eP6tFHH7XmZ2RkqEOHDkpLS9P69ev1xRdfKDIyUmPGjLH6HDhwQB06dNADDzyguLg4DR06VP3799eKFSusPnPnzlVERITGjh2rTZs2qX79+goNDdXx48fztE8AAAAA4BAml959911TqlQps2XLlmzz4uLiTKlSpcy7776b29Xl6Pjx40aSiYmJMcYYk5iYaAoXLmzmz59v9dm1a5eRZGJjY40xxixdutS4uLiY+Ph4q8/06dONl5eXSU1NNcYYM2LECFOnTh27bT355JMmNDTU+tykSRMTHh5ufc7IyDAVKlQw48ePz1XtSUlJRpJJSkrK417fHtI/ewIAAAAcxVHZINdn7oYNG6aAgAA1bNhQ7dq107BhwzRs2DC1a9dOjRo1Ut26dTVs2LBbCppJSUmSpJIlS0qSNm7cqPT0dIWEhFh9atWqpbvuukuxsbGSpNjYWAUEBKhcuXJWn9DQUCUnJ2vHjh1WnyvXkdUnax1paWnauHGjXR8XFxeFhIRYfa6Wmpqq5ORkuwkAAAAAHCXX4a5w4cL64Ycf9NZbb+nYsWP65JNP9PHHH+vYsWN666239MMPP6hw4cI3XUhmZqaGDh2qZs2aqW7dupKk+Ph4ubm5ycfHx65vuXLlFB8fb/W5Mthlzc+ad70+ycnJunDhgk6ePKmMjIwc+2St42rjx4+Xt7e3Nfn5+d3cjgMAAABAPiiUl86FCxfWiBEjNGLEiHwvJDw8XNu3b9e6devyfd23w+jRoxUREWF9Tk5OJuABAAAAcJg8hbvbZfDgwfr++++1Zs0aVapUyWr39fVVWlqaEhMT7c7eJSQkyNfX1+pz9VMts56meWWfq5+wmZCQIC8vLxUtWlSurq5ydXXNsU/WOq7m7u4ud3f3m9thAAAAAMhnub4s83Ywxmjw4MFatGiRVq5cqapVq9rNb9iwoQoXLqzo6Girbc+ePTp06JCCg4MlScHBwdq2bZvdUy2joqLk5eUlf39/q8+V68jqk7UONzc3NWzY0K5PZmamoqOjrT4AAAAAUJA59MxdeHi4Zs+erW+++Uaenp7W/W3e3t4qWrSovL291a9fP0VERKhkyZLy8vLSkCFDFBwcbL1QvU2bNvL391fPnj01YcIExcfH65VXXlF4eLh1Zm3gwIGaMmWKRowYob59+2rlypWaN2+elixZYtUSERGhsLAwNWrUSE2aNNGkSZOUkpKiPn363PkDAwAAAAB5ZDPGGIdt3GbLsX3mzJnq3bu3pMsvMX/xxRf11VdfKTU1VaGhoZo2bZrd5ZJ//vmnBg0apNWrV6t48eIKCwvTO++8o0KF/pddV69erWHDhmnnzp2qVKmSXn31VWsbWaZMmaL33ntP8fHxCgwM1OTJkxUUFJSrfUlOTpa3t7eSkpLk5eWVtwNxG1zj0P5jOO5XDQAAgH86R2WDPIe77du3W0+zvNrixYvVpUuX/Kjrb4dwV7AQ7gAAAOAojsoGeb7nLjQ0VAcOHMjWvnDhQvXo0SNfigIAAAAA5E2ew13//v0VEhJi9/63uXPnqlevXoqMjMzP2gAAAAAAuZTnB6q89tprOn36tEJCQrRmzRotX75c/fv313//+1917dr1dtQIAAAAALiBm3pa5kcffaQePXqoadOmOnLkiL766it17tw5v2sDAAAAAORSrsLdt99+m63t0Ucf1dq1a9W9e3fZbDarz8MPP5y/FQIAAAAAbihXT8t0ccndrXk2m00ZGRm3XNTfEU/LLFh4WiYAAAAcxVHZIFdn7jIzM293HQAAAACAW5Dnp2UCAAAAAAqePIe7559/XpMnT87WPmXKFA0dOjQ/agIAAAAA5FGew93ChQvVrFmzbO333XefFixYkC9FAQAAAADyJs/h7tSpU/L29s7W7uXlpZMnT+ZLUQAAAACAvMlzuKtRo4aWL1+erX3ZsmWqVq1avhQFAAAAAMibPL/EPCIiQoMHD9aJEyf04IMPSpKio6P1/vvva9KkSfldHwAAAAAgF/Ic7vr27avU1FS99dZbeuONNyRJVapU0fTp09WrV698LxAAAAAAcGO5eon5tZw4cUJFixaVh4dHftb0t8RLzAsWXmIOAAAARynQLzHPyYkTJ7Rnzx5JUq1atVS6dOl8KwoAAAAAkDd5fqBKSkqK+vbtq/Lly6tFixZq0aKFypcvr379+un8+fO3o0YAAAAAwA3kOdxFREQoJiZG3333nRITE5WYmKhvvvlGMTExevHFF29HjQAAAACAG8jzPXelS5fWggUL1KpVK7v2VatW6YknntCJEyfys76/De65K1i45w4AAACO4qhskOczd+fPn1e5cuWytZctW5bLMgEAAADAQfIc7oKDgzV27FhdvHjRartw4YJee+01BQcH52txAAAAAIDcyfPTMj/88EOFhoaqUqVKql+/viRpy5YtKlKkiFasWJHvBQIAAAAAbuym3nN3/vx5zZo1S7t375Yk1a5dWz169FDRokXzvcC/C+65K1i45w4AAACO8rd6z12xYsU0YMCA/K4FAAAAAHCTchXuvv3221yv8OGHH77pYgAAAAAANydX4a5Lly65WpnNZlNGRsat1AMAAAAAuAm5CneZmZm3uw4AAAAAwC3I86sQAAAAAAAFT67D3cqVK+Xv76/k5ORs85KSklSnTh2tWbMmX4sDAAAAAOROrsPdpEmTNGDAgBwf5ent7a1nn31WEydOzNfiAAAAAAC5k+twt2XLFrVt2/aa89u0aaONGzfmS1EAAAAAgLzJdbhLSEhQ4cKFrzm/UKFCOnHiRL4UBQAAAADIm1yHu4oVK2r79u3XnL9161aVL18+X4oCAAAAAORNrsNd+/bt9eqrr+rixYvZ5l24cEFjx45Vx44d87U4AAAAAEDu2IwxJjcdExIS1KBBA7m6umrw4MGqWbOmJGn37t2aOnWqMjIytGnTJpUrV+62FlxQJScny9vbW0lJSTk+dOZOs9kcXYFj5e5XDQAAAOQ/R2WDXL3EXJLKlSun9evXa9CgQRo9erSyMqHNZlNoaKimTp36jw12AAAAAOBouQ53klS5cmUtXbpUZ86c0b59+2SM0d13360SJUrcrvoAAAAAALmQ63vurlSiRAk1btxYTZo0uaVgt2bNGnXq1EkVKlSQzWbT4sWL7eb37t1bNpvNbrr6dQynT59Wjx495OXlJR8fH/Xr10/nzp2z67N161Y1b95cRYoUkZ+fnyZMmJCtlvnz56tWrVoqUqSIAgICtHTp0pveLwAAAAC4024q3OWXlJQU1a9fX1OnTr1mn7Zt2+rYsWPW9NVXX9nN79Gjh3bs2KGoqCh9//33WrNmjZ555hlrfnJystq0aaPKlStr48aNeu+99zRu3Dh98sknVp/169ere/fu6tevnzZv3qwuXbqoS5cu1306KAAAAAAUJLl+oMrtZrPZtGjRInXp0sVq6927txITE7Od0cuya9cu+fv7a8OGDWrUqJEkafny5Wrfvr3++usvVahQQdOnT9fLL7+s+Ph4ubm5SZJGjRqlxYsXa/fu3ZKkJ598UikpKfr++++tdTdt2lSBgYGaMWNGjttOTU1Vamqq9Tk5OVl+fn48UKWAKBi/agAAAPwTOeqBKg49c5cbq1evVtmyZVWzZk0NGjRIp06dsubFxsbKx8fHCnaSFBISIhcXF/3yyy9WnxYtWljBTpJCQ0O1Z88enTlzxuoTEhJit93Q0FDFxsZes67x48fL29vbmvz8/PJlfwEAAADgZhTocNe2bVt9+eWXio6O1rvvvquYmBi1a9dOGRkZkqT4+HiVLVvWbplChQqpZMmSio+Pt/pc/RTPrM836pM1PyejR49WUlKSNR0+fPjWdhYAAAAAbkGenpZ5p3Xr1s363wEBAapXr56qV6+u1atXq3Xr1g6sTHJ3d5e7u7tDawAAAACALAX6zN3VqlWrptKlS2vfvn2SJF9fXx0/ftyuz6VLl3T69Gn5+vpafRISEuz6ZH2+UZ+s+QAAAABQ0P2twt1ff/2lU6dOqXz58pKk4OBgJSYmauPGjVaflStXKjMzU0FBQVafNWvWKD093eoTFRWlmjVrWq9xCA4OVnR0tN22oqKiFBwcfLt3CQAAAADyhUPD3blz5xQXF6e4uDhJ0oEDBxQXF6dDhw7p3LlzGj58uH7++WcdPHhQ0dHR6ty5s2rUqKHQ0FBJUu3atdW2bVsNGDBAv/76q3766ScNHjxY3bp1U4UKFSRJTz31lNzc3NSvXz/t2LFDc+fO1YcffqiIiAirjhdeeEHLly/X+++/r927d2vcuHH67bffNHjw4Dt+TAAAAADgZjj0VQirV6/WAw88kK09LCxM06dPV5cuXbR582YlJiaqQoUKatOmjd544w27h5+cPn1agwcP1nfffScXFxd17dpVkydPloeHh9Vn69atCg8P14YNG1S6dGkNGTJEI0eOtNvm/Pnz9corr+jgwYO6++67NWHCBLVv3z7X++Kox51eC69CcHQFAAAA+KdyVDYoMO+5+7sj3BUs/KoBAADgKLznDgAAAABw0wh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQcGu7WrFmjTp06qUKFCrLZbFq8eLHdfGOMxowZo/Lly6to0aIKCQnR3r177fqcPn1aPXr0kJeXl3x8fNSvXz+dO3fOrs/WrVvVvHlzFSlSRH5+fpowYUK2WubPn69atWqpSJEiCggI0NKlS/N9fwEAAADgdnFouEtJSVH9+vU1derUHOdPmDBBkydP1owZM/TLL7+oePHiCg0N1cWLF60+PXr00I4dOxQVFaXvv/9ea9as0TPPPGPNT05OVps2bVS5cmVt3LhR7733nsaNG6dPPvnE6rN+/Xp1795d/fr10+bNm9WlSxd16dJF27dvv307DwAAAAD5yGaMMY4uQpJsNpsWLVqkLl26SLp81q5ChQp68cUX9dJLL0mSkpKSVK5cOUVGRqpbt27atWuX/P39tWHDBjVq1EiStHz5crVv315//fWXKlSooOnTp+vll19WfHy83NzcJEmjRo3S4sWLtXv3bknSk08+qZSUFH3//fdWPU2bNlVgYKBmzJiRq/qTk5Pl7e2tpKQkeXl55ddhuWk2m6MrcKyC8asGAADAP5GjskGBvefuwIEDio+PV0hIiNXm7e2toKAgxcbGSpJiY2Pl4+NjBTtJCgkJkYuLi3755RerT4sWLaxgJ0mhoaHas2ePzpw5Y/W5cjtZfbK2k5PU1FQlJyfbTQAAAADgKAU23MXHx0uSypUrZ9derlw5a158fLzKli1rN79QoUIqWbKkXZ+c1nHlNq7VJ2t+TsaPHy9vb29r8vPzy+suAgAAAEC+KbDhrqAbPXq0kpKSrOnw4cOOLgkAAADAP1iBDXe+vr6SpISEBLv2hIQEa56vr6+OHz9uN//SpUs6ffq0XZ+c1nHlNq7VJ2t+Ttzd3eXl5WU3AQAAAICjFNhwV7VqVfn6+io6OtpqS05O1i+//KLg4GBJUnBwsBITE7Vx40arz8qVK5WZmamgoCCrz5o1a5Senm71iYqKUs2aNVWiRAmrz5XbyeqTtR0AAAAAKOgcGu7OnTunuLg4xcXFSbr8EJW4uDgdOnRINptNQ4cO1Ztvvqlvv/1W27ZtU69evVShQgXriZq1a9dW27ZtNWDAAP3666/66aefNHjwYHXr1k0VKlSQJD311FNyc3NTv379tGPHDs2dO1cffvihIiIirDpeeOEFLV++XO+//752796tcePG6bffftPgwYPv9CEBAAAAgJvi0FchrF69Wg888EC29rCwMEVGRsoYo7Fjx+qTTz5RYmKi7r//fk2bNk333HOP1ff06dMaPHiwvvvuO7m4uKhr166aPHmyPDw8rD5bt25VeHi4NmzYoNKlS2vIkCEaOXKk3Tbnz5+vV155RQcPHtTdd9+tCRMmqH379rneF16FULDwKgQAAAA4iqOyQYF5z93fHeGuYOFXDQAAAEfhPXcAAAAAgJtGuAMAAAAAJ0C4AwAAAAAnQLgDAAAAACdAuAMAAAAAJ0C4AwAAAAAnQLgDAAAAACdAuAMAAAAAJ0C4AwAAAAAnQLgDAAAAACdAuAMAAAAAJ0C4AwAAAAAnQLgDAAAAACdAuAMAAAAAJ0C4AwAAAAAnQLgDAAAAACdAuAMAAAAAJ0C4AwAAAAAnQLgDAAAAACdAuAMAAAAAJ0C4AwAAAAAnQLgDAAAAACdAuAMAAAAAJ0C4AwAAAAAnQLgDAAAAACdAuAMAAAAAJ0C4AwAAAAAnQLgDAAAAACdAuAMAAAAAJ0C4AwAAAAAnQLgDAAAAACdAuAMAAAAAJ0C4AwAAAAAnQLgDAAAAACdAuAMAAAAAJ0C4AwAAAAAnQLgDAAAAACdQoMPduHHjZLPZ7KZatWpZ8y9evKjw8HCVKlVKHh4e6tq1qxISEuzWcejQIXXo0EHFihVT2bJlNXz4cF26dMmuz+rVq9WgQQO5u7urRo0aioyMvBO7BwAAAAD5pkCHO0mqU6eOjh07Zk3r1q2z5g0bNkzfffed5s+fr5iYGB09elSPPvqoNT8jI0MdOnRQWlqa1q9fry+++EKRkZEaM2aM1efAgQPq0KGDHnjgAcXFxWno0KHq37+/VqxYcUf3EwAAAABuhc0YYxxdxLWMGzdOixcvVlxcXLZ5SUlJKlOmjGbPnq3HHntMkrR7927Vrl1bsbGxatq0qZYtW6aOHTvq6NGjKleunCRpxowZGjlypE6cOCE3NzeNHDlSS5Ys0fbt2611d+vWTYmJiVq+fHmua01OTpa3t7eSkpLk5eV1azueD2w2R1fgWAX3Vw0AAABn56hsUODP3O3du1cVKlRQtWrV1KNHDx06dEiStHHjRqWnpyskJMTqW6tWLd11112KjY2VJMXGxiogIMAKdpIUGhqq5ORk7dixw+pz5Tqy+mSt41pSU1OVnJxsNwEAAACAoxTocBcUFKTIyEgtX75c06dP14EDB9S8eXOdPXtW8fHxcnNzk4+Pj90y5cqVU3x8vCQpPj7eLthlzc+ad70+ycnJunDhwjVrGz9+vLy9va3Jz8/vVncXAAAAAG5aIUcXcD3t2rWz/ne9evUUFBSkypUra968eSpatKgDK5NGjx6tiIgI63NycjIBDwAAAIDDFOgzd1fz8fHRPffco3379snX11dpaWlKTEy065OQkCBfX19Jkq+vb7anZ2Z9vlEfLy+v6wZId3d3eXl52U0AAAAA4Ch/q3B37tw57d+/X+XLl1fDhg1VuHBhRUdHW/P37NmjQ4cOKTg4WJIUHBysbdu26fjx41afqKgoeXl5yd/f3+pz5Tqy+mStAwAAAAD+Dgp0uHvppZcUExOjgwcPav369XrkkUfk6uqq7t27y9vbW/369VNERIRWrVqljRs3qk+fPgoODlbTpk0lSW3atJG/v7969uypLVu2aMWKFXrllVcUHh4ud3d3SdLAgQP1xx9/aMSIEdq9e7emTZumefPmadiwYY7cdQAAAADIkwJ9z91ff/2l7t2769SpUypTpozuv/9+/fzzzypTpowkaeLEiXJxcVHXrl2Vmpqq0NBQTZs2zVre1dVV33//vQYNGqTg4GAVL15cYWFhev31160+VatW1ZIlSzRs2DB9+OGHqlSpkj777DOFhobe8f0FAAAAgJtVoN9z93fCe+4KFn7VAAAAcBTecwcAAAAAuGkF+rJMAChIOCPu6ArgbBhTjq4AgLPhzB0AAAAAOAHCHQAAAAA4AcIdAAAAADgBwh0AAAAAOAHCHQAAAAA4AcIdAAAAADgBwh0AAAAAOAHCHQAAAAA4AcIdAAAAADgBwh0AAAAAOAHCHQAAAAA4AcIdAAAAADgBwh0AAAAAOAHCHQAAAAA4AcIdAAAAADgBwh0AAAAAOAHCHQAAAAA4AcIdAAAAADgBwh0AAAAAOAHCHQAAAAA4AcIdAAAAADgBwh0AAAAAOAHCHQAAAAA4AcIdAAAAADgBwh0AAAAAOAHCHQAAAAA4AcIdAAAAADgBwh0AAAAAOAHCHQAAAAA4AcIdAAAAADgBwh0AAAAAOAHCHQAAAAA4AcIdAAAAADgBwh0AAAAAOAHCHQAAAAA4AcLdVaZOnaoqVaqoSJEiCgoK0q+//urokgAAAADghgh3V5g7d64iIiI0duxYbdq0SfXr11doaKiOHz/u6NIAAAAA4LoId1f44IMPNGDAAPXp00f+/v6aMWOGihUrps8//9zRpQEAAADAdRVydAEFRVpamjZu3KjRo0dbbS4uLgoJCVFsbGy2/qmpqUpNTbU+JyUlSZKSk5Nvf7G4Ib4GIP8xroD8xZjC7eDt7egKHOv//pPc4bIygTHmjm6XcPd/Tp48qYyMDJUrV86uvVy5ctq9e3e2/uPHj9drr72Wrd3Pz++21Yjc+6f/wwbcDowrIH8xpoD8V9DG1dmzZ+V9B4si3N2k0aNHKyIiwvqcmZmp06dPq1SpUrLZbA6szPGSk5Pl5+enw4cPy8vLy9HlAE6BcQXkL8YUkP8YV/9jjNHZs2dVoUKFO7pdwt3/KV26tFxdXZWQkGDXnpCQIF9f32z93d3d5e7ubtfm4+NzO0v82/Hy8vrHD2wgvzGugPzFmALyH+Pqsjt5xi4LD1T5P25ubmrYsKGio6OttszMTEVHRys4ONiBlQEAAADAjXHm7goREREKCwtTo0aN1KRJE02aNEkpKSnq06ePo0sDAAAAgOsi3F3hySef1IkTJzRmzBjFx8crMDBQy5cvz/aQFVyfu7u7xo4dm+2yVQA3j3EF5C/GFJD/GFeOZzN3+vmcAAAAAIB8xz13AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3DlalShVNmjTJ0WX87Rw8eFA2m01xcXG3fVt8R38vfF83hzGF6+E7uzmMK1wL39fNYUzlgoEJCwszksyzzz6bbd5zzz1nJJmwsLBcrevAgQNGktm8eXOu+h8/ftykpKTkqm/Hjh1NaGhojvPWrFljJJktW7bkal3XsmrVKiPJnDlz5pbWc7Xz58+bEiVKmFKlSpmLFy/madmwsDDTuXNnu7ZLly6ZY8eOmfT09HyrcebMmcbb2ztbe16+o/wyZcoUU7lyZePu7m6aNGlifvnllzu6/VvFmPofxpR3tvY7PaZiYmJMx44dTfny5Y0ks2jRoju27fzEuPofxpV3tvY7Pa7efvtt06hRI+Ph4WHKlCljOnfubHbv3n3Htp8fGFP/w5jyztZ+p8fUtGnTTEBAgPH09DSenp6madOmZunSpXleD2fu/o+fn5/mzJmjCxcuWG0XL17U7Nmzddddd+X79tLS0iRJZcqUUbFixXK1TL9+/RQVFaW//vor27yZM2eqUaNGqlevXr7WebOMMbp06ZL1eeHChapTp45q1aqlxYsX3/L6XV1d5evrq0KFbv/bPPLyHeWHuXPnKiIiQmPHjtWmTZtUv359hYaG6vjx43eshvzAmMpfjKmbl5KSovr162vq1Kl3bJu3C+MqfzGubl5MTIzCw8P1888/KyoqSunp6WrTpo1SUlLuWA35gTGVvxhTN69SpUp65513tHHjRv3222968MEH1blzZ+3YsSNvK8rn0Pm3lPWXgbp165r/9//+n9U+a9YsU69ePdO5c2frLzfLli0zzZo1M97e3qZkyZKmQ4cOZt++fdYykuymli1b2m3jzTffNOXLlzdVqlQxxhhTuXJlM3HiRGPM5b+aFC5c2KxZs8Za37vvvmvKlClj4uPjTXp6uilXrpx544037Oo/e/as8fDwMNOnTzfGGLN27Vpz//33myJFiphKlSqZIUOGmHPnzln9L168aEaMGGEqVapk3NzcTPXq1c1nn31m/dXpyilrvy9evGiGDBliypQpY9zd3U2zZs3Mr7/+aq0z6y8+S5cuNQ0aNDCFCxc2q1atsua3atXKzJgxw0yfPt089NBD2b6D7du3mw4dOhhPT0/j4eFh7r//frNv3z4zduzYbDWtWrXK7i9kGRkZpmLFimbatGl269y0aZOx2Wzm4MGDxhhj3n//fVO3bl1TrFgxU6lSJTNo0CBz9uxZu/qvnMaOHZvtOzLGmD///NM8/PDDpnjx4sbT09M8/vjjJj4+3po/duxYU79+ffPll1+aypUrGy8vL/Pkk0+a5OTkbPudkyZNmpjw8HDrc0ZGhqlQoYIZP358rpYvCBhTjKmCNKaupL/5mTvGFeOqII4rYy6f5ZBkYmJibmp5R2BMMaYK8pgyxpgSJUqYzz77LE/LEO7M/wbeBx98YFq3bm21t27d2kycONFucC9YsMAsXLjQ7N2712zevNl06tTJBAQEmIyMDGOMMb/++quRZH788Udz7Ngxc+rUKWsbHh4epmfPnmb79u1m+/btxpjsP5zhw4ebypUrm8TERLNp0ybj5uZmvvnmG7v51atXN5mZmVbb559/booWLWoSExPNvn37TPHixc3EiRPN77//bn766Sdz7733mt69e1v9n3jiCePn52e+/vprs3//fvPjjz+aOXPmmEuXLpmFCxcaSWbPnj3m2LFjJjEx0RhjzPPPP28qVKhgli5danbs2GHCwsJMiRIlrP3LGhz16tUzP/zwg9m3b581b9++fcbd3d2cPn3anDp1yhQpUsQacMYY89dff5mSJUuaRx991GzYsMHs2bPHfP7552b37t3m7Nmz5oknnjBt27Y1x44dM8eOHTOpqanZLn946aWXzP3332/3vb744ot2bRMnTjQrV640Bw4cMNHR0aZmzZpm0KBBxhhjUlNTzaRJk4yXl5e1nayBf+V3lJGRYQIDA839999vfvvtN/Pzzz+bhg0bWv+IG3N5cHt4eJhHH33UbNu2zaxZs8b4+vqaf/3rX9f8DWZJTU01rq6u2f7js1evXubhhx++4fIFBWOKMVVQxtTVnCHcMa4YVwVtXBljzN69e40ks23btpta3hEYU4ypgjqmLl26ZL766ivj5uZmduzYkadlCXfmf4P7+PHjxt3d3Rw8eNAcPHjQFClSxJw4ccJucF/txIkTdv+YXeua67CwMFOuXDmTmppq13714E5NTTWBgYHmiSeeMP7+/mbAgAF2/Xft2mX99SJL8+bNzdNPP22MMaZfv37mmWeesVtm7dq1xsXFxVy4cMHs2bPHSDJRUVE57k9O11yfO3fOFC5c2MyaNctqS0tLMxUqVDATJkywW27x4sXZ1vmvf/3LdOnSxfrcuXNn668ixhgzevRoU7VqVZOWlpZjTTldc331cd68ebOx2Wzmzz//NMYY6685WX/Nysn8+fNNqVKlrM/Xuub6yu/ohx9+MK6urubQoUPW/B07dhhJ1l+yxo4da4oVK2b3l5rhw4eboKCga9aS5ciRI0aSWb9+vV378OHDTZMmTW64fEHBmPofxpR3tn53ckxdzRnCHeOKcVXQxlVGRobp0KGDadasWZ6XdSTG1P8wpryz9XPEmNq6daspXry4cXV1Nd7e3mbJkiW5XjYL99xdoUyZMurQoYMiIyM1c+ZMdejQQaVLl7brs3fvXnXv3l3VqlWTl5eXqlSpIkk6dOjQDdcfEBAgNze36/Zxc3PTrFmztHDhQl28eFETJ060m1+rVi3dd999+vzzzyVJ+/bt09q1a9WvXz9J0pYtWxQZGSkPDw9rCg0NVWZmpg4cOKC4uDi5urqqZcuWuT0s2r9/v9LT09WsWTOrrXDhwmrSpIl27dpl17dRo0Z2nzMyMvTFF1/o6aefttqefvppRUZGKjMzU5IUFxen5s2bq3Dhwrmu6WqBgYGqXbu2Zs+eLenyvQDHjx/X448/bvX58ccf1bp1a1WsWFGenp7q2bOnTp06pfPnz+d6O7t27ZKfn5/8/PysNn9/f/n4+NgdiypVqsjT09P6XL58+b/dPXP5gTGVM8bU/zCm8o5xlTPG1f/c6XEVHh6u7du3a86cOXletiBgTOWMMfU/d2pM1axZU3Fxcfrll180aNAghYWFaefOnbleXuJVCNn07dtXkZGR+uKLL9S3b99s8zt16qTTp0/r008/1S+//KJffvlF0v9ukL2e4sWL56qG9evXS5JOnz6t06dPZ5vfr18/LVy4UGfPntXMmTNVvXp1a7CeO3dOzz77rOLi4qxpy5Yt2rt3r6pXr66iRYvmqoabdfU+rlixQkeOHNGTTz6pQoUKqVChQurWrZv+/PNPRUdHS1K+1dSjRw9rcM+ePVtt27ZVqVKlJF1+dG7Hjh1Vr149LVy4UBs3brQerpCb7y6vrv6HymazWf+YXU/p0qXl6uqqhIQEu/aEhAT5+vrma413CmPq1jCmLrvZMeWsGFe3hnF1WX6Mq8GDB+v777/XqlWrVKlSpfws745iTN0axtRltzqm3NzcVKNGDTVs2FDjx49X/fr19eGHH+apBsLdVdq2bau0tDSlp6crNDTUbt6pU6e0Z88evfLKK2rdurVq166tM2fO2PXJ+stMRkbGTW1///79GjZsmD799FMFBQUpLCws24/iiSeekIuLi2bPnq0vv/xSffv2lc1mkyQ1aNBAO3fuVI0aNbJNbm5uCggIUGZmpmJiYnLcfk71V69eXW5ubvrpp5+stvT0dG3YsEH+/v7X3Z///Oc/6tatm90/NnFxcerWrZv+85//SJLq1auntWvXKj09/Zo15eZ4PvXUU9q+fbs2btyoBQsWqEePHta8jRs3KjMzU++//76aNm2qe+65R0ePHs3zdmrXrq3Dhw/r8OHDVtvOnTuVmJh4w2ORG25ubmrYsKH1D58kZWZmKjo6WsHBwbe8fkdgTDGmrud2jylnxbhiXF3PnRhXxhgNHjxYixYt0sqVK1W1atV8Wa+jMKYYU9fjqP9flZmZqdTU1LwtlOcLOZ3Q1df0JiUlmaSkJOtz1jXXGRkZplSpUubpp582e/fuNdHR0aZx48Z293Ckp6ebokWLmjfffNPEx8dbN6TmdN2wMfbX8166dMk0bdrUdO3a1RhjzNGjR02pUqWs65qv1K9fP1OiRAnj6upqjhw5YrVv2bLFFC1a1ISHh5vNmzeb33//3SxevNju6Yu9e/c2fn5+ZtGiReaPP/4wq1atMnPnzjXGXL651WazmcjISHP8+HHrptIXXnjBVKhQwSxbtszuhtrTp08bY3K+Vvv48eOmcOHCZtmyZdnqX7p0qXF3dzenTp0yJ0+eNKVKlbJuqP3999/Nl19+ab0v56233jJ33XWX2b17tzlx4oRJS0u75rXtzZo1M/Xr1zeenp7m/PnzVntcXJyRZCZNmmT2799vvvzyS1OxYkW7mn/66SfrZugTJ05Y7za58jvKzMw0gYGBpnnz5mbjxo3ml19+yfGG2vr169vVNXHiRFO5cuVsxyEnc+bMMe7u7iYyMtLs3LnTPPPMM8bHx8fuiUwFHWOKMWVMwRlTZ8+eNZs3bzabN282kswHH3xgNm/ebN2j8XfBuGJcGVNwxtWgQYOMt7e3Wb16tfUgimPHjtntT0HHmGJMGVNwxtSoUaNMTEyMOXDggNm6dasZNWqUsdls5ocffsjV8lkId+baAy/LlTfURkVFmdq1axt3d3dTr149s3r16mw36H/66afGz8/PuLi4ZHsU7tWu/OG89tprpnz58ubkyZPW/IULFxo3NzcTFxdnt9z69euNJNO+ffts6/z111/NQw89ZDw8PEzx4sVNvXr1zFtvvWXNv3Dhghk2bJgpX768cXNzMzVq1DCff/65Nf/11183vr6+xmazWft94cIFM2TIEFO6dOnrPgr3ysH973//2/j4+OR4o2xqaqrx8fExH374oTHm8j9Kbdq0McWKFTOenp6mefPmZv/+/caYy/9IZO2PcngU7pWmTZtmJJlevXpl2+YHH3xgypcvb4oWLWpCQ0PNl19+ma3mgQMHmlKlSuXLo3CvlJfBbYwxH330kbnrrruMm5ubadKkifn5559zvWxBwJhiTGUpCGMqp0ddS7l/OXFBwbhiXGUpCOMqpzElycycOTNXyxcEjCnGVJaCMKb69u1rKleubNzc3EyZMmVM69at8xzsjDHGZowxeTvXBwAAAAAoaLjnDgAAAACcAOEOuIMOHTpk95jiq6fcPFIZwP8wpoD8x7gC8tedHFNclgncQZcuXdLBgwevOb9KlSoqVKjQnSsI+JtjTAH5j3EF5K87OaYIdwAAAADgBLgsEwAAAACcAOEOAAAAAJwA4Q4AAAAAnADhDgAAAACcAOEOAIBb1KpVKw0dOtTRZQAA/uEIdwAAh+ndu7dsNpveeecdu/bFixfLZrPlaV1VqlTRpEmT8rG62+fgwYOy2WyKi4tzdCkAACdCuAMAOFSRIkX07rvv6syZM44uJc/S0tIcXUK+Sk9Pd3QJAIBbQLgDADhUSEiIfH19NX78+Ov2W7dunZo3b66iRYvKz89Pzz//vFJSUiRdvizyzz//1LBhw2Sz2WSz2WSMUZkyZbRgwQJrHYGBgSpfvrzdOt3d3XX+/HlJ0qFDh9S5c2d5eHjIy8tLTzzxhBISEqz+48aNU2BgoD777DNVrVpVRYoUybHWJUuWyNvbW7NmzbqpY7J//3517txZ5cqVk4eHhxo3bqwff/zRmv/666+rbt262ZYLDAzUq6++an3+7LPPVLt2bRUpUkS1atXStGnTrHlZZw/nzp2rli1bqkiRIpo1a5b+/PNPderUSSVKlFDx4sVVp04dLV269Kb2AwBwZxHuAAAO5erqqrffflsfffSR/vrrrxz77N+/X23btlXXrl21detWzZ07V+vWrdPgwYMlSV9//bUqVaqk119/XceOHdOxY8dks9nUokULrV69WpJ05swZ7dq1SxcuXNDu3bslSTExMWrcuLGKFSumzMxMde7cWadPn1ZMTIyioqL0xx9/6Mknn7SrZd++fVq4cKG+/vrrHC+rnD17trp3765Zs2apR48eN3VMzp07p/bt2ys6OlqbN29W27Zt1alTJx06dEiS1LdvX+3atUsbNmywltm8ebO2bt2qPn36SJJmzZqlMWPG6K233tKuXbv09ttv69VXX9UXX3xht61Ro0bphRde0K5duxQaGqrw8HClpqZqzZo12rZtm9599115eHjc1H4AAO6sQo4uAACARx55RIGBgRo7dqz+85//ZJs/fvx49ejRw3poyd13363JkyerZcuWmj59ukqWLClXV1d5enrK19fXWq5Vq1b6+OOPJUlr1qzRvffeK19fX61evVq1atXS6tWr1bJlS0lSdHS0tm3bpgMHDsjPz0+S9OWXX6pOnTrasGGDGjduLOnypZhffvmlypQpk63OqVOn6uWXX9Z3331nrfdm1K9fX/Xr17c+v/HGG1q0aJG+/fZbDR48WJUqVVJoaKhmzpxp1TVz5ky1bNlS1apVkySNHTtW77//vh599FFJUtWqVbVz5059/PHHCgsLs9Y9dOhQq490+exl165dFRAQIEnW+gAABR9n7gAABcK7776rL774Qrt27co2b8uWLYqMjJSHh4c1hYaGKjMzUwcOHLjmOlu2bKmdO3fqxIkTiomJUatWrdSqVSutXr1a6enpWr9+vVq1aiVJ2rVrl/z8/KxgJ0n+/v7y8fGxq6ly5co5BrsFCxZo2LBhioqKuqVgJ10+c/fSSy+pdu3a8vHxkYeHh3bt2mWduZOkAQMG6KuvvtLFixeVlpam2bNnq2/fvpKklJQU7d+/X/369bM7Zm+++ab2799vt61GjRrZfX7++ef15ptvqlmzZho7dqy2bt16S/sCALhzCHcAgAKhRYsWCg0N1ejRo7PNO3funJ599lnFxcVZ05YtW7R3715Vr179musMCAhQyZIlFRMTYxfuYmJitGHDBqWnp+u+++7LU53FixfPsf3ee+9VmTJl9Pnnn8sYk6d1Xu2ll17SokWL9Pbbb2vt2rWKi4tTQECA3QNcOnXqJHd3dy1atEjfffed0tPT9dhjj0m6fLwk6dNPP7U7Ztu3b9fPP/983f3p37+//vjjD/Xs2VPbtm1To0aN9NFHH93S/gAA7gwuywQAFBjvvPOOAgMDVbNmTbv2Bg0aaOfOnapRo8Y1l3Vzc1NGRoZdm81mU/PmzfXNN99ox44duv/++1WsWDGlpqbq448/VqNGjaxwU7t2bR0+fFiHDx+2zt7t3LlTiYmJ8vf3v2Ht1atX1/vvv69WrVrJ1dVVU6ZMyevuW3766Sf17t1bjzzyiKTLYe3gwYN2fQoVKqSwsDDNnDlTbm5u6tatm4oWLSpJKleunCpUqKA//vjjpu778/Pz08CBAzVw4ECNHj1an376qYYMGXLT+wMAuDMIdwCAAiMgIEA9evTQ5MmT7dpHjhyppk2bavDgwerfv7+KFy+unTt3KioqygpRVapU0Zo1a9StWze5u7urdOnSki7fd/fiiy+qUaNG1oNBWrRooVmzZmn48OHWNkJCQqztT5o0SZcuXdJzzz2nli1bZrt08VruuecerVq1Sq1atVKhQoVu+N69PXv2ZGurU6eO7r77bn399dfq1KmTbDabXn31VWVmZmbr279/f9WuXVvS5UB4pddee03PP/+8vL291bZtW6Wmpuq3337TmTNnFBERcc2ahg4dqnbt2umee+7RmTNntGrVKmsbAICCjcsyAQAFyuuvv54tyNSrV08xMTH6/fff1bx5c917770aM2aMKlSoYLfcwYMHVb16dbt74lq2bKmMjAzr3jrpcuC7us1ms+mbb75RiRIl1KJFC4WEhKhatWqaO3dunuqvWbOmVq5cqa+++kovvvjidft269ZN9957r92UkJCgDz74QCVKlNB9992nTp06KTQ0VA0aNMi2/N1336377rtPtWrVUlBQkN28/v3767PPPtPMmTMVEBCgli1bKjIyUlWrVr1uTRkZGQoPD1ft2rXVtm1b3XPPPXavUAAAFFw2c6s3BgAAAIcwxujuu+/Wc889d92zcQCAfwYuywQA4G/oxIkTmjNnjuLj46132wEA/tkIdwAA/A2VLVtWpUuX1ieffKISJUo4uhwAQAFAuAMA4G+IuyoAAFfjgSoAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBAh3AAAAAOAECHcAAAAA4AQIdwAAAADgBP4/da6Cud3tvjMAAAAASUVORK5CYII=", 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/Y4z69OmjCRMm6L///a/Ddx5k8vT0tL6f0tPTdeLECXl5eem+++6zPreSFBoaqrJly9r1oa1bt2rz5s3WlW/J8XPbtm1b6/ZXANfGbZnAP1y9evWuO6DKSy+9pC+//FKPPfaY7rrrLjVv3lxPP/30LQ+vXr58ebvXPj4+kiR/f/8s5RkZGUpOTrZuFV2zZo1GjBihuLg4nTt3zq5+cnKy1da17N69W5s3b77mHwrHjh2TJB04cEBlypTJcqvitW55uparj7VYsWKSZD2TlJnkXd2uh4eH7r77bmt9Th0/flznzp3LNs6qVasqIyNDhw4dsm49y6m9e/fqvvvuU758Of9fhyOx7N27V23bts1Ru/3799eFCxe0adOmHB9HTuPv3Lmz+vTpowMHDiggIEBz587VxYsX1alTJ4fbutLx48eVlJSkjz/+WB9//HG2dTI/e0OGDNGyZctUr149Va5cWc2bN9ezzz6rhg0b5nh/Vzpw4IB1++uVMm+fPnDggJVYSMp2BN3s7N69W8nJySpVqlS26zOPR7p8e+6wYcO0fPnyLD8uZP4ok/m84pWxXEuBAgWy9OFixYpledbvWq7ul9ltn9Pviutp1KiRpk6dqj179mjv3r2y2WwKCQmxkr4ePXroxx9/VMOGDa3k6cCBA3Jzc8syarGfn5+KFi2a5Tvheu/XzJkzdebMGU2ZMkXPPPPMDeO9loyMDE2YMEGTJ09WQkKC3bONmd/NkuTm5qaOHTtqypQpOnfunAoVKqRZs2apQIEC1vPZkuPnNqefSeCfjuQOwHWVKlVK8fHxWrp0qRYvXqzFixdr+vTp6ty5s2bMmHHT7V75LEZOyo0xki7/8desWTNVqVJF7733nvz9/eXh4aHvv/9e77//fpYBUbKTkZGhRx55RIMHD852/b333pvDo8iZGx0THNeqVSvNmTNHb731lmbOnJmrIzl26NBBAwYM0KxZs/Tqq6/qv//9r+rUqeNwUn+1zM/mc889d82rJ5nPZVWtWlW7du3SwoULtWTJEs2fP1+TJ0/W8OHDrSH3b6ecjrSYkZGhUqVK2V2luVLmH+5JSUlq0qSJvL29NXr0aFWqVEkFChTQxo0bNWTIkBz126tdq1/d6vZX9svc+K7IvFq6evVq7du3T7Vq1VLhwoXVqFEjTZw4UWfOnNGmTZv05ptvZtn2WleBr3a996thw4aKj4/XpEmT9PTTT9/0s2r//ve/9a9//UvdunXT66+/ruLFi8vNzU39+/fP8v517txZb7/9thYsWKBnnnlGs2fPtgY9yuTouXXl0T+B3ERyB+CGPDw89Pjjj+vxxx9XRkaGXnrpJX300Uf617/+pcqVK+f4D5Dc8N133yk1NVXffvut3S/vV97+lelacVWqVElnzpxRaGjodfcVEBCg2NhYnTlzxu7q3a5du24y+mvvJ7PdK29dTEtLU0JCwg3jvJqvr68KFSqUbZw7d+6Um5tbliukOVGpUiWtW7dOFy9ezPEAL47EUqlSJW3dujVH7bZu3VrNmzdXly5dVKRIkSyjpd5K/MWLF1d4eLhmzZqljh07as2aNVkGd7jZc1GkSBGlp6fn6D0tXLiw2rdvr/bt2ystLU1t2rTRm2++qaioKBUoUCBH+8wUEBBwzfcgc/3NqFSpkpYtW6aGDRte94/vlStX6sSJE/rqq6/UuHFjqzwhISFLe9Ll2/gc/dzfDjn9rrjed2D58uVVvnx5/fjjj9q3b591K2jjxo0VGRmpuXPnKj093e68BAQEKCMjQ7t377YbnOro0aNKSkpy6P2qXLmyxo0bp6ZNm+rRRx9VbGysihQpkuPtM82bN08PPfSQPvvsM7vypKSkLIMdVa9eXffff79mzZqlcuXK6eDBg1lG58zpuQXgGJ65A3BdJ06csHvt5uZmXV3IHJK7cOHCknRLw/bnVOav7Vf+up6cnKzp06dnqVu4cOFsY3r66acVFxenpUuXZlmXlJRkPd/XokULXbp0yS5xSE9Pd3gI8RsJDQ2Vh4eHJk6caHdcn332mZKTkxUeHm6VHTx40PqD/Frc3d3VvHlzffPNN9q/f79VfvToUc2ePVsPPvigvL29HY6zbdu2+uuvvzRp0qQs6651FdKRWNq2bavffvsty0iA12q/c+fOmjhxoqZOnaohQ4bkavydOnXS9u3bNWjQILm7u6tDhw433VYmd3d3tW3bVvPnz882ib1yeoyr+52Hh4cCAwNljNHFixevfZDX0KJFC61fv15xcXFW2dmzZ/Xxxx+rQoUKCgwMdLhN6XJfSk9P1+uvv55l3aVLl6z+l12/TUtL0+TJk+22qVWrlipWrKjx48dn6bvOuNKd0++KQoUKWWXZadSokZYvX67169dbyV1wcLCKFCmit956SwULFlTt2rWt+i1atJCkLD8qvPfee5Jk952QE0FBQfr++++1Y8cOPf744zp//rxD20uX38Or34O5c+fqzz//zLZ+p06d9MMPP2j8+PEqUaKEHnvsMbv1OT23ABzDlTvgH27x4sXZJgsPPPCA7r77bj3//PM6efKkHn74YZUrV04HDhzQBx98oODgYOsX5eDgYLm7u2vs2LFKTk6Wp6enNQ9dbmvevLl1JbFnz546c+aMPvnkE5UqVUpHjhyxq1u7dm1NmTJFb7zxhipXrqxSpUrp4Ycf1qBBg/Ttt9+qZcuW1tDnZ8+e1ZYtWzRv3jzt379fJUuW1OOPP66GDRtq6NCh2r9/vwIDA/XVV1/laNAWR/j6+ioqKkqjRo3So48+qieeeEK7du3S5MmTVbduXbtBCDp37qxVq1bd8A/dN954QzExMXrwwQf10ksvKV++fProo4+UmpqqcePG3VScnTt31syZMxUZGWn9kXr27FktW7ZML730UrbzwzkSy6BBgzRv3jw99dRT6tatm2rXrq2TJ0/q22+/1dSpU1WzZs0sbffp00cpKSl67bXX5OPjo1dffTVX4g8PD1eJEiU0d+5cPfbYY1k+yzd7Lt566y2tWLFC9evXV48ePRQYGKiTJ09q48aNWrZsmU6ePCnp8ufcz89PDRs2VOnSpbVjxw5NmjRJ4eHhN3XVZejQofr888/12GOP6eWXX1bx4sU1Y8YMJSQkaP78+Td9W2uTJk3Us2dPjRkzRvHx8WrevLny58+v3bt3a+7cuZowYYLatWunBx54QMWKFVNERIRefvll2Ww2/ec//8nyOXZzc9OUKVP0+OOPKzg4WF27dlWZMmW0c+dObdu2LdtE4HbK6XdFwYIFFRgYqC+++EL33nuvihcvrurVq1vPDjZq1EizZs2SzWazbtN0d3fXAw88oKVLl6pp06Z2003UrFlTERER+vjjj61bWtevX68ZM2aodevWeuihhxw+lgYNGuibb75RixYt1K5dOy1YsMChKVZatmyp0aNHq2vXrnrggQe0ZcsWzZo1y+5ugys9++yzGjx4sL7++mv16tUry75yem4BOOgOj84JII+43lQIumKY/3nz5pnmzZubUqVKGQ8PD1O+fHnTs2dPc+TIEbv2PvnkE3P33Xcbd3d3u2kRrjUVwty5c7ON55dffrErHzFihJFkjh8/bpV9++23JigoyBQoUMBUqFDBjB071hqaPiEhwaqXmJhowsPDTZEiRYwkuzhOnz5toqKiTOXKlY2Hh4cpWbKkeeCBB8w777xjN0XDiRMnTKdOnYy3t7fx8fExnTp1Mps2bXJoKoSrjynzHFw9dcSkSZNMlSpVTP78+U3p0qVNr169sgwH36RJE5PTr+6NGzeasLAw4+XlZQoVKmQeeughs3btWrs6jkyFYMzl4exfe+01U7FiRZM/f37j5+dn2rVrZzfNgbIZEj4nsRhz+Xz36dPH3HXXXcbDw8OUK1fOREREWFMHXOvzM3jwYCPJTJo06Zbjz/TSSy8ZSWb27Nm5ei6OHj1qevfubfz9/a3tmjVrZj7++GOrzkcffWQaN25sSpQoYTw9PU2lSpXMoEGDTHJy8nWPL3OfV0+FYIwxe/fuNe3atTNFixY1BQoUMPXq1TMLFy60q3Ot83sjH3/8saldu7YpWLCgKVKkiKlRo4YZPHiwOXz4sFVnzZo1pkGDBqZgwYKmbNmyZvDgwdaw+Vf3hZ9++sk88sgjpkiRIqZw4cImKCjIfPDBB9b6iIgIU7hw4SxxZH5f3EhAQIAJDw/PUn7195UxOf+uWLt2raldu7bx8PDI8r5v27bNSDJVq1a1a/uNN94wksy//vWvLLFcvHjRjBo1yvp8+fv7m6ioKGvaiBsdizHZfxa++eYbky9fPtO+ffssUxtc3e7VUyEMHDjQlClTxhQsWNA0bNjQxMXFZXvOMrVo0cJIyravG5Ozc+vodxTwT2czhif6AQC42oABA/TZZ58pMTHRuu0OQM49+eST2rJli/bs2ePsUIB/DJ65AwDgKhcuXNB///tftW3blsQOuAlHjhzRokWL7KYQAXD78cwdAAD/79ixY1q2bJnmzZunEydOqF+/fs4OCfhbSUhI0Jo1a/Tpp58qf/786tmzp7NDAv5RSO4AAPh/27dvV8eOHVWqVClNnDhRwcHBzg4J+FtZtWqVunbtqvLly2vGjBny8/NzdkjAPwrP3AEAAACAC+CZOwAAAABwASR3AAAAAOAC8swzd2+99ZaioqLUr18/jR8/XtLl0coGDhyoOXPmKDU1VWFhYZo8ebJKly5tbXfw4EH16tVLK1askJeXlyIiIjRmzBjly/e/Q1u5cqUiIyO1bds2+fv7a9iwYerSpYvd/j/88EO9/fbbSkxMVM2aNfXBBx+oXr16OY4/IyNDhw8fVpEiRWSz2W7pXAAAAAD4+zLG6PTp0ypbtqzc3O7g9TSnzrL3/9avX28qVKhggoKCTL9+/azyF1980fj7+5vY2Fjz66+/mgYNGpgHHnjAWn/p0iVTvXp1ExoaajZt2mS+//57U7JkSRMVFWXV2bdvnylUqJCJjIw027dvNx988IFxd3c3S5YsserMmTPHeHh4mGnTpplt27aZHj16mKJFi5qjR4/m+BgOHTp03QmhWVhYWFhYWFhYWFj+WcuhQ4duLVFykNMHVDlz5oxq1aqlyZMn64033lBwcLDGjx+v5ORk+fr6avbs2WrXrp0kaefOnapatari4uLUoEEDLV68WC1bttThw4etq3lTp07VkCFDdPz4cXl4eGjIkCFatGiRtm7dau2zQ4cOSkpK0pIlSyRJ9evXV926dTVp0iRJl6/C+fv7q2/fvho6dGiOjiM5OVlFixbVoUOH5O3tnZunCAAAAMDfSEpKivz9/ZWUlCQfH587tl+n35bZu3dvhYeHKzQ0VG+88YZVvmHDBl28eFGhoaFWWZUqVVS+fHkruYuLi1ONGjXsbtMMCwtTr169tG3bNt1///2Ki4uzayOzTv/+/SVJaWlp2rBhg6Kioqz1bm5uCg0NVVxc3DXjTk1NVWpqqvX69OnTkiRvb2+SOwAAAAB3/HEtpyZ3c+bM0caNG/XLL79kWZeYmCgPDw8VLVrUrrx06dJKTEy06lyZ2GWuz1x3vTopKSk6f/68Tp06pfT09Gzr7Ny585qxjxkzRqNGjcrZgQIAAADAbea00TIPHTqkfv36adasWSpQoICzwrhpUVFRSk5OtpZDhw45OyQAAAAA/2BOS+42bNigY8eOqVatWsqXL5/y5cunVatWaeLEicqXL59Kly6ttLQ0JSUl2W139OhR+fn5SZL8/Px09OjRLOsz112vjre3twoWLKiSJUvK3d092zqZbWTH09PTugWTWzEBAAAAOJvTkrtmzZppy5Ytio+Pt5Y6deqoY8eO1r/z58+v2NhYa5tdu3bp4MGDCgkJkSSFhIRoy5YtOnbsmFUnJiZG3t7eCgwMtOpc2UZmncw2PDw8VLt2bbs6GRkZio2NteoAAAAAQF7ntGfuihQpourVq9uVFS5cWCVKlLDKu3fvrsjISBUvXlze3t7q27evQkJC1KBBA0lS8+bNFRgYqE6dOmncuHFKTEzUsGHD1Lt3b3l6ekqSXnzxRU2aNEmDBw9Wt27dtHz5cn355ZdatGiRtd/IyEhFRESoTp06qlevnsaPH6+zZ8+qa9eud+hsAAAAAMCtcfpomdfz/vvvy83NTW3btrWbxDyTu7u7Fi5cqF69eikkJESFCxdWRESERo8ebdWpWLGiFi1apAEDBmjChAkqV66cPv30U4WFhVl12rdvr+PHj2v48OFKTExUcHCwlixZkmWQFQAAAADIq5w+z52rSElJkY+Pj5KTk3n+DgAAAPgHc1Zu4LRn7gAAAAAAuYfkDgAAAABcAMkdAAAAALgAkjsAAAAAcAEkdwAAAADgAkjuAAAAAMAFkNwBAAAAgAsguQMAAAAAF5DP2QHg9rDZnB2Bcxnj7AgAAACAO4srdwAAAADgAkjuAAAAAMAFkNwBAAAAgAsguQMAAAAAF0ByBwAAAAAugOQOAAAAAFwAyR0AAAAAuACSOwAAAABwASR3AAAAAOACSO4AAAAAwAWQ3AEAAACACyC5AwAAAAAXQHIHAAAAAC6A5A4AAAAAXADJHQAAAAC4AJI7AAAAAHABJHcAAAAA4AJI7gAAAADABZDcAQAAAIALILkDAAAAABdAcgcAAAAALoDkDgAAAABcAMkdAAAAALgAkjsAAAAAcAEkdwAAAADgAkjuAAAAAMAFkNwBAAAAgAsguQMAAAAAF+DU5G7KlCkKCgqSt7e3vL29FRISosWLF1vrmzZtKpvNZre8+OKLdm0cPHhQ4eHhKlSokEqVKqVBgwbp0qVLdnVWrlypWrVqydPTU5UrV1Z0dHSWWD788ENVqFBBBQoUUP369bV+/frbcswAAAAAcDs4NbkrV66c3nrrLW3YsEG//vqrHn74YbVq1Urbtm2z6vTo0UNHjhyxlnHjxlnr0tPTFR4errS0NK1du1YzZsxQdHS0hg8fbtVJSEhQeHi4HnroIcXHx6t///56/vnntXTpUqvOF198ocjISI0YMUIbN25UzZo1FRYWpmPHjt2ZEwEAAAAAt8hmjDHODuJKxYsX19tvv63u3buradOmCg4O1vjx47Otu3jxYrVs2VKHDx9W6dKlJUlTp07VkCFDdPz4cXl4eGjIkCFatGiRtm7dam3XoUMHJSUlacmSJZKk+vXrq27dupo0aZIkKSMjQ/7+/urbt6+GDh2a7b5TU1OVmppqvU5JSZG/v7+Sk5Pl7e2dG6filthszo7AufLWpxoAAAD/JCkpKfLx8bnjuUGeeeYuPT1dc+bM0dmzZxUSEmKVz5o1SyVLllT16tUVFRWlc+fOWevi4uJUo0YNK7GTpLCwMKWkpFhX/+Li4hQaGmq3r7CwMMXFxUmS0tLStGHDBrs6bm5uCg0NtepkZ8yYMfLx8bEWf3//WzsBAAAAAHAL8jk7gC1btigkJEQXLlyQl5eXvv76awUGBkqSnn32WQUEBKhs2bLavHmzhgwZol27dumrr76SJCUmJtoldpKs14mJidetk5KSovPnz+vUqVNKT0/Pts7OnTuvGXdUVJQiIyOt15lX7gAAAADAGZye3N13332Kj49XcnKy5s2bp4iICK1atUqBgYF64YUXrHo1atRQmTJl1KxZM+3du1eVKlVyYtSSp6enPD09nRoDAAAAAGRy+m2ZHh4eqly5smrXrq0xY8aoZs2amjBhQrZ169evL0nas2ePJMnPz09Hjx61q5P52s/P77p1vL29VbBgQZUsWVLu7u7Z1slsAwAAAADyOqcnd1fLyMiwG6jkSvHx8ZKkMmXKSJJCQkK0ZcsWu1EtY2Ji5O3tbd3aGRISotjYWLt2YmJirOf6PDw8VLt2bbs6GRkZio2NtXv2DwAAAADyMqfelhkVFaXHHntM5cuX1+nTpzV79mytXLlSS5cu1d69ezV79my1aNFCJUqU0ObNmzVgwAA1btxYQUFBkqTmzZsrMDBQnTp10rhx45SYmKhhw4apd+/e1i2TL774oiZNmqTBgwerW7duWr58ub788kstWrTIiiMyMlIRERGqU6eO6tWrp/Hjx+vs2bPq2rWrU84LAAAAADjKqcndsWPH1LlzZx05ckQ+Pj4KCgrS0qVL9cgjj+jQoUNatmyZlWj5+/urbdu2GjZsmLW9u7u7Fi5cqF69eikkJESFCxdWRESERo8ebdWpWLGiFi1apAEDBmjChAkqV66cPv30U4WFhVl12rdvr+PHj2v48OFKTExUcHCwlixZkmWQFQAAAADIq/LcPHd/V86ay+JamOfO2REAAADgn+ofP88dAAAAAODmkdwBAAAAgAsguQMAAAAAF0ByBwAAAAAugOQOAAAAAFwAyR0AAAAAuACSOwAAAABwASR3AAAAAOACSO4AAAAAwAWQ3AEAAACACyC5AwAAAAAXQHIHAAAAAC6A5A4AAAAAXADJHQAAAAC4AJI7AAAAAHABJHcAAAAA4AJI7gAAAADABZDcAQAAAIALILkDAAAAABdAcgcAAAAALoDkDgAAAABcAMkdAAAAALgAkjsAAAAAcAEkdwAAAADgAkjuAAAAAMAFkNwBAAAAgAsguQMAAAAAF0ByBwAAAAAugOQOAAAAAFwAyR0AAAAAuACSOwAAAABwASR3AAAAAOACSO4AAAAAwAWQ3AEAAACACyC5AwAAAAAXQHIHAAAAAC7AqcndlClTFBQUJG9vb3l7eyskJESLFy+21l+4cEG9e/dWiRIl5OXlpbZt2+ro0aN2bRw8eFDh4eEqVKiQSpUqpUGDBunSpUt2dVauXKlatWrJ09NTlStXVnR0dJZYPvzwQ1WoUEEFChRQ/fr1tX79+ttyzAAAAABwOzg1uStXrpzeeustbdiwQb/++qsefvhhtWrVStu2bZMkDRgwQN99953mzp2rVatW6fDhw2rTpo21fXp6usLDw5WWlqa1a9dqxowZio6O1vDhw606CQkJCg8P10MPPaT4+Hj1799fzz//vJYuXWrV+eKLLxQZGakRI0Zo48aNqlmzpsLCwnTs2LE7dzIAAAAA4BbYjDHG2UFcqXjx4nr77bfVrl07+fr6avbs2WrXrp0kaefOnapatari4uLUoEEDLV68WC1bttThw4dVunRpSdLUqVM1ZMgQHT9+XB4eHhoyZIgWLVqkrVu3Wvvo0KGDkpKStGTJEklS/fr1VbduXU2aNEmSlJGRIX9/f/Xt21dDhw7NUdwpKSny8fFRcnKyvL29c/OU3BSbzdkROFfe+lQDAADgn8RZuUGeeeYuPT1dc+bM0dmzZxUSEqINGzbo4sWLCg0NtepUqVJF5cuXV1xcnCQpLi5ONWrUsBI7SQoLC1NKSop19S8uLs6ujcw6mW2kpaVpw4YNdnXc3NwUGhpq1clOamqqUlJS7BYAAAAAcBanJ3dbtmyRl5eXPD099eKLL+rrr79WYGCgEhMT5eHhoaJFi9rVL126tBITEyVJiYmJdold5vrMdderk5KSovPnz+uvv/5Senp6tnUy28jOmDFj5OPjYy3+/v43dfwAAAAAkBucntzdd999io+P17p169SrVy9FRERo+/btzg7rhqKiopScnGwthw4dcnZIAAAAAP7B8jk7AA8PD1WuXFmSVLt2bf3yyy+aMGGC2rdvr7S0NCUlJdldvTt69Kj8/PwkSX5+fllGtcwcTfPKOlePsHn06FF5e3urYMGCcnd3l7u7e7Z1MtvIjqenpzw9PW/uoAEAAAAglzn9yt3VMjIylJqaqtq1ayt//vyKjY211u3atUsHDx5USEiIJCkkJERbtmyxG9UyJiZG3t7eCgwMtOpc2UZmncw2PDw8VLt2bbs6GRkZio2NteoAAAAAQF7n1Ct3UVFReuyxx1S+fHmdPn1as2fP1sqVK7V06VL5+Pioe/fuioyMVPHixeXt7a2+ffsqJCREDRo0kCQ1b95cgYGB6tSpk8aNG6fExEQNGzZMvXv3tq6qvfjii5o0aZIGDx6sbt26afny5fryyy+1aNEiK47IyEhFRESoTp06qlevnsaPH6+zZ8+qa9euTjkvAAAAAOAopyZ3x44dU+fOnXXkyBH5+PgoKChIS5cu1SOPPCJJev/99+Xm5qa2bdsqNTVVYWFhmjx5srW9u7u7Fi5cqF69eikkJESFCxdWRESERo8ebdWpWLGiFi1apAEDBmjChAkqV66cPv30U4WFhVl12rdvr+PHj2v48OFKTExUcHCwlixZkmWQFQAAAADIq/LcPHd/V8xzl7fwqQYAAICz/OPnuQMAAAAA3DySOwAAAABwASR3AAAAAOACSO4AAAAAwAWQ3AEAAACACyC5AwAAAAAXQHIHAAAAAC6A5A4AAAAAXIDDyd358+d17tw56/WBAwc0fvx4/fDDD7kaGAAAAAAg5xxO7lq1aqWZM2dKkpKSklS/fn29++67atWqlaZMmZLrAQIAAAAAbszh5G7jxo1q1KiRJGnevHkqXbq0Dhw4oJkzZ2rixIm5HiAAAAAA4MYcTu7OnTunIkWKSJJ++OEHtWnTRm5ubmrQoIEOHDiQ6wECAAAAAG7M4eSucuXKWrBggQ4dOqSlS5eqefPmkqRjx47J29s71wMEAAAAANyYw8nd8OHD9corr6hChQqqV6+eQkJCJF2+inf//ffneoAAAAAAgBuzGWOMoxslJibqyJEjqlmzptzcLueH69evl7e3t6pUqZLrQf4dpKSkyMfHR8nJyXniCqbN5uwInMvxTzUAAACQO5yVG9zUPHd+fn4qUqSIYmJidP78eUlS3bp1/7GJHQAAAAA4m8PJ3YkTJ9SsWTPde++9atGihY4cOSJJ6t69uwYOHJjrAQIAAAAAbszh5G7AgAHKnz+/Dh48qEKFClnl7du315IlS3I1OAAAAABAzuRzdIMffvhBS5cuVbly5ezK77nnHqZCAAAAAAAncfjK3dmzZ+2u2GU6efKkPD09cyUoAAAAAIBjHE7uGjVqpJkzZ1qvbTabMjIyNG7cOD300EO5GhwAAAAAIGccvi1z3LhxatasmX799VelpaVp8ODB2rZtm06ePKk1a9bcjhgBAAAAADfg8JW76tWr6/fff9eDDz6oVq1a6ezZs2rTpo02bdqkSpUq3Y4YAQAAAAA3cFOTmCMrJjHPW/hUAwAAwFmclRvk6LbMzZs357jBoKCgmw4GAAAAAHBzcpTcBQcHy2az6UYX+Ww2m9LT03MlMAAAAABAzuUouUtISLjdcQAAAAAAbkGOkruAgIDbHQcAAAAA4BY4PFrmmDFjNG3atCzl06ZN09ixY3MlKAAAAACAYxxO7j766CNVqVIlS3m1atU0derUXAkKAAAAAOAYh5O7xMRElSlTJku5r6+vjhw5kitBAQAAAAAc43By5+/vrzVr1mQpX7NmjcqWLZsrQQEAAAAAHJOjAVWu1KNHD/Xv318XL17Uww8/LEmKjY3V4MGDNXDgwFwPEAAAAABwYw4nd4MGDdKJEyf00ksvKS0tTZJUoEABDRkyRFFRUbkeIAAAAADgxmzmRjOTX8OZM2e0Y8cOFSxYUPfcc488PT1zO7a/lZSUFPn4+Cg5OVne3t7ODkc2m7MjcK6b+1QDAAAAt85ZuYHDz9xNnz5d58+fl5eXl+rWravq1av/4xM7AAAAAHA2h5O7oUOHqnTp0urevbvWrl17O2ICAAAAADjI4eTuzz//1IwZM/TXX3+padOmqlKlisaOHavExESHdz5mzBjVrVtXRYoUUalSpdS6dWvt2rXLrk7Tpk1ls9nslhdffNGuzsGDBxUeHq5ChQqpVKlSGjRokC5dumRXZ+XKlapVq5Y8PT1VuXJlRUdHZ4nnww8/VIUKFVSgQAHVr19f69evd/iYAAAAAMAZHE7u8uXLpyeffFLffPONDh06pB49emjWrFkqX768nnjiCX3zzTfKyMjIUVurVq1S79699fPPPysmJkYXL15U8+bNdfbsWbt6PXr00JEjR6xl3Lhx1rr09HSFh4crLS1Na9eu1YwZMxQdHa3hw4dbdRISEhQeHq6HHnpI8fHx6t+/v55//nktXbrUqvPFF18oMjJSI0aM0MaNG1WzZk2FhYXp2LFjjp4iAAAAALjjbnpAlUzr1q3TtGnTNGPGDJUpU0anTp1SsWLFNH36dDVt2tShto4fP65SpUpp1apVaty4saTLV+6Cg4M1fvz4bLdZvHixWrZsqcOHD6t06dKSpKlTp2rIkCE6fvy4PDw8NGTIEC1atEhbt261tuvQoYOSkpK0ZMkSSVL9+vVVt25dTZo0SZKUkZEhf39/9e3bV0OHDr1h7AyokrcwoAoAAACc5W8zoIokHT16VO+8846qVaumpk2bKiUlRQsXLlRCQoL+/PNPPf3004qIiHC43eTkZElS8eLF7cpnzZqlkiVLqnr16oqKitK5c+esdXFxcapRo4aV2ElSWFiYUlJStG3bNqtOaGioXZthYWGKi4uTJKWlpWnDhg12ddzc3BQaGmrVuVpqaqpSUlLsFgAAAABwFofnuXv88ce1dOlS3XvvverRo4c6d+5sl4wVLlxYAwcO1Ntvv+1QuxkZGerfv78aNmyo6tWrW+XPPvusAgICVLZsWW3evFlDhgzRrl279NVXX0mSEhMT7RI7SdbrzOcAr1UnJSVF58+f16lTp5Senp5tnZ07d2Yb75gxYzRq1CiHjhEAAAAAbheHk7vM2yZDQkKuWcfX11cJCQkOtdu7d29t3bpVP/30k135Cy+8YP27Ro0aKlOmjJo1a6a9e/eqUqVKjgWfi6KiohQZGWm9TklJkb+/v9PiAQAAAPDP5nBy99lnn92wjs1mU0BAQI7b7NOnjxYuXKjVq1erXLly161bv359SdKePXtUqVIl+fn5ZRnV8ujRo5IkPz8/67+ZZVfW8fb2VsGCBeXu7i53d/ds62S2cTVPT0/m9wMAAACQZzj8zN3LL7+siRMnZimfNGmS+vfv71Bbxhj16dNHX3/9tZYvX66KFSvecJv4+HhJUpkyZSRJISEh2rJli92oljExMfL29lZgYKBVJzY21q6dmJgY6+qjh4eHateubVcnIyNDsbGx171CCQAAAAB5hcPJ3fz589WwYcMs5Q888IDmzZvnUFu9e/fWf//7X82ePVtFihRRYmKiEhMTdf78eUnS3r179frrr2vDhg3av3+/vv32W3Xu3FmNGzdWUFCQJKl58+YKDAxUp06d9Ntvv2np0qUaNmyYevfubV1Ze/HFF7Vv3z4NHjxYO3fu1OTJk/Xll19qwIABViyRkZH65JNPNGPGDO3YsUO9evXS2bNn1bVrV0dPEQAAAADccQ7flnnixAn5+PhkKff29tZff/3lUFtTpkyRpCxTJkyfPl1dunSRh4eHli1bpvHjx+vs2bPy9/dX27ZtNWzYMKuuu7u7Fi5cqF69eikkJESFCxdWRESERo8ebdWpWLGiFi1apAEDBmjChAkqV66cPv30U4WFhVl12rdvr+PHj2v48OFKTExUcHCwlixZkmWQFQAAAADIixye56569ep68cUX1adPH7vyDz74QFOmTNH27dtzNcC/C+a5y1uY5w4AAADO4qzcwOErd5GRkerTp4+OHz+uhx9+WJIUGxurd99995oTjQMAAAAAbi+Hk7tu3bopNTVVb775pl5//XVJUoUKFTRlyhR17tw51wMEAAAAANyYw7dlXun48eMqWLCgvLy8cjOmvyVuy8xbuC0TAAAAzvK3uS3zSr6+vrkVBwAAAADgFjg8FQIAAAAAIO8huQMAAAAAF0ByBwAAAAAuwOHk7o8//rjmup9//vmWggEAAAAA3ByHk7vmzZvr5MmTWcrXrFmjRx99NFeCAgAAAAA4xuHkrkGDBmrevLlOnz5tla1evVotWrTQiBEjcjU4AAAAAEDOOJzcffrppypfvrwef/xxpaamasWKFQoPD9fo0aM1YMCA2xEjAAAAAOAGHE7u3NzcNGfOHOXPn18PP/ywnnjiCY0ZM0b9+vW7HfEBAAAAAHLAZowxN6q0efPmLGWnT5/WM888o/DwcPXq1csqDwoKyt0I/yacNQv9tdhszo7AuW78qQYAAABuD2flBjlK7tzc3GSz2XRl1StfZ/7bZrMpPT399kWbh5Hc5S0kdwAAAHAWZ+UG+XJSKSEh4XbHAQAAAAC4BTlK7gICAm53HAAAAACAW+DwgCpjxozRtGnTspRPmzZNY8eOzZWgAAAAAACOcTi5++ijj1SlSpUs5dWqVdPUqVNzJSgAAAAAgGMcTu4SExNVpkyZLOW+vr46cuRIrgQFAAAAAHCMw8mdv7+/1qxZk6V8zZo1Klu2bK4EBQAAAABwTI4GVLlSjx491L9/f128eFEPP/ywJCk2NlaDBw/WwIEDcz1AAAAAAMCNOZzcDRo0SCdOnNBLL72ktLQ0SVKBAgU0ZMgQRUVF5XqAAAAAAIAby9Ek5tk5c+aMduzYoYIFC+qee+6Rp6dnbsf2t8Ik5nkLk5gDAADAWfL0JObZ8fLysgZW+acndgAAAADgbA4PqJKRkaHRo0fLx8dHAQEBCggIUNGiRfX6668rIyPjdsQIAAAAALgBh6/cvfbaa/rss8/01ltvqWHDhpKkn376SSNHjtSFCxf05ptv5nqQAAAAAIDrc/iZu7Jly2rq1Kl64okn7Mq/+eYbvfTSS/rzzz9zNcC/C565y1t45g4AAADO4qzcwOHbMk+ePKkqVapkKa9SpYpOnjyZK0EBAAAAABzjcHJXs2ZNTZo0KUv5pEmTVLNmzVwJCgAAAADgGIefuRs3bpzCw8O1bNkyhYSESJLi4uJ06NAhff/997keIAAAAADgxhy+ctekSRP9/vvvevLJJ5WUlKSkpCS1adNGu3btUqNGjW5HjAAAAACAG7jpScxhjwFV8hY+1QAAAHCWPD2J+ebNm3PcYFBQ0E0HAwAAAAC4OTlK7oKDg2Wz2XSji3w2m03p6em5EhgAAAAAIOdylNwlJCTc7jgAAAAAALcgR8ldQEDA7Y4DAAAAAHALHB4tc8yYMZo2bVqW8mnTpmns2LG5EhQAAAAAwDEOJ3cfffSRqlSpkqW8WrVqmjp1qkNtjRkzRnXr1lWRIkVUqlQptW7dWrt27bKrc+HCBfXu3VslSpSQl5eX2rZtq6NHj9rVOXjwoMLDw1WoUCGVKlVKgwYN0qVLl+zqrFy5UrVq1ZKnp6cqV66s6OjoLPF8+OGHqlChggoUKKD69etr/fr1Dh0PAAAAADiLw8ldYmKiypQpk6Xc19dXR44ccaitVatWqXfv3vr5558VExOjixcvqnnz5jp79qxVZ8CAAfruu+80d+5crVq1SocPH1abNm2s9enp6QoPD1daWprWrl2rGTNmKDo6WsOHD7fqJCQkKDw8XA899JDi4+PVv39/Pf/881q6dKlV54svvlBkZKRGjBihjRs3qmbNmgoLC9OxY8ccOiYAAAAAcAaH57m75557NGLECD333HN25f/5z380YsQI7du376aDOX78uEqVKqVVq1apcePGSk5Olq+vr2bPnq127dpJknbu3KmqVasqLi5ODRo00OLFi9WyZUsdPnxYpUuXliRNnTpVQ4YM0fHjx+Xh4aEhQ4Zo0aJF2rp1q7WvDh06KCkpSUuWLJEk1a9fX3Xr1tWkSZMkSRkZGfL391ffvn01dOjQG8bOPHd5C/PcAQAAwFmclRs4fOWuR48e6t+/v6ZPn64DBw7owIEDmjZtmgYMGKAePXrcUjDJycmSpOLFi0uSNmzYoIsXLyo0NNSqU6VKFZUvX15xcXGSpLi4ONWoUcNK7CQpLCxMKSkp2rZtm1XnyjYy62S2kZaWpg0bNtjVcXNzU2hoqFXnaqmpqUpJSbFbAAAAAMBZcjRa5pUGDRqkEydO6KWXXlJaWpokqUCBAhoyZIiioqJuOpCMjAz1799fDRs2VPXq1SVdvgXUw8NDRYsWtatbunRpJSYmWnWuTOwy12euu16dlJQUnT9/XqdOnVJ6enq2dXbu3JltvGPGjNGoUaNu7mABAAAAIJc5fOXOZrNp7NixOn78uH7++Wf99ttvOnnypN0zbjejd+/e2rp1q+bMmXNL7dwpUVFRSk5OtpZDhw45OyQAAAAA/2AOX7nL5OXlpbp16+ZKEH369NHChQu1evVqlStXzir38/NTWlqakpKS7K7eHT16VH5+fladq0e1zBxN88o6V4+wefToUXl7e6tgwYJyd3eXu7t7tnUy27iap6enPD09b+6AAQAAACCXOXzlLjcZY9SnTx99/fXXWr58uSpWrGi3vnbt2sqfP79iY2Otsl27dungwYMKCQmRJIWEhGjLli12o1rGxMTI29tbgYGBVp0r28isk9mGh4eHateubVcnIyNDsbGxVh0AAAAAyMtu+spdbujdu7dmz56tb775RkWKFLGekfPx8VHBggXl4+Oj7t27KzIyUsWLF5e3t7f69u2rkJAQNWjQQJLUvHlzBQYGqlOnTho3bpwSExM1bNgw9e7d27qy9uKLL2rSpEkaPHiwunXrpuXLl+vLL7/UokWLrFgiIyMVERGhOnXqqF69eho/frzOnj2rrl273vkTAwAAAAAOcngqhFzd+TXG658+fbq6dOki6fIk5gMHDtTnn3+u1NRUhYWFafLkyXa3Sx44cEC9evXSypUrVbhwYUVEROitt95Svnz/y11XrlypAQMGaPv27SpXrpz+9a9/WfvINGnSJL399ttKTExUcHCwJk6cqPr16+foWJgKIW9hKgQAAAA4i7Nygxwld7Vq1VJsbKyKFSum0aNH65VXXlGhQoXuRHx/GyR3eQvJHQAAAJwlT89zt2PHDp09e1aSNGrUKJ05c+a2BgUAAAAAcEyOnrkLDg5W165d9eCDD8oYo3feeUdeXl7Z1r3VKREAAAAAAI7L0W2Zu3bt0ogRI7R3715t3LhRgYGBds+zWY3ZbNq4ceNtCTSv47bMvIXbMgEAAOAsefqZuyu5ubkpMTFRpUqVul0x/S2R3OUtJHcAAABwFmflBg5PhZCRkXE74gAAAAAA3IKbmudu7969Gj9+vHbs2CFJCgwMVL9+/VSpUqVcDQ4AAAAAkDM5Gi3zSkuXLlVgYKDWr1+voKAgBQUFad26dapWrZpiYmJuR4wAAAAAgBtw+Jm7+++/X2FhYXrrrbfsyocOHaoffviBAVV45i5P4Jk7AAAAOEuenufuSjt27FD37t2zlHfr1k3bt2/PlaAAAAAAAI5xOLnz9fVVfHx8lvL4+HhG0AQAAAAAJ3F4QJUePXrohRde0L59+/TAAw9IktasWaOxY8cqMjIy1wMEAAAAANyYw8/cGWM0fvx4vfvuuzp8+LAkqWzZsho0aJBefvll2f6hD3vxzF3ewjN3AAAAcJa/zSTmVzp9+rQkqUiRIrkW0N8VyV3eQnIHAAAAZ/nbTGJ+JZI6AAAAAMgbHB5QBQAAAACQ95DcAQAAAIALILkDAAAAABfgUHJ38eJFNWvWTLt3775d8QAAAAAAboJDyV3+/Pm1efPm2xULAAAAAOAmOXxb5nPPPafPPvvsdsQCAAAAALhJDk+FcOnSJU2bNk3Lli1T7dq1VbhwYbv17733Xq4FBwAAAADIGYeTu61bt6pWrVqSpN9//91une2fPnM2AAAAADiJw8ndihUrbkccAAAAAIBbcNNTIezZs0dLly7V+fPnJUnGmFwLCgAAAADgGIeTuxMnTqhZs2a699571aJFCx05ckSS1L17dw0cODDXAwQAAAAA3JjDyd2AAQOUP39+HTx4UIUKFbLK27dvryVLluRqcAAAAACAnHH4mbsffvhBS5cuVbly5ezK77nnHh04cCDXAgMAAAAA5JzDV+7Onj1rd8Uu08mTJ+Xp6ZkrQQEAAAAAHONwcteoUSPNnDnTem2z2ZSRkaFx48bpoYceytXgAAAAAAA54/BtmePGjVOzZs3066+/Ki0tTYMHD9a2bdt08uRJrVmz5nbECAAAAAC4AYev3FWvXl2///67HnzwQbVq1Upnz55VmzZttGnTJlWqVOl2xAgAAAAAuAGbYYK6XJGSkiIfHx8lJyfL29vb2eHIZnN2BM7FpxoAAADO4qzcwOHbMiXp1KlT+uyzz7Rjxw5JUmBgoLp27arixYvnanAAAAAAgJxx+LbM1atXq0KFCpo4caJOnTqlU6dOaeLEiapYsaJWr159O2IEAAAAANyAw7dl1qhRQyEhIZoyZYrc3d0lSenp6XrppZe0du1abdmy5bYEmtdxW2bewm2ZAAAAcBZn5QYOX7nbs2ePBg4caCV2kuTu7q7IyEjt2bMnV4MDAAAAAOSMw8ldrVq1rGftrrRjxw7VrFkzV4ICAAAAADgmR8nd5s2breXll19Wv3799M477+inn37STz/9pHfeeUcDBgzQgAEDHNr56tWr9fjjj6ts2bKy2WxasGCB3fouXbrIZrPZLY8++qhdnZMnT6pjx47y9vZW0aJF1b17d505cyZL/I0aNVKBAgXk7++vcePGZYll7ty5qlKligoUKKAaNWro+++/d+hYAAAAAMCZcjRaZnBwsGw2m658PG/w4MFZ6j377LNq3759jnd+9uxZ1axZU926dVObNm2yrfPoo49q+vTp1mtPT0+79R07dtSRI0cUExOjixcvqmvXrnrhhRc0e/ZsSZfvd23evLlCQ0M1depUbdmyRd26dVPRokX1wgsvSJLWrl2rZ555RmPGjFHLli01e/ZstW7dWhs3blT16tVzfDwAAAAA4Cw5GlDlwIEDOW4wICDg5gKx2fT111+rdevWVlmXLl2UlJSU5Ypeph07digwMFC//PKL6tSpI0lasmSJWrRooT/++ENly5bVlClT9NprrykxMVEeHh6SpKFDh2rBggXauXOnJKl9+/Y6e/asFi5caLXdoEEDBQcHa+rUqdnuOzU1VampqdbrlJQU+fv7M6BKHsGAKgAAAHCWPD2gSkBAQI6X3LZy5UqVKlVK9913n3r16qUTJ05Y6+Li4lS0aFErsZOk0NBQubm5ad26dVadxo0bW4mdJIWFhWnXrl06deqUVSc0NNRuv2FhYYqLi7tmXGPGjJGPj4+1+Pv758rxAgAAAMDNuKlJzA8fPqyffvpJx44dU0ZGht26l19+OVcCky7fktmmTRtVrFhRe/fu1auvvqrHHntMcXFxcnd3V2JiokqVKmW3Tb58+VS8eHElJiZKkhITE1WxYkW7OqVLl7bWFStWTImJiVbZlXUy28hOVFSUIiMjrdeZV+4AAAAAwBkcTu6io6PVs2dPeXh4qESJErJdcf+fzWbL1eSuQ4cO1r9r1KihoKAgVapUSStXrlSzZs1ybT83w9PTM8vzfwAAAADgLA5PhfCvf/1Lw4cPV3Jysvbv36+EhARr2bdv3+2I0XL33XerZMmS1nx6fn5+OnbsmF2dS5cu6eTJk/Lz87PqHD161K5O5usb1clcDwAAAAB5ncPJ3blz59ShQwe5uTm86S37448/dOLECZUpU0aSFBISoqSkJG3YsMGqs3z5cmVkZKh+/fpWndWrV+vixYtWnZiYGN13330qVqyYVSc2NtZuXzExMQoJCbndhwQAAAAAucLhDK179+6aO3duruz8zJkzio+PV3x8vCQpISFB8fHxOnjwoM6cOaNBgwbp559/1v79+xUbG6tWrVqpcuXKCgsLkyRVrVpVjz76qHr06KH169drzZo16tOnjzp06KCyZctKujw9g4eHh7p3765t27bpiy++0IQJE+yel+vXr5+WLFmid999Vzt37tTIkSP166+/qk+fPrlynAAAAABwu+VoKoQrpaenq2XLljp//rxq1Kih/Pnz261/7733ctzWypUr9dBDD2Upj4iI0JQpU9S6dWtt2rRJSUlJKlu2rJo3b67XX3/dbvCTkydPqk+fPvruu+/k5uamtm3bauLEifLy8rLqbN68Wb1799Yvv/yikiVLqm/fvhoyZIjdPufOnathw4Zp//79uueeezRu3Di1aNEix8firOFOr4WpEJwdAQAAAP6pnJUbOJzcvfHGGxo+fLjuu+8+lS5dOsuAKsuXL8/1IP8OSO7yFpI7AAAAOIuzcgOHR8t89913NW3aNHXp0uU2hAMAAAAAuBkOP3Pn6emphg0b3o5YAAAAAAA3yeHkrl+/fvrggw9uRywAAAAAgJvk8G2Z69ev1/Lly7Vw4UJVq1Yty4AqX331Va4FBwAAAADIGYeTu6JFi6pNmza3IxYAAAAAwE1yOLmbPn367YgDAAAAAHALHH7mDgAAAACQ9zh85a5ixYp2c9tdbd++fbcUEAAAAADAcQ4nd/3797d7ffHiRW3atElLlizRoEGDcisuAAAAAIADHE7u+vXrl235hx9+qF9//fWWAwIAAAAAOC7Xnrl77LHHNH/+/NxqDgAAAADggFxL7ubNm6fixYvnVnMAAAAAAAc4fFvm/fffbzegijFGiYmJOn78uCZPnpyrwQEAAAAAcsbh5K5169Z2r93c3OTr66umTZuqSpUquRUXAAAAAMABNmOMcXYQriAlJUU+Pj5KTk6Wt7e3s8PRdWar+EfgUw0AAABncVZuwCTmAAAAAOACcnxbppub23UnL5ckm82mS5cu3XJQAAAAAADH5Di5+/rrr6+5Li4uThMnTlRGRkauBAUAAAAAcEyOk7tWrVplKdu1a5eGDh2q7777Th07dtTo0aNzNTgAAAAAQM7c1DN3hw8fVo8ePVSjRg1dunRJ8fHxmjFjhgICAnI7PgAAAABADjiU3CUnJ2vIkCGqXLmytm3bptjYWH333XeqXr367YoPAAAAAJADOb4tc9y4cRo7dqz8/Pz0+eefZ3ubJgAAAADAOXI8z52bm5sKFiyo0NBQubu7X7PeV199lWvB/Z0wz13ewjx3AAAAcBZn5QY5vnLXuXPnG06FAAAAAABwjhwnd9HR0bcxDAAAAADArbip0TIBAAAAAHkLyR0AAAAAuACSOwAAAABwASR3AAAAAOACSO4AAAAAwAWQ3AEAAACACyC5AwAAAAAXQHIHAAAAAC6A5A4AAAAAXADJHQAAAAC4AJI7AAAAAHABTk3uVq9erccff1xly5aVzWbTggUL7NYbYzR8+HCVKVNGBQsWVGhoqHbv3m1X5+TJk+rYsaO8vb1VtGhRde/eXWfOnLGrs3nzZjVq1EgFChSQv7+/xo0blyWWuXPnqkqVKipQoIBq1Kih77//PtePFwAAAABuF6cmd2fPnlXNmjX14YcfZrt+3LhxmjhxoqZOnap169apcOHCCgsL04ULF6w6HTt21LZt2xQTE6OFCxdq9erVeuGFF6z1KSkpat68uQICArRhwwa9/fbbGjlypD7++GOrztq1a/XMM8+oe/fu2rRpk1q3bq3WrVtr69att+/gAQAAACAX2YwxxtlBSJLNZtPXX3+t1q1bS7p81a5s2bIaOHCgXnnlFUlScnKySpcurejoaHXo0EE7duxQYGCgfvnlF9WpU0eStGTJErVo0UJ//PGHypYtqylTpui1115TYmKiPDw8JElDhw7VggULtHPnTklS+/btdfbsWS1cuNCKp0GDBgoODtbUqVNzFH9KSop8fHyUnJwsb2/v3DotN81mc3YEzpU3PtUAAAD4J3JWbpBnn7lLSEhQYmKiQkNDrTIfHx/Vr19fcXFxkqS4uDgVLVrUSuwkKTQ0VG5ublq3bp1Vp3HjxlZiJ0lhYWHatWuXTp06ZdW5cj+ZdTL3k53U1FSlpKTYLQAAAADgLHk2uUtMTJQklS5d2q68dOnS1rrExESVKlXKbn2+fPlUvHhxuzrZtXHlPq5VJ3N9dsaMGSMfHx9r8ff3d/QQAQAAACDX5NnkLq+LiopScnKytRw6dMjZIQEAAAD4B8uzyZ2fn58k6ejRo3blR48etdb5+fnp2LFjdusvXbqkkydP2tXJro0r93GtOpnrs+Pp6Slvb2+7BQAAAACcJc8mdxUrVpSfn59iY2OtspSUFK1bt04hISGSpJCQECUlJWnDhg1WneXLlysjI0P169e36qxevVoXL1606sTExOi+++5TsWLFrDpX7iezTuZ+AAAAACCvc2pyd+bMGcXHxys+Pl7S5UFU4uPjdfDgQdlsNvXv319vvPGGvv32W23ZskWdO3dW2bJlrRE1q1atqkcffVQ9evTQ+vXrtWbNGvXp00cdOnRQ2bJlJUnPPvusPDw81L17d23btk1ffPGFJkyYoMjISCuOfv36acmSJXr33Xe1c+dOjRw5Ur/++qv69Olzp08JAAAAANwUp06FsHLlSj300ENZyiMiIhQdHS1jjEaMGKGPP/5YSUlJevDBBzV58mTde++9Vt2TJ0+qT58++u677+Tm5qa2bdtq4sSJ8vLysups3rxZvXv31i+//KKSJUuqb9++GjJkiN0+586dq2HDhmn//v265557NG7cOLVo0SLHx8JUCHkLUyEAAADAWZyVG+SZee7+7kju8hY+1QAAAHAW5rkDAAAAANw0kjsAAAAAcAEkdwAAAADgAkjuAAAAAMAFkNwBAAAAgAsguQMAAAAAF0ByBwAAAAAugOQOAAAAAFwAyR0AAAAAuACSOwAAAABwASR3AAAAAOACSO4AAAAAwAWQ3AEAAACACyC5AwAAAAAXQHIHAAAAAC6A5A4AAAAAXADJHQAAAAC4AJI7AAAAAHABJHcAAAAA4AJI7gAAAADABZDcAQAAAIALILkDAAAAABdAcgcAAAAALoDkDgAAAABcAMkdAAAAALgAkjsAAAAAcAEkdwAAAADgAkjuAAAAAMAFkNwBAAAAgAsguQMAAAAAF0ByBwAAAAAugOQOAAAAAFwAyR0AAAAAuACSOwAAAABwASR3AAAAAOACSO4AAAAAwAWQ3AEAAACAC8jTyd3IkSNls9nslipVqljrL1y4oN69e6tEiRLy8vJS27ZtdfToUbs2Dh48qPDwcBUqVEilSpXSoEGDdOnSJbs6K1euVK1ateTp6anKlSsrOjr6ThweAAAAAOSaPJ3cSVK1atV05MgRa/npp5+sdQMGDNB3332nuXPnatWqVTp8+LDatGljrU9PT1d4eLjS0tK0du1azZgxQ9HR0Ro+fLhVJyEhQeHh4XrooYcUHx+v/v376/nnn9fSpUvv6HECAAAAwK2wGWOMs4O4lpEjR2rBggWKj4/Psi45OVm+vr6aPXu22rVrJ0nauXOnqlatqri4ODVo0ECLFy9Wy5YtdfjwYZUuXVqSNHXqVA0ZMkTHjx+Xh4eHhgwZokWLFmnr1q1W2x06dFBSUpKWLFmS41hTUlLk4+Oj5ORkeXt739qB5wKbzdkROFfe/VQDAADA1TkrN8jzV+52796tsmXL6u6771bHjh118OBBSdKGDRt08eJFhYaGWnWrVKmi8uXLKy4uTpIUFxenGjVqWImdJIWFhSklJUXbtm2z6lzZRmadzDauJTU1VSkpKXYLAAAAADhLnk7u6tevr+joaC1ZskRTpkxRQkKCGjVqpNOnTysxMVEeHh4qWrSo3TalS5dWYmKiJCkxMdEusctcn7nuenVSUlJ0/vz5a8Y2ZswY+fj4WIu/v/+tHi4AAAAA3LR8zg7geh577DHr30FBQapfv74CAgL05ZdfqmDBgk6MTIqKilJkZKT1OiUlhQQPAAAAgNPk6St3VytatKjuvfde7dmzR35+fkpLS1NSUpJdnaNHj8rPz0+S5Ofnl2X0zMzXN6rj7e193QTS09NT3t7edgsAAAAAOMvfKrk7c+aM9u7dqzJlyqh27drKnz+/YmNjrfW7du3SwYMHFRISIkkKCQnRli1bdOzYMatOTEyMvL29FRgYaNW5so3MOpltAAAAAMDfQZ5O7l555RWtWrVK+/fv19q1a/Xkk0/K3d1dzzzzjHx8fNS9e3dFRkZqxYoV2rBhg7p27aqQkBA1aNBAktS8eXMFBgaqU6dO+u2337R06VINGzZMvXv3lqenpyTpxRdf1L59+zR48GDt3LlTkydP1pdffqkBAwY489ABAAAAwCF5+pm7P/74Q88884xOnDghX19fPfjgg/r555/l6+srSXr//ffl5uamtm3bKjU1VWFhYZo8ebK1vbu7uxYuXKhevXopJCREhQsXVkREhEaPHm3VqVixohYtWqQBAwZowoQJKleunD799FOFhYXd8eMFAAAAgJuVp+e5+zthnru8hU81AAAAnIV57gAAAAAANy1P35YJAHkJV8SdHQFcDX3K2REAcDVcuQMAAAAAF0ByBwAAAAAugOQOAAAAAFwAyR0AAAAAuACSOwAAAABwASR3AAAAAOACSO4AAAAAwAWQ3AEAAACACyC5AwAAAAAXQHIHAAAAAC6A5A4AAAAAXADJHQAAAAC4AJI7AAAAAHABJHcAAAAA4AJI7gAAAADABZDcAQAAAIALILkDAAAAABdAcgcAAAAALoDkDgAAAABcAMkdAAAAALgAkjsAAAAAcAEkdwAAAADgAkjuAAAAAMAFkNwBAAAAgAsguQMAAAAAF0ByBwAAAAAugOQOAAAAAFwAyR0AAAAAuACSOwAAAABwASR3AAAAAOACSO4AAAAAwAWQ3AEAAACACyC5AwAAAAAXQHIHAAAAAC6A5A4AAAAAXADJ3VU+/PBDVahQQQUKFFD9+vW1fv16Z4cEAAAAADdEcneFL774QpGRkRoxYoQ2btyomjVrKiwsTMeOHXN2aAAAAABwXSR3V3jvvffUo0cPde3aVYGBgZo6daoKFSqkadOmOTs0AAAAALiufM4OIK9IS0vThg0bFBUVZZW5ubkpNDRUcXFxWeqnpqYqNTXVep2cnCxJSklJuf3B4oZ4G4DcR78Cchd9CreDj4+zI3Cu//+T3OkycwJjzB3dL8nd//vrr7+Unp6u0qVL25WXLl1aO3fuzFJ/zJgxGjVqVJZyf3//2xYjcu6f/sUG3A70KyB30aeA3JfX+tXp06flcweDIrm7SVFRUYqMjLReZ2Rk6OTJkypRooRsNpsTI3O+lJQU+fv769ChQ/L29nZ2OIBLoF8BuYs+BeQ++tX/GGN0+vRplS1b9o7ul+Tu/5UsWVLu7u46evSoXfnRo0fl5+eXpb6np6c8PT3tyooWLXo7Q/zb8fb2/sd3bCC30a+A3EWfAnIf/eqyO3nFLhMDqvw/Dw8P1a5dW7GxsVZZRkaGYmNjFRIS4sTIAAAAAODGuHJ3hcjISEVERKhOnTqqV6+exo8fr7Nnz6pr167ODg0AAAAArovk7grt27fX8ePHNXz4cCUmJio4OFhLlizJMsgKrs/T01MjRozIctsqgJtHvwJyF30KyH30K+ezmTs9PicAAAAAINfxzB0AAAAAuACSOwAAAABwASR3AAAAAOACSO6crEKFCho/fryzw/jb2b9/v2w2m+Lj42/7vniP/l54v24OfQrXw3t2c+hXuBber5tDn8oBAxMREWEkmZ49e2ZZ99JLLxlJJiIiIkdtJSQkGElm06ZNOap/7Ngxc/bs2RzVbdmypQkLC8t23erVq40k89tvv+WorWtZsWKFkWROnTp1S+1c7dy5c6ZYsWKmRIkS5sKFCw5tGxERYVq1amVXdunSJXPkyBFz8eLFXItx+vTpxsfHJ0u5I+9Rbpk0aZIJCAgwnp6epl69embdunV3dP+3ij71P/Qpnyzld7pPrVq1yrRs2dKUKVPGSDJff/31Hdt3bqJf/Q/9yidL+Z3uV//+979NnTp1jJeXl/H19TWtWrUyO3fuvGP7zw30qf+hT/lkKb/TfWry5MmmRo0apkiRIqZIkSKmQYMG5vvvv3e4Ha7c/T9/f3/NmTNH58+ft8ouXLig2bNnq3z58rm+v7S0NEmSr6+vChUqlKNtunfvrpiYGP3xxx9Z1k2fPl116tRRUFBQrsZ5s4wxunTpkvV6/vz5qlatmqpUqaIFCxbccvvu7u7y8/NTvny3fzYPR96j3PDFF18oMjJSI0aM0MaNG1WzZk2FhYXp2LFjdyyG3ECfyl30qZt39uxZ1axZUx9++OEd2+ftQr/KXfSrm7dq1Sr17t1bP//8s2JiYnTx4kU1b95cZ8+evWMx5Ab6VO6iT928cuXK6a233tKGDRv066+/6uGHH1arVq20bds2xxrK5aTzbynzl4Hq1aub//73v1b5rFmzTFBQkGnVqpX1y83ixYtNw4YNjY+PjylevLgJDw83e/bssbaRZLc0adLEbh9vvPGGKVOmjKlQoYIxxpiAgADz/vvvG2Mu/2qSP39+s3r1aqu9sWPHGl9fX5OYmGguXrxoSpcubV5//XW7+E+fPm28vLzMlClTjDHG/Pjjj+bBBx80BQoUMOXKlTN9+/Y1Z86csepfuHDBDB482JQrV854eHiYSpUqmU8//dT61enKJfO4L1y4YPr27Wt8fX2Np6enadiwoVm/fr3VZuYvPt9//72pVauWyZ8/v1mxYoW1vmnTpmbq1KlmypQp5pFHHsnyHmzdutWEh4ebIkWKGC8vL/Pggw+aPXv2mBEjRmSJacWKFXa/kKWnp5u77rrLTJ482a7NjRs3GpvNZvbv32+MMebdd9811atXN4UKFTLlypUzvXr1MqdPn7aL/8plxIgRWd4jY4w5cOCAeeKJJ0zhwoVNkSJFzFNPPWUSExOt9SNGjDA1a9Y0M2fONAEBAcbb29u0b9/epKSkZDnu7NSrV8/07t3bep2enm7Kli1rxowZk6Pt8wL6FH0qL/WpK+lvfuWOfkW/yov9ypjLVzkkmVWrVt3U9s5An6JP5eU+ZYwxxYoVM59++qlD25Dcmf91vPfee880a9bMKm/WrJl5//337Tr3vHnzzPz5883u3bvNpk2bzOOPP25q1Khh0tPTjTHGrF+/3kgyy5YtM0eOHDEnTpyw9uHl5WU6depktm7darZu3WqMyfrBGTRokAkICDBJSUlm48aNxsPDw3zzzTd26ytVqmQyMjKssmnTppmCBQuapKQks2fPHlO4cGHz/vvvm99//92sWbPG3H///aZLly5W/aefftr4+/ubr776yuzdu9csW7bMzJkzx1y6dMnMnz/fSDK7du0yR44cMUlJScYYY15++WVTtmxZ8/3335tt27aZiIgIU6xYMev4MjtHUFCQ+eGHH8yePXusdXv27DGenp7m5MmT5sSJE6ZAgQJWhzPGmD/++MMUL17ctGnTxvzyyy9m165dZtq0aWbnzp3m9OnT5umnnzaPPvqoOXLkiDly5IhJTU3NcvvDK6+8Yh588EG793XgwIF2Ze+//75Zvny5SUhIMLGxsea+++4zvXr1MsYYk5qaasaPH2+8vb2t/WR2/Cvfo/T0dBMcHGwefPBB8+uvv5qff/7Z1K5d2/oSN+Zy5/by8jJt2rQxW7ZsMatXrzZ+fn7m1VdfveZnMFNqaqpxd3fP8sdn586dzRNPPHHD7fMK+hR9Kq/0qau5QnJHv6Jf5bV+ZYwxu3fvNpLMli1bbmp7Z6BP0afyap+6dOmS+fzzz42Hh4fZtm2bQ9uS3Jn/de5jx44ZT09Ps3//frN//35ToEABc/z4cbvOfbXjx4/bfZld657riIgIU7p0aZOammpXfnXnTk1NNcHBwebpp582gYGBpkePHnb1d+zYYf16kalRo0bmueeeM8YY0717d/PCCy/YbfPjjz8aNzc3c/78ebNr1y4jycTExGR7PNndc33mzBmTP39+M2vWLKssLS3NlC1b1owbN85uuwULFmRp89VXXzWtW7e2Xrdq1cr6VcQYY6KiokzFihVNWlpatjFld8/11ed506ZNxmazmQMHDhhjjPVrTuavWdmZO3euKVGihPX6WvdcX/ke/fDDD8bd3d0cPHjQWr9t2zYjyfola8SIEaZQoUJ2v9QMGjTI1K9f/5qxZPrzzz+NJLN27Vq78kGDBpl69erdcPu8gj71P/Qpnyz17mSfuporJHf0K/pVXutX6enpJjw83DRs2NDhbZ2JPvU/9CmfLPWc0ac2b95sChcubNzd3Y2Pj49ZtGhRjrfNxDN3V/D19VV4eLiio6M1ffp0hYeHq2TJknZ1du/erWeeeUZ33323vL29VaFCBUnSwYMHb9h+jRo15OHhcd06Hh4emjVrlubPn68LFy7o/ffft1tfpUoVPfDAA5o2bZokac+ePfrxxx/VvXt3SdJvv/2m6OhoeXl5WUtYWJgyMjKUkJCg+Ph4ubu7q0mTJjk9Ldq7d68uXryohg0bWmX58+dXvXr1tGPHDru6derUsXudnp6uGTNm6LnnnrPKnnvuOUVHRysjI0OSFB8fr0aNGil//vw5julqwcHBqlq1qmbPni3p8rMAx44d01NPPWXVWbZsmZo1a6a77rpLRYoUUadOnXTixAmdO3cux/vZsWOH/P395e/vb5UFBgaqaNGidueiQoUKKlKkiPW6TJkyf7tn5nIDfSp79Kn/oU85jn6VPfrV/9zpftW7d29t3bpVc+bMcXjbvIA+lT361P/cqT513333KT4+XuvWrVOvXr0UERGh7du353h7iakQsujWrZuio6M1Y8YMdevWLcv6xx9/XCdPntQnn3yidevWad26dZL+94Ds9RQuXDhHMaxdu1aSdPLkSZ08eTLL+u7du2v+/Pk6ffq0pk+frkqVKlmd9cyZM+rZs6fi4+Ot5bffftPu3btVqVIlFSxYMEcx3Kyrj3Hp0qX6888/1b59e+XLl0/58uVThw4ddODAAcXGxkpSrsXUsWNHq3PPnj1bjz76qEqUKCHp8tC5LVu2VFBQkObPn68NGzZYgyvk5L1z1NVfVDabzfoyu56SJUvK3d1dR48etSs/evSo/Pz8cjXGO4U+dWvoU5fdbJ9yVfSrW0O/uiw3+lWfPn20cOFCrVixQuXKlcvN8O4o+tStoU9ddqt9ysPDQ5UrV1bt2rU1ZswY1axZUxMmTHAoBpK7qzz66KNKS0vTxYsXFRYWZrfuxIkT2rVrl4YNG6ZmzZqpatWqOnXqlF2dzF9m0tPTb2r/e/fu1YABA/TJJ5+ofv36ioiIyPKhePrpp+Xm5qbZs2dr5syZ6tatm2w2mySpVq1a2r59uypXrpxl8fDwUI0aNZSRkaFVq1Zlu//s4q9UqZI8PDy0Zs0aq+zixYv65ZdfFBgYeN3j+eyzz9ShQwe7L5v4+Hh16NBBn332mSQpKChIP/74oy5evHjNmHJyPp999llt3bpVGzZs0Lx589SxY0dr3YYNG5SRkaF3331XDRo00L333qvDhw87vJ+qVavq0KFDOnTokFW2fft2JSUl3fBc5ISHh4dq165tffFJUkZGhmJjYxUSEnLL7TsDfYo+dT23u0+5KvoV/ep67kS/MsaoT58++vrrr7V8+XJVrFgxV9p1FvoUfep6nPX/qoyMDKWmpjq2kcM3crqgq+/pTU5ONsnJydbrzHuu09PTTYkSJcxzzz1ndu/ebWJjY03dunXtnuG4ePGiKViwoHnjjTdMYmKi9UBqdvcNG2N/P++lS5dMgwYNTNu2bY0xxhw+fNiUKFHCuq/5St27dzfFihUz7u7u5s8//7TKf/vtN1OwYEHTu3dvs2nTJvP777+bBQsW2I2+2KVLF+Pv72++/vprs2/fPrNixQrzxRdfGGMuP9xqs9lMdHS0OXbsmPVQab9+/UzZsmXN4sWL7R6oPXnypDEm+3u1jx07ZvLnz28WL16cJf7vv//eeHp6mhMnTpi//vrLlChRwnqg9vfffzczZ8605st58803Tfny5c3OnTvN8ePHTVpa2jXvbW/YsKGpWbOmKVKkiDl37pxVHh8fbySZ8ePHm71795qZM2eau+66yy7mNWvWWA9DHz9+3Jrb5Mr3KCMjwwQHB5tGjRqZDRs2mHXr1mX7QG3NmjXt4nr//fdNQEBAlvOQnTlz5hhPT08THR1ttm/fbl544QVTtGhRuxGZ8jr6FH3KmLzTp06fPm02bdpkNm3aZCSZ9957z2zatMl6RuPvgn5FvzIm7/SrXr16GR8fH7Ny5UprIIojR47YHU9eR5+iTxmTd/rU0KFDzapVq0xCQoLZvHmzGTp0qLHZbOaHH37I0faZSO7MtTtepisfqI2JiTFVq1Y1np6eJigoyKxcuTLLA/qffPKJ8ff3N25ublmGwr3alR+cUaNGmTJlypi//vrLWj9//nzj4eFh4uPj7bZbu3atkWRatGiRpc3169ebRx55xHh5eZnChQuboKAg8+abb1rrz58/bwYMGGDKlCljPDw8TOXKlc20adOs9aNHjzZ+fn7GZrNZx33+/HnTt29fU7JkyesOhXtl537nnXdM0aJFs31QNjU11RQtWtRMmDDBGHP5S6l58+amUKFCpkiRIqZRo0Zm7969xpjLXxKZx6NshsK90uTJk40k07lz5yz7fO+990yZMmVMwYIFTVhYmJk5c2aWmF988UVTokSJXBkK90qOdG5jjPnggw9M+fLljYeHh6lXr575+eefc7xtXkCfok9lygt9KruhrqWcT06cV9Cv6FeZ8kK/yq5PSTLTp0/P0fZ5AX2KPpUpL/Spbt26mYCAAOPh4WF8fX1Ns2bNHE7sjDHGZowxjl3rAwAAAADkNTxzBwAAAAAugOQOuIMOHjxoN0zx1UtOhlQG8D/0KSD30a+A3HUn+xS3ZQJ30KVLl7R///5rrq9QoYLy5ct35wIC/uboU0Duo18BuetO9imSOwAAAABwAdyWCQAAAAAugOQOAAAAAFwAyR0AAAAAuACSOwAAAABwASR3AADkkqZNm6p///45rr9y5UrZbDYlJSXdtpgAAP8cJHcAAKfr0qWLbDab3nrrLbvyBQsWyGazOdRWhQoVNH78+FyMDgCAvweSOwBAnlCgQAGNHTtWp06dcnYoDktLS3N2CLfk4sWLzg4BAJALSO4AAHlCaGio/Pz8NGbMmOvW++mnn9SoUSMVLFhQ/v7+evnll3X27FlJl2+LPHDggAYMGCCbzSabzSZjjHx9fTVv3jyrjeDgYJUpU8auTU9PT507d06SdPDgQbVq1UpeXl7y9vbW008/raNHj1r1R44cqeDgYH366aeqWLGiChQokG2sixYtko+Pj2bNmpWjc3DixAk988wzuuuuu1SoUCHVqFFDn3/+ubV+5syZKlGihFJTU+22a926tTp16mS9/uabb1SrVi0VKFBAd999t0aNGqVLly5Z6202m6ZMmaInnnhChQsX1ptvvqlTp06pY8eO8vX1VcGCBXXPPfdo+vTpOYobAJA3kNwBAPIEd3d3/fvf/9YHH3ygP/74I9s6e/fu1aOPPqq2bdtq8+bN+uKLL/TTTz+pT58+kqSvvvpK5cqV0+jRo3XkyBEdOXJENptNjRs31sqVKyVJp06d0o4dO3T+/Hnt3LlTkrRq1SrVrVtXhQoVUkZGhlq1aqWTJ09q1apViomJ0b59+9S+fXu7WPbs2aP58+frq6++Unx8fJZYZ8+erWeeeUazZs1Sx44dc3QOLly4oNq1a2vRokXaunWrXnjhBXXq1Enr16+XJD311FNKT0/Xt99+a21z7NgxLVq0SN26dZMk/fjjj+rcubP69eun7du366OPPlJ0dLTefPNNu32NHDlSTz75pLZs2aJu3brpX//6l7Zv367Fixdrx44dmjJlikqWLJmjuAEAeUM+ZwcAAECmJ598UsHBwRoxYoQ+++yzLOvHjBmjjh07WoOW3HPPPZo4caKaNGmiKVOmqHjx4nJ3d1eRIkXk5+dnbde0aVN99NFHkqTVq1fr/vvvl5+fn1auXKkqVapo5cqVatKkiSQpNjZWW7ZsUUJCgvz9/SVdvmJWrVo1/fLLL6pbt66ky7dizpw5U76+vlni/PDDD/Xaa6/pu+++s9rNibvuukuvvPKK9bpv375aunSpvvzyS9WrV08FCxbUs88+q+nTp+upp56SJP33v/9V+fLl1bRpU0nSqFGjNHToUEVEREiS7r77br3++usaPHiwRowYYbX97LPPqmvXrtbrgwcP6v7771edOnUkXX52EQDw98KVOwBAnjJ27FjNmDFDO3bsyLLut99+U3R0tLy8vKwlLCxMGRkZSkhIuGabTZo00fbt23X8+HGtWrVKTZs2VdOmTbVy5UpdvHhRa9eutZKjHTt2yN/f30rsJCkwMFBFixa1iykgICDbxG7evHkaMGCAYmJiHErsJCk9PV2vv/66atSooeLFi8vLy0tLly7VwYMHrTo9evTQDz/8oD///FOSFB0dbQ1Ik3mORo8ebXeOevTooSNHjli3nUqykrhMvXr10pw5cxQcHKzBgwdr7dq1DsUOAHA+kjsAQJ7SuHFjhYWFKSoqKsu6M2fOqGfPnoqPj7eW3377Tbt371alSpWu2WZmsrRq1Sq75G7VqlX65ZdfdPHiRT3wwAMOxVm4cOFsy++//375+vpq2rRpMsY41Obbb7+tCRMmaMiQIVqxYoXi4+MVFhZmN2DL/fffr5o1a2rmzJnasGGDtm3bpi5duljrz5w5o1GjRtmdoy1btmj37t12zwZeHf9jjz1mPa94+PBhNWvWzO4qIgAg7+O2TABAnvPWW28pODhY9913n115rVq1tH37dlWuXPma23p4eCg9Pd2uzGazqVGjRvrmm2+0bds2PfjggypUqJBSU1P10UcfqU6dOlayU7VqVR06dEiHDh2yrt5t375dSUlJCgwMvGHslSpV0rvvvqumTZvK3d1dkyZNyvFxr1mzRq1atdJzzz0nScrIyNDvv/+eZb/PP/+8xo8frz///FOhoaF2Vxlr1aqlXbt2XfccXYuvr68iIiIUERGhRo0aadCgQXrnnXccbgcA4BxcuQMA5Dk1atRQx44dNXHiRLvyIUOGaO3aterTp4/i4+O1e/duffPNN9aAKtLlZ8VWr16tP//8U3/99ZdV3rRpU33++ecKDg6Wl5eX3Nzc1LhxY82aNcvu9snQ0FBr/xs3btT69evVuXNnNWnSJMutjNdy7733asWKFZo/f75Dk5rfc889iomJ0dq1a7Vjxw717NnTbpTOTM8++6z++OMPffLJJ9ZAKpmGDx+umTNnatSoUdq2bZt27NihOXPmaNiwYdfd9/Dhw/XNN99oz5492rZtmxYuXKiqVavmOHYAgPOR3AEA8qTRo0crIyPDriwoKEirVq3S77//rkaNGun+++/X8OHDVbZsWbvt9u/fr0qVKtk9E9ekSROlp6dbz9ZJlxO+q8tsNpu++eYbFStWTI0bN1ZoaKjuvvtuffHFFw7Ff99992n58uX6/PPPNXDgwBxtM2zYMNWqVUthYWFq2rSp/Pz81Lp16yz1fHx81LZtW3l5eWVZHxYWpoULF+qHH35Q3bp11aBBA73//vsKCAi47r49PDwUFRWloKAgNW7cWO7u7pozZ05ODxcAkAfYjKMPBAAAAKdr1qyZqlWrluXqJgDgn4vkDgCAv5FTp05p5cqVateunbZv357luUQAwD8XA6oAAPA3cv/99+vUqVMaO3YsiR0AwA5X7gAAAADABTCgCgAAAAC4AJI7AAAAAHABJHcAAAAA4AJI7gAAAADABZDcAQAAAIALILkDAAAAABdAcgcAAAAALoDkDgAAAABcwP8Binx+rd+7B7sAAAAASUVORK5CYII=", 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    " ] @@ -315,76 +267,118 @@ "source": [ "import matplotlib.pyplot as plt\n", "\n", - "layers = list(cycles_dict.keys())\n", - "cycles = list(cycles_dict.values())\n", "fig = plt.figure(figsize = (10, 5))\n", - "plt.bar(layers, cycles, color ='blue', width = 0.3)\n", - "plt.xlabel(\"Network Layers\")\n", - "plt.ylabel(\"Clock Cycles\")\n", - "plt.title(\"Estimated clock cycles for each network layer\")\n", + "plt.bar(cycles_dict.keys(), cycles_dict.values(), color ='blue', width = 0.3)\n", + "plt.xlabel(\"Network layers\")\n", + "plt.ylabel(\"Number of clock cycles\")\n", + "plt.title(\"Estimated no. of clock cycles for each network layer\")\n", "plt.show()" ] }, { - "cell_type": "code", - "execution_count": 8, + "cell_type": "markdown", "metadata": {}, - "outputs": [], "source": [ - "res_dict = []\n", - "res_dict = res_estimation(model)" + "We observe that the bottleneck in the execution of the model on hardware would come from the execution of the first layer which takes estimated 38400 clock cycles to execute one set of its inputs.\n", + "\n", + "No matter how quickly the other layers execute, the throughput will be defined by the first layer's execution latency.\n", + "\n", + "Let's have a look now at the estimated resources per layer by calling another analysis pass.\n", + "The keys are again the layer names, but the values are now a dictionary with the resource estimates per layer." ] }, { "cell_type": "code", - "execution_count": 9, + "execution_count": 8, "metadata": {}, "outputs": [ { "data": { - "image/png": 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etHz5cg0cOFArV67U+fPnncYnJCRY67qW3bt3a/PmzcqfP3+G/Wk3YDhw4IAKFCggLy8vp/6HH374BnuXvbLrFvj58uVT3bp1NWXKFA0dOlTS5dMYXV1d1aJFC2tc2jVCo0aN0r59+5SSkmL1ZeYUs8zYvXu3EhISFBAQkGF/2nsQGRmpli1bavDgwRo2bJjq1KmjJ598Us8++6zc3d2zpZYhQ4aoefPmKl26tMqXL6+GDRuqXbt2CgsLkyTt2bNHxhi99dZbeuutt65Zb6FChXTgwAFVrVo1Xf+tfGYOHDhwzXWUKVNGv/76q1Obq6urChcufMP1Hj9+XKdPn9aYMWM0ZsyYDMekvQ+SNGHCBH388cfasWOHU0i+8q6ue/fuVcGCBeXv73/D7V/9O0CS8uTJk+4aw8wunydPHkmylk8L2tc79TghIcFaLiMuLi6KiIjQsmXLJF0OZrVq1VLNmjWVkpKiVatWKTAwUCdPnnQKZtf6HKSd4n3gwAGVL1/eas/ozrhp2rVrJ1dXV23fvl1BQUHXHHcjBw8e1IABA/Tjjz+me42v/INW/fr1VaBAAU2cOFF169ZVamqqvvvuOzVv3lze3t6Sbu61vd4+AsgaghnwgAoICNCmTZs0b948zZ07V3PnztW4cePUvn17TZgw4abX6+LikqV28/+vSdi7d6/q1q2rMmXK6JNPPlFwcLDc3Nw0Z84cDRs2LFM3WUhNTVX9+vX16quvZthfunTpTO7FrXN3d3e6+P5KaaHzyqMkt6p169bq2LGjNm3apPDwcE2ZMkV169a1rquRLl/k/9Zbb6lTp04aOnSo/P39lSNHDvXs2fOGr6/D4cjw+pErw510+T0ICAjQxIkTM1xPWmhO+x64VatW6aefftK8efPUqVMnffzxx1q1alW60JwZV9dSu3Zt7d27Vz/88IN++eUXffXVVxo2bJg+//xzdenSxdrnPn36KCoqKsN1ZuXrJW63K494Xk/afj333HPX/Ad2Wjj99ttv1aFDBz355JPq27evAgIC5OLiotjYWO3du/em6rzRXL/V5dP278MPP3S6Bu5Kmfn81KxZU++8844uXLigZcuW6Y033pCfn5/Kly+vZcuWWdeuXhnMsup61yC2aNFC33zzjUaMGKHY2NibWn9KSop1fdprr72mMmXKyNPTU3/99Zc6dOjgNK9dXFz07LPP6ssvv9SoUaO0fPlyHT582Onurzfz2mbmOksAmUMwAx5gbm5uatasmZo1a6bU1FS9+OKL+uKLL/TWW2+pVKlSd/RLjX/66SclJSXpxx9/dPqLeUZ3h7tWXSVLltTZs2dv+D1RRYsW1cKFC3X27Fmnf2Rk9W5oN9rGtdaX1n6zpy5l5Mknn1S3bt2s0xl37dql/v37O42ZNm2aHnvsMY0dO9ap/fTp004BLiN58uTJ8FS0tKM+aUqWLKkFCxaoRo0amfoHW7Vq1VStWjW98847mjRpktq2bavJkyerS5cu163l6jtoXrx4UUeOHEk31t/fXx07dlTHjh119uxZ1a5dW4MGDVKXLl1UokQJSVLOnDkz9ZnJ6JTIW/nMpL3/O3fu1OOPP55uvTf7+cifP7+8vb2VkpJyw/2aNm2aSpQooRkzZjjNq6tPWSxZsqTmzZunkydPZuqo2e2Udpqkj4/PDffver/DatWqpYsXL+q7777TX3/9ZQWw2rVrW8GsdOnSVkCTrj2vd+zYYfVn1ksvvaRSpUppwIAB8vX1Vb9+/TK9bJotW7Zo165dmjBhgtq3b2+1X+sU9fbt2+vjjz/WTz/9pLlz5yp//vxOf5TIymsLIPtxjRnwgDpx4oTT8xw5clh/RU+7jX3a99HcidvIp/2V/Mq/qickJGjcuHHpxnp6emZYU6tWrbRy5UrNmzcvXd/p06et69kaN26s5ORkp1vxp6Sk6LPPPrvV3bA0btxYq1at0vr169PVMXHiRIWHh9/S6UtX8/PzU1RUlKZMmaLJkyfLzc1NTz75pNMYFxeXdEctpk6dmu7W7BkpWbKkduzYoePHj1ttv/32W7pbaLdq1UopKSnWKZVXSk5Ott63U6dOpasl7S/0V3+NQka1pF0blGbMmDHpjphd/Rn38vJSqVKlrPUHBASoTp06+uKLLzIMdVfua9r7uWbNGqf+ax0ZzIzKlSsrICBAn3/+udM+z507V9u3b1eTJk1uar0uLi5q2bKlpk+frt9//z1d/5X7ldG8W716tVauXOm0TMuWLWWMyfBrGTJ7JCy7VKpUSSVLltRHH32ks2fPpuu/cv+u9zusatWqypkzp95//335+/urXLlyki4HtlWrVikuLi7d0bLGjRtrzZo1Tq/PuXPnNGbMGBUrVkwhISFZ2pe33npLffr0Uf/+/dN9NUhmZPT+GWOsrz25WlhYmMLCwvTVV19p+vTpat26tVxd//c3+qy8tgCyH0fMgPvU3Llzrb/iXql69eoqUaKEunTpopMnT+rxxx9X4cKFdeDAAX322WcKDw+3rpcIDw+Xi4uL3n//fSUkJMjd3d36nrHs1qBBA+sIXrdu3XT27Fl9+eWXCggISPeP5kqVKmn06NF6++23VapUKQUEBOjxxx9X37599eOPP6pp06bq0KGDKlWqpHPnzmnLli2aNm2a9u/fr3z58qlZs2aqUaOG+vXrp/379yskJEQzZszI1A1GrjR9+vQMX+Po6Gj169dPU6dOVe3atdWtWzeVKVNGhw8f1vjx43XkyJEMA+eteuaZZ/Tcc89p1KhRioqKSvdlxk2bNtWQIUPUsWNHVa9eXVu2bNHEiROtI0fX06lTJ33yySeKiopS586ddezYMX3++ecqV66c03czRUZGqlu3boqNjdWmTZvUoEED5cyZU7t379bUqVM1YsQIPfXUU5owYYJGjRqlf/3rXypZsqTOnDmjL7/8Uj4+PmrcuPF1a+nSpYteeOEFtWzZUvXr19dvv/2mefPmpTvqFxISojp16qhSpUry9/fXunXrNG3aNPXo0cMaM3LkSNWsWVOhoaHq2rWrSpQooaNHj2rlypX6888/re94e/XVV/Wf//xHDRs21CuvvGLdLr9o0aLavHnzDV+/jKSFgo4dOyoyMlJt2rSxbpdfrFgx9erV66bWK12+5fzixYtVtWpVde3aVSEhITp58qQ2bNigBQsW6OTJk5IufyZmzJihf/3rX2rSpIn27dunzz//XCEhIU7/MH/sscfUrl07ffrpp9q9e7caNmyo1NRULVu2TI899pjTa3q75ciRQ1999ZUaNWqkcuXKqWPHjipUqJD++usvLV68WD4+Pvrpp58kXf5dIV3+yoLWrVsrZ86catasmTw9PZU7d25VqlRJq1atsr7DTLp8xOzcuXM6d+5cumDWr18/fffdd2rUqJFefvll+fv7a8KECdq3b5+mT5+eqVNNr/bhhx8qISFBMTEx8vb2ztIXy5cpU0YlS5ZUnz599Ndff8nHx0fTp0+/7vV87du3V58+fSQp3bay8toCuA3u9G0gAdxe17tdvq64LfK0adNMgwYNTEBAgHFzczNFihQx3bp1M0eOHHFa35dffmlKlChhXFxcnG7TfK3b5V99C/mMbhNuzP9utXz8+HGr7ccffzRhYWHGw8PDFCtWzLz//vvm66+/Tne76/j4eNOkSRPj7e1tJDnVcebMGdO/f39TqlQp4+bmZvLly2eqV69uPvroI6fb+J84ccK0a9fO+Pj4GF9fX9OuXTuzcePGLN0u/1qPtFtp//nnn6ZLly6mUKFCxtXV1fj7+5umTZuaVatWXXf9Wb1dfprExESTK1cuI8l8++236fovXLhg/u///s8UKFDA5MqVy9SoUcOsXLky3XuZ0e3yjTHm22+/NSVKlDBubm4mPDzczJs3L93t8tOMGTPGVKpUyeTKlct4e3ub0NBQ8+qrr5rDhw8bYy7fprtNmzamSJEixt3d3QQEBJimTZuadevW3XA/U1JSzGuvvWby5ctncufObaKiosyePXvS3S7/7bffNlWqVDF+fn4mV65cpkyZMuadd95x+hwYY8zevXtN+/btTVBQkMmZM6cpVKiQadq0qZk2bZrTuM2bN5vIyEjj4eFhChUqZIYOHWrGjh1707fLT/P999+bihUrGnd3d+Pv72/atm1r/vzzT6cx0dHRxtPT84avzZWOHj1qYmJiTHBwsMmZM6cJCgoydevWNWPGjLHGpKammnfffdcULVrUuLu7m4oVK5rZs2dn+L4mJyebDz/80JQpU8a4ubmZ/Pnzm0aNGpn169dbY3SNr4m4+r3JyLV+h1zr87hx40bTokULkzdvXuPu7m6KFi1qWrVqZRYuXOg0bujQoaZQoUImR44c6d6rvn37Gknm/fffd1qmVKlSRpLZu3dvujr37t1rnnrqKePn52c8PDxMlSpVzOzZszO1L8Zk/FlISUkxbdq0Ma6urmbWrFk3fI2uvF3+tm3bTL169YyXl5fJly+f6dq1q/UVBRn9Ljty5IhxcXExpUuXvuZ2MvPaZvQ7HMCtcRjDtwECAAA8CP7++28VKFBAAwYMuObdSAHYg2vMAAAAHhDjx49XSkqK2rVrZ3cpAK7CNWYAAAD3uUWLFmnbtm1655139OSTT6pYsWJ2lwTgKpzKCAAAcJ+rU6eOVqxYoRo1aujbb79VoUKF7C4JwFUIZgAAAABgM64xAwAAAACbEcwAAAAAwGbc/ENSamqqDh8+LG9vb+sLJgEAAAA8eIwxOnPmjAoWLHhTXxx/swhmkg4fPqzg4GC7ywAAAABwlzh06JAKFy58x7ZHMJPk7e0t6fKL7+PjY3M1AAAAAOySmJio4OBgKyPcKQQzyTp90cfHh2AGAAAA4I5f4sTNPwAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbOZqdwFIzzHYYXcJtjIDjd0lAAAAAHcUR8wAAAAAwGZ3TTB777335HA41LNnT6vtwoULiomJUd68eeXl5aWWLVvq6NGjTssdPHhQTZo0Ue7cuRUQEKC+ffsqOTn5DlcPAAAAADfvrghma9eu1RdffKGwsDCn9l69eumnn37S1KlTFRcXp8OHD6tFixZWf0pKipo0aaKLFy9qxYoVmjBhgsaPH68BAwbc6V0AAAAAgJtmezA7e/as2rZtqy+//FJ58uSx2hMSEjR27Fh98sknevzxx1WpUiWNGzdOK1as0KpVqyRJv/zyi7Zt26Zvv/1W4eHhatSokYYOHaqRI0fq4sWL19xmUlKSEhMTnR4AAAAAYBfbg1lMTIyaNGmievXqObWvX79ely5dcmovU6aMihQpopUrV0qSVq5cqdDQUAUGBlpjoqKilJiYqK1bt15zm7GxsfL19bUewcHB2bxXAAAAAJB5tgazyZMna8OGDYqNjU3XFx8fLzc3N/n5+Tm1BwYGKj4+3hpzZShL60/ru5b+/fsrISHBehw6dOgW9wQAAAAAbp5tt8s/dOiQXnnlFc2fP18eHh53dNvu7u5yd3e/o9sEAAAAgGux7YjZ+vXrdezYMT3yyCNydXWVq6ur4uLi9Omnn8rV1VWBgYG6ePGiTp8+7bTc0aNHFRQUJEkKCgpKd5fGtOdpYwAAAADgbmdbMKtbt662bNmiTZs2WY/KlSurbdu21s85c+bUwoULrWV27typgwcPKiIiQpIUERGhLVu26NixY9aY+fPny8fHRyEhIXd8nwAAAADgZth2KqO3t7fKly/v1Obp6am8efNa7Z07d1bv3r3l7+8vHx8fvfTSS4qIiFC1atUkSQ0aNFBISIjatWunDz74QPHx8XrzzTcVExPDqYoAAAAA7hm2BbPMGDZsmHLkyKGWLVsqKSlJUVFRGjVqlNXv4uKi2bNnq3v37oqIiJCnp6eio6M1ZMgQG6sGAAAAgKxxGGOM3UXYLTExUb6+vkpISJCPj4/d5cgx2GF3CbYyAx/4jyQAAABsYlc2sP17zAAAAADgQUcwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAm93V32MGANmBr6DgKyiQ/ZhXzCsA2YsjZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANrM1mI0ePVphYWHy8fGRj4+PIiIiNHfuXKu/Tp06cjgcTo8XXnjBaR0HDx5UkyZNlDt3bgUEBKhv375KTk6+07sCAAAAADfN1c6NFy5cWO+9954eeughGWM0YcIENW/eXBs3blS5cuUkSV27dtWQIUOsZXLnzm39nJKSoiZNmigoKEgrVqzQkSNH1L59e+XMmVPvvvvuHd8fAAAAALgZtgazZs2aOT1/5513NHr0aK1atcoKZrlz51ZQUFCGy//yyy/atm2bFixYoMDAQIWHh2vo0KF67bXXNGjQILm5uWW4XFJSkpKSkqzniYmJ2bRHAAAAAJB1d801ZikpKZo8ebLOnTuniIgIq33ixInKly+fypcvr/79++v8+fNW38qVKxUaGqrAwECrLSoqSomJidq6des1txUbGytfX1/rERwcfHt2CgAAAAAywdYjZpK0ZcsWRURE6MKFC/Ly8tLMmTMVEhIiSXr22WdVtGhRFSxYUJs3b9Zrr72mnTt3asaMGZKk+Ph4p1AmyXoeHx9/zW32799fvXv3tp4nJiYSzgAAAADYxvZg9vDDD2vTpk1KSEjQtGnTFB0drbi4OIWEhOj555+3xoWGhqpAgQKqW7eu9u7dq5IlS970Nt3d3eXu7p4d5QMAAADALbP9VEY3NzeVKlVKlSpVUmxsrCpUqKARI0ZkOLZq1aqSpD179kiSgoKCdPToUacxac+vdV0aAAAAANxtbA9mV0tNTXW6MceVNm3aJEkqUKCAJCkiIkJbtmzRsWPHrDHz58+Xj4+PdTokAAAAANztbD2VsX///mrUqJGKFCmiM2fOaNKkSVqyZInmzZunvXv3atKkSWrcuLHy5s2rzZs3q1evXqpdu7bCwsIkSQ0aNFBISIjatWunDz74QPHx8XrzzTcVExPDqYoAAAAA7hm2BrNjx46pffv2OnLkiHx9fRUWFqZ58+apfv36OnTokBYsWKDhw4fr3LlzCg4OVsuWLfXmm29ay7u4uGj27Nnq3r27IiIi5OnpqejoaKfvPQMAAACAu52twWzs2LHX7AsODlZcXNwN11G0aFHNmTMnO8sCAAAA7ijHYIfdJdjKDDR2l2C7u+4aMwAAAAB40BDMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGa2BrPRo0crLCxMPj4+8vHxUUREhObOnWv1X7hwQTExMcqbN6+8vLzUsmVLHT161GkdBw8eVJMmTZQ7d24FBASob9++Sk5OvtO7AgAAAAA3zdZgVrhwYb333ntav3691q1bp8cff1zNmzfX1q1bJUm9evXSTz/9pKlTpyouLk6HDx9WixYtrOVTUlLUpEkTXbx4UStWrNCECRM0fvx4DRgwwK5dAgAAAIAscxhjjN1FXMnf318ffvihnnrqKeXPn1+TJk3SU089JUnasWOHypYtq5UrV6patWqaO3eumjZtqsOHDyswMFCS9Pnnn+u1117T8ePH5ebmlqltJiYmytfXVwkJCfLx8blt+5ZZjsEOu0uwlRl4V30kcR9gTjGnkP2YV8wrZC/m1N0zp+zKBnfNNWYpKSmaPHmyzp07p4iICK1fv16XLl1SvXr1rDFlypRRkSJFtHLlSknSypUrFRoaaoUySYqKilJiYqJ11C0jSUlJSkxMdHoAAAAAgF1sD2ZbtmyRl5eX3N3d9cILL2jmzJkKCQlRfHy83Nzc5Ofn5zQ+MDBQ8fHxkqT4+HinUJbWn9Z3LbGxsfL19bUewcHB2btTAAAAAJAFtgezhx9+WJs2bdLq1avVvXt3RUdHa9u2bbd1m/3791dCQoL1OHTo0G3dHgAAAABcj6vdBbi5ualUqVKSpEqVKmnt2rUaMWKEnnnmGV28eFGnT592Omp29OhRBQUFSZKCgoK0Zs0ap/Wl3bUxbUxG3N3d5e7uns17AgAAAAA3x/YjZldLTU1VUlKSKlWqpJw5c2rhwoVW386dO3Xw4EFFRERIkiIiIrRlyxYdO3bMGjN//nz5+PgoJCTkjtcOAAAAADfD1iNm/fv3V6NGjVSkSBGdOXNGkyZN0pIlSzRv3jz5+vqqc+fO6t27t/z9/eXj46OXXnpJERERqlatmiSpQYMGCgkJUbt27fTBBx8oPj5eb775pmJiYjgiBgAAAOCeYWswO3bsmNq3b68jR47I19dXYWFhmjdvnurXry9JGjZsmHLkyKGWLVsqKSlJUVFRGjVqlLW8i4uLZs+ere7duysiIkKenp6Kjo7WkCFD7NolAAAAAMgyW4PZ2LFjr9vv4eGhkSNHauTIkdccU7RoUc2ZMye7SwMAAACAO+auu8YMAAAAAB40BDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAm7nezEK7d+/W4sWLdezYMaWmpjr1DRgwIFsKAwAAAIAHRZaD2Zdffqnu3bsrX758CgoKksPhsPocDgfBDAAAAACyKMvB7O2339Y777yj11577XbUAwAAAAAPnCxfY3bq1Ck9/fTTt6MWAAAAAHggZTmYPf300/rll19uRy0AAAAA8EDK8qmMpUqV0ltvvaVVq1YpNDRUOXPmdOp/+eWXs604AAAAAHgQZDmYjRkzRl5eXoqLi1NcXJxTn8PhIJgBAAAAQBZlOZjt27fvdtQBAAAAAA+sW/qCaWOMjDHZVQsAAAAAPJBuKph98803Cg0NVa5cuZQrVy6FhYXpP//5T3bXBgAAAAAPhCwHs08++UTdu3dX48aNNWXKFE2ZMkUNGzbUCy+8oGHDhmVpXbGxsXr00Ufl7e2tgIAAPfnkk9q5c6fTmDp16sjhcDg9XnjhBacxBw8eVJMmTZQ7d24FBASob9++Sk5OzuquAQAAAIAtsnyN2WeffabRo0erffv2VtsTTzyhcuXKadCgQerVq1em1xUXF6eYmBg9+uijSk5O1uuvv64GDRpo27Zt8vT0tMZ17dpVQ4YMsZ7nzp3b+jklJUVNmjRRUFCQVqxYoSNHjqh9+/bKmTOn3n333azuHgAAAADccVkOZkeOHFH16tXTtVevXl1HjhzJ0rp+/vlnp+fjx49XQECA1q9fr9q1a1vtuXPnVlBQUIbr+OWXX7Rt2zYtWLBAgYGBCg8P19ChQ/Xaa69p0KBBcnNzy1JNAAAAAHCnZflUxlKlSmnKlCnp2r///ns99NBDt1RMQkKCJMnf39+pfeLEicqXL5/Kly+v/v376/z581bfypUrFRoaqsDAQKstKipKiYmJ2rp1a4bbSUpKUmJiotMDAAAAAOyS5SNmgwcP1jPPPKOlS5eqRo0akqTly5dr4cKFGQa2zEpNTVXPnj1Vo0YNlS9f3mp/9tlnVbRoURUsWFCbN2/Wa6+9pp07d2rGjBmSpPj4eKdQJsl6Hh8fn+G2YmNjNXjw4JuuFQAAAACyU5aDWcuWLbV69WoNGzZMs2bNkiSVLVtWa9asUcWKFW+6kJiYGP3+++/69ddfndqff/556+fQ0FAVKFBAdevW1d69e1WyZMmb2lb//v3Vu3dv63liYqKCg4NvrnAAAAAAuEVZDmaSVKlSJX377bfZVkSPHj00e/ZsLV26VIULF77u2KpVq0qS9uzZo5IlSyooKEhr1qxxGnP06FFJuuZ1ae7u7nJ3d8+GygEAAADg1mXqGrMrr8G6+tqsW7lWyxijHj16aObMmVq0aJGKFy9+w2U2bdokSSpQoIAkKSIiQlu2bNGxY8esMfPnz5ePj49CQkKyVA8AAAAA2CFTR8zy5MmjI0eOKCAgQH5+fnI4HOnGGGPkcDiUkpKS6Y3HxMRo0qRJ+uGHH+Tt7W1dE+br66tcuXJp7969mjRpkho3bqy8efNq8+bN6tWrl2rXrq2wsDBJUoMGDRQSEqJ27drpgw8+UHx8vN58803FxMRwVAwAAADAPSFTwWzRokXWnRIXL16cbRsfPXq0pMtfIn2lcePGqUOHDnJzc9OCBQs0fPhwnTt3TsHBwWrZsqXefPNNa6yLi4tmz56t7t27KyIiQp6enoqOjnb63jMAAAAAuJtlKphFRkZaPxcvXlzBwcHpjpoZY3To0KEsbdwYc93+4OBgxcXF3XA9RYsW1Zw5c7K0bQAAAAC4W2T5e8yKFy+u48ePp2s/efJkpq4RAwAAAAA4y3IwS7uW7Gpnz56Vh4dHthQFAAAAAA+STN8uP+17vxwOh9566y3lzp3b6ktJSdHq1asVHh6e7QUCAAAAwP0u08Fs48aNki4fMduyZYvc3NysPjc3N1WoUEF9+vTJ/goBAAAA4D6X6WCWdjfGjh07asSIEfLx8bltRQEAAADAgyTTwSzNuHHjbkcdAAAAAPDAynIwk6R169ZpypQpOnjwoC5evOjUN2PGjGwpDAAAAAAeFFm+K+PkyZNVvXp1bd++XTNnztSlS5e0detWLVq0SL6+vrejRgAAAAC4r2U5mL377rsaNmyYfvrpJ7m5uWnEiBHasWOHWrVqpSJFityOGgEAAADgvpblYLZ37141adJE0uW7MZ47d04Oh0O9evXSmDFjsr1AAAAAALjfZTmY5cmTR2fOnJEkFSpUSL///rsk6fTp0zp//nz2VgcAAAAAD4As3/yjdu3amj9/vkJDQ/X000/rlVde0aJFizR//nzVrVv3dtQIAAAAAPe1LAezf//737pw4YIk6Y033lDOnDm1YsUKtWzZUm+++Wa2FwgAAAAA97ssBzN/f3/r5xw5cqhfv37ZWhAAAAAAPGiyfI3Zhg0btGXLFuv5Dz/8oCeffFKvv/56uu80AwAAAADcWJaDWbdu3bRr1y5J0h9//KFnnnlGuXPn1tSpU/Xqq69me4EAAAAAcL/LcjDbtWuXwsPDJUlTp05VZGSkJk2apPHjx2v69OnZXR8AAAAA3PeyHMyMMUpNTZUkLViwQI0bN5YkBQcH6++//87e6gAAAADgAZDlYFa5cmW9/fbb+s9//qO4uDjry6b37dunwMDAbC8QAAAAAO53WQ5mw4cP14YNG9SjRw+98cYbKlWqlCRp2rRpql69erYXCAAAAAD3uyzfLj8sLMzproxpPvzwQ7m4uGRLUQAAAADwIMlyMLsWDw+P7FoVAAAAADxQMhXM/P39tWvXLuXLl0958uSRw+G45tiTJ09mW3EAAAAA8CDIVDAbNmyYvL29JV2+xgwAAAAAkH0yFcyio6Mz/BkAAAAAcOsyFcwSExMzvUIfH5+bLgYAAAAAHkSZCmZ+fn7Xva5MuvzF0w6HQykpKdlSGAAAAAA8KDIVzBYvXny76wAAAACAB1amgllkZOTtrgMAAAAAHliZCmabN29W+fLllSNHDm3evPm6Y8PCwrKlMAAAAAB4UGQqmIWHhys+Pl4BAQEKDw+Xw+GQMSbdOK4xAwAAAICsy1Qw27dvn/Lnz2/9DAAAAADIPpkKZkWLFrV+PnDggKpXry5XV+dFk5OTtWLFCqexAAAAAIAby5HVBR577DGdPHkyXXtCQoIee+yxbCkKAAAAAB4kWQ5mad9XdrUTJ07I09MzS+uKjY3Vo48+Km9vbwUEBOjJJ5/Uzp07ncZcuHBBMTExyps3r7y8vNSyZUsdPXrUaczBgwfVpEkT5c6dWwEBAerbt6+Sk5OzumsAAAAAYItMncooSS1atJB0+QYfHTp0kLu7u9WXkpKizZs3q3r16lnaeFxcnGJiYvToo48qOTlZr7/+uho0aKBt27ZZIa9Xr17673//q6lTp8rX11c9evRQixYttHz5cmvbTZo0UVBQkFasWKEjR46offv2ypkzp959990s1QMAAAAAdsh0MPP19ZV0+YiZt7e3cuXKZfW5ubmpWrVq6tq1a5Y2/vPPPzs9Hz9+vAICArR+/XrVrl1bCQkJGjt2rCZNmqTHH39ckjRu3DiVLVtWq1atUrVq1fTLL79o27ZtWrBggQIDAxUeHq6hQ4fqtdde06BBg+Tm5palmgAAAADgTst0MBs3bpwkqVixYurTp0+WT1vMjISEBEmSv7+/JGn9+vW6dOmS6tWrZ40pU6aMihQpopUrV6patWpauXKlQkNDFRgYaI2JiopS9+7dtXXrVlWsWDHddpKSkpSUlGQ9T0xMzPZ9AQAAAIDMyvI1ZgMHDrwtoSw1NVU9e/ZUjRo1VL58eUlSfHy83Nzc5Ofn5zQ2MDBQ8fHx1pgrQ1laf1pfRmJjY+Xr62s9goODs3lvAAAAACDzMh3M8uTJI39//3SP4sWLKyoqSvPnz7+lQmJiYvT7779r8uTJt7SezOjfv78SEhKsx6FDh277NgEAAADgWjJ9KuPw4cMzbD99+rTWr1+vpk2batq0aWrWrFmWi+jRo4dmz56tpUuXqnDhwlZ7UFCQLl68qNOnTzsdNTt69KiCgoKsMWvWrHFaX9pdG9PGXM3d3d3p5iUAAAAAYKdMB7Po6Ojr9oeHhys2NjZLwcwYo5deekkzZ87UkiVLVLx4caf+SpUqKWfOnFq4cKFatmwpSdq5c6cOHjyoiIgISVJERITeeecdHTt2TAEBAZKk+fPny8fHRyEhIZmuBQAAAADskuVrzK6ladOm2rFjR5aWiYmJ0bfffqtJkybJ29tb8fHxio+P1z///CPp8p0gO3furN69e2vx4sVav369OnbsqIiICFWrVk2S1KBBA4WEhKhdu3b67bffNG/ePL355puKiYnhqBgAAACAe0Kmj5jdSFJSUpZvTT969GhJUp06dZzax40bpw4dOkiShg0bphw5cqhly5ZKSkpSVFSURo0aZY11cXHR7Nmz1b17d0VERMjT01PR0dEaMmTILe0PAAAAANwp2RbMxo4dq/Dw8CwtY4y54RgPDw+NHDlSI0eOvOaYokWLas6cOVnaNgAAAADcLTIdzHr37p1he0JCgjZs2KBdu3Zp6dKl2VYYAAAAADwoMh3MNm7cmGG7j4+P6tevrxkzZqS7eQcAAAAA4MYyHcwWL158O+sAAAAAgAdWtt2VEQAAAABwcwhmAAAAAGAzghkAAAAA2IxgBgAAAAA2y3Qw69Spk86cOXM7awEAAACAB1Kmg9mECRP0zz//3M5aAAAAAOCBlOlgZoy5nXUAAAAAwAMr099jJklnzpyRh4fHdcf4+PjcUkEAAAAA8KDJUjArXbr0NfuMMXI4HEpJSbnlogAAAADgQZKlYDZt2jT5+/vfrloAAAAA4IGUpWBWo0YNBQQE3K5aAAAAAOCBxPeYAQAAAIDNMh3MihYtKhcXl9tZCwAAAAA8kDJ9KuO+fftuZx0AAAAA8MDKdDDLkyePHA5HunZfX1+VLl1affr0Uf369bO1OAAAAAB4EGQ6mA0bNizDYHb69GmtX79eTZs21bRp09SsWbNsLRAAAAAA7neZDmYdOnS4bn94eLhiY2MJZgAAAACQRdl2V8amTZtqx44d2bU6AAAAAHhgZFswS0pKkpubW3atDgAAAAAeGNkWzMaOHavw8PDsWh0AAAAAPDAyfY1Z7969M2xPSEjQhg0btGvXLi1dujTbCgMAAACAB0Wmg9nGjRszbPfx8VH9+vU1Y8YMFS9ePNsKAwAAAIAHRaaD2eLFi6/b/+eff+r555/XmDFjbrkoAAAAAHiQZNs1ZidOnNDYsWOza3UAAAAA8MDItmAGAAAAALg5BDMAAAAAsBnBDAAAAABslumbf7Ro0eK6/adPn77VWgAAAADggZTpYObr63vD/vbt299yQQAAAADwoMl0MBs3btztrAMAAAAAHlhcYwYAAAAANrM1mC1dulTNmjVTwYIF5XA4NGvWLKf+Dh06yOFwOD0aNmzoNObkyZNq27atfHx85Ofnp86dO+vs2bN3cC8AAAAA4NbYGszOnTunChUqaOTIkdcc07BhQx05csR6fPfdd079bdu21datWzV//nzNnj1bS5cu1fPPP3+7SwcAAACAbJPpa8xuh0aNGqlRo0bXHePu7q6goKAM+7Zv366ff/5Za9euVeXKlSVJn332mRo3bqyPPvpIBQsWzPaaAQAAACC73fXXmC1ZskQBAQF6+OGH1b17d504ccLqW7lypfz8/KxQJkn16tVTjhw5tHr16muuMykpSYmJiU4PAAAAALDLXR3MGjZsqG+++UYLFy7U+++/r7i4ODVq1EgpKSmSpPj4eAUEBDgt4+rqKn9/f8XHx19zvbGxsfL19bUewcHBt3U/AAAAAOB6bD2V8UZat25t/RwaGqqwsDCVLFlSS5YsUd26dW96vf3791fv3r2t54mJiYQzAAAAALa5q4+YXa1EiRLKly+f9uzZI0kKCgrSsWPHnMYkJyfr5MmT17wuTbp83ZqPj4/TAwAAAADsck8Fsz///FMnTpxQgQIFJEkRERE6ffq01q9fb41ZtGiRUlNTVbVqVbvKBAAAAIAssfVUxrNnz1pHvyRp37592rRpk/z9/eXv76/BgwerZcuWCgoK0t69e/Xqq6+qVKlSioqKkiSVLVtWDRs2VNeuXfX555/r0qVL6tGjh1q3bs0dGQEAAADcM2w9YrZu3TpVrFhRFStWlCT17t1bFStW1IABA+Ti4qLNmzfriSeeUOnSpdW5c2dVqlRJy5Ytk7u7u7WOiRMnqkyZMqpbt64aN26smjVrasyYMXbtEgAAAABkma1HzOrUqSNjzDX7582bd8N1+Pv7a9KkSdlZFgAAAADcUffUNWYAAAAAcD8imAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDNbg9nSpUvVrFkzFSxYUA6HQ7NmzXLqN8ZowIABKlCggHLlyqV69epp9+7dTmNOnjyptm3bysfHR35+furcubPOnj17B/cCAAAAAG6NrcHs3LlzqlChgkaOHJlh/wcffKBPP/1Un3/+uVavXi1PT09FRUXpwoUL1pi2bdtq69atmj9/vmbPnq2lS5fq+eefv1O7AAAAAAC3zNXOjTdq1EiNGjXKsM8Yo+HDh+vNN99U8+bNJUnffPONAgMDNWvWLLVu3Vrbt2/Xzz//rLVr16py5cqSpM8++0yNGzfWRx99pIIFC2a47qSkJCUlJVnPExMTs3nPAAAAACDz7tprzPbt26f4+HjVq1fPavP19VXVqlW1cuVKSdLKlSvl5+dnhTJJqlevnnLkyKHVq1dfc92xsbHy9fW1HsHBwbdvRwAAAADgBu7aYBYfHy9JCgwMdGoPDAy0+uLj4xUQEODU7+rqKn9/f2tMRvr376+EhATrcejQoWyuHgAAAAAyz9ZTGe3i7u4ud3d3u8sAAAAAAEl38RGzoKAgSdLRo0ed2o8ePWr1BQUF6dixY079ycnJOnnypDUGAAAAAO52d20wK168uIKCgrRw4UKrLTExUatXr1ZERIQkKSIiQqdPn9b69eutMYsWLVJqaqqqVq16x2sGAAAAgJth66mMZ8+e1Z49e6zn+/bt06ZNm+Tv768iRYqoZ8+eevvtt/XQQw+pePHieuutt1SwYEE9+eSTkqSyZcuqYcOG6tq1qz7//HNdunRJPXr0UOvWra95R0YAAAAAuNvYGszWrVunxx57zHreu3dvSVJ0dLTGjx+vV199VefOndPzzz+v06dPq2bNmvr555/l4eFhLTNx4kT16NFDdevWVY4cOdSyZUt9+umnd3xfAAAAAOBm2RrM6tSpI2PMNfsdDoeGDBmiIUOGXHOMv7+/Jk2adDvKAwAAAIA74q69xgwAAAAAHhQEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALDZXR3MBg0aJIfD4fQoU6aM1X/hwgXFxMQob9688vLyUsuWLXX06FEbKwYAAACArLurg5kklStXTkeOHLEev/76q9XXq1cv/fTTT5o6dari4uJ0+PBhtWjRwsZqAQAAACDrXO0u4EZcXV0VFBSUrj0hIUFjx47VpEmT9Pjjj0uSxo0bp7Jly2rVqlWqVq3aNdeZlJSkpKQk63liYmL2Fw4AAAAAmXTXHzHbvXu3ChYsqBIlSqht27Y6ePCgJGn9+vW6dOmS6tWrZ40tU6aMihQpopUrV153nbGxsfL19bUewcHBt3UfAAAAAOB67upgVrVqVY0fP14///yzRo8erX379qlWrVo6c+aM4uPj5ebmJj8/P6dlAgMDFR8ff9319u/fXwkJCdbj0KFDt3EvAAAAAOD67upTGRs1amT9HBYWpqpVq6po0aKaMmWKcuXKddPrdXd3l7u7e3aUCAAAAAC37K4+YnY1Pz8/lS5dWnv27FFQUJAuXryo06dPO405evRohtekAQAAAMDd6p4KZmfPntXevXtVoEABVapUSTlz5tTChQut/p07d+rgwYOKiIiwsUoAAAAAyJq7+lTGPn36qFmzZipatKgOHz6sgQMHysXFRW3atJGvr686d+6s3r17y9/fXz4+PnrppZcUERFx3TsyAgAAAMDd5q4OZn/++afatGmjEydOKH/+/KpZs6ZWrVql/PnzS5KGDRumHDlyqGXLlkpKSlJUVJRGjRplc9UAAAAAkDV3dTCbPHnydfs9PDw0cuRIjRw58g5VBAAAAADZ7566xgwAAAAA7kcEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALDZfRPMRo4cqWLFisnDw0NVq1bVmjVr7C4JAAAAADLlvghm33//vXr37q2BAwdqw4YNqlChgqKionTs2DG7SwMAAACAG7ovgtknn3yirl27qmPHjgoJCdHnn3+u3Llz6+uvv7a7NAAAAAC4IVe7C7hVFy9e1Pr169W/f3+rLUeOHKpXr55WrlyZ4TJJSUlKSkqynickJEiSEhMTb2+xmXXB7gLsdde8D7h/MKfsLgH3I+aV3SXgfsOcsrsES1otxpg7ut17Ppj9/fffSklJUWBgoFN7YGCgduzYkeEysbGxGjx4cLr24ODg21Ijssb3PV+7SwDuK8wpIPsxr4DsdTfOqTNnzsjX987Vdc8Hs5vRv39/9e7d23qempqqkydPKm/evHI4HDZWZr/ExEQFBwfr0KFD8vHxsbsc4J7HnAKyH/MKyF7MKWfGGJ05c0YFCxa8o9u954NZvnz55OLioqNHjzq1Hz16VEFBQRku4+7uLnd3d6c2Pz+/21XiPcnHx4eJCWQj5hSQ/ZhXQPZiTv3PnTxSluaev/mHm5ubKlWqpIULF1ptqampWrhwoSIiImysDAAAAAAy554/YiZJvXv3VnR0tCpXrqwqVapo+PDhOnfunDp27Gh3aQAAAABwQ/dFMHvmmWd0/PhxDRgwQPHx8QoPD9fPP/+c7oYguDF3d3cNHDgw3ameAG4OcwrIfswrIHsxp+4ODnOn7wMJAAAAAHByz19jBgAAAAD3OoIZAAAAANiMYAYAAAAANiOY3aRixYpp+PDhdpdxz9m/f78cDoc2bdp027fFe3Tv4T27OcwrXAvv181hTuF6eM9uDvMqE8w9LDo62kgy3bp1S9f34osvGkkmOjo6U+vat2+fkWQ2btyYqfHHjh0z586dy9TYpk2bmqioqAz7li5daiSZ3377LVPrupbFixcbSebUqVO3tJ6rnT9/3uTJk8fkzZvXXLhwIUvLRkdHm+bNmzu1JScnmyNHjphLly5lW43jxo0zvr6+6dqz8h5ll3//+9+maNGixt3d3VSpUsWsXr36jm4/OzCv/od55Zuu/U7Pq7i4ONO0aVNToEABI8nMnDnzjm07uzCn/oc55Zuu/U7PqXfffddUrlzZeHl5mfz585vmzZubHTt23LHtZxfm1f8wr3zTtd/peTVq1CgTGhpqvL29jbe3t6lWrZqZM2dOltdzzx8xCw4O1uTJk/XPP/9YbRcuXNCkSZNUpEiRbN/exYsXJUn58+dX7ty5M7VM586dNX/+fP3555/p+saNG6fKlSsrLCwsW+u8WcYYJScnW8+nT5+ucuXKqUyZMpo1a9Ytr9/FxUVBQUFydb3939SQlfcoO3z//ffq3bu3Bg4cqA0bNqhChQqKiorSsWPH7lgN2YV5lb2YVzfv3LlzqlChgkaOHHnHtnk7MKeyF3Pq5sXFxSkmJkarVq3S/PnzdenSJTVo0EDnzp27YzVkF+ZV9mJe3bzChQvrvffe0/r167Vu3To9/vjjat68ubZu3Zq1FWVzYLyj0tJ4+fLlzbfffmu1T5w40YSFhZnmzZtbfy2ZO3euqVGjhvH19TX+/v6mSZMmZs+ePdYykpwekZGRTtt4++23TYECBUyxYsWMMcYULVrUDBs2zBhz+S8VOXPmNEuXLrXW9/7775v8+fOb+Ph4c+nSJRMYGGiGDh3qVP+ZM2eMl5eXGT16tDHGmGXLlpmaNWsaDw8PU7hwYfPSSy+Zs2fPWuMvXLhgXn31VVO4cGHj5uZmSpYsab766ivrLz1XPtL2+8KFC+all14y+fPnN+7u7qZGjRpmzZo11jrT/soyZ84c88gjj5icOXOaxYsXW/116tQxn3/+uRk9erSpX79+uvfg999/N02aNDHe3t7Gy8vL1KxZ0+zZs8cMHDgwXU2LFy92+qtUSkqKKVSokBk1apTTOjds2GAcDofZv3+/McaYjz/+2JQvX97kzp3bFC5c2HTv3t2cOXPGqf4rHwMHDkz3HhljzIEDB8wTTzxhPD09jbe3t3n66adNfHy81T9w4EBToUIF880335iiRYsaHx8f88wzz5jExMR0+52RKlWqmJiYGOt5SkqKKViwoImNjc3U8ncL5hXz6m6aV1fSPXzEjDnFnLob55Qxl48sSDJxcXE3tbxdmFfMq7t5XhljTJ48ecxXX32VpWXui2D2ySefmLp161rtdevWNcOGDXOalNOmTTPTp083u3fvNhs3bjTNmjUzoaGhJiUlxRhjzJo1a4wks2DBAnPkyBFz4sQJaxteXl6mXbt25vfffze///67MSb9G963b19TtGhRc/r0abNhwwbj5uZmfvjhB6f+kiVLmtTUVKvt66+/Nrly5TKnT582e/bsMZ6enmbYsGFm165dZvny5aZixYqmQ4cO1vhWrVqZ4OBgM2PGDLN3716zYMECM3nyZJOcnGymT59uJJmdO3eaI0eOmNOnTxtjjHn55ZdNwYIFzZw5c8zWrVtNdHS0yZMnj7V/aR/qsLAw88svv5g9e/ZYfXv27DHu7u7m5MmT5sSJE8bDw8OaKMYY8+effxp/f3/TokULs3btWrNz507z9ddfmx07dpgzZ86YVq1amYYNG5ojR46YI0eOmKSkpHSnC/Tp08fUrFnT6X39v//7P6e2YcOGmUWLFpl9+/aZhQsXmocffth0797dGGNMUlKSGT58uPHx8bG2kzZhr3yPUlJSTHh4uKlZs6ZZt26dWbVqlalUqZL1y9eYy5PSy8vLtGjRwmzZssUsXbrUBAUFmddff/2an8E0SUlJxsXFJd0/Gtu3b2+eeOKJGy5/N2FeMa/ulnl1tXs9mDGnmFN325wyxpjdu3cbSWbLli03tbxdmFfMq7t1XiUnJ5vvvvvOuLm5ma1bt2Zp2fsimB07dsy4u7ub/fv3m/379xsPDw9z/Phxp0l5tePHjzv9IrrW+cXR0dEmMDDQJCUlObVfPSmTkpJMeHi4adWqlQkJCTFdu3Z1Gr99+3brLwZpatWqZZ577jljjDGdO3c2zz//vNMyy5YtMzly5DD//POP2blzp5Fk5s+fn+H+ZHR+8dmzZ03OnDnNxIkTrbaLFy+aggULmg8++MBpuVmzZqVb5+uvv26efPJJ63nz5s2tv0QYY0z//v1N8eLFzcWLFzOsKaPzi69+nTdu3GgcDoc5cOCAMcZYf0FJ+wtSRqZOnWry5s1rPb/W+cVXvke//PKLcXFxMQcPHrT6t27daiRZfz0aOHCgyZ07t9NfR/r27WuqVq16zVrS/PXXX0aSWbFihVN73759TZUqVW64/N2EefU/zCvfdOPu5Ly62r0ezJhTzKm7bU6lpKSYJk2amBo1amR5Wbsxr/6HeeWbbpwd82rz5s3G09PTuLi4GF9fX/Pf//4308umueevMZMun0fapEkTjR8/XuPGjVOTJk2UL18+pzG7d+9WmzZtVKJECfn4+KhYsWKSpIMHD95w/aGhoXJzc7vuGDc3N02cOFHTp0/XhQsXNGzYMKf+MmXKqHr16vr6668lSXv27NGyZcvUuXNnSdJvv/2m8ePHy8vLy3pERUUpNTVV+/bt06ZNm+Ti4qLIyMjMvizau3evLl26pBo1alhtOXPmVJUqVbR9+3ansZUrV3Z6npKSogkTJui5556z2p577jmNHz9eqampkqRNmzapVq1aypkzZ6Zrulp4eLjKli2rSZMmSbp87vuxY8f09NNPW2MWLFigunXrqlChQvL29la7du104sQJnT9/PtPb2b59u4KDgxUcHGy1hYSEyM/Pz+m1KFasmLy9va3nBQoUuCevEcsOzKuMMa/+h3mVNcypjDGn/udOz6mYmBj9/vvvmjx5cpaXvVswrzLGvPqfOzWvHn74YW3atEmrV69W9+7dFR0drW3btmV6eek+ul1+p06dNH78eE2YMEGdOnVK19+sWTOdPHlSX375pVavXq3Vq1dL+t+FnNfj6emZqRpWrFghSTp58qROnjyZrr9z586aPn26zpw5o3HjxqlkyZLWJDt79qy6deumTZs2WY/ffvtNu3fvVsmSJZUrV65M1XCzrt7HefPm6a+//tIzzzwjV1dXubq6qnXr1jpw4IAWLlwoSdlWU9u2ba1JOWnSJDVs2FB58+aVdPnWqk2bNlVYWJimT5+u9evXWzcByMx7l1VX/4JxOBzWL6HryZcvn1xcXHT06FGn9qNHjyooKChba7yTmFe3hnl12c3Oq/sRc+rWMKcuy4451aNHD82ePVuLFy9W4cKFs7O8O455dWuYV5fd6rxyc3NTqVKlVKlSJcXGxqpChQoaMWJElmq4b4JZw4YNdfHiRV26dElRUVFOfSdOnNDOnTv15ptvqm7duipbtqxOnTrlNCbtryEpKSk3tf29e/eqV69e+vLLL1W1alVFR0enezNbtWqlHDlyaNKkSfrmm2/UqVMnORwOSdIjjzyibdu2qVSpUukebm5uCg0NVWpqquLi4jLcfkb1lyxZUm5ublq+fLnVdunSJa1du1YhISHX3Z+xY8eqdevWTr8kNm3apNatW2vs2LGSpLCwMC1btkyXLl26Zk2ZeT2fffZZ/f7771q/fr2mTZumtm3bWn3r169XamqqPv74Y1WrVk2lS5fW4cOHs7ydsmXL6tChQzp06JDVtm3bNp0+ffqGr0VmuLm5qVKlStYvLElKTU3VwoULFRERccvrtwvzinl1Pbd7Xt2PmFPMqeu5E3PKGKMePXpo5syZWrRokYoXL54t67UT84p5dT12/b8qNTVVSUlJWVsoyyc/3kWuPn81ISHBJCQkWM/Tzi9OSUkxefPmNc8995zZvXu3WbhwoXn00Uedrle4dOmSyZUrl3n77bdNfHy8deFkRufIGuN87mpycrKpVq2aadmypTHGmMOHD5u8efNa5/BeqXPnziZPnjzGxcXF/PXXX1b7b7/9ZnLlymViYmLMxo0bza5du8ysWbOc7vLXoUMHExwcbGbOnGn++OMPs3jxYvP9998bYy5fhOlwOMz48ePNsWPHrIsfX3nlFVOwYEEzd+5cpws/T548aYzJ+LzkY8eOmZw5c5q5c+emq3/OnDnG3d3dnDhxwvz9998mb9681oWfu3btMt988431fSjvvPOOKVKkiNmxY4c5fvy4uXjx4jXP465Ro4apUKGC8fb2NufPn7faN23aZCSZ4cOHm71795pvvvnGFCpUyKnm5cuXWxftHj9+3Preiivfo9TUVBMeHm5q1apl1q9fb1avXp3hhZ8VKlRwqmvYsGGmaNGi6V6HjEyePNm4u7ub8ePHm23btpnnn3/e+Pn5Od31517AvGJeGXP3zKszZ86YjRs3mo0bNxpJ5pNPPjEbN260rkm4FzCnmFPG3D1zqnv37sbX19csWbLEumHCkSNHnPbnXsC8Yl4Zc/fMq379+pm4uDizb98+s3nzZtOvXz/jcDjML7/8kqnl09xXwexqV174OX/+fFO2bFnj7u5uwsLCzJIlS9JdSP7ll1+a4OBgkyNHjnS3Sr3alW/44MGDTYECBczff/9t9U+fPt24ubmZTZs2OS23YsUKI8k0btw43TrXrFlj6tevb7y8vIynp6cJCwsz77zzjtX/zz//mF69epkCBQoYNzc3U6pUKfP1119b/UOGDDFBQUHG4XBY+/3PP/+Yl156yeTLl++6t0q9clJ+9NFHxs/PL8MLOpOSkoyfn58ZMWKEMebyL5MGDRqY3LlzG29vb1OrVi2zd+9eY8zlyZ22P8rgVqlXGjVqlJFk2rdvn26bn3zyiSlQoIDJlSuXiYqKMt988026ml944QWTN2/ebLlV6pWyMimNMeazzz4zRYoUMW5ubqZKlSpm1apVmV72bsG8Yl6luRvmVUa3Q5Yy/8WxdwPmFHMqzd0wpzKaT5LMuHHjMrX83YJ5xbxKczfMq06dOpmiRYsaNzc3kz9/flO3bt0shzJjjHEYY0zWjrEBAAAAALLTfXONGQAAAADcqwhmQCYcPHjQ6Ta2Vz8yc8tdAM6YV0D2Yk4B2e9OzitOZQQyITk5Wfv3779mf7FixeTq6nrnCgLuA8wrIHsxp4DsdyfnFcEMAAAAAGzGqYwAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAIAHWp06ddSzZ0+7ywAAPOAIZgCAm9KhQwc5HA699957Tu2zZs2Sw+HI0rqKFSum4cOHZ2N1t8/+/fvlcDi0adMmu0sBANxHCGYAgJvm4eGh999/X6dOnbK7lCy7ePGi3SVkq0uXLtldAgDgFhDMAAA3rV69egoKClJsbOx1x/3666+qVauWcuXKpeDgYL388ss6d+6cpMunEh44cEC9evWSw+GQw+GQMUb58+fXtGnTrHWEh4erQIECTut0d3fX+fPnJUkHDx5U8+bN5eXlJR8fH7Vq1UpHjx61xg8aNEjh4eH66quvVLx4cXl4eGRY63//+1/5+vpq4sSJN/Wa7N27V82bN1dgYKC8vLz06KOPasGCBVb/kCFDVL58+XTLhYeH66233rKef/XVVypbtqw8PDxUpkwZjRo1yupLO2r3/fffKzIyUh4eHpo4caIOHDigZs2aKU+ePPL09FS5cuU0Z86cm9oPAMCdRTADANw0FxcXvfvuu/rss8/0559/Zjhm7969atiwoVq2bKnNmzfr+++/16+//qoePXpIkmbMmKHChQtryJAhOnLkiI4cOSKHw6HatWtryZIlkqRTp05p+/bt+ueff7Rjxw5JUlxcnB599FHlzp1bqampat68uU6ePKm4uDjNnz9ff/zxh5555hmnWvbs2aPp06drxowZGZ6KOGnSJLVp00YTJ05U27Ztb+o1OXv2rBo3bqyFCxdq48aNatiwoZo1a6aDBw9Kkjp16qTt27dr7dq11jIbN27U5s2b1bFjR0nSxIkTNWDAAL3zzjvavn273n33Xb311luaMGGC07b69eunV155Rdu3b1dUVJRiYmKUlJSkpUuXasuWLXr//ffl5eV1U/sBALizXO0uAABwb/vXv/6l8PBwDRw4UGPHjk3XHxsbq7Zt21o32HjooYf06aefKjIyUqNHj5a/v79cXFzk7e2toKAga7k6deroiy++kCQtXbpUFStWVFBQkJYsWaIyZcpoyZIlioyMlCQtXLhQW7Zs0b59+xQcHCxJ+uabb1SuXDmtXbtWjz76qKTLpy9+8803yp8/f7o6R44cqTfeeEM//fSTtd6bUaFCBVWoUMF6PnToUM2cOVM//vijevToocKFCysqKkrjxo2z6ho3bpwiIyNVokQJSdLAgQP18ccfq0WLFpKk4sWLa9u2bfriiy8UHR1trbtnz57WGOnyUcOWLVsqNDRUkqz1AQDufhwxAwDcsvfff18TJkzQ9u3b0/X99ttvGj9+vLy8vKxHVFSUUlNTtW/fvmuuMzIyUtu2bdPx48cVFxenOnXqqE6dOlqyZIkuXbqkFStWqE6dOpKk7du3Kzg42AplkhQSEiI/Pz+nmooWLZphKJs2bZp69eql+fPn31Ioky4fMevTp4/Kli0rPz8/eXl5afv27dYRM0nq2rWrvvvuO124cEEXL17UpEmT1KlTJ0nSuXPntHfvXnXu3NnpNXv77be1d+9ep21VrlzZ6fnLL7+st99+WzVq1NDAgQO1efPmW9oXAMCdQzADANyy2rVrKyoqSv3790/Xd/bsWXXr1k2bNm2yHr/99pt2796tkiVLXnOdoaGh8vf3V1xcnFMwi4uL09q1a3Xp0iVVr149S3V6enpm2F6xYkXlz59fX3/9tYwxWVrn1fr06aOZM2fq3Xff1bJly7Rp0yaFhoY63WykWbNmcnd318yZM/XTTz/p0qVLeuqppyRdfr0k6csvv3R6zX7//XetWrXquvvTpUsX/fHHH2rXrp22bNmiypUr67PPPrul/QEA3BmcyggAyBbvvfeewsPD9fDDDzu1P/LII9q2bZtKlSp1zWXd3NyUkpLi1OZwOFSrVi398MMP2rp1q2rWrKncuXMrKSlJX3zxhSpXrmwFk7Jly+rQoUM6dOiQddRs27ZtOn36tEJCQm5Ye8mSJfXxxx+rTp06cnFx0b///e+s7r5l+fLl6tChg/71r39Juhy09u/f7zTG1dVV0dHRGjdunNzc3NS6dWvlypVLkhQYGKiCBQvqjz/+uKnr3IKDg/XCCy/ohRdeUP/+/fXll1/qpZdeuun9AQDcGQQzAEC2CA0NVdu2bfXpp586tb/22muqVq2aevTooS5dusjT01Pbtm3T/PnzrQBUrFgxLV26VK1bt5a7u7vy5csn6fJ1Zv/3f/+nypUrWzexqF27tiZOnKi+ffta26hXr561/eHDhys5OVkvvviiIiMj053udy2lS5fW4sWLVadOHbm6ut7we9V27tyZrq1cuXJ66KGHNGPGDDVr1kwOh0NvvfWWUlNT043t0qWLypYtK+lymLvS4MGD9fLLL8vX11cNGzZUUlKS1q1bp1OnTql3797XrKlnz55q1KiRSpcurVOnTmnx4sXWNgAAdzdOZQQAZJshQ4akCyFhYWGKi4vTrl27VKtWLVWsWFEDBgxQwYIFnZbbv3+/SpYs6XQNWGRkpFJSUqxryaTLYe3qNofDoR9++EF58uRR7dq1Va9ePZUoUULff/99lup/+OGHtWjRIn333Xf6v//7v+uObd26tSpWrOj0OHr0qD755BPlyZNH1atXV7NmzRQVFaVHHnkk3fIPPfSQqlevrjJlyqhq1apOfV26dNFXX32lcePGKTQ0VJGRkRo/fryKFy9+3ZpSUlIUExOjsmXLqmHDhipdurTTbfYBAHcvh7nVk+kBAECWGWP00EMP6cUXX7zuUTAAwIOBUxkBALjDjh8/rsmTJys+Pt767jIAwIONYAYAwB0WEBCgfPnyacyYMcqTJ4/d5QAA7gIEMwAA7jCuIgAAXI2bfwAAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANvt/0FgPyPFgHAkAAAAASUVORK5CYII=", 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    " + "{'MatrixVectorActivation_0': {'BRAM_18K': 5,\n", + " 'BRAM_efficiency': 0.8333333333333334,\n", + " 'LUT': 319,\n", + " 'URAM': 0,\n", + " 'URAM_efficiency': 1,\n", + " 'DSP': 0},\n", + " 'MatrixVectorActivation_1': {'BRAM_18K': 1,\n", + " 'BRAM_efficiency': 0.4444444444444444,\n", + " 'LUT': 320,\n", + " 'URAM': 0,\n", + " 'URAM_efficiency': 1,\n", + " 'DSP': 0},\n", + " 'MatrixVectorActivation_2': {'BRAM_18K': 1,\n", + " 'BRAM_efficiency': 0.4444444444444444,\n", + " 'LUT': 320,\n", + " 'URAM': 0,\n", + " 'URAM_efficiency': 1,\n", + " 'DSP': 0},\n", + " 'MatrixVectorActivation_3': {'BRAM_18K': 1,\n", + " 'BRAM_efficiency': 0.006944444444444444,\n", + " 'LUT': 320,\n", + " 'URAM': 0,\n", + " 'URAM_efficiency': 1,\n", + " 'DSP': 0}}" ] }, + "execution_count": 8, "metadata": {}, - "output_type": "display_data" + "output_type": "execute_result" } ], "source": [ - "layers = list(res_dict.keys())\n", - "utilisation = list(res_dict.values())\n", - "lut_values = [] #Initializing a list to store LUT values.\n", - "for i in range(len(layers)):\n", - " x = list(utilisation[i].values()) #Extracting the resource utilisation for each layer as a list.\n", - " lut_values.append(x[2]) #Extracting the LUT values of resource utilisation from each layer and appending to the list\n", - " \n", - "#Plotting the bar graph of each network layer with their corresponding LUT resource utilisation\n", - "fig = plt.figure(figsize = (10, 5))\n", - "plt.bar(layers, lut_values, color ='green', width = 0.3)\n", - "plt.xlabel(\"Network Layers\")\n", - "plt.ylabel(\"LUT Utilisation\")\n", - "plt.title(\"Estimated LUT values used for each network layer\")\n", - "plt.show()" + "res_dict = model.analysis(res_estimation)\n", + "res_dict" ] }, { "cell_type": "markdown", "metadata": {}, "source": [ - "Note, from the above result we observe that the bottleneck in the execution of the model on hardware would come from the execution of the first layer which takes estimated 38400 clock cycles to execute one set of its inputs.\n", - "No matter how quickly the layers execute the (throughput or latency?) will be defined by the first layer's execution latency.\n", + "Next to the absolute numbers of LUTs, BRAM, URAM and DSPs, the analysis pass also provides information about the efficiency of the memory usage. If the memory type is not utilized, the efficiency is by default 1. You can see that above for the `URAM_efficiency`. In all other cases the efficiency indicates the actual parameter storage needed divided by the allocated BRAM/URAM storage. So, this means in our example MVAU_0 uses 5 block ram and they are 83% utilized. " + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "After we extract that information from the model, we plot the number of LUTs. In this notebook we concentrate on the influence on the LUT usage, but by manipulating the code below, you can also extract information about memory and dsp usage." + ] + }, + { + "cell_type": "code", + "execution_count": 13, + "metadata": {}, + "outputs": [ + { + "data": { + "image/png": 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/flzS1XtrihUrlu7yvptdHpaR6481f/78kmSFgbSAdv12PTw8VKZMGWt5Zp04cUIXLlzIsM4KFSooNTVVhw4dUsWKFV3ablbJ7Hcs3a3PXhpPT08NHTpUffv2VdGiRVWrVi01bdpUHTp0UEBAgKSrnxVJeuKJJzLchq+vr6T/vYcPPvhguj7lypVzCjCu+OOPP+Tm5pZultSAgAD5+/un+2xkNMNqRtKO62aX5SYmJip//vy6ePGihgwZogkTJujPP/90utzu2j+E7Nu3T61atcrU/m81Ju5kfV9fX+3Zs0fGmAzfD0mZujS4WrVqypcvn1atWqXIyEitWrVKgwYNUkBAgEaNGqVLly5ZAS3t3rAbjWXp6thbsGBBugk+bvSeXbp0SVFRUapevbq+/fZb5cp1+7+OZfZnZocOHTR06FDNmjVLHTp00K5du7Rx40Z99tlnVn9XX9sHHniASaCALEQwA3KwIkWKKDY2VgsWLNC8efM0b948TZgwQR06dNCkSZNue7vu7u4utaf9Mrhv3z5FRESofPny+vjjjxUYGCgPDw/99NNPGj58eLrJOzKSmpqqJ598Uq+88kqGyx966KFMHkXm3OqY7id58uTRxYsXM1yW9gthnjx5MrWt2/3s3Sj4paSkpGvr1auXmjVrptmzZ2vBggV68803NWTIEC1dulQPP/yw9Xn66quvrLB2rTv5ZdkVmQ2zmb33KO24Pvjggxt+kXXaHyR69uypCRMmqFevXgoLC7O+iLxNmzaZGm8ZudMxcav1U1NT5XA4NG/evAz7ZuZeyty5c6tmzZpauXKl9u7dq/j4eIWHh6to0aJKTk7WunXrtGrVKpUvX/6OvtLhRu+Zp6enmjRpojlz5mj+/Pk3/H7AW3HlZ2ZISIiqV6+u//73v+rQoYP++9//ysPDQ61bt7b6uPraMisokLUIZkAO5+HhoWbNmqlZs2ZKTU3VCy+8oM8//1xvvvmmypYtm+lfGrPCDz/8oKSkJH3//fdOfzXP6NKkG9UVHBysc+fOqUGDBjfdV1BQkJYsWaJz5845/bKxa9eu26z+xvtJ2+61lx5evnxZ+/fvv2Wd1ytcuLDy5cuXYZ07d+6Um5tbujOTWSUoKEg7duzIcFlaPWnHmxm3+uxlJO3syfUzWt7ozGNwcLD69u2rvn37as+ePQoNDdVHH32k//73vwoODpZ0NSTe7H1IO6a0M1HXupPPS1BQkFJTU7Vnzx6nCXWOHTumhIQEl17La6Udl6+v7y0/X9OnT1d0dLQ++ugjq+3SpUvpXt/g4GBt27btturJasHBwTLGqHTp0rf8Q8vNfn6Fh4dr6NChWrx4sQoVKqTy5cvL4XCoYsWKWrVqlVatWuUUmK4dy9fbuXOnChUqlOnp8B0Oh6ZMmaLmzZvr6aef1rx585xmls0sV35mSlfPmvXp00dHjx7V1KlTFRUVZY0pybXXFkDW4x4zIAc7efKk03M3NzdVqVJFkqzputN+0biTqd0zK+0vtNdfTjVhwoR0fb28vDKsqXXr1lq7dq0WLFiQbllCQoJ1P1uTJk105coVp2mlU1JSNGrUqDs9DCcNGjSQh4eHRo4c6XRc48aNU2JiojX7myQdPHhQO3fuvOn23N3d1bBhQ82ZM8dpSvNjx45p6tSpqlOnjnUJXlZr0qSJDh8+rNmzZzu1JyUlWTPnVatWLVPbysxnLyNBQUFyd3d3mlFPuvp1BNe6cOGCLl265NQWHBwsHx8fa/uRkZHy9fXVe++9l+E04mlfe1CsWDGFhoZq0qRJTpf3LVq06IZBNTOaNGkiSdZMoWk+/vhjSXL6bLiievXqCg4O1ocffpjh1OvXfp2Du7t7ujNZo0aNSncGslWrVvrtt98y/IqAe312uGXLlnJ3d9egQYPS7dsY4/TZ8vLyuuG9qeHh4UpKStKIESNUp04dK8SFh4frq6++0pEjR6z7yyTnz8G1P3u2bdumhQsXWu9nZnl4eGjmzJl65JFH1KxZM61fv96l9SXXfmZKUtu2beVwOPTSSy/p999/T/e9gq68tgCyHmfMgPvYvHnzMvxF/7HHHlOZMmX0r3/9S6dOndITTzyhEiVK6I8//tCoUaMUGhpq/QU/NDRU7u7uGjp0qBITE+Xp6Wl9Z05Wa9iwoXUW5fnnn9e5c+f0xRdfqEiRIjp69KhT3+rVq2vs2LF65513VLZsWRUpUkRPPPGE+vXrp++//15NmzZVx44dVb16dZ0/f15bt27V9OnTdeDAARUqVEjNmjVT7dq19dprr+nAgQMKCQnRzJkzMzXBiCsKFy6s/v37a9CgQWrUqJGeeuop7dq1S2PGjNEjjzzi9ItRhw4dtGLFilv+ovvOO+9o0aJFqlOnjl544QXlypVLn3/+uZKSkjRs2LA7qnfJkiXpAo0ktWjRQt26ddP48eP19NNPq3Pnznr44Yd18uRJffPNN9q2bZsmT56c6ftNMvPZy4ifn5+efvppjRo1Sg6HQ8HBwZo7d65172Ca3bt3KyIiQq1bt1ZISIhy5cqlWbNm6dixY2rTpo2kq2eUxo4dq/bt26tatWpq06aNChcurIMHD+rHH39U7dq19emnn0q6+hUQUVFRqlOnjjp37qxTp05p1KhRqlixosvfO5WmatWqio6O1v/93/8pISFB9erV0/r16zVp0iS1aNFCjz/++G1t183NTV9++aUaN26sihUrqlOnTnrggQf0559/atmyZfL19dUPP/wgSWratKm++uor+fn5KSQkRGvXrtXixYutez7T9OvXT9OnT7fe++rVq+vUqVP6/vvv9dlnn6lq1aq3VevtCA4O1jvvvKP+/fvrwIEDatGihXx8fLR//37NmjVL3bp108svvyzp6s+Jb775Rn369NEjjzwib29vNWvWTJIUFhamXLlyadeuXerWrZu1/bp161p/sLk2mElXLw9t3LixwsLC1KVLF2u6fD8/Pw0cONDlY8mbN6/mzp2rJ554Qo0bN9aKFStUqVKlTK/vys9M6erPo0aNGum7776Tv79/uvDvymsL4C64t5NAArgXbjZdvq6ZUnz69OmmYcOGpkiRIsbDw8OULFnSPP/88+bo0aNO2/viiy9MmTJljLu7u9NU5TeaLv+7777LsJ4NGzY4tadN/XzixAmr7fvvvzdVqlQxefLkMaVKlTJDhw4148ePN5LM/v37rX7x8fEmKirK+Pj4GElOdZw9e9b079/flC1b1nh4eJhChQqZxx57zHz44YdO0/ifPHnStG/f3vj6+ho/Pz/Tvn17s3nzZpemy7/+mG40nfunn35qypcvb3Lnzm2KFi1qunfvbk6fPu3UJ2366czYtGmTiYyMNN7e3iZfvnzm8ccfN2vWrHHqczvT5d/o8dVXXxljrk5D37t3b1O6dGmTO3du4+vrax5//HEzb968m27/+mnLM/vZy8iJEydMq1atTL58+Uz+/PnN888/b7Zt2+b0vv31118mJibGlC9f3nh5eRk/Pz9Ts2ZN8+2336bb3rJly0xkZKTx8/MzefLkMcHBwaZjx47m119/deo3Y8YMU6FCBePp6WlCQkLMzJkzTXR09G1Pl2+MMcnJyWbQoEHW6xkYGGj69++fbur0m31VwY1s3rzZtGzZ0hQsWNB4enqaoKAg07p1a7NkyRKrz+nTp02nTp1MoUKFjLe3t4mMjDQ7d+40QUFBJjo62ml7J0+eND169DAPPPCA8fDwMCVKlDDR0dHmr7/+MsbcePxf/1UGN5LRzwNj/jfWrh3/xlx9P+rUqWO8vLyMl5eXKV++vImJiTG7du2y+pw7d848++yzxt/fP8OvNnjkkUeMJLNu3Tqr7fDhw0aSCQwMzLDOxYsXm9q1a5u8efMaX19f06xZM7Njx45MHYsxGX8W/vrrLxMSEmICAgLMnj17bvkaXSuzPzPTfPvtt0aS6dat2w33k5nXtl69eqZixYo33AYA1zmMuQ/vUAcAAEA6c+bMUYsWLbRy5cp0ZwQB2ItgBgAAkEM0bdpUcXFx2rt37z2d3AnArXGPGQAAwH1u2rRp2rJli3788Ud98sknhDIgG+KMGQAAwH3O4XDI29tbzzzzjD777LN79j19ADKPUQkAAHCf4+/wQPbH95gBAAAAgM0IZgAAAABgMy5llJSamqojR47Ix8eHm2EBAACAHMwYo7Nnz6p48eJyc7t357EIZpKOHDmiwMBAu8sAAAAAkE0cOnRIJUqUuGf7I5hJ8vHxkXT1xff19bW5GgAAAAB2OXPmjAIDA62McK8QzCTr8kVfX1+CGQAAAIB7fosTk38AAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANgsl90FAMDd5hjksLsEW5kBxu4ScB9iXDGukLUYU4wpglk2xMBkYAIAACBn4VJGAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwma3BbOzYsapSpYp8fX3l6+ursLAwzZs3z1p+6dIlxcTEqGDBgvL29larVq107Ngxp20cPHhQUVFRypcvn4oUKaJ+/frpypUr9/pQAAAAAOC22RrMSpQooffff18bN27Ur7/+qieeeELNmzfX9u3bJUm9e/fWDz/8oO+++04rVqzQkSNH1LJlS2v9lJQURUVF6fLly1qzZo0mTZqkiRMn6q233rLrkAAAAADAZQ5jjLG7iGsVKFBAH3zwgf75z3+qcOHCmjp1qv75z39Kknbu3KkKFSpo7dq1qlWrlubNm6emTZvqyJEjKlq0qCTps88+06uvvqoTJ07Iw8MjU/s8c+aM/Pz8lJiYKF9f37t2bJnlGOSwuwRbmQHZ6iOJ+wBjijGFrMe4YlwhazGmss+YsisbZJt7zFJSUjRt2jSdP39eYWFh2rhxo5KTk9WgQQOrT/ny5VWyZEmtXbtWkrR27VpVrlzZCmWSFBkZqTNnzlhn3TKSlJSkM2fOOD0AAAAAwC62B7OtW7fK29tbnp6e+ve//61Zs2YpJCRE8fHx8vDwkL+/v1P/okWLKj4+XpIUHx/vFMrSlqctu5EhQ4bIz8/PegQGBmbtQQEAAACAC2wPZuXKlVNsbKzWrVun7t27Kzo6Wjt27Lir++zfv78SExOtx6FDh+7q/gAAAADgZnLZXYCHh4fKli0rSapevbo2bNigTz75RM8884wuX76shIQEp7Nmx44dU0BAgCQpICBA69evd9pe2qyNaX0y4unpKU9Pzyw+EgAAAAC4PbafMbteamqqkpKSVL16deXOnVtLliyxlu3atUsHDx5UWFiYJCksLExbt27V8ePHrT6LFi2Sr6+vQkJC7nntAAAAAHA7bD1j1r9/fzVu3FglS5bU2bNnNXXqVC1fvlwLFiyQn5+funTpoj59+qhAgQLy9fVVz549FRYWplq1akmSGjZsqJCQELVv317Dhg1TfHy83njjDcXExHBGDAAAAMDfhq3B7Pjx4+rQoYOOHj0qPz8/ValSRQsWLNCTTz4pSRo+fLjc3NzUqlUrJSUlKTIyUmPGjLHWd3d319y5c9W9e3eFhYXJy8tL0dHRGjx4sF2HBAAAAAAuszWYjRs37qbL8+TJo9GjR2v06NE37BMUFKSffvopq0sDAAAAgHsm291jBgAAAAA5DcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbGZrMBsyZIgeeeQR+fj4qEiRImrRooV27drl1Kd+/fpyOBxOj3//+99OfQ4ePKioqCjly5dPRYoUUb9+/XTlypV7eSgAAAAAcNty2bnzFStWKCYmRo888oiuXLmi119/XQ0bNtSOHTvk5eVl9evatasGDx5sPc+XL5/175SUFEVFRSkgIEBr1qzR0aNH1aFDB+XOnVvvvffePT0eAAAAALgdtgaz+fPnOz2fOHGiihQpoo0bN6pu3bpWe758+RQQEJDhNhYuXKgdO3Zo8eLFKlq0qEJDQ/X222/r1Vdf1cCBA+Xh4XFXjwEAAAAA7lS2uscsMTFRklSgQAGn9ilTpqhQoUKqVKmS+vfvrwsXLljL1q5dq8qVK6to0aJWW2RkpM6cOaPt27dnuJ+kpCSdOXPG6QEAAAAAdrH1jNm1UlNT1atXL9WuXVuVKlWy2p999lkFBQWpePHi2rJli1599VXt2rVLM2fOlCTFx8c7hTJJ1vP4+PgM9zVkyBANGjToLh0JAAAAALgm2wSzmJgYbdu2TT///LNTe7du3ax/V65cWcWKFVNERIT27dun4ODg29pX//791adPH+v5mTNnFBgYeHuFAwAAAMAdyhaXMvbo0UNz587VsmXLVKJEiZv2rVmzpiRp7969kqSAgAAdO3bMqU/a8xvdl+bp6SlfX1+nBwAAAADYxdZgZoxRjx49NGvWLC1dulSlS5e+5TqxsbGSpGLFikmSwsLCtHXrVh0/ftzqs2jRIvn6+iokJOSu1A0AAAAAWcnWSxljYmI0depUzZkzRz4+PtY9YX5+fsqbN6/27dunqVOnqkmTJipYsKC2bNmi3r17q27duqpSpYokqWHDhgoJCVH79u01bNgwxcfH64033lBMTIw8PT3tPDwAAAAAyBRbz5iNHTtWiYmJql+/vooVK2Y9vvnmG0mSh4eHFi9erIYNG6p8+fLq27evWrVqpR9++MHahru7u+bOnSt3d3eFhYXpueeeU4cOHZy+9wwAAAAAsjNbz5gZY266PDAwUCtWrLjldoKCgvTTTz9lVVkAAAAAcE9li8k/AAAAACAnI5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzl4PZ/Pnz9fPPP1vPR48erdDQUD377LM6ffp0lhYHAAAAADmBy8GsX79+OnPmjCRp69at6tu3r5o0aaL9+/erT58+WV4gAAAAANzvcrm6wv79+xUSEiJJmjFjhpo2bar33ntPmzZtUpMmTbK8QAAAAAC437l8xszDw0MXLlyQJC1evFgNGzaUJBUoUMA6kwYAAAAAyLxMB7POnTvr7Nmzql27tvr06aO3335b69evV1RUlCRp9+7dKlGixF0rFAAAAADuV5kOZpMmTdLFixc1evRo5cqVS9OnT9fYsWP1wAMPSJLmzZunRo0a3bVCAQAAAOB+lel7zIwxkqSSJUtq7ty56ZYPHz4866oCAAAAgBzEpck/zp49qzx58ty0j6+v7x0VBAAAAAA5jUvB7KGHHrrhMmOMHA6HUlJS7rgoAAAAAMhJXApm06dPV4ECBe5WLQAAAACQI7kUzGrXrq0iRYrcrVoAAAAAIEdy+XvMAAAAAABZK9PBLCgoSO7u7lm68yFDhuiRRx6Rj4+PihQpohYtWmjXrl1OfS5duqSYmBgVLFhQ3t7eatWqlY4dO+bU5+DBg4qKilK+fPlUpEgR9evXT1euXMnSWgEAAADgbsl0MNu/f78KFiyYpTtfsWKFYmJi9Msvv2jRokVKTk5Ww4YNdf78eatP79699cMPP+i7777TihUrdOTIEbVs2dJanpKSoqioKF2+fFlr1qzRpEmTNHHiRL311ltZWisAAAAA3C2Zvscsf/78cjgc6dr9/Pz00EMP6eWXX9aTTz7p0s7nz5/v9HzixIkqUqSINm7cqLp16yoxMVHjxo3T1KlT9cQTT0iSJkyYoAoVKuiXX35RrVq1tHDhQu3YsUOLFy9W0aJFFRoaqrfffluvvvqqBg4cKA8Pj3T7TUpKUlJSkvX8zJkzLtUNAAAAAFkp08Fs+PDhGQazhIQEbdy4UU2bNtX06dPVrFmz2y4mMTFRkqyZHzdu3Kjk5GQ1aNDA6lO+fHmVLFlSa9euVa1atbR27VpVrlxZRYsWtfpERkaqe/fu2r59ux5++OF0+xkyZIgGDRp023UCAAAAQFbKdDDr2LHjTZeHhoZqyJAhtx3MUlNT1atXL9WuXVuVKlWSJMXHx8vDw0P+/v5OfYsWLar4+Hirz7WhLG152rKM9O/fX3369LGenzlzRoGBgbdVNwAAAADcqSyblbFp06bauXPnba8fExOjbdu2adq0aVlV0g15enrK19fX6QEAAAAAdsmyYJaUlJTh/VyZ0aNHD82dO1fLli1TiRIlrPaAgABdvnxZCQkJTv2PHTumgIAAq8/1szSmPU/rAwAAAADZWZYFs3Hjxik0NNSldYwx6tGjh2bNmqWlS5eqdOnSTsurV6+u3Llza8mSJVbbrl27dPDgQYWFhUmSwsLCtHXrVh0/ftzqs2jRIvn6+iokJOT2DwgAAAAA7pFM32N27T1Z10pMTNSmTZu0e/durVy50qWdx8TEaOrUqZozZ458fHyse8L8/PyUN29e+fn5qUuXLurTp48KFCggX19f9ezZU2FhYapVq5YkqWHDhgoJCVH79u01bNgwxcfH64033lBMTIw8PT1dqgcAAAAA7JDpYLZ58+YM2319ffXkk09q5syZ6c543crYsWMlSfXr13dqnzBhgjXZyPDhw+Xm5qZWrVopKSlJkZGRGjNmjNXX3d1dc+fOVffu3RUWFiYvLy9FR0dr8ODBLtUCAAAAAHbJdDBbtmzZTZcfPnxY3bp10//93/9leufGmFv2yZMnj0aPHq3Ro0ffsE9QUJB++umnTO8XAAAAALKTLLvH7OTJkxo3blxWbQ4AAAAAcowsC2YAAAAAgNtDMAMAAAAAmxHMAAAAAMBmmZ78o2XLljddfv2XQAMAAAAAMifTwczPz++Wyzt06HDHBQEAAABATpPpYDZhwoS7WQcAAAAA5FjcYwYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYLFPBrFq1ajp9+rQkafDgwbpw4cJdLQoAAAAAcpJMBbO4uDidP39ekjRo0CCdO3furhYFAAAAADlJpqbLDw0NVadOnVSnTh0ZY/Thhx/K29s7w75vvfVWlhYIAAAAAPe7TAWziRMnasCAAZo7d64cDofmzZunXLnSr+pwOAhmAAAAAOCiTAWzcuXKadq0aZIkNzc3LVmyREWKFLmrhQEAAABATpGpYHat1NTUu1EHAAAAAORYLgczSdq3b59GjBihuLg4SVJISIheeuklBQcHZ2lxAAAAAJATuPw9ZgsWLFBISIjWr1+vKlWqqEqVKlq3bp0qVqyoRYsW3Y0aAQAAAOC+5vIZs9dee029e/fW+++/n6791Vdf1ZNPPpllxQEAAABATuDyGbO4uDh16dIlXXvnzp21Y8eOLCkKAAAAAHISl4NZ4cKFFRsbm649NjaWmRoBAAAA4Da4fClj165d1a1bN/3+++967LHHJEmrV6/W0KFD1adPnywvEAAAAADudy4HszfffFM+Pj766KOP1L9/f0lS8eLFNXDgQL344otZXiAAAAAA3O9cDmYOh0O9e/dW7969dfbsWUmSj49PlhcGAAAAADnFbX2PWRoCGQAAAADcOZcn/wAAAAAAZC2CGQAAAADYjGAGAAAAADZzKZglJycrIiJCe/bsuVv1AAAAAECO41Iwy507t7Zs2XK3agEAAACAHMnlSxmfe+45jRs37m7UAgAAAAA5ksvT5V+5ckXjx4/X4sWLVb16dXl5eTkt//jjj7OsOAAAAADICVwOZtu2bVO1atUkSbt373Za5nA4sqYqAAAAAMhBXA5my5Ytuxt1AAAAAECOddvT5e/du1cLFizQxYsXJUnGmCwrCgAAAAByEpeD2cmTJxUREaGHHnpITZo00dGjRyVJXbp0Ud++fbO8QAAAAAC437kczHr37q3cuXPr4MGDypcvn9X+zDPPaP78+VlaHAAAAADkBC7fY7Zw4UItWLBAJUqUcGp/8MEH9ccff2RZYQAAAACQU7h8xuz8+fNOZ8rSnDp1Sp6enllSFAAAAADkJC4Hs/DwcE2ePNl67nA4lJqaqmHDhunxxx/P0uIAAAAAICdw+VLGYcOGKSIiQr/++qsuX76sV155Rdu3b9epU6e0evXqu1EjAAAAANzXXD5jVqlSJe3evVt16tRR8+bNdf78ebVs2VKbN29WcHDw3agRAAAAAO5rLp8xkyQ/Pz/95z//yepaAAAAACBHuq1gdvr0aY0bN05xcXGSpJCQEHXq1EkFChTI0uIAAAAAICdw+VLGlStXqlSpUho5cqROnz6t06dPa+TIkSpdurRWrlx5N2oEAAAAgPuay8EsJiZGzzzzjPbv36+ZM2dq5syZ+v3339WmTRvFxMS4tK2VK1eqWbNmKl68uBwOh2bPnu20vGPHjnI4HE6PRo0aOfU5deqU2rVrJ19fX/n7+6tLly46d+6cq4cFAAAAALZxOZjt3btXffv2lbu7u9Xm7u6uPn36aO/evS5t6/z586patapGjx59wz6NGjXS0aNHrcfXX3/ttLxdu3bavn27Fi1apLlz52rlypXq1q2bawcFAAAAADZy+R6zatWqKS4uTuXKlXNqj4uLU9WqVV3aVuPGjdW4ceOb9vH09FRAQECGy+Li4jR//nxt2LBBNWrUkCSNGjVKTZo00YcffqjixYu7VA8AAAAA2CFTwWzLli3Wv1988UW99NJL2rt3r2rVqiVJ+uWXXzR69Gi9//77WV7g8uXLVaRIEeXPn19PPPGE3nnnHRUsWFCStHbtWvn7+1uhTJIaNGggNzc3rVu3Tv/4xz8y3GZSUpKSkpKs52fOnMnyugEAAAAgszIVzEJDQ+VwOGSMsdpeeeWVdP2effZZPfPMM1lWXKNGjdSyZUuVLl1a+/bt0+uvv67GjRtr7dq1cnd3V3x8vIoUKeK0Tq5cuVSgQAHFx8ffcLtDhgzRoEGDsqxOAAAAALgTmQpm+/fvv9t1ZKhNmzbWvytXrqwqVaooODhYy5cvV0RExG1vt3///urTp4/1/MyZMwoMDLyjWgEAAADgdmUqmAUFBd3tOjKlTJkyKlSokPbu3auIiAgFBATo+PHjTn2uXLmiU6dO3fC+NOnqfWuenp53u1wAAAAAyJTb+oLpI0eO6Oeff9bx48eVmprqtOzFF1/MksIycvjwYZ08eVLFihWTJIWFhSkhIUEbN25U9erVJUlLly5VamqqatasedfqAAAAAICs5HIwmzhxop5//nl5eHioYMGCcjgc1jKHw+FSMDt37pzTFPv79+9XbGysChQooAIFCmjQoEFq1aqVAgICtG/fPr3yyisqW7asIiMjJUkVKlRQo0aN1LVrV3322WdKTk5Wjx491KZNG2ZkBAAAAPC34XIwe/PNN/XWW2+pf//+cnNz+WvQnPz66696/PHHredp931FR0dr7Nix2rJliyZNmqSEhAQVL15cDRs21Ntvv+10GeKUKVPUo0cPRUREyM3NTa1atdLIkSPvqC4AAAAAuJdcDmYXLlxQmzZt7jiUSVL9+vWdZnq83oIFC265jQIFCmjq1Kl3XAsAAAAA2MXldNWlSxd99913d6MWAAAAAMiRXD5jNmTIEDVt2lTz589X5cqVlTt3bqflH3/8cZYVBwAAAAA5wW0FswULFqhcuXKSlG7yDwAAAACAa1wOZh999JHGjx+vjh073oVyAAAAACDncfkeM09PT9WuXftu1AIAAAAAOZLLweyll17SqFGj7kYtAAAAAJAjuXwp4/r167V06VLNnTtXFStWTDf5x8yZM7OsOAAAAADICVwOZv7+/mrZsuXdqAUAAAAAciSXg9mECRPuRh0AAAAAkGO5fI8ZAAAAACBruXzGrHTp0jf9vrLff//9jgoCAAAAgJzG5WDWq1cvp+fJycnavHmz5s+fr379+mVVXQAAAACQY7gczF566aUM20ePHq1ff/31jgsCAAAAgJwmy+4xa9y4sWbMmJFVmwMAAACAHCPLgtn06dNVoECBrNocAAAAAOQYLl/K+PDDDztN/mGMUXx8vE6cOKExY8ZkaXEAAAAAkBO4HMxatGjh9NzNzU2FCxdW/fr1Vb58+ayqCwAAAAByDJeD2YABA+5GHQAAAACQY/EF0wAAAABgs0yfMXNzc7vpF0tLksPh0JUrV+64KAAAAADISTIdzGbNmnXDZWvXrtXIkSOVmpqaJUUBAAAAQE6S6WDWvHnzdG27du3Sa6+9ph9++EHt2rXT4MGDs7Q4AAAAAMgJbusesyNHjqhr166qXLmyrly5otjYWE2aNElBQUFZXR8AAAAA3PdcCmaJiYl69dVXVbZsWW3fvl1LlizRDz/8oEqVKt2t+gAAAADgvpfpSxmHDRumoUOHKiAgQF9//XWGlzYCAAAAAFyX6WD22muvKW/evCpbtqwmTZqkSZMmZdhv5syZWVYcAAAAAOQEmQ5mHTp0uOV0+QAAAAAA12U6mE2cOPEulgEAAAAAOddtzcoIAAAAAMg6BDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALCZrcFs5cqVatasmYoXLy6Hw6HZs2c7LTfG6K233lKxYsWUN29eNWjQQHv27HHqc+rUKbVr106+vr7y9/dXly5ddO7cuXt4FAAAAABwZ2wNZufPn1fVqlU1evToDJcPGzZMI0eO1GeffaZ169bJy8tLkZGRunTpktWnXbt22r59uxYtWqS5c+dq5cqV6tat2706BAAAAAC4Y7ns3Hnjxo3VuHHjDJcZYzRixAi98cYbat68uSRp8uTJKlq0qGbPnq02bdooLi5O8+fP14YNG1SjRg1J0qhRo9SkSRN9+OGHKl68+D07FgAAAAC4Xdn2HrP9+/crPj5eDRo0sNr8/PxUs2ZNrV27VpK0du1a+fv7W6FMkho0aCA3NzetW7fuhttOSkrSmTNnnB4AAAAAYJdsG8zi4+MlSUWLFnVqL1q0qLUsPj5eRYoUcVqeK1cuFShQwOqTkSFDhsjPz896BAYGZnH1AAAAAJB52TaY3U39+/dXYmKi9Th06JDdJQEAAADIwbJtMAsICJAkHTt2zKn92LFj1rKAgAAdP37cafmVK1d06tQpq09GPD095evr6/QAAAAAALtk22BWunRpBQQEaMmSJVbbmTNntG7dOoWFhUmSwsLClJCQoI0bN1p9li5dqtTUVNWsWfOe1wwAAAAAt8PWWRnPnTunvXv3Ws/379+v2NhYFShQQCVLllSvXr30zjvv6MEHH1Tp0qX15ptvqnjx4mrRooUkqUKFCmrUqJG6du2qzz77TMnJyerRo4fatGnDjIwAAAAA/jZsDWa//vqrHn/8cet5nz59JEnR0dGaOHGiXnnlFZ0/f17dunVTQkKC6tSpo/nz5ytPnjzWOlOmTFGPHj0UEREhNzc3tWrVSiNHjrznxwIAAAAAt8vWYFa/fn0ZY2643OFwaPDgwRo8ePAN+xQoUEBTp069G+UBAAAAwD2Rbe8xAwAAAICcgmAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNsnUwGzhwoBwOh9OjfPny1vJLly4pJiZGBQsWlLe3t1q1aqVjx47ZWDEAAAAAuC5bBzNJqlixoo4ePWo9fv75Z2tZ79699cMPP+i7777TihUrdOTIEbVs2dLGagEAAADAdbnsLuBWcuXKpYCAgHTtiYmJGjdunKZOnaonnnhCkjRhwgRVqFBBv/zyi2rVqnXDbSYlJSkpKcl6fubMmawvHAAAAAAyKdufMduzZ4+KFy+uMmXKqF27djp48KAkaePGjUpOTlaDBg2svuXLl1fJkiW1du3am25zyJAh8vPzsx6BgYF39RgAAAAA4GaydTCrWbOmJk6cqPnz52vs2LHav3+/wsPDdfbsWcXHx8vDw0P+/v5O6xQtWlTx8fE33W7//v2VmJhoPQ4dOnQXjwIAAAAAbi5bX8rYuHFj699VqlRRzZo1FRQUpG+//VZ58+a97e16enrK09MzK0oEAAAAgDuWrc+YXc/f318PPfSQ9u7dq4CAAF2+fFkJCQlOfY4dO5bhPWkAAAAAkF39rYLZuXPntG/fPhUrVkzVq1dX7ty5tWTJEmv5rl27dPDgQYWFhdlYJQAAAAC4Jltfyvjyyy+rWbNmCgoK0pEjRzRgwAC5u7urbdu28vPzU5cuXdSnTx8VKFBAvr6+6tmzp8LCwm46IyMAAAAAZDfZOpgdPnxYbdu21cmTJ1W4cGHVqVNHv/zyiwoXLixJGj58uNzc3NSqVSslJSUpMjJSY8aMsblqAAAAAHBNtg5m06ZNu+nyPHnyaPTo0Ro9evQ9qggAAAAAst7f6h4zAAAAALgfEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZvdNMBs9erRKlSqlPHnyqGbNmlq/fr3dJQEAAABAptwXweybb75Rnz59NGDAAG3atElVq1ZVZGSkjh8/bndpAAAAAHBL90Uw+/jjj9W1a1d16tRJISEh+uyzz5QvXz6NHz/e7tIAAAAA4JZy2V3Anbp8+bI2btyo/v37W21ubm5q0KCB1q5dm+E6SUlJSkpKsp4nJiZKks6cOXN3i82sS3YXYK9s8z7g/sGYsrsE3I8YV3aXgPsNY8ruEixptRhj7ul+//bB7K+//lJKSoqKFi3q1F60aFHt3Lkzw3WGDBmiQYMGpWsPDAy8KzXCNX7v+9ldAnBfYUwBWY9xBWSt7Dimzp49Kz+/e1fX3z6Y3Y7+/furT58+1vPU1FSdOnVKBQsWlMPhsLEy+505c0aBgYE6dOiQfH197S4H+NtjTAFZj3EFZC3GlDNjjM6ePavixYvf0/3+7YNZoUKF5O7urmPHjjm1Hzt2TAEBARmu4+npKU9PT6c2f3//u1Xi35Kvry8DE8hCjCkg6zGugKzFmPqfe3mmLM3ffvIPDw8PVa9eXUuWLLHaUlNTtWTJEoWFhdlYGQAAAABkzt/+jJkk9enTR9HR0apRo4YeffRRjRgxQufPn1enTp3sLg0AAAAAbum+CGbPPPOMTpw4obfeekvx8fEKDQ3V/Pnz000Iglvz9PTUgAED0l3qCeD2MKaArMe4ArIWYyp7cJh7PQ8kAAAAAMDJ3/4eMwAAAAD4uyOYAQAAAIDNCGYAAAAAYDOC2W0qVaqURowYYXcZfzsHDhyQw+FQbGzsXd8X79HfD+/Z7WFc4UZ4v24PYwo3w3t2exhXmWD+xqKjo40k8/zzz6db9sILLxhJJjo6OlPb2r9/v5FkNm/enKn+x48fN+fPn89U36ZNm5rIyMgMl61cudJIMr/99lumtnUjy5YtM5LM6dOn72g717tw4YLJnz+/KViwoLl06ZJL60ZHR5vmzZs7tV25csUcPXrUJCcnZ1mNEyZMMH5+funaXXmPssqnn35qgoKCjKenp3n00UfNunXr7un+swLj6n8YV37p2u/1uFqxYoVp2rSpKVasmJFkZs2adc/2nVUYU//DmPJL136vx9R7771natSoYby9vU3hwoVN8+bNzc6dO+/Z/rMK4+p/GFd+6drv9bgaM2aMqVy5svHx8TE+Pj6mVq1a5qeffnJ5O3/7M2aBgYGaNm2aLl68aLVdunRJU6dOVcmSJbN8f5cvX5YkFS5cWPny5cvUOl26dNGiRYt0+PDhdMsmTJigGjVqqEqVKlla5+0yxujKlSvW8xkzZqhixYoqX768Zs+efcfbd3d3V0BAgHLluvvf1ODKe5QVvvnmG/Xp00cDBgzQpk2bVLVqVUVGRur48eP3rIaswrjKWoyr23f+/HlVrVpVo0ePvmf7vBsYU1mLMXX7VqxYoZiYGP3yyy9atGiRkpOT1bBhQ50/f/6e1ZBVGFdZi3F1+0qUKKH3339fGzdu1K+//qonnnhCzZs31/bt213bUBYHxnsqLY1XqlTJ/Pe//7Xap0yZYqpUqWKaN29u/bVk3rx5pnbt2sbPz88UKFDAREVFmb1791rrSHJ61KtXz2kf77zzjilWrJgpVaqUMcaYoKAgM3z4cGPM1b9U5M6d26xcudLa3tChQ03hwoVNfHy8SU5ONkWLFjVvv/22U/1nz5413t7eZuzYscYYY1atWmXq1Klj8uTJY0qUKGF69uxpzp07Z/W/dOmSeeWVV0yJEiWMh4eHCQ4ONl9++aX1l55rH2nHfenSJdOzZ09TuHBh4+npaWrXrm3Wr19vbTPtryw//fSTqVatmsmdO7dZtmyZtbx+/frms88+M2PHjjVPPvlkuvdg27ZtJioqyvj4+Bhvb29Tp04ds3fvXjNgwIB0NS1btszpr1IpKSnmgQceMGPGjHHa5qZNm4zD4TAHDhwwxhjz0UcfmUqVKpl8+fKZEiVKmO7du5uzZ8861X/tY8CAAeneI2OM+eOPP8xTTz1lvLy8jI+Pj3n66adNfHy8tXzAgAGmatWqZvLkySYoKMj4+vqaZ555xpw5cybdcWfk0UcfNTExMdbzlJQUU7x4cTNkyJBMrZ9dMK4YV9lpXF1Lf+MzZowpxlR2HFPGXD2zIMmsWLHitta3C+OKcZWdx5UxxuTPn998+eWXLq1zXwSzjz/+2ERERFjtERERZvjw4U6Dcvr06WbGjBlmz549ZvPmzaZZs2amcuXKJiUlxRhjzPr1640ks3jxYnP06FFz8uRJax/e3t6mffv2Ztu2bWbbtm3GmPRveL9+/UxQUJBJSEgwmzZtMh4eHmbOnDlOy4ODg01qaqrVNn78eJM3b16TkJBg9u7da7y8vMzw4cPN7t27zerVq83DDz9sOnbsaPVv3bq1CQwMNDNnzjT79u0zixcvNtOmTTNXrlwxM2bMMJLMrl27zNGjR01CQoIxxpgXX3zRFC9e3Pz0009m+/btJjo62uTPn986vrQPdZUqVczChQvN3r17rWV79+41np6e5tSpU+bkyZMmT5481kAxxpjDhw+bAgUKmJYtW5oNGzaYXbt2mfHjx5udO3eas2fPmtatW5tGjRqZo0ePmqNHj5qkpKR0lwu8/PLLpk6dOk7va9++fZ3ahg8fbpYuXWr2799vlixZYsqVK2e6d+9ujDEmKSnJjBgxwvj6+lr7SRuw175HKSkpJjQ01NSpU8f8+uuv5pdffjHVq1e3fvgac3VQent7m5YtW5qtW7ealStXmoCAAPP666/f8DOYJikpybi7u6f7pbFDhw7mqaeeuuX62QnjinGVXcbV9f7uwYwxxZjKbmPKGGP27NljJJmtW7fe1vp2YVwxrrLruLpy5Yr5+uuvjYeHh9m+fbtL694Xwez48ePG09PTHDhwwBw4cMDkyZPHnDhxwmlQXu/EiRNOP4hudH1xdHS0KVq0qElKSnJqv35QJiUlmdDQUNO6dWsTEhJiunbt6tQ/Li7O+otBmvDwcPPcc88ZY4zp0qWL6datm9M6q1atMm5ububixYtm165dRpJZtGhRhseT0fXF586dM7lz5zZTpkyx2i5fvmyKFy9uhg0b5rTe7Nmz023z9ddfNy1atLCeN2/e3PpLhDHG9O/f35QuXdpcvnw5w5oyur74+td58+bNxuFwmD/++MMYY6y/oKT9BSkj3333nSlYsKD1/EbXF1/7Hi1cuNC4u7ubgwcPWsu3b99uJFl/PRowYIDJly+f019H+vXrZ2rWrHnDWtL8+eefRpJZs2aNU3u/fv3Mo48+esv1sxPG1f8wrvzS9buX4+p6f/dgxphiTGW3MZWSkmKioqJM7dq1XV7Xboyr/2Fc+aXrZ8e42rJli/Hy8jLu7u7Gz8/P/Pjjj5leN83f/h4z6ep1pFFRUZo4caImTJigqKgoFSpUyKnPnj171LZtW5UpU0a+vr4qVaqUJOngwYO33H7lypXl4eFx0z4eHh6aMmWKZsyYoUuXLmn48OFOy8uXL6/HHntM48ePlyTt3btXq1atUpcuXSRJv/32myZOnChvb2/rERkZqdTUVO3fv1+xsbFyd3dXvXr1MvuyaN++fUpOTlbt2rWttty5c+vRRx9VXFycU98aNWo4PU9JSdGkSZP03HPPWW3PPfecJk6cqNTUVElSbGyswsPDlTt37kzXdL3Q0FBVqFBBU6dOlXT12vfjx4/r6aeftvosXrxYEREReuCBB+Tj46P27dvr5MmTunDhQqb3ExcXp8DAQAUGBlptISEh8vf3d3otSpUqJR8fH+t5sWLF/pb3iGUFxlXGGFf/w7hyDWMqY4yp/7nXYyomJkbbtm3TtGnTXF43u2BcZYxx9T/3alyVK1dOsbGxWrdunbp3767o6Gjt2LEj0+tL99F0+Z07d9bEiRM1adIkde7cOd3yZs2a6dSpU/riiy+0bt06rVu3TtL/buS8GS8vr0zVsGbNGknSqVOndOrUqXTLu3TpohkzZujs2bOaMGGCgoODrUF27tw5Pf/884qNjbUev/32m/bs2aPg4GDlzZs3UzXcruuPccGCBfrzzz/1zDPPKFeuXMqVK5fatGmjP/74Q0uWLJGkLKupXbt21qCcOnWqGjVqpIIFC0q6OrVq06ZNVaVKFc2YMUMbN260JgHIzHvnqut/wDgcDuuH0M0UKlRI7u7uOnbsmFP7sWPHFBAQkKU13kuMqzvDuLrqdsfV/YgxdWcYU1dlxZjq0aOH5s6dq2XLlqlEiRJZWd49x7i6M4yrq+50XHl4eKhs2bKqXr26hgwZoqpVq+qTTz5xqYb7Jpg1atRIly9fVnJysiIjI52WnTx5Urt27dIbb7yhiIgIVahQQadPn3bqk/bXkJSUlNva/759+9S7d2998cUXqlmzpqKjo9O9ma1bt5abm5umTp2qyZMnq3PnznI4HJKkatWqaceOHSpbtmy6h4eHhypXrqzU1FStWLEiw/1nVH9wcLA8PDy0evVqqy05OVkbNmxQSEjITY9n3LhxatOmjdMPidjYWLVp00bjxo2TJFWpUkWrVq1ScnLyDWvKzOv57LPPatu2bdq4caOmT5+udu3aWcs2btyo1NRUffTRR6pVq5YeeughHTlyxOX9VKhQQYcOHdKhQ4esth07dighIeGWr0VmeHh4qHr16tYPLElKTU3VkiVLFBYWdsfbtwvjinF1M3d7XN2PGFOMqZu5F2PKGKMePXpo1qxZWrp0qUqXLp0l27UT44pxdTN2/b8qNTVVSUlJrq3k8sWP2cj1168mJiaaxMRE63na9cUpKSmmYMGC5rnnnjN79uwxS5YsMY888ojT/QrJyckmb9685p133jHx8fHWjZMZXSNrjPO1q1euXDG1atUyrVq1MsYYc+TIEVOwYEHrGt5rdenSxeTPn9+4u7ubP//802r/7bffTN68eU1MTIzZvHmz2b17t5k9e7bTLH8dO3Y0gYGBZtasWeb33383y5YtM998840x5upNmA6Hw0ycONEcP37cuvnxpZdeMsWLFzfz5s1zuvHz1KlTxpiMr0s+fvy4yZ07t5k3b166+n/66Sfj6elpTp48af766y9TsGBB68bP3bt3m8mTJ1vfh/Luu++akiVLmp07d5oTJ06Yy5cv3/A67tq1a5uqVasaHx8fc+HCBas9NjbWSDIjRoww+/btM5MnTzYPPPCAU82rV6+2bto9ceKE9b0V175HqampJjQ01ISHh5uNGzeadevWZXjjZ9WqVZ3qGj58uAkKCkr3OmRk2rRpxtPT00ycONHs2LHDdOvWzfj7+zvN+vN3wLhiXBmTfcbV2bNnzebNm83mzZuNJPPxxx+bzZs3W/ck/B0wphhTxmSfMdW9e3fj5+dnli9fbk2YcPToUafj+TtgXDGujMk+4+q1114zK1asMPv37zdbtmwxr732mnE4HGbhwoWZWj/NfRXMrnftjZ+LFi0yFSpUMJ6enqZKlSpm+fLl6W4k/+KLL0xgYKBxc3NLN1Xq9a59wwcNGmSKFStm/vrrL2v5jBkzjIeHh4mNjXVab82aNUaSadKkSbptrl+/3jz55JPG29vbeHl5mSpVqph3333XWn7x4kXTu3dvU6xYMePh4WHKli1rxo8fby0fPHiwCQgIMA6Hwzruixcvmp49e5pChQrddKrUawflhx9+aPz9/TO8oTMpKcn4+/ubTz75xBhz9YdJw4YNTb58+YyPj48JDw83+/btM8ZcHdxpx6MMpkq91pgxY4wk06FDh3T7/Pjjj02xYsVM3rx5TWRkpJk8eXK6mv/973+bggULZslUqddyZVAaY8yoUaNMyZIljYeHh3n00UfNL7/8kul1swvGFeMqTXYYVxlNhyxl/otjswPGFGMqTXYYUxmNJ0lmwoQJmVo/u2BcMa7SZIdx1blzZxMUFGQ8PDxM4cKFTUREhMuhzBhjHMYY49o5NgAAAABAVrpv7jEDAAAAgL8rghmQCQcPHnSaxvb6R2am3AXgjHEFZC3GFJD17uW44lJGIBOuXLmiAwcO3HB5qVKllCtXrntXEHAfYFwBWYsxBWS9ezmuCGYAAAAAYDMuZQQAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAEBS/fr11atXr0z3X758uRwOhxISEu5aTQCAnINgBgC4Ix07dpTD4dD777/v1D579mw5HA6XtlWqVCmNGDEiC6sDAODvgWAGALhjefLk0dChQ3X69Gm7S3HZ5cuX7S7hjiQnJ9tdAgAgCxDMAAB3rEGDBgoICNCQIUNu2u/nn39WeHi48ubNq8DAQL344os6f/68pKuXEv7xxx/q3bu3HA6HHA6HjDEqXLiwpk+fbm0jNDRUxYoVc9qmp6enLly4IEk6ePCgmjdvLm9vb/n6+qp169Y6duyY1X/gwIEKDQ3Vl19+qdKlSytPnjwZ1vrjjz/Kz89PU6ZMydRrcPLkSbVt21YPPPCA8uXLp8qVK+vrr7+2lk+ePFkFCxZUUlKS03otWrRQ+/btredz5sxRtWrVlCdPHpUpU0aDBg3SlStXrOUOh0Njx47VU089JS8vL7377rs6ffq02rVrp8KFCytv3rx68MEHNWHChEzVDQDIHghmAIA75u7urvfee0+jRo3S4cOHM+yzb98+NWrUSK1atdKWLVv0zTff6Oeff1aPHj0kSTNnzlSJEiU0ePBgHT16VEePHpXD4VDdunW1fPlySdLp06cVFxenixcvaufOnZKkFStW6JFHHlG+fPmUmpqq5s2b69SpU1qxYoUWLVqk33//Xc8884xTLXv37tWMGTM0c+ZMxcbGpqt16tSpatu2raZMmaJ27dpl6jW4dOmSqlevrh9//FHbtm1Tt27d1L59e61fv16S9PTTTyslJUXff/+9tc7x48f1448/qnPnzpKkVatWqUOHDnrppZe0Y8cOff7555o4caLeffddp30NHDhQ//jHP7R161Z17txZb775pnbs2KF58+YpLi5OY8eOVaFChTJVNwAgmzAAANyB6Oho07x5c2OMMbVq1TKdO3c2xhgza9Ysc+3/Zrp06WK6devmtO6qVauMm5ubuXjxojHGmKCgIDN8+HCnPiNHjjQVK1Y0xhgze/ZsU7NmTdO8eXMzduxYY4wxDRo0MK+//roxxpiFCxcad3d3c/DgQWv97du3G0lm/fr1xhhjBgwYYHLnzm2OHz/utJ969eqZl156yXz66afGz8/PLF++/KbHvWzZMiPJnD59+oZ9oqKiTN++fa3n3bt3N40bN7aef/TRR6ZMmTImNTXVGGNMRESEee+995y28dVXX5lixYpZzyWZXr16OfVp1qyZ6dSp003rBQBkb5wxAwBkmaFDh2rSpEmKi4tLt+y3337TxIkT5e3tbT0iIyOVmpqq/fv333Cb9erV044dO3TixAmtWLFC9evXV/369bV8+XIlJydrzZo1ql+/viQpLi5OgYGBCgwMtNYPCQmRv7+/U01BQUEqXLhwun1Nnz5dvXv31qJFi1SvXj2Xjj0lJUVvv/22KleurAIFCsjb21sLFizQwYMHrT5du3bVwoUL9eeff0qSJk6caE2ekvYaDR482Ok16tq1q44ePWpdqilJNWrUcNp39+7dNW3aNIWGhuqVV17RmjVrXKodAGA/ghkAIMvUrVtXkZGR6t+/f7pl586d0/PPP6/Y2Fjr8dtvv2nPnj0KDg6+4TbTgs6KFSucgtmKFSu0YcMGJScn67HHHnOpTi8vrwzbH374YRUuXFjjx4+XMcalbX7wwQf65JNP9Oqrr2rZsmWKjY1VZGSk0+QiDz/8sKpWrarJkydr48aN2r59uzp27GgtP3funAYNGuT0Gm3dulV79uxxuhfu+vobN25s3Z935MgRRURE6OWXX3apfgCAvXLZXQAA4P7y/vvvKzQ0VOXKlXNqr1atmnbs2KGyZcvecF0PDw+lpKQ4tTkcDoWHh2vOnDnavn276tSpo3z58ikpKUmff/65atSoYQWVChUq6NChQzp06JB11mzHjh1KSEhQSEjILWsPDg7WRx99pPr168vd3V2ffvpppo979erVat68uZ577jlJUmpqqnbv3p1uv//61780YsQI/fnnn2rQoIHT2b1q1app165dN32NbqRw4cKKjo5WdHS0wsPD1a9fP3344YcubwcAYA/OmAEAslTlypXVrl07jRw50qn91Vdf1Zo1a9SjRw/FxsZqz549mjNnjjX5h3T1e8xWrlypP//8U3/99ZfVXr9+fX399dcKDQ2Vt7e33NzcVLduXU2ZMsXpksMGDRpY+9+0aZPWr1+vDh06qF69euku/7uRhx56SMuWLdOMGTNc+sLpBx98UIsWLdKaNWsUFxen559/3mk2yDTPPvusDh8+rC+++MKa9CPNW2+9pcmTJ2vQoEHavn274uLiNG3aNL3xxhs33fdbb72lOXPmaO/evdq+fbvmzp2rChUqZLp2AID9CGYAgCw3ePBgpaamOrVVqVJFK1as0O7duxUeHq6HH35Yb731looXL+603oEDBxQcHOx0D1i9evWUkpJi3UsmXQ1r17c5HA7NmTNH+fPnV926ddWgQQOVKVNG33zzjUv1lytXTkuXLtXXX3+tvn37ZmqdN954Q9WqVVNkZKTq16+vgIAAtWjRIl0/Pz8/tWrVSt7e3umWR0ZGau7cuVq4cKEeeeQR1apVS8OHD1dQUNBN9+3h4aH+/furSpUqqlu3rtzd3TVt2rTMHi4AIBtwGFcvogcAAHckIiJCFStWTHdWEQCQcxHMAAC4R06fPq3ly5frn//8p3bs2JHuPjwAQM7F5B8AANwjDz/8sE6fPq2hQ4cSygAATjhjBgAAAAA2Y/IPAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBm/w/0qOvg3rATgQAAAABJRU5ErkJggg==", + "text/plain": [ + "
    " + ] + }, + "metadata": {}, + "output_type": "display_data" + } + ], + "source": [ + "# Extracting LUTs from res_dict\n", + "LUTs = [res_dict[key][\"LUT\"] for key in res_dict.keys()] \n", "\n", - "So our goal to adjust the folding parameters would be to expand the computation of the first layer to reduce its latency at the expense an of increase in resource utilization." + "#Plotting the bar graph of each network layer with their corresponding LUT resource utilization\n", + "fig = plt.figure(figsize = (10, 5))\n", + "plt.bar(res_dict.keys(), LUTs, color ='green', width = 0.3)\n", + "plt.xlabel(\"Network layers\")\n", + "plt.ylabel(\"Number of LUTs\")\n", + "plt.title(\"Estimated no. of LUTs used for each network layer\")\n", + "plt.show()" ] }, { "cell_type": "markdown", "metadata": {}, "source": [ - "
    \n", - "Question in the first line of the above cell.\n", - "
    " + "Since we identified above that the first layer takes the highest number of cycles to complete the execution, we will now try to adjust the folding parameters to reduce its latency at the expense of an increase in resource utilization." ] }, { @@ -1931,7 +1925,12 @@ "source": [ "## Modify Parameters\n", "\n", - "We now modify the parallelization attributes of the first network layer to reduce its overall latency." + "We now modify the parallelization attributes of the first network layer to reduce its overall latency.\n", + "We now individually extract the `MatrixVectorActivation` blocks from the onnx file and set the config values manually (although this can be done automatically by Vivado tools also as mentioned in the introduction).\n", + "\n", + "In the first step, we set the `PE` & `SIMD` values for all the layers to be '1' to establish a baseline and measure the estimated clock cycles and resource utilization for each of the individual layers.\n", + "\n", + "We utilize from (`getCustomOp()`) as the helper function to set different properties of the node. The (`set_nodeattr()`) function within this function call helps us set these values." ] }, { @@ -2061,8 +2060,8 @@ "metadata": {}, "outputs": [], "source": [ - "res_dict_updated = []\n", - "res_dict_updated = res_estimation(model)" + "res_dict_updated = model.analysis(res_estimation)\n", + "res_dict_updated" ] }, { @@ -2082,16 +2081,12 @@ } ], "source": [ - "layers_updated = list(res_dict_updated.keys())\n", - "utilisation_updated = list(res_dict_updated.values())\n", - "lut_values_updated = [] #Initializing a list to store LUT values.\n", - "for i in range(len(layers_updated)):\n", - " x = list(utilisation_updated[i].values()) #Extracting the resource utilisation for each layer.\n", - " lut_values_updated.append(x[2]) #Extracting the LUT values of resource utilisation from each layer and appending to the list\n", + "# Extracting LUTs from res_dict\n", + "LUTs_updated = [res_dict[key][\"LUT\"] for key in res_dict_updated.keys()] \n", "\n", - "#Plotting the bar graph of each network layer with their corresponding LUT resource utilisation\n", + "#Plotting the bar graph of each network layer with their corresponding LUT resource utilization\n", "fig = plt.figure(figsize = (10, 5))\n", - "plt.bar(layers_updated, lut_values_updated, color ='green', width = 0.3)\n", + "plt.bar(res_dict_updated.keys(), LUTs_updated, color ='green', width = 0.3)\n", "plt.xlabel(\"Network Layers\")\n", "plt.ylabel(\"LUT Utilisation\")\n", "plt.title(\"Estimated LUT values used for each network layer\")\n", diff --git a/notebooks/advanced/finn-dataflow.png b/notebooks/advanced/finn-dataflow.png new file mode 100755 index 0000000000000000000000000000000000000000..ebe98d0fbd1878fabb9ae2d87bd9b111d62dc39e GIT binary patch literal 164258 zcmbrlcTiK|*ELEn(nWzt2^|rnO7BGi(nXq7Nf4z-2Pp|vKnM_uBGRQw6-1;Xs3D*d ziWos42tf#)5K01p%kQ0g=gxiK@B99_d*)1X@|>L6`)OzGwbyxWV+CTnbnOxq6&0JA zsqtMZDtbXGDjGi~hKpYUgl~0Td{Bqp1sPH`j|t!}PUw6LEDflrTC-VBAJAW%GY6SE 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From 5180d1f987f11a27471a86a0ee061b333f9d7fba Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Tue, 27 Jun 2023 07:51:41 +0100 Subject: [PATCH 172/665] Change end2end tests to use board type as opposed to kind to allow for more boards to be parameterized Signed-off-by: Fionn O'Donohoe --- src/finn/util/test.py | 22 +++---- tests/end2end/test_end2end_bnn_pynq.py | 84 +++++++++++------------- tests/end2end/test_end2end_cybsec_mlp.py | 6 +- tests/end2end/test_ext_weights.py | 6 +- 4 files changed, 54 insertions(+), 64 deletions(-) diff --git a/src/finn/util/test.py b/src/finn/util/test.py index 4250079ef3..3545e2be8e 100644 --- a/src/finn/util/test.py +++ b/src/finn/util/test.py @@ -106,26 +106,26 @@ def load_test_checkpoint_or_skip(filename): pytest.skip(filename + " not found from previous test step, skipping") -def get_build_env(kind, target_clk_ns): +def get_build_env(board, target_clk_ns): """Get board-related build environment for testing. - - kind = either zynq or alveo. + - board = any from pynq_part_map or alveo_part_map """ ret = {} - if kind == "zynq": - ret["board"] = os.getenv("PYNQ_BOARD", default="Pynq-Z1") - ret["part"] = pynq_part_map[ret["board"]] - ret["build_fxn"] = ZynqBuild(ret["board"], target_clk_ns) - elif kind == "alveo": - ret["board"] = os.getenv("ALVEO_BOARD", default="U250") - ret["part"] = alveo_part_map[ret["board"]] + if board in pynq_part_map: + ret["kind"] = "zynq" + ret["part"] = pynq_part_map[board] + ret["build_fxn"] = ZynqBuild(board, target_clk_ns) + elif board in alveo_part_map: + ret["kind"] = "alveo" + ret["part"] = alveo_part_map[board] ret["build_fxn"] = VitisBuild( ret["part"], target_clk_ns, - alveo_default_platform[ret["board"]], + alveo_default_platform[board], strategy=VitisOptStrategy.BUILD_SPEED, ) else: - raise Exception("Unknown test build environment spec") + raise Exception("Unknown board specified") return ret diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index 27aaa1986d..5274d923c1 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -296,7 +296,7 @@ def topology2dataset(topology): @pytest.mark.parametrize("QONNX_export", [False, True]) @pytest.mark.end2end class TestEnd2End: - def test_export(self, topology, wbits, abits, QONNX_export): + def test_export(self, topology, wbits, abits, QONNX_export, board): if wbits > abits: pytest.skip("No wbits > abits end2end network configs for now") if topology == "lfc" and not (wbits == 1 and abits == 1): @@ -313,7 +313,7 @@ def test_export(self, topology, wbits, abits, QONNX_export): export_finn_onnx(model, torch.randn(ishape), chkpt_name) assert os.path.isfile(chkpt_name) - def test_import_and_tidy(self, topology, wbits, abits, QONNX_export): + def test_import_and_tidy(self, topology, wbits, abits, QONNX_export, board): prev_chkpt_name = get_checkpoint_name( topology, wbits, abits, QONNX_export, "export" ) @@ -329,7 +329,7 @@ def test_import_and_tidy(self, topology, wbits, abits, QONNX_export): ) model.save(chkpt) - def test_add_pre_and_postproc(self, topology, wbits, abits, QONNX_export): + def test_add_pre_and_postproc(self, topology, wbits, abits, QONNX_export, board): prev_chkpt_name = get_checkpoint_name( topology, wbits, abits, QONNX_export, "import_and_tidy" ) @@ -366,7 +366,7 @@ def test_add_pre_and_postproc(self, topology, wbits, abits, QONNX_export): model.save(chkpt_name) assert os.path.isfile(chkpt_name) - def test_streamline(self, topology, wbits, abits, QONNX_export): + def test_streamline(self, topology, wbits, abits, QONNX_export, board): prev_chkpt_name = get_checkpoint_name( topology, wbits, abits, QONNX_export, "pre_post" ) @@ -389,7 +389,7 @@ def test_streamline(self, topology, wbits, abits, QONNX_export): get_checkpoint_name(topology, wbits, abits, QONNX_export, "streamline") ) - def test_convert_to_hls_layers(self, topology, wbits, abits, QONNX_export): + def test_convert_to_hls_layers(self, topology, wbits, abits, QONNX_export, board): prev_chkpt_name = get_checkpoint_name( topology, wbits, abits, QONNX_export, "streamline" ) @@ -455,7 +455,7 @@ def test_convert_to_hls_layers(self, topology, wbits, abits, QONNX_export): for (op_type, exp_count) in exp_layer_counts: assert len(model.get_nodes_by_op_type(op_type)) == exp_count - def test_create_dataflow_partition(self, topology, wbits, abits, QONNX_export): + def test_create_dataflow_partition(self, topology, wbits, abits, QONNX_export, board): prev_chkpt_name = get_checkpoint_name( topology, wbits, abits, QONNX_export, "convert_to_hls_layers" ) @@ -474,7 +474,7 @@ def test_create_dataflow_partition(self, topology, wbits, abits, QONNX_export): ) dataflow_model.save(dataflow_model_chkpt) - def test_fold(self, topology, wbits, abits, QONNX_export): + def test_fold(self, topology, wbits, abits, QONNX_export, board): prev_chkpt_name = get_checkpoint_name( topology, wbits, abits, QONNX_export, "dataflow_model" ) @@ -483,7 +483,7 @@ def test_fold(self, topology, wbits, abits, QONNX_export): model = folding_fxn(model) model.save(get_checkpoint_name(topology, wbits, abits, QONNX_export, "fold")) - def test_minimize_bit_width(self, topology, wbits, abits, QONNX_export): + def test_minimize_bit_width(self, topology, wbits, abits, QONNX_export, board): prev_chkpt_name = get_checkpoint_name( topology, wbits, abits, QONNX_export, "fold" ) @@ -497,7 +497,7 @@ def test_minimize_bit_width(self, topology, wbits, abits, QONNX_export): @pytest.mark.slow @pytest.mark.vivado - def test_cppsim(self, topology, wbits, abits, QONNX_export): + def test_cppsim(self, topology, wbits, abits, QONNX_export, board): prev_chkpt_name = get_checkpoint_name( topology, wbits, abits, QONNX_export, "minimize_bit_width" ) @@ -520,49 +520,46 @@ def test_cppsim(self, topology, wbits, abits, QONNX_export): @pytest.mark.slow @pytest.mark.vivado - @pytest.mark.parametrize("kind", ["zynq", "alveo"]) - def test_ipgen(self, topology, wbits, abits, QONNX_export, kind): - if kind == "alveo" and ("VITIS_PATH" not in os.environ): + def test_ipgen(self, topology, wbits, abits, QONNX_export, board): + build_data = get_build_env(board, target_clk_ns) + if build_data["kind"] == "alveo" and ("VITIS_PATH" not in os.environ): pytest.skip("VITIS_PATH not set") prev_chkpt_name = get_checkpoint_name( topology, wbits, abits, QONNX_export, "fold" ) model = load_test_checkpoint_or_skip(prev_chkpt_name) - test_fpga_part = get_build_env(kind, target_clk_ns)["part"] model = model.transform(GiveUniqueNodeNames()) - model = model.transform(PrepareIP(test_fpga_part, target_clk_ns)) + model = model.transform(PrepareIP(build_data["part"], target_clk_ns)) model = model.transform(HLSSynthIP()) model.save( - get_checkpoint_name(topology, wbits, abits, QONNX_export, "ipgen_" + kind) + get_checkpoint_name(topology, wbits, abits, QONNX_export, "ipgen_" + board) ) @pytest.mark.slow @pytest.mark.vivado - @pytest.mark.parametrize("kind", ["zynq", "alveo"]) - def test_set_fifo_depths(self, topology, wbits, abits, QONNX_export, kind): + def test_set_fifo_depths(self, topology, wbits, abits, QONNX_export, board): prev_chkpt_name = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "ipgen_" + kind + topology, wbits, abits, QONNX_export, "ipgen_" + board ) model = load_test_checkpoint_or_skip(prev_chkpt_name) - test_fpga_part = get_build_env(kind, target_clk_ns)["part"] + test_fpga_part = get_build_env(board, target_clk_ns)["part"] model = model.transform(InsertAndSetFIFODepths(test_fpga_part, target_clk_ns)) fifo_layers = model.get_nodes_by_op_type("StreamingFIFO") assert len(fifo_layers) > 0 model.save( get_checkpoint_name( - topology, wbits, abits, QONNX_export, "fifodepth_" + kind + topology, wbits, abits, QONNX_export, "fifodepth_" + board ) ) @pytest.mark.slow @pytest.mark.vivado - @pytest.mark.parametrize("kind", ["zynq"]) - def test_ipstitch_rtlsim(self, topology, wbits, abits, QONNX_export, kind): + def test_ipstitch_rtlsim(self, topology, wbits, abits, QONNX_export, board): prev_chkpt_name = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "fifodepth_" + kind + topology, wbits, abits, QONNX_export, "fifodepth_" + board ) model = load_test_checkpoint_or_skip(prev_chkpt_name) - test_fpga_part = get_build_env(kind, target_clk_ns)["part"] + test_fpga_part = get_build_env(board, target_clk_ns)["part"] model = model.transform(InsertDWC()) model = model.transform(GiveUniqueNodeNames()) model = model.transform(AnnotateCycles()) @@ -582,7 +579,7 @@ def test_ipstitch_rtlsim(self, topology, wbits, abits, QONNX_export, kind): ) os.environ["RTLSIM_TRACE_DEPTH"] = "3" rtlsim_chkpt = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "ipstitch_rtlsim_" + kind + topology, wbits, abits, QONNX_export, "ipstitch_rtlsim_" + board ) model.save(rtlsim_chkpt) parent_chkpt = get_checkpoint_name( @@ -596,10 +593,9 @@ def test_ipstitch_rtlsim(self, topology, wbits, abits, QONNX_export, kind): @pytest.mark.slow @pytest.mark.vivado - @pytest.mark.parametrize("kind", ["zynq"]) - def test_throughput_rtlsim(self, topology, wbits, abits, QONNX_export, kind): + def test_throughput_rtlsim(self, topology, wbits, abits, QONNX_export, board): prev_chkpt_name = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "ipstitch_rtlsim_" + kind + topology, wbits, abits, QONNX_export, "ipstitch_rtlsim_" + board ) model = load_test_checkpoint_or_skip(prev_chkpt_name) n_nodes = len(model.graph.node) @@ -615,8 +611,7 @@ def test_throughput_rtlsim(self, topology, wbits, abits, QONNX_export, kind): @pytest.mark.slow @pytest.mark.vivado - @pytest.mark.parametrize("kind", ["zynq"]) - def test_validate_top1(self, topology, wbits, abits, QONNX_export, kind): + def test_validate_top1(self, topology, wbits, abits, QONNX_export, board): if "TEST_END2END_VALIDATE_TOP1" not in os.environ: pytest.skip("TEST_END2END_VALIDATE_TOP1 not set") prepostproc_chkpt = get_checkpoint_name( @@ -632,7 +627,7 @@ def test_validate_top1(self, topology, wbits, abits, QONNX_export, kind): topology, wbits, abits, QONNX_export, "cppsim" ) rtlsim_chkpt = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "ipstitch_rtlsim_" + kind + topology, wbits, abits, QONNX_export, "ipstitch_rtlsim_" + board ) dataset = topology2dataset(topology) assert measure_top1_accuracy(prepostproc_chkpt, dataset) > 80 @@ -643,34 +638,33 @@ def test_validate_top1(self, topology, wbits, abits, QONNX_export, kind): @pytest.mark.slow @pytest.mark.vivado @pytest.mark.vitis - @pytest.mark.parametrize("kind", ["zynq", "alveo"]) - def test_build(self, topology, wbits, abits, QONNX_export, kind): - if kind == "alveo" and ("VITIS_PATH" not in os.environ): + def test_build(self, topology, wbits, abits, QONNX_export, board): + build_data = get_build_env(board, target_clk_ns) + if build_data["kind"] == "alveo" and ("VITIS_PATH" not in os.environ): pytest.skip("VITIS_PATH not set") prev_chkpt_name = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "fifodepth_" + kind + topology, wbits, abits, QONNX_export, "fifodepth_" + board ) model = load_test_checkpoint_or_skip(prev_chkpt_name) - cfg = get_build_env(kind, target_clk_ns) - model = model.transform(cfg["build_fxn"]) + model = model.transform(build_data["build_fxn"]) model = model.transform(AnnotateResources("synth")) model.save( - get_checkpoint_name(topology, wbits, abits, QONNX_export, "build_" + kind) + get_checkpoint_name(topology, wbits, abits, QONNX_export, "build_" + board) ) @pytest.mark.slow @pytest.mark.vivado @pytest.mark.vitis - @pytest.mark.parametrize("kind", ["zynq", "alveo"]) - def test_make_pynq_driver(self, topology, wbits, abits, QONNX_export, kind): - if kind == "alveo" and ("VITIS_PATH" not in os.environ): + def test_make_pynq_driver(self, topology, wbits, abits, QONNX_export, board): + build_data = get_build_env(board, target_clk_ns) + if build_data["kind"] == "alveo" and ("VITIS_PATH" not in os.environ): pytest.skip("VITIS_PATH not set") prev_chkpt_name = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "build_" + kind + topology, wbits, abits, QONNX_export, "build_" + board ) model = load_test_checkpoint_or_skip(prev_chkpt_name) - kind_to_driver_platform = {"zynq": "zynq-iodma", "alveo": "alveo"} - model = model.transform(MakePYNQDriver(kind_to_driver_platform[kind])) + board_to_driver_platform = "alveo" if build_data["kind"] == "alveo" else "zynq-iodma" + model = model.transform(MakePYNQDriver(board_to_driver_platform)) model.save( - get_checkpoint_name(topology, wbits, abits, QONNX_export, "driver_" + kind) + get_checkpoint_name(topology, wbits, abits, QONNX_export, "driver_" + board) ) diff --git a/tests/end2end/test_end2end_cybsec_mlp.py b/tests/end2end/test_end2end_cybsec_mlp.py index 5e402bdeb4..ba1de29735 100644 --- a/tests/end2end/test_end2end_cybsec_mlp.py +++ b/tests/end2end/test_end2end_cybsec_mlp.py @@ -48,10 +48,9 @@ import finn.builder.build_dataflow_config as build_cfg from finn.transformation.qonnx.convert_qonnx_to_finn import ConvertQONNXtoFINN from finn.util.basic import make_build_dir -from finn.util.test import get_build_env, load_test_checkpoint_or_skip +from finn.util.test import load_test_checkpoint_or_skip target_clk_ns = 10 -build_kind = "zynq" build_dir = os.environ["FINN_BUILD_DIR"] @@ -183,14 +182,13 @@ def test_end2end_cybsec_mlp_export(QONNX_export): def test_end2end_cybsec_mlp_build(QONNX_export): model_file = get_checkpoint_name("export", QONNX_export) load_test_checkpoint_or_skip(model_file) - build_env = get_build_env(build_kind, target_clk_ns) output_dir = make_build_dir(f"test_end2end_cybsec_mlp_build_QONNX-{QONNX_export}") cfg = build.DataflowBuildConfig( output_dir=output_dir, target_fps=1000000, synth_clk_period_ns=target_clk_ns, - board=build_env["board"], + board="Pynq-Z1", shell_flow_type=build_cfg.ShellFlowType.VIVADO_ZYNQ, generate_outputs=[ build_cfg.DataflowOutputType.ESTIMATE_REPORTS, diff --git a/tests/end2end/test_ext_weights.py b/tests/end2end/test_ext_weights.py index bef2e0ffa7..8bbfb4be9a 100644 --- a/tests/end2end/test_ext_weights.py +++ b/tests/end2end/test_ext_weights.py @@ -38,10 +38,9 @@ import finn.builder.build_dataflow as build import finn.builder.build_dataflow_config as build_cfg from finn.util.basic import make_build_dir -from finn.util.test import get_build_env, load_test_checkpoint_or_skip +from finn.util.test import load_test_checkpoint_or_skip target_clk_ns = 10 -build_kind = "zynq" build_dir = os.environ["FINN_BUILD_DIR"] onnx_zip_url = "https://github.com/Xilinx/finn-examples" onnx_zip_url += "/releases/download/v0.0.1a/onnx-models-bnn-pynq.zip" @@ -83,7 +82,6 @@ def test_end2end_ext_weights_download(): def test_end2end_ext_weights_build(): model_file = get_checkpoint_name("download") load_test_checkpoint_or_skip(model_file) - build_env = get_build_env(build_kind, target_clk_ns) folding_config_file = pk.resource_filename( "finn.qnn-data", "test_ext_weights/tfc-w1a1-extw.json" ) @@ -93,7 +91,7 @@ def test_end2end_ext_weights_build(): verbose=True, folding_config_file=folding_config_file, synth_clk_period_ns=target_clk_ns, - board=build_env["board"], + board="Pynq-Z1", shell_flow_type=build_cfg.ShellFlowType.VIVADO_ZYNQ, generate_outputs=[ build_cfg.DataflowOutputType.ESTIMATE_REPORTS, From 56e43152931207189741034659b34e626da63705 Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Tue, 27 Jun 2023 07:56:08 +0100 Subject: [PATCH 173/665] Add test_deploy method for BNN end2end tests for Jenkins setup Signed-off-by: Fionn O'Donohoe --- tests/end2end/test_end2end_bnn_pynq.py | 52 +++++++++++++++++++++++++- 1 file changed, 51 insertions(+), 1 deletion(-) diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index 5274d923c1..02ea7c24ff 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -38,6 +38,8 @@ import warnings from brevitas.export import export_finn_onnx, export_qonnx from dataset_loading import cifar, mnist +from distutils.dir_util import copy_tree +from shutil import copy from qonnx.core.datatype import DataType from qonnx.core.modelwrapper import ModelWrapper from qonnx.custom_op.registry import getCustomOp @@ -89,7 +91,7 @@ MakeMaxPoolNHWC, MoveScalarLinearPastInvariants, ) -from finn.util.basic import get_finn_root +from finn.util.basic import get_finn_root, make_build_dir from finn.util.pytorch import ToTensor from finn.util.test import ( execute_parent, @@ -290,6 +292,42 @@ def topology2dataset(topology): raise Exception("Unrecognized topology") +def deploy_based_on_board(model, model_title, topology, wbits, abits, board): + if os.environ.get('FINN_DEPLOY_DIR') is not None: + deploy_dir_root = os.environ["FINN_DEPLOY_DIR"] + else: + deploy_dir_root = make_build_dir(prefix="hw_deployment_" + board + "_") + # Set it for the next round if multiple bitstreams are selected for generation + os.environ["FINN_DEPLOY_DIR"] = deploy_dir_root + + # create directory for deployment files + deployment_dir = deploy_dir_root + "/" + board + "/" + model_title + os.makedirs(deployment_dir) + model.set_metadata_prop("pynq_deployment_dir", deployment_dir) + + # get and copy necessary files + # .bit and .hwh file + bitfile = model.get_metadata_prop("bitfile") + hwh_file = model.get_metadata_prop("hw_handoff") + deploy_files = [bitfile, hwh_file] + + for dfile in deploy_files: + if dfile is not None: + copy(dfile, deployment_dir) + + # create input and output test files + (input_tensor_npy, output_tensor_npy) = get_golden_io_pair( + topology, wbits, abits, return_topk=1 + ) + np.save(os.path.join(deployment_dir, "input.npy"), input_tensor_npy) + np.save(os.path.join(deployment_dir, "output_reference.npy"), output_tensor_npy) + + # driver.py and python libraries + pynq_driver_dir = model.get_metadata_prop("pynq_driver_dir") + copy_tree(pynq_driver_dir, deployment_dir) + model.set_metadata_prop("pynq_deploy_dir", deployment_dir) + + @pytest.mark.parametrize("wbits", [1, 2]) @pytest.mark.parametrize("abits", [1, 2]) @pytest.mark.parametrize("topology", ["lfc", "tfc", "cnv"]) @@ -668,3 +706,15 @@ def test_make_pynq_driver(self, topology, wbits, abits, QONNX_export, board): model.save( get_checkpoint_name(topology, wbits, abits, QONNX_export, "driver_" + board) ) + + def test_deploy(self, topology, wbits, abits, QONNX_export, board): + prev_chkpt_name = get_checkpoint_name( + topology, wbits, abits, QONNX_export, "driver_" + board + ) + model = load_test_checkpoint_or_skip(prev_chkpt_name) + model_title = "%s_w%d_a%d_%s_QE-%s" % ("bnn", wbits, abits, topology, QONNX_export) + deploy_based_on_board(model, model_title, topology, wbits, abits, board) + # save the model to be able to link it to the parent + model.save( + get_checkpoint_name(topology, wbits, abits, QONNX_export, "deploy_" + board) + ) From 5c03333b923194a1f3c4d2359b7f8701aa2f4410 Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Tue, 27 Jun 2023 07:59:58 +0100 Subject: [PATCH 174/665] Add parameterized tests for all supported boards. Split test matrix by board marker Signed-off-by: Fionn O'Donohoe --- src/finn/util/basic.py | 3 ++ tests/end2end/test_end2end_bnn_pynq.py | 69 ++++++++++++++++++++++++-- 2 files changed, 67 insertions(+), 5 deletions(-) diff --git a/src/finn/util/basic.py b/src/finn/util/basic.py index 3bc5b803db..abbf85d37d 100644 --- a/src/finn/util/basic.py +++ b/src/finn/util/basic.py @@ -31,6 +31,9 @@ import sys import tempfile +# supported boards +test_support_board_map = ["Pynq-Z1", "KV260_SOM", "ZCU104", "U250"] + # mapping from PYNQ board names to FPGA part names pynq_part_map = dict() pynq_part_map["Ultra96"] = "xczu3eg-sbva484-1-e" diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index 02ea7c24ff..30bbadb6fc 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -328,11 +328,70 @@ def deploy_based_on_board(model, model_title, topology, wbits, abits, board): model.set_metadata_prop("pynq_deploy_dir", deployment_dir) -@pytest.mark.parametrize("wbits", [1, 2]) -@pytest.mark.parametrize("abits", [1, 2]) -@pytest.mark.parametrize("topology", ["lfc", "tfc", "cnv"]) -@pytest.mark.parametrize("QONNX_export", [False, True]) -@pytest.mark.end2end +# parameters that make up inputs to test case(s) +def get_full_parameterized_test_list(marker, wbits_list, abits_list, topology_list, QONNX_export_list, board_list): + test_cases = [ + (f'{marker}_w{param1}_a{param2}_{param3}_QE{param4}_{param5}', { + 'wbits': param1, + 'abits': param2, + 'topology': param3, + 'QONNX_export': param4, + 'board': param5 + }) + for param1, param2, param3, param4, param5 in itertools.product( + wbits_list, + abits_list, + topology_list, + QONNX_export_list, + board_list, + ) + ] + return test_cases + + +def pytest_generate_tests(metafunc): + idlist = [] + argvalues = [] + scenarios = [] + + # Full set of test parameters + wbits = [1, 2] + abits = [1, 2] + topology = ["lfc", "tfc", "cnv"] + QONNX_export = [False, True] + + # Separate the full list of markers used on command line. + # This allows a user to select multiple markers + all_markers_used = metafunc.config.getoption("-m").split(" ") + + for marker in all_markers_used: + if "sanity_bnn" in marker: + # Define a set of sanity tests that target each of the supported boards with fixed parameters + scenarios.extend(get_full_parameterized_test_list("sanity_bnn", wbits_list=[1], abits_list=[1], topology_list=["lfc"], QONNX_export_list=[False], board_list=[test_support_board_map[0]])) + scenarios.extend(get_full_parameterized_test_list("sanity_bnn", wbits_list=[1], abits_list=[2], topology_list=["cnv"], QONNX_export_list=[True], board_list=[test_support_board_map[1]])) + scenarios.extend(get_full_parameterized_test_list("sanity_bnn", wbits_list=[2], abits_list=[2], topology_list=["tfc"], QONNX_export_list=[False], board_list=[test_support_board_map[2]])) + scenarios.extend(get_full_parameterized_test_list("sanity_bnn", wbits_list=[2], abits_list=[2], topology_list=["cnv"], QONNX_export_list=[True], board_list=[test_support_board_map[3]])) + + if "bnn_" in marker: + # Target the full set of parameters for a single board + # Extract the board name from the marker used, as it is in the form of 'bnn_' + bnn_board = next((element for element in test_support_board_map if marker.split("_")[1] in element.lower()), None) + test_cases = get_full_parameterized_test_list("bnn", wbits, abits, topology, QONNX_export, [bnn_board]) + scenarios.extend(test_cases) + + if len(scenarios) > 0: + for scenario in scenarios: + idlist.append(scenario[0]) + items = scenario[1].items() + argnames = [x[0] for x in items] + argvalues.append([x[1] for x in items]) + metafunc.parametrize(argnames, argvalues, ids=idlist, scope="class") + +@pytest.mark.sanity_bnn +@pytest.mark.bnn_pynq +@pytest.mark.bnn_zcu104 +@pytest.mark.bnn_kv260 +@pytest.mark.bnn_u250 class TestEnd2End: def test_export(self, topology, wbits, abits, QONNX_export, board): if wbits > abits: From 8c98882a1609f5c5cbd6aa853756806132ed545b Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Tue, 27 Jun 2023 08:03:06 +0100 Subject: [PATCH 175/665] Add scripts used by Jenkins to test bnn end2end hardware tests Signed-off-by: Fionn O'Donohoe --- docker/jenkins/hack_driver_script.py | 53 ++++++++ docker/jenkins/test_bnn_hw_pytest.py | 177 +++++++++++++++++++++++++++ 2 files changed, 230 insertions(+) create mode 100755 docker/jenkins/hack_driver_script.py create mode 100755 docker/jenkins/test_bnn_hw_pytest.py diff --git a/docker/jenkins/hack_driver_script.py b/docker/jenkins/hack_driver_script.py new file mode 100755 index 0000000000..cd3becf7cf --- /dev/null +++ b/docker/jenkins/hack_driver_script.py @@ -0,0 +1,53 @@ +import os + +def remove_cache_dirs(dir_list): + tmp_list = list(dir_list) + for i in range(len(tmp_list)-1, -1, -1): + if ".pytest_cache" in tmp_list[i]: + del tmp_list[i] + elif "__pycache__" in tmp_list[i]: + del tmp_list[i] + return tmp_list + +def hack_driver_script(board, test_dir): + test_script_file = "driver.py" + # Read the contents of the test script file + with open(test_script_file, "r") as f: + lines = f.readlines() + + # Specify the line to be replaced and the new line + line_to_replace = "ishape_normal" + if "cnv" in test_dir: + new_line = " \"ishape_normal\" : [(1, 32, 32, 3)]," + else: + # Usually a size of (1, 784) to being with + if board == "Pynq-Z1": + new_line = " \"ishape_normal\" : [(1, 28, 28, 1)]," + else: + new_line = " \"ishape_normal\" : [(1, 1, 28, 28)]," + + # Iterate over the lines and replace the specified line + for i in range(len(lines)): + if line_to_replace in lines[i]: + lines[i] = new_line + "\n" + break # Only replace the first occurrence + + # Write the modified contents back to the test script file + with open(test_script_file, "w") as f: + f.writelines(lines) + +if __name__ == "__main__": + current_dir = os.getcwd() + board = os.path.basename(current_dir) + + # Get list of local directories - removing the Python cache directories + local_dirs = [name for name in os.listdir(current_dir) if os.path.isdir(os.path.join(current_dir, name))] + local_dirs = remove_cache_dirs(local_dirs) + + # Now create the full paths for each relative path + local_dirs_full_path = [os.path.join(current_dir, name) for name in local_dirs if os.path.isdir(os.path.join(current_dir, name))] + + # Change the driver.py script for each of the test directories + for dir in local_dirs_full_path: + os.chdir(dir) + hack_driver_script(board, dir) diff --git a/docker/jenkins/test_bnn_hw_pytest.py b/docker/jenkins/test_bnn_hw_pytest.py new file mode 100755 index 0000000000..09e62fd1d9 --- /dev/null +++ b/docker/jenkins/test_bnn_hw_pytest.py @@ -0,0 +1,177 @@ +import os +import numpy as np +from scipy.stats import linregress +import subprocess +import pytest +import itertools +import logging + +# no __init__ constructors allowed in Pytest - so use global variables instead +base_dir_global = os.getcwd() +default_test_run_timeout = 30 # seconds +output_execute_results_file = "output.npy" +execute_results_reference_file = "output_reference.npy" +output_throughput_results_file = "nw_metrics.txt" +throughput_results_formatted_file = "throughput_metrics_formatted.txt" +logger = logging.getLogger(__name__) + + +def remove_cache_dirs(dir_list): + tmp_list = list(dir_list) + for i in range(len(tmp_list)-1, -1, -1): + if ".pytest_cache" in tmp_list[i]: + del tmp_list[i] + elif "__pycache__" in tmp_list[i]: + del tmp_list[i] + return tmp_list + +def remove_destructive_board_tests(board, test_list): + tmp_list = list(test_list) + if "Pynq" in board: + # both tests are destructive to the Pynq-Z1 board and require a board reboot + for i in range(len(tmp_list)-1, -1, -1): + if "bnn_w2_a2_cnv_QE-True" in tmp_list[i]: + del tmp_list[i] + elif "bnn_w1_a1_tfc_QE-True" in tmp_list[i]: + del tmp_list[i] + return tmp_list + +def delete_file(file_path): + # Check if the file exists before deleting it + if os.path.exists(file_path): + try: + os.remove(file_path) + logger.info(f"File '{file_path}' deleted successfully.") + except Exception as e: + logger.error(f"An error occurred while deleting the file: {e}") + else: + logger.info(f"File '{file_path}' does not exist. Continuing with the script.") + +def get_platform(board_str): + return "alveo" if "U250" in board_str else "zynq-iodma" + +def get_full_parameterized_test_list(marker, test_dir_list, batch_size_list, platform_list): + test_cases = [ + (f'{marker}_{param1}_batchSize-{param2}_platform-{param3}', { + 'test_dir': param1, + 'batch_size': param2, + 'platform': param3, + }) + for param1, param2, param3 in itertools.product( + test_dir_list, + batch_size_list, + platform_list, + ) + ] + return test_cases + +def pytest_generate_tests(metafunc): + idlist = [] + argvalues = [] + scenarios = [] + + # Separate the full list of markers used on command line. + # This allows a user to select multiple markers + all_markers_used = metafunc.config.getoption("-m").split(" ") + current_dir = os.getcwd() + test_dirs = [name for name in os.listdir(current_dir) if os.path.isdir(os.path.join(current_dir, name))] + test_dirs = remove_cache_dirs(test_dirs) + + for marker in all_markers_used: + platform = get_platform(marker) + if "Pynq" in marker: + remove_destructive_board_tests("Pynq", test_dirs) + scenarios.extend(get_full_parameterized_test_list(marker, test_dir_list=test_dirs, batch_size_list=[1], platform_list=[platform])) + elif "U250" in marker or "ZCU104" in marker or "KV260_SOM" in marker: + scenarios.extend(get_full_parameterized_test_list(marker, test_dir_list=test_dirs, batch_size_list=[1], platform_list=[platform])) + + if len(scenarios) > 0: + for scenario in scenarios: + idlist.append(scenario[0]) + items = scenario[1].items() + argnames = [x[0] for x in items] + argvalues.append([x[1] for x in items]) + metafunc.parametrize(argnames, argvalues, ids=idlist, scope="class") + + +@pytest.mark.Pynq +@pytest.mark.U250 +@pytest.mark.ZCU104 +@pytest.mark.KV260_SOM +class TestBnn: + def test_type_execute(self, test_dir, batch_size, platform): + # Enter into test directory and clean any files from a potential previous run + os.chdir(os.path.join(base_dir_global, test_dir)) + delete_file(output_execute_results_file) + + # Run test option: execute + result = subprocess.run(["python", "driver.py", "--exec_mode=execute", f"--batchsize={batch_size}", "--bitfile=resizer.bit", "--inputfile=input.npy", "--outputfile=output.npy", f"--platform={platform}"], capture_output=True, text=True, timeout=default_test_run_timeout) + assert result.returncode == 0 + + # Load the output and reference arrays + output_array = np.load(output_execute_results_file) + reference_array = np.load(execute_results_reference_file) + + # Compare the arrays + try: + assert np.isclose(output_array, reference_array).all() + except AssertionError as e: + logger.error("AssertionError occurred: %s", e, exc_info=True) + raise + + def test_type_throughput(self, test_dir, batch_size, platform): + os.chdir(os.path.join(base_dir_global, test_dir)) + delete_file(output_throughput_results_file) + + result = subprocess.run(["python", "driver.py", "--exec_mode=throughput_test", f"--batchsize={batch_size}", "--bitfile=resizer.bit", "--inputfile=input.npy", "--outputfile=output.npy", f"--platform={platform}"], capture_output=True, text=True, timeout=default_test_run_timeout) + assert result.returncode == 0 + + # Check if nw_metrics.txt now exists after test run + assert os.path.exists(output_throughput_results_file) + + with open(output_throughput_results_file, "r") as file: + res = eval(file.read()) + + # try a range of batch sizes, some may fail due to insufficient DMA + # buffers + bsize_range_in = [8**i for i in range(5)] + bsize_range = [] + ret = dict() + for bsize in bsize_range_in: + if res is not None: + ret[bsize] = res + bsize_range.append(bsize) + else: + # assume we reached largest possible N + break + + y = [ret[key]["runtime[ms]"] for key in bsize_range] + lrret = linregress(bsize_range, y) + ret_str = "" + ret_str += "\n" + "%s Throughput Test Results" % test_dir + ret_str += "\n" + "-----------------------------" + ret_str += "\n" + "From linear regression:" + ret_str += "\n" + "Invocation overhead: %f ms" % lrret.intercept + ret_str += "\n" + "Time per sample: %f ms" % lrret.slope + ret_str += "\n" + "Raw data:" + + ret_str += "\n" + "{:<8} {:<16} {:<16} {:<16} {:<16} {:<16}".format( + "N", "runtime[ms]", "fclk[mhz]", "fps", "DRAM rd[MB/s]", "DRAM wr[MB/s]" + ) + for k in bsize_range: + v = ret[k] + ret_str += "\n" + "{:<8} {:<16} {:<16} {:<16} {:<16} {:<16}".format( + k, + np.round(v["runtime[ms]"], 4), + v["fclk[mhz]"], + np.round(v["throughput[images/s]"], 2), + np.round(v["DRAM_in_bandwidth[MB/s]"], 2), + np.round(v["DRAM_out_bandwidth[MB/s]"], 2), + ) + ret_str += "\n" + "-----------------------------" + largest_bsize = bsize_range[-1] + + # Dump the metrics to a text file + with open(throughput_results_formatted_file, "w") as f: + f.write(ret_str) + assert os.path.exists(throughput_results_formatted_file) \ No newline at end of file From b3166e4548253afa9b780d6643998e983a213b10 Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Tue, 27 Jun 2023 09:37:17 +0100 Subject: [PATCH 176/665] Add U250 xclbin for end2end bnn testing Signed-off-by: Fionn O'Donohoe --- docker/jenkins/test_bnn_hw_pytest.py | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/docker/jenkins/test_bnn_hw_pytest.py b/docker/jenkins/test_bnn_hw_pytest.py index 09e62fd1d9..f2b437e800 100755 --- a/docker/jenkins/test_bnn_hw_pytest.py +++ b/docker/jenkins/test_bnn_hw_pytest.py @@ -105,7 +105,8 @@ def test_type_execute(self, test_dir, batch_size, platform): delete_file(output_execute_results_file) # Run test option: execute - result = subprocess.run(["python", "driver.py", "--exec_mode=execute", f"--batchsize={batch_size}", "--bitfile=resizer.bit", "--inputfile=input.npy", "--outputfile=output.npy", f"--platform={platform}"], capture_output=True, text=True, timeout=default_test_run_timeout) + bitfile = "a.xclbin" if platform == "alveo" else "resizer.bit" + result = subprocess.run(["python", "driver.py", "--exec_mode=execute", f"--batchsize={batch_size}", f"--bitfile={bitfile}", "--inputfile=input.npy", "--outputfile=output.npy", f"--platform={platform}"], capture_output=True, text=True, timeout=default_test_run_timeout) assert result.returncode == 0 # Load the output and reference arrays @@ -123,7 +124,9 @@ def test_type_throughput(self, test_dir, batch_size, platform): os.chdir(os.path.join(base_dir_global, test_dir)) delete_file(output_throughput_results_file) - result = subprocess.run(["python", "driver.py", "--exec_mode=throughput_test", f"--batchsize={batch_size}", "--bitfile=resizer.bit", "--inputfile=input.npy", "--outputfile=output.npy", f"--platform={platform}"], capture_output=True, text=True, timeout=default_test_run_timeout) + # Run test option: throughput + bitfile = "a.xclbin" if platform == "alveo" else "resizer.bit" + result = subprocess.run(["python", "driver.py", "--exec_mode=throughput_test", f"--batchsize={batch_size}", f"--bitfile={bitfile}", "--inputfile=input.npy", "--outputfile=output.npy", f"--platform={platform}"], capture_output=True, text=True, timeout=default_test_run_timeout) assert result.returncode == 0 # Check if nw_metrics.txt now exists after test run From 74918647cfe44e66e917c8de4874008d2bedda42 Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 27 Jun 2023 10:51:09 +0100 Subject: [PATCH 177/665] [notebooks/docs] Update second half of folding nb and update internals doc --- docs/finn/internals.rst | 38 + notebooks/advanced/3_folding.ipynb | 2133 ++++++---------------------- 2 files changed, 482 insertions(+), 1689 deletions(-) diff --git a/docs/finn/internals.rst b/docs/finn/internals.rst index d0c4cd2065..9c1ff626b2 100644 --- a/docs/finn/internals.rst +++ b/docs/finn/internals.rst @@ -206,6 +206,44 @@ How to set *mem_mode* --------------------- When the nodes in the network are converted to HLS layers, the *mem_mode* can be passed. More detailed information about the transformations that prepare the network and the transformation that performs the conversion to HLS layers can be found in chapter :ref:`nw_prep`. The *mem_mode* is passed as argument. Note that if no argument is passed, the default is *const*. + +.. _folding_factors: + +Constraints to folding factors per layer +========================================= ++------------------------------------+------------+----------------------------------------------------------------+ +| Layers | Attributes | Assertions | ++====================================+============+================================================================+ +| addstreams_batch | PE | inp_channels % PE == 0 | +| channelwise_op_batch | PE | channels % PE == 0 | +| checksum | - | - | +| concat | - | - | +| convolutioninputgenerator | SIMD | inp_channels % SIMD == 0 | +| convolutioninputgenerator1d | SIMD | inp_channels % SIMD == 0 | +| convolutioninputgenerator_rtl | SIMD | inp_channels % SIMD == 0 | +| downsampler | SIMD | inp_channels % SIMD == 0 | +| duplicatestreams_batch | PE | channels % PE == 0 | +| eltwise | PE | inp_channels % PE == 0 | +| fmpadding_batch | SIMD | inp_channels % SIMD == 0 | +| fmpadding_rtl | SIMD | inp_channels % SIMD == 0 | +| globalaccpool_batch | PE | channels % PE == 0 | +| iodma | - | - | +| labelselect_batch | PE | num_labels % PE == 0 | +| lookup | - | - | +| matrixvectoractivation | PE & SIMD | matrix_height % PE == 0 & matrix_width % SIMD == 0 | +| pool_batch | PE | inp_channels % PE == 0 | +| streamingdataflowpartition | - | - | +| streamingdatawidthconverter_batch | - | - | +| streamingfifo | - | - | +| streamingmaxpool_batch | - | - | +| templates | - | - | +| thresholding_batch | PE | matrix_height % PE == 0 | +| tlastmarker | - | - | +| upsampler | - | - | +| vectorvectoractivation | PE & SIMD | kernel_height * kernel_width % SIMD == 0 & channels % PE == 0 | ++------------------------------------+------------+----------------------------------------------------------------+ + + RTL ConvolutionInputGenerator ============================= diff --git a/notebooks/advanced/3_folding.ipynb b/notebooks/advanced/3_folding.ipynb index b1baf69cab..a411d3bc88 100644 --- a/notebooks/advanced/3_folding.ipynb +++ b/notebooks/advanced/3_folding.ipynb @@ -8,7 +8,9 @@ "--------------------------------------\n", "**Note: To run this notebook, you first need to run the build flow in the 3rd cybersecurity notebook as we utilize one of the intermediate models generated in that process in this notebook.** \n", "\n", - "This notebook describes the use of FINN parallelization parameters (PE & SIMD) to efficiently streamline models so as to extract the maximum performance out of them.\n", + "This notebook describes the use of FINN parallelization parameters (PE & SIMD) to efficiently streamline models so as to extract the maximum performance out of them. \n", + "\n", + "Please be aware that the folding factors can not be selected arbitrarily, each layer has constraints on which values the parallelization parameters can be set to, for more information see here: https://finn-dev.readthedocs.io/en/latest/internals.html#folding-factors\n", "\n", "We'll use the utility function `showInNetron()` to visualize and interact with our network in the Jupyter Notebook and `showSrc()` to show source code of FINN library calls." ] @@ -84,7 +86,7 @@ "name": "stdout", "output_type": "stream", "text": [ - "Serving 'step_convert_to_hls.onnx' at http://0.0.0.0:5920\n" + "Serving 'cybsec_PE_SIMD.onnx' at http://0.0.0.0:5920\n" ] }, { @@ -102,7 +104,7 @@ " " ], "text/plain": [ - "" + "" ] }, "execution_count": 2, @@ -113,9 +115,9 @@ "source": [ "from qonnx.core.modelwrapper import ModelWrapper\n", "model = ModelWrapper(\"../end2end_example/cybersecurity/output_estimates_only/intermediate_models/step_convert_to_hls.onnx\")\n", - "model.save(\"step_convert_to_hls.onnx\")\n", + "model.save(\"cybsec_PE_SIMD.onnx\")\n", "\n", - "showInNetron(\"step_convert_to_hls.onnx\")" + "showInNetron(\"cybsec_PE_SIMD.onnx\")" ] }, { @@ -168,7 +170,7 @@ "output_type": "stream", "text": [ "Stopping http://0.0.0.0:5920\n", - "Serving 'step_convert_to_hls.onnx' at http://0.0.0.0:5920\n" + "Serving 'cybsec_PE_SIMD.onnx' at http://0.0.0.0:5920\n" ] }, { @@ -186,7 +188,7 @@ " " ], "text/plain": [ - "" + "" ] }, "execution_count": 3, @@ -195,7 +197,7 @@ } ], "source": [ - "showInNetron(\"step_convert_to_hls.onnx\")" + "showInNetron(\"cybsec_PE_SIMD.onnx\")" ] }, { @@ -250,7 +252,7 @@ }, { "cell_type": "code", - "execution_count": 7, + "execution_count": 6, "metadata": {}, "outputs": [ { @@ -289,7 +291,7 @@ }, { "cell_type": "code", - "execution_count": 8, + "execution_count": 7, "metadata": {}, "outputs": [ { @@ -321,7 +323,7 @@ " 'DSP': 0}}" ] }, - "execution_count": 8, + "execution_count": 7, "metadata": {}, "output_type": "execute_result" } @@ -347,7 +349,7 @@ }, { "cell_type": "code", - "execution_count": 13, + "execution_count": 8, "metadata": {}, "outputs": [ { @@ -385,73 +387,75 @@ "cell_type": "markdown", "metadata": {}, "source": [ - "# QuickNote : StreamingDataWidthConverter Layer" + "## Modify Parameters\n", + "\n", + "We now modify the parallelization parameters of the first network layer to reduce its overall latency.\n", + "We individually extract the `MatrixVectorActivation` blocks from the `.onnx` file and set the config values manually (although this can be done automatically by the FINN compiler as mentioned in the introduction).\n", + "\n", + "In the first step, we left the `PE` & `SIMD` values for all the layers on default (=1) to establish a baseline and measure the estimated clock cycles and resource utilization for each of the individual layers.\n", + "\n", + "To set `PE` & `SIMD`, we will utilize functionality from the FINN compiler. Each layer type has a Python wrapper which can be instantiated using the `getCustomOp()` function. The wrapper offers several helper functions like `get_nodeattr()` and `set_nodeattr()` to access and set the attributes of a node." ] }, { "cell_type": "code", - "execution_count": 37, + "execution_count": 9, "metadata": {}, "outputs": [ { "name": "stdout", "output_type": "stream", "text": [ - "Instream Width = 1 Outstream Width = 2\n", - "Instream Width = 2 Outstream Width = 2\n", - "Instream Width = 2 Outstream Width = 2\n", - "Instream Width = 2 Outstream Width = 1\n" + "The parallelization parameters of MatrixVectorActivation_0 were: \n", + "PE: 1\n", + "SIMD: 1\n", + "The parallelization parameters of MatrixVectorActivation_0 are updated to: \n", + "PE: 2\n", + "SIMD: 5\n" ] } ], "source": [ - "fc_layers = model.get_nodes_by_op_type(\"MatrixVectorActivation\")\n", - "for fcl in fc_layers:\n", - " fcl_inst = getCustomOp(fcl)\n", - " print('Instream Width =',(fcl_inst.get_instream_width()),'Outstream Width =',int(fcl_inst.get_outstream_width()))" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "We can also view the `instream_width` and `outstream_width` of each layer using the `get_instream_width()` and `get_outstream_width()` helper functions. These widths are of particular importance as for a (balanced pipeline?) these width's should be the same.\n", + "from qonnx.custom_op.registry import getCustomOp\n", + "\n", + "list_of_mvaus = model.get_nodes_by_op_type(\"MatrixVectorActivation\")\n", + "mvau0 = list_of_mvaus[0]\n", + "\n", + "mvau0_inst = getCustomOp(mvau0)\n", "\n", - "For example, the outwidth of a given layer of the network should match the inwidth of the next layer for the (pipeline to be stable?). If they are not the same then the FINN compiler adds an extra `streamingdatawidthconverter` (which increases the overall resource utilization of the design slightly) layer to make sure these widths match.\n", + "# Get the node attributes to check the current setting\n", + "print(\"The parallelization parameters of %s were: \" % mvau0.name)\n", + "print(\"PE: \" + str(mvau0_inst.get_nodeattr(\"PE\")))\n", + "print(\"SIMD: \" + str(mvau0_inst.get_nodeattr(\"SIMD\")))\n", "\n", - "Note, that if these widths are the same then even if we call the `InsertDWC()` transformation on our model (responsible for adding the above layer), the datawidth conversion layers will not be a part of our model as shown in the below cells. " + "# Set the new node attributes\n", + "mvau0_inst.set_nodeattr(\"PE\", 2)\n", + "mvau0_inst.set_nodeattr(\"SIMD\", 5)\n", + "\n", + "# Get the node attributes to check the updated setting\n", + "print(\"The parallelization parameters of %s are updated to: \" % mvau0.name)\n", + "print(\"PE: \" + str(mvau0_inst.get_nodeattr(\"PE\")))\n", + "print(\"SIMD: \" + str(mvau0_inst.get_nodeattr(\"SIMD\")))" ] }, { "cell_type": "markdown", "metadata": {}, "source": [ - "
    \n", - "Question in the first and the second line of the above cell.\n", - "
    " + "We save the model and view it. On expanding the first `MatrixVectorActivation` we can view the updated `PE` & `SIMD` parameters for that layer." ] }, { "cell_type": "code", - "execution_count": 11, - "metadata": {}, - "outputs": [], - "source": [ - "from finn.transformation.fpgadataflow.insert_dwc import InsertDWC\n", - "model = model.transform(InsertDWC())" - ] - }, - { - "cell_type": "code", - "execution_count": 12, + "execution_count": 10, "metadata": {}, "outputs": [ { "name": "stdout", "output_type": "stream", "text": [ - "Stopping http://0.0.0.0:5901\n", - "Serving './cybsec_DWC_not_inserted.onnx' at http://0.0.0.0:5901\n" + "Stopping http://0.0.0.0:5920\n", + "Serving 'cybsec_PE_SIMD_modified.onnx' at http://0.0.0.0:5920\n" ] }, { @@ -461,7 +465,7 @@ " " + "" + ] + }, + "execution_count": 10, + "metadata": {}, + "output_type": "execute_result" + } + ], + "source": [ + "model.save(\"cybsec_PE_SIMD_modified.onnx\")\n", + "showInNetron(\"cybsec_PE_SIMD_modified.onnx\")" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "From the above total folding formula, we have reduced the total folding of our layer from `600 x 64` to `120 x 32`. Hence, resulting in an estimated `10x` decrease in the execution latency of our layer. \n", + "This can be observed in the new estimated clock cycles." + ] + }, + { + "cell_type": "code", + "execution_count": 12, + "metadata": {}, + "outputs": [ + { + "data": { + "text/plain": [ + "{'MatrixVectorActivation_0': 3840,\n", + " 'MatrixVectorActivation_1': 4096,\n", + " 'MatrixVectorActivation_2': 4096,\n", + " 'MatrixVectorActivation_3': 64}" ] }, "execution_count": 12, @@ -478,8 +514,8 @@ } ], "source": [ - "model.save(\"./cybsec_DWC_not_inserted.onnx\")\n", - "showInNetron(\"./cybsec_DWC_not_inserted.onnx\",localhost_url='xirxlabs53')#localhost_url='xirxlabs60'" + "cycles_dict_updated = model.analysis(exp_cycles_per_layer)\n", + "cycles_dict_updated" ] }, { @@ -488,1665 +524,397 @@ "metadata": {}, "outputs": [ { - "name": "stdout", - "output_type": "stream", - "text": [ - "class MatrixVectorActivation(HLSCustomOp):\n", - " \"\"\"Class that corresponds to finn-hls Matrix_Vector_Activate(_Stream)_Batch\n", - " function.\"\"\"\n", - "\n", - " def __init__(self, onnx_node):\n", - " super().__init__(onnx_node)\n", - " self.decoupled_wrapper = templates.decoupled_wrapper\n", - "\n", - " def get_nodeattr_types(self):\n", - " my_attrs = {\n", - " \"PE\": (\"i\", True, 0),\n", - " \"SIMD\": (\"i\", True, 0),\n", - " \"MW\": (\"i\", True, 0),\n", - " \"MH\": (\"i\", True, 0),\n", - " \"resType\": (\"s\", False, \"lut\", {\"auto\", \"lut\", \"dsp\"}),\n", - " \"ActVal\": (\"i\", False, 0),\n", - " # FINN DataTypes for inputs, weights, outputs\n", - " \"inputDataType\": (\"s\", True, \"\"),\n", - " \"weightDataType\": (\"s\", True, \"\"),\n", - " \"outputDataType\": (\"s\", True, \"\"),\n", - " # FINN DataType for accumulator -- auto-computed and updated\n", - " \"accDataType\": (\"s\", False, \"INT32\"),\n", - " # use xnor-popcount for binary weights/inputs, thus treating them\n", - " # as bipolar\n", - " \"binaryXnorMode\": (\"i\", False, 0, {0, 1}),\n", - " # no-activation mode (produce accumulators)\n", - " \"noActivation\": (\"i\", False, 0, {0, 1}),\n", - " # number of input vectors, examples:\n", - " # [1] is a single vector (like a FC layer with batch=1)\n", - " # [4] is four vectors (like a FC layer with batch=4)\n", - " # [1, 4, 4] is four * four vectors (like a conv layer with batch=1)\n", - " \"numInputVectors\": (\"ints\", False, [1]),\n", - " # memory mode for the FC weights\n", - " # const -- embedded weights, default, long compile/synth times\n", - " # decoupled -- streaming weights with weight streamer packaged inside IP\n", - " # external -- streaming weights with external streamer\n", - " \"mem_mode\": (\"s\", False, \"const\", {\"const\", \"decoupled\", \"external\"}),\n", - " # FPGA resource type for memories in decoupled mode\n", - " # auto -- let Vivado decide\n", - " # block -- use BRAM\n", - " # distributed -- use LUTRAM\n", - " # ultra -- use UltraRAM (URAM), must have runtime_writeable_weights=1\n", - " # see also https://www.xilinx.com/support/answers/38070.html\n", - " \"ram_style\": (\n", - " \"s\",\n", - " False,\n", - " \"auto\",\n", - " {\"auto\", \"block\", \"distributed\", \"ultra\"},\n", - " ),\n", - " # FPGA resource type for threshold memories (if noActivation is False)\n", - " # auto -- let Vivado decide\n", - " # block -- use BRAM\n", - " # distributed -- use LUTRAM\n", - " \"ram_style_thresholds\": (\n", - " \"s\",\n", - " False,\n", - " \"auto\",\n", - " {\"auto\", \"block\", \"distributed\"},\n", - " ),\n", - " # (mem_mode = decoupled only) whether weights will be writable through\n", - " # an AXI-lite interface during runtime\n", - " # 1 for enabled, 0 for disabled.\n", - " # see finn-rtllib/memstream/doc/README for more about the memory\n", - " # address map used for writable weights\n", - " # IMPORTANT: After using AXI lite to either read or write the weights,\n", - " # always \"flush\" the accelerator by first passing a dummy input\n", - " # vector through the accelerator. This will get rid of any old\n", - " # weight data from the weight FIFOs.\n", - " \"runtime_writeable_weights\": (\"i\", False, 0, {0, 1}),\n", - " }\n", - " my_attrs.update(super().get_nodeattr_types())\n", - " return my_attrs\n", - "\n", - " def calc_wmem(self):\n", - " \"\"\"Calculates and returns WMEM.\"\"\"\n", - " mw = self.get_nodeattr(\"MW\")\n", - " mh = self.get_nodeattr(\"MH\")\n", - " pe = self.get_nodeattr(\"PE\")\n", - " simd = self.get_nodeattr(\"SIMD\")\n", - " assert mh % pe == 0, \"Requirement MH divisable by PE is violated.\"\n", - " assert mw % simd == 0, \"Requirement MW divisable by SIMD is violated.\"\n", - " wmem = mw * mh // (pe * simd)\n", - " return wmem\n", - "\n", - " def calc_tmem(self):\n", - " \"\"\"Calculates and returns TMEM.\"\"\"\n", - " if self.get_nodeattr(\"noActivation\") == 1:\n", - " return 0\n", - " else:\n", - " mh = self.get_nodeattr(\"MH\")\n", - " pe = self.get_nodeattr(\"PE\")\n", - " return mh // pe\n", - "\n", - " def make_shape_compatible_op(self, model):\n", - " oshape = self.get_normal_output_shape()\n", - " return super().make_const_shape_op(oshape)\n", - "\n", - " def infer_node_datatype(self, model):\n", - " node = self.onnx_node\n", - " idt = model.get_tensor_datatype(node.input[0])\n", - " if idt != self.get_input_datatype():\n", - " warn_str = \"inputDataType changing for %s: %s -> %s \" % (\n", - " node.name,\n", - " str(self.get_input_datatype()),\n", - " str(idt),\n", - " )\n", - " warnings.warn(warn_str)\n", - " self.set_nodeattr(\"inputDataType\", idt.name)\n", - " # set output datatype from property\n", - " odt = self.get_output_datatype()\n", - " model.set_tensor_datatype(node.output[0], odt)\n", - "\n", - " def verify_node(self):\n", - " info_messages = []\n", - " # verify that \"backend\" is set to \"fpgadataflow\"\n", - " backend_value = self.get_nodeattr(\"backend\")\n", - " if backend_value == \"fpgadataflow\":\n", - " info_messages.append(\"Attribute backend is set correctly\")\n", - " else:\n", - " info_messages.append('Attribute backend should be set to \"fpgadataflow\"')\n", - "\n", - " # verify that all necessary attributes exist\n", - " # TODO collect automatically from get_nodeattr_types\n", - " try:\n", - " self.get_nodeattr(\"code_gen_dir_cppsim\")\n", - " self.get_nodeattr(\"executable_path\")\n", - " self.get_nodeattr(\"resType\")\n", - " self.get_nodeattr(\"MW\")\n", - " self.get_nodeattr(\"MH\")\n", - " self.get_nodeattr(\"SIMD\")\n", - " self.get_nodeattr(\"PE\")\n", - " self.get_nodeattr(\"inputDataType\")\n", - " self.get_nodeattr(\"weightDataType\")\n", - " self.get_nodeattr(\"outputDataType\")\n", - " info_messages.append(\"All necessary attributes exist\")\n", - " except Exception:\n", - " info_messages.append(\n", - " \"\"\"The required MatrixVectorActivation attributes do not exist.\"\"\"\n", - " )\n", - "\n", - " # verify the number of inputs depending on noActivation value\n", - " # check noActivation value to determine the number of inputs\n", - " no_act = self.get_nodeattr(\"noActivation\")\n", - "\n", - " if no_act == 1:\n", - " if len(self.onnx_node.input) == 2:\n", - " info_messages.append(\"The number of inputs is correct\")\n", - " else:\n", - " info_messages.append(\n", - " \"\"\"MatrixVectorActivation needs in no\n", - " activation mode 2 inputs (data input and weights)\"\"\"\n", - " )\n", - " elif no_act == 0:\n", - " if len(self.onnx_node.input) == 3:\n", - " info_messages.append(\"The number of inputs is correct\")\n", - " else:\n", - " info_messages.append(\n", - " \"\"\"MatrixVectorActivation needs 3 inputs\n", - " (data input and weights and threshold values)\"\"\"\n", - " )\n", - " else:\n", - " info_messages.append(\n", - " \"\"\"noActivation attribute contains {} should\n", - " be 0 or 1\"\"\".format(\n", - " no_act\n", - " )\n", - " )\n", - "\n", - " return info_messages\n", - "\n", - " def uram_estimation(self):\n", - " P = self.get_nodeattr(\"PE\")\n", - " Q = self.get_nodeattr(\"SIMD\")\n", - " wdt = self.get_weight_datatype()\n", - " W = wdt.bitwidth()\n", - " D_in = self.get_nodeattr(\"MW\")\n", - " D_out = self.get_nodeattr(\"MH\")\n", - " omega = (D_in * D_out) / (Q * P)\n", - " mem_width = Q * W * P\n", - " mmode = self.get_nodeattr(\"mem_mode\")\n", - " mstyle = self.get_nodeattr(\"ram_style\")\n", - " if (\n", - " (mmode == \"decoupled\" and mstyle != \"ultra\")\n", - " or (mmode == \"const\" and self.calc_wmem() <= 128)\n", - " or (mmode == \"external\")\n", - " ):\n", - " return 0\n", - " width_multiplier = math.ceil(mem_width / 72)\n", - " depth_multiplier = math.ceil(omega / 4096)\n", - " return width_multiplier * depth_multiplier\n", - "\n", - " def bram_estimation(self):\n", - " \"\"\"Calculates resource estimation for BRAM based on:\n", - " - FINN-R: An End-to-End Deep-Learning Framework for Fast\n", - " Exploration of Quantized Neural Networks\n", - " - M. Blott, T. B. Preusser, N. J. Fraser, G. Gambardella, K. O'Brien,\n", - " Y. Umuroglu, M. Leeser and K. Vissers\n", - " - 12. Sep 2018\n", - " \"\"\"\n", - " # TODO add in/out FIFO contributions\n", - " P = self.get_nodeattr(\"PE\")\n", - " Q = self.get_nodeattr(\"SIMD\")\n", - " wdt = self.get_weight_datatype()\n", - " W = wdt.bitwidth()\n", - " D_in = self.get_nodeattr(\"MW\")\n", - " D_out = self.get_nodeattr(\"MH\")\n", - " omega = (D_in * D_out) / (Q * P)\n", - " mem_width = Q * W * P\n", - " mmode = self.get_nodeattr(\"mem_mode\")\n", - " mstyle = self.get_nodeattr(\"ram_style\")\n", - " if (\n", - " (mmode == \"decoupled\" and mstyle in [\"distributed\", \"ultra\"])\n", - " or (mmode == \"const\" and self.calc_wmem() <= 128)\n", - " or (mmode == \"external\")\n", - " ):\n", - " return 0\n", - " # assuming SDP mode RAMB18s (see UG573 Table 1-10)\n", - " # assuming decoupled (RTL) memory, which is more efficient than const (HLS)\n", - " if mem_width == 1:\n", - " return math.ceil(omega / 16384)\n", - " elif mem_width == 2:\n", - " return math.ceil(omega / 8192)\n", - " elif mem_width <= 4:\n", - " return (math.ceil(omega / 4096)) * (math.ceil(mem_width / 4))\n", - " elif mem_width <= 9:\n", - " return (math.ceil(omega / 2048)) * (math.ceil(mem_width / 9))\n", - " elif mem_width <= 18 or omega > 512:\n", - " return (math.ceil(omega / 1024)) * (math.ceil(mem_width / 18))\n", - " else:\n", - " return (math.ceil(omega / 512)) * (math.ceil(mem_width / 36))\n", - "\n", - " def bram_efficiency_estimation(self):\n", - " wdt = self.get_weight_datatype()\n", - " W = wdt.bitwidth()\n", - " D_in = self.get_nodeattr(\"MW\")\n", - " D_out = self.get_nodeattr(\"MH\")\n", - " bram16_est = self.bram_estimation()\n", - " if bram16_est == 0:\n", - " return 1\n", - " wbits = W * D_in * D_out\n", - " bram16_est_capacity = bram16_est * 36 * 512\n", - " return wbits / bram16_est_capacity\n", - "\n", - " def uram_efficiency_estimation(self):\n", - " \"\"\"Function for URAM efficiency estimation: actual parameter storage\n", - " needed divided by the allocated URAM storage (from estimation)\"\"\"\n", - " wdt = self.get_weight_datatype()\n", - " W = wdt.bitwidth()\n", - " D_in = self.get_nodeattr(\"MW\")\n", - " D_out = self.get_nodeattr(\"MH\")\n", - " uram_est = self.uram_estimation()\n", - " if uram_est == 0:\n", - " return 1\n", - " wbits = W * D_in * D_out\n", - " uram_est_capacity = uram_est * 72 * 4096\n", - " return wbits / uram_est_capacity\n", - "\n", - " def lut_estimation(self):\n", - " \"\"\"Calculates resource estimations for LUTs based on:\n", - " - FINN-R: An End-to-End Deep-Learning Framework for Fast\n", - " Exploration of Quantized Neural Networks\n", - " - M. Blott, T. B. Preusser, N. J. Fraser, G. Gambardella, K. O'Brien,\n", - " Y. Umuroglu, M. Leeser and K. Vissers\n", - " - 12. Sep 2018\n", - " \"\"\"\n", - " # TODO add in/out FIFO contributions\n", - " P = self.get_nodeattr(\"PE\")\n", - " Q = self.get_nodeattr(\"SIMD\")\n", - " MW = self.get_nodeattr(\"MW\")\n", - " wdt = self.get_weight_datatype()\n", - " W = wdt.bitwidth()\n", - " # determine tdt with input and weight data types\n", - " idt = self.get_input_datatype()\n", - " A = idt.bitwidth()\n", - " # parameters from experiments in paper mentioned above\n", - " c0 = 300\n", - " c1 = 1.1\n", - " c2 = 0\n", - " mmode = self.get_nodeattr(\"mem_mode\")\n", - " mstyle = self.get_nodeattr(\"ram_style\")\n", - " if (mmode == \"decoupled\" and mstyle == \"distributed\") or (\n", - " mmode == \"const\" and self.calc_wmem() <= 128\n", - " ):\n", - " c2 = (P * Q * W) * math.ceil(self.calc_wmem() / 64)\n", - "\n", - " # multiplication\n", - " res_type = self.get_nodeattr(\"resType\")\n", - " if res_type == \"dsp\":\n", - " mult_luts = 0\n", - " else:\n", - " mult_luts = Q * (2 * math.ceil((W + A) / 6) - 1) * (W + A)\n", - " # adder tree\n", - " addertree_luts = (W + A) * (2 * Q - 1)\n", - " # accumulator\n", - " acc_bits = W + A + np.ceil(math.log(MW, 2))\n", - " acc_luts = acc_bits\n", - " # thresholds and threshold comparators\n", - " thr_luts = 0\n", - " comp_luts = 0\n", - " noact = self.get_nodeattr(\"noActivation\")\n", - " if noact == 0:\n", - " odt = self.get_output_datatype()\n", - " B = odt.bitwidth()\n", - " thr_luts = (2**B - 1) * acc_bits * math.ceil(self.calc_tmem() / 64)\n", - " comp_luts = (2**B - 1) * acc_bits\n", - "\n", - " return int(\n", - " c0\n", - " + c1 * (P * (mult_luts + addertree_luts + acc_luts + thr_luts + comp_luts))\n", - " + c2\n", - " )\n", - "\n", - " def dsp_estimation(self):\n", - " # multiplication\n", - " P = self.get_nodeattr(\"PE\")\n", - " res_type = self.get_nodeattr(\"resType\")\n", - " Q = self.get_nodeattr(\"SIMD\")\n", - " wdt = self.get_weight_datatype()\n", - " W = wdt.bitwidth()\n", - " idt = self.get_input_datatype()\n", - " A = idt.bitwidth()\n", - " if res_type == \"dsp\":\n", - " mult_dsp = P * Q * np.ceil((W + A) / 48) # TODO: more accurate modelling\n", - " else:\n", - " mult_dsp = 0\n", - " return int(mult_dsp)\n", - "\n", - " def get_exp_cycles(self):\n", - " pe = self.get_nodeattr(\"PE\")\n", - " simd = self.get_nodeattr(\"SIMD\")\n", - " num_inp_vec = self.get_nodeattr(\"numInputVectors\")\n", - " mh = self.get_nodeattr(\"MH\")\n", - " mw = self.get_nodeattr(\"MW\")\n", - " # since mmv != 1 is not supported yet, we set mmv for now to 1\n", - " mmv = 1\n", - " exp_cycles = (mh / pe) * (mw / simd) * np.prod(num_inp_vec) / mmv\n", - " return int(exp_cycles)\n", - "\n", - " def get_input_datatype(self, ind=0):\n", - " \"\"\"Returns FINN DataType of input.\"\"\"\n", - " # when performing FIFO insertion on an FC layer with ext weights, the ind\n", - " # parameter can be > 0 (referring to the weights) so handle that here\n", - " if ind == 0:\n", - " return DataType[self.get_nodeattr(\"inputDataType\")]\n", - " elif ind == 1:\n", - " return DataType[self.get_nodeattr(\"weightDataType\")]\n", - " else:\n", - " raise Exception(\"Undefined input ind for this layer type\")\n", - "\n", - " def get_weight_datatype(self):\n", - " \"\"\"Returns FINN DataType of weights.\"\"\"\n", - " return DataType[self.get_nodeattr(\"weightDataType\")]\n", - "\n", - " def get_output_datatype(self, ind=0):\n", - " \"\"\"Returns FINN DataType of output.\"\"\"\n", - " return DataType[self.get_nodeattr(\"outputDataType\")]\n", - "\n", - " def get_instream_width(self, ind=0):\n", - " i_bits = self.get_input_datatype().bitwidth()\n", - " in_width = i_bits * self.get_nodeattr(\"SIMD\")\n", - " return in_width\n", - "\n", - " def get_outstream_width(self, ind=0):\n", - " o_bits = self.get_output_datatype().bitwidth()\n", - " out_width = o_bits * self.get_nodeattr(\"PE\")\n", - " return out_width\n", - "\n", - " def get_weightstream_width(self):\n", - " \"\"\"Returns weight stream width. Used only in decoupled mode.\"\"\"\n", - " if (\n", - " self.get_nodeattr(\"mem_mode\") == \"decoupled\"\n", - " or self.get_nodeattr(\"mem_mode\") == \"external\"\n", - " ):\n", - " pe = self.get_nodeattr(\"PE\")\n", - " simd = self.get_nodeattr(\"SIMD\")\n", - " wp = self.get_weight_datatype().bitwidth()\n", - " w_width = pe * simd * wp\n", - " return w_width\n", - " else:\n", - " return 0\n", - "\n", - " def get_weightstream_width_padded(self):\n", - " \"\"\"Returns weight stream width padded to a multiple of 8. This is required\n", - " by the AXI Stream spec. Used in decoupled mode.\"\"\"\n", - " weight_width = self.get_weightstream_width()\n", - " return roundup_to_integer_multiple(weight_width, 8)\n", - "\n", - " def get_ap_int_max_w(self):\n", - " # base class impl (max of inp/out stream widths)\n", - " max_of_io = super().get_ap_int_max_w()\n", - " # decoupled mode weight stream\n", - " weightstream = self.get_weightstream_width()\n", - " # single PE weight entry\n", - " weight_bits = self.get_weight_datatype().bitwidth()\n", - " simd = self.get_nodeattr(\"SIMD\")\n", - " single_pe_w = simd * weight_bits\n", - " return max([weightstream, max_of_io, single_pe_w])\n", - "\n", - " def get_folded_input_shape(self, ind=0):\n", - " mw = self.get_nodeattr(\"MW\")\n", - " mh = self.get_nodeattr(\"MH\")\n", - " simd = self.get_nodeattr(\"SIMD\")\n", - " pe = self.get_nodeattr(\"PE\")\n", - " sf = mw // simd\n", - " nf = mh // pe\n", - " vecs = list(self.get_nodeattr(\"numInputVectors\"))\n", - "\n", - " if ind == 0:\n", - " # calculate shape of input 0\n", - " folded_input_shape = tuple(vecs + [sf, simd])\n", - " elif ind == 1 and self.get_nodeattr(\"mem_mode\") == \"external\":\n", - " # calculate shape of input 1 (weights)\n", - " folded_input_shape = tuple(vecs + [sf * nf, simd * pe])\n", - " else:\n", - " raise Exception(\"Undefined input shape for requested input\")\n", - "\n", - " return folded_input_shape\n", - "\n", - " def get_folded_output_shape(self, ind=0):\n", - " mh = self.get_nodeattr(\"MH\")\n", - " pe = self.get_nodeattr(\"PE\")\n", - " nf = mh // pe\n", - " vecs = list(self.get_nodeattr(\"numInputVectors\"))\n", - " folded_output_shape = tuple(vecs + [nf, pe])\n", - " return folded_output_shape\n", - "\n", - " def get_normal_input_shape(self, ind=0):\n", - " mw = self.get_nodeattr(\"MW\")\n", - " vecs = list(self.get_nodeattr(\"numInputVectors\"))\n", - " normal_input_shape = tuple(vecs + [mw])\n", - " return normal_input_shape\n", - "\n", - " def get_normal_output_shape(self, ind=0):\n", - " mh = self.get_nodeattr(\"MH\")\n", - " vecs = list(self.get_nodeattr(\"numInputVectors\"))\n", - " normal_output_shape = tuple(vecs + [mh])\n", - " return normal_output_shape\n", - "\n", - " def get_number_output_values(self):\n", - " nf = np.prod(self.get_folded_output_shape()[:-1])\n", - " return nf\n", - "\n", - " def get_template_param_values(self):\n", - " \"\"\"Returns the template parameter values according to input, output and weight\n", - " data types.\"\"\"\n", - " ret = dict()\n", - " inp_hls_str = self.get_input_datatype().get_hls_datatype_str()\n", - " out_hls_str = self.get_output_datatype().get_hls_datatype_str()\n", - " inp_is_binary = self.get_input_datatype() == DataType[\"BINARY\"]\n", - " # out_is_binary = self.get_output_datatype() == DataType[\"BINARY\"]\n", - " wt_is_binary = self.get_weight_datatype() == DataType[\"BINARY\"]\n", - " bin_xnor_mode = self.get_nodeattr(\"binaryXnorMode\") == 1\n", - " if (inp_is_binary or wt_is_binary) and (not bin_xnor_mode):\n", - " raise Exception(\"True binary (non-bipolar) inputs not yet supported\")\n", - " inp_is_bipolar = self.get_input_datatype() == DataType[\"BIPOLAR\"]\n", - " # out_is_bipolar = self.get_output_datatype() == DataType[\"BIPOLAR\"]\n", - " wt_is_bipolar = self.get_weight_datatype() == DataType[\"BIPOLAR\"]\n", - " # reinterpret inp/wt as bipolar if bin_xnor_mode is iset\n", - " inp_is_bipolar = inp_is_bipolar or (inp_is_binary and bin_xnor_mode)\n", - " wt_is_bipolar = wt_is_bipolar or (wt_is_binary and bin_xnor_mode)\n", - " # fill in TSrcI and TWeightI\n", - " # TODO check these with Giulio\n", - " # TODO handle non-bipolar binary inputs\n", - " if inp_is_bipolar and wt_is_bipolar:\n", - " ret[\"TSrcI\"] = \"Recast\"\n", - " ret[\"TWeightI\"] = \"Identity\"\n", - " elif (not inp_is_bipolar) and wt_is_bipolar:\n", - " ret[\"TSrcI\"] = \"Slice<%s>\" % inp_hls_str\n", - " ret[\"TWeightI\"] = \"Recast\"\n", - " elif inp_is_bipolar and (not wt_is_bipolar):\n", - " ret[\"TSrcI\"] = \"Recast\"\n", - " ret[\"TWeightI\"] = \"Identity\"\n", - " elif (not inp_is_bipolar) and (not wt_is_bipolar):\n", - " ret[\"TSrcI\"] = \"Slice<%s>\" % inp_hls_str\n", - " ret[\"TWeightI\"] = \"Identity\"\n", - "\n", - " # fill in TDstI\n", - " ret[\"TDstI\"] = \"Slice<%s>\" % out_hls_str\n", - "\n", - " return ret\n", - "\n", - " def get_hls_compatible_weight_tensor(self, orig_weight_matrix):\n", - " \"\"\"Convert the original numpy weight matrix orig_weight_matrix into\n", - " a form suitable for passing to the hlslib call:\n", - " * ensure MH % PE == 0 and MW % SIMD == 0\n", - " * for bipolar {-1,+1} weights, convert to binary {0, 1}\n", - " * interleave rows between PEs\n", - " * reshape into (1, PE, WMEM, SIMD) and return\n", - " \"\"\"\n", - " mw = self.get_nodeattr(\"MW\")\n", - " mh = self.get_nodeattr(\"MH\")\n", - " pe = self.get_nodeattr(\"PE\")\n", - " simd = self.get_nodeattr(\"SIMD\")\n", - " wmem = self.calc_wmem()\n", - " assert orig_weight_matrix.shape == (\n", - " mw,\n", - " mh,\n", - " ), \"\"\"Weights matrix doesn't\n", - " have expected shape (mw, mh)\"\"\"\n", - " assert mw % simd == 0, \"Requirement MH divisable by SIMD is violated.\"\n", - " assert mh % pe == 0, \"Requirement MH divisable by PE is violated.\"\n", - " # start by transposing the original weight matrix, since ONNX and\n", - " # finn-hlslib use different assumptions\n", - " # ONNX uses (in_features, out_features) and matmul(x, W)\n", - " # finn-hlslib uses (out_features, in_features) and matmul(W, x)\n", - " ret = orig_weight_matrix.T\n", - " if self.get_weight_datatype() == DataType[\"BIPOLAR\"]:\n", - " # convert bipolar to binary\n", - " ret = (ret + 1) / 2\n", - " # interleave rows between PEs and reshape\n", - " # distribute rows between PEs\n", - " ret = interleave_matrix_outer_dim_from_partitions(ret, pe)\n", - " # create SIMD as innermost dimension and add a dummy outer dim\n", - " ret = ret.reshape(1, pe, wmem, simd)\n", - " # reverse the SIMD dimension\n", - " ret = np.flip(ret, axis=-1)\n", - " return ret\n", - "\n", - " def minimize_accumulator_width(self, model):\n", - " weights = model.get_initializer(self.onnx_node.input[1])\n", - " # since in the calculation the values of the weight matrix are used,\n", - " # for the bipolar case they need to be converted to bipolar\n", - " if self.get_nodeattr(\"binaryXnorMode\"):\n", - " weights = 2 * weights - 1\n", - " if len(self.onnx_node.input) > 2:\n", - " thresholds = model.get_initializer(self.onnx_node.input[2])\n", - " else:\n", - " thresholds = None\n", - " idt = self.get_input_datatype()\n", - " # calculate minimum and maximum values of accumulator\n", - " (acc_min, acc_max) = calculate_matvec_accumulator_range(weights, idt)\n", - " if thresholds is not None:\n", - " threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds)\n", - " # set threshold datatype (and accumulator datatype implicitly)\n", - " min_threshold = thresholds.min()\n", - " max_threshold = thresholds.max()\n", - " # clip threshold values\n", - " clip_upper = None\n", - " clip_lower = None\n", - " if max_threshold > acc_max + 1:\n", - " clip_upper = acc_max + 1\n", - " if min_threshold < acc_min:\n", - " clip_lower = acc_min\n", - " if (clip_lower is not None) or (clip_upper is not None):\n", - " warnings.warn(\"Clipping some thresholds in %s\" % self.onnx_node.name)\n", - " thresholds = np.clip(thresholds, clip_lower, clip_upper)\n", - " model.set_initializer(self.onnx_node.input[2], thresholds)\n", - " threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds)\n", - " min_threshold = thresholds.min()\n", - " max_threshold = thresholds.max()\n", - " # get range required by threshold values\n", - " tdt_min = min(acc_min, min_threshold)\n", - " tdt_max = max(acc_max, max_threshold)\n", - " if tdt_min < 0:\n", - " if abs(tdt_min) > tdt_max:\n", - " tdt = DataType.get_smallest_possible(tdt_min)\n", - " else:\n", - " tdt = DataType.get_smallest_possible(-tdt_max - 1)\n", - " else:\n", - " tdt = DataType.get_smallest_possible(tdt_max)\n", - " assert np.vectorize(tdt.allowed)(\n", - " threshold_tensor\n", - " ).all(), \"Thresholds in %s can't be expressed with type %s\" % (\n", - " self.onnx_node.name,\n", - " str(tdt),\n", - " )\n", - " self.set_nodeattr(\"accDataType\", tdt.name)\n", - " else:\n", - " if acc_min < 0:\n", - " if abs(acc_min) > acc_max:\n", - " adt = DataType.get_smallest_possible(acc_min)\n", - " else:\n", - " adt = DataType.get_smallest_possible(-acc_max - 1)\n", - " else:\n", - " adt = DataType.get_smallest_possible(acc_max)\n", - " # ensure a datatype divisible by 8-bits in case this is the last node\n", - " bw = roundup_to_integer_multiple(adt.bitwidth(), 8)\n", - " new_adt_name = adt.name.replace(str(adt.bitwidth()), str(bw))\n", - " adt = DataType[new_adt_name]\n", - " self.set_nodeattr(\"accDataType\", adt.name)\n", - " # for no-activation nodes, output dt = acc dt\n", - " self.set_nodeattr(\"outputDataType\", adt.name)\n", - " return DataType[self.get_nodeattr(\"accDataType\")]\n", - "\n", - " def get_hls_compatible_threshold_tensor(self, orig_thres_matrix):\n", - " \"\"\"Convert the original numpy weight matrix orig_weight_matrix into\n", - " a form suitable for passing to the hlslib call:\n", - " * ensure MH % PE == 0\n", - " * for bipolar weights&inputs, ensure thresholds are positive\n", - " * interleave rows between PEs\n", - " * reshape into (PE, TMEM, n_thres_steps) and return\n", - " \"\"\"\n", - " mh = self.get_nodeattr(\"MH\")\n", - " pe = self.get_nodeattr(\"PE\")\n", - " tmem = mh // pe\n", - " assert mh % pe == 0, \"Requirement MH divisable by PE is violated.\"\n", - " assert (\n", - " orig_thres_matrix.ndim == 2\n", - " ), \"\"\"Threshold matrix dimension is\n", - " not as expected (2).\"\"\"\n", - " n_thres_steps = orig_thres_matrix.shape[1]\n", - " inp_is_bipolar = self.get_input_datatype() == DataType[\"BIPOLAR\"]\n", - " wt_is_bipolar = self.get_weight_datatype() == DataType[\"BIPOLAR\"]\n", - " # reinterpret inp/wt as bipolar if bin_xnor_mode is iset\n", - " inp_is_binary = self.get_input_datatype() == DataType[\"BINARY\"]\n", - " wt_is_binary = self.get_weight_datatype() == DataType[\"BINARY\"]\n", - " bin_xnor_mode = self.get_nodeattr(\"binaryXnorMode\") == 1\n", - " inp_is_bipolar = inp_is_bipolar or (inp_is_binary and bin_xnor_mode)\n", - " wt_is_bipolar = wt_is_bipolar or (wt_is_binary and bin_xnor_mode)\n", - " if inp_is_bipolar and wt_is_bipolar:\n", - " # ensure all thresholds are nonnegative\n", - " assert (orig_thres_matrix >= 0).all()\n", - " # ensure all thresholds are integer\n", - " assert (orig_thres_matrix.astype(np.int32) == orig_thres_matrix).all()\n", - " ret = orig_thres_matrix\n", - " # workaround for vivado_hls threshold bug\n", - " if ret[0][0] == 0 and n_thres_steps == 1:\n", - " ret = np.copy(ret)\n", - " ret[0][0] = 1\n", - " warnings.warn(\n", - " \"Setting 0-valued first threshold to 1 to avoid vivado_hls bug\"\n", - " )\n", - " # ensure channels = mh , duplicating if necessary\n", - " if ret.shape[0] == 1:\n", - " ret = np.tile(ret, (mh, 1))\n", - " assert (\n", - " ret.shape[0] == mh\n", - " ), \"Channels of threshold matrix are not as expected (mh)\"\n", - " # distribute rows between PEs\n", - " ret = interleave_matrix_outer_dim_from_partitions(ret, pe)\n", - " assert (\n", - " ret.shape[0] == pe\n", - " ), \"\"\"First dimension after distribution of the\n", - " rows between PEs is not as expected (pe)\"\"\"\n", - " assert (\n", - " ret.shape[1] == tmem\n", - " ), \"\"\"Second dimension after distribution of the\n", - " rows between PEs is not as expected (tmem)\"\"\"\n", - " assert (\n", - " ret.shape[2] == n_thres_steps\n", - " ), \"\"\"Third dimension after distribution of the\n", - " rows between PEs is not as expected (n_thres_steps)\"\"\"\n", - " return ret.reshape(1, pe, tmem, n_thres_steps)\n", - "\n", - " def make_weight_file(self, weights, weight_file_mode, weight_file_name):\n", - " \"\"\"Produce a file containing given weights in appropriate format for this\n", - " layer. This file can be used for either synthesis or run-time reconfig\n", - " of weights.\n", - "\n", - " Arguments:\n", - "\n", - " * weights : numpy array with weights to be put into the file\n", - " * weight_file_mode : one of {hls_header, decoupled_verilog_dat,\n", - " decoupled_runtime}\n", - " * weight_file_name : filename for the weight file to be generated\n", - "\n", - " \"\"\"\n", - " # convert weights into hlslib-compatible format\n", - " weight_tensor = self.get_hls_compatible_weight_tensor(weights)\n", - " export_wdt = self.get_weight_datatype()\n", - " # we have converted bipolar weights to binary for export,\n", - " # so use it as such for weight generation\n", - " if self.get_weight_datatype() == DataType[\"BIPOLAR\"]:\n", - " export_wdt = DataType[\"BINARY\"]\n", - " if weight_file_mode == \"hls_header\":\n", - " weight_hls_code = numpy_to_hls_code(\n", - " weight_tensor, export_wdt, \"weights\", True, True\n", - " )\n", - " # write weights into C++ header file as dictated by finn-hlslib\n", - " f_weights = open(weight_file_name, \"w\")\n", - " if export_wdt.bitwidth() != 1:\n", - " f_weights.write(\n", - " \"const FixedPointWeights<{},{},{},{}> weights = \".format(\n", - " self.get_nodeattr(\"SIMD\"),\n", - " export_wdt.get_hls_datatype_str(),\n", - " self.get_nodeattr(\"PE\"),\n", - " self.calc_wmem(),\n", - " )\n", - " )\n", - " else:\n", - " f_weights.write(\n", - " \"const BinaryWeights<{},{},{}> weights = \".format(\n", - " self.get_nodeattr(\"SIMD\"),\n", - " self.get_nodeattr(\"PE\"),\n", - " self.calc_wmem(),\n", - " )\n", - " )\n", - " f_weights.write(weight_hls_code)\n", - " f_weights.close()\n", - " elif \"decoupled\" in weight_file_mode:\n", - " # create a weight stream for various flavors of decoupled mode:\n", - " # transpose weight tensor from (1, PE, WMEM, SIMD) to (1, WMEM, PE, SIMD)\n", - " weight_tensor_unflipped = np.transpose(weight_tensor, (0, 2, 1, 3))\n", - " # reverse SIMD flip for saving weights in .npy\n", - " weight_tensor_simd_flipped = np.flip(weight_tensor_unflipped, axis=-1)\n", - " # PE flip for saving weights in .dat\n", - " weight_tensor_pe_flipped = np.flip(weight_tensor_unflipped, axis=-2)\n", - " # reshape weight tensor (simd_flipped and pe_flipped) to desired shape\n", - " pe = self.get_nodeattr(\"PE\")\n", - " simd = self.get_nodeattr(\"SIMD\")\n", - " # simd_flipped\n", - " weight_tensor_simd_flipped = weight_tensor_simd_flipped.reshape(\n", - " 1, -1, pe * simd\n", - " )\n", - " weight_tensor_simd_flipped = weight_tensor_simd_flipped.copy()\n", - " # flipped\n", - " weight_tensor_pe_flipped = weight_tensor_pe_flipped.reshape(\n", - " 1, -1, pe * simd\n", - " )\n", - " weight_tensor_pe_flipped = weight_tensor_pe_flipped.copy()\n", - " if weight_file_mode == \"decoupled_npy\":\n", - " # save weight stream into npy for cppsim\n", - " np.save(weight_file_name, weight_tensor_simd_flipped)\n", - " elif weight_file_mode == \"decoupled_verilog_dat\":\n", - " # convert weight values into hexstring\n", - " weight_width = self.get_weightstream_width()\n", - " # pad to nearest 4 bits to get hex strings\n", - " weight_width_padded = roundup_to_integer_multiple(weight_width, 4)\n", - " weight_tensor_pe_flipped = pack_innermost_dim_as_hex_string(\n", - " weight_tensor_pe_flipped, export_wdt, weight_width_padded, prefix=\"\"\n", - " )\n", - " # add zeroes to pad out file to 1024 entries\n", - " weight_stream = weight_tensor_pe_flipped.flatten()\n", - " weight_stream = weight_stream.copy()\n", - " with open(weight_file_name, \"w\") as f:\n", - " for val in weight_stream:\n", - " f.write(val + \"\\n\")\n", - " elif weight_file_mode == \"decoupled_runtime\":\n", - " # memstream axi-lite interface will map each mem line to\n", - " # one or multiple 32-bit words\n", - " weight_width = self.get_weightstream_width()\n", - " words_per_memwidth = 2 ** math.ceil(math.log2(weight_width / 32))\n", - " if words_per_memwidth < 1:\n", - " words_per_memwidth = 1\n", - " weight_width_padded = words_per_memwidth * 32\n", - " # first, pack and ensure padding to 32 bits\n", - " weight_tensor_pe_flipped = pack_innermost_dim_as_hex_string(\n", - " weight_tensor_pe_flipped, export_wdt, weight_width_padded, prefix=\"\"\n", - " )\n", - " weight_stream = weight_tensor_pe_flipped.flatten()\n", - " weight_stream = weight_stream.copy()\n", - " with open(weight_file_name, \"w\") as f:\n", - " for val in weight_stream:\n", - " # split into groups of 8 hex digits (= 32 bits)\n", - " words_32b = textwrap.wrap(val, 8)\n", - " words_32b.reverse()\n", - " for word_32b in words_32b:\n", - " f.write(word_32b + \"\\n\")\n", - " else:\n", - " raise Exception(\"Unknown weight_file_mode\")\n", - "\n", - " else:\n", - " raise Exception(\"Unknown weight_file_mode\")\n", - "\n", - " def generate_params(self, model, path):\n", - " mem_mode = self.get_nodeattr(\"mem_mode\")\n", - " code_gen_dir = path\n", - " # weights, if not external\n", - " weights = model.get_initializer(self.onnx_node.input[1])\n", - " if mem_mode == \"const\":\n", - " # save hlslib-compatible weights in params.h\n", - " weight_filename = \"{}/params.h\".format(code_gen_dir)\n", - " self.make_weight_file(weights, \"hls_header\", weight_filename)\n", - " elif mem_mode == \"decoupled\" or mem_mode == \"external\":\n", - " weight_filename_sim = \"{}/weights.npy\".format(code_gen_dir)\n", - " # save decoupled weights for cppsim\n", - " self.make_weight_file(weights, \"decoupled_npy\", weight_filename_sim)\n", - " if mem_mode == \"decoupled\":\n", - " # also save weights as Verilog .dat file\n", - " # note that we provide two different .dat files, one for synth\n", - " # and one for synthesis. this is because URAM-based weights always\n", - " # need zero weights for synthesis, otherwise they get inferred\n", - " # as BRAM\n", - " weight_filename_rtl_synth = \"{}/memblock_synth_0.dat\".format(\n", - " code_gen_dir\n", - " )\n", - " weight_filename_rtl_sim = \"{}/memblock_sim_0.dat\".format(code_gen_dir)\n", - " # sim weights are always the true weights\n", - " self.make_weight_file(\n", - " weights, \"decoupled_verilog_dat\", weight_filename_rtl_sim\n", - " )\n", - " ram_style = self.get_nodeattr(\"ram_style\")\n", - " if ram_style == \"ultra\":\n", - " # UltraRAM must have no memory initializer, or only zeroes\n", - " # otherwise BRAM will be inferred instead of URAM\n", - " # as a workaround we provide a zero-weight init here\n", - " synth_weights = np.zeros_like(weights, dtype=np.float32)\n", - " else:\n", - " synth_weights = weights\n", - " self.make_weight_file(\n", - " synth_weights, \"decoupled_verilog_dat\", weight_filename_rtl_synth\n", - " )\n", - " else:\n", - " raise Exception(\n", - " \"\"\"Please set mem_mode to \"const\", \"decoupled\", or \"external\",\n", - " currently no other parameter value is supported!\"\"\"\n", - " )\n", - "\n", - " # save thresholds in thresh.h\n", - " if len(self.onnx_node.input) > 2:\n", - " thresholds = model.get_initializer(self.onnx_node.input[2])\n", - " if thresholds is not None:\n", - " threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds)\n", - " # use UINT32 threshold export for bipolar times bipolar\n", - " inp_is_bipolar = self.get_input_datatype() == DataType[\"BIPOLAR\"]\n", - " wt_is_bipolar = self.get_weight_datatype() == DataType[\"BIPOLAR\"]\n", - " # reinterpret inp/wt as bipolar if bin_xnor_mode is iset\n", - " inp_is_binary = self.get_input_datatype() == DataType[\"BINARY\"]\n", - " wt_is_binary = self.get_weight_datatype() == DataType[\"BINARY\"]\n", - " bin_xnor_mode = self.get_nodeattr(\"binaryXnorMode\") == 1\n", - " inp_is_bipolar = inp_is_bipolar or (inp_is_binary and bin_xnor_mode)\n", - " wt_is_bipolar = wt_is_bipolar or (wt_is_binary and bin_xnor_mode)\n", - " # get computed threshold datatype from attribute\n", - " tdt = DataType[self.get_nodeattr(\"accDataType\")]\n", - "\n", - " assert np.vectorize(tdt.allowed)(\n", - " threshold_tensor\n", - " ).all(), \"Thresholds in %s can't be expressed with type %s\" % (\n", - " self.onnx_node.name,\n", - " str(tdt),\n", - " )\n", - " thresholds_hls_code = numpy_to_hls_code(\n", - " threshold_tensor, tdt, \"thresholds\", False, True\n", - " )\n", - " # write thresholds into thresh.h\n", - " f_thresh = open(\"{}/thresh.h\".format(code_gen_dir), \"w\")\n", - " tdt_hls = tdt.get_hls_datatype_str()\n", - " # use binary to export bipolar activations\n", - " export_odt = self.get_output_datatype()\n", - " if self.get_output_datatype() == DataType[\"BIPOLAR\"]:\n", - " export_odt = DataType[\"BINARY\"]\n", - " odt_hls = export_odt.get_hls_datatype_str()\n", - " f_thresh.write(\n", - " \"static ThresholdsActivation<{},{},{},{},{},{},{}> threshs \\\n", - " = \".format(\n", - " self.calc_tmem(),\n", - " self.get_nodeattr(\"PE\"),\n", - " threshold_tensor.shape[-1],\n", - " tdt_hls,\n", - " odt_hls,\n", - " self.get_nodeattr(\"ActVal\"),\n", - " \"comp::less_equal<%s, %s>\" % (tdt_hls, tdt_hls),\n", - " )\n", - " )\n", - " f_thresh.write(thresholds_hls_code)\n", - " f_thresh.close()\n", - "\n", - " def execute_node(self, context, graph):\n", - " mode = self.get_nodeattr(\"exec_mode\")\n", - " mem_mode = self.get_nodeattr(\"mem_mode\")\n", - " node = self.onnx_node\n", - "\n", - " # TODO ensure codegen dir exists\n", - " if mode == \"cppsim\":\n", - " code_gen_dir = self.get_nodeattr(\"code_gen_dir_cppsim\")\n", - " elif mode == \"rtlsim\":\n", - " code_gen_dir = self.get_nodeattr(\"code_gen_dir_ipgen\")\n", - " else:\n", - " raise Exception(\n", - " \"\"\"Invalid value for attribute exec_mode! Is currently set to: {}\n", - " has to be set to one of the following value (\"cppsim\", \"rtlsim\")\"\"\".format(\n", - " mode\n", - " )\n", - " )\n", - "\n", - " # create a npy file fore each input of the node (in_ind is input index)\n", - " in_ind = 0\n", - " for inputs in node.input:\n", - " # it is assumed that the first input of the node is the data input\n", - " # the second input are the weights\n", - " # the third input are the thresholds\n", - " if in_ind == 0:\n", - " assert (\n", - " str(context[inputs].dtype) == \"float32\"\n", - " ), \"\"\"Input datatype is\n", - " not float32 as expected.\"\"\"\n", - " expected_inp_shape = self.get_folded_input_shape()\n", - " reshaped_input = context[inputs].reshape(expected_inp_shape)\n", - " if self.get_input_datatype() == DataType[\"BIPOLAR\"]:\n", - " # store bipolar activations as binary\n", - " reshaped_input = (reshaped_input + 1) / 2\n", - " export_idt = DataType[\"BINARY\"]\n", - " else:\n", - " export_idt = self.get_input_datatype()\n", - " # make copy before saving the array\n", - " reshaped_input = reshaped_input.copy()\n", - " np.save(\n", - " os.path.join(code_gen_dir, \"input_{}.npy\".format(in_ind)),\n", - " reshaped_input,\n", - " )\n", - " elif in_ind > 2:\n", - " raise Exception(\"Unexpected input found for MatrixVectorActivation\")\n", - " in_ind += 1\n", - "\n", - " if mode == \"cppsim\":\n", - " # execute the precompiled model\n", - " super().exec_precompiled_singlenode_model()\n", - " # load output npy file\n", - " super().npy_to_dynamic_output(context)\n", - " # reinterpret binary output as bipolar where needed\n", - " if self.get_output_datatype() == DataType[\"BIPOLAR\"]:\n", - " out = context[node.output[0]]\n", - " out = 2 * out - 1\n", - " context[node.output[0]] = out\n", - " assert (\n", - " context[node.output[0]].shape == self.get_normal_output_shape()\n", - " ), \"cppsim did not produce expected output shape\"\n", - " elif mode == \"rtlsim\":\n", - " sim = self.get_rtlsim()\n", - " nbits = self.get_instream_width()\n", - " inp = npy_to_rtlsim_input(\n", - " \"{}/input_0.npy\".format(code_gen_dir), export_idt, nbits\n", - " )\n", - " super().reset_rtlsim(sim)\n", - " super().toggle_clk(sim)\n", - " if mem_mode == \"external\" or mem_mode == \"decoupled\":\n", - " wnbits = self.get_weightstream_width()\n", - " export_wdt = self.get_weight_datatype()\n", - " # we have converted bipolar weights to binary for export,\n", - " # so use it as such for weight generation\n", - " if self.get_weight_datatype() == DataType[\"BIPOLAR\"]:\n", - " export_wdt = DataType[\"BINARY\"]\n", - " wei = npy_to_rtlsim_input(\n", - " \"{}/weights.npy\".format(code_gen_dir), export_wdt, wnbits\n", - " )\n", - " num_w_reps = np.prod(self.get_nodeattr(\"numInputVectors\"))\n", - " io_dict = {\n", - " \"inputs\": {\"in0\": inp, \"weights\": wei * num_w_reps},\n", - " \"outputs\": {\"out\": []},\n", - " }\n", - " self.rtlsim_multi_io(sim, io_dict)\n", - " output = io_dict[\"outputs\"][\"out\"]\n", - " else:\n", - " output = self.rtlsim(sim, inp)\n", - " odt = self.get_output_datatype()\n", - " target_bits = odt.bitwidth()\n", - " packed_bits = self.get_outstream_width()\n", - " out_npy_path = \"{}/output.npy\".format(code_gen_dir)\n", - " out_shape = self.get_folded_output_shape()\n", - " rtlsim_output_to_npy(\n", - " output, out_npy_path, odt, out_shape, packed_bits, target_bits\n", - " )\n", - "\n", - " # load and reshape output\n", - " output = np.load(out_npy_path)\n", - " oshape = self.get_normal_output_shape()\n", - " output = np.asarray([output], dtype=np.float32).reshape(*oshape)\n", - " context[node.output[0]] = output\n", - " else:\n", - " raise Exception(\n", - " \"\"\"Invalid value for attribute exec_mode! Is currently set to: {}\n", - " has to be set to one of the following value (\"cppsim\", \"rtlsim\")\"\"\".format(\n", - " mode\n", - " )\n", - " )\n", - "\n", - " def global_includes(self):\n", - " self.code_gen_dict[\"$GLOBALS$\"] = ['#include \"weights.hpp\"']\n", - " self.code_gen_dict[\"$GLOBALS$\"] += ['#include \"activations.hpp\"']\n", - "\n", - " mem_mode = self.get_nodeattr(\"mem_mode\")\n", - " if mem_mode not in [\"const\", \"decoupled\", \"external\"]:\n", - " raise Exception(\n", - " \"\"\"Please set mem_mode to \"const\", \"decoupled\", or \"external\",\n", - " currently no other parameter value is supported!\"\"\"\n", - " )\n", - " self.code_gen_dict[\"$GLOBALS$\"] += ['#include \"mvau.hpp\"']\n", - " if self.calc_tmem() != 0:\n", - " # TODO find a better way of checking for no pregenerated thresholds\n", - " self.code_gen_dict[\"$GLOBALS$\"] += ['#include \"thresh.h\"']\n", - "\n", - " def defines(self, var):\n", - " # Only ipgen mode: Make sure that SIMD parameter satisfies minimum requirements.\n", - " if var == \"ipgen\":\n", - " SIMD = self.get_nodeattr(\"SIMD\")\n", - " MW = self.get_nodeattr(\"MW\")\n", - " condition = SIMD >= (MW / 1024)\n", - " msg = (\n", - " f\"HLS synthesis of MatrixVectorActivation requires: \"\n", - " f\"SIMD >= MW / 1024. This is not fulfilled with: SIMD={SIMD} \"\n", - " f\"and MW={MW} for node: {self.onnx_node.name}.\"\n", - " )\n", - " assert condition, msg\n", - " mem_mode = self.get_nodeattr(\"mem_mode\")\n", - " numInputVectors = list(self.get_nodeattr(\"numInputVectors\"))\n", - " numReps = np.prod(numInputVectors)\n", - " self.code_gen_dict[\"$DEFINES$\"] = [\n", - " \"\"\"#define MW1 {}\\n #define MH1 {}\\n\n", - " #define SIMD1 {}\\n #define PE1 {}\\n #define WMEM1 {}\\n\n", - " #define TMEM1 {}\\n #define numReps {}\"\"\".format(\n", - " self.get_nodeattr(\"MW\"),\n", - " self.get_nodeattr(\"MH\"),\n", - " self.get_nodeattr(\"SIMD\"),\n", - " self.get_nodeattr(\"PE\"),\n", - " self.calc_wmem(),\n", - " self.calc_tmem(),\n", - " numReps,\n", - " )\n", - " ]\n", - " if mem_mode == \"decoupled\" or mem_mode == \"external\":\n", - " wdt = self.get_weight_datatype()\n", - " self.code_gen_dict[\"$DEFINES$\"].append(\n", - " \"#define WP1 {}\\n\".format(wdt.bitwidth())\n", - " )\n", - "\n", - " def read_npy_data(self):\n", - " code_gen_dir = self.get_nodeattr(\"code_gen_dir_cppsim\")\n", - " dtype = self.get_input_datatype()\n", - " if dtype == DataType[\"BIPOLAR\"]:\n", - " # use binary for bipolar storage\n", - " dtype = DataType[\"BINARY\"]\n", - " elem_bits = dtype.bitwidth()\n", - " packed_bits = self.get_instream_width()\n", - " packed_hls_type = \"ap_uint<%d>\" % packed_bits\n", - " elem_hls_type = dtype.get_hls_datatype_str()\n", - " npy_type = \"float\"\n", - " npy_in = \"%s/input_0.npy\" % code_gen_dir\n", - " self.code_gen_dict[\"$READNPYDATA$\"] = []\n", - " # note: the innermost dim is reversed for the input\n", - " self.code_gen_dict[\"$READNPYDATA$\"].append(\n", - " 'npy2apintstream<%s, %s, %d, %s>(\"%s\", in0, false);'\n", - " % (packed_hls_type, elem_hls_type, elem_bits, npy_type, npy_in)\n", - " )\n", - "\n", - " mem_mode = self.get_nodeattr(\"mem_mode\")\n", - " if mem_mode == \"decoupled\" or mem_mode == \"external\":\n", - " wdt = self.get_weight_datatype()\n", - " elem_bits = wdt.bitwidth()\n", - " packed_bits = self.get_weightstream_width()\n", - " packed_hls_type = \"ap_uint<%d>\" % packed_bits\n", - " elem_hls_type = wdt.get_hls_datatype_str()\n", - " npy_type = \"float\"\n", - " npy_in = \"%s/weights.npy\" % code_gen_dir\n", - "\n", - " self.code_gen_dict[\"$READNPYDATA$\"].append(\n", - " 'npy2apintstream<%s, %s, %d, %s>(\"%s\", weights, false, numReps);'\n", - " % (packed_hls_type, elem_hls_type, elem_bits, npy_type, npy_in)\n", - " )\n", - "\n", - " def strm_decl(self):\n", - " mem_mode = self.get_nodeattr(\"mem_mode\")\n", - " self.code_gen_dict[\"$STREAMDECLARATIONS$\"] = []\n", - " self.code_gen_dict[\"$STREAMDECLARATIONS$\"].append(\n", - " 'hls::stream> in0 (\"in0\");'.format(self.get_instream_width())\n", - " )\n", - " self.code_gen_dict[\"$STREAMDECLARATIONS$\"].append(\n", - " 'hls::stream> out (\"out\");'.format(self.get_outstream_width())\n", - " )\n", - "\n", - " if mem_mode == \"decoupled\" or mem_mode == \"external\":\n", - " self.code_gen_dict[\"$STREAMDECLARATIONS$\"].append(\n", - " 'hls::stream> weights (\"weights\");'.format(\n", - " self.get_weightstream_width()\n", - " )\n", - " )\n", - "\n", - " def docompute(self):\n", - " mem_mode = self.get_nodeattr(\"mem_mode\")\n", - " map_to_hls_mult_style = {\n", - " \"auto\": \"ap_resource_dflt()\",\n", - " \"lut\": \"ap_resource_lut()\",\n", - " \"dsp\": \"ap_resource_dsp()\",\n", - " }\n", - " tmpl_args = self.get_template_param_values()\n", - " if self.calc_tmem() == 0:\n", - " odtype_hls_str = self.get_output_datatype().get_hls_datatype_str()\n", - " threshs = \"PassThroughActivation<%s>()\" % odtype_hls_str\n", - " else:\n", - " threshs = \"threshs\"\n", - " if mem_mode == \"const\":\n", - " self.code_gen_dict[\"$DOCOMPUTE$\"] = [\n", - " \"\"\"Matrix_Vector_Activate_Batch\n", - " (in0, out, weights, {}, numReps, {});\"\"\".format(\n", - " tmpl_args[\"TSrcI\"],\n", - " tmpl_args[\"TDstI\"],\n", - " tmpl_args[\"TWeightI\"],\n", - " threshs,\n", - " map_to_hls_mult_style[self.get_nodeattr(\"resType\")],\n", - " )\n", - " ]\n", - " elif mem_mode == \"decoupled\" or mem_mode == \"external\":\n", - " wdt = self.get_weight_datatype()\n", - " if wdt == DataType[\"BIPOLAR\"]:\n", - " export_wdt = DataType[\"BINARY\"]\n", - " else:\n", - " export_wdt = wdt\n", - " wdtype_hls_str = export_wdt.get_hls_datatype_str()\n", - " self.code_gen_dict[\"$DOCOMPUTE$\"] = [\n", - " \"\"\"Matrix_Vector_Activate_Stream_Batch\n", - " (in0, out, weights, {}, numReps, {});\"\"\".format(\n", - " tmpl_args[\"TSrcI\"],\n", - " tmpl_args[\"TDstI\"],\n", - " tmpl_args[\"TWeightI\"],\n", - " wdtype_hls_str,\n", - " threshs,\n", - " map_to_hls_mult_style[self.get_nodeattr(\"resType\")],\n", - " )\n", - " ]\n", - "\n", - " else:\n", - " raise Exception(\n", - " \"\"\"Please set mem_mode to \"const\", \"decoupled\", or \"external\",\n", - " currently no other parameter value is supported!\"\"\"\n", - " )\n", - "\n", - " def dataoutstrm(self):\n", - " code_gen_dir = self.get_nodeattr(\"code_gen_dir_cppsim\")\n", - " dtype = self.get_output_datatype()\n", - " if dtype == DataType[\"BIPOLAR\"]:\n", - " # use binary for bipolar storage\n", - " dtype = DataType[\"BINARY\"]\n", - " elem_bits = dtype.bitwidth()\n", - " packed_bits = self.get_outstream_width()\n", - " packed_hls_type = \"ap_uint<%d>\" % packed_bits\n", - " elem_hls_type = dtype.get_hls_datatype_str()\n", - " npy_type = \"float\"\n", - " npy_out = \"%s/output.npy\" % code_gen_dir\n", - " shape = self.get_folded_output_shape()\n", - " shape_cpp_str = str(shape).replace(\"(\", \"{\").replace(\")\", \"}\")\n", - "\n", - " # note: the innermost dim is not reversed for the output\n", - " self.code_gen_dict[\"$DATAOUTSTREAM$\"] = [\n", - " 'apintstream2npy<%s, %s, %d, %s>(out, %s, \"%s\", false);'\n", - " % (\n", - " packed_hls_type,\n", - " elem_hls_type,\n", - " elem_bits,\n", - " npy_type,\n", - " shape_cpp_str,\n", - " npy_out,\n", - " )\n", - " ]\n", - "\n", - " def save_as_npy(self):\n", - " self.code_gen_dict[\"$SAVEASCNPY$\"] = []\n", - "\n", - " def blackboxfunction(self):\n", - " mem_mode = self.get_nodeattr(\"mem_mode\")\n", - " if mem_mode == \"const\":\n", - " self.code_gen_dict[\"$BLACKBOXFUNCTION$\"] = [\n", - " \"\"\"void {}(hls::stream> &in0,\n", - " hls::stream> &out\n", - " )\"\"\".format(\n", - " self.onnx_node.name,\n", - " self.get_instream_width(),\n", - " self.get_outstream_width(),\n", - " )\n", - " ]\n", - " elif mem_mode == \"decoupled\" or mem_mode == \"external\":\n", - " self.code_gen_dict[\"$BLACKBOXFUNCTION$\"] = [\n", - " \"\"\"void {}(\n", - " hls::stream> &in0,\n", - " hls::stream> &weights,\n", - " hls::stream> &out\n", - " )\"\"\".format(\n", - " self.onnx_node.name,\n", - " self.get_instream_width(),\n", - " self.get_weightstream_width(),\n", - " self.get_outstream_width(),\n", - " )\n", - " ]\n", - "\n", - " else:\n", - " raise Exception(\n", - " \"\"\"Please set mem_mode to \"const\" or \"decoupled\", currently no other\n", - " parameter value is supported!\"\"\"\n", - " )\n", - "\n", - " def pragmas(self):\n", - " mem_mode = self.get_nodeattr(\"mem_mode\")\n", - " ram_style_thresholds = self.get_nodeattr(\"ram_style_thresholds\")\n", - " self.code_gen_dict[\"$PRAGMAS$\"] = [\n", - " \"#pragma HLS INTERFACE axis port=in0 name=in0_\" + self.hls_sname()\n", - " ]\n", - " self.code_gen_dict[\"$PRAGMAS$\"].append(\n", - " \"#pragma HLS INTERFACE axis port=out name=out_\" + self.hls_sname()\n", - " )\n", - " self.code_gen_dict[\"$PRAGMAS$\"].append(\n", - " \"#pragma HLS INTERFACE ap_ctrl_none port=return\"\n", - " )\n", - "\n", - " if mem_mode == \"const\":\n", - " self.code_gen_dict[\"$PRAGMAS$\"].append('#include \"params.h\"')\n", - " # the weight tensor is ap_uint [PE][WMEM]\n", - " # partition for parallel access along the PE dimension (dim 1)\n", - " self.code_gen_dict[\"$PRAGMAS$\"].append(\n", - " (\n", - " \"#pragma HLS ARRAY_PARTITION variable=weights.m_weights \"\n", - " \"complete dim=1\"\n", - " )\n", - " )\n", - " elif mem_mode == \"decoupled\" or mem_mode == \"external\":\n", - " self.code_gen_dict[\"$PRAGMAS$\"].append(\n", - " \"#pragma HLS INTERFACE axis port=weights name=weights_\"\n", - " + self.hls_sname()\n", - " )\n", - " self.code_gen_dict[\"$PRAGMAS$\"].append(\n", - " \"#pragma HLS stream depth=8 variable=weights\"\n", - " )\n", - "\n", - " else:\n", - " raise Exception(\n", - " \"\"\"Please set mem_mode to \"const\", \"decoupled\", or external,\n", - " currently no other parameter value is supported!\"\"\"\n", - " )\n", - "\n", - " # the threshold tensor is acc_type [PE][TMEM][N_THRES]\n", - " # partition for parallel access along PE and N_THRES\n", - " # dimensions (dims 1 and 3)\n", - " if self.calc_tmem() != 0:\n", - " # TODO find a better way of checking for no pregenerated thresholds\n", - " self.code_gen_dict[\"$PRAGMAS$\"].append(\n", - " (\n", - " \"#pragma HLS ARRAY_PARTITION variable=threshs.m_thresholds \"\n", - " \"complete dim=1\"\n", - " )\n", - " )\n", - " self.code_gen_dict[\"$PRAGMAS$\"].append(\n", - " (\n", - " \"#pragma HLS ARRAY_PARTITION variable=threshs.m_thresholds \"\n", - " \"complete dim=3\"\n", - " )\n", - " )\n", - " # add resource pragma for thresholds if set\n", - " if ram_style_thresholds == \"distributed\":\n", - " self.code_gen_dict[\"$PRAGMAS$\"].append(\n", - " (\n", - " \"#pragma HLS RESOURCE variable=threshs.m_thresholds \"\n", - " \"core=ROM_2P_LUTRAM\"\n", - " )\n", - " )\n", - " elif ram_style_thresholds == \"block\":\n", - " self.code_gen_dict[\"$PRAGMAS$\"].append(\n", - " (\n", - " \"#pragma HLS RESOURCE variable=threshs.m_thresholds \"\n", - " \"core=ROM_2P_BRAM\"\n", - " )\n", - " )\n", - " elif ram_style_thresholds == \"auto\":\n", - " # no pragma needed\n", - " pass\n", - " else:\n", - " raise Exception(\n", - " \"Unrecognized ram_style_thresholds value:\" + ram_style_thresholds\n", - " )\n", - "\n", - " def code_generation_ipi(self):\n", - " cmd = []\n", - " # add streamer if needed\n", - " mem_mode = self.get_nodeattr(\"mem_mode\")\n", - " if mem_mode == \"decoupled\":\n", - " runtime_writable = self.get_nodeattr(\"runtime_writeable_weights\") == 1\n", - " if self.get_nodeattr(\"ram_style\") == \"ultra\":\n", - " assert (\n", - " runtime_writable == 1\n", - " ), \"Layer with URAM weights must have runtime_writeable_weights=1\"\n", - " node_name = self.onnx_node.name\n", - " sname = self.hls_sname()\n", - " # create a hierarchy for this layer, with the same port names\n", - " clk_name = self.get_verilog_top_module_intf_names()[\"clk\"][0]\n", - " rst_name = self.get_verilog_top_module_intf_names()[\"rst\"][0]\n", - " dout_name = self.get_verilog_top_module_intf_names()[\"m_axis\"][0][0]\n", - " din_name = self.get_verilog_top_module_intf_names()[\"s_axis\"][0][0]\n", - " cmd.append(\"create_bd_cell -type hier %s\" % node_name)\n", - " cmd.append(\"create_bd_pin -dir I -type clk /%s/%s\" % (node_name, clk_name))\n", - " cmd.append(\"create_bd_pin -dir I -type rst /%s/%s\" % (node_name, rst_name))\n", - " cmd.append(\n", - " \"create_bd_intf_pin -mode Master \"\n", - " \"-vlnv xilinx.com:interface:axis_rtl:1.0 /%s/%s\"\n", - " % (node_name, dout_name)\n", - " )\n", - " cmd.append(\n", - " \"create_bd_intf_pin -mode Slave \"\n", - " \"-vlnv xilinx.com:interface:axis_rtl:1.0 /%s/%s\" % (node_name, din_name)\n", - " )\n", - " # instantiate the hls ip\n", - " cmd.append(\n", - " \"create_bd_cell -type ip -vlnv %s /%s/%s\"\n", - " % (self.get_nodeattr(\"ip_vlnv\"), node_name, node_name)\n", - " )\n", - " # instantiate a streamer and connect it to the HLS IP\n", - " strm_vlnv = \"xilinx.com:user:memstream:1.0\"\n", - " strm_inst = node_name + \"_wstrm\"\n", - " cmd.append(\n", - " \"create_bd_cell -type ip -vlnv %s /%s/%s\"\n", - " % (strm_vlnv, node_name, strm_inst)\n", - " )\n", - " cmd.append(\n", - " \"set_property -dict [list \"\n", - " \"CONFIG.NSTREAMS {1} \"\n", - " \"CONFIG.MEM_DEPTH {%d} \"\n", - " \"CONFIG.MEM_WIDTH {%d} \"\n", - " \"CONFIG.MEM_INIT {%s} \"\n", - " \"CONFIG.RAM_STYLE {%s} \"\n", - " \"CONFIG.STRM0_DEPTH {%d} \"\n", - " \"CONFIG.STRM0_WIDTH {%d} \"\n", - " \"CONFIG.STRM0_OFFSET {0} \"\n", - " \"] [get_bd_cells /%s/%s]\"\n", - " % (\n", - " self.calc_wmem(),\n", - " self.get_weightstream_width_padded(),\n", - " self.get_nodeattr(\"code_gen_dir_ipgen\") + \"/\",\n", - " self.get_nodeattr(\"ram_style\"),\n", - " self.calc_wmem(),\n", - " self.get_weightstream_width_padded(),\n", - " node_name,\n", - " strm_inst,\n", - " )\n", - " )\n", - " cmd.append(\n", - " \"connect_bd_intf_net [get_bd_intf_pins %s/%s/m_axis_0] \"\n", - " \"[get_bd_intf_pins %s/%s/weights_%s]\"\n", - " % (node_name, strm_inst, node_name, node_name, sname)\n", - " )\n", - " cmd.append(\n", - " \"connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/aresetn]\"\n", - " % (node_name, rst_name, node_name, strm_inst)\n", - " )\n", - " cmd.append(\n", - " \"connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/aclk]\"\n", - " % (node_name, clk_name, node_name, strm_inst)\n", - " )\n", - " cmd.append(\n", - " \"connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/%s]\"\n", - " % (node_name, rst_name, node_name, node_name, rst_name)\n", - " )\n", - " cmd.append(\n", - " \"connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/%s]\"\n", - " % (node_name, clk_name, node_name, node_name, clk_name)\n", - " )\n", - " cmd.append(\n", - " \"connect_bd_intf_net [get_bd_intf_pins %s/%s] \"\n", - " \"[get_bd_intf_pins %s/%s/%s]\"\n", - " % (node_name, din_name, node_name, node_name, din_name)\n", - " )\n", - " cmd.append(\n", - " \"connect_bd_intf_net [get_bd_intf_pins %s/%s] \"\n", - " \"[get_bd_intf_pins %s/%s/%s]\"\n", - " % (node_name, dout_name, node_name, node_name, dout_name)\n", - " )\n", - " if runtime_writable:\n", - " # expose axi lite interface for writeable weights\n", - " axilite_name = self.get_verilog_top_module_intf_names()[\"axilite\"][0]\n", - " cmd.append(\n", - " \"create_bd_intf_pin -mode Slave \"\n", - " \"-vlnv xilinx.com:interface:aximm_rtl:1.0 /%s/%s\"\n", - " % (node_name, axilite_name)\n", - " )\n", - " cmd.append(\n", - " \"connect_bd_intf_net [get_bd_intf_pins %s/%s] \"\n", - " \"[get_bd_intf_pins %s/%s/%s]\"\n", - " % (node_name, axilite_name, node_name, strm_inst, axilite_name)\n", - " )\n", - " # TODO calculate and pass in segment size here\n", - " cmd.append(\"assign_bd_address\")\n", - " cmd.append(\"save_bd_design\")\n", - " elif mem_mode == \"const\" or mem_mode == \"external\":\n", - " # base class impl sufficient for const/external modes\n", - " return super().code_generation_ipi()\n", - " else:\n", - " raise Exception(\"Unrecognized mem_mode for MatrixVectorActivation\")\n", - " return cmd\n", - "\n", - " def get_verilog_top_module_intf_names(self):\n", - " intf_names = super().get_verilog_top_module_intf_names()\n", - " mem_mode = self.get_nodeattr(\"mem_mode\")\n", - " sname = self.hls_sname()\n", - " if mem_mode == \"external\":\n", - " intf_names[\"s_axis\"].append(\n", - " (\"weights_\" + sname, self.get_weightstream_width_padded())\n", - " )\n", - " if mem_mode == \"decoupled\":\n", - " # only expose axilite interface if attribute is set\n", - " runtime_writable = self.get_nodeattr(\"runtime_writeable_weights\") == 1\n", - " if runtime_writable:\n", - " intf_names[\"axilite\"] = [\"s_axilite\"]\n", - " return intf_names\n", - "\n", - " def get_op_and_param_counts(self):\n", - " in_features = self.get_nodeattr(\"MW\")\n", - " out_features = self.get_nodeattr(\"MH\")\n", - " weight_bits = self.get_weight_datatype().bitwidth()\n", - " inp_bits = self.get_input_datatype().bitwidth()\n", - " num_inp_vec = self.get_nodeattr(\"numInputVectors\")\n", - " num_repetitions = int(np.prod(num_inp_vec))\n", - " mac_count = in_features * out_features * num_repetitions\n", - " # cannonicalize op type: highest bitwidth operand first s.t.\n", - " # e.g. mac_8bx4b and mac_4bx8b don't appear as two different op types\n", - " bw1 = min(inp_bits, weight_bits)\n", - " bw2 = max(inp_bits, weight_bits)\n", - " mac_op_type = \"op_mac_%dbx%db\" % (bw1, bw2)\n", - " weight_param_type = \"param_weight_%db\" % (weight_bits)\n", - " weight_count = in_features * out_features\n", - " ret_dict = {mac_op_type: mac_count, weight_param_type: weight_count}\n", - " if self.get_nodeattr(\"noActivation\") == 0:\n", - " tdt = DataType[self.get_nodeattr(\"accDataType\")]\n", - " thres_bits = tdt.bitwidth()\n", - " thres_param_type = \"param_threshold_%db\" % (thres_bits)\n", - " thres_count = out_features\n", - " ret_dict[thres_param_type] = thres_count\n", - " return ret_dict\n", - "\n", - " def derive_characteristic_fxns(self, period):\n", - " n_inps = np.prod(self.get_folded_input_shape()[:-1])\n", - " io_dict = {\n", - " \"inputs\": {\n", - " \"in0\": [0 for i in range(n_inps)],\n", - " },\n", - " \"outputs\": {\"out\": []},\n", - " }\n", - " mem_mode = self.get_nodeattr(\"mem_mode\")\n", - " if mem_mode in [\"decoupled\", \"external\"]:\n", - " n_weight_inps = self.calc_wmem()\n", - " num_w_reps = np.prod(self.get_nodeattr(\"numInputVectors\"))\n", - " io_dict[\"inputs\"][\"weights\"] = [\n", - " 0 for i in range(num_w_reps * n_weight_inps)\n", - " ]\n", - " super().derive_characteristic_fxns(period, override_rtlsim_dict=io_dict)\n", - "\n" - ] + "data": { + "image/png": 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3xqhXr14aP368/ve//9l95kAWT09P6/dTRkaGTpw4IW9vb1WpUsX6uZWkpk2bKjAw0CaHtm3bpi1btliPXEv2v7Zt2rSxnp4K4No4bRK4jT3wwAPXnLDklVde0TfffKPmzZvrrrvuUrNmzfTMM8/c9PTj5cqVs3nu6+srSQoKCsrWnpmZqZSUFOupnGvXrtXQoUO1fv16nT171qZ/SkqKdayr2bNnj7Zs2XLVPwQSExMlSQcPHlSZMmWynUp4tVOSrubKfS1evLgkWa8JyirirhzXw8NDFStWtC7PrePHj+vs2bM5xlmtWjVlZmbq8OHD1lPDcmvfvn2qUqWKChTI/T8L9sSyb98+tWnTJlfj9u3bV+fPn9fmzZtzvR+5jb9jx47q1auXDh48qODgYM2ZM0fp6enq0KGD3WNd7vjx40pOTtZnn32mzz77LMc+WZ+9wYMHa/ny5XrggQdUuXJlNWvWTM8//7waNGiQ6+1d7uDBg9bTUy+XdXrzwYMHrYWDpBxnoM3Jnj17lJKSotKlS+e4PGt/pEunz7711ltauXJlth8Psn50ybpe8PJYrqZQoULZcrh48eLZrrW7mivzMqf1c/tdcS3h4eGaMmWK9u7dq3379slisSgsLMxa1HXt2lU//fSTGjRoYC2ODh48KDc3t2yz/gYEBKhYsWLZvhOu9X7NmDFDp0+f1uTJk/Xcc89dN96ryczM1Pjx4zVp0iTt37/f5trCrO9mSXJzc1P79u01efJknT17VoULF9bMmTNVqFAh6/XRkv2vbW4/kwAo3oA7WunSpRUfH6+lS5dq8eLFWrx4saZNm6aOHTtq+vTpNzzu5ddC5KbdGCPp0h93TZo0UdWqVfXRRx8pKChIHh4e+vHHHzV27NhsE47kJDMzU48++qgGDRqU4/J77rknl3uRO9fbJ9ivVatWmj17tkaNGqUZM2Y4dCbEdu3aqV+/fpo5c6beeOMN/e9//9N9991nd9F+pazP5gsvvHDVox9Z10VVq1ZNu3fv1sKFC7VkyRLNmzdPkyZN0pAhQ6xT0uel3M5UmJmZqdKlS9scZblc1h/mycnJatSokXx8fDRixAhVqlRJhQoV0u+//67BgwfnKm+vdLW8utn1L89LR3xXZB3tXLNmjf766y/VqVNHRYoUUXh4uCZMmKDTp09r8+bNevfdd7Ote7WjuFe61vvVoEEDxcfHa+LEiXrmmWdu+Fqx9957T//5z3/UuXNnvf322ypRooTc3NzUt2/fbO9fx44d9f7772v+/Pl67rnnNGvWLOukQlnsfW1v59kzAUejeAPucB4eHmrZsqVatmypzMxMvfLKK/r000/1n//8R5UrV871HxiO8MMPPygtLU3ff/+9zS/nl5+eleVqcVWqVEmnT59W06ZNr7mt4OBgrVixQqdPn7Y5+rZ79+4bjP7q28ka9/JTCy9cuKD9+/dfN84r+fn5qXDhwjnGuWvXLrm5uWU7wpkblSpV0oYNG5Senp7rCVTsiaVSpUratm1brsZ98skn1axZM3Xq1ElFixbNNtvozcRfokQJRUZGaubMmWrfvr3Wrl2bbfKEG30tihYtqoyMjFy9p0WKFNGzzz6rZ599VhcuXFDr1q317rvvKjo6WoUKFcrVNrMEBwdf9T3IWn4jKlWqpOXLl6tBgwbX/ON69erVOnHihL799ls1bNjQ2r5///5s40mXTrOz93OfF3L7XXGt78By5cqpXLly+umnn/TXX39ZT9Vs2LCh+vfvrzlz5igjI8PmdQkODlZmZqb27NljM/nTsWPHlJycbNf7VblyZY0ZM0aNGzfWY489phUrVqho0aK5Xj/L3Llz9fDDD+vLL7+0aU9OTs42mVCNGjV07733aubMmSpbtqwOHTqUbXbL3L62AOzHNW/AHezEiRM2z93c3KxHB7KmrC5SpIgk3dS09rmV9Wv55b+Op6SkaNq0adn6FilSJMeYnnnmGa1fv15Lly7Ntiw5Odl6fd3jjz+uixcv2hQGGRkZdk+xfT1NmzaVh4eHJkyYYLNfX375pVJSUhQZGWltO3TokPUP7qtxd3dXs2bNtGDBAh04cMDafuzYMc2aNUsPPfSQfHx87I6zTZs2+vfffzVx4sRsy652FNGeWNq0aaM//vgj20x6Vxu/Y8eOmjBhgqZMmaLBgwc7NP4OHTpox44dGjhwoNzd3dWuXbsbHiuLu7u72rRpo3nz5uVYpF5++4gr887Dw0MhISEyxig9Pf3qO3kVjz/+uDZu3Kj169db286cOaPPPvtM5cuXV0hIiN1jSpdyKSMjQ2+//Xa2ZRcvXrTmX055e+HCBU2aNMlmnTp16qhChQoaN25cttx1xpHq3H5XFC5c2NqWk/DwcK1cuVIbN260Fm+1a9dW0aJFNWrUKHl5ealu3brW/o8//rgkZfvR4KOPPpIkm++E3AgNDdWPP/6onTt3qmXLljp37pxd60uX3sMr34M5c+bon3/+ybF/hw4dtGzZMo0bN04lS5ZU8+bNbZbn9rUFYD+OvAG3scWLF+dYDDz44IOqWLGiXnrpJSUlJemRRx5R2bJldfDgQX388ceqXbu29Rfh2rVry93dXaNHj1ZKSoo8PT2t92FztGbNmlmPBHbv3l2nT5/W559/rtKlS+vo0aM2fevWravJkyfrnXfeUeXKlVW6dGk98sgjGjhwoL7//nu1aNHCOjX4mTNntHXrVs2dO1cHDhxQqVKl1LJlSzVo0ECvv/66Dhw4oJCQEH377be5mhTFHn5+foqOjtbw4cP12GOP6YknntDu3bs1adIk3X///TYX+Xfs2FFxcXHX/UP2nXfeUWxsrB566CG98sorKlCggD799FOlpaVpzJgxNxRnx44dNWPGDPXv39/6R+iZM2e0fPlyvfLKKzneH82eWAYOHKi5c+fq6aefVufOnVW3bl0lJSXp+++/15QpU1SrVq1sY/fq1Uupqal688035evrqzfeeMMh8UdGRqpkyZKaM2eOmjdvnu2zfKOvxahRo7Rq1SrVq1dPXbt2VUhIiJKSkvT7779r+fLlSkpKknTpcx4QEKAGDRrI399fO3fu1MSJExUZGXlDR01ef/11ffXVV2revLl69+6tEiVKaPr06dq/f7/mzZt3w6edNmrUSN27d9fIkSMVHx+vZs2aqWDBgtqzZ4/mzJmj8ePHq23btnrwwQdVvHhxRUVFqXfv3rJYLPrvf/+b7XPs5uamyZMnq2XLlqpdu7ZefPFFlSlTRrt27dL27dtz/EM/L+X2u8LLy0shISH6+uuvdc8996hEiRKqUaOG9dq98PBwzZw5UxaLxXoapbu7ux588EEtXbpUjRs3trkdQ61atRQVFaXPPvvMesrpxo0bNX36dD355JN6+OGH7d6X+vXra8GCBXr88cfVtm1bzZ8/365bkLRo0UIjRozQiy++qAcffFBbt27VzJkzbc4WuNzzzz+vQYMG6bvvvlOPHj2ybSu3ry2AG3CLZ7cEcAtc61YBumwa/Llz55pmzZqZ0qVLGw8PD1OuXDnTvXt3c/ToUZvxPv/8c1OxYkXj7u5uc9uAq90qYM6cOTnG8+uvv9q0Dx061Egyx48ft7Z9//33JjQ01BQqVMiUL1/ejB492jp1+/79+639EhISTGRkpClatKiRZBPHqVOnTHR0tKlcubLx8PAwpUqVMg8++KD54IMPbG5hcOLECdOhQwfj4+NjfH19TYcOHczmzZvtulXAlfuU9RpceWuFiRMnmqpVq5qCBQsaf39/06NHj2zTpTdq1Mjk9mv5999/NxEREcbb29sULlzYPPzww2bdunU2fey5VYAxl6Z7f/PNN02FChVMwYIFTUBAgGnbtq3NbQCUw5TpuYnFmEuvd69evcxdd91lPDw8TNmyZU1UVJR1av2rfX4GDRpkJJmJEyfedPxZXnnlFSPJzJo1y6GvxbFjx0zPnj1NUFCQdb0mTZqYzz77zNrn008/NQ0bNjQlS5Y0np6eplKlSmbgwIEmJSXlmvuXtc0rbxVgjDH79u0zbdu2NcWKFTOFChUyDzzwgFm4cKFNn6u9vtfz2Wefmbp16xovLy9TtGhRU7NmTTNo0CBz5MgRa5+1a9ea+vXrGy8vLxMYGGgGDRpknVb+ylz4+eefzaOPPmqKFi1qihQpYkJDQ83HH39sXR4VFWWKFCmSLY6s74vrCQ4ONpGRkdnar/y+Mib33xXr1q0zdevWNR4eHtne9+3btxtJplq1ajZjv/POO0aS+c9//pMtlvT0dDN8+HDr5ysoKMhER0dbb6twvX0xJufPwoIFC0yBAgXMs88+m23q/yvHvfJWAQMGDDBlypQxXl5epkGDBmb9+vU5vmZZHn/8cSMpx1w3Jnevrb3fUQCMsRjDVfUAgDtLv3799OWXXyohIcF6WhyA3Hvqqae0detW7d2719mhAHcUrnkDANxRzp8/r//9739q06YNhRtwA44ePapFixbZ3GIDwK3BNW8AgDtCYmKili9frrlz5+rEiRPq06ePs0MCXMr+/fu1du1affHFFypYsKC6d+/u7JCAOw7FGwDgjrBjxw61b99epUuX1oQJE1S7dm1nhwS4lLi4OL344osqV66cpk+froCAAGeHBNxxuOYNAAAAAFwA17wBAAAAgAugeAMAAAAAF8A1b7mQmZmpI0eOqGjRorJYLM4OBwAAAICTGGN06tQpBQYGys3t1h4Lo3jLhSNHjigoKMjZYQAAAADIJw4fPqyyZcve0m1SvOVC0aJFJV16g3x8fJwcDQAAAABnSU1NVVBQkLVGuJUo3nIh61RJHx8fijcAAAAATrmciglLAAAAAMAFULwBAAAAgAugeAMAAAAAF0DxBgAAAAAugOINAAAAAFwAxRsAAAAAuACKNwAAAABwARRvAAAAAOACKN4AAAAAwAVQvAEAAACAC6B4AwAAAAAXQPEGAAAAAC6A4g0AAAAAXADFGwAAAAC4AIo3AAAAAHABBZwdAADkBxaLsyNwLmOcHQFuR+SVsyMAcLvhyBsAAAAAuACKNwAAAABwARRvAAAAAOACKN4AAAAAwAXkm+Jt1KhRslgs6tu3r7Xt/Pnz6tmzp0qWLClvb2+1adNGx44ds1nv0KFDioyMVOHChVW6dGkNHDhQFy9etOmzevVq1alTR56enqpcubJiYmJuwR4BAAAAgOPki+Lt119/1aeffqrQ0FCb9n79+umHH37QnDlzFBcXpyNHjqh169bW5RkZGYqMjNSFCxe0bt06TZ8+XTExMRoyZIi1z/79+xUZGamHH35Y8fHx6tu3r1566SUtXbr0lu0fAAAAANwsizHOncj29OnTqlOnjiZNmqR33nlHtWvX1rhx45SSkiI/Pz/NmjVLbdu2lSTt2rVL1apV0/r161W/fn0tXrxYLVq00JEjR+Tv7y9JmjJligYPHqzjx4/Lw8NDgwcP1qJFi7Rt2zbrNtu1a6fk5GQtWbIkVzGmpqbK19dXKSkp8vHxcfyLAMDpmNLc2RHgdkReOTsCAHnBmbWB04+89ezZU5GRkWratKlN+6ZNm5Senm7TXrVqVZUrV07r16+XJK1fv141a9a0Fm6SFBERodTUVG3fvt3a58qxIyIirGPkJC0tTampqTYPAAAAAHAmp96ke/bs2fr999/166+/ZluWkJAgDw8PFStWzKbd399fCQkJ1j6XF25Zy7OWXatPamqqzp07Jy8vr2zbHjlypIYPH37D+wUAAAAAjua0I2+HDx9Wnz59NHPmTBUqVMhZYeQoOjpaKSkp1sfhw4edHRIAAACAO5zTirdNmzYpMTFRderUUYECBVSgQAHFxcVpwoQJKlCggPz9/XXhwgUlJyfbrHfs2DEFBARIkgICArLNPpn1/Hp9fHx8cjzqJkmenp7y8fGxeQAAAACAMzmteGvSpIm2bt2q+Ph46+O+++5T+/btrf9fsGBBrVixwrrO7t27dejQIYWFhUmSwsLCtHXrViUmJlr7xMbGysfHRyEhIdY+l4+R1SdrDAAAAABwBU675q1o0aKqUaOGTVuRIkVUsmRJa3uXLl3Uv39/lShRQj4+Pnr11VcVFham+vXrS5KaNWumkJAQdejQQWPGjFFCQoLeeust9ezZU56enpKkl19+WRMnTtSgQYPUuXNnrVy5Ut98840WLVp0a3cYAAAAAG6CUycsuZ6xY8fKzc1Nbdq0UVpamiIiIjRp0iTrcnd3dy1cuFA9evRQWFiYihQpoqioKI0YMcLap0KFClq0aJH69eun8ePHq2zZsvriiy8UERHhjF0CAAAAgBvi9Pu8uQLu8wbc/rgflbMjwO2IvHJ2BADywh19nzcAAAAAwPVRvAEAAACAC6B4AwAAAAAXQPEGAAAAAC6A4g0AAAAAXADFGwAAAAC4AIo3AAAAAHAB+fom3bg67p3j7AgAAACAW4sjbwAAAADgAijeAAAAAMAFULwBAAAAgAugeAMAAAAAF0DxBgAAAAAugOINAAAAAFwAxRsAAAAAuACKNwAAAABwARRvAAAAAOACKN4AAAAAwAVQvAEAAACAC6B4AwAAAAAXQPEGAAAAAC6A4g0AAAAAXADFGwAAAAC4AIo3AAAAAHABFG8AAAAA4AIo3gAAAADABVC8AQAAAIALoHgDAAAAABdA8QYAAAAALoDiDQAAAABcAMUbAAAAALgAijcAAAAAcAEUbwAAAADgAijeAAAAAMAFOLV4mzx5skJDQ+Xj4yMfHx+FhYVp8eLF1uWNGzeWxWKxebz88ss2Yxw6dEiRkZEqXLiwSpcurYEDB+rixYs2fVavXq06derI09NTlStXVkxMzK3YPQAAAABwmALO3HjZsmU1atQo3X333TLGaPr06WrVqpU2b96s6tWrS5K6du2qESNGWNcpXLiw9f8zMjIUGRmpgIAArVu3TkePHlXHjh1VsGBBvffee5Kk/fv3KzIyUi+//LJmzpypFStW6KWXXlKZMmUUERFxa3cYAAAAAG6QxRhjnB3E5UqUKKH3339fXbp0UePGjVW7dm2NGzcux76LFy9WixYtdOTIEfn7+0uSpkyZosGDB+v48ePy8PDQ4MGDtWjRIm3bts26Xrt27ZScnKwlS5bkOG5aWprS0tKsz1NTUxUUFKSUlBT5+Pg4bmdvgsXi7AicK399anE7IKecHQFuR+SVsyMAkBdSU1Pl6+vrlNog31zzlpGRodmzZ+vMmTMKCwuzts+cOVOlSpVSjRo1FB0drbNnz1qXrV+/XjVr1rQWbpIUERGh1NRUbd++3dqnadOmNtuKiIjQ+vXrrxrLyJEj5evra30EBQU5ajcBAAAA4IY49bRJSdq6davCwsJ0/vx5eXt767vvvlNISIgk6fnnn1dwcLACAwO1ZcsWDR48WLt379a3334rSUpISLAp3CRZnyckJFyzT2pqqs6dOycvL69sMUVHR6t///7W51lH3gAAAADAWZxevFWpUkXx8fFKSUnR3LlzFRUVpbi4OIWEhKhbt27WfjVr1lSZMmXUpEkT7du3T5UqVcqzmDw9PeXp6Zln4wMAAACAvZx+2qSHh4cqV66sunXrauTIkapVq5bGjx+fY9969epJkvbu3StJCggI0LFjx2z6ZD0PCAi4Zh8fH58cj7oBAAAAQH7k9OLtSpmZmTaThVwuPj5eklSmTBlJUlhYmLZu3arExERrn9jYWPn4+FhPvQwLC9OKFStsxomNjbW5rg4AAAAA8junnjYZHR2t5s2bq1y5cjp16pRmzZql1atXa+nSpdq3b59mzZqlxx9/XCVLltSWLVvUr18/NWzYUKGhoZKkZs2aKSQkRB06dNCYMWOUkJCgt956Sz179rSe9vjyyy9r4sSJGjRokDp37qyVK1fqm2++0aJFi5y56wAAAABgF6cWb4mJierYsaOOHj0qX19fhYaGaunSpXr00Ud1+PBhLV++XOPGjdOZM2cUFBSkNm3a6K233rKu7+7uroULF6pHjx4KCwtTkSJFFBUVZXNfuAoVKmjRokXq16+fxo8fr7Jly+qLL77gHm8AAAAAXEq+u89bfuTMezlcDffOcXYEuN2QU86OALcj8srZEQDIC9znDQAAAABwTRRvAAAAAOACKN4AAAAAwAVQvAEAAACAC6B4AwAAAAAXQPEGAAAAAC6A4g0AAAAAXADFGwAAAAC4AIo3AAAAAHABFG8AAAAA4AIo3gAAAADABVC8AQAAAIALoHgDAAAAABdA8QYAAAAALoDiDQAAAABcAMUbAAAAALgAijcAAAAAcAEUbwAAAADgAijeAAAAAMAFULwBAAAAgAugeAMAAAAAF0DxBgAAAAAugOINAAAAAFwAxRsAAAAAuACKNwAAAABwARRvAAAAAOACKN4AAAAAwAVQvAEAAACAC6B4AwAAAAAXQPEGAAAAAC6A4g0AAAAAXADFGwAAAAC4AIo3AAAAAHABTi3eJk+erNDQUPn4+MjHx0dhYWFavHixdfn58+fVs2dPlSxZUt7e3mrTpo2OHTtmM8ahQ4cUGRmpwoULq3Tp0ho4cKAuXrxo02f16tWqU6eOPD09VblyZcXExNyK3QMAAAAAh7G7eDt37pzOnj1rfX7w4EGNGzdOy5Yts3vjZcuW1ahRo7Rp0yb99ttveuSRR9SqVStt375dktSvXz/98MMPmjNnjuLi4nTkyBG1bt3aun5GRoYiIyN14cIFrVu3TtOnT1dMTIyGDBli7bN//35FRkbq4YcfVnx8vPr27auXXnpJS5cutTteAAAAAHAWizHG2LNCs2bN1Lp1a7388stKTk5W1apVVbBgQf3777/66KOP1KNHj5sKqESJEnr//ffVtm1b+fn5adasWWrbtq0kadeuXapWrZrWr1+v+vXra/HixWrRooWOHDkif39/SdKUKVM0ePBgHT9+XB4eHho8eLAWLVqkbdu2WbfRrl07JScna8mSJbmKKTU1Vb6+vkpJSZGPj89N7Z+jWCzOjsC57PvUAtdHTjk7AtyOyCtnRwAgLzizNrD7yNvvv/+u8PBwSdLcuXPl7++vgwcPasaMGZowYcINB5KRkaHZs2frzJkzCgsL06ZNm5Senq6mTZta+1StWlXlypXT+vXrJUnr169XzZo1rYWbJEVERCg1NdV69G79+vU2Y2T1yRojJ2lpaUpNTbV5AAAAAIAz2V28nT17VkWLFpUkLVu2TK1bt5abm5vq16+vgwcP2h3A1q1b5e3tLU9PT7388sv67rvvFBISooSEBHl4eKhYsWI2/f39/ZWQkCBJSkhIsCncspZnLbtWn9TUVJ07dy7HmEaOHClfX1/rIygoyO79AgAAAABHsrt4q1y5subPn6/Dhw9r6dKlatasmSQpMTHxhg4bVqlSRfHx8dqwYYN69OihqKgo7dixw+5xHCk6OlopKSnWx+HDh50aDwAAAADYXbwNGTJEr732msqXL68HHnhAYWFhki4dhbv33nvtDsDDw0OVK1dW3bp1NXLkSNWqVUvjx49XQECALly4oOTkZJv+x44dU0BAgCQpICAg2+yTWc+v18fHx0deXl45xuTp6WmdATPrAQAAAADOZHfx1rZtWx06dEi//fabzYyNTZo00dixY286oMzMTKWlpalu3boqWLCgVqxYYV22e/duHTp0yFowhoWFaevWrUpMTLT2iY2NlY+Pj0JCQqx9Lh8jq0/WGAAAAADgCgrcyEoBAQE6ffq0YmNj1bBhQ3l5een++++Xxc5ppaKjo9W8eXOVK1dOp06d0qxZs7R69WotXbpUvr6+6tKli/r3768SJUrIx8dHr776qsLCwlS/fn1Jl2a+DAkJUYcOHTRmzBglJCTorbfeUs+ePeXp6SlJevnllzVx4kQNGjRInTt31sqVK/XNN99o0aJFN7LrAAAAAOAUdhdvJ06c0DPPPKNVq1bJYrFoz549qlixorp06aLixYvrww8/zPVYiYmJ6tixo44ePSpfX1+FhoZq6dKlevTRRyVJY8eOlZubm9q0aaO0tDRFRERo0qRJ1vXd3d21cOFC9ejRQ2FhYSpSpIiioqI0YsQIa58KFSpo0aJF6tevn8aPH6+yZcvqiy++UEREhL27DgAAAABOY/d93jp27KjExER98cUXqlatmv744w9VrFhRS5cuVf/+/a1T9N9OuM9b/sO9c+Bo5JSzI8DtiLxydgQA8oIzawO7j7wtW7ZMS5cuVdmyZW3a77777hu6VQAAAAAA4PrsnrDkzJkzKly4cLb2pKQk63VmAAAAAADHsrt4Cw8P14wZM6zPLRaLMjMzNWbMGD388MMODQ4AAAAAcIndp02OGTNGTZo00W+//aYLFy5o0KBB2r59u5KSkrR27dq8iBEAAAAA7nh2H3mrUaOG/vzzTz300ENq1aqVzpw5o9atW2vz5s2qVKlSXsQIAAAAAHc8u2ebvBMx22T+w6cWjkZOOTsC3I7IK2dHACAv5PvZJrds2ZLrAUNDQ284GAAAAABAznJVvNWuXVsWi0XXO0hnsViUkZHhkMAAAAAAAP8vV8Xb/v378zoOAAAAAMA15Kp4Cw4Ozus4AAAAAADXYPdskyNHjtTUqVOztU+dOlWjR492SFAAAAAAAFt2F2+ffvqpqlatmq29evXqmjJlikOCAgAAAADYsrt4S0hIUJkyZbK1+/n56ejRow4JCgAAAABgy+7iLSgoSGvXrs3WvnbtWgUGBjokKAAAAACArVxNWHK5rl27qm/fvkpPT9cjjzwiSVqxYoUGDRqkAQMGODxAAAAAAMANFG8DBw7UiRMn9Morr+jChQuSpEKFCmnw4MGKjo52eIAAAAAAAMlirnfn7as4ffq0du7cKS8vL919993y9PR0dGz5Rmpqqnx9fZWSkiIfHx9nhyNJslicHYFz3dinFrg6csrZEeB2RF45OwIAecGZtYHd17xNmzZN586dk7e3t+6//37VqFHjti7cAAAAACA/sLt4e/311+Xv768uXbpo3bp1eRETAAAAAOAKdhdv//zzj6ZPn65///1XjRs3VtWqVTV69GglJCTkRXwAAAAAAN1A8VagQAE99dRTWrBggQ4fPqyuXbtq5syZKleunJ544gktWLBAmZmZeRErAAAAANyx7C7eLufv76+HHnpIYWFhcnNz09atWxUVFaVKlSpp9erVDgoRAAAAAHBDxduxY8f0wQcfqHr16mrcuLFSU1O1cOFC7d+/X//884+eeeYZRUVFOTpWAAAAALhj2X2rgJYtW2rp0qW655579NJLL6ljx44qUaKETZ/ExEQFBATcNqdPcquA/Ifpl+Fo5JSzI8DtiLxydgQA8oIzawO7b9JdunRpxcXFKSws7Kp9/Pz8tH///psKDAAAAADw/274Jt13Eo685T98auFo5JSzI8DtiLxydgQA8oJL3aS7d+/emjBhQrb2iRMnqm/fvo6ICQAAAABwBbuLt3nz5qlBgwbZ2h988EHNnTvXIUEBAAAAAGzZXbydOHFCvr6+2dp9fHz077//OiQoAAAAAIAtu4u3ypUra8mSJdnaFy9erIoVKzokKAAAAACALbtnm+zfv7969eql48eP65FHHpEkrVixQh9++KHGjRvn6PgAAAAAALqB4q1z585KS0vTu+++q7fffluSVL58eU2ePFkdO3Z0eIAAAAAAgJu8VcDx48fl5eUlb29vR8aU73CrgPyH6ZfhaOSUsyPA7Yi8cnYEAPKCS92k+3J+fn6OigMAAAAAcA12T1jiSCNHjtT999+vokWLqnTp0nryySe1e/dumz6NGzeWxWKxebz88ss2fQ4dOqTIyEgVLlxYpUuX1sCBA3Xx4kWbPqtXr1adOnXk6empypUrKyYmJq93DwAAAAAcxqnFW1xcnHr27KlffvlFsbGxSk9PV7NmzXTmzBmbfl27dtXRo0etjzFjxliXZWRkKDIyUhcuXNC6des0ffp0xcTEaMiQIdY++/fvV2RkpB5++GHFx8erb9++eumll7R06dJbtq8AAAAAcDNu6po3Rzt+/LhKly6tuLg4NWzYUNKlI2+1a9e+6kyWixcvVosWLXTkyBH5+/tLkqZMmaLBgwfr+PHj8vDw0ODBg7Vo0SJt27bNul67du2UnJyc420PrsQ1b/lP/vnU4nZBTjk7AtyOyCtnRwAgLzizNrD7yNvff/991WW//PLLTQWTkpIiSSpRooRN+8yZM1WqVCnVqFFD0dHROnv2rHXZ+vXrVbNmTWvhJkkRERFKTU3V9u3brX2aNm1qM2ZERITWr1+fYxxpaWlKTU21eQAAAACAM9ldvDVr1kxJSUnZ2teuXavHHnvshgPJzMxU37591aBBA9WoUcPa/vzzz+t///ufVq1apejoaP33v//VCy+8YF2ekJBgU7hJsj5PSEi4Zp/U1FSdO3cuWywjR46Ur6+v9REUFHTD+wUAAAAAjmD3bJP169dXs2bNtGrVKhUtWlSStGbNGrVs2VLDhg274UB69uypbdu26eeff7Zp79atm/X/a9asqTJlyqhJkybat2+fKlWqdMPbu5bo6Gj179/f+jw1NZUCDgAAAIBT2X3k7YsvvlC5cuXUsmVLpaWladWqVYqMjNSIESPUr1+/GwqiV69eWrhwoVatWqWyZctes2+9evUkSXv37pUkBQQE6NixYzZ9sp4HBARcs4+Pj4+8vLyybcPT01M+Pj42DwAAAABwJruLNzc3N82ePVsFCxbUI488oieeeEIjR45Unz597N64MUa9evXSd999p5UrV6pChQrXXSc+Pl6SVKZMGUlSWFiYtm7dqsTERGuf2NhY+fj4KCQkxNpnxYoVNuPExsYqLCzM7pgBAAAAwBlyNdvkli1bsrWdOnVKzz33nCIjI9WjRw9re2hoaK43/sorr2jWrFlasGCBqlSpYm339fWVl5eX9u3bp1mzZunxxx9XyZIltWXLFvXr109ly5ZVXFycpEu3Cqhdu7YCAwM1ZswYJSQkqEOHDnrppZf03nvvSbp0q4AaNWqoZ8+e6ty5s1auXKnevXtr0aJFioiIuG6czDaZ/zCDFxyNnHJ2BLgdkVfOjgBAXnBmbZCr4s3NzU0Wi0WXd738edb/WywWZWRk5H7jV/lWnzZtmjp16qTDhw/rhRde0LZt23TmzBkFBQXpqaee0ltvvWXzQh08eFA9evTQ6tWrVaRIEUVFRWnUqFEqUOD/L+lbvXq1+vXrpx07dqhs2bL6z3/+o06dOuUqToq3/Id/EOFo5JSzI8DtiLxydgQA8kK+L94OHjyY6wGDg4NvKqD8iOIt/+EfRDgaOeXsCHA7Iq+cHQGAvODM2iBXs03ejgUZAAAAALgSuycsGTlypKZOnZqtferUqRo9erRDggIAAAAA2LK7ePv0009VtWrVbO3Vq1fXlClTHBIUAAAAAMCW3cVbQkKCdZr+y/n5+eno0aMOCQoAAAAAYMvu4i0oKEhr167N1r527VoFBgY6JCgAAAAAgK1cTVhyua5du6pv375KT0/XI488IklasWKFBg0apAEDBjg8QAAAAADADRRvAwcO1IkTJ/TKK6/owoULkqRChQpp8ODBio6OdniAAAAAAIBc3uctJ6dPn9bOnTvl5eWlu+++W56eno6OLd/gPm/5D/fOgaORU86OALcj8srZEQDIC/n+Pm858fb2tk5ccjsXbgAAAACQH9g9YUlmZqZGjBghX19fBQcHKzg4WMWKFdPbb7+tzMzMvIgRAAAAAO54dh95e/PNN/Xll19q1KhRatCggSTp559/1rBhw3T+/Hm9++67Dg8SAAAAAO50dl/zFhgYqClTpuiJJ56waV+wYIFeeeUV/fPPPw4NMD/gmrf8h+sI4GjklLMjwO2IvHJ2BADygjNrA7tPm0xKSlLVqlWztVetWlVJSUkOCQoAAAAAYMvu4q1WrVqaOHFitvaJEyeqVq1aDgkKAAAAAGDL7mvexowZo8jISC1fvlxhYWGSpPXr1+vw4cP68ccfHR4gAAAAAOAGjrw1atRIf/75p5566iklJycrOTlZrVu31u7duxUeHp4XMQIAAADAHe+Gb9J9J2HCkvyHTy0cjZxydgS4HZFXzo4AQF7I9zfp3rJlS64HDA0NveFgAAAAAAA5y1XxVrt2bVksFl3vIJ3FYlFGRoZDAgMAAAAA/L9cFW/79+/P6zgAAAAAANeQq+ItODg4r+MAAAAAAFyD3bNNjhw5UlOnTs3WPnXqVI0ePdohQQEAAAAAbNldvH366aeqWrVqtvbq1atrypQpDgkKAAAAAGDL7uItISFBZcqUydbu5+eno0ePOiQoAAAAAIAtu4u3oKAgrV27Nlv72rVrFRgY6JCgAAAAAAC2cjVhyeW6du2qvn37Kj09XY888ogkacWKFRo0aJAGDBjg8AABAAAAADdQvA0cOFAnTpzQK6+8ogsXLkiSChUqpMGDBys6OtrhAQIAAAAAJIu53p23r+L06dPauXOnvLy8dPfdd8vT09PRseUbqamp8vX1VUpKinx8fJwdjiTJYnF2BM51Y59a4OrIKWdHgNsReeXsCADkBWfWBnYfecvi7e2t+++/35GxAAAAAACuwu4JSwAAAAAAtx7FGwAAAAC4AIo3AAAAAHABuSre6tSpo5MnT0qSRowYobNnz+ZpUAAAAAAAW7kq3nbu3KkzZ85IkoYPH67Tp0/naVAAAAAAAFu5Kt5q166tF198UcOHD5cxRh988IFGjBiR48MeI0eO1P3336+iRYuqdOnSevLJJ7V7926bPufPn1fPnj1VsmRJeXt7q02bNjp27JhNn0OHDikyMlKFCxdW6dKlNXDgQF28eNGmz+rVq1WnTh15enqqcuXKiomJsStWAAAAAHCmXN0qICYmRkOHDtXChQtlsVi0ePFiFSiQfVWLxaIhQ4bkeuNxcXHq2bOn7r//fl28eFFvvPGGmjVrph07dqhIkSKSpH79+mnRokWaM2eOfH191atXL7Vu3Vpr166VJGVkZCgyMlIBAQFat26djh49qo4dO6pgwYJ67733JEn79+9XZGSkXn75Zc2cOVMrVqzQSy+9pDJlyigiIiLX8QIAAACAs9h9k243NzclJCSodOnSDg/m+PHjKl26tOLi4tSwYUOlpKTIz89Ps2bNUtu2bSVJu3btUrVq1bR+/XrVr19fixcvVosWLXTkyBH5+/tLkqZMmaLBgwfr+PHj8vDw0ODBg7Vo0SJt27bNuq127dopOTlZS5YsuW5c3KQ7/+HGp3A0csrZEeB2RF45OwIAecGZtYHds01mZmbmSeEmSSkpKZKkEiVKSJI2bdqk9PR0NW3a1NqnatWqKleunNavXy9JWr9+vWrWrGkt3CQpIiJCqamp2r59u7XP5WNk9cka40ppaWlKTU21eQAAAACAM93QrQL27dunV199VU2bNlXTpk3Vu3dv7du376YCyczMVN++fdWgQQPVqFFDkpSQkCAPDw8VK1bMpq+/v78SEhKsfS4v3LKWZy27Vp/U1FSdO3cuWywjR46Ur6+v9REUFHRT+wYAAAAAN8vu4m3p0qUKCQnRxo0bFRoaqtDQUG3YsEHVq1dXbGzsDQfSs2dPbdu2TbNnz77hMRwlOjpaKSkp1sfhw4edHRIAAACAO1yuJiy53Ouvv65+/fpp1KhR2doHDx6sRx991O4gevXqpYULF2rNmjUqW7astT0gIEAXLlxQcnKyzdG3Y8eOKSAgwNpn48aNNuNlzUZ5eZ8rZ6g8duyYfHx85OXllS0eT09PeXp62r0fAAAAAJBX7D7ytnPnTnXp0iVbe+fOnbVjxw67xjLGqFevXvruu++0cuVKVahQwWZ53bp1VbBgQa1YscLatnv3bh06dEhhYWGSpLCwMG3dulWJiYnWPrGxsfLx8VFISIi1z+VjZPXJGgMAAAAA8ju7izc/Pz/Fx8dna4+Pj7d7IpOePXvqf//7n2bNmqWiRYsqISFBCQkJ1uvQfH191aVLF/Xv31+rVq3Spk2b9OKLLyosLEz169eXJDVr1kwhISHq0KGD/vjjDy1dulRvvfWWevbsaT169vLLL+uvv/7SoEGDtGvXLk2aNEnffPON+vXrZ+/uAwAAAIBT2H3aZNeuXdWtWzf99ddfevDBByVJa9eu1ejRo9W/f3+7xpo8ebIkqXHjxjbt06ZNU6dOnSRJY8eOlZubm9q0aaO0tDRFRERo0qRJ1r7u7u5auHChevToobCwMBUpUkRRUVE2NwyvUKGCFi1apH79+mn8+PEqW7asvvjiC+7xBgAAAMBl2H2fN2OMxo0bpw8//FBHjhyRJAUGBmrgwIHq3bu3LLfhTV24z1v+w71z4GjklLMjwO2IvHJ2BADygjNrA7uLt8udOnVKklS0aFGHBZQfUbzlP/yDCEcjp5wdAW5H5JWzIwCQF5xZG9h92uTlbveiDQAAAADyixu6STcAAAAA4NaieAMAAAAAF0DxBgAAAAAuwK7iLT09XU2aNNGePXvyKh4AAAAAQA7sKt4KFiyoLVu25FUsAAAAAICrsPu0yRdeeEFffvllXsQCAAAAALgKu28VcPHiRU2dOlXLly9X3bp1VaRIEZvlH330kcOCAwAAAABcYnfxtm3bNtWpU0eS9Oeff9oss9zpd+MEAAAAgDxid/G2atWqvIgDAAAAAHANN3yrgL1792rp0qU6d+6cJMkY47CgAAAAAAC27C7eTpw4oSZNmuiee+7R448/rqNHj0qSunTpogEDBjg8QAAAAADADRRv/fr1U8GCBXXo0CEVLlzY2v7ss89qyZIlDg0OAAAAAHCJ3de8LVu2TEuXLlXZsmVt2u+++24dPHjQYYEBAAAAAP6f3Ufezpw5Y3PELUtSUpI8PT0dEhQAAAAAwJbdxVt4eLhmzJhhfW6xWJSZmakxY8bo4YcfdmhwAAAAAIBL7D5tcsyYMWrSpIl+++03XbhwQYMGDdL27duVlJSktWvX5kWMAAAAAHDHs/vIW40aNfTnn3/qoYceUqtWrXTmzBm1bt1amzdvVqVKlfIiRgAAAAC441kMN2i7rtTUVPn6+iolJUU+Pj7ODkeSZLE4OwLn4lMLRyOnnB0BbkfklbMjAJAXnFkb2H3apCSdPHlSX375pXbu3ClJCgkJ0YsvvqgSJUo4NDgAAAAAwCV2nza5Zs0alS9fXhMmTNDJkyd18uRJTZgwQRUqVNCaNWvyIkYAAAAAuOPZfdpkzZo1FRYWpsmTJ8vd3V2SlJGRoVdeeUXr1q3T1q1b8yRQZ+K0yfyHU1HgaOSUsyPA7Yi8cnYEAPKCM2sDu4+87d27VwMGDLAWbpLk7u6u/v37a+/evQ4NDgAAAABwid3FW506dazXul1u586dqlWrlkOCAgAAAADYytWEJVu2bLH+f+/evdWnTx/t3btX9evXlyT98ssv+uSTTzRq1Ki8iRIAAAAA7nC5uubNzc1NFotF1+tqsViUkZHhsODyC655y3+4jgCORk45OwLcjsgrZ0cAIC/k+1sF7N+/P6/jAAAAAABcQ66Kt+Dg4LyOAwAAAABwDTd0k+4jR47o559/VmJiojIzM22W9e7d2yGBAQAAAAD+n93FW0xMjLp37y4PDw+VLFlSlstOaLdYLBRvAAAAAJAH7C7e/vOf/2jIkCGKjo6Wm5vddxoAAAAAANwAu6uvs2fPql27dhRuAAAAAHAL2V2BdenSRXPmzMmLWAAAAAAAV2F38TZy5EjFxcWpcePGevXVV9W/f3+bhz3WrFmjli1bKjAwUBaLRfPnz7dZ3qlTJ1ksFpvHY489ZtMnKSlJ7du3l4+Pj4oVK6YuXbro9OnTNn22bNmi8PBwFSpUSEFBQRozZoy9uw0AAAAATmX3NW8jR47U0qVLVaVKFUnKNmGJPc6cOaNatWqpc+fOat26dY59HnvsMU2bNs363NPT02Z5+/btdfToUcXGxio9PV0vvviiunXrplmzZkm6dBO9Zs2aqWnTppoyZYq2bt2qzp07q1ixYurWrZtd8QIAAACAs9hdvH344YeaOnWqOnXqdNMbb968uZo3b37NPp6engoICMhx2c6dO7VkyRL9+uuvuu+++yRJH3/8sR5//HF98MEHCgwM1MyZM3XhwgVNnTpVHh4eql69uuLj4/XRRx9dtXhLS0tTWlqa9XlqauoN7iEAAAAAOIbdp016enqqQYMGeRFLjlavXq3SpUurSpUq6tGjh06cOGFdtn79ehUrVsxauElS06ZN5ebmpg0bNlj7NGzYUB4eHtY+ERER2r17t06ePJnjNkeOHClfX1/rIygoKI/2DgAAAAByx+7irU+fPvr444/zIpZsHnvsMc2YMUMrVqzQ6NGjFRcXp+bNmysjI0OSlJCQoNKlS9usU6BAAZUoUUIJCQnWPv7+/jZ9sp5n9blSdHS0UlJSrI/Dhw87etcAAAAAwC52nza5ceNGrVy5UgsXLlT16tVVsGBBm+Xffvutw4Jr166d9f9r1qyp0NBQVapUSatXr1aTJk0ctp0reXp6Zru2DgAAAACcye7irVixYledXCSvVaxYUaVKldLevXvVpEkTBQQEKDEx0abPxYsXlZSUZL1OLiAgQMeOHbPpk/X8atfSAQAAAEB+Y3fxdvnMj7fa33//rRMnTqhMmTKSpLCwMCUnJ2vTpk2qW7euJGnlypXKzMxUvXr1rH3efPNNpaenW48SxsbGqkqVKipevLhzdgQAAAAA7GT3NW+OdPr0acXHxys+Pl6StH//fsXHx+vQoUM6ffq0Bg4cqF9++UUHDhzQihUr1KpVK1WuXFkRERGSpGrVqumxxx5T165dtXHjRq1du1a9evVSu3btFBgYKEl6/vnn5eHhoS5dumj79u36+uuvNX78eLvvSQcAAAAAzmQxxhh7VqhQocI17+f2119/5Xqs1atX6+GHH87WHhUVpcmTJ+vJJ5/U5s2blZycrMDAQDVr1kxvv/22zQQkSUlJ6tWrl3744Qe5ubmpTZs2mjBhgry9va19tmzZop49e+rXX39VqVKl9Oqrr2rw4MG5jjM1NVW+vr5KSUmRj49PrtfLS3beUu+2Y9+nFrg+csrZEeB2RF45OwIAecGZtYHdxdv48eNtnqenp2vz5s1asmSJBg4cqNdff92hAeYHFG/5D/8gwtHIKWdHgNsReeXsCADkBWfWBnZf89anT58c2z/55BP99ttvNx0QAAAAACA7h13z1rx5c82bN89RwwEAAAAALuOw4m3u3LkqUaKEo4YDAAAAAFzG7tMm7733XpsJS4wxSkhI0PHjxzVp0iSHBgcAAAAAuMTu4u3JJ5+0ee7m5iY/Pz81btxYVatWdVRcAAAAAIDL2D3b5J2I2SbzHz61cDRyytkR4HZEXjk7AgB5wZm1gVNv0g0AAAAAyJ1cnzbp5uZ2zZtzS5LFYtHFixdvOigAAAAAgK1cF2/ffffdVZetX79eEyZMUGZmpkOCAgAAAADYynXx1qpVq2xtu3fv1uuvv64ffvhB7du314gRIxwaHAAAAADgkhu65u3IkSPq2rWratasqYsXLyo+Pl7Tp09XcHCwo+MDAAAAAMjO4i0lJUWDBw9W5cqVtX37dq1YsUI//PCDatSokVfxAQAAAABkx2mTY8aM0ejRoxUQEKCvvvoqx9MoAQAAAAB5I9f3eXNzc5OXl5eaNm0qd3f3q/b79ttvHRZcfsF93vIf7p0DRyOnnB0BbkfklbMjAJAXnFkb5PrIW8eOHa97qwAAAAAAQN7IdfEWExOTh2EAAAAAAK7lhmabBAAAAADcWhRvAAAAAOACKN4AAAAAwAVQvAEAAACAC6B4AwAAAAAXQPEGAAAAAC6A4g0AAAAAXADFGwAAAAC4AIo3AAAAAHABFG8AAAAA4AIo3gAAAADABVC8AQAAAIALoHgDAAAAABdA8QYAAAAALoDiDQAAAABcAMUbAAAAALgAijcAAAAAcAFOLd7WrFmjli1bKjAwUBaLRfPnz7dZbozRkCFDVKZMGXl5ealp06bas2ePTZ+kpCS1b99ePj4+KlasmLp06aLTp0/b9NmyZYvCw8NVqFAhBQUFacyYMXm9awAAAADgUE4t3s6cOaNatWrpk08+yXH5mDFjNGHCBE2ZMkUbNmxQkSJFFBERofPnz1v7tG/fXtu3b1dsbKwWLlyoNWvWqFu3btblqampatasmYKDg7Vp0ya9//77GjZsmD777LM83z8AAAAAcBSLMcY4OwhJslgs+u677/Tkk09KunTULTAwUAMGDNBrr70mSUpJSZG/v79iYmLUrl077dy5UyEhIfr111913333SZKWLFmixx9/XH///bcCAwM1efJkvfnmm0pISJCHh4ck6fXXX9f8+fO1a9euXMWWmpoqX19fpaSkyMfHx/E7fwMsFmdH4Fz541OL2wk55ewIcDsir5wdAYC84MzaIN9e87Z//34lJCSoadOm1jZfX1/Vq1dP69evlyStX79exYoVsxZuktS0aVO5ublpw4YN1j4NGza0Fm6SFBERod27d+vkyZM5bjstLU2pqak2DwAAAABwpnxbvCUkJEiS/P39bdr9/f2tyxISElS6dGmb5QUKFFCJEiVs+uQ0xuXbuNLIkSPl6+trfQQFBd38DgEAAADATci3xZszRUdHKyUlxfo4fPiws0MCAAAAcIfLt8VbQECAJOnYsWM27ceOHbMuCwgIUGJios3yixcvKikpyaZPTmNcvo0reXp6ysfHx+YBAAAAAM6Ub4u3ChUqKCAgQCtWrLC2paamasOGDQoLC5MkhYWFKTk5WZs2bbL2WblypTIzM1WvXj1rnzVr1ig9Pd3aJzY2VlWqVFHx4sVv0d4AAAAAwM1xavF2+vRpxcfHKz4+XtKlSUri4+N16NAhWSwW9e3bV++8846+//57bd26VR07dlRgYKB1Rspq1arpscceU9euXbVx40atXbtWvXr1Urt27RQYGChJev755+Xh4aEuXbpo+/bt+vrrrzV+/Hj179/fSXsNAAAAAPZz6q0CVq9erYcffjhbe1RUlGJiYmSM0dChQ/XZZ58pOTlZDz30kCZNmqR77rnH2jcpKUm9evXSDz/8IDc3N7Vp00YTJkyQt7e3tc+WLVvUs2dP/frrrypVqpReffVVDR48ONdxcquA/Ifpl+Fo5JSzI8DtiLxydgQA8oIza4N8c5+3/IziLf/hUwtHI6ecHQFuR+SVsyMAkBe4zxsAAAAA4Joo3gAAAADABVC8AQAAAIALoHgDAAAAABdA8QYAAAAALoDiDQAAAABcAMUbAAAAALgAijcAAAAAcAEUbwAAAADgAijeAAAAAMAFULwBAAAAgAugeAMAAAAAF0DxBgAAAAAugOINAAAAAFwAxRsAAAAAuACKNwAAAABwARRvAAAAAOACKN4AAAAAwAVQvAEAAACAC6B4AwAAAAAXQPEGAAAAAC6A4g0AAAAAXADFGwAAAAC4AIo3AAAAAHABFG8AAAAA4AIo3gAAAADABVC8AQAAAIALoHgDAAAAABdA8QYAAAAALoDiDQAAAABcAMUbAAAAALgAijcAAAAAcAEUbwAAAADgAijeAAAAAMAF5OvibdiwYbJYLDaPqlWrWpefP39ePXv2VMmSJeXt7a02bdro2LFjNmMcOnRIkZGRKly4sEqXLq2BAwfq4sWLt3pXAAAAAOCmFHB2ANdTvXp1LV++3Pq8QIH/D7lfv35atGiR5syZI19fX/Xq1UutW7fW2rVrJUkZGRmKjIxUQECA1q1bp6NHj6pjx44qWLCg3nvvvVu+LwAAAABwo/J98VagQAEFBARka09JSdGXX36pWbNm6ZFHHpEkTZs2TdWqVdMvv/yi+vXra9myZdqxY4eWL18uf39/1a5dW2+//bYGDx6sYcOGycPD41bvDgAAAADckHx92qQk7dmzR4GBgapYsaLat2+vQ4cOSZI2bdqk9PR0NW3a1Nq3atWqKleunNavXy9JWr9+vWrWrCl/f39rn4iICKWmpmr79u1X3WZaWppSU1NtHgAAAADgTPm6eKtXr55iYmK0ZMkSTZ48Wfv371d4eLhOnTqlhIQEeXh4qFixYjbr+Pv7KyEhQZKUkJBgU7hlLc9adjUjR46Ur6+v9REUFOTYHQMAAAAAO+Xr0yabN29u/f/Q0FDVq1dPwcHB+uabb+Tl5ZVn242Ojlb//v2tz1NTUyngAAAAADhVvj7ydqVixYrpnnvu0d69exUQEKALFy4oOTnZps+xY8es18gFBARkm30y63lO19Fl8fT0lI+Pj80DAAAAAJzJpYq306dPa9++fSpTpozq1q2rggULasWKFdblu3fv1qFDhxQWFiZJCgsL09atW5WYmGjtExsbKx8fH4WEhNzy+AEAAADgRuXr0yZfe+01tWzZUsHBwTpy5IiGDh0qd3d3Pffcc/L19VWXLl3Uv39/lShRQj4+Pnr11VcVFham+vXrS5KaNWumkJAQdejQQWPGjFFCQoLeeust9ezZU56enk7eOwAAAADIvXxdvP3999967rnndOLECfn5+emhhx7SL7/8Ij8/P0nS2LFj5ebmpjZt2igtLU0RERGaNGmSdX13d3ctXLhQPXr0UFhYmIoUKaKoqCiNGDHCWbsEAAAAADfEYowxzg4iv0tNTZWvr69SUlLyzfVvFouzI3AuPrVwNHLK2RHgdkReOTsCAHnBmbWBS13zBgAAAAB3Koo3AAAAAHABFG8AAAAA4AIo3gAAAADABVC8AQAAAIALoHgDAAAAABdA8QYAAAAALoDiDQAAAABcAMUbAAAAALgAijcAAAAAcAEUbwAAAADgAijeAAAAAMAFULwBAAAAgAugeAMAAAAAF0DxBgAAAAAugOINAAAAAFwAxRsAAAAAuACKNwAAAABwARRvAAAAAOACKN4AAAAAwAVQvAEAAACAC6B4AwAAAAAXQPEGAAAAAC6A4g0AAAAAXADFGwAAAAC4AIo3AAAAAHABFG8AAAAA4AIo3gAAAADABVC8AQAAAIALoHgDAAAAABdA8QYAAAAALoDiDQAAAABcQAFnBwAAAADg+iwWZ0fgXMY4OwLn48gbAAAAALiAO6p4++STT1S+fHkVKlRI9erV08aNG50dEgAAAADkyh1TvH399dfq37+/hg4dqt9//121atVSRESEEhMTnR0aAAAAAFzXHVO8ffTRR+ratatefPFFhYSEaMqUKSpcuLCmTp3q7NAAAAAA4LruiAlLLly4oE2bNik6Otra5ubmpqZNm2r9+vXZ+qelpSktLc36PCUlRZKUmpqa98EiV3grAMcipwDHI68Ax8ovOZVVExgnzKByRxRv//77rzIyMuTv72/T7u/vr127dmXrP3LkSA0fPjxbe1BQUJ7FCPv4+jo7AuD2Qk4BjkdeAY6V33Lq1KlT8r3FQd0RxZu9oqOj1b9/f+vzzMxMJSUlqWTJkrLc6XO06tKvDUFBQTp8+LB8fHycHQ7g8sgpwPHIK8CxyKn/Z4zRqVOnFBgYeMu3fUcUb6VKlZK7u7uOHTtm037s2DEFBARk6+/p6SlPT0+btmLFiuVliC7Jx8fnjk9ewJHIKcDxyCvAscipS271Ebcsd8SEJR4eHqpbt65WrFhhbcvMzNSKFSsUFhbmxMgAAAAAIHfuiCNvktS/f39FRUXpvvvu0wMPPKBx48bpzJkzevHFF50dGgAAAABc1x1TvD377LM6fvy4hgwZooSEBNWuXVtLlizJNokJrs/T01NDhw7NdmopgBtDTgGOR14BjkVO5Q8W44w5LgEAAAAAdrkjrnkDAAAAAFdH8QYAAAAALoDiDQAAAABcAMVbHipfvrzGjRvn7DBczoEDB2SxWBQfH5/n2+I9cj28ZzeGvMLV8H7dGHIK18J7dmPIq1wwt7moqCgjyXTv3j3bsldeecVIMlFRUbkaa//+/UaS2bx5c676JyYmmjNnzuSqb4sWLUxERESOy9asWWMkmT/++CNXY13NqlWrjCRz8uTJmxrnSmfPnjXFixc3JUuWNOfPn7dr3aioKNOqVSubtosXL5qjR4+a9PR0h8U4bdo04+vrm63dnvfIUSZOnGiCg4ONp6eneeCBB8yGDRtu6fYdgbz6f+SVb7b2W51XcXFxpkWLFqZMmTJGkvnuu+9u2bYdhZz6f+SUb7b2W51T7733nrnvvvuMt7e38fPzM61atTK7du26Zdt3FPLq/5FXvtnab3VeTZo0ydSsWdMULVrUFC1a1NSvX9/8+OOPdo9zRxx5CwoK0uzZs3Xu3Dlr2/nz5zVr1iyVK1fO4du7cOGCJMnPz0+FCxfO1TpdunRRbGys/v7772zLpk2bpvvuu0+hoaEOjfNGGWN08eJF6/N58+apevXqqlq1qubPn3/T47u7uysgIEAFCuT9nSzseY8c4euvv1b//v01dOhQ/f7776pVq5YiIiKUmJh4y2JwFPLKscirG3fmzBnVqlVLn3zyyS3bZl4gpxyLnLpxcXFx6tmzp3755RfFxsYqPT1dzZo105kzZ25ZDI5CXjkWeXXjypYtq1GjRmnTpk367bff9Mgjj6hVq1bavn27fQM5uKjMd7Kq+ho1apj//e9/1vaZM2ea0NBQ06pVK+uvLosXLzYNGjQwvr6+pkSJEiYyMtLs3bvXuo4km0ejRo1stvHOO++YMmXKmPLlyxtjjAkODjZjx441xlz6xaNgwYJmzZo11vFGjx5t/Pz8TEJCgklPTzf+/v7m7bffton/1KlTxtvb20yePNkYY8xPP/1kHnroIVOoUCFTtmxZ8+qrr5rTp09b+58/f94MGjTIlC1b1nh4eJhKlSqZL774wvqL0eWPrP0+f/68efXVV42fn5/x9PQ0DRo0MBs3brSOmfVrzY8//mjq1KljChYsaFatWmVd3rhxYzNlyhQzefJk8+ijj2Z7D7Zt22YiIyNN0aJFjbe3t3nooYfM3r17zdChQ7PFtGrVKptftzIyMsxdd91lJk2aZDPm77//biwWizlw4IAxxpgPP/zQ1KhRwxQuXNiULVvW9OjRw5w6dcom/ssfQ4cOzfYeGWPMwYMHzRNPPGGKFCliihYtap5++mmTkJBgXT506FBTq1YtM2PGDBMcHGx8fHzMs88+a1JTU7Ptd04eeOAB07NnT+vzjIwMExgYaEaOHJmr9fML8oq8yk95dTm58JE3coqcyo85ZcylIxSSTFxc3A2t7yzkFXmVn/PKGGOKFy9uvvjiC7vWuWOKt48++sg0adLE2t6kSRMzduxYm8SdO3eumTdvntmzZ4/ZvHmzadmypalZs6bJyMgwxhizceNGI8ksX77cHD161Jw4ccK6DW9vb9OhQwezbds2s23bNmNM9g/FwIEDTXBwsElOTja///678fDwMAsWLLBZXqlSJZOZmWltmzp1qvHy8jLJyclm7969pkiRImbs2LHmzz//NGvXrjX33nuv6dSpk7X/M888Y4KCgsy3335r9u3bZ5YvX25mz55tLl68aObNm2ckmd27d5ujR4+a5ORkY4wxvXv3NoGBgebHH38027dvN1FRUaZ48eLW/cv64IeGhpply5aZvXv3Wpft3bvXeHp6mqSkJHPixAlTqFAhazIZY8zff/9tSpQoYVq3bm1+/fVXs3v3bjN16lSza9cuc+rUKfPMM8+Yxx57zBw9etQcPXrUpKWlZTs14bXXXjMPPfSQzfs6YMAAm7axY8ealStXmv3795sVK1aYKlWqmB49ehhjjElLSzPjxo0zPj4+1u1kJfXl71FGRoapXbu2eeihh8xvv/1mfvnlF1O3bl3rF7QxlxLX29vbtG7d2mzdutWsWbPGBAQEmDfeeOOqn8EsaWlpxt3dPdsflh07djRPPPHEddfPT8gr8iq/5NWVXL14I6fIqfyWU8YYs2fPHiPJbN269YbWdxbyirzKr3l18eJF89VXXxkPDw+zfft2u9a9Y4q3xMRE4+npaQ4cOGAOHDhgChUqZI4fP26TuFc6fvy4zZfV1c53joqKMv7+/iYtLc2m/crETUtLM7Vr1zbPPPOMCQkJMV27drXpv3PnTusvD1nCw8PNCy+8YIwxpkuXLqZbt2426/z000/Gzc3NnDt3zuzevdtIMrGxsTnuT07nO58+fdoULFjQzJw509p24cIFExgYaMaMGWOz3vz587ON+cYbb5gnn3zS+rxVq1bWXzSMMSY6OtpUqFDBXLhwIceYcjrf+crXefPmzcZisZiDBw8aY4z1l5isX6JyMmfOHFOyZEnr86ud73z5e7Rs2TLj7u5uDh06ZF2+fft2I8n6K9TQoUNN4cKFbX5lGThwoKlXr95VY8nyzz//GElm3bp1Nu0DBw40DzzwwHXXz0/Iq/9HXvlm63cr8+pKrl68kVPkVH7LqYyMDBMZGWkaNGhg97rORl79P/LKN1s/Z+TVli1bTJEiRYy7u7vx9fU1ixYtyvW6We6Ia96kS+e1RkZGKiYmRtOmTVNkZKRKlSpl02fPnj167rnnVLFiRfn4+Kh8+fKSpEOHDl13/Jo1a8rDw+OafTw8PDRz5kzNmzdP58+f19ixY22WV61aVQ8++KCmTp0qSdq7d69++ukndenSRZL0xx9/KCYmRt7e3tZHRESEMjMztX//fsXHx8vd3V2NGjXK7cuiffv2KT09XQ0aNLC2FSxYUA888IB27txp0/e+++6zeZ6RkaHp06frhRdesLa98MILiomJUWZmpiQpPj5e4eHhKliwYK5julLt2rVVrVo1zZo1S9Klc/ETExP19NNPW/ssX75cTZo00V133aWiRYuqQ4cOOnHihM6ePZvr7ezcuVNBQUEKCgqytoWEhKhYsWI2r0X58uVVtGhR6/MyZcq45DVrjkBe5Yy8+n/klX3IqZyRU//vVudUz549tW3bNs2ePdvudfML8ipn5NX/u1V5VaVKFcXHx2vDhg3q0aOHoqKitGPHjlyvL91htwro3LmzYmJiNH36dHXu3Dnb8pYtWyopKUmff/65NmzYoA0bNkj6/4tPr6VIkSK5imHdunWSpKSkJCUlJWVb3qVLF82bN0+nTp3StGnTVKlSJWsinj59Wt27d1d8fLz18ccff2jPnj2qVKmSvLy8chXDjbpyH5cuXap//vlHzz77rAoUKKACBQqoXbt2OnjwoFasWCFJDoupffv21sSdNWuWHnvsMZUsWVLSpWllW7RoodDQUM2bN0+bNm2yTlyQm/fOXld+CVksFusX1bWUKlVK7u7uOnbsmE37sWPHFBAQ4NAYbyXy6uaQV5fcaF7djsipm0NOXeKInOrVq5cWLlyoVatWqWzZso4M75Yjr24OeXXJzeaVh4eHKleurLp162rkyJGqVauWxo8fb1cMd1Tx9thjj+nChQtKT09XRESEzbITJ05o9+7deuutt9SkSRNVq1ZNJ0+etOmT9atKRkbGDW1/37596tevnz7//HPVq1dPUVFR2d7wZ555Rm5ubpo1a5ZmzJihzp07y2KxSJLq1KmjHTt2qHLlytkeHh4eqlmzpjIzMxUXF5fj9nOKv1KlSvLw8NDatWutbenp6fr1118VEhJyzf358ssv1a5dO5svkvj4eLVr105ffvmlJCk0NFQ//fST0tPTrxpTbl7P559/Xtu2bdOmTZs0d+5ctW/f3rps06ZNyszM1Icffqj69evrnnvu0ZEjR+zeTrVq1XT48GEdPnzY2rZjxw4lJydf97XIDQ8PD9WtW9f6pSZJmZmZWrFihcLCwm56fGchr8ira8nrvLodkVPk1LXcipwyxqhXr1767rvvtHLlSlWoUMEh4zoTeUVeXYuz/q3KzMxUWlqafSvZfaKli7nyfNqUlBSTkpJifZ51vnNGRoYpWbKkeeGFF8yePXvMihUrzP33329z/UR6errx8vIy77zzjklISLBe7JnTObvG2J5Le/HiRVO/fn3Tpk0bY4wxR44cMSVLlrSeU3y5Ll26mOLFixt3d3fzzz//WNv/+OMP4+XlZXr27Gk2b95s/vzzTzN//nyb2Qs7depkgoKCzHfffWf++usvs2rVKvP1118bYy5dOGqxWExMTIxJTEy0XrDZp08fExgYaBYvXmxzsWpSUpIxJufzpBMTE03BggXN4sWLs8X/448/Gk9PT3PixAnz77//mpIlS1ovVv3zzz/NjBkzrPeLeffdd025cuXMrl27zPHjx82FCxeuel55gwYNTK1atUzRokXN2bNnre3x8fFGkhk3bpzZt2+fmTFjhrnrrrtsYl67dq31QuPjx49b7+tx+XuUmZlpateubcLDw82mTZvMhg0bcrxYtVatWjZxjR071gQHB2d7HXIye/Zs4+npaWJiYsyOHTtMt27dTLFixWxmM3IF5BV5ZUz+yatTp06ZzZs3m82bNxtJ5qOPPjKbN2+2XiPhCsgpcsqY/JNTPXr0ML6+vmb16tXWSR6OHj1qsz+ugLwir4zJP3n1+uuvm7i4OLN//36zZcsW8/rrrxuLxWKWLVuWq/Wz3HHF25Uuv1g1NjbWVKtWzXh6eprQ0FCzevXqbBe/f/755yYoKMi4ubllmyb2Spd/KIYPH27KlClj/v33X+vyefPmGQ8PDxMfH2+z3rp164wk8/jjj2cbc+PGjebRRx813t7epkiRIiY0NNS8++671uXnzp0z/fr1M2XKlDEeHh6mcuXKZurUqdblI0aMMAEBAcZisVj3+9y5c+bVV181pUqVuuY0sZcn7gcffGCKFSuW40WoaWlpplixYmb8+PHGmEtfOM2aNTOFCxc2RYsWNeHh4Wbfvn3GmEtfAFn7oxymib3cpEmTjCTTsWPHbNv86KOPTJkyZYyXl5eJiIgwM2bMyBbzyy+/bEqWLOmQaWIvZ0/iGmPMxx9/bMqVK2c8PDzMAw88YH755Zdcr5tfkFfkVZb8kFc5TQUt5f7mu/kBOUVOZckPOZVTPkky06ZNy9X6+QV5RV5lyQ951blzZxMcHGw8PDyMn5+fadKkid2FmzHGWIwxxr5jdQAAAACAW+2OuuYNAAAAAFwVxRvgIIcOHbKZwvfKR26mGwZgi7wCHIucAhzvVuYVp00CDnLx4kUdOHDgqsvLly+vAgUK3LqAgNsAeQU4FjkFON6tzCuKNwAAAABwAZw2CQAAAAAugOINAAAAAFwAxRsAAAAAuACKNwAAAABwARRvAADkUuPGjdW3b99c91+9erUsFouSk5PzLCYAwJ2D4g0AkOc6deoki8WiUaNG2bTPnz9fFovFrrHKly+vcePGOTA6AABcA8UbAOCWKFSokEaPHq2TJ086OxS7Xbhwwdkh3JT09HRnhwAAcACKNwDALdG0aVMFBARo5MiR1+z3888/Kzw8XF5eXgoKClLv3r115swZSZdOWzx48KD69esni8Uii8UiY4z8/Pw0d+5c6xi1a9dWmTJlbMb09PTU2bNnJUmHDh1Sq1at5O3tLR8fHz3zzDM6duyYtf+wYcNUu3ZtffHFF6pQoYIKFSqUY6yLFi2Sr6+vZs6cmavX4MSJE3ruued01113qXDhwqpZs6a++uor6/IZM2aoZMmSSktLs1nvySefVIcOHazPFyxYoDp16qhQoUKqWLGihg8frosXL1qXWywWTZ48WU888YSKFCmid999VydPnlT79u3l5+cnLy8v3X333Zo2bVqu4gYA5A8UbwCAW8Ld3V3vvfeePv74Y/3999859tm3b58ee+wxtWnTRlu2bNHXX3+tn3/+Wb169ZIkffvttypbtqxGjBiho0eP6ujRo7JYLGrYsKFWr14tSTp58qR27typc+fOadeuXZKkuLg43X///SpcuLAyMzPVqlUrJSUlKS4uTrGxsfrrr7/07LPP2sSyd+9ezZs3T99++63i4+OzxTpr1iw999xzmjlzptq3b5+r1+D8+fOqW7euFi1apG3btqlbt27q0KGDNm7cKEl6+umnlZGRoe+//966TmJiohYtWqTOnTtLkn766Sd17NhRffr00Y4dO/Tpp58qJiZG7777rs22hg0bpqeeekpbt25V586d9Z///Ec7duzQ4sWLtXPnTk2ePFmlSpXKVdwAgHzCAACQx6KiokyrVq2MMcbUr1/fdO7c2RhjzHfffWcu/6eoS5cuplu3bjbr/vTTT8bNzc2cO3fOGGNMcHCwGTt2rE2fCRMmmOrVqxtjjJk/f76pV6+eadWqlZk8ebIxxpimTZuaN954wxhjzLJly4y7u7s5dOiQdf3t27cbSWbjxo3GGGOGDh1qChYsaBITE22206hRI9OnTx8zceJE4+vra1avXn3N/V61apWRZE6ePHnVPpGRkWbAgAHW5z169DDNmze3Pv/www9NxYoVTWZmpjHGmCZNmpj33nvPZoz//ve/pkyZMtbnkkzfvn1t+rRs2dK8+OKL14wXAJC/ceQNAHBLjR49WtOnT9fOnTuzLfvjjz8UExMjb29v6yMiIkKZmZnav3//Vcds1KiRduzYoePHjysuLk6NGzdW48aNtXr1aqWnp2vdunVq3LixJGnnzp0KCgpSUFCQdf2QkBAVK1bMJqbg4GD5+fll29bcuXPVr18/xcbGqlGjRnbte0ZGht5++23VrFlTJUqUkLe3t5YuXapDhw5Z+3Tt2lXLli3TP//8I0mKiYmxTviS9RqNGDHC5jXq2rWrjh49aj0tVJLuu+8+m2336NFDs2fPVu3atTVo0CCtW7fOrtgBAM5H8QYAuKUaNmyoiIgIRUdHZ1t2+vRpde/eXfHx8dbHH3/8oT179qhSpUpXHTOrGIqLi7Mp3uLi4vTrr78qPT1dDz74oF1xFilSJMf2e++9V35+fpo6daqMMXaN+f7772v8+PEaPHiwVq1apfj4eEVERNhMiHLvvfeqVq1amjFjhjZt2qTt27erU6dO1uWnT5/W8OHDbV6jrVu3as+ePTbX5l0Zf/Pmza3XCx45ckRNmjTRa6+9Zlf8AADnKuDsAAAAd55Ro0apdu3aqlKlik17nTp1tGPHDlWuXPmq63p4eCgjI8OmzWKxKDw8XAsWLND27dv10EMPqXDhwkpLS9Onn36q++67z1rMVKtWTYcPH9bhw4etR9927Nih5ORkhYSEXDf2SpUq6cMPP1Tjxo3l7u6uiRMn5nq/165dq1atWumFF16QJGVmZurPP//Mtt2XXnpJ48aN0z///KOmTZvaHCWsU6eOdu/efc3X6Gr8/PwUFRWlqKgohYeHa+DAgfrggw/sHgcA4BwceQMA3HI1a9ZU+/btNWHCBJv2wYMHa926derVq5fi4+O1Z88eLViwwDphiXTpPm9r1qzRP//8o3///dfa3rhxY3311VeqXbu2vL295ebmpoYNG2rmzJk2pzc2bdrUuv3ff/9dGzduVMeOHdWoUaNspxpezT333KNVq1Zp3rx5dt20++6771ZsbKzWrVunnTt3qnv37jazXGZ5/vnn9ffff+vzzz+3TlSSZciQIZoxY4aGDx+u7du3a+fOnZo9e7beeuuta257yJAhWrBggfbu3avt27dr4cKFqlatWq5jBwA4H8UbAMApRowYoczMTJu20NBQxcXF6c8//1R4eLjuvfdeDRkyRIGBgTbrHThwQJUqVbK5Jq1Ro0bKyMiwXtsmXSrormyzWCxasGCBihcvroYNG6pp06aqWLGivv76a7vir1KlilauXKmvvvpKAwYMyNU6b731lurUqaOIiAg1btxYAQEBevLJJ7P18/X1VZs2beTt7Z1teUREhBYuXKhly5bp/vvvV/369TV27FgFBwdfc9seHh6Kjo5WaGioGjZsKHd3d82ePTu3uwsAyAcsxt4T9gEAQJ5r0qSJqlevnu3oJADgzkXxBgBAPnLy5EmtXr1abdu21Y4dO7JdFwgAuHMxYQkAAPnIvffeq5MnT2r06NEUbgAAGxx5AwAAAAAXwIQlAAAAAOACKN4AAAAAwAVQvAEAAACAC6B4AwAAAAAXQPEGAAAAAC6A4g0AAAAAXADFGwAAAAC4AIo3AAAAAHAB/wdjk8kS8Ch0wAAAAABJRU5ErkJggg==", + "text/plain": [ + "
    " + ] + }, + "metadata": {}, + "output_type": "display_data" } ], "source": [ - "#To view the source code of the matrix vector activation function\n", - "from finn.custom_op.fpgadataflow.matrixvectoractivation import MatrixVectorActivation\n", - "showSrc(MatrixVectorActivation)" + "fig = plt.figure(figsize = (10, 5))\n", + "plt.bar(cycles_dict_updated.keys(), cycles_dict_updated.values(), color ='blue', width = 0.3)\n", + "plt.xlabel(\"Network layers\")\n", + "plt.ylabel(\"Number of clock cycles\")\n", + "plt.title(\"Estimated no. of clock cycles for each network layer\")\n", + "plt.show()" ] }, { - "cell_type": "markdown", + "cell_type": "code", + "execution_count": 14, + "metadata": {}, + "outputs": [ + { + "data": { + "text/plain": [ + "{'MatrixVectorActivation_0': {'BRAM_18K': 8,\n", + " 'BRAM_efficiency': 0.5208333333333334,\n", + " 'LUT': 418,\n", + " 'URAM': 0,\n", + " 'URAM_efficiency': 1,\n", + " 'DSP': 0},\n", + " 'MatrixVectorActivation_1': {'BRAM_18K': 1,\n", + " 'BRAM_efficiency': 0.4444444444444444,\n", + " 'LUT': 320,\n", + " 'URAM': 0,\n", + " 'URAM_efficiency': 1,\n", + " 'DSP': 0},\n", + " 'MatrixVectorActivation_2': {'BRAM_18K': 1,\n", + " 'BRAM_efficiency': 0.4444444444444444,\n", + " 'LUT': 320,\n", + " 'URAM': 0,\n", + " 'URAM_efficiency': 1,\n", + " 'DSP': 0},\n", + " 'MatrixVectorActivation_3': {'BRAM_18K': 1,\n", + " 'BRAM_efficiency': 0.006944444444444444,\n", + " 'LUT': 320,\n", + " 'URAM': 0,\n", + " 'URAM_efficiency': 1,\n", + " 'DSP': 0}}" + ] + }, + "execution_count": 14, + "metadata": {}, + "output_type": "execute_result" + } + ], + "source": [ + "res_dict_updated = model.analysis(res_estimation)\n", + "res_dict_updated" + ] + }, + { + "cell_type": "code", + "execution_count": 16, "metadata": {}, + "outputs": [ + { + "data": { + "image/png": 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GRoaSk5Ot05uWL1+uYcOGaeXKlTpz5oxT/+TkZGtdl7Nr1y5t2rRJRYsWzXZ+5g0Y/vjjDxUrVkw+Pj5O8+++++6r7F3+yq9b4BcpUkSNGzfW119/rZEjR0q6cBqjq6ur2rVrZ/XLvEZo3Lhx2rNnj9LT0615OTnFLCd27dql5ORkBQUFZTs/8zWIjo5W+/btNXz4cI0ePVqNGjXSgw8+qMcff1weHh75UsuIESPUtm1bVaxYUVWrVlXz5s3VuXNnRURESJJ2794tY4yGDBmiIUOGXLbeEiVK6I8//lDt2rWzzL+W98wff/xx2XVUqlRJP//8s1Obq6urSpYsedX1HjlyRCdOnNCECRM0YcKEbPtkvg6SNHnyZL3zzjvavn27U0i++K6uiYmJKl68uAIDA6+6/Us/AySpUKFCWa4xzOnyhQoVkiRr+cygfaVTj5OTk63lsuPi4qKoqCgtW7ZM0oVg1qBBA9WvX1/p6elatWqVgoODdezYMadgdrn3QeYp3n/88YeqVq1qtWd3Z9xMnTt3lqurq7Zt26aQkJDL9ruaffv2aejQofr222+zPMcXf6HVtGlTFStWTFOmTFHjxo2VkZGhL7/8Um3btpWvr6+kvD23V9pHALlDMAPuUEFBQdq4caPmz5+vefPmad68eZo4caK6dOmiyZMn53m9Li4uuWo3//+ahMTERDVu3FiVKlXSu+++q9DQULm7u+v777/X6NGjc3SThYyMDDVt2lQvvPBCtvMrVqyYw724dh4eHk4X318sM3RefJTkWnXs2FHdunXTxo0bFRkZqa+//lqNGze2rquRLlzkP2TIEHXv3l0jR45UYGCgChQooOeff/6qz6/D4cj2+pGLw5104TUICgrSlClTsl1PZmjO/B24VatW6bvvvtP8+fPVvXt3vfPOO1q1alWW0JwTl9bSsGFDJSYm6ptvvtGPP/6oTz75RKNHj9aHH36oJ5980trnAQMGKCYmJtt15ubnJa63i494Xknmfj3xxBOX/Qd2Zjj94osv1LVrVz344IMaOHCggoKC5OLiovj4eCUmJuapzquN9WtdPnP/3nrrLadr4C6Wk/dP/fr1NWrUKJ09e1bLli3Tv/71LwUEBKhq1apatmyZde3qxcEst650DWK7du30+eef67333lN8fHye1p+enm5dn/biiy+qUqVK8vb21l9//aWuXbs6jWsXFxc9/vjj+vjjjzVu3DgtX75cBw4ccLr7a16e25xcZwkgZwhmwB3M3d1dbdq0UZs2bZSRkaFnnnlGH330kYYMGaIKFSrc0B81/u6775Samqpvv/3W6Rvz7O4Od7m6ypcvr1OnTl31d6JKly6thQsX6tSpU07/yMjt3dCuto3LrS+zPa+nLmXnwQcfVK9evazTGXfu3KnBgwc79ZkxY4buu+8+ffrpp07tJ06ccApw2SlUqFC2p6JlHvXJVL58ef3000+qV69ejv7BVqdOHdWpU0ejRo3S1KlT1alTJ02bNk1PPvnkFWu59A6a586d08GDB7P0DQwMVLdu3dStWzedOnVKDRs21CuvvKInn3xS5cqVkyS5ubnl6D2T3SmR1/KeyXz9d+zYofvvvz/LevP6/ihatKh8fX2Vnp5+1f2aMWOGypUrp1mzZjmNq0tPWSxfvrzmz5+vY8eO5eio2fWUeZqkn5/fVffvSp9hDRo00Llz5/Tll1/qr7/+sgJYw4YNrWBWsWJFK6BJlx/X27dvt+bnVN++fVWhQgUNHTpU/v7+GjRoUI6XzbR582bt3LlTkydPVpcuXaz2y52i3qVLF73zzjv67rvvNG/ePBUtWtTpS4ncPLcA8h/XmAF3qKNHjzo9LlCggPUteuZt7DN/j+ZG3EY+81vyi79VT05O1sSJE7P09fb2zramDh06aOXKlZo/f36WeSdOnLCuZ2vZsqXS0tKcbsWfnp6uDz744Fp3w9KyZUutWrVK69aty1LHlClTFBkZeU2nL10qICBAMTEx+vrrrzVt2jS5u7vrwQcfdOrj4uKS5ajF9OnTs9yaPTvly5fX9u3bdeTIEavt119/zXIL7Q4dOig9Pd06pfJiaWlp1ut2/PjxLLVkfkN/6c8oZFdL5rVBmSZMmJDliNml73EfHx9VqFDBWn9QUJAaNWqkjz76KNtQd/G+Zr6ev/zyi9P8yx0ZzImaNWsqKChIH374odM+z5s3T9u2bVOrVq3ytF4XFxe1b99eM2fO1G+//ZZl/sX7ld24W716tVauXOm0TPv27WWMyfZnGXJ6JCy/1KhRQ+XLl9fbb7+tU6dOZZl/8f5d6TOsdu3acnNz0xtvvKHAwEBVqVJF0oXAtmrVKiUkJGQ5WtayZUv98ssvTs/P6dOnNWHCBJUpU0ZhYWG52pchQ4ZowIABGjx4cJafBsmJ7F4/Y4z1syeXioiIUEREhD755BPNnDlTHTt2lKvr/76jz81zCyD/ccQMuE3NmzfP+hb3YnXr1lW5cuX05JNP6tixY7r//vtVsmRJ/fHHH/rggw8UGRlpXS8RGRkpFxcXvfHGG0pOTpaHh4f1O2P5rVmzZtYRvF69eunUqVP6+OOPFRQUlOUfzTVq1ND48eP16quvqkKFCgoKCtL999+vgQMH6ttvv1Xr1q3VtWtX1ahRQ6dPn9bmzZs1Y8YM7d27V0WKFFGbNm1Ur149DRo0SHv37lVYWJhmzZqVoxuMXGzmzJnZPsexsbEaNGiQpk+froYNG6pXr16qVKmSDhw4oEmTJungwYPZBs5r9eijj+qJJ57QuHHjFBMTk+XHjFu3bq0RI0aoW7duqlu3rjZv3qwpU6ZYR46upHv37nr33XcVExOjHj166PDhw/rwww9VpUoVp99mio6OVq9evRQfH6+NGzeqWbNmcnNz065duzR9+nS99957evjhhzV58mSNGzdODz30kMqXL6+TJ0/q448/lp+fn1q2bHnFWp588kk9/fTTat++vZo2bapff/1V8+fPz3LULywsTI0aNVKNGjUUGBiotWvXasaMGerTp4/VZ+zYsapfv77Cw8PVs2dPlStXTocOHdLKlSv1559/Wr/x9sILL+g///mPmjdvrueee866XX7p0qW1adOmqz5/2ckMBd26dVN0dLQee+wx63b5ZcqUUb9+/fK0XunCLecXL16s2rVrq2fPngoLC9OxY8e0fv16/fTTTzp27JikC++JWbNm6aGHHlKrVq20Z88effjhhwoLC3P6h/l9992nzp076/3339euXbvUvHlzZWRkaNmyZbrvvvucntPrrUCBAvrkk0/UokULValSRd26dVOJEiX0119/afHixfLz89N3330n6cJnhXThJws6duwoNzc3tWnTRt7e3ipYsKBq1KihVatWWb9hJl04Ynb69GmdPn06SzAbNGiQvvzyS7Vo0ULPPvusAgMDNXnyZO3Zs0czZ87M0amml3rrrbeUnJysuLg4+fr65uqH5StVqqTy5ctrwIAB+uuvv+Tn56eZM2de8Xq+Ll26aMCAAZKUZVu5eW4BXAc3+jaQAK6vK90uXxfdFnnGjBmmWbNmJigoyLi7u5tSpUqZXr16mYMHDzqt7+OPPzblypUzLi4uTrdpvtzt8i+9hXx2twk35n+3Wj5y5IjV9u2335qIiAjj6elpypQpY9544w3z2WefZbnddVJSkmnVqpXx9fU1kpzqOHnypBk8eLCpUKGCcXd3N0WKFDF169Y1b7/9ttNt/I8ePWo6d+5s/Pz8jL+/v+ncubPZsGFDrm6Xf7kp81baf/75p3nyySdNiRIljKurqwkMDDStW7c2q1atuuL6c3u7/EwpKSnGy8vLSDJffPFFlvlnz541//d//2eKFStmvLy8TL169czKlSuzvJbZ3S7fGGO++OILU65cOePu7m4iIyPN/Pnzs9wuP9OECRNMjRo1jJeXl/H19TXh4eHmhRdeMAcOHDDGXLhN92OPPWZKlSplPDw8TFBQkGndurVZu3btVfczPT3dvPjii6ZIkSKmYMGCJiYmxuzevTvL7fJfffVVU6tWLRMQEGC8vLxMpUqVzKhRo5zeB8YYk5iYaLp06WJCQkKMm5ubKVGihGndurWZMWOGU79NmzaZ6Oho4+npaUqUKGFGjhxpPv300zzfLj/TV199ZapXr248PDxMYGCg6dSpk/nzzz+d+sTGxhpvb++rPjcXO3TokImLizOhoaHGzc3NhISEmMaNG5sJEyZYfTIyMsxrr71mSpcubTw8PEz16tXN3Llzs31d09LSzFtvvWUqVapk3N3dTdGiRU2LFi3MunXrrD66zM9EXPraZOdynyGXez9u2LDBtGvXzhQuXNh4eHiY0qVLmw4dOpiFCxc69Rs5cqQpUaKEKVCgQJbXauDAgUaSeeONN5yWqVChgpFkEhMTs9SZmJhoHn74YRMQEGA8PT1NrVq1zNy5c3O0L8Zk/15IT083jz32mHF1dTVz5sy56nN08e3yt27dapo0aWJ8fHxMkSJFTM+ePa2fKMjus+zgwYPGxcXFVKxY8bLbyclzm91nOIBr4zCGXwMEAAC4E/z9998qVqyYhg4detm7kQKwB9eYAQAA3CEmTZqk9PR0de7c2e5SAFyCa8wAAABuc4sWLdLWrVs1atQoPfjggypTpozdJQG4BKcyAgAA3OYaNWqkFStWqF69evriiy9UokQJu0sCcAmCGQAAAADYjGvMAAAAAMBmBDMAAAAAsBk3/5CUkZGhAwcOyNfX1/qBSQAAAAB3HmOMTp48qeLFi+fph+PzimAm6cCBAwoNDbW7DAAAAAA3if3796tkyZI3bHsEM0m+vr6SLjz5fn5+NlcDAAAAwC4pKSkKDQ21MsKNQjCTrNMX/fz8CGYAAAAAbvglTtz8AwAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZq52F4CsHMMddpdgKzPM2F0CAAAAcENxxAwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZjdNMHv99dflcDj0/PPPW21nz55VXFycChcuLB8fH7Vv316HDh1yWm7fvn1q1aqVChYsqKCgIA0cOFBpaWk3uHoAAAAAyLubIpitWbNGH330kSIiIpza+/Xrp++++07Tp09XQkKCDhw4oHbt2lnz09PT1apVK507d04rVqzQ5MmTNWnSJA0dOvRG7wIAAAAA5JntwezUqVPq1KmTPv74YxUqVMhqT05O1qeffqp3331X999/v2rUqKGJEydqxYoVWrVqlSTpxx9/1NatW/XFF18oMjJSLVq00MiRIzV27FidO3fOrl0CAAAAgFyxPZjFxcWpVatWatKkiVP7unXrdP78eaf2SpUqqVSpUlq5cqUkaeXKlQoPD1dwcLDVJyYmRikpKdqyZctlt5mamqqUlBSnCQAAAADs4mrnxqdNm6b169drzZo1WeYlJSXJ3d1dAQEBTu3BwcFKSkqy+lwcyjLnZ867nPj4eA0fPvwaqwcAAACA/GHbEbP9+/frueee05QpU+Tp6XlDtz148GAlJydb0/79+2/o9gEAAADgYrYFs3Xr1unw4cO655575OrqKldXVyUkJOj999+Xq6urgoODde7cOZ04ccJpuUOHDikkJESSFBISkuUujZmPM/tkx8PDQ35+fk4TAAAAANjFtmDWuHFjbd68WRs3brSmmjVrqlOnTtbfbm5uWrhwobXMjh07tG/fPkVFRUmSoqKitHnzZh0+fNjqs2DBAvn5+SksLOyG7xMAAAAA5IVt15j5+vqqatWqTm3e3t4qXLiw1d6jRw/1799fgYGB8vPzU9++fRUVFaU6depIkpo1a6awsDB17txZb775ppKSkvTyyy8rLi5OHh4eN3yfAAAAACAvbL35x9WMHj1aBQoUUPv27ZWamqqYmBiNGzfOmu/i4qK5c+eqd+/eioqKkre3t2JjYzVixAgbqwYAAACA3HEYY4zdRdgtJSVF/v7+Sk5OvimuN3MMd9hdgq3MsDv+LQkAAACb2JUNbP8dMwAAAAC40xHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACb2RrMxo8fr4iICPn5+cnPz09RUVGaN2+eNb9Ro0ZyOBxO09NPP+20jn379qlVq1YqWLCggoKCNHDgQKWlpd3oXQEAAACAPHO1c+MlS5bU66+/rrvuukvGGE2ePFlt27bVhg0bVKVKFUlSz549NWLECGuZggULWn+np6erVatWCgkJ0YoVK3Tw4EF16dJFbm5ueu211274/gAAAABAXtgazNq0aeP0eNSoURo/frxWrVplBbOCBQsqJCQk2+V//PFHbd26VT/99JOCg4MVGRmpkSNH6sUXX9Qrr7wid3f3674PAAAAAHCtbpprzNLT0zVt2jSdPn1aUVFRVvuUKVNUpEgRVa1aVYMHD9aZM2eseStXrlR4eLiCg4OttpiYGKWkpGjLli2X3VZqaqpSUlKcJgAAAACwi61HzCRp8+bNioqK0tmzZ+Xj46PZs2crLCxMkvT444+rdOnSKl68uDZt2qQXX3xRO3bs0KxZsyRJSUlJTqFMkvU4KSnpstuMj4/X8OHDr9MeAQAAAEDu2B7M7r77bm3cuFHJycmaMWOGYmNjlZCQoLCwMD311FNWv/DwcBUrVkyNGzdWYmKiypcvn+dtDh48WP3797cep6SkKDQ09Jr2AwAAAADyyvZTGd3d3VWhQgXVqFFD8fHxqlatmt57771s+9auXVuStHv3bklSSEiIDh065NQn8/HlrkuTJA8PD+tOkJkTAAAAANjF9mB2qYyMDKWmpmY7b+PGjZKkYsWKSZKioqK0efNmHT582OqzYMEC+fn5WadDAgAAAMDNztZTGQcPHqwWLVqoVKlSOnnypKZOnaolS5Zo/vz5SkxM1NSpU9WyZUsVLlxYmzZtUr9+/dSwYUNFRERIkpo1a6awsDB17txZb775ppKSkvTyyy8rLi5OHh4edu4aAAAAAOSYrcHs8OHD6tKliw4ePCh/f39FRERo/vz5atq0qfbv36+ffvpJY8aM0enTpxUaGqr27dvr5ZdftpZ3cXHR3Llz1bt3b0VFRcnb21uxsbFOv3sGAAAAADc7hzHG2F2E3VJSUuTv76/k5OSb4nozx3CH3SXYygy749+SAAAAsIld2eCmu8YMAAAAAO40BDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbOZqdwEAcL05hjvsLsFWZpixuwTchhhXjCvkL8YUY4ojZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM1uD2fjx4xURESE/Pz/5+fkpKipK8+bNs+afPXtWcXFxKly4sHx8fNS+fXsdOnTIaR379u1Tq1atVLBgQQUFBWngwIFKS0u70bsCAAAAAHlmazArWbKkXn/9da1bt05r167V/fffr7Zt22rLli2SpH79+um7777T9OnTlZCQoAMHDqhdu3bW8unp6WrVqpXOnTunFStWaPLkyZo0aZKGDh1q1y4BAAAAQK45jDHG7iIuFhgYqLfeeksPP/ywihYtqqlTp+rhhx+WJG3fvl2VK1fWypUrVadOHc2bN0+tW7fWgQMHFBwcLEn68MMP9eKLL+rIkSNyd3fPdhupqalKTU21HqekpCg0NFTJycny8/O7/jt5FY7hDrtLsJUZdlO9JXEbYEwxppD/GFeMK+QvxtTNM6ZSUlLk7+9/w7PBTXONWXp6uqZNm6bTp08rKipK69at0/nz59WkSROrT6VKlVSqVCmtXLlSkrRy5UqFh4dboUySYmJilJKSYh11y058fLz8/f2tKTQ09PrtGAAAAABche3BbPPmzfLx8ZGHh4eefvppzZ49W2FhYUpKSpK7u7sCAgKc+gcHByspKUmSlJSU5BTKMudnzrucwYMHKzk52Zr279+fvzsFAAAAALngancBd999tzZu3Kjk5GTNmDFDsbGxSkhIuK7b9PDwkIeHx3XdBgAAAADklO3BzN3dXRUqVJAk1ahRQ2vWrNF7772nRx99VOfOndOJEyecjpodOnRIISEhkqSQkBD98ssvTuvLvGtjZh8AAAAAuNnZfirjpTIyMpSamqoaNWrIzc1NCxcutObt2LFD+/btU1RUlCQpKipKmzdv1uHDh60+CxYskJ+fn8LCwm547QAAAACQF7YeMRs8eLBatGihUqVK6eTJk5o6daqWLFmi+fPny9/fXz169FD//v0VGBgoPz8/9e3bV1FRUapTp44kqVmzZgoLC1Pnzp315ptvKikpSS+//LLi4uI4VREAAADALcPWYHb48GF16dJFBw8elL+/vyIiIjR//nw1bdpUkjR69GgVKFBA7du3V2pqqmJiYjRu3DhreRcXF82dO1e9e/dWVFSUvL29FRsbqxEjRti1SwAAAACQa7YGs08//fSK8z09PTV27FiNHTv2sn1Kly6t77//Pr9LAwAAAIAb5qa7xgwAAAAA7jQEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAm7nmZaFdu3Zp8eLFOnz4sDIyMpzmDR06NF8KAwAAAIA7Ra6D2ccff6zevXurSJEiCgkJkcPhsOY5HA6CGQAAAADkUq6D2auvvqpRo0bpxRdfvB71AAAAAMAdJ9fXmB0/flyPPPLI9agFAAAAAO5IuQ5mjzzyiH788cfrUQsAAAAA3JFyfSpjhQoVNGTIEK1atUrh4eFyc3Nzmv/ss8/mW3EAAAAAcCfIdTCbMGGCfHx8lJCQoISEBKd5DoeDYAYAAAAAuZTrYLZnz57rUQcAAAAA3LGu6QemjTEyxuRXLQAAAABwR8pTMPv8888VHh4uLy8veXl5KSIiQv/5z3/yuzYAAAAAuCPk+lTGd999V0OGDFGfPn1Ur149SdLPP/+sp59+Wn///bf69euX70UCAAAAwO0s18Hsgw8+0Pjx49WlSxer7YEHHlCVKlX0yiuvEMwAAAAAIJdyfSrjwYMHVbdu3SztdevW1cGDB/OlKAAAAAC4k+Q6mFWoUEFff/11lvavvvpKd911V74UBQAAAAB3klyfyjh8+HA9+uijWrp0qXWN2fLly7Vw4cJsAxsAAAAA4MpyfcSsffv2Wr16tYoUKaI5c+Zozpw5KlKkiH755Rc99NBD16NGAAAAALit5fqImSTVqFFDX3zxRX7XAgAAAAB3pBwdMUtJSXH6+0pTbsTHx+vee++Vr6+vgoKC9OCDD2rHjh1OfRo1aiSHw+E0Pf3000599u3bp1atWqlgwYIKCgrSwIEDlZaWlqtaAAAAAMAuOTpiVqhQIR08eFBBQUEKCAiQw+HI0scYI4fDofT09BxvPCEhQXFxcbr33nuVlpaml156Sc2aNdPWrVvl7e1t9evZs6dGjBhhPS5YsKD1d3p6ulq1aqWQkBCtWLFCBw8eVJcuXeTm5qbXXnstx7UAAAAAgF1yFMwWLVqkwMBASdLixYvzbeM//PCD0+NJkyYpKChI69atU8OGDa32ggULKiQkJNt1/Pjjj9q6dat++uknBQcHKzIyUiNHjtSLL76oV155Re7u7lmWSU1NVWpqqvU4t0f6AAAAACA/5SiYRUdHW3+XLVtWoaGhWY6aGWO0f//+ayomOTlZkqwQmGnKlCn64osvFBISojZt2mjIkCHWUbOVK1cqPDxcwcHBVv+YmBj17t1bW7ZsUfXq1bNsJz4+XsOHD7+mWgEAAAAgv+T65h9ly5a1Tmu82LFjx1S2bNlcncp4sYyMDD3//POqV6+eqlatarU//vjjKl26tIoXL65NmzbpxRdf1I4dOzRr1ixJUlJSklMok2Q9TkpKynZbgwcPVv/+/a3HKSkpCg0NzVPdAAAAAHCtch3MMq8lu9SpU6fk6emZ50Li4uL022+/6eeff3Zqf+qpp6y/w8PDVaxYMTVu3FiJiYkqX758nrbl4eEhDw+PPNcKAAAAAPkpx8Es8wiTw+FwOpVQunADjtWrVysyMjJPRfTp00dz587V0qVLVbJkySv2rV27tiRp9+7dKl++vEJCQvTLL7849Tl06JAkXfa6NAAAAAC4meQ4mG3YsEHShSNmmzdvdrqphru7u6pVq6YBAwbkauPGGPXt21ezZ8/WkiVLVLZs2asus3HjRklSsWLFJElRUVEaNWqUDh8+bJ1euWDBAvn5+SksLCxX9QAAAACAHXIczDLvxtitWze999578vPzu+aNx8XFaerUqfrmm2/k6+trXRPm7+8vLy8vJSYmaurUqWrZsqUKFy6sTZs2qV+/fmrYsKEiIiIkSc2aNVNYWJg6d+6sN998U0lJSXr55ZcVFxfH6YoAAAAAbgm5vsZs4sSJ+bbx8ePHS7rwI9KXbqNr165yd3fXTz/9pDFjxuj06dMKDQ1V+/bt9fLLL1t9XVxcNHfuXPXu3VtRUVHy9vZWbGys0++eAQAAAMDNLNfBTJLWrl2rr7/+Wvv27dO5c+ec5mXeLTEnjDFXnB8aGqqEhISrrqd06dL6/vvvc7xdAAAAALiZFMjtAtOmTVPdunW1bds2zZ49W+fPn9eWLVu0aNEi+fv7X48aAQAAAOC2lutg9tprr2n06NH67rvv5O7urvfee0/bt29Xhw4dVKpUqetRIwAAAADc1nIdzBITE9WqVStJF+7GePr0aTkcDvXr108TJkzI9wIBAAAA4HaX62BWqFAhnTx5UpJUokQJ/fbbb5KkEydO6MyZM/lbHQAAAADcAXJ984+GDRtqwYIFCg8P1yOPPKLnnntOixYt0oIFC9S4cePrUSMAAAAA3NZyHcz+/e9/6+zZs5Kkf/3rX3Jzc9OKFSuy3MYeAAAAAJAzuQ5mgYGB1t8FChTQoEGD8rUgAAAAALjT5Poas/Xr12vz5s3W42+++UYPPvigXnrppSy/aQYAAAAAuLpcB7NevXpp586dkqTff/9djz76qAoWLKjp06frhRdeyPcCAQAAAOB2l+tgtnPnTkVGRkqSpk+frujoaE2dOlWTJk3SzJkz87s+AAAAALjt5TqYGWOUkZEhSfrpp5/UsmVLSVJoaKj+/vvv/K0OAAAAAO4AuQ5mNWvW1Kuvvqr//Oc/SkhIsH5ses+ePQoODs73AgEAAADgdpfrYDZmzBitX79effr00b/+9S9VqFBBkjRjxgzVrVs33wsEAAAAgNtdrm+XHxER4XRXxkxvvfWWXFxc8qUoAAAAALiT5DqYXY6np2d+rQoAAAAA7ig5CmaBgYHauXOnihQpokKFCsnhcFy277Fjx/KtOAAAAAC4E+QomI0ePVq+vr6SLlxjBgAAAADIPzkKZrGxsdn+DQAAAAC4djkKZikpKTleoZ+fX56LAQAAAIA7UY6CWUBAwBWvK5Mu/PC0w+FQenp6vhQGAAAAAHeKHAWzxYsXX+86AAAAAOCOlaNgFh0dfb3rAAAAAIA7Vo6C2aZNm1S1alUVKFBAmzZtumLfiIiIfCkMAAAAAO4UOQpmkZGRSkpKUlBQkCIjI+VwOGSMydKPa8wAAAAAIPdyFMz27NmjokWLWn8DAAAAAPJPjoJZ6dKlrb//+OMP1a1bV66uzoumpaVpxYoVTn0BAAAAAFdXILcL3HfffTp27FiW9uTkZN133335UhQAAAAA3ElyHcwyf6/sUkePHpW3t3e+FAUAAAAAd5IcncooSe3atZN04QYfXbt2lYeHhzUvPT1dmzZtUt26dfO/QgAAAAC4zeU4mPn7+0u6cMTM19dXXl5e1jx3d3fVqVNHPXv2zP8KAQAAAOA2l+NgNnHiRElSmTJlNGDAAE5bBAAAAIB8kuNglmnYsGHXow4AAAAAuGPl+OYfhQoVUmBgYJapbNmyiomJ0YIFC3K98fj4eN17773y9fVVUFCQHnzwQe3YscOpz9mzZxUXF6fChQvLx8dH7du316FDh5z67Nu3T61atVLBggUVFBSkgQMHKi0tLdf1AAAAAIAdcnzEbMyYMdm2nzhxQuvWrVPr1q01Y8YMtWnTJscbT0hIUFxcnO69916lpaXppZdeUrNmzbR161brVMl+/frpv//9r6ZPny5/f3/16dNH7dq10/LlyyVduPFIq1atFBISohUrVujgwYPq0qWL3Nzc9Nprr+W4FgAAAACwi8MYY/JjRe+++65mzJihFStW5HkdR44cUVBQkBISEtSwYUMlJyeraNGimjp1qh5++GFJ0vbt21W5cmWtXLlSderU0bx589S6dWsdOHBAwcHBkqQPP/xQL774oo4cOSJ3d/erbjclJUX+/v5KTk6Wn59fnuvPL47hWX+O4E5ihuXLWxKwMKYYU8h/jCvGFfIXY+rmGVN2ZYNc/47Z5bRu3Vrbt2+/pnUkJydLkgIDAyVJ69at0/nz59WkSROrT6VKlVSqVCmtXLlSkrRy5UqFh4dboUySYmJilJKSoi1btmS7ndTUVKWkpDhNAAAAAGCXfAtmqampOTo6dTkZGRl6/vnnVa9ePVWtWlWSlJSUJHd3dwUEBDj1DQ4OVlJSktXn4lCWOT9zXnbi4+Pl7+9vTaGhoXmuGwAAAACuVb4Fs08//VSRkZF5Xj4uLk6//fabpk2bll8lXdbgwYOVnJxsTfv377/u2wQAAACAy8nxzT/69++fbXtycrLWr1+vnTt3aunSpXkqok+fPpo7d66WLl2qkiVLWu0hISE6d+6cTpw44XTU7NChQwoJCbH6/PLLL07ry7xrY2afS3l4eMjDwyNPtQIAAABAfstxMNuwYUO27X5+fmratKlmzZqlsmXL5mrjxhj17dtXs2fP1pIlS7IsX6NGDbm5uWnhwoVq3769JGnHjh3at2+foqKiJElRUVEaNWqUDh8+rKCgIEnSggUL5Ofnp7CwsFzVAwAAAAB2yHEwW7x4cb5vPC4uTlOnTtU333wjX19f65owf39/eXl5yd/fXz169FD//v0VGBgoPz8/9e3bV1FRUapTp44kqVmzZgoLC1Pnzp315ptvKikpSS+//LLi4uI4KgYAAADglpDjYHY9jB8/XpLUqFEjp/aJEyeqa9eukqTRo0erQIECat++vVJTUxUTE6Nx48ZZfV1cXDR37lz17t1bUVFR8vb2VmxsrEaMGHGjdgMAAAAAromtwSwnP6Hm6empsWPHauzYsZftU7p0aX3//ff5WRoAAAAA3DD5dldGAAAAAEDeEMwAAAAAwGY5Dmbdu3fXyZMnr2ctAAAAAHBHynEwmzx5sv7555/rWQsAAAAA3JFyHMxycqMOAAAAAEDu5equjCdPnpSnp+cV+/j5+V1TQQAAAABwp8lVMKtYseJl5xlj5HA4lJ6efs1FAQAAAMCdJFfBbMaMGQoMDLxetQAAAADAHSlXwaxevXoKCgq6XrUAAAAAwB2J3zEDAAAAAJvlOJiVLl1aLi4u17MWAAAAALgj5fhUxj179lzPOgAAAADgjpXjYFaoUCE5HI4s7f7+/qpYsaIGDBigpk2b5mtxAAAAAHAnyHEwGz16dLbB7MSJE1q3bp1at26tGTNmqE2bNvlaIAAAAADc7nIczLp27XrF+ZGRkYqPjyeYAQAAAEAu5dtdGVu3bq3t27fn1+oAAAAA4I6Rb8EsNTVV7u7u+bU6AAAAALhj5Fsw+/TTTxUZGZlfqwMAAACAO0aOrzHr379/tu3Jyclav369du7cqaVLl+ZbYQAAAABwp8hxMNuwYUO27X5+fmratKlmzZqlsmXL5lthAAAAAHCnyHEwW7x48RXn//nnn3rqqac0YcKEay4KAAAAAO4k+XaN2dGjR/Xpp5/m1+oAAAAA4I6Rb8EMAAAAAJA3BDMAAAAAsBnBDAAAAABsluObf7Rr1+6K80+cOHGttQAAAADAHSnHwczf3/+q87t06XLNBQEAAADAnSbHwWzixInXsw4AAAAAuGNxjRkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANjM1mC2dOlStWnTRsWLF5fD4dCcOXOc5nft2lUOh8Npat68uVOfY8eOqVOnTvLz81NAQIB69OihU6dO3cC9AAAAAIBrY2swO336tKpVq6axY8detk/z5s118OBBa/ryyy+d5nfq1ElbtmzRggULNHfuXC1dulRPPfXU9S4dAAAAAPJNjn/H7Hpo0aKFWrRoccU+Hh4eCgkJyXbetm3b9MMPP2jNmjWqWbOmJOmDDz5Qy5Yt9fbbb6t48eL5XjMAAAAA5Leb/hqzJUuWKCgoSHfffbd69+6to0ePWvNWrlypgIAAK5RJUpMmTVSgQAGtXr36sutMTU1VSkqK0wQAAAAAdrmpg1nz5s31+eefa+HChXrjjTeUkJCgFi1aKD09XZKUlJSkoKAgp2VcXV0VGBiopKSky643Pj5e/v7+1hQaGnpd9wMAAAAArsTWUxmvpmPHjtbf4eHhioiIUPny5bVkyRI1btw4z+sdPHiw+vfvbz1OSUkhnAEAAACwzU19xOxS5cqVU5EiRbR7925JUkhIiA4fPuzUJy0tTceOHbvsdWnShevW/Pz8nCYAAAAAsMstFcz+/PNPHT16VMWKFZMkRUVF6cSJE1q3bp3VZ9GiRcrIyFDt2rXtKhMAAAAAcsXWUxlPnTplHf2SpD179mjjxo0KDAxUYGCghg8frvbt2yskJESJiYl64YUXVKFCBcXExEiSKleurObNm6tnz5768MMPdf78efXp00cdO3bkjowAAAAAbhm2HjFbu3atqlevrurVq0uS+vfvr+rVq2vo0KFycXHRpk2b9MADD6hixYrq0aOHatSooWXLlsnDw8Nax5QpU1SpUiU1btxYLVu2VP369TVhwgS7dgkAAAAAcs3WI2aNGjWSMeay8+fPn3/VdQQGBmrq1Kn5WRYAAAAA3FC31DVmAAAAAHA7IpgBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADazNZgtXbpUbdq0UfHixeVwODRnzhyn+cYYDR06VMWKFZOXl5eaNGmiXbt2OfU5duyYOnXqJD8/PwUEBKhHjx46derUDdwLAAAAALg2tgaz06dPq1q1aho7dmy289988029//77+vDDD7V69Wp5e3srJiZGZ8+etfp06tRJW7Zs0YIFCzR37lwtXbpUTz311I3aBQAAAAC4Zq52brxFixZq0aJFtvOMMRozZoxefvlltW3bVpL0+eefKzg4WHPmzFHHjh21bds2/fDDD1qzZo1q1qwpSfrggw/UsmVLvf322ypevPgN2xcAAAAAyKub9hqzPXv2KCkpSU2aNLHa/P39Vbt2ba1cuVKStHLlSgUEBFihTJKaNGmiAgUKaPXq1Zddd2pqqlJSUpwmAAAAALDLTRvMkpKSJEnBwcFO7cHBwda8pKQkBQUFOc13dXVVYGCg1Sc78fHx8vf3t6bQ0NB8rh4AAAAAcu6mDWbX0+DBg5WcnGxN+/fvt7skAAAAAHewmzaYhYSESJIOHTrk1H7o0CFrXkhIiA4fPuw0Py0tTceOHbP6ZMfDw0N+fn5OEwAAAADY5aYNZmXLllVISIgWLlxotaWkpGj16tWKioqSJEVFRenEiRNat26d1WfRokXKyMhQ7dq1b3jNAAAAAJAXtt6V8dSpU9q9e7f1eM+ePdq4caMCAwNVqlQpPf/883r11Vd11113qWzZshoyZIiKFy+uBx98UJJUuXJlNW/eXD179tSHH36o8+fPq0+fPurYsSN3ZAQAAABwy7A1mK1du1b33Xef9bh///6SpNjYWE2aNEkvvPCCTp8+raeeekonTpxQ/fr19cMPP8jT09NaZsqUKerTp48aN26sAgUKqH379nr//fdv+L4AAAAAQF7ZGswaNWokY8xl5zscDo0YMUIjRoy4bJ/AwEBNnTr1epQHAAAAADfETXuNGQAAAADcKQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNbupg9sorr8jhcDhNlSpVsuafPXtWcXFxKly4sHx8fNS+fXsdOnTIxooBAAAAIPdu6mAmSVWqVNHBgwet6eeff7bm9evXT999952mT5+uhIQEHThwQO3atbOxWgAAAADIPVe7C7gaV1dXhYSEZGlPTk7Wp59+qqlTp+r++++XJE2cOFGVK1fWqlWrVKdOnRtdKgAAAADkyU1/xGzXrl0qXry4ypUrp06dOmnfvn2SpHXr1un8+fNq0qSJ1bdSpUoqVaqUVq5cecV1pqamKiUlxWkCAAAAALvc1MGsdu3amjRpkn744QeNHz9ee/bsUYMGDXTy5EklJSXJ3d1dAQEBTssEBwcrKSnpiuuNj4+Xv7+/NYWGhl7HvQAAAACAK7upT2Vs0aKF9XdERIRq166t0qVL6+uvv5aXl1ee1zt48GD179/fepySkkI4AwAAAGCbm/qI2aUCAgJUsWJF7d69WyEhITp37pxOnDjh1OfQoUPZXpN2MQ8PD/n5+TlNAAAAAGCXWyqYnTp1SomJiSpWrJhq1KghNzc3LVy40Jq/Y8cO7du3T1FRUTZWCQAAAAC5c1OfyjhgwAC1adNGpUuX1oEDBzRs2DC5uLjosccek7+/v3r06KH+/fsrMDBQfn5+6tu3r6KiorgjIwAAAIBbyk0dzP7880899thjOnr0qIoWLar69etr1apVKlq0qCRp9OjRKlCggNq3b6/U1FTFxMRo3LhxNlcNAAAAALlzUwezadOmXXG+p6enxo4dq7Fjx96gigAAAAAg/91S15gBAAAAwO2IYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2Oy2CWZjx45VmTJl5Onpqdq1a+uXX36xuyQAAAAAyJHbIph99dVX6t+/v4YNG6b169erWrVqiomJ0eHDh+0uDQAAAACu6rYIZu+++6569uypbt26KSwsTB9++KEKFiyozz77zO7SAAAAAOCqXO0u4FqdO3dO69at0+DBg622AgUKqEmTJlq5cmW2y6Smpio1NdV6nJycLElKSUm5vsXm1Fm7C7DXTfM64PbBmLK7BNyOGFd2l4DbDWPK7hIsmbUYY27odm/5YPb3338rPT1dwcHBTu3BwcHavn17tsvEx8dr+PDhWdpDQ0OvS43IHf/X/e0uAbitMKaA/Me4AvLXzTimTp48KX//G1fXLR/M8mLw4MHq37+/9TgjI0PHjh1T4cKF5XA4bKzMfikpKQoNDdX+/fvl5+dndznALY8xBeQ/xhWQvxhTzowxOnnypIoXL35Dt3vLB7MiRYrIxcVFhw4dcmo/dOiQQkJCsl3Gw8NDHh4eTm0BAQHXq8Rbkp+fHwMTyEeMKSD/Ma6A/MWY+p8beaQs0y1/8w93d3fVqFFDCxcutNoyMjK0cOFCRUVF2VgZAAAAAOTMLX/ETJL69++v2NhY1axZU7Vq1dKYMWN0+vRpdevWze7SAAAAAOCqbotg9uijj+rIkSMaOnSokpKSFBkZqR9++CHLDUFwdR4eHho2bFiWUz0B5A1jCsh/jCsgfzGmbg4Oc6PvAwkAAAAAcHLLX2MGAAAAALc6ghkAAAAA2IxgBgAAAAA2I5jlUZkyZTRmzBi7y7jl7N27Vw6HQxs3brzu2+I1uvXwmuUN4wqXw+uVN4wpXAmvWd4wrnLA3MJiY2ONJNOrV68s85555hkjycTGxuZoXXv27DGSzIYNG3LU//Dhw+b06dM56tu6dWsTExOT7bylS5caSebXX3/N0bouZ/HixUaSOX78+DWt51JnzpwxhQoVMoULFzZnz57N1bKxsbGmbdu2Tm1paWnm4MGD5vz58/lW48SJE42/v3+W9ty8Rvnl3//+tyldurTx8PAwtWrVMqtXr76h288PjKv/YVz5Z2m/0eMqISHBtG7d2hQrVsxIMrNnz75h284vjKn/YUz5Z2m/0WPqtddeMzVr1jQ+Pj6maNGipm3btmb79u03bPv5hXH1P4wr/yztN3pcjRs3zoSHhxtfX1/j6+tr6tSpY77//vtcr+eWP2IWGhqqadOm6Z9//rHazp49q6lTp6pUqVL5vr1z585JkooWLaqCBQvmaJkePXpowYIF+vPPP7PMmzhxomrWrKmIiIh8rTOvjDFKS0uzHs+cOVNVqlRRpUqVNGfOnGtev4uLi0JCQuTqev1/qSE3r1F++Oqrr9S/f38NGzZM69evV7Vq1RQTE6PDhw/fsBryC+MqfzGu8u706dOqVq2axo4de8O2eT0wpvIXYyrvEhISFBcXp1WrVmnBggU6f/68mjVrptOnT9+wGvIL4yp/Ma7yrmTJknr99de1bt06rV27Vvfff7/atm2rLVu25G5F+RwYb6jMNF61alXzxRdfWO1TpkwxERERpm3btta3JfPmzTP16tUz/v7+JjAw0LRq1crs3r3bWkaS0xQdHe20jVdffdUUK1bMlClTxhhjTOnSpc3o0aONMRe+qXBzczNLly611vfGG2+YokWLmqSkJHP+/HkTHBxsRo4c6VT/yZMnjY+Pjxk/frwxxphly5aZ+vXrG09PT1OyZEnTt29fc+rUKav/2bNnzQsvvGBKlixp3N3dTfny5c0nn3xifdNz8ZS532fPnjV9+/Y1RYsWNR4eHqZevXrml19+sdaZ+S3L999/b+655x7j5uZmFi9ebM1v1KiR+fDDD8348eNN06ZNs7wGv/32m2nVqpXx9fU1Pj4+pn79+mb37t1m2LBhWWpavHix07dS6enppkSJEmbcuHFO61y/fr1xOBxm7969xhhj3nnnHVO1alVTsGBBU7JkSdO7d29z8uRJp/ovnoYNG5blNTLGmD/++MM88MADxtvb2/j6+ppHHnnEJCUlWfOHDRtmqlWrZj7//HNTunRp4+fnZx599FGTkpKSZb+zU6tWLRMXF2c9Tk9PN8WLFzfx8fE5Wv5mwbhiXN1M4+piuoWPmDGmGFM345gy5sKRBUkmISEhT8vbhXHFuLqZx5UxxhQqVMh88sknuVrmtghm7777rmncuLHV3rhxYzN69GinQTljxgwzc+ZMs2vXLrNhwwbTpk0bEx4ebtLT040xxvzyyy9Gkvnpp5/MwYMHzdGjR61t+Pj4mM6dO5vffvvN/Pbbb8aYrC/4wIEDTenSpc2JEyfM+vXrjbu7u/nmm2+c5pcvX95kZGRYbZ999pnx8vIyJ06cMLt37zbe3t5m9OjRZufOnWb58uWmevXqpmvXrlb/Dh06mNDQUDNr1iyTmJhofvrpJzNt2jSTlpZmZs6caSSZHTt2mIMHD5oTJ04YY4x59tlnTfHixc33339vtmzZYmJjY02hQoWs/ct8U0dERJgff/zR7N6925q3e/du4+HhYY4dO2aOHj1qPD09rYFijDF//vmnCQwMNO3atTNr1qwxO3bsMJ999pnZvn27OXnypOnQoYNp3ry5OXjwoDl48KBJTU3NcrrAgAEDTP369Z1e1//7v/9zahs9erRZtGiR2bNnj1m4cKG5++67Te/evY0xxqSmppoxY8YYPz8/azuZA/bi1yg9Pd1ERkaa+vXrm7Vr15pVq1aZGjVqWB++xlwYlD4+PqZdu3Zm8+bNZunSpSYkJMS89NJLl30PZkpNTTUuLi5Z/tHYpUsX88ADD1x1+ZsJ44pxdbOMq0vd6sGMMcWYutnGlDHG7Nq1y0gymzdvztPydmFcMa5u1nGVlpZmvvzyS+Pu7m62bNmSq2Vvi2B2+PBh4+HhYfbu3Wv27t1rPD09zZEjR5wG5aWOHDni9EF0ufOLY2NjTXBwsElNTXVqv3RQpqammsjISNOhQwcTFhZmevbs6dR/27Zt1jcGmRo0aGCeeOIJY4wxPXr0ME899ZTTMsuWLTMFChQw//zzj9mxY4eRZBYsWJDt/mR3fvGpU6eMm5ubmTJlitV27tw5U7x4cfPmm286LTdnzpws63zppZfMgw8+aD1u27at9U2EMcYMHjzYlC1b1pw7dy7bmrI7v/jS53nDhg3G4XCYP/74wxhjrG9QMr9Bys706dNN4cKFrceXO7/44tfoxx9/NC4uLmbfvn3W/C1bthhJ1rdHw4YNMwULFnT6dmTgwIGmdu3al60l019//WUkmRUrVji1Dxw40NSqVeuqy99MGFf/w7jyz9LvRo6rS93qwYwxxZi62cZUenq6adWqlalXr16ul7Ub4+p/GFf+WfrZMa42bdpkvL29jYuLi/H39zf//e9/c7xsplv+GjPpwnmkrVq10qRJkzRx4kS1atVKRYoUceqza9cuPfbYYypXrpz8/PxUpkwZSdK+ffuuuv7w8HC5u7tfsY+7u7umTJmimTNn6uzZsxo9erTT/EqVKqlu3br67LPPJEm7d+/WsmXL1KNHD0nSr7/+qkmTJsnHx8eaYmJilJGRoT179mjjxo1ycXFRdHR0Tp8WJSYm6vz586pXr57V5ubmplq1amnbtm1OfWvWrOn0OD09XZMnT9YTTzxhtT3xxBOaNGmSMjIyJEkbN25UgwYN5ObmluOaLhUZGanKlStr6tSpki6c+3748GE98sgjVp+ffvpJjRs3VokSJeTr66vOnTvr6NGjOnPmTI63s23bNoWGhio0NNRqCwsLU0BAgNNzUaZMGfn6+lqPixUrdkteI5YfGFfZY1z9D+MqdxhT2WNM/c+NHlNxcXH67bffNG3atFwve7NgXGWPcfU/N2pc3X333dq4caNWr16t3r17KzY2Vlu3bs3x8tJtdLv87t27a9KkSZo8ebK6d++eZX6bNm107Ngxffzxx1q9erVWr14t6X8Xcl6Jt7d3jmpYsWKFJOnYsWM6duxYlvk9evTQzJkzdfLkSU2cOFHly5e3BtmpU6fUq1cvbdy40Zp+/fVX7dq1S+XLl5eXl1eOasirS/dx/vz5+uuvv/Too4/K1dVVrq6u6tixo/744w8tXLhQkvKtpk6dOlmDcurUqWrevLkKFy4s6cKtVVu3bq2IiAjNnDlT69ats24CkJPXLrcu/YBxOBzWh9CVFClSRC4uLjp06JBT+6FDhxQSEpKvNd5IjKtrw7i6IK/j6nbEmLo2jKkL8mNM9enTR3PnztXixYtVsmTJ/CzvhmNcXRvG1QXXOq7c3d1VoUIF1ahRQ/Hx8apWrZree++9XNVw2wSz5s2b69y5czp//rxiYmKc5h09elQ7duzQyy+/rMaNG6ty5co6fvy4U5/Mb0PS09PztP3ExET169dPH3/8sWrXrq3Y2NgsL2aHDh1UoEABTZ06VZ9//rm6d+8uh8MhSbrnnnu0detWVahQIcvk7u6u8PBwZWRkKCEhIdvtZ1d/+fLl5e7uruXLl1tt58+f15o1axQWFnbF/fn000/VsWNHpw+JjRs3qmPHjvr0008lSREREVq2bJnOnz9/2Zpy8nw+/vjj+u2337Ru3TrNmDFDnTp1suatW7dOGRkZeuedd1SnTh1VrFhRBw4cyPV2KleurP3792v//v1W29atW3XixImrPhc54e7urho1algfWJKUkZGhhQsXKioq6prXbxfGFePqSq73uLodMaYYU1dyI8aUMUZ9+vTR7NmztWjRIpUtWzZf1msnxhXj6krs+n9VRkaGUlNTc7dQrk9+vIlcev5qcnKySU5Oth5nnl+cnp5uChcubJ544gmza9cus3DhQnPvvfc6Xa9w/vx54+XlZV599VWTlJRkXTiZ3Tmyxjifu5qWlmbq1Klj2rdvb4wx5sCBA6Zw4cLWObwX69GjhylUqJBxcXExf/31l9X+66+/Gi8vLxMXF2c2bNhgdu7caebMmeN0l7+uXbua0NBQM3v2bPP777+bxYsXm6+++soYc+EiTIfDYSZNmmQOHz5sXfz43HPPmeLFi5t58+Y5Xfh57NgxY0z25yUfPnzYuLm5mXnz5mWp//vvvzceHh7m6NGj5u+//zaFCxe2LvzcuXOn+fzzz63fQxk1apQpVaqU2b59uzly5Ig5d+7cZc/jrlevnqlWrZrx9fU1Z86csdo3btxoJJkxY8aYxMRE8/nnn5sSJUo41bx8+XLrot0jR45Yv1tx8WuUkZFhIiMjTYMGDcy6devM6tWrs73ws1q1ak51jR492pQuXTrL85CdadOmGQ8PDzNp0iSzdetW89RTT5mAgACnu/7cChhXjCtjbp5xdfLkSbNhwwazYcMGI8m8++67ZsOGDdY1CbcCxhRjypibZ0z17t3b+Pv7myVLllg3TDh48KDT/twKGFeMK2NunnE1aNAgk5CQYPbs2WM2bdpkBg0aZBwOh/nxxx9ztHym2yqYXeriCz8XLFhgKleubDw8PExERIRZsmRJlgvJP/74YxMaGmoKFCiQ5Vapl7r4BR8+fLgpVqyY+fvvv635M2fONO7u7mbjxo1Oy61YscJIMi1btsyyzl9++cU0bdrU+Pj4GG9vbxMREWFGjRplzf/nn39Mv379TLFixYy7u7upUKGC+eyzz6z5I0aMMCEhIcbhcFj7/c8//5i+ffuaIkWKXPFWqRcPyrffftsEBARke0FnamqqCQgIMO+9954x5sKHSbNmzUzBggWNr6+vadCggUlMTDTGXBjcmfujbG6VerFx48YZSaZLly5Ztvnuu++aYsWKGS8vLxMTE2M+//zzLDU//fTTpnDhwvlyq9SL5WZQGmPMBx98YEqVKmXc3d1NrVq1zKpVq3K87M2CccW4ynQzjKvsbocs5fyHY28GjCnGVKabYUxlN54kmYkTJ+Zo+ZsF44pxlelmGFfdu3c3pUuXNu7u7qZo0aKmcePGuQ5lxhjjMMaY3B1jAwAAAADkp9vmGjMAAAAAuFURzIAc2Ldvn9NtbC+dcnLLXQDOGFdA/mJMAfnvRo4rTmUEciAtLU179+697PwyZcrI1dX1xhUE3AYYV0D+YkwB+e9GjiuCGQAAAADYjFMZAQAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAd7RGjRrp+eeft7sMAMAdjmAGAMiTrl27yuFw6PXXX3dqnzNnjhwOR67WVaZMGY0ZMyYfq7t+9u7dK4fDoY0bN9pdCgDgNkIwAwDkmaenp9544w0dP37c7lJy7dy5c3aXkK/Onz9vdwkAgGtAMAMA5FmTJk0UEhKi+Pj4K/b7+eef1aBBA3l5eSk0NFTPPvusTp8+LenCqYR//PGH+vXrJ4fDIYfDIWOMihYtqhkzZljriIyMVLFixZzW6eHhoTNnzkiS9u3bp7Zt28rHx0d+fn7q0KGDDh06ZPV/5ZVXFBkZqU8++URly5aVp6dntrX+97//lb+/v6ZMmZKn5yQxMVFt27ZVcHCwfHx8dO+99+qnn36y5o8YMUJVq1bNslxkZKSGDBliPf7kk09UuXJleXp6qlKlSho3bpw1L/Oo3VdffaXo6Gh5enpqypQp+uOPP9SmTRsVKlRI3t7eqlKlir7//vs87QcA4MYimAEA8szFxUWvvfaaPvjgA/3555/Z9klMTFTz5s3Vvn17bdq0SV999ZV+/vln9enTR5I0a9YslSxZUiNGjNDBgwd18OBBORwONWzYUEuWLJEkHT9+XNu2bdM///yj7du3S5ISEhJ07733qmDBgsrIyFDbtm117NgxJSQkaMGCBfr999/16KOPOtWye/duzZw5U7Nmzcr2VMSpU6fqscce05QpU9SpU6c8PSenTp1Sy5YttXDhQm3YsEHNmzdXmzZttG/fPklS9+7dtW3bNq1Zs8ZaZsOGDdq0aZO6desmSZoyZYqGDh2qUaNGadu2bXrttdc0ZMgQTZ482WlbgwYN0nPPPadt27YpJiZGcXFxSk1N1dKlS7V582a98cYb8vHxydN+AABuLFe7CwAA3NoeeughRUZGatiwYfr000+zzI+Pj1enTp2sG2zcddddev/99xUdHa3x48crMDBQLi4u8vX1VUhIiLVco0aN9NFHH0mSli5dqurVqyskJERLlixRpUqVtGTJEkVHR0uSFi5cqM2bN2vPnj0KDQ2VJH3++eeqUqWK1qxZo3vvvVfShdMXP//8cxUtWjRLnWPHjtW//vUvfffdd9Z686JatWqqVq2a9XjkyJGaPXu2vv32W/Xp00clS5ZUTEyMJk6caNU1ceJERUdHq1y5cpKkYcOG6Z133lG7du0kSWXLltXWrVv10UcfKTY21lr3888/b/WRLhw1bN++vcLDwyXJWh8A4ObHETMAwDV74403NHnyZG3bti3LvF9//VWTJk2Sj4+PNcXExCgjI0N79uy57Dqjo6O1detWHTlyRAkJCWrUqJEaNWqkJUuW6Pz581qxYoUaNWokSdq2bZtCQ0OtUCZJYWFhCggIcKqpdOnS2YayGTNmqF+/flqwYME1hTLpwhGzAQMGqHLlygoICJCPj4+2bdtmHTGTpJ49e+rLL7/U2bNnde7cOU2dOlXdu3eXJJ0+fVqJiYnq0aOH03P26quvKjEx0WlbNWvWdHr87LPP6tVXX1W9evU0bNgwbdq06Zr2BQBw4xDMAADXrGHDhoqJidHgwYOzzDt16pR69eqljRs3WtOvv/6qXbt2qXz58pddZ3h4uAIDA5WQkOAUzBISErRmzRqdP39edevWzVWd3t7e2bZXr15dRYsW1WeffSZjTK7WeakBAwZo9uzZeu2117Rs2TJt3LhR4eHhTjcbadOmjTw8PDR79mx99913On/+vB5++GFJF54vSfr444+dnrPffvtNq1atuuL+PPnkk/r999/VuXNnbd68WTVr1tQHH3xwTfsDALgxOJURAJAvXn/9dUVGRuruu+92ar/nnnu0detWVahQ4bLLuru7Kz093anN4XCoQYMG+uabb7RlyxbVr19fBQsWVGpqqj766CPVrFnTCiaVK1fW/v37tX//fuuo2datW3XixAmFhYVdtfby5cvrnXfeUaNGjeTi4qJ///vfud19y/Lly9W1a1c99NBDki4Erb179zr1cXV1VWxsrCZOnCh3d3d17NhRXl5ekqTg4GAVL15cv//+e56ucwsNDdXTTz+tp59+WoMHD9bHH3+svn375nl/AAA3BsEMAJAvwsPD1alTJ73//vtO7S+++KLq1KmjPn366Mknn5S3t7e2bt2qBQsWWAGoTJkyWrp0qTp27CgPDw8VKVJE0oXrzP7v//5PNWvWtG5i0bBhQ02ZMkUDBw60ttGkSRNr+2PGjFFaWpqeeeYZRUdHZznd73IqVqyoxYsXq1GjRnJ1db3q76rt2LEjS1uVKlV01113adasWWrTpo0cDoeGDBmijIyMLH2ffPJJVa5cWdKFMHex4cOH69lnn5W/v7+aN2+u1NRUrV27VsePH1f//v0vW9Pzzz+vFi1aqGLFijp+/LgWL15sbQMAcHPjVEYAQL4ZMWJElhASERGhhIQE7dy5Uw0aNFD16tU1dOhQFS9e3Gm5vXv3qnz58k7XgEVHRys9Pd26lky6ENYubXM4HPrmm29UqFAhNWzYUE2aNFG5cuX01Vdf5ar+u+++W4sWLdKXX36p//u//7ti344dO6p69epO06FDh/Tuu++qUKFCqlu3rtq0aaOYmBjdc889WZa/6667VLduXVWqVEm1a9d2mvfkk0/qk08+0cSJExUeHq7o6GhNmjRJZcuWvWJN6enpiouLU+XKldW8eXNVrFjR6Tb7AICbl8Nc68n0AAAg14wxuuuuu/TMM89c8SgYAODOwKmMAADcYEeOHNG0adOUlJRk/XYZAODORjADAOAGCwoKUpEiRTRhwgQVKlTI7nIAADcBghkAADcYVxEAAC7FzT8AAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJv9P5KKOBMzm6wXAAAAAElFTkSuQmCC", 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    " + ] + }, + "metadata": {}, + "output_type": "display_data" + } + ], "source": [ - "## Modify Parameters\n", - "\n", - "We now modify the parallelization attributes of the first network layer to reduce its overall latency.\n", - "We now individually extract the `MatrixVectorActivation` blocks from the onnx file and set the config values manually (although this can be done automatically by Vivado tools also as mentioned in the introduction).\n", + "# Extracting LUTs from res_dict\n", + "LUTs_updated = [res_dict_updated[key][\"LUT\"] for key in res_dict_updated.keys()] \n", "\n", - "In the first step, we set the `PE` & `SIMD` values for all the layers to be '1' to establish a baseline and measure the estimated clock cycles and resource utilization for each of the individual layers.\n", + "#Plotting the bar graph of each network layer with their corresponding LUT resource utilization\n", + "fig = plt.figure(figsize = (10, 5))\n", + "plt.bar(res_dict_updated.keys(), LUTs_updated, color ='green', width = 0.3)\n", + "plt.xlabel(\"Network Layers\")\n", + "plt.ylabel(\"LUT Utilisation\")\n", + "plt.title(\"Estimated LUT values used for each network layer\")\n", + "plt.show()" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "From these numbers, we see that the first layer has been removed as the bottleneck and that the entire network can now perform one inference in ~4096 clock cycles (when the pipeline is full) as compared to the earlier configuration where it took ~38400 execution cycles.\n", "\n", - "We utilize from (`getCustomOp()`) as the helper function to set different properties of the node. The (`set_nodeattr()`) function within this function call helps us set these values." + "This decrease in execution latency of the network though comes at a cost of a 45% increase in LUT resource utilization for layer 1 of the network." + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "# Important Note : StreamingDataWidthConverters" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "Next to resources and performance, folding factors (or parallelization parameters) are influencing also other properties of the generated design. Since we are able to generate results in parallel, the data that gets feed into the layer needs to be packed in a specific format to provide the correct data at the correct time for the internal parallelism. Also, the data that comes out of a layer will be in a specific format depending on the internal parallelism." + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "To analyze the influence of the folding factors on the data streams between layers, we first will import the original model (with `PE=SIMD=1`) and then we will import the updated model, so that we can compare the two of them." ] }, { "cell_type": "code", - "execution_count": 14, + "execution_count": 17, "metadata": {}, "outputs": [], "source": [ - "fc_layers = model.get_nodes_by_op_type(\"MatrixVectorActivation\") \n", - "# (PE, SIMD, in_fifo_depth, out_fifo_depth, ramstyle) for each layer\n", - "config = [\n", - " (2, 5, [16], [64], \"block\"),\n", - " (1, 1, [64], [64], \"auto\"),#8,8\n", - " (1, 1, [64], [64], \"auto\"),#8,8\n", - " (1, 1, [64], [1], \"distributed\"),\n", - "]\n", - "for fcl, (pe, simd, ififo, ofifo, ramstyle) in zip(fc_layers, config):\n", - " fcl_inst = getCustomOp(fcl)\n", - " fcl_inst.set_nodeattr(\"PE\", pe)\n", - " fcl_inst.set_nodeattr(\"SIMD\", simd)\n", - " fcl_inst.set_nodeattr(\"inFIFODepths\", ififo)\n", - " fcl_inst.set_nodeattr(\"outFIFODepths\", ofifo)\n", - " fcl_inst.set_nodeattr(\"ram_style\", ramstyle)\n", - " num_inp_vec = fcl_inst.get_nodeattr(\"numInputVectors\")" + "model_orig = ModelWrapper(\"cybsec_PE_SIMD.onnx\")\n", + "model_updated = ModelWrapper(\"cybsec_PE_SIMD_modified.onnx\")" ] }, { "cell_type": "markdown", "metadata": {}, "source": [ - "We again save the model and view it. On expanding the first `MatrixVectorActivation` we can view the updated `PE` & `SIMD` parameters for that layer." + "In the next step we extract the information from all layers. For MVAUs the input shape is (1, MW/SIMD, SIMD) and the output shape is (1, MH/PE, PE)." ] }, { "cell_type": "code", - "execution_count": 16, - "metadata": { - "scrolled": true - }, + "execution_count": 25, + "metadata": {}, "outputs": [ { "name": "stdout", "output_type": "stream", "text": [ - "Stopping http://0.0.0.0:5901\n", - "Serving './cybsec_PE_SIMD_modified.onnx' at http://0.0.0.0:5901\n" + "In the original model (pe=simd=1): \n", + "Layer: MatrixVectorActivation_0\n", + "Input shape: (1, 600, 1)\n", + "Output shape: (1, 64, 1)\n", + "Layer: MatrixVectorActivation_1\n", + "Input shape: (1, 64, 1)\n", + "Output shape: (1, 64, 1)\n", + "Layer: MatrixVectorActivation_2\n", + "Input shape: (1, 64, 1)\n", + "Output shape: (1, 64, 1)\n", + "Layer: MatrixVectorActivation_3\n", + "Input shape: (1, 64, 1)\n", + "Output shape: (1, 1, 1)\n" ] - }, + } + ], + "source": [ + "# Original model\n", + "list_of_mvaus = model_orig.get_nodes_by_op_type(\"MatrixVectorActivation\")\n", + "print(\"In the original model (pe=simd=1): \")\n", + "for mvau in list_of_mvaus:\n", + " mvau_inst = getCustomOp(mvau)\n", + " print(\"Layer: \" + mvau.name)\n", + " print(\"Input shape: \" + str(mvau_inst.get_folded_input_shape()))\n", + " print(\"Output shape: \" + str(mvau_inst.get_folded_output_shape()))" + ] + }, + { + "cell_type": "code", + "execution_count": 26, + "metadata": {}, + "outputs": [ { - "data": { - "text/html": [ - "\n", - " \n", - " " - ], - "text/plain": [ - "" - ] - }, - "execution_count": 16, - "metadata": {}, - "output_type": "execute_result" + "name": "stdout", + "output_type": "stream", + "text": [ + "In the original model (pe=simd=1): \n", + "Layer: MatrixVectorActivation_0\n", + "Input shape: (1, 120, 5)\n", + "Output shape: (1, 32, 2)\n", + "Layer: MatrixVectorActivation_1\n", + "Input shape: (1, 64, 1)\n", + "Output shape: (1, 64, 1)\n", + "Layer: MatrixVectorActivation_2\n", + "Input shape: (1, 64, 1)\n", + "Output shape: (1, 64, 1)\n", + "Layer: MatrixVectorActivation_3\n", + "Input shape: (1, 64, 1)\n", + "Output shape: (1, 1, 1)\n" + ] } ], "source": [ - "model.save(\"./cybsec_PE_SIMD_modified.onnx\")\n", - "showInNetron(\"./cybsec_PE_SIMD_modified.onnx\",localhost_url='xirxlabs53')" + "# Updated model\n", + "list_of_mvaus = model_updated.get_nodes_by_op_type(\"MatrixVectorActivation\")\n", + "print(\"In the original model (pe=simd=1): \")\n", + "for mvau in list_of_mvaus:\n", + " mvau_inst = getCustomOp(mvau)\n", + " print(\"Layer: \" + mvau.name)\n", + " print(\"Input shape: \" + str(mvau_inst.get_folded_input_shape()))\n", + " print(\"Output shape: \" + str(mvau_inst.get_folded_output_shape()))" ] }, { "cell_type": "markdown", "metadata": {}, "source": [ - "From the above total folding formula, we have reduced the total folding of our layer from `600 x 64` to `120 x 32`. Hence, resulting in an estimated `10x` decrease in the execution latency of our layer. \n", - "This can be observed in the new estimated clock cycles." + "We can see that the input and output shape for MatrixVectorActivation_0 has changed after we have changed the folding factors. These changes have direct influence on the in/out stream width. We can have a closer look at the formula to calculate the stream width of an MVAU." ] }, { "cell_type": "code", - "execution_count": 17, - "metadata": { - "scrolled": true - }, - "outputs": [], + "execution_count": 30, + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + " def get_instream_width(self, ind=0):\n", + " i_bits = self.get_input_datatype().bitwidth()\n", + " in_width = i_bits * self.get_nodeattr(\"SIMD\")\n", + " return in_width\n", + "\n" + ] + } + ], "source": [ - "cycles_dict_updated = []\n", - "cycles_dict_updated = exp_cycles_per_layer(model)" + "showSrc(mvau_inst.get_instream_width)" ] }, { "cell_type": "code", - "execution_count": 18, + "execution_count": 31, "metadata": {}, "outputs": [ { - "data": { - "image/png": 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xYsWsayFzuqyr7d27V8YYvfLKK3rllVey7XPs2DFVrFhR48aNU+fOnXXPPfeodu3aateunXr27Kk6derkap3S5ZuYnDt37pqfQUZGhg4dOqRatWpZ7dndsTU7e/bs0c6dO2/43ZNy9j3ft2+fJOXoexAYGJgl0JUqVUpbtmzJUe1Xj9nM+U+dOiXp8n5LSkrSJ598ok8++STbZVy5fdfSvHlz63ThNWvWqEKFCqpfv77q1q2rNWvW6KGHHtLatWv1+OOPW/P88ccfCggIkLe3t8OyMk/fzhxXma73eY0fP15nzpzR4sWLb+oZlefPn9f48eM1bdo0HT582OHauyv/yOTr66tOnTpp5syZevXVVyVdPmWyYsWKVqjPy77N6XcSwK1DeANQ4MqXL6/4+HgtXbpUixcv1uLFizVt2jT16tVL06dPz/Nyr3WU4lrtmb/47Nu3T61bt1aNGjX07rvvKigoSB4eHvr+++81ceLELDccyU5GRoYeeughvfjii9lOv+eee3K4Fa7jkUce0RdffKH33nvP4SYi+aFXr156++23tXDhQnXv3l0zZ85Ux44dbxiibyTzs3zhhRcUHh6ebZ/MR1q0aNFC+/bt09dff60ffvhBn332mSZOnKiPPvpI/fr1u6k6ciKnRzgyMjIUGhqqd999N9vpmX+8yI/v+dVuNLZudv7Mmp588slrXheakzDdrFkzpaWlKS4uTmvWrLGuiWvevLnWrFmjXbt26fjx41Z7Xlzv8woPD9eSJUs0YcIEtWrVKssRzZwaPHiwpk2bpiFDhigsLMx6CHy3bt2yfH69evXS3LlztW7dOoWGhuqbb77RwIEDrbtD5mXfctQNKHwIbwBuCQ8PD3Xq1EmdOnVSRkaGBg4cqI8//livvPKKgoODr3naW0H49ttvlZqaqm+++cbhSMCVp5tlulZd1apV05kzZ9SmTZvrrqtSpUpavny5zpw543D07UZ3aLxyPdu2bctR3yvXea117Nq1S2XLllXJkiVVvHhx2e32HC9/8ODBCg4O1qhRo+Tj46OXXnop3+qvXbu27r33Xs2YMUOBgYE6ePCg3n///Twt60qZpywWLVr0hp+VJJUuXVpPPfWUnnrqKetmFmPGjMl1eCtXrpxKlChxzc+gSJEiWY4Q51S1atW0efNmtW7d+rrjJqff88zTGLdt25arZzMWhHLlysnb21vp6ek3/Lyut+2NGjWSh4eH1qxZozVr1mj48OGSLgf0Tz/9VMuXL7feZ6pUqZKWLVum06dPOxx927VrlzU9p5o0aaL+/furY8eOeuyxx7RgwQK5u+f+V6558+YpMjJS77zzjtV24cKFbO9W265dO5UrV04zZsxQ48aNde7cOfXs2dOanpt9C6Dw4po3AAXuxIkTDu+LFCli/YU389bmmc+0ys0t9PMq86//V5+CNG3atCx9S5YsmW1Njz/+uOLi4rR06dIs05KSkqzr6zp06KBLly453J49PT09SzC5lq5du2rz5s1asGBBlmnXOtpRoUIF1atXT9OnT3eofdu2bfrhhx/UoUMHSZc/hy5duujbb7/Vr7/+mqPlv/LKK3rhhRc0cuTIa95yPq/19+zZUz/88IMmTZqkMmXKZLl7YV72Rfny5dWqVSt9/PHHOnr0aJbpmc9ok7J+T728vBQcHJzl9vs54ebmprZt2+rrr792uK17YmKiZs6cqWbNmslut+d6udLl797hw4f16aefZpl2/vx5606VOf2et23bVt7e3ho/frwuXLjgMC2nR9Tyi5ubm7p27ar58+dnG9Sv/Lyu9zOjWLFiuu+++/Tll1/q4MGDDkfezp8/r8mTJ6tatWqqUKGCNU+HDh2Unp6uDz74wGFZEydOlM1my9HdNK/Upk0bzZo1S0uWLFHPnj3zfKTz6s/g/fffV3p6epa+7u7u6t69u+bMmaPo6GiFhoY6HEnLzb4FUHhx5A3ATVu8eLH11+kr3X///apatar69eunkydP6sEHH1RgYKD++OMPvf/++6pXr551PUm9evXk5uamt956S8nJyfL09LSeT5Xf2rZtax0JfPbZZ3XmzBl9+umnKl++fJZf8Bs0aKCpU6fqtddeU3BwsMqXL68HH3xQw4cP1zfffKOOHTuqd+/eatCggc6ePautW7dq3rx5OnDggMqWLatOnTqpadOmeumll3TgwAGFhIToq6++ytFNUaTLzw6bN2+eHnvsMfXp00cNGjTQyZMn9c033+ijjz5S3bp1s53v7bffVvv27RUWFqa+fftajwrw8fHRmDFjrH5vvPGGfvjhB7Vs2dK67fzRo0c1d+5crV27NtsHT7/99ttKTk5WVFSUvL29HW5gcTP1P/HEE3rxxRe1YMECDRgwwOFmNDezLz788EM1a9ZMoaGhevrpp1W1alUlJiYqLi5Of/75pzZv3ixJCgkJUatWrdSgQQOVLl1av/76q+bNm6dBgwZdc/uu57XXXlNMTIyaNWumgQMHyt3dXR9//LFSU1Nz/Gy07PTs2VNz5sxR//79tXLlSjVt2lTp6enatWuX5syZo6VLl6phw4Y5/p7b7XZNnDhR/fr103333acnnnhCpUqV0ubNm3Xu3LmbOrU5L958802tXLlSjRs31tNPP62QkBCdPHlSGzdu1LJly3Ty5ElJl48Y+vr66qOPPpK3t7dKliypxo0bW9dpNW/eXG+++aZ8fHwUGhoq6XKYr169unbv3q3evXs7rLdTp0564IEH9K9//UsHDhxQ3bp19cMPP+jrr7/WkCFDrvtIjGvp0qWLdYq43W7Xxx9/nKv5O3bsqP/+97/y8fFRSEiI4uLitGzZMuva3av16tVLkydP1sqVK63Hslwpp/sWQCF2a29uCeB2cr1HBeiKW3jPmzfPtG3b1pQvX954eHiYu+66yzz77LPm6NGjDsv79NNPTdWqVY2bm5vDYwOu9aiAuXPnZlvP1be9Hz16tJFkjh8/brV98803pk6dOqZYsWKmcuXK5q233jKff/65kWT2799v9UtISDARERHG29vbSHKo4/Tp02bkyJEmODjYeHh4mLJly5r777/f/Pvf/3Z4hMGJEydMz549jd1uNz4+PqZnz55m06ZNOXpUQOb8gwYNMhUrVjQeHh4mMDDQREZGWrf7zu72+MYYs2zZMtO0aVNTvHhxY7fbTadOncyOHTuyLP+PP/4wvXr1MuXKlTOenp6matWqJioqyqSmpl5zv6anp5vu3bsbd3d3s3Dhwpuq/0odOnQwksy6devydV/s27fP9OrVy/j7+5uiRYuaihUrmo4dO5p58+ZZfV577TXTqFEj4+vra4oXL25q1KhhXn/9dYfPMjvXelSAMcZs3LjRhIeHGy8vL1OiRAnzwAMPZNm2a31vr+fixYvmrbfeMrVq1TKenp6mVKlSpkGDBmbs2LEmOTnZ6pfT73lm3/vvv9/6vjRq1Mh8+eWX1vSWLVuaWrVqZaklMjIyy6M4siPJREVFZWmvVKmSw+3sjTEmMTHRREVFmaCgIFO0aFHj7+9vWrdubT755BOHfl9//bUJCQkx7u7uWT73RYsWGUlZHh3Sr18/I8n85z//yVLL6dOnzdChQ01AQIApWrSoufvuu83bb7/t8MiE623Ltb4LU6ZMMZLMCy+8kO2+uXK5Vz4q4NSpU+app54yZcuWNV5eXiY8PNzs2rUr232WqVatWqZIkSLmzz//zHZ6TvbttX7GAnA+mzG3+JwIAACu4W9/+5u2bt2qvXv3OrsUwCXde++9Kl26tHVdH4DbC9e8AQAKhaNHj2rRokUON1kAkHO//vqr4uPj1atXL2eXAqCAcOQNAOBU+/fv148//qjPPvtM69ev1759+3L8HDkAl29GtGHDBr3zzjv666+/9Pvvv+f58QQACjeOvAEAnCo2NlY9e/bU/v37NX36dIIbkEvz5s3TU089pbS0NH355ZcEN+A2xpE3AAAAAHABHHkDAAAAABdAeAMAAAAAF8BDunMgIyNDR44ckbe3t2w2m7PLAQAAAOAkxhidPn1aAQEBKlLk1h4LI7zlwJEjRxQUFOTsMgAAAAAUEocOHVJgYOAtXSfhLQe8vb0lXf6A7Ha7k6sBAAAA4CwpKSkKCgqyMsKtRHjLgcxTJe12O+ENAAAAgFMup+KGJQAAAADgAghvAAAAAOACCG8AAAAA4AIIbwAAAADgAghvAAAAAOACCG8AAAAA4AIIbwAAAADgAghvAAAAAOACCG8AAAAA4AIIbwAAAADgAghvAAAAAOACCG8AAAAA4AIIbwAAAADgAghvAAAAAOACCG8AAAAA4ALcnV0AABQGNpuzK3AuY5xdAW5HjCtnVwDgdsORNwAAAABwAYQ3AAAAAHABhDcAAAAAcAGENwAAAABwAYUmvL355puy2WwaMmSI1XbhwgVFRUWpTJky8vLyUteuXZWYmOgw38GDBxUREaESJUqofPnyGj58uC5duuTQZ9WqVapfv748PT0VHBys6OjoW7BFAAAAAJB/CkV4W79+vT7++GPVqVPHoX3o0KH69ttvNXfuXMXGxurIkSN65JFHrOnp6emKiIjQxYsXtW7dOk2fPl3R0dEaNWqU1Wf//v2KiIjQAw88oPj4eA0ZMkT9+vXT0qVLb9n2AQAAAMDNshnj3BvZnjlzRvXr19eUKVP02muvqV69epo0aZKSk5NVrlw5zZw5U48++qgkadeuXapZs6bi4uLUpEkTLV68WB07dtSRI0fk5+cnSfroo480YsQIHT9+XB4eHhoxYoQWLVqkbdu2Wevs1q2bkpKStGTJkhzVmJKSIh8fHyUnJ8tut+f/TgDgdNzS3NkV4HbEuHJ2BQAKgjOzgdOPvEVFRSkiIkJt2rRxaN+wYYPS0tIc2mvUqKG77rpLcXFxkqS4uDiFhoZawU2SwsPDlZKSou3bt1t9rl52eHi4tYzspKamKiUlxeEFAAAAAM7k1Id0z5o1Sxs3btT69euzTEtISJCHh4d8fX0d2v38/JSQkGD1uTK4ZU7PnHa9PikpKTp//ryKFy+eZd3jx4/X2LFj87xdAAAAAJDfnHbk7dChQ/rHP/6hGTNmqFixYs4qI1sjR45UcnKy9Tp06JCzSwIAAABwh3NaeNuwYYOOHTum+vXry93dXe7u7oqNjdXkyZPl7u4uPz8/Xbx4UUlJSQ7zJSYmyt/fX5Lk7++f5e6Tme9v1Mdut2d71E2SPD09ZbfbHV4AAAAA4ExOC2+tW7fW1q1bFR8fb70aNmyoHj16WP9ftGhRLV++3Jpn9+7dOnjwoMLCwiRJYWFh2rp1q44dO2b1iYmJkd1uV0hIiNXnymVk9slcBgAAAAC4Aqdd8+bt7a3atWs7tJUsWVJlypSx2vv27athw4apdOnSstvtGjx4sMLCwtSkSRNJUtu2bRUSEqKePXtqwoQJSkhI0Msvv6yoqCh5enpKkvr3768PPvhAL774ovr06aMVK1Zozpw5WrRo0a3dYAAAAAC4CU69YcmNTJw4UUWKFFHXrl2Vmpqq8PBwTZkyxZru5uam7777TgMGDFBYWJhKliypyMhIjRs3zupTpUoVLVq0SEOHDtV7772nwMBAffbZZwoPD3fGJgEAAABAnjj9OW+ugOe8Abc/nkfl7ApwO2JcObsCAAXhjn7OGwAAAADgxghvAAAAAOACCG8AAAAA4AIIbwAAAADgAghvAAAAAOACCG8AAAAA4AIIbwAAAADgAgr1Q7pxbTw7x9kVAAAAALcWR94AAAAAwAUQ3gAAAADABRDeAAAAAMAFEN4AAAAAwAUQ3gAAAADABRDeAAAAAMAFEN4AAAAAwAUQ3gAAAADABRDeAAAAAMAFEN4AAAAAwAUQ3gAAAADABRDeAAAAAMAFEN4AAAAAwAUQ3gAAAADABRDeAAAAAMAFEN4AAAAAwAUQ3gAAAADABRDeAAAAAMAFEN4AAAAAwAUQ3gAAAADABRDeAAAAAMAFEN4AAAAAwAUQ3gAAAADABRDeAAAAAMAFEN4AAAAAwAUQ3gAAAADABTg1vE2dOlV16tSR3W6X3W5XWFiYFi9ebE1v1aqVbDabw6t///4Oyzh48KAiIiJUokQJlS9fXsOHD9elS5cc+qxatUr169eXp6engoODFR0dfSs2DwAAAADyjbszVx4YGKg333xTd999t4wxmj59ujp37qxNmzapVq1akqSnn35a48aNs+YpUaKE9f/p6emKiIiQv7+/1q1bp6NHj6pXr14qWrSo3njjDUnS/v37FRERof79+2vGjBlavny5+vXrpwoVKig8PPzWbjAAAAAA5JHNGGOcXcSVSpcurbffflt9+/ZVq1atVK9ePU2aNCnbvosXL1bHjh115MgR+fn5SZI++ugjjRgxQsePH5eHh4dGjBihRYsWadu2bdZ83bp1U1JSkpYsWZLtclNTU5Wammq9T0lJUVBQkJKTk2W32/NvY2+CzebsCpyrcH1rcTtgTDm7AtyOGFfOrgBAQUhJSZGPj49TskGhueYtPT1ds2bN0tmzZxUWFma1z5gxQ2XLllXt2rU1cuRInTt3zpoWFxen0NBQK7hJUnh4uFJSUrR9+3arT5s2bRzWFR4erri4uGvWMn78ePn4+FivoKCg/NpMAAAAAMgTp542KUlbt25VWFiYLly4IC8vLy1YsEAhISGSpCeeeEKVKlVSQECAtmzZohEjRmj37t366quvJEkJCQkOwU2S9T4hIeG6fVJSUnT+/HkVL148S00jR47UsGHDrPeZR94AAAAAwFmcHt6qV6+u+Ph4JScna968eYqMjFRsbKxCQkL0zDPPWP1CQ0NVoUIFtW7dWvv27VO1atUKrCZPT095enoW2PIBAAAAILecftqkh4eHgoOD1aBBA40fP15169bVe++9l23fxo0bS5L27t0rSfL391diYqJDn8z3/v7+1+1jt9uzPeoGAAAAAIWR08Pb1TIyMhxuFnKl+Ph4SVKFChUkSWFhYdq6dauOHTtm9YmJiZHdbrdOvQwLC9Py5csdlhMTE+NwXR0AAAAAFHZOPW1y5MiRat++ve666y6dPn1aM2fO1KpVq7R06VLt27dPM2fOVIcOHVSmTBlt2bJFQ4cOVYsWLVSnTh1JUtu2bRUSEqKePXtqwoQJSkhI0Msvv6yoqCjrtMf+/fvrgw8+0Isvvqg+ffpoxYoVmjNnjhYtWuTMTQcAAACAXHFqeDt27Jh69eqlo0ePysfHR3Xq1NHSpUv10EMP6dChQ1q2bJkmTZqks2fPKigoSF27dtXLL79sze/m5qbvvvtOAwYMUFhYmEqWLKnIyEiH58JVqVJFixYt0tChQ/Xee+8pMDBQn332Gc94AwAAAOBSCt1z3gojZz7L4Vp4do6zK8DthjHl7ApwO2JcObsCAAWB57wBAAAAAK6L8AYAAAAALoDwBgAAAAAugPAGAAAAAC6A8AYAAAAALoDwBgAAAAAugPAGAAAAAC6A8AYAAAAALoDwBgAAAAAugPAGAAAAAC6A8AYAAAAALoDwBgAAAAAugPAGAAAAAC6A8AYAAAAALoDwBgAAAAAugPAGAAAAAC6A8AYAAAAALoDwBgAAAAAugPAGAAAAAC6A8AYAAAAALoDwBgAAAAAugPAGAAAAAC6A8AYAAAAALoDwBgAAAAAugPAGAAAAAC6A8AYAAAAALoDwBgAAAAAugPAGAAAAAC6A8AYAAAAALoDwBgAAAAAugPAGAAAAAC6A8AYAAAAALoDwBgAAAAAuwKnhberUqapTp47sdrvsdrvCwsK0ePFia/qFCxcUFRWlMmXKyMvLS127dlViYqLDMg4ePKiIiAiVKFFC5cuX1/Dhw3Xp0iWHPqtWrVL9+vXl6emp4OBgRUdH34rNAwAAAIB849TwFhgYqDfffFMbNmzQr7/+qgcffFCdO3fW9u3bJUlDhw7Vt99+q7lz5yo2NlZHjhzRI488Ys2fnp6uiIgIXbx4UevWrdP06dMVHR2tUaNGWX3279+viIgIPfDAA4qPj9eQIUPUr18/LV269JZvLwAAAADklc0YY5xdxJVKly6tt99+W48++qjKlSunmTNn6tFHH5Uk7dq1SzVr1lRcXJyaNGmixYsXq2PHjjpy5Ij8/PwkSR999JFGjBih48ePy8PDQyNGjNCiRYu0bds2ax3dunVTUlKSlixZkqOaUlJS5OPjo+TkZNnt9vzf6Dyw2ZxdgXMVrm8tbgeMKWdXgNsR48rZFQAoCM7MBoXmmrf09HTNmjVLZ8+eVVhYmDZs2KC0tDS1adPG6lOjRg3dddddiouLkyTFxcUpNDTUCm6SFB4erpSUFOvoXVxcnMMyMvtkLiM7qampSklJcXgBAAAAgDM5Pbxt3bpVXl5e8vT0VP/+/bVgwQKFhIQoISFBHh4e8vX1dejv5+enhIQESVJCQoJDcMucnjnten1SUlJ0/vz5bGsaP368fHx8rFdQUFB+bCoAAAAA5JnTw1v16tUVHx+vn3/+WQMGDFBkZKR27Njh1JpGjhyp5ORk63Xo0CGn1gMAAAAA7s4uwMPDQ8HBwZKkBg0aaP369Xrvvff097//XRcvXlRSUpLD0bfExET5+/tLkvz9/fXLL784LC/zbpRX9rn6DpWJiYmy2+0qXrx4tjV5enrK09MzX7YPAAAAAPKD04+8XS0jI0Opqalq0KCBihYtquXLl1vTdu/erYMHDyosLEySFBYWpq1bt+rYsWNWn5iYGNntdoWEhFh9rlxGZp/MZQAAAACAK3DqkbeRI0eqffv2uuuuu3T69GnNnDlTq1at0tKlS+Xj46O+fftq2LBhKl26tOx2uwYPHqywsDA1adJEktS2bVuFhISoZ8+emjBhghISEvTyyy8rKirKOnLWv39/ffDBB3rxxRfVp08frVixQnPmzNGiRYucuekAAAAAkCtODW/Hjh1Tr169dPToUfn4+KhOnTpaunSpHnroIUnSxIkTVaRIEXXt2lWpqakKDw/XlClTrPnd3Nz03XffacCAAQoLC1PJkiUVGRmpcePGWX2qVKmiRYsWaejQoXrvvfcUGBiozz77TOHh4bd8ewEAAAAgrwrdc94KI57zVvjwrUV+Y0w5uwLcjhhXzq4AQEHgOW8AAAAAgOsivAEAAACACyC8AQAAAIALILwBAAAAgAsgvAEAAACACyC8AQAAAIALILwBAAAAgAsgvAEAAACACyC8AQAAAIALILwBAAAAgAsgvAEAAACACyC8AQAAAIALILwBAAAAgAsgvAEAAACACyC8AQAAAIALILwBAAAAgAsgvAEAAACACyC8AQAAAIALILwBAAAAgAsgvAEAAACACyC8AQAAAIALILwBAAAAgAsgvAEAAACACyC8AQAAAIALILwBAAAAgAsgvAEAAACACyC8AQAAAIALILwBAAAAgAvIdXjbuHGjtm7dar3/+uuv1aVLF/3zn//UxYsX87U4AAAAAMBluQ5vzz77rH777TdJ0u+//65u3bqpRIkSmjt3rl588cV8LxAAAAAAkIfw9ttvv6levXqSpLlz56pFixaaOXOmoqOjNX/+/PyuDwAAAACgPIQ3Y4wyMjIkScuWLVOHDh0kSUFBQfrrr7/ytzoAAAAAgKQ8hLeGDRvqtdde03//+1/FxsYqIiJCkrR//375+fnle4EAAAAAgDyEt0mTJmnjxo0aNGiQ/vWvfyk4OFiSNG/ePN1///35XiAAAAAAIA/hrU6dOtq6dauSk5M1evRoq/3tt9/W9OnTc7Ws8ePH67777pO3t7fKly+vLl26aPfu3Q59WrVqJZvN5vDq37+/Q5+DBw8qIiJCJUqUUPny5TV8+HBdunTJoc+qVatUv359eXp6Kjg4WNHR0bnbcAAAAABwojw95y0pKUmfffaZRo4cqZMnT0qSduzYoWPHjuVqObGxsYqKitJPP/2kmJgYpaWlqW3btjp79qxDv6efflpHjx61XhMmTLCmpaenKyIiQhcvXtS6des0ffp0RUdHa9SoUVaf/fv3KyIiQg888IDi4+M1ZMgQ9evXT0uXLs3L5gMAAADALWczxpjczLBlyxa1bt1avr6+OnDggHbv3q2qVavq5Zdf1sGDB/XFF1/kuZjjx4+rfPnyio2NVYsWLSRdPvJWr149TZo0Kdt5Fi9erI4dO+rIkSPWNXcfffSRRowYoePHj8vDw0MjRozQokWLtG3bNmu+bt26KSkpSUuWLLlhXSkpKfLx8VFycrLsdnuety8/2WzOrsC5cvetBW6MMeXsCnA7Ylw5uwIABcGZ2SDXR96GDRump556Snv27FGxYsWs9g4dOmj16tU3VUxycrIkqXTp0g7tM2bMUNmyZVW7dm2NHDlS586ds6bFxcUpNDTU4WYp4eHhSklJ0fbt260+bdq0cVhmeHi44uLisq0jNTVVKSkpDi8AAAAAcCb33M6wfv16ffzxx1naK1asqISEhDwXkpGRoSFDhqhp06aqXbu21f7EE0+oUqVKCggI0JYtWzRixAjt3r1bX331lSQpISEhy10uM99n1nOtPikpKTp//ryKFy/uMG38+PEaO3ZsnrcFAAAAAPJbrsObp6dntkeifvvtN5UrVy7PhURFRWnbtm1au3atQ/szzzxj/X9oaKgqVKig1q1ba9++fapWrVqe13c9I0eO1LBhw6z3KSkpCgoKKpB1AQAAAEBO5Pq0yYcffljjxo1TWlqaJMlms+ngwYMaMWKEunbtmqciBg0apO+++04rV65UYGDgdfs2btxYkrR3715Jkr+/vxITEx36ZL739/e/bh+73Z7lqJt0OaDa7XaHFwAAAAA4U67D2zvvvKMzZ86ofPnyOn/+vFq2bKng4GB5e3vr9ddfz9WyjDEaNGiQFixYoBUrVqhKlSo3nCc+Pl6SVKFCBUlSWFiYtm7d6nCny5iYGNntdoWEhFh9li9f7rCcmJgYhYWF5apeAAAAAHCWXN9tMtPatWu1ZcsWnTlzRvXr189yQ5CcGDhwoGbOnKmvv/5a1atXt9p9fHxUvHhx7du3TzNnzlSHDh1UpkwZbdmyRUOHDlVgYKBiY2MlXX5UQL169RQQEKAJEyYoISFBPXv2VL9+/fTGG29IuvyogNq1aysqKkp9+vTRihUr9Nxzz2nRokUKDw+/YZ3cbbLw4Q5eyG+MKWdXgNsR48rZFQAoCM7MBnkOb/my8mv8VJ82bZp69+6tQ4cO6cknn9S2bdt09uxZBQUF6W9/+5tefvllhx31xx9/aMCAAVq1apVKliypyMhIvfnmm3J3/98lfatWrdLQoUO1Y8cOBQYG6pVXXlHv3r1zVCfhrfDhH0TkN8aUsyvA7Yhx5ewKABSEQh/eJk+enOMFPvfcczdVUGFEeCt8+AcR+Y0x5ewKcDtiXDm7AgAFodCHt5xciyZdPpL2+++/33RRhQ3hrfDhH0TkN8aUsyvA7Yhx5ewKABQEZ2aDHD0qYP/+/QVdBwAAAADgOnJ9t0kAAAAAwK2X6/DWtWtXvfXWW1naJ0yYoMceeyxfigIAAAAAOMp1eFu9erU6dOiQpb19+/ZavXp1vhQFAAAAAHCU6/B25swZeXh4ZGkvWrSoUlJS8qUoAAAAAICjXIe30NBQzZ49O0v7rFmzFBISki9FAQAAAAAc5ehuk1d65ZVX9Mgjj2jfvn168MEHJUnLly/Xl19+qblz5+Z7gQAAAACAPIS3Tp06aeHChXrjjTc0b948FS9eXHXq1NGyZcvUsmXLgqgRAAAAAO54OXpI952Oh3QXPnxrkd8YU86uALcjxpWzKwBQEJyZDXJ9zVtkZCR3lQQAAACAWyzX4S05OVlt2rTR3XffrTfeeEOHDx8uiLoAAAAAAFfIdXhbuHChDh8+rAEDBmj27NmqXLmy2rdvr3nz5iktLa0gagQAAACAO16uw5sklStXTsOGDdPmzZv1888/Kzg4WD179lRAQICGDh2qPXv25HedAAAAAHBHy1N4y3T06FHFxMQoJiZGbm5u6tChg7Zu3aqQkBBNnDgxv2oEAAAAgDtersNbWlqa5s+fr44dO6pSpUqaO3euhgwZoiNHjmj69OlatmyZ5syZo3HjxhVEvQAAAABwR8r1c94qVKigjIwMde/eXb/88ovq1auXpc8DDzwgX1/ffCgPAAAAACDlIbxNnDhRjz32mIoVK3bNPr6+vtq/f/9NFQYAAAAA+J8cnzaZnp6uLVu26NFHH80S3M6dO6ctW7YoIyMj3wsEAAAAAOQivP33v/9Vnz595OHhkWWah4eH+vTpo5kzZ+ZrcQAAAACAy3Ic3v7zn//ohRdekJubW5Zp7u7uevHFF/XJJ5/ka3EAAAAAgMtyHN52796tJk2aXHP6fffdp507d+ZLUQAAAAAARzkOb2fPnlVKSso1p58+fVrnzp3Ll6IAAAAAAI5yHN7uvvturVu37prT165dq7vvvjtfigIAAAAAOMpxeHviiSf08ssva8uWLVmmbd68WaNGjdITTzyRr8UBAAAAAC6zGWNMTjqmpaWpbdu2Wrt2rdq0aaMaNWpIknbt2qVly5apadOmiomJUdGiRQu0YGdISUmRj4+PkpOTZbfbnV2OJMlmc3YFzpWzby2Qc4wpZ1eA2xHjytkVACgIzswGOQ5v0uUAN3HiRM2cOVN79uyRMUb33HOPnnjiCQ0ZMiTbxwjcDghvhQ//ICK/MaacXQFuR4wrZ1cAoCC4THi7UxHeCh++tchvjClnV4DbEePK2RUAKAjOzAY5vuYNAAAAAOA8hDcAAAAAcAGENwAAAABwAYQ3AAAAAHABuQ5v27Ztu+a0hQsX3kwtAAAAAIBryHV4Cw8P1/79+7O0z58/Xz169MiXogAAAAAAjnId3vr166c2bdooISHBaps9e7Z69eql6OjoXC1r/Pjxuu++++Tt7a3y5curS5cu2r17t0OfCxcuKCoqSmXKlJGXl5e6du2qxMREhz4HDx5URESESpQoofLly2v48OG6dOmSQ59Vq1apfv368vT0VHBwcK5rBQAAAABnynV4Gzt2rDp06KA2bdro5MmTmjlzpp566il98cUXeuyxx3K1rNjYWEVFRemnn35STEyM0tLS1LZtW509e9bqM3ToUH377beaO3euYmNjdeTIET3yyCPW9PT0dEVEROjixYtat26dpk+frujoaI0aNcrqs3//fkVEROiBBx5QfHy8hgwZon79+mnp0qW53XwAAAAAcIo8P6S7R48eWr9+vQ4fPqyZM2eqc+fON13M8ePHVb58ecXGxqpFixZKTk5WuXLlNHPmTD366KOSpF27dqlmzZqKi4tTkyZNtHjxYnXs2FFHjhyRn5+fJOmjjz7SiBEjdPz4cXl4eGjEiBFatGiRw/V63bp1U1JSkpYsWXLDunhId+HDg0+R3xhTzq4AtyPGlbMrAFAQnJkN3HPS6ZtvvsnS9sgjj2jNmjXq3r27bDab1efhhx/OczHJycmSpNKlS0uSNmzYoLS0NLVp08bqU6NGDd11111WeIuLi1NoaKgV3KTL1+UNGDBA27dv17333qu4uDiHZWT2GTJkSLZ1pKamKjU11XqfkpKS520CAAAAgPyQo/DWpUuXa077/PPP9fnnn0uSbDab0tPT81RIRkaGhgwZoqZNm6p27dqSpISEBHl4eMjX19ehr5+fn3XNXUJCgkNwy5yeOe16fVJSUnT+/HkVL17cYdr48eM1duzYPG0HAAAAABSEHF3zlpGRkaNXXoObJEVFRWnbtm2aNWtWnpeRX0aOHKnk5GTrdejQIWeXBAAAAOAOl6MjbwVt0KBB+u6777R69WoFBgZa7f7+/rp48aKSkpIcjr4lJibK39/f6vPLL784LC/zbpRX9rn6DpWJiYmy2+1ZjrpJkqenpzw9PfNl2wAAAAAgP+T6bpPPPfecJk+enKX9gw8+uOY1ZNdijNGgQYO0YMECrVixQlWqVHGY3qBBAxUtWlTLly+32nbv3q2DBw8qLCxMkhQWFqatW7fq2LFjVp+YmBjZ7XaFhIRYfa5cRmafzGUAAAAAQGGX6/A2f/58NW3aNEv7/fffr3nz5uVqWVFRUfq///s/zZw5U97e3kpISFBCQoLOnz8vSfLx8VHfvn01bNgwrVy5Uhs2bNBTTz2lsLAwNWnSRJLUtm1bhYSEqGfPntq8ebOWLl2ql19+WVFRUdbRs/79++v333/Xiy++qF27dmnKlCmaM2eOhg4dmtvNBwAAAACnyPWjAooVK6Zt27YpODjYoX3v3r2qXbu2Lly4kPOVX+MewtOmTVPv3r0lXX5I9/PPP68vv/xSqampCg8P15QpU6xTIiXpjz/+0IABA7Rq1SqVLFlSkZGRevPNN+Xu/r+zQletWqWhQ4dqx44dCgwM1CuvvGKt40Z4VEDhw+2Xkd8YU86uALcjxpWzKwBQEJyZDXId3mrXrq3+/ftr0KBBDu3vv/++pk6dqh07duRrgYUB4a3w4R9E5DfGlLMrwO2IceXsCgAUhEL/nLcrDRs2TIMGDdLx48f14IMPSpKWL1+ud955R5MmTcrv+gAAAAAAykN469Onj1JTU/X666/r1VdflSRVrlxZU6dOVa9evfK9QAAAAABAHk6bvNLx48dVvHhxeXl55WdNhQ6nTRY+nIqC/MaYcnYFuB0xrpxdAYCC4FKnTWY6fvy4du/eLUmqUaOGypYtm29FAQAAAAAc5fpRAWfPnlWfPn1UoUIFtWjRQi1atFCFChXUt29fnTt3riBqBAAAAIA7Xq7D27BhwxQbG6tvv/1WSUlJSkpK0tdff63Y2Fg9//zzBVEjAAAAANzxcn3NW9myZTVv3jy1atXKoX3lypV6/PHHdfz48fysr1DgmrfCh+sIkN8YU86uALcjxpWzKwBQEJyZDXJ95O3cuXPy8/PL0l6+fHlOmwQAAACAApLr8BYWFqbRo0frwoULVtv58+c1duxYhYWF5WtxAAAAAIDLcn23yffee0/h4eEKDAxU3bp1JUmbN29WsWLFtHTp0nwvEAAAAACQh/BWu3Zt7dmzRzNmzNCuXbskSd27d1ePHj1UvHjxfC8QAAAAAJDH57yVKFFCTz/9dH7XAgAAAAC4hhyFt2+++SbHC3z44YfzXAwAAAAAIHs5Cm9dunTJ0cJsNpvS09Nvph4AAAAAQDZyFN4yMjIKug4AAAAAwHXk+lEBAAAAAIBbL8fhbcWKFQoJCVFKSkqWacnJyapVq5ZWr16dr8UBAAAAAC7LcXibNGmSnn76adnt9izTfHx89Oyzz2rixIn5WhwAAAAA4LIch7fNmzerXbt215zetm1bbdiwIV+KAgAAAAA4ynF4S0xMVNGiRa853d3dXcePH8+XogAAAAAAjnIc3ipWrKht27Zdc/qWLVtUoUKFfCkKAAAAAOAox+GtQ4cOeuWVV3ThwoUs086fP6/Ro0erY8eO+VocAAAAAOAymzHG5KRjYmKi6tevLzc3Nw0aNEjVq1eXJO3atUsffvih0tPTtXHjRvn5+RVowc6QkpIiHx8fJScnZ3vDFmew2ZxdgXPl7FsL5BxjytkV4HbEuHJ2BQAKgjOzQY4e0i1Jfn5+WrdunQYMGKCRI0cqM/PZbDaFh4frww8/vC2DGwAAAAAUBjkOb5JUqVIlff/99zp16pT27t0rY4zuvvtulSpVqqDqAwAAAAAol+EtU6lSpXTffffldy0AAAAAgGvI8Q1LAAAAAADOQ3gDAAAAABdAeAMAAAAAF0B4AwAAAAAXQHgDAAAAABdAeAMAAAAAF0B4AwAAAAAXQHgDAAAAABfg1PC2evVqderUSQEBAbLZbFq4cKHD9N69e8tmszm82rVr59Dn5MmT6tGjh+x2u3x9fdW3b1+dOXPGoc+WLVvUvHlzFStWTEFBQZowYUJBbxoAAAAA5CunhrezZ8+qbt26+vDDD6/Zp127djp69Kj1+vLLLx2m9+jRQ9u3b1dMTIy+++47rV69Ws8884w1PSUlRW3btlWlSpW0YcMGvf322xozZow++eSTAtsuAAAAAMhv7s5cefv27dW+ffvr9vH09JS/v3+203bu3KklS5Zo/fr1atiwoSTp/fffV4cOHfTvf/9bAQEBmjFjhi5evKjPP/9cHh4eqlWrluLj4/Xuu+86hLwrpaamKjU11XqfkpKSxy0EAAAAgPxR6K95W7VqlcqXL6/q1atrwIABOnHihDUtLi5Ovr6+VnCTpDZt2qhIkSL6+eefrT4tWrSQh4eH1Sc8PFy7d+/WqVOnsl3n+PHj5ePjY72CgoIKaOsAAAAAIGcKdXhr166dvvjiCy1fvlxvvfWWYmNj1b59e6Wnp0uSEhISVL58eYd53N3dVbp0aSUkJFh9/Pz8HPpkvs/sc7WRI0cqOTnZeh06dCi/Nw0AAAAAcsWpp03eSLdu3az/Dw0NVZ06dVStWjWtWrVKrVu3LrD1enp6ytPTs8CWDwAAAAC5VaiPvF2tatWqKlu2rPbu3StJ8vf317Fjxxz6XLp0SSdPnrSuk/P391diYqJDn8z317qWDgAAAAAKG5cKb3/++adOnDihChUqSJLCwsKUlJSkDRs2WH1WrFihjIwMNW7c2OqzevVqpaWlWX1iYmJUvXp1lSpV6tZuAAAAAADkkVPD25kzZxQfH6/4+HhJ0v79+xUfH6+DBw/qzJkzGj58uH766ScdOHBAy5cvV+fOnRUcHKzw8HBJUs2aNdWuXTs9/fTT+uWXX/Tjjz9q0KBB6tatmwICAiRJTzzxhDw8PNS3b19t375ds2fP1nvvvadhw4Y5a7MBAAAAINdsxhjjrJWvWrVKDzzwQJb2yMhITZ06VV26dNGmTZuUlJSkgIAAtW3bVq+++qrDDUhOnjypQYMG6dtvv1WRIkXUtWtXTZ48WV5eXlafLVu2KCoqSuvXr1fZsmU1ePBgjRgxIsd1pqSkyMfHR8nJybLb7Te30fnEZnN2Bc7lvG8tbleMKWdXgNsR48rZFQAoCM7MBk4Nb66C8Fb48K1FfmNMObsC3I4YV86uAEBBcGY2cKlr3gAAAADgTkV4AwAAAAAXQHgDAAAAABdAeAMAAAAAF0B4AwAAAAAXQHgDAAAAABdAeAMAAAAAF0B4AwAAAAAXQHgDAAAAABdAeAMAAAAAF0B4AwAAAAAXQHgDAAAAABdAeAMAAAAAF0B4AwAAAAAXQHgDAAAAABdAeAMAAAAAF0B4AwAAAAAXQHgDAAAAABdAeAMAAAAAF0B4AwAAAAAXQHgDAAAAABdAeAMAAAAAF0B4AwAAAAAXQHgDAAAAABdAeAMAAAAAF0B4AwAAAAAXQHgDAAAAABdAeAMAAAAAF0B4AwAAAAAXQHgDAAAAABdAeAMAAAAAF0B4AwAAAAAXQHgDAAAAABfg1PC2evVqderUSQEBAbLZbFq4cKHDdGOMRo0apQoVKqh48eJq06aN9uzZ49Dn5MmT6tGjh+x2u3x9fdW3b1+dOXPGoc+WLVvUvHlzFStWTEFBQZowYUJBbxoAAAAA5CunhrezZ8+qbt26+vDDD7OdPmHCBE2ePFkfffSRfv75Z5UsWVLh4eG6cOGC1adHjx7avn27YmJi9N1332n16tV65plnrOkpKSlq27atKlWqpA0bNujtt9/WmDFj9MknnxT49gEAAABAfrEZY4yzi5Akm82mBQsWqEuXLpIuH3ULCAjQ888/rxdeeEGSlJycLD8/P0VHR6tbt27auXOnQkJCtH79ejVs2FCStGTJEnXo0EF//vmnAgICNHXqVP3rX/9SQkKCPDw8JEkvvfSSFi5cqF27duWotpSUFPn4+Cg5OVl2uz3/Nz4PbDZnV+BcheNbi9sJY8rZFeB2xLhydgUACoIzs0GhveZt//79SkhIUJs2baw2Hx8fNW7cWHFxcZKkuLg4+fr6WsFNktq0aaMiRYro559/tvq0aNHCCm6SFB4ert27d+vUqVPZrjs1NVUpKSkOLwAAAABwpkIb3hISEiRJfn5+Du1+fn7WtISEBJUvX95huru7u0qXLu3QJ7tlXLmOq40fP14+Pj7WKygo6OY3CAAAAABuQqENb840cuRIJScnW69Dhw45uyQAAAAAd7hCG978/f0lSYmJiQ7tiYmJ1jR/f38dO3bMYfqlS5d08uRJhz7ZLePKdVzN09NTdrvd4QUAAAAAzlRow1uVKlXk7++v5cuXW20pKSn6+eefFRYWJkkKCwtTUlKSNmzYYPVZsWKFMjIy1LhxY6vP6tWrlZaWZvWJiYlR9erVVapUqVu0NQAAAABwc5wa3s6cOaP4+HjFx8dLunyTkvj4eB08eFA2m01DhgzRa6+9pm+++UZbt25Vr169FBAQYN2RsmbNmmrXrp2efvpp/fLLL/rxxx81aNAgdevWTQEBAZKkJ554Qh4eHurbt6+2b9+u2bNn67333tOwYcOctNUAAAAAkHtOfVTAqlWr9MADD2Rpj4yMVHR0tIwxGj16tD755BMlJSWpWbNmmjJliu655x6r78mTJzVo0CB9++23KlKkiLp27arJkyfLy8vL6rNlyxZFRUVp/fr1Klu2rAYPHqwRI0bkuE4eFVD4cPtl5DfGlLMrwO2IceXsCgAUBGdmg0LznLfCjPBW+PCtRX5jTDm7AtyOGFfOrgBAQeA5bwAAAACA6yK8AQAAAIALILwBAAAAgAsgvAEAAACACyC8AQAAAIALILwBAAAAgAsgvAEAAACACyC8AQAAAIALILwBAAAAgAsgvAEAAACACyC8AQAAAIALILwBAAAAgAsgvAEAAACACyC8AQAAAIALILwBAAAAgAsgvAEAAACACyC8AQAAAIALILwBAAAAgAsgvAEAAACACyC8AQAAAIALILwBAAAAgAsgvAEAAACACyC8AQAAAIALILwBAAAAgAsgvAEAAACACyC8AQAAAIALILwBAAAAgAsgvAEAAACACyC8AQAAAIALILwBAAAAgAsgvAEAAACACyC8AQAAAIALILwBAAAAgAsgvAEAAACACyjU4W3MmDGy2WwOrxo1aljTL1y4oKioKJUpU0ZeXl7q2rWrEhMTHZZx8OBBRUREqESJEipfvryGDx+uS5cu3epNAQAAAICb4u7sAm6kVq1aWrZsmfXe3f1/JQ8dOlSLFi3S3Llz5ePjo0GDBumRRx7Rjz/+KElKT09XRESE/P39tW7dOh09elS9evVS0aJF9cYbb9zybQEAAACAvCr04c3d3V3+/v5Z2pOTk/Wf//xHM2fO1IMPPihJmjZtmmrWrKmffvpJTZo00Q8//KAdO3Zo2bJl8vPzU7169fTqq69qxIgRGjNmjDw8PG715gAAAABAnhTq0yYlac+ePQoICFDVqlXVo0cPHTx4UJK0YcMGpaWlqU2bNlbfGjVq6K677lJcXJwkKS4uTqGhofLz87P6hIeHKyUlRdu3b7/mOlNTU5WSkuLwAgAAAABnKtThrXHjxoqOjtaSJUs0depU7d+/X82bN9fp06eVkJAgDw8P+fr6Oszj5+enhIQESVJCQoJDcMucnjntWsaPHy8fHx/rFRQUlL8bBgAAAAC5VKhPm2zfvr31/3Xq1FHjxo1VqVIlzZkzR8WLFy+w9Y4cOVLDhg2z3qekpBDgAAAAADhVoT7ydjVfX1/dc8892rt3r/z9/XXx4kUlJSU59ElMTLSukfP3989y98nM99ldR5fJ09NTdrvd4QUAAAAAzuRS4e3MmTPat2+fKlSooAYNGqho0aJavny5NX337t06ePCgwsLCJElhYWHaunWrjh07ZvWJiYmR3W5XSEjILa8fAAAAAPKqUJ82+cILL6hTp06qVKmSjhw5otGjR8vNzU3du3eXj4+P+vbtq2HDhql06dKy2+0aPHiwwsLC1KRJE0lS27ZtFRISop49e2rChAlKSEjQyy+/rKioKHl6ejp56wAAAAAg5wp1ePvzzz/VvXt3nThxQuXKlVOzZs30008/qVy5cpKkiRMnqkiRIuratatSU1MVHh6uKVOmWPO7ubnpu+++04ABAxQWFqaSJUsqMjJS48aNc9YmAQAAAECe2IwxxtlFFHYpKSny8fFRcnJyobn+zWZzdgXOxbcW+Y0x5ewKcDtiXDm7AgAFwZnZwKWueQMAAACAOxXhDQAAAABcAOENAAAAAFwA4Q0AAAAAXADhDQAAAABcAOENAAAAAFwA4Q0AAAAAXADhDQAAAABcAOENAAAAAFwA4Q0AAAAAXADhDQAAAABcAOENAAAAAFwA4Q0AAAAAXADhDQAAAABcAOENAAAAAFwA4Q0AAAAAXADhDQAAAABcAOENAAAAAFwA4Q0AAAAAXADhDQAAAABcAOENAAAAAFwA4Q0AAAAAXADhDQAAAABcAOENAAAAAFwA4Q0AAAAAXADhDQAAAABcAOENAAAAAFwA4Q0AAAAAXADhDQAAAABcAOENAAAAAFwA4Q0AAAAAXADhDQAAAABcgLuzCwAAAABwYzabsytwLmOcXYHzceQNAAAAAFzAHRXePvzwQ1WuXFnFihVT48aN9csvvzi7JAAAAADIkTsmvM2ePVvDhg3T6NGjtXHjRtWtW1fh4eE6duyYs0sDAAAAgBu6Y8Lbu+++q6efflpPPfWUQkJC9NFHH6lEiRL6/PPPnV0aAAAAANzQHXHDkosXL2rDhg0aOXKk1VakSBG1adNGcXFxWfqnpqYqNTXVep+cnCxJSklJKfhikSN8FED+YkwB+Y9xBeSvwjKmMjOBccIdVO6I8PbXX38pPT1dfn5+Du1+fn7atWtXlv7jx4/X2LFjs7QHBQUVWI3IHR8fZ1cA3F4YU0D+Y1wB+auwjanTp0/L5xYXdUeEt9waOXKkhg0bZr3PyMjQyZMnVaZMGdnu9Hu06vJfG4KCgnTo0CHZ7XZnlwO4PMYUkP8YV0D+Ykz9jzFGp0+fVkBAwC1f9x0R3sqWLSs3NzclJiY6tCcmJsrf3z9Lf09PT3l6ejq0+fr6FmSJLslut9/xgxfIT4wpIP8xroD8xZi67FYfcct0R9ywxMPDQw0aNNDy5cuttoyMDC1fvlxhYWFOrAwAAAAAcuaOOPImScOGDVNkZKQaNmyoRo0aadKkSTp79qyeeuopZ5cGAAAAADd0x4S3v//97zp+/LhGjRqlhIQE1atXT0uWLMlyExPcmKenp0aPHp3l1FIAecOYAvIf4wrIX4ypwsFmnHGPSwAAAABArtwR17wBAAAAgKsjvAEAAACACyC8AQAAAIALILwVoMqVK2vSpEnOLsPlHDhwQDabTfHx8QW+Lj4j18NnljeMK1wLn1feMKZwPXxmecO4ygFzm4uMjDSSzLPPPptl2sCBA40kExkZmaNl7d+/30gymzZtylH/Y8eOmbNnz+aob8eOHU14eHi201avXm0kmc2bN+doWdeycuVKI8mcOnXqppZztXPnzplSpUqZMmXKmAsXLuRq3sjISNO5c2eHtkuXLpmjR4+atLS0fKtx2rRpxsfHJ0t7bj6j/PLBBx+YSpUqGU9PT9OoUSPz888/39L15wfG1f8wrnyytN/qcRUbG2s6duxoKlSoYCSZBQsW3LJ15xfG1P8wpnyytN/qMfXGG2+Yhg0bGi8vL1OuXDnTuXNns2vXrlu2/vzCuPofxpVPlvZbPa6mTJliQkNDjbe3t/H29jZNmjQx33//fa6Xc0cceQsKCtKsWbN0/vx5q+3ChQuaOXOm7rrrrnxf38WLFyVJ5cqVU4kSJXI0T9++fRUTE6M///wzy7Rp06apYcOGqlOnTr7WmVfGGF26dMl6P3/+fNWqVUs1atTQwoULb3r5bm5u8vf3l7t7wT/JIjefUX6YPXu2hg0bptGjR2vjxo2qW7euwsPDdezYsVtWQ35hXOUvxlXenT17VnXr1tWHH354y9ZZEBhT+YsxlXexsbGKiorSTz/9pJiYGKWlpalt27Y6e/bsLashvzCu8hfjKu8CAwP15ptvasOGDfr111/14IMPqnPnztq+fXvuFpTPobLQyUz1tWvXNv/3f/9ntc+YMcPUqVPHdO7c2fqry+LFi03Tpk2Nj4+PKV26tImIiDB79+615pHk8GrZsqXDOl577TVToUIFU7lyZWOMMZUqVTITJ040xlz+i0fRokXN6tWrreW99dZbply5ciYhIcGkpaUZPz8/8+qrrzrUf/r0aePl5WWmTp1qjDFmzZo1plmzZqZYsWImMDDQDB482Jw5c8bqf+HCBfPiiy+awMBA4+HhYapVq2Y+++wz6y9GV74yt/vChQtm8ODBply5csbT09M0bdrU/PLLL9YyM/9a8/3335v69eubokWLmpUrV1rTW7VqZT766CMzdepU89BDD2X5DLZt22YiIiKMt7e38fLyMs2aNTN79+41o0ePzlLTypUrHf66lZ6ebipWrGimTJnisMyNGzcam81mDhw4YIwx5p133jG1a9c2JUqUMIGBgWbAgAHm9OnTDvVf+Ro9enSWz8gYY/744w/z8MMPm5IlSxpvb2/z2GOPmYSEBGv66NGjTd26dc0XX3xhKlWqZOx2u/n73/9uUlJSsmx3dho1amSioqKs9+np6SYgIMCMHz8+R/MXFowrxlVhGldXkgsfeWNMMaYK45gy5vIRCkkmNjY2T/M7C+OKcVWYx5UxxpQqVcp89tlnuZrnjglv7777rmndurXV3rp1azNx4kSHgTtv3jwzf/58s2fPHrNp0ybTqVMnExoaatLT040xxvzyyy9Gklm2bJk5evSoOXHihLUOLy8v07NnT7Nt2zazbds2Y0zWL8Xw4cNNpUqVTFJSktm4caPx8PAwX3/9tcP0atWqmYyMDKvt888/N8WLFzdJSUlm7969pmTJkmbixInmt99+Mz/++KO59957Te/eva3+jz/+uAkKCjJfffWV2bdvn1m2bJmZNWuWuXTpkpk/f76RZHbv3m2OHj1qkpKSjDHGPPfccyYgIMB8//33Zvv27SYyMtKUKlXK2r7ML36dOnXMDz/8YPbu3WtN27t3r/H09DQnT540J06cMMWKFbMGkzHG/Pnnn6Z06dLmkUceMevXrze7d+82n3/+udm1a5c5ffq0efzxx027du3M0aNHzdGjR01qamqWUxNeeOEF06xZM4fP9fnnn3domzhxolmxYoXZv3+/Wb58ualevboZMGCAMcaY1NRUM2nSJGO32631ZA7qKz+j9PR0U69ePdOsWTPz66+/mp9++sk0aNDA+gFtzOWB6+XlZR555BGzdetWs3r1auPv72/++c9/XvM7mCk1NdW4ubll+cWyV69e5uGHH77h/IUJ44pxVVjG1dVcPbwxphhThW1MGWPMnj17jCSzdevWPM3vLIwrxlVhHVeXLl0yX375pfHw8DDbt2/P1bx3THg7duyY8fT0NAcOHDAHDhwwxYoVM8ePH3cYuFc7fvy4ww+ra53vHBkZafz8/ExqaqpD+9UDNzU11dSrV888/vjjJiQkxDz99NMO/Xfu3Gn95SFT8+bNzZNPPmmMMaZv377mmWeecZhnzZo1pkiRIub8+fNm9+7dRpKJiYnJdnuyO9/5zJkzpmjRombGjBlW28WLF01AQICZMGGCw3wLFy7Mssx//vOfpkuXLtb7zp07W3/RMMaYkSNHmipVqpiLFy9mW1N25ztfvZ83bdpkbDab+eOPP4wxxvpLTOZforIzd+5cU6ZMGev9tc53vvIz+uGHH4ybm5s5ePCgNX379u1GkvVXqNGjR5sSJUo4/JVl+PDhpnHjxtesJdPhw4eNJLNu3TqH9uHDh5tGjRrdcP7ChHH1P4wrnyz9buW4upqrhzfGFGOqsI2p9PR0ExERYZo2bZrreZ2NcfU/jCufLP2cMa62bNliSpYsadzc3IyPj49ZtGhRjufNdEdc8yZdPq81IiJC0dHRmjZtmiIiIlS2bFmHPnv27FH37t1VtWpV2e12Va5cWZJ08ODBGy4/NDRUHh4e1+3j4eGhGTNmaP78+bpw4YImTpzoML1GjRq6//779fnnn0uS9u7dqzVr1qhv376SpM2bNys6OlpeXl7WKzw8XBkZGdq/f7/i4+Pl5uamli1b5nS3aN++fUpLS1PTpk2ttqJFi6pRo0bauXOnQ9+GDRs6vE9PT9f06dP15JNPWm1PPvmkoqOjlZGRIUmKj49X8+bNVbRo0RzXdLV69eqpZs2amjlzpqTL5+IfO3ZMjz32mNVn2bJlat26tSpWrChvb2/17NlTJ06c0Llz53K8np07dyooKEhBQUFWW0hIiHx9fR32ReXKleXt7W29r1Chgktes5YfGFfZY1z9D+MqdxhT2WNM/c+tHlNRUVHatm2bZs2alet5CwvGVfYYV/9zq8ZV9erVFR8fr59//lkDBgxQZGSkduzYkeP5pTvsUQF9+vRRdHS0pk+frj59+mSZ3qlTJ508eVKffvqpfv75Z/3888+S/nfx6fWULFkyRzWsW7dOknTy5EmdPHkyy/S+fftq/vz5On36tKZNm6Zq1apZA/HMmTN69tlnFR8fb702b96sPXv2qFq1aipevHiOasirq7dx6dKlOnz4sP7+97/L3d1d7u7u6tatm/744w8tX75ckvKtph49elgDd+bMmWrXrp3KlCkj6fJtZTt27Kg6depo/vz52rBhg3Xjgpx8drl19Q8hm81m/aC6nrJly8rNzU2JiYkO7YmJifL398/XGm8lxtXNYVxdltdxdTtiTN0cxtRl+TGmBg0apO+++04rV65UYGBgfpZ3yzGubg7j6rKbHVceHh4KDg5WgwYNNH78eNWtW1fvvfdermq4o8Jbu3btdPHiRaWlpSk8PNxh2okTJ7R79269/PLLat26tWrWrKlTp0459Mn8q0p6enqe1r9v3z4NHTpUn376qRo3bqzIyMgsH/jjjz+uIkWKaObMmfriiy/Up08f2Ww2SVL9+vW1Y8cOBQcHZ3l5eHgoNDRUGRkZio2NzXb92dVfrVo1eXh46Mcff7Ta0tLStH79eoWEhFx3e/7zn/+oW7duDj9I4uPj1a1bN/3nP/+RJNWpU0dr1qxRWlraNWvKyf584okntG3bNm3YsEHz5s1Tjx49rGkbNmxQRkaG3nnnHTVp0kT33HOPjhw5kuv11KxZU4cOHdKhQ4esth07digpKemG+yInPDw81KBBA+uHmiRlZGRo+fLlCgsLu+nlOwvjinF1PQU9rm5HjCnG1PXcijFljNGgQYO0YMECrVixQlWqVMmX5ToT44pxdT3O+rcqIyNDqampuZsp1ydaupirz6dNTk42ycnJ1vvM853T09NNmTJlzJNPPmn27Nljli9fbu677z6H6yfS0tJM8eLFzWuvvWYSEhKsiz2zO2fXGMdzaS9dumSaNGliunbtaowx5siRI6ZMmTLWOcVX6tu3rylVqpRxc3Mzhw8ftto3b95sihcvbqKiosymTZvMb7/9ZhYuXOhw98LevXuboKAgs2DBAvP777+blStXmtmzZxtjLl84arPZTHR0tDl27Jh1weY//vEPExAQYBYvXuxwserJkyeNMdmfJ33s2DFTtGhRs3jx4iz1f//998bT09OcOHHC/PXXX6ZMmTLWxaq//fab+eKLL6znxbz++uvmrrvuMrt27TLHjx83Fy9evOZ55U2bNjV169Y13t7e5ty5c1Z7fHy8kWQmTZpk9u3bZ7744gtTsWJFh5p//PFH60Lj48ePW8/1uPIzysjIMPXq1TPNmzc3GzZsMD///HO2F6vWrVvXoa6JEyeaSpUqZdkP2Zk1a5bx9PQ00dHRZseOHeaZZ54xvr6+DnczcgWMK8aVMYVnXJ0+fdps2rTJbNq0yUgy7777rtm0aZN1jYQrYEwxpowpPGNqwIABxsfHx6xatcq6ycPRo0cdtscVMK4YV8YUnnH10ksvmdjYWLN//36zZcsW89JLLxmbzWZ++OGHHM2f6Y4Lb1e78mLVmJgYU7NmTePp6Wnq1KljVq1aleXi908//dQEBQWZIkWKZLlN7NWu/FKMHTvWVKhQwfz111/W9Pnz5xsPDw8THx/vMN+6deuMJNOhQ4csy/zll1/MQw89ZLy8vEzJkiVNnTp1zOuvv25NP3/+vBk6dKipUKGC8fDwMMHBwebzzz+3po8bN874+/sbm81mbff58+fN4MGDTdmyZa97m9grB+6///1v4+vrm+1FqKmpqcbX19e89957xpjLP3Datm1rSpQoYby9vU3z5s3Nvn37jDGXfwBkbo+yuU3slaZMmWIkmV69emVZ57vvvmsqVKhgihcvbsLDw80XX3yRpeb+/fubMmXK5MttYq+Um4FrjDHvv/++ueuuu4yHh4dp1KiR+emnn3I8b2HBuGJcZSoM4yq7W0FLOX/4bmHAmGJMZSoMYyq78STJTJs2LUfzFxaMK8ZVpsIwrvr06WMqVapkPDw8TLly5Uzr1q1zHdyMMcZmjDG5O1YHAAAAALjV7qhr3gAAAADAVRHegHxy8OBBh1v4Xv3Kye2GAThiXAH5izEF5L9bOa44bRLIJ5cuXdKBAweuOb1y5cpyd3e/dQUBtwHGFZC/GFNA/ruV44rwBgAAAAAugNMmAQAAAMAFEN4AAAAAwAUQ3gAAAADABRDeAAAAAMAFEN4AALiBVq1aaciQIc4uAwBwhyO8AQAKTO/evWWz2fTmm286tC9cuFA2my1Xy6pcubImTZqUj9UVnAMHDshmsyk+Pt7ZpQAAbiOENwBAgSpWrJjeeustnTp1ytml5NrFixedXUK+SktLc3YJAICbQHgDABSoNm3ayN/fX+PHj79uv7Vr16p58+YqXry4goKC9Nxzz+ns2bOSLp+2+Mcff2jo0KGy2Wyy2WwyxqhcuXKaN2+etYx69eqpQoUKDsv09PTUuXPnJEkHDx5U586d5eXlJbvdrscff1yJiYlW/zFjxqhevXr67LPPVKVKFRUrVizbWhctWiQfHx/NmDEjT/tk37596ty5s/z8/OTl5aX77rtPy5Yts6aPGzdOtWvXzjJfvXr19Morr1jvP/vsM9WsWVPFihVTjRo1NGXKFGta5tG/2bNnq2XLlipWrJhmzJihP/74Q506dVKpUqVUsmRJ1apVS99//32etgMAcGsR3gAABcrNzU1vvPGG3n//ff3555/Z9tm3b5/atWunrl27asuWLZo9e7bWrl2rQYMGSZK++uorBQYGaty4cTp69KiOHj0qm82mFi1aaNWqVZKkU6dOaefOnTp//rx27dolSYqNjdV9992nEiVKKCMjQ507d9bJkycVGxurmJgY/f777/r73//uUMvevXs1f/58ffXVV9me9jhz5kx1795dM2bMUI8ePfK0T86cOaMOHTpo+fLl2rRpk9q1a6dOnTrp4MGDkqQ+ffpo586dWr9+vTXPpk2btGXLFj311FOSpBkzZmjUqFF6/fXXtXPnTr3xxht65ZVXNH36dId1vfTSS/rHP/6hnTt3Kjw8XFFRUUpNTdXq1au1detWvfXWW/Ly8srTdgAAbi13ZxcAALj9/e1vf1O9evU0evRo/ec//8kyffz48erRo4d1U5C7775bkydPVsuWLTV16lSVLl1abm5u8vb2lr+/vzVfq1at9PHHH0uSVq9erXvvvVf+/v5atWqVatSooVWrVqlly5aSpOXLl2vr1q3av3+/goKCJElffPGFatWqpfXr1+u+++6TdPlUyS+++ELlypXLUueHH36of/3rX/r222+t5eZF3bp1VbduXev9q6++qgULFuibb77RoEGDFBgYqPDwcE2bNs2qa9q0aWrZsqWqVq0qSRo9erTeeecdPfLII5KkKlWqaMeOHfr4448VGRlpLXvIkCFWH+ny0ceuXbsqNDRUkqzlAQAKP468AQBuibfeekvTp0/Xzp07s0zbvHmzoqOj5eXlZb3Cw8OVkZGh/fv3X3OZLVu21I4dO3T8+HHFxsaqVatWatWqlVatWqW0tDStW7dOrVq1kiTt3LlTQUFBVnCTpJCQEPn6+jrUVKlSpWyD27x58zR06FDFxMTcVHCTLh95e+GFF1SzZk35+vrKy8tLO3futI68SdLTTz+tL7/8UhcuXNDFixc1c+ZM9enTR5J09uxZ7du3T3379nXYZ6+99pr27dvnsK6GDRs6vH/uuef02muvqWnTpho9erS2bNlyU9sCALh1CG8AgFuiRYsWCg8P18iRI7NMO3PmjJ599lnFx8dbr82bN2vPnj2qVq3aNZcZGhqq0qVLKzY21iG8xcbGav369UpLS9P999+fqzpLliyZbfu9996rcuXK6fPPP5cxJlfLvNoLL7ygBQsW6I033tCaNWsUHx+v0NBQhxukdOrUSZ6enlqwYIG+/fZbpaWl6dFHH5V0eX9J0qeffuqwz7Zt26affvrputvTr18//f777+rZs6e2bt2qhg0b6v3337+p7QEA3BqcNgkAuGXefPNN1atXT9WrV3dor1+/vnbs2KHg4OBrzuvh4aH09HSHNpvNpubNm+vrr7/W9u3b1axZM5UoUUKpqan6+OOP1bBhQyu81KxZU4cOHdKhQ4eso287duxQUlKSQkJCblh7tWrV9M4776hVq1Zyc3PTBx98kNvNt/z444/q3bu3/va3v0m6HMYOHDjg0Mfd3V2RkZGaNm2aPDw81K1bNxUvXlyS5Ofnp4CAAP3+++95uu4uKChI/fv3V//+/TVy5Eh9+umnGjx4cJ63BwBwaxDeAAC3TGhoqHr06KHJkyc7tI8YMUJNmjTRoEGD1K9fP5UsWVI7duxQTEyMFZIqV66s1atXq1u3bvL09FTZsmUlXb7u7fnnn1fDhg2tG2+0aNFCM2bM0PDhw611tGnTxlr/pEmTdOnSJQ0cOFAtW7bMcmrhtdxzzz1auXKlWrVqJXd39xs+d2737t1Z2mrVqqW7775bX331lTp16iSbzaZXXnlFGRkZWfr269dPNWvWlHQ58F1p7Nixeu655+Tj46N27dopNTVVv/76q06dOqVhw4Zds6YhQ4aoffv2uueee3Tq1CmtXLnSWgcAoHDjtEkAwC01bty4LEGlTp06io2N1W+//abmzZvr3nvv1ahRoxQQEOAw34EDB1StWjWHa9Jatmyp9PR069o26XKgu7rNZrPp66+/VqlSpdSiRQu1adNGVatW1ezZs3NVf/Xq1bVixQp9+eWXev7556/bt1u3brr33nsdXomJiXr33XdVqlQp3X///erUqZPCw8NVv379LPPffffduv/++1WjRg01btzYYVq/fv302Wefadq0aQoNDVXLli0VHR2tKlWqXLem9PR0RUVFqWbNmmrXrp3uueceh0cMAAAKL5u52RP3AQBAgTDG6O6779bAgQOvezQNAHBn4LRJAAAKoePHj2vWrFlKSEiwnu0GALizEd4AACiEypcvr7Jly+qTTz5RqVKlnF0OAKAQILwBAFAIcVUDAOBq3LAEAAAAAFwA4Q0AAAAAXADhDQAAAABcAOENAAAAAFwA4Q0AAAAAXADhDQAAAABcAOENAAAAAFwA4Q0AAAAAXMD/A+rVYcrBq9R7AAAAAElFTkSuQmCC", - "text/plain": [ - "
    " - ] - }, - "metadata": {}, - "output_type": "display_data" + "name": "stdout", + "output_type": "stream", + "text": [ + " def get_outstream_width(self, ind=0):\n", + " o_bits = self.get_output_datatype().bitwidth()\n", + " out_width = o_bits * self.get_nodeattr(\"PE\")\n", + " return out_width\n", + "\n" + ] } ], "source": [ - "layers_updated = list(cycles_dict_updated.keys())\n", - "cycles_updated = list(cycles_dict_updated.values())\n", - "fig = plt.figure(figsize = (10, 5))\n", - "plt.bar(layers_updated, cycles_updated, color ='blue', width = 0.3)\n", - "plt.xlabel(\"Network Layers\")\n", - "plt.ylabel(\"Clock Cycles\")\n", - "plt.title(\"Estimated clock cycles for each network layer\")\n", - "plt.show()" + "showSrc(mvau_inst.get_outstream_width)" ] }, { - "cell_type": "code", - "execution_count": 19, + "cell_type": "markdown", "metadata": {}, - "outputs": [], "source": [ - "res_dict_updated = model.analysis(res_estimation)\n", - "res_dict_updated" + "The input stream width can be calculated by multiplying the input bit width with SIMD and the output stream width can be calculated by multiplying the output bit width with PE." + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "To connect two layers with each other for the final design, the input stream width of a node needs to match the output stream width of the preceding node. If that is not the case FINN inserts DataWidthConverters (DWCs) to resolve this mismatch. Let's have a look at the input/output stream width of the layers before updating the parallelization parameters." ] }, { "cell_type": "code", - "execution_count": 20, + "execution_count": 32, "metadata": {}, "outputs": [ { - "data": { - "image/png": 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m1atXa+TIkVq7dq3Onj3rND41NdVa15Xs3btXP/74o0qUKJFrf/YNGA4dOqSSJUvK19fXqf+uu+66xt4VrIK6BX7x4sXVtGlTffLJJxo7dqyki6cxurm5qX379ta47GuEJk+erAMHDigzM9Pqy8spZnmxd+9epaamKjg4ONf+7PcgJiZGHTp00OjRozVhwgQ1adJEDz/8sP72t7/J09OzQGoZM2aM2rVrpypVqujuu+9Wy5Yt1a1bN9WoUUOStG/fPhljNHz4cA0fPvyK9ZYuXVqHDh1SvXr1cvTfyGfm0KFDV1xH1apV9f333zu1ubm5qUyZMtdc7++//66TJ09q6tSpmjp1aq5jst8HSZo5c6Zef/117dq1yykkX3pX1/3796tUqVIKCgq65vYv/xkgSUWLFs1xjWFely9atKgkWctnB+2rnXqcmppqLZcbV1dXRUdHa9WqVZIuBrPGjRurUaNGyszM1Lp16xQSEqKUlBSnYHalz0H2Kd6HDh3S3XffbbXndmfcbN26dZObm5t27typ0NDQK467lsOHD2vEiBH6/PPPc7zGl/5Bq3nz5ipZsqRmzZqlpk2bKisrSx999JHatWsnPz8/Sdf32l5tHwHkD8EMKKSCg4O1bds2ff3111q8eLEWL16shIQEde/eXTNnzrzu9bq6uuar3fz/axL279+vpk2bqmrVqnrjjTcUFhYmDw8Pffnll5owYUKebrKQlZWl5s2b6/nnn8+1v0qVKnncixvn6enpdPH9pbJD56VHSW5U586d1bNnT23btk1RUVH65JNP1LRpU+u6GuniRf7Dhw9Xr169NHbsWAUFBcnFxUUDBgy45uvrcDhyvX7k0nAnXXwPgoODNWvWrFzXkx2as78Hbt26dfriiy/09ddfq1evXnr99de1bt26HKE5Ly6v5b777tP+/fv12Wef6ZtvvtF7772nCRMm6J133lGfPn2sfR48eLBiY2NzXWd+vl7iZrv0iOfVZO/X448/fsVfsLPD6YcffqgePXro4Ycf1pAhQxQcHCxXV1eNHz9e+/fvv646rzXXb3T57P375z//6XQN3KXy8vlp1KiRXn75ZZ07d06rVq3SP/7xDwUGBuruu+/WqlWrrGtXLw1m+XW1axDbt2+vDz74QG+++abGjx9/XevPzMy0rk974YUXVLVqVfn4+OjXX39Vjx49nOa1q6ur/va3v2natGmaPHmyVq9erd9++83p7q/X89rm5TpLAHlDMAMKMQ8PD7Vt21Zt27ZVVlaWnn76ab377rsaPny4KlWqdEu/1PiLL75Qenq6Pv/8c6e/mOd2d7gr1VWxYkWdPn36mt8TVa5cOS1dulSnT592+iUjv3dDu9Y2rrS+7PbrPXUpNw8//LD69u1rnc64Z88eDRs2zGnMvHnzdP/992v69OlO7SdPnnQKcLkpWrRorqeiZR/1yVaxYkV9++23atiwYZ5+Yatfv77q16+vl19+WbNnz1bXrl01Z84c9enT56q1XH4HzfPnz+vo0aM5xgYFBalnz57q2bOnTp8+rfvuu0+jRo1Snz59VKFCBUmSu7t7nj4zuZ0SeSOfmez3f/fu3XrggQdyrPd6Px8lSpSQn5+fMjMzr7lf8+bNU4UKFbRgwQKneXX5KYsVK1bU119/rZSUlDwdNbuZsk+T9Pf3v+b+Xe1nWOPGjXX+/Hl99NFH+vXXX60Adt9991nBrEqVKlZAk648r3ft2mX159UzzzyjSpUqacSIEQoICNDQoUPzvGy27du3a8+ePZo5c6a6d+9utV/pFPXu3bvr9ddf1xdffKHFixerRIkSTn+UyM9rC6DgcY0ZUEgdP37c6bmLi4v1V/Ts29hnfx/NrbiNfPZfyS/9q3pqaqoSEhJyjPXx8cm1pk6dOmnt2rX6+uuvc/SdPHnSup7twQcfVEZGhtOt+DMzM/X222/f6G5YHnzwQa1bt06bN2/OUcesWbMUFRV1Q6cvXS4wMFCxsbH65JNPNGfOHHl4eOjhhx92GuPq6prjqMXcuXNz3Jo9NxUrVtSuXbv0+++/W20//PBDjltod+rUSZmZmdYplZfKyMiw3rcTJ07kqCX7L/SXf41CbrVkXxuUberUqTmOmF3+Gff19VWlSpWs9QcHB6tJkyZ69913cw11l+5r9vu5YcMGp/4rHRnMizp16ig4OFjvvPOO0z4vXrxYO3fuVOvWra9rva6ururQoYPmz5+vn376KUf/pfuV27xbv3691q5d67RMhw4dZIzJ9WsZ8nokrKDUrl1bFStW1L/+9S+dPn06R/+l+3e1n2H16tWTu7u7Xn31VQUFBal69eqSLga2devWacWKFTmOlj344IPasGGD0+tz5swZTZ06VeXLl1dERES+9mX48OEaPHiwhg0bluOrQfIit/fPGGN97cnlatSooRo1aui9997T/Pnz1blzZ7m5/e9v9Pl5bQEUPI6YAXeoxYsXW3/FvVSDBg1UoUIF9enTRykpKXrggQdUpkwZHTp0SG+//baioqKs6yWioqLk6uqqV199VampqfL09LS+Z6ygtWjRwjqC17dvX50+fVrTpk1TcHBwjl+aa9eurSlTpuill15SpUqVFBwcrAceeEBDhgzR559/rjZt2qhHjx6qXbu2zpw5o+3bt2vevHk6ePCgihcvrrZt26phw4YaOnSoDh48qIiICC1YsCBPNxi51Pz583N9jePi4jR06FDNnTtX9913n/r27auqVavqt99+04wZM3T06NFcA+eNeuyxx/T4449r8uTJio2NzfFlxm3atNGYMWPUs2dPNWjQQNu3b9esWbOsI0dX06tXL73xxhuKjY1V7969dezYMb3zzjuqXr2603czxcTEqG/fvho/fry2bdumFi1ayN3dXXv37tXcuXP15ptv6tFHH9XMmTM1efJkPfLII6pYsaJOnTqladOmyd/fXw8++OBVa+nTp4+eeuopdejQQc2bN9cPP/ygr7/+OsdRv4iICDVp0kS1a9dWUFCQNm3apHnz5ql///7WmEmTJqlRo0aKjIzUE088oQoVKig5OVlr167VL7/8Yn3H2/PPP6///Oc/atmypZ577jnrdvnlypXTjz/+eM3XLzfZoaBnz56KiYlRly5drNvlly9fXgMHDryu9UoXbzm/fPly1atXT0888YQiIiKUkpKiLVu26Ntvv1VKSoqki5+JBQsW6JFHHlHr1q114MABvfPOO4qIiHD6xfz+++9Xt27d9NZbb2nv3r1q2bKlsrKytGrVKt1///1Or+nN5uLiovfee0+tWrVS9erV1bNnT5UuXVq//vqrli9fLn9/f33xxReSLv6skC5+ZUHnzp3l7u6utm3bysfHR0WKFFHt2rW1bt066zvMpItHzM6cOaMzZ87kCGZDhw7VRx99pFatWunZZ59VUFCQZs6cqQMHDmj+/Pl5OtX0cv/85z+Vmpqq+Ph4+fn55euL5atWraqKFStq8ODB+vXXX+Xv76/58+df9Xq+7t27a/DgwZKUY1v5eW0B3AS3+jaQAG6uq90uX5fcFnnevHmmRYsWJjg42Hh4eJiyZcuavn37mqNHjzqtb9q0aaZChQrG1dXV6TbNV7pd/uW3kM/tNuHG/O9Wy7///rvV9vnnn5saNWoYLy8vU758efPqq6+a999/P8ftrpOSkkzr1q2Nn5+fkeRUx6lTp8ywYcNMpUqVjIeHhylevLhp0KCB+de//uV0G//jx4+bbt26GX9/fxMQEGC6detmtm7dmq/b5V/pkX0r7V9++cX06dPHlC5d2ri5uZmgoCDTpk0bs27duquuP7+3y8+WlpZmvL29jSTz4Ycf5ug/d+6c+fvf/25KlixpvL29TcOGDc3atWtzvJe53S7fGGM+/PBDU6FCBePh4WGioqLM119/neN2+dmmTp1qateubby9vY2fn5+JjIw0zz//vPntt9+MMRdv092lSxdTtmxZ4+npaYKDg02bNm3Mpk2brrmfmZmZ5oUXXjDFixc3RYoUMbGxsWbfvn05bpf/0ksvmbp165rAwEDj7e1tqlatal5++WWnz4Exxuzfv990797dhIaGGnd3d1O6dGnTpk0bM2/ePKdxP/74o4mJiTFeXl6mdOnSZuzYsWb69OnXfbv8bB9//LGpVauW8fT0NEFBQaZr167ml19+cRoTFxdnfHx8rvnaXCo5OdnEx8ebsLAw4+7ubkJDQ03Tpk3N1KlTrTFZWVlm3Lhxply5csbT09PUqlXLLFq0KNf3NSMjw/zzn/80VatWNR4eHqZEiRKmVatWZvPmzdYYXeFrIi5/b3JzpZ8hV/o8bt261bRv394UK1bMeHp6mnLlyplOnTqZpUuXOo0bO3asKV26tHFxccnxXg0ZMsRIMq+++qrTMpUqVTKSzP79+3PUuX//fvPoo4+awMBA4+XlZerWrWsWLVqUp30xJvfPQmZmpunSpYtxc3MzCxcuvOZrdOnt8hMTE02zZs2Mr6+vKV68uHniiSesryjI7WfZ0aNHjaurq6lSpcoVt5OX1za3n+EAbozDGL4NEAAAoDD4448/VLJkSY0YMeKKdyMFYA+uMQMAACgkZsyYoczMTHXr1s3uUgBchmvMAAAA7nDLli1TYmKiXn75ZT388MMqX7683SUBuAynMgIAANzhmjRpojVr1qhhw4b68MMPVbp0abtLAnAZghkAAAAA2IxrzAAAAADAZgQzAAAAALAZN/+QlJWVpd9++01+fn7WF0wCAAAAKHyMMTp16pRKlSp1XV8cf70IZpJ+++03hYWF2V0GAAAAgNvEkSNHVKZMmVu2PYKZJD8/P0kXX3x/f3+bqwEAAABgl7S0NIWFhVkZ4VYhmEnW6Yv+/v4EMwAAAAC3/BInbv4BAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM1sD2a//vqrHn/8cRUrVkze3t6KjIzUpk2brH5jjEaMGKGSJUvK29tbzZo10969e53WkZKSoq5du8rf31+BgYHq3bu3Tp8+fat3BQAAAACui63B7MSJE2rYsKHc3d21ePFiJSYm6vXXX1fRokWtMa+99preeustvfPOO1q/fr18fHwUGxurc+fOWWO6du2qHTt2aMmSJVq0aJFWrlypJ5980o5dAgAAAIB8cxhjjF0bHzp0qFavXq1Vq1bl2m+MUalSpfT3v/9dgwcPliSlpqYqJCREM2bMUOfOnbVz505FRERo48aNqlOnjiTpq6++0oMPPqhffvlFpUqVumYdaWlpCggIUGpqKl8wDQAAABRidmUDW4+Yff7556pTp446duyo4OBg1apVS9OmTbP6Dxw4oKSkJDVr1sxqCwgIUL169bR27VpJ0tq1axUYGGiFMklq1qyZXFxctH79+ly3m56errS0NKcHAAAAANjF1mD2888/a8qUKapcubK+/vpr9evXT88++6xmzpwpSUpKSpIkhYSEOC0XEhJi9SUlJSk4ONip383NTUFBQdaYy40fP14BAQHWIywsrKB3DQAAAADyzNZglpWVpXvuuUfjxo1TrVq19OSTT+qJJ57QO++8c1O3O2zYMKWmplqPI0eO3NTtAQAAAMDV2BrMSpYsqYiICKe2atWq6fDhw5Kk0NBQSVJycrLTmOTkZKsvNDRUx44dc+rPyMhQSkqKNeZynp6e8vf3d3oAAAAAgF1sDWYNGzbU7t27ndr27NmjcuXKSZLCw8MVGhqqpUuXWv1paWlav369oqOjJUnR0dE6efKkNm/ebI1ZtmyZsrKyVK9evVuwFwAAAABwY9zs3PjAgQPVoEEDjRs3Tp06ddKGDRs0depUTZ06VZLkcDg0YMAAvfTSS6pcubLCw8M1fPhwlSpVSg8//LCki0fYWrZsaZ0CeeHCBfXv31+dO3fO0x0ZAQAAAMButt4uX5IWLVqkYcOGae/evQoPD9egQYP0xBNPWP3GGI0cOVJTp07VyZMn1ahRI02ePFlVqlSxxqSkpKh///764osv5OLiog4dOuitt96Sr69vnmq43W6X7xjtsLsEW5mRtn4kAQAAUIjZlQ1sD2a3A4LZ7YVgBgAAALsUyu8xAwAAAAAQzAAAAADAdgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALCZrcFs1KhRcjgcTo+qVata/efOnVN8fLyKFSsmX19fdejQQcnJyU7rOHz4sFq3bq0iRYooODhYQ4YMUUZGxq3eFQAAAAC4bm52F1C9enV9++231nM3t/+VNHDgQP33v//V3LlzFRAQoP79+6t9+/ZavXq1JCkzM1OtW7dWaGio1qxZo6NHj6p79+5yd3fXuHHjbvm+AAAAAMD1sD2Yubm5KTQ0NEd7amqqpk+frtmzZ+uBBx6QJCUkJKhatWpat26d6tevr2+++UaJiYn69ttvFRISoqioKI0dO1YvvPCCRo0aJQ8Pj1u9OwAAAACQb7ZfY7Z3716VKlVKFSpUUNeuXXX48GFJ0ubNm3XhwgU1a9bMGlu1alWVLVtWa9eulSStXbtWkZGRCgkJscbExsYqLS1NO3bsuOI209PTlZaW5vQAAAAAALvYGszq1aunGTNm6KuvvtKUKVN04MABNW7cWKdOnVJSUpI8PDwUGBjotExISIiSkpIkSUlJSU6hLLs/u+9Kxo8fr4CAAOsRFhZWsDsGAAAAAPlg66mMrVq1sv5do0YN1atXT+XKldMnn3wib2/vm7bdYcOGadCgQdbztLQ0whkAAAAA29h+KuOlAgMDVaVKFe3bt0+hoaE6f/68Tp486TQmOTnZuiYtNDQ0x10as5/ndt1aNk9PT/n7+zs9AAAAAMAut1UwO336tPbv36+SJUuqdu3acnd319KlS63+3bt36/Dhw4qOjpYkRUdHa/v27Tp27Jg1ZsmSJfL391dERMQtrx8AAAAAroetpzIOHjxYbdu2Vbly5fTbb79p5MiRcnV1VZcuXRQQEKDevXtr0KBBCgoKkr+/v5555hlFR0erfv36kqQWLVooIiJC3bp102uvvaakpCS9+OKLio+Pl6enp527BgAAAAB5Zmsw++WXX9SlSxcdP35cJUqUUKNGjbRu3TqVKFFCkjRhwgS5uLioQ4cOSk9PV2xsrCZPnmwt7+rqqkWLFqlfv36Kjo6Wj4+P4uLiNGbMGLt2CQAAAADyzWGMMXYXYbe0tDQFBAQoNTX1trjezDHaYXcJtjIjC/1HEgAAADaxKxvcVteYAQAAAEBhRDADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZrdNMHvllVfkcDg0YMAAq+3cuXOKj49XsWLF5Ovrqw4dOig5OdlpucOHD6t169YqUqSIgoODNWTIEGVkZNzi6gEAAADg+t0WwWzjxo169913VaNGDaf2gQMH6osvvtDcuXO1YsUK/fbbb2rfvr3Vn5mZqdatW+v8+fNas2aNZs6cqRkzZmjEiBG3ehcAAAAA4LrZHsxOnz6trl27atq0aSpatKjVnpqaqunTp+uNN97QAw88oNq1ayshIUFr1qzRunXrJEnffPONEhMT9eGHHyoqKkqtWrXS2LFjNWnSJJ0/f96uXQIAAACAfLE9mMXHx6t169Zq1qyZU/vmzZt14cIFp/aqVauqbNmyWrt2rSRp7dq1ioyMVEhIiDUmNjZWaWlp2rFjxxW3mZ6errS0NKcHAAAAANjFzc6Nz5kzR1u2bNHGjRtz9CUlJcnDw0OBgYFO7SEhIUpKSrLGXBrKsvuz+65k/PjxGj169A1WDwAAAAAFw7YjZkeOHNFzzz2nWbNmycvL65Zue9iwYUpNTbUeR44cuaXbBwAAAIBL2RbMNm/erGPHjumee+6Rm5ub3NzctGLFCr311ltyc3NTSEiIzp8/r5MnTzotl5ycrNDQUElSaGhojrs0Zj/PHpMbT09P+fv7Oz0AAAAAwC62BbOmTZtq+/bt2rZtm/WoU6eOunbtav3b3d1dS5cutZbZvXu3Dh8+rOjoaElSdHS0tm/frmPHjlljlixZIn9/f0VERNzyfQIAAACA62HbNWZ+fn66++67ndp8fHxUrFgxq713794aNGiQgoKC5O/vr2eeeUbR0dGqX7++JKlFixaKiIhQt27d9NprrykpKUkvvvii4uPj5enpecv3CQAAAACuh603/7iWCRMmyMXFRR06dFB6erpiY2M1efJkq9/V1VWLFi1Sv379FB0dLR8fH8XFxWnMmDE2Vg0AAAAA+eMwxhi7i7BbWlqaAgIClJqaeltcb+YY7bC7BFuZkYX+IwkAAACb2JUNbP8eMwAAAAAo7K7rVMa9e/dq+fLlOnbsmLKyspz6RowYUSCFAQAAAEBhke9gNm3aNPXr10/FixdXaGioHI7/nXbncDgIZgBuO5wezOnBKHjMK+YVgIKV72D20ksv6eWXX9YLL7xwM+oBAAAAgEIn39eYnThxQh07drwZtQAAAABAoZTvYNaxY0d98803N6MWAAAAACiU8n0qY6VKlTR8+HCtW7dOkZGRcnd3d+p/9tlnC6w4AAAAACgM8h3Mpk6dKl9fX61YsUIrVqxw6nM4HAQzAAAAAMinfAezAwcO3Iw6AAAAAKDQuqEvmDbGyBhuFwsAAAAAN+K6gtkHH3ygyMhIeXt7y9vbWzVq1NB//vOfgq4NAAAAAAqFfJ/K+MYbb2j48OHq37+/GjZsKEn6/vvv9dRTT+mPP/7QwIEDC7xIAAAAALiT5TuYvf3225oyZYq6d+9utT300EOqXr26Ro0aRTADAAAAgHzK96mMR48eVYMGDXK0N2jQQEePHi2QogAAAACgMMl3MKtUqZI++eSTHO0ff/yxKleuXCBFAQAAAEBhku9TGUePHq3HHntMK1eutK4xW716tZYuXZprYAMAAAAAXF2+j5h16NBB69evV/HixbVw4UItXLhQxYsX14YNG/TII4/cjBoBAAAA4I6W7yNmklS7dm19+OGHBV0LAAAAABRKeQpmaWlp8vf3t/59NdnjAAAAAAB5k6dgVrRoUR09elTBwcEKDAyUw+HIMcYYI4fDoczMzAIvEgAAAADuZHkKZsuWLVNQUJAkafny5Te1IAAAAAAobPIUzGJiYqx/h4eHKywsLMdRM2OMjhw5UrDVAQAAAEAhkO+7MoaHh+v333/P0Z6SkqLw8PACKQoAAAAACpN8B7Psa8kud/r0aXl5eRVIUQAAAABQmOT5dvmDBg2SJDkcDg0fPlxFihSx+jIzM7V+/XpFRUUVeIEAAAAAcKfLczDbunWrpItHzLZv3y4PDw+rz8PDQzVr1tTgwYMLvkIAAAAAuMPlOZhl342xZ8+eevPNN/m+MgAAAAAoIHkOZtkSEhJuRh0AAAAAUGjlO5hJ0qZNm/TJJ5/o8OHDOn/+vFPfggULCqQwAAAAoLBwjM55c73CxIw0dpdgu3zflXHOnDlq0KCBdu7cqU8//VQXLlzQjh07tGzZMgUEBNyMGgEAAADgjpbvYDZu3DhNmDBBX3zxhTw8PPTmm29q165d6tSpk8qWLXszagQAAACAO1q+g9n+/fvVunVrSRfvxnjmzBk5HA4NHDhQU6dOLfACAQAAAOBOl+9gVrRoUZ06dUqSVLp0af3000+SpJMnT+rs2bMFWx0AAAAAFAL5vvnHfffdpyVLligyMlIdO3bUc889p2XLlmnJkiVq2rTpzagRAAAAAO5o+Q5m//73v3Xu3DlJ0j/+8Q+5u7trzZo16tChg1588cUCLxAAAAAA7nT5DmZBQUHWv11cXDR06NACLQgAAAAACpt8X2O2ZcsWbd++3Xr+2Wef6eGHH9b//d//5fhOMwAAAADAteU7mPXt21d79uyRJP3888967LHHVKRIEc2dO1fPP/98gRcIAAAAAHe6fAezPXv2KCoqSpI0d+5cxcTEaPbs2ZoxY4bmz59f0PUBAAAAwB0v38HMGKOsrCxJ0rfffqsHH3xQkhQWFqY//vijYKsDAAAAgEIg38GsTp06eumll/Sf//xHK1assL5s+sCBAwoJCSnwAgEAAADgTpfvYDZx4kRt2bJF/fv31z/+8Q9VqlRJkjRv3jw1aNCgwAsEAAAAgDtdvm+XX6NGDae7Mmb75z//KVdX1wIpCgAAAAAKk3wHsyvx8vIqqFUBAAAAQKGSp2AWFBSkPXv2qHjx4ipatKgcDscVx6akpBRYcQAAAABQGOQpmE2YMEF+fn6SLl5jBgAAAAAoOHkKZnFxcbn+GwAAAABw4/IUzNLS0vK8Qn9//+suBgAAAAAKozwFs8DAwKteVyZd/OJph8OhzMzMAikMAAAAAAqLPAWz5cuX3+w6AAAAAKDQylMwi4mJudl1AAAAAECh5ZKXQT/++KOysrKsf1/tkR9TpkxRjRo15O/vL39/f0VHR2vx4sVW/7lz5xQfH69ixYrJ19dXHTp0UHJystM6Dh8+rNatW6tIkSIKDg7WkCFDlJGRka86AAAAAMBOeTpiFhUVpaSkJAUHBysqKkoOh0PGmBzj8nuNWZkyZfTKK6+ocuXKMsZo5syZateunbZu3arq1atr4MCB+u9//6u5c+cqICBA/fv3V/v27bV69WpJUmZmplq3bq3Q0FCtWbNGR48eVffu3eXu7q5x48bluQ4AAAAAsFOegtmBAwdUokQJ698FpW3btk7PX375ZU2ZMkXr1q1TmTJlNH36dM2ePVsPPPCAJCkhIUHVqlXTunXrVL9+fX3zzTdKTEzUt99+q5CQEEVFRWns2LF64YUXNGrUKHl4eBRYrQAAAABws+TpVMZy5cpZd2U8dOiQSpcurXLlyjk9SpcurUOHDl13IZmZmZozZ47OnDmj6Ohobd68WRcuXFCzZs2sMVWrVlXZsmW1du1aSdLatWsVGRmpkJAQa0xsbKzS0tK0Y8eOK24rPT1daWlpTg8AAAAAsEuegtml7r//fqWkpORoT01N1f3335/vArZv3y5fX195enrqqaee0qeffqqIiAglJSXJw8NDgYGBTuNDQkKUlJQkSUpKSnIKZdn92X1XMn78eAUEBFiPsLCwfNcNAAAAAAUl38Es+/vKLnf8+HH5+Pjku4C77rpL27Zt0/r169WvXz/FxcUpMTEx3+vJj2HDhik1NdV6HDly5KZuDwAAAACuJk/XmElS+/btJV28wUePHj3k6elp9WVmZurHH39UgwYN8l2Ah4eHKlWqJEmqXbu2Nm7cqDfffFOPPfaYzp8/r5MnTzodNUtOTlZoaKgkKTQ0VBs2bHBaX/ZdG7PH5MbT09OpfgAAAACwU56PmGWf9meMkZ+fn9OpgKGhoXryySf14Ycf3nBBWVlZSk9PV+3ateXu7q6lS5dafbt379bhw4cVHR0tSYqOjtb27dt17Ngxa8ySJUvk7++viIiIG64FAAAAAG6FPB8xS0hIkCSVL19egwcPvq7TFi83bNgwtWrVSmXLltWpU6c0e/Zsfffdd/r6668VEBCg3r17a9CgQQoKCpK/v7+eeeYZRUdHq379+pKkFi1aKCIiQt26ddNrr72mpKQkvfjii4qPj+eIGAAAAIC/jDwHs2wjR44ssI0fO3ZM3bt319GjRxUQEKAaNWro66+/VvPmzSVJEyZMkIuLizp06KD09HTFxsZq8uTJ1vKurq5atGiR+vXrp+joaPn4+CguLk5jxowpsBoBAAAA4GbLczArWrRorjf9CAgIUJUqVTR48GArUOXV9OnTr9rv5eWlSZMmadKkSVccU65cOX355Zf52i4AAAAA3E7yHMwmTpyYa/vJkye1efNmtWnTRvPmzcvxpdEAAAAAgKvLczCLi4u7an9UVJTGjx9PMAMAAACAfMr395hdSZs2bbRr166CWh0AAAAAFBoFFszS09Pl4eFRUKsDAAAAgEKjwILZ9OnTFRUVVVCrAwAAAIBCI8/XmA0aNCjX9tTUVG3ZskV79uzRypUrC6wwAAAAACgs8hzMtm7dmmu7v7+/mjdvrgULFig8PLzACgMAAACAwiLPwWz58uU3sw4AAAAAKLQK7BozAAAAAMD1IZgBAAAAgM0IZgAAAABgM4IZAAAAANgsz8GsV69eOnXq1M2sBQAAAAAKpTwHs5kzZ+rPP/+8mbUAAAAAQKGU52BmjLmZdQAAAABAoZXn7zGTpFOnTsnLy+uqY/z9/W+oIAAAAAAobPIVzKpUqXLFPmOMHA6HMjMzb7goAAAAAChM8hXM5s2bp6CgoJtVCwAAAAAUSvkKZg0bNlRwcPDNqgUAAAAACiW+xwwAAAAAbJbnYFauXDm5urrezFoAAAAAoFDK86mMBw4cuJl1AAAAAEChledgVrRoUTkcjhztAQEBqlKligYPHqzmzZsXaHEAAAAAUBjkOZhNmDAh12B28uRJbd68WW3atNG8efPUtm3bAi0QAAAAAO50eQ5mPXr0uGp/VFSUxo8fTzADAAAAgHwqsLsytmnTRrt27Sqo1QEAAABAoVFgwSw9PV0eHh4FtToAAAAAKDQKLJhNnz5dUVFRBbU6AAAAACg08nyN2aBBg3JtT01N1ZYtW7Rnzx6tXLmywAoDAAAAgMIiz8Fs69atubb7+/urefPmWrBggcLDwwusMAAAAAAoLPIczJYvX37V/l9++UVPPvmkpk6desNFAQAAAEBhUmDXmB0/flzTp08vqNUBAAAAQKFRYMEMAAAAAHB9CGYAAAAAYDOCGQAAAADYLM83/2jfvv1V+0+ePHmjtQAAAABAoZTnYBYQEHDN/u7du99wQQAAAABQ2OQ5mCUkJNzMOgAAAACg0OIaMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwma3BbPz48br33nvl5+en4OBgPfzww9q9e7fTmHPnzik+Pl7FihWTr6+vOnTooOTkZKcxhw8fVuvWrVWkSBEFBwdryJAhysjIuJW7AgAAAADXzdZgtmLFCsXHx2vdunVasmSJLly4oBYtWujMmTPWmIEDB+qLL77Q3LlztWLFCv32229q37691Z+ZmanWrVvr/PnzWrNmjWbOnKkZM2ZoxIgRduwSAAAAAOSbm50b/+qrr5yez5gxQ8HBwdq8ebPuu+8+paamavr06Zo9e7YeeOABSVJCQoKqVaumdevWqX79+vrmm2+UmJiob7/9ViEhIYqKitLYsWP1wgsvaNSoUfLw8LBj1wAAAAAgz26ra8xSU1MlSUFBQZKkzZs368KFC2rWrJk1pmrVqipbtqzWrl0rSVq7dq0iIyMVEhJijYmNjVVaWpp27NiR63bS09OVlpbm9AAAAAAAu9w2wSwrK0sDBgxQw4YNdffdd0uSkpKS5OHhocDAQKexISEhSkpKssZcGsqy+7P7cjN+/HgFBARYj7CwsALeGwAAAADIu9smmMXHx+unn37SnDlzbvq2hg0bptTUVOtx5MiRm75NAAAAALgSW68xy9a/f38tWrRIK1euVJkyZaz20NBQnT9/XidPnnQ6apacnKzQ0FBrzIYNG5zWl33Xxuwxl/P09JSnp2cB7wUAAAAAXB9bj5gZY9S/f399+umnWrZsmcLDw536a9euLXd3dy1dutRq2717tw4fPqzo6GhJUnR0tLZv365jx45ZY5YsWSJ/f39FRETcmh0BAAAAgBtg6xGz+Ph4zZ49W5999pn8/Pysa8ICAgLk7e2tgIAA9e7dW4MGDVJQUJD8/f31zDPPKDo6WvXr15cktWjRQhEREerWrZtee+01JSUl6cUXX1R8fDxHxQAAAAD8JdgazKZMmSJJatKkiVN7QkKCevToIUmaMGGCXFxc1KFDB6Wnpys2NlaTJ0+2xrq6umrRokXq16+foqOj5ePjo7i4OI0ZM+ZW7QYAAAAA3BBbg5kx5ppjvLy8NGnSJE2aNOmKY8qVK6cvv/yyIEsDAAAAgFvmtrkrIwAAAAAUVgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbGZrMFu5cqXatm2rUqVKyeFwaOHChU79xhiNGDFCJUuWlLe3t5o1a6a9e/c6jUlJSVHXrl3l7++vwMBA9e7dW6dPn76FewEAAAAAN8bWYHbmzBnVrFlTkyZNyrX/tdde01tvvaV33nlH69evl4+Pj2JjY3Xu3DlrTNeuXbVjxw4tWbJEixYt0sqVK/Xkk0/eql0AAAAAgBvmZufGW7VqpVatWuXaZ4zRxIkT9eKLL6pdu3aSpA8++EAhISFauHChOnfurJ07d+qrr77Sxo0bVadOHUnS22+/rQcffFD/+te/VKpUqVu2LwAAAABwvW7ba8wOHDigpKQkNWvWzGoLCAhQvXr1tHbtWknS2rVrFRgYaIUySWrWrJlcXFy0fv36K647PT1daWlpTg8AAAAAsMttG8ySkpIkSSEhIU7tISEhVl9SUpKCg4Od+t3c3BQUFGSNyc348eMVEBBgPcLCwgq4egAAAADIu9s2mN1Mw4YNU2pqqvU4cuSI3SUBAAAAKMRu22AWGhoqSUpOTnZqT05OtvpCQ0N17Ngxp/6MjAylpKRYY3Lj6ekpf39/pwcAAAAA2OW2DWbh4eEKDQ3V0qVLrba0tDStX79e0dHRkqTo6GidPHlSmzdvtsYsW7ZMWVlZqlev3i2vGQAAAACuh613ZTx9+rT27dtnPT9w4IC2bdumoKAglS1bVgMGDNBLL72kypUrKzw8XMOHD1epUqX08MMPS5KqVaumli1b6oknntA777yjCxcuqH///urcuTN3ZAQAAADwl2FrMNu0aZPuv/9+6/mgQYMkSXFxcZoxY4aef/55nTlzRk8++aROnjypRo0a6auvvpKXl5e1zKxZs9S/f381bdpULi4u6tChg956661bvi8AAAAAcL1sDWZNmjSRMeaK/Q6HQ2PGjNGYMWOuOCYoKEizZ8++GeUBAAAAwC1x215jBgAAAACFBcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAm90xwWzSpEkqX768vLy8VK9ePW3YsMHukgAAAAAgT+6IYPbxxx9r0KBBGjlypLZs2aKaNWsqNjZWx44ds7s0AAAAALimOyKYvfHGG3riiSfUs2dPRURE6J133lGRIkX0/vvv210aAAAAAFyTm90F3Kjz589r8+bNGjZsmNXm4uKiZs2aae3atbkuk56ervT0dOt5amqqJCktLe3mFptX5+wuwF63zfuAOwdzyu4ScCdiXtldAu40zCm7S7Bk12KMuaXb/csHsz/++EOZmZkKCQlxag8JCdGuXbtyXWb8+PEaPXp0jvawsLCbUiPyJ+CVALtLAO4ozCmg4DGvgIJ1O86pU6dOKSDg1tX1lw9m12PYsGEaNGiQ9TwrK0spKSkqVqyYHA6HjZXZLy0tTWFhYTpy5Ij8/f3tLgf4y2NOAQWPeQUULOaUM2OMTp06pVKlSt3S7f7lg1nx4sXl6uqq5ORkp/bk5GSFhobmuoynp6c8PT2d2gIDA29WiX9J/v7+TEygADGngILHvAIKFnPqf27lkbJsf/mbf3h4eKh27dpaunSp1ZaVlaWlS5cqOjraxsoAAAAAIG/+8kfMJGnQoEGKi4tTnTp1VLduXU2cOFFnzpxRz5497S4NAAAAAK7pjghmjz32mH7//XeNGDFCSUlJioqK0ldffZXjhiC4Nk9PT40cOTLHqZ4Arg9zCih4zCugYDGnbg8Oc6vvAwkAAAAAcPKXv8YMAAAAAP7qCGYAAAAAYDOCGQAAAADYjGB2ncqXL6+JEyfaXcZfzsGDB+VwOLRt27abvi3eo78e3rPrw7zClfB+XR/mFK6G9+z6MK/ywPyFxcXFGUmmb9++OfqefvppI8nExcXlaV0HDhwwkszWrVvzNP7YsWPmzJkzeRrbpk0bExsbm2vfypUrjSTzww8/5GldV7J8+XIjyZw4ceKG1nO5s2fPmqJFi5pixYqZc+fO5WvZuLg4065dO6e2jIwMc/ToUXPhwoUCqzEhIcEEBATkaM/Pe1RQ/v3vf5ty5coZT09PU7duXbN+/fpbuv2CwLz6H+ZVQI72Wz2vVqxYYdq0aWNKlixpJJlPP/30lm27oDCn/oc5FZCj/VbPqXHjxpk6deoYX19fU6JECdOuXTuza9euW7b9gsK8+h/mVUCO9ls9ryZPnmwiIyONn5+f8fPzM/Xr1zdffvllvtfzlz9iFhYWpjlz5ujPP/+02s6dO6fZs2erbNmyBb698+fPS5JKlCihIkWK5GmZ3r17a8mSJfrll19y9CUkJKhOnTqqUaNGgdZ5vYwxysjIsJ7Pnz9f1atXV9WqVbVw4cIbXr+rq6tCQ0Pl5nbzv6khP+9RQfj44481aNAgjRw5Ulu2bFHNmjUVGxurY8eO3bIaCgrzqmAxr67fmTNnVLNmTU2aNOmWbfNmYE4VLObU9VuxYoXi4+O1bt06LVmyRBcuXFCLFi105syZW1ZDQWFeFSzm1fUrU6aMXnnlFW3evFmbNm3SAw88oHbt2mnHjh35W1EBB8ZbKjuN33333ebDDz+02mfNmmVq1Khh2rVrZ/21ZPHixaZhw4YmICDABAUFmdatW5t9+/ZZy0hyesTExDht46WXXjIlS5Y05cuXN8YYU65cOTNhwgRjzMW/VLi7u5uVK1da63v11VdNiRIlTFJSkrlw4YIJCQkxY8eOdar/1KlTxtfX10yZMsUYY8yqVatMo0aNjJeXlylTpox55plnzOnTp63x586dM88//7wpU6aM8fDwMBUrVjTvvfee9ZeeSx/Z+33u3DnzzDPPmBIlShhPT0/TsGFDs2HDBmud2X9l+fLLL80999xj3N3dzfLly63+Jk2amHfeecdMmTLFNG/ePMd78NNPP5nWrVsbPz8/4+vraxo1amT27dtnRo4cmaOm5cuXO/1VKjMz05QuXdpMnjzZaZ1btmwxDofDHDx40BhjzOuvv27uvvtuU6RIEVOmTBnTr18/c+rUKaf6L32MHDkyx3tkjDGHDh0yDz30kPHx8TF+fn6mY8eOJikpyeofOXKkqVmzpvnggw9MuXLljL+/v3nsscdMWlpajv3OTd26dU18fLz1PDMz05QqVcqMHz8+T8vfLphXzKvbaV5dSn/hI2bMKebU7TinjLl4ZEGSWbFixXUtbxfmFfPqdp5XxhhTtGhR89577+VrmTsimL3xxhumadOmVnvTpk3NhAkTnCblvHnzzPz5883evXvN1q1bTdu2bU1kZKTJzMw0xhizYcMGI8l8++235ujRo+b48ePWNnx9fU23bt3MTz/9ZH766SdjTM43fMiQIaZcuXLm5MmTZsuWLcbDw8N89tlnTv0VK1Y0WVlZVtv7779vvL29zcmTJ82+ffuMj4+PmTBhgtmzZ49ZvXq1qVWrlunRo4c1vlOnTiYsLMwsWLDA7N+/33z77bdmzpw5JiMjw8yfP99IMrt37zZHjx41J0+eNMYY8+yzz5pSpUqZL7/80uzYscPExcWZokWLWvuX/aGuUaOG+eabb8y+ffusvn379hlPT0+TkpJijh8/bry8vKyJYowxv/zyiwkKCjLt27c3GzduNLt37zbvv/++2bVrlzl16pTp1KmTadmypTl69Kg5evSoSU9Pz3G6wODBg02jRo2c3te///3vTm0TJkwwy5YtMwcOHDBLly41d911l+nXr58xxpj09HQzceJE4+/vb20ne8Je+h5lZmaaqKgo06hRI7Np0yazbt06U7t2beuHrzEXJ6Wvr69p37692b59u1m5cqUJDQ01//d//3fFz2C29PR04+rqmuOXxu7du5uHHnromsvfTphXzKvbZV5d7q8ezJhTzKnbbU4ZY8zevXuNJLN9+/brWt4uzCvm1e06rzIyMsxHH31kPDw8zI4dO/K17B0RzI4dO2Y8PT3NwYMHzcGDB42Xl5f5/fffnSbl5X7//XenH0RXOr84Li7OhISEmPT0dKf2yydlenq6iYqKMp06dTIRERHmiSeecBq/c+dO6y8G2Ro3bmwef/xxY4wxvXv3Nk8++aTTMqtWrTIuLi7mzz//NLt37zaSzJIlS3Ldn9zOLz59+rRxd3c3s2bNstrOnz9vSpUqZV577TWn5RYuXJhjnf/3f/9nHn74Yet5u3btrL9EGGPMsGHDTHh4uDl//nyuNeV2fvHlr/PWrVuNw+Ewhw4dMsYY6y8o2X9Bys3cuXNNsWLFrOdXOr/40vfom2++Ma6urubw4cNW/44dO4wk669HI0eONEWKFHH668iQIUNMvXr1rlhLtl9//dVIMmvWrHFqHzJkiKlbt+41l7+dMK/+h3kVkGPcrZxXl/urBzPmFHPqdptTmZmZpnXr1qZhw4b5XtZuzKv/YV4F5Bhnx7z68ccfjY+Pj3F1dTUBAQHmv//9b56XzfaXv8ZMungeaevWrTVjxgwlJCSodevWKl68uNOYvXv3qkuXLqpQoYL8/f1Vvnx5SdLhw4evuf7IyEh5eHhcdYyHh4dmzZql+fPn69y5c5owYYJTf9WqVdWgQQO9//77kqR9+/Zp1apV6t27tyTphx9+0IwZM+Tr62s9YmNjlZWVpQMHDmjbtm1ydXVVTExMXl8W7d+/XxcuXFDDhg2tNnd3d9WtW1c7d+50GlunTh2n55mZmZo5c6Yef/xxq+3xxx/XjBkzlJWVJUnatm2bGjduLHd39zzXdLmoqChVq1ZNs2fPlnTx3Pdjx46pY8eO1phvv/1WTZs2VenSpeXn56du3brp+PHjOnv2bJ63s3PnToWFhSksLMxqi4iIUGBgoNNrUb58efn5+VnPS5Ys+Ze8RqwgMK9yx7z6H+ZV/jCncsec+p9bPafi4+P1008/ac6cOfle9nbBvMod8+p/btW8uuuuu7Rt2zatX79e/fr1U1xcnBITE/O8vHQH3S6/V69emjFjhmbOnKlevXrl6G/btq1SUlI0bdo0rV+/XuvXr5f0vws5r8bHxydPNaxZs0aSlJKSopSUlBz9vXv31vz583Xq1CklJCSoYsWK1iQ7ffq0+vbtq23btlmPH374QXv37lXFihXl7e2dpxqu1+X7+PXXX+vXX3/VY489Jjc3N7m5ualz5846dOiQli5dKkkFVlPXrl2tSTl79my1bNlSxYoVk3Tx1qpt2rRRjRo1NH/+fG3evNm6CUBe3rv8uvwHjMPhsH4IXU3x4sXl6uqq5ORkp/bk5GSFhoYWaI23EvPqxjCvLrreeXUnYk7dGObURQUxp/r3769FixZp+fLlKlOmTEGWd8sxr24M8+qiG51XHh4eqlSpkmrXrq3x48erZs2aevPNN/NVwx0TzFq2bKnz58/rwoULio2Ndeo7fvy4du/erRdffFFNmzZVtWrVdOLECacx2X8NyczMvK7t79+/XwMHDtS0adNUr149xcXF5XgzO3XqJBcXF82ePVsffPCBevXqJYfDIUm65557lJiYqEqVKuV4eHh4KDIyUllZWVqxYkWu28+t/ooVK8rDw0OrV6+22i5cuKCNGzcqIiLiqvszffp0de7c2emHxLZt29S5c2dNnz5dklSjRg2tWrVKFy5cuGJNeXk9//a3v+mnn37S5s2bNW/ePHXt2tXq27x5s7KysvT666+rfv36qlKlin777bd8b6datWo6cuSIjhw5YrUlJibq5MmT13wt8sLDw0O1a9e2fmBJUlZWlpYuXaro6OgbXr9dmFfMq6u52fPqTsScYk5dza2YU8YY9e/fX59++qmWLVum8PDwAlmvnZhXzKursev/VVlZWUpPT8/fQvk++fE2cvn5q6mpqSY1NdV6nn1+cWZmpilWrJh5/PHHzd69e83SpUvNvffe63S9woULF4y3t7d56aWXTFJSknXhZG7nyBrjfO5qRkaGqV+/vunQoYMxxpjffvvNFCtWzDqH91K9e/c2RYsWNa6urubXX3+12n/44Qfj7e1t4uPjzdatW82ePXvMwoULne7y16NHDxMWFmY+/fRT8/PPP5vly5ebjz/+2Bhz8SJMh8NhZsyYYY4dO2Zd/Pjcc8+ZUqVKmcWLFztd+JmSkmKMyf285GPHjhl3d3ezePHiHPV/+eWXxtPT0xw/ftz88ccfplixYtaFn3v27DEffPCB9X0oL7/8silbtqzZtWuX+f3338358+eveB53w4YNTc2aNY2fn585e/as1b5t2zYjyUycONHs37/ffPDBB6Z06dJONa9evdq6aPf333+3vrfi0vcoKyvLREVFmcaNG5vNmzeb9evX53rhZ82aNZ3qmjBhgilXrlyO1yE3c+bMMZ6enmbGjBkmMTHRPPnkkyYwMNDprj9/Bcwr5pUxt8+8OnXqlNm6davZunWrkWTeeOMNs3XrVuuahL8C5hRzypjbZ07169fPBAQEmO+++866YcLRo0ed9uevgHnFvDLm9plXQ4cONStWrDAHDhwwP/74oxk6dKhxOBzmm2++ydPy2e6oYHa5Sy/8XLJkialWrZrx9PQ0NWrUMN99912OC8mnTZtmwsLCjIuLS45bpV7u0jd89OjRpmTJkuaPP/6w+ufPn288PDzMtm3bnJZbs2aNkWQefPDBHOvcsGGDad68ufH19TU+Pj6mRo0a5uWXX7b6//zzTzNw4EBTsmRJ4+HhYSpVqmTef/99q3/MmDEmNDTUOBwOa7///PNP88wzz5jixYtf9Vapl07Kf/3rXyYwMDDXCzrT09NNYGCgefPNN40xF3+YtGjRwhQpUsT4+fmZxo0bm/379xtjLk7u7P1RLrdKvdTkyZONJNO9e/cc23zjjTdMyZIljbe3t4mNjTUffPBBjpqfeuopU6xYsQK5Veql8jMpjTHm7bffNmXLljUeHh6mbt26Zt26dXle9nbBvGJeZbsd5lVut0OW8v7FsbcD5hRzKtvtMKdym0+STEJCQp6Wv10wr5hX2W6HedWrVy9Trlw54+HhYUqUKGGaNm2a71BmjDEOY4zJ3zE2AAAAAEBBumOuMQMAAACAvyqCGZAHhw8fdrqN7eWPvNxyF4Az5hVQsJhTQMG7lfOKUxmBPMjIyNDBgwev2F++fHm5ubnduoKAOwDzCihYzCmg4N3KeUUwAwAAAACbcSojAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQCgUGvSpIkGDBhgdxkAgEKOYAYAuC49evSQw+HQK6+84tS+cOFCORyOfK2rfPnymjhxYgFWd/McPHhQDodD27Zts7sUAMAdhGAGALhuXl5eevXVV3XixAm7S8m38+fP211Cgbpw4YLdJQAAbgDBDABw3Zo1a6bQ0FCNHz/+quO+//57NW7cWN7e3goLC9Ozzz6rM2fOSLp4KuGhQ4c0cOBAORwOORwOGWNUokQJzZs3z1pHVFSUSpYs6bROT09PnT17VpJ0+PBhtWvXTr6+vvL391enTp2UnJxsjR81apSioqL03nvvKTw8XF5eXrnW+t///lcBAQGaNWvWdb0m+/fvV7t27RQSEiJfX1/de++9+vbbb63+MWPG6O67786xXFRUlIYPH249f++991StWjV5eXmpatWqmjx5stWXfdTu448/VkxMjLy8vDRr1iwdOnRIbdu2VdGiReXj46Pq1avryy+/vK79AADcWgQzAMB1c3V11bhx4/T222/rl19+yXXM/v371bJlS3Xo0EE//vijPv74Y33//ffq37+/JGnBggUqU6aMxowZo6NHj+ro0aNyOBy677779N1330mSTpw4oZ07d+rPP//Url27JEkrVqzQvffeqyJFiigrK0vt2rVTSkqKVqxYoSVLlujnn3/WY4895lTLvn37NH/+fC1YsCDXUxFnz56tLl26aNasWeratet1vSanT5/Wgw8+qKVLl2rr1q1q2bKl2rZtq8OHD0uSevXqpZ07d2rjxo3WMlu3btWPP/6onj17SpJmzZqlESNG6OWXX9bOnTs1btw4DR8+XDNnznTa1tChQ/Xcc89p586dio2NVXx8vNLT07Vy5Upt375dr776qnx9fa9rPwAAt5ab3QUAAP7aHnnkEUVFRWnkyJGaPn16jv7x48era9eu1g02KleurLfeeksxMTGaMmWKgoKC5OrqKj8/P4WGhlrLNWnSRO+++64kaeXKlapVq5ZCQ0P13XffqWrVqvruu+8UExMjSVq6dKm2b9+uAwcOKCwsTJL0wQcfqHr16tq4caPuvfdeSRdPX/zggw9UokSJHHVOmjRJ//jHP/TFF19Y670eNWvWVM2aNa3nY8eO1aeffqrPP/9c/fv3V5kyZRQbG6uEhASrroSEBMXExKhChQqSpJEjR+r1119X+/btJUnh4eFKTEzUu+++q7i4OGvdAwYMsMZIF48adujQQZGRkZJkrQ8AcPvjiBkA4Ia9+uqrmjlzpnbu3Jmj74cfftCMGTPk6+trPWJjY5WVlaUDBw5ccZ0xMTFKTEzU77//rhUrVqhJkyZq0qSJvvvuO124cEFr1qxRkyZNJEk7d+5UWFiYFcokKSIiQoGBgU41lStXLtdQNm/ePA0cOFBLliy5oVAmXTxiNnjwYFWrVk2BgYHy9fXVzp07rSNmkvTEE0/oo48+0rlz53T+/HnNnj1bvXr1kiSdOXNG+/fvV+/evZ1es5deekn79+932ladOnWcnj/77LN66aWX1LBhQ40cOVI//vjjDe0LAODWIZgBAG7Yfffdp9jYWA0bNixH3+nTp9W3b19t27bNevzwww/au3evKlaseMV1RkZGKigoSCtWrHAKZitWrNDGjRt14cIFNWjQIF91+vj45Npeq1YtlShRQu+//76MMfla5+UGDx6sTz/9VOPGjdOqVau0bds2RUZGOt1spG3btvL09NSnn36qL774QhcuXNCjjz4q6eLrJUnTpk1zes1++uknrVu37qr706dPH/3888/q1q2btm/frjp16ujtt9++of0BANwanMoIACgQr7zyiqKionTXXXc5td9zzz1KTExUpUqVrrish4eHMjMzndocDocaN26szz77TDt27FCjRo1UpEgRpaen691331WdOnWsYFKtWjUdOXJER44csY6aJSYm6uTJk4qIiLhm7RUrVtTrr7+uJk2ayNXVVf/+97/zu/uW1atXq0ePHnrkkUckXQxaBw8edBrj5uamuLg4JSQkyMPDQ507d5a3t7ckKSQkRKVKldLPP/98Xde5hYWF6amnntJTTz2lYcOGadq0aXrmmWeue38AALcGwQwAUCAiIyPVtWtXvfXWW07tL7zwgurXr6/+/furT58+8vHxUWJiopYsWWIFoPLly2vlypXq3LmzPD09Vbx4cUkXrzP7+9//rjp16lg3sbjvvvs0a9YsDRkyxNpGs2bNrO1PnDhRGRkZevrppxUTE5PjdL8rqVKlipYvX64mTZrIzc3tmt+rtnv37hxt1atXV+XKlbVgwQK1bdtWDodDw4cPV1ZWVo6xffr0UbVq1SRdDHOXGj16tJ599lkFBASoZcuWSk9P16ZNm3TixAkNGjToijUNGDBArVq1UpUqVXTixAktX77c2gYA4PbGqYwAgAIzZsyYHCGkRo0aWrFihfbs2aPGjRurVq1aGjFihEqVKuW03MGDB1WxYkWna8BiYmKUmZlpXUsmXQxrl7c5HA599tlnKlq0qO677z41a9ZMFSpU0Mcff5yv+u+66y4tW7ZMH330kf7+979fdWznzp1Vq1Ytp0dycrLeeOMNFS1aVA0aNFDbtm0VGxure+65J8fylStXVoMGDVS1alXVq1fPqa9Pnz567733lJCQoMjISMXExGjGjBkKDw+/ak2ZmZmKj49XtWrV1LJlS1WpUsXpNvsAgNuXw9zoyfQAACDfjDGqXLmynn766aseBQMAFA6cyggAwC32+++/a86cOUpKSrK+uwwAULgRzAAAuMWCg4NVvHhxTZ06VUWLFrW7HADAbYBgBgDALcZVBACAy3HzDwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZv8Ps17pkj9surgAAAAASUVORK5CYII=", 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    " - ] - }, - "metadata": {}, - "output_type": "display_data" + "name": "stdout", + "output_type": "stream", + "text": [ + "In the original model (pe=simd=1): \n", + "Layer: MatrixVectorActivation_0\n", + "Input stream width: 1\n", + "Output stream width: 2\n", + "Layer: MatrixVectorActivation_1\n", + "Input stream width: 2\n", + "Output stream width: 2\n", + "Layer: MatrixVectorActivation_2\n", + "Input stream width: 2\n", + "Output stream width: 2\n", + "Layer: MatrixVectorActivation_3\n", + "Input stream width: 2\n", + "Output stream width: 1\n" + ] } ], "source": [ - "# Extracting LUTs from res_dict\n", - "LUTs_updated = [res_dict[key][\"LUT\"] for key in res_dict_updated.keys()] \n", - "\n", - "#Plotting the bar graph of each network layer with their corresponding LUT resource utilization\n", - "fig = plt.figure(figsize = (10, 5))\n", - "plt.bar(res_dict_updated.keys(), LUTs_updated, color ='green', width = 0.3)\n", - "plt.xlabel(\"Network Layers\")\n", - "plt.ylabel(\"LUT Utilisation\")\n", - "plt.title(\"Estimated LUT values used for each network layer\")\n", - "plt.show()" + "# Original model\n", + "list_of_mvaus = model_orig.get_nodes_by_op_type(\"MatrixVectorActivation\")\n", + "print(\"In the original model (pe=simd=1): \")\n", + "for mvau in list_of_mvaus:\n", + " mvau_inst = getCustomOp(mvau)\n", + " print(\"Layer: \" + mvau.name)\n", + " print(\"Input stream width: \" + str(mvau_inst.get_instream_width()))\n", + " print(\"Output stream width: \" + str(mvau_inst.get_outstream_width()))" ] }, { "cell_type": "markdown", "metadata": {}, "source": [ - "From these numbers, we see that the first layer has been removed as the bottleneck and that the entire network can now perform one inference in ~4096 clock cycles (when the pipeline is full) as compared to the earlier configuration where it took ~38400 execution cycles.\n", - "\n", - "This decrease in execution latency of the network though comes at a cost of a 45% increase in LUT resource utilization for layer 1 of the network.\n", - "\n", - "We now observe the `instream_width` and `outstream_width` of our network with the updated folding parameters and then apply the `InsertDWC()` transform to it in case there is a mismatch in these widths due to the updates. " + "In the original model the output stream width of one layer matches the input stream width of the following layer. So there would be no DWC required when generating the final design." + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "For the updated model, the situation is different. Let's have a look how the stream widths have changed." ] }, { "cell_type": "code", - "execution_count": 21, + "execution_count": 34, "metadata": {}, "outputs": [ { "name": "stdout", "output_type": "stream", "text": [ - "Instream Width = 5 Outstream Width = 4\n", - "Instream Width = 2 Outstream Width = 2\n", - "Instream Width = 2 Outstream Width = 2\n", - "Instream Width = 2 Outstream Width = 1\n" + "In the original model (pe=simd=1): \n", + "Layer: MatrixVectorActivation_0\n", + "Input stream width: 5\n", + "Output stream width: 4\n", + "Layer: MatrixVectorActivation_1\n", + "Input stream width: 2\n", + "Output stream width: 2\n", + "Layer: MatrixVectorActivation_2\n", + "Input stream width: 2\n", + "Output stream width: 2\n", + "Layer: MatrixVectorActivation_3\n", + "Input stream width: 2\n", + "Output stream width: 1\n" ] } ], "source": [ - "fc_layers = model.get_nodes_by_op_type(\"MatrixVectorActivation\")\n", - "for fcl in fc_layers:\n", - " fcl_inst = getCustomOp(fcl)\n", - " print('Instream Width =',(fcl_inst.get_instream_width()),'Outstream Width =',int(fcl_inst.get_outstream_width()))" + "# Updated model\n", + "list_of_mvaus = model_updated.get_nodes_by_op_type(\"MatrixVectorActivation\")\n", + "print(\"In the original model (pe=simd=1): \")\n", + "for mvau in list_of_mvaus:\n", + " mvau_inst = getCustomOp(mvau)\n", + " print(\"Layer: \" + mvau.name)\n", + " print(\"Input stream width: \" + str(mvau_inst.get_instream_width()))\n", + " print(\"Output stream width: \" + str(mvau_inst.get_outstream_width()))" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "As we can see, the output stream width of MatrixVectorActivation_0 has now changed to `4`, while the input stream width of MatrixVectorActivation_1 stayed `2`. So, the FINN compiler would insert a DWC between these nodes, we can manually invoke this behavior by calling the transformation `InsertDWC` on our model." ] }, { "cell_type": "code", - "execution_count": 22, + "execution_count": 39, "metadata": {}, "outputs": [], "source": [ - "model = model.transform(InsertDWC())" + "from finn.transformation.fpgadataflow.insert_dwc import InsertDWC\n", + "from qonnx.transformation.general import GiveUniqueNodeNames\n", + "\n", + "model_updated = model_updated.transform(InsertDWC())\n", + "model_updated = model_updated.transform(GiveUniqueNodeNames())" ] }, { "cell_type": "code", - "execution_count": 24, + "execution_count": 40, "metadata": {}, "outputs": [ { "name": "stdout", "output_type": "stream", "text": [ - "Stopping http://0.0.0.0:5901\n", - "Serving './cybsec_DWC_inserted.onnx' at http://0.0.0.0:5901\n" + "Stopping http://0.0.0.0:5920\n", + "Serving 'cybsec_DWC.onnx' at http://0.0.0.0:5920\n" ] }, { @@ -2156,7 +924,7 @@ " " + "" ] }, - "execution_count": 24, + "execution_count": 40, "metadata": {}, "output_type": "execute_result" } ], "source": [ - "model.save(\"./cybsec_DWC_inserted.onnx\")\n", - "showInNetron(\"./cybsec_DWC_inserted.onnx\",localhost_url='xirxlabs53')" + "model_updated.save(\"cybsec_DWC.onnx\")\n", + "showInNetron(\"cybsec_DWC.onnx\")" ] }, { "cell_type": "markdown", "metadata": {}, "source": [ - "Because there is a mismatch in the `outstream_width` (4) of layer 1 and the `inputstream_width` (2) of layer 2 the FINN compiler inserts the `StreamingDataWidthConverter` layer to remedy this when we call that transformation for our network above.\n", - "\n", - "On expanding this layer in the netron we see that the `inWidth` of this layer is 4 and the `outWidth` is 2.\n", - "\n", - "Note, we do not see this insertion where these widths match. They are only mismatched for the first two layers and hence we see that the data width converter is being inserted there." + "We can observe in the model that a DWC was inserted between the first two layers.\n", + "Since the DWC will also be a hardware block in our final FINN design, it has a latency and resources associated with it. Let's have a final look in our resource estimates." ] }, { "cell_type": "code", - "execution_count": 25, - "metadata": {}, - "outputs": [], - "source": [ - "res_dict_DWC = []\n", - "res_dict_DWC = res_estimation(model)" - ] - }, - { - "cell_type": "code", - "execution_count": 26, + "execution_count": 42, "metadata": {}, "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "['MatrixVectorActivation_0', '', 'MatrixVectorActivation_1', 'MatrixVectorActivation_2', 'MatrixVectorActivation_3']\n" - ] - }, { "data": { - "image/png": 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Vc3rv7+8vSQoNDc3SnpGRoaSkJOs031WrVmns2LFas2aNzp8/7zR+UlKSNa9r2bt3r3799VeVLFky2+GZN047dOiQSpUqJR8fH6fhd9xxxw3WLm/l1aP2SpQooebNm+uLL77Qiy++KOnS6fyurq7q2LGjNV7mNdiTJ0/WgQMHlJ6ebg3LyanWObF3714lJSUpKCgo2+GZn0F0dLQ6deqkcePGaeLEiWrWrJkeeOAB/eMf/5CHh0ee1PLCCy+oQ4cOqlq1qu688061bt1aPXr0UM2aNSVJ+/btkzFGo0eP1ujRo69Zb5kyZXTo0CHVr18/y/Bb+c4cOnTomvOoVq2afv75Z6c2V1dXlS1b9obzPXnypBITEzVlyhRNmTIl23EyPwdJmjFjhl5//XXt2rXL6ceXK5/ysX//fpUuXVqBgYE3XP7VfwMkqVixYlnu4ZDT6YsVKyZJ1vSZP+Bc7xKcpKQka7rsuLi4KCoqSitXrpR0KfA3adJEjRs3Vnp6utauXavg4GAlJCQ4Bf5rfQ8yL3U6dOiQ7rzzTqs9uyelZOrRo4dcXV21c+dOhYSEXHO8Gzl8+LDGjBmjr7/+Oss2vvKH0pYtW6pUqVKaOXOmmjdvroyMDH322Wfq0KGDfH19Jd3ctr3eOgJAXiLwA0AuBAUFaevWrfr++++1aNEiLVq0SNOmTVPPnj01Y8aMm56vi4tLrtrN/7/mc//+/WrevLmqVaumN954Q6GhoXJ3d9e3336riRMn5ujmaBkZGWrZsqWeeeaZbIdXrVo1h2tx6zw8PJxumnWlzB8zrjyqe6u6du2q3r17a+vWrYqMjNQXX3yh5s2bW9ctS5duzjV69Gj16dNHL774ogIDA1WkSBENGTLkhtvX4XBke33ulT8aSJc+g6CgIM2cOTPb+WT+GONwODR37lytXbtW33zzjb7//nv16dNHr7/+utauXZvlx5icuLqWpk2bav/+/frqq6/0ww8/6MMPP9TEiRP1/vvvq1+/ftY6Dx8+XDExMdnOMzePsbzdrjxD43oy1+uRRx65ZnDL/NHj008/Va9evfTAAw9oxIgRCgoKkouLiyZMmKD9+/ffVJ036uu3On3m+v3rX/9yusfAlXLy/WncuLFefvllXbhwQStXrtQ///lPBQQE6M4779TKlSute4NcGfhz63r3eOjYsaM++eQTvfnmm5owYcJNzT89Pd26/v/ZZ59VtWrV5O3trT/++EO9evVy6tcuLi76xz/+oalTp2ry5MlatWqVjh075vQ0kJvZtjm5jwUA5AUCPwDkkru7u9q3b6/27dsrIyNDTzzxhD744AONHj1alStXzrMj0DnxzTffKCUlRV9//bXTEb7s7hZ+rboqVaqks2fP3vA55+XLl9eSJUt09uxZp/95ze3dsW+0jGvNL7P9Zk/hzc4DDzyg/v37W6f179mzR6NGjXIaZ+7cubrnnnv00UcfObUnJiY6/TCQnWLFimV7SnbmUepMlSpV0o8//qhGjRrlKAg0aNBADRo00Msvv6xZs2ape/fumj17tvr163fdWq5+osLFixd1/PjxLOMGBgaqd+/e6t27t86ePaumTZvq+eefV79+/VSxYkVJkpubW46+M9ldGnAr35nMz3/37t269957s8z3Zr8fJUuWlK+vr9LT02+4XnPnzlXFihU1f/58p3519an7lSpV0vfff6+EhIQcHeW/nTIvF/Dz87vh+l3vb1iTJk108eJFffbZZ/rjjz+sYN+0aVMr8FetWtUK/tK1+/WuXbus4Tk1ePBgVa5cWWPGjJG/v79GjhyZ42kzbdu2TXv27NGMGTPUs2dPq/1al2r17NlTr7/+ur755hstWrRIJUuWdPqxKzfbFgDyG9fwA0AunDp1yul9kSJFrKN+mY/Ly3yecn48ri7zqN6VRwGTkpI0bdq0LON6e3tnW1OXLl20Zs0aff/991mGJSYmWvcLuO+++5SWlub0yL/09HS9/fbbt7oalvvuu09r167Vpk2bstQxc+ZMRUZG3tJpvFcLCAhQTEyMvvjiC82ePVvu7u564IEHnMZxcXHJcpR1zpw5WR4Bl51KlSpp165dOnnypNX2yy+/ZHlUV5cuXZSenm5dWnCltLQ063M7ffp0lloyjyhe/bjG7GrJvPY605QpU7Ic4b/6O+7j46PKlStb8w8KClKzZs30wQcfZPtjwZXrmvl5rl+/3mn4tc5kyIm6desqKChI77//vtM6L1q0SDt37lTbtm1var4uLi7q1KmT5s2bp99++y3L8CvXK7t+t27dOq1Zs8Zpmk6dOskYk+3jH3N65D6v1KlTR5UqVdK///1vnT17NsvwK9fven/D6tevLzc3N7366qsKDAxUjRo1JF36IWDt2rVavnx5lqP79913n9avX++0fc6dO6cpU6aoQoUKCg8Pz9W6jB49WsOHD9eoUaOyPII0J7L7/Iwx1uNVr1azZk3VrFlTH374oebNm6euXbvK1fXyMbPcbFsAyG8c4QeAKyxatMg66nSlhg0bqmLFiurXr58SEhJ07733qmzZsjp06JDefvttRUZGWtejRkZGysXFRa+++qqSkpLk4eGhe++995rXZ9+KVq1aWWcc9O/fX2fPntXUqVMVFBSUJYzVqVNH7733nl566SVVrlxZQUFBuvfeezVixAh9/fXXateunXr16qU6dero3Llz2rZtm+bOnauDBw+qRIkSat++vRo1aqSRI0fq4MGDCg8P1/z583N0Y8ArzZs3L9ttHBsbq5EjR2rOnDlq2rSp+vfvr2rVqunYsWOaPn26jh8/nu0PGbfq4Ycf1iOPPKLJkycrJibG6ZFuktSuXTu98MIL6t27txo2bKht27Zp5syZ1pHu6+nTp4/eeOMNxcTEqG/fvjpx4oTef/991ahRw+nZ4tHR0erfv78mTJigrVu3qlWrVnJzc9PevXs1Z84cvfnmm3rooYc0Y8YMTZ48WQ8++KAqVaqkM2fOaOrUqfLz89N999133Vr69eunxx9/XJ06dVLLli31yy+/6Pvvv89ylkJ4eLiaNWumOnXqKDAwUBs3btTcuXM1aNAga5x3331XjRs3VkREhB599FFVrFhR8fHxWrNmjY4ePapffvlFkvTMM8/oP//5j1q3bq2nnnrKeixf+fLl9euvv95w+2UnM2z27t1b0dHR6tatm/VYvgoVKmjo0KE3NV/p0qPtli1bpvr16+vRRx9VeHi4EhIStHnzZv34449KSEiQdOk7MX/+fD344INq27atDhw4oPfff1/h4eFOge+ee+5Rjx499NZbb2nv3r1q3bq1MjIytHLlSt1zzz1O2/R2K1KkiD788EO1adNGNWrUUO/evVWmTBn98ccfWrZsmfz8/PTNN99IuvS3Qrr0aMSuXbvKzc1N7du3l7e3t4oWLao6depo7dq1at++vXU2QNOmTXXu3DmdO3cuS+AfOXKkPvvsM7Vp00ZPPvmkAgMDNWPGDB04cEDz5s3L0SUXV/vXv/6lpKQkDRw4UL6+vk6n2N9ItWrVVKlSJQ0fPlx//PGH/Pz8NG/evOveL6Fnz54aPny4JGVZVm62LQDku/x+LAAAFEbXeyyfrnj80ty5c02rVq1MUFCQcXd3N+XKlTP9+/c3x48fd5rf1KlTTcWKFY2Li4vT46Cu9Vi+qx9Vl93jyIy5/EinkydPWm1ff/21qVmzpvH09DQVKlQwr776qvn444+zPFYrLi7OtG3b1vj6+hpJTnWcOXPGjBo1ylSuXNm4u7ubEiVKmIYNG5p///vfTo8LPHXqlOnRo4fx8/Mz/v7+pkePHmbLli25eizftV6Zj+w6evSo6devnylTpoxxdXU1gYGBpl27dmbt2rXXnX9uH8uXKTk52Xh5eRlJ5tNPP80y/MKFC+bpp582pUqVMl5eXqZRo0ZmzZo1WT7L7B7LZ4wxn376qalYsaJxd3c3kZGR5vvvv8/yWL5MU6ZMMXXq1DFeXl7G19fXREREmGeeecYcO3bMGHPpcWDdunUz5cqVMx4eHiYoKMi0a9fObNy48YbrmZ6ebp599llTokQJU7RoURMTE2P27duX5bF8L730kqlXr54JCAgwXl5eplq1aubll192+h4YY8z+/ftNz549TUhIiHFzczNlypQx7dq1M3PnznUa79dffzXR0dHG09PTlClTxrz44ovmo48+uunH8mX6/PPPTe3atY2Hh4cJDAw03bt3N0ePHnUaJzY21nh7e99w21wpPj7eDBw40ISGhho3NzcTEhJimjdvbqZMmWKNk5GRYcaPH2/Kly9vPDw8TO3atc3ChQuz/VzT0tLMv/71L1OtWjXj7u5uSpYsadq0aWM2bdpkjaNrPI7y6s8mO9f6G3Kt7+OWLVtMx44dTfHixY2Hh4cpX7686dKli1myZInTeC+++KIpU6aMKVKkSJbPasSIEUaSefXVV52mqVy5spFk9u/fn6XO/fv3m4ceesgEBAQYT09PU69ePbNw4cIcrYsx2X8X0tPTTbdu3Yyrq6v58ssvb7iNrnws344dO0yLFi2Mj4+PKVGihHn00UetRyFm97fs+PHjxsXFxVStWvWay8nJts3ubzgA3E4OY/L5nDIAAADgb+TPP/9UqVKlNGbMmGs+nQIACiOu4QcAAACuY/r06UpPT1ePHj0KuhQAyBWu4QcAAACysXTpUu3YsUMvv/yyHnjgAVWoUKGgSwKAXOGUfgAAACAbzZo10+rVq9WoUSN9+umnKlOmTEGXBAC5QuAHAAAAAMCGuIYfAAAAAAAbIvADAAAAAGBD3LRPUkZGho4dOyZfX185HI6CLgcAAAAAYHPGGJ05c0alS5dWkSK351g8gV/SsWPHFBoaWtBlAAAAAAD+xxw5ckRly5a9LfMm8Evy9fWVdGlD+/n5FXA1AAAAAAC7S05OVmhoqJVHbwcCv2Sdxu/n50fgBwAAAADkm9t5WTk37QMAAAAAwIYI/AAAAAAA2BCBHwAAAAAAGyLwAwAAAABgQwR+AAAAAABsiMAPAAAAAIANFXjg/+OPP/TII4+oePHi8vLyUkREhDZu3GgNN8ZozJgxKlWqlLy8vNSiRQvt3bvXaR4JCQnq3r27/Pz8FBAQoL59++rs2bP5vSoAAAAAABQaBRr4T58+rUaNGsnNzU2LFi3Sjh079Prrr6tYsWLWOK+99preeustvf/++1q3bp28vb0VExOjCxcuWON0795d27dv1+LFi7Vw4UKtWLFCjz32WEGsEgAAAAAAhYLDGGMKauEjR47UqlWrtHLlymyHG2NUunRpPf300xo+fLgkKSkpScHBwZo+fbq6du2qnTt3Kjw8XBs2bFDdunUlSd99953uu+8+HT16VKVLl75hHcnJyfL391dSUpL8/PzybgUBAAAAAMhGfuTQAj3C//XXX6tu3brq3LmzgoKCVLt2bU2dOtUafuDAAcXFxalFixZWm7+/v+rXr681a9ZIktasWaOAgAAr7EtSixYtVKRIEa1bty7b5aakpCg5OdnpBQAAAACAnRRo4P/999/13nvvqUqVKvr+++81YMAAPfnkk5oxY4YkKS4uTpIUHBzsNF1wcLA1LC4uTkFBQU7DXV1dFRgYaI1ztQkTJsjf3996hYaG5vWqAQAAAABQoAo08GdkZOiuu+7S+PHjVbt2bT322GN69NFH9f7779/W5Y4aNUpJSUnW68iRI7d1eQAAAAAA5LcCDfylSpVSeHi4U1v16tV1+PBhSVJISIgkKT4+3mmc+Ph4a1hISIhOnDjhNDwtLU0JCQnWOFfz8PCQn5+f0wsAAAAAADsp0MDfqFEj7d6926ltz549Kl++vCQpLCxMISEhWrJkiTU8OTlZ69atU1RUlCQpKipKiYmJ2rRpkzXO0qVLlZGRofr16+fDWgAAAAAAUPi4FuTChw4dqoYNG2r8+PHq0qWL1q9frylTpmjKlCmSJIfDoSFDhuill15SlSpVFBYWptGjR6t06dJ64IEHJF06I6B169bWpQCpqakaNGiQunbtmqM79AMAAAAAYEcF+lg+SVq4cKFGjRqlvXv3KiwsTMOGDdOjjz5qDTfGaOzYsZoyZYoSExPVuHFjTZ48WVWrVrXGSUhI0KBBg/TNN9+oSJEi6tSpk9566y35+PjkqIa/1WP5HI6CriD/FOxXEwAAAABum/zIoQUe+AsDAn8hxVcTAAAAgE3lRw4t0Gv4AQAAAADA7UHgBwAAAADAhgj8AAAAAADYEIEfAAAAAAAbIvADAAAAAGBDBH4AAAAAAGyIwA8AAAAAgA0R+AEAAAAAsCECPwAAAAAANkTgBwAAAADAhgj8AAAAAADYEIEfAAAAAAAbIvADAAAAAGBDBH4AAAAAAGyIwA8AAAAAgA0R+AEAAAAAsCECPwAAAAAANkTgBwAAAADAhgj8AAAAAADYEIEfAAAAAAAbIvADAAAAAGBDBH4AAAAAAGyIwA8AAAAAgA0R+AEAAAAAsCECPwAAAAAANkTgBwAAAADAhgj8AAAAAADYEIEfAAAAAAAbIvADAAAAAGBDBH4AAAAAAGyIwA8AAAAAgA0R+AEAAAAAsCECPwAAAAAANkTgBwAAAADAhgj8AAAAAADYEIEfAAAAAAAbIvADAAAAAGBDBH4AAAAAAGyIwA8AAAAAgA0R+AEAAAAAsCECPwAAAAAANkTgBwAAAADAhgj8AAAAAADYEIEfAAAAAAAbIvADAAAAAGBDBH4AAAAAAGyIwA8AAAAAgA0R+AEAAAAAsCECPwAAAAAANkTgBwAAAADAhgj8AAAAAADYUIEG/ueff14Oh8PpVa1aNWv4hQsXNHDgQBUvXlw+Pj7q1KmT4uPjneZx+PBhtW3bVkWLFlVQUJBGjBihtLS0/F4VAAAAAAAKFdeCLqBGjRr68ccfrfeurpdLGjp0qP773/9qzpw58vf316BBg9SxY0etWrVKkpSenq62bdsqJCREq1ev1vHjx9WzZ0+5ublp/Pjx+b4uAAAAAAAUFgUe+F1dXRUSEpKlPSkpSR999JFmzZqle++9V5I0bdo0Va9eXWvXrlWDBg30ww8/aMeOHfrxxx8VHBysyMhIvfjii3r22Wf1/PPPy93dPb9XBwAAAACAQqHAr+Hfu3evSpcurYoVK6p79+46fPiwJGnTpk1KTU1VixYtrHGrVaumcuXKac2aNZKkNWvWKCIiQsHBwdY4MTExSk5O1vbt26+5zJSUFCUnJzu9AAAAAACwkwIN/PXr19f06dP13Xff6b333tOBAwfUpEkTnTlzRnFxcXJ3d1dAQIDTNMHBwYqLi5MkxcXFOYX9zOGZw65lwoQJ8vf3t16hoaF5u2IAAAAAABSwAj2lv02bNta/a9asqfr166t8+fL64osv5OXldduWO2rUKA0bNsx6n5ycTOgHAAAAANhKgZ/Sf6WAgABVrVpV+/btU0hIiC5evKjExESnceLj461r/kNCQrLctT/zfXb3Bcjk4eEhPz8/pxcAAAAAAHZSqAL/2bNntX//fpUqVUp16tSRm5ublixZYg3fvXu3Dh8+rKioKElSVFSUtm3bphMnTljjLF68WH5+fgoPD8/3+gEAAAAAKCwK9JT+4cOHq3379ipfvryOHTumsWPHysXFRd26dZO/v7/69u2rYcOGKTAwUH5+fho8eLCioqLUoEEDSVKrVq0UHh6uHj166LXXXlNcXJyee+45DRw4UB4eHgW5agAAAAAAFKgCDfxHjx5Vt27ddOrUKZUsWVKNGzfW2rVrVbJkSUnSxIkTVaRIEXXq1EkpKSmKiYnR5MmTreldXFy0cOFCDRgwQFFRUfL29lZsbKxeeOGFglolAAAAAAAKBYcxxhR0EQUtOTlZ/v7+SkpKKvzX8zscBV1B/uGrCQAAAMCm8iOHFqpr+AEAAAAAQN4g8AMAAAAAYEMEfgAAAAAAbIjADwAAAACADRH4AQAAAACwIQI/AAAAAAA2ROAHAAAAAMCGCPwAAAAAANgQgR8AAAAAABsi8AMAAAAAYEMEfgAAAAAAbIjADwAAAACADRH4AQAAAACwIQI/AAAAAAA2ROAHAAAAAMCGCPwAAAAAANgQgR8AAAAAABsi8AMAAAAAYEMEfgAAAAAAbIjADwAAAACADRH4AQAAAACwIQI/AAAAAAA2ROAHAAAAAMCGCPwAAAAAANgQgR8AAAAAABsi8AMAAAAAYEMEfgAAAAAAbIjADwAAAACADRH4AQAAAACwIQI/AAAAAAA2ROAHAAAAAMCGCPwAAAAAANgQgR8AAAAAABsi8AMAAAAAYEMEfgAAAAAAbIjADwAAAACADRH4AQAAAACwIQI/AAAAAAA2ROAHAAAAAMCGCPwAAAAAANgQgR8AAAAAABsi8AMAAAAAYEMEfgAAAAAAbIjADwAAAACADRH4AQAAAACwIQI/AAAAAAA2ROAHAAAAAMCGCPwAAAAAANgQgR8AAAAAABsi8AMAAAAAYEMEfgAAAAAAbKjQBP5XXnlFDodDQ4YMsdouXLiggQMHqnjx4vLx8VGnTp0UHx/vNN3hw4fVtm1bFS1aVEFBQRoxYoTS0tLyuXoAAAAAAAqXQhH4N2zYoA8++EA1a9Z0ah86dKi++eYbzZkzR8uXL9exY8fUsWNHa3h6erratm2rixcvavXq1ZoxY4amT5+uMWPG5PcqAAAAAABQqBR44D979qy6d++uqVOnqlixYlZ7UlKSPvroI73xxhu69957VadOHU2bNk2rV6/W2rVrJUk//PCDduzYoU8//VSRkZFq06aNXnzxRb377ru6ePFiQa0SAAAAAAAFrsAD/8CBA9W2bVu1aNHCqX3Tpk1KTU11aq9WrZrKlSunNWvWSJLWrFmjiIgIBQcHW+PExMQoOTlZ27dvv+YyU1JSlJyc7PQCAAAAAMBOXAty4bNnz9bmzZu1YcOGLMPi4uLk7u6ugIAAp/bg4GDFxcVZ41wZ9jOHZw67lgkTJmjcuHG3WD0AAAAAAIVXgR3hP3LkiJ566inNnDlTnp6e+brsUaNGKSkpyXodOXIkX5cPAAAAAMDtVmCBf9OmTTpx4oTuuusuubq6ytXVVcuXL9dbb70lV1dXBQcH6+LFi0pMTHSaLj4+XiEhIZKkkJCQLHftz3yfOU52PDw85Ofn5/QCAAAAAMBOCizwN2/eXNu2bdPWrVutV926ddW9e3fr325ublqyZIk1ze7du3X48GFFRUVJkqKiorRt2zadOHHCGmfx4sXy8/NTeHh4vq8TAAAAAACFRYFdw+/r66s777zTqc3b21vFixe32vv27athw4YpMDBQfn5+Gjx4sKKiotSgQQNJUqtWrRQeHq4ePXrotddeU1xcnJ577jkNHDhQHh4e+b5OAAAAAAAUFgV6074bmThxoooUKaJOnTopJSVFMTExmjx5sjXcxcVFCxcu1IABAxQVFSVvb2/FxsbqhRdeKMCqAQAAAAAoeA5jjCnoIgpacnKy/P39lZSUVPiv53c4CrqC/MNXEwAAAIBN5UcOLbBr+AEAAAAAwO1zU6f07927V8uWLdOJEyeUkZHhNGzMmDF5UhgAAAAAALh5uQ78U6dO1YABA1SiRAmFhITIccUp5g6Hg8APAEBB4bIvwBl9AsD/uFwH/pdeekkvv/yynn322dtRDwAAAAAAyAO5vob/9OnT6ty58+2oBQAAAAAA5JFcB/7OnTvrhx9+uB21AAAAAACAPJLrU/orV66s0aNHa+3atYqIiJCbm5vT8CeffDLPigMAAAAAADfHYUzu7vARFhZ27Zk5HPr9999vuaj8lh/PP8wz3HwGAHAt7CMAZ/QJAIVYfuTQXB/hP3DgwO2oAwAAAAAA5KFcX8N/JWOMcnmCAAAAAAAAyAc3Ffg/+eQTRUREyMvLS15eXqpZs6b+85//5HVtAAAAAADgJuX6lP433nhDo0eP1qBBg9SoUSNJ0s8//6zHH39cf/75p4YOHZrnRQIAAAAAgNy5qZv2jRs3Tj179nRqnzFjhp5//vm/5TX+3LSvkOJyEQDIHfYRgDP6BIBCLD9yaK5P6T9+/LgaNmyYpb1hw4Y6fvx4nhQFAAAAAABuTa4Df+XKlfXFF19kaf/8889VpUqVPCkKAAAAAADcmlxfwz9u3Dg9/PDDWrFihXUN/6pVq7RkyZJsfwgAAAAAAAD5L9dH+Dt16qR169apRIkS+vLLL/Xll1+qRIkSWr9+vR588MHbUSMAAAAAAMilXN+0z464aV8hxVcTAHKHfQTgjD4BoBDLjxyao1P6k5OTrQKSk5OvO26hD8wAAAAAAPwPyFHgL1asmI4fP66goCAFBATIkc2vpcYYORwOpaen53mRAAAAAAAgd3IU+JcuXarAwEBJ0rJly25rQQAAAAAA4NblKPBHR0db/w4LC1NoaGiWo/zGGB05ciRvqwMAAAAAADcl13fpDwsL08mTJ7O0JyQkKCwsLE+KAgAAAAAAtybXgT/zWv2rnT17Vp6ennlSFAAAAAAAuDU5OqVfkoYNGyZJcjgcGj16tIoWLWoNS09P17p16xQZGZnnBQIAAAAAgNzLceDfsmWLpEtH+Ldt2yZ3d3drmLu7u2rVqqXhw4fnfYUAAAAAACDXchz4M+/O37t3b7355pvy8/O7bUUBAAAAAIBbk+PAn2natGm3ow4AAAAAAJCHch34JWnjxo364osvdPjwYV28eNFp2Pz58/OkMAAAAABAHsnmxuu2ZUxBV1Bo5Pou/bNnz1bDhg21c+dOLViwQKmpqdq+fbuWLl0qf3//21EjAAAAAADIpVwH/vHjx2vixIn65ptv5O7urjfffFO7du1Sly5dVK5cudtRIwAAAAAAyKVcB/79+/erbdu2ki7dnf/cuXNyOBwaOnSopkyZkucFAgAAAACA3Mt14C9WrJjOnDkjSSpTpox+++03SVJiYqLOnz+ft9UBAAAAAICbkuub9jVt2lSLFy9WRESEOnfurKeeekpLly7V4sWL1bx589tRIwAAAAAAyKVcB/533nlHFy5ckCT985//lJubm1avXq1OnTrpueeey/MCAQAAAABA7jmM4ZkFycnJ8vf3V1JSkvz8/Aq6nOvjcRoAgGthHwE4o08Al9EfCp38yKG5voZ/8+bN2rZtm/X+q6++0gMPPKD/+7//08WLF/O0OAAAAAAAcHNyHfj79++vPXv2SJJ+//13PfzwwypatKjmzJmjZ555Js8LBAAAAAAAuZfrwL9nzx5FRkZKkubMmaPo6GjNmjVL06dP17x58/K6PgAAAAAAcBNyHfiNMcrIyJAk/fjjj7rvvvskSaGhofrzzz/ztjoAAAAAAHBTch3469atq5deekn/+c9/tHz5crVt21aSdODAAQUHB+d5gQAAAAAAIPdyHfgnTZqkzZs3a9CgQfrnP/+pypUrS5Lmzp2rhg0b5nmBAAAAAAAg9/LssXwXLlyQi4uL3Nzc8mJ2+YrH8hVSf5PHaQBAocE+AnBGnwAuoz8UOvmRQ13zakaenp55NSsAAAAAAHCLchT4AwMDtWfPHpUoUULFihWT4zq/DiUkJORZcQAAAAAA4ObkKPBPnDhRvr6+ki5dww8AAAAAAAq3PLuG/++Ma/gLKb6aAJA77CMAZ/QJ4DL6Q6FTaK7hT05OzvEMC31gBgAAAADgf0COAn9AQMB1r9uXJGOMHA6H0tPT86QwAAAAAABw83IU+JctW3a76wAAAAAAAHkoR4E/Ojr6dtcBAAAAAADyUJGcjPTrr78qIyPD+vf1Xrnx3nvvqWbNmvLz85Ofn5+ioqK0aNEia/iFCxc0cOBAFS9eXD4+PurUqZPi4+Od5nH48GG1bdtWRYsWVVBQkEaMGKG0tLRc1QEAAAAAgN3k6Ah/ZGSk4uLiFBQUpMjISDkcDmV3c//cXsNftmxZvfLKK6pSpYqMMZoxY4Y6dOigLVu2qEaNGho6dKj++9//as6cOfL399egQYPUsWNHrVq1SpKUnp6utm3bKiQkRKtXr9bx48fVs2dPubm5afz48TmuAwAAAAAAu8nRY/kOHTqkcuXKyeFw6NChQ9cdt3z58rdUUGBgoP71r3/poYceUsmSJTVr1iw99NBDkqRdu3apevXqWrNmjRo0aKBFixapXbt2OnbsmIKDgyVJ77//vp599lmdPHlS7u7uOVomj+UrpP4mj9MAgEKDfQTgjD4BXEZ/KHTyI4fm6JT+8uXLW3fpP3TokMqUKaPy5cs7vcqUKXPDHwOuJz09XbNnz9a5c+cUFRWlTZs2KTU1VS1atLDGqVatmsqVK6c1a9ZIktasWaOIiAgr7EtSTEyMkpOTtX379msuKyUlRcnJyU4vAAAAAADsJEeB/0r33HOPEhISsrQnJSXpnnvuyXUB27Ztk4+Pjzw8PPT4449rwYIFCg8PV1xcnNzd3RUQEOA0fnBwsOLi4iRJcXFxTmE/c3jmsGuZMGGC/P39rVdoaGiu6wYAAAAAoDDLdeA3xlhH+6906tQpeXt757qAO+64Q1u3btW6des0YMAAxcbGaseOHbmeT26MGjVKSUlJ1uvIkSO3dXkAAAAAAOS3HN20T5I6duwo6dKN+Xr16iUPDw9rWHp6un799Vc1bNgw1wW4u7urcuXKkqQ6depow4YNevPNN/Xwww/r4sWLSkxMdDrKHx8fr5CQEElSSEiI1q9f7zS/zLv4Z46THQ8PD6f6AQAAAACwmxwf4c88/d0YI19fX6dT4kNCQvTYY4/p008/veWCMjIylJKSojp16sjNzU1Lliyxhu3evVuHDx9WVFSUJCkqKkrbtm3TiRMnrHEWL14sPz8/hYeH33ItAAAAAAD8XeX4CP+0adMkSRUqVNDw4cNv6vT9q40aNUpt2rRRuXLldObMGc2aNUs//fSTvv/+e/n7+6tv374aNmyYAgMD5efnp8GDBysqKkoNGjSQJLVq1Urh4eHq0aOHXnvtNcXFxem5557TwIEDOYIPAAAAAPifluPAn2ns2LF5tvATJ06oZ8+eOn78uPz9/VWzZk19//33atmypSRp4sSJKlKkiDp16qSUlBTFxMRo8uTJ1vQuLi5auHChBgwYoKioKHl7eys2NlYvvPBCntUIAAAAAMDfkcOYnD2ksFixYtnerM/f319Vq1bV8OHDraD+d5Mfzz/MMzw/EwBwLewjAGf0CeAy+kOhkx85NMdH+CdNmpRte2JiojZt2qR27dpp7ty5at++fV7VBgAAAAAAblKOA39sbOx1h0dGRmrChAkEfgAAAAAACoEc36X/Rtq1a6ddu3bl1ewAAAAAAMAtyLPAn5KSInd397yaHQAAAAAAuAV5Fvg/+ugjRUZG5tXsAAAAAADALcjxNfzDhg3Ltj0pKUmbN2/Wnj17tGLFijwrDAAAAAAA3LwcB/4tW7Zk2+7n56eWLVtq/vz5CgsLy7PCAAAAAADAzctx4F+2bNntrAMAAAAAAOShPLuGHwAAAAAAFB4EfgAAAAAAbIjADwAAAACADRH4AQAAAACwoRwH/j59+ujMmTO3sxYAAAAAAJBHchz4Z8yYob/++ut21gIAAAAAAPJIjgO/MeZ21gEAAAAAAPKQa25GPnPmjDw9Pa87jp+f3y0VBAAAAAAAbl2uAn/VqlWvOcwYI4fDofT09FsuCgAAAAAA3JpcBf65c+cqMDDwdtUCAAAAAADySK4Cf6NGjRQUFHS7agEAAAAAAHkkxzftAwAAAAAAfx85Dvzly5eXi4vL7awFAAAAAADkkRyf0n/gwIHbWQcAAAAAAMhDOQ78xYoVk8PhyNLu7++vqlWravjw4WrZsmWeFgcAAAAAAG5OjgP/xIkTsw38iYmJ2rRpk9q1a6e5c+eqffv2eVogAAAAAADIvRwH/l69el13eGRkpCZMmEDgBwAAAACgEMizu/S3a9dOu3btyqvZAQAAAACAW5BngT8lJUXu7u55NTsAAAAAAHAL8izwf/TRR4qMjMyr2QEAAAAAgFuQ42v4hw0blm17UlKSNm/erD179mjFihV5VhgAAAAAALh5OQ78W7Zsybbdz89PLVu21Pz58xUWFpZnhQEAAAAAgJuX48C/bNmy6w4/evSoHnvsMU2ZMuWWiwIAAAAAALcmz67hP3XqlD766KO8mh0AAAAAALgFeRb4AQAAAABA4UHgBwAAAADAhgj8AAAAAADYUI5v2texY8frDk9MTLzVWgAAAAAAQB7JceD39/e/4fCePXveckEAAAAAAODW5TjwT5s27XbWAQAAAAAA8hDX8AMAAAAAYEMEfgAAAAAAbIjADwAAAACADRH4AQAAAACwIQI/AAAAAAA2ROAHAAAAAMCGCPwAAAAAANgQgR8AAAAAABsi8AMAAAAAYEMEfgAAAAAAbIjADwAAAACADRH4AQAAAACwIQI/AAAAAAA2VKCBf8KECbr77rvl6+uroKAgPfDAA9q9e7fTOBcuXNDAgQNVvHhx+fj4qFOnToqPj3ca5/Dhw2rbtq2KFi2qoKAgjRgxQmlpafm5KgAAAAAAFCoFGviXL1+ugQMHau3atVq8eLFSU1PVqlUrnTt3zhpn6NCh+uabbzRnzhwtX75cx44dU8eOHa3h6enpatu2rS5evKjVq1drxowZmj59usaMGVMQqwQAAAAAQKHgMMaYgi4i08mTJxUUFKTly5eradOmSkpKUsmSJTVr1iw99NBDkqRdu3apevXqWrNmjRo0aKBFixapXbt2OnbsmIKDgyVJ77//vp599lmdPHlS7u7uN1xucnKy/P39lZSUJD8/v9u6jrfM4SjoCvJP4flqAsDfA/sIwBl9AriM/lDo5EcOLVTX8CclJUmSAgMDJUmbNm1SamqqWrRoYY1TrVo1lStXTmvWrJEkrVmzRhEREVbYl6SYmBglJydr+/bt2S4nJSVFycnJTi8AAAAAAOyk0AT+jIwMDRkyRI0aNdKdd94pSYqLi5O7u7sCAgKcxg0ODlZcXJw1zpVhP3N45rDsTJgwQf7+/tYrNDQ0j9cGAAAAAICCVWgC/8CBA/Xbb79p9uzZt31Zo0aNUlJSkvU6cuTIbV8mAAAAAAD5ybWgC5CkQYMGaeHChVqxYoXKli1rtYeEhOjixYtKTEx0OsofHx+vkJAQa5z169c7zS/zLv6Z41zNw8NDHh4eebwWAAAAAAAUHgV6hN8Yo0GDBmnBggVaunSpwsLCnIbXqVNHbm5uWrJkidW2e/duHT58WFFRUZKkqKgobdu2TSdOnLDGWbx4sfz8/BQeHp4/KwIAAAAAQCFToEf4Bw4cqFmzZumrr76Sr6+vdc29v7+/vLy85O/vr759+2rYsGEKDAyUn5+fBg8erKioKDVo0ECS1KpVK4WHh6tHjx567bXXFBcXp+eee04DBw7kKD4AAAAA4H9WgT6Wz3GNR0NMmzZNvXr1kiRduHBBTz/9tD777DOlpKQoJiZGkydPdjpd/9ChQxowYIB++ukneXt7KzY2Vq+88opcXXP2ewaP5Suk/iaP0wCAQoN9BOCMPgFcRn8odPIjhxZo4C8sCPyFFF9NAMgd9hGAM/oEcBn9odDJjxxaaO7SDwAAAAAA8g6BHwAAAAAAGyLwAwAAAABgQwR+AAAAAABsiMAPAAAAAIANEfgBAAAAALAhAj8AAAAAADZE4AcAAAAAwIYI/AAAAAAA2BCBHwAAAAAAGyLwAwAAAABgQwR+AAAAAABsiMAPAAAAAIANEfgBAAAAALAhAj8AAAAAADZE4AcAAAAAwIYI/AAAAAAA2BCBHwAAAAAAGyLwAwAAAABgQwR+AAAAAABsiMAPAAAAAIANEfgBAAAAALAhAj8AAAAAADZE4AcAAAAAwIYI/AAAAAAA2BCBHwAAAAAAGyLwAwAAAABgQwR+AAAAAABsiMAPAAAAAIANEfgBAAAAALAhAj8AAAAAADZE4AcAAAAAwIYI/AAAAAAA2BCBHwAAAAAAGyLwAwAAAABgQwR+AAAAAABsiMAPAAAAAIANEfgBAAAAALAhAj8AAAAAADZE4AcAAAAAwIYI/AAAAAAA2BCBHwAAAAAAGyLwAwAAAABgQwR+AAAAAABsiMAPAAAAAIANEfgBAAAAALAhAj8AAAAAADZE4AcAAAAAwIYI/AAAAAAA2BCBHwAAAAAAGyLwAwAAAABgQwUa+FesWKH27durdOnScjgc+vLLL52GG2M0ZswYlSpVSl5eXmrRooX27t3rNE5CQoK6d+8uPz8/BQQEqG/fvjp79mw+rgUAAAAAAIVPgQb+c+fOqVatWnr33XezHf7aa6/prbfe0vvvv69169bJ29tbMTExunDhgjVO9+7dtX37di1evFgLFy7UihUr9Nhjj+XXKgAAAAAAUCg5jDGmoIuQJIfDoQULFuiBBx6QdOnofunSpfX0009r+PDhkqSkpCQFBwdr+vTp6tq1q3bu3Knw8HBt2LBBdevWlSR99913uu+++3T06FGVLl06R8tOTk6Wv7+/kpKS5Ofnd1vWL884HAVdQf4pHF9NAPj7YB8BOKNPAJfRHwqd/MihhfYa/gMHDiguLk4tWrSw2vz9/VW/fn2tWbNGkrRmzRoFBARYYV+SWrRooSJFimjdunXXnHdKSoqSk5OdXgAAAAAA2EmhDfxxcXGSpODgYKf24OBga1hcXJyCgoKchru6uiowMNAaJzsTJkyQv7+/9QoNDc3j6gEAAAAAKFiFNvDfTqNGjVJSUpL1OnLkSEGXBAAAAABAniq0gT8kJESSFB8f79QeHx9vDQsJCdGJEyechqelpSkhIcEaJzseHh7y8/NzegEAAAAAYCeFNvCHhYUpJCRES5YssdqSk5O1bt06RUVFSZKioqKUmJioTZs2WeMsXbpUGRkZql+/fr7XDAAAAABAYeFakAs/e/as9u3bZ70/cOCAtm7dqsDAQJUrV05DhgzRSy+9pCpVqigsLEyjR49W6dKlrTv5V69eXa1bt9ajjz6q999/X6mpqRo0aJC6du2a4zv0AwAAAABgRwUa+Ddu3Kh77rnHej9s2DBJUmxsrKZPn65nnnlG586d02OPPabExEQ1btxY3333nTw9Pa1pZs6cqUGDBql58+YqUqSIOnXqpLfeeivf1wUAAAAAgMLEYczf5CGFt1F+PP8wz/D8TADAtbCPAJzRJ4DL6A+FTn7k0EJ7DT8AAAAAALh5BH4AAAAAAGyIwA8AAAAAgA0R+AEAAAAAsCECPwAAAAAANkTgBwAAAADAhgj8AAAAAADYEIEfAAAAAAAbIvADAAAAAGBDBH4AAAAAAGyIwA8AAAAAgA0R+AEAAAAAsCECPwAAAAAANkTgBwAAAADAhgj8AAAAAADYEIEfAAAAAAAbIvADAAAAAGBDBH4AAAAAAGyIwA8AAAAAgA0R+AEAAAAAsCECPwAAAAAANkTgBwAAAADAhgj8AAAAAADYEIEfAAAAAAAbIvADAAAAAGBDBH4AAAAAAGyIwA8AAAAAgA0R+AEAAAAAsCECPwAAAAAANkTgBwAAAADAhgj8AAAAAADYEIEfAAAAAAAbIvADAAAAAGBDBH4AAAAAAGyIwA8AAAAAgA0R+AEAAAAAsCECPwAAAAAANkTgBwAAAADAhgj8AAAAAADYEIEfAAAAAAAbIvADAAAAAGBDBH4AAAAAAGyIwA8AAAAAgA0R+AEAAAAAsCECPwAAAAAANkTgBwAAAADAhgj8AAAAAADYEIEfAAAAAAAbIvADAAAAAGBDBH4AAAAAAGyIwA8AAAAAgA3ZJvC/++67qlChgjw9PVW/fn2tX7++oEsCAAAAAKDA2CLwf/755xo2bJjGjh2rzZs3q1atWoqJidGJEycKujQAAAAAAAqEwxhjCrqIW1W/fn3dfffdeueddyRJGRkZCg0N1eDBgzVy5MgbTp+cnCx/f38lJSXJz8/vdpd7axyOgq4g//z9v5rID/QJ4DL6A+CMPgFcRn8odPIjh7relrnmo4sXL2rTpk0aNWqU1VakSBG1aNFCa9asyXaalJQUpaSkWO+TkpIkXdrgKET4PABn9AngMvoD4Iw+AVz2N+kPmfnzdh6D/9sH/j///FPp6ekKDg52ag8ODtauXbuynWbChAkaN25clvbQ0NDbUiNukr9/QVcAFC70CeAy+gPgjD4BXPY36w9nzpyR/22q+W8f+G/GqFGjNGzYMOt9RkaGEhISVLx4cTn+l051yYHk5GSFhobqyJEjhf9yByAf0CcAZ/QJ4DL6A+CMPnF9xhidOXNGpUuXvm3L+NsH/hIlSsjFxUXx8fFO7fHx8QoJCcl2Gg8PD3l4eDi1BQQE3K4SbcHPz49OClyBPgE4o08Al9EfAGf0iWu7XUf2M/3t79Lv7u6uOnXqaMmSJVZbRkaGlixZoqioqAKsDAAAAACAgvO3P8IvScOGDVNsbKzq1q2revXqadKkSTp37px69+5d0KUBAAAAAFAgbBH4H374YZ08eVJjxoxRXFycIiMj9d1332W5kR9yz8PDQ2PHjs1yCQTwv4o+ATijTwCX0R8AZ/SJgucwt/MZAAAAAAAAoED87a/hBwAAAAAAWRH4AQAAAACwIQI/AAAAAAA2RODPQxUqVNCkSZMKuoy/nYMHD8rhcGjr1q23fVl8RgAKCn9/bg77CPtie98c+oQ9sa1vDv0hB4zNxMbGGkmmf//+WYY98cQTRpKJjY3N0bwOHDhgJJktW7bkaPwTJ06Yc+fO5Wjcdu3amZiYmGyHrVixwkgyv/zyS47mdS3Lli0zkszp06dvaT5XO3/+vClWrJgpXry4uXDhQq6mjY2NNR06dHBqS0tLM8ePHzepqal5VuO0adOMv79/lvbcfEZ55Z133jHly5c3Hh4epl69embdunX5unwAl7GPuIx9hH+W9vzeRyxfvty0a9fOlCpVykgyCxYsyLdlZ6JPXEaf8M/Snt99Yvz48aZu3brGx8fHlCxZ0nTo0MHs2rUr35ZPf7iM/uCfpT2/+8PkyZNNRESE8fX1Nb6+vqZBgwbm22+/zfV8bHmEPzQ0VLNnz9Zff/1ltV24cEGzZs1SuXLl8nx5Fy9elCSVLFlSRYsWzdE0ffv21eLFi3X06NEsw6ZNm6a6deuqZs2aeVrnzTLGKC0tzXo/b9481ahRQ9WqVdOXX355y/N3cXFRSEiIXF1v/1Mic/MZ5YXPP/9cw4YN09ixY7V582bVqlVLMTExOnHiRL7VAMAZ+4i8xT7i5p07d061atXSu+++m2/LzA59Im/RJ27e8uXLNXDgQK1du1aLFy9WamqqWrVqpXPnzuVbDfSHvEV/uHlly5bVK6+8ok2bNmnjxo2699571aFDB23fvj13M8rjHyIKXOYvP3feeaf59NNPrfaZM2eamjVrmg4dOli/zC1atMg0atTI+Pv7m8DAQNO2bVuzb98+axpJTq/o6GinZbz00kumVKlSpkKFCsYYY8qXL28mTpxojLn0q5ibm5tZsWKFNb9XX33VlCxZ0sTFxZnU1FQTHBxsXnzxRaf6z5w5Y3x8fMx7771njDFm5cqVpnHjxsbT09OULVvWDB482Jw9e9Ya/8KFC+aZZ54xZcuWNe7u7qZSpUrmww8/tH5VvPKVud4XLlwwgwcPNiVLljQeHh6mUaNGZv369dY8M3/R+/bbb81dd91l3NzczLJly6zhzZo1M++//7557733TMuWLbN8Br/99ptp27at8fX1NT4+PqZx48Zm3759ZuzYsVlqWrZsmdMvoOnp6aZMmTJm8uTJTvPcvHmzcTgc5uDBg8YYY15//XVz5513mqJFi5qyZcuaAQMGmDNnzjjVf+Vr7NixWT4jY4w5dOiQuf/++423t7fx9fU1nTt3NnFxcdbwsWPHmlq1aplPPvnElC9f3vj5+ZmHH37YJCcnZ1nv7NSrV88MHDjQep+enm5Kly5tJkyYkKPpAeQt9hHsIwrTPuJKKsAj/PQJ+kRh7BPGXDqiKsksX778pqbPLfoD/aEw9wdjjClWrJj58MMPczWNbQP/G2+8YZo3b261N2/e3EycONGpo86dO9fMmzfP7N2712zZssW0b9/eREREmPT0dGOMMevXrzeSzI8//miOHz9uTp06ZS3Dx8fH9OjRw/z222/mt99+M8Zk/RKMGDHClC9f3iQmJprNmzcbd3d389VXXzkNr1SpksnIyLDaPv74Y+Pl5WUSExPNvn37jLe3t5k4caLZs2ePWbVqlaldu7bp1auXNX6XLl1MaGiomT9/vtm/f7/58ccfzezZs01aWpqZN2+ekWR2795tjh8/bhITE40xxjz55JOmdOnS5ttvvzXbt283sbGxplixYtb6ZX7Ra9asaX744Qezb98+a9i+ffuMh4eHSUhIMKdOnTKenp5W5zHGmKNHj5rAwEDTsWNHs2HDBrN7927z8ccfm127dpkzZ86YLl26mNatW5vjx4+b48ePm5SUlCynPA0fPtw0btzY6XN9+umnndomTpxoli5dag4cOGCWLFli7rjjDjNgwABjjDEpKSlm0qRJxs/Pz1pOZie+8jNKT083kZGRpnHjxmbjxo1m7dq1pk6dOtYfZGMudVQfHx/TsWNHs23bNrNixQoTEhJi/u///u+a38FMKSkpxsXFJcv/wPXs2dPcf//9N5weQN5jH8E+orDsI65W0IGfPkGfKGx9whhj9u7daySZbdu23dT0uUV/oD8U1v6QlpZmPvvsM+Pu7m62b9+eq2ltG/hPnDhhPDw8zMGDB83BgweNp6enOXnypFNHvdrJkyed/qhc69qb2NhYExwcbFJSUpzar+6oKSkpJjIy0nTp0sWEh4ebRx991Gn8nTt3Wr9OZWrSpIl55JFHjDHG9O3b1zz22GNO06xcudIUKVLE/PXXX2b37t1Gklm8eHG265PdtTdnz541bm5uZubMmVbbxYsXTenSpc1rr73mNN2XX36ZZZ7/93//Zx544AHrfYcOHaxfvYwxZtSoUSYsLMxcvHgx25qyu/bm6u28ZcsW43A4zKFDh4wxxvq1LvPXyuzMmTPHFC9e3Hp/rWtvrvyMfvjhB+Pi4mIOHz5sDd++fbuRZP1SOXbsWFO0aFGnX+JGjBhh6tevf81aMv3xxx9Gklm9erVT+4gRI0y9evVuOD2AvMc+4jL2Ef5ZxsvPfcTVCjrw0yfoE4WtT6Snp5u2bduaRo0a5Xram0V/uIz+4J9lvILoD7/++qvx9vY2Li4uxt/f3/z3v//N8bSZbHkNv3TpGou2bdtq+vTpmjZtmtq2basSJUo4jbN3715169ZNFStWlJ+fnypUqCBJOnz48A3nHxERIXd39+uO4+7urpkzZ2revHm6cOGCJk6c6DS8WrVqatiwoT7++GNJ0r59+7Ry5Ur17dtXkvTLL79o+vTp8vHxsV4xMTHKyMjQgQMHtHXrVrm4uCg6Ojqnm0X79+9XamqqGjVqZLW5ubmpXr162rlzp9O4devWdXqfnp6uGTNm6JFHHrHaHnnkEU2fPl0ZGRmSpK1bt6pJkyZyc3PLcU1Xi4yMVPXq1TVr1ixJl67nOnHihDp37myN8+OPP6p58+YqU6aMfH191aNHD506dUrnz5/P8XJ27typ0NBQhYaGWm3h4eEKCAhw2hYVKlSQr6+v9b5UqVJcgw/8zbGPyB77iMv+1/YR9Ins0Scuy+8+MXDgQP3222+aPXt2rqe9VfSH7NEfLsuv/nDHHXdo69atWrdunQYMGKDY2Fjt2LEjx9NLNn8sX58+fTR9+nTNmDFDffr0yTK8ffv2SkhI0NSpU7Vu3TqtW7dO0uWbZ1yPt7d3jmpYvXq1JCkhIUEJCQlZhvft21fz5s3TmTNnNG3aNFWqVMnqeGfPnlX//v21detW6/XLL79o7969qlSpkry8vHJUw826eh2///57/fHHH3r44Yfl6uoqV1dXde3aVYcOHdKSJUskKc9q6t69u9VRZ82apdatW6t48eKSLj1+o127dqpZs6bmzZunTZs2WTc8yslnl1tX/9FxOBzWH6brKVGihFxcXBQfH+/UHh8fr5CQkDytEUDusY+4NewjLrnZfURhRJ+4NfSJS/KiTwwaNEgLFy7UsmXLVLZs2bwsL8foD7eG/nDJrfYHd3d3Va5cWXXq1NGECRNUq1Ytvfnmm7mqwdaBv3Xr1rp48aJSU1MVExPjNOzUqVPavXu3nnvuOTVv3lzVq1fX6dOnncbJ/OUtPT39ppa/f/9+DR06VFOnTlX9+vUVGxub5QPu0qWLihQpolmzZumTTz5Rnz595HA4JEl33XWXduzYocqVK2d5ubu7KyIiQhkZGVq+fHm2y8+u/kqVKsnd3V2rVq2y2lJTU7VhwwaFh4dfd30++ugjde3a1ekPx9atW9W1a1d99NFHkqSaNWtq5cqVSk1NvWZNOdme//jHP/Tbb79p06ZNmjt3rrp3724N27RpkzIyMvT666+rQYMGqlq1qo4dO5br5VSvXl1HjhzRkSNHrLYdO3YoMTHxhtsiJ9zd3VWnTh3rj5gkZWRkaMmSJYqKirrl+QO4Newj2Edcz+3eRxRG9An6xPXkR58wxmjQoEFasGCBli5dqrCwsDyZ782gP9Afrqeg9hEZGRlKSUnJ3US5vgigkLv62o6kpCSTlJRkvc+89iY9Pd0UL17cPPLII2bv3r1myZIl5u6773a6hi41NdV4eXmZl156ycTFxVk3q8ju+hFjnK/rSEtLMw0aNDCdOnUyxhhz7NgxU7x4cev6liv17dvXFCtWzLi4uJg//vjDav/ll1+Ml5eXGThwoNmyZYvZs2eP+fLLL53u+t6rVy8TGhpqFixYYH7//XezbNky8/nnnxtjLt34wuFwmOnTp5sTJ05YN5x46qmnTOnSpc2iRYucbraRkJBgjMn+mp0TJ04YNzc3s2jRoiz1f/vtt8bDw8OcOnXK/Pnnn6Z48eLWzTb27NljPvnkE+sZqi+//LIpV66c2bVrlzl58qS5ePHiNa9xatSokalVq5bx9fU158+ft9q3bt1qJJlJkyaZ/fv3m08++cSUKVPGqeZVq1ZZN0o5efKk9czMKz+jjIwMExkZaZo0aWI2bdpk1q1bl+3NNmrVquVU18SJE0358uWzbIfszJ4923h4eJjp06ebHTt2mMcee8wEBAQ43cETQP5hH8E+wpjCs484c+aM2bJli9myZYuRZN544w2zZcsW69rT/ECfoE8YU3j6xIABA4y/v7/56aefrBumHT9+3Gl9bif6A/3BmMLTH0aOHGmWL19uDhw4YH799VczcuRI43A4zA8//JCj6TPZPvBf7cqbbSxevNhUr17deHh4mJo1a5qffvopy01zpk6dakJDQ02RIkWyPE7jald+CcaNG2dKlSpl/vzzT2v4vHnzjLu7u9m6davTdKtXrzaSzH333ZdlnuvXrzctW7Y0Pj4+xtvb29SsWdO8/PLL1vC//vrLDB061JQqVcq4u7ubypUrm48//tga/sILL5iQkBDjcDis9f7rr7/M4MGDTYkSJa77OI0rO+q///1vExAQkO1NNFJSUkxAQIB58803jTGX/sC0atXKFC1a1Pj6+pomTZqY/fv3G2MudfjM9VE2j9O40uTJk40k07NnzyzLfOONN0ypUqWMl5eXiYmJMZ988kmWmh9//HFTvHjxPHmcxpVy01GNMebtt9825cqVM+7u7qZevXpm7dq1OZ4WQN5iH8E+IlNh2Edk9/gnXfH4q/xAn6BPZCoMfSK7/iDJTJs2LUfT3yr6A/0hU2HoD3369DHly5c37u7upmTJkqZ58+a5DvvGGOMwxpjcnRMAAAAAAAAKO1tfww8AAAAAwP8qAj9wkw4fPuz0qJOrXzl5LAsAwJ7YRwDO6BPAZfnZHzilH7hJaWlpOnjw4DWHV6hQQa6urvlXEACg0GAfATijTwCX5Wd/IPADAAAAAGBDnNIPAAAAAIANEfgBAAAAALAhAj8AAAAAADZE4AcAAAAAwIYI/AAAIFeaNWumIUOGFHQZAADgBgj8AADkk169esnhcOiVV15xav/yyy/lcDhyNa8KFSpo0qRJeVjd7XPw4EE5HA5t3bq1oEsBAOB/CoEfAIB85OnpqVdffVWnT58u6FJy7eLFiwVdQp5KTU0t6BIAALitCPwAAOSjFi1aKCQkRBMmTLjueD///LOaNGkiLy8vhYaG6sknn9S5c+ckXTql/tChQxo6dKgcDoccDoeMMSpZsqTmzp1rzSMyMlKlSpVymqeHh4fOnz8vSTp8+LA6dOggHx8f+fn5qUuXLoqPj7fGf/755xUZGakPP/xQYWFh8vT0zLbW//73v/L399fMmTNvapvs379fHTp0UHBwsHx8fHT33Xfrxx9/tIa/8MILuvPOO7NMFxkZqdGjR1vvP/zwQ1WvXl2enp6qVq2aJk+ebA3LPMvg888/V3R0tDw9PTVz5kwdOnRI7du3V7FixeTt7a0aNWro22+/van1AACgsCHwAwCQj1xcXDR+/Hi9/fbbOnr0aLbj7N+/X61bt1anTp3066+/6vPPP9fPP/+sQYMGSZLmz5+vsmXL6oUXXtDx48d1/PhxORwONW3aVD/99JMk6fTp09q5c6f++usv7dq1S5K0fPly3X333SpatKgyMjLUoUMHJSQkaPny5Vq8eLF+//13Pfzww0617Nu3T/PmzdP8+fOzPSV/1qxZ6tatm2bOnKnu3bvf1DY5e/as7rvvPi1ZskRbtmxR69at1b59ex0+fFiS1KdPH+3cuVMbNmywptmyZYt+/fVX9e7dW5I0c+ZMjRkzRi+//LJ27typ8ePHa/To0ZoxY4bTskaOHKmnnnpKO3fuVExMjAYOHKiUlBStWLFC27Zt06uvviofH5+bWg8AAAob14IuAACA/zUPPvigIiMjNXbsWH300UdZhk+YMEHdu3e3boxXpUoVvfXWW4qOjtZ7772nwMBAubi4yNfXVyEhIdZ0zZo10wcffCBJWrFihWrXrq2QkBD99NNPqlatmn766SdFR0dLkpYsWaJt27bpwIEDCg0NlSR98sknqlGjhjZs2KC7775b0qXT+D/55BOVLFkyS53vvvuu/vnPf+qbb76x5nszatWqpVq1alnvX3zxRS1YsEBff/21Bg0apLJlyyomJkbTpk2z6po2bZqio6NVsWJFSdLYsWP1+uuvq2PHjpKksLAw7dixQx988IFiY2OteQ8ZMsQaR7p0lkOnTp0UEREhSdb8AACwA47wAwBQAF599VXNmDFDO3fuzDLsl19+0fTp0+Xj42O9YmJilJGRoQMHDlxzntHR0dqxY4dOnjyp5cuXq1mzZmrWrJl++uknpaamavXq1WrWrJkkaefOnQoNDbXCviSFh4crICDAqaby5ctnG/bnzp2roUOHavHixbcU9qVLR/iHDx+u6tWrKyAgQD4+Ptq5c6d1hF+SHn30UX322We6cOGCLl68qFmzZqlPnz6SpHPnzmn//v3q27ev0zZ76aWXtH//fqdl1a1b1+n9k08+qZdeekmNGjXS2LFj9euvv97SugAAUJgQ+AEAKABNmzZVTEyMRo0alWXY2bNn1b9/f23dutV6/fLLL9q7d68qVap0zXlGREQoMDBQy5cvdwr8y5cv14YNG5SamqqGDRvmqk5vb+9s22vXrq2SJUvq448/ljEmV/O82vDhw7VgwQKNHz9eK1eu1NatWxUREeF0k8D27dvLw8NDCxYs0DfffKPU1FQ99NBDki5tL0maOnWq0zb77bfftHbt2uuuT79+/fT777+rR48e2rZtm+rWrau33377ltYHAIDCglP6AQAoIK+88ooiIyN1xx13OLXfdddd2rFjhypXrnzNad3d3ZWenu7U5nA41KRJE3311Vfavn27GjdurKJFiyolJUUffPCB6tatawXe6tWr68iRIzpy5Ih1lH/Hjh1KTExUeHj4DWuvVKmSXn/9dTVr1kwuLi565513crv6llWrVqlXr1568MEHJV0K8AcPHnQax9XVVbGxsZo2bZrc3d3VtWtXeXl5SZKCg4NVunRp/f777zd1H4HQ0FA9/vjjevzxxzVq1ChNnTpVgwcPvun1AQCgsCDwAwBQQCIiItS9e3e99dZbTu3PPvusGjRooEGDBqlfv37y9vbWjh07tHjxYitYV6hQQStWrFDXrl3l4eGhEiVKSLp0Hf/TTz+tunXrWjefa9q0qWbOnKkRI0ZYy2jRooW1/EmTJiktLU1PPPGEoqOjs5z2fi1Vq1bVsmXL1KxZM7m6umrSpEnXHX/37t1Z2mrUqKEqVapo/vz5at++vRwOh0aPHq2MjIws4/br10/Vq1eXdOlHgiuNGzdOTz75pPz9/dW6dWulpKRo48aNOn36tIYNG3bNmoYMGaI2bdqoatWqOn36tJYtW2YtAwCAvztO6QcAoAC98MILWcJtzZo1tXz5cu3Zs0dNmjRR7dq1NWbMGJUuXdppuoMHD6pSpUpO19hHR0crPT3dulZfuvQjwNVtDodDX331lYoVK6amTZuqRYsWqlixoj7//PNc1X/HHXdo6dKl+uyzz/T0009fd9yuXbuqdu3aTq/4+Hi98cYbKlasmBo2bKj27dsrJiZGd911V5bpq1SpooYNG6patWqqX7++07B+/frpww8/1LRp0xQREaHo6GhNnz5dYWFh160pPT1dAwcOVPXq1dW6dWtVrVrV6XF+AAD8nTnMrV54BwAAkA+MMapSpYqeeOKJ6x61BwAAl3BKPwAAKPROnjyp2bNnKy4uTr179y7ocgAA+Fsg8AMAgEIvKChIJUqU0JQpU1SsWLGCLgcAgL8FAj8AACj0uAIRAIDc46Z9AAAAAADYEIEfAAAAAAAbIvADAAAAAGBDBH4AAAAAAGyIwA8AAAAAgA0R+AEAAAAAsCECPwAAAAAANkTgBwAAAADAhv4fvqS0ZW20Rz0AAAAASUVORK5CYII=", "text/plain": [ - "
    " + "{'MatrixVectorActivation_0': {'BRAM_18K': 8,\n", + " 'BRAM_efficiency': 0.5208333333333334,\n", + " 'LUT': 418,\n", + " 'URAM': 0,\n", + " 'URAM_efficiency': 1,\n", + " 'DSP': 0},\n", + " 'StreamingDataWidthConverter_Batch_0': {'BRAM_18K': 0,\n", + " 'BRAM_efficiency': 1,\n", + " 'LUT': 3,\n", + " 'URAM': 0,\n", + " 'URAM_efficiency': 1,\n", + " 'DSP': 0},\n", + " 'MatrixVectorActivation_1': {'BRAM_18K': 1,\n", + " 'BRAM_efficiency': 0.4444444444444444,\n", + " 'LUT': 320,\n", + " 'URAM': 0,\n", + " 'URAM_efficiency': 1,\n", + " 'DSP': 0},\n", + " 'MatrixVectorActivation_2': {'BRAM_18K': 1,\n", + " 'BRAM_efficiency': 0.4444444444444444,\n", + " 'LUT': 320,\n", + " 'URAM': 0,\n", + " 'URAM_efficiency': 1,\n", + " 'DSP': 0},\n", + " 'MatrixVectorActivation_3': {'BRAM_18K': 1,\n", + " 'BRAM_efficiency': 0.006944444444444444,\n", + " 'LUT': 320,\n", + " 'URAM': 0,\n", + " 'URAM_efficiency': 1,\n", + " 'DSP': 0}}" ] }, + "execution_count": 42, "metadata": {}, - "output_type": "display_data" + "output_type": "execute_result" } ], "source": [ - "layers_DWC = list(res_dict_DWC.keys())\n", - "print(layers_DWC)\n", - "utilisation_DWC = list(res_dict_DWC.values())\n", - "lut_values_DWC = [] #Initializing a list to store LUT values.\n", - "for i in range(len(layers_DWC)):\n", - " x = list(utilisation_DWC[i].values()) #Extracting the resource utilisation for each layer.\n", - " lut_values_DWC.append(x[2]) #Extracting the LUT values of resource utilisation from each layer and appending to the list\n", - "\n", - "#Plotting the bar graph of each network layer with their corresponding LUT resource utilisation\n", - "fig = plt.figure(figsize = (12, 5))\n", - "plt.bar(layers_DWC, lut_values_DWC, color ='red', width = 0.3)\n", - "plt.xlabel(\"Network Layers\")\n", - "plt.ylabel(\"LUT Utilisation\")\n", - "plt.title(\"Estimated LUT values used for each network layer\")\n", - "plt.show()" + "model_dwc = ModelWrapper(\"cybsec_DWC.onnx\")\n", + "res_dict_dwc = model_dwc.analysis(res_estimation)\n", + "res_dict_dwc" ] }, { "cell_type": "markdown", "metadata": {}, "source": [ - "The `StreamingDataWidthConverter` layer does not consume a large number of LUT resources as shown in the above graph." + "Since we have now one additional layer, we manipulate the data to shorten the layer names in the plot." ] }, { - "cell_type": "markdown", + "cell_type": "code", + "execution_count": 48, "metadata": {}, + "outputs": [], "source": [ - "
    \n", - "Question: The name of the 'StreamingDataWidthConverter' layer is not coming in the graph.\n", - "
    " + "layers = res_dict_dwc.keys()\n", + "# replace names of layers with abbreviations\n", + "layers = [n.replace(\"MatrixVectorActivation_\", \"MVU\") for n in layers]\n", + "layers = [n.replace(\"StreamingDataWidthConverter_Batch\", \"DWC\") for n in layers]" ] }, { - "cell_type": "markdown", + "cell_type": "code", + "execution_count": 50, "metadata": {}, + "outputs": [ + { + "data": { + "image/png": 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kBQYGZmpPT09XUlKS7XKf9evXa+zYsYqLi9Pff/9tN39SUpJtXTdy4MAB7dy5UyVKlMhyesYN/8eOHVPJkiXl5eVlN/2+++67xd7lrJwa0rx48eJq1qyZ5s6dq4kTJ0q6dlmfm5ubOnbsaJsv4x6XadOm6ciRI0pLS7NNy84lV9lx4MABJSUlyc/PL8vpGd9BWFiYIiMjNX78eE2ePFnh4eHq0KGDnnzySXl4eORILRMmTNCjjz6qKlWqqGbNmmrVqpW6d++uWrVqSZIOHjwowzA0evRojR49+ob1li5dWseOHVPdunUzTb+TPnPs2LEbrqNq1ar6+eef7drc3NxUpkyZW6737NmzOn/+vGbMmKEZM2ZkOU/G9yBJM2fO1DvvvKN9+/bZhdrrR/08dOiQSpUqJV9f31tu/9/HAEkqWrRopnvksrt80aJFJcm2fEYwvtmluElJSbblsuLq6qrQ0FCtW7dO0rUg1ahRIzVs2FBpaWnauHGj/P39lZiYaBekbtQPMi55PnbsmGrWrGlrz2rk1Azdu3eXm5ub9u7dq4CAgBvOdyvHjx/XmDFj9N1332X6jK//A1SLFi1UsmRJzZo1S82aNVN6erq++uorPfrooypSpIik2/tsb7aPQH5HkALuUX5+ftqxY4d++OEHLV26VEuXLlVMTIx69OihmTNn3vZ6XV1dTbUb//+a+kOHDqlZs2aqWrWq3n33XQUGBsrd3V3ff/+9Jk+enK2b+tPT09WiRQu99NJLWU6vUqVKNvfiznl4eNjd7H29jJB4/VmIO9WlSxf16tVLO3bsUEhIiObOnatmzZrZ7guRrt1UPnr0aPXu3VsTJ06Ur6+vXFxcNGTIkFt+vhaLJcv7H64PY9K178DPz0+zZs3Kcj0ZITfjOVwbN27U4sWL9cMPP6h379565513tHHjxkwhNzv+XUvjxo116NAhffvtt/rxxx/1ySefaPLkyZo+fbr69u1r2+fhw4crIiIiy3WaeVxAbrv+jOLNZOzXU089dcNfiDPC5JdffqmePXuqQ4cOevHFF+Xn5ydXV1dFR0fr0KFDt1XnrX7W73T5jP17++237e7hul52+k/Dhg31+uuv6/Lly1q3bp1eeeUV+fj4qGbNmlq3bp3t3svrg5RZN7uHrmPHjvr888/13nvvKTo6+rbWn5aWZru/asSIEapataoKFy6sP/74Qz179rT7uXZ1ddWTTz6pjz/+WNOmTdP69et16tQpu9FBb+ezzc59gkB+RZAC7mHu7u5q37692rdvr/T0dD3zzDP66KOPNHr0aFWqVOmuPgR28eLFSklJ0XfffWf3F+msRg+7UV0VK1bUxYsXb/mcnnLlymnFihW6ePGi3S8FZkfLutU2brS+jPbbvZQnKx06dFD//v1tl/f9/vvvGjVqlN088+fPV5MmTfTpp5/atZ8/f94ucGWlaNGiWV6alXFWJUPFihX1008/qUGDBtn6BatevXqqV6+eXn/9dc2ePVvdunXTnDlz1Ldv35vW8u8RFq9cuaLTp09nmtfX11e9evVSr169dPHiRTVu3Fjjxo1T3759VaFCBUlSgQIFstVnsrpE8E76TMb3v3//fjVt2jTTem+3f5QoUUJFihRRWlraLfdr/vz5qlChghYuXGj3c/XvS/gqVqyoH374QYmJidk6K5WbMi4btFqtt9y/mx3DGjVqpCtXruirr77SH3/8YQtMjRs3tgWpKlWq2AKVdOOf63379tmmZ9ezzz6rSpUqacyYMfL29tbIkSOzvWyGXbt26ffff9fMmTPVo0cPW/uNLtnu0aOH3nnnHS1evFhLly5ViRIl7P6IYOazBcDw58A969y5c3bvXVxcbH+lzhiWPON5IHdjWPCMv0Jf/1frpKQkxcTEZJq3cOHCWdb0+OOPKy4uTj/88EOmaefPn7fdj9WmTRulpqbaDa2elpamqVOn3ulu2LRp00YbN27U1q1bM9Uxa9YshYSE3NHlPP/m4+OjiIgIzZ07V3PmzJG7u7s6dOhgN4+rq2umswLz5s3LNNR2VipWrKh9+/bp7NmztrZff/0105DIjz/+uNLS0myXGF4vNTXV9r399ddfmWrJ+Av4v4fFz6qWjHtbMsyYMSPTGal/93EvLy9VqlTJtn4/Pz+Fh4fro48+yjKEXb+vGd/nL7/8Yjf9RmfesqNOnTry8/PT9OnT7fZ56dKl2rt3r9q2bXtb63V1dVVkZKQWLFig3377LdP06/crq5+7TZs2KS4uzm6ZyMhIGYaR5TD72T3TlFNq166tihUr6j//+Y8uXryYafr1+3ezY1jdunVVoEABvfnmm/L19VWNGjUkXQtYGzdu1Jo1azKdjWrTpo1++eUXu8/n0qVLmjFjhsqXL6/q1aub2pfRo0dr+PDhGjVqVKZHPWRHVt+fYRi2x1j8W61atVSrVi198sknWrBggbp06SI3t//7m7qZzxYAZ6SAfGvp0qW2v5Jer379+qpQoYL69u2rxMRENW3aVGXKlNGxY8c0depUhYSE2K73DwkJkaurq958800lJSXJw8PD9pynnNayZUvbGbL+/fvr4sWL+vjjj+Xn55fpl9zatWvrww8/1GuvvaZKlSrJz89PTZs21YsvvqjvvvtO7dq1U8+ePVW7dm1dunRJu3bt0vz583X06FEVL15c7du3V4MGDTRy5EgdPXpU1atX18KFC7M1oMX1FixYkOVnHBUVpZEjR2revHlq3Lix+vfvr6pVq+rUqVOKjY3V6dOnswyId+qJJ57QU089pWnTpikiIiLTw1/btWunCRMmqFevXqpfv7527dqlWbNm2c7M3Ezv3r317rvvKiIiQn369NGZM2c0ffp01ahRw+7ZOGFhYerfv7+io6O1Y8cOtWzZUgUKFNCBAwc0b948vffee+rUqZNmzpypadOm6bHHHlPFihV14cIFffzxx7JarWrTps1Na+nbt68GDBigyMhItWjRQr/++qt++OGHTGfVqlevrvDwcNWuXVu+vr7asmWL5s+fr8GDB9vm+eCDD9SwYUMFBwerX79+qlChghISEhQXF6eTJ0/anrH10ksv6YsvvlCrVq30/PPP24Y/L1eunHbu3HnLzy8rGb/E9+rVS2FhYeratatt+PPy5ctr6NCht7Ve6doQ4qtWrVLdunXVr18/Va9eXYmJidq2bZt++uknJSYmSrrWJxYuXKjHHntMbdu21ZEjRzR9+nRVr17d7hfpJk2aqHv37nr//fd14MABtWrVSunp6Vq3bp2aNGli95nmNhcXF33yySdq3bq1atSooV69eql06dL6448/tGrVKlmtVi1evFjStWOFdG0I+i5duqhAgQJq3769ChcurEKFCql27drauHGj7RlS0rUzUpcuXdKlS5cyBamRI0fqq6++UuvWrfXcc8/J19dXM2fO1JEjR7RgwYJsXXr5b2+//baSkpI0aNAgFSlSxNSDuKtWraqKFStq+PDh+uOPP2S1WrVgwYKb3o/Wo0cPDR8+XJIybcvMZwtADH8O5Dc3G/5c1w1zO3/+fKNly5aGn5+f4e7ubpQtW9bo37+/cfr0abv1ffzxx0aFChUMV1dXu2F3bzT8+b+HBM9q2GfD+L+hc8+ePWtr++6774xatWoZBQsWNMqXL2+8+eabxmeffZZp+OL4+Hijbdu2RpEiRQxJdnVcuHDBGDVqlFGpUiXD3d3dKF68uFG/fn3jP//5j92w7OfOnTO6d+9uWK1Ww9vb2+jevbuxfft2U8Of3+iVMTTyyZMnjb59+xqlS5c23NzcDF9fX6Ndu3bGxo0bb7p+s8OfZ0hOTjY8PT0NScaXX36Zafrly5eNF154wShZsqTh6elpNGjQwIiLi8v0XWY1/LlhGMaXX35pVKhQwXB3dzdCQkKMH374IdPw5xlmzJhh1K5d2/D09DSKFCliBAcHGy+99JJx6tQpwzCuDbvctWtXo2zZsoaHh4fh5+dntGvXztiyZcst9zMtLc0YMWKEUbx4caNQoUJGRESEcfDgwUzDn7/22mvGww8/bPj4+Bienp5G1apVjddff92uHxiGYRw6dMjo0aOHERAQYBQoUMAoXbq00a5dO2P+/Pl28+3cudMICwszChYsaJQuXdqYOHGi8emnn9728OcZvv76a+OBBx4wPDw8DF9fX6Nbt27GyZMn7eaJiooyChcufMvP5noJCQnGoEGDjMDAQKNAgQJGQECA0axZM2PGjBm2edLT041JkyYZ5cqVMzw8PIwHHnjAWLJkSZbfa2pqqvH2228bVatWNdzd3Y0SJUoYrVu3NrZu3WqbRzcY9v/f301WbnQMuVF/3L59u9GxY0ejWLFihoeHh1GuXDnj8ccfN1asWGE338SJE43SpUsbLi4umb6rF1980ZBkvPnmm3bLVKpUyZBkHDp0KFOdhw4dMjp16mT4+PgYBQsWNB5++GFjyZIl2doXw8i6L6SlpRldu3Y13NzcjG+++eaWn9H1w5/v2bPHaN68ueHl5WUUL17c6Nevn23I+ayOZadPnzZcXV2NKlWq3HA72flsszqGA/cai2Hw9DQAAIB7wZ9//qmSJUtqzJgxNxytEkD2cI8UAADAPSI2NlZpaWnq3r27o0sB8jzukQIAAMjnVq5cqT179uj1119Xhw4dVL58eUeXBOR5XNoHAACQz4WHh2vDhg1q0KCBvvzyS5UuXdrRJQF5HkEKAAAAAEziHikAAAAAMIkgBQAAAAAmMdiEpPT0dJ06dUpFihSxPZAPAAAAwL3HMAxduHBBpUqVuumDtglSkk6dOqXAwEBHlwEAAADASZw4cUJlypS54XSClKQiRYpIuvZhWa1WB1cDAAAAwFGSk5MVGBhoywg3QpCSbJfzWa1WghQAAACAW97yw2ATAAAAAGASQQoAAAAATCJIAQAAAIBJBCkAAAAAMIkgBQAAAAAmEaQAAAAAwCSCFAAAAACYRJACAAAAAJMIUgAAAABgEkEKAAAAAEwiSAEAAACASQQpAAAAADCJIAUAAAAAJhGkAAAAAMAkghQAAAAAmOTm6AKQBYvF0RXcOcNwdAUAAABAruGMFAAAAACYRJACAAAAAJMIUgAAAABgEkEKAAAAAEwiSAEAAACASQQpAAAAADCJIAUAAAAAJhGkAAAAAMAkghQAAAAAmESQAgAAAACTCFIAAAAAYJLTBKk33nhDFotFQ4YMsbVdvnxZgwYNUrFixeTl5aXIyEglJCTYLXf8+HG1bdtWhQoVkp+fn1588UWlpqbe5eoBAAAA3EucIkht3rxZH330kWrVqmXXPnToUC1evFjz5s3TmjVrdOrUKXXs2NE2PS0tTW3bttWVK1e0YcMGzZw5U7GxsRozZszd3gUAAAAA9xCHB6mLFy+qW7du+vjjj1W0aFFbe1JSkj799FO9++67atq0qWrXrq2YmBht2LBBGzdulCT9+OOP2rNnj7788kuFhISodevWmjhxoj744ANduXLFUbsEAAAAIJ9zeJAaNGiQ2rZtq+bNm9u1b926VVevXrVrr1q1qsqWLau4uDhJUlxcnIKDg+Xv72+bJyIiQsnJydq9e/cNt5mSkqLk5GS7FwAAAABkl5sjNz5nzhxt27ZNmzdvzjQtPj5e7u7u8vHxsWv39/dXfHy8bZ7rQ1TG9IxpNxIdHa3x48ffYfUAAAAA7lUOOyN14sQJPf/885o1a5YKFix4V7c9atQoJSUl2V4nTpy4q9sHAAAAkLc5LEht3bpVZ86c0YMPPig3Nze5ublpzZo1ev/99+Xm5iZ/f39duXJF58+ft1suISFBAQEBkqSAgIBMo/hlvM+YJyseHh6yWq12LwAAAADILocFqWbNmmnXrl3asWOH7VWnTh1169bN9u8CBQpoxYoVtmX279+v48ePKzQ0VJIUGhqqXbt26cyZM7Z5li9fLqvVqurVq9/1fQIAAABwb3DYPVJFihRRzZo17doKFy6sYsWK2dr79OmjYcOGydfXV1arVc8++6xCQ0NVr149SVLLli1VvXp1de/eXW+99Zbi4+P16quvatCgQfLw8Ljr+wQAAADg3uDQwSZuZfLkyXJxcVFkZKRSUlIUERGhadOm2aa7urpqyZIlGjhwoEJDQ1W4cGFFRUVpwoQJDqwaAAAAQH5nMQzDcHQRjpacnCxvb28lJSU5x/1SFoujK7hzdCsAAADkQdnNBg5/jhQAAAAA5DUEKQAAAAAwiSAFAAAAACYRpAAAAADAJIIUAAAAAJhEkAIAAAAAkwhSAAAAAGASQQoAAAAATCJIAQAAAIBJBCkAAAAAMIkgBQAAAAAmEaQAAAAAwCSCFAAAAACYRJACAAAAAJMIUgAAAABgEkEKAAAAAEwiSAEAAACASQQpAAAAADCJIAUAAAAAJhGkAAAAAMAkghQAAAAAmESQAgAAAACTCFIAAAAAYBJBCgAAAABMIkgBAAAAgEkEKQAAAAAwiSAFAAAAACYRpAAAAADAJIIUAAAAAJhEkAIAAAAAkwhSAAAAAGASQQoAAAAATCJIAQAAAIBJDg1SH374oWrVqiWr1Sqr1arQ0FAtXbrUNj08PFwWi8XuNWDAALt1HD9+XG3btlWhQoXk5+enF198UampqXd7VwAAAADcQ9wcufEyZcrojTfeUOXKlWUYhmbOnKlHH31U27dvV40aNSRJ/fr104QJE2zLFCpUyPbvtLQ0tW3bVgEBAdqwYYNOnz6tHj16qECBApo0adJd3x8AAAAA9waLYRiGo4u4nq+vr95++2316dNH4eHhCgkJ0ZQpU7Kcd+nSpWrXrp1OnTolf39/SdL06dM1YsQInT17Vu7u7tnaZnJysry9vZWUlCSr1ZpTu3L7LBZHV3DnnKtbAQAAANmS3WzgNPdIpaWlac6cObp06ZJCQ0Nt7bNmzVLx4sVVs2ZNjRo1Sn///bdtWlxcnIKDg20hSpIiIiKUnJys3bt333BbKSkpSk5OtnsBAAAAQHY59NI+Sdq1a5dCQ0N1+fJleXl5adGiRapevbok6cknn1S5cuVUqlQp7dy5UyNGjND+/fu1cOFCSVJ8fLxdiJJkex8fH3/DbUZHR2v8+PG5tEcAAAAA8juHB6n77rtPO3bsUFJSkubPn6+oqCitWbNG1atX19NPP22bLzg4WCVLllSzZs106NAhVaxY8ba3OWrUKA0bNsz2Pjk5WYGBgXe0HwAAAADuHQ6/tM/d3V2VKlVS7dq1FR0drfvvv1/vvfdelvPWrVtXknTw4EFJUkBAgBISEuzmyXgfEBBww216eHjYRgrMeAEAAABAdjk8SP1benq6UlJSspy2Y8cOSVLJkiUlSaGhodq1a5fOnDljm2f58uWyWq22ywMBAAAAIKc59NK+UaNGqXXr1ipbtqwuXLig2bNna/Xq1frhhx906NAhzZ49W23atFGxYsW0c+dODR06VI0bN1atWrUkSS1btlT16tXVvXt3vfXWW4qPj9err76qQYMGycPDw5G7BgAAACAfc2iQOnPmjHr06KHTp0/L29tbtWrV0g8//KAWLVroxIkT+umnnzRlyhRdunRJgYGBioyM1Kuvvmpb3tXVVUuWLNHAgQMVGhqqwoULKyoqyu65UwAAAACQ05zuOVKOwHOkcgHdCgAAAHlQnnuOFAAAAADkFQQpAAAAADCJIAUAAAAAJhGkAAAAAMAkghQAAAAAmESQAgAAAACTCFIAAAAAYBJBCgAAAABMIkgBAAAAgEkEKQAAAAAwiSAFAAAAACYRpAAAAADAJIIUAAAAAJhEkAIAAAAAkwhSAAAAAGASQQoAAAAATCJIAQAAAIBJBCkAAAAAMIkgBQAAAAAmuTm6AAAAss1icXQFd84wHF0BckJ+6IsS/TG/yA/9MQ/2Rc5IAQAAAIBJBCkAAAAAMIkgBQAAAAAmEaQAAAAAwCSCFAAAAACYRJACAAAAAJMIUgAAAABgEkEKAAAAAEwiSAEAAACASQQpAAAAADCJIAUAAAAAJhGkAAAAAMAkghQAAAAAmOTQIPXhhx+qVq1aslqtslqtCg0N1dKlS23TL1++rEGDBqlYsWLy8vJSZGSkEhIS7NZx/PhxtW3bVoUKFZKfn59efPFFpaam3u1dAQAAAHAPcWiQKlOmjN544w1t3bpVW7ZsUdOmTfXoo49q9+7dkqShQ4dq8eLFmjdvntasWaNTp06pY8eOtuXT0tLUtm1bXblyRRs2bNDMmTMVGxurMWPGOGqXAAAAANwDLIZhGI4u4nq+vr56++231alTJ5UoUUKzZ89Wp06dJEn79u1TtWrVFBcXp3r16mnp0qVq166dTp06JX9/f0nS9OnTNWLECJ09e1bu7u7Z2mZycrK8vb2VlJQkq9Waa/uWbRaLoyu4c87VrQDkFxwf4SzyQ1+U6I/5RX7oj07UF7ObDZzmHqm0tDTNmTNHly5dUmhoqLZu3aqrV6+qefPmtnmqVq2qsmXLKi4uTpIUFxen4OBgW4iSpIiICCUnJ9vOamUlJSVFycnJdi8AAAAAyC6HB6ldu3bJy8tLHh4eGjBggBYtWqTq1asrPj5e7u7u8vHxsZvf399f8fHxkqT4+Hi7EJUxPWPajURHR8vb29v2CgwMzNmdAgAAAJCvOTxI3XfffdqxY4c2bdqkgQMHKioqSnv27MnVbY4aNUpJSUm214kTJ3J1ewAAAADyFzdHF+Du7q5KlSpJkmrXrq3Nmzfrvffe0xNPPKErV67o/PnzdmelEhISFBAQIEkKCAjQL7/8Yre+jFH9MubJioeHhzw8PHJ4TwAAAADcKxx+Rurf0tPTlZKSotq1a6tAgQJasWKFbdr+/ft1/PhxhYaGSpJCQ0O1a9cunTlzxjbP8uXLZbVaVb169bteOwAAAIB7g0PPSI0aNUqtW7dW2bJldeHCBc2ePVurV6/WDz/8IG9vb/Xp00fDhg2Tr6+vrFarnn32WYWGhqpevXqSpJYtW6p69erq3r273nrrLcXHx+vVV1/VoEGDOOMEAAAAINc4NEidOXNGPXr00OnTp+Xt7a1atWrphx9+UIsWLSRJkydPlouLiyIjI5WSkqKIiAhNmzbNtryrq6uWLFmigQMHKjQ0VIULF1ZUVJQmTJjgqF0CAAAAcA9wuudIOQLPkcoFdCsAuYHjI5xFfuiLEv0xv8gP/dGJ+mKee44UAAAAAOQVBCkAAAAAMIkgBQAAAAAmEaQAAAAAwCSCFAAAAACYRJACAAAAAJMIUgAAAABgEkEKAAAAAEwiSAEAAACASQQpAAAAADCJIAUAAAAAJhGkAAAAAMAkghQAAAAAmESQAgAAAACTCFIAAAAAYBJBCgAAAABMcrudhQ4cOKBVq1bpzJkzSk9Pt5s2ZsyYHCkMAAAAAJyV6SD18ccfa+DAgSpevLgCAgJksVhs0ywWC0EKAAAAQL5nOki99tprev311zVixIjcqAcAAAAAnJ7pe6T++usvde7cOTdqAQAAAIA8wXSQ6ty5s3788cfcqAUAAAAA8gTTl/ZVqlRJo0eP1saNGxUcHKwCBQrYTX/uuedyrDgAAAAAcEYWwzAMMwsEBQXdeGUWiw4fPnzHRd1tycnJ8vb2VlJSkqxWq6PLka4bwCPPMtetACB7OD7CWeSHvijRH/OL/NAfnagvZjcbmD4jdeTIkTsqDAAAAADyujt6IK9hGDJ5QgsAAAAA8rzbClKff/65goOD5enpKU9PT9WqVUtffPFFTtcGAAAAAE7J9KV97777rkaPHq3BgwerQYMGkqSff/5ZAwYM0J9//qmhQ4fmeJEAAAAA4Exua7CJ8ePHq0ePHnbtM2fO1Lhx4/LkPVQMNpELuOQTQG7g+AhnkR/6okR/zC/yQ390or6Y3Wxg+tK+06dPq379+pna69evr9OnT5tdHQAAAADkOaaDVKVKlTR37txM7V9//bUqV66cI0UBAAAAgDMzfY/U+PHj9cQTT2jt2rW2e6TWr1+vFStWZBmwAAAAACC/MX1GKjIyUps2bVLx4sX1zTff6JtvvlHx4sX1yy+/6LHHHsuNGgEAAADAqZgebCI/YrCJXEC3ApAbOD7CWeSHvijRH/OL/NAfnagv5uhgE8nJyXb/vtnLjOjoaD300EMqUqSI/Pz81KFDB+3fv99unvDwcFksFrvXgAED7OY5fvy42rZtq0KFCsnPz08vvviiUlNTTdUCAAAAANmVrXukihYtqtOnT8vPz08+Pj6yZJF6DcOQxWJRWlpatje+Zs0aDRo0SA899JBSU1P18ssvq2XLltqzZ48KFy5sm69fv36aMGGC7X2hQoVs/05LS1Pbtm0VEBCgDRs26PTp0+rRo4cKFCigSZMmZbsWAAAAAMiubAWplStXytfXV5K0atWqHNv4smXL7N7HxsbKz89PW7duVePGjW3thQoVUkBAQJbr+PHHH7Vnzx799NNP8vf3V0hIiCZOnKgRI0Zo3Lhxcnd3z7RMSkqKUlJSbO/NnkkDAAAAcG/LVpAKCwuz/TsoKEiBgYGZzkoZhqETJ07cUTFJSUmSZAttGWbNmqUvv/xSAQEBat++vUaPHm07KxUXF6fg4GD5+/vb5o+IiNDAgQO1e/duPfDAA5m2Ex0drfHjx99RrQAAAADuXaaHPw8KCrJd5ne9xMREBQUFmbq073rp6ekaMmSIGjRooJo1a9ran3zySZUrV06lSpXSzp07NWLECO3fv18LFy6UJMXHx9uFKEm29/Hx8Vlua9SoURo2bJjtfXJysgIDA2+rbgAAAAD3HtNBKuNeqH+7ePGiChYseNuFDBo0SL/99pt+/vlnu/ann37a9u/g4GCVLFlSzZo106FDh1SxYsXb2paHh4c8PDxuu1YAAAAA97ZsB6mMMzgWi8Xu0jrp2oAPmzZtUkhIyG0VMXjwYC1ZskRr165VmTJlbjpv3bp1JUkHDx5UxYoVFRAQoF9++cVunoSEBEm64X1VAAAAAHAnsh2ktm/fLunaGaldu3bZDeLg7u6u+++/X8OHDze1ccMw9Oyzz2rRokVavXq1goKCbrnMjh07JEklS5aUJIWGhur111/XmTNnbJcbLl++XFarVdWrVzdVDwAAAABkh+kH8vbq1Uvvvfdejjy49plnntHs2bP17bff6r777rO1e3t7y9PTU4cOHdLs2bPVpk0bFStWTDt37tTQoUNVpkwZrVmzRtK1s2EhISEqVaqU3nrrLcXHx6t79+7q27dvtoc/54G8ucCJHqoGIB/h+AhnkR/6okR/zC/yQ390or6Y3WxgOkjlpKzutZKkmJgY9ezZUydOnNBTTz2l3377TZcuXVJgYKAee+wxvfrqq3Y7dezYMQ0cOFCrV69W4cKFFRUVpTfeeENubtk74UaQygVO9MMAIB/h+AhnkR/6okR/zC/yQ390or6Yq0Fqy5Ytmjt3ro4fP64rV67YTcsYTS8vIUjlAif6YQCQj3B8hLPID31Roj/mF/mhPzpRX8xuNnAxu+I5c+aofv362rt3rxYtWqSrV69q9+7dWrlypby9ve+oaAAAAADIC0wHqUmTJmny5MlavHix3N3d9d5772nfvn16/PHHVbZs2dyoEQAAAACciukgdejQIbVt21bStdH6Ll26JIvFoqFDh2rGjBk5XiAAAAAAOBvTQapo0aK6cOGCJKl06dL67bffJEnnz5/X33//nbPVAQAAAIATyvZzpDI0btxYy5cvV3BwsDp37qznn39eK1eu1PLly9WsWbPcqBEAAAAAnIrpIPXf//5Xly9fliS98sorKlCggDZs2KDIyEi9+uqrOV4gAAAAADgbhz5Hylkw/HkuoFsByA0cH+Es8kNflOiP+UV+6I9O1Bdzbfjzbdu2adeuXbb33377rTp06KCXX3450zOlAAAAACA/Mh2k+vfvr99//12SdPjwYT3xxBMqVKiQ5s2bp5deeinHCwQAAAAAZ2M6SP3+++8KCQmRJM2bN09hYWGaPXu2YmNjtWDBgpyuDwAAAACcjukgZRiG0tPTJUk//fST2rRpI0kKDAzUn3/+mbPVAQAAAIATMh2k6tSpo9dee01ffPGF1qxZY3s475EjR+Tv75/jBQIAAACAszEdpKZMmaJt27Zp8ODBeuWVV1SpUiVJ0vz581W/fv0cLxAAAAAAnE2ODX9++fJlubq6qkCBAjmxuruK4c9zgRMNYQkgH+H4CGeRH/qiRH/ML/JDf3SivpjdbGD6gbw3UrBgwZxaFQAAAAA4tWwFKV9fX/3+++8qXry4ihYtKstNUm9iYmKOFQcAAAAAzihbQWry5MkqUqSIpGv3SAEAAADAvSzH7pHKy7hHKhfQrQDkBo6PcBb5oS9K9Mf8Ij/0Ryfqizl6j1RycnK2N+wUQQQAAAAAclG2gpSPj89N74uSrj2o12KxKC0tLUcKAwAAAABnla0gtWrVqtyuAwAAAADyjGwFqbCwsNyuAwAAAADyjGwFqZ07d6pmzZpycXHRzp07bzpvrVq1cqQwAAAAAHBW2QpSISEhio+Pl5+fn0JCQmSxWJTVYH/cIwUAAADgXpCtIHXkyBGVKFHC9m8AAAAAuJdlK0iVK1fO9u9jx46pfv36cnOzXzQ1NVUbNmywmxcAAAAA8iMXsws0adJEiYmJmdqTkpLUpEmTHCkKAAAAAJyZ6SCV8byofzt37pwKFy6cI0UBAAAAgDPL1qV9ktSxY0dJ1waU6Nmzpzw8PGzT0tLStHPnTtWvXz/nKwQAAAAAJ5PtIOXt7S3p2hmpIkWKyNPT0zbN3d1d9erVU79+/XK+QgAAAABwMtkOUjExMZKk8uXLa/jw4VzGBwAAAOCeZTGyeiDUPSY5OVne3t5KSkqS1Wp1dDlSFveg5Tl0KwC5geMjnEV+6IsS/TG/yA/90Yn6YnazQbYHmyhatKh8fX0zvYKCghQREaHly5ebLjI6OloPPfSQihQpIj8/P3Xo0EH79++3m+fy5csaNGiQihUrJi8vL0VGRiohIcFunuPHj6tt27YqVKiQ/Pz89OKLLyo1NdV0PQAAAACQHdm+tG/KlClZtp8/f15bt25Vu3btNH/+fLVv3z7bG1+zZo0GDRqkhx56SKmpqXr55ZfVsmVL7dmzx3bp4NChQ/W///1P8+bNk7e3twYPHqyOHTtq/fr1kq4NdNG2bVsFBARow4YNOn36tHr06KECBQpo0qRJ2a4FAAAAALIrxy7te/fddzV//nxt2LDhttdx9uxZ+fn5ac2aNWrcuLGSkpJUokQJzZ49W506dZIk7du3T9WqVVNcXJzq1aunpUuXql27djp16pT8/f0lSdOnT9eIESN09uxZubu733K7XNqXC5zo9CyAfITjI5xFfuiLEv0xv8gP/dGJ+mKOX9p3K+3atdO+ffvuaB1JSUmSJF9fX0nS1q1bdfXqVTVv3tw2T9WqVVW2bFnFxcVJkuLi4hQcHGwLUZIUERGh5ORk7d69O8vtpKSkKDk52e4FAAAAANmVY0EqJSUlW2d/biQ9PV1DhgxRgwYNVLNmTUlSfHy83N3d5ePjYzevv7+/4uPjbfNcH6IypmdMy0p0dLS8vb1tr8DAwNuuGwAAAMC9J8eC1KeffqqQkJDbXn7QoEH67bffNGfOnJwq6YZGjRqlpKQk2+vEiRO5vk0AAAAA+Ue2B5sYNmxYlu1JSUnatm2bfv/9d61du/a2ihg8eLCWLFmitWvXqkyZMrb2gIAAXblyRefPn7c7K5WQkKCAgADbPL/88ovd+jJG9cuY5988PDzk4eFxW7UCAAAAQLaD1Pbt27Nst1qtatGihRYuXKigoCBTGzcMQ88++6wWLVqk1atXZ1q+du3aKlCggFasWKHIyEhJ0v79+3X8+HGFhoZKkkJDQ/X666/rzJkz8vPzkyQtX75cVqtV1atXN1UPAAAAAGSHQx/I+8wzz2j27Nn69ttvdd9999navb295enpKUkaOHCgvv/+e8XGxspqterZZ5+VJNvogGlpaQoJCVGpUqX01ltvKT4+Xt27d1ffvn2zPfw5o/blAicaeQVAPsLxEc4iP/RFif6YX+SH/uhEfTG72cChQcpygy89JiZGPXv2lHTtgbwvvPCCvvrqK6WkpCgiIkLTpk2zu2zv2LFjGjhwoFavXq3ChQsrKipKb7zxhtzcsnfCjSCVC5zohwFAPsLxEc4iP/RFif6YX+SH/uhEfTFPBClnQZDKBXQrALmB4yOcRX7oixL9Mb/ID/3RifriXX+OFAAAAADcKwhSAAAAAGBStoNU7969deHChdysBQAAAADyhGwHqZkzZ+qff/7JzVoAAAAAIE/IdpBiTAoAAAAAuCbbD+SVpAsXLqhgwYI3nccpRr0DAAAAgFxkKkhVqVLlhtMMw5DFYlFaWtodFwUAAAAAzsxUkJo/f758fX1zqxYAAAAAyBNMBakGDRrIz88vt2oBAAAAgDyB50gBAAAAgEnZDlLlypWTq6trbtYCAAAAAHlCti/tO3LkSG7WAQAAAAB5RraDVNGiRWWxWDK1e3t7q0qVKho+fLhatGiRo8UBAAAAgDPKdpCaPHlylkHq/Pnz2rp1q9q1a6f58+erffv2OVogAAAAADibbAepnj173nR6SEiIoqOjCVIAAAAA8r0cG7WvXbt22rdvX06tDgAAAACcVo4FqZSUFLm7u+fU6gAAAADAaeVYkPr0008VEhKSU6sDAAAAAKeV7Xukhg0blmV7UlKStm3bpt9//11r167NscIAAAAAwFllO0ht3749y3ar1aoWLVpo4cKFCgoKyrHCAAAAAMBZZTtIrVq16qbTT548qaefflozZsy446IAAAAAwJnl2D1S586d06effppTqwMAAAAAp5VjQQoAAAAA7hUEKQAAAAAwiSAFAAAAACZle7CJjh073nT6+fPn77QWAAAAAMgTsh2kvL29bzm9R48ed1wQAAAAADi7bAepmJiY3KwDAAAAAPIM7pECAAAAAJMIUgAAAABgEkEKAAAAAEwiSAEAAACASQQpAAAAADDJoUFq7dq1at++vUqVKiWLxaJvvvnGbnrPnj1lsVjsXq1atbKbJzExUd26dZPVapWPj4/69Omjixcv3sW9AAAAAHCvcWiQunTpku6//3598MEHN5ynVatWOn36tO311Vdf2U3v1q2bdu/ereXLl2vJkiVau3atnn766dwuHQAAAMA9LNvPkcoNrVu3VuvWrW86j4eHhwICArKctnfvXi1btkybN29WnTp1JElTp05VmzZt9J///EelSpXK8ZoBAAAAwOnvkVq9erX8/Px03333aeDAgTp37pxtWlxcnHx8fGwhSpKaN28uFxcXbdq06YbrTElJUXJyst0LAAAAALLLqYNUq1at9Pnnn2vFihV68803tWbNGrVu3VppaWmSpPj4ePn5+dkt4+bmJl9fX8XHx99wvdHR0fL29ra9AgMDc3U/AAAAAOQvDr2071a6dOli+3dwcLBq1aqlihUravXq1WrWrNltr3fUqFEaNmyY7X1ycjJhCgAAAEC2OfUZqX+rUKGCihcvroMHD0qSAgICdObMGbt5UlNTlZiYeMP7qqRr911ZrVa7FwAAAABkV54KUidPntS5c+dUsmRJSVJoaKjOnz+vrVu32uZZuXKl0tPTVbduXUeVCQAAACCfc+ilfRcvXrSdXZKkI0eOaMeOHfL19ZWvr6/Gjx+vyMhIBQQE6NChQ3rppZdUqVIlRURESJKqVaumVq1aqV+/fpo+fbquXr2qwYMHq0uXLozYBwAAACDXWAzDMBy18dWrV6tJkyaZ2qOiovThhx+qQ4cO2r59u86fP69SpUqpZcuWmjhxovz9/W3zJiYmavDgwVq8eLFcXFwUGRmp999/X15eXtmuIzk5Wd7e3kpKSnKOy/wsFkdXcOcc160A5GccH+Es8kNflOiP+UV+6I9O1Bezmw0cGqScBUEqF9CtAOQGjo9wFvmhL0r0x/wiP/RHJ+qL2c0GeeoeKQAAAABwBgQpAAAAADCJIAUAAAAAJhGkAAAAAMAkghQAAAAAmESQAgAAAACTCFIAAAAAYBJBCgAAAABMIkgBAAAAgEkEKQAAAAAwiSAFAAAAACYRpAAAAADAJIIUAAAAAJhEkAIAAAAAkwhSAAAAAGASQQoAAAAATCJIAQAAAIBJBCkAAAAAMIkgBQAAAAAmEaQAAAAAwCSCFAAAAACYRJACAAAAAJMIUgAAAABgEkEKAAAAAEwiSAEAAACASQQpAAAAADCJIAUAAAAAJhGkAAAAAMAkghQAAAAAmESQAgAAAACTCFIAAAAAYBJBCgAAAABMIkgBAAAAgEkODVJr165V+/btVapUKVksFn3zzTd20w3D0JgxY1SyZEl5enqqefPmOnDggN08iYmJ6tatm6xWq3x8fNSnTx9dvHjxLu4FAAAAgHuNQ4PUpUuXdP/99+uDDz7Icvpbb72l999/X9OnT9emTZtUuHBhRURE6PLly7Z5unXrpt27d2v58uVasmSJ1q5dq6effvpu7QIAAACAe5DFMAzD0UVIksVi0aJFi9ShQwdJ185GlSpVSi+88IKGDx8uSUpKSpK/v79iY2PVpUsX7d27V9WrV9fmzZtVp04dSdKyZcvUpk0bnTx5UqVKlcrWtpOTk+Xt7a2kpCRZrdZc2T9TLBZHV3DnnKNbAchvOD7CWeSHvijRH/OL/NAfnagvZjcbOO09UkeOHFF8fLyaN29ua/P29lbdunUVFxcnSYqLi5OPj48tRElS8+bN5eLiok2bNt1w3SkpKUpOTrZ7AQAAAEB2OW2Qio+PlyT5+/vbtfv7+9umxcfHy8/Pz266m5ubfH19bfNkJTo6Wt7e3rZXYGBgDlcPAAAAID9z2iCVm0aNGqWkpCTb68SJE44uCQAAAEAe4rRBKiAgQJKUkJBg156QkGCbFhAQoDNnzthNT01NVWJiom2erHh4eMhqtdq9AAAAACC7nDZIBQUFKSAgQCtWrLC1JScna9OmTQoNDZUkhYaG6vz589q6dattnpUrVyo9PV1169a96zUDAAAAuDe4OXLjFy9e1MGDB23vjxw5oh07dsjX11dly5bVkCFD9Nprr6ly5coKCgrS6NGjVapUKdvIftWqVVOrVq3Ur18/TZ8+XVevXtXgwYPVpUuXbI/YBwAAAABmOTRIbdmyRU2aNLG9HzZsmCQpKipKsbGxeumll3Tp0iU9/fTTOn/+vBo2bKhly5apYMGCtmVmzZqlwYMHq1mzZnJxcVFkZKTef//9u74vAAAAAO4dTvMcKUfiOVK5gG4FIDdwfISzyA99UaI/5hf5oT86UV/M88+RAgAAAABnRZACAAAAAJMIUgAAAABgEkEKAAAAAEwiSAEAAACASQQpAAAAADCJIAUAAAAAJhGkAAAAAMAkghQAAAAAmESQAgAAAACTCFIAAAAAYBJBCgAAAABMIkgBAAAAgEkEKQAAAAAwiSAFAAAAACYRpAAAAADAJIIUAAAAAJhEkAIAAAAAkwhSAAAAAGASQQoAAAAATCJIAQAAAIBJBCkAAAAAMIkgBQAAAAAmEaQAAAAAwCSCFAAAAACYRJACAAAAAJMIUgAAAABgEkEKAAAAAEwiSAEAAACASQQpAAAAADCJIAUAAAAAJhGkAAAAAMAkghQAAAAAmOTUQWrcuHGyWCx2r6pVq9qmX758WYMGDVKxYsXk5eWlyMhIJSQkOLBiAAAAAPcCpw5SklSjRg2dPn3a9vr5559t04YOHarFixdr3rx5WrNmjU6dOqWOHTs6sFoAAAAA9wI3RxdwK25ubgoICMjUnpSUpE8//VSzZ89W06ZNJUkxMTGqVq2aNm7cqHr16t3tUgEAAADcI5z+jNSBAwdUqlQpVahQQd26ddPx48clSVu3btXVq1fVvHlz27xVq1ZV2bJlFRcXd9N1pqSkKDk52e4FAAAAANnl1EGqbt26io2N1bJly/Thhx/qyJEjatSokS5cuKD4+Hi5u7vLx8fHbhl/f3/Fx8ffdL3R0dHy9va2vQIDA3NxLwAAAADkN059aV/r1q1t/65Vq5bq1q2rcuXKae7cufL09Lzt9Y4aNUrDhg2zvU9OTiZMAQAAAMg2pz4j9W8+Pj6qUqWKDh48qICAAF25ckXnz5+3mychISHLe6qu5+HhIavVavcCAAAAgOzKU0Hq4sWLOnTokEqWLKnatWurQIECWrFihW36/v37dfz4cYWGhjqwSgAAAAD5nVNf2jd8+HC1b99e5cqV06lTpzR27Fi5urqqa9eu8vb2Vp8+fTRs2DD5+vrKarXq2WefVWhoKCP2AQAAAMhVTh2kTp48qa5du+rcuXMqUaKEGjZsqI0bN6pEiRKSpMmTJ8vFxUWRkZFKSUlRRESEpk2b5uCqAQAAAOR3FsMwDEcX4WjJycny9vZWUlKSc9wvZbE4uoI7R7cCkBs4PsJZ5Ie+KNEf84v80B+dqC9mNxvkqXukAAAAAMAZEKQAAAAAwCSCFAAAAACYRJACAAAAAJMIUgAAAABgEkEKAAAAAEwiSAEAAACASQQpAAAAADCJIAUAAAAAJhGkAAAAAMAkghQAAAAAmESQAgAAAACTCFIAAAAAYBJBCgAAAABMIkgBAAAAgEkEKQAAAAAwiSAFAAAAACYRpAAAAADAJIIUAAAAAJhEkAIAAAAAkwhSAAAAAGASQQoAAAAATCJIAQAAAIBJBCkAAAAAMIkgBQAAAAAmEaQAAAAAwCSCFAAAAACYRJACAAAAAJMIUgAAAABgEkEKAAAAAEwiSAEAAACASQQpAAAAADCJIAUAAAAAJuWbIPXBBx+ofPnyKliwoOrWratffvnF0SUBAAAAyKfyRZD6+uuvNWzYMI0dO1bbtm3T/fffr4iICJ05c8bRpQF5n8WS918AAAA5LF8EqXfffVf9+vVTr169VL16dU2fPl2FChXSZ5995ujSAAAAAORDbo4u4E5duXJFW7du1ahRo2xtLi4uat68ueLi4rJcJiUlRSkpKbb3SUlJkqTk5OTcLfZewmcJZ0J/hDOhP8KZ0B/hLJyoL2ZkAsMwbjpfng9Sf/75p9LS0uTv72/X7u/vr3379mW5THR0tMaPH5+pPTAwMFdqvCd5ezu6AuD/0B/hTOiPcCb0RzgLJ+yLFy5ckPdN6srzQep2jBo1SsOGDbO9T09PV2JioooVKyZLPr+fIjk5WYGBgTpx4oSsVqujy8E9jv4IZ0J/hDOhP8KZ3Gv90TAMXbhwQaVKlbrpfHk+SBUvXlyurq5KSEiwa09ISFBAQECWy3h4eMjDw8OuzcfHJ7dKdEpWq/We+EFA3kB/hDOhP8KZ0B/hTO6l/nizM1EZ8vxgE+7u7qpdu7ZWrFhha0tPT9eKFSsUGhrqwMoAAAAA5Fd5/oyUJA0bNkxRUVGqU6eOHn74YU2ZMkWXLl1Sr169HF0aAAAAgHwoXwSpJ554QmfPntWYMWMUHx+vkJAQLVu2LNMAFLh2WePYsWMzXdoIOAL9Ec6E/ghnQn+EM6E/Zs1i3GpcPwAAAACAnTx/jxQAAAAA3G0EKQAAAAAwiSAFAAAAACYRpAAAAADAJIJUHtKzZ09ZLBYNGDAg07RBgwbJYrGoZ8+eat++vVq1apXlOtatWyeLxaKdO3dq9erVslgsOn/+fKb5ypcvrylTptjeJyYmqlu3brJarfLx8VGfPn108eLFnNo1OLmMvmexWFSgQAH5+/urRYsW+uyzz5Seni5J6tKlS6Z+t2zZMlksFo0bN86ufdy4cSpbtqxd24IFCxQeHi5vb295eXmpVq1amjBhghITE7NV4+rVq/Xggw/Kw8NDlSpVUmxs7G3vL/IWRx4bX3/9ddWvX1+FChW65x7sjqw5qj8ePXpUffr0UVBQkDw9PVWxYkWNHTtWV65cycndQx7jyOPjI488orJly6pgwYIqWbKkunfvrlOnTuXUrjkFglQeExgYqDlz5uiff/6xtV2+fFmzZ8+2/WLap08fLV++XCdPnsy0fExMjOrUqaNatWqZ2m63bt20e/duLV++XEuWLNHatWv19NNP39nOIE9p1aqVTp8+raNHj2rp0qVq0qSJnn/+ebVr106pqalq0qSJ1q9fr9TUVNsyq1atUmBgoFavXm23rlWrVqlJkya296+88oqeeOIJPfTQQ1q6dKl+++03vfPOO/r111/1xRdf3LK2I0eOqG3btmrSpIl27NihIUOGqG/fvvrhhx9ybP/h3Bx1bLxy5Yo6d+6sgQMH3tkOIF9xRH/ct2+f0tPT9dFHH2n37t2aPHmypk+frpdffvnOdwh5mqOOj02aNNHcuXO1f/9+LViwQIcOHVKnTp3ubGecDEEqj3nwwQcVGBiohQsX2toWLlyosmXL6oEHHpAktWvXTiVKlMj0F/mLFy9q3rx56tOnj6lt7t27V8uWLdMnn3yiunXrqmHDhpo6darmzJmT7/6ygBvz8PBQQECASpcurQcffFAvv/yyvv32Wy1dulSxsbFq0qSJLl68qC1bttiWWb16tUaOHKlNmzbp8uXLkq4dvDdt2mQLUr/88osmTZqkd955R2+//bbq16+v8uXLq0WLFlqwYIGioqJuWdv06dMVFBSkd955R9WqVdPgwYPVqVMnTZ48OXc+DDgdRxwbJWn8+PEaOnSogoOD76h+5C+O6I+tWrVSTEyMWrZsqQoVKuiRRx7R8OHD7WrAvclRx8ehQ4eqXr16KleunOrXr6+RI0dq48aNunr16h3tjzMhSOVBvXv3VkxMjO39Z599pl69etneu7m5qUePHoqNjdX1jwmbN2+e0tLS1LVrV1Pbi4uLk4+Pj+rUqWNra968uVxcXLRp06Y72BPkdU2bNtX999+vhQsXqkqVKipVqpRWrVolSbpw4YK2bdumzp07q3z58oqLi5MkbdiwQSkpKbYgNWvWLHl5eemZZ57JchvZuVwqLi5OzZs3t2uLiIiwbRP3hrt9bARuxhn6Y1JSknx9fe94Pcj7HN0fExMTNWvWLNWvX18FChS4o3U5E4JUHvTUU0/p559/1rFjx3Ts2DGtX79eTz31lN08vXv31qFDh7RmzRpbW0xMjCIjI+Xt7W1qe/Hx8fLz87Nrc3Nzk6+vr+Lj429/R5AvVK1aVUePHpV07TR+xmV869atU5UqVVSiRAk1btzY1r569WoFBQWpXLlykqQDBw6oQoUKd3RgjY+Pl7+/v12bv7+/kpOT7S5lQP52t4+NwM04uj8ePHhQU6dOVf/+/e9oPcgfHNUfR4wYocKFC6tYsWI6fvy4vv322zvaD2dDkMqDSpQoobZt2yo2NlYxMTFq27atihcvbjdP1apVVb9+fX322WeSrh1Q161bd1unZoGbMQxDFotFkhQeHq7169fr6tWrWr16tcLDwyVJYWFhdkHq+vujrv/LF3AnODbCmTiyP/7xxx9q1aqVOnfurH79+t3RupA/OKo/vvjii9q+fbt+/PFHubq6qkePHvnq//sEqTyqd+/eio2N1cyZM9W7d+8s5+nTp48WLFigCxcuKCYmRhUrVlRYWJhtutVqlXTt1P+/nT9/3vbXh4CAAJ05c8ZuempqqhITExUQEJBTu4Q8au/evQoKCpJ07YzUpUuXtHnzZq1atcrW38LCwrRp0yYlJiZq06ZNatq0qW35KlWq6PDhw3d0zXRAQIASEhLs2hISEmS1WuXp6Xnb60XeczePjcCtOKI/njp1Sk2aNFH9+vU1Y8aMHNwb5HWO6I/FixdXlSpV1KJFC82ZM0fff/+9Nm7cmIN75VgEqTyqVatWunLliq5evaqIiIgs53n88cfl4uKi2bNn6/PPP1fv3r1tZw4kqXLlynJxcdHWrVvtljt8+LCSkpJUpUoVSVJoaKjOnz9vN9/KlSuVnp6uunXr5sLeIa9YuXKldu3apcjISElSxYoVFRgYqO+++047duywHXxLly6t0qVL65133tGVK1fszkg9+eSTunjxoqZNm5blNrIaYvXfQkNDtWLFCru25cuXKzQ09Db3DHnV3Tw2Ardyt/vjH3/8ofDwcNWuXVsxMTFyceHXPPwfRx8fMx6XkpKSkgN74xzcHF0Abo+rq6v27t1r+3dWvLy89MQTT2jUqFFKTk5Wz5497aYXKVJEffv21QsvvCA3NzcFBwfrxIkTGjFihOrVq6f69etLkqpVq6ZWrVqpX79+mj59uq5evarBgwerS5cuKlWqVK7uJ5xHSkqK4uPjlZaWpoSEBC1btkzR0dFq166devToYZuvSZMmmjZtmipVqmR331JYWJimTp1qG5QiQ926dfXSSy/phRde0B9//KHHHntMpUqV0sGDBzV9+nQ1bNhQzz///E1rGzBggP773//qpZdeUu/evbVy5UrNnTtX//vf/3L+g4BTu5vHRkk6fvy4EhMTdfz4caWlpWnHjh2SpEqVKsnLyytX9hF5x93sjxkhqly5cvrPf/6js2fP2tbB1SOQ7m5/3LRpkzZv3qyGDRuqaNGiOnTokEaPHq2KFSvmrz9yGsgzoqKijEcfffSG0x999FEjKirKrm3Dhg2GJKNNmzZZLvPPP/8YY8eONapWrWp4enoaQUFBxtNPP22cPXvWbr5z584ZXbt2Nby8vAyr1Wr06tXLuHDhwp3uEvKIqKgoQ5IhyXBzczNKlChhNG/e3Pjss8+MtLQ0u3ljYmIMScaAAQPs2mNjYw1JRv/+/bPcxtdff200btzYKFKkiFG4cGGjVq1axoQJE4y//vorWzWuWrXKCAkJMdzd3Y0KFSoYMTExt7OryIMceWy8/mfj+teqVavucK+QVzmqP2Yce7N64d7lqP64c+dOo0mTJoavr6/h4eFhlC9f3hgwYIBx8uTJnNgtp2ExjHx0xxcAAAAA3AVcPAsAAAAAJhGkADi9GjVqyMvLK8vXrFmzHF0eAAC4B3FpHwCnd+zYsRsOj+7v768iRYrc5YoAAMC9jiAFAAAAACZxaR8AAAAAmESQAgAAAACTCFIAAAAAYBJBCgAAAABMIkgBAO5p4eHhGjJkiKPLAADkMQQpAMBt6dmzpywWi9544w279m+++UYWi8XUusqXL68pU6bkYHW55+jRo7JYLNqxY4ejSwEAOBBBCgBw2woWLKg333xTf/31l6NLMe3KlSuOLiFH3ehZawCA3EGQAgDctubNmysgIEDR0dE3ne/nn39Wo0aN5OnpqcDAQD333HO6dOmSpGuX1h07dkxDhw6VxWKRxWKRYRgqUaKE5s+fb1tHSEiISpYsabdODw8P/f3335Kk48eP69FHH5WXl5esVqsef/xxJSQk2OYfN26cQkJC9MknnygoKEgFCxbMstb//e9/8vb21qxZs27rMzl06JAeffRR+fv7y8vLSw899JB++ukn2/QJEyaoZs2amZYLCQnR6NGjbe8/+eQTVatWTQULFlTVqlU1bdo027SMs2Jff/21wsLCVLBgQc2aNUvHjh1T+/btVbRoURUuXFg1atTQ999/f1v7AQC4OYIUAOC2ubq6atKkSZo6dapOnjyZ5TyHDh1Sq1atFBkZqZ07d+rrr7/Wzz//rMGDB0uSFi5cqDJlymjChAk6ffq0Tp8+LYvFosaNG2v16tWSpL/++kt79+7VP//8o3379kmS1qxZo4ceekiFChVSenq6Hn30USUmJmrNmjVavny5Dh8+rCeeeMKuloMHD2rBggVauHBhlpfmzZ49W127dtWsWbPUrVu32/pMLl68qDZt2mjFihXavn27WrVqpfbt2+v48eOSpN69e2vv3r3avHmzbZnt27dr586d6tWrlyRp1qxZGjNmjF5//XXt3btXkyZN0ujRozVz5ky7bY0cOVLPP/+89u7dq4iICA0aNEgpKSlau3atdu3apTfffFNeXl63tR8AgJtzc3QBAIC87bHHHlNISIjGjh2rTz/9NNP06OhodevWzTagQ+XKlfX+++8rLCxMH374oXx9feXq6qoiRYooICDAtlx4eLg++ugjSdLatWv1wAMPKCAgQKtXr1bVqlW1evVqhYWFSZJWrFihXbt26ciRIwoMDJQkff7556pRo4Y2b96shx56SNK1y/k+//xzlShRIlOdH3zwgV555RUtXrzYtt7bcf/99+v++++3vZ84caIWLVqk7777ToMHD1aZMmUUERGhmJgYW10xMTEKCwtThQoVJEljx47VO++8o44dO0qSgoKCtGfPHn300UeKioqyrXvIkCG2eaRrZ+UiIyMVHBwsSbb1AQByHmekAAB37M0339TMmTO1d+/eTNN+/fVXxcbGysvLy/aKiIhQenq6jhw5csN1hoWFac+ePTp79qzWrFmj8PBwhYeHa/Xq1bp69ao2bNig8PBwSdLevXsVGBhoC1GSVL16dfn4+NjVVK5cuSxD1Pz58zV06FAtX778jkKUdO2M1PDhw1WtWjX5+PjIy8tLe/futZ2RkqR+/frpq6++0uXLl3XlyhXNnj1bvXv3liRdunRJhw4dUp8+few+s9dee02HDh2y21adOnXs3j/33HN67bXX1KBBA40dO1Y7d+68o30BANwYQQoAcMcaN26siIgIjRo1KtO0ixcvqn///tqxY4ft9euvv+rAgQOqWLHiDdcZHBwsX19frVmzxi5IrVmzRps3b9bVq1dVv359U3UWLlw4y/YHHnhAJUqU0GeffSbDMEyt89+GDx+uRYsWadKkSVq3bp127Nih4OBgu8Et2rdvLw8PDy1atEiLFy/W1atX1alTJ0nXPi9J+vjjj+0+s99++00bN2686f707dtXhw8fVvfu3bVr1y7VqVNHU6dOvaP9AQBkjUv7AAA54o033lBISIjuu+8+u/YHH3xQe/bsUaVKlW64rLu7u9LS0uzaLBaLGjVqpG+//Va7d+9Ww4YNVahQIaWkpOijjz5SnTp1bEGiWrVqOnHihE6cOGE7K7Vnzx6dP39e1atXv2XtFStW1DvvvKPw8HC5urrqv//9r9ndt1m/fr169uypxx57TNK1YHT06FG7edzc3BQVFaWYmBi5u7urS5cu8vT0lCT5+/urVKlSOnz48G3dpxUYGKgBAwZowIABGjVqlD7++GM9++yzt70/AICsEaQAADkiODhY3bp10/vvv2/XPmLECNWrV0+DBw9W3759VbhwYe3Zs0fLly+3BZby5ctr7dq16tKlizw8PFS8eHFJ1+6TeuGFF1SnTh3boAmNGzfWrFmz9OKLL9q20bx5c9v2p0yZotTUVD3zzDMKCwvLdPnbjVSpUkWrVq1SeHi43Nzcbvlcq/3792dqq1GjhipXrqyFCxeqffv2slgsGj16tNLT0zPN27dvX1WrVk3StfB1vfHjx+u5556Tt7e3WrVqpZSUFG3ZskV//fWXhg0bdsOahgwZotatW6tKlSr666+/tGrVKts2AAA5i0v7AAA5ZsKECZlCQ61atbRmzRr9/vvvatSokR544AGNGTNGpUqVslvu6NGjqlixot09TGFhYUpLS7PdCyVdC1f/brNYLPr2229VtGhRNW7cWM2bN1eFChX09ddfm6r/vvvu08qVK/XVV1/phRdeuOm8Xbp00QMPPGD3SkhI0LvvvquiRYuqfv36at++vSIiIvTggw9mWr5y5cqqX7++qlatqrp169pN69u3rz755BPFxMQoODhYYWFhio2NVVBQ0E1rSktL06BBg1StWjW1atVKVapUsRs2HQCQcyzGnV4MDgAATDMMQ5UrV9Yzzzxz07NMAADnxKV9AADcZWfPntWcOXMUHx9ve3YUACBvIUgBAHCX+fn5qXjx4poxY4aKFi3q6HIAALeBIAUAwF3GVfUAkPcx2AQAAAAAmESQAgAAAACTCFIAAAAAYBJBCgAAAABMIkgBAAAAgEkEKQAAAAAwiSAFAAAAACYRpAAAAADApP8H3ngi6RaSud8AAAAASUVORK5CYII=", + "text/plain": [ + "
    " + ] + }, + "metadata": {}, + "output_type": "display_data" + } + ], "source": [ - "# Additional Information : Constraints table\n", + "# Extracting LUTs from res_dict\n", + "LUTs_dwc = [res_dict_dwc[key][\"LUT\"] for key in res_dict_dwc.keys()] \n", "\n", - "The below table exposes the constraints associated with each layer. A developer working with these layers has to be mindful of not violating them when setting the PE & SIMD values manually." + "#Plotting the bar graph of each network layer with their corresponding LUT resource utilization\n", + "fig = plt.figure(figsize = (10, 5))\n", + "plt.bar(layers, LUTs_dwc, color ='red', width = 0.3)\n", + "plt.xlabel(\"Network Layers\")\n", + "plt.ylabel(\"LUT Utilisation\")\n", + "plt.title(\"Estimated LUT values used for each network layer\")\n", + "plt.show()" ] }, { - "cell_type": "code", - "execution_count": null, + "cell_type": "markdown", "metadata": {}, - "outputs": [], "source": [ - "+------------------------------------+------------+----------------------------------------------------------------+\n", - "| Layers | Attributes | Assertions |\n", - "+====================================+============+================================================================+\n", - "| addstreams_batch | PE | inp_channels % PE == 0 |\n", - "| channelwise_op_batch | PE | channels % PE == 0 |\n", - "| checksum | ~ | ~ |\n", - "| concat | ~ | ~ |\n", - "| convolutioninputgenerator | SIMD | inp_feature_map_channels % SIMD == 0 |\n", - "| convolutioninputgenerator1d | SIMD | inp_feature_map_channels % SIMD == 0 |\n", - "| convolutioninputgenerator_rtl | SIMD | inp_feature_map_channels % SIMD == 0 |\n", - "| downsampler | SIMD | inp_feature_map_channels % SIMD == 0 |\n", - "| duplicatestreams_batch | PE | channels % PE == 0 |\n", - "| eltwise | PE | inp_channels % PE == 0 |\n", - "| fmpadding_batch | SIMD | inp_feature_map_channels % SIMD == 0 |\n", - "| fmpadding_rtl | SIMD | inp_feature_map_channels % SIMD == 0 |\n", - "| globalaccpool_batch | PE | channels % PE == 0 |\n", - "| hlscustomop | ~ | ~ |\n", - "| iodma | ~ | ~ |\n", - "| labelselect_batch | PE | num_labels % PE == 0 |\n", - "| lookup | ~ | ~ |\n", - "| matrixvectoractivation | PE & SIMD | matrix_height % PE == 0 & matrix_width % SIMD == 0 |\n", - "| pool_batch | PE | input_feature_map_channels % PE == 0 |\n", - "| streamingdataflowpartition | ~ | ~ |\n", - "| streamingdatawidthconverter_batch | ~ | ~ |\n", - "| streamingfifo | ~ | ~ |\n", - "| streamingmaxpool_batch | ~ | ~ |\n", - "| templates | ~ | ~ |\n", - "| thresholding_batch | PE | matrix_height % PE == 0 |\n", - "| tlastmarker | ~ | ~ |\n", - "| upsampler | ~ | ~ |\n", - "| vectorvectoractivation | PE & SIMD | kernel_height * kernel_width % SIMD == 0 & channels % PE == 0 |\n", - "+------------------------------------+------------+----------------------------------------------------------------+" + "In the case of our example network, the `StreamingDataWidthConverter_Batch` layer does not consume a large number of LUT resources as shown in the graph. This might be different for larger models and if there are a higher number of DWCs inserted. Please be aware of this when setting the folding factors for your network." ] } ], From 9bfc9b4fb1aca8ed3ea600fac4f354673011e3cc Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 27 Jun 2023 11:22:06 +0100 Subject: [PATCH 178/665] [docs] Update table for folding factor constraints --- docs/finn/internals.rst | 82 +++++++++++++++++++++++++---------------- 1 file changed, 51 insertions(+), 31 deletions(-) diff --git a/docs/finn/internals.rst b/docs/finn/internals.rst index 9c1ff626b2..652c94ac24 100644 --- a/docs/finn/internals.rst +++ b/docs/finn/internals.rst @@ -211,37 +211,57 @@ When the nodes in the network are converted to HLS layers, the *mem_mode* can be Constraints to folding factors per layer ========================================= -+------------------------------------+------------+----------------------------------------------------------------+ -| Layers | Attributes | Assertions | -+====================================+============+================================================================+ -| addstreams_batch | PE | inp_channels % PE == 0 | -| channelwise_op_batch | PE | channels % PE == 0 | -| checksum | - | - | -| concat | - | - | -| convolutioninputgenerator | SIMD | inp_channels % SIMD == 0 | -| convolutioninputgenerator1d | SIMD | inp_channels % SIMD == 0 | -| convolutioninputgenerator_rtl | SIMD | inp_channels % SIMD == 0 | -| downsampler | SIMD | inp_channels % SIMD == 0 | -| duplicatestreams_batch | PE | channels % PE == 0 | -| eltwise | PE | inp_channels % PE == 0 | -| fmpadding_batch | SIMD | inp_channels % SIMD == 0 | -| fmpadding_rtl | SIMD | inp_channels % SIMD == 0 | -| globalaccpool_batch | PE | channels % PE == 0 | -| iodma | - | - | -| labelselect_batch | PE | num_labels % PE == 0 | -| lookup | - | - | -| matrixvectoractivation | PE & SIMD | matrix_height % PE == 0 & matrix_width % SIMD == 0 | -| pool_batch | PE | inp_channels % PE == 0 | -| streamingdataflowpartition | - | - | -| streamingdatawidthconverter_batch | - | - | -| streamingfifo | - | - | -| streamingmaxpool_batch | - | - | -| templates | - | - | -| thresholding_batch | PE | matrix_height % PE == 0 | -| tlastmarker | - | - | -| upsampler | - | - | -| vectorvectoractivation | PE & SIMD | kernel_height * kernel_width % SIMD == 0 & channels % PE == 0 | -+------------------------------------+------------+----------------------------------------------------------------+ + +.. list-table:: Folding factor constraints + + * - **Layers** + - **Parameters** + - **Constraints** + * - Addstreams_Batch + - PE + - inp_channels % PE == 0 + * - ChannelwiseOp_Batch + - PE + - channels % PE == 0 + * - ConvolutionInputGenerator + - SIMD + - inp_channels % SIMD == 0 + * - ConvolutionInputGenerator1d + - SIMD + - inp_channels % SIMD == 0 + * - Downsampler + - SIMD + - inp_channels % SIMD == 0 + * - DuplicateStreams_Batch + - PE + - channels % PE == 0 + * - Eltwise + - PE + - inp_channels % PE == 0 + * - FMPadding_batch + - SIMD + - inp_channels % SIMD == 0 + * - FMPadding_rtl + - SIMD + - inp_channels % SIMD == 0 + * - Globalaccpool_Batch + - PE + - channels % PE == 0 + * - Labelselect_Batch + - PE + - num_labels % PE == 0 + * - MatrixVectorActivation + - PE & SIMD + - MH % PE == 0 & MW % SIMD == 0 + * - Pool_Batch + - PE + - inp_channels % PE == 0 + * - Thresholding_Batch + - PE + - MH % PE == 0 + * - VectorVectorActivation + - PE & SIMD + - k_h * k_w % SIMD == 0 & channels % PE == 0 RTL ConvolutionInputGenerator From 75eda8537b52bf452f9fc800754f5ac32ac4973e Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 27 Jun 2023 11:50:50 +0100 Subject: [PATCH 179/665] [notebooks] Clean-up folding nb and add onnx file --- notebooks/advanced/3_folding.ipynb | 571 ++++--------------------- notebooks/advanced/cybsec_PE_SIMD.onnx | Bin 0 -> 192234 bytes 2 files changed, 74 insertions(+), 497 deletions(-) create mode 100644 notebooks/advanced/cybsec_PE_SIMD.onnx diff --git a/notebooks/advanced/3_folding.ipynb b/notebooks/advanced/3_folding.ipynb index a411d3bc88..1eb99206e2 100644 --- a/notebooks/advanced/3_folding.ipynb +++ b/notebooks/advanced/3_folding.ipynb @@ -6,18 +6,20 @@ "source": [ "# FINN - Folding\n", "--------------------------------------\n", - "**Note: To run this notebook, you first need to run the build flow in the 3rd cybersecurity notebook as we utilize one of the intermediate models generated in that process in this notebook.** \n", + "**Note: We will utilize one of the intermediate models generated in the process of the cybersecurity end2end example**\n", "\n", - "This notebook describes the use of FINN parallelization parameters (PE & SIMD) to efficiently streamline models so as to extract the maximum performance out of them. \n", + "There is a local copy of `step_convert_to_hls.onnx` in this directory, which was renamed to `cybsec_PE_SIMD.onnx` to be able to go through this tutorial without requisites. But you can also generate it yourself with the [third cybersecurity Jupyter notebook](../end2end_example/cybersecurity/3-build-accelerator-with-finn.ipynb). After the execution of the estimates only build flow, it can be found in `../end2end_example/cybersecurity/output_estimates_only/intermediate_models/step_convert_to_hls.onnx`. \n", "\n", - "Please be aware that the folding factors can not be selected arbitrarily, each layer has constraints on which values the parallelization parameters can be set to, for more information see here: https://finn-dev.readthedocs.io/en/latest/internals.html#folding-factors\n", + "This notebook describes the use of FINN parallelization parameters (PE & SIMD), also called folding factors, to efficiently optimize models so as to extract the maximum performance out of them. \n", + "\n", + "Please be aware that the folding factors can not be selected arbitrarily, each layer has constraints on which values the parallelization parameters can be set to, for more information see here: https://finn-dev.readthedocs.io/en/latest/internals.html#constraints-to-folding-factors-per-layer\n", "\n", "We'll use the utility function `showInNetron()` to visualize and interact with our network in the Jupyter Notebook and `showSrc()` to show source code of FINN library calls." ] }, { "cell_type": "code", - "execution_count": 1, + "execution_count": null, "metadata": {}, "outputs": [], "source": [ @@ -39,7 +41,7 @@ "source": [ "This notebook shows the manual version of this step and explains how these attributes can improve performance and what are their effects on resource utilization for developers who need to maximize the performance of their network. \n", "\n", - "For that we will use the `step_convert_to_hls.onnx` file as starting point. This intermediate model from the cybersecurity example is the model representation after the high-level ONNX layers are converted to HLS layers. Each node in the graph now corresponds to an HLS C++ function call and the parallelization parameters can be set using the node attributes.\n", + "For that we will use the `cybsec_PE_SIMD.onnx` file as starting point. This intermediate model from the cybersecurity example is the model representation after the high-level ONNX layers are converted to HLS layers. Each node in the graph now corresponds to an HLS C++ function call and the parallelization parameters can be set using the node attributes.\n", "\n", "We will take this model to show how to set the folding factors manually and analyze the estimated execution clock cycles and the resource utilization of each layer in the network." ] @@ -56,7 +58,7 @@ "\n", "In practice, the layers are instantiated by function calls to optimized Vitis HLS building blocks from the [finn-hlslib](https://github.com/Xilinx/finn-hlslib) library.\n", "\n", - "Since each layer will be instantiated, we can flexibly set the parallelization of each layer and thus control resources and throughput of our network, as visualized in the imaged below:\n", + "Since each layer will be instantiated, we can flexibly set the parallelization of each layer and thus control resources and throughput of our network, as visualized in the image below:\n", "\n", "![](finn-folding.png)" ] @@ -70,52 +72,21 @@ "As discussed above, the network needs to go through a few preparation steps before it can be fed into our estimation functions.\n", "\n", "The `.onnx` file loaded here is taken from the cybersecurity end2end example notebook. \n", - "We pick the onnx file `step_convert_to_hls.onnx` to which the necessary transformations have been applied for this notebook (Network layers mapped to necessary FINN-HLS blocks. In this case, the `MatrixVectorActivation` Units). \n", + "We pick the onnx file `cybsec_PE_SIMD.onnx` to which the necessary transformations have been applied for this notebook. This means, network layers mapped to necessary FINN-HLS blocks. In this case, the `MatrixVectorActivation` units. \n", "\n", - "To interact with the `.onnx` file we use the `ModelWrapper()`. This wrapper simplifies the access to different model attributes and allows us to apply custom transformations on the model.\n", + "To interact with the `.onnx` file we use `ModelWrapper()`. This wrapper simplifies the access to different model attributes and allows us to apply custom transformations on the model.\n", "\n", "In the below cell, we load our onnx file and view the cybersecurity MLP network in Netron." ] }, { "cell_type": "code", - "execution_count": 2, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "Serving 'cybsec_PE_SIMD.onnx' at http://0.0.0.0:5920\n" - ] - }, - { - "data": { - "text/html": [ - "\n", - " \n", - " " - ], - "text/plain": [ - "" - ] - }, - "execution_count": 2, - "metadata": {}, - "output_type": "execute_result" - } - ], + "outputs": [], "source": [ "from qonnx.core.modelwrapper import ModelWrapper\n", - "model = ModelWrapper(\"../end2end_example/cybersecurity/output_estimates_only/intermediate_models/step_convert_to_hls.onnx\")\n", - "model.save(\"cybsec_PE_SIMD.onnx\")\n", + "model = ModelWrapper(\"cybsec_PE_SIMD.onnx\")\n", "\n", "showInNetron(\"cybsec_PE_SIMD.onnx\")" ] @@ -162,40 +133,9 @@ }, { "cell_type": "code", - "execution_count": 3, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "Stopping http://0.0.0.0:5920\n", - "Serving 'cybsec_PE_SIMD.onnx' at http://0.0.0.0:5920\n" - ] - }, - { - "data": { - "text/html": [ - "\n", - " \n", - " " - ], - "text/plain": [ - "" - ] - }, - "execution_count": 3, - "metadata": {}, - "output_type": "execute_result" - } - ], + "outputs": [], "source": [ "showInNetron(\"cybsec_PE_SIMD.onnx\")" ] @@ -204,12 +144,12 @@ "cell_type": "markdown", "metadata": {}, "source": [ - "We import the analysis passes (`exp_cycles_per_layer()`) and (`res_estimation()`) to estimate the number of clock cycles and resource utilization of each network layer." + "We import the analysis passes `exp_cycles_per_layer()` and `res_estimation()` to estimate the number of clock cycles and resource utilization of each network layer." ] }, { "cell_type": "code", - "execution_count": 4, + "execution_count": null, "metadata": {}, "outputs": [], "source": [ @@ -228,23 +168,9 @@ }, { "cell_type": "code", - "execution_count": 5, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "data": { - "text/plain": [ - "{'MatrixVectorActivation_0': 38400,\n", - " 'MatrixVectorActivation_1': 4096,\n", - " 'MatrixVectorActivation_2': 4096,\n", - " 'MatrixVectorActivation_3': 64}" - ] - }, - "execution_count": 5, - "metadata": {}, - "output_type": "execute_result" - } - ], + "outputs": [], "source": [ "cycles_dict = model.analysis(exp_cycles_per_layer)\n", "cycles_dict" @@ -252,20 +178,9 @@ }, { "cell_type": "code", - "execution_count": 6, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "data": { - "image/png": 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/Y4z69OmjCRMm6L///a/Ddx5k8vT0tL6f0tPTdeLECXl5eem+++6zPreSFBoaqrJly9r1oa1bt2rz5s3WlW/J8XPbtm1b6/ZXANfGbZnAP1y9evWuO6DKSy+9pC+//FKPPfaY7rrrLjVv3lxPP/30LQ+vXr58ebvXPj4+kiR/f/8s5RkZGUpOTrZuFV2zZo1GjBihuLg4nTt3zq5+cnKy1da17N69W5s3b77mHwrHjh2TJB04cEBlypTJcqvitW55uparj7VYsWKSZD2TlJnkXd2uh4eH7r77bmt9Th0/flznzp3LNs6qVasqIyNDhw4dsm49y6m9e/fqvvvuU758Of9fhyOx7N27V23bts1Ru/3799eFCxe0adOmHB9HTuPv3Lmz+vTpowMHDiggIEBz587VxYsX1alTJ4fbutLx48eVlJSkjz/+WB9//HG2dTI/e0OGDNGyZctUr149Va5cWc2bN9ezzz6rhg0b5nh/Vzpw4IB1++uVMm+fPnDggJVYSMp2BN3s7N69W8nJySpVqlS26zOPR7p8e+6wYcO0fPnyLD8uZP4ok/m84pWxXEuBAgWy9OFixYpledbvWq7ul9ltn9Pviutp1KiRpk6dqj179mjv3r2y2WwKCQmxkr4ePXroxx9/VMOGDa3k6cCBA3Jzc8syarGfn5+KFi2a5Tvheu/XzJkzdebMGU2ZMkXPPPPMDeO9loyMDE2YMEGTJ09WQkKC3bONmd/NkuTm5qaOHTtqypQpOnfunAoVKqRZs2apQIEC1vPZkuPnNqefSeCfjuQOwHWVKlVK8fHxWrp0qRYvXqzFixdr+vTp6ty5s2bMmHHT7V75LEZOyo0xki7/8desWTNVqVJF7733nvz9/eXh4aHvv/9e77//fpYBUbKTkZGhRx55RIMHD852/b333pvDo8iZGx0THNeqVSvNmTNHb731lmbOnJmrIzl26NBBAwYM0KxZs/Tqq6/qv//9r+rUqeNwUn+1zM/mc889d82rJ5nPZVWtWlW7du3SwoULtWTJEs2fP1+TJ0/W8OHDrSH3b6ecjrSYkZGhUqVK2V2luVLmH+5JSUlq0qSJvL29NXr0aFWqVEkFChTQxo0bNWTIkBz126tdq1/d6vZX9svc+K7IvFq6evVq7du3T7Vq1VLhwoXVqFEjTZw4UWfOnNGmTZv05ptvZtn2WleBr3a996thw4aKj4/XpEmT9PTTT9/0s2r//ve/9a9//UvdunXT66+/ruLFi8vNzU39+/fP8v517txZb7/9thYsWKBnnnlGs2fPtgY9yuTouXXl0T+B3ERyB+CGPDw89Pjjj+vxxx9XRkaGXnrpJX300Uf617/+pcqVK+f4D5Dc8N133yk1NVXffvut3S/vV97+lelacVWqVElnzpxRaGjodfcVEBCg2NhYnTlzxu7q3a5du24y+mvvJ7PdK29dTEtLU0JCwg3jvJqvr68KFSqUbZw7d+6Um5tbliukOVGpUiWtW7dOFy9ezPEAL47EUqlSJW3dujVH7bZu3VrNmzdXly5dVKRIkSyjpd5K/MWLF1d4eLhmzZqljh07as2aNVkGd7jZc1GkSBGlp6fn6D0tXLiw2rdvr/bt2ystLU1t2rTRm2++qaioKBUoUCBH+8wUEBBwzfcgc/3NqFSpkpYtW6aGDRte94/vlStX6sSJE/rqq6/UuHFjqzwhISFLe9Ll2/gc/dzfDjn9rrjed2D58uVVvnx5/fjjj9q3b591K2jjxo0VGRmpuXPnKj093e68BAQEKCMjQ7t377YbnOro0aNKSkpy6P2qXLmyxo0bp6ZNm+rRRx9VbGysihQpkuPtM82bN08PPfSQPvvsM7vypKSkLIMdVa9eXffff79mzZqlcuXK6eDBg1lG58zpuQXgGJ65A3BdJ06csHvt5uZmXV3IHJK7cOHCknRLw/bnVOav7Vf+up6cnKzp06dnqVu4cOFsY3r66acVFxenpUuXZlmXlJRkPd/XokULXbp0yS5xSE9Pd3gI8RsJDQ2Vh4eHJk6caHdcn332mZKTkxUeHm6VHTx40PqD/Frc3d3VvHlzffPNN9q/f79VfvToUc2ePVsPPvigvL29HY6zbdu2+uuvvzRp0qQs6651FdKRWNq2bavffvsty0iA12q/c+fOmjhxoqZOnaohQ4bkavydOnXS9u3bNWjQILm7u6tDhw433VYmd3d3tW3bVvPnz882ib1yeoyr+52Hh4cCAwNljNHFixevfZDX0KJFC61fv15xcXFW2dmzZ/Xxxx+rQoUKCgwMdLhN6XJfSk9P1+uvv55l3aVLl6z+l12/TUtL0+TJk+22qVWrlipWrKjx48dn6bvOuNKd0++KQoUKWWXZadSokZYvX67169dbyV1wcLCKFCmit956SwULFlTt2rWt+i1atJCkLD8qvPfee5Jk952QE0FBQfr++++1Y8cOPf744zp//rxD20uX38Or34O5c+fqzz//zLZ+p06d9MMPP2j8+PEqUaKEHnvsMbv1OT23ABzDlTvgH27x4sXZJgsPPPCA7r77bj3//PM6efKkHn74YZUrV04HDhzQBx98oODgYOsX5eDgYLm7u2vs2LFKTk6Wp6enNQ9dbmvevLl1JbFnz546c+aMPvnkE5UqVUpHjhyxq1u7dm1NmTJFb7zxhipXrqxSpUrp4Ycf1qBBg/Ttt9+qZcuW1tDnZ8+e1ZYtWzRv3jzt379fJUuW1OOPP66GDRtq6NCh2r9/vwIDA/XVV1/laNAWR/j6+ioqKkqjRo3So48+qieeeEK7du3S5MmTVbduXbtBCDp37qxVq1bd8A/dN954QzExMXrwwQf10ksvKV++fProo4+UmpqqcePG3VScnTt31syZMxUZGWn9kXr27FktW7ZML730UrbzwzkSy6BBgzRv3jw99dRT6tatm2rXrq2TJ0/q22+/1dSpU1WzZs0sbffp00cpKSl67bXX5OPjo1dffTVX4g8PD1eJEiU0d+5cPfbYY1k+yzd7Lt566y2tWLFC9evXV48ePRQYGKiTJ09q48aNWrZsmU6ePCnp8ufcz89PDRs2VOnSpbVjxw5NmjRJ4eHhN3XVZejQofr888/12GOP6eWXX1bx4sU1Y8YMJSQkaP78+Td9W2uTJk3Us2dPjRkzRvHx8WrevLny58+v3bt3a+7cuZowYYLatWunBx54QMWKFVNERIRefvll2Ww2/ec//8nyOXZzc9OUKVP0+OOPKzg4WF27dlWZMmW0c+dObdu2LdtE4HbK6XdFwYIFFRgYqC+++EL33nuvihcvrurVq1vPDjZq1EizZs2SzWazbtN0d3fXAw88oKVLl6pp06Z2003UrFlTERER+vjjj61bWtevX68ZM2aodevWeuihhxw+lgYNGuibb75RixYt1K5dOy1YsMChKVZatmyp0aNHq2vXrnrggQe0ZcsWzZo1y+5ugys9++yzGjx4sL7++mv16tUry75yem4BOOgOj84JII+43lQIumKY/3nz5pnmzZubUqVKGQ8PD1O+fHnTs2dPc+TIEbv2PvnkE3P33Xcbd3d3u2kRrjUVwty5c7ON55dffrErHzFihJFkjh8/bpV9++23JigoyBQoUMBUqFDBjB071hqaPiEhwaqXmJhowsPDTZEiRYwkuzhOnz5toqKiTOXKlY2Hh4cpWbKkeeCBB8w777xjN0XDiRMnTKdOnYy3t7fx8fExnTp1Mps2bXJoKoSrjynzHFw9dcSkSZNMlSpVTP78+U3p0qVNr169sgwH36RJE5PTr+6NGzeasLAw4+XlZQoVKmQeeughs3btWrs6jkyFYMzl4exfe+01U7FiRZM/f37j5+dn2rVrZzfNgbIZEj4nsRhz+Xz36dPH3HXXXcbDw8OUK1fOREREWFMHXOvzM3jwYCPJTJo06Zbjz/TSSy8ZSWb27Nm5ei6OHj1qevfubfz9/a3tmjVrZj7++GOrzkcffWQaN25sSpQoYTw9PU2lSpXMoEGDTHJy8nWPL3OfV0+FYIwxe/fuNe3atTNFixY1BQoUMPXq1TMLFy60q3Ot83sjH3/8saldu7YpWLCgKVKkiKlRo4YZPHiwOXz4sFVnzZo1pkGDBqZgwYKmbNmyZvDgwdaw+Vf3hZ9++sk88sgjpkiRIqZw4cImKCjIfPDBB9b6iIgIU7hw4SxxZH5f3EhAQIAJDw/PUn7195UxOf+uWLt2raldu7bx8PDI8r5v27bNSDJVq1a1a/uNN94wksy//vWvLLFcvHjRjBo1yvp8+fv7m6ioKGvaiBsdizHZfxa++eYbky9fPtO+ffssUxtc3e7VUyEMHDjQlClTxhQsWNA0bNjQxMXFZXvOMrVo0cJIyravG5Ozc+vodxTwT2czhif6AQC42oABA/TZZ58pMTHRuu0OQM49+eST2rJli/bs2ePsUIB/DJ65AwDgKhcuXNB///tftW3blsQOuAlHjhzRokWL7KYQAXD78cwdAAD/79ixY1q2bJnmzZunEydOqF+/fs4OCfhbSUhI0Jo1a/Tpp58qf/786tmzp7NDAv5RSO4AAPh/27dvV8eOHVWqVClNnDhRwcHBzg4J+FtZtWqVunbtqvLly2vGjBny8/NzdkjAPwrP3AEAAACAC+CZOwAAAABwASR3AAAAAOAC8swzd2+99ZaioqLUr18/jR8/XtLl0coGDhyoOXPmKDU1VWFhYZo8ebJKly5tbXfw4EH16tVLK1askJeXlyIiIjRmzBjly/e/Q1u5cqUiIyO1bds2+fv7a9iwYerSpYvd/j/88EO9/fbbSkxMVM2aNfXBBx+oXr16OY4/IyNDhw8fVpEiRWSz2W7pXAAAAAD4+zLG6PTp0ypbtqzc3O7g9TSnzrL3/9avX28qVKhggoKCTL9+/azyF1980fj7+5vY2Fjz66+/mgYNGpgHHnjAWn/p0iVTvXp1ExoaajZt2mS+//57U7JkSRMVFWXV2bdvnylUqJCJjIw027dvNx988IFxd3c3S5YsserMmTPHeHh4mGnTpplt27aZHj16mKJFi5qjR4/m+BgOHTp03QmhWVhYWFhYWFhYWFj+WcuhQ4duLVFykNMHVDlz5oxq1aqlyZMn64033lBwcLDGjx+v5ORk+fr6avbs2WrXrp0kaefOnapatari4uLUoEEDLV68WC1bttThw4etq3lTp07VkCFDdPz4cXl4eGjIkCFatGiRtm7dau2zQ4cOSkpK0pIlSyRJ9evXV926dTVp0iRJl6/C+fv7q2/fvho6dGiOjiM5OVlFixbVoUOH5O3tnZunCAAAAMDfSEpKivz9/ZWUlCQfH587tl+n35bZu3dvhYeHKzQ0VG+88YZVvmHDBl28eFGhoaFWWZUqVVS+fHkruYuLi1ONGjXsbtMMCwtTr169tG3bNt1///2Ki4uzayOzTv/+/SVJaWlp2rBhg6Kioqz1bm5uCg0NVVxc3DXjTk1NVWpqqvX69OnTkiRvb2+SOwAAAAB3/HEtpyZ3c+bM0caNG/XLL79kWZeYmCgPDw8VLVrUrrx06dJKTEy06lyZ2GWuz1x3vTopKSk6f/68Tp06pfT09Gzr7Ny585qxjxkzRqNGjcrZgQIAAADAbea00TIPHTqkfv36adasWSpQoICzwrhpUVFRSk5OtpZDhw45OyQAAAAA/2BOS+42bNigY8eOqVatWsqXL5/y5cunVatWaeLEicqXL59Kly6ttLQ0JSUl2W139OhR+fn5SZL8/Px09OjRLOsz112vjre3twoWLKiSJUvK3d092zqZbWTH09PTugWTWzEBAAAAOJvTkrtmzZppy5Ytio+Pt5Y6deqoY8eO1r/z58+v2NhYa5tdu3bp4MGDCgkJkSSFhIRoy5YtOnbsmFUnJiZG3t7eCgwMtOpc2UZmncw2PDw8VLt2bbs6GRkZio2NteoAAAAAQF7ntGfuihQpourVq9uVFS5cWCVKlLDKu3fvrsjISBUvXlze3t7q27evQkJC1KBBA0lS8+bNFRgYqE6dOmncuHFKTEzUsGHD1Lt3b3l6ekqSXnzxRU2aNEmDBw9Wt27dtHz5cn355ZdatGiRtd/IyEhFRESoTp06qlevnsaPH6+zZ8+qa9eud+hsAAAAAMCtcfpomdfz/vvvy83NTW3btrWbxDyTu7u7Fi5cqF69eikkJESFCxdWRESERo8ebdWpWLGiFi1apAEDBmjChAkqV66cPv30U4WFhVl12rdvr+PHj2v48OFKTExUcHCwlixZkmWQFQAAAADIq5w+z52rSElJkY+Pj5KTk3n+DgAAAPgHc1Zu4LRn7gAAAAAAuYfkDgAAAABcAMkdAAAAALgAkjsAAAAAcAEkdwAAAADgAkjuAAAAAMAFkNwBAAAAgAsguQMAAAAAF5DP2QHg9rDZnB2Bcxnj7AgAAACAO4srdwAAAADgAkjuAAAAAMAFkNwBAAAAgAsguQMAAAAAF0ByBwAAAAAugOQOAAAAAFwAyR0AAAAAuACSOwAAAABwASR3AAAAAOACSO4AAAAAwAWQ3AEAAACACyC5AwAAAAAXQHIHAAAAAC6A5A4AAAAAXADJHQAAAAC4AJI7AAAAAHABJHcAAAAA4AJI7gAAAADABZDcAQAAAIALILkDAAAAABdAcgcAAAAALoDkDgAAAABcAMkdAAAAALgAkjsAAAAAcAEkdwAAAADgAkjuAAAAAMAFkNwBAAAAgAsguQMAAAAAF+DU5G7KlCkKCgqSt7e3vL29FRISosWLF1vrmzZtKpvNZre8+OKLdm0cPHhQ4eHhKlSokEqVKqVBgwbp0qVLdnVWrlypWrVqydPTU5UrV1Z0dHSWWD788ENVqFBBBQoUUP369bV+/frbcswAAAAAcDs4NbkrV66c3nrrLW3YsEG//vqrHn74YbVq1Urbtm2z6vTo0UNHjhyxlnHjxlnr0tPTFR4errS0NK1du1YzZsxQdHS0hg8fbtVJSEhQeHi4HnroIcXHx6t///56/vnntXTpUqvOF198ocjISI0YMUIbN25UzZo1FRYWpmPHjt2ZEwEAAAAAt8hmjDHODuJKxYsX19tvv63u3buradOmCg4O1vjx47Otu3jxYrVs2VKHDx9W6dKlJUlTp07VkCFDdPz4cXl4eGjIkCFatGiRtm7dam3XoUMHJSUlacmSJZKk+vXrq27dupo0aZIkKSMjQ/7+/urbt6+GDh2a7b5TU1OVmppqvU5JSZG/v7+Sk5Pl7e2dG6filthszo7AufLWpxoAAAD/JCkpKfLx8bnjuUGeeeYuPT1dc+bM0dmzZxUSEmKVz5o1SyVLllT16tUVFRWlc+fOWevi4uJUo0YNK7GTpLCwMKWkpFhX/+Li4hQaGmq3r7CwMMXFxUmS0tLStGHDBrs6bm5uCg0NtepkZ8yYMfLx8bEWf3//WzsBAAAAAHAL8jk7gC1btigkJEQXLlyQl5eXvv76awUGBkqSnn32WQUEBKhs2bLavHmzhgwZol27dumrr76SJCUmJtoldpKs14mJidetk5KSovPnz+vUqVNKT0/Pts7OnTuvGXdUVJQiIyOt15lX7gAAAADAGZye3N13332Kj49XcnKy5s2bp4iICK1atUqBgYF64YUXrHo1atRQmTJl1KxZM+3du1eVKlVyYtSSp6enPD09nRoDAAAAAGRy+m2ZHh4eqly5smrXrq0xY8aoZs2amjBhQrZ169evL0nas2ePJMnPz09Hjx61q5P52s/P77p1vL29VbBgQZUsWVLu7u7Z1slsAwAAAADyOqcnd1fLyMiwG6jkSvHx8ZKkMmXKSJJCQkK0ZcsWu1EtY2Ji5O3tbd3aGRISotjYWLt2YmJirOf6PDw8VLt2bbs6GRkZio2NtXv2DwAAAADyMqfelhkVFaXHHntM5cuX1+nTpzV79mytXLlSS5cu1d69ezV79my1aNFCJUqU0ObNmzVgwAA1btxYQUFBkqTmzZsrMDBQnTp10rhx45SYmKhhw4apd+/e1i2TL774oiZNmqTBgwerW7duWr58ub788kstWrTIiiMyMlIRERGqU6eO6tWrp/Hjx+vs2bPq2rWrU84LAAAAADjKqcndsWPH1LlzZx05ckQ+Pj4KCgrS0qVL9cgjj+jQoUNatmyZlWj5+/urbdu2GjZsmLW9u7u7Fi5cqF69eikkJESFCxdWRESERo8ebdWpWLGiFi1apAEDBmjChAkqV66cPv30U4WFhVl12rdvr+PHj2v48OFKTExUcHCwlixZkmWQFQAAAADIq/LcPHd/V86ay+JamOfO2REAAADgn+ofP88dAAAAAODmkdwBAAAAgAsguQMAAAAAF0ByBwAAAAAugOQOAAAAAFwAyR0AAAAAuACSOwAAAABwASR3AAAAAOACSO4AAAAAwAWQ3AEAAACACyC5AwAAAAAXQHIHAAAAAC6A5A4AAAAAXADJHQAAAAC4AJI7AAAAAHABJHcAAAAA4AJI7gAAAADABZDcAQAAAIALILkDAAAAABdAcgcAAAAALoDkDgAAAABcAMkdAAAAALgAkjsAAAAAcAEkdwAAAADgAkjuAAAAAMAFkNwBAAAAgAsguQMAAAAAF0ByBwAAAAAugOQOAAAAAFwAyR0AAAAAuACSOwAAAABwASR3AAAAAOACSO4AAAAAwAWQ3AEAAACACyC5AwAAAAAXQHIHAAAAAC7AqcndlClTFBQUJG9vb3l7eyskJESLFy+21l+4cEG9e/dWiRIl5OXlpbZt2+ro0aN2bRw8eFDh4eEqVKiQSpUqpUGDBunSpUt2dVauXKlatWrJ09NTlStXVnR0dJZYPvzwQ1WoUEEFChRQ/fr1tX79+ttyzAAAAABwOzg1uStXrpzeeustbdiwQb/++qsefvhhtWrVStu2bZMkDRgwQN99953mzp2rVatW6fDhw2rTpo21fXp6usLDw5WWlqa1a9dqxowZio6O1vDhw606CQkJCg8P10MPPaT4+Hj1799fzz//vJYuXWrV+eKLLxQZGakRI0Zo48aNqlmzpsLCwnTs2LE7dzIAAAAA4BbYjDHG2UFcqXjx4nr77bfVrl07+fr6avbs2WrXrp0kaefOnapatari4uLUoEEDLV68WC1bttThw4dVunRpSdLUqVM1ZMgQHT9+XB4eHhoyZIgWLVqkrVu3Wvvo0KGDkpKStGTJEklS/fr1VbduXU2aNEmSlJGRIX9/f/Xt21dDhw7NUdwpKSny8fFRcnKyvL29c/OU3BSbzdkROFfe+lQDAADgn8RZuUGeeeYuPT1dc+bM0dmzZxUSEqINGzbo4sWLCg0NtepUqVJF5cuXV1xcnCQpLi5ONWrUsBI7SQoLC1NKSop19S8uLs6ujcw6mW2kpaVpw4YNdnXc3NwUGhpq1clOamqqUlJS7BYAAAAAcBanJ3dbtmyRl5eXPD099eKLL+rrr79WYGCgEhMT5eHhoaJFi9rVL126tBITEyVJiYmJdold5vrMdderk5KSovPnz+uvv/5Senp6tnUy28jOmDFj5OPjYy3+/v43dfwAAAAAkBucntzdd999io+P17p169SrVy9FRERo+/btzg7rhqKiopScnGwthw4dcnZIAAAAAP7B8jk7AA8PD1WuXFmSVLt2bf3yyy+aMGGC2rdvr7S0NCUlJdldvTt69Kj8/PwkSX5+fllGtcwcTfPKOlePsHn06FF5e3urYMGCcnd3l7u7e7Z1MtvIjqenpzw9PW/uoAEAAAAglzn9yt3VMjIylJqaqtq1ayt//vyKjY211u3atUsHDx5USEiIJCkkJERbtmyxG9UyJiZG3t7eCgwMtOpc2UZmncw2PDw8VLt2bbs6GRkZio2NteoAAAAAQF7n1Ct3UVFReuyxx1S+fHmdPn1as2fP1sqVK7V06VL5+Pioe/fuioyMVPHixeXt7a2+ffsqJCREDRo0kCQ1b95cgYGB6tSpk8aNG6fExEQNGzZMvXv3tq6qvfjii5o0aZIGDx6sbt26afny5fryyy+1aNEiK47IyEhFRESoTp06qlevnsaPH6+zZ8+qa9euTjkvAAAAAOAopyZ3x44dU+fOnXXkyBH5+PgoKChIS5cu1SOPPCJJev/99+Xm5qa2bdsqNTVVYWFhmjx5srW9u7u7Fi5cqF69eikkJESFCxdWRESERo8ebdWpWLGiFi1apAEDBmjChAkqV66cPv30U4WFhVl12rdvr+PHj2v48OFKTExUcHCwlixZkmWQFQAAAADIq/LcPHd/V8xzl7fwqQYAAICz/OPnuQMAAAAA3DySOwAAAABwASR3AAAAAOACSO4AAAAAwAWQ3AEAAACACyC5AwAAAAAXQHIHAAAAAC6A5A4AAAAAXIDDyd358+d17tw56/WBAwc0fvx4/fDDD7kaGAAAAAAg5xxO7lq1aqWZM2dKkpKSklS/fn29++67atWqlaZMmZLrAQIAAAAAbszh5G7jxo1q1KiRJGnevHkqXbq0Dhw4oJkzZ2rixIm5HiAAAAAA4MYcTu7OnTunIkWKSJJ++OEHtWnTRm5ubmrQoIEOHDiQ6wECAAAAAG7M4eSucuXKWrBggQ4dOqSlS5eqefPmkqRjx47J29s71wMEAAAAANyYw8nd8OHD9corr6hChQqqV6+eQkJCJF2+inf//ffneoAAAAAAgBuzGWOMoxslJibqyJEjqlmzptzcLueH69evl7e3t6pUqZLrQf4dpKSkyMfHR8nJyXniCqbN5uwInMvxTzUAAACQO5yVG9zUPHd+fn4qUqSIYmJidP78eUlS3bp1/7GJHQAAAAA4m8PJ3YkTJ9SsWTPde++9atGihY4cOSJJ6t69uwYOHJjrAQIAAAAAbszh5G7AgAHKnz+/Dh48qEKFClnl7du315IlS3I1OAAAAABAzuRzdIMffvhBS5cuVbly5ezK77nnHqZCAAAAAAAncfjK3dmzZ+2u2GU6efKkPD09cyUoAAAAAIBjHE7uGjVqpJkzZ1qvbTabMjIyNG7cOD300EO5GhwAAAAAIGccvi1z3LhxatasmX799VelpaVp8ODB2rZtm06ePKk1a9bcjhgBAAAAADfg8JW76tWr6/fff9eDDz6oVq1a6ezZs2rTpo02bdqkSpUq3Y4YAQAAAAA3cFOTmCMrJjHPW/hUAwAAwFmclRvk6LbMzZs357jBoKCgmw4GAAAAAHBzcpTcBQcHy2az6UYX+Ww2m9LT03MlMAAAAABAzuUouUtISLjdcQAAAAAAbkGOkruAgIDbHQcAAAAA4BY4PFrmmDFjNG3atCzl06ZN09ixY3MlKAAAAACAYxxO7j766CNVqVIlS3m1atU0derUXAkKAAAAAOAYh5O7xMRElSlTJku5r6+vjhw5kitBAQAAAAAc43By5+/vrzVr1mQpX7NmjcqWLZsrQQEAAAAAHJOjAVWu1KNHD/Xv318XL17Uww8/LEmKjY3V4MGDNXDgwFwPEAAAAABwYw4nd4MGDdKJEyf00ksvKS0tTZJUoEABDRkyRFFRUbkeIAAAAADgxmzmRjOTX8OZM2e0Y8cOFSxYUPfcc488PT1zO7a/lZSUFPn4+Cg5OVne3t7ODkc2m7MjcK6b+1QDAAAAt85ZuYHDz9xNnz5d58+fl5eXl+rWravq1av/4xM7AAAAAHA2h5O7oUOHqnTp0urevbvWrl17O2ICAAAAADjI4eTuzz//1IwZM/TXX3+padOmqlKlisaOHavExESHdz5mzBjVrVtXRYoUUalSpdS6dWvt2rXLrk7Tpk1ls9nslhdffNGuzsGDBxUeHq5ChQqpVKlSGjRokC5dumRXZ+XKlapVq5Y8PT1VuXJlRUdHZ4nnww8/VIUKFVSgQAHVr19f69evd/iYAAAAAMAZHE7u8uXLpyeffFLffPONDh06pB49emjWrFkqX768nnjiCX3zzTfKyMjIUVurVq1S79699fPPPysmJkYXL15U8+bNdfbsWbt6PXr00JEjR6xl3Lhx1rr09HSFh4crLS1Na9eu1YwZMxQdHa3hw4dbdRISEhQeHq6HHnpI8fHx6t+/v55//nktXbrUqvPFF18oMjJSI0aM0MaNG1WzZk2FhYXp2LFjjp4iAAAAALjjbnpAlUzr1q3TtGnTNGPGDJUpU0anTp1SsWLFNH36dDVt2tShto4fP65SpUpp1apVaty4saTLV+6Cg4M1fvz4bLdZvHixWrZsqcOHD6t06dKSpKlTp2rIkCE6fvy4PDw8NGTIEC1atEhbt261tuvQoYOSkpK0ZMkSSVL9+vVVt25dTZo0SZKUkZEhf39/9e3bV0OHDr1h7AyokrcwoAoAAACc5W8zoIokHT16VO+8846qVaumpk2bKiUlRQsXLlRCQoL+/PNPPf3004qIiHC43eTkZElS8eLF7cpnzZqlkiVLqnr16oqKitK5c+esdXFxcapRo4aV2ElSWFiYUlJStG3bNqtOaGioXZthYWGKi4uTJKWlpWnDhg12ddzc3BQaGmrVuVpqaqpSUlLsFgAAAABwFofnuXv88ce1dOlS3XvvverRo4c6d+5sl4wVLlxYAwcO1Ntvv+1QuxkZGerfv78aNmyo6tWrW+XPPvusAgICVLZsWW3evFlDhgzRrl279NVXX0mSEhMT7RI7SdbrzOcAr1UnJSVF58+f16lTp5Senp5tnZ07d2Yb75gxYzRq1CiHjhEAAAAAbheHk7vM2yZDQkKuWcfX11cJCQkOtdu7d29t3bpVP/30k135Cy+8YP27Ro0aKlOmjJo1a6a9e/eqUqVKjgWfi6KiohQZGWm9TklJkb+/v9PiAQAAAPDP5nBy99lnn92wjs1mU0BAQI7b7NOnjxYuXKjVq1erXLly161bv359SdKePXtUqVIl+fn5ZRnV8ujRo5IkPz8/67+ZZVfW8fb2VsGCBeXu7i53d/ds62S2cTVPT0/m9wMAAACQZzj8zN3LL7+siRMnZimfNGmS+vfv71Bbxhj16dNHX3/9tZYvX66KFSvecJv4+HhJUpkyZSRJISEh2rJli92oljExMfL29lZgYKBVJzY21q6dmJgY6+qjh4eHateubVcnIyNDsbGx171CCQAAAAB5hcPJ3fz589WwYcMs5Q888IDmzZvnUFu9e/fWf//7X82ePVtFihRRYmKiEhMTdf78eUnS3r179frrr2vDhg3av3+/vv32W3Xu3FmNGzdWUFCQJKl58+YKDAxUp06d9Ntvv2np0qUaNmyYevfubV1Ze/HFF7Vv3z4NHjxYO3fu1OTJk/Xll19qwIABViyRkZH65JNPNGPGDO3YsUO9evXS2bNn1bVrV0dPEQAAAADccQ7flnnixAn5+PhkKff29tZff/3lUFtTpkyRpCxTJkyfPl1dunSRh4eHli1bpvHjx+vs2bPy9/dX27ZtNWzYMKuuu7u7Fi5cqF69eikkJESFCxdWRESERo8ebdWpWLGiFi1apAEDBmjChAkqV66cPv30U4WFhVl12rdvr+PHj2v48OFKTExUcHCwlixZkmWQFQAAAADIixye56569ep68cUX1adPH7vyDz74QFOmTNH27dtzNcC/C+a5y1uY5w4AAADO4qzcwOErd5GRkerTp4+OHz+uhx9+WJIUGxurd99995oTjQMAAAAAbi+Hk7tu3bopNTVVb775pl5//XVJUoUKFTRlyhR17tw51wMEAAAAANyYw7dlXun48eMqWLCgvLy8cjOmvyVuy8xbuC0TAAAAzvK3uS3zSr6+vrkVBwAAAADgFjg8FQIAAAAAIO8huQMAAAAAF0ByBwAAAAAuwOHk7o8//rjmup9//vmWggEAAAAA3ByHk7vmzZvr5MmTWcrXrFmjRx99NFeCAgAAAAA4xuHkrkGDBmrevLlOnz5tla1evVotWrTQiBEjcjU4AAAAAEDOOJzcffrppypfvrwef/xxpaamasWKFQoPD9fo0aM1YMCA2xEjAAAAAOAGHE7u3NzcNGfOHOXPn18PP/ywnnjiCY0ZM0b9+vW7HfEBAAAAAHLAZowxN6q0efPmLGWnT5/WM888o/DwcPXq1csqDwoKyt0I/yacNQv9tdhszo7AuW78qQYAAABuD2flBjlK7tzc3GSz2XRl1StfZ/7bZrMpPT399kWbh5Hc5S0kdwAAAHAWZ+UG+XJSKSEh4XbHAQAAAAC4BTlK7gICAm53HAAAAACAW+DwgCpjxozRtGnTspRPmzZNY8eOzZWgAAAAAACOcTi5++ijj1SlSpUs5dWqVdPUqVNzJSgAAAAAgGMcTu4SExNVpkyZLOW+vr46cuRIrgQFAAAAAHCMw8mdv7+/1qxZk6V8zZo1Klu2bK4EBQAAAABwTI4GVLlSjx491L9/f128eFEPP/ywJCk2NlaDBw/WwIEDcz1AAAAAAMCNOZzcDRo0SCdOnNBLL72ktLQ0SVKBAgU0ZMgQRUVF5XqAAAAAAIAby9Ek5tk5c+aMduzYoYIFC+qee+6Rp6dnbsf2t8Ik5nkLk5gDAADAWfL0JObZ8fLysgZW+acndgAAAADgbA4PqJKRkaHRo0fLx8dHAQEBCggIUNGiRfX6668rIyPjdsQIAAAAALgBh6/cvfbaa/rss8/01ltvqWHDhpKkn376SSNHjtSFCxf05ptv5nqQAAAAAIDrc/iZu7Jly2rq1Kl64okn7Mq/+eYbvfTSS/rzzz9zNcC/C565y1t45g4AAADO4qzcwOHbMk+ePKkqVapkKa9SpYpOnjyZK0EBAAAAABzjcHJXs2ZNTZo0KUv5pEmTVLNmzVwJCgAAAADgGIefuRs3bpzCw8O1bNkyhYSESJLi4uJ06NAhff/997keIAAAAADgxhy+ctekSRP9/vvvevLJJ5WUlKSkpCS1adNGu3btUqNGjW5HjAAAAACAG7jpScxhjwFV8hY+1QAAAHCWPD2J+ebNm3PcYFBQ0E0HAwAAAAC4OTlK7oKDg2Wz2XSji3w2m03p6em5EhgAAAAAIOdylNwlJCTc7jgAAAAAALcgR8ldQEDA7Y4DAAAAAHALHB4tc8yYMZo2bVqW8mnTpmns2LG5EhQAAAAAwDEOJ3cfffSRqlSpkqW8WrVqmjp1qkNtjRkzRnXr1lWRIkVUqlQptW7dWrt27bKrc+HCBfXu3VslSpSQl5eX2rZtq6NHj9rVOXjwoMLDw1WoUCGVKlVKgwYN0qVLl+zqrFy5UrVq1ZKnp6cqV66s6OjoLPF8+OGHqlChggoUKKD69etr/fr1Dh0PAAAAADiLw8ldYmKiypQpk6Xc19dXR44ccaitVatWqXfv3vr5558VExOjixcvqnnz5jp79qxVZ8CAAfruu+80d+5crVq1SocPH1abNm2s9enp6QoPD1daWprWrl2rGTNmKDo6WsOHD7fqJCQkKDw8XA899JDi4+PVv39/Pf/881q6dKlV54svvlBkZKRGjBihjRs3qmbNmgoLC9OxY8ccOiYAAAAAcAaH57m75557NGLECD333HN25f/5z380YsQI7du376aDOX78uEqVKqVVq1apcePGSk5Olq+vr2bPnq127dpJknbu3KmqVasqLi5ODRo00OLFi9WyZUsdPnxYpUuXliRNnTpVQ4YM0fHjx+Xh4aEhQ4Zo0aJF2rp1q7WvDh06KCkpSUuWLJEk1a9fX3Xr1tWkSZMkSRkZGfL391ffvn01dOjQG8bOPHd5C/PcAQAAwFmclRs4fOWuR48e6t+/v6ZPn64DBw7owIEDmjZtmgYMGKAePXrcUjDJycmSpOLFi0uSNmzYoIsXLyo0NNSqU6VKFZUvX15xcXGSpLi4ONWoUcNK7CQpLCxMKSkp2rZtm1XnyjYy62S2kZaWpg0bNtjVcXNzU2hoqFXnaqmpqUpJSbFbAAAAAMBZcjRa5pUGDRqkEydO6KWXXlJaWpokqUCBAhoyZIiioqJuOpCMjAz1799fDRs2VPXq1SVdvgXUw8NDRYsWtatbunRpJSYmWnWuTOwy12euu16dlJQUnT9/XqdOnVJ6enq2dXbu3JltvGPGjNGoUaNu7mABAAAAIJc5fOXOZrNp7NixOn78uH7++Wf99ttvOnnypN0zbjejd+/e2rp1q+bMmXNL7dwpUVFRSk5OtpZDhw45OyQAAAAA/2AOX7nL5OXlpbp16+ZKEH369NHChQu1evVqlStXzir38/NTWlqakpKS7K7eHT16VH5+fladq0e1zBxN88o6V4+wefToUXl7e6tgwYJyd3eXu7t7tnUy27iap6enPD09b+6AAQAAACCXOXzlLjcZY9SnTx99/fXXWr58uSpWrGi3vnbt2sqfP79iY2Otsl27dungwYMKCQmRJIWEhGjLli12o1rGxMTI29tbgYGBVp0r28isk9mGh4eHateubVcnIyNDsbGxVh0AAAAAyMtu+spdbujdu7dmz56tb775RkWKFLGekfPx8VHBggXl4+Oj7t27KzIyUsWLF5e3t7f69u2rkJAQNWjQQJLUvHlzBQYGqlOnTho3bpwSExM1bNgw9e7d27qy9uKLL2rSpEkaPHiwunXrpuXLl+vLL7/UokWLrFgiIyMVERGhOnXqqF69eho/frzOnj2rrl273vkTAwAAAAAOcngqhFzd+TXG658+fbq6dOki6fIk5gMHDtTnn3+u1NRUhYWFafLkyXa3Sx44cEC9evXSypUrVbhwYUVEROitt95Svnz/y11XrlypAQMGaPv27SpXrpz+9a9/WfvINGnSJL399ttKTExUcHCwJk6cqPr16+foWJgKIW9hKgQAAAA4i7Nygxwld7Vq1VJsbKyKFSum0aNH65VXXlGhQoXuRHx/GyR3eQvJHQAAAJwlT89zt2PHDp09e1aSNGrUKJ05c+a2BgUAAAAAcEyOnrkLDg5W165d9eCDD8oYo3feeUdeXl7Z1r3VKREAAAAAAI7L0W2Zu3bt0ogRI7R3715t3LhRgYGBds+zWY3ZbNq4ceNtCTSv47bMvIXbMgEAAOAsefqZuyu5ubkpMTFRpUqVul0x/S2R3OUtJHcAAABwFmflBg5PhZCRkXE74gAAAAAA3IKbmudu7969Gj9+vHbs2CFJCgwMVL9+/VSpUqVcDQ4AAAAAkDM5Gi3zSkuXLlVgYKDWr1+voKAgBQUFad26dapWrZpiYmJuR4wAAAAAgBtw+Jm7+++/X2FhYXrrrbfsyocOHaoffviBAVV45i5P4Jk7AAAAOEuenufuSjt27FD37t2zlHfr1k3bt2/PlaAAAAAAAI5xOLnz9fVVfHx8lvL4+HhG0AQAAAAAJ3F4QJUePXrohRde0L59+/TAAw9IktasWaOxY8cqMjIy1wMEAAAAANyYw8/cGWM0fvx4vfvuuzp8+LAkqWzZsho0aJBefvll2f6hD3vxzF3ewjN3AAAAcJa/zSTmVzp9+rQkqUiRIrkW0N8VyV3eQnIHAAAAZ/nbTGJ+JZI6AAAAAMgbHB5QBQAAAACQ95DcAQAAAIALILkDAAAAABfgUHJ38eJFNWvWTLt3775d8QAAAAAAboJDyV3+/Pm1efPm2xULAAAAAOAmOXxb5nPPPafPPvvsdsQCAAAAALhJDk+FcOnSJU2bNk3Lli1T7dq1VbhwYbv17733Xq4FBwAAAADIGYeTu61bt6pWrVqSpN9//91une2fPnM2AAAAADiJw8ndihUrbkccAAAAAIBbcNNTIezZs0dLly7V+fPnJUnGmFwLCgAAAADgGIeTuxMnTqhZs2a699571aJFCx05ckSS1L17dw0cODDXAwQAAAAA3JjDyd2AAQOUP39+HTx4UIUKFbLK27dvryVLluRqcAAAAACAnHH4mbsffvhBS5cuVbly5ezK77nnHh04cCDXAgMAAAAA5JzDV+7Onj1rd8Uu08mTJ+Xp6ZkrQQEAAAAAHONwcteoUSPNnDnTem2z2ZSRkaFx48bpoYceytXgAAAAAAA54/BtmePGjVOzZs3066+/Ki0tTYMHD9a2bdt08uRJrVmz5nbECAAAAAC4AYev3FWvXl2///67HnzwQbVq1Upnz55VmzZttGnTJlWqVOl2xAgAAAAAuAGbYYK6XJGSkiIfHx8lJyfL29vb2eHIZnN2BM7FpxoAAADO4qzcwOHbMiXp1KlT+uyzz7Rjxw5JUmBgoLp27arixYvnanAAAAAAgJxx+LbM1atXq0KFCpo4caJOnTqlU6dOaeLEiapYsaJWr159O2IEAAAAANyAw7dl1qhRQyEhIZoyZYrc3d0lSenp6XrppZe0du1abdmy5bYEmtdxW2bewm2ZAAAAcBZn5QYOX7nbs2ePBg4caCV2kuTu7q7IyEjt2bMnV4MDAAAAAOSMw8ldrVq1rGftrrRjxw7VrFkzV4ICAAAAADgmR8nd5s2breXll19Wv3799M477+inn37STz/9pHfeeUcDBgzQgAEDHNr56tWr9fjjj6ts2bKy2WxasGCB3fouXbrIZrPZLY8++qhdnZMnT6pjx47y9vZW0aJF1b17d505cyZL/I0aNVKBAgXk7++vcePGZYll7ty5qlKligoUKKAaNWro+++/d+hYAAAAAMCZcjRaZnBwsGw2m658PG/w4MFZ6j377LNq3759jnd+9uxZ1axZU926dVObNm2yrfPoo49q+vTp1mtPT0+79R07dtSRI0cUExOjixcvqmvXrnrhhRc0e/ZsSZfvd23evLlCQ0M1depUbdmyRd26dVPRokX1wgsvSJLWrl2rZ555RmPGjFHLli01e/ZstW7dWhs3blT16tVzfDwAAAAA4Cw5GlDlwIEDOW4wICDg5gKx2fT111+rdevWVlmXLl2UlJSU5Ypeph07digwMFC//PKL6tSpI0lasmSJWrRooT/++ENly5bVlClT9NprrykxMVEeHh6SpKFDh2rBggXauXOnJKl9+/Y6e/asFi5caLXdoEEDBQcHa+rUqdnuOzU1VampqdbrlJQU+fv7M6BKHsGAKgAAAHCWPD2gSkBAQI6X3LZy5UqVKlVK9913n3r16qUTJ05Y6+Li4lS0aFErsZOk0NBQubm5ad26dVadxo0bW4mdJIWFhWnXrl06deqUVSc0NNRuv2FhYYqLi7tmXGPGjJGPj4+1+Pv758rxAgAAAMDNuKlJzA8fPqyffvpJx44dU0ZGht26l19+OVcCky7fktmmTRtVrFhRe/fu1auvvqrHHntMcXFxcnd3V2JiokqVKmW3Tb58+VS8eHElJiZKkhITE1WxYkW7OqVLl7bWFStWTImJiVbZlXUy28hOVFSUIiMjrdeZV+4AAAAAwBkcTu6io6PVs2dPeXh4qESJErJdcf+fzWbL1eSuQ4cO1r9r1KihoKAgVapUSStXrlSzZs1ybT83w9PTM8vzfwAAAADgLA5PhfCvf/1Lw4cPV3Jysvbv36+EhARr2bdv3+2I0XL33XerZMmS1nx6fn5+OnbsmF2dS5cu6eTJk/Lz87PqHD161K5O5usb1clcDwAAAAB5ncPJ3blz59ShQwe5uTm86S37448/dOLECZUpU0aSFBISoqSkJG3YsMGqs3z5cmVkZKh+/fpWndWrV+vixYtWnZiYGN13330qVqyYVSc2NtZuXzExMQoJCbndhwQAAAAAucLhDK179+6aO3duruz8zJkzio+PV3x8vCQpISFB8fHxOnjwoM6cOaNBgwbp559/1v79+xUbG6tWrVqpcuXKCgsLkyRVrVpVjz76qHr06KH169drzZo16tOnjzp06KCyZctKujw9g4eHh7p3765t27bpiy++0IQJE+yel+vXr5+WLFmid999Vzt37tTIkSP166+/qk+fPrlynAAAAABwu+VoKoQrpaenq2XLljp//rxq1Kih/Pnz261/7733ctzWypUr9dBDD2Upj4iI0JQpU9S6dWtt2rRJSUlJKlu2rJo3b67XX3/dbvCTkydPqk+fPvruu+/k5uamtm3bauLEifLy8rLqbN68Wb1799Yvv/yikiVLqm/fvhoyZIjdPufOnathw4Zp//79uueeezRu3Di1aNEix8firOFOr4WpEJwdAQAAAP6pnJUbOJzcvfHGGxo+fLjuu+8+lS5dOsuAKsuXL8/1IP8OSO7yFpI7AAAAOIuzcgOHR8t89913NW3aNHXp0uU2hAMAAAAAuBkOP3Pn6emphg0b3o5YAAAAAAA3yeHkrl+/fvrggw9uRywAAAAAgJvk8G2Z69ev1/Lly7Vw4UJVq1Yty4AqX331Va4FBwAAAADIGYeTu6JFi6pNmza3IxYAAAAAwE1yOLmbPn367YgDAAAAAHALHH7mDgAAAACQ9zh85a5ixYp2c9tdbd++fbcUEAAAAADAcQ4nd/3797d7ffHiRW3atElLlizRoEGDcisuAAAAAIADHE7u+vXrl235hx9+qF9//fWWAwIAAAAAOC7Xnrl77LHHNH/+/NxqDgAAAADggFxL7ubNm6fixYvnVnMAAAAAAAc4fFvm/fffbzegijFGiYmJOn78uCZPnpyrwQEAAAAAcsbh5K5169Z2r93c3OTr66umTZuqSpUquRUXAAAAAMABNmOMcXYQriAlJUU+Pj5KTk6Wt7e3s8PRdWar+EfgUw0AAABncVZuwCTmAAAAAOACcnxbppub23UnL5ckm82mS5cu3XJQAAAAAADH5Di5+/rrr6+5Li4uThMnTlRGRkauBAUAAAAAcEyOk7tWrVplKdu1a5eGDh2q7777Th07dtTo0aNzNTgAAAAAQM7c1DN3hw8fVo8ePVSjRg1dunRJ8fHxmjFjhgICAnI7PgAAAABADjiU3CUnJ2vIkCGqXLmytm3bptjYWH333XeqXr367YoPAAAAAJADOb4tc9y4cRo7dqz8/Pz0+eefZ3ubJgAAAADAOXI8z52bm5sKFiyo0NBQubu7X7PeV199lWvB/Z0wz13ewjx3AAAAcBZn5QY5vnLXuXPnG06FAAAAAABwjhwnd9HR0bcxDAAAAADArbip0TIBAAAAAHkLyR0AAAAAuACSOwAAAABwASR3AAAAAOACSO4AAAAAwAWQ3AEAAACACyC5AwAAAAAXQHIHAAAAAC6A5A4AAAAAXADJHQAAAAC4AJI7AAAAAHABTk3uVq9erccff1xly5aVzWbTggUL7NYbYzR8+HCVKVNGBQsWVGhoqHbv3m1X5+TJk+rYsaO8vb1VtGhRde/eXWfOnLGrs3nzZjVq1EgFChSQv7+/xo0blyWWuXPnqkqVKipQoIBq1Kih77//PtePFwAAAABuF6cmd2fPnlXNmjX14YcfZrt+3LhxmjhxoqZOnap169apcOHCCgsL04ULF6w6HTt21LZt2xQTE6OFCxdq9erVeuGFF6z1KSkpat68uQICArRhwwa9/fbbGjlypD7++GOrztq1a/XMM8+oe/fu2rRpk1q3bq3WrVtr69att+/gAQAAACAX2YwxxtlBSJLNZtPXX3+t1q1bS7p81a5s2bIaOHCgXnnlFUlScnKySpcurejoaHXo0EE7duxQYGCgfvnlF9WpU0eStGTJErVo0UJ//PGHypYtqylTpui1115TYmKiPDw8JElDhw7VggULtHPnTklS+/btdfbsWS1cuNCKp0GDBgoODtbUqVNzFH9KSop8fHyUnJwsb2/v3DotN81mc3YEzpU3PtUAAAD4J3JWbpBnn7lLSEhQYmKiQkNDrTIfHx/Vr19fcXFxkqS4uDgVLVrUSuwkKTQ0VG5ublq3bp1Vp3HjxlZiJ0lhYWHatWuXTp06ZdW5cj+ZdTL3k53U1FSlpKTYLQAAAADgLHk2uUtMTJQklS5d2q68dOnS1rrExESVKlXKbn2+fPlUvHhxuzrZtXHlPq5VJ3N9dsaMGSMfHx9r8ff3d/QQAQAAACDX5NnkLq+LiopScnKytRw6dMjZIQEAAAD4B8uzyZ2fn58k6ejRo3blR48etdb5+fnp2LFjdusvXbqkkydP2tXJro0r93GtOpnrs+Pp6Slvb2+7BQAAAACcJc8mdxUrVpSfn59iY2OtspSUFK1bt04hISGSpJCQECUlJWnDhg1WneXLlysjI0P169e36qxevVoXL1606sTExOi+++5TsWLFrDpX7iezTuZ+AAAAACCvc2pyd+bMGcXHxys+Pl7S5UFU4uPjdfDgQdlsNvXv319vvPGGvv32W23ZskWdO3dW2bJlrRE1q1atqkcffVQ9evTQ+vXrtWbNGvXp00cdOnRQ2bJlJUnPPvusPDw81L17d23btk1ffPGFJkyYoMjISCuOfv36acmSJXr33Xe1c+dOjRw5Ur/++qv69Olzp08JAAAAANwUp06FsHLlSj300ENZyiMiIhQdHS1jjEaMGKGPP/5YSUlJevDBBzV58mTde++9Vt2TJ0+qT58++u677+Tm5qa2bdtq4sSJ8vLysups3rxZvXv31i+//KKSJUuqb9++GjJkiN0+586dq2HDhmn//v265557NG7cOLVo0SLHx8JUCHkLUyEAAADAWZyVG+SZee7+7kju8hY+1QAAAHAW5rkDAAAAANw0kjsAAAAAcAEkdwAAAADgAkjuAAAAAMAFkNwBAAAAgAsguQMAAAAAF0ByBwAAAAAugOQOAAAAAFwAyR0AAAAAuACSOwAAAABwASR3AAAAAOACSO4AAAAAwAWQ3AEAAACACyC5AwAAAAAXQHIHAAAAAC6A5A4AAAAAXADJHQAAAAC4AJI7AAAAAHABJHcAAAAA4AJI7gAAAADABZDcAQAAAIALILkDAAAAABdAcgcAAAAALoDkDgAAAABcAMkdAAAAALgAkjsAAAAAcAEkdwAAAADgAkjuAAAAAMAFkNwBAAAAgAsguQMAAAAAF0ByBwAAAAAugOQOAAAAAFwAyR0AAAAAuACSOwAAAABwASR3AAAAAOACSO4AAAAAwAWQ3AEAAACAC8jTyd3IkSNls9nslipVqljrL1y4oN69e6tEiRLy8vJS27ZtdfToUbs2Dh48qPDwcBUqVEilSpXSoEGDdOnSJbs6K1euVK1ateTp6anKlSsrOjr6ThweAAAAAOSaPJ3cSVK1atV05MgRa/npp5+sdQMGDNB3332nuXPnatWqVTp8+LDatGljrU9PT1d4eLjS0tK0du1azZgxQ9HR0Ro+fLhVJyEhQeHh4XrooYcUHx+v/v376/nnn9fSpUvv6HECAAAAwK2wGWOMs4O4lpEjR2rBggWKj4/Psi45OVm+vr6aPXu22rVrJ0nauXOnqlatqri4ODVo0ECLFy9Wy5YtdfjwYZUuXVqSNHXqVA0ZMkTHjx+Xh4eHhgwZokWLFmnr1q1W2x06dFBSUpKWLFmS41hTUlLk4+Oj5ORkeXt739qB5wKbzdkROFfe/VQDAADA1TkrN8jzV+52796tsmXL6u6771bHjh118OBBSdKGDRt08eJFhYaGWnWrVKmi8uXLKy4uTpIUFxenGjVqWImdJIWFhSklJUXbtm2z6lzZRmadzDauJTU1VSkpKXYLAAAAADhLnk7u6tevr+joaC1ZskRTpkxRQkKCGjVqpNOnTysxMVEeHh4qWrSo3TalS5dWYmKiJCkxMdEusctcn7nuenVSUlJ0/vz5a8Y2ZswY+fj4WIu/v/+tHi4AAAAA3LR8zg7geh577DHr30FBQapfv74CAgL05ZdfqmDBgk6MTIqKilJkZKT1OiUlhQQPAAAAgNPk6St3VytatKjuvfde7dmzR35+fkpLS1NSUpJdnaNHj8rPz0+S5Ofnl2X0zMzXN6rj7e193QTS09NT3t7edgsAAAAAOMvfKrk7c+aM9u7dqzJlyqh27drKnz+/YmNjrfW7du3SwYMHFRISIkkKCQnRli1bdOzYMatOTEyMvL29FRgYaNW5so3MOpltAAAAAMDfQZ5O7l555RWtWrVK+/fv19q1a/Xkk0/K3d1dzzzzjHx8fNS9e3dFRkZqxYoV2rBhg7p27aqQkBA1aNBAktS8eXMFBgaqU6dO+u2337R06VINGzZMvXv3lqenpyTpxRdf1L59+zR48GDt3LlTkydP1pdffqkBAwY489ABAAAAwCF5+pm7P/74Q88884xOnDghX19fPfjgg/r555/l6+srSXr//ffl5uamtm3bKjU1VWFhYZo8ebK1vbu7uxYuXKhevXopJCREhQsXVkREhEaPHm3VqVixohYtWqQBAwZowoQJKleunD799FOFhYXd8eMFAAAAgJuVp+e5+zthnru8hU81AAAAnIV57gAAAAAANy1P35YJAHkJV8SdHQFcDX3K2REAcDVcuQMAAAAAF0ByBwAAAAAugOQOAAAAAFwAyR0AAAAAuACSOwAAAABwASR3AAAAAOACSO4AAAAAwAWQ3AEAAACACyC5AwAAAAAXQHIHAAAAAC6A5A4AAAAAXADJHQAAAAC4AJI7AAAAAHABJHcAAAAA4AJI7gAAAADABZDcAQAAAIALILkDAAAAABdAcgcAAAAALoDkDgAAAABcAMkdAAAAALgAkjsAAAAAcAEkdwAAAADgAkjuAAAAAMAFkNwBAAAAgAsguQMAAAAAF0ByBwAAAAAugOQOAAAAAFwAyR0AAAAAuACSOwAAAABwASR3AAAAAOACSO4AAAAAwAWQ3AEAAACACyC5AwAAAAAXQHIHAAAAAC6A5A4AAAAAXADJ3VU+/PBDVahQQQUKFFD9+vW1fv16Z4cEAAAAADdEcneFL774QpGRkRoxYoQ2btyomjVrKiwsTMeOHXN2aAAAAABwXSR3V3jvvffUo0cPde3aVYGBgZo6daoKFSqkadOmOTs0AAAAALiufM4OIK9IS0vThg0bFBUVZZW5ubkpNDRUcXFxWeqnpqYqNTXVep2cnCxJSklJuf3B4oZ4G4DcR78Cchd9CreDj4+zI3Cu//+T3OkycwJjzB3dL8nd//vrr7+Unp6u0qVL25WXLl1aO3fuzFJ/zJgxGjVqVJZyf3//2xYjcu6f/sUG3A70KyB30aeA3JfX+tXp06flcweDIrm7SVFRUYqMjLReZ2Rk6OTJkypRooRsNpsTI3O+lJQU+fv769ChQ/L29nZ2OIBLoF8BuYs+BeQ++tX/GGN0+vRplS1b9o7ul+Tu/5UsWVLu7u46evSoXfnRo0fl5+eXpb6np6c8PT3tyooWLXo7Q/zb8fb2/sd3bCC30a+A3EWfAnIf/eqyO3nFLhMDqvw/Dw8P1a5dW7GxsVZZRkaGYmNjFRIS4sTIAAAAAODGuHJ3hcjISEVERKhOnTqqV6+exo8fr7Nnz6pr167ODg0AAAAArovk7grt27fX8ePHNXz4cCUmJio4OFhLlizJMsgKrs/T01MjRozIctsqgJtHvwJyF30KyH30K+ezmTs9PicAAAAAINfxzB0AAAAAuACSOwAAAABwASR3AAAAAOACSO6crEKFCho/fryzw/jb2b9/v2w2m+Lj42/7vniP/l54v24OfQrXw3t2c+hXuBber5tDn8oBAxMREWEkmZ49e2ZZ99JLLxlJJiIiIkdtJSQkGElm06ZNOap/7Ngxc/bs2RzVbdmypQkLC8t23erVq40k89tvv+WorWtZsWKFkWROnTp1S+1c7dy5c6ZYsWKmRIkS5sKFCw5tGxERYVq1amVXdunSJXPkyBFz8eLFXItx+vTpxsfHJ0u5I+9Rbpk0aZIJCAgwnp6epl69embdunV3dP+3ij71P/Qpnyzld7pPrVq1yrRs2dKUKVPGSDJff/31Hdt3bqJf/Q/9yidL+Z3uV//+979NnTp1jJeXl/H19TWtWrUyO3fuvGP7zw30qf+hT/lkKb/TfWry5MmmRo0apkiRIqZIkSKmQYMG5vvvv3e4Ha7c/T9/f3/NmTNH58+ft8ouXLig2bNnq3z58rm+v7S0NEmSr6+vChUqlKNtunfvrpiYGP3xxx9Z1k2fPl116tRRUFBQrsZ5s4wxunTpkvV6/vz5qlatmqpUqaIFCxbccvvu7u7y8/NTvny3fzYPR96j3PDFF18oMjJSI0aM0MaNG1WzZk2FhYXp2LFjdyyG3ECfyl30qZt39uxZ1axZUx9++OEd2+ftQr/KXfSrm7dq1Sr17t1bP//8s2JiYnTx4kU1b95cZ8+evWMx5Ab6VO6iT928cuXK6a233tKGDRv066+/6uGHH1arVq20bds2xxrK5aTzbynzl4Hq1aub//73v1b5rFmzTFBQkGnVqpX1y83ixYtNw4YNjY+PjylevLgJDw83e/bssbaRZLc0adLEbh9vvPGGKVOmjKlQoYIxxpiAgADz/vvvG2Mu/2qSP39+s3r1aqu9sWPHGl9fX5OYmGguXrxoSpcubV5//XW7+E+fPm28vLzMlClTjDHG/Pjjj+bBBx80BQoUMOXKlTN9+/Y1Z86csepfuHDBDB482JQrV854eHiYSpUqmU8//dT61enKJfO4L1y4YPr27Wt8fX2Np6enadiwoVm/fr3VZuYvPt9//72pVauWyZ8/v1mxYoW1vmnTpmbq1KlmypQp5pFHHsnyHmzdutWEh4ebIkWKGC8vL/Pggw+aPXv2mBEjRmSJacWKFXa/kKWnp5u77rrLTJ482a7NjRs3GpvNZvbv32+MMebdd9811atXN4UKFTLlypUzvXr1MqdPn7aL/8plxIgRWd4jY4w5cOCAeeKJJ0zhwoVNkSJFzFNPPWUSExOt9SNGjDA1a9Y0M2fONAEBAcbb29u0b9/epKSkZDnu7NSrV8/07t3bep2enm7Kli1rxowZk6Pt8wL6FH0qL/WpK+lvfuWOfkW/yov9ypjLVzkkmVWrVt3U9s5An6JP5eU+ZYwxxYoVM59++qlD25Dcmf91vPfee880a9bMKm/WrJl5//337Tr3vHnzzPz5883u3bvNpk2bzOOPP25q1Khh0tPTjTHGrF+/3kgyy5YtM0eOHDEnTpyw9uHl5WU6depktm7darZu3WqMyfrBGTRokAkICDBJSUlm48aNxsPDw3zzzTd26ytVqmQyMjKssmnTppmCBQuapKQks2fPHlO4cGHz/vvvm99//92sWbPG3H///aZLly5W/aefftr4+/ubr776yuzdu9csW7bMzJkzx1y6dMnMnz/fSDK7du0yR44cMUlJScYYY15++WVTtmxZ8/3335tt27aZiIgIU6xYMev4MjtHUFCQ+eGHH8yePXusdXv27DGenp7m5MmT5sSJE6ZAgQJWhzPGmD/++MMUL17ctGnTxvzyyy9m165dZtq0aWbnzp3m9OnT5umnnzaPPvqoOXLkiDly5IhJTU3NcvvDK6+8Yh588EG793XgwIF2Ze+//75Zvny5SUhIMLGxsea+++4zvXr1MsYYk5qaasaPH2+8vb2t/WR2/Cvfo/T0dBMcHGwefPBB8+uvv5qff/7Z1K5d2/oSN+Zy5/by8jJt2rQxW7ZsMatXrzZ+fn7m1VdfveZnMFNqaqpxd3fP8sdn586dzRNPPHHD7fMK+hR9Kq/0qau5QnJHv6Jf5bV+ZYwxu3fvNpLMli1bbmp7Z6BP0afyap+6dOmS+fzzz42Hh4fZtm2bQ9uS3Jn/de5jx44ZT09Ps3//frN//35ToEABc/z4cbvOfbXjx4/bfZld657riIgIU7p0aZOammpXfnXnTk1NNcHBwebpp582gYGBpkePHnb1d+zYYf16kalRo0bmueeeM8YY0717d/PCCy/YbfPjjz8aNzc3c/78ebNr1y4jycTExGR7PNndc33mzBmTP39+M2vWLKssLS3NlC1b1owbN85uuwULFmRp89VXXzWtW7e2Xrdq1cr6VcQYY6KiokzFihVNWlpatjFld8/11ed506ZNxmazmQMHDhhjjPVrTuavWdmZO3euKVGihPX6WvdcX/ke/fDDD8bd3d0cPHjQWr9t2zYjyfola8SIEaZQoUJ2v9QMGjTI1K9f/5qxZPrzzz+NJLN27Vq78kGDBpl69erdcPu8gj71P/Qpnyz17mSfuporJHf0K/pVXutX6enpJjw83DRs2NDhbZ2JPvU/9CmfLPWc0ac2b95sChcubNzd3Y2Pj49ZtGhRjrfNxDN3V/D19VV4eLiio6M1ffp0hYeHq2TJknZ1du/erWeeeUZ33323vL29VaFCBUnSwYMHb9h+jRo15OHhcd06Hh4emjVrlubPn68LFy7o/ffft1tfpUoVPfDAA5o2bZokac+ePfrxxx/VvXt3SdJvv/2m6OhoeXl5WUtYWJgyMjKUkJCg+Ph4ubu7q0mTJjk9Ldq7d68uXryohg0bWmX58+dXvXr1tGPHDru6derUsXudnp6uGTNm6LnnnrPKnnvuOUVHRysjI0OSFB8fr0aNGil//vw5julqwcHBqlq1qmbPni3p8rMAx44d01NPPWXVWbZsmZo1a6a77rpLRYoUUadOnXTixAmdO3cux/vZsWOH/P395e/vb5UFBgaqaNGidueiQoUKKlKkiPW6TJkyf7tn5nIDfSp79Kn/oU85jn6VPfrV/9zpftW7d29t3bpVc+bMcXjbvIA+lT361P/cqT513333KT4+XuvWrVOvXr0UERGh7du353h7iakQsujWrZuio6M1Y8YMdevWLcv6xx9/XCdPntQnn3yidevWad26dZL+94Ds9RQuXDhHMaxdu1aSdPLkSZ08eTLL+u7du2v+/Pk6ffq0pk+frkqVKlmd9cyZM+rZs6fi4+Ot5bffftPu3btVqVIlFSxYMEcx3Kyrj3Hp0qX6888/1b59e+XLl0/58uVThw4ddODAAcXGxkpSrsXUsWNHq3PPnj1bjz76qEqUKCHp8tC5LVu2VFBQkObPn68NGzZYgyvk5L1z1NVfVDabzfoyu56SJUvK3d1dR48etSs/evSo/Pz8cjXGO4U+dWvoU5fdbJ9yVfSrW0O/uiw3+lWfPn20cOFCrVixQuXKlcvN8O4o+tStoU9ddqt9ysPDQ5UrV1bt2rU1ZswY1axZUxMmTHAoBpK7qzz66KNKS0vTxYsXFRYWZrfuxIkT2rVrl4YNG6ZmzZqpatWqOnXqlF2dzF9m0tPTb2r/e/fu1YABA/TJJ5+ofv36ioiIyPKhePrpp+Xm5qbZs2dr5syZ6tatm2w2mySpVq1a2r59uypXrpxl8fDwUI0aNZSRkaFVq1Zlu//s4q9UqZI8PDy0Zs0aq+zixYv65ZdfFBgYeN3j+eyzz9ShQwe7L5v4+Hh16NBBn332mSQpKChIP/74oy5evHjNmHJyPp999llt3bpVGzZs0Lx589SxY0dr3YYNG5SRkaF3331XDRo00L333qvDhw87vJ+qVavq0KFDOnTokFW2fft2JSUl3fBc5ISHh4dq165tffFJUkZGhmJjYxUSEnLL7TsDfYo+dT23u0+5KvoV/ep67kS/MsaoT58++vrrr7V8+XJVrFgxV9p1FvoUfep6nPX/qoyMDKWmpjq2kcM3crqgq+/pTU5ONsnJydbrzHuu09PTTYkSJcxzzz1ndu/ebWJjY03dunXtnuG4ePGiKViwoHnjjTdMYmKi9UBqdvcNG2N/P++lS5dMgwYNTNu2bY0xxhw+fNiUKFHCuq/5St27dzfFihUz7u7u5s8//7TKf/vtN1OwYEHTu3dvs2nTJvP777+bBQsW2I2+2KVLF+Pv72++/vprs2/fPrNixQrzxRdfGGMuP9xqs9lMdHS0OXbsmPVQab9+/UzZsmXN4sWL7R6oPXnypDEm+3u1jx07ZvLnz28WL16cJf7vv//eeHp6mhMnTpi//vrLlChRwnqg9vfffzczZ8605st58803Tfny5c3OnTvN8ePHTVpa2jXvbW/YsKGpWbOmKVKkiDl37pxVHh8fbySZ8ePHm71795qZM2eau+66yy7mNWvWWA9DHz9+3Jrb5Mr3KCMjwwQHB5tGjRqZDRs2mHXr1mX7QG3NmjXt4nr//fdNQEBAlvOQnTlz5hhPT08THR1ttm/fbl544QVTtGhRuxGZ8jr6FH3KmLzTp06fPm02bdpkNm3aZCSZ9957z2zatMl6RuPvgn5FvzIm7/SrXr16GR8fH7Ny5UprIIojR47YHU9eR5+iTxmTd/rU0KFDzapVq0xCQoLZvHmzGTp0qLHZbOaHH37I0faZSO7MtTtepisfqI2JiTFVq1Y1np6eJigoyKxcuTLLA/qffPKJ8ff3N25ublmGwr3alR+cUaNGmTJlypi//vrLWj9//nzj4eFh4uPj7bZbu3atkWRatGiRpc3169ebRx55xHh5eZnChQuboKAg8+abb1rrz58/bwYMGGDKlCljPDw8TOXKlc20adOs9aNHjzZ+fn7GZrNZx33+/HnTt29fU7JkyesOhXtl537nnXdM0aJFs31QNjU11RQtWtRMmDDBGHP5S6l58+amUKFCpkiRIqZRo0Zm7969xpjLXxKZx6NshsK90uTJk40k07lz5yz7fO+990yZMmVMwYIFTVhYmJk5c2aWmF988UVTokSJXBkK90qOdG5jjPnggw9M+fLljYeHh6lXr575+eefc7xtXkCfok9lygt9KruhrqWcT06cV9Cv6FeZ8kK/yq5PSTLTp0/P0fZ5AX2KPpUpL/Spbt26mYCAAOPh4WF8fX1Ns2bNHE7sjDHGZowxjl3rAwAAAADkNTxzBwAAAAAugOQOuIMOHjxoN0zx1UtOhlQG8D/0KSD30a+A3HUn+xS3ZQJ30KVLl7R///5rrq9QoYLy5ct35wIC/uboU0Duo18BuetO9imSOwAAAABwAdyWCQAAAAAugOQOAAAAAFwAyR0AAAAAuACSOwAAAABwASR3AADkkqZNm6p///45rr9y5UrZbDYlJSXdtpgAAP8cJHcAAKfr0qWLbDab3nrrLbvyBQsWyGazOdRWhQoVNH78+FyMDgCAvweSOwBAnlCgQAGNHTtWp06dcnYoDktLS3N2CLfk4sWLzg4BAJALSO4AAHlCaGio/Pz8NGbMmOvW++mnn9SoUSMVLFhQ/v7+evnll3X27FlJl2+LPHDggAYMGCCbzSabzSZjjHx9fTVv3jyrjeDgYJUpU8auTU9PT507d06SdPDgQbVq1UpeXl7y9vbW008/raNHj1r1R44cqeDgYH366aeqWLGiChQokG2sixYtko+Pj2bNmpWjc3DixAk988wzuuuuu1SoUCHVqFFDn3/+ubV+5syZKlGihFJTU+22a926tTp16mS9/uabb1SrVi0VKFBAd999t0aNGqVLly5Z6202m6ZMmaInnnhChQsX1ptvvqlTp06pY8eO8vX1VcGCBXXPPfdo+vTpOYobAJA3kNwBAPIEd3d3/fvf/9YHH3ygP/74I9s6e/fu1aOPPqq2bdtq8+bN+uKLL/TTTz+pT58+kqSvvvpK5cqV0+jRo3XkyBEdOXJENptNjRs31sqVKyVJp06d0o4dO3T+/Hnt3LlTkrRq1SrVrVtXhQoVUkZGhlq1aqWTJ09q1apViomJ0b59+9S+fXu7WPbs2aP58+frq6++Unx8fJZYZ8+erWeeeUazZs1Sx44dc3QOLly4oNq1a2vRokXaunWrXnjhBXXq1Enr16+XJD311FNKT0/Xt99+a21z7NgxLVq0SN26dZMk/fjjj+rcubP69eun7du366OPPlJ0dLTefPNNu32NHDlSTz75pLZs2aJu3brpX//6l7Zv367Fixdrx44dmjJlikqWLJmjuAEAeUM+ZwcAAECmJ598UsHBwRoxYoQ+++yzLOvHjBmjjh07WoOW3HPPPZo4caKaNGmiKVOmqHjx4nJ3d1eRIkXk5+dnbde0aVN99NFHkqTVq1fr/vvvl5+fn1auXKkqVapo5cqVatKkiSQpNjZWW7ZsUUJCgvz9/SVdvmJWrVo1/fLLL6pbt66ky7dizpw5U76+vlni/PDDD/Xaa6/pu+++s9rNibvuukuvvPKK9bpv375aunSpvvzyS9WrV08FCxbUs88+q+nTp+upp56SJP33v/9V+fLl1bRpU0nSqFGjNHToUEVEREiS7r77br3++usaPHiwRowYYbX97LPPqmvXrtbrgwcP6v7771edOnUkXX52EQDw98KVOwBAnjJ27FjNmDFDO3bsyLLut99+U3R0tLy8vKwlLCxMGRkZSkhIuGabTZo00fbt23X8+HGtWrVKTZs2VdOmTbVy5UpdvHhRa9eutZKjHTt2yN/f30rsJCkwMFBFixa1iykgICDbxG7evHkaMGCAYmJiHErsJCk9PV2vv/66atSooeLFi8vLy0tLly7VwYMHrTo9evTQDz/8oD///FOSFB0dbQ1Ik3mORo8ebXeOevTooSNHjli3nUqykrhMvXr10pw5cxQcHKzBgwdr7dq1DsUOAHA+kjsAQJ7SuHFjhYWFKSoqKsu6M2fOqGfPnoqPj7eW3377Tbt371alSpWu2WZmsrRq1Sq75G7VqlX65ZdfdPHiRT3wwAMOxVm4cOFsy++//375+vpq2rRpMsY41Obbb7+tCRMmaMiQIVqxYoXi4+MVFhZmN2DL/fffr5o1a2rmzJnasGGDtm3bpi5duljrz5w5o1GjRtmdoy1btmj37t12zwZeHf9jjz1mPa94+PBhNWvWzO4qIgAg7+O2TABAnvPWW28pODhY9913n115rVq1tH37dlWuXPma23p4eCg9Pd2uzGazqVGjRvrmm2+0bds2PfjggypUqJBSU1P10UcfqU6dOlayU7VqVR06dEiHDh2yrt5t375dSUlJCgwMvGHslSpV0rvvvqumTZvK3d1dkyZNyvFxr1mzRq1atdJzzz0nScrIyNDvv/+eZb/PP/+8xo8frz///FOhoaF2Vxlr1aqlXbt2XfccXYuvr68iIiIUERGhRo0aadCgQXrnnXccbgcA4BxcuQMA5Dk1atRQx44dNXHiRLvyIUOGaO3aterTp4/i4+O1e/duffPNN9aAKtLlZ8VWr16tP//8U3/99ZdV3rRpU33++ecKDg6Wl5eX3Nzc1LhxY82aNcvu9snQ0FBr/xs3btT69evVuXNnNWnSJMutjNdy7733asWKFZo/f75Dk5rfc889iomJ0dq1a7Vjxw717NnTbpTOTM8++6z++OMPffLJJ9ZAKpmGDx+umTNnatSoUdq2bZt27NihOXPmaNiwYdfd9/Dhw/XNN99oz5492rZtmxYuXKiqVavmOHYAgPOR3AEA8qTRo0crIyPDriwoKEirVq3S77//rkaNGun+++/X8OHDVbZsWbvt9u/fr0qVKtk9E9ekSROlp6dbz9ZJlxO+q8tsNpu++eYbFStWTI0bN1ZoaKjuvvtuffHFFw7Ff99992n58uX6/PPPNXDgwBxtM2zYMNWqVUthYWFq2rSp/Pz81Lp16yz1fHx81LZtW3l5eWVZHxYWpoULF+qHH35Q3bp11aBBA73//vsKCAi47r49PDwUFRWloKAgNW7cWO7u7pozZ05ODxcAkAfYjKMPBAAAAKdr1qyZqlWrluXqJgDgn4vkDgCAv5FTp05p5cqVateunbZv357luUQAwD8XA6oAAPA3cv/99+vUqVMaO3YsiR0AwA5X7gAAAADABTCgCgAAAAC4AJI7AAAAAHABJHcAAAAA4AJI7gAAAADABZDcAQAAAIALILkDAAAAABdAcgcAAAAALoDkDgAAAABcwP8Binx+rd+7B7sAAAAASUVORK5CYII=", - "text/plain": [ - "
    " - ] - }, - "metadata": {}, - "output_type": "display_data" - } - ], + "outputs": [], "source": [ "import matplotlib.pyplot as plt\n", "\n", @@ -273,7 +188,7 @@ "plt.bar(cycles_dict.keys(), cycles_dict.values(), color ='blue', width = 0.3)\n", "plt.xlabel(\"Network layers\")\n", "plt.ylabel(\"Number of clock cycles\")\n", - "plt.title(\"Estimated no. of clock cycles for each network layer\")\n", + "plt.title(\"Clock cycles per layer PE=SIMD=1\")\n", "plt.show()" ] }, @@ -291,43 +206,9 @@ }, { "cell_type": "code", - "execution_count": 7, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "data": { - "text/plain": [ - "{'MatrixVectorActivation_0': {'BRAM_18K': 5,\n", - " 'BRAM_efficiency': 0.8333333333333334,\n", - " 'LUT': 319,\n", - " 'URAM': 0,\n", - " 'URAM_efficiency': 1,\n", - " 'DSP': 0},\n", - " 'MatrixVectorActivation_1': {'BRAM_18K': 1,\n", - " 'BRAM_efficiency': 0.4444444444444444,\n", - " 'LUT': 320,\n", - " 'URAM': 0,\n", - " 'URAM_efficiency': 1,\n", - " 'DSP': 0},\n", - " 'MatrixVectorActivation_2': {'BRAM_18K': 1,\n", - " 'BRAM_efficiency': 0.4444444444444444,\n", - " 'LUT': 320,\n", - " 'URAM': 0,\n", - " 'URAM_efficiency': 1,\n", - " 'DSP': 0},\n", - " 'MatrixVectorActivation_3': {'BRAM_18K': 1,\n", - " 'BRAM_efficiency': 0.006944444444444444,\n", - " 'LUT': 320,\n", - " 'URAM': 0,\n", - " 'URAM_efficiency': 1,\n", - " 'DSP': 0}}" - ] - }, - "execution_count": 7, - "metadata": {}, - "output_type": "execute_result" - } - ], + "outputs": [], "source": [ "res_dict = model.analysis(res_estimation)\n", "res_dict" @@ -349,20 +230,9 @@ }, { "cell_type": "code", - "execution_count": 8, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "data": { - "image/png": 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/flzS1XtrihUrlu7yvptdHpaR6481f/78kmSFgbSAdv12PTw8VKZMGWt5Zp04cUIXLlzIsM4KFSooNTVVhw4dUsWKFV3ablbJ7Hcs3a3PXhpPT08NHTpUffv2VdGiRVWrVi01bdpUHTp0UEBAgKSrnxVJeuKJJzLchq+vr6T/vYcPPvhguj7lypVzCjCu+OOPP+Tm5pZultSAgAD5+/un+2xkNMNqRtKO62aX5SYmJip//vy6ePGihgwZogkTJujPP/90utzu2j+E7Nu3T61atcrU/m81Ju5kfV9fX+3Zs0fGmAzfD0mZujS4WrVqypcvn1atWqXIyEitWrVKgwYNUkBAgEaNGqVLly5ZAS3t3rAbjWXp6thbsGBBugk+bvSeXbp0SVFRUapevbq+/fZb5cp1+7+OZfZnZocOHTR06FDNmjVLHTp00K5du7Rx40Z99tlnVn9XX9sHHniASaCALEQwA3KwIkWKKDY2VgsWLNC8efM0b948TZgwQR06dNCkSZNue7vu7u4utaf9Mrhv3z5FRESofPny+vjjjxUYGCgPDw/99NNPGj58eLrJOzKSmpqqJ598Uq+88kqGyx966KFMHkXm3OqY7id58uTRxYsXM1yW9gthnjx5MrWt2/3s3Sj4paSkpGvr1auXmjVrptmzZ2vBggV68803NWTIEC1dulQPP/yw9Xn66quvrLB2rTv5ZdkVmQ2zmb33KO24Pvjggxt+kXXaHyR69uypCRMmqFevXgoLC7O+iLxNmzaZGm8ZudMxcav1U1NT5XA4NG/evAz7ZuZeyty5c6tmzZpauXKl9u7dq/j4eIWHh6to0aJKTk7WunXrtGrVKpUvX/6OvtLhRu+Zp6enmjRpojlz5mj+/Pk3/H7AW3HlZ2ZISIiqV6+u//73v+rQoYP++9//ysPDQ61bt7b6uPraMisokLUIZkAO5+HhoWbNmqlZs2ZKTU3VCy+8oM8//1xvvvmmypYtm+lfGrPCDz/8oKSkJH3//fdOfzXP6NKkG9UVHBysc+fOqUGDBjfdV1BQkJYsWaJz5845/bKxa9eu26z+xvtJ2+61lx5evnxZ+/fvv2Wd1ytcuLDy5cuXYZ07d+6Um5tbujOTWSUoKEg7duzIcFlaPWnHmxm3+uxlJO3syfUzWt7ozGNwcLD69u2rvn37as+ePQoNDdVHH32k//73vwoODpZ0NSTe7H1IO6a0M1HXupPPS1BQkFJTU7Vnzx6nCXWOHTumhIQEl17La6Udl6+v7y0/X9OnT1d0dLQ++ugjq+3SpUvpXt/g4GBt27btturJasHBwTLGqHTp0rf8Q8vNfn6Fh4dr6NChWrx4sQoVKqTy5cvL4XCoYsWKWrVqlVatWuUUmK4dy9fbuXOnChUqlOnp8B0Oh6ZMmaLmzZvr6aef1rx585xmls0sV35mSlfPmvXp00dHjx7V1KlTFRUVZY0pybXXFkDW4x4zIAc7efKk03M3NzdVqVJFkqzputN+0biTqd0zK+0vtNdfTjVhwoR0fb28vDKsqXXr1lq7dq0WLFiQbllCQoJ1P1uTJk105coVp2mlU1JSNGrUqDs9DCcNGjSQh4eHRo4c6XRc48aNU2JiojX7myQdPHhQO3fuvOn23N3d1bBhQ82ZM8dpSvNjx45p6tSpqlOnjnUJXlZr0qSJDh8+rNmzZzu1JyUlWTPnVatWLVPbysxnLyNBQUFyd3d3mlFPuvp1BNe6cOGCLl265NQWHBwsHx8fa/uRkZHy9fXVe++9l+E04mlfe1CsWDGFhoZq0qRJTpf3LVq06IZBNTOaNGkiSdZMoWk+/vhjSXL6bLiievXqCg4O1ocffpjh1OvXfp2Du7t7ujNZo0aNSncGslWrVvrtt98y/IqAe312uGXLlnJ3d9egQYPS7dsY4/TZ8vLyuuG9qeHh4UpKStKIESNUp04dK8SFh4frq6++0pEjR6z7yyTnz8G1P3u2bdumhQsXWu9nZnl4eGjmzJl65JFH1KxZM61fv96l9SXXfmZKUtu2beVwOPTSSy/p999/T/e9gq68tgCyHmfMgPvYvHnzMvxF/7HHHlOZMmX0r3/9S6dOndITTzyhEiVK6I8//tCoUaMUGhpq/QU/NDRU7u7uGjp0qBITE+Xp6Wl9Z05Wa9iwoXUW5fnnn9e5c+f0xRdfqEiRIjp69KhT3+rVq2vs2LF65513VLZsWRUpUkRPPPGE+vXrp++//15NmzZVx44dVb16dZ0/f15bt27V9OnTdeDAARUqVEjNmjVT7dq19dprr+nAgQMKCQnRzJkzMzXBiCsKFy6s/v37a9CgQWrUqJGeeuop7dq1S2PGjNEjjzzi9ItRhw4dtGLFilv+ovvOO+9o0aJFqlOnjl544QXlypVLn3/+uZKSkjRs2LA7qnfJkiXpAo0ktWjRQt26ddP48eP19NNPq3Pnznr44Yd18uRJffPNN9q2bZsmT56c6ftNMvPZy4ifn5+efvppjRo1Sg6HQ8HBwZo7d65172Ca3bt3KyIiQq1bt1ZISIhy5cqlWbNm6dixY2rTpo2kq2eUxo4dq/bt26tatWpq06aNChcurIMHD+rHH39U7dq19emnn0q6+hUQUVFRqlOnjjp37qxTp05p1KhRqlixosvfO5WmatWqio6O1v/93/8pISFB9erV0/r16zVp0iS1aNFCjz/++G1t183NTV9++aUaN26sihUrqlOnTnrggQf0559/atmyZfL19dUPP/wgSWratKm++uor+fn5KSQkRGvXrtXixYutez7T9OvXT9OnT7fe++rVq+vUqVP6/vvv9dlnn6lq1aq3VevtCA4O1jvvvKP+/fvrwIEDatGihXx8fLR//37NmjVL3bp108svvyzp6s+Jb775Rn369NEjjzwib29vNWvWTJIUFhamXLlyadeuXerWrZu1/bp161p/sLk2mElXLw9t3LixwsLC1KVLF2u6fD8/Pw0cONDlY8mbN6/mzp2rJ554Qo0bN9aKFStUqVKlTK/vys9M6erPo0aNGum7776Tv79/uvDvymsL4C64t5NAArgXbjZdvq6ZUnz69OmmYcOGpkiRIsbDw8OULFnSPP/88+bo0aNO2/viiy9MmTJljLu7u9NU5TeaLv+7777LsJ4NGzY4tadN/XzixAmr7fvvvzdVqlQxefLkMaVKlTJDhw4148ePN5LM/v37rX7x8fEmKirK+Pj4GElOdZw9e9b079/flC1b1nh4eJhChQqZxx57zHz44YdO0/ifPHnStG/f3vj6+ho/Pz/Tvn17s3nzZpemy7/+mG40nfunn35qypcvb3Lnzm2KFi1qunfvbk6fPu3UJ2366czYtGmTiYyMNN7e3iZfvnzm8ccfN2vWrHHqczvT5d/o8dVXXxljrk5D37t3b1O6dGmTO3du4+vrax5//HEzb968m27/+mnLM/vZy8iJEydMq1atTL58+Uz+/PnN888/b7Zt2+b0vv31118mJibGlC9f3nh5eRk/Pz9Ts2ZN8+2336bb3rJly0xkZKTx8/MzefLkMcHBwaZjx47m119/deo3Y8YMU6FCBePp6WlCQkLMzJkzTXR09G1Pl2+MMcnJyWbQoEHW6xkYGGj69++fbur0m31VwY1s3rzZtGzZ0hQsWNB4enqaoKAg07p1a7NkyRKrz+nTp02nTp1MoUKFjLe3t4mMjDQ7d+40QUFBJjo62ml7J0+eND169DAPPPCA8fDwMCVKlDDR0dHmr7/+MsbcePxf/1UGN5LRzwNj/jfWrh3/xlx9P+rUqWO8vLyMl5eXKV++vImJiTG7du2y+pw7d848++yzxt/fP8OvNnjkkUeMJLNu3Tqr7fDhw0aSCQwMzLDOxYsXm9q1a5u8efMaX19f06xZM7Njx45MHYsxGX8W/vrrLxMSEmICAgLMnj17bvkaXSuzPzPTfPvtt0aS6dat2w33k5nXtl69eqZixYo33AYA1zmMuQ/vUAcAAEA6c+bMUYsWLbRy5cp0ZwQB2ItgBgAAkEM0bdpUcXFx2rt37z2d3AnArXGPGQAAwH1u2rRp2rJli3788Ud98sknhDIgG+KMGQAAwH3O4XDI29tbzzzzjD777LN79j19ADKPUQkAAHCf4+/wQPbH95gBAAAAgM0IZgAAAABgMy5llJSamqojR47Ix8eHm2EBAACAHMwYo7Nnz6p48eJyc7t357EIZpKOHDmiwMBAu8sAAAAAkE0cOnRIJUqUuGf7I5hJ8vHxkXT1xff19bW5GgAAAAB2OXPmjAIDA62McK8QzCTr8kVfX1+CGQAAAIB7fosTk38AAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANgsl90FAMDd5hjksLsEW5kBxu4ScB9iXDGukLUYU4wpglk2xMBkYAIAACBn4VJGAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwma3BbOzYsapSpYp8fX3l6+ursLAwzZs3z1p+6dIlxcTEqGDBgvL29larVq107Ngxp20cPHhQUVFRypcvn4oUKaJ+/frpypUr9/pQAAAAAOC22RrMSpQooffff18bN27Ur7/+qieeeELNmzfX9u3bJUm9e/fWDz/8oO+++04rVqzQkSNH1LJlS2v9lJQURUVF6fLly1qzZo0mTZqkiRMn6q233rLrkAAAAADAZQ5jjLG7iGsVKFBAH3zwgf75z3+qcOHCmjp1qv75z39Kknbu3KkKFSpo7dq1qlWrlubNm6emTZvqyJEjKlq0qCTps88+06uvvqoTJ07Iw8MjU/s8c+aM/Pz8lJiYKF9f37t2bJnlGOSwuwRbmQHZ6iOJ+wBjijGFrMe4YlwhazGmss+YsisbZJt7zFJSUjRt2jSdP39eYWFh2rhxo5KTk9WgQQOrT/ny5VWyZEmtXbtWkrR27VpVrlzZCmWSFBkZqTNnzlhn3TKSlJSkM2fOOD0AAAAAwC62B7OtW7fK29tbnp6e+ve//61Zs2YpJCRE8fHx8vDwkL+/v1P/okWLKj4+XpIUHx/vFMrSlqctu5EhQ4bIz8/PegQGBmbtQQEAAACAC2wPZuXKlVNsbKzWrVun7t27Kzo6Wjt27Lir++zfv78SExOtx6FDh+7q/gAAAADgZnLZXYCHh4fKli0rSapevbo2bNigTz75RM8884wuX76shIQEp7Nmx44dU0BAgCQpICBA69evd9pe2qyNaX0y4unpKU9Pzyw+EgAAAAC4PbafMbteamqqkpKSVL16deXOnVtLliyxlu3atUsHDx5UWFiYJCksLExbt27V8ePHrT6LFi2Sr6+vQkJC7nntAAAAAHA7bD1j1r9/fzVu3FglS5bU2bNnNXXqVC1fvlwLFiyQn5+funTpoj59+qhAgQLy9fVVz549FRYWplq1akmSGjZsqJCQELVv317Dhg1TfHy83njjDcXExHBGDAAAAMDfhq3B7Pjx4+rQoYOOHj0qPz8/ValSRQsWLNCTTz4pSRo+fLjc3NzUqlUrJSUlKTIyUmPGjLHWd3d319y5c9W9e3eFhYXJy8tL0dHRGjx4sF2HBAAAAAAuszWYjRs37qbL8+TJo9GjR2v06NE37BMUFKSffvopq0sDAAAAgHsm291jBgAAAAA5DcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbGZrMBsyZIgeeeQR+fj4qEiRImrRooV27drl1Kd+/fpyOBxOj3//+99OfQ4ePKioqCjly5dPRYoUUb9+/XTlypV7eSgAAAAAcNty2bnzFStWKCYmRo888oiuXLmi119/XQ0bNtSOHTvk5eVl9evatasGDx5sPc+XL5/175SUFEVFRSkgIEBr1qzR0aNH1aFDB+XOnVvvvffePT0eAAAAALgdtgaz+fPnOz2fOHGiihQpoo0bN6pu3bpWe758+RQQEJDhNhYuXKgdO3Zo8eLFKlq0qEJDQ/X222/r1Vdf1cCBA+Xh4XFXjwEAAAAA7lS2uscsMTFRklSgQAGn9ilTpqhQoUKqVKmS+vfvrwsXLljL1q5dq8qVK6to0aJWW2RkpM6cOaPt27dnuJ+kpCSdOXPG6QEAAAAAdrH1jNm1UlNT1atXL9WuXVuVKlWy2p999lkFBQWpePHi2rJli1599VXt2rVLM2fOlCTFx8c7hTJJ1vP4+PgM9zVkyBANGjToLh0JAAAAALgm2wSzmJgYbdu2TT///LNTe7du3ax/V65cWcWKFVNERIT27dun4ODg29pX//791adPH+v5mTNnFBgYeHuFAwAAAMAdyhaXMvbo0UNz587VsmXLVKJEiZv2rVmzpiRp7969kqSAgAAdO3bMqU/a8xvdl+bp6SlfX1+nBwAAAADYxdZgZoxRjx49NGvWLC1dulSlS5e+5TqxsbGSpGLFikmSwsLCtHXrVh0/ftzqs2jRIvn6+iokJOSu1A0AAAAAWcnWSxljYmI0depUzZkzRz4+PtY9YX5+fsqbN6/27dunqVOnqkmTJipYsKC2bNmi3r17q27duqpSpYokqWHDhgoJCVH79u01bNgwxcfH64033lBMTIw8PT3tPDwAAAAAyBRbz5iNHTtWiYmJql+/vooVK2Y9vvnmG0mSh4eHFi9erIYNG6p8+fLq27evWrVqpR9++MHahru7u+bOnSt3d3eFhYXpueeeU4cOHZy+9wwAAAAAsjNbz5gZY266PDAwUCtWrLjldoKCgvTTTz9lVVkAAAAAcE9li8k/AAAAACAnI5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzl4PZ/Pnz9fPPP1vPR48erdDQUD377LM6ffp0lhYHAAAAADmBy8GsX79+OnPmjCRp69at6tu3r5o0aaL9+/erT58+WV4gAAAAANzvcrm6wv79+xUSEiJJmjFjhpo2bar33ntPmzZtUpMmTbK8QAAAAAC437l8xszDw0MXLlyQJC1evFgNGzaUJBUoUMA6kwYAAAAAyLxMB7POnTvr7Nmzql27tvr06aO3335b69evV1RUlCRp9+7dKlGixF0rFAAAAADuV5kOZpMmTdLFixc1evRo5cqVS9OnT9fYsWP1wAMPSJLmzZunRo0a3bVCAQAAAOB+lel7zIwxkqSSJUtq7ty56ZYPHz4866oCAAAAgBzEpck/zp49qzx58ty0j6+v7x0VBAAAAAA5jUvB7KGHHrrhMmOMHA6HUlJS7rgoAAAAAMhJXApm06dPV4ECBe5WLQAAAACQI7kUzGrXrq0iRYrcrVoAAAAAIEdy+XvMAAAAAABZK9PBLCgoSO7u7lm68yFDhuiRRx6Rj4+PihQpohYtWmjXrl1OfS5duqSYmBgVLFhQ3t7eatWqlY4dO+bU5+DBg4qKilK+fPlUpEgR9evXT1euXMnSWgEAAADgbsl0MNu/f78KFiyYpTtfsWKFYmJi9Msvv2jRokVKTk5Ww4YNdf78eatP79699cMPP+i7777TihUrdOTIEbVs2dJanpKSoqioKF2+fFlr1qzRpEmTNHHiRL311ltZWisAAAAA3C2Zvscsf/78cjgc6dr9/Pz00EMP6eWXX9aTTz7p0s7nz5/v9HzixIkqUqSINm7cqLp16yoxMVHjxo3T1KlT9cQTT0iSJkyYoAoVKuiXX35RrVq1tHDhQu3YsUOLFy9W0aJFFRoaqrfffluvvvqqBg4cKA8Pj3T7TUpKUlJSkvX8zJkzLtUNAAAAAFkp08Fs+PDhGQazhIQEbdy4UU2bNtX06dPVrFmz2y4mMTFRkqyZHzdu3Kjk5GQ1aNDA6lO+fHmVLFlSa9euVa1atbR27VpVrlxZRYsWtfpERkaqe/fu2r59ux5++OF0+xkyZIgGDRp023UCAAAAQFbKdDDr2LHjTZeHhoZqyJAhtx3MUlNT1atXL9WuXVuVKlWSJMXHx8vDw0P+/v5OfYsWLar4+Hirz7WhLG152rKM9O/fX3369LGenzlzRoGBgbdVNwAAAADcqSyblbFp06bauXPnba8fExOjbdu2adq0aVlV0g15enrK19fX6QEAAAAAdsmyYJaUlJTh/VyZ0aNHD82dO1fLli1TiRIlrPaAgABdvnxZCQkJTv2PHTumgIAAq8/1szSmPU/rAwAAAADZWZYFs3Hjxik0NNSldYwx6tGjh2bNmqWlS5eqdOnSTsurV6+u3Llza8mSJVbbrl27dPDgQYWFhUmSwsLCtHXrVh0/ftzqs2jRIvn6+iokJOT2DwgAAAAA7pFM32N27T1Z10pMTNSmTZu0e/durVy50qWdx8TEaOrUqZozZ458fHyse8L8/PyUN29e+fn5qUuXLurTp48KFCggX19f9ezZU2FhYapVq5YkqWHDhgoJCVH79u01bNgwxcfH64033lBMTIw8PT1dqgcAAAAA7JDpYLZ58+YM2319ffXkk09q5syZ6c543crYsWMlSfXr13dqnzBhgjXZyPDhw+Xm5qZWrVopKSlJkZGRGjNmjNXX3d1dc+fOVffu3RUWFiYvLy9FR0dr8ODBLtUCAAAAAHbJdDBbtmzZTZcfPnxY3bp10//93/9leufGmFv2yZMnj0aPHq3Ro0ffsE9QUJB++umnTO8XAAAAALKTLLvH7OTJkxo3blxWbQ4AAAAAcowsC2YAAAAAgNtDMAMAAAAAmxHMAAAAAMBmmZ78o2XLljddfv2XQAMAAAAAMifTwczPz++Wyzt06HDHBQEAAABATpPpYDZhwoS7WQcAAAAA5FjcYwYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYLFPBrFq1ajp9+rQkafDgwbpw4cJdLQoAAAAAcpJMBbO4uDidP39ekjRo0CCdO3furhYFAAAAADlJpqbLDw0NVadOnVSnTh0ZY/Thhx/K29s7w75vvfVWlhYIAAAAAPe7TAWziRMnasCAAZo7d64cDofmzZunXLnSr+pwOAhmAAAAAOCiTAWzcuXKadq0aZIkNzc3LVmyREWKFLmrhQEAAABATpGpYHat1NTUu1EHAAAAAORYLgczSdq3b59GjBihuLg4SVJISIheeuklBQcHZ2lxAAAAAJATuPw9ZgsWLFBISIjWr1+vKlWqqEqVKlq3bp0qVqyoRYsW3Y0aAQAAAOC+5vIZs9dee029e/fW+++/n6791Vdf1ZNPPpllxQEAAABATuDyGbO4uDh16dIlXXvnzp21Y8eOLCkKAAAAAHISl4NZ4cKFFRsbm649NjaWmRoBAAAA4Da4fClj165d1a1bN/3+++967LHHJEmrV6/W0KFD1adPnywvEAAAAADudy4HszfffFM+Pj766KOP1L9/f0lS8eLFNXDgQL344otZXiAAAAAA3O9cDmYOh0O9e/dW7969dfbsWUmSj49PlhcGAAAAADnFbX2PWRoCGQAAAADcOZcn/wAAAAAAZC2CGQAAAADYjGAGAAAAADZzKZglJycrIiJCe/bsuVv1AAAAAECO41Iwy507t7Zs2XK3agEAAACAHMnlSxmfe+45jRs37m7UAgAAAAA5ksvT5V+5ckXjx4/X4sWLVb16dXl5eTkt//jjj7OsOAAAAADICVwOZtu2bVO1atUkSbt373Za5nA4sqYqAAAAAMhBXA5my5Ytuxt1AAAAAECOddvT5e/du1cLFizQxYsXJUnGmCwrCgAAAAByEpeD2cmTJxUREaGHHnpITZo00dGjRyVJXbp0Ud++fbO8QAAAAAC437kczHr37q3cuXPr4MGDypcvn9X+zDPPaP78+VlaHAAAAADkBC7fY7Zw4UItWLBAJUqUcGp/8MEH9ccff2RZYQAAAACQU7h8xuz8+fNOZ8rSnDp1Sp6enllSFAAAAADkJC4Hs/DwcE2ePNl67nA4lJqaqmHDhunxxx/P0uIAAAAAICdw+VLGYcOGKSIiQr/++qsuX76sV155Rdu3b9epU6e0evXqu1EjAAAAANzXXD5jVqlSJe3evVt16tRR8+bNdf78ebVs2VKbN29WcHDw3agRAAAAAO5rLp8xkyQ/Pz/95z//yepaAAAAACBHuq1gdvr0aY0bN05xcXGSpJCQEHXq1EkFChTI0uIAAAAAICdw+VLGlStXqlSpUho5cqROnz6t06dPa+TIkSpdurRWrlx5N2oEAAAAgPuay8EsJiZGzzzzjPbv36+ZM2dq5syZ+v3339WmTRvFxMS4tK2VK1eqWbNmKl68uBwOh2bPnu20vGPHjnI4HE6PRo0aOfU5deqU2rVrJ19fX/n7+6tLly46d+6cq4cFAAAAALZxOZjt3btXffv2lbu7u9Xm7u6uPn36aO/evS5t6/z586patapGjx59wz6NGjXS0aNHrcfXX3/ttLxdu3bavn27Fi1apLlz52rlypXq1q2bawcFAAAAADZy+R6zatWqKS4uTuXKlXNqj4uLU9WqVV3aVuPGjdW4ceOb9vH09FRAQECGy+Li4jR//nxt2LBBNWrUkCSNGjVKTZo00YcffqjixYu7VA8AAAAA2CFTwWzLli3Wv1988UW99NJL2rt3r2rVqiVJ+uWXXzR69Gi9//77WV7g8uXLVaRIEeXPn19PPPGE3nnnHRUsWFCStHbtWvn7+1uhTJIaNGggNzc3rVu3Tv/4xz8y3GZSUpKSkpKs52fOnMnyugEAAAAgszIVzEJDQ+VwOGSMsdpeeeWVdP2effZZPfPMM1lWXKNGjdSyZUuVLl1a+/bt0+uvv67GjRtr7dq1cnd3V3x8vIoUKeK0Tq5cuVSgQAHFx8ffcLtDhgzRoEGDsqxOAAAAALgTmQpm+/fvv9t1ZKhNmzbWvytXrqwqVaooODhYy5cvV0RExG1vt3///urTp4/1/MyZMwoMDLyjWgEAAADgdmUqmAUFBd3tOjKlTJkyKlSokPbu3auIiAgFBATo+PHjTn2uXLmiU6dO3fC+NOnqfWuenp53u1wAAAAAyJTb+oLpI0eO6Oeff9bx48eVmprqtOzFF1/MksIycvjwYZ08eVLFihWTJIWFhSkhIUEbN25U9erVJUlLly5VamqqatasedfqAAAAAICs5HIwmzhxop5//nl5eHioYMGCcjgc1jKHw+FSMDt37pzTFPv79+9XbGysChQooAIFCmjQoEFq1aqVAgICtG/fPr3yyisqW7asIiMjJUkVKlRQo0aN1LVrV3322WdKTk5Wjx491KZNG2ZkBAAAAPC34XIwe/PNN/XWW2+pf//+cnNz+WvQnPz66696/PHHredp931FR0dr7Nix2rJliyZNmqSEhAQVL15cDRs21Ntvv+10GeKUKVPUo0cPRUREyM3NTa1atdLIkSPvqC4AAAAAuJdcDmYXLlxQmzZt7jiUSVL9+vWdZnq83oIFC265jQIFCmjq1Kl3XAsAAAAA2MXldNWlSxd99913d6MWAAAAAMiRXD5jNmTIEDVt2lTz589X5cqVlTt3bqflH3/8cZYVBwAAAAA5wW0FswULFqhcuXKSlG7yDwAAAACAa1wOZh999JHGjx+vjh073oVyAAAAACDncfkeM09PT9WuXftu1AIAAAAAOZLLweyll17SqFGj7kYtAAAAAJAjuXwp4/r167V06VLNnTtXFStWTDf5x8yZM7OsOAAAAADICVwOZv7+/mrZsuXdqAUAAAAAciSXg9mECRPuRh0AAAAAkGO5fI8ZAAAAACBruXzGrHTp0jf9vrLff//9jgoCAAAAgJzG5WDWq1cvp+fJycnavHmz5s+fr379+mVVXQAAAACQY7gczF566aUM20ePHq1ff/31jgsCAAAAgJwmy+4xa9y4sWbMmJFVmwMAAACAHCPLgtn06dNVoECBrNocAAAAAOQYLl/K+PDDDztN/mGMUXx8vE6cOKExY8ZkaXEAAAAAkBO4HMxatGjh9NzNzU2FCxdW/fr1Vb58+ayqCwAAAAByDJeD2YABA+5GHQAAAACQY/EF0wAAAABgs0yfMXNzc7vpF0tLksPh0JUrV+64KAAAAADISTIdzGbNmnXDZWvXrtXIkSOVmpqaJUUBAAAAQE6S6WDWvHnzdG27du3Sa6+9ph9++EHt2rXT4MGDs7Q4AAAAAMgJbusesyNHjqhr166qXLmyrly5otjYWE2aNElBQUFZXR8AAAAA3PdcCmaJiYl69dVXVbZsWW3fvl1LlizRDz/8oEqVKt2t+gAAAADgvpfpSxmHDRumoUOHKiAgQF9//XWGlzYCAAAAAFyX6WD22muvKW/evCpbtqwmTZqkSZMmZdhv5syZWVYcAAAAAOQEmQ5mHTp0uOV0+QAAAAAA12U6mE2cOPEulgEAAAAAOddtzcoIAAAAAMg6BDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALCZrcFs5cqVatasmYoXLy6Hw6HZs2c7LTfG6K233lKxYsWUN29eNWjQQHv27HHqc+rUKbVr106+vr7y9/dXly5ddO7cuXt4FAAAAABwZ2wNZufPn1fVqlU1evToDJcPGzZMI0eO1GeffaZ169bJy8tLkZGRunTpktWnXbt22r59uxYtWqS5c+dq5cqV6tat2706BAAAAAC4Y7ns3Hnjxo3VuHHjDJcZYzRixAi98cYbat68uSRp8uTJKlq0qGbPnq02bdooLi5O8+fP14YNG1SjRg1J0qhRo9SkSRN9+OGHKl68+D07FgAAAAC4Xdn2HrP9+/crPj5eDRo0sNr8/PxUs2ZNrV27VpK0du1a+fv7W6FMkho0aCA3NzetW7fuhttOSkrSmTNnnB4AAAAAYJdsG8zi4+MlSUWLFnVqL1q0qLUsPj5eRYoUcVqeK1cuFShQwOqTkSFDhsjPz896BAYGZnH1AAAAAJB52TaY3U39+/dXYmKi9Th06JDdJQEAAADIwbJtMAsICJAkHTt2zKn92LFj1rKAgAAdP37cafmVK1d06tQpq09GPD095evr6/QAAAAAALtk22BWunRpBQQEaMmSJVbbmTNntG7dOoWFhUmSwsLClJCQoI0bN1p9li5dqtTUVNWsWfOe1wwAAAAAt8PWWRnPnTunvXv3Ws/379+v2NhYFShQQCVLllSvXr30zjvv6MEHH1Tp0qX15ptvqnjx4mrRooUkqUKFCmrUqJG6du2qzz77TMnJyerRo4fatGnDjIwAAAAA/jZsDWa//vqrHn/8cet5nz59JEnR0dGaOHGiXnnlFZ0/f17dunVTQkKC6tSpo/nz5ytPnjzWOlOmTFGPHj0UEREhNzc3tWrVSiNHjrznxwIAAAAAt8vWYFa/fn0ZY2643OFwaPDgwRo8ePAN+xQoUEBTp069G+UBAAAAwD2Rbe8xAwAAAICcgmAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNsnUwGzhwoBwOh9OjfPny1vJLly4pJiZGBQsWlLe3t1q1aqVjx47ZWDEAAAAAuC5bBzNJqlixoo4ePWo9fv75Z2tZ79699cMPP+i7777TihUrdOTIEbVs2dLGagEAAADAdbnsLuBWcuXKpYCAgHTtiYmJGjdunKZOnaonnnhCkjRhwgRVqFBBv/zyi2rVqnXDbSYlJSkpKcl6fubMmawvHAAAAAAyKdufMduzZ4+KFy+uMmXKqF27djp48KAkaePGjUpOTlaDBg2svuXLl1fJkiW1du3am25zyJAh8vPzsx6BgYF39RgAAAAA4GaydTCrWbOmJk6cqPnz52vs2LHav3+/wsPDdfbsWcXHx8vDw0P+/v5O6xQtWlTx8fE33W7//v2VmJhoPQ4dOnQXjwIAAAAAbi5bX8rYuHFj699VqlRRzZo1FRQUpG+//VZ58+a97e16enrK09MzK0oEAAAAgDuWrc+YXc/f318PPfSQ9u7dq4CAAF2+fFkJCQlOfY4dO5bhPWkAAAAAkF39rYLZuXPntG/fPhUrVkzVq1dX7ty5tWTJEmv5rl27dPDgQYWFhdlYJQAAAAC4Jltfyvjyyy+rWbNmCgoK0pEjRzRgwAC5u7urbdu28vPzU5cuXdSnTx8VKFBAvr6+6tmzp8LCwm46IyMAAAAAZDfZOpgdPnxYbdu21cmTJ1W4cGHVqVNHv/zyiwoXLixJGj58uNzc3NSqVSslJSUpMjJSY8aMsblqAAAAAHBNtg5m06ZNu+nyPHnyaPTo0Ro9evQ9qggAAAAAst7f6h4zAAAAALgfEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZvdNMBs9erRKlSqlPHnyqGbNmlq/fr3dJQEAAABAptwXweybb75Rnz59NGDAAG3atElVq1ZVZGSkjh8/bndpAAAAAHBL90Uw+/jjj9W1a1d16tRJISEh+uyzz5QvXz6NHz/e7tIAAAAA4JZy2V3Anbp8+bI2btyo/v37W21ubm5q0KCB1q5dm+E6SUlJSkpKsp4nJiZKks6cOXN3i82sS3YXYK9s8z7g/sGYsrsE3I8YV3aXgPsNY8ruEixptRhj7ul+//bB7K+//lJKSoqKFi3q1F60aFHt3Lkzw3WGDBmiQYMGpWsPDAy8KzXCNX7v+9ldAnBfYUwBWY9xBWSt7Dimzp49Kz+/e1fX3z6Y3Y7+/furT58+1vPU1FSdOnVKBQsWlMPhsLEy+505c0aBgYE6dOiQfH197S4H+NtjTAFZj3EFZC3GlDNjjM6ePavixYvf0/3+7YNZoUKF5O7urmPHjjm1Hzt2TAEBARmu4+npKU9PT6c2f3//u1Xi35Kvry8DE8hCjCkg6zGugKzFmPqfe3mmLM3ffvIPDw8PVa9eXUuWLLHaUlNTtWTJEoWFhdlYGQAAAABkzt/+jJkk9enTR9HR0apRo4YeffRRjRgxQufPn1enTp3sLg0AAAAAbum+CGbPPPOMTpw4obfeekvx8fEKDQ3V/Pnz000Iglvz9PTUgAED0l3qCeD2MKaArMe4ArIWYyp7cJh7PQ8kAAAAAMDJ3/4eMwAAAAD4uyOYAQAAAIDNCGYAAAAAYDOC2W0qVaqURowYYXcZfzsHDhyQw+FQbGzsXd8X79HfD+/Z7WFc4UZ4v24PYwo3w3t2exhXmWD+xqKjo40k8/zzz6db9sILLxhJJjo6OlPb2r9/v5FkNm/enKn+x48fN+fPn89U36ZNm5rIyMgMl61cudJIMr/99lumtnUjy5YtM5LM6dOn72g717tw4YLJnz+/KViwoLl06ZJL60ZHR5vmzZs7tV25csUcPXrUJCcnZ1mNEyZMMH5+funaXXmPssqnn35qgoKCjKenp3n00UfNunXr7un+swLj6n8YV37p2u/1uFqxYoVp2rSpKVasmJFkZs2adc/2nVUYU//DmPJL136vx9R7771natSoYby9vU3hwoVN8+bNzc6dO+/Z/rMK4+p/GFd+6drv9bgaM2aMqVy5svHx8TE+Pj6mVq1a5qeffnJ5O3/7M2aBgYGaNm2aLl68aLVdunRJU6dOVcmSJbN8f5cvX5YkFS5cWPny5cvUOl26dNGiRYt0+PDhdMsmTJigGjVqqEqVKlla5+0yxujKlSvW8xkzZqhixYoqX768Zs+efcfbd3d3V0BAgHLluvvf1ODKe5QVvvnmG/Xp00cDBgzQpk2bVLVqVUVGRur48eP3rIaswrjKWoyr23f+/HlVrVpVo0ePvmf7vBsYU1mLMXX7VqxYoZiYGP3yyy9atGiRkpOT1bBhQ50/f/6e1ZBVGFdZi3F1+0qUKKH3339fGzdu1K+//qonnnhCzZs31/bt213bUBYHxnsqLY1XqlTJ/Pe//7Xap0yZYqpUqWKaN29u/bVk3rx5pnbt2sbPz88UKFDAREVFmb1791rrSHJ61KtXz2kf77zzjilWrJgpVaqUMcaYoKAgM3z4cGPM1b9U5M6d26xcudLa3tChQ03hwoVNfHy8SU5ONkWLFjVvv/22U/1nz5413t7eZuzYscYYY1atWmXq1Klj8uTJY0qUKGF69uxpzp07Z/W/dOmSeeWVV0yJEiWMh4eHCQ4ONl9++aX1l55rH2nHfenSJdOzZ09TuHBh4+npaWrXrm3Wr19vbTPtryw//fSTqVatmsmdO7dZtmyZtbx+/frms88+M2PHjjVPPvlkuvdg27ZtJioqyvj4+Bhvb29Tp04ds3fvXjNgwIB0NS1btszpr1IpKSnmgQceMGPGjHHa5qZNm4zD4TAHDhwwxhjz0UcfmUqVKpl8+fKZEiVKmO7du5uzZ8861X/tY8CAAeneI2OM+eOPP8xTTz1lvLy8jI+Pj3n66adNfHy8tXzAgAGmatWqZvLkySYoKMj4+vqaZ555xpw5cybdcWfk0UcfNTExMdbzlJQUU7x4cTNkyJBMrZ9dMK4YV9lpXF1Lf+MzZowpxlR2HFPGXD2zIMmsWLHitta3C+OKcZWdx5UxxuTPn998+eWXLq1zXwSzjz/+2ERERFjtERERZvjw4U6Dcvr06WbGjBlmz549ZvPmzaZZs2amcuXKJiUlxRhjzPr1640ks3jxYnP06FFz8uRJax/e3t6mffv2Ztu2bWbbtm3GmPRveL9+/UxQUJBJSEgwmzZtMh4eHmbOnDlOy4ODg01qaqrVNn78eJM3b16TkJBg9u7da7y8vMzw4cPN7t27zerVq83DDz9sOnbsaPVv3bq1CQwMNDNnzjT79u0zixcvNtOmTTNXrlwxM2bMMJLMrl27zNGjR01CQoIxxpgXX3zRFC9e3Pz0009m+/btJjo62uTPn986vrQPdZUqVczChQvN3r17rWV79+41np6e5tSpU+bkyZMmT5481kAxxpjDhw+bAgUKmJYtW5oNGzaYXbt2mfHjx5udO3eas2fPmtatW5tGjRqZo0ePmqNHj5qkpKR0lwu8/PLLpk6dOk7va9++fZ3ahg8fbpYuXWr2799vlixZYsqVK2e6d+9ujDEmKSnJjBgxwvj6+lr7SRuw175HKSkpJjQ01NSpU8f8+uuv5pdffjHVq1e3fvgac3VQent7m5YtW5qtW7ealStXmoCAAPP666/f8DOYJikpybi7u6f7pbFDhw7mqaeeuuX62QnjinGVXcbV9f7uwYwxxZjKbmPKGGP27NljJJmtW7fe1vp2YVwxrrLruLpy5Yr5+uuvjYeHh9m+fbtL694Xwez48ePG09PTHDhwwBw4cMDkyZPHnDhxwmlQXu/EiRNOP4hudH1xdHS0KVq0qElKSnJqv35QJiUlmdDQUNO6dWsTEhJiunbt6tQ/Li7O+otBmvDwcPPcc88ZY4zp0qWL6datm9M6q1atMm5ububixYtm165dRpJZtGhRhseT0fXF586dM7lz5zZTpkyx2i5fvmyKFy9uhg0b5rTe7Nmz023z9ddfNy1atLCeN2/e3PpLhDHG9O/f35QuXdpcvnw5w5oyur74+td58+bNxuFwmD/++MMYY6y/oKT9BSkj3333nSlYsKD1/EbXF1/7Hi1cuNC4u7ubgwcPWsu3b99uJFl/PRowYIDJly+f019H+vXrZ2rWrHnDWtL8+eefRpJZs2aNU3u/fv3Mo48+esv1sxPG1f8wrvzS9buX4+p6f/dgxphiTGW3MZWSkmKioqJM7dq1XV7Xboyr/2Fc+aXrZ8e42rJli/Hy8jLu7u7Gz8/P/Pjjj5leN83f/h4z6ep1pFFRUZo4caImTJigqKgoFSpUyKnPnj171LZtW5UpU0a+vr4qVaqUJOngwYO33H7lypXl4eFx0z4eHh6aMmWKZsyYoUuXLmn48OFOy8uXL6/HHntM48ePlyTt3btXq1atUpcuXSRJv/32myZOnChvb2/rERkZqdTUVO3fv1+xsbFyd3dXvXr1MvuyaN++fUpOTlbt2rWttty5c+vRRx9VXFycU98aNWo4PU9JSdGkSZP03HPPWW3PPfecJk6cqNTUVElSbGyswsPDlTt37kzXdL3Q0FBVqFBBU6dOlXT12vfjx4/r6aeftvosXrxYEREReuCBB+Tj46P27dvr5MmTunDhQqb3ExcXp8DAQAUGBlptISEh8vf3d3otSpUqJR8fH+t5sWLF/pb3iGUFxlXGGFf/w7hyDWMqY4yp/7nXYyomJkbbtm3TtGnTXF43u2BcZYxx9T/3alyVK1dOsbGxWrdunbp3767o6Gjt2LEj0+tL99F0+Z07d9bEiRM1adIkde7cOd3yZs2a6dSpU/riiy+0bt06rVu3TtL/buS8GS8vr0zVsGbNGknSqVOndOrUqXTLu3TpohkzZujs2bOaMGGCgoODrUF27tw5Pf/884qNjbUev/32m/bs2aPg4GDlzZs3UzXcruuPccGCBfrzzz/1zDPPKFeuXMqVK5fatGmjP/74Q0uWLJGkLKupXbt21qCcOnWqGjVqpIIFC0q6OrVq06ZNVaVKFc2YMUMbN260JgHIzHvnqut/wDgcDuuH0M0UKlRI7u7uOnbsmFP7sWPHFBAQkKU13kuMqzvDuLrqdsfV/YgxdWcYU1dlxZjq0aOH5s6dq2XLlqlEiRJZWd49x7i6M4yrq+50XHl4eKhs2bKqXr26hgwZoqpVq+qTTz5xqYb7Jpg1atRIly9fVnJysiIjI52WnTx5Urt27dIbb7yhiIgIVahQQadPn3bqk/bXkJSUlNva/759+9S7d2998cUXqlmzpqKjo9O9ma1bt5abm5umTp2qyZMnq3PnznI4HJKkatWqaceOHSpbtmy6h4eHhypXrqzU1FStWLEiw/1nVH9wcLA8PDy0evVqqy05OVkbNmxQSEjITY9n3LhxatOmjdMPidjYWLVp00bjxo2TJFWpUkWrVq1ScnLyDWvKzOv57LPPatu2bdq4caOmT5+udu3aWcs2btyo1NRUffTRR6pVq5YeeughHTlyxOX9VKhQQYcOHdKhQ4esth07dighIeGWr0VmeHh4qHr16tYPLElKTU3VkiVLFBYWdsfbtwvjinF1M3d7XN2PGFOMqZu5F2PKGKMePXpo1qxZWrp0qUqXLp0l27UT44pxdTN2/b8qNTVVSUlJrq3k8sWP2cj1168mJiaaxMRE63na9cUpKSmmYMGC5rnnnjN79uwxS5YsMY888ojT/QrJyckmb9685p133jHx8fHWjZMZXSNrjPO1q1euXDG1atUyrVq1MsYYc+TIEVOwYEHrGt5rdenSxeTPn9+4u7ubP//802r/7bffTN68eU1MTIzZvHmz2b17t5k9e7bTLH8dO3Y0gYGBZtasWeb33383y5YtM998840x5upNmA6Hw0ycONEcP37cuvnxpZdeMsWLFzfz5s1zuvHz1KlTxpiMr0s+fvy4yZ07t5k3b166+n/66Sfj6elpTp48af766y9TsGBB68bP3bt3m8mTJ1vfh/Luu++akiVLmp07d5oTJ06Yy5cv3/A67tq1a5uqVasaHx8fc+HCBas9NjbWSDIjRoww+/btM5MnTzYPPPCAU82rV6+2bto9ceKE9b0V175HqampJjQ01ISHh5uNGzeadevWZXjjZ9WqVZ3qGj58uAkKCkr3OmRk2rRpxtPT00ycONHs2LHDdOvWzfj7+zvN+vN3wLhiXBmTfcbV2bNnzebNm83mzZuNJPPxxx+bzZs3W/ck/B0wphhTxmSfMdW9e3fj5+dnli9fbk2YcPToUafj+TtgXDGujMk+4+q1114zK1asMPv37zdbtmwxr732mnE4HGbhwoWZWj/NfRXMrnftjZ+LFi0yFSpUMJ6enqZKlSpm+fLl6W4k/+KLL0xgYKBxc3NLN1Xq9a59wwcNGmSKFStm/vrrL2v5jBkzjIeHh4mNjXVab82aNUaSadKkSbptrl+/3jz55JPG29vbeHl5mSpVqph3333XWn7x4kXTu3dvU6xYMePh4WHKli1rxo8fby0fPHiwCQgIMA6Hwzruixcvmp49e5pChQrddKrUawflhx9+aPz9/TO8oTMpKcn4+/ubTz75xBhz9YdJw4YNTb58+YyPj48JDw83+/btM8ZcHdxpx6MMpkq91pgxY4wk06FDh3T7/Pjjj02xYsVM3rx5TWRkpJk8eXK6mv/973+bggULZslUqddyZVAaY8yoUaNMyZIljYeHh3n00UfNL7/8kul1swvGFeMqTXYYVxlNhyxl/otjswPGFGMqTXYYUxmNJ0lmwoQJmVo/u2BcMa7SZIdx1blzZxMUFGQ8PDxM4cKFTUREhMuhzBhjHMYY49o5NgAAAABAVrpv7jEDAAAAgL8rghmQCQcPHnSaxvb6R2am3AXgjHEFZC3GFJD17uW44lJGIBOuXLmiAwcO3HB5qVKllCtXrntXEHAfYFwBWYsxBWS9ezmuCGYAAAAAYDMuZQQAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAEBS/fr11atXr0z3X758uRwOhxISEu5aTQCAnINgBgC4Ix07dpTD4dD777/v1D579mw5HA6XtlWqVCmNGDEiC6sDAODvgWAGALhjefLk0dChQ3X69Gm7S3HZ5cuX7S7hjiQnJ9tdAgAgCxDMAAB3rEGDBgoICNCQIUNu2u/nn39WeHi48ubNq8DAQL344os6f/68pKuXEv7xxx/q3bu3HA6HHA6HjDEqXLiwpk+fbm0jNDRUxYoVc9qmp6enLly4IEk6ePCgmjdvLm9vb/n6+qp169Y6duyY1X/gwIEKDQ3Vl19+qdKlSytPnjwZ1vrjjz/Kz89PU6ZMydRrcPLkSbVt21YPPPCA8uXLp8qVK+vrr7+2lk+ePFkFCxZUUlKS03otWrRQ+/btredz5sxRtWrVlCdPHpUpU0aDBg3SlStXrOUOh0Njx47VU089JS8vL7377rs6ffq02rVrp8KFCytv3rx68MEHNWHChEzVDQDIHghmAIA75u7urvfee0+jRo3S4cOHM+yzb98+NWrUSK1atdKWLVv0zTff6Oeff1aPHj0kSTNnzlSJEiU0ePBgHT16VEePHpXD4VDdunW1fPlySdLp06cVFxenixcvaufOnZKkFStW6JFHHlG+fPmUmpqq5s2b69SpU1qxYoUWLVqk33//Xc8884xTLXv37tWMGTM0c+ZMxcbGpqt16tSpatu2raZMmaJ27dpl6jW4dOmSqlevrh9//FHbtm1Tt27d1L59e61fv16S9PTTTyslJUXff/+9tc7x48f1448/qnPnzpKkVatWqUOHDnrppZe0Y8cOff7555o4caLeffddp30NHDhQ//jHP7R161Z17txZb775pnbs2KF58+YpLi5OY8eOVaFChTJVNwAgmzAAANyB6Oho07x5c2OMMbVq1TKdO3c2xhgza9Ysc+3/Zrp06WK6devmtO6qVauMm5ubuXjxojHGmKCgIDN8+HCnPiNHjjQVK1Y0xhgze/ZsU7NmTdO8eXMzduxYY4wxDRo0MK+//roxxpiFCxcad3d3c/DgQWv97du3G0lm/fr1xhhjBgwYYHLnzm2OHz/utJ969eqZl156yXz66afGz8/PLF++/KbHvWzZMiPJnD59+oZ9oqKiTN++fa3n3bt3N40bN7aef/TRR6ZMmTImNTXVGGNMRESEee+995y28dVXX5lixYpZzyWZXr16OfVp1qyZ6dSp003rBQBkb5wxAwBkmaFDh2rSpEmKi4tLt+y3337TxIkT5e3tbT0iIyOVmpqq/fv333Cb9erV044dO3TixAmtWLFC9evXV/369bV8+XIlJydrzZo1ql+/viQpLi5OgYGBCgwMtNYPCQmRv7+/U01BQUEqXLhwun1Nnz5dvXv31qJFi1SvXj2Xjj0lJUVvv/22KleurAIFCsjb21sLFizQwYMHrT5du3bVwoUL9eeff0qSJk6caE2ekvYaDR482Ok16tq1q44ePWpdqilJNWrUcNp39+7dNW3aNIWGhuqVV17RmjVrXKodAGA/ghkAIMvUrVtXkZGR6t+/f7pl586d0/PPP6/Y2Fjr8dtvv2nPnj0KDg6+4TbTgs6KFSucgtmKFSu0YcMGJScn67HHHnOpTi8vrwzbH374YRUuXFjjx4+XMcalbX7wwQf65JNP9Oqrr2rZsmWKjY1VZGSk0+QiDz/8sKpWrarJkydr48aN2r59uzp27GgtP3funAYNGuT0Gm3dulV79uxxuhfu+vobN25s3Z935MgRRURE6OWXX3apfgCAvXLZXQAA4P7y/vvvKzQ0VOXKlXNqr1atmnbs2KGyZcvecF0PDw+lpKQ4tTkcDoWHh2vOnDnavn276tSpo3z58ikpKUmff/65atSoYQWVChUq6NChQzp06JB11mzHjh1KSEhQSEjILWsPDg7WRx99pPr168vd3V2ffvpppo979erVat68uZ577jlJUmpqqnbv3p1uv//61780YsQI/fnnn2rQoIHT2b1q1app165dN32NbqRw4cKKjo5WdHS0wsPD1a9fP3344YcubwcAYA/OmAEAslTlypXVrl07jRw50qn91Vdf1Zo1a9SjRw/FxsZqz549mjNnjjX5h3T1e8xWrlypP//8U3/99ZfVXr9+fX399dcKDQ2Vt7e33NzcVLduXU2ZMsXpksMGDRpY+9+0aZPWr1+vDh06qF69euku/7uRhx56SMuWLdOMGTNc+sLpBx98UIsWLdKaNWsUFxen559/3mk2yDTPPvusDh8+rC+++MKa9CPNW2+9pcmTJ2vQoEHavn274uLiNG3aNL3xxhs33fdbb72lOXPmaO/evdq+fbvmzp2rChUqZLp2AID9CGYAgCw3ePBgpaamOrVVqVJFK1as0O7duxUeHq6HH35Yb731looXL+603oEDBxQcHOx0D1i9evWUkpJi3UsmXQ1r17c5HA7NmTNH+fPnV926ddWgQQOVKVNG33zzjUv1lytXTkuXLtXXX3+tvn37ZmqdN954Q9WqVVNkZKTq16+vgIAAtWjRIl0/Pz8/tWrVSt7e3umWR0ZGau7cuVq4cKEeeeQR1apVS8OHD1dQUNBN9+3h4aH+/furSpUqqlu3rtzd3TVt2rTMHi4AIBtwGFcvogcAAHckIiJCFStWTHdWEQCQcxHMAAC4R06fPq3ly5frn//8p3bs2JHuPjwAQM7F5B8AANwjDz/8sE6fPq2hQ4cSygAATjhjBgAAAAA2Y/IPAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBm/w/0qOvg3rATgQAAAABJRU5ErkJggg==", - "text/plain": [ - "
    " - ] - }, - "metadata": {}, - "output_type": "display_data" - } - ], + "outputs": [], "source": [ "# Extracting LUTs from res_dict\n", "LUTs = [res_dict[key][\"LUT\"] for key in res_dict.keys()] \n", @@ -372,7 +242,7 @@ "plt.bar(res_dict.keys(), LUTs, color ='green', width = 0.3)\n", "plt.xlabel(\"Network layers\")\n", "plt.ylabel(\"Number of LUTs\")\n", - "plt.title(\"Estimated no. of LUTs used for each network layer\")\n", + "plt.title(\"No. of LUTs per layer PE=SIMD=1\")\n", "plt.show()" ] }, @@ -389,8 +259,8 @@ "source": [ "## Modify Parameters\n", "\n", - "We now modify the parallelization parameters of the first network layer to reduce its overall latency.\n", - "We individually extract the `MatrixVectorActivation` blocks from the `.onnx` file and set the config values manually (although this can be done automatically by the FINN compiler as mentioned in the introduction).\n", + "We now modify the parallelization parameters of the first network layer to reduce its latency.\n", + "We only extract the first `MatrixVectorActivation` block from the model and set the parallelization parameters manually.\n", "\n", "In the first step, we left the `PE` & `SIMD` values for all the layers on default (=1) to establish a baseline and measure the estimated clock cycles and resource utilization for each of the individual layers.\n", "\n", @@ -399,22 +269,9 @@ }, { "cell_type": "code", - "execution_count": 9, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "The parallelization parameters of MatrixVectorActivation_0 were: \n", - "PE: 1\n", - "SIMD: 1\n", - "The parallelization parameters of MatrixVectorActivation_0 are updated to: \n", - "PE: 2\n", - "SIMD: 5\n" - ] - } - ], + "outputs": [], "source": [ "from qonnx.custom_op.registry import getCustomOp\n", "\n", @@ -442,45 +299,14 @@ "cell_type": "markdown", "metadata": {}, "source": [ - "We save the model and view it. On expanding the first `MatrixVectorActivation` we can view the updated `PE` & `SIMD` parameters for that layer." + "We save the model and view it. On expanding the first `MatrixVectorActivation` we can see the updated `PE` & `SIMD` parameters for that layer." ] }, { "cell_type": "code", - "execution_count": 10, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "Stopping http://0.0.0.0:5920\n", - "Serving 'cybsec_PE_SIMD_modified.onnx' at http://0.0.0.0:5920\n" - ] - }, - { - "data": { - "text/html": [ - "\n", - " \n", - " " - ], - "text/plain": [ - "" - ] - }, - "execution_count": 10, - "metadata": {}, - "output_type": "execute_result" - } - ], + "outputs": [], "source": [ "model.save(\"cybsec_PE_SIMD_modified.onnx\")\n", "showInNetron(\"cybsec_PE_SIMD_modified.onnx\")" @@ -496,23 +322,9 @@ }, { "cell_type": "code", - "execution_count": 12, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "data": { - "text/plain": [ - "{'MatrixVectorActivation_0': 3840,\n", - " 'MatrixVectorActivation_1': 4096,\n", - " 'MatrixVectorActivation_2': 4096,\n", - " 'MatrixVectorActivation_3': 64}" - ] - }, - "execution_count": 12, - "metadata": {}, - "output_type": "execute_result" - } - ], + "outputs": [], "source": [ "cycles_dict_updated = model.analysis(exp_cycles_per_layer)\n", "cycles_dict_updated" @@ -520,68 +332,30 @@ }, { "cell_type": "code", - "execution_count": 13, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "data": { - "image/png": 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3xqhXr14aP368/ve//9l95kAWT09P6/dTRkaGTpw4IW9vb1WpUsX6uZWkpk2bKjAw0CaHtm3bpi1btliPXEv2v7Zt2rSxnp4K4No4bRK4jT3wwAPXnLDklVde0TfffKPmzZvrrrvuUrNmzfTMM8/c9PTj5cqVs3nu6+srSQoKCsrWnpmZqZSUFOupnGvXrtXQoUO1fv16nT171qZ/SkqKdayr2bNnj7Zs2XLVPwQSExMlSQcPHlSZMmWynUp4tVOSrubKfS1evLgkWa8JyirirhzXw8NDFStWtC7PrePHj+vs2bM5xlmtWjVlZmbq8OHD1lPDcmvfvn2qUqWKChTI/T8L9sSyb98+tWnTJlfj9u3bV+fPn9fmzZtzvR+5jb9jx47q1auXDh48qODgYM2ZM0fp6enq0KGD3WNd7vjx40pOTtZnn32mzz77LMc+WZ+9wYMHa/ny5XrggQdUuXJlNWvWTM8//7waNGiQ6+1d7uDBg9bTUy+XdXrzwYMHrYWDpBxnoM3Jnj17lJKSotKlS+e4PGt/pEunz7711ltauXJlth8Psn50ybpe8PJYrqZQoULZcrh48eLZrrW7mivzMqf1c/tdcS3h4eGaMmWK9u7dq3379slisSgsLMxa1HXt2lU//fSTGjRoYC2ODh48KDc3t2yz/gYEBKhYsWLZvhOu9X7NmDFDp0+f1uTJk/Xcc89dN96ryczM1Pjx4zVp0iTt37/f5trCrO9mSXJzc1P79u01efJknT17VoULF9bMmTNVqFAh6/XRkv2vbW4/kwAo3oA7WunSpRUfH6+lS5dq8eLFWrx4saZNm6aOHTtq+vTpNzzu5ddC5KbdGCPp0h93TZo0UdWqVfXRRx8pKChIHh4e+vHHHzV27NhsE47kJDMzU48++qgGDRqU4/J77rknl3uRO9fbJ9ivVatWmj17tkaNGqUZM2Y4dCbEdu3aqV+/fpo5c6beeOMN/e9//9N9991nd9F+pazP5gsvvHDVox9Z10VVq1ZNu3fv1sKFC7VkyRLNmzdPkyZN0pAhQ6xT0uel3M5UmJmZqdKlS9scZblc1h/mycnJatSokXx8fDRixAhVqlRJhQoV0u+//67BgwfnKm+vdLW8utn1L89LR3xXZB3tXLNmjf766y/VqVNHRYoUUXh4uCZMmKDTp09r8+bNevfdd7Ote7WjuFe61vvVoEEDxcfHa+LEiXrmmWdu+Fqx9957T//5z3/UuXNnvf322ypRooTc3NzUt2/fbO9fx44d9f7772v+/Pl67rnnNGvWLOukQlnsfW1v59kzAUejeAPucB4eHmrZsqVatmypzMxMvfLKK/r000/1n//8R5UrV871HxiO8MMPPygtLU3ff/+9zS/nl5+eleVqcVWqVEmnT59W06ZNr7mt4OBgrVixQqdPn7Y5+rZ79+4bjP7q28ka9/JTCy9cuKD9+/dfN84r+fn5qXDhwjnGuWvXLrm5uWU7wpkblSpV0oYNG5Senp7rCVTsiaVSpUratm1brsZ98skn1axZM3Xq1ElFixbNNtvozcRfokQJRUZGaubMmWrfvr3Wrl2bbfKEG30tihYtqoyMjFy9p0WKFNGzzz6rZ599VhcuXFDr1q317rvvKjo6WoUKFcrVNrMEBwdf9T3IWn4jKlWqpOXLl6tBgwbX/ON69erVOnHihL799ls1bNjQ2r5///5s40mXTrOz93OfF3L7XXGt78By5cqpXLly+umnn/TXX39ZT9Vs2LCh+vfvrzlz5igjI8PmdQkODlZmZqb27NljM/nTsWPHlJycbNf7VblyZY0ZM0aNGzfWY489phUrVqho0aK5Xj/L3Llz9fDDD+vLL7+0aU9OTs42mVCNGjV07733aubMmSpbtqwOHTqUbXbL3L62AOzHNW/AHezEiRM2z93c3KxHB7KmrC5SpIgk3dS09rmV9Wv55b+Op6SkaNq0adn6FilSJMeYnnnmGa1fv15Lly7Ntiw5Odl6fd3jjz+uixcv2hQGGRkZdk+xfT1NmzaVh4eHJkyYYLNfX375pVJSUhQZGWltO3TokPUP7qtxd3dXs2bNtGDBAh04cMDafuzYMc2aNUsPPfSQfHx87I6zTZs2+vfffzVx4sRsy652FNGeWNq0aaM//vgj20x6Vxu/Y8eOmjBhgqZMmaLBgwc7NP4OHTpox44dGjhwoNzd3dWuXbsbHiuLu7u72rRpo3nz5uVYpF5++4gr887Dw0MhISEyxig9Pf3qO3kVjz/+uDZu3Kj169db286cOaPPPvtM5cuXV0hIiN1jSpdyKSMjQ2+//Xa2ZRcvXrTmX055e+HCBU2aNMlmnTp16qhChQoaN25cttx1xpHq3H5XFC5c2NqWk/DwcK1cuVIbN260Fm+1a9dW0aJFNWrUKHl5ealu3brW/o8//rgkZfvR4KOPPpIkm++E3AgNDdWPP/6onTt3qmXLljp37pxd60uX3sMr34M5c+bon3/+ybF/hw4dtGzZMo0bN04lS5ZU8+bNbZbn9rUFYD+OvAG3scWLF+dYDDz44IOqWLGiXnrpJSUlJemRRx5R2bJldfDgQX388ceqXbu29Rfh2rVry93dXaNHj1ZKSoo8PT2t92FztGbNmlmPBHbv3l2nT5/W559/rtKlS+vo0aM2fevWravJkyfrnXfeUeXKlVW6dGk98sgjGjhwoL7//nu1aNHCOjX4mTNntHXrVs2dO1cHDhxQqVKl1LJlSzVo0ECvv/66Dhw4oJCQEH377be5mhTFHn5+foqOjtbw4cP12GOP6YknntDu3bs1adIk3X///TYX+Xfs2FFxcXHX/UP2nXfeUWxsrB566CG98sorKlCggD799FOlpaVpzJgxNxRnx44dNWPGDPXv39/6R+iZM2e0fPlyvfLKKzneH82eWAYOHKi5c+fq6aefVufOnVW3bl0lJSXp+++/15QpU1SrVq1sY/fq1Uupqal688035evrqzfeeMMh8UdGRqpkyZKaM2eOmjdvnu2zfKOvxahRo7Rq1SrVq1dPXbt2VUhIiJKSkvT7779r+fLlSkpKknTpcx4QEKAGDRrI399fO3fu1MSJExUZGXlDR01ef/11ffXVV2revLl69+6tEiVKaPr06dq/f7/mzZt3w6edNmrUSN27d9fIkSMVHx+vZs2aqWDBgtqzZ4/mzJmj8ePHq23btnrwwQdVvHhxRUVFqXfv3rJYLPrvf/+b7XPs5uamyZMnq2XLlqpdu7ZefPFFlSlTRrt27dL27dtz/EM/L+X2u8LLy0shISH6+uuvdc8996hEiRKqUaOG9dq98PBwzZw5UxaLxXoapbu7ux588EEtXbpUjRs3trkdQ61atRQVFaXPPvvMesrpxo0bNX36dD355JN6+OGH7d6X+vXra8GCBXr88cfVtm1bzZ8/365bkLRo0UIjRozQiy++qAcffFBbt27VzJkzbc4WuNzzzz+vQYMG6bvvvlOPHj2ybSu3ry2AG3CLZ7cEcAtc61YBumwa/Llz55pmzZqZ0qVLGw8PD1OuXDnTvXt3c/ToUZvxPv/8c1OxYkXj7u5uc9uAq90qYM6cOTnG8+uvv9q0Dx061Egyx48ft7Z9//33JjQ01BQqVMiUL1/ejB492jp1+/79+639EhISTGRkpClatKiRZBPHqVOnTHR0tKlcubLx8PAwpUqVMg8++KD54IMPbG5hcOLECdOhQwfj4+NjfH19TYcOHczmzZvtulXAlfuU9RpceWuFiRMnmqpVq5qCBQsaf39/06NHj2zTpTdq1Mjk9mv5999/NxEREcbb29sULlzYPPzww2bdunU2fey5VYAxl6Z7f/PNN02FChVMwYIFTUBAgGnbtq3NbQCUw5TpuYnFmEuvd69evcxdd91lPDw8TNmyZU1UVJR1av2rfX4GDRpkJJmJEyfedPxZXnnlFSPJzJo1y6GvxbFjx0zPnj1NUFCQdb0mTZqYzz77zNrn008/NQ0bNjQlS5Y0np6eplKlSmbgwIEmJSXlmvuXtc0rbxVgjDH79u0zbdu2NcWKFTOFChUyDzzwgFm4cKFNn6u9vtfz2Wefmbp16xovLy9TtGhRU7NmTTNo0CBz5MgRa5+1a9ea+vXrGy8vLxMYGGgGDRpknVb+ylz4+eefzaOPPmqKFi1qihQpYkJDQ83HH39sXR4VFWWKFCmSLY6s74vrCQ4ONpGRkdnar/y+Mib33xXr1q0zdevWNR4eHtne9+3btxtJplq1ajZjv/POO0aS+c9//pMtlvT0dDN8+HDr5ysoKMhER0dbb6twvX0xJufPwoIFC0yBAgXMs88+m23q/yvHvfJWAQMGDDBlypQxXl5epkGDBmb9+vU5vmZZHn/8cSMpx1w3Jnevrb3fUQCMsRjDVfUAgDtLv3799OWXXyohIcF6WhyA3Hvqqae0detW7d2719mhAHcUrnkDANxRzp8/r//9739q06YNhRtwA44ePapFixbZ3GIDwK3BNW8AgDtCYmKili9frrlz5+rEiRPq06ePs0MCXMr+/fu1du1affHFFypYsKC6d+/u7JCAOw7FGwDgjrBjxw61b99epUuX1oQJE1S7dm1nhwS4lLi4OL344osqV66cpk+froCAAGeHBNxxuOYNAAAAAFwA17wBAAAAgAugeAMAAAAAF8A1b7mQmZmpI0eOqGjRorJYLM4OBwAAAICTGGN06tQpBQYGys3t1h4Lo3jLhSNHjigoKMjZYQAAAADIJw4fPqyyZcve0m1SvOVC0aJFJV16g3x8fJwcDQAAAABnSU1NVVBQkLVGuJUo3nIh61RJHx8fijcAAAAATrmciglLAAAAAMAFULwBAAAAgAugeAMAAAAAF0DxBgAAAAAugOINAAAAAFwAxRsAAAAAuACKNwAAAABwARRvAAAAAOACKN4AAAAAwAVQvAEAAACAC6B4AwAAAAAXQPEGAAAAAC6A4g0AAAAAXADFGwAAAAC4AIo3AAAAAHABBZwdAADkBxaLsyNwLmOcHQFuR+SVsyMAcLvhyBsAAAAAuACKNwAAAABwARRvAAAAAOACKN4AAAAAwAXkm+Jt1KhRslgs6tu3r7Xt/Pnz6tmzp0qWLClvb2+1adNGx44ds1nv0KFDioyMVOHChVW6dGkNHDhQFy9etOmzevVq1alTR56enqpcubJiYmJuwR4BAAAAgOPki+Lt119/1aeffqrQ0FCb9n79+umHH37QnDlzFBcXpyNHjqh169bW5RkZGYqMjNSFCxe0bt06TZ8+XTExMRoyZIi1z/79+xUZGamHH35Y8fHx6tu3r1566SUtXbr0lu0fAAAAANwsizHOncj29OnTqlOnjiZNmqR33nlHtWvX1rhx45SSkiI/Pz/NmjVLbdu2lSTt2rVL1apV0/r161W/fn0tXrxYLVq00JEjR+Tv7y9JmjJligYPHqzjx4/Lw8NDgwcP1qJFi7Rt2zbrNtu1a6fk5GQtWbIkVzGmpqbK19dXKSkp8vHxcfyLAMDpmNLc2RHgdkReOTsCAHnBmbWB04+89ezZU5GRkWratKlN+6ZNm5Senm7TXrVqVZUrV07r16+XJK1fv141a9a0Fm6SFBERodTUVG3fvt3a58qxIyIirGPkJC0tTampqTYPAAAAAHAmp96ke/bs2fr999/166+/ZluWkJAgDw8PFStWzKbd399fCQkJ1j6XF25Zy7OWXatPamqqzp07Jy8vr2zbHjlypIYPH37D+wUAAAAAjua0I2+HDx9Wnz59NHPmTBUqVMhZYeQoOjpaKSkp1sfhw4edHRIAAACAO5zTirdNmzYpMTFRderUUYECBVSgQAHFxcVpwoQJKlCggPz9/XXhwgUlJyfbrHfs2DEFBARIkgICArLNPpn1/Hp9fHx8cjzqJkmenp7y8fGxeQAAAACAMzmteGvSpIm2bt2q+Ph46+O+++5T+/btrf9fsGBBrVixwrrO7t27dejQIYWFhUmSwsLCtHXrViUmJlr7xMbGysfHRyEhIdY+l4+R1SdrDAAAAABwBU675q1o0aKqUaOGTVuRIkVUsmRJa3uXLl3Uv39/lShRQj4+Pnr11VcVFham+vXrS5KaNWumkJAQdejQQWPGjFFCQoLeeust9ezZU56enpKkl19+WRMnTtSgQYPUuXNnrVy5Ut98840WLVp0a3cYAAAAAG6CUycsuZ6xY8fKzc1Nbdq0UVpamiIiIjRp0iTrcnd3dy1cuFA9evRQWFiYihQpoqioKI0YMcLap0KFClq0aJH69eun8ePHq2zZsvriiy8UERHhjF0CAAAAgBvi9Pu8uQLu8wbc/rgflbMjwO2IvHJ2BADywh19nzcAAAAAwPVRvAEAAACAC6B4AwAAAAAXQPEGAAAAAC6A4g0AAAAAXADFGwAAAAC4AIo3AAAAAHAB+fom3bg67p3j7AgAAACAW4sjbwAAAADgAijeAAAAAMAFULwBAAAAgAugeAMAAAAAF0DxBgAAAAAugOINAAAAAFwAxRsAAAAAuACKNwAAAABwARRvAAAAAOACKN4AAAAAwAVQvAEAAACAC6B4AwAAAAAXQPEGAAAAAC6A4g0AAAAAXADFGwAAAAC4AIo3AAAAAHABFG8AAAAA4AIo3gAAAADABVC8AQAAAIALoHgDAAAAABdA8QYAAAAALoDiDQAAAABcAMUbAAAAALgAijcAAAAAcAEUbwAAAADgAijeAAAAAMAFOLV4mzx5skJDQ+Xj4yMfHx+FhYVp8eLF1uWNGzeWxWKxebz88ss2Yxw6dEiRkZEqXLiwSpcurYEDB+rixYs2fVavXq06derI09NTlStXVkxMzK3YPQAAAABwmALO3HjZsmU1atQo3X333TLGaPr06WrVqpU2b96s6tWrS5K6du2qESNGWNcpXLiw9f8zMjIUGRmpgIAArVu3TkePHlXHjh1VsGBBvffee5Kk/fv3KzIyUi+//LJmzpypFStW6KWXXlKZMmUUERFxa3cYAAAAAG6QxRhjnB3E5UqUKKH3339fXbp0UePGjVW7dm2NGzcux76LFy9WixYtdOTIEfn7+0uSpkyZosGDB+v48ePy8PDQ4MGDtWjRIm3bts26Xrt27ZScnKwlS5bkOG5aWprS0tKsz1NTUxUUFKSUlBT5+Pg4bmdvgsXi7AicK399anE7IKecHQFuR+SVsyMAkBdSU1Pl6+vrlNog31zzlpGRodmzZ+vMmTMKCwuzts+cOVOlSpVSjRo1FB0drbNnz1qXrV+/XjVr1rQWbpIUERGh1NRUbd++3dqnadOmNtuKiIjQ+vXrrxrLyJEj5evra30EBQU5ajcBAAAA4IY49bRJSdq6davCwsJ0/vx5eXt767vvvlNISIgk6fnnn1dwcLACAwO1ZcsWDR48WLt379a3334rSUpISLAp3CRZnyckJFyzT2pqqs6dOycvL69sMUVHR6t///7W51lH3gAAAADAWZxevFWpUkXx8fFKSUnR3LlzFRUVpbi4OIWEhKhbt27WfjVr1lSZMmXUpEkT7du3T5UqVcqzmDw9PeXp6Zln4wMAAACAvZx+2qSHh4cqV66sunXrauTIkapVq5bGjx+fY9969epJkvbu3StJCggI0LFjx2z6ZD0PCAi4Zh8fH58cj7oBAAAAQH7k9OLtSpmZmTaThVwuPj5eklSmTBlJUlhYmLZu3arExERrn9jYWPn4+FhPvQwLC9OKFStsxomNjbW5rg4AAAAA8junnjYZHR2t5s2bq1y5cjp16pRmzZql1atXa+nSpdq3b59mzZqlxx9/XCVLltSWLVvUr18/NWzYUKGhoZKkZs2aKSQkRB06dNCYMWOUkJCgt956Sz179rSe9vjyyy9r4sSJGjRokDp37qyVK1fqm2++0aJFi5y56wAAAABgF6cWb4mJierYsaOOHj0qX19fhYaGaunSpXr00Ud1+PBhLV++XOPGjdOZM2cUFBSkNm3a6K233rKu7+7uroULF6pHjx4KCwtTkSJFFBUVZXNfuAoVKmjRokXq16+fxo8fr7Jly+qLL77gHm8AAAAAXEq+u89bfuTMezlcDffOcXYEuN2QU86OALcj8srZEQDIC9znDQAAAABwTRRvAAAAAOACKN4AAAAAwAVQvAEAAACAC6B4AwAAAAAXQPEGAAAAAC6A4g0AAAAAXADFGwAAAAC4AIo3AAAAAHABFG8AAAAA4AIo3gAAAADABVC8AQAAAIALoHgDAAAAABdA8QYAAAAALoDiDQAAAABcAMUbAAAAALgAijcAAAAAcAEUbwAAAADgAijeAAAAAMAFULwBAAAAgAugeAMAAAAAF0DxBgAAAAAugOINAAAAAFwAxRsAAAAAuACKNwAAAABwARRvAAAAAOACKN4AAAAAwAVQvAEAAACAC6B4AwAAAAAXQPEGAAAAAC6A4g0AAAAAXADFGwAAAAC4AIo3AAAAAHABTi3eJk+erNDQUPn4+MjHx0dhYWFavHixdfn58+fVs2dPlSxZUt7e3mrTpo2OHTtmM8ahQ4cUGRmpwoULq3Tp0ho4cKAuXrxo02f16tWqU6eOPD09VblyZcXExNyK3QMAAAAAh7G7eDt37pzOnj1rfX7w4EGNGzdOy5Yts3vjZcuW1ahRo7Rp0yb99ttveuSRR9SqVStt375dktSvXz/98MMPmjNnjuLi4nTkyBG1bt3aun5GRoYiIyN14cIFrVu3TtOnT1dMTIyGDBli7bN//35FRkbq4YcfVnx8vPr27auXXnpJS5cutTteAAAAAHAWizHG2LNCs2bN1Lp1a7388stKTk5W1apVVbBgQf3777/66KOP1KNHj5sKqESJEnr//ffVtm1b+fn5adasWWrbtq0kadeuXapWrZrWr1+v+vXra/HixWrRooWOHDkif39/SdKUKVM0ePBgHT9+XB4eHho8eLAWLVqkbdu2WbfRrl07JScna8mSJbmKKTU1Vb6+vkpJSZGPj89N7Z+jWCzOjsC57PvUAtdHTjk7AtyOyCtnRwAgLzizNrD7yNvvv/+u8PBwSdLcuXPl7++vgwcPasaMGZowYcINB5KRkaHZs2frzJkzCgsL06ZNm5Senq6mTZta+1StWlXlypXT+vXrJUnr169XzZo1rYWbJEVERCg1NdV69G79+vU2Y2T1yRojJ2lpaUpNTbV5AAAAAIAz2V28nT17VkWLFpUkLVu2TK1bt5abm5vq16+vgwcP2h3A1q1b5e3tLU9PT7388sv67rvvFBISooSEBHl4eKhYsWI2/f39/ZWQkCBJSkhIsCncspZnLbtWn9TUVJ07dy7HmEaOHClfX1/rIygoyO79AgAAAABHsrt4q1y5subPn6/Dhw9r6dKlatasmSQpMTHxhg4bVqlSRfHx8dqwYYN69OihqKgo7dixw+5xHCk6OlopKSnWx+HDh50aDwAAAADYXbwNGTJEr732msqXL68HHnhAYWFhki4dhbv33nvtDsDDw0OVK1dW3bp1NXLkSNWqVUvjx49XQECALly4oOTkZJv+x44dU0BAgCQpICAg2+yTWc+v18fHx0deXl45xuTp6WmdATPrAQAAAADOZHfx1rZtWx06dEi//fabzYyNTZo00dixY286oMzMTKWlpalu3boqWLCgVqxYYV22e/duHTp0yFowhoWFaevWrUpMTLT2iY2NlY+Pj0JCQqx9Lh8jq0/WGAAAAADgCgrcyEoBAQE6ffq0YmNj1bBhQ3l5een++++Xxc5ppaKjo9W8eXOVK1dOp06d0qxZs7R69WotXbpUvr6+6tKli/r3768SJUrIx8dHr776qsLCwlS/fn1Jl2a+DAkJUYcOHTRmzBglJCTorbfeUs+ePeXp6SlJevnllzVx4kQNGjRInTt31sqVK/XNN99o0aJFN7LrAAAAAOAUdhdvJ06c0DPPPKNVq1bJYrFoz549qlixorp06aLixYvrww8/zPVYiYmJ6tixo44ePSpfX1+FhoZq6dKlevTRRyVJY8eOlZubm9q0aaO0tDRFRERo0qRJ1vXd3d21cOFC9ejRQ2FhYSpSpIiioqI0YsQIa58KFSpo0aJF6tevn8aPH6+yZcvqiy++UEREhL27DgAAAABOY/d93jp27KjExER98cUXqlatmv744w9VrFhRS5cuVf/+/a1T9N9OuM9b/sO9c+Bo5JSzI8DtiLxydgQA8oIzawO7j7wtW7ZMS5cuVdmyZW3a77777hu6VQAAAAAA4PrsnrDkzJkzKly4cLb2pKQk63VmAAAAAADHsrt4Cw8P14wZM6zPLRaLMjMzNWbMGD388MMODQ4AAAAAcIndp02OGTNGTZo00W+//aYLFy5o0KBB2r59u5KSkrR27dq8iBEAAAAA7nh2H3mrUaOG/vzzTz300ENq1aqVzpw5o9atW2vz5s2qVKlSXsQIAAAAAHc8u2ebvBMx22T+w6cWjkZOOTsC3I7IK2dHACAv5PvZJrds2ZLrAUNDQ284GAAAAABAznJVvNWuXVsWi0XXO0hnsViUkZHhkMAAAAAAAP8vV8Xb/v378zoOAAAAAMA15Kp4Cw4Ozus4AAAAAADXYPdskyNHjtTUqVOztU+dOlWjR492SFAAAAAAAFt2F2+ffvqpqlatmq29evXqmjJlikOCAgAAAADYsrt4S0hIUJkyZbK1+/n56ejRow4JCgAAAABgy+7iLSgoSGvXrs3WvnbtWgUGBjokKAAAAACArVxNWHK5rl27qm/fvkpPT9cjjzwiSVqxYoUGDRqkAQMGODxAAAAAAMANFG8DBw7UiRMn9Morr+jChQuSpEKFCmnw4MGKjo52eIAAAAAAAMlirnfn7as4ffq0du7cKS8vL919993y9PR0dGz5Rmpqqnx9fZWSkiIfHx9nhyNJslicHYFz3dinFrg6csrZEeB2RF45OwIAecGZtYHd17xNmzZN586dk7e3t+6//37VqFHjti7cAAAAACA/sLt4e/311+Xv768uXbpo3bp1eRETAAAAAOAKdhdv//zzj6ZPn65///1XjRs3VtWqVTV69GglJCTkRXwAAAAAAN1A8VagQAE99dRTWrBggQ4fPqyuXbtq5syZKleunJ544gktWLBAmZmZeRErAAAAANyx7C7eLufv76+HHnpIYWFhcnNz09atWxUVFaVKlSpp9erVDgoRAAAAAHBDxduxY8f0wQcfqHr16mrcuLFSU1O1cOFC7d+/X//884+eeeYZRUVFOTpWAAAAALhj2X2rgJYtW2rp0qW655579NJLL6ljx44qUaKETZ/ExEQFBATcNqdPcquA/Ifpl+Fo5JSzI8DtiLxydgQA8oIzawO7b9JdunRpxcXFKSws7Kp9/Pz8tH///psKDAAAAADw/274Jt13Eo685T98auFo5JSzI8DtiLxydgQA8oJL3aS7d+/emjBhQrb2iRMnqm/fvo6ICQAAAABwBbuLt3nz5qlBgwbZ2h988EHNnTvXIUEBAAAAAGzZXbydOHFCvr6+2dp9fHz077//OiQoAAAAAIAtu4u3ypUra8mSJdnaFy9erIoVKzokKAAAAACALbtnm+zfv7969eql48eP65FHHpEkrVixQh9++KHGjRvn6PgAAAAAALqB4q1z585KS0vTu+++q7fffluSVL58eU2ePFkdO3Z0eIAAAAAAgJu8VcDx48fl5eUlb29vR8aU73CrgPyH6ZfhaOSUsyPA7Yi8cnYEAPKCS92k+3J+fn6OigMAAAAAcA12T1jiSCNHjtT999+vokWLqnTp0nryySe1e/dumz6NGzeWxWKxebz88ss2fQ4dOqTIyEgVLlxYpUuX1sCBA3Xx4kWbPqtXr1adOnXk6empypUrKyYmJq93DwAAAAAcxqnFW1xcnHr27KlffvlFsbGxSk9PV7NmzXTmzBmbfl27dtXRo0etjzFjxliXZWRkKDIyUhcuXNC6des0ffp0xcTEaMiQIdY++/fvV2RkpB5++GHFx8erb9++eumll7R06dJbtq8AAAAAcDNu6po3Rzt+/LhKly6tuLg4NWzYUNKlI2+1a9e+6kyWixcvVosWLXTkyBH5+/tLkqZMmaLBgwfr+PHj8vDw0ODBg7Vo0SJt27bNul67du2UnJyc420PrsQ1b/lP/vnU4nZBTjk7AtyOyCtnRwAgLzizNrD7yNvff/991WW//PLLTQWTkpIiSSpRooRN+8yZM1WqVCnVqFFD0dHROnv2rHXZ+vXrVbNmTWvhJkkRERFKTU3V9u3brX2aNm1qM2ZERITWr1+fYxxpaWlKTU21eQAAAACAM9ldvDVr1kxJSUnZ2teuXavHHnvshgPJzMxU37591aBBA9WoUcPa/vzzz+t///ufVq1apejoaP33v//VCy+8YF2ekJBgU7hJsj5PSEi4Zp/U1FSdO3cuWywjR46Ur6+v9REUFHTD+wUAAAAAjmD3bJP169dXs2bNtGrVKhUtWlSStGbNGrVs2VLDhg274UB69uypbdu26eeff7Zp79atm/X/a9asqTJlyqhJkybat2+fKlWqdMPbu5bo6Gj179/f+jw1NZUCDgAAAIBT2X3k7YsvvlC5cuXUsmVLpaWladWqVYqMjNSIESPUr1+/GwqiV69eWrhwoVatWqWyZctes2+9evUkSXv37pUkBQQE6NixYzZ9sp4HBARcs4+Pj4+8vLyybcPT01M+Pj42DwAAAABwJruLNzc3N82ePVsFCxbUI488oieeeEIjR45Unz597N64MUa9evXSd999p5UrV6pChQrXXSc+Pl6SVKZMGUlSWFiYtm7dqsTERGuf2NhY+fj4KCQkxNpnxYoVNuPExsYqLCzM7pgBAAAAwBlyNdvkli1bsrWdOnVKzz33nCIjI9WjRw9re2hoaK43/sorr2jWrFlasGCBqlSpYm339fWVl5eX9u3bp1mzZunxxx9XyZIltWXLFvXr109ly5ZVXFycpEu3Cqhdu7YCAwM1ZswYJSQkqEOHDnrppZf03nvvSbp0q4AaNWqoZ8+e6ty5s1auXKnevXtr0aJFioiIuG6czDaZ/zCDFxyNnHJ2BLgdkVfOjgBAXnBmbZCr4s3NzU0Wi0WXd738edb/WywWZWRk5H7jV/lWnzZtmjp16qTDhw/rhRde0LZt23TmzBkFBQXpqaee0ltvvWXzQh08eFA9evTQ6tWrVaRIEUVFRWnUqFEqUOD/L+lbvXq1+vXrpx07dqhs2bL6z3/+o06dOuUqToq3/Id/EOFo5JSzI8DtiLxydgQA8kK+L94OHjyY6wGDg4NvKqD8iOIt/+EfRDgaOeXsCHA7Iq+cHQGAvODM2iBXs03ejgUZAAAAALgSuycsGTlypKZOnZqtferUqRo9erRDggIAAAAA2LK7ePv0009VtWrVbO3Vq1fXlClTHBIUAAAAAMCW3cVbQkKCdZr+y/n5+eno0aMOCQoAAAAAYMvu4i0oKEhr167N1r527VoFBgY6JCgAAAAAgK1cTVhyua5du6pv375KT0/XI488IklasWKFBg0apAEDBjg8QAAAAADADRRvAwcO1IkTJ/TKK6/owoULkqRChQpp8ODBio6OdniAAAAAAIBc3uctJ6dPn9bOnTvl5eWlu+++W56eno6OLd/gPm/5D/fOgaORU86OALcj8srZEQDIC/n+Pm858fb2tk5ccjsXbgAAAACQH9g9YUlmZqZGjBghX19fBQcHKzg4WMWKFdPbb7+tzMzMvIgRAAAAAO54dh95e/PNN/Xll19q1KhRatCggSTp559/1rBhw3T+/Hm9++67Dg8SAAAAAO50dl/zFhgYqClTpuiJJ56waV+wYIFeeeUV/fPPPw4NMD/gmrf8h+sI4GjklLMjwO2IvHJ2BADygjNrA7tPm0xKSlLVqlWztVetWlVJSUkOCQoAAAAAYMvu4q1WrVqaOHFitvaJEyeqVq1aDgkKAAAAAGDL7mvexowZo8jISC1fvlxhYWGSpPXr1+vw4cP68ccfHR4gAAAAAOAGjrw1atRIf/75p5566iklJycrOTlZrVu31u7duxUeHp4XMQIAAADAHe+Gb9J9J2HCkvyHTy0cjZxydgS4HZFXzo4AQF7I9zfp3rJlS64HDA0NveFgAAAAAAA5y1XxVrt2bVksFl3vIJ3FYlFGRoZDAgMAAAAA/L9cFW/79+/P6zgAAAAAANeQq+ItODg4r+MAAAAAAFyD3bNNjhw5UlOnTs3WPnXqVI0ePdohQQEAAAAAbNldvH366aeqWrVqtvbq1atrypQpDgkKAAAAAGDL7uItISFBZcqUydbu5+eno0ePOiQoAAAAAIAtu4u3oKAgrV27Nlv72rVrFRgY6JCgAAAAAAC2cjVhyeW6du2qvn37Kj09XY888ogkacWKFRo0aJAGDBjg8AABAAAAADdQvA0cOFAnTpzQK6+8ogsXLkiSChUqpMGDBys6OtrhAQIAAAAAJIu53p23r+L06dPauXOnvLy8dPfdd8vT09PRseUbqamp8vX1VUpKinx8fJwdjiTJYnF2BM51Y59a4OrIKWdHgNsReeXsCADkBWfWBnYfecvi7e2t+++/35GxAAAAAACuwu4JSwAAAAAAtx7FGwAAAAC4AIo3AAAAAHABuSre6tSpo5MnT0qSRowYobNnz+ZpUAAAAAAAW7kq3nbu3KkzZ85IkoYPH67Tp0/naVAAAAAAAFu5Kt5q166tF198UcOHD5cxRh988IFGjBiR48MeI0eO1P3336+iRYuqdOnSevLJJ7V7926bPufPn1fPnj1VsmRJeXt7q02bNjp27JhNn0OHDikyMlKFCxdW6dKlNXDgQF28eNGmz+rVq1WnTh15enqqcuXKiomJsStWAAAAAHCmXN0qICYmRkOHDtXChQtlsVi0ePFiFSiQfVWLxaIhQ4bkeuNxcXHq2bOn7r//fl28eFFvvPGGmjVrph07dqhIkSKSpH79+mnRokWaM2eOfH191atXL7Vu3Vpr166VJGVkZCgyMlIBAQFat26djh49qo4dO6pgwYJ67733JEn79+9XZGSkXn75Zc2cOVMrVqzQSy+9pDJlyigiIiLX8QIAAACAs9h9k243NzclJCSodOnSDg/m+PHjKl26tOLi4tSwYUOlpKTIz89Ps2bNUtu2bSVJu3btUrVq1bR+/XrVr19fixcvVosWLXTkyBH5+/tLkqZMmaLBgwfr+PHj8vDw0ODBg7Vo0SJt27bNuq127dopOTlZS5YsuW5c3KQ7/+HGp3A0csrZEeB2RF45OwIAecGZtYHds01mZmbmSeEmSSkpKZKkEiVKSJI2bdqk9PR0NW3a1NqnatWqKleunNavXy9JWr9+vWrWrGkt3CQpIiJCqamp2r59u7XP5WNk9cka40ppaWlKTU21eQAAAACAM93QrQL27dunV199VU2bNlXTpk3Vu3dv7du376YCyczMVN++fdWgQQPVqFFDkpSQkCAPDw8VK1bMpq+/v78SEhKsfS4v3LKWZy27Vp/U1FSdO3cuWywjR46Ur6+v9REUFHRT+wYAAAAAN8vu4m3p0qUKCQnRxo0bFRoaqtDQUG3YsEHVq1dXbGzsDQfSs2dPbdu2TbNnz77hMRwlOjpaKSkp1sfhw4edHRIAAACAO1yuJiy53Ouvv65+/fpp1KhR2doHDx6sRx991O4gevXqpYULF2rNmjUqW7astT0gIEAXLlxQcnKyzdG3Y8eOKSAgwNpn48aNNuNlzUZ5eZ8rZ6g8duyYfHx85OXllS0eT09PeXp62r0fAAAAAJBX7D7ytnPnTnXp0iVbe+fOnbVjxw67xjLGqFevXvruu++0cuVKVahQwWZ53bp1VbBgQa1YscLatnv3bh06dEhhYWGSpLCwMG3dulWJiYnWPrGxsfLx8VFISIi1z+VjZPXJGgMAAAAA8ju7izc/Pz/Fx8dna4+Pj7d7IpOePXvqf//7n2bNmqWiRYsqISFBCQkJ1uvQfH191aVLF/Xv31+rVq3Spk2b9OKLLyosLEz169eXJDVr1kwhISHq0KGD/vjjDy1dulRvvfWWevbsaT169vLLL+uvv/7SoEGDtGvXLk2aNEnffPON+vXrZ+/uAwAAAIBT2H3aZNeuXdWtWzf99ddfevDBByVJa9eu1ejRo9W/f3+7xpo8ebIkqXHjxjbt06ZNU6dOnSRJY8eOlZubm9q0aaO0tDRFRERo0qRJ1r7u7u5auHChevToobCwMBUpUkRRUVE2NwyvUKGCFi1apH79+mn8+PEqW7asvvjiC+7xBgAAAMBl2H2fN2OMxo0bpw8//FBHjhyRJAUGBmrgwIHq3bu3LLfhTV24z1v+w71z4GjklLMjwO2IvHJ2BADygjNrA7uLt8udOnVKklS0aFGHBZQfUbzlP/yDCEcjp5wdAW5H5JWzIwCQF5xZG9h92uTlbveiDQAAAADyixu6STcAAAAA4NaieAMAAAAAF0DxBgAAAAAuwK7iLT09XU2aNNGePXvyKh4AAAAAQA7sKt4KFiyoLVu25FUsAAAAAICrsPu0yRdeeEFffvllXsQCAAAAALgKu28VcPHiRU2dOlXLly9X3bp1VaRIEZvlH330kcOCAwAAAABcYnfxtm3bNtWpU0eS9Oeff9oss9zpd+MEAAAAgDxid/G2atWqvIgDAAAAAHANN3yrgL1792rp0qU6d+6cJMkY47CgAAAAAAC27C7eTpw4oSZNmuiee+7R448/rqNHj0qSunTpogEDBjg8QAAAAADADRRv/fr1U8GCBXXo0CEVLlzY2v7ss89qyZIlDg0OAAAAAHCJ3de8LVu2TEuXLlXZsmVt2u+++24dPHjQYYEBAAAAAP6f3Ufezpw5Y3PELUtSUpI8PT0dEhQAAAAAwJbdxVt4eLhmzJhhfW6xWJSZmakxY8bo4YcfdmhwAAAAAIBL7D5tcsyYMWrSpIl+++03XbhwQYMGDdL27duVlJSktWvX5kWMAAAAAHDHs/vIW40aNfTnn3/qoYceUqtWrXTmzBm1bt1amzdvVqVKlfIiRgAAAAC441kMN2i7rtTUVPn6+iolJUU+Pj7ODkeSZLE4OwLn4lMLRyOnnB0BbkfklbMjAJAXnFkb2H3apCSdPHlSX375pXbu3ClJCgkJ0YsvvqgSJUo4NDgAAAAAwCV2nza5Zs0alS9fXhMmTNDJkyd18uRJTZgwQRUqVNCaNWvyIkYAAAAAuOPZfdpkzZo1FRYWpsmTJ8vd3V2SlJGRoVdeeUXr1q3T1q1b8yRQZ+K0yfyHU1HgaOSUsyPA7Yi8cnYEAPKCM2sDu4+87d27VwMGDLAWbpLk7u6u/v37a+/evQ4NDgAAAABwid3FW506dazXul1u586dqlWrlkOCAgAAAADYytWEJVu2bLH+f+/evdWnTx/t3btX9evXlyT98ssv+uSTTzRq1Ki8iRIAAAAA7nC5uubNzc1NFotF1+tqsViUkZHhsODyC655y3+4jgCORk45OwLcjsgrZ0cAIC/k+1sF7N+/P6/jAAAAAABcQ66Kt+Dg4LyOAwAAAABwDTd0k+4jR47o559/VmJiojIzM22W9e7d2yGBAQAAAAD+n93FW0xMjLp37y4PDw+VLFlSlstOaLdYLBRvAAAAAJAH7C7e/vOf/2jIkCGKjo6Wm5vddxoAAAAAANwAu6uvs2fPql27dhRuAAAAAHAL2V2BdenSRXPmzMmLWAAAAAAAV2F38TZy5EjFxcWpcePGevXVV9W/f3+bhz3WrFmjli1bKjAwUBaLRfPnz7dZ3qlTJ1ksFpvHY489ZtMnKSlJ7du3l4+Pj4oVK6YuXbro9OnTNn22bNmi8PBwFSpUSEFBQRozZoy9uw0AAAAATmX3NW8jR47U0qVLVaVKFUnKNmGJPc6cOaNatWqpc+fOat26dY59HnvsMU2bNs363NPT02Z5+/btdfToUcXGxio9PV0vvviiunXrplmzZkm6dBO9Zs2aqWnTppoyZYq2bt2qzp07q1ixYurWrZtd8QIAAACAs9hdvH344YeaOnWqOnXqdNMbb968uZo3b37NPp6engoICMhx2c6dO7VkyRL9+uuvuu+++yRJH3/8sR5//HF98MEHCgwM1MyZM3XhwgVNnTpVHh4eql69uuLj4/XRRx9dtXhLS0tTWlqa9XlqauoN7iEAAAAAOIbdp016enqqQYMGeRFLjlavXq3SpUurSpUq6tGjh06cOGFdtn79ehUrVsxauElS06ZN5ebmpg0bNlj7NGzYUB4eHtY+ERER2r17t06ePJnjNkeOHClfX1/rIygoKI/2DgAAAAByx+7irU+fPvr444/zIpZsHnvsMc2YMUMrVqzQ6NGjFRcXp+bNmysjI0OSlJCQoNKlS9usU6BAAZUoUUIJCQnWPv7+/jZ9sp5n9blSdHS0UlJSrI/Dhw87etcAAAAAwC52nza5ceNGrVy5UgsXLlT16tVVsGBBm+Xffvutw4Jr166d9f9r1qyp0NBQVapUSatXr1aTJk0ctp0reXp6Zru2DgAAAACcye7irVixYledXCSvVaxYUaVKldLevXvVpEkTBQQEKDEx0abPxYsXlZSUZL1OLiAgQMeOHbPpk/X8atfSAQAAAEB+Y3fxdvnMj7fa33//rRMnTqhMmTKSpLCwMCUnJ2vTpk2qW7euJGnlypXKzMxUvXr1rH3efPNNpaenW48SxsbGqkqVKipevLhzdgQAAAAA7GT3NW+OdPr0acXHxys+Pl6StH//fsXHx+vQoUM6ffq0Bg4cqF9++UUHDhzQihUr1KpVK1WuXFkRERGSpGrVqumxxx5T165dtXHjRq1du1a9evVSu3btFBgYKEl6/vnn5eHhoS5dumj79u36+uuvNX78eLvvSQcAAAAAzmQxxhh7VqhQocI17+f2119/5Xqs1atX6+GHH87WHhUVpcmTJ+vJJ5/U5s2blZycrMDAQDVr1kxvv/22zQQkSUlJ6tWrl3744Qe5ubmpTZs2mjBhgry9va19tmzZop49e+rXX39VqVKl9Oqrr2rw4MG5jjM1NVW+vr5KSUmRj49PrtfLS3beUu+2Y9+nFrg+csrZEeB2RF45OwIAecGZtYHdxdv48eNtnqenp2vz5s1asmSJBg4cqNdff92hAeYHFG/5D/8gwtHIKWdHgNsReeXsCADkBWfWBnZf89anT58c2z/55BP99ttvNx0QAAAAACA7h13z1rx5c82bN89RwwEAAAAALuOw4m3u3LkqUaKEo4YDAAAAAFzG7tMm7733XpsJS4wxSkhI0PHjxzVp0iSHBgcAAAAAuMTu4u3JJ5+0ee7m5iY/Pz81btxYVatWdVRcAAAAAIDL2D3b5J2I2SbzHz61cDRyytkR4HZEXjk7AgB5wZm1gVNv0g0AAAAAyJ1cnzbp5uZ2zZtzS5LFYtHFixdvOigAAAAAgK1cF2/ffffdVZetX79eEyZMUGZmpkOCAgAAAADYynXx1qpVq2xtu3fv1uuvv64ffvhB7du314gRIxwaHAAAAADgkhu65u3IkSPq2rWratasqYsXLyo+Pl7Tp09XcHCwo+MDAAAAAMjO4i0lJUWDBw9W5cqVtX37dq1YsUI//PCDatSokVfxAQAAAABkx2mTY8aM0ejRoxUQEKCvvvoqx9MoAQAAAAB5I9f3eXNzc5OXl5eaNm0qd3f3q/b79ttvHRZcfsF93vIf7p0DRyOnnB0BbkfklbMjAJAXnFkb5PrIW8eOHa97qwAAAAAAQN7IdfEWExOTh2EAAAAAAK7lhmabBAAAAADcWhRvAAAAAOACKN4AAAAAwAVQvAEAAACAC6B4AwAAAAAXQPEGAAAAAC6A4g0AAAAAXADFGwAAAAC4AIo3AAAAAHABFG8AAAAA4AIo3gAAAADABVC8AQAAAIALoHgDAAAAABdA8QYAAAAALoDiDQAAAABcAMUbAAAAALgAijcAAAAAcAFOLd7WrFmjli1bKjAwUBaLRfPnz7dZbozRkCFDVKZMGXl5ealp06bas2ePTZ+kpCS1b99ePj4+KlasmLp06aLTp0/b9NmyZYvCw8NVqFAhBQUFacyYMXm9awAAAADgUE4t3s6cOaNatWrpk08+yXH5mDFjNGHCBE2ZMkUbNmxQkSJFFBERofPnz1v7tG/fXtu3b1dsbKwWLlyoNWvWqFu3btblqampatasmYKDg7Vp0ya9//77GjZsmD777LM83z8AAAAAcBSLMcY4OwhJslgs+u677/Tkk09KunTULTAwUAMGDNBrr70mSUpJSZG/v79iYmLUrl077dy5UyEhIfr111913333SZKWLFmixx9/XH///bcCAwM1efJkvfnmm0pISJCHh4ck6fXXX9f8+fO1a9euXMWWmpoqX19fpaSkyMfHx/E7fwMsFmdH4Fz541OL2wk55ewIcDsir5wdAYC84MzaIN9e87Z//34lJCSoadOm1jZfX1/Vq1dP69evlyStX79exYoVsxZuktS0aVO5ublpw4YN1j4NGza0Fm6SFBERod27d+vkyZM5bjstLU2pqak2DwAAAABwpnxbvCUkJEiS/P39bdr9/f2tyxISElS6dGmb5QUKFFCJEiVs+uQ0xuXbuNLIkSPl6+trfQQFBd38DgEAAADATci3xZszRUdHKyUlxfo4fPiws0MCAAAAcIfLt8VbQECAJOnYsWM27ceOHbMuCwgIUGJios3yixcvKikpyaZPTmNcvo0reXp6ysfHx+YBAAAAAM6Ub4u3ChUqKCAgQCtWrLC2paamasOGDQoLC5MkhYWFKTk5WZs2bbL2WblypTIzM1WvXj1rnzVr1ig9Pd3aJzY2VlWqVFHx4sVv0d4AAAAAwM1xavF2+vRpxcfHKz4+XtKlSUri4+N16NAhWSwW9e3bV++8846+//57bd26VR07dlRgYKB1Rspq1arpscceU9euXbVx40atXbtWvXr1Urt27RQYGChJev755+Xh4aEuXbpo+/bt+vrrrzV+/Hj179/fSXsNAAAAAPZz6q0CVq9erYcffjhbe1RUlGJiYmSM0dChQ/XZZ58pOTlZDz30kCZNmqR77rnH2jcpKUm9evXSDz/8IDc3N7Vp00YTJkyQt7e3tc+WLVvUs2dP/frrrypVqpReffVVDR48ONdxcquA/Ifpl+Fo5JSzI8DtiLxydgQA8oIza4N8c5+3/IziLf/hUwtHI6ecHQFuR+SVsyMAkBe4zxsAAAAA4Joo3gAAAADABVC8AQAAAIALoHgDAAAAABdA8QYAAAAALoDiDQAAAABcAMUbAAAAALgAijcAAAAAcAEUbwAAAADgAijeAAAAAMAFULwBAAAAgAugeAMAAAAAF0DxBgAAAAAugOINAAAAAFwAxRsAAAAAuACKNwAAAABwARRvAAAAAOACKN4AAAAAwAVQvAEAAACAC6B4AwAAAAAXQPEGAAAAAC6A4g0AAAAAXADFGwAAAAC4AIo3AAAAAHABFG8AAAAA4AIo3gAAAADABVC8AQAAAIALoHgDAAAAABdA8QYAAAAALoDiDQAAAABcAMUbAAAAALgAijcAAAAAcAEUbwAAAADgAijeAAAAAMAF5OvibdiwYbJYLDaPqlWrWpefP39ePXv2VMmSJeXt7a02bdro2LFjNmMcOnRIkZGRKly4sEqXLq2BAwfq4sWLt3pXAAAAAOCmFHB2ANdTvXp1LV++3Pq8QIH/D7lfv35atGiR5syZI19fX/Xq1UutW7fW2rVrJUkZGRmKjIxUQECA1q1bp6NHj6pjx44qWLCg3nvvvVu+LwAAAABwo/J98VagQAEFBARka09JSdGXX36pWbNm6ZFHHpEkTZs2TdWqVdMvv/yi+vXra9myZdqxY4eWL18uf39/1a5dW2+//bYGDx6sYcOGycPD41bvDgAAAADckHx92qQk7dmzR4GBgapYsaLat2+vQ4cOSZI2bdqk9PR0NW3a1Nq3atWqKleunNavXy9JWr9+vWrWrCl/f39rn4iICKWmpmr79u1X3WZaWppSU1NtHgAAAADgTPm6eKtXr55iYmK0ZMkSTZ48Wfv371d4eLhOnTqlhIQEeXh4qFixYjbr+Pv7KyEhQZKUkJBgU7hlLc9adjUjR46Ur6+v9REUFOTYHQMAAAAAO+Xr0yabN29u/f/Q0FDVq1dPwcHB+uabb+Tl5ZVn242Ojlb//v2tz1NTUyngAAAAADhVvj7ydqVixYrpnnvu0d69exUQEKALFy4oOTnZps+xY8es18gFBARkm30y63lO19Fl8fT0lI+Pj80DAAAAAJzJpYq306dPa9++fSpTpozq1q2rggULasWKFdblu3fv1qFDhxQWFiZJCgsL09atW5WYmGjtExsbKx8fH4WEhNzy+AEAAADgRuXr0yZfe+01tWzZUsHBwTpy5IiGDh0qd3d3Pffcc/L19VWXLl3Uv39/lShRQj4+Pnr11VcVFham+vXrS5KaNWumkJAQdejQQWPGjFFCQoLeeust9ezZU56enk7eOwAAAADIvXxdvP3999967rnndOLECfn5+emhhx7SL7/8Ij8/P0nS2LFj5ebmpjZt2igtLU0RERGaNGmSdX13d3ctXLhQPXr0UFhYmIoUKaKoqCiNGDHCWbsEAAAAADfEYowxzg4iv0tNTZWvr69SUlLyzfVvFouzI3AuPrVwNHLK2RHgdkReOTsCAHnBmbWBS13zBgAAAAB3Koo3AAAAAHABFG8AAAAA4AIo3gAAAADABVC8AQAAAIALoHgDAAAAABdA8QYAAAAALoDiDQAAAABcAMUbAAAAALgAijcAAAAAcAEUbwAAAADgAijeAAAAAMAFULwBAAAAgAugeAMAAAAAF0DxBgAAAAAugOINAAAAAFwAxRsAAAAAuACKNwAAAABwARRvAAAAAOACKN4AAAAAwAVQvAEAAACAC6B4AwAAAAAXQPEGAAAAAC6A4g0AAAAAXADFGwAAAAC4AIo3AAAAAHABFG8AAAAA4AIo3gAAAADABVC8AQAAAIALoHgDAAAAABdA8QYAAAAALoDiDQAAAABcQAFnBwAAAADg+iwWZ0fgXMY4OwLn48gbAAAAALiAO6p4++STT1S+fHkVKlRI9erV08aNG50dEgAAAADkyh1TvH399dfq37+/hg4dqt9//121atVSRESEEhMTnR0aAAAAAFzXHVO8ffTRR+ratatefPFFhYSEaMqUKSpcuLCmTp3q7NAAAAAA4LruiAlLLly4oE2bNik6Otra5ubmpqZNm2r9+vXZ+qelpSktLc36PCUlRZKUmpqa98EiV3grAMcipwDHI68Ax8ovOZVVExgnzKByRxRv//77rzIyMuTv72/T7u/vr127dmXrP3LkSA0fPjxbe1BQUJ7FCPv4+jo7AuD2Qk4BjkdeAY6V33Lq1KlT8r3FQd0RxZu9oqOj1b9/f+vzzMxMJSUlqWTJkrLc6XO06tKvDUFBQTp8+LB8fHycHQ7g8sgpwPHIK8CxyKn/Z4zRqVOnFBgYeMu3fUcUb6VKlZK7u7uOHTtm037s2DEFBARk6+/p6SlPT0+btmLFiuVliC7Jx8fnjk9ewJHIKcDxyCvAscipS271Ebcsd8SEJR4eHqpbt65WrFhhbcvMzNSKFSsUFhbmxMgAAAAAIHfuiCNvktS/f39FRUXpvvvu0wMPPKBx48bpzJkzevHFF50dGgAAAABc1x1TvD377LM6fvy4hgwZooSEBNWuXVtLlizJNokJrs/T01NDhw7NdmopgBtDTgGOR14BjkVO5Q8W44w5LgEAAAAAdrkjrnkDAAAAAFdH8QYAAAAALoDiDQAAAABcAMVbHipfvrzGjRvn7DBczoEDB2SxWBQfH5/n2+I9cj28ZzeGvMLV8H7dGHIK18J7dmPIq1wwt7moqCgjyXTv3j3bsldeecVIMlFRUbkaa//+/UaS2bx5c676JyYmmjNnzuSqb4sWLUxERESOy9asWWMkmT/++CNXY13NqlWrjCRz8uTJmxrnSmfPnjXFixc3JUuWNOfPn7dr3aioKNOqVSubtosXL5qjR4+a9PR0h8U4bdo04+vrm63dnvfIUSZOnGiCg4ONp6eneeCBB8yGDRtu6fYdgbz6f+SVb7b2W51XcXFxpkWLFqZMmTJGkvnuu+9u2bYdhZz6f+SUb7b2W51T7733nrnvvvuMt7e38fPzM61atTK7du26Zdt3FPLq/5FXvtnab3VeTZo0ydSsWdMULVrUFC1a1NSvX9/8+OOPdo9zRxx5CwoK0uzZs3Xu3Dlr2/nz5zVr1iyVK1fO4du7cOGCJMnPz0+FCxfO1TpdunRRbGys/v7772zLpk2bpvvuu0+hoaEOjfNGGWN08eJF6/N58+apevXqqlq1qubPn3/T47u7uysgIEAFCuT9nSzseY8c4euvv1b//v01dOhQ/f7776pVq5YiIiKUmJh4y2JwFPLKscirG3fmzBnVqlVLn3zyyS3bZl4gpxyLnLpxcXFx6tmzp3755RfFxsYqPT1dzZo105kzZ25ZDI5CXjkWeXXjypYtq1GjRmnTpk367bff9Mgjj6hVq1bavn27fQM5uKjMd7Kq+ho1apj//e9/1vaZM2ea0NBQ06pVK+uvLosXLzYNGjQwvr6+pkSJEiYyMtLs3bvXuo4km0ejRo1stvHOO++YMmXKmPLlyxtjjAkODjZjx441xlz6xaNgwYJmzZo11vFGjx5t/Pz8TEJCgklPTzf+/v7m7bffton/1KlTxtvb20yePNkYY8xPP/1kHnroIVOoUCFTtmxZ8+qrr5rTp09b+58/f94MGjTIlC1b1nh4eJhKlSqZL774wvqL0eWPrP0+f/68efXVV42fn5/x9PQ0DRo0MBs3brSOmfVrzY8//mjq1KljChYsaFatWmVd3rhxYzNlyhQzefJk8+ijj2Z7D7Zt22YiIyNN0aJFjbe3t3nooYfM3r17zdChQ7PFtGrVKptftzIyMsxdd91lJk2aZDPm77//biwWizlw4IAxxpgPP/zQ1KhRwxQuXNiULVvW9OjRw5w6dcom/ssfQ4cOzfYeGWPMwYMHzRNPPGGKFCliihYtap5++mmTkJBgXT506FBTq1YtM2PGDBMcHGx8fHzMs88+a1JTU7Ptd04eeOAB07NnT+vzjIwMExgYaEaOHJmr9fML8oq8yk95dTm58JE3coqcyo85ZcylIxSSTFxc3A2t7yzkFXmVn/PKGGOKFy9uvvjiC7vWuWOKt48++sg0adLE2t6kSRMzduxYm8SdO3eumTdvntmzZ4/ZvHmzadmypalZs6bJyMgwxhizceNGI8ksX77cHD161Jw4ccK6DW9vb9OhQwezbds2s23bNmNM9g/FwIEDTXBwsElOTja///678fDwMAsWLLBZXqlSJZOZmWltmzp1qvHy8jLJyclm7969pkiRImbs2LHmzz//NGvXrjX33nuv6dSpk7X/M888Y4KCgsy3335r9u3bZ5YvX25mz55tLl68aObNm2ckmd27d5ujR4+a5ORkY4wxvXv3NoGBgebHH38027dvN1FRUaZ48eLW/cv64IeGhpply5aZvXv3Wpft3bvXeHp6mqSkJHPixAlTqFAhazIZY8zff/9tSpQoYVq3bm1+/fVXs3v3bjN16lSza9cuc+rUKfPMM8+Yxx57zBw9etQcPXrUpKWlZTs14bXXXjMPPfSQzfs6YMAAm7axY8ealStXmv3795sVK1aYKlWqmB49ehhjjElLSzPjxo0zPj4+1u1kJfXl71FGRoapXbu2eeihh8xvv/1mfvnlF1O3bl3rF7QxlxLX29vbtG7d2mzdutWsWbPGBAQEmDfeeOOqn8EsaWlpxt3dPdsflh07djRPPPHEddfPT8gr8iq/5NWVXL14I6fIqfyWU8YYs2fPHiPJbN269YbWdxbyirzKr3l18eJF89VXXxkPDw+zfft2u9a9Y4q3xMRE4+npaQ4cOGAOHDhgChUqZI4fP26TuFc6fvy4zZfV1c53joqKMv7+/iYtLc2m/crETUtLM7Vr1zbPPPOMCQkJMV27drXpv3PnTusvD1nCw8PNCy+8YIwxpkuXLqZbt2426/z000/Gzc3NnDt3zuzevdtIMrGxsTnuT07nO58+fdoULFjQzJw509p24cIFExgYaMaMGWOz3vz587ON+cYbb5gnn3zS+rxVq1bWXzSMMSY6OtpUqFDBXLhwIceYcjrf+crXefPmzcZisZiDBw8aY4z1l5isX6JyMmfOHFOyZEnr86ud73z5e7Rs2TLj7u5uDh06ZF2+fft2I8n6K9TQoUNN4cKFbX5lGThwoKlXr95VY8nyzz//GElm3bp1Nu0DBw40DzzwwHXXz0/Iq/9HXvlm63cr8+pKrl68kVPkVH7LqYyMDBMZGWkaNGhg97rORl79P/LKN1s/Z+TVli1bTJEiRYy7u7vx9fU1ixYtyvW6We6Ia96kS+e1RkZGKiYmRtOmTVNkZKRKlSpl02fPnj167rnnVLFiRfn4+Kh8+fKSpEOHDl13/Jo1a8rDw+OafTw8PDRz5kzNmzdP58+f19ixY22WV61aVQ8++KCmTp0qSdq7d69++ukndenSRZL0xx9/KCYmRt7e3tZHRESEMjMztX//fsXHx8vd3V2NGjXK7cuiffv2KT09XQ0aNLC2FSxYUA888IB27txp0/e+++6zeZ6RkaHp06frhRdesLa98MILiomJUWZmpiQpPj5e4eHhKliwYK5julLt2rVVrVo1zZo1S9Klc/ETExP19NNPW/ssX75cTZo00V133aWiRYuqQ4cOOnHihM6ePZvr7ezcuVNBQUEKCgqytoWEhKhYsWI2r0X58uVVtGhR6/MyZcq45DVrjkBe5Yy8+n/klX3IqZyRU//vVudUz549tW3bNs2ePdvudfML8ipn5NX/u1V5VaVKFcXHx2vDhg3q0aOHoqKitGPHjlyvL91htwro3LmzYmJiNH36dHXu3Dnb8pYtWyopKUmff/65NmzYoA0bNkj6/4tPr6VIkSK5imHdunWSpKSkJCUlJWVb3qVLF82bN0+nTp3StGnTVKlSJWsinj59Wt27d1d8fLz18ccff2jPnj2qVKmSvLy8chXDjbpyH5cuXap//vlHzz77rAoUKKACBQqoXbt2OnjwoFasWCFJDoupffv21sSdNWuWHnvsMZUsWVLSpWllW7RoodDQUM2bN0+bNm2yTlyQm/fOXld+CVksFusX1bWUKlVK7u7uOnbsmE37sWPHFBAQ4NAYbyXy6uaQV5fcaF7djsipm0NOXeKInOrVq5cWLlyoVatWqWzZso4M75Yjr24OeXXJzeaVh4eHKleurLp162rkyJGqVauWxo8fb1cMd1Tx9thjj+nChQtKT09XRESEzbITJ05o9+7deuutt9SkSRNVq1ZNJ0+etOmT9atKRkbGDW1/37596tevnz7//HPVq1dPUVFR2d7wZ555Rm5ubpo1a5ZmzJihzp07y2KxSJLq1KmjHTt2qHLlytkeHh4eqlmzpjIzMxUXF5fj9nOKv1KlSvLw8NDatWutbenp6fr1118VEhJyzf358ssv1a5dO5svkvj4eLVr105ffvmlJCk0NFQ//fST0tPTrxpTbl7P559/Xtu2bdOmTZs0d+5ctW/f3rps06ZNyszM1Icffqj69evrnnvu0ZEjR+zeTrVq1XT48GEdPnzY2rZjxw4lJydf97XIDQ8PD9WtW9f6pSZJmZmZWrFihcLCwm56fGchr8ira8nrvLodkVPk1LXcipwyxqhXr1767rvvtHLlSlWoUMEh4zoTeUVeXYuz/q3KzMxUWlqafSvZfaKli7nyfNqUlBSTkpJifZ51vnNGRoYpWbKkeeGFF8yePXvMihUrzP33329z/UR6errx8vIy77zzjklISLBe7JnTObvG2J5Le/HiRVO/fn3Tpk0bY4wxR44cMSVLlrSeU3y5Ll26mOLFixt3d3fzzz//WNv/+OMP4+XlZXr27Gk2b95s/vzzTzN//nyb2Qs7depkgoKCzHfffWf++usvs2rVKvP1118bYy5dOGqxWExMTIxJTEy0XrDZp08fExgYaBYvXmxzsWpSUpIxJufzpBMTE03BggXN4sWLs8X/448/Gk9PT3PixAnz77//mpIlS1ovVv3zzz/NjBkzrPeLeffdd025cuXMrl27zPHjx82FCxeuel55gwYNTK1atUzRokXN2bNnre3x8fFGkhk3bpzZt2+fmTFjhrnrrrtsYl67dq31QuPjx49b7+tx+XuUmZlpateubcLDw82mTZvMhg0bcrxYtVatWjZxjR071gQHB2d7HXIye/Zs4+npaWJiYsyOHTtMt27dTLFixWxmM3IF5BV5ZUz+yatTp06ZzZs3m82bNxtJ5qOPPjKbN2+2XiPhCsgpcsqY/JNTPXr0ML6+vmb16tXWSR6OHj1qsz+ugLwir4zJP3n1+uuvm7i4OLN//36zZcsW8/rrrxuLxWKWLVuWq/Wz3HHF25Uuv1g1NjbWVKtWzXh6eprQ0FCzevXqbBe/f/755yYoKMi4ubllmyb2Spd/KIYPH27KlClj/v33X+vyefPmGQ8PDxMfH2+z3rp164wk8/jjj2cbc+PGjebRRx813t7epkiRIiY0NNS8++671uXnzp0z/fr1M2XKlDEeHh6mcuXKZurUqdblI0aMMAEBAcZisVj3+9y5c+bVV181pUqVuuY0sZcn7gcffGCKFSuW40WoaWlpplixYmb8+PHGmEtfOM2aNTOFCxc2RYsWNeHh4Wbfvn3GmEtfAFn7oxymib3cpEmTjCTTsWPHbNv86KOPTJkyZYyXl5eJiIgwM2bMyBbzyy+/bEqWLOmQaWIvZ0/iGmPMxx9/bMqVK2c8PDzMAw88YH755Zdcr5tfkFfkVZb8kFc5TQUt5f7mu/kBOUVOZckPOZVTPkky06ZNy9X6+QV5RV5lyQ951blzZxMcHGw8PDyMn5+fadKkid2FmzHGWIwxxr5jdQAAAACAW+2OuuYNAAAAAFwVxRvgIIcOHbKZwvfKR26mGwZgi7wCHIucAhzvVuYVp00CDnLx4kUdOHDgqsvLly+vAgUK3LqAgNsAeQU4FjkFON6tzCuKNwAAAABwAZw2CQAAAAAugOINAAAAAFwAxRsAAAAAuACKNwAAAABwARRvAADkUuPGjdW3b99c91+9erUsFouSk5PzLCYAwJ2D4g0AkOc6deoki8WiUaNG2bTPnz9fFovFrrHKly+vcePGOTA6AABcA8UbAOCWKFSokEaPHq2TJ086OxS7Xbhwwdkh3JT09HRnhwAAcACKNwDALdG0aVMFBARo5MiR1+z3888/Kzw8XF5eXgoKClLv3r115swZSZdOWzx48KD69esni8Uii8UiY4z8/Pw0d+5c6xi1a9dWmTJlbMb09PTU2bNnJUmHDh1Sq1at5O3tLR8fHz3zzDM6duyYtf+wYcNUu3ZtffHFF6pQoYIKFSqUY6yLFi2Sr6+vZs6cmavX4MSJE3ruued01113qXDhwqpZs6a++uor6/IZM2aoZMmSSktLs1nvySefVIcOHazPFyxYoDp16qhQoUKqWLGihg8frosXL1qXWywWTZ48WU888YSKFCmid999VydPnlT79u3l5+cnLy8v3X333Zo2bVqu4gYA5A8UbwCAW8Ld3V3vvfeePv74Y/3999859tm3b58ee+wxtWnTRlu2bNHXX3+tn3/+Wb169ZIkffvttypbtqxGjBiho0eP6ujRo7JYLGrYsKFWr14tSTp58qR27typc+fOadeuXZKkuLg43X///SpcuLAyMzPVqlUrJSUlKS4uTrGxsfrrr7/07LPP2sSyd+9ezZs3T99++63i4+OzxTpr1iw999xzmjlzptq3b5+r1+D8+fOqW7euFi1apG3btqlbt27q0KGDNm7cKEl6+umnlZGRoe+//966TmJiohYtWqTOnTtLkn766Sd17NhRffr00Y4dO/Tpp58qJiZG7777rs22hg0bpqeeekpbt25V586d9Z///Ec7duzQ4sWLtXPnTk2ePFmlSpXKVdwAgHzCAACQx6KiokyrVq2MMcbUr1/fdO7c2RhjzHfffWcu/6eoS5cuplu3bjbr/vTTT8bNzc2cO3fOGGNMcHCwGTt2rE2fCRMmmOrVqxtjjJk/f76pV6+eadWqlZk8ebIxxpimTZuaN954wxhjzLJly4y7u7s5dOiQdf3t27cbSWbjxo3GGGOGDh1qChYsaBITE22206hRI9OnTx8zceJE4+vra1avXn3N/V61apWRZE6ePHnVPpGRkWbAgAHW5z169DDNmze3Pv/www9NxYoVTWZmpjHGmCZNmpj33nvPZoz//ve/pkyZMtbnkkzfvn1t+rRs2dK8+OKL14wXAJC/ceQNAHBLjR49WtOnT9fOnTuzLfvjjz8UExMjb29v6yMiIkKZmZnav3//Vcds1KiRduzYoePHjysuLk6NGzdW48aNtXr1aqWnp2vdunVq3LixJGnnzp0KCgpSUFCQdf2QkBAVK1bMJqbg4GD5+fll29bcuXPVr18/xcbGqlGjRnbte0ZGht5++23VrFlTJUqUkLe3t5YuXapDhw5Z+3Tt2lXLli3TP//8I0mKiYmxTviS9RqNGDHC5jXq2rWrjh49aj0tVJLuu+8+m2336NFDs2fPVu3atTVo0CCtW7fOrtgBAM5H8QYAuKUaNmyoiIgIRUdHZ1t2+vRpde/eXfHx8dbHH3/8oT179qhSpUpXHTOrGIqLi7Mp3uLi4vTrr78qPT1dDz74oF1xFilSJMf2e++9V35+fpo6daqMMXaN+f7772v8+PEaPHiwVq1apfj4eEVERNhMiHLvvfeqVq1amjFjhjZt2qTt27erU6dO1uWnT5/W8OHDbV6jrVu3as+ePTbX5l0Zf/Pmza3XCx45ckRNmjTRa6+9Zlf8AADnKuDsAAAAd55Ro0apdu3aqlKlik17nTp1tGPHDlWuXPmq63p4eCgjI8OmzWKxKDw8XAsWLND27dv10EMPqXDhwkpLS9Onn36q++67z1rMVKtWTYcPH9bhw4etR9927Nih5ORkhYSEXDf2SpUq6cMPP1Tjxo3l7u6uiRMn5nq/165dq1atWumFF16QJGVmZurPP//Mtt2XXnpJ48aN0z///KOmTZvaHCWsU6eOdu/efc3X6Gr8/PwUFRWlqKgohYeHa+DAgfrggw/sHgcA4BwceQMA3HI1a9ZU+/btNWHCBJv2wYMHa926derVq5fi4+O1Z88eLViwwDphiXTpPm9r1qzRP//8o3///dfa3rhxY3311VeqXbu2vL295ebmpoYNG2rmzJk2pzc2bdrUuv3ff/9dGzduVMeOHdWoUaNspxpezT333KNVq1Zp3rx5dt20++6771ZsbKzWrVunnTt3qnv37jazXGZ5/vnn9ffff+vzzz+3TlSSZciQIZoxY4aGDx+u7du3a+fOnZo9e7beeuuta257yJAhWrBggfbu3avt27dr4cKFqlatWq5jBwA4H8UbAMApRowYoczMTJu20NBQxcXF6c8//1R4eLjuvfdeDRkyRIGBgTbrHThwQJUqVbK5Jq1Ro0bKyMiwXtsmXSrormyzWCxasGCBihcvroYNG6pp06aqWLGivv76a7vir1KlilauXKmvvvpKAwYMyNU6b731lurUqaOIiAg1btxYAQEBevLJJ7P18/X1VZs2beTt7Z1teUREhBYuXKhly5bp/vvvV/369TV27FgFBwdfc9seHh6Kjo5WaGioGjZsKHd3d82ePTu3uwsAyAcsxt4T9gEAQJ5r0qSJqlevnu3oJADgzkXxBgBAPnLy5EmtXr1abdu21Y4dO7JdFwgAuHMxYQkAAPnIvffeq5MnT2r06NEUbgAAGxx5AwAAAAAXwIQlAAAAAOACKN4AAAAAwAVQvAEAAACAC6B4AwAAAAAXQPEGAAAAAC6A4g0AAAAAXADFGwAAAAC4AIo3AAAAAHAB/wdjk8kS8Ch0wAAAAABJRU5ErkJggg==", - "text/plain": [ - "
    " - ] - }, - "metadata": {}, - "output_type": "display_data" - } - ], + "outputs": [], "source": [ "fig = plt.figure(figsize = (10, 5))\n", "plt.bar(cycles_dict_updated.keys(), cycles_dict_updated.values(), color ='blue', width = 0.3)\n", "plt.xlabel(\"Network layers\")\n", "plt.ylabel(\"Number of clock cycles\")\n", - "plt.title(\"Estimated no. of clock cycles for each network layer\")\n", + "plt.title(\"Clock cycles per layer with updated folding factors\")\n", "plt.show()" ] }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "This has of course consequences for the resource usage of the network." + ] + }, { "cell_type": "code", - "execution_count": 14, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "data": { - "text/plain": [ - "{'MatrixVectorActivation_0': {'BRAM_18K': 8,\n", - " 'BRAM_efficiency': 0.5208333333333334,\n", - " 'LUT': 418,\n", - " 'URAM': 0,\n", - " 'URAM_efficiency': 1,\n", - " 'DSP': 0},\n", - " 'MatrixVectorActivation_1': {'BRAM_18K': 1,\n", - " 'BRAM_efficiency': 0.4444444444444444,\n", - " 'LUT': 320,\n", - " 'URAM': 0,\n", - " 'URAM_efficiency': 1,\n", - " 'DSP': 0},\n", - " 'MatrixVectorActivation_2': {'BRAM_18K': 1,\n", - " 'BRAM_efficiency': 0.4444444444444444,\n", - " 'LUT': 320,\n", - " 'URAM': 0,\n", - " 'URAM_efficiency': 1,\n", - " 'DSP': 0},\n", - " 'MatrixVectorActivation_3': {'BRAM_18K': 1,\n", - " 'BRAM_efficiency': 0.006944444444444444,\n", - " 'LUT': 320,\n", - " 'URAM': 0,\n", - " 'URAM_efficiency': 1,\n", - " 'DSP': 0}}" - ] - }, - "execution_count": 14, - "metadata": {}, - "output_type": "execute_result" - } - ], + "outputs": [], "source": [ "res_dict_updated = model.analysis(res_estimation)\n", "res_dict_updated" @@ -589,20 +363,9 @@ }, { "cell_type": "code", - "execution_count": 16, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "data": { - "image/png": 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GRoaSk5Ot05uWL1+uYcOGaeXKlTpz5oxT/+TkZGtdl7Nr1y5t2rRJRYsWzXZ+5g0Y/vjjDxUrVkw+Pj5O8+++++6r7F3+yq9b4BcpUkSNGzfW119/rZEjR0q6cBqjq6ur2rVrZ/XLvEZo3Lhx2rNnj9LT0615OTnFLCd27dql5ORkBQUFZTs/8zWIjo5W+/btNXz4cI0ePVqNGjXSgw8+qMcff1weHh75UsuIESPUtm1bVaxYUVWrVlXz5s3VuXNnRURESJJ2794tY4yGDBmiIUOGXLbeEiVK6I8//lDt2rWzzL+W98wff/xx2XVUqlRJP//8s1Obq6urSpYsedX1HjlyRCdOnNCECRM0YcKEbPtkvg6SNHnyZL3zzjvavn27U0i++K6uiYmJKl68uAIDA6+6/Us/AySpUKFCWa4xzOnyhQoVkiRr+cygfaVTj5OTk63lsuPi4qKoqCgtW7ZM0oVg1qBBA9WvX1/p6elatWqVgoODdezYMadgdrn3QeYp3n/88YeqVq1qtWd3Z9xMnTt3lqurq7Zt26aQkJDL9ruaffv2aejQofr222+zPMcXf6HVtGlTFStWTFOmTFHjxo2VkZGhL7/8Um3btpWvr6+kvD23V9pHALlDMAPuUEFBQdq4caPmz5+vefPmad68eZo4caK6dOmiyZMn53m9Li4uuWo3//+ahMTERDVu3FiVKlXSu+++q9DQULm7u+v777/X6NGjc3SThYyMDDVt2lQvvPBCtvMrVqyYw724dh4eHk4X318sM3RefJTkWnXs2FHdunXTxo0bFRkZqa+//lqNGze2rquRLlzkP2TIEHXv3l0jR45UYGCgChQooOeff/6qz6/D4cj2+pGLw5104TUICgrSlClTsl1PZmjO/B24VatW6bvvvtP8+fPVvXt3vfPOO1q1alWW0JwTl9bSsGFDJSYm6ptvvtGPP/6oTz75RKNHj9aHH36oJ5980trnAQMGKCYmJtt15ubnJa63i494Xknmfj3xxBOX/Qd2Zjj94osv1LVrVz344IMaOHCggoKC5OLiovj4eCUmJuapzquN9WtdPnP/3nrrLadr4C6Wk/dP/fr1NWrUKJ09e1bLli3Tv/71LwUEBKhq1apatmyZde3qxcEst650DWK7du30+eef67333lN8fHye1p+enm5dn/biiy+qUqVK8vb21l9//aWuXbs6jWsXFxc9/vjj+vjjjzVu3DgtX75cBw4ccLr7a16e25xcZwkgZwhmwB3M3d1dbdq0UZs2bZSRkaFnnnlGH330kYYMGaIKFSrc0B81/u6775Samqpvv/3W6Rvz7O4Od7m6ypcvr1OnTl31d6JKly6thQsX6tSpU07/yMjt3dCuto3LrS+zPa+nLmXnwQcfVK9evazTGXfu3KnBgwc79ZkxY4buu+8+ffrpp07tJ06ccApw2SlUqFC2p6JlHvXJVL58ef3000+qV69ejv7BVqdOHdWpU0ejRo3S1KlT1alTJ02bNk1PPvnkFWu59A6a586d08GDB7P0DQwMVLdu3dStWzedOnVKDRs21CuvvKInn3xS5cqVkyS5ubnl6D2T3SmR1/KeyXz9d+zYofvvvz/LevP6/ihatKh8fX2Vnp5+1f2aMWOGypUrp1mzZjmNq0tPWSxfvrzmz5+vY8eO5eio2fWUeZqkn5/fVffvSp9hDRo00Llz5/Tll1/qr7/+sgJYw4YNrWBWsWJFK6BJlx/X27dvt+bnVN++fVWhQgUNHTpU/v7+GjRoUI6XzbR582bt3LlTkydPVpcuXaz2y52i3qVLF73zzjv67rvvNG/ePBUtWtTpS4ncPLcA8h/XmAF3qKNHjzo9LlCggPUteuZt7DN/j+ZG3EY+81vyi79VT05O1sSJE7P09fb2zramDh06aOXKlZo/f36WeSdOnLCuZ2vZsqXS0tKcbsWfnp6uDz744Fp3w9KyZUutWrVK69aty1LHlClTFBkZeU2nL10qICBAMTEx+vrrrzVt2jS5u7vrwQcfdOrj4uKS5ajF9OnTs9yaPTvly5fX9u3bdeTIEavt119/zXIL7Q4dOig9Pd06pfJiaWlp1ut2/PjxLLVkfkN/6c8oZFdL5rVBmSZMmJDliNml73EfHx9VqFDBWn9QUJAaNWqkjz76KNtQd/G+Zr6ev/zyi9P8yx0ZzImaNWsqKChIH374odM+z5s3T9u2bVOrVq3ytF4XFxe1b99eM2fO1G+//ZZl/sX7ld24W716tVauXOm0TPv27WWMyfZnGXJ6JCy/1KhRQ+XLl9fbb7+tU6dOZZl/8f5d6TOsdu3acnNz0xtvvKHAwEBVqVJF0oXAtmrVKiUkJGQ5WtayZUv98ssvTs/P6dOnNWHCBJUpU0ZhYWG52pchQ4ZowIABGjx4cJafBsmJ7F4/Y4z1syeXioiIUEREhD755BPNnDlTHTt2lKvr/76jz81zCyD/ccQMuE3NmzfP+hb3YnXr1lW5cuX05JNP6tixY7r//vtVsmRJ/fHHH/rggw8UGRlpXS8RGRkpFxcXvfHGG0pOTpaHh4f1O2P5rVmzZtYRvF69eunUqVP6+OOPFRQUlOUfzTVq1ND48eP16quvqkKFCgoKCtL999+vgQMH6ttvv1Xr1q3VtWtX1ahRQ6dPn9bmzZs1Y8YM7d27V0WKFFGbNm1Ur149DRo0SHv37lVYWJhmzZqVoxuMXGzmzJnZPsexsbEaNGiQpk+froYNG6pXr16qVKmSDhw4oEmTJungwYPZBs5r9eijj+qJJ57QuHHjFBMTk+XHjFu3bq0RI0aoW7duqlu3rjZv3qwpU6ZYR46upHv37nr33XcVExOjHj166PDhw/rwww9VpUoVp99mio6OVq9evRQfH6+NGzeqWbNmcnNz065duzR9+nS99957evjhhzV58mSNGzdODz30kMqXL6+TJ0/q448/lp+fn1q2bHnFWp588kk9/fTTat++vZo2bapff/1V8+fPz3LULywsTI0aNVKNGjUUGBiotWvXasaMGerTp4/VZ+zYsapfv77Cw8PVs2dPlStXTocOHdLKlSv1559/Wr/x9sILL+g///mPmjdvrueee866XX7p0qW1adOmqz5/2ckMBd26dVN0dLQee+wx63b5ZcqUUb9+/fK0XunCLecXL16s2rVrq2fPngoLC9OxY8e0fv16/fTTTzp27JikC++JWbNm6aGHHlKrVq20Z88effjhhwoLC3P6h/l9992nzp076/3339euXbvUvHlzZWRkaNmyZbrvvvucntPrrUCBAvrkk0/UokULValSRd26dVOJEiX0119/afHixfLz89N3330n6cJnhXThJws6duwoNzc3tWnTRt7e3ipYsKBq1KihVatWWb9hJl04Ynb69GmdPn06SzAbNGiQvvzyS7Vo0ULPPvusAgMDNXnyZO3Zs0czZ87M0amml3rrrbeUnJysuLg4+fr65uqH5StVqqTy5ctrwIAB+uuvv+Tn56eZM2de8Xq+Ll26aMCAAZKUZVu5eW4BXAc3+jaQAK6vK90uXxfdFnnGjBmmWbNmJigoyLi7u5tSpUqZXr16mYMHDzqt7+OPPzblypUzLi4uTrdpvtzt8i+9hXx2twk35n+3Wj5y5IjV9u2335qIiAjj6elpypQpY9544w3z2WefZbnddVJSkmnVqpXx9fU1kpzqOHnypBk8eLCpUKGCcXd3N0WKFDF169Y1b7/9ttNt/I8ePWo6d+5s/Pz8jL+/v+ncubPZsGFDrm6Xf7kp81baf/75p3nyySdNiRIljKurqwkMDDStW7c2q1atuuL6c3u7/EwpKSnGy8vLSDJffPFFlvlnz541//d//2eKFStmvLy8TL169czKlSuzvJbZ3S7fGGO++OILU65cOePu7m4iIyPN/Pnzs9wuP9OECRNMjRo1jJeXl/H19TXh4eHmhRdeMAcOHDDGXLhN92OPPWZKlSplPDw8TFBQkGndurVZu3btVfczPT3dvPjii6ZIkSKmYMGCJiYmxuzevTvL7fJfffVVU6tWLRMQEGC8vLxMpUqVzKhRo5zeB8YYk5iYaLp06WJCQkKMm5ubKVGihGndurWZMWOGU79NmzaZ6Oho4+npaUqUKGFGjhxpPv300zzfLj/TV199ZapXr248PDxMYGCg6dSpk/nzzz+d+sTGxhpvb++rPjcXO3TokImLizOhoaHGzc3NhISEmMaNG5sJEyZYfTIyMsxrr71mSpcubTw8PEz16tXN3Llzs31d09LSzFtvvWUqVapk3N3dTdGiRU2LFi3MunXrrD66zM9EXPraZOdynyGXez9u2LDBtGvXzhQuXNh4eHiY0qVLmw4dOpiFCxc69Rs5cqQpUaKEKVCgQJbXauDAgUaSeeONN5yWqVChgpFkEhMTs9SZmJhoHn74YRMQEGA8PT1NrVq1zNy5c3O0L8Zk/15IT083jz32mHF1dTVz5sy56nN08e3yt27dapo0aWJ8fHxMkSJFTM+ePa2fKMjus+zgwYPGxcXFVKxY8bLbyclzm91nOIBr4zCGXwMEAAC4E/z9998qVqyYhg4detm7kQKwB9eYAQAA3CEmTZqk9PR0de7c2e5SAFyCa8wAAABuc4sWLdLWrVs1atQoPfjggypTpozdJQG4BKcyAgAA3OYaNWqkFStWqF69evriiy9UokQJu0sCcAmCGQAAAADYjGvMAAAAAMBmBDMAAAAAsBk3/5CUkZGhAwcOyNfX1/qBSQAAAAB3HmOMTp48qeLFi+fph+PzimAm6cCBAwoNDbW7DAAAAAA3if3796tkyZI3bHsEM0m+vr6SLjz5fn5+NlcDAAAAwC4pKSkKDQ21MsKNQjCTrNMX/fz8CGYAAAAAbvglTtz8AwAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZq52F4CsHMMddpdgKzPM2F0CAAAAcENxxAwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZjdNMHv99dflcDj0/PPPW21nz55VXFycChcuLB8fH7Vv316HDh1yWm7fvn1q1aqVChYsqKCgIA0cOFBpaWk3uHoAAAAAyLubIpitWbNGH330kSIiIpza+/Xrp++++07Tp09XQkKCDhw4oHbt2lnz09PT1apVK507d04rVqzQ5MmTNWnSJA0dOvRG7wIAAAAA5JntwezUqVPq1KmTPv74YxUqVMhqT05O1qeffqp3331X999/v2rUqKGJEydqxYoVWrVqlSTpxx9/1NatW/XFF18oMjJSLVq00MiRIzV27FidO3fOrl0CAAAAgFyxPZjFxcWpVatWatKkiVP7unXrdP78eaf2SpUqqVSpUlq5cqUkaeXKlQoPD1dwcLDVJyYmRikpKdqyZctlt5mamqqUlBSnCQAAAADs4mrnxqdNm6b169drzZo1WeYlJSXJ3d1dAQEBTu3BwcFKSkqy+lwcyjLnZ867nPj4eA0fPvwaqwcAAACA/GHbEbP9+/frueee05QpU+Tp6XlDtz148GAlJydb0/79+2/o9gEAAADgYrYFs3Xr1unw4cO655575OrqKldXVyUkJOj999+Xq6urgoODde7cOZ04ccJpuUOHDikkJESSFBISkuUujZmPM/tkx8PDQ35+fk4TAAAAANjFtmDWuHFjbd68WRs3brSmmjVrqlOnTtbfbm5uWrhwobXMjh07tG/fPkVFRUmSoqKitHnzZh0+fNjqs2DBAvn5+SksLOyG7xMAAAAA5IVt15j5+vqqatWqTm3e3t4qXLiw1d6jRw/1799fgYGB8vPzU9++fRUVFaU6depIkpo1a6awsDB17txZb775ppKSkvTyyy8rLi5OHh4eN3yfAAAAACAvbL35x9WMHj1aBQoUUPv27ZWamqqYmBiNGzfOmu/i4qK5c+eqd+/eioqKkre3t2JjYzVixAgbqwYAAACA3HEYY4zdRdgtJSVF/v7+Sk5OvimuN3MMd9hdgq3MsDv+LQkAAACb2JUNbP8dMwAAAAC40xHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACb2RrMxo8fr4iICPn5+cnPz09RUVGaN2+eNb9Ro0ZyOBxO09NPP+20jn379qlVq1YqWLCggoKCNHDgQKWlpd3oXQEAAACAPHO1c+MlS5bU66+/rrvuukvGGE2ePFlt27bVhg0bVKVKFUlSz549NWLECGuZggULWn+np6erVatWCgkJ0YoVK3Tw4EF16dJFbm5ueu211274/gAAAABAXtgazNq0aeP0eNSoURo/frxWrVplBbOCBQsqJCQk2+V//PFHbd26VT/99JOCg4MVGRmpkSNH6sUXX9Qrr7wid3f3674PAAAAAHCtbpprzNLT0zVt2jSdPn1aUVFRVvuUKVNUpEgRVa1aVYMHD9aZM2eseStXrlR4eLiCg4OttpiYGKWkpGjLli2X3VZqaqpSUlKcJgAAAACwi61HzCRp8+bNioqK0tmzZ+Xj46PZs2crLCxMkvT444+rdOnSKl68uDZt2qQXX3xRO3bs0KxZsyRJSUlJTqFMkvU4KSnpstuMj4/X8OHDr9MeAQAAAEDu2B7M7r77bm3cuFHJycmaMWOGYmNjlZCQoLCwMD311FNWv/DwcBUrVkyNGzdWYmKiypcvn+dtDh48WP3797cep6SkKDQ09Jr2AwAAAADyyvZTGd3d3VWhQgXVqFFD8fHxqlatmt57771s+9auXVuStHv3bklSSEiIDh065NQn8/HlrkuTJA8PD+tOkJkTAAAAANjF9mB2qYyMDKWmpmY7b+PGjZKkYsWKSZKioqK0efNmHT582OqzYMEC+fn5WadDAgAAAMDNztZTGQcPHqwWLVqoVKlSOnnypKZOnaolS5Zo/vz5SkxM1NSpU9WyZUsVLlxYmzZtUr9+/dSwYUNFRERIkpo1a6awsDB17txZb775ppKSkvTyyy8rLi5OHh4edu4aAAAAAOSYrcHs8OHD6tKliw4ePCh/f39FRERo/vz5atq0qfbv36+ffvpJY8aM0enTpxUaGqr27dvr5ZdftpZ3cXHR3Llz1bt3b0VFRcnb21uxsbFOv3sGAAAAADc7hzHG2F2E3VJSUuTv76/k5OSb4nozx3CH3SXYygy749+SAAAAsIld2eCmu8YMAAAAAO40BDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbOZqdwEAcL05hjvsLsFWZpixuwTchhhXjCvkL8YUY4ojZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM1uD2fjx4xURESE/Pz/5+fkpKipK8+bNs+afPXtWcXFxKly4sHx8fNS+fXsdOnTIaR379u1Tq1atVLBgQQUFBWngwIFKS0u70bsCAAAAAHlmazArWbKkXn/9da1bt05r167V/fffr7Zt22rLli2SpH79+um7777T9OnTlZCQoAMHDqhdu3bW8unp6WrVqpXOnTunFStWaPLkyZo0aZKGDh1q1y4BAAAAQK45jDHG7iIuFhgYqLfeeksPP/ywihYtqqlTp+rhhx+WJG3fvl2VK1fWypUrVadOHc2bN0+tW7fWgQMHFBwcLEn68MMP9eKLL+rIkSNyd3fPdhupqalKTU21HqekpCg0NFTJycny8/O7/jt5FY7hDrtLsJUZdlO9JXEbYEwxppD/GFeMK+QvxtTNM6ZSUlLk7+9/w7PBTXONWXp6uqZNm6bTp08rKipK69at0/nz59WkSROrT6VKlVSqVCmtXLlSkrRy5UqFh4dboUySYmJilJKSYh11y058fLz8/f2tKTQ09PrtGAAAAABche3BbPPmzfLx8ZGHh4eefvppzZ49W2FhYUpKSpK7u7sCAgKc+gcHByspKUmSlJSU5BTKMudnzrucwYMHKzk52Zr279+fvzsFAAAAALngancBd999tzZu3Kjk5GTNmDFDsbGxSkhIuK7b9PDwkIeHx3XdBgAAAADklO3BzN3dXRUqVJAk1ahRQ2vWrNF7772nRx99VOfOndOJEyecjpodOnRIISEhkqSQkBD98ssvTuvLvGtjZh8AAAAAuNnZfirjpTIyMpSamqoaNWrIzc1NCxcutObt2LFD+/btU1RUlCQpKipKmzdv1uHDh60+CxYskJ+fn8LCwm547QAAAACQF7YeMRs8eLBatGihUqVK6eTJk5o6daqWLFmi+fPny9/fXz169FD//v0VGBgoPz8/9e3bV1FRUapTp44kqVmzZgoLC1Pnzp315ptvKikpSS+//LLi4uI4VREAAADALcPWYHb48GF16dJFBw8elL+/vyIiIjR//nw1bdpUkjR69GgVKFBA7du3V2pqqmJiYjRu3DhreRcXF82dO1e9e/dWVFSUvL29FRsbqxEjRti1SwAAAACQa7YGs08//fSK8z09PTV27FiNHTv2sn1Kly6t77//Pr9LAwAAAIAb5qa7xgwAAAAA7jQEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAAADAZgQzAAAAALAZwQwAAAAAbEYwAwAAAACbEcwAAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAm7nmZaFdu3Zp8eLFOnz4sDIyMpzmDR06NF8KAwAAAIA7Ra6D2ccff6zevXurSJEiCgkJkcPhsOY5HA6CGQAAAADkUq6D2auvvqpRo0bpxRdfvB71AAAAAMAdJ9fXmB0/flyPPPLI9agFAAAAAO5IuQ5mjzzyiH788cfrUQsAAAAA3JFyfSpjhQoVNGTIEK1atUrh4eFyc3Nzmv/ss8/mW3EAAAAAcCfIdTCbMGGCfHx8lJCQoISEBKd5DoeDYAYAAAAAuZTrYLZnz57rUQcAAAAA3LGu6QemjTEyxuRXLQAAAABwR8pTMPv8888VHh4uLy8veXl5KSIiQv/5z3/yuzYAAAAAuCPk+lTGd999V0OGDFGfPn1Ur149SdLPP/+sp59+Wn///bf69euX70UCAAAAwO0s18Hsgw8+0Pjx49WlSxer7YEHHlCVKlX0yiuvEMwAAAAAIJdyfSrjwYMHVbdu3SztdevW1cGDB/OlKAAAAAC4k+Q6mFWoUEFff/11lvavvvpKd911V74UBQAAAAB3klyfyjh8+HA9+uijWrp0qXWN2fLly7Vw4cJsAxsAAAAA4MpyfcSsffv2Wr16tYoUKaI5c+Zozpw5KlKkiH755Rc99NBD16NGAAAAALit5fqImSTVqFFDX3zxRX7XAgAAAAB3pBwdMUtJSXH6+0pTbsTHx+vee++Vr6+vgoKC9OCDD2rHjh1OfRo1aiSHw+E0Pf3000599u3bp1atWqlgwYIKCgrSwIEDlZaWlqtaAAAAAMAuOTpiVqhQIR08eFBBQUEKCAiQw+HI0scYI4fDofT09BxvPCEhQXFxcbr33nuVlpaml156Sc2aNdPWrVvl7e1t9evZs6dGjBhhPS5YsKD1d3p6ulq1aqWQkBCtWLFCBw8eVJcuXeTm5qbXXnstx7UAAAAAgF1yFMwWLVqkwMBASdLixYvzbeM//PCD0+NJkyYpKChI69atU8OGDa32ggULKiQkJNt1/Pjjj9q6dat++uknBQcHKzIyUiNHjtSLL76oV155Re7u7lmWSU1NVWpqqvU4t0f6AAAAACA/5SiYRUdHW3+XLVtWoaGhWY6aGWO0f//+ayomOTlZkqwQmGnKlCn64osvFBISojZt2mjIkCHWUbOVK1cqPDxcwcHBVv+YmBj17t1bW7ZsUfXq1bNsJz4+XsOHD7+mWgEAAAAgv+T65h9ly5a1Tmu82LFjx1S2bNlcncp4sYyMDD3//POqV6+eqlatarU//vjjKl26tIoXL65NmzbpxRdf1I4dOzRr1ixJUlJSklMok2Q9TkpKynZbgwcPVv/+/a3HKSkpCg0NzVPdAAAAAHCtch3MMq8lu9SpU6fk6emZ50Li4uL022+/6eeff3Zqf+qpp6y/w8PDVaxYMTVu3FiJiYkqX758nrbl4eEhDw+PPNcKAAAAAPkpx8Es8wiTw+FwOpVQunADjtWrVysyMjJPRfTp00dz587V0qVLVbJkySv2rV27tiRp9+7dKl++vEJCQvTLL7849Tl06JAkXfa6NAAAAAC4meQ4mG3YsEHShSNmmzdvdrqphru7u6pVq6YBAwbkauPGGPXt21ezZ8/WkiVLVLZs2asus3HjRklSsWLFJElRUVEaNWqUDh8+bJ1euWDBAvn5+SksLCxX9QAAAACAHXIczDLvxtitWze999578vPzu+aNx8XFaerUqfrmm2/k6+trXRPm7+8vLy8vJSYmaurUqWrZsqUKFy6sTZs2qV+/fmrYsKEiIiIkSc2aNVNYWJg6d+6sN998U0lJSXr55ZcVFxfH6YoAAAAAbgm5vsZs4sSJ+bbx8ePHS7rwI9KXbqNr165yd3fXTz/9pDFjxuj06dMKDQ1V+/bt9fLLL1t9XVxcNHfuXPXu3VtRUVHy9vZWbGys0++eAQAAAMDNLNfBTJLWrl2rr7/+Wvv27dO5c+ec5mXeLTEnjDFXnB8aGqqEhISrrqd06dL6/vvvc7xdAAAAALiZFMjtAtOmTVPdunW1bds2zZ49W+fPn9eWLVu0aNEi+fv7X48aAQAAAOC2lutg9tprr2n06NH67rvv5O7urvfee0/bt29Xhw4dVKpUqetRIwAAAADc1nIdzBITE9WqVStJF+7GePr0aTkcDvXr108TJkzI9wIBAAAA4HaX62BWqFAhnTx5UpJUokQJ/fbbb5KkEydO6MyZM/lbHQAAAADcAXJ984+GDRtqwYIFCg8P1yOPPKLnnntOixYt0oIFC9S4cePrUSMAAAAA3NZyHcz+/e9/6+zZs5Kkf/3rX3Jzc9OKFSuy3MYeAAAAAJAzuQ5mgYGB1t8FChTQoEGD8rUgAAAAALjT5Poas/Xr12vz5s3W42+++UYPPvigXnrppSy/aQYAAAAAuLpcB7NevXpp586dkqTff/9djz76qAoWLKjp06frhRdeyPcCAQAAAOB2l+tgtnPnTkVGRkqSpk+frujoaE2dOlWTJk3SzJkz87s+AAAAALjt5TqYGWOUkZEhSfrpp5/UsmVLSVJoaKj+/vvv/K0OAAAAAO4AuQ5mNWvW1Kuvvqr//Oc/SkhIsH5ses+ePQoODs73AgEAAADgdpfrYDZmzBitX79effr00b/+9S9VqFBBkjRjxgzVrVs33wsEAAAAgNtdrm+XHxER4XRXxkxvvfWWXFxc8qUoAAAAALiT5DqYXY6np2d+rQoAAAAA7ig5CmaBgYHauXOnihQpokKFCsnhcFy277Fjx/KtOAAAAAC4E+QomI0ePVq+vr6SLlxjBgAAAADIPzkKZrGxsdn+DQAAAAC4djkKZikpKTleoZ+fX56LAQAAAIA7UY6CWUBAwBWvK5Mu/PC0w+FQenp6vhQGAAAAAHeKHAWzxYsXX+86AAAAAOCOlaNgFh0dfb3rAAAAAIA7Vo6C2aZNm1S1alUVKFBAmzZtumLfiIiIfCkMAAAAAO4UOQpmkZGRSkpKUlBQkCIjI+VwOGSMydKPa8wAAAAAIPdyFMz27NmjokWLWn8DAAAAAPJPjoJZ6dKlrb//+OMP1a1bV66uzoumpaVpxYoVTn0BAAAAAFdXILcL3HfffTp27FiW9uTkZN133335UhQAAAAA3ElyHcwyf6/sUkePHpW3t3e+FAUAAAAAd5IcncooSe3atZN04QYfXbt2lYeHhzUvPT1dmzZtUt26dfO/QgAAAAC4zeU4mPn7+0u6cMTM19dXXl5e1jx3d3fVqVNHPXv2zP8KAQAAAOA2l+NgNnHiRElSmTJlNGDAAE5bBAAAAIB8kuNglmnYsGHXow4AAAAAuGPl+OYfhQoVUmBgYJapbNmyiomJ0YIFC3K98fj4eN17773y9fVVUFCQHnzwQe3YscOpz9mzZxUXF6fChQvLx8dH7du316FDh5z67Nu3T61atVLBggUVFBSkgQMHKi0tLdf1AAAAAIAdcnzEbMyYMdm2nzhxQuvWrVPr1q01Y8YMtWnTJscbT0hIUFxcnO69916lpaXppZdeUrNmzbR161brVMl+/frpv//9r6ZPny5/f3/16dNH7dq10/LlyyVduPFIq1atFBISohUrVujgwYPq0qWL3Nzc9Nprr+W4FgAAAACwi8MYY/JjRe+++65mzJihFStW5HkdR44cUVBQkBISEtSwYUMlJyeraNGimjp1qh5++GFJ0vbt21W5cmWtXLlSderU0bx589S6dWsdOHBAwcHBkqQPP/xQL774oo4cOSJ3d/erbjclJUX+/v5KTk6Wn59fnuvPL47hWX+O4E5ihuXLWxKwMKYYU8h/jCvGFfIXY+rmGVN2ZYNc/47Z5bRu3Vrbt2+/pnUkJydLkgIDAyVJ69at0/nz59WkSROrT6VKlVSqVCmtXLlSkrRy5UqFh4dboUySYmJilJKSoi1btmS7ndTUVKWkpDhNAAAAAGCXfAtmqampOTo6dTkZGRl6/vnnVa9ePVWtWlWSlJSUJHd3dwUEBDj1DQ4OVlJSktXn4lCWOT9zXnbi4+Pl7+9vTaGhoXmuGwAAAACuVb4Fs08//VSRkZF5Xj4uLk6//fabpk2bll8lXdbgwYOVnJxsTfv377/u2wQAAACAy8nxzT/69++fbXtycrLWr1+vnTt3aunSpXkqok+fPpo7d66WLl2qkiVLWu0hISE6d+6cTpw44XTU7NChQwoJCbH6/PLLL07ry7xrY2afS3l4eMjDwyNPtQIAAABAfstxMNuwYUO27X5+fmratKlmzZqlsmXL5mrjxhj17dtXs2fP1pIlS7IsX6NGDbm5uWnhwoVq3769JGnHjh3at2+foqKiJElRUVEaNWqUDh8+rKCgIEnSggUL5Ofnp7CwsFzVAwAAAAB2yHEwW7x4cb5vPC4uTlOnTtU333wjX19f65owf39/eXl5yd/fXz169FD//v0VGBgoPz8/9e3bV1FRUapTp44kqVmzZgoLC1Pnzp315ptvKikpSS+//LLi4uI4KgYAAADglpDjYHY9jB8/XpLUqFEjp/aJEyeqa9eukqTRo0erQIECat++vVJTUxUTE6Nx48ZZfV1cXDR37lz17t1bUVFR8vb2VmxsrEaMGHGjdgMAAAAAromtwSwnP6Hm6empsWPHauzYsZftU7p0aX3//ff5WRoAAAAA3DD5dldGAAAAAEDeEMwAAAAAwGY5Dmbdu3fXyZMnr2ctAAAAAHBHynEwmzx5sv7555/rWQsAAAAA3JFyHMxycqMOAAAAAEDu5equjCdPnpSnp+cV+/j5+V1TQQAAAABwp8lVMKtYseJl5xlj5HA4lJ6efs1FAQAAAMCdJFfBbMaMGQoMDLxetQAAAADAHSlXwaxevXoKCgq6XrUAAAAAwB2J3zEDAAAAAJvlOJiVLl1aLi4u17MWAAAAALgj5fhUxj179lzPOgAAAADgjpXjYFaoUCE5HI4s7f7+/qpYsaIGDBigpk2b5mtxAAAAAHAnyHEwGz16dLbB7MSJE1q3bp1at26tGTNmqE2bNvlaIAAAAADc7nIczLp27XrF+ZGRkYqPjyeYAQAAAEAu5dtdGVu3bq3t27fn1+oAAAAA4I6Rb8EsNTVV7u7u+bU6AAAAALhj5Fsw+/TTTxUZGZlfqwMAAACAO0aOrzHr379/tu3Jyclav369du7cqaVLl+ZbYQAAAABwp8hxMNuwYUO27X5+fmratKlmzZqlsmXL5lthAAAAAHCnyHEwW7x48RXn//nnn3rqqac0YcKEay4KAAAAAO4k+XaN2dGjR/Xpp5/m1+oAAAAA4I6Rb8EMAAAAAJA3BDMAAAAAsBnBDAAAAABsluObf7Rr1+6K80+cOHGttQAAAADAHSnHwczf3/+q87t06XLNBQEAAADAnSbHwWzixInXsw4AAAAAuGNxjRkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANjM1mC2dOlStWnTRsWLF5fD4dCcOXOc5nft2lUOh8Npat68uVOfY8eOqVOnTvLz81NAQIB69OihU6dO3cC9AAAAAIBrY2swO336tKpVq6axY8detk/z5s118OBBa/ryyy+d5nfq1ElbtmzRggULNHfuXC1dulRPPfXU9S4dAAAAAPJNjn/H7Hpo0aKFWrRoccU+Hh4eCgkJyXbetm3b9MMPP2jNmjWqWbOmJOmDDz5Qy5Yt9fbbb6t48eL5XjMAAAAA5Leb/hqzJUuWKCgoSHfffbd69+6to0ePWvNWrlypgIAAK5RJUpMmTVSgQAGtXr36sutMTU1VSkqK0wQAAAAAdrmpg1nz5s31+eefa+HChXrjjTeUkJCgFi1aKD09XZKUlJSkoKAgp2VcXV0VGBiopKSky643Pj5e/v7+1hQaGnpd9wMAAAAArsTWUxmvpmPHjtbf4eHhioiIUPny5bVkyRI1btw4z+sdPHiw+vfvbz1OSUkhnAEAAACwzU19xOxS5cqVU5EiRbR7925JUkhIiA4fPuzUJy0tTceOHbvsdWnShevW/Pz8nCYAAAAAsMstFcz+/PNPHT16VMWKFZMkRUVF6cSJE1q3bp3VZ9GiRcrIyFDt2rXtKhMAAAAAcsXWUxlPnTplHf2SpD179mjjxo0KDAxUYGCghg8frvbt2yskJESJiYl64YUXVKFCBcXExEiSKleurObNm6tnz5768MMPdf78efXp00cdO3bkjowAAAAAbhm2HjFbu3atqlevrurVq0uS+vfvr+rVq2vo0KFycXHRpk2b9MADD6hixYrq0aOHatSooWXLlsnDw8Nax5QpU1SpUiU1btxYLVu2VP369TVhwgS7dgkAAAAAcs3WI2aNGjWSMeay8+fPn3/VdQQGBmrq1Kn5WRYAAAAA3FC31DVmAAAAAHA7IpgBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADazNZgtXbpUbdq0UfHixeVwODRnzhyn+cYYDR06VMWKFZOXl5eaNGmiXbt2OfU5duyYOnXqJD8/PwUEBKhHjx46derUDdwLAAAAALg2tgaz06dPq1q1aho7dmy289988029//77+vDDD7V69Wp5e3srJiZGZ8+etfp06tRJW7Zs0YIFCzR37lwtXbpUTz311I3aBQAAAAC4Zq52brxFixZq0aJFtvOMMRozZoxefvlltW3bVpL0+eefKzg4WHPmzFHHjh21bds2/fDDD1qzZo1q1qwpSfrggw/UsmVLvf322ypevPgN2xcAAAAAyKub9hqzPXv2KCkpSU2aNLHa/P39Vbt2ba1cuVKStHLlSgUEBFihTJKaNGmiAgUKaPXq1Zddd2pqqlJSUpwmAAAAALDLTRvMkpKSJEnBwcFO7cHBwda8pKQkBQUFOc13dXVVYGCg1Sc78fHx8vf3t6bQ0NB8rh4AAAAAcu6mDWbX0+DBg5WcnGxN+/fvt7skAAAAAHewmzaYhYSESJIOHTrk1H7o0CFrXkhIiA4fPuw0Py0tTceOHbP6ZMfDw0N+fn5OEwAAAADY5aYNZmXLllVISIgWLlxotaWkpGj16tWKioqSJEVFRenEiRNat26d1WfRokXKyMhQ7dq1b3jNAAAAAJAXtt6V8dSpU9q9e7f1eM+ePdq4caMCAwNVqlQpPf/883r11Vd11113qWzZshoyZIiKFy+uBx98UJJUuXJlNW/eXD179tSHH36o8+fPq0+fPurYsSN3ZAQAAABwy7A1mK1du1b33Xef9bh///6SpNjYWE2aNEkvvPCCTp8+raeeekonTpxQ/fr19cMPP8jT09NaZsqUKerTp48aN26sAgUKqH379nr//fdv+L4AAAAAQF7ZGswaNWokY8xl5zscDo0YMUIjRoy4bJ/AwEBNnTr1epQHAAAAADfETXuNGQAAAADcKQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNbupg9sorr8jhcDhNlSpVsuafPXtWcXFxKly4sHx8fNS+fXsdOnTIxooBAAAAIPdu6mAmSVWqVNHBgwet6eeff7bm9evXT999952mT5+uhIQEHThwQO3atbOxWgAAAADIPVe7C7gaV1dXhYSEZGlPTk7Wp59+qqlTp+r++++XJE2cOFGVK1fWqlWrVKdOnRtdKgAAAADkyU1/xGzXrl0qXry4ypUrp06dOmnfvn2SpHXr1un8+fNq0qSJ1bdSpUoqVaqUVq5cecV1pqamKiUlxWkCAAAAALvc1MGsdu3amjRpkn744QeNHz9ee/bsUYMGDXTy5EklJSXJ3d1dAQEBTssEBwcrKSnpiuuNj4+Xv7+/NYWGhl7HvQAAAACAK7upT2Vs0aKF9XdERIRq166t0qVL6+uvv5aXl1ee1zt48GD179/fepySkkI4AwAAAGCbm/qI2aUCAgJUsWJF7d69WyEhITp37pxOnDjh1OfQoUPZXpN2MQ8PD/n5+TlNAAAAAGCXWyqYnTp1SomJiSpWrJhq1KghNzc3LVy40Jq/Y8cO7du3T1FRUTZWCQAAAAC5c1OfyjhgwAC1adNGpUuX1oEDBzRs2DC5uLjosccek7+/v3r06KH+/fsrMDBQfn5+6tu3r6KiorgjIwAAAIBbyk0dzP7880899thjOnr0qIoWLar69etr1apVKlq0qCRp9OjRKlCggNq3b6/U1FTFxMRo3LhxNlcNAAAAALlzUwezadOmXXG+p6enxo4dq7Fjx96gigAAAAAg/91S15gBAAAAwO2IYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2IxgBgAAAAA2I5gBAAAAgM0IZgAAAABgM4IZAAAAANiMYAYAAAAANiOYAQAAAIDNCGYAAAAAYDOCGQAAAADYjGAGAAAAADYjmAEAAACAzQhmAAAAAGAzghkAAAAA2Oy2CWZjx45VmTJl5Onpqdq1a+uXX36xuyQAAAAAyJHbIph99dVX6t+/v4YNG6b169erWrVqiomJ0eHDh+0uDQAAAACu6rYIZu+++6569uypbt26KSwsTB9++KEKFiyozz77zO7SAAAAAOCqXO0u4FqdO3dO69at0+DBg622AgUKqEmTJlq5cmW2y6Smpio1NdV6nJycLElKSUm5vsXm1Fm7C7DXTfM64PbBmLK7BNyOGFd2l4DbDWPK7hIsmbUYY27odm/5YPb3338rPT1dwcHBTu3BwcHavn17tsvEx8dr+PDhWdpDQ0OvS43IHf/X/e0uAbitMKaA/Me4AvLXzTimTp48KX//G1fXLR/M8mLw4MHq37+/9TgjI0PHjh1T4cKF5XA4bKzMfikpKQoNDdX+/fvl5+dndznALY8xBeQ/xhWQvxhTzowxOnnypIoXL35Dt3vLB7MiRYrIxcVFhw4dcmo/dOiQQkJCsl3Gw8NDHh4eTm0BAQHXq8Rbkp+fHwMTyEeMKSD/Ma6A/MWY+p8beaQs0y1/8w93d3fVqFFDCxcutNoyMjK0cOFCRUVF2VgZAAAAAOTMLX/ETJL69++v2NhY1axZU7Vq1dKYMWN0+vRpdevWze7SAAAAAOCqbotg9uijj+rIkSMaOnSokpKSFBkZqR9++CHLDUFwdR4eHho2bFiWUz0B5A1jCsh/jCsgfzGmbg4Oc6PvAwkAAAAAcHLLX2MGAAAAALc6ghkAAAAA2IxgBgAAAAA2I5jlUZkyZTRmzBi7y7jl7N27Vw6HQxs3brzu2+I1uvXwmuUN4wqXw+uVN4wpXAmvWd4wrnLA3MJiY2ONJNOrV68s85555hkjycTGxuZoXXv27DGSzIYNG3LU//Dhw+b06dM56tu6dWsTExOT7bylS5caSebXX3/N0bouZ/HixUaSOX78+DWt51JnzpwxhQoVMoULFzZnz57N1bKxsbGmbdu2Tm1paWnm4MGD5vz58/lW48SJE42/v3+W9ty8Rvnl3//+tyldurTx8PAwtWrVMqtXr76h288PjKv/YVz5Z2m/0eMqISHBtG7d2hQrVsxIMrNnz75h284vjKn/YUz5Z2m/0WPqtddeMzVr1jQ+Pj6maNGipm3btmb79u03bPv5hXH1P4wr/yztN3pcjRs3zoSHhxtfX1/j6+tr6tSpY77//vtcr+eWP2IWGhqqadOm6Z9//rHazp49q6lTp6pUqVL5vr1z585JkooWLaqCBQvmaJkePXpowYIF+vPPP7PMmzhxomrWrKmIiIh8rTOvjDFKS0uzHs+cOVNVqlRRpUqVNGfOnGtev4uLi0JCQuTqev1/qSE3r1F++Oqrr9S/f38NGzZM69evV7Vq1RQTE6PDhw/fsBryC+MqfzGu8u706dOqVq2axo4de8O2eT0wpvIXYyrvEhISFBcXp1WrVmnBggU6f/68mjVrptOnT9+wGvIL4yp/Ma7yrmTJknr99de1bt06rV27Vvfff7/atm2rLVu25G5F+RwYb6jMNF61alXzxRdfWO1TpkwxERERpm3btta3JfPmzTP16tUz/v7+JjAw0LRq1crs3r3bWkaS0xQdHe20jVdffdUUK1bMlClTxhhjTOnSpc3o0aONMRe+qXBzczNLly611vfGG2+YokWLmqSkJHP+/HkTHBxsRo4c6VT/yZMnjY+Pjxk/frwxxphly5aZ+vXrG09PT1OyZEnTt29fc+rUKav/2bNnzQsvvGBKlixp3N3dTfny5c0nn3xifdNz8ZS532fPnjV9+/Y1RYsWNR4eHqZevXrml19+sdaZ+S3L999/b+655x7j5uZmFi9ebM1v1KiR+fDDD8348eNN06ZNs7wGv/32m2nVqpXx9fU1Pj4+pn79+mb37t1m2LBhWWpavHix07dS6enppkSJEmbcuHFO61y/fr1xOBxm7969xhhj3nnnHVO1alVTsGBBU7JkSdO7d29z8uRJp/ovnoYNG5blNTLGmD/++MM88MADxtvb2/j6+ppHHnnEJCUlWfOHDRtmqlWrZj7//HNTunRp4+fnZx599FGTkpKSZb+zU6tWLRMXF2c9Tk9PN8WLFzfx8fE5Wv5mwbhiXN1M4+piuoWPmDGmGFM345gy5sKRBUkmISEhT8vbhXHFuLqZx5UxxhQqVMh88sknuVrmtghm7777rmncuLHV3rhxYzN69GinQTljxgwzc+ZMs2vXLrNhwwbTpk0bEx4ebtLT040xxvzyyy9Gkvnpp5/MwYMHzdGjR61t+Pj4mM6dO5vffvvN/Pbbb8aYrC/4wIEDTenSpc2JEyfM+vXrjbu7u/nmm2+c5pcvX95kZGRYbZ999pnx8vIyJ06cMLt37zbe3t5m9OjRZufOnWb58uWmevXqpmvXrlb/Dh06mNDQUDNr1iyTmJhofvrpJzNt2jSTlpZmZs6caSSZHTt2mIMHD5oTJ04YY4x59tlnTfHixc33339vtmzZYmJjY02hQoWs/ct8U0dERJgff/zR7N6925q3e/du4+HhYY4dO2aOHj1qPD09rYFijDF//vmnCQwMNO3atTNr1qwxO3bsMJ999pnZvn27OXnypOnQoYNp3ry5OXjwoDl48KBJTU3NcrrAgAEDTP369Z1e1//7v/9zahs9erRZtGiR2bNnj1m4cKG5++67Te/evY0xxqSmppoxY8YYPz8/azuZA/bi1yg9Pd1ERkaa+vXrm7Vr15pVq1aZGjVqWB++xlwYlD4+PqZdu3Zm8+bNZunSpSYkJMS89NJLl30PZkpNTTUuLi5Z/tHYpUsX88ADD1x1+ZsJ44pxdbOMq0vd6sGMMcWYutnGlDHG7Nq1y0gymzdvztPydmFcMa5u1nGVlpZmvvzyS+Pu7m62bNmSq2Vvi2B2+PBh4+HhYfbu3Wv27t1rPD09zZEjR5wG5aWOHDni9EF0ufOLY2NjTXBwsElNTXVqv3RQpqammsjISNOhQwcTFhZmevbs6dR/27Zt1jcGmRo0aGCeeOIJY4wxPXr0ME899ZTTMsuWLTMFChQw//zzj9mxY4eRZBYsWJDt/mR3fvGpU6eMm5ubmTJlitV27tw5U7x4cfPmm286LTdnzpws63zppZfMgw8+aD1u27at9U2EMcYMHjzYlC1b1pw7dy7bmrI7v/jS53nDhg3G4XCYP/74wxhjrG9QMr9Bys706dNN4cKFrceXO7/44tfoxx9/NC4uLmbfvn3W/C1bthhJ1rdHw4YNMwULFnT6dmTgwIGmdu3al60l019//WUkmRUrVji1Dxw40NSqVeuqy99MGFf/w7jyz9LvRo6rS93qwYwxxZi62cZUenq6adWqlalXr16ul7Ub4+p/GFf+WfrZMa42bdpkvL29jYuLi/H39zf//e9/c7xsplv+GjPpwnmkrVq10qRJkzRx4kS1atVKRYoUceqza9cuPfbYYypXrpz8/PxUpkwZSdK+ffuuuv7w8HC5u7tfsY+7u7umTJmimTNn6uzZsxo9erTT/EqVKqlu3br67LPPJEm7d+/WsmXL1KNHD0nSr7/+qkmTJsnHx8eaYmJilJGRoT179mjjxo1ycXFRdHR0Tp8WJSYm6vz586pXr57V5ubmplq1amnbtm1OfWvWrOn0OD09XZMnT9YTTzxhtT3xxBOaNGmSMjIyJEkbN25UgwYN5ObmluOaLhUZGanKlStr6tSpki6c+3748GE98sgjVp+ffvpJjRs3VokSJeTr66vOnTvr6NGjOnPmTI63s23bNoWGhio0NNRqCwsLU0BAgNNzUaZMGfn6+lqPixUrdkteI5YfGFfZY1z9D+MqdxhT2WNM/c+NHlNxcXH67bffNG3atFwve7NgXGWPcfU/N2pc3X333dq4caNWr16t3r17KzY2Vlu3bs3x8tJtdLv87t27a9KkSZo8ebK6d++eZX6bNm107Ngxffzxx1q9erVWr14t6X8Xcl6Jt7d3jmpYsWKFJOnYsWM6duxYlvk9evTQzJkzdfLkSU2cOFHly5e3BtmpU6fUq1cvbdy40Zp+/fVX7dq1S+XLl5eXl1eOasirS/dx/vz5+uuvv/Too4/K1dVVrq6u6tixo/744w8tXLhQkvKtpk6dOlmDcurUqWrevLkKFy4s6cKtVVu3bq2IiAjNnDlT69ats24CkJPXLrcu/YBxOBzWh9CVFClSRC4uLjp06JBT+6FDhxQSEpKvNd5IjKtrw7i6IK/j6nbEmLo2jKkL8mNM9enTR3PnztXixYtVsmTJ/CzvhmNcXRvG1QXXOq7c3d1VoUIF1ahRQ/Hx8apWrZree++9XNVw2wSz5s2b69y5czp//rxiYmKc5h09elQ7duzQyy+/rMaNG6ty5co6fvy4U5/Mb0PS09PztP3ExET169dPH3/8sWrXrq3Y2NgsL2aHDh1UoEABTZ06VZ9//rm6d+8uh8MhSbrnnnu0detWVahQIcvk7u6u8PBwZWRkKCEhIdvtZ1d/+fLl5e7uruXLl1tt58+f15o1axQWFnbF/fn000/VsWNHpw+JjRs3qmPHjvr0008lSREREVq2bJnOnz9/2Zpy8nw+/vjj+u2337Ru3TrNmDFDnTp1suatW7dOGRkZeuedd1SnTh1VrFhRBw4cyPV2KleurP3792v//v1W29atW3XixImrPhc54e7urho1algfWJKUkZGhhQsXKioq6prXbxfGFePqSq73uLodMaYYU1dyI8aUMUZ9+vTR7NmztWjRIpUtWzZf1msnxhXj6krs+n9VRkaGUlNTc7dQrk9+vIlcev5qcnKySU5Oth5nnl+cnp5uChcubJ544gmza9cus3DhQnPvvfc6Xa9w/vx54+XlZV599VWTlJRkXTiZ3Tmyxjifu5qWlmbq1Klj2rdvb4wx5sCBA6Zw4cLWObwX69GjhylUqJBxcXExf/31l9X+66+/Gi8vLxMXF2c2bNhgdu7caebMmeN0l7+uXbua0NBQM3v2bPP777+bxYsXm6+++soYc+EiTIfDYSZNmmQOHz5sXfz43HPPmeLFi5t58+Y5Xfh57NgxY0z25yUfPnzYuLm5mXnz5mWp//vvvzceHh7m6NGj5u+//zaFCxe2LvzcuXOn+fzzz63fQxk1apQpVaqU2b59uzly5Ig5d+7cZc/jrlevnqlWrZrx9fU1Z86csdo3btxoJJkxY8aYxMRE8/nnn5sSJUo41bx8+XLrot0jR45Yv1tx8WuUkZFhIiMjTYMGDcy6devM6tWrs73ws1q1ak51jR492pQuXTrL85CdadOmGQ8PDzNp0iSzdetW89RTT5mAgACnu/7cChhXjCtjbp5xdfLkSbNhwwazYcMGI8m8++67ZsOGDdY1CbcCxhRjypibZ0z17t3b+Pv7myVLllg3TDh48KDT/twKGFeMK2NunnE1aNAgk5CQYPbs2WM2bdpkBg0aZBwOh/nxxx9ztHym2yqYXeriCz8XLFhgKleubDw8PExERIRZsmRJlgvJP/74YxMaGmoKFCiQ5Vapl7r4BR8+fLgpVqyY+fvvv635M2fONO7u7mbjxo1Oy61YscJIMi1btsyyzl9++cU0bdrU+Pj4GG9vbxMREWFGjRplzf/nn39Mv379TLFixYy7u7upUKGC+eyzz6z5I0aMMCEhIcbhcFj7/c8//5i+ffuaIkWKXPFWqRcPyrffftsEBARke0FnamqqCQgIMO+9954x5sKHSbNmzUzBggWNr6+vadCggUlMTDTGXBjcmfujbG6VerFx48YZSaZLly5Ztvnuu++aYsWKGS8vLxMTE2M+//zzLDU//fTTpnDhwvlyq9SL5WZQGmPMBx98YEqVKmXc3d1NrVq1zKpVq3K87M2CccW4ynQzjKvsbocs5fyHY28GjCnGVKabYUxlN54kmYkTJ+Zo+ZsF44pxlelmGFfdu3c3pUuXNu7u7qZo0aKmcePGuQ5lxhjjMMaY3B1jAwAAAADkp9vmGjMAAAAAuFURzIAc2Ldvn9NtbC+dcnLLXQDOGFdA/mJMAfnvRo4rTmUEciAtLU179+697PwyZcrI1dX1xhUE3AYYV0D+YkwB+e9GjiuCGQAAAADYjFMZAQAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJsRzAAAd7RGjRrp+eeft7sMAMAdjmAGAMiTrl27yuFw6PXXX3dqnzNnjhwOR67WVaZMGY0ZMyYfq7t+9u7dK4fDoY0bN9pdCgDgNkIwAwDkmaenp9544w0dP37c7lJy7dy5c3aXkK/Onz9vdwkAgGtAMAMA5FmTJk0UEhKi+Pj4K/b7+eef1aBBA3l5eSk0NFTPPvusTp8+LenCqYR//PGH+vXrJ4fDIYfDIWOMihYtqhkzZljriIyMVLFixZzW6eHhoTNnzkiS9u3bp7Zt28rHx0d+fn7q0KGDDh06ZPV/5ZVXFBkZqU8++URly5aVp6dntrX+97//lb+/v6ZMmZKn5yQxMVFt27ZVcHCwfHx8dO+99+qnn36y5o8YMUJVq1bNslxkZKSGDBliPf7kk09UuXJleXp6qlKlSho3bpw1L/Oo3VdffaXo6Gh5enpqypQp+uOPP9SmTRsVKlRI3t7eqlKlir7//vs87QcA4MYimAEA8szFxUWvvfaaPvjgA/3555/Z9klMTFTz5s3Vvn17bdq0SV999ZV+/vln9enTR5I0a9YslSxZUiNGjNDBgwd18OBBORwONWzYUEuWLJEkHT9+XNu2bdM///yj7du3S5ISEhJ07733qmDBgsrIyFDbtm117NgxJSQkaMGCBfr999/16KOPOtWye/duzZw5U7Nmzcr2VMSpU6fqscce05QpU9SpU6c8PSenTp1Sy5YttXDhQm3YsEHNmzdXmzZttG/fPklS9+7dtW3bNq1Zs8ZaZsOGDdq0aZO6desmSZoyZYqGDh2qUaNGadu2bXrttdc0ZMgQTZ482WlbgwYN0nPPPadt27YpJiZGcXFxSk1N1dKlS7V582a98cYb8vHxydN+AABuLFe7CwAA3NoeeughRUZGatiwYfr000+zzI+Pj1enTp2sG2zcddddev/99xUdHa3x48crMDBQLi4u8vX1VUhIiLVco0aN9NFHH0mSli5dqurVqyskJERLlixRpUqVtGTJEkVHR0uSFi5cqM2bN2vPnj0KDQ2VJH3++eeqUqWK1qxZo3vvvVfShdMXP//8cxUtWjRLnWPHjtW//vUvfffdd9Z686JatWqqVq2a9XjkyJGaPXu2vv32W/Xp00clS5ZUTEyMJk6caNU1ceJERUdHq1y5cpKkYcOG6Z133lG7du0kSWXLltXWrVv10UcfKTY21lr3888/b/WRLhw1bN++vcLDwyXJWh8A4ObHETMAwDV74403NHnyZG3bti3LvF9//VWTJk2Sj4+PNcXExCgjI0N79uy57Dqjo6O1detWHTlyRAkJCWrUqJEaNWqkJUuW6Pz581qxYoUaNWokSdq2bZtCQ0OtUCZJYWFhCggIcKqpdOnS2YayGTNmqF+/flqwYME1hTLpwhGzAQMGqHLlygoICJCPj4+2bdtmHTGTpJ49e+rLL7/U2bNnde7cOU2dOlXdu3eXJJ0+fVqJiYnq0aOH03P26quvKjEx0WlbNWvWdHr87LPP6tVXX1W9evU0bNgwbdq06Zr2BQBw4xDMAADXrGHDhoqJidHgwYOzzDt16pR69eqljRs3WtOvv/6qXbt2qXz58pddZ3h4uAIDA5WQkOAUzBISErRmzRqdP39edevWzVWd3t7e2bZXr15dRYsW1WeffSZjTK7WeakBAwZo9uzZeu2117Rs2TJt3LhR4eHhTjcbadOmjTw8PDR79mx99913On/+vB5++GFJF54vSfr444+dnrPffvtNq1atuuL+PPnkk/r999/VuXNnbd68WTVr1tQHH3xwTfsDALgxOJURAJAvXn/9dUVGRuruu+92ar/nnnu0detWVahQ4bLLuru7Kz093anN4XCoQYMG+uabb7RlyxbVr19fBQsWVGpqqj766CPVrFnTCiaVK1fW/v37tX//fuuo2datW3XixAmFhYVdtfby5cvrnXfeUaNGjeTi4qJ///vfud19y/Lly9W1a1c99NBDki4Erb179zr1cXV1VWxsrCZOnCh3d3d17NhRXl5ekqTg4GAVL15cv//+e56ucwsNDdXTTz+tp59+WoMHD9bHH3+svn375nl/AAA3BsEMAJAvwsPD1alTJ73//vtO7S+++KLq1KmjPn366Mknn5S3t7e2bt2qBQsWWAGoTJkyWrp0qTp27CgPDw8VKVJE0oXrzP7v//5PNWvWtG5i0bBhQ02ZMkUDBw60ttGkSRNr+2PGjFFaWpqeeeYZRUdHZznd73IqVqyoxYsXq1GjRnJ1db3q76rt2LEjS1uVKlV01113adasWWrTpo0cDoeGDBmijIyMLH2ffPJJVa5cWdKFMHex4cOH69lnn5W/v7+aN2+u1NRUrV27VsePH1f//v0vW9Pzzz+vFi1aqGLFijp+/LgWL15sbQMAcHPjVEYAQL4ZMWJElhASERGhhIQE7dy5Uw0aNFD16tU1dOhQFS9e3Gm5vXv3qnz58k7XgEVHRys9Pd26lky6ENYubXM4HPrmm29UqFAhNWzYUE2aNFG5cuX01Vdf5ar+u+++W4sWLdKXX36p//u//7ti344dO6p69epO06FDh/Tuu++qUKFCqlu3rtq0aaOYmBjdc889WZa/6667VLduXVWqVEm1a9d2mvfkk0/qk08+0cSJExUeHq7o6GhNmjRJZcuWvWJN6enpiouLU+XKldW8eXNVrFjR6Tb7AICbl8Nc68n0AAAg14wxuuuuu/TMM89c8SgYAODOwKmMAADcYEeOHNG0adOUlJRk/XYZAODORjADAOAGCwoKUpEiRTRhwgQVKlTI7nIAADcBghkAADcYVxEAAC7FzT8AAAAAwGYEMwAAAACwGcEMAAAAAGxGMAMAAAAAmxHMAAAAAMBmBDMAAAAAsBnBDAAAAABsRjADAAAAAJv9P5KKOBMzm6wXAAAAAElFTkSuQmCC", - "text/plain": [ - "
    " - ] - }, - "metadata": {}, - "output_type": "display_data" - } - ], + "outputs": [], "source": [ "# Extracting LUTs from res_dict\n", "LUTs_updated = [res_dict_updated[key][\"LUT\"] for key in res_dict_updated.keys()] \n", @@ -612,7 +375,7 @@ "plt.bar(res_dict_updated.keys(), LUTs_updated, color ='green', width = 0.3)\n", "plt.xlabel(\"Network Layers\")\n", "plt.ylabel(\"LUT Utilisation\")\n", - "plt.title(\"Estimated LUT values used for each network layer\")\n", + "plt.title(\"No. of LUTs per layer with updated folding factors\")\n", "plt.show()" ] }, @@ -622,7 +385,7 @@ "source": [ "From these numbers, we see that the first layer has been removed as the bottleneck and that the entire network can now perform one inference in ~4096 clock cycles (when the pipeline is full) as compared to the earlier configuration where it took ~38400 execution cycles.\n", "\n", - "This decrease in execution latency of the network though comes at a cost of a 45% increase in LUT resource utilization for layer 1 of the network." + "This decrease in execution latency of the network though comes at a cost of a 45% increase in LUT resource utilization for the first layer of the network." ] }, { @@ -636,7 +399,7 @@ "cell_type": "markdown", "metadata": {}, "source": [ - "Next to resources and performance, folding factors (or parallelization parameters) are influencing also other properties of the generated design. Since we are able to generate results in parallel, the data that gets feed into the layer needs to be packed in a specific format to provide the correct data at the correct time for the internal parallelism. Also, the data that comes out of a layer will be in a specific format depending on the internal parallelism." + "Next to resources and performance, folding factors (or parallelization parameters) are influencing also other properties of the generated design. Since we are able to generate results in parallel, the data that gets fed into the layer needs to be packed in a specific format to provide the correct data at the correct time for the internal parallelism. Also, the data that comes out of a layer will be in a specific format depending on the internal parallelism." ] }, { @@ -648,7 +411,7 @@ }, { "cell_type": "code", - "execution_count": 17, + "execution_count": null, "metadata": {}, "outputs": [], "source": [ @@ -665,29 +428,9 @@ }, { "cell_type": "code", - "execution_count": 25, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "In the original model (pe=simd=1): \n", - "Layer: MatrixVectorActivation_0\n", - "Input shape: (1, 600, 1)\n", - "Output shape: (1, 64, 1)\n", - "Layer: MatrixVectorActivation_1\n", - "Input shape: (1, 64, 1)\n", - "Output shape: (1, 64, 1)\n", - "Layer: MatrixVectorActivation_2\n", - "Input shape: (1, 64, 1)\n", - "Output shape: (1, 64, 1)\n", - "Layer: MatrixVectorActivation_3\n", - "Input shape: (1, 64, 1)\n", - "Output shape: (1, 1, 1)\n" - ] - } - ], + "outputs": [], "source": [ "# Original model\n", "list_of_mvaus = model_orig.get_nodes_by_op_type(\"MatrixVectorActivation\")\n", @@ -701,29 +444,9 @@ }, { "cell_type": "code", - "execution_count": 26, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "In the original model (pe=simd=1): \n", - "Layer: MatrixVectorActivation_0\n", - "Input shape: (1, 120, 5)\n", - "Output shape: (1, 32, 2)\n", - "Layer: MatrixVectorActivation_1\n", - "Input shape: (1, 64, 1)\n", - "Output shape: (1, 64, 1)\n", - "Layer: MatrixVectorActivation_2\n", - "Input shape: (1, 64, 1)\n", - "Output shape: (1, 64, 1)\n", - "Layer: MatrixVectorActivation_3\n", - "Input shape: (1, 64, 1)\n", - "Output shape: (1, 1, 1)\n" - ] - } - ], + "outputs": [], "source": [ "# Updated model\n", "list_of_mvaus = model_updated.get_nodes_by_op_type(\"MatrixVectorActivation\")\n", @@ -744,42 +467,18 @@ }, { "cell_type": "code", - "execution_count": 30, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - " def get_instream_width(self, ind=0):\n", - " i_bits = self.get_input_datatype().bitwidth()\n", - " in_width = i_bits * self.get_nodeattr(\"SIMD\")\n", - " return in_width\n", - "\n" - ] - } - ], + "outputs": [], "source": [ "showSrc(mvau_inst.get_instream_width)" ] }, { "cell_type": "code", - "execution_count": 31, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - " def get_outstream_width(self, ind=0):\n", - " o_bits = self.get_output_datatype().bitwidth()\n", - " out_width = o_bits * self.get_nodeattr(\"PE\")\n", - " return out_width\n", - "\n" - ] - } - ], + "outputs": [], "source": [ "showSrc(mvau_inst.get_outstream_width)" ] @@ -800,29 +499,9 @@ }, { "cell_type": "code", - "execution_count": 32, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "In the original model (pe=simd=1): \n", - "Layer: MatrixVectorActivation_0\n", - "Input stream width: 1\n", - "Output stream width: 2\n", - "Layer: MatrixVectorActivation_1\n", - "Input stream width: 2\n", - "Output stream width: 2\n", - "Layer: MatrixVectorActivation_2\n", - "Input stream width: 2\n", - "Output stream width: 2\n", - "Layer: MatrixVectorActivation_3\n", - "Input stream width: 2\n", - "Output stream width: 1\n" - ] - } - ], + "outputs": [], "source": [ "# Original model\n", "list_of_mvaus = model_orig.get_nodes_by_op_type(\"MatrixVectorActivation\")\n", @@ -850,29 +529,9 @@ }, { "cell_type": "code", - "execution_count": 34, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "In the original model (pe=simd=1): \n", - "Layer: MatrixVectorActivation_0\n", - "Input stream width: 5\n", - "Output stream width: 4\n", - "Layer: MatrixVectorActivation_1\n", - "Input stream width: 2\n", - "Output stream width: 2\n", - "Layer: MatrixVectorActivation_2\n", - "Input stream width: 2\n", - "Output stream width: 2\n", - "Layer: MatrixVectorActivation_3\n", - "Input stream width: 2\n", - "Output stream width: 1\n" - ] - } - ], + "outputs": [], "source": [ "# Updated model\n", "list_of_mvaus = model_updated.get_nodes_by_op_type(\"MatrixVectorActivation\")\n", @@ -893,7 +552,7 @@ }, { "cell_type": "code", - "execution_count": 39, + "execution_count": null, "metadata": {}, "outputs": [], "source": [ @@ -906,40 +565,9 @@ }, { "cell_type": "code", - "execution_count": 40, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "Stopping http://0.0.0.0:5920\n", - "Serving 'cybsec_DWC.onnx' at http://0.0.0.0:5920\n" - ] - }, - { - "data": { - "text/html": [ - "\n", - " \n", - " " - ], - "text/plain": [ - "" - ] - }, - "execution_count": 40, - "metadata": {}, - "output_type": "execute_result" - } - ], + "outputs": [], "source": [ "model_updated.save(\"cybsec_DWC.onnx\")\n", "showInNetron(\"cybsec_DWC.onnx\")" @@ -955,49 +583,9 @@ }, { "cell_type": "code", - "execution_count": 42, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "data": { - "text/plain": [ - "{'MatrixVectorActivation_0': {'BRAM_18K': 8,\n", - " 'BRAM_efficiency': 0.5208333333333334,\n", - " 'LUT': 418,\n", - " 'URAM': 0,\n", - " 'URAM_efficiency': 1,\n", - " 'DSP': 0},\n", - " 'StreamingDataWidthConverter_Batch_0': {'BRAM_18K': 0,\n", - " 'BRAM_efficiency': 1,\n", - " 'LUT': 3,\n", - " 'URAM': 0,\n", - " 'URAM_efficiency': 1,\n", - " 'DSP': 0},\n", - " 'MatrixVectorActivation_1': {'BRAM_18K': 1,\n", - " 'BRAM_efficiency': 0.4444444444444444,\n", - " 'LUT': 320,\n", - " 'URAM': 0,\n", - " 'URAM_efficiency': 1,\n", - " 'DSP': 0},\n", - " 'MatrixVectorActivation_2': {'BRAM_18K': 1,\n", - " 'BRAM_efficiency': 0.4444444444444444,\n", - " 'LUT': 320,\n", - " 'URAM': 0,\n", - " 'URAM_efficiency': 1,\n", - " 'DSP': 0},\n", - " 'MatrixVectorActivation_3': {'BRAM_18K': 1,\n", - " 'BRAM_efficiency': 0.006944444444444444,\n", - " 'LUT': 320,\n", - " 'URAM': 0,\n", - " 'URAM_efficiency': 1,\n", - " 'DSP': 0}}" - ] - }, - "execution_count": 42, - "metadata": {}, - "output_type": "execute_result" - } - ], + "outputs": [], "source": [ "model_dwc = ModelWrapper(\"cybsec_DWC.onnx\")\n", "res_dict_dwc = model_dwc.analysis(res_estimation)\n", @@ -1013,7 +601,7 @@ }, { "cell_type": "code", - "execution_count": 48, + "execution_count": null, "metadata": {}, "outputs": [], "source": [ @@ -1025,20 +613,9 @@ }, { "cell_type": "code", - "execution_count": 50, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "data": { - "image/png": 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kBQYGZmpPT09XUlKS7XKf9evXa+zYsYqLi9Pff/9tN39SUpJtXTdy4MAB7dy5UyVKlMhyesYN/8eOHVPJkiXl5eVlN/2+++67xd7lrJwa0rx48eJq1qyZ5s6dq4kTJ0q6dlmfm5ubOnbsaJsv4x6XadOm6ciRI0pLS7NNy84lV9lx4MABJSUlyc/PL8vpGd9BWFiYIiMjNX78eE2ePFnh4eHq0KGDnnzySXl4eORILRMmTNCjjz6qKlWqqGbNmmrVqpW6d++uWrVqSZIOHjwowzA0evRojR49+ob1li5dWseOHVPdunUzTb+TPnPs2LEbrqNq1ar6+eef7drc3NxUpkyZW6737NmzOn/+vGbMmKEZM2ZkOU/G9yBJM2fO1DvvvKN9+/bZhdrrR/08dOiQSpUqJV9f31tu/9/HAEkqWrRopnvksrt80aJFJcm2fEYwvtmluElJSbblsuLq6qrQ0FCtW7dO0rUg1ahRIzVs2FBpaWnauHGj/P39lZiYaBekbtQPMi55PnbsmGrWrGlrz2rk1Azdu3eXm5ub9u7dq4CAgBvOdyvHjx/XmDFj9N1332X6jK//A1SLFi1UsmRJzZo1S82aNVN6erq++uorPfrooypSpIik2/tsb7aPQH5HkALuUX5+ftqxY4d++OEHLV26VEuXLlVMTIx69OihmTNn3vZ6XV1dTbUb//+a+kOHDqlZs2aqWrWq3n33XQUGBsrd3V3ff/+9Jk+enK2b+tPT09WiRQu99NJLWU6vUqVKNvfiznl4eNjd7H29jJB4/VmIO9WlSxf16tVLO3bsUEhIiObOnatmzZrZ7guRrt1UPnr0aPXu3VsTJ06Ur6+vXFxcNGTIkFt+vhaLJcv7H64PY9K178DPz0+zZs3Kcj0ZITfjOVwbN27U4sWL9cMPP6h379565513tHHjxkwhNzv+XUvjxo116NAhffvtt/rxxx/1ySefaPLkyZo+fbr69u1r2+fhw4crIiIiy3WaeVxAbrv+jOLNZOzXU089dcNfiDPC5JdffqmePXuqQ4cOevHFF+Xn5ydXV1dFR0fr0KFDt1XnrX7W73T5jP17++237e7hul52+k/Dhg31+uuv6/Lly1q3bp1eeeUV+fj4qGbNmlq3bp3t3svrg5RZN7uHrmPHjvr888/13nvvKTo6+rbWn5aWZru/asSIEapataoKFy6sP/74Qz179rT7uXZ1ddWTTz6pjz/+WNOmTdP69et16tQpu9FBb+ezzc59gkB+RZAC7mHu7u5q37692rdvr/T0dD3zzDP66KOPNHr0aFWqVOmuPgR28eLFSklJ0XfffWf3F+msRg+7UV0VK1bUxYsXb/mcnnLlymnFihW6ePGi3S8FZkfLutU2brS+jPbbvZQnKx06dFD//v1tl/f9/vvvGjVqlN088+fPV5MmTfTpp5/atZ8/f94ucGWlaNGiWV6alXFWJUPFihX1008/qUGDBtn6BatevXqqV6+eXn/9dc2ePVvdunXTnDlz1Ldv35vW8u8RFq9cuaLTp09nmtfX11e9evVSr169dPHiRTVu3Fjjxo1T3759VaFCBUlSgQIFstVnsrpE8E76TMb3v3//fjVt2jTTem+3f5QoUUJFihRRWlraLfdr/vz5qlChghYuXGj3c/XvS/gqVqyoH374QYmJidk6K5WbMi4btFqtt9y/mx3DGjVqpCtXruirr77SH3/8YQtMjRs3tgWpKlWq2AKVdOOf63379tmmZ9ezzz6rSpUqacyYMfL29tbIkSOzvWyGXbt26ffff9fMmTPVo0cPW/uNLtnu0aOH3nnnHS1evFhLly5ViRIl7P6IYOazBcDw58A969y5c3bvXVxcbH+lzhiWPON5IHdjWPCMv0Jf/1frpKQkxcTEZJq3cOHCWdb0+OOPKy4uTj/88EOmaefPn7fdj9WmTRulpqbaDa2elpamqVOn3ulu2LRp00YbN27U1q1bM9Uxa9YshYSE3NHlPP/m4+OjiIgIzZ07V3PmzJG7u7s6dOhgN4+rq2umswLz5s3LNNR2VipWrKh9+/bp7NmztrZff/0105DIjz/+uNLS0myXGF4vNTXV9r399ddfmWrJ+Av4v4fFz6qWjHtbMsyYMSPTGal/93EvLy9VqlTJtn4/Pz+Fh4fro48+yjKEXb+vGd/nL7/8Yjf9RmfesqNOnTry8/PT9OnT7fZ56dKl2rt3r9q2bXtb63V1dVVkZKQWLFig3377LdP06/crq5+7TZs2KS4uzm6ZyMhIGYaR5TD72T3TlFNq166tihUr6j//+Y8uXryYafr1+3ezY1jdunVVoEABvfnmm/L19VWNGjUkXQtYGzdu1Jo1azKdjWrTpo1++eUXu8/n0qVLmjFjhsqXL6/q1aub2pfRo0dr+PDhGjVqVKZHPWRHVt+fYRi2x1j8W61atVSrVi198sknWrBggbp06SI3t//7m7qZzxYAZ6SAfGvp0qW2v5Jer379+qpQoYL69u2rxMRENW3aVGXKlNGxY8c0depUhYSE2K73DwkJkaurq958800lJSXJw8PD9pynnNayZUvbGbL+/fvr4sWL+vjjj+Xn55fpl9zatWvrww8/1GuvvaZKlSrJz89PTZs21YsvvqjvvvtO7dq1U8+ePVW7dm1dunRJu3bt0vz583X06FEVL15c7du3V4MGDTRy5EgdPXpU1atX18KFC7M1oMX1FixYkOVnHBUVpZEjR2revHlq3Lix+vfvr6pVq+rUqVOKjY3V6dOnswyId+qJJ57QU089pWnTpikiIiLTw1/btWunCRMmqFevXqpfv7527dqlWbNm2c7M3Ezv3r317rvvKiIiQn369NGZM2c0ffp01ahRw+7ZOGFhYerfv7+io6O1Y8cOtWzZUgUKFNCBAwc0b948vffee+rUqZNmzpypadOm6bHHHlPFihV14cIFffzxx7JarWrTps1Na+nbt68GDBigyMhItWjRQr/++qt++OGHTGfVqlevrvDwcNWuXVu+vr7asmWL5s+fr8GDB9vm+eCDD9SwYUMFBwerX79+qlChghISEhQXF6eTJ0/anrH10ksv6YsvvlCrVq30/PPP24Y/L1eunHbu3HnLzy8rGb/E9+rVS2FhYeratatt+PPy5ctr6NCht7Ve6doQ4qtWrVLdunXVr18/Va9eXYmJidq2bZt++uknJSYmSrrWJxYuXKjHHntMbdu21ZEjRzR9+nRVr17d7hfpJk2aqHv37nr//fd14MABtWrVSunp6Vq3bp2aNGli95nmNhcXF33yySdq3bq1atSooV69eql06dL6448/tGrVKlmtVi1evFjStWOFdG0I+i5duqhAgQJq3769ChcurEKFCql27drauHGj7RlS0rUzUpcuXdKlS5cyBamRI0fqq6++UuvWrfXcc8/J19dXM2fO1JEjR7RgwYJsXXr5b2+//baSkpI0aNAgFSlSxNSDuKtWraqKFStq+PDh+uOPP2S1WrVgwYKb3o/Wo0cPDR8+XJIybcvMZwtADH8O5Dc3G/5c1w1zO3/+fKNly5aGn5+f4e7ubpQtW9bo37+/cfr0abv1ffzxx0aFChUMV1dXu2F3bzT8+b+HBM9q2GfD+L+hc8+ePWtr++6774xatWoZBQsWNMqXL2+8+eabxmeffZZp+OL4+Hijbdu2RpEiRQxJdnVcuHDBGDVqlFGpUiXD3d3dKF68uFG/fn3jP//5j92w7OfOnTO6d+9uWK1Ww9vb2+jevbuxfft2U8Of3+iVMTTyyZMnjb59+xqlS5c23NzcDF9fX6Ndu3bGxo0bb7p+s8OfZ0hOTjY8PT0NScaXX36Zafrly5eNF154wShZsqTh6elpNGjQwIiLi8v0XWY1/LlhGMaXX35pVKhQwXB3dzdCQkKMH374IdPw5xlmzJhh1K5d2/D09DSKFCliBAcHGy+99JJx6tQpwzCuDbvctWtXo2zZsoaHh4fh5+dntGvXztiyZcst9zMtLc0YMWKEUbx4caNQoUJGRESEcfDgwUzDn7/22mvGww8/bPj4+Bienp5G1apVjddff92uHxiGYRw6dMjo0aOHERAQYBQoUMAoXbq00a5dO2P+/Pl28+3cudMICwszChYsaJQuXdqYOHGi8emnn9728OcZvv76a+OBBx4wPDw8DF9fX6Nbt27GyZMn7eaJiooyChcufMvP5noJCQnGoEGDjMDAQKNAgQJGQECA0axZM2PGjBm2edLT041JkyYZ5cqVMzw8PIwHHnjAWLJkSZbfa2pqqvH2228bVatWNdzd3Y0SJUoYrVu3NrZu3WqbRzcY9v/f301WbnQMuVF/3L59u9GxY0ejWLFihoeHh1GuXDnj8ccfN1asWGE338SJE43SpUsbLi4umb6rF1980ZBkvPnmm3bLVKpUyZBkHDp0KFOdhw4dMjp16mT4+PgYBQsWNB5++GFjyZIl2doXw8i6L6SlpRldu3Y13NzcjG+++eaWn9H1w5/v2bPHaN68ueHl5WUUL17c6Nevn23I+ayOZadPnzZcXV2NKlWq3HA72flsszqGA/cai2Hw9DQAAIB7wZ9//qmSJUtqzJgxNxytEkD2cI8UAADAPSI2NlZpaWnq3r27o0sB8jzukQIAAMjnVq5cqT179uj1119Xhw4dVL58eUeXBOR5XNoHAACQz4WHh2vDhg1q0KCBvvzyS5UuXdrRJQF5HkEKAAAAAEziHikAAAAAMIkgBQAAAAAmMdiEpPT0dJ06dUpFihSxPZAPAAAAwL3HMAxduHBBpUqVuumDtglSkk6dOqXAwEBHlwEAAADASZw4cUJlypS54XSClKQiRYpIuvZhWa1WB1cDAAAAwFGSk5MVGBhoywg3QpCSbJfzWa1WghQAAACAW97yw2ATAAAAAGASQQoAAAAATCJIAQAAAIBJBCkAAAAAMIkgBQAAAAAmEaQAAAAAwCSCFAAAAACYRJACAAAAAJMIUgAAAABgEkEKAAAAAEwiSAEAAACASQQpAAAAADCJIAUAAAAAJhGkAAAAAMAkghQAAAAAmOTm6AKQBYvF0RXcOcNwdAUAAABAruGMFAAAAACYRJACAAAAAJMIUgAAAABgEkEKAAAAAEwiSAEAAACASQQpAAAAADCJIAUAAAAAJhGkAAAAAMAkghQAAAAAmESQAgAAAACTCFIAAAAAYJLTBKk33nhDFotFQ4YMsbVdvnxZgwYNUrFixeTl5aXIyEglJCTYLXf8+HG1bdtWhQoVkp+fn1588UWlpqbe5eoBAAAA3EucIkht3rxZH330kWrVqmXXPnToUC1evFjz5s3TmjVrdOrUKXXs2NE2PS0tTW3bttWVK1e0YcMGzZw5U7GxsRozZszd3gUAAAAA9xCHB6mLFy+qW7du+vjjj1W0aFFbe1JSkj799FO9++67atq0qWrXrq2YmBht2LBBGzdulCT9+OOP2rNnj7788kuFhISodevWmjhxoj744ANduXLFUbsEAAAAIJ9zeJAaNGiQ2rZtq+bNm9u1b926VVevXrVrr1q1qsqWLau4uDhJUlxcnIKDg+Xv72+bJyIiQsnJydq9e/cNt5mSkqLk5GS7FwAAAABkl5sjNz5nzhxt27ZNmzdvzjQtPj5e7u7u8vHxsWv39/dXfHy8bZ7rQ1TG9IxpNxIdHa3x48ffYfUAAAAA7lUOOyN14sQJPf/885o1a5YKFix4V7c9atQoJSUl2V4nTpy4q9sHAAAAkLc5LEht3bpVZ86c0YMPPig3Nze5ublpzZo1ev/99+Xm5iZ/f39duXJF58+ft1suISFBAQEBkqSAgIBMo/hlvM+YJyseHh6yWq12LwAAAADILocFqWbNmmnXrl3asWOH7VWnTh1169bN9u8CBQpoxYoVtmX279+v48ePKzQ0VJIUGhqqXbt26cyZM7Z5li9fLqvVqurVq9/1fQIAAABwb3DYPVJFihRRzZo17doKFy6sYsWK2dr79OmjYcOGydfXV1arVc8++6xCQ0NVr149SVLLli1VvXp1de/eXW+99Zbi4+P16quvatCgQfLw8Ljr+wQAAADg3uDQwSZuZfLkyXJxcVFkZKRSUlIUERGhadOm2aa7urpqyZIlGjhwoEJDQ1W4cGFFRUVpwoQJDqwaAAAAQH5nMQzDcHQRjpacnCxvb28lJSU5x/1SFoujK7hzdCsAAADkQdnNBg5/jhQAAAAA5DUEKQAAAAAwiSAFAAAAACYRpAAAAADAJIIUAAAAAJhEkAIAAAAAkwhSAAAAAGASQQoAAAAATCJIAQAAAIBJBCkAAAAAMIkgBQAAAAAmEaQAAAAAwCSCFAAAAACYRJACAAAAAJMIUgAAAABgEkEKAAAAAEwiSAEAAACASQQpAAAAADCJIAUAAAAAJhGkAAAAAMAkghQAAAAAmESQAgAAAACTCFIAAAAAYBJBCgAAAABMIkgBAAAAgEkEKQAAAAAwiSAFAAAAACYRpAAAAADAJIIUAAAAAJhEkAIAAAAAkwhSAAAAAGASQQoAAAAATCJIAQAAAIBJDg1SH374oWrVqiWr1Sqr1arQ0FAtXbrUNj08PFwWi8XuNWDAALt1HD9+XG3btlWhQoXk5+enF198UampqXd7VwAAAADcQ9wcufEyZcrojTfeUOXKlWUYhmbOnKlHH31U27dvV40aNSRJ/fr104QJE2zLFCpUyPbvtLQ0tW3bVgEBAdqwYYNOnz6tHj16qECBApo0adJd3x8AAAAA9waLYRiGo4u4nq+vr95++2316dNH4eHhCgkJ0ZQpU7Kcd+nSpWrXrp1OnTolf39/SdL06dM1YsQInT17Vu7u7tnaZnJysry9vZWUlCSr1ZpTu3L7LBZHV3DnnKtbAQAAANmS3WzgNPdIpaWlac6cObp06ZJCQ0Nt7bNmzVLx4sVVs2ZNjRo1Sn///bdtWlxcnIKDg20hSpIiIiKUnJys3bt333BbKSkpSk5OtnsBAAAAQHY59NI+Sdq1a5dCQ0N1+fJleXl5adGiRapevbok6cknn1S5cuVUqlQp7dy5UyNGjND+/fu1cOFCSVJ8fLxdiJJkex8fH3/DbUZHR2v8+PG5tEcAAAAA8juHB6n77rtPO3bsUFJSkubPn6+oqCitWbNG1atX19NPP22bLzg4WCVLllSzZs106NAhVaxY8ba3OWrUKA0bNsz2Pjk5WYGBgXe0HwAAAADuHQ6/tM/d3V2VKlVS7dq1FR0drfvvv1/vvfdelvPWrVtXknTw4EFJUkBAgBISEuzmyXgfEBBww216eHjYRgrMeAEAAABAdjk8SP1benq6UlJSspy2Y8cOSVLJkiUlSaGhodq1a5fOnDljm2f58uWyWq22ywMBAAAAIKc59NK+UaNGqXXr1ipbtqwuXLig2bNna/Xq1frhhx906NAhzZ49W23atFGxYsW0c+dODR06VI0bN1atWrUkSS1btlT16tXVvXt3vfXWW4qPj9err76qQYMGycPDw5G7BgAAACAfc2iQOnPmjHr06KHTp0/L29tbtWrV0g8//KAWLVroxIkT+umnnzRlyhRdunRJgYGBioyM1Kuvvmpb3tXVVUuWLNHAgQMVGhqqwoULKyoqyu65UwAAAACQ05zuOVKOwHOkcgHdCgAAAHlQnnuOFAAAAADkFQQpAAAAADCJIAUAAAAAJhGkAAAAAMAkghQAAAAAmESQAgAAAACTCFIAAAAAYBJBCgAAAABMIkgBAAAAgEkEKQAAAAAwiSAFAAAAACYRpAAAAADAJIIUAAAAAJhEkAIAAAAAkwhSAAAAAGASQQoAAAAATCJIAQAAAIBJBCkAAAAAMIkgBQAAAAAmuTm6AAAAss1icXQFd84wHF0BckJ+6IsS/TG/yA/9MQ/2Rc5IAQAAAIBJBCkAAAAAMIkgBQAAAAAmEaQAAAAAwCSCFAAAAACYRJACAAAAAJMIUgAAAABgEkEKAAAAAEwiSAEAAACASQQpAAAAADCJIAUAAAAAJhGkAAAAAMAkghQAAAAAmOTQIPXhhx+qVq1aslqtslqtCg0N1dKlS23TL1++rEGDBqlYsWLy8vJSZGSkEhIS7NZx/PhxtW3bVoUKFZKfn59efPFFpaam3u1dAQAAAHAPcWiQKlOmjN544w1t3bpVW7ZsUdOmTfXoo49q9+7dkqShQ4dq8eLFmjdvntasWaNTp06pY8eOtuXT0tLUtm1bXblyRRs2bNDMmTMVGxurMWPGOGqXAAAAANwDLIZhGI4u4nq+vr56++231alTJ5UoUUKzZ89Wp06dJEn79u1TtWrVFBcXp3r16mnp0qVq166dTp06JX9/f0nS9OnTNWLECJ09e1bu7u7Z2mZycrK8vb2VlJQkq9Waa/uWbRaLoyu4c87VrQDkFxwf4SzyQ1+U6I/5RX7oj07UF7ObDZzmHqm0tDTNmTNHly5dUmhoqLZu3aqrV6+qefPmtnmqVq2qsmXLKi4uTpIUFxen4OBgW4iSpIiICCUnJ9vOamUlJSVFycnJdi8AAAAAyC6HB6ldu3bJy8tLHh4eGjBggBYtWqTq1asrPj5e7u7u8vHxsZvf399f8fHxkqT4+Hi7EJUxPWPajURHR8vb29v2CgwMzNmdAgAAAJCvOTxI3XfffdqxY4c2bdqkgQMHKioqSnv27MnVbY4aNUpJSUm214kTJ3J1ewAAAADyFzdHF+Du7q5KlSpJkmrXrq3Nmzfrvffe0xNPPKErV67o/PnzdmelEhISFBAQIEkKCAjQL7/8Yre+jFH9MubJioeHhzw8PHJ4TwAAAADcKxx+Rurf0tPTlZKSotq1a6tAgQJasWKFbdr+/ft1/PhxhYaGSpJCQ0O1a9cunTlzxjbP8uXLZbVaVb169bteOwAAAIB7g0PPSI0aNUqtW7dW2bJldeHCBc2ePVurV6/WDz/8IG9vb/Xp00fDhg2Tr6+vrFarnn32WYWGhqpevXqSpJYtW6p69erq3r273nrrLcXHx+vVV1/VoEGDOOMEAAAAINc4NEidOXNGPXr00OnTp+Xt7a1atWrphx9+UIsWLSRJkydPlouLiyIjI5WSkqKIiAhNmzbNtryrq6uWLFmigQMHKjQ0VIULF1ZUVJQmTJjgqF0CAAAAcA9wuudIOQLPkcoFdCsAuYHjI5xFfuiLEv0xv8gP/dGJ+mKee44UAAAAAOQVBCkAAAAAMIkgBQAAAAAmEaQAAAAAwCSCFAAAAACYRJACAAAAAJMIUgAAAABgEkEKAAAAAEwiSAEAAACASQQpAAAAADCJIAUAAAAAJhGkAAAAAMAkghQAAAAAmESQAgAAAACTCFIAAAAAYBJBCgAAAABMcrudhQ4cOKBVq1bpzJkzSk9Pt5s2ZsyYHCkMAAAAAJyV6SD18ccfa+DAgSpevLgCAgJksVhs0ywWC0EKAAAAQL5nOki99tprev311zVixIjcqAcAAAAAnJ7pe6T++usvde7cOTdqAQAAAIA8wXSQ6ty5s3788cfcqAUAAAAA8gTTl/ZVqlRJo0eP1saNGxUcHKwCBQrYTX/uuedyrDgAAAAAcEYWwzAMMwsEBQXdeGUWiw4fPnzHRd1tycnJ8vb2VlJSkqxWq6PLka4bwCPPMtetACB7OD7CWeSHvijRH/OL/NAfnagvZjcbmD4jdeTIkTsqDAAAAADyujt6IK9hGDJ5QgsAAAAA8rzbClKff/65goOD5enpKU9PT9WqVUtffPFFTtcGAAAAAE7J9KV97777rkaPHq3BgwerQYMGkqSff/5ZAwYM0J9//qmhQ4fmeJEAAAAA4Exua7CJ8ePHq0ePHnbtM2fO1Lhx4/LkPVQMNpELuOQTQG7g+AhnkR/6okR/zC/yQ390or6Y3Wxg+tK+06dPq379+pna69evr9OnT5tdHQAAAADkOaaDVKVKlTR37txM7V9//bUqV66cI0UBAAAAgDMzfY/U+PHj9cQTT2jt2rW2e6TWr1+vFStWZBmwAAAAACC/MX1GKjIyUps2bVLx4sX1zTff6JtvvlHx4sX1yy+/6LHHHsuNGgEAAADAqZgebCI/YrCJXEC3ApAbOD7CWeSHvijRH/OL/NAfnagv5uhgE8nJyXb/vtnLjOjoaD300EMqUqSI/Pz81KFDB+3fv99unvDwcFksFrvXgAED7OY5fvy42rZtq0KFCsnPz08vvviiUlNTTdUCAAAAANmVrXukihYtqtOnT8vPz08+Pj6yZJF6DcOQxWJRWlpatje+Zs0aDRo0SA899JBSU1P18ssvq2XLltqzZ48KFy5sm69fv36aMGGC7X2hQoVs/05LS1Pbtm0VEBCgDRs26PTp0+rRo4cKFCigSZMmZbsWAAAAAMiubAWplStXytfXV5K0atWqHNv4smXL7N7HxsbKz89PW7duVePGjW3thQoVUkBAQJbr+PHHH7Vnzx799NNP8vf3V0hIiCZOnKgRI0Zo3Lhxcnd3z7RMSkqKUlJSbO/NnkkDAAAAcG/LVpAKCwuz/TsoKEiBgYGZzkoZhqETJ07cUTFJSUmSZAttGWbNmqUvv/xSAQEBat++vUaPHm07KxUXF6fg4GD5+/vb5o+IiNDAgQO1e/duPfDAA5m2Ex0drfHjx99RrQAAAADuXaaHPw8KCrJd5ne9xMREBQUFmbq073rp6ekaMmSIGjRooJo1a9ran3zySZUrV06lSpXSzp07NWLECO3fv18LFy6UJMXHx9uFKEm29/Hx8Vlua9SoURo2bJjtfXJysgIDA2+rbgAAAAD3HtNBKuNeqH+7ePGiChYseNuFDBo0SL/99pt+/vlnu/ann37a9u/g4GCVLFlSzZo106FDh1SxYsXb2paHh4c8PDxuu1YAAAAA97ZsB6mMMzgWi8Xu0jrp2oAPmzZtUkhIyG0VMXjwYC1ZskRr165VmTJlbjpv3bp1JUkHDx5UxYoVFRAQoF9++cVunoSEBEm64X1VAAAAAHAnsh2ktm/fLunaGaldu3bZDeLg7u6u+++/X8OHDze1ccMw9Oyzz2rRokVavXq1goKCbrnMjh07JEklS5aUJIWGhur111/XmTNnbJcbLl++XFarVdWrVzdVDwAAAABkh+kH8vbq1Uvvvfdejjy49plnntHs2bP17bff6r777rO1e3t7y9PTU4cOHdLs2bPVpk0bFStWTDt37tTQoUNVpkwZrVmzRtK1s2EhISEqVaqU3nrrLcXHx6t79+7q27dvtoc/54G8ucCJHqoGIB/h+AhnkR/6okR/zC/yQ390or6Y3WxgOkjlpKzutZKkmJgY9ezZUydOnNBTTz2l3377TZcuXVJgYKAee+wxvfrqq3Y7dezYMQ0cOFCrV69W4cKFFRUVpTfeeENubtk74UaQygVO9MMAIB/h+AhnkR/6okR/zC/yQ390or6Yq0Fqy5Ytmjt3ro4fP64rV67YTcsYTS8vIUjlAif6YQCQj3B8hLPID31Roj/mF/mhPzpRX8xuNnAxu+I5c+aofv362rt3rxYtWqSrV69q9+7dWrlypby9ve+oaAAAAADIC0wHqUmTJmny5MlavHix3N3d9d5772nfvn16/PHHVbZs2dyoEQAAAACciukgdejQIbVt21bStdH6Ll26JIvFoqFDh2rGjBk5XiAAAAAAOBvTQapo0aK6cOGCJKl06dL67bffJEnnz5/X33//nbPVAQAAAIATyvZzpDI0btxYy5cvV3BwsDp37qznn39eK1eu1PLly9WsWbPcqBEAAAAAnIrpIPXf//5Xly9fliS98sorKlCggDZs2KDIyEi9+uqrOV4gAAAAADgbhz5Hylkw/HkuoFsByA0cH+Es8kNflOiP+UV+6I9O1Bdzbfjzbdu2adeuXbb33377rTp06KCXX3450zOlAAAAACA/Mh2k+vfvr99//12SdPjwYT3xxBMqVKiQ5s2bp5deeinHCwQAAAAAZ2M6SP3+++8KCQmRJM2bN09hYWGaPXu2YmNjtWDBgpyuDwAAAACcjukgZRiG0tPTJUk//fST2rRpI0kKDAzUn3/+mbPVAQAAAIATMh2k6tSpo9dee01ffPGF1qxZY3s475EjR+Tv75/jBQIAAACAszEdpKZMmaJt27Zp8ODBeuWVV1SpUiVJ0vz581W/fv0cLxAAAAAAnE2ODX9++fJlubq6qkCBAjmxuruK4c9zgRMNYQkgH+H4CGeRH/qiRH/ML/JDf3SivpjdbGD6gbw3UrBgwZxaFQAAAAA4tWwFKV9fX/3+++8qXry4ihYtKstNUm9iYmKOFQcAAAAAzihbQWry5MkqUqSIpGv3SAEAAADAvSzH7pHKy7hHKhfQrQDkBo6PcBb5oS9K9Mf8Ij/0Ryfqizl6j1RycnK2N+wUQQQAAAAAclG2gpSPj89N74uSrj2o12KxKC0tLUcKAwAAAABnla0gtWrVqtyuAwAAAADyjGwFqbCwsNyuAwAAAADyjGwFqZ07d6pmzZpycXHRzp07bzpvrVq1cqQwAAAAAHBW2QpSISEhio+Pl5+fn0JCQmSxWJTVYH/cIwUAAADgXpCtIHXkyBGVKFHC9m8AAAAAuJdlK0iVK1fO9u9jx46pfv36cnOzXzQ1NVUbNmywmxcAAAAA8iMXsws0adJEiYmJmdqTkpLUpEmTHCkKAAAAAJyZ6SCV8byofzt37pwKFy6cI0UBAAAAgDPL1qV9ktSxY0dJ1waU6Nmzpzw8PGzT0tLStHPnTtWvXz/nKwQAAAAAJ5PtIOXt7S3p2hmpIkWKyNPT0zbN3d1d9erVU79+/XK+QgAAAABwMtkOUjExMZKk8uXLa/jw4VzGBwAAAOCeZTGyeiDUPSY5OVne3t5KSkqS1Wp1dDlSFveg5Tl0KwC5geMjnEV+6IsS/TG/yA/90Yn6YnazQbYHmyhatKh8fX0zvYKCghQREaHly5ebLjI6OloPPfSQihQpIj8/P3Xo0EH79++3m+fy5csaNGiQihUrJi8vL0VGRiohIcFunuPHj6tt27YqVKiQ/Pz89OKLLyo1NdV0PQAAAACQHdm+tG/KlClZtp8/f15bt25Vu3btNH/+fLVv3z7bG1+zZo0GDRqkhx56SKmpqXr55ZfVsmVL7dmzx3bp4NChQ/W///1P8+bNk7e3twYPHqyOHTtq/fr1kq4NdNG2bVsFBARow4YNOn36tHr06KECBQpo0qRJ2a4FAAAAALIrxy7te/fddzV//nxt2LDhttdx9uxZ+fn5ac2aNWrcuLGSkpJUokQJzZ49W506dZIk7du3T9WqVVNcXJzq1aunpUuXql27djp16pT8/f0lSdOnT9eIESN09uxZubu733K7XNqXC5zo9CyAfITjI5xFfuiLEv0xv8gP/dGJ+mKOX9p3K+3atdO+ffvuaB1JSUmSJF9fX0nS1q1bdfXqVTVv3tw2T9WqVVW2bFnFxcVJkuLi4hQcHGwLUZIUERGh5ORk7d69O8vtpKSkKDk52e4FAAAAANmVY0EqJSUlW2d/biQ9PV1DhgxRgwYNVLNmTUlSfHy83N3d5ePjYzevv7+/4uPjbfNcH6IypmdMy0p0dLS8vb1tr8DAwNuuGwAAAMC9J8eC1KeffqqQkJDbXn7QoEH67bffNGfOnJwq6YZGjRqlpKQk2+vEiRO5vk0AAAAA+Ue2B5sYNmxYlu1JSUnatm2bfv/9d61du/a2ihg8eLCWLFmitWvXqkyZMrb2gIAAXblyRefPn7c7K5WQkKCAgADbPL/88ovd+jJG9cuY5988PDzk4eFxW7UCAAAAQLaD1Pbt27Nst1qtatGihRYuXKigoCBTGzcMQ88++6wWLVqk1atXZ1q+du3aKlCggFasWKHIyEhJ0v79+3X8+HGFhoZKkkJDQ/X666/rzJkz8vPzkyQtX75cVqtV1atXN1UPAAAAAGSHQx/I+8wzz2j27Nn69ttvdd9999navb295enpKUkaOHCgvv/+e8XGxspqterZZ5+VJNvogGlpaQoJCVGpUqX01ltvKT4+Xt27d1ffvn2zPfw5o/blAicaeQVAPsLxEc4iP/RFif6YX+SH/uhEfTG72cChQcpygy89JiZGPXv2lHTtgbwvvPCCvvrqK6WkpCgiIkLTpk2zu2zv2LFjGjhwoFavXq3ChQsrKipKb7zxhtzcsnfCjSCVC5zohwFAPsLxEc4iP/RFif6YX+SH/uhEfTFPBClnQZDKBXQrALmB4yOcRX7oixL9Mb/ID/3RifriXX+OFAAAAADcKwhSAAAAAGBStoNU7969deHChdysBQAAAADyhGwHqZkzZ+qff/7JzVoAAAAAIE/IdpBiTAoAAAAAuCbbD+SVpAsXLqhgwYI3nccpRr0DAAAAgFxkKkhVqVLlhtMMw5DFYlFaWtodFwUAAAAAzsxUkJo/f758fX1zqxYAAAAAyBNMBakGDRrIz88vt2oBAAAAgDyB50gBAAAAgEnZDlLlypWTq6trbtYCAAAAAHlCti/tO3LkSG7WAQAAAAB5RraDVNGiRWWxWDK1e3t7q0qVKho+fLhatGiRo8UBAAAAgDPKdpCaPHlylkHq/Pnz2rp1q9q1a6f58+erffv2OVogAAAAADibbAepnj173nR6SEiIoqOjCVIAAAAA8r0cG7WvXbt22rdvX06tDgAAAACcVo4FqZSUFLm7u+fU6gAAAADAaeVYkPr0008VEhKSU6sDAAAAAKeV7Xukhg0blmV7UlKStm3bpt9//11r167NscIAAAAAwFllO0ht3749y3ar1aoWLVpo4cKFCgoKyrHCAAAAAMBZZTtIrVq16qbTT548qaefflozZsy446IAAAAAwJnl2D1S586d06effppTqwMAAAAAp5VjQQoAAAAA7hUEKQAAAAAwiSAFAAAAACZle7CJjh073nT6+fPn77QWAAAAAMgTsh2kvL29bzm9R48ed1wQAAAAADi7bAepmJiY3KwDAAAAAPIM7pECAAAAAJMIUgAAAABgEkEKAAAAAEwiSAEAAACASQQpAAAAADDJoUFq7dq1at++vUqVKiWLxaJvvvnGbnrPnj1lsVjsXq1atbKbJzExUd26dZPVapWPj4/69Omjixcv3sW9AAAAAHCvcWiQunTpku6//3598MEHN5ynVatWOn36tO311Vdf2U3v1q2bdu/ereXLl2vJkiVau3atnn766dwuHQAAAMA9LNvPkcoNrVu3VuvWrW86j4eHhwICArKctnfvXi1btkybN29WnTp1JElTp05VmzZt9J///EelSpXK8ZoBAAAAwOnvkVq9erX8/Px03333aeDAgTp37pxtWlxcnHx8fGwhSpKaN28uFxcXbdq06YbrTElJUXJyst0LAAAAALLLqYNUq1at9Pnnn2vFihV68803tWbNGrVu3VppaWmSpPj4ePn5+dkt4+bmJl9fX8XHx99wvdHR0fL29ra9AgMDc3U/AAAAAOQvDr2071a6dOli+3dwcLBq1aqlihUravXq1WrWrNltr3fUqFEaNmyY7X1ycjJhCgAAAEC2OfUZqX+rUKGCihcvroMHD0qSAgICdObMGbt5UlNTlZiYeMP7qqRr911ZrVa7FwAAAABkV54KUidPntS5c+dUsmRJSVJoaKjOnz+vrVu32uZZuXKl0tPTVbduXUeVCQAAACCfc+ilfRcvXrSdXZKkI0eOaMeOHfL19ZWvr6/Gjx+vyMhIBQQE6NChQ3rppZdUqVIlRURESJKqVaumVq1aqV+/fpo+fbquXr2qwYMHq0uXLozYBwAAACDXWAzDMBy18dWrV6tJkyaZ2qOiovThhx+qQ4cO2r59u86fP69SpUqpZcuWmjhxovz9/W3zJiYmavDgwVq8eLFcXFwUGRmp999/X15eXtmuIzk5Wd7e3kpKSnKOy/wsFkdXcOcc160A5GccH+Es8kNflOiP+UV+6I9O1Bezmw0cGqScBUEqF9CtAOQGjo9wFvmhL0r0x/wiP/RHJ+qL2c0GeeoeKQAAAABwBgQpAAAAADCJIAUAAAAAJhGkAAAAAMAkghQAAAAAmESQAgAAAACTCFIAAAAAYBJBCgAAAABMIkgBAAAAgEkEKQAAAAAwiSAFAAAAACYRpAAAAADAJIIUAAAAAJhEkAIAAAAAkwhSAAAAAGASQQoAAAAATCJIAQAAAIBJBCkAAAAAMIkgBQAAAAAmEaQAAAAAwCSCFAAAAACYRJACAAAAAJMIUgAAAABgEkEKAAAAAEwiSAEAAACASQQpAAAAADCJIAUAAAAAJhGkAAAAAMAkghQAAAAAmESQAgAAAACTCFIAAAAAYBJBCgAAAABMIkgBAAAAgEkODVJr165V+/btVapUKVksFn3zzTd20w3D0JgxY1SyZEl5enqqefPmOnDggN08iYmJ6tatm6xWq3x8fNSnTx9dvHjxLu4FAAAAgHuNQ4PUpUuXdP/99+uDDz7Icvpbb72l999/X9OnT9emTZtUuHBhRURE6PLly7Z5unXrpt27d2v58uVasmSJ1q5dq6effvpu7QIAAACAe5DFMAzD0UVIksVi0aJFi9ShQwdJ185GlSpVSi+88IKGDx8uSUpKSpK/v79iY2PVpUsX7d27V9WrV9fmzZtVp04dSdKyZcvUpk0bnTx5UqVKlcrWtpOTk+Xt7a2kpCRZrdZc2T9TLBZHV3DnnKNbAchvOD7CWeSHvijRH/OL/NAfnagvZjcbOO09UkeOHFF8fLyaN29ua/P29lbdunUVFxcnSYqLi5OPj48tRElS8+bN5eLiok2bNt1w3SkpKUpOTrZ7AQAAAEB2OW2Qio+PlyT5+/vbtfv7+9umxcfHy8/Pz266m5ubfH19bfNkJTo6Wt7e3rZXYGBgDlcPAAAAID9z2iCVm0aNGqWkpCTb68SJE44uCQAAAEAe4rRBKiAgQJKUkJBg156QkGCbFhAQoDNnzthNT01NVWJiom2erHh4eMhqtdq9AAAAACC7nDZIBQUFKSAgQCtWrLC1JScna9OmTQoNDZUkhYaG6vz589q6dattnpUrVyo9PV1169a96zUDAAAAuDe4OXLjFy9e1MGDB23vjxw5oh07dsjX11dly5bVkCFD9Nprr6ly5coKCgrS6NGjVapUKdvIftWqVVOrVq3Ur18/TZ8+XVevXtXgwYPVpUuXbI/YBwAAAABmOTRIbdmyRU2aNLG9HzZsmCQpKipKsbGxeumll3Tp0iU9/fTTOn/+vBo2bKhly5apYMGCtmVmzZqlwYMHq1mzZnJxcVFkZKTef//9u74vAAAAAO4dTvMcKUfiOVK5gG4FIDdwfISzyA99UaI/5hf5oT86UV/M88+RAgAAAABnRZACAAAAAJMIUgAAAABgEkEKAAAAAEwiSAEAAACASQQpAAAAADCJIAUAAAAAJhGkAAAAAMAkghQAAAAAmESQAgAAAACTCFIAAAAAYBJBCgAAAABMIkgBAAAAgEkEKQAAAAAwiSAFAAAAACYRpAAAAADAJIIUAAAAAJhEkAIAAAAAkwhSAAAAAGASQQoAAAAATCJIAQAAAIBJBCkAAAAAMIkgBQAAAAAmEaQAAAAAwCSCFAAAAACYRJACAAAAAJMIUgAAAABgEkEKAAAAAEwiSAEAAACASQQpAAAAADCJIAUAAAAAJhGkAAAAAMAkghQAAAAAmOTUQWrcuHGyWCx2r6pVq9qmX758WYMGDVKxYsXk5eWlyMhIJSQkOLBiAAAAAPcCpw5SklSjRg2dPn3a9vr5559t04YOHarFixdr3rx5WrNmjU6dOqWOHTs6sFoAAAAA9wI3RxdwK25ubgoICMjUnpSUpE8//VSzZ89W06ZNJUkxMTGqVq2aNm7cqHr16t3tUgEAAADcI5z+jNSBAwdUqlQpVahQQd26ddPx48clSVu3btXVq1fVvHlz27xVq1ZV2bJlFRcXd9N1pqSkKDk52e4FAAAAANnl1EGqbt26io2N1bJly/Thhx/qyJEjatSokS5cuKD4+Hi5u7vLx8fHbhl/f3/Fx8ffdL3R0dHy9va2vQIDA3NxLwAAAADkN059aV/r1q1t/65Vq5bq1q2rcuXKae7cufL09Lzt9Y4aNUrDhg2zvU9OTiZMAQAAAMg2pz4j9W8+Pj6qUqWKDh48qICAAF25ckXnz5+3mychISHLe6qu5+HhIavVavcCAAAAgOzKU0Hq4sWLOnTokEqWLKnatWurQIECWrFihW36/v37dfz4cYWGhjqwSgAAAAD5nVNf2jd8+HC1b99e5cqV06lTpzR27Fi5urqqa9eu8vb2Vp8+fTRs2DD5+vrKarXq2WefVWhoKCP2AQAAAMhVTh2kTp48qa5du+rcuXMqUaKEGjZsqI0bN6pEiRKSpMmTJ8vFxUWRkZFKSUlRRESEpk2b5uCqAQAAAOR3FsMwDEcX4WjJycny9vZWUlKSc9wvZbE4uoI7R7cCkBs4PsJZ5Ie+KNEf84v80B+dqC9mNxvkqXukAAAAAMAZEKQAAAAAwCSCFAAAAACYRJACAAAAAJMIUgAAAABgEkEKAAAAAEwiSAEAAACASQQpAAAAADCJIAUAAAAAJhGkAAAAAMAkghQAAAAAmESQAgAAAACTCFIAAAAAYBJBCgAAAABMIkgBAAAAgEkEKQAAAAAwiSAFAAAAACYRpAAAAADAJIIUAAAAAJhEkAIAAAAAkwhSAAAAAGASQQoAAAAATCJIAQAAAIBJBCkAAAAAMIkgBQAAAAAmEaQAAAAAwCSCFAAAAACYRJACAAAAAJMIUgAAAABgEkEKAAAAAEwiSAEAAACASQQpAAAAADCJIAUAAAAAJuWbIPXBBx+ofPnyKliwoOrWratffvnF0SUBAAAAyKfyRZD6+uuvNWzYMI0dO1bbtm3T/fffr4iICJ05c8bRpQF5n8WS918AAAA5LF8EqXfffVf9+vVTr169VL16dU2fPl2FChXSZ5995ujSAAAAAORDbo4u4E5duXJFW7du1ahRo2xtLi4uat68ueLi4rJcJiUlRSkpKbb3SUlJkqTk5OTcLfZewmcJZ0J/hDOhP8KZ0B/hLJyoL2ZkAsMwbjpfng9Sf/75p9LS0uTv72/X7u/vr3379mW5THR0tMaPH5+pPTAwMFdqvCd5ezu6AuD/0B/hTOiPcCb0RzgLJ+yLFy5ckPdN6srzQep2jBo1SsOGDbO9T09PV2JioooVKyZLPr+fIjk5WYGBgTpx4oSsVqujy8E9jv4IZ0J/hDOhP8KZ3Gv90TAMXbhwQaVKlbrpfHk+SBUvXlyurq5KSEiwa09ISFBAQECWy3h4eMjDw8OuzcfHJ7dKdEpWq/We+EFA3kB/hDOhP8KZ0B/hTO6l/nizM1EZ8vxgE+7u7qpdu7ZWrFhha0tPT9eKFSsUGhrqwMoAAAAA5Fd5/oyUJA0bNkxRUVGqU6eOHn74YU2ZMkWXLl1Sr169HF0aAAAAgHwoXwSpJ554QmfPntWYMWMUHx+vkJAQLVu2LNMAFLh2WePYsWMzXdoIOAL9Ec6E/ghnQn+EM6E/Zs1i3GpcPwAAAACAnTx/jxQAAAAA3G0EKQAAAAAwiSAFAAAAACYRpAAAAADAJIJUHtKzZ09ZLBYNGDAg07RBgwbJYrGoZ8+eat++vVq1apXlOtatWyeLxaKdO3dq9erVslgsOn/+fKb5ypcvrylTptjeJyYmqlu3brJarfLx8VGfPn108eLFnNo1OLmMvmexWFSgQAH5+/urRYsW+uyzz5Seni5J6tKlS6Z+t2zZMlksFo0bN86ufdy4cSpbtqxd24IFCxQeHi5vb295eXmpVq1amjBhghITE7NV4+rVq/Xggw/Kw8NDlSpVUmxs7G3vL/IWRx4bX3/9ddWvX1+FChW65x7sjqw5qj8ePXpUffr0UVBQkDw9PVWxYkWNHTtWV65cycndQx7jyOPjI488orJly6pgwYIqWbKkunfvrlOnTuXUrjkFglQeExgYqDlz5uiff/6xtV2+fFmzZ8+2/WLap08fLV++XCdPnsy0fExMjOrUqaNatWqZ2m63bt20e/duLV++XEuWLNHatWv19NNP39nOIE9p1aqVTp8+raNHj2rp0qVq0qSJnn/+ebVr106pqalq0qSJ1q9fr9TUVNsyq1atUmBgoFavXm23rlWrVqlJkya296+88oqeeOIJPfTQQ1q6dKl+++03vfPOO/r111/1xRdf3LK2I0eOqG3btmrSpIl27NihIUOGqG/fvvrhhx9ybP/h3Bx1bLxy5Yo6d+6sgQMH3tkOIF9xRH/ct2+f0tPT9dFHH2n37t2aPHmypk+frpdffvnOdwh5mqOOj02aNNHcuXO1f/9+LViwQIcOHVKnTp3ubGecDEEqj3nwwQcVGBiohQsX2toWLlyosmXL6oEHHpAktWvXTiVKlMj0F/mLFy9q3rx56tOnj6lt7t27V8uWLdMnn3yiunXrqmHDhpo6darmzJmT7/6ygBvz8PBQQECASpcurQcffFAvv/yyvv32Wy1dulSxsbFq0qSJLl68qC1bttiWWb16tUaOHKlNmzbp8uXLkq4dvDdt2mQLUr/88osmTZqkd955R2+//bbq16+v8uXLq0WLFlqwYIGioqJuWdv06dMVFBSkd955R9WqVdPgwYPVqVMnTZ48OXc+DDgdRxwbJWn8+PEaOnSogoOD76h+5C+O6I+tWrVSTEyMWrZsqQoVKuiRRx7R8OHD7WrAvclRx8ehQ4eqXr16KleunOrXr6+RI0dq48aNunr16h3tjzMhSOVBvXv3VkxMjO39Z599pl69etneu7m5qUePHoqNjdX1jwmbN2+e0tLS1LVrV1Pbi4uLk4+Pj+rUqWNra968uVxcXLRp06Y72BPkdU2bNtX999+vhQsXqkqVKipVqpRWrVolSbpw4YK2bdumzp07q3z58oqLi5MkbdiwQSkpKbYgNWvWLHl5eemZZ57JchvZuVwqLi5OzZs3t2uLiIiwbRP3hrt9bARuxhn6Y1JSknx9fe94Pcj7HN0fExMTNWvWLNWvX18FChS4o3U5E4JUHvTUU0/p559/1rFjx3Ts2DGtX79eTz31lN08vXv31qFDh7RmzRpbW0xMjCIjI+Xt7W1qe/Hx8fLz87Nrc3Nzk6+vr+Lj429/R5AvVK1aVUePHpV07TR+xmV869atU5UqVVSiRAk1btzY1r569WoFBQWpXLlykqQDBw6oQoUKd3RgjY+Pl7+/v12bv7+/kpOT7S5lQP52t4+NwM04uj8ePHhQU6dOVf/+/e9oPcgfHNUfR4wYocKFC6tYsWI6fvy4vv322zvaD2dDkMqDSpQoobZt2yo2NlYxMTFq27atihcvbjdP1apVVb9+fX322WeSrh1Q161bd1unZoGbMQxDFotFkhQeHq7169fr6tWrWr16tcLDwyVJYWFhdkHq+vujrv/LF3AnODbCmTiyP/7xxx9q1aqVOnfurH79+t3RupA/OKo/vvjii9q+fbt+/PFHubq6qkePHvnq//sEqTyqd+/eio2N1cyZM9W7d+8s5+nTp48WLFigCxcuKCYmRhUrVlRYWJhtutVqlXTt1P+/nT9/3vbXh4CAAJ05c8ZuempqqhITExUQEJBTu4Q8au/evQoKCpJ07YzUpUuXtHnzZq1atcrW38LCwrRp0yYlJiZq06ZNatq0qW35KlWq6PDhw3d0zXRAQIASEhLs2hISEmS1WuXp6Xnb60XeczePjcCtOKI/njp1Sk2aNFH9+vU1Y8aMHNwb5HWO6I/FixdXlSpV1KJFC82ZM0fff/+9Nm7cmIN75VgEqTyqVatWunLliq5evaqIiIgs53n88cfl4uKi2bNn6/PPP1fv3r1tZw4kqXLlynJxcdHWrVvtljt8+LCSkpJUpUoVSVJoaKjOnz9vN9/KlSuVnp6uunXr5sLeIa9YuXKldu3apcjISElSxYoVFRgYqO+++047duywHXxLly6t0qVL65133tGVK1fszkg9+eSTunjxoqZNm5blNrIaYvXfQkNDtWLFCru25cuXKzQ09Db3DHnV3Tw2Ardyt/vjH3/8ofDwcNWuXVsxMTFyceHXPPwfRx8fMx6XkpKSkgN74xzcHF0Abo+rq6v27t1r+3dWvLy89MQTT2jUqFFKTk5Wz5497aYXKVJEffv21QsvvCA3NzcFBwfrxIkTGjFihOrVq6f69etLkqpVq6ZWrVqpX79+mj59uq5evarBgwerS5cuKlWqVK7uJ5xHSkqK4uPjlZaWpoSEBC1btkzR0dFq166devToYZuvSZMmmjZtmipVqmR331JYWJimTp1qG5QiQ926dfXSSy/phRde0B9//KHHHntMpUqV0sGDBzV9+nQ1bNhQzz///E1rGzBggP773//qpZdeUu/evbVy5UrNnTtX//vf/3L+g4BTu5vHRkk6fvy4EhMTdfz4caWlpWnHjh2SpEqVKsnLyytX9hF5x93sjxkhqly5cvrPf/6js2fP2tbB1SOQ7m5/3LRpkzZv3qyGDRuqaNGiOnTokEaPHq2KFSvmrz9yGsgzoqKijEcfffSG0x999FEjKirKrm3Dhg2GJKNNmzZZLvPPP/8YY8eONapWrWp4enoaQUFBxtNPP22cPXvWbr5z584ZXbt2Nby8vAyr1Wr06tXLuHDhwp3uEvKIqKgoQ5IhyXBzczNKlChhNG/e3Pjss8+MtLQ0u3ljYmIMScaAAQPs2mNjYw1JRv/+/bPcxtdff200btzYKFKkiFG4cGGjVq1axoQJE4y//vorWzWuWrXKCAkJMdzd3Y0KFSoYMTExt7OryIMceWy8/mfj+teqVavucK+QVzmqP2Yce7N64d7lqP64c+dOo0mTJoavr6/h4eFhlC9f3hgwYIBx8uTJnNgtp2ExjHx0xxcAAAAA3AVcPAsAAAAAJhGkADi9GjVqyMvLK8vXrFmzHF0eAAC4B3FpHwCnd+zYsRsOj+7v768iRYrc5YoAAMC9jiAFAAAAACZxaR8AAAAAmESQAgAAAACTCFIAAAAAYBJBCgAAAABMIkgBAO5p4eHhGjJkiKPLAADkMQQpAMBt6dmzpywWi9544w279m+++UYWi8XUusqXL68pU6bkYHW55+jRo7JYLNqxY4ejSwEAOBBBCgBw2woWLKg333xTf/31l6NLMe3KlSuOLiFH3ehZawCA3EGQAgDctubNmysgIEDR0dE3ne/nn39Wo0aN5OnpqcDAQD333HO6dOmSpGuX1h07dkxDhw6VxWKRxWKRYRgqUaKE5s+fb1tHSEiISpYsabdODw8P/f3335Kk48eP69FHH5WXl5esVqsef/xxJSQk2OYfN26cQkJC9MknnygoKEgFCxbMstb//e9/8vb21qxZs27rMzl06JAeffRR+fv7y8vLSw899JB++ukn2/QJEyaoZs2amZYLCQnR6NGjbe8/+eQTVatWTQULFlTVqlU1bdo027SMs2Jff/21wsLCVLBgQc2aNUvHjh1T+/btVbRoURUuXFg1atTQ999/f1v7AQC4OYIUAOC2ubq6atKkSZo6dapOnjyZ5TyHDh1Sq1atFBkZqZ07d+rrr7/Wzz//rMGDB0uSFi5cqDJlymjChAk6ffq0Tp8+LYvFosaNG2v16tWSpL/++kt79+7VP//8o3379kmS1qxZo4ceekiFChVSenq6Hn30USUmJmrNmjVavny5Dh8+rCeeeMKuloMHD2rBggVauHBhlpfmzZ49W127dtWsWbPUrVu32/pMLl68qDZt2mjFihXavn27WrVqpfbt2+v48eOSpN69e2vv3r3avHmzbZnt27dr586d6tWrlyRp1qxZGjNmjF5//XXt3btXkyZN0ujRozVz5ky7bY0cOVLPP/+89u7dq4iICA0aNEgpKSlau3atdu3apTfffFNeXl63tR8AgJtzc3QBAIC87bHHHlNISIjGjh2rTz/9NNP06OhodevWzTagQ+XKlfX+++8rLCxMH374oXx9feXq6qoiRYooICDAtlx4eLg++ugjSdLatWv1wAMPKCAgQKtXr1bVqlW1evVqhYWFSZJWrFihXbt26ciRIwoMDJQkff7556pRo4Y2b96shx56SNK1y/k+//xzlShRIlOdH3zwgV555RUtXrzYtt7bcf/99+v++++3vZ84caIWLVqk7777ToMHD1aZMmUUERGhmJgYW10xMTEKCwtThQoVJEljx47VO++8o44dO0qSgoKCtGfPHn300UeKioqyrXvIkCG2eaRrZ+UiIyMVHBwsSbb1AQByHmekAAB37M0339TMmTO1d+/eTNN+/fVXxcbGysvLy/aKiIhQenq6jhw5csN1hoWFac+ePTp79qzWrFmj8PBwhYeHa/Xq1bp69ao2bNig8PBwSdLevXsVGBhoC1GSVL16dfn4+NjVVK5cuSxD1Pz58zV06FAtX778jkKUdO2M1PDhw1WtWjX5+PjIy8tLe/futZ2RkqR+/frpq6++0uXLl3XlyhXNnj1bvXv3liRdunRJhw4dUp8+few+s9dee02HDh2y21adOnXs3j/33HN67bXX1KBBA40dO1Y7d+68o30BANwYQQoAcMcaN26siIgIjRo1KtO0ixcvqn///tqxY4ft9euvv+rAgQOqWLHiDdcZHBwsX19frVmzxi5IrVmzRps3b9bVq1dVv359U3UWLlw4y/YHHnhAJUqU0GeffSbDMEyt89+GDx+uRYsWadKkSVq3bp127Nih4OBgu8Et2rdvLw8PDy1atEiLFy/W1atX1alTJ0nXPi9J+vjjj+0+s99++00bN2686f707dtXhw8fVvfu3bVr1y7VqVNHU6dOvaP9AQBkjUv7AAA54o033lBISIjuu+8+u/YHH3xQe/bsUaVKlW64rLu7u9LS0uzaLBaLGjVqpG+//Va7d+9Ww4YNVahQIaWkpOijjz5SnTp1bEGiWrVqOnHihE6cOGE7K7Vnzx6dP39e1atXv2XtFStW1DvvvKPw8HC5urrqv//9r9ndt1m/fr169uypxx57TNK1YHT06FG7edzc3BQVFaW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z&-yQt&+&@?%}>4f{I9xZd++@Ex4!VBFMj0p*S_%i7k}mT*IxY4>wo&W|L{{U zUd-;dzw_Z2{>F>HuJ-HQmgSp&=f#hH_1zEkueo@wi~p6k4&eZKUd9;z zCAW=9i+{v#EdSuey?;)@FTVJ(n|}lA1%D}Sit*() zZ;fAm=b6T@9E~6R^z8@oV=sQ>KmGc*zV*(py!+w1AO80H-}u7ke&LsX`77aEZ|6zp zdO1%z*Sopnd^^9FKe6BNuf6>XU;7uo_;dgA3xE5?k9_!zZ~f-CKX~W8cYmAj=!<{* z#b5g3KYH_vKmWyl|G_Wbd(A(-&-<(Yibwvm)8=RK8BLoX*!MK;=Py5}-{b50^8KHn z+e_(v{p?phxZSe8E6?AuzBJF@vc5fcw!Hnh7Y}cI{_UT9@#B26f95}a=Qlt6_HVrN V?e~A?SHJPCZ+!6XdvCn Date: Tue, 27 Jun 2023 12:25:00 +0100 Subject: [PATCH 180/665] [tests] Enable ci to automatically test new folding nb --- notebooks/advanced/3_folding.ipynb | 11 +++++++---- tests/notebooks/test_jupyter_notebooks.py | 1 + 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/notebooks/advanced/3_folding.ipynb b/notebooks/advanced/3_folding.ipynb index 1eb99206e2..07b66da52f 100644 --- a/notebooks/advanced/3_folding.ipynb +++ b/notebooks/advanced/3_folding.ipynb @@ -85,10 +85,12 @@ "metadata": {}, "outputs": [], "source": [ + "import os\n", "from qonnx.core.modelwrapper import ModelWrapper\n", - "model = ModelWrapper(\"cybsec_PE_SIMD.onnx\")\n", + "model_path = os.environ[\"FINN_ROOT\"] + \"/notebooks/advanced/cybsec_PE_SIMD.onnx\" \n", + "model = ModelWrapper(model_path)\n", "\n", - "showInNetron(\"cybsec_PE_SIMD.onnx\")" + "showInNetron(model_path)" ] }, { @@ -137,7 +139,7 @@ "metadata": {}, "outputs": [], "source": [ - "showInNetron(\"cybsec_PE_SIMD.onnx\")" + "showInNetron(model_path)" ] }, { @@ -415,7 +417,8 @@ "metadata": {}, "outputs": [], "source": [ - "model_orig = ModelWrapper(\"cybsec_PE_SIMD.onnx\")\n", + "dir_path = os.environ[\"FINN_ROOT\"] + \"/notebooks/advanced/\" \n", + "model_orig = ModelWrapper(dir_path + \"cybsec_PE_SIMD.onnx\")\n", "model_updated = ModelWrapper(\"cybsec_PE_SIMD_modified.onnx\")" ] }, diff --git a/tests/notebooks/test_jupyter_notebooks.py b/tests/notebooks/test_jupyter_notebooks.py index 819b4ccde0..836f1e059e 100644 --- a/tests/notebooks/test_jupyter_notebooks.py +++ b/tests/notebooks/test_jupyter_notebooks.py @@ -21,6 +21,7 @@ pytest.param(notebook_advanced_dir + "0_custom_analysis_pass.ipynb"), pytest.param(notebook_advanced_dir + "1_custom_transformation_pass.ipynb"), pytest.param(notebook_advanced_dir + "2_custom_op.ipynb"), + pytest.param(notebook_advanced_dir + "3_folding.ipynb"), ] cyber_notebooks = [ From bad0613b01047590da19cfa8abc919621a587214 Mon Sep 17 00:00:00 2001 From: Hugo LE BLEVEC Date: Wed, 28 Jun 2023 09:58:11 +0200 Subject: [PATCH 181/665] Changing test to use ConvTranspose from standard ONNX as a reference model for comparison --- .../fpgadataflow/test_fpgadataflow_deconv.py | 210 +++++++++--------- 1 file changed, 103 insertions(+), 107 deletions(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_deconv.py b/tests/fpgadataflow/test_fpgadataflow_deconv.py index 07d1d30b16..92738a6dee 100644 --- a/tests/fpgadataflow/test_fpgadataflow_deconv.py +++ b/tests/fpgadataflow/test_fpgadataflow_deconv.py @@ -46,7 +46,11 @@ InferConvInpGen, InferQuantizedMatrixVectorActivation, ) -from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP + +# from finn.transformation.fpgadataflow.create_dataflow_partition import ( +# CreateDataflowPartition, +# ) +# from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim from finn.transformation.fpgadataflow.prepare_ip import PrepareIP @@ -60,75 +64,67 @@ target_clk_ns = 10 -def convolution_2d( - x: np.ndarray, - weight: np.ndarray, - in_channels: int, - out_channels: int, - kernel_size: int = 3, - padding: int = 0, - stride: int = 1, -) -> np.ndarray: - Ic, Ih, Iw = x[0, :].shape - assert Ic == in_channels - Oh = 1 + (Ih - kernel_size + 2 * padding) // stride - Ow = 1 + (Iw - kernel_size + 2 * padding) // stride - output = np.zeros((1, out_channels, Oh, Ow)) - for oh in range(Oh): - for ow in range(Ow): - for oc in range(out_channels): - for ic in range(in_channels): - for kh in range(kernel_size): - for kw in range(kernel_size): - ih = stride * oh + kh - padding - iw = stride * ow + kw - padding - if ih >= 0 and ih < Ih and iw >= 0 and iw < Iw: - output[0, oc, oh, ow] += ( - weight[oc, ic, kh, kw] * x[0, ic, ih, iw] - ) - return output - - -def fractionally_strided_convolution( - x: np.ndarray, - weight: np.ndarray, - in_channels: int, - out_channels: int, - kernel_size: int = 3, - padding: int = 0, - stride: np.ndarray = np.array([1, 1]), -) -> np.ndarray: - x_ = np.zeros( - ( +def set_up_reference_model(idt, wdt, k, idim, ifm_ch, ofm_ch, stride, padding, weights): + idim_h, idim_w = idim + stride_h, stride_w = stride + odim_h = (idim_h - 1) * stride_h - 2 * padding + (k - 1) + 1 + odim_w = (idim_w - 1) * stride_w - 2 * padding + (k - 1) + 1 + odt = DataType["INT32"] + + inp = helper.make_tensor_value_info( + "inp", + TensorProto.FLOAT, + [ 1, - x.shape[1], - x.shape[2] + (x.shape[2] - 1) * (stride[0] - 1), - x.shape[3] + (x.shape[3] - 1) * (stride[1] - 1), - ) + ifm_ch, + idim_h, + idim_w, + ], + ) + outp = helper.make_tensor_value_info( + "outp", TensorProto.FLOAT, [1, ofm_ch, odim_h, odim_w] ) - # adding the zeros into the input space for the fractional strides - for i in range(x.shape[2]): - for j in range(x.shape[3]): - ih = i * stride[0] - iw = j * stride[1] - x_[0, :, ih, iw] = x[0, :, i, j] - padding = kernel_size - padding - 1 - stride = 1 - # weight = np.rot90(weight, 2, [2,3]) - # weight = np.moveaxis(weight, 0, 1) - output = convolution_2d( - x_, - weight=weight, - in_channels=in_channels, - out_channels=out_channels, - kernel_size=kernel_size, - stride=stride, - padding=padding, + + W = helper.make_tensor_value_info("W", TensorProto.FLOAT, [ofm_ch, ifm_ch, k, k]) + + ConvTranspose = helper.make_node( + "ConvTranspose", + ["inp", "W"], + ["outp"], + dilations=(1, 1), + group=1, + kernel_shape=(k, k), + pads=(padding, padding, padding, padding), + strides=(stride_h, stride_w), + ) + + node_list = [ConvTranspose] + value_info = [W] + + graph = helper.make_graph( + nodes=node_list, + name="convtranspose_graph", + inputs=[inp], + outputs=[outp], + value_info=value_info, ) - return output + + model = qonnx_make_model(graph, producer_name="convtranspose-model") + model = ModelWrapper(model) + + # initialize model + model.set_tensor_datatype("inp", idt) + model.set_tensor_datatype(model.graph.output[0].name, odt) + model.set_tensor_datatype("W", wdt) + + model.set_initializer("W", weights) + + model = model.transform(InferShapes()) + + return model -def set_up_reference_model(idt, wdt, k, idim, ifm_ch, ofm_ch, stride, padding, simd): +def set_up_test_model(idt, wdt, k, idim, ifm_ch, ofm_ch, stride, padding, simd): idim_h, idim_w = idim stride_h, stride_w = stride @@ -157,8 +153,8 @@ def set_up_reference_model(idt, wdt, k, idim, ifm_ch, ofm_ch, stride, padding, s FMPadding_Pixel = helper.make_node( "FMPadding_Pixel", - [inp], - [out_pad], + ["inp"], + ["out_pad"], domain="finn.custom_op.fpgadataflow", backend="fpgadataflow", ImgDim=idim, @@ -174,8 +170,8 @@ def set_up_reference_model(idt, wdt, k, idim, ifm_ch, ofm_ch, stride, padding, s Conv = helper.make_node( "Conv", - [out_pad_trans, W], - [outp], + ["out_pad_trans", "W"], + ["outp"], dilations=(1, 1), group=1, kernel_shape=(k, k), @@ -184,7 +180,7 @@ def set_up_reference_model(idt, wdt, k, idim, ifm_ch, ofm_ch, stride, padding, s ) node_list = [FMPadding_Pixel, Transpose, Conv] - value_info = [W] + value_info = [W, out_pad, out_pad_trans] graph = helper.make_graph( nodes=node_list, @@ -225,13 +221,10 @@ def set_up_reference_model(idt, wdt, k, idim, ifm_ch, ofm_ch, stride, padding, s @pytest.mark.parametrize("k", [2, 4]) # padding @pytest.mark.parametrize("padding", [0, 1]) -# execution mode -@pytest.mark.parametrize("mode", ["cppsim", "rtlsim"]) -# @pytest.mark.parametrize("mode", ["stitched_ip_rtlsim"]) @pytest.mark.fpgadataflow @pytest.mark.slow @pytest.mark.vivado -def test_fpgadataflow_deconv(idim, stride, ifm_ch, ofm_ch, simd, pe, k, padding, mode): +def test_fpgadataflow_deconv(idim, stride, ifm_ch, ofm_ch, simd, pe, k, padding): idt = wdt = DataType["INT4"] idim_h, idim_w = idim stride_h, stride_w = stride @@ -241,19 +234,22 @@ def test_fpgadataflow_deconv(idim, stride, ifm_ch, ofm_ch, simd, pe, k, padding, else: convinpgen_rtl = True - if convinpgen_rtl and mode == "cppsim": - pytest.skip("ConvolutionInputGenerator_rtl has no cppsim, skipping") - - model = set_up_reference_model( - idt, wdt, k, idim, ifm_ch, ofm_ch, stride, padding, simd - ) + model = set_up_test_model(idt, wdt, k, idim, ifm_ch, ofm_ch, stride, padding, simd) odim_h = (idim_h - 1) * stride_h - 2 * padding + (k - 1) + 1 odim_w = (idim_w - 1) * stride_w - 2 * padding + (k - 1) + 1 input_tensor = gen_finn_dt_tensor(idt, [1, idim_h, idim_w, ifm_ch]) + input_tensor_tr = input_tensor.transpose(0, 3, 1, 2) weight_tensor = model.get_initializer("W") + weight_tensor = np.rot90(weight_tensor, 2, [2, 3]) + weight_tensor = np.moveaxis(weight_tensor, 0, 1) input_dict = {"inp": input_tensor} + input_dict_tr = {"inp": input_tensor_tr} + + ref_model = set_up_reference_model( + idt, wdt, k, idim, ifm_ch, ofm_ch, stride, padding, weight_tensor + ) model = model.transform(LowerConvsToMatMul()) model = model.transform(InferDataTypes()) @@ -261,10 +257,6 @@ def test_fpgadataflow_deconv(idim, stride, ifm_ch, ofm_ch, simd, pe, k, padding, model = model.transform(InferQuantizedMatrixVectorActivation()) model = model.transform(AbsorbConsecutiveTransposes()) model = model.transform(InferShapes()) - if mode == "stitched_ip_rtlsim": - model = model.transform(SetExecMode("rtlsim")) - else: - model = model.transform(SetExecMode(mode)) model = model.transform(GiveUniqueNodeNames()) for n in model.graph.node: @@ -276,31 +268,35 @@ def test_fpgadataflow_deconv(idim, stride, ifm_ch, ofm_ch, simd, pe, k, padding, mvau_node.set_nodeattr("PE", pe) mvau_node.set_nodeattr("SIMD", simd) - if mode == "cppsim": + expected_oshape = (1, ofm_ch, odim_h, odim_w) + y_expected = oxe.execute_onnx(ref_model, input_dict_tr)["outp"] + # cppsim + if convinpgen_rtl: + print("ConvolutionInputGenerator_rtl has no cppsim, skipping cppsim") + else: model = model.transform(PrepareCppSim()) model = model.transform(CompileCppSim()) - elif mode == "rtlsim": - model = model.transform(PrepareIP(test_fpga_part, target_clk_ns)) - model = model.transform(HLSSynthIP()) - model = model.transform(PrepareRTLSim()) - elif mode == "stitched_ip_rtlsim": - model = model.transform(PrepareIP(test_fpga_part, target_clk_ns)) - model = model.transform(HLSSynthIP()) - model = model.transform( - CreateStitchedIP(test_fpga_part, target_clk_ns, vitis=False) - ) - + model = model.transform(SetExecMode("cppsim")) + y_produced = oxe.execute_onnx(model, input_dict)["outp"] + assert y_produced.shape == expected_oshape + assert (y_produced == y_expected).all() + + # rtlsim + model = model.transform(PrepareIP(test_fpga_part, target_clk_ns)) + model = model.transform(HLSSynthIP()) + # parent_model = model.transform(CreateDataflowPartition()) + # sdp_nodes = parent_model.get_nodes_by_op_type("StreamingDataflowPartition") + # assert len(sdp_nodes) == 1, "Only a single StreamingDataflowPartition supported." + # sdp_node = sdp_nodes[0] + # sdp_node = getCustomOp(sdp_node) + # dataflow_model_filename = sdp_node.get_nodeattr("model") + # model = ModelWrapper(dataflow_model_filename) + # model = model.transform( + # CreateStitchedIP(test_fpga_part, target_clk_ns, vitis=False) + # ) + model = model.transform(PrepareRTLSim()) + # model = model.transform(GiveReadableTensorNames()) + model = model.transform(SetExecMode("rtlsim")) y_produced = oxe.execute_onnx(model, input_dict)["outp"] - expected_oshape = (1, ofm_ch, odim_h, odim_w) assert y_produced.shape == expected_oshape - - y_expected = fractionally_strided_convolution( - input_tensor.transpose(0, 3, 1, 2), - weight_tensor, - ifm_ch, - ofm_ch, - k, - padding, - stride, - ) assert (y_produced == y_expected).all() From 3db0e2c83e627bb1e187a5a4ac89cc418e92f3bb Mon Sep 17 00:00:00 2001 From: Hugo LE BLEVEC Date: Wed, 28 Jun 2023 10:00:20 +0200 Subject: [PATCH 182/665] Creating (ConvTranspose -> FMPixelPadding + ConvInpGen + MVAU) transformation --- .../infer_pixel_padding_deconv.py | 244 ++++++++++++++++++ 1 file changed, 244 insertions(+) create mode 100644 src/finn/transformation/fpgadataflow/infer_pixel_padding_deconv.py diff --git a/src/finn/transformation/fpgadataflow/infer_pixel_padding_deconv.py b/src/finn/transformation/fpgadataflow/infer_pixel_padding_deconv.py new file mode 100644 index 0000000000..ac4b121155 --- /dev/null +++ b/src/finn/transformation/fpgadataflow/infer_pixel_padding_deconv.py @@ -0,0 +1,244 @@ +import numpy as np +import warnings +from onnx import TensorProto, helper +from qonnx.transformation.base import Transformation +from qonnx.transformation.lower_convs_to_matmul import _auto_pad_to_explicit_padding +from qonnx.util.basic import get_by_name + +from finn.transformation.fpgadataflow.convert_to_hls_layers import ( + InferConvInpGen, + InferQuantizedMatrixVectorActivation, +) + + +class InferPixelPaddingDeconv(Transformation): + def __init__(self, use_convinpgen_rtl_variant=False): + super().__init__() + self.use_convinpgen_rtl_variant = use_convinpgen_rtl_variant + + def apply(self, model): + graph = model.graph + node_ind = 0 + graph_modified = False + for n in graph.node: + node_ind += 1 + if n.op_type == "ConvTranspose": + deconv_input = n.input[0] + deconv_output = n.output[0] + idt = model.get_tensor_datatype(deconv_input) + odt = model.get_tensor_datatype(deconv_output) + if not idt.is_integer(): + warnings.warn( + "%s : Input is not int. Can't infer PixelPaddingDeconv." + % n.name + ) + continue + # extract conv transpose parameters + k_h = get_by_name(n.attribute, "kernel_shape").ints[0] + k_w = get_by_name(n.attribute, "kernel_shape").ints[1] + stride_h = get_by_name(n.attribute, "strides").ints[0] + stride_w = get_by_name(n.attribute, "strides").ints[1] + group = get_by_name(n.attribute, "group").i + weight_name = n.input[1] + W_conv = model.get_initializer(weight_name) + ifm_ch = model.get_tensor_shape(n.input[0])[1] # assume NCHW + ofm_ch = model.get_tensor_shape(n.output[0])[1] # assume NCHW + ifm_dim_h = model.get_tensor_shape(n.input[0])[2] # assume NCHW + ifm_dim_w = model.get_tensor_shape(n.input[0])[3] + ofm_dim_h = model.get_tensor_shape(n.output[0])[2] # assume NCHW + ofm_dim_w = model.get_tensor_shape(n.output[0])[3] + dilation_attr = get_by_name(n.attribute, "dilations") + if dilation_attr is not None: + dilation = dilation_attr.ints + else: + dilation = [1, 1] # default value + # handle both auto_pad and explicit padding + auto_pad = get_by_name(n.attribute, "auto_pad") + if auto_pad is not None: + # find equivalent specified padding + auto_pad = auto_pad.s.decode("utf-8") + if auto_pad == "NOTSET": + # use specified padding + pad = get_by_name(n.attribute, "pads").ints + else: + pad = _auto_pad_to_explicit_padding( + auto_pad, + ifm_dim_h, + ifm_dim_w, + k_h, + k_w, + stride_h, + stride_w, + len(model.get_tensor_shape(n.input[0])) - 2, + ) + else: + # use specified padding + pad = get_by_name(n.attribute, "pads").ints + + # If len(pad) == 2, assume no padding for other dimension + if len(pad) == 2: # only one dimension should be padded + assert ( + ifm_dim_h == 1 or ifm_dim_w == 1 + ), "Padding is assumed to be 1D, image is 2D" + + # if depthwise conv create sparse matrix and variable "dw" + # to store as attribute in Im2Col that indicates that the created + # Im2Col node belongs to a depthwise convolution + dw = False + if group == ifm_ch and ofm_ch == ifm_ch: + W_sparse = np.zeros( + (ofm_ch, ifm_ch, k_h, k_w) + ) # (OFM, IFM, k_H, k_W) + for ch in range(ifm_ch): + W_sparse[ch][ch] = W_conv[ch][ + 0 + ] # W_conv = [OFM, IFM, k_H, k_W] + W_conv = W_sparse.astype(np.float32) + # we need to store information of the + # sparsity of the weight matrix. For this + # we use the sparsity annotation of the + # weight tensor + sparsity = {"dw": {"kernel_shape": [k_h, k_w]}} + model.set_tensor_sparsity(weight_name, sparsity) + # additionally create variable "dw" to store + # as attribute in Im2Col that indicates that the created + # Im2Col node belongs to a depthwise convolution + dw = True + + # reuse conv weights for new matmul weights + # conv weights are [OFM][IFM][k][k] + # We need to rotate the weights and swap the first two dimensions + # for pixel padding deconv to remain mathematically equivalent + # and then first convert to [OFM][k][k][IFM] (to remain compatible + # with finn-hlslib and how it does im2col/sliding window) + W_conv = np.rot90(W_conv, 2, [2, 3]) + W_conv = np.moveaxis(W_conv, 0, 1) + W_matmul = W_conv.transpose(0, 2, 3, 1) # W_conv = [OFM, IFM, k_H, k_W] + # reshape into [OFM][k*k*IFM] matrix + W_matmul = W_matmul.reshape(ofm_ch, ifm_ch * k_h * k_w) + # transpose to get ONNX-compatible [k*k*IFM][OFM] matrix + W_matmul = W_matmul.T + model.set_initializer(weight_name, W_matmul) + + # Compute intermediate parameters + padded_odim_h = ifm_dim_h + (ifm_dim_h - 1) * (stride_h - 1) + padded_odim_w = ifm_dim_w + (ifm_dim_w - 1) * (stride_w - 1) + conv_padding = [dilation[0] * (k_h - 1) - pad[0]] * 4 + + # create new intermediate values + inp_trans_out = helper.make_tensor_value_info( + model.make_new_valueinfo_name(), + TensorProto.FLOAT, + (1, ifm_dim_h, ifm_dim_w, ifm_ch), # NHWC + ) + padding_pixel_out = helper.make_tensor_value_info( + model.make_new_valueinfo_name(), + TensorProto.FLOAT, + (1, padded_odim_h, padded_odim_w, ifm_ch), # NHWC + ) + graph.value_info.append(inp_trans_out) + graph.value_info.append(padding_pixel_out) + inp_trans_out = inp_trans_out.name + padding_pixel_out = padding_pixel_out.name + model.set_tensor_datatype(inp_trans_out, idt) + model.set_tensor_datatype(padding_pixel_out, idt) + + need_im2col = True + if all(p == 0 for p in conv_padding): + padding = 0 + + # k_h=k_w==1: pointwise convolution, thus no im2col needed + if ( + k_h == 1 + and k_w == 1 + and padding == 0 + and stride_h == 1 + and stride_w == 1 + ): + need_im2col = False + + if need_im2col: + im2col_out = helper.make_tensor_value_info( + model.make_new_valueinfo_name(), + TensorProto.FLOAT, + (1, ofm_dim_h, ofm_dim_w, ifm_ch * k_h * k_w), + ) + graph.value_info.append(im2col_out) + im2col_out = im2col_out.name + model.set_tensor_datatype(im2col_out, idt) + + matmul_out = helper.make_tensor_value_info( + model.make_new_valueinfo_name(), + TensorProto.FLOAT, + (1, ofm_dim_h, ofm_dim_w, ofm_ch), + ) + graph.value_info.append(matmul_out) + matmul_out = matmul_out.name + model.set_tensor_datatype(matmul_out, odt) + + # create new nodes + + # NCHW -> NHWC + inp_trans_node = helper.make_node( + "Transpose", [deconv_input], [inp_trans_out], perm=[0, 2, 3, 1] + ) + # Pixel Padding + fmpadding_pixel_node = helper.make_node( + "FMPadding_Pixel", + [inp_trans_out], + [padding_pixel_out], + domain="finn.custom_op.fpgadataflow", + backend="fpgadataflow", + ImgDim=(ifm_dim_h, ifm_dim_w), + Stride=[stride_h, stride_w], + NumChannels=ifm_ch, + inputDataType=str(idt.name), + numInputVectors=1, + SIMD=1, + ) + # lower input tensor + matmul_input = padding_pixel_out + if need_im2col: + matmul_input = im2col_out + im2col_node = helper.make_node( + "Im2Col", + [padding_pixel_out], + [im2col_out], + domain="qonnx.custom_op.general", + stride=[1, 1], + kernel_size=[k_h, k_w], + pad_amount=conv_padding, + input_shape="(1,{},{},{})".format( + padded_odim_h, padded_odim_w, ifm_ch + ), + depthwise=dw, + dilations=dilation, + ) + + # do matmul + matmul_node = helper.make_node( + "MatMul", [matmul_input, weight_name], [matmul_out] + ) + # NHWC -> NCHW + out_trans_node = helper.make_node( + "Transpose", [matmul_out], [deconv_output], perm=[0, 3, 1, 2] + ) + # insert nodes where the conv is to preserve topological ordering + graph.node.insert(node_ind, inp_trans_node) + if need_im2col: + graph.node.insert(node_ind + 1, fmpadding_pixel_node) + graph.node.insert(node_ind + 2, im2col_node) + graph.node.insert(node_ind + 3, matmul_node) + graph.node.insert(node_ind + 4, out_trans_node) + else: + graph.node.insert(node_ind + 1, fmpadding_pixel_node) + graph.node.insert(node_ind + 2, matmul_node) + graph.node.insert(node_ind + 3, out_trans_node) + # remove old nodes + graph.node.remove(n) + + model = model.transform( + InferConvInpGen(use_rtl_variant=self.use_convinpgen_rtl_variant) + ) + model = model.transform(InferQuantizedMatrixVectorActivation()) + return (model, graph_modified) From 21f191ec9f64e33fc767a861297b76d25c8597ea Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 28 Jun 2023 14:18:44 +0100 Subject: [PATCH 183/665] [gha] Update python version for pre-commit gha --- .github/workflows/pre-commit.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/pre-commit.yml b/.github/workflows/pre-commit.yml index 5f03379bbc..011ccebadc 100644 --- a/.github/workflows/pre-commit.yml +++ b/.github/workflows/pre-commit.yml @@ -18,7 +18,7 @@ jobs: - name: Setup Python uses: actions/setup-python@v4 with: - python-version: '3.8' + python-version: '3.10' - name: Run Lint uses: pre-commit/action@v3.0.0 From d3465bc31684886ef1079184f486f36a75c640e2 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 28 Jun 2023 14:31:31 +0100 Subject: [PATCH 184/665] [linting] Pre-commit with python 3.10 on all files --- .pre-commit-config.yaml | 3 +- .../cybersecurity/dataloader_quantized.py | 18 +-- .../cybersecurity/validate-unsw-nb15.py | 4 +- .../fpgadataflow/dataflow_performance.py | 4 +- .../analysis/fpgadataflow/post_synth_res.py | 2 +- .../analysis/fpgadataflow/res_estimation.py | 5 +- src/finn/builder/build_dataflow.py | 18 +-- src/finn/builder/build_dataflow_config.py | 14 +-- src/finn/builder/build_dataflow_steps.py | 60 +++------- src/finn/core/onnx_exec.py | 8 +- .../fpgadataflow/addstreams_batch.py | 16 +-- .../fpgadataflow/channelwise_op_batch.py | 39 ++----- src/finn/custom_op/fpgadataflow/checksum.py | 19 +--- src/finn/custom_op/fpgadataflow/concat.py | 21 +--- .../fpgadataflow/convolutioninputgenerator.py | 8 +- .../convolutioninputgenerator1d.py | 37 ++---- .../convolutioninputgenerator_rtl.py | 78 ++++--------- .../custom_op/fpgadataflow/downsampler.py | 4 +- .../fpgadataflow/duplicatestreams_batch.py | 16 +-- src/finn/custom_op/fpgadataflow/eltwise.py | 17 +-- .../custom_op/fpgadataflow/fmpadding_batch.py | 4 +- .../custom_op/fpgadataflow/fmpadding_rtl.py | 12 +- .../fpgadataflow/globalaccpool_batch.py | 8 +- .../custom_op/fpgadataflow/hlscustomop.py | 28 ++--- src/finn/custom_op/fpgadataflow/iodma.py | 30 ++--- .../fpgadataflow/labelselect_batch.py | 8 +- src/finn/custom_op/fpgadataflow/lookup.py | 24 +--- .../fpgadataflow/matrixvectoractivation.py | 94 ++++------------ src/finn/custom_op/fpgadataflow/pool_batch.py | 16 +-- .../streamingdatawidthconverter_batch.py | 26 ++--- .../custom_op/fpgadataflow/streamingfifo.py | 32 ++---- .../fpgadataflow/streamingmaxpool_batch.py | 12 +- .../fpgadataflow/thresholding_batch.py | 72 +++--------- .../custom_op/fpgadataflow/tlastmarker.py | 16 +-- src/finn/custom_op/fpgadataflow/upsampler.py | 8 +- .../fpgadataflow/vectorvectoractivation.py | 80 ++++--------- .../qnn-data/cybsec-mlp/validate-unsw-nb15.py | 8 +- .../qnn-data/templates/driver/driver_base.py | 32 ++---- .../qnn-data/templates/driver/validate.py | 4 +- .../fpgadataflow/annotate_resources.py | 4 +- .../transformation/fpgadataflow/cleanup.py | 4 +- .../fpgadataflow/compile_cppsim.py | 4 +- .../fpgadataflow/convert_to_hls_layers.py | 78 ++++--------- .../fpgadataflow/create_stitched_ip.py | 106 +++++------------- .../fpgadataflow/derive_characteristic.py | 30 ++--- .../fpgadataflow/externalize_params.py | 6 +- .../transformation/fpgadataflow/floorplan.py | 9 +- .../fpgadataflow/hlssynth_ip.py | 12 +- .../transformation/fpgadataflow/insert_dwc.py | 3 +- .../fpgadataflow/insert_fifo.py | 19 +--- .../fpgadataflow/insert_hook.py | 3 +- .../fpgadataflow/insert_iodma.py | 31 ++--- .../fpgadataflow/insert_tlastmarker.py | 13 +-- .../fpgadataflow/make_pynq_driver.py | 59 +++------- .../fpgadataflow/make_zynq_proj.py | 43 ++----- .../fpgadataflow/prepare_cppsim.py | 4 +- .../transformation/fpgadataflow/prepare_ip.py | 4 +- .../fpgadataflow/prepare_rtlsim.py | 4 +- .../fpgadataflow/set_exec_mode.py | 4 +- .../fpgadataflow/set_fifo_depths.py | 27 ++--- .../fpgadataflow/set_folding.py | 15 +-- .../fpgadataflow/vitis_build.py | 49 +++----- src/finn/transformation/move_reshape.py | 8 +- .../qonnx/convert_qonnx_to_finn.py | 4 +- .../qonnx/fold_quant_weights.py | 19 +--- .../qonnx/infer_quant_avg_pool_2d.py | 53 ++------- .../qonnx/qonnx_activation_handlers.py | 32 ++---- .../qonnx/quant_act_to_multithreshold.py | 4 +- src/finn/transformation/streamline/absorb.py | 47 ++------ src/finn/transformation/streamline/reorder.py | 86 +++----------- .../streamline/round_thresholds.py | 3 +- src/finn/util/create.py | 8 +- src/finn/util/data_packing.py | 20 +--- src/finn/util/imagenet.py | 15 +-- src/finn/util/platforms.py | 12 +- src/finn/util/pyverilator.py | 20 +--- src/finn/util/test.py | 4 +- src/finn/util/vcd.py | 4 +- .../brevitas/test_brevitas_avg_pool_export.py | 2 +- tests/brevitas/test_brevitas_mobilenet.py | 8 +- ...revitas_non_scaled_quanthardtanh_export.py | 8 +- tests/brevitas/test_brevitas_qlinear.py | 8 +- .../brevitas/test_brevitas_relu_act_export.py | 2 - .../test_brevitas_scaled_qhardtanh_export.py | 8 +- .../brevitas/test_brevitas_selu_act_export.py | 4 +- .../test_brevitas_validate_mobilenet.py | 6 +- tests/end2end/test_end2end_bnn_pynq.py | 100 +++++------------ tests/end2end/test_end2end_cybsec_mlp.py | 17 ++- tests/end2end/test_end2end_mobilenet_v1.py | 20 +--- .../test_convert_to_hls_1d_conv_layer.py | 16 +-- .../test_convert_to_hls_channelwise_layer.py | 17 +-- .../test_convert_to_hls_conv_fc_transition.py | 60 +++------- .../test_convert_to_hls_conv_layer.py | 12 +- .../test_convert_to_hls_layers_cnv.py | 6 +- .../test_convert_to_hls_layers_fc.py | 6 +- .../test_convert_to_hls_layers_synthetic.py | 20 +--- .../test_convert_to_hls_pool_batch.py | 36 ++---- .../test_depthwise_convolution.py | 17 +-- tests/fpgadataflow/test_fifosizing.py | 11 +- .../test_fpgadataflow_channelwise_ops.py | 4 +- .../test_fpgadataflow_checksum.py | 8 +- .../test_fpgadataflow_convinputgenerator.py | 20 +--- .../test_fpgadataflow_convinputgenerator1d.py | 16 +-- ...est_fpgadataflow_convinputgenerator_rtl.py | 28 ++--- ...dataflow_convinputgenerator_rtl_dynamic.py | 60 +++------- .../test_fpgadataflow_downsampler.py | 4 +- .../test_fpgadataflow_duplicatestreams.py | 8 +- tests/fpgadataflow/test_fpgadataflow_dwc.py | 9 +- tests/fpgadataflow/test_fpgadataflow_fifo.py | 6 +- .../test_fpgadataflow_fmpadding.py | 16 +-- .../test_fpgadataflow_globalaccpool.py | 4 +- .../test_fpgadataflow_ipstitch.py | 8 +- .../test_fpgadataflow_labelselect.py | 4 +- .../fpgadataflow/test_fpgadataflow_lookup.py | 4 +- .../test_fpgadataflow_streamingmaxpool.py | 16 +-- .../test_fpgadataflow_thresholding.py | 28 ++--- tests/fpgadataflow/test_fpgadataflow_vvau.py | 12 +- tests/fpgadataflow/test_minimize_bit_width.py | 26 +---- tests/fpgadataflow/test_runtime_weights.py | 4 +- tests/fpgadataflow/test_set_folding.py | 10 +- tests/fpgadataflow/test_split_large_fifos.py | 8 +- tests/notebooks/test_jupyter_notebooks.py | 4 +- .../streamline/test_absorb_mul_into_topk.py | 16 +-- .../test_absorb_transp_into_flatten.py | 4 +- .../streamline/test_linear_past_eltwise.py | 20 +--- .../streamline/test_maxpool_nhwc.py | 24 +--- .../streamline/test_move_chw_add_past_conv.py | 8 +- .../test_move_identical_op_past_join_op.py | 16 +-- .../test_move_maxpool_past_multithreshold.py | 12 +- .../streamline/test_move_mul_past_dw_conv.py | 8 +- .../streamline/test_move_mul_past_maxpool.py | 8 +- .../streamline/test_move_past_fork.py | 8 +- .../test_move_scalar_past_matmul.py | 8 +- .../streamline/test_scale_resize_nhwc.py | 44 ++------ .../test_infer_data_layouts_cnv.py | 10 +- tests/transformation/test_qonnx_to_finn.py | 15 +-- tests/util/test_build_dataflow.py | 20 +--- tests/util/test_create.py | 4 +- tests/util/test_data_packing_hls.py | 8 +- tutorials/fpga_flow/gen_tb_data.py | 4 +- 140 files changed, 702 insertions(+), 2001 deletions(-) diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index 42a18b2737..72a9688505 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -60,11 +60,12 @@ repos: hooks: - id: black language_version: python3 + args: [--line-length=100] - repo: https://github.com/PyCQA/flake8 rev: 6.0.0 hooks: - id: flake8 # black-compatible flake-8 config - args: ['--max-line-length=88', # black default + args: ['--max-line-length=100', # black default '--extend-ignore=E203'] # E203 is not PEP8 compliant diff --git a/notebooks/end2end_example/cybersecurity/dataloader_quantized.py b/notebooks/end2end_example/cybersecurity/dataloader_quantized.py index 738811fa72..38505fb6ef 100644 --- a/notebooks/end2end_example/cybersecurity/dataloader_quantized.py +++ b/notebooks/end2end_example/cybersecurity/dataloader_quantized.py @@ -48,7 +48,6 @@ def __init__( onehot=False, train=True, ): - self.dataframe = ( pd.concat([pd.read_csv(file_path_train), pd.read_csv(file_path_test)]) .reset_index() @@ -77,9 +76,7 @@ def __getitem__(self, index): data_val = self.data[index][:-1] return data_val, target - def dec2bin( - self, column: pd.Series, number_of_bits: int, left_msb: bool = True - ) -> pd.Series: + def dec2bin(self, column: pd.Series, number_of_bits: int, left_msb: bool = True) -> pd.Series: """Convert a decimal pd.Series to binary pd.Series with numbers in their # base-2 equivalents. The output is a numpy nd array. @@ -133,6 +130,7 @@ def integer_encoding(self, df): def quantize_df(self, df): """Quantized the input dataframe. The scaling is done by multiplying every column by the inverse of the minimum of that column""" + # gets the smallest positive number of a vector def get_min_positive_number(vector): return vector[vector > 0].min() @@ -178,24 +176,18 @@ def char_split(s): column_data = np.clip( column_data, 0, 4294967295 ) # clip due to overflow of uint32 of matlab code - column_data = self.round_like_matlab_series( - column_data - ) # round like matlab + column_data = self.round_like_matlab_series(column_data) # round like matlab column_data = column_data.astype(np.uint32) # cast like matlab if column == "rate": column_data.update(pd.Series(dict_correct_rate_values)) python_quantized_df[column] = ( - self.dec2bin(column_data, maxbits, left_msb=False) - .reshape((-1, 1)) - .flatten() + self.dec2bin(column_data, maxbits, left_msb=False).reshape((-1, 1)).flatten() ) for column in python_quantized_df.columns: - python_quantized_df[column] = ( - python_quantized_df[column].apply(char_split).values - ) + python_quantized_df[column] = python_quantized_df[column].apply(char_split).values python_quantized_df_separated = pd.DataFrame( np.column_stack(python_quantized_df.values.T.tolist()) diff --git a/notebooks/end2end_example/cybersecurity/validate-unsw-nb15.py b/notebooks/end2end_example/cybersecurity/validate-unsw-nb15.py index 0ffb525544..c4570616d2 100644 --- a/notebooks/end2end_example/cybersecurity/validate-unsw-nb15.py +++ b/notebooks/end2end_example/cybersecurity/validate-unsw-nb15.py @@ -57,9 +57,7 @@ def make_unsw_nb15_test_batches(bsize, dataset_root): help='name of bitfile (i.e. "resizer.bit")', default="../bitfile/finn-accel.bit", ) - parser.add_argument( - "--dataset_root", help="dataset root dir for download/reuse", default="." - ) + parser.add_argument("--dataset_root", help="dataset root dir for download/reuse", default=".") # parse arguments args = parser.parse_args() bsize = args.batchsize diff --git a/src/finn/analysis/fpgadataflow/dataflow_performance.py b/src/finn/analysis/fpgadataflow/dataflow_performance.py index 5726702666..824690f5f6 100644 --- a/src/finn/analysis/fpgadataflow/dataflow_performance.py +++ b/src/finn/analysis/fpgadataflow/dataflow_performance.py @@ -66,9 +66,7 @@ def dataflow_performance(model): max_pred_latency = 0 else: # find max of any of predecessors - pred_latencies = map( - lambda x: latency_at_node_output[x.name], predecessors - ) + pred_latencies = map(lambda x: latency_at_node_output[x.name], predecessors) max_pred_latency = max(pred_latencies) latency_at_node_output[node.name] = node_cycles + max_pred_latency critical_path_cycles = max(latency_at_node_output.values()) diff --git a/src/finn/analysis/fpgadataflow/post_synth_res.py b/src/finn/analysis/fpgadataflow/post_synth_res.py index 1202120529..3304b88d60 100644 --- a/src/finn/analysis/fpgadataflow/post_synth_res.py +++ b/src/finn/analysis/fpgadataflow/post_synth_res.py @@ -86,7 +86,7 @@ def get_instance_stats(inst_name): if row != []: node_dict = {} row = list(row[0]) - for (restype, ind) in restype_to_ind.items(): + for restype, ind in restype_to_ind.items(): node_dict[restype] = int(row[ind].attrib["contents"]) return node_dict else: diff --git a/src/finn/analysis/fpgadataflow/res_estimation.py b/src/finn/analysis/fpgadataflow/res_estimation.py index 406496bc0e..be4cf417bc 100644 --- a/src/finn/analysis/fpgadataflow/res_estimation.py +++ b/src/finn/analysis/fpgadataflow/res_estimation.py @@ -62,10 +62,7 @@ def res_estimation_complete(model): if is_fpgadataflow_node(node) is True: op_type = node.op_type inst = registry.getCustomOp(node) - if ( - op_type == "MatrixVectorActivation" - or op_type == "VectorVectorActivation" - ): + if op_type == "MatrixVectorActivation" or op_type == "VectorVectorActivation": orig_restype = inst.get_nodeattr("resType") res_dict[node.name] = [] inst.set_nodeattr("resType", "dsp") diff --git a/src/finn/builder/build_dataflow.py b/src/finn/builder/build_dataflow.py index d6864994a7..284cd2baa3 100644 --- a/src/finn/builder/build_dataflow.py +++ b/src/finn/builder/build_dataflow.py @@ -91,12 +91,8 @@ def resolve_build_steps(cfg: DataflowBuildConfig, partial: bool = True): return steps_as_fxns -def resolve_step_filename( - step_name: str, cfg: DataflowBuildConfig, step_delta: int = 0 -): - step_names = list( - map(lambda x: x.__name__, resolve_build_steps(cfg, partial=False)) - ) +def resolve_step_filename(step_name: str, cfg: DataflowBuildConfig, step_delta: int = 0): + step_names = list(map(lambda x: x.__name__, resolve_build_steps(cfg, partial=False))) assert step_name in step_names, "start_step %s not found" + step_name step_no = step_names.index(step_name) + step_delta assert step_no >= 0, "Invalid step+delta combination" @@ -150,19 +146,13 @@ def build_dataflow_cfg(model_filename, cfg: DataflowBuildConfig): for transform_step in build_dataflow_steps: try: step_name = transform_step.__name__ - print( - "Running step: %s [%d/%d]" - % (step_name, step_num, len(build_dataflow_steps)) - ) + print("Running step: %s [%d/%d]" % (step_name, step_num, len(build_dataflow_steps))) # redirect output to logfile if not cfg.verbose: sys.stdout = stdout_logger sys.stderr = stderr_logger # also log current step name to logfile - print( - "Running step: %s [%d/%d]" - % (step_name, step_num, len(build_dataflow_steps)) - ) + print("Running step: %s [%d/%d]" % (step_name, step_num, len(build_dataflow_steps))) # run the step step_start = time.time() model = transform_step(model, cfg) diff --git a/src/finn/builder/build_dataflow_config.py b/src/finn/builder/build_dataflow_config.py index 4c3e4ff899..e4fed05731 100644 --- a/src/finn/builder/build_dataflow_config.py +++ b/src/finn/builder/build_dataflow_config.py @@ -267,9 +267,7 @@ class DataflowBuildConfig: #: When `auto_fifo_depths = True`, select which method will be used for #: setting the FIFO sizes. - auto_fifo_strategy: Optional[ - AutoFIFOSizingMethod - ] = AutoFIFOSizingMethod.LARGEFIFO_RTLSIM + auto_fifo_strategy: Optional[AutoFIFOSizingMethod] = AutoFIFOSizingMethod.LARGEFIFO_RTLSIM #: Avoid using C++ rtlsim for auto FIFO sizing and rtlsim throughput test #: if set to True, always using Python instead @@ -366,9 +364,7 @@ def _resolve_driver_platform(self): elif self.shell_flow_type == ShellFlowType.VITIS_ALVEO: return "alveo" else: - raise Exception( - "Couldn't resolve driver platform for " + str(self.shell_flow_type) - ) + raise Exception("Couldn't resolve driver platform for " + str(self.shell_flow_type)) def _resolve_fpga_part(self): if self.fpga_part is None: @@ -410,8 +406,7 @@ def _resolve_vitis_platform(self): return alveo_default_platform[self.board] else: raise Exception( - "Could not resolve Vitis platform:" - " need either board or vitis_platform specified" + "Could not resolve Vitis platform:" " need either board or vitis_platform specified" ) def _resolve_verification_steps(self): @@ -429,8 +424,7 @@ def _resolve_verification_io_pair(self): ) verify_input_npy = np.load(self.verify_input_npy) assert os.path.isfile(self.verify_expected_output_npy), ( - "verify_expected_output_npy not found: " - + self.verify_expected_output_npy + "verify_expected_output_npy not found: " + self.verify_expected_output_npy ) verify_expected_output_npy = np.load(self.verify_expected_output_npy) return ( diff --git a/src/finn/builder/build_dataflow_steps.py b/src/finn/builder/build_dataflow_steps.py index a22b5adc98..54ba7e4ea1 100644 --- a/src/finn/builder/build_dataflow_steps.py +++ b/src/finn/builder/build_dataflow_steps.py @@ -145,9 +145,7 @@ def verify_step( in_npy = np.expand_dims(in_npy_all[b], axis=0) exp_out_npy = np.expand_dims(exp_out_npy_all[b], axis=0) if need_parent: - assert ( - cfg.save_intermediate_models - ), "Enable save_intermediate_models for verification" + assert cfg.save_intermediate_models, "Enable save_intermediate_models for verification" parent_model_fn = intermediate_models_dir + "/dataflow_parent.onnx" child_model_fn = intermediate_models_dir + "/verify_%s.onnx" % step_name model.save(child_model_fn) @@ -161,9 +159,7 @@ def verify_step( ) print("Attempting to force model shape on verification input") in_npy = in_npy.reshape(exp_ishape) - out_dict = execute_parent( - parent_model_fn, child_model_fn, in_npy, return_full_ctx=True - ) + out_dict = execute_parent(parent_model_fn, child_model_fn, in_npy, return_full_ctx=True) out_npy = out_dict[out_tensor_name] else: inp_tensor_name = model.graph.input[0].name @@ -230,9 +226,7 @@ def prepare_for_stitched_ip_rtlsim(verify_model, cfg): inst.set_nodeattr("ipgen_path", "") need_restitch = True # StreamingDataWidthConverter must have impl_style=hls - for dwc_layer in verify_model.get_nodes_by_op_type( - "StreamingDataWidthConverter_Batch" - ): + for dwc_layer in verify_model.get_nodes_by_op_type("StreamingDataWidthConverter_Batch"): inst = getCustomOp(dwc_layer) if inst.get_nodeattr("impl_style") != "hls": inst.set_nodeattr("impl_style", "hls") @@ -382,8 +376,7 @@ def step_create_dataflow_partition(model: ModelWrapper, cfg: DataflowBuildConfig parent_model = model.transform( CreateDataflowPartition( - partition_model_dir=cfg.output_dir - + "/intermediate_models/supported_op_partitions" + partition_model_dir=cfg.output_dir + "/intermediate_models/supported_op_partitions" ) ) sdp_nodes = parent_model.get_nodes_by_op_type("StreamingDataflowPartition") @@ -422,9 +415,7 @@ def step_target_fps_parallelization(model: ModelWrapper, cfg: DataflowBuildConfi "mem_mode", "runtime_writeable_weights", ] - extract_model_config_to_json( - model, cfg.output_dir + "/auto_folding_config.json", hw_attrs - ) + extract_model_config_to_json(model, cfg.output_dir + "/auto_folding_config.json", hw_attrs) return model @@ -459,9 +450,7 @@ def step_generate_estimate_reports(model: ModelWrapper, cfg: DataflowBuildConfig with open(report_dir + "/estimate_layer_cycles.json", "w") as f: json.dump(estimate_layer_cycles, f, indent=2) estimate_layer_resources = model.analysis(res_estimation) - estimate_layer_resources["total"] = aggregate_dict_keys( - estimate_layer_resources - ) + estimate_layer_resources["total"] = aggregate_dict_keys(estimate_layer_resources) with open(report_dir + "/estimate_layer_resources.json", "w") as f: json.dump(estimate_layer_resources, f, indent=2) estimate_layer_resources_complete = model.analysis(res_estimation_complete) @@ -475,8 +464,7 @@ def step_generate_estimate_reports(model: ModelWrapper, cfg: DataflowBuildConfig est_fps = n_clock_cycles_per_sec / estimate_network_performance["max_cycles"] estimate_network_performance["estimated_throughput_fps"] = est_fps est_latency_ns = ( - estimate_network_performance["critical_path_cycles"] - * cfg.synth_clk_period_ns + estimate_network_performance["critical_path_cycles"] * cfg.synth_clk_period_ns ) estimate_network_performance["estimated_latency_ns"] = est_latency_ns with open(report_dir + "/estimate_network_performance.json", "w") as f: @@ -497,9 +485,7 @@ def step_minimize_bit_width(model: ModelWrapper, cfg: DataflowBuildConfig): def step_hls_codegen(model: ModelWrapper, cfg: DataflowBuildConfig): "Generate Vivado HLS code to prepare HLSCustomOp nodes for IP generation." - model = model.transform( - PrepareIP(cfg._resolve_fpga_part(), cfg._resolve_hls_clk_period()) - ) + model = model.transform(PrepareIP(cfg._resolve_fpga_part(), cfg._resolve_hls_clk_period())) return model @@ -599,9 +585,7 @@ def step_set_fifo_depths(model: ModelWrapper, cfg: DataflowBuildConfig): "inFIFODepths", "outFIFODepths", ] - extract_model_config_to_json( - model, cfg.output_dir + "/final_hw_config.json", hw_attrs - ) + extract_model_config_to_json(model, cfg.output_dir + "/final_hw_config.json", hw_attrs) # perform FIFO splitting and shallow FIFO removal only after the final config # json file has been written. otherwise, since these transforms may add/remove @@ -612,9 +596,7 @@ def step_set_fifo_depths(model: ModelWrapper, cfg: DataflowBuildConfig): # after FIFOs are ready to go, call PrepareIP and HLSSynthIP again # this will only run for the new nodes (e.g. FIFOs and DWCs) - model = model.transform( - PrepareIP(cfg._resolve_fpga_part(), cfg._resolve_hls_clk_period()) - ) + model = model.transform(PrepareIP(cfg._resolve_fpga_part(), cfg._resolve_hls_clk_period())) model = model.transform(HLSSynthIP()) return model @@ -651,9 +633,7 @@ def step_create_stitched_ip(model: ModelWrapper, cfg: DataflowBuildConfig): if cfg.verify_save_rtlsim_waveforms: report_dir = cfg.output_dir + "/report" os.makedirs(report_dir, exist_ok=True) - verify_model.set_metadata_prop( - "rtlsim_trace", "%s/verify_rtlsim.vcd" % (report_dir) - ) + verify_model.set_metadata_prop("rtlsim_trace", "%s/verify_rtlsim.vcd" % (report_dir)) verify_step(verify_model, cfg, "stitched_ip_rtlsim", need_parent=True) os.environ["LIVENESS_THRESHOLD"] = str(prev_liveness) return model @@ -674,9 +654,7 @@ def step_measure_rtlsim_performance(model: ModelWrapper, cfg: DataflowBuildConfi rtlsim_model = deepcopy(model) rtlsim_model = prepare_for_stitched_ip_rtlsim(rtlsim_model, cfg) # multi-in/out streams currently not supported in our C++ verilator driver - model_multi_io = ( - len(rtlsim_model.graph.input) > 1 or len(rtlsim_model.graph.output) > 1 - ) + model_multi_io = len(rtlsim_model.graph.input) > 1 or len(rtlsim_model.graph.output) > 1 force_python_rtlsim = cfg.force_python_rtlsim or model_multi_io if model_multi_io: warnings.warn( @@ -694,9 +672,7 @@ def step_measure_rtlsim_performance(model: ModelWrapper, cfg: DataflowBuildConfi "rtlsim_trace", "%s/rtlsim_perf_batch_%d.vcd" % (report_dir, rtlsim_bs), ) - rtlsim_model.set_metadata_prop( - "extra_verilator_args", str(["-CFLAGS", "-O3"]) - ) + rtlsim_model.set_metadata_prop("extra_verilator_args", str(["-CFLAGS", "-O3"])) # run with single input to get latency rtlsim_latency_dict = throughput_test_rtlsim(rtlsim_model, 1) # run with batch to get stable-state throughput @@ -712,7 +688,7 @@ def step_measure_rtlsim_performance(model: ModelWrapper, cfg: DataflowBuildConfi rtlsim_perf_dict["runtime[ms]"] = runtime_s * 1000 rtlsim_perf_dict["throughput[images/s]"] = rtlsim_bs / runtime_s rtlsim_perf_dict["fclk[mhz]"] = fclk_mhz - for (key, val) in rtlsim_perf_dict.items(): + for key, val in rtlsim_perf_dict.items(): if "max_count" in key: del rtlsim_perf_dict[key] # estimate stable-state throughput based on latency+throughput @@ -754,13 +730,9 @@ def step_out_of_context_synthesis(model: ModelWrapper, cfg: DataflowBuildConfig) """Run out-of-context synthesis and generate reports. Depends on the DataflowOutputType.STITCHED_IP output product.""" if DataflowOutputType.OOC_SYNTH in cfg.generate_outputs: - assert ( - DataflowOutputType.STITCHED_IP in cfg.generate_outputs - ), "OOC needs stitched IP" + assert DataflowOutputType.STITCHED_IP in cfg.generate_outputs, "OOC needs stitched IP" model = model.transform( - SynthOutOfContext( - part=cfg._resolve_fpga_part(), clk_period_ns=cfg.synth_clk_period_ns - ) + SynthOutOfContext(part=cfg._resolve_fpga_part(), clk_period_ns=cfg.synth_clk_period_ns) ) report_dir = cfg.output_dir + "/report" os.makedirs(report_dir, exist_ok=True) diff --git a/src/finn/core/onnx_exec.py b/src/finn/core/onnx_exec.py index daecb59743..588e97e9e4 100644 --- a/src/finn/core/onnx_exec.py +++ b/src/finn/core/onnx_exec.py @@ -34,9 +34,7 @@ from finn.core.rtlsim_exec import rtlsim_exec -def execute_onnx( - model, input_dict, return_full_exec_context=False, start_node=None, end_node=None -): +def execute_onnx(model, input_dict, return_full_exec_context=False, start_node=None, end_node=None): """Executes given ONNX ModelWrapper with given named inputs. If return_full_exec_context is False, a dict of named outputs is returned as indicated by the model.graph.output. @@ -53,9 +51,7 @@ def execute_onnx( # if set to "rtlsim" execute model using pyverilator model_exec_mode = model.get_metadata_prop("exec_mode") if (model_exec_mode is None) or (model_exec_mode == ""): - return execute_onnx_base( - model, input_dict, return_full_exec_context, start_node, end_node - ) + return execute_onnx_base(model, input_dict, return_full_exec_context, start_node, end_node) if not model.check_all_tensor_shapes_specified(): raise Exception("Found unspecified tensor shapes, try infer_shapes") diff --git a/src/finn/custom_op/fpgadataflow/addstreams_batch.py b/src/finn/custom_op/fpgadataflow/addstreams_batch.py index 8fbdf9c452..51de1590ec 100644 --- a/src/finn/custom_op/fpgadataflow/addstreams_batch.py +++ b/src/finn/custom_op/fpgadataflow/addstreams_batch.py @@ -121,9 +121,7 @@ def verify_node(self): self.get_nodeattr("inputDataType") info_messages.append("All necessary attributes exist") except Exception: - info_messages.append( - """The required LabelSelect_Batch attributes do not exist.""" - ) + info_messages.append("""The required LabelSelect_Batch attributes do not exist.""") return info_messages @@ -184,9 +182,7 @@ def execute_node(self, context, graph): inp = context[node.input[0]] assert str(inp.dtype) == "float32", "Input datatype is not float32" - assert ( - inp.shape == exp_ishape - ), """Input0 shape doesn't match expected shape .""" + assert inp.shape == exp_ishape, """Input0 shape doesn't match expected shape .""" export_idt = self.get_input_datatype() # reshape input into folded form inp = inp.reshape(folded_ishape) @@ -197,9 +193,7 @@ def execute_node(self, context, graph): # exact same thing for input1 inp = context[node.input[1]] assert str(inp.dtype) == "float32", "Input datatype is not float32" - assert ( - inp.shape == exp_ishape - ), """Input1 shape doesn't match expected shape .""" + assert inp.shape == exp_ishape, """Input1 shape doesn't match expected shape .""" export_idt = self.get_input_datatype() # reshape input into folded form inp = inp.reshape(folded_ishape) @@ -377,9 +371,7 @@ def pragmas(self): self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() ) - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE ap_ctrl_none port=return" - ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") def get_verilog_top_module_intf_names(self): intf_names = super().get_verilog_top_module_intf_names() diff --git a/src/finn/custom_op/fpgadataflow/channelwise_op_batch.py b/src/finn/custom_op/fpgadataflow/channelwise_op_batch.py index 71fc37b184..5e0063ac33 100644 --- a/src/finn/custom_op/fpgadataflow/channelwise_op_batch.py +++ b/src/finn/custom_op/fpgadataflow/channelwise_op_batch.py @@ -178,9 +178,7 @@ def verify_node(self): self.get_nodeattr("outputDataType") info_messages.append("All necessary attributes exist") except Exception: - info_messages.append( - """The required Threshold_Batch attributes do not exist.""" - ) + info_messages.append("""The required Threshold_Batch attributes do not exist.""") return info_messages @@ -300,9 +298,7 @@ def get_hls_compatible_parameter_tensor(self, orig_param_vector): assert (orig_param_vector.astype(np.int32) == orig_param_vector).all() ret = orig_param_vector - assert ( - ret.shape[0] == chn - ), "Cardinality of parameter vector is not as expected (chn)" + assert ret.shape[0] == chn, "Cardinality of parameter vector is not as expected (chn)" # distribute rows between PEs ret = ret.reshape(tmem, pe).transpose() @@ -324,9 +320,7 @@ def generate_params(self, model, path): parameter_tensor = self.get_hls_compatible_parameter_tensor(parameters) pdt = DataType[self.get_nodeattr("paramDataType")] - parameters_hls_code = numpy_to_hls_code( - parameter_tensor, pdt, "parameters", False, True - ) + parameters_hls_code = numpy_to_hls_code(parameter_tensor, pdt, "parameters", False, True) # get input data type export_idt = self.get_input_datatype() if self.get_input_datatype() == DataType["BIPOLAR"]: @@ -430,9 +424,7 @@ def execute_node(self, context, graph): elif mode == "rtlsim": sim = self.get_rtlsim() nbits = self.get_instream_width() - inp = npy_to_rtlsim_input( - "{}/input_0.npy".format(code_gen_dir), export_idt, nbits - ) + inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) super().reset_rtlsim(sim) super().toggle_clk(sim) output = self.rtlsim(sim, inp) @@ -441,9 +433,7 @@ def execute_node(self, context, graph): packed_bits = self.get_outstream_width() out_npy_path = "{}/output.npy".format(code_gen_dir) out_shape = self.get_folded_output_shape() - rtlsim_output_to_npy( - output, out_npy_path, odt, out_shape, packed_bits, target_bits - ) + rtlsim_output_to_npy(output, out_npy_path, odt, out_shape, packed_bits, target_bits) # load and reshape output output = np.load(out_npy_path) @@ -584,18 +574,13 @@ def pragmas(self): self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() ) - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE ap_ctrl_none port=return" - ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") # the channelwise parameter tensor is acc_type [PE][TMEM][N_PARAMS_PER_CHANNEL] # partition for parallel access along PE and N_PARAMS_PER_CHANNEL # dimensions (dims 1 and 3) self.code_gen_dict["$PRAGMAS$"].append( - ( - "#pragma HLS ARRAY_PARTITION variable=threshs.parameters " - "complete dim=1" - ) + ("#pragma HLS ARRAY_PARTITION variable=threshs.parameters " "complete dim=1") ) # self.code_gen_dict["$PRAGMAS$"].append( # ( @@ -613,17 +598,11 @@ def pragmas(self): if pe < ich: if ram_style == "distributed": self.code_gen_dict["$PRAGMAS$"].append( - ( - "#pragma HLS RESOURCE variable=threshs.parameters " - "core=ROM_2P_LUTRAM" - ) + ("#pragma HLS RESOURCE variable=threshs.parameters " "core=ROM_2P_LUTRAM") ) elif ram_style == "block": self.code_gen_dict["$PRAGMAS$"].append( - ( - "#pragma HLS RESOURCE variable=threshs.parameters " - "core=ROM_2P_BRAM" - ) + ("#pragma HLS RESOURCE variable=threshs.parameters " "core=ROM_2P_BRAM") ) else: raise Exception( diff --git a/src/finn/custom_op/fpgadataflow/checksum.py b/src/finn/custom_op/fpgadataflow/checksum.py index c9d16c0011..6121c5d97a 100644 --- a/src/finn/custom_op/fpgadataflow/checksum.py +++ b/src/finn/custom_op/fpgadataflow/checksum.py @@ -183,9 +183,7 @@ def execute_node(self, context, graph): np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input) sim = self.get_rtlsim() nbits = self.get_instream_width() - inp = npy_to_rtlsim_input( - "{}/input_0.npy".format(code_gen_dir), export_idt, nbits - ) + inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) super().reset_rtlsim(sim) super().toggle_clk(sim) io_dict = { @@ -199,9 +197,7 @@ def execute_node(self, context, graph): packed_bits = self.get_outstream_width() out_npy_path = "{}/output.npy".format(code_gen_dir) out_shape = self.get_folded_output_shape() - rtlsim_output_to_npy( - output, out_npy_path, odt, out_shape, packed_bits, target_bits - ) + rtlsim_output_to_npy(output, out_npy_path, odt, out_shape, packed_bits, target_bits) # load and reshape output output = np.load(out_npy_path) @@ -303,8 +299,7 @@ def dataoutstrm(self): ), "std::vector checksum(1);", "checksum[0] = chk;", - 'cnpy::npy_save("%s/output_checksum.npy",&checksum[0],{1},"w");' - % code_gen_dir, + 'cnpy::npy_save("%s/output_checksum.npy",&checksum[0],{1},"w");' % code_gen_dir, ] def save_as_npy(self): @@ -331,13 +326,9 @@ def pragmas(self): self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS interface s_axilite port=drain bundle=checksum" ) - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS interface ap_ctrl_none port=return" - ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS interface ap_ctrl_none port=return") self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS dataflow") - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS dataflow disable_start_propagation" - ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS dataflow disable_start_propagation") def get_verilog_top_module_intf_names(self): intf_names = super().get_verilog_top_module_intf_names() diff --git a/src/finn/custom_op/fpgadataflow/concat.py b/src/finn/custom_op/fpgadataflow/concat.py index c43e88d59d..8c24dadbeb 100644 --- a/src/finn/custom_op/fpgadataflow/concat.py +++ b/src/finn/custom_op/fpgadataflow/concat.py @@ -134,7 +134,7 @@ def generate_params(self, model, path): idt = self.get_input_datatype() total_elems = self.get_total_elems() total_bw = idt.bitwidth() * total_elems - for (i, elems) in enumerate(elems_per_stream): + for i, elems in enumerate(elems_per_stream): bw = idt.bitwidth() * elems inp_stream = "hls::stream > &in%d" % (bw, i) inp_streams.append(inp_stream) @@ -298,8 +298,7 @@ def strm_decl(self): packed_hls_type = "ap_uint<%d>" % packed_bits stream_name = "in%d_%s" % (i, self.hls_sname()) self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream<%s> %s ("%s");' - % (packed_hls_type, stream_name, stream_name) + 'hls::stream<%s> %s ("%s");' % (packed_hls_type, stream_name, stream_name) ) self.code_gen_dict["$STREAMDECLARATIONS$"].append( 'hls::stream> out_{} ("out_{}");'.format( @@ -353,9 +352,7 @@ def blackboxfunction(self): in_streams = [] for i in range(n_inputs): iwidth = self.get_instream_width(i) - in_streams.append( - "hls::stream> &in%d_%s" % (iwidth, i, self.hls_sname()) - ) + in_streams.append("hls::stream> &in%d_%s" % (iwidth, i, self.hls_sname())) in_streams = ",".join(in_streams) total_width = self.get_input_datatype().bitwidth() * self.get_total_elems() out_stream = "hls::stream> &out_%s" % ( @@ -369,16 +366,12 @@ def pragmas(self): n_inputs = self.get_n_inputs() pragmas = [] for i in range(n_inputs): - pragmas.append( - "#pragma HLS INTERFACE axis port=in%d_%s" % (i, self.hls_sname()) - ) + pragmas.append("#pragma HLS INTERFACE axis port=in%d_%s" % (i, self.hls_sname())) self.code_gen_dict["$PRAGMAS$"] = pragmas self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() ) - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE ap_ctrl_none port=return" - ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") def get_instream_width_padded(self, ind=0): in_width = self.get_instream_width(ind) @@ -390,7 +383,5 @@ def get_verilog_top_module_intf_names(self): sname = self.hls_sname() intf_names["s_axis"] = [] for i in range(n_inputs): - intf_names["s_axis"].append( - ("in%d_%s" % (i, sname), self.get_instream_width_padded(i)) - ) + intf_names["s_axis"].append(("in%d_%s" % (i, sname), self.get_instream_width_padded(i))) return intf_names diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py index c80f79a8c9..33c542d79d 100644 --- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py +++ b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py @@ -202,9 +202,7 @@ def get_exp_cycles(self): cycles_write_block = (ofm_dim_w * k_w * k_h * (ifm_ch / simd)) / mmv cycles_read_block = stride_w * ifm_dim_w * (ifm_ch / simd) max_cycles = max(cycles_write_block, cycles_read_block) - exp_cycles = ( - ifm_dim_w * k_h * dilation_h * (ifm_ch / simd) + ofm_dim_h * max_cycles - ) + exp_cycles = ifm_dim_w * k_h * dilation_h * (ifm_ch / simd) + ofm_dim_h * max_cycles return int(exp_cycles) @@ -505,6 +503,4 @@ def pragmas(self): self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() ) - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE ap_ctrl_none port=return" - ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator1d.py b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator1d.py index 43e8df17b4..046e8e096d 100644 --- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator1d.py +++ b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator1d.py @@ -245,13 +245,7 @@ def use_parallel_window_output(self): no_dilation = dilation_h == 1 and dilation_w == 1 supported_ram_style = ram_style in ["auto", "distributed"] if self.get_nodeattr("parallel_window") == 1: - if ( - fully_unfolded - and non_dws - and no_stride - and no_dilation - and supported_ram_style - ): + if fully_unfolded and non_dws and no_stride and no_dilation and supported_ram_style: return True else: warnings.warn( @@ -289,10 +283,7 @@ def get_exp_cycles(self): "ConvolutionInputGenerator_1D_dws_stride", ]: exp_cycles = ( - 1 - + ofm_dim_w * k_w * ifm_ch / simd - + (ifm_ch / simd) * (k_w - 1) - - (k_w - 1) + 1 + ofm_dim_w * k_w * ifm_ch / simd + (ifm_ch / simd) * (k_w - 1) - (k_w - 1) ) elif swu_variant == "ConvolutionInputGenerator_1D_dws_naive": cycles_read_block = ifm_dim_w * ifm_ch / simd @@ -337,9 +328,7 @@ def bram_estimation(self): ram_width = 2 else: ram_width = 1 - width_mul = math.ceil( - simd * self.get_input_datatype().bitwidth() / ram_width - ) + width_mul = math.ceil(simd * self.get_input_datatype().bitwidth() / ram_width) depth_mul = math.ceil(ram_depth / 18432) return width_mul * depth_mul else: @@ -358,25 +347,17 @@ def lut_estimation(self): ram_style = self.get_nodeattr("ram_style") swu_variant = self.get_swu_variant() if swu_variant == "ConvolutionInputGenerator_1D_parallel": - ram_luts = math.ceil( - simd * self.get_input_datatype().bitwidth() * (k_w + 1) / 64 - ) + ram_luts = math.ceil(simd * self.get_input_datatype().bitwidth() * (k_w + 1) / 64) elif ram_style == "distributed": if swu_variant == "ConvolutionInputGenerator_1D": - ram_luts = math.ceil( - self.get_input_datatype().bitwidth() * (k_w - 1) * ifm_ch / 64 - ) + ram_luts = math.ceil(self.get_input_datatype().bitwidth() * (k_w - 1) * ifm_ch / 64) elif swu_variant == "ConvolutionInputGenerator_1D_dws_naive": - ram_luts = math.ceil( - self.get_input_datatype().bitwidth() * ifm_dim_w * ifm_ch / 64 - ) + ram_luts = math.ceil(self.get_input_datatype().bitwidth() * ifm_dim_w * ifm_ch / 64) elif swu_variant in [ "ConvolutionInputGenerator_1D_dws", "ConvolutionInputGenerator_1D_dws_stride", ]: - ram_luts = math.ceil( - self.get_input_datatype().bitwidth() * k_w * ifm_ch / 64 - ) + ram_luts = math.ceil(self.get_input_datatype().bitwidth() * k_w * ifm_ch / 64) else: ram_luts = 0 return 300 + ram_luts @@ -741,6 +722,4 @@ def pragmas(self): self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() ) - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE ap_ctrl_none port=return" - ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py index c54c4ac1c9..a55cdcc0be 100755 --- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py +++ b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py @@ -239,9 +239,7 @@ def get_buffer_depth(self): channel_factor = int(ifm_ch / simd) # compute minimal buffer length (assuming it holds 1 complete window) - buffer_min_size = ( - (k_h - 1) * dilation_h * w + (k_w - 1) * dilation_w + 1 - ) * channel_factor + buffer_min_size = ((k_h - 1) * dilation_h * w + (k_w - 1) * dilation_w + 1) * channel_factor impl_style = self.select_impl_style() if impl_style == "default": @@ -251,13 +249,11 @@ def get_buffer_depth(self): buffer_min_size + max( 0, - ((stride_w - 1) - (int(mmv_out * k_h * k_w / mmv_in))) - * channel_factor, + ((stride_w - 1) - (int(mmv_out * k_h * k_w / mmv_in))) * channel_factor, ) + max( 0, - ((stride_h - 1) * w - (int(mmv_out * k_h * k_w / mmv_in))) - * channel_factor, + ((stride_h - 1) * w - (int(mmv_out * k_h * k_w / mmv_in))) * channel_factor, ) ) elif impl_style == "parallel": @@ -377,9 +373,7 @@ def bram_estimation(self): remainder_cascade_width = math.ceil(buffer_width / remainder_width) cascade_savings = ram_cascade_width - remainder_cascade_width - return int( - (ram_cascade_depth * ram_cascade_width - cascade_savings) * buffer_count - ) + return int((ram_cascade_depth * ram_cascade_width - cascade_savings) * buffer_count) else: return 0 @@ -430,9 +424,7 @@ def execute_node(self, context, graph): folded_ishape = self.get_folded_input_shape() if mode == "cppsim": - raise Exception( - "cppsim not possible for RTL SWG, please set exec_mode to rtlsim" - ) + raise Exception("cppsim not possible for RTL SWG, please set exec_mode to rtlsim") elif mode == "rtlsim": code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") else: @@ -463,9 +455,7 @@ def execute_node(self, context, graph): sim = self.get_rtlsim() nbits = self.get_instream_width() - rtlsim_inp = npy_to_rtlsim_input( - "{}/input_0.npy".format(code_gen_dir), export_idt, nbits - ) + rtlsim_inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) super().reset_rtlsim(sim) super().toggle_clk(sim) rtlsim_output = self.rtlsim(sim, rtlsim_inp) @@ -474,9 +464,7 @@ def execute_node(self, context, graph): packed_bits = self.get_outstream_width() out_npy_path = "{}/output.npy".format(code_gen_dir) out_shape = self.get_folded_output_shape() - rtlsim_output_to_npy( - rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits - ) + rtlsim_output_to_npy(rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits) # load and reshape output output = np.load(out_npy_path) output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) @@ -524,9 +512,7 @@ def prepare_codegen_default(self): channel_factor = int(ifm_ch / simd) # compute minimal buffer length (assuming it holds 1 complete window) - buffer_min_size = ( - (k_h - 1) * dilation_h * w + (k_w - 1) * dilation_w + 1 - ) * channel_factor + buffer_min_size = ((k_h - 1) * dilation_h * w + (k_w - 1) * dilation_w + 1) * channel_factor buffer_actual_size = self.get_buffer_depth() code_gen_dict["$BUF_ELEM_TOTAL$"] = [str(buffer_actual_size)] @@ -680,9 +666,7 @@ def prepare_codegen_parallel(self): the loop controller configuration and partitioning the fixed buffer into shift-registers (for parallel read access) and line buffers (for efficient LUTRAM/BRAM/URAM implementation).""" - template_path = ( - os.environ["FINN_ROOT"] + "/finn-rtllib/swg/swg_template_parallel.sv" - ) + template_path = os.environ["FINN_ROOT"] + "/finn-rtllib/swg/swg_template_parallel.sv" code_gen_dict = {} ifm_ch = self.get_nodeattr("IFMChannels") @@ -707,9 +691,7 @@ def prepare_codegen_parallel(self): channel_factor = int(ifm_ch / simd) # compute minimal buffer length (assuming it holds 1 complete window) - buffer_min_size = ( - (k_h - 1) * dilation_h * w + (k_w - 1) * dilation_w + 1 - ) * channel_factor + buffer_min_size = ((k_h - 1) * dilation_h * w + (k_w - 1) * dilation_w + 1) * channel_factor buffer_actual_size = self.get_buffer_depth() code_gen_dict["$BUF_ELEM_TOTAL$"] = [str(buffer_actual_size)] @@ -902,9 +884,7 @@ def prepare_codegen_parallel(self): OUT_ELEM_WIDTH*{mmv_idx}+:OUT_ELEM_WIDTH];""".format( out_idx=out_idx, fifo_id=fifo_id, - access_idx=len(reg_fifo) - - 1 - - int((max(reg_fifo) - access_idx) / M), + access_idx=len(reg_fifo) - 1 - int((max(reg_fifo) - access_idx) / M), mmv_idx=(max(reg_fifo) - access_idx) % M, mmv=M, ) @@ -970,22 +950,16 @@ def select_impl_style(self): if self.get_nodeattr("parallel_window"): # mmv_in = M * 1 mmv_out = M * k_h * k_w - assert ( - ifm_ch == simd - ), "Constraint violated: SIMD must be equal to IFMChannels" + assert ifm_ch == simd, "Constraint violated: SIMD must be equal to IFMChannels" else: # mmv_in = 1 mmv_out = 1 - assert ( - ifm_ch % simd == 0 - ), "Constraint violated: SIMD must divide IFMChannels" + assert ifm_ch % simd == 0, "Constraint violated: SIMD must divide IFMChannels" # choose implementation style if mmv_out > 1 or (k_h == 1 and k_w == 1): impl_style = "parallel" - assert ( - ifm_ch == simd - ), "Constraint violated: SIMD must be equal to IFMChannels" + assert ifm_ch == simd, "Constraint violated: SIMD must be equal to IFMChannels" else: impl_style = "default" @@ -1025,9 +999,7 @@ def generate_hdl(self): template_select = "/finn-rtllib/swg/swg_template_wrapper.v" with open(os.environ["FINN_ROOT"] + template_select, "r") as f: template_wrapper = f.read() - with open( - os.environ["FINN_ROOT"] + "/finn-rtllib/swg/swg_template_axilite.v", "r" - ) as f: + with open(os.environ["FINN_ROOT"] + "/finn-rtllib/swg/swg_template_axilite.v", "r") as f: template_axilite = f.read() for key in code_gen_dict: # transform list into long string separated by '\n' @@ -1036,16 +1008,12 @@ def generate_hdl(self): template_wrapper = template_wrapper.replace(key, code_gen_line) template_axilite = template_axilite.replace(key, code_gen_line) with open( - os.path.join( - code_gen_dir, self.get_nodeattr("gen_top_module") + "_impl.sv" - ), + os.path.join(code_gen_dir, self.get_nodeattr("gen_top_module") + "_impl.sv"), "w", ) as f: f.write(template) with open( - os.path.join( - code_gen_dir, self.get_nodeattr("gen_top_module") + "_wrapper.v" - ), + os.path.join(code_gen_dir, self.get_nodeattr("gen_top_module") + "_wrapper.v"), "w", ) as f: f.write(template_wrapper) @@ -1053,20 +1021,14 @@ def generate_hdl(self): # AXI-Lite reg. file component is only needed for dynamic mode if self.get_nodeattr("dynamic_mode"): with open( - os.path.join( - code_gen_dir, self.get_nodeattr("gen_top_module") + "_axilite.v" - ), + os.path.join(code_gen_dir, self.get_nodeattr("gen_top_module") + "_axilite.v"), "w", ) as f: f.write(template_axilite) # Copy static source file for common core components - shutil.copy2( - os.environ["FINN_ROOT"] + "/finn-rtllib/swg/swg_common.sv", code_gen_dir - ) - shutil.copy2( - os.environ["FINN_ROOT"] + "/finn-rtllib/swg/swg_pkg.sv", code_gen_dir - ) + shutil.copy2(os.environ["FINN_ROOT"] + "/finn-rtllib/swg/swg_common.sv", code_gen_dir) + shutil.copy2(os.environ["FINN_ROOT"] + "/finn-rtllib/swg/swg_pkg.sv", code_gen_dir) # set ipgen_path and ip_path so that HLS-Synth transformation # and stich_ip transformation do not complain diff --git a/src/finn/custom_op/fpgadataflow/downsampler.py b/src/finn/custom_op/fpgadataflow/downsampler.py index d42a076c30..e2cea6da6b 100644 --- a/src/finn/custom_op/fpgadataflow/downsampler.py +++ b/src/finn/custom_op/fpgadataflow/downsampler.py @@ -296,9 +296,7 @@ def pragmas(self): self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() ) - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE ap_ctrl_none port=return" - ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") def execute_node(self, context, graph): mode = self.get_nodeattr("exec_mode") diff --git a/src/finn/custom_op/fpgadataflow/duplicatestreams_batch.py b/src/finn/custom_op/fpgadataflow/duplicatestreams_batch.py index 0d5d806dc5..1f2d1b79be 100644 --- a/src/finn/custom_op/fpgadataflow/duplicatestreams_batch.py +++ b/src/finn/custom_op/fpgadataflow/duplicatestreams_batch.py @@ -132,9 +132,7 @@ def verify_node(self): self.get_nodeattr("inputDataType") info_messages.append("All necessary attributes exist") except Exception: - info_messages.append( - """The required GlobalAccPool_Batch attributes do not exist.""" - ) + info_messages.append("""The required GlobalAccPool_Batch attributes do not exist.""") return info_messages @@ -161,9 +159,7 @@ def get_outstream_width(self, ind=0): return out_width def get_number_output_values(self): - return self.get_num_output_streams() * np.prod( - self.get_folded_output_shape()[1:-1] - ) + return self.get_num_output_streams() * np.prod(self.get_folded_output_shape()[1:-1]) def get_exp_cycles(self): # Channels/PE * batch size * fmdim * fmdim @@ -235,9 +231,7 @@ def execute_node(self, context, graph): # execute the precompiled model super().exec_precompiled_singlenode_model() # load output npy file - super().npy_to_dynamic_outputs( - context, ["output%d.npy" % i for i in range(n_outputs)] - ) + super().npy_to_dynamic_outputs(context, ["output%d.npy" % i for i in range(n_outputs)]) for i in range(n_outputs): assert ( context[node.output[i]].shape == exp_oshape @@ -411,9 +405,7 @@ def pragmas(self): self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE axis port=out%d_%s" % (i, self.hls_sname()) ) - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE ap_ctrl_none port=return" - ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") def get_verilog_top_module_intf_names(self): intf_names = super().get_verilog_top_module_intf_names() diff --git a/src/finn/custom_op/fpgadataflow/eltwise.py b/src/finn/custom_op/fpgadataflow/eltwise.py index 348e314792..ab1dc00118 100644 --- a/src/finn/custom_op/fpgadataflow/eltwise.py +++ b/src/finn/custom_op/fpgadataflow/eltwise.py @@ -42,7 +42,6 @@ def __init__(self, onnx_node, **kwargs): super().__init__(onnx_node, **kwargs) def get_nodeattr_types(self): - my_attrs = super().get_nodeattr_types() my_attrs.update( { @@ -154,9 +153,7 @@ def verify_node(self): self.get_nodeattr("eltwiseOp") info_messages.append("All necessary attributes exist") except Exception: - info_messages.append( - """The required StreamingEltwise attributes do not exist.""" - ) + info_messages.append("""The required StreamingEltwise attributes do not exist.""") return info_messages @@ -235,9 +232,7 @@ def execute_node(self, context, graph): inp = context[node.input[0]] assert str(inp.dtype) == "float32", "Input datatype is not float32" - assert ( - inp.shape == exp_ishape - ), """Input0 shape doesn't match expected shape .""" + assert inp.shape == exp_ishape, """Input0 shape doesn't match expected shape .""" export_idt0 = self.get_input_datatype(0) # reshape input into folded form inp = inp.reshape(folded_ishape) @@ -248,9 +243,7 @@ def execute_node(self, context, graph): # exact same thing for input1 inp = context[node.input[1]] assert str(inp.dtype) == "float32", "Input datatype is not float32" - assert ( - inp.shape == exp_ishape - ), """Input1 shape doesn't match expected shape .""" + assert inp.shape == exp_ishape, """Input1 shape doesn't match expected shape .""" export_idt1 = self.get_input_datatype(1) # reshape input into folded form inp = inp.reshape(folded_ishape) @@ -481,9 +474,7 @@ def pragmas(self): self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() ) - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE ap_ctrl_none port=return" - ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") def get_verilog_top_module_intf_names(self): intf_names = super().get_verilog_top_module_intf_names() diff --git a/src/finn/custom_op/fpgadataflow/fmpadding_batch.py b/src/finn/custom_op/fpgadataflow/fmpadding_batch.py index ea9028d925..5bd5e07916 100644 --- a/src/finn/custom_op/fpgadataflow/fmpadding_batch.py +++ b/src/finn/custom_op/fpgadataflow/fmpadding_batch.py @@ -333,9 +333,7 @@ def pragmas(self): self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() ) - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE ap_ctrl_none port=return" - ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") def execute_node(self, context, graph): mode = self.get_nodeattr("exec_mode") diff --git a/src/finn/custom_op/fpgadataflow/fmpadding_rtl.py b/src/finn/custom_op/fpgadataflow/fmpadding_rtl.py index 9c27503224..d79c214730 100644 --- a/src/finn/custom_op/fpgadataflow/fmpadding_rtl.py +++ b/src/finn/custom_op/fpgadataflow/fmpadding_rtl.py @@ -192,9 +192,7 @@ def execute_node(self, context, graph): folded_ishape = self.get_folded_input_shape() if mode == "cppsim": - raise Exception( - "cppsim not possible for FMPadding_rtl, please set exec_mode to rtlsim" - ) + raise Exception("cppsim not possible for FMPadding_rtl, please set exec_mode to rtlsim") elif mode == "rtlsim": code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") else: @@ -218,9 +216,7 @@ def execute_node(self, context, graph): sim = self.get_rtlsim() nbits = self.get_instream_width() - rtlsim_inp = npy_to_rtlsim_input( - "{}/input_0.npy".format(code_gen_dir), export_idt, nbits - ) + rtlsim_inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) super().reset_rtlsim(sim) super().toggle_clk(sim) rtlsim_output = self.rtlsim(sim, rtlsim_inp) @@ -229,9 +225,7 @@ def execute_node(self, context, graph): packed_bits = self.get_outstream_width() out_npy_path = "{}/output.npy".format(code_gen_dir) out_shape = self.get_folded_output_shape() - rtlsim_output_to_npy( - rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits - ) + rtlsim_output_to_npy(rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits) # load and reshape output output = np.load(out_npy_path) output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) diff --git a/src/finn/custom_op/fpgadataflow/globalaccpool_batch.py b/src/finn/custom_op/fpgadataflow/globalaccpool_batch.py index e518507034..5ed440dace 100644 --- a/src/finn/custom_op/fpgadataflow/globalaccpool_batch.py +++ b/src/finn/custom_op/fpgadataflow/globalaccpool_batch.py @@ -128,9 +128,7 @@ def verify_node(self): self.get_nodeattr("inputDataType") info_messages.append("All necessary attributes exist") except Exception: - info_messages.append( - """The required GlobalAccPool_Batch attributes do not exist.""" - ) + info_messages.append("""The required GlobalAccPool_Batch attributes do not exist.""") # verify that input data is 2D if len(self.get_nodeattr("numInputVectors")) != 3: @@ -351,6 +349,4 @@ def pragmas(self): self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() ) - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE ap_ctrl_none port=return" - ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") diff --git a/src/finn/custom_op/fpgadataflow/hlscustomop.py b/src/finn/custom_op/fpgadataflow/hlscustomop.py index d5d0c9ea6e..4fed8ed4b5 100644 --- a/src/finn/custom_op/fpgadataflow/hlscustomop.py +++ b/src/finn/custom_op/fpgadataflow/hlscustomop.py @@ -169,9 +169,7 @@ def get_all_verilog_paths(self): code_gen_dir != "" ), """Node attribute "code_gen_dir_ipgen" is not set. Please run HLSSynthIP first.""" - verilog_path = "{}/project_{}/sol1/impl/verilog/".format( - code_gen_dir, self.onnx_node.name - ) + verilog_path = "{}/project_{}/sol1/impl/verilog/".format(code_gen_dir, self.onnx_node.name) # default impl only returns the HLS verilog codegen dir return [verilog_path] @@ -355,9 +353,10 @@ def ipgen_singlenode_code(self): assert os.path.isdir(ipgen_path), "IPGen failed: %s not found" % (ipgen_path) self.set_nodeattr("ipgen_path", ipgen_path) ip_path = ipgen_path + "/sol1/impl/ip" - assert os.path.isdir( - ip_path - ), "IPGen failed: %s not found. Check log under %s" % (ip_path, code_gen_dir) + assert os.path.isdir(ip_path), "IPGen failed: %s not found. Check log under %s" % ( + ip_path, + code_gen_dir, + ) self.set_nodeattr("ip_path", ip_path) vlnv = "xilinx.com:hls:%s:1.0" % node.name self.set_nodeattr("ip_vlnv", vlnv) @@ -756,22 +755,15 @@ def get_ap_int_max_w(self): instream = self.get_instream_width() outstream = self.get_outstream_width() ret = max([instream, outstream]) - assert ret <= 32768, ( - "AP_INT_MAX_W=%d is larger than allowed maximum of 32768" % ret - ) + assert ret <= 32768, "AP_INT_MAX_W=%d is larger than allowed maximum of 32768" % ret return ret def derive_characteristic_fxns(self, period, override_rtlsim_dict=None): """Return the unconstrained characteristic functions for this node.""" # ensure rtlsim is ready - assert self.get_nodeattr("rtlsim_so") != "", ( - "rtlsim not ready for " + self.onnx_node.name - ) + assert self.get_nodeattr("rtlsim_so") != "", "rtlsim not ready for " + self.onnx_node.name if self.get_nodeattr("io_chrc_period") > 0: - warnings.warn( - "Skipping node %s: already has FIFO characteristic" - % self.onnx_node.name - ) + warnings.warn("Skipping node %s: already has FIFO characteristic" % self.onnx_node.name) return exp_cycles = self.get_exp_cycles() n_inps = np.prod(self.get_folded_input_shape()[:-1]) @@ -802,9 +794,7 @@ def derive_characteristic_fxns(self, period, override_rtlsim_dict=None): # extra dicts to keep track of cycle-by-cycle transaction behavior # note that we restrict key names to filter out weight streams etc txns_in = {key: [] for (key, value) in io_dict["inputs"].items() if "in" in key} - txns_out = { - key: [] for (key, value) in io_dict["outputs"].items() if "out" in key - } + txns_out = {key: [] for (key, value) in io_dict["outputs"].items() if "out" in key} def monitor_txns(sim_obj): for inp in txns_in: diff --git a/src/finn/custom_op/fpgadataflow/iodma.py b/src/finn/custom_op/fpgadataflow/iodma.py index 4b4ad28def..bb3de268a0 100644 --- a/src/finn/custom_op/fpgadataflow/iodma.py +++ b/src/finn/custom_op/fpgadataflow/iodma.py @@ -116,9 +116,7 @@ def get_folded_input_shape(self, ind=0): shape = list(self.get_normal_input_shape()) itype_bits = self.get_input_datatype().bitwidth() intfw = self.get_nodeattr("streamWidth") - assert ( - intfw % itype_bits == 0 - ), "Input stream width must be a multiple of datatype bits" + assert intfw % itype_bits == 0, "Input stream width must be a multiple of datatype bits" elems_per_word = intfw // itype_bits assert shape[-1] % elems_per_word == 0, "Fold depth must be integer" fold_depth = shape[-1] // elems_per_word @@ -133,9 +131,7 @@ def get_folded_output_shape(self, ind=0): shape = list(self.get_normal_output_shape()) itype_bits = self.get_output_datatype().bitwidth() intfw = self.get_nodeattr("streamWidth") - assert ( - intfw % itype_bits == 0 - ), "Input stream width must be a multiple of datatype bits" + assert intfw % itype_bits == 0, "Input stream width must be a multiple of datatype bits" elems_per_word = intfw // itype_bits assert shape[-1] % elems_per_word == 0, "Fold depth must be integer" fold_depth = shape[-1] // elems_per_word @@ -196,9 +192,7 @@ def get_number_output_values(self): stream_width = self.get_nodeattr("streamWidth") nelems = np.prod(oshape) nbits = nelems * itype_bits - assert ( - nbits % stream_width == 0 - ), "DMA: total transfer size must be word multiple" + assert nbits % stream_width == 0, "DMA: total transfer size must be word multiple" ovalues = nbits // stream_width return ovalues @@ -255,8 +249,7 @@ def docompute(self): if strmw == intfw: # case 0: AXI MM width = out width, no DWCs needed self.code_gen_dict["$DOCOMPUTE$"] = [ - dma_inst_template - % ("in0_" + self.hls_sname(), "out_" + self.hls_sname()) + dma_inst_template % ("in0_" + self.hls_sname(), "out_" + self.hls_sname()) ] elif (strmw % intfw == 0) or (intfw % strmw == 0): # case 1: AXI MM width divisible by out width or vice versa @@ -298,8 +291,7 @@ def docompute(self): if strmw == intfw: # case 0: in width = AXI MM width, no DWCs needed self.code_gen_dict["$DOCOMPUTE$"] = [ - dma_inst_template - % ("in0_" + self.hls_sname(), "out_" + self.hls_sname()) + dma_inst_template % ("in0_" + self.hls_sname(), "out_" + self.hls_sname()) ] elif (strmw % intfw == 0) or (intfw % strmw == 0): # case 1: AXI MM width divisible by in width or vice versa @@ -381,16 +373,14 @@ def pragmas(self): if direction == "in": if intfname == "": self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE m_axi offset=slave port=in0_" - + self.hls_sname() + "#pragma HLS INTERFACE m_axi offset=slave port=in0_" + self.hls_sname() ) else: self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE m_axi offset=slave port=%s" % (intfname) ) self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE s_axilite port=in0_%s bundle=control" - % (self.hls_sname()) + "#pragma HLS INTERFACE s_axilite port=in0_%s bundle=control" % (self.hls_sname()) ) self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() @@ -401,16 +391,14 @@ def pragmas(self): ) if intfname == "": self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE m_axi offset=slave port=out_" - + self.hls_sname() + "#pragma HLS INTERFACE m_axi offset=slave port=out_" + self.hls_sname() ) else: self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE m_axi offset=slave port=%s" % (intfname) ) self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE s_axilite port=out_%s bundle=control" - % (self.hls_sname()) + "#pragma HLS INTERFACE s_axilite port=out_%s bundle=control" % (self.hls_sname()) ) else: raise ValueError("Invalid IODMA direction, please set to in or out") diff --git a/src/finn/custom_op/fpgadataflow/labelselect_batch.py b/src/finn/custom_op/fpgadataflow/labelselect_batch.py index 12a88dacd4..60d3eb9154 100644 --- a/src/finn/custom_op/fpgadataflow/labelselect_batch.py +++ b/src/finn/custom_op/fpgadataflow/labelselect_batch.py @@ -141,9 +141,7 @@ def verify_node(self): self.get_nodeattr("outputDataType") info_messages.append("All necessary attributes exist") except Exception: - info_messages.append( - """The required LabelSelect_Batch attributes do not exist.""" - ) + info_messages.append("""The required LabelSelect_Batch attributes do not exist.""") # verify that input data is 1D if len(self.get_nodeattr("numInputVectors")) > 1: @@ -362,9 +360,7 @@ def pragmas(self): self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() ) - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE ap_ctrl_none port=return" - ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") def get_exp_cycles(self): nlabels = self.get_nodeattr("Labels") diff --git a/src/finn/custom_op/fpgadataflow/lookup.py b/src/finn/custom_op/fpgadataflow/lookup.py index ecf630ef7f..2dfca90ed9 100644 --- a/src/finn/custom_op/fpgadataflow/lookup.py +++ b/src/finn/custom_op/fpgadataflow/lookup.py @@ -184,9 +184,7 @@ def defines(self, var): my_defines.append("#define T_SRC %s" % elem_hls_type) my_defines.append("#define T_DST ap_uint") elif mem_mode == "const": - my_defines.append( - "#define NumEmbeddings %d" % self.get_nodeattr("NumEmbeddings") - ) + my_defines.append("#define NumEmbeddings %d" % self.get_nodeattr("NumEmbeddings")) my_defines.append("#define EmbeddingDim %d" % emb_dim) my_defines.append("#define InputType %s" % elem_hls_type) my_defines.append("#define EmbeddingType %s" % emb_hls_type) @@ -310,18 +308,12 @@ def pragmas(self): my_pragmas.append("#pragma HLS INTERFACE axis port=out_" + self.hls_sname()) my_pragmas.append("#pragma HLS INTERFACE ap_ctrl_none port=return") if mem_mode == "const": - my_pragmas.append( - "#pragma HLS BIND_STORAGE variable=embeddings type=ROM_2P impl=BRAM" - ) + my_pragmas.append("#pragma HLS BIND_STORAGE variable=embeddings type=ROM_2P impl=BRAM") elif mem_mode == "external": my_pragmas.append("#pragma HLS INTERFACE m_axi offset=slave port=mem") my_pragmas.append("#pragma HLS INTERFACE s_axilite port=mem bundle=control") - my_pragmas.append( - "#pragma HLS INTERFACE s_axilite port=size bundle=control" - ) - my_pragmas.append( - "#pragma HLS INTERFACE s_axilite port=oob_count bundle=control" - ) + my_pragmas.append("#pragma HLS INTERFACE s_axilite port=size bundle=control") + my_pragmas.append("#pragma HLS INTERFACE s_axilite port=oob_count bundle=control") my_pragmas.append("#pragma HLS INTERFACE ap_none port=oob_irq") else: raise Exception("Unrecognized mem_mode: " + mem_mode) @@ -342,9 +334,7 @@ def generate_params(self, model, path): # reverse innertmost dim in embeddings to remain compatible with # how we normally encode the data in FINN embeddings_rev = np.flip(embeddings, -1) - embeddings_hls_code = numpy_to_hls_code( - embeddings_rev, edt, "embeddings", True, False - ) + embeddings_hls_code = numpy_to_hls_code(embeddings_rev, edt, "embeddings", True, False) f_thresh = open(weight_filename, "w") f_thresh.write(embeddings_hls_code) f_thresh.close() @@ -366,9 +356,7 @@ def generate_params(self, model, path): pad_amount = align_factor - emb_dim embeddings_padded = np.pad(embeddings, [(0, 0), (0, pad_amount)]) # reshape for packing the innermost dim - embeddings_padded = embeddings_padded.reshape( - -1, emb_elems_per_ext_mem_width - ) + embeddings_padded = embeddings_padded.reshape(-1, emb_elems_per_ext_mem_width) weight_filename = "%s/%s.dat" % (path, self.onnx_node.name) ret = pack_innermost_dim_as_hex_string( embeddings_padded, edt, ext_mem_width, True, prefix="" diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index fae2d86d88..204a41e21c 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -189,9 +189,7 @@ def verify_node(self): self.get_nodeattr("outputDataType") info_messages.append("All necessary attributes exist") except Exception: - info_messages.append( - """The required MatrixVectorActivation attributes do not exist.""" - ) + info_messages.append("""The required MatrixVectorActivation attributes do not exist.""") # verify the number of inputs depending on noActivation value # check noActivation value to determine the number of inputs @@ -370,9 +368,7 @@ def lut_estimation(self): comp_luts = (2**B - 1) * acc_bits return int( - c0 - + c1 * (P * (mult_luts + addertree_luts + acc_luts + thr_luts + comp_luts)) - + c2 + c0 + c1 * (P * (mult_luts + addertree_luts + acc_luts + thr_luts + comp_luts)) + c2 ) def dsp_estimation(self): @@ -720,9 +716,7 @@ def get_hls_compatible_threshold_tensor(self, orig_thres_matrix): # ensure channels = mh , duplicating if necessary if ret.shape[0] == 1: ret = np.tile(ret, (mh, 1)) - assert ( - ret.shape[0] == mh - ), "Channels of threshold matrix are not as expected (mh)" + assert ret.shape[0] == mh, "Channels of threshold matrix are not as expected (mh)" # distribute rows between PEs ret = interleave_matrix_outer_dim_from_partitions(ret, pe) assert ( @@ -760,9 +754,7 @@ def make_weight_file(self, weights, weight_file_mode, weight_file_name): if self.get_weight_datatype() == DataType["BIPOLAR"]: export_wdt = DataType["BINARY"] if weight_file_mode == "hls_header": - weight_hls_code = numpy_to_hls_code( - weight_tensor, export_wdt, "weights", True, True - ) + weight_hls_code = numpy_to_hls_code(weight_tensor, export_wdt, "weights", True, True) # write weights into C++ header file as dictated by finn-hlslib f_weights = open(weight_file_name, "w") if export_wdt.bitwidth() != 1: @@ -796,14 +788,10 @@ def make_weight_file(self, weights, weight_file_mode, weight_file_name): pe = self.get_nodeattr("PE") simd = self.get_nodeattr("SIMD") # simd_flipped - weight_tensor_simd_flipped = weight_tensor_simd_flipped.reshape( - 1, -1, pe * simd - ) + weight_tensor_simd_flipped = weight_tensor_simd_flipped.reshape(1, -1, pe * simd) weight_tensor_simd_flipped = weight_tensor_simd_flipped.copy() # flipped - weight_tensor_pe_flipped = weight_tensor_pe_flipped.reshape( - 1, -1, pe * simd - ) + weight_tensor_pe_flipped = weight_tensor_pe_flipped.reshape(1, -1, pe * simd) weight_tensor_pe_flipped = weight_tensor_pe_flipped.copy() if weight_file_mode == "decoupled_npy": # save weight stream into npy for cppsim @@ -866,9 +854,7 @@ def generate_params(self, model, path): # also save weights as Verilog .dat file # This file will be ignored when synthesizing UltraScale memory. weight_filename_rtl = "{}/memblock.dat".format(code_gen_dir) - self.make_weight_file( - weights, "decoupled_verilog_dat", weight_filename_rtl - ) + self.make_weight_file(weights, "decoupled_verilog_dat", weight_filename_rtl) else: raise Exception( """Please set mem_mode to "const", "decoupled", or "external", @@ -987,9 +973,7 @@ def execute_node(self, context, graph): elif mode == "rtlsim": sim = self.get_rtlsim() nbits = self.get_instream_width() - inp = npy_to_rtlsim_input( - "{}/input_0.npy".format(code_gen_dir), export_idt, nbits - ) + inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) super().reset_rtlsim(sim) super().toggle_clk(sim) if mem_mode == "external" or mem_mode == "decoupled": @@ -999,9 +983,7 @@ def execute_node(self, context, graph): # so use it as such for weight generation if self.get_weight_datatype() == DataType["BIPOLAR"]: export_wdt = DataType["BINARY"] - wei = npy_to_rtlsim_input( - "{}/weights.npy".format(code_gen_dir), export_wdt, wnbits - ) + wei = npy_to_rtlsim_input("{}/weights.npy".format(code_gen_dir), export_wdt, wnbits) num_w_reps = np.prod(self.get_nodeattr("numInputVectors")) io_dict = { "inputs": {"in0": inp, "weights": wei * num_w_reps}, @@ -1016,9 +998,7 @@ def execute_node(self, context, graph): packed_bits = self.get_outstream_width() out_npy_path = "{}/output.npy".format(code_gen_dir) out_shape = self.get_folded_output_shape() - rtlsim_output_to_npy( - output, out_npy_path, odt, out_shape, packed_bits, target_bits - ) + rtlsim_output_to_npy(output, out_npy_path, odt, out_shape, packed_bits, target_bits) # load and reshape output output = np.load(out_npy_path) @@ -1078,9 +1058,7 @@ def defines(self, var): ] if mem_mode == "decoupled" or mem_mode == "external": wdt = self.get_weight_datatype() - self.code_gen_dict["$DEFINES$"].append( - "#define WP1 {}\n".format(wdt.bitwidth()) - ) + self.code_gen_dict["$DEFINES$"].append("#define WP1 {}\n".format(wdt.bitwidth())) def read_npy_data(self): code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") @@ -1283,19 +1261,14 @@ def pragmas(self): self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() ) - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE ap_ctrl_none port=return" - ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") if mem_mode == "const": self.code_gen_dict["$PRAGMAS$"].append('#include "params.h"') # the weight tensor is ap_uint [PE][WMEM] # partition for parallel access along the PE dimension (dim 1) self.code_gen_dict["$PRAGMAS$"].append( - ( - "#pragma HLS ARRAY_PARTITION variable=weights.m_weights " - "complete dim=1" - ) + ("#pragma HLS ARRAY_PARTITION variable=weights.m_weights " "complete dim=1") ) elif mem_mode == "decoupled" or mem_mode == "external": self.code_gen_dict["$PRAGMAS$"].append( @@ -1317,39 +1290,25 @@ def pragmas(self): if self.calc_tmem() != 0: # TODO find a better way of checking for no pregenerated thresholds self.code_gen_dict["$PRAGMAS$"].append( - ( - "#pragma HLS ARRAY_PARTITION variable=threshs.m_thresholds " - "complete dim=1" - ) + ("#pragma HLS ARRAY_PARTITION variable=threshs.m_thresholds " "complete dim=1") ) self.code_gen_dict["$PRAGMAS$"].append( - ( - "#pragma HLS ARRAY_PARTITION variable=threshs.m_thresholds " - "complete dim=3" - ) + ("#pragma HLS ARRAY_PARTITION variable=threshs.m_thresholds " "complete dim=3") ) # add resource pragma for thresholds if set if ram_style_thresholds == "distributed": self.code_gen_dict["$PRAGMAS$"].append( - ( - "#pragma HLS RESOURCE variable=threshs.m_thresholds " - "core=ROM_2P_LUTRAM" - ) + ("#pragma HLS RESOURCE variable=threshs.m_thresholds " "core=ROM_2P_LUTRAM") ) elif ram_style_thresholds == "block": self.code_gen_dict["$PRAGMAS$"].append( - ( - "#pragma HLS RESOURCE variable=threshs.m_thresholds " - "core=ROM_2P_BRAM" - ) + ("#pragma HLS RESOURCE variable=threshs.m_thresholds " "core=ROM_2P_BRAM") ) elif ram_style_thresholds == "auto": # no pragma needed pass else: - raise Exception( - "Unrecognized ram_style_thresholds value:" + ram_style_thresholds - ) + raise Exception("Unrecognized ram_style_thresholds value:" + ram_style_thresholds) def code_generation_ipi(self): cmd = [] @@ -1373,8 +1332,7 @@ def code_generation_ipi(self): cmd.append("create_bd_pin -dir I -type rst /%s/%s" % (node_name, rst_name)) cmd.append( "create_bd_intf_pin -mode Master " - "-vlnv xilinx.com:interface:axis_rtl:1.0 /%s/%s" - % (node_name, dout_name) + "-vlnv xilinx.com:interface:axis_rtl:1.0 /%s/%s" % (node_name, dout_name) ) cmd.append( "create_bd_intf_pin -mode Slave " @@ -1389,8 +1347,7 @@ def code_generation_ipi(self): strm_vlnv = "amd.com:finn:memstream:1.0" strm_inst = node_name + "_wstrm" cmd.append( - "create_bd_cell -type ip -vlnv %s /%s/%s" - % (strm_vlnv, node_name, strm_inst) + "create_bd_cell -type ip -vlnv %s /%s/%s" % (strm_vlnv, node_name, strm_inst) ) cmd.append( "set_property -dict [list " @@ -1444,8 +1401,7 @@ def code_generation_ipi(self): axilite_name = self.get_verilog_top_module_intf_names()["axilite"][0] cmd.append( "create_bd_intf_pin -mode Slave " - "-vlnv xilinx.com:interface:aximm_rtl:1.0 /%s/%s" - % (node_name, axilite_name) + "-vlnv xilinx.com:interface:aximm_rtl:1.0 /%s/%s" % (node_name, axilite_name) ) cmd.append( "connect_bd_intf_net [get_bd_intf_pins %s/%s] " @@ -1467,9 +1423,7 @@ def get_verilog_top_module_intf_names(self): mem_mode = self.get_nodeattr("mem_mode") sname = self.hls_sname() if mem_mode == "external": - intf_names["s_axis"].append( - ("weights_" + sname, self.get_weightstream_width_padded()) - ) + intf_names["s_axis"].append(("weights_" + sname, self.get_weightstream_width_padded())) if mem_mode == "decoupled": # only expose axilite interface if attribute is set runtime_writable = self.get_nodeattr("runtime_writeable_weights") == 1 @@ -1513,7 +1467,5 @@ def derive_characteristic_fxns(self, period): if mem_mode in ["decoupled", "external"]: n_weight_inps = self.calc_wmem() num_w_reps = np.prod(self.get_nodeattr("numInputVectors")) - io_dict["inputs"]["weights"] = [ - 0 for i in range(num_w_reps * n_weight_inps) - ] + io_dict["inputs"]["weights"] = [0 for i in range(num_w_reps * n_weight_inps)] super().derive_characteristic_fxns(period, override_rtlsim_dict=io_dict) diff --git a/src/finn/custom_op/fpgadataflow/pool_batch.py b/src/finn/custom_op/fpgadataflow/pool_batch.py index 8ccfce7820..8c7bc83141 100644 --- a/src/finn/custom_op/fpgadataflow/pool_batch.py +++ b/src/finn/custom_op/fpgadataflow/pool_batch.py @@ -191,13 +191,9 @@ def verify_node(self): # check supported function fnx = self.get_nodeattr("Function") if fnx in ["MaxPool", "QuantAvgPool"]: - info_messages.append( - "Attribute Function contains a supported pool function" - ) + info_messages.append("Attribute Function contains a supported pool function") else: - info_messages.append( - "Attribute Function contains an unsupported pool function" - ) + info_messages.append("Attribute Function contains an unsupported pool function") return info_messages def global_includes(self): @@ -283,9 +279,7 @@ def docompute(self): else: act_hls_dt = "ap_uint<{}>".format(accum_bits) self.code_gen_dict["$DOCOMPUTE$"] += [ - "QuantAvgPoolFunction<{},{},{}> pool_fxn;".format( - act_hls_dt, o_hls_dt, size - ) + "QuantAvgPoolFunction<{},{},{}> pool_fxn;".format(act_hls_dt, o_hls_dt, size) ] else: raise Exception("Pool_Batch doesn't currently support " + fxn) @@ -352,9 +346,7 @@ def pragmas(self): self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() ) - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE ap_ctrl_none port=return" - ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") def execute_node(self, context, graph): mode = self.get_nodeattr("exec_mode") diff --git a/src/finn/custom_op/fpgadataflow/streamingdatawidthconverter_batch.py b/src/finn/custom_op/fpgadataflow/streamingdatawidthconverter_batch.py index dc905658b1..baf4aed502 100644 --- a/src/finn/custom_op/fpgadataflow/streamingdatawidthconverter_batch.py +++ b/src/finn/custom_op/fpgadataflow/streamingdatawidthconverter_batch.py @@ -213,14 +213,10 @@ def defines(self, var): ] if self.needs_lcm(): lcmWidth = self.get_iowidth_lcm() - assert ( - numInWords % (lcmWidth / inWidth) == 0 - ), "Error in DWC LCM calculation" + assert numInWords % (lcmWidth / inWidth) == 0, "Error in DWC LCM calculation" numLCMToOut = numInWords // (lcmWidth / inWidth) self.code_gen_dict["$DEFINES$"].append("#define LCMWidth %d" % lcmWidth) - self.code_gen_dict["$DEFINES$"].append( - "#define NumLCMToOut %d" % (numLCMToOut) - ) + self.code_gen_dict["$DEFINES$"].append("#define NumLCMToOut %d" % (numLCMToOut)) def read_npy_data(self): code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") @@ -339,13 +335,9 @@ def pragmas(self): self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() ) - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE ap_ctrl_none port=return" - ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") if self.needs_lcm(): - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS DATAFLOW disable_start_propagation" - ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS DATAFLOW disable_start_propagation") def execute_node(self, context, graph): mode = self.get_nodeattr("exec_mode") @@ -371,9 +363,7 @@ def execute_node(self, context, graph): inp = context[node.input[0]] assert str(inp.dtype) == "float32", "Input datatype is not float32" - assert inp.shape == tuple( - exp_shape - ), "Input shape does not match expected shape." + assert inp.shape == tuple(exp_shape), "Input shape does not match expected shape." if self.get_input_datatype() == DataType["BIPOLAR"]: # store bipolar activations as binary @@ -447,8 +437,7 @@ def code_generation_ipi(self): cmd.append("create_bd_pin -dir I -type rst /%s/%s" % (node_name, rst_name)) cmd.append( "create_bd_intf_pin -mode Master " - "-vlnv xilinx.com:interface:axis_rtl:1.0 /%s/%s" - % (node_name, dout_name) + "-vlnv xilinx.com:interface:axis_rtl:1.0 /%s/%s" % (node_name, dout_name) ) cmd.append( "create_bd_intf_pin -mode Slave " @@ -493,8 +482,7 @@ def code_generation_ipi(self): return cmd else: raise Exception( - "DWC implementation style %s not supported, please use hls or vivado" - % impl_style + "DWC implementation style %s not supported, please use hls or vivado" % impl_style ) def lut_estimation(self): diff --git a/src/finn/custom_op/fpgadataflow/streamingfifo.py b/src/finn/custom_op/fpgadataflow/streamingfifo.py index 34b1940fa1..1249bc1251 100644 --- a/src/finn/custom_op/fpgadataflow/streamingfifo.py +++ b/src/finn/custom_op/fpgadataflow/streamingfifo.py @@ -137,9 +137,7 @@ def get_verilog_top_module_name(self): def code_generation_ipgen(self, model, fpgapart, clk): code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - verilog_dir = "{}/project_{}/sol1/impl/verilog".format( - code_gen_dir, self.onnx_node.name - ) + verilog_dir = "{}/project_{}/sol1/impl/verilog".format(code_gen_dir, self.onnx_node.name) os.makedirs(verilog_dir) # copy Q_srl.v from finn-rtllib to verilog directory memstream_dir = get_finn_root() + "/finn-rtllib/memstream/hdl/" @@ -175,9 +173,7 @@ def code_generation_ipgen(self, model, fpgapart, clk): def ipgen_singlenode_code(self): code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - verilog_dir = "{}/project_{}/sol1/impl/verilog".format( - code_gen_dir, self.onnx_node.name - ) + verilog_dir = "{}/project_{}/sol1/impl/verilog".format(code_gen_dir, self.onnx_node.name) # prepare the IP packaging tcl template template = templates.ip_package_tcl self.code_gen_dict.clear() @@ -215,9 +211,7 @@ def get_normal_input_shape(self, ind=0): depth = self.get_adjusted_depth() assert depth >= 2, """Depth is too low""" if depth > 256 and self.get_nodeattr("impl_style") == "rtl": - warnings.warn( - "Depth is high, set between 2 and 256 for efficient SRL implementation" - ) + warnings.warn("Depth is high, set between 2 and 256 for efficient SRL implementation") # derive normal shape from folded shape # StreamingFIFOs are inserted in between fpgadataflow nodes # the folded shape could be for example (1, nf, pe) @@ -297,9 +291,7 @@ def execute_node(self, context, graph): np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input) sim = self.get_rtlsim() nbits = self.get_instream_width() - inp = npy_to_rtlsim_input( - "{}/input_0.npy".format(code_gen_dir), export_idt, nbits - ) + inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) super().reset_rtlsim(sim) super().toggle_clk(sim) output = self.rtlsim(sim, inp) @@ -308,9 +300,7 @@ def execute_node(self, context, graph): packed_bits = self.get_outstream_width() out_npy_path = "{}/output.npy".format(code_gen_dir) out_shape = self.get_folded_output_shape() - rtlsim_output_to_npy( - output, out_npy_path, odt, out_shape, packed_bits, target_bits - ) + rtlsim_output_to_npy(output, out_npy_path, odt, out_shape, packed_bits, target_bits) # load and reshape output output = np.load(out_npy_path) oshape = self.get_normal_output_shape() @@ -375,8 +365,7 @@ def code_generation_ipi(self): cmd.append("create_bd_pin -dir I -type rst /%s/%s" % (node_name, rst_name)) cmd.append( "create_bd_intf_pin -mode Master " - "-vlnv xilinx.com:interface:axis_rtl:1.0 /%s/%s" - % (node_name, dout_name) + "-vlnv xilinx.com:interface:axis_rtl:1.0 /%s/%s" % (node_name, dout_name) ) cmd.append( "create_bd_intf_pin -mode Slave " @@ -397,8 +386,7 @@ def code_generation_ipi(self): ) cmd.append( "set_property -dict [list CONFIG.TDATA_NUM_BYTES {%d}] " - "[get_bd_cells /%s/fifo]" - % (np.ceil(self.get_outstream_width() / 8), node_name) + "[get_bd_cells /%s/fifo]" % (np.ceil(self.get_outstream_width() / 8), node_name) ) cmd.append( "connect_bd_intf_net [get_bd_intf_pins %s/fifo/M_AXIS] " @@ -410,8 +398,7 @@ def code_generation_ipi(self): ) cmd.append( "connect_bd_net [get_bd_pins %s/%s] " - "[get_bd_pins %s/fifo/s_axis_aresetn]" - % (node_name, rst_name, node_name) + "[get_bd_pins %s/fifo/s_axis_aresetn]" % (node_name, rst_name, node_name) ) cmd.append( "connect_bd_net [get_bd_pins %s/%s] " @@ -420,8 +407,7 @@ def code_generation_ipi(self): return cmd else: raise Exception( - "FIFO implementation style %s not supported, please use rtl or vivado" - % impl_style + "FIFO implementation style %s not supported, please use rtl or vivado" % impl_style ) def bram_estimation(self): diff --git a/src/finn/custom_op/fpgadataflow/streamingmaxpool_batch.py b/src/finn/custom_op/fpgadataflow/streamingmaxpool_batch.py index 78f4095cbe..8f294da4ac 100755 --- a/src/finn/custom_op/fpgadataflow/streamingmaxpool_batch.py +++ b/src/finn/custom_op/fpgadataflow/streamingmaxpool_batch.py @@ -105,12 +105,8 @@ def get_normal_output_shape(self, ind=0): ifm_ch = self.get_nodeattr("NumChannels") ceil_mode = self.get_nodeattr("CeilMode") if not self.is_1d(): - assert ( - ifm_dim_h % k_h == 0 - ), "StreamingMaxPool needs ImgDim_h % PoolDim_h == 0" - assert ( - ifm_dim_w % k_w == 0 - ), "StreamingMaxPool needs ImgDim_w % PoolDim_w == 0" + assert ifm_dim_h % k_h == 0, "StreamingMaxPool needs ImgDim_h % PoolDim_h == 0" + assert ifm_dim_w % k_w == 0, "StreamingMaxPool needs ImgDim_w % PoolDim_w == 0" ofm_dim_h = compute_pool_output_dim(ifm_dim_h, k_h, k_h, 0, ceil_mode) ofm_dim_w = compute_pool_output_dim(ifm_dim_w, k_w, k_w, 0, ceil_mode) oshape = (1, ofm_dim_h, ofm_dim_w, ifm_ch) @@ -359,9 +355,7 @@ def pragmas(self): self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() ) - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE ap_ctrl_none port=return" - ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") def execute_node(self, context, graph): mode = self.get_nodeattr("exec_mode") diff --git a/src/finn/custom_op/fpgadataflow/thresholding_batch.py b/src/finn/custom_op/fpgadataflow/thresholding_batch.py index fc5aa61d66..3bcc5c05cf 100644 --- a/src/finn/custom_op/fpgadataflow/thresholding_batch.py +++ b/src/finn/custom_op/fpgadataflow/thresholding_batch.py @@ -142,9 +142,7 @@ def verify_node(self): self.get_nodeattr("outputDataType") info_messages.append("All necessary attributes exist") except Exception: - info_messages.append( - """The required Threshold_Batch attributes do not exist.""" - ) + info_messages.append("""The required Threshold_Batch attributes do not exist.""") return info_messages @@ -305,23 +303,17 @@ def get_hls_compatible_threshold_tensor(self, orig_thres_matrix): ), """Threshold matrix dimension is not as expected (2).""" n_thres_steps = orig_thres_matrix.shape[1] - assert n_thres_steps == self.get_nodeattr( - "numSteps" - ), "Mismatch in threshold steps" + assert n_thres_steps == self.get_nodeattr("numSteps"), "Mismatch in threshold steps" if not self.get_input_datatype().signed(): # ensure all thresholds are nonnegative assert (orig_thres_matrix >= 0).all() # ensure all thresholds are integer - assert np.equal( - np.mod(orig_thres_matrix, 1), 0 - ).all(), "Need int threshold tensor" + assert np.equal(np.mod(orig_thres_matrix, 1), 0).all(), "Need int threshold tensor" ret = orig_thres_matrix # ensure channels = mh , duplicating if necessary if ret.shape[0] == 1: ret = np.tile(ret, (mh, 1)) - assert ( - ret.shape[0] == mh - ), "Channels of threshold matrix are not as expected (mh)" + assert ret.shape[0] == mh, "Channels of threshold matrix are not as expected (mh)" # distribute rows between PEs ret = interleave_matrix_outer_dim_from_partitions(ret, pe) assert ( @@ -456,9 +448,7 @@ def generate_params(self, model, path): # also save weights as Verilog .dat file # This file will be ignored when synthesizing UltraScale memory. weight_filename_rtl = "{}/memblock.dat".format(code_gen_dir) - self.make_weight_file( - thresholds, "decoupled_verilog_dat", weight_filename_rtl - ) + self.make_weight_file(thresholds, "decoupled_verilog_dat", weight_filename_rtl) else: raise Exception("Unrecognized mem_mode") @@ -519,15 +509,11 @@ def execute_node(self, context, graph): out = 2 * out - 1 context[node.output[0]] = out oshape = self.get_normal_output_shape() - assert ( - context[node.output[0]].shape == oshape - ), """Output shape is not as expected""" + assert context[node.output[0]].shape == oshape, """Output shape is not as expected""" elif mode == "rtlsim": sim = self.get_rtlsim() nbits = self.get_instream_width() - inp = npy_to_rtlsim_input( - "{}/input_0.npy".format(code_gen_dir), export_idt, nbits - ) + inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) super().reset_rtlsim(sim) super().toggle_clk(sim) if self.get_nodeattr("mem_mode") == "decoupled": @@ -552,9 +538,7 @@ def execute_node(self, context, graph): packed_bits = self.get_outstream_width() out_npy_path = "{}/output.npy".format(code_gen_dir) out_shape = self.get_folded_output_shape() - rtlsim_output_to_npy( - output, out_npy_path, odt, out_shape, packed_bits, target_bits - ) + rtlsim_output_to_npy(output, out_npy_path, odt, out_shape, packed_bits, target_bits) # load and reshape output output = np.load(out_npy_path) @@ -594,8 +578,7 @@ def defines(self, var): "#define ActVal1 %d" % self.get_nodeattr("ActVal") ) self.code_gen_dict["$DEFINES$"].append( - "#define ThresType1 %s" - % self.get_weight_datatype().get_hls_datatype_str() + "#define ThresType1 %s" % self.get_weight_datatype().get_hls_datatype_str() ) self.code_gen_dict["$DEFINES$"].append( "#define NumSteps1 %d" % self.get_nodeattr("numSteps") @@ -768,25 +751,17 @@ def pragmas(self): self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() ) - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE ap_ctrl_none port=return" - ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") if self.get_nodeattr("mem_mode") == "const": # the threshold tensor is acc_type [PE][TMEM][N_THRES] # partition for parallel access along PE and N_THRES # dimensions (dims 1 and 3) self.code_gen_dict["$PRAGMAS$"].append( - ( - "#pragma HLS ARRAY_PARTITION variable=threshs.m_thresholds " - "complete dim=1" - ) + ("#pragma HLS ARRAY_PARTITION variable=threshs.m_thresholds " "complete dim=1") ) self.code_gen_dict["$PRAGMAS$"].append( - ( - "#pragma HLS ARRAY_PARTITION variable=threshs.m_thresholds " - "complete dim=3" - ) + ("#pragma HLS ARRAY_PARTITION variable=threshs.m_thresholds " "complete dim=3") ) # set resource type ram_style = self.get_nodeattr("ram_style") @@ -797,17 +772,11 @@ def pragmas(self): if pe < ich: if ram_style == "distributed": self.code_gen_dict["$PRAGMAS$"].append( - ( - "#pragma HLS RESOURCE variable=threshs.m_thresholds " - "core=ROM_2P_LUTRAM" - ) + ("#pragma HLS RESOURCE variable=threshs.m_thresholds " "core=ROM_2P_LUTRAM") ) elif ram_style == "block": self.code_gen_dict["$PRAGMAS$"].append( - ( - "#pragma HLS RESOURCE variable=threshs.m_thresholds " - "core=ROM_2P_BRAM" - ) + ("#pragma HLS RESOURCE variable=threshs.m_thresholds " "core=ROM_2P_BRAM") ) else: raise Exception( @@ -839,8 +808,7 @@ def code_generation_ipi(self): cmd.append("create_bd_pin -dir I -type rst /%s/%s" % (node_name, rst_name)) cmd.append( "create_bd_intf_pin -mode Master " - "-vlnv xilinx.com:interface:axis_rtl:1.0 /%s/%s" - % (node_name, dout_name) + "-vlnv xilinx.com:interface:axis_rtl:1.0 /%s/%s" % (node_name, dout_name) ) cmd.append( "create_bd_intf_pin -mode Slave " @@ -855,8 +823,7 @@ def code_generation_ipi(self): strm_vlnv = "amd.com:finn:memstream:1.0" strm_inst = node_name + "_wstrm" cmd.append( - "create_bd_cell -type ip -vlnv %s /%s/%s" - % (strm_vlnv, node_name, strm_inst) + "create_bd_cell -type ip -vlnv %s /%s/%s" % (strm_vlnv, node_name, strm_inst) ) cmd.append( "set_property -dict [list " @@ -910,8 +877,7 @@ def code_generation_ipi(self): axilite_name = self.get_verilog_top_module_intf_names()["axilite"][0] cmd.append( "create_bd_intf_pin -mode Slave " - "-vlnv xilinx.com:interface:aximm_rtl:1.0 /%s/%s" - % (node_name, axilite_name) + "-vlnv xilinx.com:interface:aximm_rtl:1.0 /%s/%s" % (node_name, axilite_name) ) cmd.append( "connect_bd_intf_net [get_bd_intf_pins %s/%s] " @@ -966,7 +932,5 @@ def derive_characteristic_fxns(self, period): if mem_mode in ["decoupled", "external"]: n_weight_inps = self.calc_tmem() num_w_reps = np.prod(self.get_nodeattr("numInputVectors")) - io_dict["inputs"]["weights"] = [ - 0 for i in range(num_w_reps * n_weight_inps) - ] + io_dict["inputs"]["weights"] = [0 for i in range(num_w_reps * n_weight_inps)] super().derive_characteristic_fxns(period, override_rtlsim_dict=io_dict) diff --git a/src/finn/custom_op/fpgadataflow/tlastmarker.py b/src/finn/custom_op/fpgadataflow/tlastmarker.py index 6eaf03ab16..9309841b2e 100644 --- a/src/finn/custom_op/fpgadataflow/tlastmarker.py +++ b/src/finn/custom_op/fpgadataflow/tlastmarker.py @@ -130,11 +130,9 @@ def docompute(self): self.code_gen_dict["$DOCOMPUTE$"] = [ "for(unsigned int i=0; i in0_%s ("in0_%s");' - % (self.hls_sname(), self.hls_sname()) + 'hls::stream in0_%s ("in0_%s");' % (self.hls_sname(), self.hls_sname()) ) self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream out_%s ("out_%s");' - % (self.hls_sname(), self.hls_sname()) + 'hls::stream out_%s ("out_%s");' % (self.hls_sname(), self.hls_sname()) ) def get_verilog_top_module_intf_names(self): diff --git a/src/finn/custom_op/fpgadataflow/upsampler.py b/src/finn/custom_op/fpgadataflow/upsampler.py index ab5a734e7c..9c0db1f3df 100644 --- a/src/finn/custom_op/fpgadataflow/upsampler.py +++ b/src/finn/custom_op/fpgadataflow/upsampler.py @@ -107,9 +107,7 @@ def make_shape_compatible_op(self, model): exp_ishape = self.get_normal_input_shape() oshape = self.get_normal_output_shape() ishape = tuple(model.get_tensor_shape(self.onnx_node.input[0])) - assert ( - ishape == exp_ishape - ), "Unexpect input shape for UpsampleNearestNeighbour_Batch." + assert ishape == exp_ishape, "Unexpect input shape for UpsampleNearestNeighbour_Batch." return super().make_const_shape_op(oshape) def infer_node_datatype(self, model): @@ -280,9 +278,7 @@ def pragmas(self): self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() ) - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE ap_ctrl_none port=return" - ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") def execute_node(self, context, graph): mode = self.get_nodeattr("exec_mode") diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index 64fb5dcbe1..f817751852 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -284,9 +284,7 @@ def get_folded_input_shape(self, ind=0): simd = self.get_nodeattr("SIMD") pe = self.get_nodeattr("PE") kernel_2 = k_h * k_w - assert ( - kernel_2 % simd == 0 - ), "Requirement kernel (k_h * k_w) divisable by SIMD is violated." + assert kernel_2 % simd == 0, "Requirement kernel (k_h * k_w) divisable by SIMD is violated." sf = kernel_2 // simd assert ch % pe == 0, "Requirement Channels divisable by PE is violated." nf = ch // pe @@ -436,9 +434,7 @@ def get_hls_compatible_threshold_tensor(self, orig_thres_matrix): # ensure channels = mh , duplicating if necessary if ret.shape[0] == 1: ret = np.tile(ret, (ch, 1)) - assert ( - ret.shape[0] == ch - ), "Channels of threshold matrix are not as expected (ch)" + assert ret.shape[0] == ch, "Channels of threshold matrix are not as expected (ch)" # distribute rows between PEs ret = interleave_matrix_outer_dim_from_partitions(ret, pe) assert ( @@ -476,9 +472,7 @@ def make_weight_file(self, weights, weight_file_mode, weight_file_name): if self.get_weight_datatype() == DataType["BIPOLAR"]: export_wdt = DataType["BINARY"] if weight_file_mode == "hls_header": - weight_hls_code = numpy_to_hls_code( - weight_tensor, export_wdt, "weights", True, True - ) + weight_hls_code = numpy_to_hls_code(weight_tensor, export_wdt, "weights", True, True) # write weights into C++ header file as dictated by finn-hlslib f_weights = open(weight_file_name, "w") if export_wdt.bitwidth() != 1: @@ -512,14 +506,10 @@ def make_weight_file(self, weights, weight_file_mode, weight_file_name): pe = self.get_nodeattr("PE") simd = self.get_nodeattr("SIMD") # simd_flipped - weight_tensor_simd_flipped = weight_tensor_simd_flipped.reshape( - 1, -1, pe * simd - ) + weight_tensor_simd_flipped = weight_tensor_simd_flipped.reshape(1, -1, pe * simd) weight_tensor_simd_flipped = weight_tensor_simd_flipped.copy() # flipped - weight_tensor_pe_flipped = weight_tensor_pe_flipped.reshape( - 1, -1, pe * simd - ) + weight_tensor_pe_flipped = weight_tensor_pe_flipped.reshape(1, -1, pe * simd) weight_tensor_pe_flipped = weight_tensor_pe_flipped.copy() if weight_file_mode == "decoupled_npy": # save weight stream into npy for cppsim @@ -582,9 +572,7 @@ def generate_params(self, model, path): # also save weights as Verilog .dat file # This file will be ignored when synthesizing UltraScale memory. weight_filename_rtl = "{}/memblock.dat".format(code_gen_dir) - self.make_weight_file( - weights, "decoupled_verilog_dat", weight_filename_rtl - ) + self.make_weight_file(weights, "decoupled_verilog_dat", weight_filename_rtl) else: raise Exception( """Please set mem_mode to "const", "decoupled", or "external", @@ -703,9 +691,7 @@ def execute_node(self, context, graph): elif mode == "rtlsim": sim = self.get_rtlsim() nbits = self.get_instream_width() - inp = npy_to_rtlsim_input( - "{}/input_0.npy".format(code_gen_dir), export_idt, nbits - ) + inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) super().reset_rtlsim(sim) super().toggle_clk(sim) @@ -716,9 +702,7 @@ def execute_node(self, context, graph): # so use it as such for weight generation if self.get_weight_datatype() == DataType["BIPOLAR"]: export_wdt = DataType["BINARY"] - wei = npy_to_rtlsim_input( - "{}/weights.npy".format(code_gen_dir), export_wdt, wnbits - ) + wei = npy_to_rtlsim_input("{}/weights.npy".format(code_gen_dir), export_wdt, wnbits) dim_h, dim_w = self.get_nodeattr("Dim") num_w_reps = dim_h * dim_w @@ -735,9 +719,7 @@ def execute_node(self, context, graph): packed_bits = self.get_outstream_width() out_npy_path = "{}/output.npy".format(code_gen_dir) out_shape = self.get_folded_output_shape() - rtlsim_output_to_npy( - output, out_npy_path, odt, out_shape, packed_bits, target_bits - ) + rtlsim_output_to_npy(output, out_npy_path, odt, out_shape, packed_bits, target_bits) # load and reshape output output = np.load(out_npy_path) @@ -783,9 +765,7 @@ def defines(self, var): ] if mem_mode == "decoupled" or mem_mode == "external": wdt = self.get_weight_datatype() - self.code_gen_dict["$DEFINES$"].append( - "#define WP1 {}\n".format(wdt.bitwidth()) - ) + self.code_gen_dict["$DEFINES$"].append("#define WP1 {}\n".format(wdt.bitwidth())) def read_npy_data(self): code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") @@ -986,19 +966,14 @@ def pragmas(self): self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() ) - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE ap_ctrl_none port=return" - ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") if mem_mode == "const": self.code_gen_dict["$PRAGMAS$"].append('#include "params.h"') # the weight tensor is ap_uint [PE][WMEM] # partition for parallel access along the PE dimension (dim 1) self.code_gen_dict["$PRAGMAS$"].append( - ( - "#pragma HLS ARRAY_PARTITION variable=weights.m_weights " - "complete dim=1" - ) + ("#pragma HLS ARRAY_PARTITION variable=weights.m_weights " "complete dim=1") ) elif mem_mode == "decoupled" or mem_mode == "external": self.code_gen_dict["$PRAGMAS$"].append( @@ -1016,16 +991,10 @@ def pragmas(self): if self.calc_tmem() != 0: # TODO find a better way of checking for no pregenerated thresholds self.code_gen_dict["$PRAGMAS$"].append( - ( - "#pragma HLS ARRAY_PARTITION variable=threshs.m_thresholds " - "complete dim=1" - ) + ("#pragma HLS ARRAY_PARTITION variable=threshs.m_thresholds " "complete dim=1") ) self.code_gen_dict["$PRAGMAS$"].append( - ( - "#pragma HLS ARRAY_PARTITION variable=threshs.m_thresholds " - "complete dim=3" - ) + ("#pragma HLS ARRAY_PARTITION variable=threshs.m_thresholds " "complete dim=3") ) def get_verilog_top_module_intf_names(self): @@ -1033,9 +1002,7 @@ def get_verilog_top_module_intf_names(self): mem_mode = self.get_nodeattr("mem_mode") sname = self.hls_sname() if mem_mode == "external": - intf_names["s_axis"].append( - ("weights_" + sname, self.get_weightstream_width_padded()) - ) + intf_names["s_axis"].append(("weights_" + sname, self.get_weightstream_width_padded())) if mem_mode == "decoupled": # only expose axilite interface if attribute is set runtime_writable = self.get_nodeattr("runtime_writeable_weights") == 1 @@ -1065,8 +1032,7 @@ def code_generation_ipi(self): cmd.append("create_bd_pin -dir I -type rst /%s/%s" % (node_name, rst_name)) cmd.append( "create_bd_intf_pin -mode Master " - "-vlnv xilinx.com:interface:axis_rtl:1.0 /%s/%s" - % (node_name, dout_name) + "-vlnv xilinx.com:interface:axis_rtl:1.0 /%s/%s" % (node_name, dout_name) ) cmd.append( "create_bd_intf_pin -mode Slave " @@ -1081,8 +1047,7 @@ def code_generation_ipi(self): strm_vlnv = "amd.com:finn:memstream:1.0" strm_inst = node_name + "_wstrm" cmd.append( - "create_bd_cell -type ip -vlnv %s /%s/%s" - % (strm_vlnv, node_name, strm_inst) + "create_bd_cell -type ip -vlnv %s /%s/%s" % (strm_vlnv, node_name, strm_inst) ) cmd.append( "set_property -dict [list " @@ -1136,8 +1101,7 @@ def code_generation_ipi(self): axilite_name = self.get_verilog_top_module_intf_names()["axilite"][0] cmd.append( "create_bd_intf_pin -mode Slave " - "-vlnv xilinx.com:interface:aximm_rtl:1.0 /%s/%s" - % (node_name, axilite_name) + "-vlnv xilinx.com:interface:aximm_rtl:1.0 /%s/%s" % (node_name, axilite_name) ) cmd.append( "connect_bd_intf_net [get_bd_intf_pins %s/%s] " @@ -1281,9 +1245,7 @@ def lut_estimation(self): comp_luts = (2**B - 1) * acc_bits return int( - c0 - + c1 * (P * (mult_luts + addertree_luts + acc_luts + thr_luts + comp_luts)) - + c2 + c0 + c1 * (P * (mult_luts + addertree_luts + acc_luts + thr_luts + comp_luts)) + c2 ) def dsp_estimation(self): @@ -1356,7 +1318,5 @@ def derive_characteristic_fxns(self, period): if mem_mode in ["decoupled", "external"]: n_weight_inps = self.calc_wmem() num_w_reps = np.prod(self.get_nodeattr("numInputVectors")) - io_dict["inputs"]["weights"] = [ - 0 for i in range(num_w_reps * n_weight_inps) - ] + io_dict["inputs"]["weights"] = [0 for i in range(num_w_reps * n_weight_inps)] super().derive_characteristic_fxns(period, override_rtlsim_dict=io_dict) diff --git a/src/finn/qnn-data/cybsec-mlp/validate-unsw-nb15.py b/src/finn/qnn-data/cybsec-mlp/validate-unsw-nb15.py index be09abad9c..e0e2a75f19 100644 --- a/src/finn/qnn-data/cybsec-mlp/validate-unsw-nb15.py +++ b/src/finn/qnn-data/cybsec-mlp/validate-unsw-nb15.py @@ -57,9 +57,7 @@ def make_unsw_nb15_test_batches(bsize, dataset_root, limit_batches): help='name of bitfile (i.e. "resizer.bit")', default="../bitfile/finn-accel.bit", ) - parser.add_argument( - "--dataset_root", help="dataset root dir for download/reuse", default="." - ) + parser.add_argument("--dataset_root", help="dataset root dir for download/reuse", default=".") parser.add_argument( "--limit_batches", help="number of batches, -1 for max", type=int, default=-1 ) @@ -72,9 +70,7 @@ def make_unsw_nb15_test_batches(bsize, dataset_root, limit_batches): limit_batches = args.limit_batches print("Loading dataset...") - (test_imgs, test_labels) = make_unsw_nb15_test_batches( - bsize, dataset_root, limit_batches - ) + (test_imgs, test_labels) = make_unsw_nb15_test_batches(bsize, dataset_root, limit_batches) ok = 0 nok = 0 diff --git a/src/finn/qnn-data/templates/driver/driver_base.py b/src/finn/qnn-data/templates/driver/driver_base.py index 5f6f00da13..f701122885 100644 --- a/src/finn/qnn-data/templates/driver/driver_base.py +++ b/src/finn/qnn-data/templates/driver/driver_base.py @@ -122,7 +122,7 @@ def load_external_weights(self): w_filenames = [] if not os.path.isdir(self.runtime_weight_dir): return - for (dirpath, dirnames, filenames) in os.walk(self.runtime_weight_dir): + for dirpath, dirnames, filenames in os.walk(self.runtime_weight_dir): w_filenames.extend(filenames) tmp_weight_dict = {} @@ -173,7 +173,7 @@ def load_runtime_weights(self, flush_accel=True, verify=True): w_filenames = [] if not os.path.isdir(self.runtime_weight_dir): return - for (dirpath, dirnames, filenames) in os.walk(self.runtime_weight_dir): + for dirpath, dirnames, filenames in os.walk(self.runtime_weight_dir): w_filenames.extend(filenames) rt_weight_dict = {} for w_filename in w_filenames: @@ -182,18 +182,14 @@ def load_runtime_weights(self, flush_accel=True, verify=True): dat = f.read() else: continue - layer_w = np.fromiter( - [int(x, 16) for x in dat.strip().split()], dtype=np.uint32 - ) + layer_w = np.fromiter([int(x, 16) for x in dat.strip().split()], dtype=np.uint32) sdp_ind = int(w_filename.split("_")[0]) layer_ind = int(w_filename.split("_")[1]) rt_weight_dict[(sdp_ind, layer_ind)] = layer_w for sdp_ind, layer_ind in rt_weight_dict.keys(): cand_if_name = "StreamingDataflowPartition_%d" % sdp_ind if cand_if_name in self.ip_dict.keys(): - layer_mmio = getattr( - self, "StreamingDataflowPartition_%d" % sdp_ind - ).mmio + layer_mmio = getattr(self, "StreamingDataflowPartition_%d" % sdp_ind).mmio layer_w = rt_weight_dict[(sdp_ind, layer_ind)] layer_mmio.write_mm(0, layer_w.tobytes()) if verify: @@ -342,9 +338,7 @@ def execute_on_buffers(self, asynch=False, batch_size=None): assert batch_size <= self.batch_size, "Specified batch_size is too large." if self.platform == "zynq-iodma": for o in range(self.num_outputs): - assert ( - self.odma[o].read(0x00) & 0x4 != 0 - ), "Output DMA %d is not idle" % (o) + assert self.odma[o].read(0x00) & 0x4 != 0, "Output DMA %d is not idle" % (o) # manually launch IODMAs since signatures are missing for iwdma, iwbuf, iwdma_name in self.external_weights: iwdma.write(0x10, iwbuf.device_address) @@ -360,17 +354,13 @@ def execute_on_buffers(self, asynch=False, batch_size=None): self.idma[i].write(0x00, 1) elif self.platform == "alveo": for o in range(self.num_outputs): - assert self.odma_handle[o] is None, ( - "Output DMA %d is already running" % o - ) + assert self.odma_handle[o] is None, "Output DMA %d is already running" % o for i in range(self.num_inputs): self.idma[i].start(self.ibuf_packed_device[i], batch_size) for iwdma, iwbuf, iwdma_name in self.external_weights: iwdma.start(iwbuf, batch_size) for o in range(self.num_outputs): - self.odma_handle[o] = self.odma[o].start( - self.obuf_packed_device[o], batch_size - ) + self.odma_handle[o] = self.odma[o].start(self.obuf_packed_device[o], batch_size) else: raise Exception("Unrecognized platform: %s" % self.platform) # blocking behavior depends on asynch parameter @@ -386,9 +376,7 @@ def wait_until_finished(self): while status & 0x2 == 0: status = self.odma[o].read(0x00) elif self.platform == "alveo": - assert all( - [x is not None for x in self.odma_handle] - ), "No odma_handle to wait on" + assert all([x is not None for x in self.odma_handle]), "No odma_handle to wait on" for o in range(self.num_outputs): self.odma_handle[o].wait() self.odma_handle[o] = None @@ -402,9 +390,7 @@ def execute(self, input_npy): # if single input, convert to list to normalize how we process the input if not type(input_npy) is list: input_npy = [input_npy] - assert self.num_inputs == len( - input_npy - ), "Not all accelerator inputs are specified." + assert self.num_inputs == len(input_npy), "Not all accelerator inputs are specified." for i in range(self.num_inputs): ibuf_folded = self.fold_input(input_npy[i], ind=i) ibuf_packed = self.pack_input(ibuf_folded, ind=i) diff --git a/src/finn/qnn-data/templates/driver/validate.py b/src/finn/qnn-data/templates/driver/validate.py index 1b29d4342c..c8bc1c009d 100644 --- a/src/finn/qnn-data/templates/driver/validate.py +++ b/src/finn/qnn-data/templates/driver/validate.py @@ -38,9 +38,7 @@ parser.add_argument( "--batchsize", help="number of samples for inference", type=int, default=100 ) - parser.add_argument( - "--dataset", help="dataset to use (mnist of cifar10)", required=True - ) + parser.add_argument("--dataset", help="dataset to use (mnist of cifar10)", required=True) parser.add_argument( "--platform", help="Target platform: zynq-iodma alveo", default="zynq-iodma" ) diff --git a/src/finn/transformation/fpgadataflow/annotate_resources.py b/src/finn/transformation/fpgadataflow/annotate_resources.py index 0cc4234c8c..bb5637f7d3 100644 --- a/src/finn/transformation/fpgadataflow/annotate_resources.py +++ b/src/finn/transformation/fpgadataflow/annotate_resources.py @@ -76,9 +76,7 @@ def apply(self, model): # recurse into model to manually annotate per-layer resources sdp_model_filename = getCustomOp(node).get_nodeattr("model") sdp_model = ModelWrapper(sdp_model_filename) - sdp_model = sdp_model.transform( - AnnotateResources(self.mode, self.res_dict) - ) + sdp_model = sdp_model.transform(AnnotateResources(self.mode, self.res_dict)) sdp_dict = sdp_model.get_metadata_prop("res_total_" + self.mode) sdp_dict = eval(sdp_dict) # save transformed model diff --git a/src/finn/transformation/fpgadataflow/cleanup.py b/src/finn/transformation/fpgadataflow/cleanup.py index 1d0efaf4bb..398580c48e 100644 --- a/src/finn/transformation/fpgadataflow/cleanup.py +++ b/src/finn/transformation/fpgadataflow/cleanup.py @@ -79,7 +79,5 @@ def apply(self, model): except KeyError: # exception if op_type is not supported - raise Exception( - "Custom op_type %s is currently not supported." % op_type - ) + raise Exception("Custom op_type %s is currently not supported." % op_type) return (model, False) diff --git a/src/finn/transformation/fpgadataflow/compile_cppsim.py b/src/finn/transformation/fpgadataflow/compile_cppsim.py index da337caa62..e93a8ec307 100644 --- a/src/finn/transformation/fpgadataflow/compile_cppsim.py +++ b/src/finn/transformation/fpgadataflow/compile_cppsim.py @@ -70,7 +70,5 @@ def applyNodeLocal(self, node): in node attribute "executable_path".""" except KeyError: # exception if op_type is not supported - raise Exception( - "Custom op_type %s is currently not supported." % op_type - ) + raise Exception("Custom op_type %s is currently not supported." % op_type) return (node, False) diff --git a/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py b/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py index fcfe9e7727..ef02453498 100644 --- a/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py +++ b/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py @@ -61,9 +61,7 @@ def apply(self, model): i2c_out_shape = model.get_tensor_shape(i2c_output) dt = model.get_tensor_datatype(i2c_input) if not dt.is_integer(): - warnings.warn( - "%s : Input is not int. Can't infer ConvInpGen." % n.name - ) + warnings.warn("%s : Input is not int. Can't infer ConvInpGen." % n.name) continue i2c_inst = getCustomOp(n) stride_h, stride_w = i2c_inst.get_nodeattr("stride") @@ -92,8 +90,7 @@ def apply(self, model): # assert dt.allowed(pad_val),"""FMPadding_Batch DataType # must support pad_val""" assert pad_val == 0, ( - "%s : FMPadding_Batch doesn't currently support pad_val!= 0" - % n.name + "%s : FMPadding_Batch doesn't currently support pad_val!= 0" % n.name ) odim_padding_h = ifm_dim_h + pad_h @@ -113,9 +110,7 @@ def apply(self, model): ConvInpGen_idim_h = odim_padding_h ConvInpGen_idim_w = odim_padding_w - padding_optype = ( - "FMPadding_rtl" if self.use_rtl_variant else "FMPadding_Batch" - ) + padding_optype = "FMPadding_rtl" if self.use_rtl_variant else "FMPadding_Batch" padding_node = helper.make_node( padding_optype, @@ -167,13 +162,9 @@ def apply(self, model): if (stride_h > 1 or stride_w > 1) and is_kernel_pointwise: downsample_1D = (ifm_dim_h == 1) or (ifm_dim_w == 1) is1D_unitx = ifm_dim_w == 1 - downsample_2D = ( - (not downsample_1D) and is_square_image and is_equal_stride - ) + downsample_2D = (not downsample_1D) and is_square_image and is_equal_stride if not (downsample_1D or downsample_2D): - warnings.warn( - f"Couldn't infer Downsample from {n.name},check config." - ) + warnings.warn(f"Couldn't infer Downsample from {n.name},check config.") continue ConvInpGen_idim = max(ConvInpGen_idim_h, ConvInpGen_idim_w) stride = max(stride_h, stride_w) @@ -196,9 +187,7 @@ def apply(self, model): graph.node.insert(ConvInpGen_node_idx, ConvInpGen_node) else: # create equivalent ConvolutionInputGenerator node - if ( - is_square_image and is_square_kernel - ): # square images and square kernels + if is_square_image and is_square_kernel: # square images and square kernels assert is_equal_stride, ( """%s: Non-equal strides along different axes is not supported for (non-)square convolutions""" @@ -290,15 +279,13 @@ def apply(self, model): dt = model.get_tensor_datatype(n.input[0]) if not dt.is_integer(): warnings.warn( - "%s: Input not int. Can't infer UpsampleNearestNeighbour." - % n.name + "%s: Input not int. Can't infer UpsampleNearestNeighbour." % n.name ) continue if model.get_tensor_layout(n.input[0]) != DataLayout.NHWC: warnings.warn( - "%s: Input not NHWC. Can't infer UpsampleNearestNeighbour." - % n.name + "%s: Input not NHWC. Can't infer UpsampleNearestNeighbour." % n.name ) continue @@ -319,8 +306,7 @@ def apply(self, model): is_scale_square_2d = scales[1] == scales[2] is_scale_1d = scales[1] > 1 and scales[2] == 1 assert is_scale_square_2d or is_scale_1d, ( - "%s: Upsampling only supported for 1D H, or 2D square scaling" - % n.name + "%s: Upsampling only supported for 1D H, or 2D square scaling" % n.name ) assert scales[0] == scales[3] == 1, ( n.name + ": Upsampling is only supported for scales with " @@ -334,8 +320,7 @@ def apply(self, model): is_shape_1d = in_shape[1] > 1 and in_shape[2] == 1 assert is_shape_square_2d or is_shape_1d, ( - "%s: Upsampling is only supported for 1D H or 2D square inputs." - % n.name + "%s: Upsampling is only supported for 1D H or 2D square inputs." % n.name ) # Extract information for HLS node @@ -538,9 +523,7 @@ def apply(self, model): elif node.op_type == "QuantAvgPool2d": assert odt.is_integer(), """Output data type for QuantAvgPool2d needs to be integer""" - assert all( - x == 0 for x in pad - ), "Padding is not supported for QuantAvgPool2d" + assert all(x == 0 for x in pad), "Padding is not supported for QuantAvgPool2d" inst = getCustomOp(node) pool_fxn = "QuantAvgPool" pool_size_param = inst.get_shifts() @@ -548,9 +531,7 @@ def apply(self, model): else: raise Exception( - "pad_value and pool_fxn not configured for {}".format( - node.op_type - ) + "pad_value and pool_fxn not configured for {}".format(node.op_type) ) # format input tensor @@ -809,17 +790,13 @@ def apply(self, model): scale = getCustomOp(consumer).get_nodeattr("out_scale") actval = getCustomOp(consumer).get_nodeattr("out_bias") assert int(actval) == actval, ( - consumer.name - + ": out_bias must be integer for HLS conversion." + consumer.name + ": out_bias must be integer for HLS conversion." ) actval = int(actval) odt_is_bipolar = odt == DataType["BIPOLAR"] - bipolar_ok = ( - odt_is_bipolar and (scale == 2.0) and (actval == -1) - ) + bipolar_ok = odt_is_bipolar and (scale == 2.0) and (actval == -1) assert scale == 1.0 or bipolar_ok, ( - consumer.name - + ": out_scale=1 or bipolar output needed for conversion." + consumer.name + ": out_scale=1 or bipolar output needed for conversion." ) assert (not odt.signed()) or (actval < 0), ( consumer.name + ": Signed output requres actval < 0" @@ -909,10 +886,7 @@ def apply(self, model): graph_modified = False for n in graph.node: node_ind += 1 - if ( - n.op_type == "MatMul" - and model.get_tensor_sparsity(n.input[1]) is not None - ): + if n.op_type == "MatMul" and model.get_tensor_sparsity(n.input[1]) is not None: sparsity = model.get_tensor_sparsity(n.input[1]) try: k_h, k_w = sparsity["dw"]["kernel_shape"] @@ -971,13 +945,11 @@ def apply(self, model): odt = model.get_tensor_datatype(mt_output) scale = getCustomOp(consumer).get_nodeattr("out_scale") assert scale == 1.0, ( - consumer.name - + ": out_scale must be equal to 1.0 for HLS conversion." + consumer.name + ": out_scale must be equal to 1.0 for HLS conversion." ) actval = getCustomOp(consumer).get_nodeattr("out_bias") assert int(actval) == actval, ( - consumer.name - + ": out_bias must be integer for HLS conversion." + consumer.name + ": out_bias must be integer for HLS conversion." ) actval = int(actval) assert (not odt.signed()) or (actval < 0), ( @@ -1093,13 +1065,11 @@ def apply(self, model): odt = model.get_tensor_datatype(thl_output) scale = getCustomOp(node).get_nodeattr("out_scale") assert scale == 1.0, ( - node.name - + ": MultiThreshold out_scale must be 1 for HLS conversion." + node.name + ": MultiThreshold out_scale must be 1 for HLS conversion." ) actval = getCustomOp(node).get_nodeattr("out_bias") assert int(actval) == actval, ( - node.name - + ": MultiThreshold out_bias must be integer for HLS conversion." + node.name + ": MultiThreshold out_bias must be integer for HLS conversion." ) actval = int(actval) assert (not odt.signed()) or (actval < 0), ( @@ -1369,9 +1339,7 @@ def apply(self, model): # check if the shape of initializer is compatible ll_cinit_shape = list(ll_cinit.shape) if np.prod(ll_cinit_shape) == 1: - warnings.warn( - "Broadcasting " + str(node.op_type) + "(" + node.name + ")" - ) + warnings.warn("Broadcasting " + str(node.op_type) + "(" + node.name + ")") ll_cinit = np.full((ch), ll_cinit.flatten()[0]) elif np.prod(ll_cinit_shape) != ch or ll_cinit_shape[ch_index] != ch: # parameter shape not compatible with Channelwise_batch @@ -1680,9 +1648,7 @@ def apply(self, model): dt0 = model.get_tensor_datatype(node.input[0]) if dt0 is None: continue - dt_coherent = all( - [model.get_tensor_datatype(x) == dt0 for x in node.input] - ) + dt_coherent = all([model.get_tensor_datatype(x) == dt0 for x in node.input]) if not dt_coherent: continue # skip conversion if any inputs are static diff --git a/src/finn/transformation/fpgadataflow/create_stitched_ip.py b/src/finn/transformation/fpgadataflow/create_stitched_ip.py index ef1afb95ca..6e40f39687 100644 --- a/src/finn/transformation/fpgadataflow/create_stitched_ip.py +++ b/src/finn/transformation/fpgadataflow/create_stitched_ip.py @@ -86,9 +86,7 @@ class CreateStitchedIP(Transformation): The packaged block design IP can be found under the ip subdirectory. """ - def __init__( - self, fpgapart, clk_ns, ip_name="finn_design", vitis=False, signature=[] - ): + def __init__(self, fpgapart, clk_ns, ip_name="finn_design", vitis=False, signature=[]): super().__init__() self.fpgapart = fpgapart self.clk_ns = clk_ns @@ -121,17 +119,13 @@ def connect_clk_rst(self, node): # make clock and reset external, if they aren't already if not self.clock_reset_are_external: self.connect_cmds.append( - "make_bd_pins_external [get_bd_pins %s/%s]" - % (inst_name, clock_intf_name) + "make_bd_pins_external [get_bd_pins %s/%s]" % (inst_name, clock_intf_name) ) self.connect_cmds.append("set_property name ap_clk [get_bd_ports ap_clk_0]") self.connect_cmds.append( - "make_bd_pins_external [get_bd_pins %s/%s]" - % (inst_name, reset_intf_name) - ) - self.connect_cmds.append( - "set_property name ap_rst_n [get_bd_ports ap_rst_n_0]" + "make_bd_pins_external [get_bd_pins %s/%s]" % (inst_name, reset_intf_name) ) + self.connect_cmds.append("set_property name ap_rst_n [get_bd_ports ap_rst_n_0]") self.clock_reset_are_external = True self.intf_names["clk"] = ["ap_clk"] self.intf_names["rst"] = ["ap_rst_n"] @@ -172,13 +166,9 @@ def connect_axi(self, node): ) self.connect_cmds.append("assign_bd_address") seg_name = "%s/Data_m_axi_gmem/SEG_%s_Reg" % (inst_name, ext_if_name) - self.connect_cmds.append( - "set_property offset 0 [get_bd_addr_segs {%s}]" % (seg_name) - ) + self.connect_cmds.append("set_property offset 0 [get_bd_addr_segs {%s}]" % (seg_name)) # TODO should propagate this information from the node instead of 4G - self.connect_cmds.append( - "set_property range 4G [get_bd_addr_segs {%s}]" % (seg_name) - ) + self.connect_cmds.append("set_property range 4G [get_bd_addr_segs {%s}]" % (seg_name)) self.intf_names["aximm"] = [(ext_if_name, aximm_intf_name[0][1])] self.has_aximm = True @@ -215,8 +205,7 @@ def connect_s_axis_external(self, node, idx=None): continue input_intf_name = input_intf_names[i][0] self.connect_cmds.append( - "make_bd_intf_pins_external [get_bd_intf_pins %s/%s]" - % (inst_name, input_intf_name) + "make_bd_intf_pins_external [get_bd_intf_pins %s/%s]" % (inst_name, input_intf_name) ) self.connect_cmds.append( "set_property name s_axis_%d [get_bd_intf_ports %s_0]" @@ -236,12 +225,10 @@ def connect_ap_none_external(self, node): for i in range(len(input_intf_names)): input_intf_name = input_intf_names[i] self.connect_cmds.append( - "make_bd_pins_external [get_bd_pins %s/%s]" - % (inst_name, input_intf_name) + "make_bd_pins_external [get_bd_pins %s/%s]" % (inst_name, input_intf_name) ) self.connect_cmds.append( - "set_property name %s [get_bd_ports %s_0]" - % (input_intf_name, input_intf_name) + "set_property name %s [get_bd_ports %s_0]" % (input_intf_name, input_intf_name) ) def insert_signature(self, checksum_count): @@ -267,12 +254,10 @@ def insert_signature(self, checksum_count): ) # set clk and reset self.connect_cmds.append( - "connect_bd_net [get_bd_ports ap_clk] [get_bd_pins %s/ap_clk]" - % signature_name + "connect_bd_net [get_bd_ports ap_clk] [get_bd_pins %s/ap_clk]" % signature_name ) self.connect_cmds.append( - "connect_bd_net [get_bd_ports ap_rst_n] [get_bd_pins %s/ap_rst_n]" - % signature_name + "connect_bd_net [get_bd_ports ap_rst_n] [get_bd_pins %s/ap_rst_n]" % signature_name ) fclk_mhz = 1 / (self.clk_ns * 0.001) fclk_hz = fclk_mhz * 1000000 @@ -290,9 +275,7 @@ def insert_signature(self, checksum_count): self.connect_cmds.append( "make_bd_intf_pins_external [get_bd_intf_pins %s/s_axi]" % signature_name ) - self.connect_cmds.append( - "set_property name s_axilite_info [get_bd_intf_ports s_axi_0]" - ) + self.connect_cmds.append("set_property name s_axilite_info [get_bd_intf_ports s_axi_0]") self.connect_cmds.append("assign_bd_address") def apply(self, model): @@ -320,9 +303,7 @@ def apply(self, model): ) for node in model.graph.node: # ensure that all nodes are fpgadataflow, and that IPs are generated - assert is_fpgadataflow_node( - node - ), "All nodes must be FINN fpgadataflow nodes." + assert is_fpgadataflow_node(node), "All nodes must be FINN fpgadataflow nodes." node_inst = getCustomOp(node) ip_dir_value = node_inst.get_nodeattr("ip_path") assert os.path.isdir(ip_dir_value), "IP generation directory doesn't exist." @@ -337,12 +318,10 @@ def apply(self, model): if producer is None: continue j = list(producer.output).index(node.input[i]) - src_intf_name = getCustomOp( - producer - ).get_verilog_top_module_intf_names()["m_axis"][j][0] - dst_intf_name = node_inst.get_verilog_top_module_intf_names()[ - "s_axis" - ][i][0] + src_intf_name = getCustomOp(producer).get_verilog_top_module_intf_names()[ + "m_axis" + ][j][0] + dst_intf_name = node_inst.get_verilog_top_module_intf_names()["s_axis"][i][0] self.connect_cmds.append( "connect_bd_intf_net [get_bd_intf_pins %s/%s] " "[get_bd_intf_pins %s/%s]" @@ -382,8 +361,7 @@ def apply(self, model): tcl = [] # create vivado project tcl.append( - "create_project %s %s -part %s" - % (prjname, vivado_stitch_proj_dir, self.fpgapart) + "create_project %s %s -part %s" % (prjname, vivado_stitch_proj_dir, self.fpgapart) ) # no warnings on long module names tcl.append("set_msg_config -id {[BD 41-1753]} -suppress") @@ -399,9 +377,7 @@ def apply(self, model): fclk_mhz = 1 / (self.clk_ns * 0.001) fclk_hz = fclk_mhz * 1000000 model.set_metadata_prop("clk_ns", str(self.clk_ns)) - tcl.append( - "set_property CONFIG.FREQ_HZ %d [get_bd_ports /ap_clk]" % round(fclk_hz) - ) + tcl.append("set_property CONFIG.FREQ_HZ %d [get_bd_ports /ap_clk]" % round(fclk_hz)) tcl.append("validate_bd_design") tcl.append("save_bd_design") # create wrapper hdl (for rtlsim later on) @@ -419,8 +395,7 @@ def apply(self, model): # synthesize to DCP and export stub, DCP and constraints if self.vitis: tcl.append( - "set_property SYNTH_CHECKPOINT_MODE Hierarchical [ get_files %s ]" - % bd_filename + "set_property SYNTH_CHECKPOINT_MODE Hierarchical [ get_files %s ]" % bd_filename ) tcl.append( "set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} " @@ -472,16 +447,9 @@ def apply(self, model): # if targeting Vitis, add some properties to the IP if self.vitis: # replace source code with dcp - tcl.append( - "set_property sdx_kernel true [ipx::find_open_core %s]" % block_vlnv - ) - tcl.append( - "set_property sdx_kernel_type rtl [ipx::find_open_core %s]" % block_vlnv - ) - tcl.append( - "set_property supported_families { } [ipx::find_open_core %s]" - % block_vlnv - ) + tcl.append("set_property sdx_kernel true [ipx::find_open_core %s]" % block_vlnv) + tcl.append("set_property sdx_kernel_type rtl [ipx::find_open_core %s]" % block_vlnv) + tcl.append("set_property supported_families { } [ipx::find_open_core %s]" % block_vlnv) tcl.append( "set_property xpm_libraries {XPM_CDC XPM_MEMORY XPM_FIFO} " "[ipx::find_open_core %s]" % block_vlnv @@ -496,32 +464,20 @@ def apply(self, model): "ipx::remove_all_file " "[ipx::get_file_groups xilinx_anylanguagebehavioralsimulation]" ) - tcl.append( - "ipx::remove_all_file " - "[ipx::get_file_groups xilinx_anylanguagesynthesis]" - ) + tcl.append("ipx::remove_all_file " "[ipx::get_file_groups xilinx_anylanguagesynthesis]") tcl.append( "ipx::remove_file_group " "xilinx_anylanguagebehavioralsimulation [ipx::current_core]" ) - tcl.append( - "ipx::remove_file_group " - "xilinx_anylanguagesynthesis [ipx::current_core]" - ) + tcl.append("ipx::remove_file_group " "xilinx_anylanguagesynthesis [ipx::current_core]") # remove sim and src folders tcl.append("file delete -force %s/ip/sim" % vivado_stitch_proj_dir) tcl.append("file delete -force %s/ip/src" % vivado_stitch_proj_dir) # copy and add DCP, stub, and xdc tcl.append("file mkdir %s/ip/dcp" % vivado_stitch_proj_dir) tcl.append("file mkdir %s/ip/impl" % vivado_stitch_proj_dir) - tcl.append( - "file copy -force %s.dcp %s/ip/dcp" - % (block_name, vivado_stitch_proj_dir) - ) - tcl.append( - "file copy -force %s.xdc %s/ip/impl" - % (block_name, vivado_stitch_proj_dir) - ) + tcl.append("file copy -force %s.dcp %s/ip/dcp" % (block_name, vivado_stitch_proj_dir)) + tcl.append("file copy -force %s.xdc %s/ip/impl" % (block_name, vivado_stitch_proj_dir)) tcl.append("ipx::add_file_group xilinx_implementation [ipx::current_core]") tcl.append( "ipx::add_file impl/%s.xdc [ipx::get_file_groups xilinx_implementation]" @@ -532,16 +488,12 @@ def apply(self, model): "[ipx::get_files impl/%s.xdc " "-of_objects [ipx::get_file_groups xilinx_implementation]]" % block_name ) - tcl.append( - "ipx::add_file_group " "xilinx_synthesischeckpoint [ipx::current_core]" - ) + tcl.append("ipx::add_file_group " "xilinx_synthesischeckpoint [ipx::current_core]") tcl.append( "ipx::add_file dcp/%s.dcp " "[ipx::get_file_groups xilinx_synthesischeckpoint]" % block_name ) - tcl.append( - "ipx::add_file_group xilinx_simulationcheckpoint [ipx::current_core]" - ) + tcl.append("ipx::add_file_group xilinx_simulationcheckpoint [ipx::current_core]") tcl.append( "ipx::add_file dcp/%s.dcp " "[ipx::get_file_groups xilinx_simulationcheckpoint]" % block_name diff --git a/src/finn/transformation/fpgadataflow/derive_characteristic.py b/src/finn/transformation/fpgadataflow/derive_characteristic.py index 67eb96995e..dc660f5fba 100644 --- a/src/finn/transformation/fpgadataflow/derive_characteristic.py +++ b/src/finn/transformation/fpgadataflow/derive_characteristic.py @@ -65,9 +65,7 @@ def applyNodeLocal(self, node): inst.derive_characteristic_fxns(period=self.period) except KeyError: # exception if op_type is not supported - raise Exception( - "Custom op_type %s is currently not supported." % op_type - ) + raise Exception("Custom op_type %s is currently not supported." % op_type) return (node, False) def apply(self, model: ModelWrapper): @@ -103,24 +101,16 @@ def apply(self, model: ModelWrapper): # for DuplicateStreams, use comp_branch_first's input characterization # for AddStreams, use comp_branch_last's output characterization period = comp_branch_first.get_nodeattr("io_chrc_period") - comp_branch_first_f = comp_branch_first.get_nodeattr("io_characteristic")[ - : 2 * period - ] - comp_branch_last_f = comp_branch_last.get_nodeattr("io_characteristic")[ - 2 * period : - ] + comp_branch_first_f = comp_branch_first.get_nodeattr("io_characteristic")[: 2 * period] + comp_branch_last_f = comp_branch_last.get_nodeattr("io_characteristic")[2 * period :] ds_node_inst = registry.getCustomOp(ds_node) addstrm_node_inst = registry.getCustomOp(addstrm_node) ds_node_inst.set_nodeattr("io_chrc_period", period) ds_node_inst.set_nodeattr("io_characteristic", comp_branch_first_f * 2) addstrm_node_inst.set_nodeattr("io_chrc_period", period) addstrm_node_inst.set_nodeattr("io_characteristic", comp_branch_last_f * 2) - warnings.warn( - f"Set {ds_node.name} chrc. from {comp_branch_first.onnx_node.name}" - ) - warnings.warn( - f"Set {addstrm_node.name} chrc. from {comp_branch_last.onnx_node.name}" - ) + warnings.warn(f"Set {ds_node.name} chrc. from {comp_branch_first.onnx_node.name}") + warnings.warn(f"Set {addstrm_node.name} chrc. from {comp_branch_last.onnx_node.name}") return (model, run_again) @@ -147,9 +137,7 @@ def applyNodeLocal(self, node): assert op_type != "StreamingFIFO", "Found existing FIFOs" period = prod.get_nodeattr("io_chrc_period") prod_chrc = prod.get_nodeattr("io_chrc_out")[0] - assert ( - len(prod_chrc) == 2 * period - ), "Found unexpected characterization attribute" + assert len(prod_chrc) == 2 * period, "Found unexpected characterization attribute" if any([x > 2 for x in prod.get_nodeattr("outFIFODepths")]): # FIFO depth already set, can skip this node return (node, False) @@ -186,14 +174,12 @@ def applyNodeLocal(self, node): # finally, check node inputs to ensure FIFOs are added to # any top-level inputs (at least self.io_fifo_depth deep) in_fifo_depths = prod.get_nodeattr("inFIFODepths") - for (i, input_name) in enumerate(node.input): + for i, input_name in enumerate(node.input): if input_name in [x.name for x in model.graph.input]: in_fifo_depths[i] = max(self.io_fifo_depth, in_fifo_depths[i]) prod.set_nodeattr("inFIFODepths", in_fifo_depths) except KeyError: # exception if op_type is not supported - raise Exception( - "Custom op_type %s is currently not supported." % op_type - ) + raise Exception("Custom op_type %s is currently not supported." % op_type) return (node, False) diff --git a/src/finn/transformation/fpgadataflow/externalize_params.py b/src/finn/transformation/fpgadataflow/externalize_params.py index 732b82c675..633db0c553 100644 --- a/src/finn/transformation/fpgadataflow/externalize_params.py +++ b/src/finn/transformation/fpgadataflow/externalize_params.py @@ -64,11 +64,7 @@ def filter_fc_extw(x): assert iodma_init is not None # remove output-side initializer to get correct dataflow partitioning model.graph.initializer.remove( - [ - x - for x in model.graph.initializer - if x.name == extw_tensor_name_out - ][0] + [x for x in model.graph.initializer if x.name == extw_tensor_name_out][0] ) graph_modified = True diff --git a/src/finn/transformation/fpgadataflow/floorplan.py b/src/finn/transformation/fpgadataflow/floorplan.py index 549b94d9f2..d43aabcf55 100644 --- a/src/finn/transformation/fpgadataflow/floorplan.py +++ b/src/finn/transformation/fpgadataflow/floorplan.py @@ -56,7 +56,6 @@ def __init__(self, floorplan=None): self.user_floorplan = floorplan def apply(self, model): - # read in a user-specified floorplan or generate a default one if self.user_floorplan is None: self.user_floorplan = model.analysis(floorplan_params) @@ -129,9 +128,7 @@ def apply(self, model): non_dma_nodes, ) ) - non_dma_nodes = list( - filter(lambda x: x not in dyn_tlastmarker_nodes, non_dma_nodes) - ) + non_dma_nodes = list(filter(lambda x: x not in dyn_tlastmarker_nodes, non_dma_nodes)) for node in dma_nodes: node_inst = getCustomOp(node) @@ -166,9 +163,7 @@ def apply(self, model): pre_inst = getCustomOp(pre_node) pre_slr = pre_inst.get_nodeattr("slr") if node_slr == pre_slr: - axilite_intf_name = pre_inst.get_verilog_top_module_intf_names()[ - "axilite" - ] + axilite_intf_name = pre_inst.get_verilog_top_module_intf_names()["axilite"] if len(axilite_intf_name) != 0: node_inst.set_nodeattr("partition_id", partition_cnt) partition_cnt += 1 diff --git a/src/finn/transformation/fpgadataflow/hlssynth_ip.py b/src/finn/transformation/fpgadataflow/hlssynth_ip.py index c091dbd5ed..08069fa00f 100644 --- a/src/finn/transformation/fpgadataflow/hlssynth_ip.py +++ b/src/finn/transformation/fpgadataflow/hlssynth_ip.py @@ -64,11 +64,9 @@ def applyNodeLocal(self, node): ), """Node attribute "code_gen_dir_ipgen" is empty. Please run transformation PrepareIP first.""" - if not os.path.isdir( - inst.get_nodeattr("ipgen_path") - ) or not inst.get_nodeattr("code_gen_dir_ipgen") in inst.get_nodeattr( - "ipgen_path" - ): + if not os.path.isdir(inst.get_nodeattr("ipgen_path")) or not inst.get_nodeattr( + "code_gen_dir_ipgen" + ) in inst.get_nodeattr("ipgen_path"): # call the compilation function for this node inst.ipgen_singlenode_code() else: @@ -81,7 +79,5 @@ def applyNodeLocal(self, node): is empty.""" except KeyError: # exception if op_type is not supported - raise Exception( - "Custom op_type %s is currently not supported." % op_type - ) + raise Exception("Custom op_type %s is currently not supported." % op_type) return (node, False) diff --git a/src/finn/transformation/fpgadataflow/insert_dwc.py b/src/finn/transformation/fpgadataflow/insert_dwc.py index cff8b60267..140d154b1a 100644 --- a/src/finn/transformation/fpgadataflow/insert_dwc.py +++ b/src/finn/transformation/fpgadataflow/insert_dwc.py @@ -48,8 +48,7 @@ def apply(self, model): if consumers == []: continue assert len(consumers) == 1, ( - n.name - + ": HLS node with fan-out higher than 1 cannot be stitched" + n.name + ": HLS node with fan-out higher than 1 cannot be stitched" ) consumer = consumers[0] if _suitable_node(consumer) is True: diff --git a/src/finn/transformation/fpgadataflow/insert_fifo.py b/src/finn/transformation/fpgadataflow/insert_fifo.py index bfeee95e9b..f57c9e41b7 100644 --- a/src/finn/transformation/fpgadataflow/insert_fifo.py +++ b/src/finn/transformation/fpgadataflow/insert_fifo.py @@ -85,9 +85,7 @@ class InsertFIFO(Transformation): The other node attributes necessary to create a FIFO node are taken from the node the FIFO node is inserted after: 'folded_shape' and 'dtype'""" - def __init__( - self, create_shallow_fifos=False, max_qsrl_depth=None, vivado_ram_style="auto" - ): + def __init__(self, create_shallow_fifos=False, max_qsrl_depth=None, vivado_ram_style="auto"): super().__init__() self.create_shallow_fifos = create_shallow_fifos self.max_qsrl_depth = max_qsrl_depth @@ -151,10 +149,7 @@ def apply(self, model): graph.value_info.append(fifo_output_tensor) model.set_tensor_datatype(fifo_output_tensor.name, dtype) - if ( - self.max_qsrl_depth is None - or fifo_depth <= self.max_qsrl_depth - ): + if self.max_qsrl_depth is None or fifo_depth <= self.max_qsrl_depth: impl_style = "rtl" else: impl_style = "vivado" @@ -187,10 +182,7 @@ def apply(self, model): for graph_in_name in graph_in_names: first_node = model.find_consumer(graph_in_name) # insert FIFO as first node, except when first node is DMA - if ( - first_node.op_type != "StreamingFIFO" - and first_node.op_type != "IODMA" - ): + if first_node.op_type != "StreamingFIFO" and first_node.op_type != "IODMA": inp_ind = list(first_node.input).index(graph_in_name) n_input = first_node.input[inp_ind] n0 = getCustomOp(first_node) @@ -242,10 +234,7 @@ def apply(self, model): graph_out_names = [x.name for x in model.graph.output] for graph_out_name in graph_out_names: final_node = model.find_producer(graph_out_name) - if ( - final_node.op_type != "StreamingFIFO" - and final_node.op_type != "IODMA" - ): + if final_node.op_type != "StreamingFIFO" and final_node.op_type != "IODMA": assert ( final_node.op_type != "TLastMarker" ), """Insert tlast marker should be done diff --git a/src/finn/transformation/fpgadataflow/insert_hook.py b/src/finn/transformation/fpgadataflow/insert_hook.py index 21ec3f049f..14989efa75 100644 --- a/src/finn/transformation/fpgadataflow/insert_hook.py +++ b/src/finn/transformation/fpgadataflow/insert_hook.py @@ -74,8 +74,7 @@ def apply(self, model): for output_name in n.output: consumers = model.find_consumers(output_name) assert len(consumers) <= 1, ( - n.name - + ": HLS node with fan-out higher than 1 cannot be stitched" + n.name + ": HLS node with fan-out higher than 1 cannot be stitched" ) n0 = getCustomOp(n) n0_hook = n0.get_nodeattr("output_hook") diff --git a/src/finn/transformation/fpgadataflow/insert_iodma.py b/src/finn/transformation/fpgadataflow/insert_iodma.py index 28bcd9598a..90700d5726 100644 --- a/src/finn/transformation/fpgadataflow/insert_iodma.py +++ b/src/finn/transformation/fpgadataflow/insert_iodma.py @@ -51,9 +51,7 @@ def __init__( self.insert_input = insert_input self.insert_output = insert_output self.insert_extmemw = insert_extmemw - assert ( - 2 ** math.log2(max_intfwidth) == max_intfwidth - ), "max_intfwidth must be a power of 2" + assert 2 ** math.log2(max_intfwidth) == max_intfwidth, "max_intfwidth must be a power of 2" self.max_intfwidth = max_intfwidth def get_mem_init(self, weights, pe, simd): @@ -122,13 +120,9 @@ def apply(self, model): padded_instream_width = first_node_inst.get_instream_width_padded() padded_instream_bytes = padded_instream_width // 8 # determine the feasible interface width - transfer_bits = padded_instream_width * np.prod( - in_folded_shape[:-1] - ) + transfer_bits = padded_instream_width * np.prod(in_folded_shape[:-1]) intfwidth = math.gcd(transfer_bits, self.max_intfwidth) - assert ( - intfwidth % 8 == 0 - ), "No feasible interface width for transfer size" + assert intfwidth % 8 == 0, "No feasible interface width for transfer size" # make new buffer first_node_in = oh.make_tensor_value_info( model.make_new_valueinfo_name(), TensorProto.FLOAT, in_shape @@ -169,18 +163,12 @@ def apply(self, model): # take advantage of AXI stream width padding for DMA alignment # (AXI streams are always padded to 8 bits) # this is the width of stream input to DMA - padded_outstream_width = ( - final_node_inst.get_outstream_width_padded() - ) + padded_outstream_width = final_node_inst.get_outstream_width_padded() padded_outstream_bytes = padded_outstream_width // 8 # determine the feasible interface width - transfer_bits = padded_outstream_width * np.prod( - out_folded_shape[:-1] - ) + transfer_bits = padded_outstream_width * np.prod(out_folded_shape[:-1]) intfwidth = math.gcd(transfer_bits, self.max_intfwidth) - assert ( - intfwidth % 8 == 0 - ), "No feasible interface width for transfer size" + assert intfwidth % 8 == 0, "No feasible interface width for transfer size" # make new buffer final_node_out = oh.make_tensor_value_info( model.make_new_valueinfo_name(), TensorProto.FLOAT, out_shape @@ -211,8 +199,7 @@ def apply(self, model): # attached IODMA fc_extw_nodes = list( filter( - lambda x: x.op_type - in ["MatrixVectorActivation", "VectorVectorActivation"] + lambda x: x.op_type in ["MatrixVectorActivation", "VectorVectorActivation"] and getCustomOp(x).get_nodeattr("mem_mode") == "external" and model.find_producer(x.input[1]) is None, all_nodes, @@ -226,9 +213,7 @@ def apply(self, model): # determine the feasible interface width transfer_bits = np.prod(w_shape) * w_dtype.bitwidth() intfwidth = math.gcd(transfer_bits, self.max_intfwidth) - assert ( - intfwidth % 8 == 0 - ), "No feasible interface width for transfer size" + assert intfwidth % 8 == 0, "No feasible interface width for transfer size" # calculate width of stream output from DMA pe = get_by_name(fc_node.attribute, "PE").i simd = get_by_name(fc_node.attribute, "SIMD").i diff --git a/src/finn/transformation/fpgadataflow/insert_tlastmarker.py b/src/finn/transformation/fpgadataflow/insert_tlastmarker.py index 1610916eb6..94f0b0eae1 100644 --- a/src/finn/transformation/fpgadataflow/insert_tlastmarker.py +++ b/src/finn/transformation/fpgadataflow/insert_tlastmarker.py @@ -54,10 +54,8 @@ def apply(self, model): graph_modified = False if final_node.op_type != "TLastMarker" and not ( final_node.op_type == "IODMA" - and get_by_name(final_node.attribute, "direction").s.decode("UTF-8") - == "out" + and get_by_name(final_node.attribute, "direction").s.decode("UTF-8") == "out" ): - custom_op = getCustomOp(final_node) num_iters = int(custom_op.get_number_output_values()) stream_width = int(custom_op.get_outstream_width()) @@ -113,18 +111,13 @@ def apply(self, model): # 2. node is either a TLastMarker or an input IODMA if first_node.op_type != "TLastMarker" and not ( first_node.op_type == "IODMA" - and get_by_name(first_node.attribute, "direction").s.decode("UTF-8") - == "in" + and get_by_name(first_node.attribute, "direction").s.decode("UTF-8") == "in" ): - custom_op = getCustomOp(first_node) num_iters = np.prod(custom_op.get_folded_input_shape()[1:-1]) inp_idx = list(first_node.input).index(graph_in_name) if inp_idx > 0: - if ( - first_node.op_type == "MatrixVectorActivation" - and inp_idx == 1 - ): + if first_node.op_type == "MatrixVectorActivation" and inp_idx == 1: stream_width = int(custom_op.get_weightstream_width()) elif first_node.op_type == "AddStreams_Batch" and inp_idx == 1: stream_width = int(custom_op.get_instream_width()) diff --git a/src/finn/transformation/fpgadataflow/make_pynq_driver.py b/src/finn/transformation/fpgadataflow/make_pynq_driver.py index dce98e54a3..5a0e47c130 100644 --- a/src/finn/transformation/fpgadataflow/make_pynq_driver.py +++ b/src/finn/transformation/fpgadataflow/make_pynq_driver.py @@ -56,14 +56,10 @@ def to_external_tensor(init, w_dtype): weight_width = init.shape[1] * w_dtype.bitwidth() weight_width_padded = roundup_to_integer_multiple(weight_width, 4) - hex_init = pack_innermost_dim_as_hex_string( - init, w_dtype, weight_width_padded, prefix="0x" - ) + hex_init = pack_innermost_dim_as_hex_string(init, w_dtype, weight_width_padded, prefix="0x") ext_weight = np.array([], dtype=np.uint8) for line in hex_init: - array_line = [ - x for x in reversed(hexstring2npbytearray(line, remove_prefix="0x")) - ] + array_line = [x for x in reversed(hexstring2npbytearray(line, remove_prefix="0x"))] ext_weight = np.append(ext_weight, array_line) return ext_weight @@ -88,7 +84,6 @@ def __init__(self, platform): self.platform = platform def apply(self, model): - # create a temporary folder for the generated driver pynq_driver_dir = make_build_dir(prefix="pynq_driver_") model.set_metadata_prop("pynq_driver_dir", pynq_driver_dir) @@ -115,9 +110,7 @@ def apply(self, model): files_to_copy.append( (qonnx_path + "/core/__init__.py", qonnx_target_path + "/core/__init__.py") ) - files_to_copy.append( - (qonnx_path + "/util/basic.py", qonnx_target_path + "/util/basic.py") - ) + files_to_copy.append((qonnx_path + "/util/basic.py", qonnx_target_path + "/util/basic.py")) files_to_copy.append( (qonnx_path + "/util/__init__.py", qonnx_target_path + "/util/__init__.py") ) @@ -133,7 +126,7 @@ def apply(self, model): finn_target_path + "/util/__init__.py", ) ) - for (src_file, target_file) in files_to_copy: + for src_file, target_file in files_to_copy: shutil.copy(src_file, target_file) # extract input-output shapes from the graph # TODO convert this to an analysis pass? @@ -165,13 +158,9 @@ def apply(self, model): first_node = successor_df_model.find_consumer( successor_df_model.graph.input[successor_input_num].name ) - i_tensor_shape_folded = tuple( - getCustomOp(first_node).get_folded_input_shape() - ) + i_tensor_shape_folded = tuple(getCustomOp(first_node).get_folded_input_shape()) # generate dummy folded i/o tensors and their packed versions - i_tensor_dummy_folded = gen_finn_dt_tensor( - i_tensor_dt, i_tensor_shape_folded - ) + i_tensor_dummy_folded = gen_finn_dt_tensor(i_tensor_dt, i_tensor_shape_folded) i_tensor_dummy_packed = dpk.finnpy_to_packed_bytearray( i_tensor_dummy_folded, i_tensor_dt ) @@ -201,24 +190,16 @@ def apply(self, model): ), """ Ensure CreateDataflowPartition called before driver creation.""" df_model = ModelWrapper(getCustomOp(o_producer).get_nodeattr("model")) - assert ( - df_model.graph.node[-1].op_type == "IODMA" - ), "Partition must hold output IODMA" + assert df_model.graph.node[-1].op_type == "IODMA", "Partition must hold output IODMA" predecessors = model.find_direct_predecessors(o_producer) - predecessor_output_num = list(predecessors[0].output).index( - o_producer.input[0] - ) + predecessor_output_num = list(predecessors[0].output).index(o_producer.input[0]) predecessor_sdp = getCustomOp(predecessors[0]) predecessor_df_model = ModelWrapper(predecessor_sdp.get_nodeattr("model")) last_node = predecessor_df_model.find_producer( predecessor_df_model.graph.output[predecessor_output_num].name ) - o_tensor_shape_folded = tuple( - getCustomOp(last_node).get_folded_output_shape() - ) - o_tensor_dummy_folded = gen_finn_dt_tensor( - o_tensor_dt, o_tensor_shape_folded - ) + o_tensor_shape_folded = tuple(getCustomOp(last_node).get_folded_output_shape()) + o_tensor_dummy_folded = gen_finn_dt_tensor(o_tensor_dt, o_tensor_shape_folded) o_tensor_dummy_packed = dpk.finnpy_to_packed_bytearray( o_tensor_dummy_folded, o_tensor_dt ) @@ -256,17 +237,11 @@ def apply(self, model): assert df_model.graph.node[0].op_type == "IODMA" iodma_node = getCustomOp(df_model.graph.node[0]) if iodma_node.get_nodeattr("burstMode") == "wrap": # input weights dma? - init_tensor = df_model.get_initializer( - iodma_node.onnx_node.input[0] - ) + init_tensor = df_model.get_initializer(iodma_node.onnx_node.input[0]) ext_weight_dma_cnt += 1 - w_dtype = df_model.get_tensor_datatype( - iodma_node.onnx_node.input[0] - ) + w_dtype = df_model.get_tensor_datatype(iodma_node.onnx_node.input[0]) init_external_tensor = to_external_tensor(init_tensor, w_dtype) - np.save( - weights_dir + "/" + idma_name + ".npy", init_external_tensor - ) + np.save(weights_dir + "/" + idma_name + ".npy", init_external_tensor) idma_idx += 1 # fill in the driver template @@ -293,9 +268,7 @@ def apply(self, model): # add validate.py to run full top-1 test (only for suitable networks) validate_py = pynq_driver_dir + "/validate.py" - validate_template = pk.resource_filename( - "finn.qnn-data", "templates/driver/validate.py" - ) + validate_template = pk.resource_filename("finn.qnn-data", "templates/driver/validate.py") shutil.copy(validate_template, validate_py) # generate weight files for runtime-writable layers @@ -318,9 +291,7 @@ def apply(self, model): rt_layer_ind, node.name, ) - node_inst.make_weight_file( - fcl_w, "decoupled_runtime", w_filename - ) + node_inst.make_weight_file(fcl_w, "decoupled_runtime", w_filename) rt_layer_ind += 1 elif node.op_type == "StreamingDataflowPartition": warnings.warn( diff --git a/src/finn/transformation/fpgadataflow/make_zynq_proj.py b/src/finn/transformation/fpgadataflow/make_zynq_proj.py index f48566326e..989eb62a88 100644 --- a/src/finn/transformation/fpgadataflow/make_zynq_proj.py +++ b/src/finn/transformation/fpgadataflow/make_zynq_proj.py @@ -92,7 +92,6 @@ def __init__(self, platform, enable_debug=False): self.enable_debug = 1 if enable_debug else 0 def apply(self, model): - # create a config file and empty list of xo files config = [] idma_idx = 0 @@ -110,15 +109,12 @@ def apply(self, model): ipstitch_path = kernel_model.get_metadata_prop("vivado_stitch_proj") if ipstitch_path is None or (not os.path.isdir(ipstitch_path)): raise Exception( - "No stitched IPI design found for %s, apply CreateStitchedIP first." - % node.name + "No stitched IPI design found for %s, apply CreateStitchedIP first." % node.name ) vivado_stitch_vlnv = kernel_model.get_metadata_prop("vivado_stitch_vlnv") if vivado_stitch_vlnv is None: - raise Exception( - "No vlnv found for %s, apply CreateStitchedIP first." % node.name - ) + raise Exception("No vlnv found for %s, apply CreateStitchedIP first." % node.name) ip_dirs = ["list"] ip_dirs += collect_ip_dirs(kernel_model, ipstitch_path) @@ -170,9 +166,7 @@ def apply(self, model): "[get_bd_intf_pins smartconnect_0/S%02d_AXI]" % (instance_names[node.name], aximm_idx) ) - assert ( - len(ifnames["axilite"]) == 1 - ), "Must have 1 AXI lite interface on IODMA nodes" + assert len(ifnames["axilite"]) == 1, "Must have 1 AXI lite interface on IODMA nodes" axilite_intf_name = ifnames["axilite"][0] assert axilite_intf_name is not None config.append( @@ -182,8 +176,7 @@ def apply(self, model): ) # assign_bd_address with appropriate range/offset config.append( - "assign_axi_addr_proc %s/%s" - % (instance_names[node.name], axilite_intf_name) + "assign_axi_addr_proc %s/%s" % (instance_names[node.name], axilite_intf_name) ) aximm_idx += 1 @@ -269,23 +262,18 @@ def apply(self, model): bash_command = ["bash", synth_project_sh] process_compile = subprocess.Popen(bash_command, stdout=subprocess.PIPE) process_compile.communicate() - bitfile_name = ( - vivado_pynq_proj_dir + "/finn_zynq_link.runs/impl_1/top_wrapper.bit" - ) + bitfile_name = vivado_pynq_proj_dir + "/finn_zynq_link.runs/impl_1/top_wrapper.bit" if not os.path.isfile(bitfile_name): raise Exception( - "Synthesis failed, no bitfile found. Check logs under %s" - % vivado_pynq_proj_dir + "Synthesis failed, no bitfile found. Check logs under %s" % vivado_pynq_proj_dir ) deploy_bitfile_name = vivado_pynq_proj_dir + "/resizer.bit" copy(bitfile_name, deploy_bitfile_name) # set bitfile attribute model.set_metadata_prop("bitfile", deploy_bitfile_name) hwh_name_alts = [ - vivado_pynq_proj_dir - + "/finn_zynq_link.srcs/sources_1/bd/top/hw_handoff/top.hwh", - vivado_pynq_proj_dir - + "/finn_zynq_link.gen/sources_1/bd/top/hw_handoff/top.hwh", + vivado_pynq_proj_dir + "/finn_zynq_link.srcs/sources_1/bd/top/hw_handoff/top.hwh", + vivado_pynq_proj_dir + "/finn_zynq_link.gen/sources_1/bd/top/hw_handoff/top.hwh", ] hwh_name = None for hwh_name_cand in hwh_name_alts: @@ -293,8 +281,7 @@ def apply(self, model): hwh_name = hwh_name_cand if not os.path.isfile(hwh_name): raise Exception( - "Synthesis failed, no bitfile found. Check logs under %s" - % vivado_pynq_proj_dir + "Synthesis failed, no bitfile found. Check logs under %s" % vivado_pynq_proj_dir ) deploy_hwh_name = vivado_pynq_proj_dir + "/resizer.hwh" copy(hwh_name, deploy_hwh_name) @@ -350,21 +337,15 @@ def apply(self, model): kernel_model = kernel_model.transform(InsertFIFO()) kernel_model = kernel_model.transform(GiveUniqueNodeNames(prefix)) kernel_model.save(dataflow_model_filename) - kernel_model = kernel_model.transform( - PrepareIP(self.fpga_part, self.period_ns) - ) + kernel_model = kernel_model.transform(PrepareIP(self.fpga_part, self.period_ns)) kernel_model = kernel_model.transform(HLSSynthIP()) kernel_model = kernel_model.transform( - CreateStitchedIP( - self.fpga_part, self.period_ns, sdp_node.onnx_node.name, False - ) + CreateStitchedIP(self.fpga_part, self.period_ns, sdp_node.onnx_node.name, False) ) kernel_model.set_metadata_prop("platform", "zynq-iodma") kernel_model.save(dataflow_model_filename) # Assemble design from IPs - model = model.transform( - MakeZYNQProject(self.platform, enable_debug=self.enable_debug) - ) + model = model.transform(MakeZYNQProject(self.platform, enable_debug=self.enable_debug)) # set platform attribute for correct remote execution model.set_metadata_prop("platform", "zynq-iodma") diff --git a/src/finn/transformation/fpgadataflow/prepare_cppsim.py b/src/finn/transformation/fpgadataflow/prepare_cppsim.py index 07021c1e8d..76c3f88310 100644 --- a/src/finn/transformation/fpgadataflow/prepare_cppsim.py +++ b/src/finn/transformation/fpgadataflow/prepare_cppsim.py @@ -49,9 +49,7 @@ def _codegen_single_node(node, model): code_gen_dir = inst.get_nodeattr("code_gen_dir_cppsim") # ensure that there is a directory if code_gen_dir == "" or not os.path.isdir(code_gen_dir): - code_gen_dir = make_build_dir( - prefix="code_gen_cppsim_" + str(node.name) + "_" - ) + code_gen_dir = make_build_dir(prefix="code_gen_cppsim_" + str(node.name) + "_") inst.set_nodeattr("code_gen_dir_cppsim", code_gen_dir) # ensure that there is generated code inside the dir inst.code_generation_cppsim(model) diff --git a/src/finn/transformation/fpgadataflow/prepare_ip.py b/src/finn/transformation/fpgadataflow/prepare_ip.py index 2ebd6310f0..5461bbd77c 100644 --- a/src/finn/transformation/fpgadataflow/prepare_ip.py +++ b/src/finn/transformation/fpgadataflow/prepare_ip.py @@ -47,9 +47,7 @@ def _codegen_single_node(node, model, fpgapart, clk): code_gen_dir = inst.get_nodeattr("code_gen_dir_ipgen") # ensure that there is a directory if code_gen_dir == "" or not os.path.isdir(code_gen_dir): - code_gen_dir = make_build_dir( - prefix="code_gen_ipgen_" + str(node.name) + "_" - ) + code_gen_dir = make_build_dir(prefix="code_gen_ipgen_" + str(node.name) + "_") inst.set_nodeattr("code_gen_dir_ipgen", code_gen_dir) # ensure that there is generated code inside the dir inst.code_generation_ipgen(model, fpgapart, clk) diff --git a/src/finn/transformation/fpgadataflow/prepare_rtlsim.py b/src/finn/transformation/fpgadataflow/prepare_rtlsim.py index 645d86cf14..8ba7cfd965 100644 --- a/src/finn/transformation/fpgadataflow/prepare_rtlsim.py +++ b/src/finn/transformation/fpgadataflow/prepare_rtlsim.py @@ -74,7 +74,5 @@ def applyNodeLocal(self, node): ), "Failed to prepare RTLSim, no rtlsim_so attribute found." except KeyError: # exception if op_type is not supported - raise Exception( - "Custom op_type %s is currently not supported." % op_type - ) + raise Exception("Custom op_type %s is currently not supported." % op_type) return (node, False) diff --git a/src/finn/transformation/fpgadataflow/set_exec_mode.py b/src/finn/transformation/fpgadataflow/set_exec_mode.py index a08d153cb2..8488b4ef83 100644 --- a/src/finn/transformation/fpgadataflow/set_exec_mode.py +++ b/src/finn/transformation/fpgadataflow/set_exec_mode.py @@ -56,7 +56,5 @@ def apply(self, model): was not successful. Node attribute "exec_mode" is not set""" except KeyError: # exception if op_type is not supported - raise Exception( - "Custom op_type %s is currently not supported." % op_type - ) + raise Exception("Custom op_type %s is currently not supported." % op_type) return (model, False) diff --git a/src/finn/transformation/fpgadataflow/set_fifo_depths.py b/src/finn/transformation/fpgadataflow/set_fifo_depths.py index 35e7b9e6c9..da6099ab9a 100644 --- a/src/finn/transformation/fpgadataflow/set_fifo_depths.py +++ b/src/finn/transformation/fpgadataflow/set_fifo_depths.py @@ -262,9 +262,7 @@ def apply(self, model): modified_fc_nodes = [] for node in model.graph.node: # verify assumptions - assert is_fpgadataflow_node(node), "Found non-fpgadataflow node: " + str( - node - ) + assert is_fpgadataflow_node(node), "Found non-fpgadataflow node: " + str(node) assert node.op_type != "StreamingFIFO", "Found existing StreamingFIFO node" node = getCustomOp(node) ifd = node.get_nodeattr("inFIFODepths") @@ -289,8 +287,7 @@ def apply(self, model): node.set_nodeattr("mem_mode", "decoupled") reset_implementation(node) warnings.warn( - "Changed mem_mode from external to decoupled for " - + node.onnx_node.name + "Changed mem_mode from external to decoupled for " + node.onnx_node.name ) # insert stream infrastructure (DWC/FIFO) @@ -308,9 +305,7 @@ def apply(self, model): node.set_nodeattr("depth_monitor", 1) node.set_nodeattr("impl_style", "rtl") # check depths and fix as necessary - if (self.max_depth is not None) and ( - node.get_nodeattr("depth") != self.max_depth - ): + if (self.max_depth is not None) and (node.get_nodeattr("depth") != self.max_depth): node.set_nodeattr("depth", self.max_depth) # insert FIFOs and do all transformations for RTLsim @@ -373,15 +368,11 @@ def apply(self, model): ncycles = ncycles - 1 if not output_detected: - warnings.warn( - "No output detected, calculated FIFO depths may not be correct" - ) + warnings.warn("No output detected, calculated FIFO depths may not be correct") else: # do rtlsim in C++ for FIFO sizing # determine # inputs for FIFO sizing according to topology type - swg_nodes = [ - x for x in model.graph.node if "ConvolutionInputGenerator" in x.op_type - ] + swg_nodes = [x for x in model.graph.node if "ConvolutionInputGenerator" in x.op_type] if len(swg_nodes) == 0: # MLP, no layer overlap # assuming half the nodes are now FIFOs, use half the # of @@ -443,9 +434,7 @@ def apply(self, model): # handle custom sizing for SWG FIFOs if desired if self.swg_exception: - model = model.transform( - CapConvolutionFIFODepths(max_qsrl_depth=self.max_qsrl_depth) - ) + model = model.transform(CapConvolutionFIFODepths(max_qsrl_depth=self.max_qsrl_depth)) # remove shallow FIFOs model = model.transform(RemoveShallowFIFOs()) @@ -575,9 +564,7 @@ def apply(self, model): if node.op_type == "StreamingFIFO": n_inst = getCustomOp(node) depth = n_inst.get_nodeattr("depth") - cfgs = get_fifo_split_configs( - depth, self.max_qsrl_depth, self.max_vivado_depth - ) + cfgs = get_fifo_split_configs(depth, self.max_qsrl_depth, self.max_vivado_depth) if len(cfgs) > 1: fld_shape = n_inst.get_folded_output_shape() dtype = n_inst.get_nodeattr("dataType") diff --git a/src/finn/transformation/fpgadataflow/set_folding.py b/src/finn/transformation/fpgadataflow/set_folding.py index 0a466afe13..eca1053f8f 100644 --- a/src/finn/transformation/fpgadataflow/set_folding.py +++ b/src/finn/transformation/fpgadataflow/set_folding.py @@ -80,9 +80,7 @@ class SetFolding(Transformation): unfolded before SIMD is increased """ - def __init__( - self, target_cycles_per_frame=1000, mvau_wwidth_max=36, two_pass_relaxation=True - ): + def __init__(self, target_cycles_per_frame=1000, mvau_wwidth_max=36, two_pass_relaxation=True): super().__init__() self.target_cycles_per_frame = target_cycles_per_frame self.mvau_wwidth_max = mvau_wwidth_max @@ -142,8 +140,7 @@ def apply(self, model): # finish if target met break if ( - node_inst.get_weight_datatype().bitwidth() - * node_inst.get_nodeattr("SIMD") + node_inst.get_weight_datatype().bitwidth() * node_inst.get_nodeattr("SIMD") > self.mvau_wwidth_max ): # revert if we've gone above width threshold @@ -196,9 +193,7 @@ def apply(self, model): else: raise Exception("Undefined edge case for %s" % op_type) if ksize != 1: # pointwise vvau/pool lack a SWU - raise Exception( - "Expected SWU on DW op input, found " + swu_node.op_type - ) + raise Exception("Expected SWU on DW op input, found " + swu_node.op_type) elif op_type in simd_ops: if op_type.startswith("ConvolutionInputGenerator"): depthwise = node_inst.get_nodeattr("depthwise") @@ -224,9 +219,7 @@ def apply(self, model): max_simd = node_inst.get_nodeattr("NumChannels") self.optimize_attribute_val(node_inst, max_simd, "SIMD") else: - warnings.warn( - "SetFolding doesn't know how to handle op_type " + op_type - ) + warnings.warn("SetFolding doesn't know how to handle op_type " + op_type) model = model.transform(GiveUniqueNodeNames()) model = model.transform(AnnotateCycles()) diff --git a/src/finn/transformation/fpgadataflow/vitis_build.py b/src/finn/transformation/fpgadataflow/vitis_build.py index e0a5666000..2fc0b2f3bb 100644 --- a/src/finn/transformation/fpgadataflow/vitis_build.py +++ b/src/finn/transformation/fpgadataflow/vitis_build.py @@ -56,9 +56,7 @@ def _check_vitis_envvars(): assert "VITIS_PATH" in os.environ, "VITIS_PATH must be set for Vitis" - assert ( - "PLATFORM_REPO_PATHS" in os.environ - ), "PLATFORM_REPO_PATHS must be set for Vitis" + assert "PLATFORM_REPO_PATHS" in os.environ, "PLATFORM_REPO_PATHS must be set for Vitis" assert ( "XILINX_XRT" in os.environ ), "XILINX_XRT must be set for Vitis, ensure the XRT env is sourced" @@ -97,9 +95,7 @@ def apply(self, model): # NOTE: this assumes the graph is Vitis-compatible: max one axi lite interface # developed from instructions in UG1393 (v2019.2) and package_xo documentation # package_xo is responsible for generating the kernel xml - assert ( - len(interfaces["axilite"]) <= 1 - ), "CreateVitisXO supports max 1 AXI lite interface" + assert len(interfaces["axilite"]) <= 1, "CreateVitisXO supports max 1 AXI lite interface" axilite_intf_name = None if len(interfaces["axilite"]) == 1: axilite_intf_name = interfaces["axilite"][0] @@ -114,14 +110,12 @@ def apply(self, model): ) arg_id += 1 args_string.append( - "{numReps:0:%s:%s:0x4:0x1C:uint:0}" - % (str(arg_id), axilite_intf_name) + "{numReps:0:%s:%s:0x4:0x1C:uint:0}" % (str(arg_id), axilite_intf_name) ) arg_id += 1 else: args_string.append( - "{numReps:0:%s:%s:0x4:0x10:uint:0}" - % (str(arg_id), axilite_intf_name) + "{numReps:0:%s:%s:0x4:0x10:uint:0}" % (str(arg_id), axilite_intf_name) ) arg_id += 1 for intf in interfaces["s_axis"] + interfaces["m_axis"]: @@ -139,9 +133,10 @@ def apply(self, model): model.set_metadata_prop("vitis_xo", xo_path) # generate the package_xo command in a tcl script - package_xo_string = ( - "package_xo -force -xo_path %s -kernel_name %s -ip_directory %s" - % (xo_path, self.ip_name, stitched_ip_dir) + package_xo_string = "package_xo -force -xo_path %s -kernel_name %s -ip_directory %s" % ( + xo_path, + self.ip_name, + stitched_ip_dir, ) for arg in args_string: package_xo_string += " -kernel_xml_args " + arg @@ -255,9 +250,7 @@ def apply(self, model): mem_type = "DDR" mem_idx = 1 node_mem_port = "%s[%d]" % (mem_type, mem_idx) - config.append( - "sp=%s.m_axi_gmem0:%s" % (instance_names[node.name], node_mem_port) - ) + config.append("sp=%s.m_axi_gmem0:%s" % (instance_names[node.name], node_mem_port)) # connect streams if producer is not None: for i in range(len(node.input)): @@ -281,14 +274,10 @@ def apply(self, model): # add Vivado physopt directives if desired if self.strategy == VitisOptStrategy.PERFORMANCE_BEST: config.append("[vivado]") - config.append( - "prop=run.impl_1.STEPS.OPT_DESIGN.ARGS.DIRECTIVE=ExploreWithRemap" - ) + config.append("prop=run.impl_1.STEPS.OPT_DESIGN.ARGS.DIRECTIVE=ExploreWithRemap") config.append("prop=run.impl_1.STEPS.PLACE_DESIGN.ARGS.DIRECTIVE=Explore") config.append("prop=run.impl_1.STEPS.PHYS_OPT_DESIGN.IS_ENABLED=true") - config.append( - "prop=run.impl_1.STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE=Explore" - ) + config.append("prop=run.impl_1.STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE=Explore") config.append("prop=run.impl_1.STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE=Explore") config = "\n".join(config) + "\n" @@ -341,9 +330,7 @@ def apply(self, model): with open(gen_rep_xml_sh, "w") as f: f.write("#!/bin/bash \n") f.write("cd {}\n".format(link_dir)) - f.write( - "vivado -mode batch -source %s\n" % (link_dir + "/gen_report_xml.tcl") - ) + f.write("vivado -mode batch -source %s\n" % (link_dir + "/gen_report_xml.tcl")) f.write("cd {}\n".format(working_dir)) bash_command = ["bash", gen_rep_xml_sh] process_genxml = subprocess.Popen(bash_command, stdout=subprocess.PIPE) @@ -419,18 +406,12 @@ def apply(self, model): kernel_model = kernel_model.transform(RemoveUnusedTensors()) kernel_model = kernel_model.transform(GiveUniqueNodeNames(prefix)) kernel_model.save(dataflow_model_filename) - kernel_model = kernel_model.transform( - PrepareIP(self.fpga_part, self.period_ns) - ) + kernel_model = kernel_model.transform(PrepareIP(self.fpga_part, self.period_ns)) kernel_model = kernel_model.transform(HLSSynthIP()) kernel_model = kernel_model.transform( - CreateStitchedIP( - self.fpga_part, self.period_ns, sdp_node.onnx_node.name, True - ) - ) - kernel_model = kernel_model.transform( - CreateVitisXO(sdp_node.onnx_node.name) + CreateStitchedIP(self.fpga_part, self.period_ns, sdp_node.onnx_node.name, True) ) + kernel_model = kernel_model.transform(CreateVitisXO(sdp_node.onnx_node.name)) kernel_model.set_metadata_prop("platform", "alveo") kernel_model.save(dataflow_model_filename) # Assemble design from kernels diff --git a/src/finn/transformation/move_reshape.py b/src/finn/transformation/move_reshape.py index cec04a182b..ed553e7cee 100644 --- a/src/finn/transformation/move_reshape.py +++ b/src/finn/transformation/move_reshape.py @@ -54,9 +54,7 @@ def apply(self, model): fc_inst = getCustomOp(consumer) mw = fc_inst.get_nodeattr("MW") mh = fc_inst.get_nodeattr("MH") - (b, h, w, c) = model.get_tensor_shape( - transp_node.input[0] - ) + (b, h, w, c) = model.get_tensor_shape(transp_node.input[0]) # absorb transpose into weight matrix, # allowing FC layer to operate on the NHWC input W = model.get_initializer(consumer.input[1]) @@ -78,8 +76,6 @@ def apply(self, model): into subsequent node" ) else: - warnings.warn( - "Unsupported transpose node before flatten layer" - ) + warnings.warn("Unsupported transpose node before flatten layer") return (model, graph_modified) diff --git a/src/finn/transformation/qonnx/convert_qonnx_to_finn.py b/src/finn/transformation/qonnx/convert_qonnx_to_finn.py index 34f11d1e95..c921b3d472 100644 --- a/src/finn/transformation/qonnx/convert_qonnx_to_finn.py +++ b/src/finn/transformation/qonnx/convert_qonnx_to_finn.py @@ -66,9 +66,7 @@ class ConvertQONNXtoFINN(Transformation): def __init__( self, - filter_function=default_filter_function_generator( - max_multithreshold_bit_width=8 - ), + filter_function=default_filter_function_generator(max_multithreshold_bit_width=8), ): super().__init__() self._filter_function = filter_function diff --git a/src/finn/transformation/qonnx/fold_quant_weights.py b/src/finn/transformation/qonnx/fold_quant_weights.py index e8339ae244..e027010271 100644 --- a/src/finn/transformation/qonnx/fold_quant_weights.py +++ b/src/finn/transformation/qonnx/fold_quant_weights.py @@ -57,13 +57,9 @@ def apply(self, model): is_const_shape = (n.op_type == "Shape") and (ishape is not None) if is_all_constant_inputs or is_const_shape: # Check node validity - if ( - n.op_type == "Quant" - and not model.get_initializer(n.input[2]) == 0 - ): + if n.op_type == "Quant" and not model.get_initializer(n.input[2]) == 0: raise ValueError( - "Only Quant nodes with zero-point == 0 " - "are currently supported." + "Only Quant nodes with zero-point == 0 " "are currently supported." ) if model.is_fork_node(n): raise ValueError( @@ -73,8 +69,7 @@ def apply(self, model): target_node = model.find_direct_successors(n) if target_node is None: raise RuntimeError( - "Weights quantized with the Quant node must have " - "a successor node." + "Weights quantized with the Quant node must have " "a successor node." ) else: target_node = target_node[0] @@ -126,9 +121,7 @@ def apply(self, model): model.set_tensor_datatype(node_out, new_dtype) # Reshape scale for Conv if required - target_output_shape = model.get_tensor_shape( - target_node.output[0] - ) + target_output_shape = model.get_tensor_shape(target_node.output[0]) if target_node.op_type == "Conv" and len(scale.shape) > 0: conv_out_shape = [1] * len(target_output_shape) # only support per-output channel scaling @@ -160,9 +153,7 @@ def apply(self, model): "Can only constant fold scaled Quant weights " "if a successor exists." ) - assert ( - len(successor) == 1 - ), "Only implemented for a single consumer" + assert len(successor) == 1, "Only implemented for a single consumer" successor = successor[0] succ_output_name = successor.output[0] diff --git a/src/finn/transformation/qonnx/infer_quant_avg_pool_2d.py b/src/finn/transformation/qonnx/infer_quant_avg_pool_2d.py index d2aaee59a4..72d473419a 100644 --- a/src/finn/transformation/qonnx/infer_quant_avg_pool_2d.py +++ b/src/finn/transformation/qonnx/infer_quant_avg_pool_2d.py @@ -124,18 +124,10 @@ def apply(self, model): node_ind += 1 if n.op_type == "AveragePool": mul_node = model.find_direct_successors(n) - if ( - mul_node is not None - and len(mul_node) == 1 - and mul_node[0].op_type == "Mul" - ): + if mul_node is not None and len(mul_node) == 1 and mul_node[0].op_type == "Mul": mul_node = mul_node[0] t_node = model.find_direct_successors(mul_node) - if ( - t_node is not None - and len(t_node) == 1 - and t_node[0].op_type == "Trunc" - ): + if t_node is not None and len(t_node) == 1 and t_node[0].op_type == "Trunc": t_node = t_node[0] running_node_index = node_ind # Check node for compatibility @@ -143,27 +135,16 @@ def apply(self, model): k_s = get_by_name(n.attribute, "kernel_shape") if k_s is None or len(k_s.ints) != 2 or len(set(k_s.ints)) != 1: raise ValueError( - "FINN only supports average pooling with " - "2D square kernels." + "FINN only supports average pooling with " "2D square kernels." ) k_s = k_s.ints[0] pads = get_by_name(n.attribute, "pads") - if ( - pads is None - or len(set(pads.ints)) != 1 - or pads.ints[0] != 0 - ): - raise ValueError( - "FINN dosn't support padding for average pooling." - ) + if pads is None or len(set(pads.ints)) != 1 or pads.ints[0] != 0: + raise ValueError("FINN dosn't support padding for average pooling.") stride = get_by_name(n.attribute, "strides") - if ( - stride is None - or len(stride.ints) != 2 - or len(set(stride.ints)) != 1 - ): + if stride is None or len(stride.ints) != 2 or len(set(stride.ints)) != 1: raise ValueError( "FINN only supports 2D strides with equal values in " "each direction." @@ -172,11 +153,7 @@ def apply(self, model): # Mul node mul_val = model.get_initializer(mul_node.input[1]) - if ( - mul_val is None - or len(mul_val.shape) != 0 - or mul_val != k_s * k_s - ): + if mul_val is None or len(mul_val.shape) != 0 or mul_val != k_s * k_s: raise ValueError( f"The Mul node after the AveragePool node must have " f"static initialization at the second input, " @@ -190,8 +167,7 @@ def apply(self, model): rounding_mode = get_by_name(t_node.attribute, "rounding_mode") if rounding_mode is None or rounding_mode.s != b"FLOOR": raise ValueError( - "The Trunc node must have the rounding_mode " - "set to 'FLOOR'." + "The Trunc node must have the rounding_mode " "set to 'FLOOR'." ) for inp in t_node.input[1:]: if model.get_initializer(inp) is None: @@ -207,13 +183,8 @@ def apply(self, model): f"the Trunc node, it currently is {zero_pt}." ) trunc_in_bits = model.get_initializer(t_node.input[3]).flatten() - trunc_out_bits = model.get_initializer( - t_node.input[4] - ).flatten() - if ( - len(trunc_in_bits.shape) != 1 - or len(trunc_out_bits.shape) != 1 - ): + trunc_out_bits = model.get_initializer(t_node.input[4]).flatten() + if len(trunc_in_bits.shape) != 1 or len(trunc_out_bits.shape) != 1: raise ValueError( f"Finn only supports scalar bit widths " f"for the Trunc node. The input bit width " @@ -228,9 +199,7 @@ def apply(self, model): # https://github.com/Xilinx/finn-base/blob/ # 7c2603a95e90e4de2575020e575c24eab6a15889/src/finn/custom_op/ # general/quantavgpool2d.py#L94 - ibits = math.floor( - math.log(2**trunc_in_bits / (k_s * k_s), 2) - ) + ibits = math.floor(math.log(2**trunc_in_bits / (k_s * k_s), 2)) # Get sign signed = _get_signed_from_upstream(model, t_node) # ToDo: Change this to NHWC, diff --git a/src/finn/transformation/qonnx/qonnx_activation_handlers.py b/src/finn/transformation/qonnx/qonnx_activation_handlers.py index bbe5e1a0e3..323e391df4 100644 --- a/src/finn/transformation/qonnx/qonnx_activation_handlers.py +++ b/src/finn/transformation/qonnx/qonnx_activation_handlers.py @@ -351,13 +351,10 @@ def _calculate_thresholds(self): bit_width = 1.0 else: raise RuntimeError("Got an unexpected quantizer node type") - quant_scale = self._model.get_initializer(self._q_node.input[1]).astype( - np.float32 - ) + quant_scale = self._model.get_initializer(self._q_node.input[1]).astype(np.float32) act_node = self._model.find_direct_predecessors(self._q_node) act_node = act_node[0] if act_node.op_type == "Relu": - # Calculate thersholds, see: https://github.com/Xilinx/brevitas/blob/ # a5bfd6dc5e030f0047ac1ee47932b60e8e873e17/src/brevitas/export/ # onnx/finn/handler/act.py#L21 @@ -367,9 +364,7 @@ def _calculate_thresholds(self): num_scale_channels = flat_scale.shape[0] step = np.abs(flat_scale).astype(np.float32) min_threshold = step / 2 - thresholds = np.empty( - (num_scale_channels, num_thresholds), dtype=np_default_dtype - ) + thresholds = np.empty((num_scale_channels, num_thresholds), dtype=np_default_dtype) for c in range(num_scale_channels): for t in range(num_thresholds): thresholds[c][t] = min_threshold[c] + step[c] * t @@ -391,9 +386,7 @@ def _calculate_thresholds(self): # from https://pytorch.org/docs/stable/generated/torch.nn.SELU.html alpha = 1.6732632423543772848170429916717 selu_scale = 1.0507009873554804934193349852946 - thresholds = np.empty( - (num_scale_channels, num_thresholds), dtype=np_default_dtype - ) + thresholds = np.empty((num_scale_channels, num_thresholds), dtype=np_default_dtype) for c in range(num_scale_channels): for t in range(num_thresholds): step = -1.0 + half_scale + scale[c] * t @@ -424,8 +417,7 @@ def _remove_activation_node(self, multi_threshold_node): act_node = self._model.find_direct_predecessors(self._q_node) if act_node is None: raise RuntimeError( - "For handling of Relu activations a predecesor to " - "the Quant node must exist." + "For handling of Relu activations a predecesor to " "the Quant node must exist." ) act_node = act_node[0] if act_node.op_type not in self.valid_predecessor_op_types(): @@ -466,9 +458,7 @@ def _check_compatibility(self): q_inst = getCustomOp(self._q_node) signed = q_inst.get_nodeattr("signed") if not signed: - raise ValueError( - "FINN only supports signed Quant nodes for identity activations." - ) + raise ValueError("FINN only supports signed Quant nodes for identity activations.") if not self._model.get_initializer(self._q_node.input[2]) == 0: raise ValueError( "Only Quant nodes with zero-point == 0 " @@ -537,9 +527,7 @@ def _calculate_thresholds(self): num_scale_channels = flat_scale.shape[0] step = np.abs(flat_scale) half_step = step / 2.0 - thresholds = np.empty( - (num_scale_channels, num_thresholds), dtype=np_default_dtype - ) + thresholds = np.empty((num_scale_channels, num_thresholds), dtype=np_default_dtype) # compute the value of the smallest threshold, we'll neg-bias all # generated thresholds by this much min_threshold = -half_step - step * ((num_thresholds // 2) - 1) @@ -550,9 +538,7 @@ def _calculate_thresholds(self): thresholds[c][t] = min_threshold[c] + step[c] * t # ToDo: The index 1 needs to be changed to -1 for the channels last format - num_output_channels = self._model.get_tensor_shape(self._q_node.output[0])[ - 1 - ] + num_output_channels = self._model.get_tensor_shape(self._q_node.output[0])[1] final_shape = (num_output_channels, num_thresholds) if thresholds.shape != final_shape: thresholds = np.broadcast_to(thresholds, final_shape) @@ -574,9 +560,7 @@ def _calculate_act_scale(self): if bit_width != 1: scale = quant_scale else: - assert ( - quant_scale.flatten().shape[0] == 1 - ), "Unsupported BIPOLAR per channel scale" + assert quant_scale.flatten().shape[0] == 1, "Unsupported BIPOLAR per channel scale" assert quant_scale.flatten()[0] == 1.0, "Unsupported BIPOLAR scale != 1" scale = quant_scale * 2 return scale diff --git a/src/finn/transformation/qonnx/quant_act_to_multithreshold.py b/src/finn/transformation/qonnx/quant_act_to_multithreshold.py index 48dda3820d..1b1aea1bab 100644 --- a/src/finn/transformation/qonnx/quant_act_to_multithreshold.py +++ b/src/finn/transformation/qonnx/quant_act_to_multithreshold.py @@ -87,9 +87,7 @@ class ConvertQuantActToMultiThreshold(Transformation): def __init__( self, - filter_function=default_filter_function_generator( - max_multithreshold_bit_width=8 - ), + filter_function=default_filter_function_generator(max_multithreshold_bit_width=8), ): super().__init__() self._filter_function = filter_function diff --git a/src/finn/transformation/streamline/absorb.py b/src/finn/transformation/streamline/absorb.py index 73df52f890..e3e2468bba 100644 --- a/src/finn/transformation/streamline/absorb.py +++ b/src/finn/transformation/streamline/absorb.py @@ -80,9 +80,7 @@ def apply(self, model): steps = T.shape[-1] new_min = bias new_max = steps + bias - odt = DataType.get_smallest_possible(steps).name.replace( - "UINT", "INT" - ) + odt = DataType.get_smallest_possible(steps).name.replace("UINT", "INT") odt = DataType[odt] assert odt.allowed(new_max) and odt.allowed( new_min @@ -112,11 +110,7 @@ def apply(self, model): graph_modified = False for n in graph.node: node_ind += 1 - if ( - n.op_type == "Add" - and not model.is_fork_node(n) - and not model.is_join_node(n) - ): + if n.op_type == "Add" and not model.is_fork_node(n) and not model.is_join_node(n): consumer = model.find_consumer(n.output[0]) if consumer is not None and consumer.op_type == "MultiThreshold": add_weight_name = n.input[1] @@ -153,11 +147,7 @@ def apply(self, model): graph_modified = False for n in graph.node: node_ind += 1 - if ( - n.op_type == "Mul" - and not model.is_fork_node(n) - and not model.is_join_node(n) - ): + if n.op_type == "Mul" and not model.is_fork_node(n) and not model.is_join_node(n): mul_weight_name = n.input[1] A = model.get_initializer(mul_weight_name) assert A is not None, "Initializer for mul weights is not set." @@ -203,9 +193,7 @@ def apply(self, model): is_scalar = np.prod(A.shape) == 1 actual_ndims = len(tuple(filter(lambda x: x > 1, A.shape))) is_1d = actual_ndims == 1 - is_not_bipolar = ( - model.get_tensor_datatype(mul_weight_name) != DataType["BIPOLAR"] - ) + is_not_bipolar = model.get_tensor_datatype(mul_weight_name) != DataType["BIPOLAR"] is_signed = (A < 0).any() if is_signed and (is_scalar or is_1d) and is_not_bipolar: start_name = n.input[0] @@ -219,9 +207,7 @@ def apply(self, model): model.set_tensor_datatype(sign_mul_param_name, DataType["BIPOLAR"]) # replace original mul weight by magnitudes model.set_initializer(mul_weight_name, np.abs(A)) - new_mul = oh.make_node( - "Mul", [start_name, sign_mul_param_name], [middle_name] - ) + new_mul = oh.make_node("Mul", [start_name, sign_mul_param_name], [middle_name]) n.input[0] = middle_name graph.node.insert(node_ind - 1, new_mul) graph_modified = True @@ -338,13 +324,9 @@ def apply(self, model): mt_cand.output[0] ) # Create a new ValueInfoProto and set the shape - model.set_tensor_shape( - intermediate_tensor_name, intermediate_tensor_shape - ) + model.set_tensor_shape(intermediate_tensor_name, intermediate_tensor_shape) # Set the tensor layout - model.set_tensor_layout( - intermediate_tensor_name, DataLayout.NHWC - ) + model.set_tensor_layout(intermediate_tensor_name, DataLayout.NHWC) # Set the tensor FINN datatype model.set_tensor_datatype( intermediate_tensor_name, intermediate_tensor_finn_dtype @@ -379,8 +361,7 @@ def apply(self, model): for n in graph.node: node_ind += 1 if ( - n.op_type == "Reshape" - and (model.get_initializer(n.input[1]) == [1, -1]).all() + n.op_type == "Reshape" and (model.get_initializer(n.input[1]) == [1, -1]).all() ) or n.op_type == "Flatten": prod = model.find_producer(n.input[0]) if ( @@ -556,23 +537,17 @@ def apply(self, model): if sizes is not None: ishape = model.get_tensor_shape(mt_cand.input[0]) ns, cs, hs, ws = sizes / np.asarray(ishape) - model.set_initializer( - mt_cand.input[2], np.asarray([ns, cs, hs, ws]) - ) + model.set_initializer(mt_cand.input[2], np.asarray([ns, cs, hs, ws])) mt_cand.input.remove(mt_cand.input[3]) # scales already specified, transpose indices to NHWC scales = model.get_initializer(mt_cand.input[2]) assert scales is not None ns, cs, hs, ws = scales - model.set_initializer( - mt_cand.input[2], np.asarray([ns, hs, ws, cs]) - ) + model.set_initializer(mt_cand.input[2], np.asarray([ns, hs, ws, cs])) # get rid of first tranpose node mt_cand.input[0] = node.input[0] graph.node.remove(node) - is_last_node = mt_cand.output[0] in [ - x.name for x in model.graph.output - ] + is_last_node = mt_cand.output[0] in [x.name for x in model.graph.output] new_tensor_name = model.make_new_valueinfo_name() if is_last_node: diff --git a/src/finn/transformation/streamline/reorder.py b/src/finn/transformation/streamline/reorder.py index 29eefacc32..2e6aebf093 100644 --- a/src/finn/transformation/streamline/reorder.py +++ b/src/finn/transformation/streamline/reorder.py @@ -53,11 +53,7 @@ def apply(self, model): graph_modified = False for n in graph.node: node_ind += 1 - if ( - n.op_type == "Add" - and not model.is_fork_node(n) - and not model.is_join_node(n) - ): + if n.op_type == "Add" and not model.is_fork_node(n) and not model.is_join_node(n): consumer = model.find_consumer(n.output[0]) if ( consumer is not None @@ -73,9 +69,7 @@ def apply(self, model): A = model.get_initializer(mul_weight_name) B = model.get_initializer(add_weight_name) if (A is None) or (B is None): - warnings.warn( - "Mul or add does not have constant params, skipping" - ) + warnings.warn("Mul or add does not have constant params, skipping") continue start_name = n.input[0] middle_name = n.output[0] @@ -116,11 +110,7 @@ def apply(self, model): graph_modified = False for n in graph.node: node_ind += 1 - if ( - n.op_type == "Mul" - and not model.is_fork_node(n) - and not model.is_join_node(n) - ): + if n.op_type == "Mul" and not model.is_fork_node(n) and not model.is_join_node(n): consumer = model.find_consumer(n.output[0]) if ( consumer is not None @@ -174,11 +164,7 @@ def apply(self, model): graph_modified = False for n in graph.node: node_ind += 1 - if ( - n.op_type == "Add" - and not model.is_fork_node(n) - and not model.is_join_node(n) - ): + if n.op_type == "Add" and not model.is_fork_node(n) and not model.is_join_node(n): consumer = model.find_consumer(n.output[0]) if ( consumer is not None @@ -235,11 +221,7 @@ def apply(self, model): graph_modified = False for n in graph.node: node_ind += 1 - if ( - n.op_type == "Add" - and not model.is_fork_node(n) - and not model.is_join_node(n) - ): + if n.op_type == "Add" and not model.is_fork_node(n) and not model.is_join_node(n): consumer = model.find_consumer(n.output[0]) if ( consumer is not None @@ -317,11 +299,7 @@ def apply(self, model): graph_modified = False for n in graph.node: node_ind += 1 - if ( - n.op_type == "Mul" - and not model.is_fork_node(n) - and not model.is_join_node(n) - ): + if n.op_type == "Mul" and not model.is_fork_node(n) and not model.is_join_node(n): consumer = model.find_consumer(n.output[0]) if ( consumer is not None @@ -370,11 +348,7 @@ def apply(self, model): graph_modified = False for n in graph.node: node_ind += 1 - if ( - n.op_type == "Mul" - and not model.is_fork_node(n) - and not model.is_join_node(n) - ): + if n.op_type == "Mul" and not model.is_fork_node(n) and not model.is_join_node(n): consumer = model.find_consumer(n.output[0]) if ( consumer is not None @@ -436,11 +410,7 @@ def apply(self, model): graph_modified = False for n in graph.node: node_ind += 1 - if ( - n.op_type == "Mul" - and not model.is_fork_node(n) - and not model.is_join_node(n) - ): + if n.op_type == "Mul" and not model.is_fork_node(n) and not model.is_join_node(n): consumer = model.find_consumer(n.output[0]) if ( consumer is not None @@ -465,9 +435,7 @@ def apply(self, model): maxpool_out_shape = model.get_tensor_shape(maxpool_out_name) # do not support non-2D MaxPool - kernel_shape = list( - get_by_name(maxpool_node.attribute, "kernel_shape").ints - ) + kernel_shape = list(get_by_name(maxpool_node.attribute, "kernel_shape").ints) if len(kernel_shape) != 2: continue @@ -675,9 +643,7 @@ def apply(self, model): if ceil_mode is not None: ceil_mode = ceil_mode.i else: - ceil_mode = ( - 0 # default to ceil_mode=0 (equivalent to np.floor) - ) + ceil_mode = 0 # default to ceil_mode=0 (equivalent to np.floor) n.op_type = "MaxPoolNHWC" n.domain = "qonnx.custom_op.general" start_name = n.input[0] @@ -702,9 +668,7 @@ def apply(self, model): if ceil_mode is not None: ceil_mode = ceil_mode.i else: - ceil_mode = ( - 0 # default to ceil_mode=0 (equivalent to np.floor) - ) + ceil_mode = 0 # default to ceil_mode=0 (equivalent to np.floor) n.op_type = "MaxPoolNHWC" n.domain = "qonnx.custom_op.general" start_name = producer.input[0] @@ -739,8 +703,7 @@ def apply(self, model): if n.op_type == "Upsample" or n.op_type == "Resize": if model.get_tensor_layout(n.input[0]) != DataLayout.NCHW: warnings.warn( - "%s: Input not NCHW. Can't operate transformation on node." - % n.name + "%s: Input not NCHW. Can't operate transformation on node." % n.name ) continue consumer = model.find_consumer(n.output[0]) @@ -818,7 +781,6 @@ def apply(self, model): and model.is_fork_node(n) and not model.is_join_node(n) ): - # Restrict this transform to operations with constant parameters # Assuming parameters is in input 1 if len(n.input) > 1: @@ -863,9 +825,7 @@ def apply(self, model): consumer_node.input[idx] = new_output_tensor_name break else: - raise Exception( - "Consumer should have the current node output as input" - ) + raise Exception("Consumer should have the current node output as input") graph.node.insert(node_ind, consumer_node) @@ -892,9 +852,7 @@ def __init__(self): class MoveTransposePastFork(MoveOpPastFork): def __init__(self): - super().__init__( - ["Transpose"], lambda x: {"perm": get_by_name(x.attribute, "perm").ints} - ) + super().__init__(["Transpose"], lambda x: {"perm": get_by_name(x.attribute, "perm").ints}) class MoveMaxPoolPastMultiThreshold(Transformation): @@ -918,9 +876,7 @@ def apply(self, model): mt_out = consumer.output[0] mt_odt = model.get_tensor_datatype(mt_out) if mt_odt.signed() and has_padding: - warnings.warn( - "Skipping padded MaxPool + signed-output MultiThreshold" - ) + warnings.warn("Skipping padded MaxPool + signed-output MultiThreshold") continue # check for non-decreasing thresholds and nonnegative # scale factor in MultiThreshold @@ -1031,11 +987,7 @@ def apply(self, model): node_ind = 0 for n in graph.node: node_ind += 1 - if ( - n.op_type == "Flatten" - and not model.is_fork_node(n) - and not model.is_join_node(n) - ): + if n.op_type == "Flatten" and not model.is_fork_node(n) and not model.is_join_node(n): consumer = model.find_consumer(n.output[0]) if ( consumer is not None @@ -1121,11 +1073,7 @@ def apply(self, model): graph_modified = False for n in graph.node: node_ind += 1 - if ( - n.op_type == "Transpose" - and not model.is_fork_node(n) - and not model.is_join_node(n) - ): + if n.op_type == "Transpose" and not model.is_fork_node(n) and not model.is_join_node(n): consumer = model.find_consumer(n.output[0]) if ( consumer is not None diff --git a/src/finn/transformation/streamline/round_thresholds.py b/src/finn/transformation/streamline/round_thresholds.py index 601dab04cb..5ba5ee0ff5 100644 --- a/src/finn/transformation/streamline/round_thresholds.py +++ b/src/finn/transformation/streamline/round_thresholds.py @@ -57,8 +57,7 @@ def apply(self, model): model.set_tensor_datatype(n.input[1], idtype) graph_modified = True if idtype.is_integer() and ( - (Tnew < (idtype.min() - 1)).any() - or (Tnew > (idtype.max() + 1)).any() + (Tnew < (idtype.min() - 1)).any() or (Tnew > (idtype.max() + 1)).any() ): # clip any large thresholds to input range + 1 Tnew = np.clip(Tnew, idtype.min() - 1, idtype.max() + 1) diff --git a/src/finn/util/create.py b/src/finn/util/create.py index ed3e1a843e..af92d1cb8e 100644 --- a/src/finn/util/create.py +++ b/src/finn/util/create.py @@ -108,15 +108,11 @@ def hls_mlp_maker(layer_spec): odt = lyr["odt"] if i == 0: - global_in = helper.make_tensor_value_info( - current_in_name, TensorProto.FLOAT, [1, mw] - ) + global_in = helper.make_tensor_value_info(current_in_name, TensorProto.FLOAT, [1, mw]) model.graph.input.append(global_in) if i == len(layer_spec) - 1: - global_out = helper.make_tensor_value_info( - current_out_name, TensorProto.FLOAT, [1, mh] - ) + global_out = helper.make_tensor_value_info(current_out_name, TensorProto.FLOAT, [1, mh]) model.graph.output.append(global_out) # there are two ways to implement bipolar weights and inputs for diff --git a/src/finn/util/data_packing.py b/src/finn/util/data_packing.py index a41fe882e5..7698850029 100644 --- a/src/finn/util/data_packing.py +++ b/src/finn/util/data_packing.py @@ -149,9 +149,7 @@ def pack_innermost_dim_as_hex_string( ndarray = np.asarray(ndarray, dtype=np.float32) def fun(x): - return array2hexstring( - x, dtype, pad_to_nbits, reverse=reverse_inner, prefix=prefix - ) + return array2hexstring(x, dtype, pad_to_nbits, reverse=reverse_inner, prefix=prefix) return np.apply_along_axis(fun, ndarray.ndim - 1, ndarray) @@ -232,9 +230,7 @@ def unpack_innermost_dim_from_hex_string( return array -def numpy_to_hls_code( - ndarray, dtype, hls_var_name, pack_innermost_dim=True, no_decl=False -): +def numpy_to_hls_code(ndarray, dtype, hls_var_name, pack_innermost_dim=True, no_decl=False): """Return C++ code representation of a numpy ndarray with FINN DataType dtype, using hls_var_name as the resulting C++ variable name. If pack_innermost_dim is specified, the innermost dimension of the ndarray @@ -311,9 +307,7 @@ def npy_to_rtlsim_input(input_file, input_dtype, pad_to_nbits, reverse_inner=Tru return packed_data -def rtlsim_output_to_npy( - output, path, dtype, shape, packedBits, targetBits, reverse_inner=True -): +def rtlsim_output_to_npy(output, path, dtype, shape, packedBits, targetBits, reverse_inner=True): """Convert a flattened sequence of Python arbitrary-precision integers output into a NumPy array, saved as npy file at path. Each arbitrary-precision integer is assumed to be a packed array of targetBits-bit elements, which @@ -418,9 +412,7 @@ def packed_bytearray_to_finnpy( """ - if ( - not issubclass(type(packed_bytearray), np.ndarray) - ) or packed_bytearray.dtype != np.uint8: + if (not issubclass(type(packed_bytearray), np.ndarray)) or packed_bytearray.dtype != np.uint8: raise Exception("packed_bytearray_to_finnpy needs NumPy uint8 arrays") if packed_bytearray.ndim == 0: raise Exception("packed_bytearray_to_finnpy expects at least 1D ndarray") @@ -446,9 +438,7 @@ def packed_bytearray_to_finnpy( if reverse_endian: packed_bytearray = np.flip(packed_bytearray, axis=-1) # convert innermost dim of byte array to hex strings - packed_hexstring = np.apply_along_axis( - npbytearray2hexstring, packed_dim, packed_bytearray - ) + packed_hexstring = np.apply_along_axis(npbytearray2hexstring, packed_dim, packed_bytearray) ret = unpack_innermost_dim_from_hex_string( packed_hexstring, dtype, output_shape, packed_bits, reverse_inner ) diff --git a/src/finn/util/imagenet.py b/src/finn/util/imagenet.py index b4548bb352..1d63adf58b 100644 --- a/src/finn/util/imagenet.py +++ b/src/finn/util/imagenet.py @@ -137,8 +137,7 @@ def measure_topk(n_images, fxn_pre, fxn_exec, fxn_post, verbose=True, k=5): class_names = { 0: "tench, Tinca tinca", 1: "goldfish, Carassius auratus", - 2: "great white shark, white shark, man-eater, man-eating shark, " - "Carcharodon carcharias", + 2: "great white shark, white shark, man-eater, man-eating shark, " "Carcharodon carcharias", 3: "tiger shark, Galeocerdo cuvieri", 4: "hammerhead, hammerhead shark", 5: "electric ray, crampfish, numbfish, torpedo", @@ -184,8 +183,7 @@ def measure_topk(n_images, fxn_pre, fxn_exec, fxn_post, verbose=True, k=5): 45: "Gila monster, Heloderma suspectum", 46: "green lizard, Lacerta viridis", 47: "African chameleon, Chamaeleo chamaeleon", - 48: "Komodo dragon, Komodo lizard, dragon lizard, giant lizard, " - "Varanus komodoensis", + 48: "Komodo dragon, Komodo lizard, dragon lizard, giant lizard, " "Varanus komodoensis", 49: "African crocodile, Nile crocodile, Crocodylus niloticus", 50: "American alligator, Alligator mississipiensis", 51: "triceratops", @@ -286,8 +284,7 @@ def measure_topk(n_images, fxn_pre, fxn_exec, fxn_post, verbose=True, k=5): 144: "pelican", 145: "king penguin, Aptenodytes patagonica", 146: "albatross, mollymawk", - 147: "grey whale, gray whale, devilfish, Eschrichtius gibbosus, " - "Eschrichtius robustus", + 147: "grey whale, gray whale, devilfish, Eschrichtius gibbosus, " "Eschrichtius robustus", 148: "killer whale, killer, orca, grampus, sea wolf, Orcinus orca", 149: "dugong, Dugong dugon", 150: "sea lion", @@ -580,8 +577,7 @@ def measure_topk(n_images, fxn_pre, fxn_exec, fxn_post, verbose=True, k=5): 433: "bathing cap, swimming cap", 434: "bath towel", 435: "bathtub, bathing tub, bath, tub", - 436: "beach wagon, station wagon, wagon, estate car, beach waggon, " - "station waggon, waggon", + 436: "beach wagon, station wagon, wagon, estate car, beach waggon, " "station waggon, waggon", 437: "beacon, lighthouse, beacon light, pharos", 438: "beaker", 439: "bearskin, busby, shako", @@ -636,8 +632,7 @@ def measure_topk(n_images, fxn_pre, fxn_exec, fxn_post, verbose=True, k=5): 487: "cellular telephone, cellular phone, cellphone, cell, mobile phone", 488: "chain", 489: "chainlink fence", - 490: "chain mail, ring mail, mail, chain armor, chain armour, ring armor, " - "ring armour", + 490: "chain mail, ring mail, mail, chain armor, chain armour, ring armor, " "ring armour", 491: "chain saw, chainsaw", 492: "chest", 493: "chiffonier, commode", diff --git a/src/finn/util/platforms.py b/src/finn/util/platforms.py index 8212cb5712..77dc591445 100644 --- a/src/finn/util/platforms.py +++ b/src/finn/util/platforms.py @@ -104,9 +104,7 @@ def compute_resources(self): def guide_resources(self): guide = [] # TODO: assert limits is of correct size - guide_res = ( - np.tile(np.array(self.compute_resources), (self.ndevices, 1)) - ).astype(int) + guide_res = (np.tile(np.array(self.compute_resources), (self.ndevices, 1))).astype(int) for i in range(self.nslr * self.ndevices): # when in multi-FPGA mode, subtract cost of UDP connection from eth_slr local_slr = i % self.nslr @@ -159,9 +157,7 @@ def compute_connection_cost(self): xlocal[i][j] = 1 # tile connection cost matrices for entire system for i in range(self.ndevices): - x[ - i * self.nslr : (i + 1) * self.nslr, i * self.nslr : (i + 1) * self.nslr - ] = xlocal + x[i * self.nslr : (i + 1) * self.nslr, i * self.nslr : (i + 1) * self.nslr] = xlocal # set cost for ethernet connections, assuming daisy-chaining for i in range(self.ndevices - 1): x[i * self.nslr + self.eth_slr][(i + 1) * self.nslr + self.eth_slr] = 10 @@ -182,9 +178,7 @@ def compute_connection_resource(self): slllocal[i][j] = self.sll_count[i][j] # tile connection cost matrices for entire system for i in range(self.ndevices): - sll[ - i * self.nslr : (i + 1) * self.nslr, i * self.nslr : (i + 1) * self.nslr - ] = slllocal + sll[i * self.nslr : (i + 1) * self.nslr, i * self.nslr : (i + 1) * self.nslr] = slllocal # set cost for ethernet connections, assuming daisy-chaining eth = np.full((self.nslr * self.ndevices, self.nslr * self.ndevices), 0) # no Eth throughput constraints from one SLR to itself diff --git a/src/finn/util/pyverilator.py b/src/finn/util/pyverilator.py index 7452394524..86cf2eed14 100644 --- a/src/finn/util/pyverilator.py +++ b/src/finn/util/pyverilator.py @@ -86,11 +86,7 @@ def file_to_basename(x): src_exts = [".v", ".sv"] all_verilog_files = list( - set( - filter( - lambda x: any(map(lambda y: x.endswith(y), src_exts)), all_verilog_srcs - ) - ) + set(filter(lambda x: any(map(lambda y: x.endswith(y), src_exts)), all_verilog_srcs)) ) verilog_header_dir = vivado_stitch_proj_dir + "/pyverilator_vh" @@ -98,9 +94,7 @@ def file_to_basename(x): # use custom version of axis infrastructure vh # to enable Verilator to simulate AMD/Xilinx components (e.g DWC) - custom_vh = pk.resource_filename( - "finn.qnn-data", "verilog/custom_axis_infrastructure.vh" - ) + custom_vh = pk.resource_filename("finn.qnn-data", "verilog/custom_axis_infrastructure.vh") shutil.copy(custom_vh, verilog_header_dir + "/axis_infrastructure_v1_1_0.vh") for fn in all_verilog_srcs: if fn.endswith(".vh"): @@ -137,9 +131,7 @@ def verilator_fifosim(model, n_inputs, max_iters=100000000): vivado_stitch_proj_dir = prepare_stitched_ip_for_verilator(model) verilog_header_dir = vivado_stitch_proj_dir + "/pyverilator_vh" build_dir = make_build_dir("verilator_fifosim_") - fifosim_cpp_fname = pk.resource_filename( - "finn.qnn-data", "cpp/verilator_fifosim.cpp" - ) + fifosim_cpp_fname = pk.resource_filename("finn.qnn-data", "cpp/verilator_fifosim.cpp") with open(fifosim_cpp_fname, "r") as f: fifosim_cpp_template = f.read() assert len(model.graph.input) == 1, "Only a single input stream is supported" @@ -148,9 +140,7 @@ def verilator_fifosim(model, n_inputs, max_iters=100000000): first_node = model.find_consumer(iname) oname = model.graph.output[0].name last_node = model.find_producer(oname) - assert (first_node is not None) and ( - last_node is not None - ), "Failed to find first/last nodes" + assert (first_node is not None) and (last_node is not None), "Failed to find first/last nodes" fnode_inst = getCustomOp(first_node) lnode_inst = getCustomOp(last_node) ishape_folded = fnode_inst.get_folded_input_shape() @@ -177,7 +167,7 @@ def verilator_fifosim(model, n_inputs, max_iters=100000000): "FIFO_DEPTH_LOGGING": fifo_log, } - for (key, val) in template_dict.items(): + for key, val in template_dict.items(): fifosim_cpp_template = fifosim_cpp_template.replace(f"@{key}@", str(val)) with open(build_dir + "/verilator_fifosim.cpp", "w") as f: diff --git a/src/finn/util/test.py b/src/finn/util/test.py index 4250079ef3..1f36486048 100644 --- a/src/finn/util/test.py +++ b/src/finn/util/test.py @@ -137,9 +137,7 @@ def get_example_input(topology): onnx_tensor = onnx.load_tensor_from_string(raw_i) return nph.to_array(onnx_tensor) elif topology == "cnv": - fn = pk.resource_filename( - "finn.qnn-data", "cifar10/cifar10-test-data-class3.npz" - ) + fn = pk.resource_filename("finn.qnn-data", "cifar10/cifar10-test-data-class3.npz") input_tensor = np.load(fn)["arr_0"].astype(np.float32) return input_tensor else: diff --git a/src/finn/util/vcd.py b/src/finn/util/vcd.py index 1f77276d5a..69dd82c5ea 100644 --- a/src/finn/util/vcd.py +++ b/src/finn/util/vcd.py @@ -69,7 +69,7 @@ def get_fifo_count_max(vcd_file, fifo_count_signal): assert len(d) != 0, "FIFO count signal not found" events = list(d.values())[0]["tv"] max = 0 - for (time, val) in events: + for time, val in events: current = int(val, base=2) if current > max: max = current @@ -140,7 +140,7 @@ def get_stream_if_stats(vcd_file, if_base_name): status = {"V": 0, "R": 0} last_time = 0 total_rising_clock_edges = 0 - for (sig, time, val) in events: + for sig, time, val in events: # pyverilator generates 5 time units per sample time = time / 5 # pyverilator generates 4 samples per clock period diff --git a/tests/brevitas/test_brevitas_avg_pool_export.py b/tests/brevitas/test_brevitas_avg_pool_export.py index 898f1fb732..053b632221 100644 --- a/tests/brevitas/test_brevitas_avg_pool_export.py +++ b/tests/brevitas/test_brevitas_avg_pool_export.py @@ -31,7 +31,7 @@ import os import torch from brevitas.export import export_qonnx -from brevitas.nn import TruncAvgPool2d, QuantIdentity, QuantReLU +from brevitas.nn import QuantIdentity, QuantReLU, TruncAvgPool2d from qonnx.core.datatype import DataType from qonnx.core.modelwrapper import ModelWrapper from qonnx.transformation.infer_datatypes import InferDataTypes diff --git a/tests/brevitas/test_brevitas_mobilenet.py b/tests/brevitas/test_brevitas_mobilenet.py index b469b197fa..fa391efcab 100644 --- a/tests/brevitas/test_brevitas_mobilenet.py +++ b/tests/brevitas/test_brevitas_mobilenet.py @@ -79,9 +79,7 @@ def test_brevitas_mobilenet(): export_finn_onnx(preproc, torch.randn(1, 3, 224, 224), preproc_onnx) preproc_model = ModelWrapper(preproc_onnx) # set input finn datatype to UINT8 - preproc_model.set_tensor_datatype( - preproc_model.graph.input[0].name, DataType["UINT8"] - ) + preproc_model.set_tensor_datatype(preproc_model.graph.input[0].name, DataType["UINT8"]) preproc_model = preproc_model.transform(InferShapes()) preproc_model = preproc_model.transform(GiveUniqueNodeNames()) preproc_model = preproc_model.transform(GiveUniqueParameterTensors()) @@ -121,6 +119,4 @@ def test_brevitas_mobilenet(): produced = odict[model.graph.output[0].name] produced_prob = odict["TopK_0_out0"] * a0 assert (produced.flatten() == expected_top5).all() - assert np.isclose( - produced_prob.flatten(), expected_top5_prob, atol=2.2 * 1e-1 - ).all() + assert np.isclose(produced_prob.flatten(), expected_top5_prob, atol=2.2 * 1e-1).all() diff --git a/tests/brevitas/test_brevitas_non_scaled_quanthardtanh_export.py b/tests/brevitas/test_brevitas_non_scaled_quanthardtanh_export.py index ad6a7e53de..2911303501 100644 --- a/tests/brevitas/test_brevitas_non_scaled_quanthardtanh_export.py +++ b/tests/brevitas/test_brevitas_non_scaled_quanthardtanh_export.py @@ -52,9 +52,7 @@ @pytest.mark.parametrize("narrow_range", [False, True]) @pytest.mark.parametrize("max_val", [1.0, 1 - 2 ** (-7)]) @pytest.mark.parametrize("QONNX_export", [False, True]) -def test_brevitas_act_export_qhardtanh_nonscaled( - abits, narrow_range, max_val, QONNX_export -): +def test_brevitas_act_export_qhardtanh_nonscaled(abits, narrow_range, max_val, QONNX_export): def get_quant_type(bit_width): if bit_width is None: return QuantType.FP @@ -86,9 +84,7 @@ def get_quant_type(bit_width): export_finn_onnx(b_act, torch.randn(ishape), export_onnx_path) model = ModelWrapper(export_onnx_path) model = model.transform(InferShapes()) - inp_tensor = np.random.uniform(low=min_val, high=max_val, size=ishape).astype( - np.float32 - ) + inp_tensor = np.random.uniform(low=min_val, high=max_val, size=ishape).astype(np.float32) idict = {model.graph.input[0].name: inp_tensor} odict = oxe.execute_onnx(model, idict, True) produced = odict[model.graph.output[0].name] diff --git a/tests/brevitas/test_brevitas_qlinear.py b/tests/brevitas/test_brevitas_qlinear.py index 1ad52fb5df..551345f649 100644 --- a/tests/brevitas/test_brevitas_qlinear.py +++ b/tests/brevitas/test_brevitas_qlinear.py @@ -53,9 +53,7 @@ @pytest.mark.parametrize("w_bits", [4]) @pytest.mark.parametrize("i_dtype", [DataType["UINT4"]]) @pytest.mark.parametrize("QONNX_export", [False, True]) -def test_brevitas_qlinear( - bias, out_features, in_features, w_bits, i_dtype, QONNX_export -): +def test_brevitas_qlinear(bias, out_features, in_features, w_bits, i_dtype, QONNX_export): i_shape = (1, in_features) w_shape = (out_features, in_features) b_linear = QuantLinear( @@ -67,9 +65,7 @@ def test_brevitas_qlinear( weight_quant_type=QuantType.INT, weight_scaling_per_output_channel=True, ) - weight_tensor_fp = np.random.uniform(low=-1.0, high=1.0, size=w_shape).astype( - np.float32 - ) + weight_tensor_fp = np.random.uniform(low=-1.0, high=1.0, size=w_shape).astype(np.float32) b_linear.weight.data = torch.from_numpy(weight_tensor_fp) b_linear.eval() if QONNX_export: diff --git a/tests/brevitas/test_brevitas_relu_act_export.py b/tests/brevitas/test_brevitas_relu_act_export.py index a4657d7924..9e1fcbdc2f 100644 --- a/tests/brevitas/test_brevitas_relu_act_export.py +++ b/tests/brevitas/test_brevitas_relu_act_export.py @@ -54,7 +54,6 @@ def test_brevitas_act_export_relu( ishape, QONNX_export, ): - b_act = QuantReLU( bit_width=abits, ) @@ -90,7 +89,6 @@ def test_brevitas_act_export_relu_channel( ishape, QONNX_export, ): - ch = ishape[1] b_act = QuantReLU( bit_width=abits, diff --git a/tests/brevitas/test_brevitas_scaled_qhardtanh_export.py b/tests/brevitas/test_brevitas_scaled_qhardtanh_export.py index d35cc8d2dd..72a15810aa 100644 --- a/tests/brevitas/test_brevitas_scaled_qhardtanh_export.py +++ b/tests/brevitas/test_brevitas_scaled_qhardtanh_export.py @@ -52,9 +52,7 @@ @pytest.mark.parametrize("narrow_range", [False, True]) @pytest.mark.parametrize("min_val", [-1.0, -(1 - 2 ** (-7)), -2]) @pytest.mark.parametrize("max_val", [1.0, 1 - 2 ** (-7), 2]) -@pytest.mark.parametrize( - "scaling_impl_type", [ScalingImplType.CONST, ScalingImplType.PARAMETER] -) +@pytest.mark.parametrize("scaling_impl_type", [ScalingImplType.CONST, ScalingImplType.PARAMETER]) @pytest.mark.parametrize("QONNX_export", [False, True]) def test_brevitas_act_export_qhardtanh_scaled( abits, narrow_range, min_val, max_val, scaling_impl_type, QONNX_export @@ -99,9 +97,7 @@ def get_quant_type(bit_width): export_finn_onnx(b_act, torch.randn(ishape), export_onnx_path) model = ModelWrapper(export_onnx_path) model = model.transform(InferShapes()) - inp_tensor = np.random.uniform(low=min_val, high=max_val, size=ishape).astype( - np.float32 - ) + inp_tensor = np.random.uniform(low=min_val, high=max_val, size=ishape).astype(np.float32) idict = {model.graph.input[0].name: inp_tensor} odict = oxe.execute_onnx(model, idict, True) produced = odict[model.graph.output[0].name] diff --git a/tests/brevitas/test_brevitas_selu_act_export.py b/tests/brevitas/test_brevitas_selu_act_export.py index 3f4807c5d7..c8d040dbee 100644 --- a/tests/brevitas/test_brevitas_selu_act_export.py +++ b/tests/brevitas/test_brevitas_selu_act_export.py @@ -48,9 +48,7 @@ @pytest.mark.parametrize("narrow", [True, False]) def test_brevitas_act_export_selu(abits, ishape, narrow): export_path = "test_brevitas_selu_act_export_%s.onnx" % str(abits) - b_act = torch.nn.Sequential( - torch.nn.SELU(), QuantIdentity(bit_width=abits, narrow=narrow) - ) + b_act = torch.nn.Sequential(torch.nn.SELU(), QuantIdentity(bit_width=abits, narrow=narrow)) export_qonnx( b_act, diff --git a/tests/brevitas/test_brevitas_validate_mobilenet.py b/tests/brevitas/test_brevitas_validate_mobilenet.py index 20e8ddad50..f3f7df0e3d 100644 --- a/tests/brevitas/test_brevitas_validate_mobilenet.py +++ b/tests/brevitas/test_brevitas_validate_mobilenet.py @@ -146,9 +146,7 @@ def test_brevitas_compare_exported_mobilenet(): model = model.transform(MergeONNXModels(preproc_model)) model.save(export_onnx_path + "/quant_mobilenet_v1_4b.onnx") - with open( - export_onnx_path + "/mobilenet_validation.csv", "w", newline="" - ) as csvfile: + with open(export_onnx_path + "/mobilenet_validation.csv", "w", newline="") as csvfile: writer = csv.writer(csvfile) writer.writerow( [ @@ -165,7 +163,7 @@ def test_brevitas_compare_exported_mobilenet(): workload = imagenet_util.get_val_images(n_images, interleave_classes=True) all_inds_ok = True all_probs_ok = True - for (img_path, target_id) in workload: + for img_path, target_id in workload: img_np = imagenet_util.load_resize_crop(img_path) img_torch = torch.from_numpy(img_np).float() # do forward pass in PyTorch/Brevitas diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index 5edd77d95d..b08028e7cb 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -314,9 +314,7 @@ def test_export(self, topology, wbits, abits, QONNX_export): assert os.path.isfile(chkpt_name) def test_import_and_tidy(self, topology, wbits, abits, QONNX_export): - prev_chkpt_name = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "export" - ) + prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, QONNX_export, "export") model = load_test_checkpoint_or_skip(prev_chkpt_name) model = model.transform(InferShapes()) model = model.transform(FoldConstants()) @@ -324,9 +322,7 @@ def test_import_and_tidy(self, topology, wbits, abits, QONNX_export): model = model.transform(GiveReadableTensorNames()) model = model.transform(InferDataTypes()) model = model.transform(RemoveStaticGraphInputs()) - chkpt = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "import_and_tidy" - ) + chkpt = get_checkpoint_name(topology, wbits, abits, QONNX_export, "import_and_tidy") model.save(chkpt) def test_add_pre_and_postproc(self, topology, wbits, abits, QONNX_export): @@ -338,9 +334,7 @@ def test_add_pre_and_postproc(self, topology, wbits, abits, QONNX_export): ishape = model.get_tensor_shape(global_inp_name) # preprocessing: torchvision's ToTensor divides uint8 inputs by 255 totensor_pyt = ToTensor() - chkpt_preproc_name = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "preproc" - ) + chkpt_preproc_name = get_checkpoint_name(topology, wbits, abits, QONNX_export, "preproc") export_finn_onnx(totensor_pyt, torch.randn(ishape), chkpt_preproc_name, opset_version=13) assert os.path.isfile(chkpt_preproc_name) # join preprocessing and core model @@ -353,9 +347,7 @@ def test_add_pre_and_postproc(self, topology, wbits, abits, QONNX_export): model.set_tensor_datatype(global_inp_name, DataType["UINT8"]) # postprocessing: insert Top-1 node at the end model = model.transform(InsertTopK(k=1)) - chkpt_name = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "pre_post" - ) + chkpt_name = get_checkpoint_name(topology, wbits, abits, QONNX_export, "pre_post") # tidy-up again model = model.transform(InferShapes()) model = model.transform(FoldConstants()) @@ -367,9 +359,7 @@ def test_add_pre_and_postproc(self, topology, wbits, abits, QONNX_export): assert os.path.isfile(chkpt_name) def test_streamline(self, topology, wbits, abits, QONNX_export): - prev_chkpt_name = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "pre_post" - ) + prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, QONNX_export, "pre_post") model = load_test_checkpoint_or_skip(prev_chkpt_name) model = model.transform(absorb.AbsorbSignBiasIntoMultiThreshold()) # move past any reshapes to be able to streamline input scaling @@ -385,14 +375,10 @@ def test_streamline(self, topology, wbits, abits, QONNX_export): model = model.transform(absorb.AbsorbScalarMulAddIntoTopK()) model = model.transform(InferDataLayouts()) model = model.transform(RemoveUnusedTensors()) - model.save( - get_checkpoint_name(topology, wbits, abits, QONNX_export, "streamline") - ) + model.save(get_checkpoint_name(topology, wbits, abits, QONNX_export, "streamline")) def test_convert_to_hls_layers(self, topology, wbits, abits, QONNX_export): - prev_chkpt_name = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "streamline" - ) + prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, QONNX_export, "streamline") model = load_test_checkpoint_or_skip(prev_chkpt_name) if topology == "tfc" and wbits == 1 and abits == 1: # use standalone thresholds for tfc-w1a1 to also exercise that option @@ -415,9 +401,7 @@ def test_convert_to_hls_layers(self, topology, wbits, abits, QONNX_export): model = model.transform(GiveUniqueNodeNames()) model = model.transform(InferDataLayouts()) model.save( - get_checkpoint_name( - topology, wbits, abits, QONNX_export, "convert_to_hls_layers" - ) + get_checkpoint_name(topology, wbits, abits, QONNX_export, "convert_to_hls_layers") ) exp_layer_counts = { "tfc": [ @@ -452,7 +436,7 @@ def test_convert_to_hls_layers(self, topology, wbits, abits, QONNX_export): else: exp_key = topology exp_layer_counts = exp_layer_counts[exp_key] - for (op_type, exp_count) in exp_layer_counts: + for op_type, exp_count in exp_layer_counts: assert len(model.get_nodes_by_op_type(op_type)) == exp_count def test_create_dataflow_partition(self, topology, wbits, abits, QONNX_export): @@ -484,9 +468,7 @@ def test_fold(self, topology, wbits, abits, QONNX_export): model.save(get_checkpoint_name(topology, wbits, abits, QONNX_export, "fold")) def test_minimize_bit_width(self, topology, wbits, abits, QONNX_export): - prev_chkpt_name = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "fold" - ) + prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, QONNX_export, "fold") model = load_test_checkpoint_or_skip(prev_chkpt_name) model = model.transform(MinimizeAccumulatorWidth()) model = model.transform(MinimizeWeightBitWidth()) @@ -505,13 +487,9 @@ def test_cppsim(self, topology, wbits, abits, QONNX_export): model = model.transform(PrepareCppSim()) model = model.transform(CompileCppSim()) model = model.transform(SetExecMode("cppsim")) - cppsim_chkpt = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "cppsim" - ) + cppsim_chkpt = get_checkpoint_name(topology, wbits, abits, QONNX_export, "cppsim") model.save(cppsim_chkpt) - parent_chkpt = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "dataflow_parent" - ) + parent_chkpt = get_checkpoint_name(topology, wbits, abits, QONNX_export, "dataflow_parent") (input_tensor_npy, output_tensor_npy) = get_golden_io_pair( topology, wbits, abits, return_topk=1 ) @@ -524,35 +502,25 @@ def test_cppsim(self, topology, wbits, abits, QONNX_export): def test_ipgen(self, topology, wbits, abits, QONNX_export, kind): if kind == "alveo" and ("VITIS_PATH" not in os.environ): pytest.skip("VITIS_PATH not set") - prev_chkpt_name = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "fold" - ) + prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, QONNX_export, "fold") model = load_test_checkpoint_or_skip(prev_chkpt_name) test_fpga_part = get_build_env(kind, target_clk_ns)["part"] model = model.transform(GiveUniqueNodeNames()) model = model.transform(PrepareIP(test_fpga_part, target_clk_ns)) model = model.transform(HLSSynthIP()) - model.save( - get_checkpoint_name(topology, wbits, abits, QONNX_export, "ipgen_" + kind) - ) + model.save(get_checkpoint_name(topology, wbits, abits, QONNX_export, "ipgen_" + kind)) @pytest.mark.slow @pytest.mark.vivado @pytest.mark.parametrize("kind", ["zynq", "alveo"]) def test_set_fifo_depths(self, topology, wbits, abits, QONNX_export, kind): - prev_chkpt_name = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "ipgen_" + kind - ) + prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, QONNX_export, "ipgen_" + kind) model = load_test_checkpoint_or_skip(prev_chkpt_name) test_fpga_part = get_build_env(kind, target_clk_ns)["part"] model = model.transform(InsertAndSetFIFODepths(test_fpga_part, target_clk_ns)) fifo_layers = model.get_nodes_by_op_type("StreamingFIFO") assert len(fifo_layers) > 0 - model.save( - get_checkpoint_name( - topology, wbits, abits, QONNX_export, "fifodepth_" + kind - ) - ) + model.save(get_checkpoint_name(topology, wbits, abits, QONNX_export, "fifodepth_" + kind)) @pytest.mark.slow @pytest.mark.vivado @@ -577,17 +545,13 @@ def test_ipstitch_rtlsim(self, topology, wbits, abits, QONNX_export, kind): model.set_metadata_prop("exec_mode", "rtlsim") os.environ["LIVENESS_THRESHOLD"] = str(int(latency * 1.1)) if rtlsim_trace: - model.set_metadata_prop( - "rtlsim_trace", "%s_w%da%d.vcd" % (topology, wbits, abits) - ) + model.set_metadata_prop("rtlsim_trace", "%s_w%da%d.vcd" % (topology, wbits, abits)) os.environ["RTLSIM_TRACE_DEPTH"] = "3" rtlsim_chkpt = get_checkpoint_name( topology, wbits, abits, QONNX_export, "ipstitch_rtlsim_" + kind ) model.save(rtlsim_chkpt) - parent_chkpt = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "dataflow_parent" - ) + parent_chkpt = get_checkpoint_name(topology, wbits, abits, QONNX_export, "dataflow_parent") (input_tensor_npy, output_tensor_npy) = get_golden_io_pair( topology, wbits, abits, return_topk=1 ) @@ -619,18 +583,10 @@ def test_throughput_rtlsim(self, topology, wbits, abits, QONNX_export, kind): def test_validate_top1(self, topology, wbits, abits, QONNX_export, kind): if "TEST_END2END_VALIDATE_TOP1" not in os.environ: pytest.skip("TEST_END2END_VALIDATE_TOP1 not set") - prepostproc_chkpt = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "pre_post" - ) - streamline_chkpt = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "streamline" - ) - parent_chkpt = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "dataflow_parent" - ) - cppsim_chkpt = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "cppsim" - ) + prepostproc_chkpt = get_checkpoint_name(topology, wbits, abits, QONNX_export, "pre_post") + streamline_chkpt = get_checkpoint_name(topology, wbits, abits, QONNX_export, "streamline") + parent_chkpt = get_checkpoint_name(topology, wbits, abits, QONNX_export, "dataflow_parent") + cppsim_chkpt = get_checkpoint_name(topology, wbits, abits, QONNX_export, "cppsim") rtlsim_chkpt = get_checkpoint_name( topology, wbits, abits, QONNX_export, "ipstitch_rtlsim_" + kind ) @@ -654,9 +610,7 @@ def test_build(self, topology, wbits, abits, QONNX_export, kind): cfg = get_build_env(kind, target_clk_ns) model = model.transform(cfg["build_fxn"]) model = model.transform(AnnotateResources("synth")) - model.save( - get_checkpoint_name(topology, wbits, abits, QONNX_export, "build_" + kind) - ) + model.save(get_checkpoint_name(topology, wbits, abits, QONNX_export, "build_" + kind)) @pytest.mark.slow @pytest.mark.vivado @@ -665,12 +619,8 @@ def test_build(self, topology, wbits, abits, QONNX_export, kind): def test_make_pynq_driver(self, topology, wbits, abits, QONNX_export, kind): if kind == "alveo" and ("VITIS_PATH" not in os.environ): pytest.skip("VITIS_PATH not set") - prev_chkpt_name = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "build_" + kind - ) + prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, QONNX_export, "build_" + kind) model = load_test_checkpoint_or_skip(prev_chkpt_name) kind_to_driver_platform = {"zynq": "zynq-iodma", "alveo": "alveo"} model = model.transform(MakePYNQDriver(kind_to_driver_platform[kind])) - model.save( - get_checkpoint_name(topology, wbits, abits, QONNX_export, "driver_" + kind) - ) + model.save(get_checkpoint_name(topology, wbits, abits, QONNX_export, "driver_" + kind)) diff --git a/tests/end2end/test_end2end_cybsec_mlp.py b/tests/end2end/test_end2end_cybsec_mlp.py index e6ca90b7b2..6e758d2d2d 100644 --- a/tests/end2end/test_end2end_cybsec_mlp.py +++ b/tests/end2end/test_end2end_cybsec_mlp.py @@ -109,9 +109,7 @@ def test_end2end_cybsec_mlp_export(QONNX_export): QuantReLU(bit_width=act_bit_width), QuantLinear(hidden3, num_classes, bias=True, weight_bit_width=weight_bit_width), ) - trained_state_dict = torch.load(assets_dir + "/state_dict.pth")[ - "models_state_dict" - ][0] + trained_state_dict = torch.load(assets_dir + "/state_dict.pth")["models_state_dict"][0] model.load_state_dict(trained_state_dict, strict=False) W_orig = model[0].weight.data.detach().numpy() # pad the second (593-sized) dimensions with 7 zeroes at the end @@ -132,9 +130,7 @@ def test_end2end_cybsec_mlp_export(QONNX_export): if QONNX_export: # With the onnx export from Brevitas we need to manually set # the FINN DataType at the input - export_qonnx( - model_for_export, torch.randn(input_shape), export_path=export_onnx_path - ) + export_qonnx(model_for_export, torch.randn(input_shape), export_path=export_onnx_path) model = ModelWrapper(export_onnx_path) model.set_tensor_datatype(model.graph.input[0].name, DataType["BIPOLAR"]) model.save(export_onnx_path) @@ -144,7 +140,10 @@ def test_end2end_cybsec_mlp_export(QONNX_export): model.save(export_onnx_path) else: export_finn_onnx( - model_for_export, export_path=export_onnx_path, input_t=input_qt, input_names=["onnx::Mul_0"] + model_for_export, + export_path=export_onnx_path, + input_t=input_qt, + input_names=["onnx::Mul_0"], ) assert os.path.isfile(export_onnx_path) # fix input datatype @@ -169,9 +168,7 @@ def test_end2end_cybsec_mlp_export(QONNX_export): assert finn_model.graph.node[3].op_type == "MatMul" assert finn_model.graph.node[-1].op_type == "MultiThreshold" # verify datatypes on some tensors - assert ( - finn_model.get_tensor_datatype(finnonnx_in_tensor_name) == DataType["BIPOLAR"] - ) + assert finn_model.get_tensor_datatype(finnonnx_in_tensor_name) == DataType["BIPOLAR"] first_matmul_w_name = finn_model.get_nodes_by_op_type("MatMul")[0].input[1] assert finn_model.get_tensor_datatype(first_matmul_w_name) == DataType["INT2"] diff --git a/tests/end2end/test_end2end_mobilenet_v1.py b/tests/end2end/test_end2end_mobilenet_v1.py index 3a3c0fe237..e53022e74b 100644 --- a/tests/end2end/test_end2end_mobilenet_v1.py +++ b/tests/end2end/test_end2end_mobilenet_v1.py @@ -98,9 +98,7 @@ def test_end2end_mobilenet_export(): export_finn_onnx(preproc, torch.randn(1, 3, 224, 224), preproc_onnx) preproc_model = ModelWrapper(preproc_onnx) # set input finn datatype to UINT8 - preproc_model.set_tensor_datatype( - preproc_model.graph.input[0].name, DataType["UINT8"] - ) + preproc_model.set_tensor_datatype(preproc_model.graph.input[0].name, DataType["UINT8"]) preproc_model = preproc_model.transform(InferShapes()) preproc_model = preproc_model.transform(FoldConstants()) preproc_model = preproc_model.transform(GiveUniqueNodeNames()) @@ -145,9 +143,7 @@ def test_end2end_mobilenet_export(): @pytest.mark.end2end def test_end2end_mobilenet_tidy_and_merge_with_preproc(): - preproc_model = load_test_checkpoint_or_skip( - build_dir + "/end2end_mobilenet_preproc.onnx" - ) + preproc_model = load_test_checkpoint_or_skip(build_dir + "/end2end_mobilenet_preproc.onnx") model = load_test_checkpoint_or_skip(build_dir + "/end2end_mobilenet_export.onnx") model = model.transform(InferShapes()) model = model.transform(FoldConstants()) @@ -191,17 +187,13 @@ def test_end2end_mobilenet_streamline(): model = model.transform(GiveReadableTensorNames()) model = model.transform(InferDataTypes()) model.save(build_dir + "/end2end_mobilenet_streamlined.onnx") - assert ( - len(model.get_nodes_by_op_type("Add")) == 1 - ) # only final quantized bias Add op remains + assert len(model.get_nodes_by_op_type("Add")) == 1 # only final quantized bias Add op remains assert len(model.get_nodes_by_op_type("Mul")) == 0 # no Mul ops remain @pytest.mark.end2end def test_end2end_mobilenet_lowering(): - model = load_test_checkpoint_or_skip( - build_dir + "/end2end_mobilenet_streamlined.onnx" - ) + model = load_test_checkpoint_or_skip(build_dir + "/end2end_mobilenet_streamlined.onnx") model = model.transform(LowerConvsToMatMul()) model = model.transform(absorb.AbsorbTransposeIntoMultiThreshold()) model = model.transform(absorb.AbsorbConsecutiveTransposes()) @@ -229,9 +221,7 @@ def test_end2end_mobilenet_convert_to_hls_layers(): @pytest.mark.end2end def test_end2end_mobilenet_folding(): - model = load_test_checkpoint_or_skip( - build_dir + "/end2end_mobilenet_hls_layers.onnx" - ) + model = load_test_checkpoint_or_skip(build_dir + "/end2end_mobilenet_hls_layers.onnx") # optional extra folding to use fewer resources # applied while setting the attributes on each node assert extra_fold in [1, 2, 4] diff --git a/tests/fpgadataflow/test_convert_to_hls_1d_conv_layer.py b/tests/fpgadataflow/test_convert_to_hls_1d_conv_layer.py index 98a7c76ee4..2af0957e12 100644 --- a/tests/fpgadataflow/test_convert_to_hls_1d_conv_layer.py +++ b/tests/fpgadataflow/test_convert_to_hls_1d_conv_layer.py @@ -96,12 +96,8 @@ def test_convert_to_hls_1d_conv_layer(conv_config, depthwise, use_rtl_swg, exec_ out_chn = 20 conv_param_shape = [out_chn, in_chn, k_h, k_w] - out_feature_dim_h = compute_conv_output_dim( - in_feature_dim_h, k_h, stride_h, pad_h, dilation_h - ) - out_feature_dim_w = compute_conv_output_dim( - in_feature_dim_w, k_w, stride_w, pad_w, dilation_w - ) + out_feature_dim_h = compute_conv_output_dim(in_feature_dim_h, k_h, stride_h, pad_h, dilation_h) + out_feature_dim_w = compute_conv_output_dim(in_feature_dim_w, k_w, stride_w, pad_w, dilation_w) input_shape = [1, in_chn, in_feature_dim_h, in_feature_dim_w] output_shape = [1, out_chn, out_feature_dim_h, out_feature_dim_w] @@ -117,9 +113,7 @@ def test_convert_to_hls_1d_conv_layer(conv_config, depthwise, use_rtl_swg, exec_ top_in = helper.make_tensor_value_info("top_in", TensorProto.FLOAT, input_shape) top_out = helper.make_tensor_value_info("top_out", TensorProto.FLOAT, output_shape) - value_info = [ - helper.make_tensor_value_info("p1", TensorProto.FLOAT, conv_param_shape) - ] + value_info = [helper.make_tensor_value_info("p1", TensorProto.FLOAT, conv_param_shape)] modelproto = qonnx_make_model( helper.make_graph( @@ -127,9 +121,7 @@ def test_convert_to_hls_1d_conv_layer(conv_config, depthwise, use_rtl_swg, exec_ inputs=[top_in], outputs=[top_out], value_info=value_info, - nodes=[ - helper.make_node("Conv", ["top_in", "p1"], ["top_out"], **conv_config) - ], + nodes=[helper.make_node("Conv", ["top_in", "p1"], ["top_out"], **conv_config)], ) ) diff --git a/tests/fpgadataflow/test_convert_to_hls_channelwise_layer.py b/tests/fpgadataflow/test_convert_to_hls_channelwise_layer.py index 089d1ae420..bb2c1d74c2 100644 --- a/tests/fpgadataflow/test_convert_to_hls_channelwise_layer.py +++ b/tests/fpgadataflow/test_convert_to_hls_channelwise_layer.py @@ -52,7 +52,6 @@ def prepare_inputs(input_tensor): def make_single_maxpool_modelwrapper(onnx_op_name, ishape, idt, pdt, pshape): - inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, ishape) outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, ishape) p0 = helper.make_tensor_value_info("p0", TensorProto.FLOAT, pshape) @@ -76,13 +75,9 @@ def make_single_maxpool_modelwrapper(onnx_op_name, ishape, idt, pdt, pshape): # parameter datatype -@pytest.mark.parametrize( - "pdt", [DataType["BIPOLAR"], DataType["UINT4"], DataType["INT2"]] -) +@pytest.mark.parametrize("pdt", [DataType["BIPOLAR"], DataType["UINT4"], DataType["INT2"]]) # input datatype -@pytest.mark.parametrize( - "idt", [DataType["INT32"], DataType["UINT4"], DataType["INT4"]] -) +@pytest.mark.parametrize("idt", [DataType["INT32"], DataType["UINT4"], DataType["INT4"]]) # function @pytest.mark.parametrize("onnx_op_name", ["Add", "Mul"]) # vector parameter or scalar parameter (broadcast) @@ -92,9 +87,7 @@ def make_single_maxpool_modelwrapper(onnx_op_name, ishape, idt, pdt, pshape): @pytest.mark.fpgadataflow @pytest.mark.vivado @pytest.mark.slow -def test_convert_to_hls_channelwise_layer( - pdt, idt, onnx_op_name, scalar_param, exec_mode -): +def test_convert_to_hls_channelwise_layer(pdt, idt, onnx_op_name, scalar_param, exec_mode): ifm_ch = 16 ifm_dim = 5 ishape = (1, ifm_ch, ifm_dim, ifm_dim) @@ -134,9 +127,7 @@ def test_convert_to_hls_channelwise_layer( else: raise Exception("Unknown exec_mode") - ctx_produced = oxe.execute_onnx( - new_model, input_dict, return_full_exec_context=True - ) + ctx_produced = oxe.execute_onnx(new_model, input_dict, return_full_exec_context=True) y_produced = ctx_produced["outp"] assert (y_produced == y_expected).all() diff --git a/tests/fpgadataflow/test_convert_to_hls_conv_fc_transition.py b/tests/fpgadataflow/test_convert_to_hls_conv_fc_transition.py index 3512c39cb3..94007bdd14 100755 --- a/tests/fpgadataflow/test_convert_to_hls_conv_fc_transition.py +++ b/tests/fpgadataflow/test_convert_to_hls_conv_fc_transition.py @@ -102,12 +102,8 @@ def test_convert_to_hls_conv_fc_transition(conv_config, depthwise, use_reshape): out_chn = 8 conv_param_shape = [out_chn, in_chn, kernel_size_h, kernel_size_w] - output_size_h = compute_conv_output_dim( - input_size_h, kernel_size_h, stride_h, 2 * pad_h - ) - output_size_w = compute_conv_output_dim( - input_size_w, kernel_size_w, stride_w, 2 * pad_w - ) + output_size_h = compute_conv_output_dim(input_size_h, kernel_size_h, stride_h, 2 * pad_h) + output_size_w = compute_conv_output_dim(input_size_w, kernel_size_w, stride_w, 2 * pad_w) input_shape = [1, in_chn, input_size_h, input_size_w] fc_param_shape = [out_chn * output_size_h * output_size_w, fc_filters] @@ -120,34 +116,20 @@ def test_convert_to_hls_conv_fc_transition(conv_config, depthwise, use_reshape): conv_config["pads"] = [pad_h, pad_w, pad_h, pad_w] conv_config["strides"] = [stride_h, stride_w] - global_in = helper.make_tensor_value_info( - "global_in", TensorProto.FLOAT, input_shape - ) - global_out = helper.make_tensor_value_info( - "global_out", TensorProto.FLOAT, output_shape - ) + global_in = helper.make_tensor_value_info("global_in", TensorProto.FLOAT, input_shape) + global_out = helper.make_tensor_value_info("global_out", TensorProto.FLOAT, output_shape) value_info = [ - helper.make_tensor_value_info( - "conv_param", TensorProto.FLOAT, conv_param_shape - ), + helper.make_tensor_value_info("conv_param", TensorProto.FLOAT, conv_param_shape), helper.make_tensor_value_info("thres1_param", TensorProto.FLOAT, (out_chn, 15)), - helper.make_tensor_value_info( - "matmul_param", TensorProto.FLOAT, fc_param_shape - ), - helper.make_tensor_value_info( - "thres2_param", TensorProto.FLOAT, (fc_filters, 15) - ), + helper.make_tensor_value_info("matmul_param", TensorProto.FLOAT, fc_param_shape), + helper.make_tensor_value_info("thres2_param", TensorProto.FLOAT, (fc_filters, 15)), helper.make_tensor_value_info("reshape_shape", TensorProto.INT64, []), ] if use_reshape: - flatten_node = helper.make_node( - "Reshape", ["thres1_out", "reshape_shape"], ["flatten_out"] - ) + flatten_node = helper.make_node("Reshape", ["thres1_out", "reshape_shape"], ["flatten_out"]) else: - flatten_node = helper.make_node( - "Flatten", ["thres1_out"], ["flatten_out"], axis=1 - ) + flatten_node = helper.make_node("Flatten", ["thres1_out"], ["flatten_out"], axis=1) modelproto = qonnx_make_model( helper.make_graph( @@ -156,9 +138,7 @@ def test_convert_to_hls_conv_fc_transition(conv_config, depthwise, use_reshape): outputs=[global_out], value_info=value_info, nodes=[ - helper.make_node( - "Conv", ["global_in", "conv_param"], ["conv_out"], **conv_config - ), + helper.make_node("Conv", ["global_in", "conv_param"], ["conv_out"], **conv_config), helper.make_node( "MultiThreshold", ["conv_out", "thres1_param"], @@ -167,9 +147,7 @@ def test_convert_to_hls_conv_fc_transition(conv_config, depthwise, use_reshape): out_dtype="UINT4", ), flatten_node, - helper.make_node( - "MatMul", ["flatten_out", "matmul_param"], ["matmul_out"] - ), + helper.make_node("MatMul", ["flatten_out", "matmul_param"], ["matmul_out"]), helper.make_node( "MultiThreshold", ["matmul_out", "thres2_param"], @@ -190,18 +168,10 @@ def test_convert_to_hls_conv_fc_transition(conv_config, depthwise, use_reshape): model.set_tensor_datatype("thres1_param", DataType["INT32"]) model.set_tensor_datatype("thres2_param", DataType["INT32"]) - model.set_initializer( - "conv_param", gen_finn_dt_tensor(conv_weight_dt, conv_param_shape) - ) - model.set_initializer( - "thres1_param", get_multithreshold_rand_params(out_chn, 15, seed=0) - ) - model.set_initializer( - "thres2_param", get_multithreshold_rand_params(fc_filters, 15, seed=0) - ) - model.set_initializer( - "matmul_param", gen_finn_dt_tensor(fc_weight_dt, fc_param_shape) - ) + model.set_initializer("conv_param", gen_finn_dt_tensor(conv_weight_dt, conv_param_shape)) + model.set_initializer("thres1_param", get_multithreshold_rand_params(out_chn, 15, seed=0)) + model.set_initializer("thres2_param", get_multithreshold_rand_params(fc_filters, 15, seed=0)) + model.set_initializer("matmul_param", gen_finn_dt_tensor(fc_weight_dt, fc_param_shape)) model.set_initializer("reshape_shape", np.array([1, -1], dtype=np.int64)) model = model.transform(InferShapes()) diff --git a/tests/fpgadataflow/test_convert_to_hls_conv_layer.py b/tests/fpgadataflow/test_convert_to_hls_conv_layer.py index 7b2793712d..95beffafac 100644 --- a/tests/fpgadataflow/test_convert_to_hls_conv_layer.py +++ b/tests/fpgadataflow/test_convert_to_hls_conv_layer.py @@ -82,9 +82,7 @@ def test_convert_to_hls_conv_layer(conv_config, depthwise, use_rtl_swg, exec_mod conv_param_shape = [out_chn, in_chn, kernel_size, kernel_size] total_pad = 2 * pad - out_feature_dim = compute_conv_output_dim( - in_feature_dim, kernel_size, stride, total_pad - ) + out_feature_dim = compute_conv_output_dim(in_feature_dim, kernel_size, stride, total_pad) input_shape = [1, in_chn, in_feature_dim, in_feature_dim] output_shape = [1, out_chn, out_feature_dim, out_feature_dim] @@ -100,9 +98,7 @@ def test_convert_to_hls_conv_layer(conv_config, depthwise, use_rtl_swg, exec_mod top_in = helper.make_tensor_value_info("top_in", TensorProto.FLOAT, input_shape) top_out = helper.make_tensor_value_info("top_out", TensorProto.FLOAT, output_shape) - value_info = [ - helper.make_tensor_value_info("p1", TensorProto.FLOAT, conv_param_shape) - ] + value_info = [helper.make_tensor_value_info("p1", TensorProto.FLOAT, conv_param_shape)] modelproto = qonnx_make_model( helper.make_graph( @@ -110,9 +106,7 @@ def test_convert_to_hls_conv_layer(conv_config, depthwise, use_rtl_swg, exec_mod inputs=[top_in], outputs=[top_out], value_info=value_info, - nodes=[ - helper.make_node("Conv", ["top_in", "p1"], ["top_out"], **conv_config) - ], + nodes=[helper.make_node("Conv", ["top_in", "p1"], ["top_out"], **conv_config)], ) ) diff --git a/tests/fpgadataflow/test_convert_to_hls_layers_cnv.py b/tests/fpgadataflow/test_convert_to_hls_layers_cnv.py index 001c353c8e..296b4cf350 100644 --- a/tests/fpgadataflow/test_convert_to_hls_layers_cnv.py +++ b/tests/fpgadataflow/test_convert_to_hls_layers_cnv.py @@ -38,7 +38,11 @@ from qonnx.custom_op.registry import getCustomOp from qonnx.transformation.bipolar_to_xnor import ConvertBipolarMatMulToXnorPopcount from qonnx.transformation.fold_constants import FoldConstants -from qonnx.transformation.general import GiveReadableTensorNames, GiveUniqueNodeNames, GiveUniqueParameterTensors +from qonnx.transformation.general import ( + GiveReadableTensorNames, + GiveUniqueNodeNames, + GiveUniqueParameterTensors, +) from qonnx.transformation.infer_data_layouts import InferDataLayouts from qonnx.transformation.infer_shapes import InferShapes from qonnx.transformation.lower_convs_to_matmul import LowerConvsToMatMul diff --git a/tests/fpgadataflow/test_convert_to_hls_layers_fc.py b/tests/fpgadataflow/test_convert_to_hls_layers_fc.py index 0fa7155ac5..e9caeddb44 100644 --- a/tests/fpgadataflow/test_convert_to_hls_layers_fc.py +++ b/tests/fpgadataflow/test_convert_to_hls_layers_fc.py @@ -39,7 +39,11 @@ from qonnx.custom_op.registry import getCustomOp from qonnx.transformation.bipolar_to_xnor import ConvertBipolarMatMulToXnorPopcount from qonnx.transformation.fold_constants import FoldConstants -from qonnx.transformation.general import GiveReadableTensorNames, GiveUniqueNodeNames, GiveUniqueParameterTensors +from qonnx.transformation.general import ( + GiveReadableTensorNames, + GiveUniqueNodeNames, + GiveUniqueParameterTensors, +) from qonnx.transformation.infer_shapes import InferShapes import finn.core.onnx_exec as oxe diff --git a/tests/fpgadataflow/test_convert_to_hls_layers_synthetic.py b/tests/fpgadataflow/test_convert_to_hls_layers_synthetic.py index c837a46a7c..f8e566156b 100644 --- a/tests/fpgadataflow/test_convert_to_hls_layers_synthetic.py +++ b/tests/fpgadataflow/test_convert_to_hls_layers_synthetic.py @@ -91,21 +91,11 @@ def make_model(ch, ifmdim): add0_node = helper.make_node("Add", [inp.name, inp1_add0_ct.name], ["out_add0"]) add1_node = helper.make_node("Add", ["out_add0", inp1_add_ct.name], [inp1_add.name]) add2_node = helper.make_node("Add", ["out_add0", inp2_add_ct.name], [inp2_add.name]) - mul1_node = helper.make_node( - "Mul", [inp1_add.name, inp1_mul_ct.name], [inp1_mul.name] - ) - mul2_node = helper.make_node( - "Mul", [inp2_add.name, inp2_mul_ct.name], [inp2_mul.name] - ) - eltwise_add_node = helper.make_node( - "Add", [inp1_mul.name, inp2_mul.name], [eltwise_add.name] - ) - globalavgpool_node = helper.make_node( - "GlobalAveragePool", [eltwise_add.name], [pool.name] - ) - reshape_node = helper.make_node( - "Reshape", [pool.name, reshape_ct.name], [outp.name] - ) + mul1_node = helper.make_node("Mul", [inp1_add.name, inp1_mul_ct.name], [inp1_mul.name]) + mul2_node = helper.make_node("Mul", [inp2_add.name, inp2_mul_ct.name], [inp2_mul.name]) + eltwise_add_node = helper.make_node("Add", [inp1_mul.name, inp2_mul.name], [eltwise_add.name]) + globalavgpool_node = helper.make_node("GlobalAveragePool", [eltwise_add.name], [pool.name]) + reshape_node = helper.make_node("Reshape", [pool.name, reshape_ct.name], [outp.name]) graph = helper.make_graph( nodes=[ diff --git a/tests/fpgadataflow/test_convert_to_hls_pool_batch.py b/tests/fpgadataflow/test_convert_to_hls_pool_batch.py index 6d628c9e53..417b4fbae2 100644 --- a/tests/fpgadataflow/test_convert_to_hls_pool_batch.py +++ b/tests/fpgadataflow/test_convert_to_hls_pool_batch.py @@ -48,9 +48,7 @@ from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode -def make_single_maxpool_modelwrapper( - k, stride, pad, ifm_ch, ifm_dim, ofm_dim, idt, use_1d=False -): +def make_single_maxpool_modelwrapper(k, stride, pad, ifm_ch, ifm_dim, ofm_dim, idt, use_1d=False): odt = idt if use_1d: ishape = [1, ifm_ch, 1, ifm_dim] @@ -74,9 +72,7 @@ def make_single_maxpool_modelwrapper( pads=pads, strides=strides, ) - graph = helper.make_graph( - nodes=[mp_node], name="mp_graph", inputs=[inp], outputs=[outp] - ) + graph = helper.make_graph(nodes=[mp_node], name="mp_graph", inputs=[inp], outputs=[outp]) model = qonnx_make_model(graph, producer_name="mp-model") model = ModelWrapper(model) @@ -89,12 +85,8 @@ def make_single_maxpool_modelwrapper( def make_single_quantavpool_modelwrapper(k, stride, ifm_ch, ifm_dim, ofm_dim, idt, odt): - inp = helper.make_tensor_value_info( - "inp", TensorProto.FLOAT, [1, ifm_ch, ifm_dim, ifm_dim] - ) - outp = helper.make_tensor_value_info( - "outp", TensorProto.FLOAT, [1, ifm_ch, ofm_dim, ofm_dim] - ) + inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, [1, ifm_ch, ifm_dim, ifm_dim]) + outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, [1, ifm_ch, ofm_dim, ofm_dim]) mp_node = helper.make_node( "QuantAvgPool2d", @@ -108,9 +100,7 @@ def make_single_quantavpool_modelwrapper(k, stride, ifm_ch, ifm_dim, ofm_dim, id signed=1 if idt.signed() else 0, data_layout="NCHW", ) - graph = helper.make_graph( - nodes=[mp_node], name="mp_graph", inputs=[inp], outputs=[outp] - ) + graph = helper.make_graph(nodes=[mp_node], name="mp_graph", inputs=[inp], outputs=[outp]) model = qonnx_make_model(graph, producer_name="mp-model") model = ModelWrapper(model) @@ -143,9 +133,7 @@ def prepare_inputs(input_tensor): @pytest.mark.fpgadataflow @pytest.mark.slow @pytest.mark.vivado -def test_convert_to_hls_pool_batch( - idt, odt, pool_config, ifm_ch, pe, op_type, exec_mode -): +def test_convert_to_hls_pool_batch(idt, odt, pool_config, ifm_ch, pe, op_type, exec_mode): k, stride, pad, ifm_dim = pool_config if ifm_ch % pe != 0: @@ -184,9 +172,7 @@ def test_convert_to_hls_pool_batch( if idt.signed() != odt.signed(): pytest.skip("Skipping QuantAvgPool2d with idt.signed() != odt.signed()") - model = make_single_quantavpool_modelwrapper( - k, stride, ifm_ch, ifm_dim, ofm_dim, idt, odt - ) + model = make_single_quantavpool_modelwrapper(k, stride, ifm_ch, ifm_dim, ofm_dim, idt, odt) else: assert False, "{} is not a supported op_type".format(op_type) @@ -209,18 +195,14 @@ def test_convert_to_hls_pool_batch( if pad == 0: assert len(new_model.graph.node) == 4 assert new_model.graph.node[0].op_type == "Transpose" - assert new_model.graph.node[1].op_type.startswith( - "ConvolutionInputGenerator" - ) + assert new_model.graph.node[1].op_type.startswith("ConvolutionInputGenerator") assert new_model.graph.node[2].op_type == "Pool_Batch" assert new_model.graph.node[3].op_type == "Transpose" else: assert len(new_model.graph.node) == 5 assert new_model.graph.node[0].op_type == "Transpose" assert new_model.graph.node[1].op_type == "FMPadding_Batch" - assert new_model.graph.node[2].op_type.startswith( - "ConvolutionInputGenerator" - ) + assert new_model.graph.node[2].op_type.startswith("ConvolutionInputGenerator") assert new_model.graph.node[3].op_type == "Pool_Batch" assert new_model.graph.node[4].op_type == "Transpose" else: diff --git a/tests/fpgadataflow/test_depthwise_convolution.py b/tests/fpgadataflow/test_depthwise_convolution.py index 8ab22bcfdc..2ffd696528 100644 --- a/tests/fpgadataflow/test_depthwise_convolution.py +++ b/tests/fpgadataflow/test_depthwise_convolution.py @@ -57,7 +57,6 @@ def set_up_reference_model(act, idt, wdt, k, ifm_dim, ifm_ch, stride, padding): - # set up reference model consisting of Im2Col + MatMul (+ MultiThreshold) ofm_ch = ifm_ch total_pad = 2 * padding @@ -84,16 +83,10 @@ def set_up_reference_model(act, idt, wdt, k, ifm_dim, ifm_ch, stride, padding): ) # set up onnx model - inp = oh.make_tensor_value_info( - "inp", TensorProto.FLOAT, [1, ifm_dim, ifm_dim, ifm_ch] - ) - outp = oh.make_tensor_value_info( - "outp", TensorProto.FLOAT, [1, ofm_dim, ofm_dim, ofm_ch] - ) + inp = oh.make_tensor_value_info("inp", TensorProto.FLOAT, [1, ifm_dim, ifm_dim, ifm_ch]) + outp = oh.make_tensor_value_info("outp", TensorProto.FLOAT, [1, ofm_dim, ofm_dim, ofm_ch]) - W_sparse = oh.make_tensor_value_info( - "W_sparse", TensorProto.FLOAT, [ifm_ch * k * k, ofm_ch] - ) + W_sparse = oh.make_tensor_value_info("W_sparse", TensorProto.FLOAT, [ifm_ch * k * k, ofm_ch]) im2col_node = oh.make_node( "Im2Col", @@ -107,9 +100,7 @@ def set_up_reference_model(act, idt, wdt, k, ifm_dim, ifm_ch, stride, padding): depthwise=1, ) - matmul_node = oh.make_node( - "MatMul", inputs=["im2col_out", "W_sparse"], outputs=["outp"] - ) + matmul_node = oh.make_node("MatMul", inputs=["im2col_out", "W_sparse"], outputs=["outp"]) if act is None: node_list = [im2col_node, matmul_node] diff --git a/tests/fpgadataflow/test_fifosizing.py b/tests/fpgadataflow/test_fifosizing.py index 922232c2c2..f3716dea9b 100644 --- a/tests/fpgadataflow/test_fifosizing.py +++ b/tests/fpgadataflow/test_fifosizing.py @@ -84,8 +84,7 @@ def test_fifosizing_linear(method, topology): with open(tmp_output_dir + "/report/rtlsim_performance.json") as f: sim_data = json.load(f) assert ( - float(sim_data["stable_throughput[images/s]"]) - / float(est_data["estimated_throughput_fps"]) + float(sim_data["stable_throughput[images/s]"]) / float(est_data["estimated_throughput_fps"]) > 0.9 ) # now run the same build using the generated folding and FIFO config @@ -98,12 +97,8 @@ def test_fifosizing_linear(method, topology): cfg_cmp.folding_config_file = tmp_output_dir + "/final_hw_config.json" build.build_dataflow_cfg(tmp_output_dir_cmp + "/model.onnx", cfg_cmp) - model0 = ModelWrapper( - tmp_output_dir + "/intermediate_models/step_create_stitched_ip.onnx" - ) - model1 = ModelWrapper( - tmp_output_dir_cmp + "/intermediate_models/step_create_stitched_ip.onnx" - ) + model0 = ModelWrapper(tmp_output_dir + "/intermediate_models/step_create_stitched_ip.onnx") + model1 = ModelWrapper(tmp_output_dir_cmp + "/intermediate_models/step_create_stitched_ip.onnx") assert len(model0.graph.node) == len(model1.graph.node) for i in range(len(model0.graph.node)): diff --git a/tests/fpgadataflow/test_fpgadataflow_channelwise_ops.py b/tests/fpgadataflow/test_fpgadataflow_channelwise_ops.py index 13fab9a47f..186a6af42c 100644 --- a/tests/fpgadataflow/test_fpgadataflow_channelwise_ops.py +++ b/tests/fpgadataflow/test_fpgadataflow_channelwise_ops.py @@ -51,9 +51,7 @@ def make_modelwrapper(C, pe, idt, odt, pdt, func, vecs): NumChannels = C.shape[0] inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, vecs + [NumChannels]) - outp = helper.make_tensor_value_info( - "outp", TensorProto.FLOAT, vecs + [NumChannels] - ) + outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, vecs + [NumChannels]) node_inp_list = ["inp", "const"] diff --git a/tests/fpgadataflow/test_fpgadataflow_checksum.py b/tests/fpgadataflow/test_fpgadataflow_checksum.py index cd404f5a63..403bb328ae 100644 --- a/tests/fpgadataflow/test_fpgadataflow_checksum.py +++ b/tests/fpgadataflow/test_fpgadataflow_checksum.py @@ -215,11 +215,7 @@ def write_drain(sim): ), """The second checksums do not match in cppsim vs. rtlsim""" - assert ( - checksum0_drain == 0 - ), "Drain read doesn't match drain write for first checksum" - assert ( - checksum1_drain == 0 - ), "Drain read doesn't match drain write for second checksum" + assert checksum0_drain == 0, "Drain read doesn't match drain write for first checksum" + assert checksum1_drain == 0, "Drain read doesn't match drain write for second checksum" # TODO: test for drain set to true diff --git a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py index 3cfff9ac34..d94b5d6399 100644 --- a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py +++ b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py @@ -46,13 +46,9 @@ from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode -def make_single_im2col_modelwrapper( - k, ifm_ch, ifm_dim, ofm_dim, simd, stride, dilation, idt -): +def make_single_im2col_modelwrapper(k, ifm_ch, ifm_dim, ofm_dim, simd, stride, dilation, idt): odt = idt - inp = helper.make_tensor_value_info( - "inp", TensorProto.FLOAT, [1, ifm_dim, ifm_dim, ifm_ch] - ) + inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, [1, ifm_dim, ifm_dim, ifm_ch]) outp = helper.make_tensor_value_info( "outp", TensorProto.FLOAT, [1, ofm_dim, ofm_dim, k * k * ifm_ch] ) @@ -86,9 +82,7 @@ def make_single_slidingwindow_modelwrapper( k, ifm_ch, ifm_dim, ofm_dim, simd, stride, dilation, idt, dw=0 ): odt = idt - inp = helper.make_tensor_value_info( - "inp", TensorProto.FLOAT, [1, ifm_dim, ifm_dim, ifm_ch] - ) + inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, [1, ifm_dim, ifm_dim, ifm_ch]) outp = helper.make_tensor_value_info( "outp", TensorProto.FLOAT, [1, ofm_dim, ofm_dim, k * k * ifm_ch] ) @@ -152,9 +146,7 @@ def prepare_inputs(input_tensor): @pytest.mark.fpgadataflow @pytest.mark.slow @pytest.mark.vivado -def test_fpgadataflow_slidingwindow( - idt, k, ifm_dim, ifm_ch, stride, dilation, exec_mode, simd, dw -): +def test_fpgadataflow_slidingwindow(idt, k, ifm_dim, ifm_ch, stride, dilation, exec_mode, simd, dw): ofm_dim = int(((ifm_dim - k) / stride) + 1) x = gen_finn_dt_tensor(idt, (1, ifm_dim, ifm_dim, ifm_ch)) @@ -187,9 +179,7 @@ def test_fpgadataflow_slidingwindow( if dw == 0: assert (y_produced == y_expected).all() else: - y_expected = y_expected.reshape( - 1, ofm_dim, ofm_dim, k * k, ifm_ch // simd, simd - ) + y_expected = y_expected.reshape(1, ofm_dim, ofm_dim, k * k, ifm_ch // simd, simd) y_expected = y_expected.transpose(0, 1, 2, 4, 3, 5) y_expected = y_expected.reshape(1, ofm_dim, ofm_dim, ifm_ch * k * k) assert (y_produced == y_expected).all() diff --git a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator1d.py b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator1d.py index f467f37618..aa89dde5e7 100644 --- a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator1d.py +++ b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator1d.py @@ -49,9 +49,7 @@ fpga_part = "xczu3eg-sbva484-1-e" -def make_single_im2col_modelwrapper( - k, ifm_ch, ifm_dim, ofm_dim, simd, stride, dilation, idt -): +def make_single_im2col_modelwrapper(k, ifm_ch, ifm_dim, ofm_dim, simd, stride, dilation, idt): k_h, k_w = k ifm_dim_h, ifm_dim_w = ifm_dim stride_h, stride_w = stride @@ -59,9 +57,7 @@ def make_single_im2col_modelwrapper( ofm_dim_h, ofm_dim_w = ofm_dim odt = idt - inp = helper.make_tensor_value_info( - "inp", TensorProto.FLOAT, [1, ifm_dim_h, ifm_dim_w, ifm_ch] - ) + inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, [1, ifm_dim_h, ifm_dim_w, ifm_ch]) outp = helper.make_tensor_value_info( "outp", TensorProto.FLOAT, [1, ofm_dim_h, ofm_dim_w, k_h * k_w * ifm_ch] ) @@ -101,9 +97,7 @@ def make_single_slidingwindow_modelwrapper( ofm_dim_h, ofm_dim_w = ofm_dim odt = idt - inp = helper.make_tensor_value_info( - "inp", TensorProto.FLOAT, [1, ifm_dim_h, ifm_dim_w, ifm_ch] - ) + inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, [1, ifm_dim_h, ifm_dim_w, ifm_ch]) outp = helper.make_tensor_value_info( "outp", TensorProto.FLOAT, [1, ofm_dim_h, ofm_dim_w, k_h * k_w * ifm_ch] ) @@ -259,9 +253,7 @@ def test_fpgadataflow_slidingwindow_1d( if dw == 0: assert (y_produced == y_expected).all() else: - y_expected = y_expected.reshape( - 1, ofm_dim_h, ofm_dim_w, k_h * k_w, ifm_ch // simd, simd - ) + y_expected = y_expected.reshape(1, ofm_dim_h, ofm_dim_w, k_h * k_w, ifm_ch // simd, simd) y_expected = y_expected.transpose(0, 1, 2, 4, 3, 5) y_expected = y_expected.reshape(1, ofm_dim_h, ofm_dim_w, ifm_ch * k_h * k_w) assert (y_produced == y_expected).all() diff --git a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py index e8236c0c6b..53d7be0ebb 100755 --- a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py +++ b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py @@ -49,9 +49,7 @@ def make_single_im2col_modelwrapper(k, ifm_ch, ifm_dim, ofm_dim, stride, dilatio ofm_dim_h, ofm_dim_w = ofm_dim odt = idt - inp = helper.make_tensor_value_info( - "inp", TensorProto.FLOAT, [1, ifm_dim_h, ifm_dim_w, ifm_ch] - ) + inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, [1, ifm_dim_h, ifm_dim_w, ifm_ch]) outp = helper.make_tensor_value_info( "outp", TensorProto.FLOAT, [1, ofm_dim_h, ofm_dim_w, k_h * k_w * ifm_ch] ) @@ -91,9 +89,7 @@ def make_single_slidingwindow_modelwrapper( ofm_dim_h, ofm_dim_w = ofm_dim odt = idt - inp = helper.make_tensor_value_info( - "inp", TensorProto.FLOAT, [1, ifm_dim_h, ifm_dim_w, ifm_ch] - ) + inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, [1, ifm_dim_h, ifm_dim_w, ifm_ch]) outp = helper.make_tensor_value_info( "outp", TensorProto.FLOAT, [1, ofm_dim_h, ofm_dim_w, k_h * k_w * ifm_ch] ) @@ -191,21 +187,13 @@ def test_fpgadataflow_slidingwindow_rtl( if ifm_ch % simd != 0: pytest.skip("SIMD must divide number of input channels") if kernel_height > ifm_dim_h or stride_h > ifm_dim_h: - pytest.skip( - "Illegal convolution configuration: kernel or stride > FM dimension" - ) + pytest.skip("Illegal convolution configuration: kernel or stride > FM dimension") if kernel_width > ifm_dim_w or stride_w > ifm_dim_w: - pytest.skip( - "Illegal convolution configuration: kernel or stride > FM dimension" - ) + pytest.skip("Illegal convolution configuration: kernel or stride > FM dimension") if (k_h == 1 and dilation_h != 1) or (k_w == 1 and dilation_w != 1): - pytest.skip( - "Illegal convolution configuration: dilation for unitary kernel dim" - ) + pytest.skip("Illegal convolution configuration: dilation for unitary kernel dim") if (stride_h > k_h) or (stride_w > k_w) and not parallel_window: - pytest.skip( - "Not all combinations for stride > k edge case supported in default mode" - ) + pytest.skip("Not all combinations for stride > k edge case supported in default mode") if k_h == 1 and k_w == 1 and simd != ifm_ch: pytest.skip("1x1 Kernel only supported in parallel mode (SIMD=C)") if parallel_window and simd != ifm_ch: @@ -253,9 +241,7 @@ def test_fpgadataflow_slidingwindow_rtl( if dw == 0: assert (y_produced == y_expected).all() else: - y_expected = y_expected.reshape( - 1, ofm_dim_h, ofm_dim_w, k_h * k_w, ifm_ch // simd, simd - ) + y_expected = y_expected.reshape(1, ofm_dim_h, ofm_dim_w, k_h * k_w, ifm_ch // simd, simd) y_expected = y_expected.transpose(0, 1, 2, 4, 3, 5) y_expected = y_expected.reshape(1, ofm_dim_h, ofm_dim_w, ifm_ch * k_h * k_w) assert (y_produced == y_expected).all() diff --git a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py index e586984b31..f5a06316e2 100644 --- a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py +++ b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py @@ -63,32 +63,18 @@ from finn.util.basic import pyverilate_get_liveness_threshold_cycles -def create_conv_model( - idim_h, idim_w, ifm, k, stride, ofm, idt, wdt, pad_mode, depthwise -): +def create_conv_model(idim_h, idim_w, ifm, k, stride, ofm, idt, wdt, pad_mode, depthwise): np.random.seed(0) group = ifm if depthwise else 1 group_str = str(group) ishp = (1, ifm, idim_h, idim_w) - pad_0 = _auto_pad_to_explicit_padding( - pad_mode, idim_h, idim_w, k, k, stride, stride, 2 - ) - int_dim_h = compute_conv_output_dim( - idim_h, k, stride, total_pad=pad_0[0] + pad_0[2] - ) - int_dim_w = compute_conv_output_dim( - idim_w, k, stride, total_pad=pad_0[1] + pad_0[3] - ) + pad_0 = _auto_pad_to_explicit_padding(pad_mode, idim_h, idim_w, k, k, stride, stride, 2) + int_dim_h = compute_conv_output_dim(idim_h, k, stride, total_pad=pad_0[0] + pad_0[2]) + int_dim_w = compute_conv_output_dim(idim_w, k, stride, total_pad=pad_0[1] + pad_0[3]) - pad_1 = _auto_pad_to_explicit_padding( - pad_mode, int_dim_h, int_dim_w, k, k, stride, stride, 2 - ) - odim_h = compute_conv_output_dim( - int_dim_h, k, stride, total_pad=pad_1[0] + pad_1[2] - ) - odim_w = compute_conv_output_dim( - int_dim_w, k, stride, total_pad=pad_1[1] + pad_1[3] - ) + pad_1 = _auto_pad_to_explicit_padding(pad_mode, int_dim_h, int_dim_w, k, k, stride, stride, 2) + odim_h = compute_conv_output_dim(int_dim_h, k, stride, total_pad=pad_1[0] + pad_1[2]) + odim_w = compute_conv_output_dim(int_dim_w, k, stride, total_pad=pad_1[1] + pad_1[3]) oshp = (1, ifm, odim_h, odim_w) if depthwise else (1, ofm, odim_h, odim_w) wshp = (ifm, 1, k, k) if depthwise else (ofm, ifm, k, k) wshp_1 = (ifm, 1, k, k) if depthwise else (ofm, ofm, k, k) @@ -263,15 +249,11 @@ def test_fpgadataflow_conv_dynamic(cfg): # convert to hardware and prepare simulation model = largest_model.transform(LowerConvsToMatMul()) model = model.transform(to_hls.InferConvInpGen(use_rtl_variant=True)) - model = model.transform( - to_hls.InferQuantizedMatrixVectorActivation(mem_mode="decoupled") - ) + model = model.transform(to_hls.InferQuantizedMatrixVectorActivation(mem_mode="decoupled")) model = model.transform(to_hls.InferVectorVectorActivation()) model = model.transform(absorb.AbsorbConsecutiveTransposes()) parent_model = model.transform(CreateDataflowPartition()) - sdp_inst = getCustomOp( - parent_model.get_nodes_by_op_type("StreamingDataflowPartition")[0] - ) + sdp_inst = getCustomOp(parent_model.get_nodes_by_op_type("StreamingDataflowPartition")[0]) model = ModelWrapper(sdp_inst.get_nodeattr("model")) assert len(model.get_nodes_by_op_type("ConvolutionInputGenerator_rtl")) == 2 if pad_mode == "VALID": @@ -331,15 +313,11 @@ def test_fpgadataflow_conv_dynamic(cfg): pad_nodes = model.get_nodes_by_op_type("FMPadding_rtl") padder0 = getCustomOp(pad_nodes[0]) update_tensor_dim(model, padder0.onnx_node.input[0], (idim_h, idim_w)) - update_tensor_dim( - model, padder0.onnx_node.output[0], (conv0_idim_h, conv0_idim_w) - ) + update_tensor_dim(model, padder0.onnx_node.output[0], (conv0_idim_h, conv0_idim_w)) pad_config0 = padder0.get_dynamic_config((idim_h, idim_w), pad0) padder1 = getCustomOp(pad_nodes[1]) update_tensor_dim(model, padder1.onnx_node.input[0], (int_dim_h, int_dim_w)) - update_tensor_dim( - model, padder1.onnx_node.output[0], (conv1_idim_h, conv1_idim_w) - ) + update_tensor_dim(model, padder1.onnx_node.output[0], (conv1_idim_h, conv1_idim_w)) pad_config1 = padder1.get_dynamic_config((int_dim_h, int_dim_w), pad1) configs = [ ("s_axilite_0_", pad_config0), @@ -380,9 +358,7 @@ def make_single_im2col_modelwrapper(k, ifm_ch, ifm_dim, ofm_dim, stride, dilatio ofm_dim_h, ofm_dim_w = ofm_dim odt = idt - inp = helper.make_tensor_value_info( - "inp", TensorProto.FLOAT, [1, ifm_dim_h, ifm_dim_w, ifm_ch] - ) + inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, [1, ifm_dim_h, ifm_dim_w, ifm_ch]) outp = helper.make_tensor_value_info( "outp", TensorProto.FLOAT, [1, ofm_dim_h, ofm_dim_w, k_h * k_w * ifm_ch] ) @@ -422,9 +398,7 @@ def make_single_slidingwindow_modelwrapper( ofm_dim_h, ofm_dim_w = ofm_dim odt = idt - inp = helper.make_tensor_value_info( - "inp", TensorProto.FLOAT, [1, ifm_dim_h, ifm_dim_w, ifm_ch] - ) + inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, [1, ifm_dim_h, ifm_dim_w, ifm_ch]) outp = helper.make_tensor_value_info( "outp", TensorProto.FLOAT, [1, ofm_dim_h, ofm_dim_w, k_h * k_w * ifm_ch] ) @@ -515,13 +489,9 @@ def test_fpgadataflow_slidingwindow_rtl_dynamic( if ifm_ch % simd != 0: pytest.skip("SIMD must divide number of input channels") if kernel_height > ifm_dim_h or stride_h > ifm_dim_h: - pytest.skip( - "Illegal convolution configuration: kernel or stride > FM dimension" - ) + pytest.skip("Illegal convolution configuration: kernel or stride > FM dimension") if kernel_width > ifm_dim_w or stride_w > ifm_dim_w: - pytest.skip( - "Illegal convolution configuration: kernel or stride > FM dimension" - ) + pytest.skip("Illegal convolution configuration: kernel or stride > FM dimension") if (k_h == 1 and (stride_h != 1 or dilation_h != 1)) or ( k_w == 1 and (stride_w != 1 or dilation_w != 1) ): diff --git a/tests/fpgadataflow/test_fpgadataflow_downsampler.py b/tests/fpgadataflow/test_fpgadataflow_downsampler.py index 64da0a2368..8a3c1fe682 100644 --- a/tests/fpgadataflow/test_fpgadataflow_downsampler.py +++ b/tests/fpgadataflow/test_fpgadataflow_downsampler.py @@ -122,9 +122,7 @@ def test_fpgadataflow_downsampler(is_1d, flip_1d, exec_mode): stride = 2 dt_in = DataType["UINT8"] dt_w = DataType["INT2"] - model = build_model( - is_1d, in_dim, k, stride, dt_in, dt_w, pad_half=0, flip_1d=flip_1d - ) + model = build_model(is_1d, in_dim, k, stride, dt_in, dt_w, pad_half=0, flip_1d=flip_1d) inp = gen_finn_dt_tensor(dt_in, model.get_tensor_shape("in0")) idict = {"in0": inp} y_expected = execute_onnx(model, idict)["out0"] diff --git a/tests/fpgadataflow/test_fpgadataflow_duplicatestreams.py b/tests/fpgadataflow/test_fpgadataflow_duplicatestreams.py index 441bbce50a..27bab93fb6 100644 --- a/tests/fpgadataflow/test_fpgadataflow_duplicatestreams.py +++ b/tests/fpgadataflow/test_fpgadataflow_duplicatestreams.py @@ -56,9 +56,7 @@ def make_dupstreams_modelwrapper(ch, pe, idim, idt, n_dupl): for i in range(n_dupl): outp_name = "outp%d" % i out_names.append(outp_name) - out_vi.append( - helper.make_tensor_value_info(outp_name, TensorProto.FLOAT, shape) - ) + out_vi.append(helper.make_tensor_value_info(outp_name, TensorProto.FLOAT, shape)) dupstrm_node = helper.make_node( "DuplicateStreams_Batch", @@ -72,9 +70,7 @@ def make_dupstreams_modelwrapper(ch, pe, idim, idt, n_dupl): inputDataType=idt.name, numInputVectors=[1, idim, idim], ) - graph = helper.make_graph( - nodes=[dupstrm_node], name="graph", inputs=[inp], outputs=out_vi - ) + graph = helper.make_graph(nodes=[dupstrm_node], name="graph", inputs=[inp], outputs=out_vi) model = qonnx_make_model(graph, producer_name="addstreams-model") model = ModelWrapper(model) diff --git a/tests/fpgadataflow/test_fpgadataflow_dwc.py b/tests/fpgadataflow/test_fpgadataflow_dwc.py index 2bde148a14..eb6e0651d9 100644 --- a/tests/fpgadataflow/test_fpgadataflow_dwc.py +++ b/tests/fpgadataflow/test_fpgadataflow_dwc.py @@ -42,7 +42,6 @@ def make_single_dwc_modelwrapper(shape, inWidth, outWidth, finn_dtype, impl_style): - inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, shape) outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, shape) @@ -59,9 +58,7 @@ def make_single_dwc_modelwrapper(shape, inWidth, outWidth, finn_dtype, impl_styl impl_style=impl_style, ) - graph = helper.make_graph( - nodes=[DWC_node], name="dwc_graph", inputs=[inp], outputs=[outp] - ) + graph = helper.make_graph(nodes=[DWC_node], name="dwc_graph", inputs=[inp], outputs=[outp]) model = qonnx_make_model(graph, producer_name="dwc-model") model = ModelWrapper(model) @@ -99,9 +96,7 @@ def test_fpgadataflow_dwc_rtlsim(config): x = gen_finn_dt_tensor(finn_dtype, shape) input_dict = prepare_inputs(x, finn_dtype) - model = make_single_dwc_modelwrapper( - shape, inWidth, outWidth, finn_dtype, impl_style - ) + model = make_single_dwc_modelwrapper(shape, inWidth, outWidth, finn_dtype, impl_style) model = model.transform(InsertFIFO(create_shallow_fifos=True)) model = model.transform(GiveUniqueNodeNames()) model = model.transform(PrepareIP(test_fpga_part, 5)) diff --git a/tests/fpgadataflow/test_fpgadataflow_fifo.py b/tests/fpgadataflow/test_fpgadataflow_fifo.py index efdb3bf6aa..27417a78e1 100644 --- a/tests/fpgadataflow/test_fpgadataflow_fifo.py +++ b/tests/fpgadataflow/test_fpgadataflow_fifo.py @@ -47,7 +47,6 @@ def make_single_fifo_modelwrapper(Shape, Depth, fld_shape, finn_dtype): - inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, Shape) outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, Shape) @@ -62,9 +61,7 @@ def make_single_fifo_modelwrapper(Shape, Depth, fld_shape, finn_dtype): dataType=str(finn_dtype.name), ) - graph = helper.make_graph( - nodes=[FIFO_node], name="fifo_graph", inputs=[inp], outputs=[outp] - ) + graph = helper.make_graph(nodes=[FIFO_node], name="fifo_graph", inputs=[inp], outputs=[outp]) model = qonnx_make_model(graph, producer_name="fifo-model") model = ModelWrapper(model) @@ -91,7 +88,6 @@ def prepare_inputs(input_tensor, dt): @pytest.mark.slow @pytest.mark.vivado def test_fpgadataflow_fifo_rtlsim(Shape, folded_shape, depth, finn_dtype): - # generate input data x = gen_finn_dt_tensor(finn_dtype, Shape) input_dict = prepare_inputs(x, finn_dtype) diff --git a/tests/fpgadataflow/test_fpgadataflow_fmpadding.py b/tests/fpgadataflow/test_fpgadataflow_fmpadding.py index b95409fda8..c871811c5e 100644 --- a/tests/fpgadataflow/test_fpgadataflow_fmpadding.py +++ b/tests/fpgadataflow/test_fpgadataflow_fmpadding.py @@ -62,12 +62,8 @@ def make_single_fmpadding_modelwrapper(optype, idim, padding, num_ch, simd, idt) odim_h = idim_h + pad_h odim_w = idim_w + pad_w - inp = helper.make_tensor_value_info( - "inp", TensorProto.FLOAT, [1, idim_h, idim_w, num_ch] - ) - outp = helper.make_tensor_value_info( - "outp", TensorProto.FLOAT, [1, odim_h, odim_w, num_ch] - ) + inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, [1, idim_h, idim_w, num_ch]) + outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, [1, odim_h, odim_w, num_ch]) FMPadding = helper.make_node( optype, @@ -99,9 +95,7 @@ def make_single_fmpadding_modelwrapper(optype, idim, padding, num_ch, simd, idt) # input image dimension @pytest.mark.parametrize("idim", [[8, 8], [10, 8]]) # number of rows and number of cols to add -@pytest.mark.parametrize( - "pad", [[1, 1, 1, 1], [1, 1, 2, 2], [1, 3, 2, 3], [7, 0, 8, 0]] -) +@pytest.mark.parametrize("pad", [[1, 1, 1, 1], [1, 1, 2, 2], [1, 3, 2, 3], [7, 0, 8, 0]]) # number of channels @pytest.mark.parametrize("num_ch", [2, 4]) # Input parallelism @@ -149,9 +143,7 @@ def test_fpgadataflow_fmpadding(idim, pad, num_ch, simd, idt, mode, impl_style): expected_oshape = (1, odim_h, odim_w, num_ch) assert y_produced.shape == expected_oshape - y_expected = np.pad( - x, ((0, 0), (pad[0], pad[2]), (pad[1], pad[3]), (0, 0)), "constant" - ) + y_expected = np.pad(x, ((0, 0), (pad[0], pad[2]), (pad[1], pad[3]), (0, 0)), "constant") assert (y_produced == y_expected).all() diff --git a/tests/fpgadataflow/test_fpgadataflow_globalaccpool.py b/tests/fpgadataflow/test_fpgadataflow_globalaccpool.py index a2c3d09a55..1b3d87c11f 100644 --- a/tests/fpgadataflow/test_fpgadataflow_globalaccpool.py +++ b/tests/fpgadataflow/test_fpgadataflow_globalaccpool.py @@ -61,9 +61,7 @@ def make_accpool_modelwrapper(ch, pe, idim, idt): inputDataType=idt.name, numInputVectors=[1, idim, idim], ) - graph = helper.make_graph( - nodes=[accpool_node], name="graph", inputs=[inp], outputs=[outp] - ) + graph = helper.make_graph(nodes=[accpool_node], name="graph", inputs=[inp], outputs=[outp]) model = qonnx_make_model(graph, producer_name="thresholding-model") model = ModelWrapper(model) diff --git a/tests/fpgadataflow/test_fpgadataflow_ipstitch.py b/tests/fpgadataflow/test_fpgadataflow_ipstitch.py index 7e4069f5c4..2d85cc98f4 100644 --- a/tests/fpgadataflow/test_fpgadataflow_ipstitch.py +++ b/tests/fpgadataflow/test_fpgadataflow_ipstitch.py @@ -96,9 +96,7 @@ def create_one_fc_model(mem_mode="const"): mem_mode=mem_mode, ) - graph = helper.make_graph( - nodes=[fc0], name="fclayer_graph", inputs=[inp], outputs=[outp] - ) + graph = helper.make_graph(nodes=[fc0], name="fclayer_graph", inputs=[inp], outputs=[outp]) model = qonnx_make_model(graph, producer_name="fclayer-model") model = ModelWrapper(model) @@ -212,9 +210,7 @@ def test_fpgadataflow_ipstitch_gen_model(mem_mode): model = model.transform(HLSSynthIP()) assert model.graph.node[0].op_type == "MatrixVectorActivation" assert model.graph.node[-1].op_type == "TLastMarker" - model.save( - ip_stitch_model_dir + "/test_fpgadataflow_ipstitch_gen_model_%s.onnx" % mem_mode - ) + model.save(ip_stitch_model_dir + "/test_fpgadataflow_ipstitch_gen_model_%s.onnx" % mem_mode) @pytest.mark.parametrize("mem_mode", ["const", "decoupled"]) diff --git a/tests/fpgadataflow/test_fpgadataflow_labelselect.py b/tests/fpgadataflow/test_fpgadataflow_labelselect.py index 553f263ba2..efd093b0b3 100644 --- a/tests/fpgadataflow/test_fpgadataflow_labelselect.py +++ b/tests/fpgadataflow/test_fpgadataflow_labelselect.py @@ -81,9 +81,7 @@ def prepare_inputs(input_tensor, idt): return {"inp": input_tensor} -@pytest.mark.parametrize( - "idt", [DataType["UINT8"], DataType["UINT16"], DataType["INT16"]] -) +@pytest.mark.parametrize("idt", [DataType["UINT8"], DataType["UINT16"], DataType["INT16"]]) # labels @pytest.mark.parametrize("labels", [10, 100]) # folding diff --git a/tests/fpgadataflow/test_fpgadataflow_lookup.py b/tests/fpgadataflow/test_fpgadataflow_lookup.py index 3164f2b4a6..7951007045 100644 --- a/tests/fpgadataflow/test_fpgadataflow_lookup.py +++ b/tests/fpgadataflow/test_fpgadataflow_lookup.py @@ -57,9 +57,7 @@ def make_lookup_model(embeddings, ishape, idt, edt): class LookupModel(nn.Module): def __init__(self, num_embeddings, embedding_dim): super().__init__() - self.lookup = nn.Embedding( - num_embeddings=num_embeddings, embedding_dim=embedding_dim - ) + self.lookup = nn.Embedding(num_embeddings=num_embeddings, embedding_dim=embedding_dim) def forward(self, x): x = self.lookup(x) diff --git a/tests/fpgadataflow/test_fpgadataflow_streamingmaxpool.py b/tests/fpgadataflow/test_fpgadataflow_streamingmaxpool.py index 628721b429..67a40d96f3 100644 --- a/tests/fpgadataflow/test_fpgadataflow_streamingmaxpool.py +++ b/tests/fpgadataflow/test_fpgadataflow_streamingmaxpool.py @@ -53,9 +53,7 @@ def make_single_maxpoolnhwc_modelwrapper(k, ifm_ch, ifm_dim, ofm_dim, idt, ceil_ ifm_dim_h, ifm_dim_w = ifm_dim ofm_dim_h, ofm_dim_w = ofm_dim odt = idt - inp = helper.make_tensor_value_info( - "inp", TensorProto.FLOAT, [1, ifm_dim_h, ifm_dim_w, ifm_ch] - ) + inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, [1, ifm_dim_h, ifm_dim_w, ifm_ch]) outp = helper.make_tensor_value_info( "outp", TensorProto.FLOAT, [1, ofm_dim_h, ofm_dim_w, ifm_ch] ) @@ -70,9 +68,7 @@ def make_single_maxpoolnhwc_modelwrapper(k, ifm_ch, ifm_dim, ofm_dim, idt, ceil_ ceil_mode=ceil_mode, pads=[0, 0, 0, 0], ) - graph = helper.make_graph( - nodes=[mp_node], name="mp_graph", inputs=[inp], outputs=[outp] - ) + graph = helper.make_graph(nodes=[mp_node], name="mp_graph", inputs=[inp], outputs=[outp]) model = qonnx_make_model(graph, producer_name="mp-model") model = ModelWrapper(model) @@ -106,9 +102,7 @@ def prepare_inputs(input_tensor): @pytest.mark.fpgadataflow @pytest.mark.slow @pytest.mark.vivado -def test_fpgadataflow_streamingmaxpool( - idt, dim_1d, k, ifm_dim, ifm_ch, pe, ceil_mode, exec_mode -): +def test_fpgadataflow_streamingmaxpool(idt, dim_1d, k, ifm_dim, ifm_ch, pe, ceil_mode, exec_mode): ifm_dim_h = ifm_dim k_h = k if dim_1d: @@ -138,9 +132,7 @@ def test_fpgadataflow_streamingmaxpool( # prepare input data input_dict = prepare_inputs(x) - golden = make_single_maxpoolnhwc_modelwrapper( - k, ifm_ch, ifm_dim, ofm_dim, idt, ceil_mode - ) + golden = make_single_maxpoolnhwc_modelwrapper(k, ifm_ch, ifm_dim, ofm_dim, idt, ceil_mode) y_expected = oxe.execute_onnx(golden, input_dict)["outp"] model = golden.transform(InferStreamingMaxPool()) diff --git a/tests/fpgadataflow/test_fpgadataflow_thresholding.py b/tests/fpgadataflow/test_fpgadataflow_thresholding.py index 445afdf458..2b7bc28a10 100644 --- a/tests/fpgadataflow/test_fpgadataflow_thresholding.py +++ b/tests/fpgadataflow/test_fpgadataflow_thresholding.py @@ -56,17 +56,11 @@ target_clk_ns = 5 -def make_single_thresholding_modelwrapper( - T, pe, idt, odt, actval, mem_mode, n_inp_vecs -): +def make_single_thresholding_modelwrapper(T, pe, idt, odt, actval, mem_mode, n_inp_vecs): NumChannels = T.shape[0] - inp = helper.make_tensor_value_info( - "inp", TensorProto.FLOAT, n_inp_vecs + [NumChannels] - ) - outp = helper.make_tensor_value_info( - "outp", TensorProto.FLOAT, n_inp_vecs + [NumChannels] - ) + inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, n_inp_vecs + [NumChannels]) + outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, n_inp_vecs + [NumChannels]) node_inp_list = ["inp", "thresh"] @@ -140,9 +134,7 @@ def test_fpgadataflow_thresholding(idt, act, nf, ich, exec_mode, mem_mode): else: actval = odt.min() - model = make_single_thresholding_modelwrapper( - T, pe, idt, odt, actval, mem_mode, n_inp_vecs - ) + model = make_single_thresholding_modelwrapper(T, pe, idt, odt, actval, mem_mode, n_inp_vecs) if exec_mode == "cppsim": model = model.transform(PrepareCppSim()) @@ -219,9 +211,7 @@ def test_runtime_thresholds_single_layer(): else: actval = odt.min() - model = make_single_thresholding_modelwrapper( - T, pe, idt, odt, actval, mem_mode, n_inp_vecs - ) + model = make_single_thresholding_modelwrapper(T, pe, idt, odt, actval, mem_mode, n_inp_vecs) op_inst = getCustomOp(model.graph.node[0]) op_inst.set_nodeattr("runtime_writeable_weights", 1) op_inst.make_weight_file(T, "decoupled_runtime", "old_weights.dat") @@ -248,9 +238,7 @@ def test_runtime_thresholds_single_layer(): def read_weights(sim): addr = 0 for i in range(len(old_weight_stream)): - extracted_weight_stream.append( - axilite_read(sim, addr, basename="s_axilite_0_") - ) + extracted_weight_stream.append(axilite_read(sim, addr, basename="s_axilite_0_")) addr += 4 rtlsim_exec(model, exec_ctx, pre_hook=read_weights) @@ -273,9 +261,7 @@ def read_weights(sim): expected += act.min() assert (y == expected).all() - new_weights = np.random.randint(idt.min(), idt.max() + 1, (ich, n_steps)).astype( - np.float32 - ) + new_weights = np.random.randint(idt.min(), idt.max() + 1, (ich, n_steps)).astype(np.float32) # provide non-decreasing thresholds new_weights = np.sort(T, axis=1) op_inst.make_weight_file(new_weights, "decoupled_runtime", "new_weights.dat") diff --git a/tests/fpgadataflow/test_fpgadataflow_vvau.py b/tests/fpgadataflow/test_fpgadataflow_vvau.py index 95501078d6..4208169c0b 100644 --- a/tests/fpgadataflow/test_fpgadataflow_vvau.py +++ b/tests/fpgadataflow/test_fpgadataflow_vvau.py @@ -135,9 +135,7 @@ def _make_single_vvau_modelwrapper( mem_mode=mem_mode, ) - graph = helper.make_graph( - nodes=[VVAU_node], name="vvau_graph", inputs=[inp], outputs=[outp] - ) + graph = helper.make_graph(nodes=[VVAU_node], name="vvau_graph", inputs=[inp], outputs=[outp]) model = qonnx_make_model(graph, producer_name="vvau-model") model = ModelWrapper(model) @@ -202,9 +200,7 @@ def test_fpgadataflow_vvau( # Generate weights in expected shape for ONNX and HLS node W = gen_finn_dt_tensor(wdt, (channels, 1, k_h, k_w)) # shape: [channels, 1, k, k] - W_onnx = _infer_sparse_weight_tensor( - W, k_h, k_w, channels - ) # shape: [k*k*channels, channels] + W_onnx = _infer_sparse_weight_tensor(W, k_h, k_w, channels) # shape: [k*k*channels, channels] # Generate inputs in expected format for ONNX and HLS node x = gen_finn_dt_tensor(idt, (1, dim_h, dim_w, k_h * k_w * channels)) @@ -273,9 +269,7 @@ def test_fpgadataflow_vvau( # signed offset y_expected += act.min() - y_produced = oxe.execute_onnx(model, input_dict, return_full_exec_context=False)[ - "outp" - ] + y_produced = oxe.execute_onnx(model, input_dict, return_full_exec_context=False)["outp"] assert (y_produced == y_expected).all(), "incorrect result" diff --git a/tests/fpgadataflow/test_minimize_bit_width.py b/tests/fpgadataflow/test_minimize_bit_width.py index dc4a076a18..805578018c 100644 --- a/tests/fpgadataflow/test_minimize_bit_width.py +++ b/tests/fpgadataflow/test_minimize_bit_width.py @@ -228,11 +228,7 @@ def phi(x: float) -> float: # if not runtime-writable weights, then use the tighter bound on the accumulator # bit width as determined by the weight values themselves else: - beta = ( - np.log2(abs(weights).sum(axis=0).max()) - + idt.bitwidth() - - float(idt.signed()) - ) + beta = np.log2(abs(weights).sum(axis=0).max()) + idt.bitwidth() - float(idt.signed()) P = np.ceil(beta + phi(beta) + 1.0) # if the node is the last in the graph, then round up to the nearest 8 bits if model.find_direct_successors(inst.onnx_node) is None: @@ -262,9 +258,7 @@ def phi(x: float) -> float: @pytest.mark.parametrize("tdt", thresh_data_types) @pytest.mark.parametrize("rww", [True, False]) @pytest.mark.fpgadataflow -def test_minimize_accumulator_width( - wdt: DataType, idt: DataType, tdt: DataType, rww: bool -): +def test_minimize_accumulator_width(wdt: DataType, idt: DataType, tdt: DataType, rww: bool): """Testing MinimizeAccumulatorWidth for VVAU and MVAU. :param wdt: (DataType) The data type that we are testing for the weights @@ -272,9 +266,7 @@ def test_minimize_accumulator_width( :param tdt: (DataType) The data type that we are testing for the thresholds :param rww: (bool) Whether or not to use runtime-writeable weights""" if (not wdt.signed()) or isinstance(wdt, BipolarType): - pytest.skip( - "Closed-form accumulator calculation is designed to consider signed weights" - ) + pytest.skip("Closed-form accumulator calculation is designed to consider signed weights") # Create uniform-precision model model = make_unit_test_model(wdt, idt, tdt) @@ -286,9 +278,7 @@ def test_minimize_accumulator_width( if isinstance(inst, (MatrixVectorActivation, VectorVectorActivation)): inst.set_nodeattr("runtime_writeable_weights", int(rww)) cur_adt = DataType[inst.get_nodeattr("accDataType")] - assert ( - cur_adt.bitwidth() == def_adt.bitwidth() - ), "Default data type is incorrect" + assert cur_adt.bitwidth() == def_adt.bitwidth(), "Default data type is incorrect" # Apply the optimization model = model.transform(MinimizeAccumulatorWidth()) @@ -304,9 +294,7 @@ def test_minimize_accumulator_width( # bit width minimization logic in the MVAU and VVAU is exact and should be # less than or equal to this calculation exp_adt = calculate_accumulator_bit_width(inst, model) - assert ( - cur_adt.bitwidth() <= exp_adt.bitwidth() - ), "Mismatched accumulation data types" + assert cur_adt.bitwidth() <= exp_adt.bitwidth(), "Mismatched accumulation data types" if model.find_direct_successors(inst.onnx_node) is None: assert ( cur_adt.bitwidth() % 8 @@ -315,6 +303,4 @@ def test_minimize_accumulator_width( cur_adt.bitwidth() == cur_odt.bitwidth() ), "outputDataType and accDataType should be equal" else: - assert ( - cur_odt.bitwidth() == idt.bitwidth() - ), "outputDataType should not be changed" + assert cur_odt.bitwidth() == idt.bitwidth(), "outputDataType should not be changed" diff --git a/tests/fpgadataflow/test_runtime_weights.py b/tests/fpgadataflow/test_runtime_weights.py index 16fed5c3cb..9b2f418776 100644 --- a/tests/fpgadataflow/test_runtime_weights.py +++ b/tests/fpgadataflow/test_runtime_weights.py @@ -96,9 +96,7 @@ def test_runtime_weights_single_layer(): def read_weights(sim): addr = 0 for i in range(len(old_weight_stream)): - extracted_weight_stream.append( - axilite_read(sim, addr, basename="s_axilite_0_") - ) + extracted_weight_stream.append(axilite_read(sim, addr, basename="s_axilite_0_")) addr += 4 rtlsim_exec(model, exec_ctx, pre_hook=read_weights) diff --git a/tests/fpgadataflow/test_set_folding.py b/tests/fpgadataflow/test_set_folding.py index 5355dd7044..ce9f4b12ed 100644 --- a/tests/fpgadataflow/test_set_folding.py +++ b/tests/fpgadataflow/test_set_folding.py @@ -45,7 +45,6 @@ def make_multi_fclayer_model(ch, wdt, adt, tdt, nnodes): - W = np.random.randint(wdt.min(), wdt.max() + 1, size=(ch, ch)) W = W.astype(np.float32) @@ -55,9 +54,7 @@ def make_multi_fclayer_model(ch, wdt, adt, tdt, nnodes): tensors = [] tensors.append(helper.make_tensor_value_info("inp", TensorProto.FLOAT, [1, ch])) for i in range(1, nnodes): - inter = helper.make_tensor_value_info( - "inter_" + str(i), TensorProto.FLOAT, [1, ch] - ) + inter = helper.make_tensor_value_info("inter_" + str(i), TensorProto.FLOAT, [1, ch]) tensors.append(inter) tensors.append(helper.make_tensor_value_info("outp", TensorProto.FLOAT, [1, ch])) @@ -115,10 +112,7 @@ def make_multi_fclayer_model(ch, wdt, adt, tdt, nnodes): @pytest.mark.parametrize("platform", ["Pynq-Z1", "Ultra96", "U200"]) @pytest.mark.fpgadataflow def test_set_folding(target_fps, platform): - - model = make_multi_fclayer_model( - 128, DataType["INT4"], DataType["INT2"], DataType["INT16"], 5 - ) + model = make_multi_fclayer_model(128, DataType["INT4"], DataType["INT2"], DataType["INT16"], 5) model = model.transform(GiveUniqueNodeNames()) parent_model = model.transform(CreateDataflowPartition()) diff --git a/tests/fpgadataflow/test_split_large_fifos.py b/tests/fpgadataflow/test_split_large_fifos.py index 0437d006cf..3061696a68 100644 --- a/tests/fpgadataflow/test_split_large_fifos.py +++ b/tests/fpgadataflow/test_split_large_fifos.py @@ -94,13 +94,9 @@ def test_split_large_fifos(depth, force_python_rtlsim): with open(tmp_output_dir + "/report/rtlsim_performance.json") as f: sim_data = json.load(f) assert ( - float(sim_data["throughput[images/s]"]) - / float(est_data["estimated_throughput_fps"]) - > 0.9 - ) - model = ModelWrapper( - tmp_output_dir + "/intermediate_models/step_set_fifo_depths.onnx" + float(sim_data["throughput[images/s]"]) / float(est_data["estimated_throughput_fps"]) > 0.9 ) + model = ModelWrapper(tmp_output_dir + "/intermediate_models/step_set_fifo_depths.onnx") # exclude final FIFO node (output FIFO, not part of test) fifo_nodes = model.get_nodes_by_op_type("StreamingFIFO")[:-1] golden_cfg = get_fifo_split_configs(depth, 256, 32768) diff --git a/tests/notebooks/test_jupyter_notebooks.py b/tests/notebooks/test_jupyter_notebooks.py index 836f1e059e..12f349b1e1 100644 --- a/tests/notebooks/test_jupyter_notebooks.py +++ b/tests/notebooks/test_jupyter_notebooks.py @@ -44,9 +44,7 @@ def test_notebook_exec(notebook): with open(notebook) as f: nb = nbformat.read(f, as_version=4) - ep = ExecutePreprocessor( - timeout=notebook_timeout_seconds, kernel_name="python3" - ) + ep = ExecutePreprocessor(timeout=notebook_timeout_seconds, kernel_name="python3") try: assert ep.preprocess(nb) is not None, f"Got empty notebook for {notebook}" except Exception: diff --git a/tests/transformation/streamline/test_absorb_mul_into_topk.py b/tests/transformation/streamline/test_absorb_mul_into_topk.py index 89ef74e0b3..1ca8fb06e9 100644 --- a/tests/transformation/streamline/test_absorb_mul_into_topk.py +++ b/tests/transformation/streamline/test_absorb_mul_into_topk.py @@ -71,18 +71,12 @@ def test_absorb_mul_into_topk(mul_positive, scalar): # initialize values # for mul if mul_positive is True: - a0_values = np.random.uniform(low=0.1, high=1, size=tuple(shape)).astype( - np.float32 - ) + a0_values = np.random.uniform(low=0.1, high=1, size=tuple(shape)).astype(np.float32) else: - a0_values = np.random.uniform(low=-1, high=-0.1, size=tuple(shape)).astype( - np.float32 - ) + a0_values = np.random.uniform(low=-1, high=-0.1, size=tuple(shape)).astype(np.float32) model.set_initializer("a0", a0_values) # for add - c0_values = np.random.uniform(low=-1, high=-0.1, size=tuple(shape)).astype( - np.float32 - ) + c0_values = np.random.uniform(low=-1, high=-0.1, size=tuple(shape)).astype(np.float32) model.set_initializer("c0", c0_values) model = model.transform(InsertTopK()) model = model.transform(InferShapes()) @@ -92,9 +86,7 @@ def test_absorb_mul_into_topk(mul_positive, scalar): model_transformed = model.transform(AbsorbScalarMulAddIntoTopK()) # compare execution results - inp_values = np.random.uniform(low=-10, high=10, size=(1, 1, 1, 1000)).astype( - np.float32 - ) + inp_values = np.random.uniform(low=-10, high=10, size=(1, 1, 1, 1000)).astype(np.float32) idict = {"global_in": inp_values} odict = oxe.execute_onnx(model, idict, True) y_indices = odict["global_out"] diff --git a/tests/transformation/streamline/test_absorb_transp_into_flatten.py b/tests/transformation/streamline/test_absorb_transp_into_flatten.py index 44b0c1d7e0..5b278bd552 100644 --- a/tests/transformation/streamline/test_absorb_transp_into_flatten.py +++ b/tests/transformation/streamline/test_absorb_transp_into_flatten.py @@ -65,9 +65,7 @@ def test_absorb_transp_into_flatten(perm, shape, ishape, data_layout): # model_transformed.save("test2.onnx") # verify transformation - inp_values = np.random.uniform(low=-1, high=1, size=tuple(ishape)).astype( - np.float32 - ) + inp_values = np.random.uniform(low=-1, high=1, size=tuple(ishape)).astype(np.float32) idict = {model.graph.input[0].name: inp_values} assert oxe.compare_execution(model, model_transformed, idict) diff --git a/tests/transformation/streamline/test_linear_past_eltwise.py b/tests/transformation/streamline/test_linear_past_eltwise.py index 4e5dcd6386..70fc395652 100644 --- a/tests/transformation/streamline/test_linear_past_eltwise.py +++ b/tests/transformation/streamline/test_linear_past_eltwise.py @@ -63,15 +63,9 @@ def make_model(shape): add1_node = helper.make_node("Add", [inp1.name, inp1_add_ct.name], [inp1_add.name]) add2_node = helper.make_node("Add", [inp2.name, inp2_add_ct.name], [inp2_add.name]) - mul1_node = helper.make_node( - "Mul", [inp1_add.name, inp1_mul_ct.name], [inp1_mul.name] - ) - mul2_node = helper.make_node( - "Mul", [inp2_add.name, inp2_mul_ct.name], [inp2_mul.name] - ) - eltwise_add_node = helper.make_node( - "Add", [inp1_mul.name, inp2_mul.name], [outp.name] - ) + mul1_node = helper.make_node("Mul", [inp1_add.name, inp1_mul_ct.name], [inp1_mul.name]) + mul2_node = helper.make_node("Mul", [inp2_add.name, inp2_mul_ct.name], [inp2_mul.name]) + eltwise_add_node = helper.make_node("Add", [inp1_mul.name, inp2_mul.name], [outp.name]) graph = helper.make_graph( nodes=[add1_node, add2_node, mul1_node, mul2_node, eltwise_add_node], name="graph", @@ -153,9 +147,7 @@ def test_linear_past_eltwise_add_multiple_forks(ch, ifmdim): num_of_params = 6 value_info = [] for i in range(num_of_params): - value_info += [ - helper.make_tensor_value_info("p" + str(i), TensorProto.FLOAT, input_shape) - ] + value_info += [helper.make_tensor_value_info("p" + str(i), TensorProto.FLOAT, input_shape)] modelproto = qonnx_make_model( helper.make_graph( @@ -180,9 +172,7 @@ def test_linear_past_eltwise_add_multiple_forks(ch, ifmdim): np.random.seed(0) for i in range(num_of_params): - model.set_initializer( - "p" + str(i), np.random.rand(*input_shape).astype(np.float32) - ) + model.set_initializer("p" + str(i), np.random.rand(*input_shape).astype(np.float32)) # need equal mults: model.set_initializer("p2", model.get_initializer("p1")) diff --git a/tests/transformation/streamline/test_maxpool_nhwc.py b/tests/transformation/streamline/test_maxpool_nhwc.py index d61eedaaf5..77dbf3a971 100644 --- a/tests/transformation/streamline/test_maxpool_nhwc.py +++ b/tests/transformation/streamline/test_maxpool_nhwc.py @@ -14,21 +14,13 @@ def create_maxpool(ifm_dim, ifm_ch, kernel_shape, pads, strides, ceil_mode, idt): - ofm_dim_h = compute_pool_output_dim( - ifm_dim[0], kernel_shape[0], strides[0], pads[0], ceil_mode - ) - ofm_dim_w = compute_pool_output_dim( - ifm_dim[1], kernel_shape[1], strides[1], pads[1], ceil_mode - ) - inp = oh.make_tensor_value_info( - "inp", TensorProto.FLOAT, [1, ifm_ch, ifm_dim[0], ifm_dim[1]] - ) + ofm_dim_h = compute_pool_output_dim(ifm_dim[0], kernel_shape[0], strides[0], pads[0], ceil_mode) + ofm_dim_w = compute_pool_output_dim(ifm_dim[1], kernel_shape[1], strides[1], pads[1], ceil_mode) + inp = oh.make_tensor_value_info("inp", TensorProto.FLOAT, [1, ifm_ch, ifm_dim[0], ifm_dim[1]]) outp_mp = oh.make_tensor_value_info( "outp_mp", TensorProto.FLOAT, [1, ifm_ch, ofm_dim_h, ofm_dim_w] ) - outp = oh.make_tensor_value_info( - "outp", TensorProto.FLOAT, [1, ofm_dim_h, ofm_dim_w, ifm_ch] - ) + outp = oh.make_tensor_value_info("outp", TensorProto.FLOAT, [1, ofm_dim_h, ofm_dim_w, ifm_ch]) maxpool_node = oh.make_node( "MaxPool", @@ -83,9 +75,7 @@ def create_maxpool(ifm_dim, ifm_ch, kernel_shape, pads, strides, ceil_mode, idt) @pytest.mark.parametrize("idt", [DataType["INT4"]]) def test_maxpool_nhwc(ifm_dim, ifm_ch, kernel_shape, pads, strides, ceil_mode, idt): # create MaxPool node - maxpool_model = create_maxpool( - ifm_dim, ifm_ch, kernel_shape, pads, strides, ceil_mode, idt - ) + maxpool_model = create_maxpool(ifm_dim, ifm_ch, kernel_shape, pads, strides, ceil_mode, idt) # generate input tensor for testing input_tensor = gen_finn_dt_tensor(idt, [1, ifm_ch, ifm_dim[0], ifm_dim[1]]) @@ -100,9 +90,7 @@ def test_maxpool_nhwc(ifm_dim, ifm_ch, kernel_shape, pads, strides, ceil_mode, i # execute transformed model output_node_name = maxpool_model.graph.output[0].name - output_dict = oxe.execute_onnx( - maxpool_model, input_dict, return_full_exec_context=False - ) + output_dict = oxe.execute_onnx(maxpool_model, input_dict, return_full_exec_context=False) output = output_dict[output_node_name] # compare outputs diff --git a/tests/transformation/streamline/test_move_chw_add_past_conv.py b/tests/transformation/streamline/test_move_chw_add_past_conv.py index e1b324a798..8b2f10b658 100644 --- a/tests/transformation/streamline/test_move_chw_add_past_conv.py +++ b/tests/transformation/streamline/test_move_chw_add_past_conv.py @@ -85,13 +85,9 @@ def test_move_chw_add_past_conv(idim, k, s, ich, och): model = ModelWrapper(model) # initialize model - a0_values = np.random.uniform(low=0, high=1, size=tuple(add_param_shape)).astype( - np.float32 - ) + a0_values = np.random.uniform(low=0, high=1, size=tuple(add_param_shape)).astype(np.float32) model.set_initializer("a0", a0_values) - a1_values = np.random.uniform(low=0, high=1, size=tuple(conv_param_shape)).astype( - np.float32 - ) + a1_values = np.random.uniform(low=0, high=1, size=tuple(conv_param_shape)).astype(np.float32) model.set_initializer("a1", a1_values) model = model.transform(InferShapes()) diff --git a/tests/transformation/streamline/test_move_identical_op_past_join_op.py b/tests/transformation/streamline/test_move_identical_op_past_join_op.py index 7be9763162..dd83681fc2 100644 --- a/tests/transformation/streamline/test_move_identical_op_past_join_op.py +++ b/tests/transformation/streamline/test_move_identical_op_past_join_op.py @@ -56,18 +56,10 @@ def create_model(perm): "Add", inputs=["out_transpose1", "out_transpose2"], outputs=["out_join1"] ) - in_transpose1 = oh.make_tensor_value_info( - "in_transpose1", TensorProto.FLOAT, in_shape - ) - in_transpose2 = oh.make_tensor_value_info( - "in_transpose2", TensorProto.FLOAT, in_shape - ) - out_transpose1 = oh.make_tensor_value_info( - "out_transpose1", TensorProto.FLOAT, out_shape - ) - out_transpose2 = oh.make_tensor_value_info( - "out_transpose2", TensorProto.FLOAT, out_shape - ) + in_transpose1 = oh.make_tensor_value_info("in_transpose1", TensorProto.FLOAT, in_shape) + in_transpose2 = oh.make_tensor_value_info("in_transpose2", TensorProto.FLOAT, in_shape) + out_transpose1 = oh.make_tensor_value_info("out_transpose1", TensorProto.FLOAT, out_shape) + out_transpose2 = oh.make_tensor_value_info("out_transpose2", TensorProto.FLOAT, out_shape) out_join1 = oh.make_tensor_value_info("out_join1", TensorProto.FLOAT, out_shape) graph = oh.make_graph( diff --git a/tests/transformation/streamline/test_move_maxpool_past_multithreshold.py b/tests/transformation/streamline/test_move_maxpool_past_multithreshold.py index 6126acd9e3..2dee153545 100644 --- a/tests/transformation/streamline/test_move_maxpool_past_multithreshold.py +++ b/tests/transformation/streamline/test_move_maxpool_past_multithreshold.py @@ -67,14 +67,10 @@ def test_move_maxpool_past_multithreshold(): value_info = [] thres1_shape = [1, 1] - value_info += [ - helper.make_tensor_value_info("thres1", TensorProto.FLOAT, thres1_shape) - ] + value_info += [helper.make_tensor_value_info("thres1", TensorProto.FLOAT, thres1_shape)] thres2_shape = [ch, 14] - value_info += [ - helper.make_tensor_value_info("thres2", TensorProto.FLOAT, thres2_shape) - ] + value_info += [helper.make_tensor_value_info("thres2", TensorProto.FLOAT, thres2_shape)] nodes = [] nodes += [helper.make_node("MaxPool", ["top_in"], ["t1"], **maxpool_config)] @@ -114,9 +110,7 @@ def test_move_maxpool_past_multithreshold(): model = model.transform(InferDataTypes()) model.set_initializer("thres1", np.array([[0]], dtype=np.float32)) - model.set_initializer( - "thres2", get_multithreshold_rand_params(*thres2_shape, seed=0) - ) + model.set_initializer("thres2", get_multithreshold_rand_params(*thres2_shape, seed=0)) # Transform new_model = model.transform(MoveMaxPoolPastMultiThreshold()) diff --git a/tests/transformation/streamline/test_move_mul_past_dw_conv.py b/tests/transformation/streamline/test_move_mul_past_dw_conv.py index 72a6650ec4..303b97c69f 100644 --- a/tests/transformation/streamline/test_move_mul_past_dw_conv.py +++ b/tests/transformation/streamline/test_move_mul_past_dw_conv.py @@ -65,14 +65,10 @@ def test_move_mul_past_dw_conv(ifm_dim, ifm_ch, k, stride, pad_amt, dw): ofm_dim = compute_conv_output_dim(ifm_dim, k, stride, total_pad) # set up onnx model - inp = helper.make_tensor_value_info( - "inp", TensorProto.FLOAT, [1, ifm_ch, ifm_dim, ifm_dim] - ) + inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, [1, ifm_ch, ifm_dim, ifm_dim]) mul = helper.make_tensor_value_info("mul", TensorProto.FLOAT, [1, ifm_ch, 1, 1]) W = helper.make_tensor_value_info("W", TensorProto.FLOAT, W_shape) - outp = helper.make_tensor_value_info( - "outp", TensorProto.FLOAT, [1, ofm_ch, ofm_dim, ofm_dim] - ) + outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, [1, ofm_ch, ofm_dim, ofm_dim]) Mul_node = helper.make_node("Mul", ["inp", "mul"], ["mul_out"]) diff --git a/tests/transformation/streamline/test_move_mul_past_maxpool.py b/tests/transformation/streamline/test_move_mul_past_maxpool.py index 3bae2905a0..61dddd56e9 100755 --- a/tests/transformation/streamline/test_move_mul_past_maxpool.py +++ b/tests/transformation/streamline/test_move_mul_past_maxpool.py @@ -65,13 +65,9 @@ def test_move_mul_past_maxpool(ifm_dim, ifm_ch, k, stride, pad, cw, negative): ofm_dim = compute_pool_output_dim(ifm_dim, k, stride, pad) # set up onnx model - inp = helper.make_tensor_value_info( - "inp", TensorProto.FLOAT, [1, ifm_ch, ifm_dim, ifm_dim] - ) + inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, [1, ifm_ch, ifm_dim, ifm_dim]) mul = helper.make_tensor_value_info("mul", TensorProto.FLOAT, mul_shape) - outp = helper.make_tensor_value_info( - "outp", TensorProto.FLOAT, [1, ofm_ch, ofm_dim, ofm_dim] - ) + outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, [1, ofm_ch, ofm_dim, ofm_dim]) Mul_node = helper.make_node("Mul", ["inp", "mul"], ["mul_out"]) diff --git a/tests/transformation/streamline/test_move_past_fork.py b/tests/transformation/streamline/test_move_past_fork.py index 7e77d7f9b3..e9433178c8 100644 --- a/tests/transformation/streamline/test_move_past_fork.py +++ b/tests/transformation/streamline/test_move_past_fork.py @@ -64,9 +64,7 @@ def test_move_past_fork_transpose(): new_model = model.transform(MoveTransposePastFork()) new_model = new_model.transform(GiveUniqueNodeNames()) nodes = new_model.graph.node - assert oxe.compare_execution( - model, new_model, {"in0": np.random.rand(*shp).astype(np.float32)} - ) + assert oxe.compare_execution(model, new_model, {"in0": np.random.rand(*shp).astype(np.float32)}) assert len(nodes) == 5 assert not new_model.is_fork_node(get_by_name(nodes, "Transpose_0")) @@ -120,9 +118,7 @@ def test_move_past_fork_linear(ch, ifmdim): for tensor_name in model.get_all_tensor_names(): if tensor_name.endswith("_param"): pshape = model.get_tensor_shape(tensor_name) - model.set_initializer( - tensor_name, np.random.rand(*pshape).astype(np.float32) - ) + model.set_initializer(tensor_name, np.random.rand(*pshape).astype(np.float32)) model = model.transform(GiveUniqueNodeNames()) # Transform new_model = model.transform(MoveLinearPastFork()) diff --git a/tests/transformation/streamline/test_move_scalar_past_matmul.py b/tests/transformation/streamline/test_move_scalar_past_matmul.py index 6c788294bc..e4f4357fff 100644 --- a/tests/transformation/streamline/test_move_scalar_past_matmul.py +++ b/tests/transformation/streamline/test_move_scalar_past_matmul.py @@ -63,9 +63,7 @@ def test_move_scalar_mul_past_matmul(): model = ModelWrapper(modelproto) model = model.transform(InferShapes()) model.set_initializer("mul_param", np.asarray([[3]], dtype=np.float32)) - model.set_initializer( - "matmul_param", np.asarray([[2, 4], [-1, 1]], dtype=np.float32) - ) + model.set_initializer("matmul_param", np.asarray([[2, 4], [-1, 1]], dtype=np.float32)) new_model = model.transform(MoveScalarMulPastMatMul()) inp_dict = {"top_in": np.asarray([[-1.0, 1.0]], dtype=np.float32)} assert ox.compare_execution(model, new_model, inp_dict) @@ -95,9 +93,7 @@ def test_move_scalar_add_past_matmul(): model = ModelWrapper(modelproto) model = model.transform(InferShapes()) model.set_initializer("add_param", np.asarray([[3]], dtype=np.float32)) - model.set_initializer( - "matmul_param", np.asarray([[2, 4], [-1, 1]], dtype=np.float32) - ) + model.set_initializer("matmul_param", np.asarray([[2, 4], [-1, 1]], dtype=np.float32)) new_model = model.transform(MoveScalarAddPastMatMul()) inp_dict = {"top_in": np.asarray([[-1.0, 1.0]], dtype=np.float32)} assert ox.compare_execution(model, new_model, inp_dict) diff --git a/tests/transformation/streamline/test_scale_resize_nhwc.py b/tests/transformation/streamline/test_scale_resize_nhwc.py index 5e107448f8..350f5b3133 100644 --- a/tests/transformation/streamline/test_scale_resize_nhwc.py +++ b/tests/transformation/streamline/test_scale_resize_nhwc.py @@ -18,9 +18,7 @@ def create_resize_transpose(ifm_dim, ifm_ch, scales, mode, idt): ofm_dim_h = ifm_dim[0] * scales[2] ofm_dim_w = ifm_dim[1] * scales[3] - inp = oh.make_tensor_value_info( - "inp", TensorProto.FLOAT, [1, ifm_ch, ifm_dim[0], ifm_dim[1]] - ) + inp = oh.make_tensor_value_info("inp", TensorProto.FLOAT, [1, ifm_ch, ifm_dim[0], ifm_dim[1]]) param = oh.make_tensor_value_info("scales", TensorProto.FLOAT, [4]) @@ -30,9 +28,7 @@ def create_resize_transpose(ifm_dim, ifm_ch, scales, mode, idt): outp_up = oh.make_tensor_value_info( "outp_up", TensorProto.FLOAT, [1, ifm_ch, ofm_dim_h, ofm_dim_w] ) - outp = oh.make_tensor_value_info( - "outp", TensorProto.FLOAT, [1, ofm_dim_h, ofm_dim_w, ifm_ch] - ) + outp = oh.make_tensor_value_info("outp", TensorProto.FLOAT, [1, ofm_dim_h, ofm_dim_w, ifm_ch]) resize_node = oh.make_node( "Resize", @@ -73,18 +69,14 @@ def create_resize_transpose(ifm_dim, ifm_ch, scales, mode, idt): def create_transpose_resize(ifm_dim, ifm_ch, scales, mode, idt): ofm_dim_h = ifm_dim[0] * scales[2] ofm_dim_w = ifm_dim[1] * scales[3] - inp = oh.make_tensor_value_info( - "inp", TensorProto.FLOAT, [1, ifm_dim[0], ifm_dim[1], ifm_ch] - ) + inp = oh.make_tensor_value_info("inp", TensorProto.FLOAT, [1, ifm_dim[0], ifm_dim[1], ifm_ch]) param = oh.make_tensor_value_info("scales", TensorProto.FLOAT, [4]) # Not actually used, only needed for compliance with the Resize node interface roi = oh.make_tensor_value_info("roi", TensorProto.FLOAT, [4]) - outp = oh.make_tensor_value_info( - "outp", TensorProto.FLOAT, [1, ifm_ch, ofm_dim_h, ofm_dim_w] - ) + outp = oh.make_tensor_value_info("outp", TensorProto.FLOAT, [1, ifm_ch, ofm_dim_h, ofm_dim_w]) outp_tr = oh.make_tensor_value_info( "outp_tr", TensorProto.FLOAT, [1, ifm_ch, ifm_dim[0], ifm_dim[1]] ) @@ -128,9 +120,7 @@ def create_transpose_resize(ifm_dim, ifm_ch, scales, mode, idt): def create_transpose_resize_transpose(ifm_dim, ifm_ch, scales, mode, idt): ofm_dim_h = ifm_dim[0] * scales[2] ofm_dim_w = ifm_dim[1] * scales[3] - inp = oh.make_tensor_value_info( - "inp", TensorProto.FLOAT, [1, ifm_dim[0], ifm_dim[1], ifm_ch] - ) + inp = oh.make_tensor_value_info("inp", TensorProto.FLOAT, [1, ifm_dim[0], ifm_dim[1], ifm_ch]) param = oh.make_tensor_value_info("scales", TensorProto.FLOAT, scales) @@ -144,9 +134,7 @@ def create_transpose_resize_transpose(ifm_dim, ifm_ch, scales, mode, idt): outp_up = oh.make_tensor_value_info( "outp_up", TensorProto.FLOAT, [1, ifm_ch, ofm_dim_h, ofm_dim_w] ) - outp = oh.make_tensor_value_info( - "outp", TensorProto.FLOAT, [1, ofm_dim_h, ofm_dim_w, ifm_ch] - ) + outp = oh.make_tensor_value_info("outp", TensorProto.FLOAT, [1, ofm_dim_h, ofm_dim_w, ifm_ch]) transpose_node1 = onnx.helper.make_node( "Transpose", @@ -209,9 +197,7 @@ def check_transform(model): # input channels @pytest.mark.parametrize("ifm_ch", [3]) # scales -@pytest.mark.parametrize( - "scales", [[1, 1, i, j] for i in range(2, 5) for j in range(2, 5)] -) +@pytest.mark.parametrize("scales", [[1, 1, i, j] for i in range(2, 5) for j in range(2, 5)]) # mode @pytest.mark.parametrize("mode", ["nearest"]) # input datatype @@ -220,9 +206,7 @@ def test_scale_resize_nhwc(ifm_dim, ifm_ch, scales, mode, idt): # create models resize_model1 = create_resize_transpose(ifm_dim, ifm_ch, scales, mode, idt) resize_model2 = create_transpose_resize(ifm_dim, ifm_ch, scales, mode, idt) - resize_model3 = create_transpose_resize_transpose( - ifm_dim, ifm_ch, scales, mode, idt - ) + resize_model3 = create_transpose_resize_transpose(ifm_dim, ifm_ch, scales, mode, idt) # set initializers resize_model1.set_initializer("scales", np.array(scales, dtype=np.float32)) @@ -245,9 +229,7 @@ def test_scale_resize_nhwc(ifm_dim, ifm_ch, scales, mode, idt): # execute transformed model output_node_name1 = resize_model1.graph.output[0].name - output_dict1 = oxe.execute_onnx( - resize_model1, input_dict_nchw, return_full_exec_context=False - ) + output_dict1 = oxe.execute_onnx(resize_model1, input_dict_nchw, return_full_exec_context=False) output1 = output_dict1[output_node_name1] # compare outputs @@ -264,9 +246,7 @@ def test_scale_resize_nhwc(ifm_dim, ifm_ch, scales, mode, idt): # execute transformed model output_node_name2 = resize_model2.graph.output[0].name - output_dict2 = oxe.execute_onnx( - resize_model2, input_dict_nhwc, return_full_exec_context=False - ) + output_dict2 = oxe.execute_onnx(resize_model2, input_dict_nhwc, return_full_exec_context=False) output2 = output_dict2[output_node_name2] # compare outputs @@ -283,9 +263,7 @@ def test_scale_resize_nhwc(ifm_dim, ifm_ch, scales, mode, idt): # execute transformed model output_node_name3 = resize_model3.graph.output[0].name - output_dict3 = oxe.execute_onnx( - resize_model3, input_dict_nhwc, return_full_exec_context=False - ) + output_dict3 = oxe.execute_onnx(resize_model3, input_dict_nhwc, return_full_exec_context=False) output3 = output_dict3[output_node_name3] # compare outputs diff --git a/tests/transformation/test_infer_data_layouts_cnv.py b/tests/transformation/test_infer_data_layouts_cnv.py index 245980f958..a5a9d34aaf 100644 --- a/tests/transformation/test_infer_data_layouts_cnv.py +++ b/tests/transformation/test_infer_data_layouts_cnv.py @@ -35,7 +35,11 @@ from qonnx.core.modelwrapper import ModelWrapper from qonnx.transformation.bipolar_to_xnor import ConvertBipolarMatMulToXnorPopcount from qonnx.transformation.fold_constants import FoldConstants -from qonnx.transformation.general import GiveReadableTensorNames, GiveUniqueNodeNames, GiveUniqueParameterTensors +from qonnx.transformation.general import ( + GiveReadableTensorNames, + GiveUniqueNodeNames, + GiveUniqueParameterTensors, +) from qonnx.transformation.infer_data_layouts import InferDataLayouts from qonnx.transformation.infer_shapes import InferShapes from qonnx.transformation.lower_convs_to_matmul import LowerConvsToMatMul @@ -105,9 +109,7 @@ def test_infer_data_layouts_cnv(): # note: im2col output isn't really NHWC or any other common layout # since the concept of channels changes with lowering... but it is # conceptually close to NHWC since the innermost dim gets multiplied - assert ( - model.get_tensor_layout("ConvolutionInputGenerator_0_out0") == DataLayout.NHWC - ) + assert model.get_tensor_layout("ConvolutionInputGenerator_0_out0") == DataLayout.NHWC assert model.get_tensor_layout("MatrixVectorActivation_3_out0") == DataLayout.NHWC assert model.get_tensor_layout("Reshape_0_out0") == DataLayout.NC assert model.get_tensor_layout("MatrixVectorActivation_6_out0") == DataLayout.NC diff --git a/tests/transformation/test_qonnx_to_finn.py b/tests/transformation/test_qonnx_to_finn.py index e5f1eefe12..10fcb79cc7 100644 --- a/tests/transformation/test_qonnx_to_finn.py +++ b/tests/transformation/test_qonnx_to_finn.py @@ -58,9 +58,7 @@ def get_brev_model_and_sample_inputs(model_name, wbits, abits): brev_model = get_test_model_trained(model_name, wbits, abits) elif model_name == "CNV": in_shape = (1, 3, 32, 32) - fn = pk.resource_filename( - "finn.qnn-data", "cifar10/cifar10-test-data-class3.npz" - ) + fn = pk.resource_filename("finn.qnn-data", "cifar10/cifar10-test-data-class3.npz") input_tensor = np.load(fn)["arr_0"].astype(np.float32) input_tensor = input_tensor / 255 brev_model = get_test_model_trained(model_name, wbits, abits) @@ -105,9 +103,7 @@ def test_QONNX_to_FINN(model_name, wbits, abits): # Get test config and model ATOL = 1e-7 - brev_model, in_shape, input_tensor = get_brev_model_and_sample_inputs( - model_name, wbits, abits - ) + brev_model, in_shape, input_tensor = get_brev_model_and_sample_inputs(model_name, wbits, abits) temp_dir = TemporaryDirectory() qonnx_base_path = temp_dir.name + "/qonnx_{}.onnx" finn_base_path = temp_dir.name + "/finn_{}.onnx" @@ -117,9 +113,7 @@ def test_QONNX_to_FINN(model_name, wbits, abits): brev_output = brev_model.forward(torch_input_tensor).detach().numpy() # Get "clean" FINN model and its output - _ = export_finn_onnx( - brev_model, torch.randn(in_shape), finn_base_path.format("raw") - ) + _ = export_finn_onnx(brev_model, torch.randn(in_shape), finn_base_path.format("raw")) model = ModelWrapper(finn_base_path.format("raw")) model = model.transform(GiveUniqueNodeNames()) model = model.transform(InferShapes()) @@ -166,8 +160,7 @@ def test_QONNX_to_FINN(model_name, wbits, abits): output_dict = oxe.execute_onnx(model, input_dict, False) test_output = output_dict[model.graph.output[0].name] assert np.isclose(test_output, finn_export_output, atol=ATOL).all(), ( - "The output of the FINN model " - "and the QONNX -> FINN converted model should match." + "The output of the FINN model " "and the QONNX -> FINN converted model should match." ) # Run analysis passes on the converted model diff --git a/tests/util/test_build_dataflow.py b/tests/util/test_build_dataflow.py index 39f0b0dc89..02136b31a2 100644 --- a/tests/util/test_build_dataflow.py +++ b/tests/util/test_build_dataflow.py @@ -57,9 +57,7 @@ def test_end2end_build_dataflow_directory(): assert os.path.isfile(output_dir + "/report/estimate_layer_cycles.json") assert os.path.isfile(output_dir + "/report/estimate_layer_resources.json") assert os.path.isfile(output_dir + "/report/rtlsim_perf_batch_1.vcd") - assert os.path.isfile( - output_dir + "/report/estimate_layer_config_alternatives.json" - ) + assert os.path.isfile(output_dir + "/report/estimate_layer_config_alternatives.json") assert os.path.isfile(output_dir + "/report/estimate_network_performance.json") assert os.path.isfile(output_dir + "/report/ooc_synth_and_timing.json") assert os.path.isfile(output_dir + "/report/rtlsim_performance.json") @@ -71,16 +69,8 @@ def test_end2end_build_dataflow_directory(): verif_batchsize = np.load(target_dir + "/input.npy").shape[0] for i in range(verif_batchsize): verify_out_dir = output_dir + "/verification_output" - assert os.path.isfile( - verify_out_dir + f"/verify_initial_python_{i}_SUCCESS.npy" - ) - assert os.path.isfile( - verify_out_dir + f"/verify_streamlined_python_{i}_SUCCESS.npy" - ) - assert os.path.isfile( - verify_out_dir + f"/verify_folded_hls_cppsim_{i}_SUCCESS.npy" - ) - assert os.path.isfile( - verify_out_dir + f"/verify_stitched_ip_rtlsim_{i}_SUCCESS.npy" - ) + assert os.path.isfile(verify_out_dir + f"/verify_initial_python_{i}_SUCCESS.npy") + assert os.path.isfile(verify_out_dir + f"/verify_streamlined_python_{i}_SUCCESS.npy") + assert os.path.isfile(verify_out_dir + f"/verify_folded_hls_cppsim_{i}_SUCCESS.npy") + assert os.path.isfile(verify_out_dir + f"/verify_stitched_ip_rtlsim_{i}_SUCCESS.npy") assert os.path.isfile(output_dir + f"/report/verify_rtlsim_{i}.vcd") diff --git a/tests/util/test_create.py b/tests/util/test_create.py index dc44e4bd45..b8b439cf18 100644 --- a/tests/util/test_create.py +++ b/tests/util/test_create.py @@ -34,9 +34,7 @@ @pytest.mark.util -@pytest.mark.parametrize( - "bitwidth", [DataType["BIPOLAR"], DataType["INT2"], DataType["INT4"]] -) +@pytest.mark.parametrize("bitwidth", [DataType["BIPOLAR"], DataType["INT2"], DataType["INT4"]]) def test_hls_random_mlp_maker(bitwidth): w = bitwidth a = bitwidth diff --git a/tests/util/test_data_packing_hls.py b/tests/util/test_data_packing_hls.py index 859b926543..b95bcd5d42 100644 --- a/tests/util/test_data_packing_hls.py +++ b/tests/util/test_data_packing_hls.py @@ -105,16 +105,12 @@ def test_npy2apintstream(test_shape, dtype): ) with open(test_dir + "/compile.sh", "w") as f: f.write(cmd_compile) - compile = subprocess.Popen( - ["sh", "compile.sh"], stdout=subprocess.PIPE, cwd=test_dir - ) + compile = subprocess.Popen(["sh", "compile.sh"], stdout=subprocess.PIPE, cwd=test_dir) (stdout, stderr) = compile.communicate() # make copy before saving the array ndarray = ndarray.copy() np.save(npy_in, ndarray) - execute = subprocess.Popen( - "./test_npy2apintstream", stdout=subprocess.PIPE, cwd=test_dir - ) + execute = subprocess.Popen("./test_npy2apintstream", stdout=subprocess.PIPE, cwd=test_dir) (stdout, stderr) = execute.communicate() produced = np.load(npy_out) success = (produced == ndarray).all() diff --git a/tutorials/fpga_flow/gen_tb_data.py b/tutorials/fpga_flow/gen_tb_data.py index a525d92bfc..e73fd65094 100755 --- a/tutorials/fpga_flow/gen_tb_data.py +++ b/tutorials/fpga_flow/gen_tb_data.py @@ -48,9 +48,7 @@ tb_data.write("{:02X}".format(test_x[i][j][k])) tb_data.write("\n") tb_data.write( - "ffffffffffffffffffffffffffffffffffffffffffffffffffffff{:02X}\n".format( - test_y[i] - ) + "ffffffffffffffffffffffffffffffffffffffffffffffffffffff{:02X}\n".format(test_y[i]) ) print("Testbench data generated at " + file_name) From 3497cfefeb29998f2b3b10c81e19c972a744cac7 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 28 Jun 2023 14:43:15 +0100 Subject: [PATCH 185/665] [deps/ci] Downgrade tool version for ci and update qonnx commit --- docker/jenkins/Jenkinsfile | 4 ++-- fetch-repos.sh | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index d8fea0124c..2954877c2a 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -5,8 +5,8 @@ node { checkout scm } withEnv([ - "FINN_XILINX_PATH=/proj/xbuilds/SWIP/2023.1_0507_1903/installs/lin64", - "FINN_XILINX_VERSION=2023.1", + "FINN_XILINX_PATH=/proj/xbuilds/SWIP/2022.2_1014_8888/installs/lin64", + "FINN_XILINX_VERSION=2022.2", "FINN_DOCKER_TAG=xilinx/finn:jenkins", "FINN_HOST_BUILD_DIR=/scratch/users/finn_ci", "PLATFORM_REPO_PATHS=/opt/xilinx/platforms" diff --git a/fetch-repos.sh b/fetch-repos.sh index ddae4020ed..4416f87bfe 100755 --- a/fetch-repos.sh +++ b/fetch-repos.sh @@ -27,7 +27,7 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -QONNX_COMMIT="0c980ef410c7c99b33c5b96486233f5a723ca1bc" +QONNX_COMMIT="6ca8f8e0af84e49facac5cdc34735eaf6e938300" FINN_EXP_COMMIT="0aa7e1c44b20cf085b6fe42cff360f0a832afd2c" BREVITAS_COMMIT="d30ba0d6b3db4a333072624fa3d10827a686488d" PYVERILATOR_COMMIT="766e457465f5c0dd315490d7b9cc5d74f9a76f4f" @@ -39,7 +39,7 @@ XIL_BDF_COMMIT="8cf4bb674a919ac34e3d99d8d71a9e60af93d14e" KV260_BDF_COMMIT="98e0d3efc901f0b974006bc4370c2a7ad8856c79" EXP_BOARD_FILES_MD5="30eecc497c31050bd46d10ea20eba232" -QONNX_URL="https://github.com/iksnagreb/qonnx.git" +QONNX_URL="https://github.com/fastmachinelearning/qonnx.git" FINN_EXP_URL="https://github.com/Xilinx/finn-experimental.git" BREVITAS_URL="https://github.com/Xilinx/brevitas.git" PYVERILATOR_URL="https://github.com/maltanar/pyverilator.git" From eb5f89efd595d76dee61de78ce7c6bbc53758df2 Mon Sep 17 00:00:00 2001 From: Hugo LE BLEVEC Date: Wed, 28 Jun 2023 17:04:03 +0200 Subject: [PATCH 186/665] Swapping weights tensors dimension to fit ususal transposed conv representation --- .../fpgadataflow/infer_pixel_padding_deconv.py | 16 ++++++++-------- tests/fpgadataflow/test_fpgadataflow_deconv.py | 2 +- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/infer_pixel_padding_deconv.py b/src/finn/transformation/fpgadataflow/infer_pixel_padding_deconv.py index ac4b121155..4acd79d362 100644 --- a/src/finn/transformation/fpgadataflow/infer_pixel_padding_deconv.py +++ b/src/finn/transformation/fpgadataflow/infer_pixel_padding_deconv.py @@ -87,12 +87,12 @@ def apply(self, model): dw = False if group == ifm_ch and ofm_ch == ifm_ch: W_sparse = np.zeros( - (ofm_ch, ifm_ch, k_h, k_w) - ) # (OFM, IFM, k_H, k_W) - for ch in range(ifm_ch): + (ifm_ch, ofm_ch, k_h, k_w) + ) # (IFM, OFM, k_H, k_W) + for ch in range(ofm_ch): W_sparse[ch][ch] = W_conv[ch][ 0 - ] # W_conv = [OFM, IFM, k_H, k_W] + ] # W_conv = [IFM, OFM, k_H, k_W] W_conv = W_sparse.astype(np.float32) # we need to store information of the # sparsity of the weight matrix. For this @@ -105,11 +105,11 @@ def apply(self, model): # Im2Col node belongs to a depthwise convolution dw = True - # reuse conv weights for new matmul weights - # conv weights are [OFM][IFM][k][k] - # We need to rotate the weights and swap the first two dimensions + # reuse ConvTranspose weights for new matmul weights + # conv weights are [IFM][OFM][k][k] + # We need to rotate the weights and make them [OFM][IFM][k][k] # for pixel padding deconv to remain mathematically equivalent - # and then first convert to [OFM][k][k][IFM] (to remain compatible + # and then convert to [OFM][k][k][IFM] (to remain compatible # with finn-hlslib and how it does im2col/sliding window) W_conv = np.rot90(W_conv, 2, [2, 3]) W_conv = np.moveaxis(W_conv, 0, 1) diff --git a/tests/fpgadataflow/test_fpgadataflow_deconv.py b/tests/fpgadataflow/test_fpgadataflow_deconv.py index 92738a6dee..d951f1624f 100644 --- a/tests/fpgadataflow/test_fpgadataflow_deconv.py +++ b/tests/fpgadataflow/test_fpgadataflow_deconv.py @@ -85,7 +85,7 @@ def set_up_reference_model(idt, wdt, k, idim, ifm_ch, ofm_ch, stride, padding, w "outp", TensorProto.FLOAT, [1, ofm_ch, odim_h, odim_w] ) - W = helper.make_tensor_value_info("W", TensorProto.FLOAT, [ofm_ch, ifm_ch, k, k]) + W = helper.make_tensor_value_info("W", TensorProto.FLOAT, [ifm_ch, ofm_ch, k, k]) ConvTranspose = helper.make_node( "ConvTranspose", From b355a6cb530a2a7c0687b5164ac1417564f2a239 Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Wed, 28 Jun 2023 16:22:54 +0100 Subject: [PATCH 187/665] Forgot to add test_support_board_map inclusion into test file Signed-off-by: Fionn O'Donohoe --- tests/end2end/test_end2end_bnn_pynq.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index 30bbadb6fc..14616522ec 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -91,7 +91,7 @@ MakeMaxPoolNHWC, MoveScalarLinearPastInvariants, ) -from finn.util.basic import get_finn_root, make_build_dir +from finn.util.basic import get_finn_root, make_build_dir, test_support_board_map from finn.util.pytorch import ToTensor from finn.util.test import ( execute_parent, From c1b86d82fc8f1af2826e812c9c0f1b6971c6798e Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 28 Jun 2023 16:36:48 +0100 Subject: [PATCH 188/665] [Deps/tests] Update brevitas and delete finn_onnx export in brevitas tests --- fetch-repos.sh | 2 +- tests/brevitas/test_brevitas_cnv.py | 16 ++--- tests/brevitas/test_brevitas_debug.py | 58 +++++-------------- tests/brevitas/test_brevitas_fc.py | 19 ++---- ...revitas_non_scaled_quanthardtanh_export.py | 20 +++---- tests/brevitas/test_brevitas_qconv2d.py | 20 +++---- tests/brevitas/test_brevitas_qlinear.py | 20 +++---- .../brevitas/test_brevitas_relu_act_export.py | 36 ++++-------- .../test_brevitas_scaled_qhardtanh_export.py | 20 +++---- 9 files changed, 67 insertions(+), 144 deletions(-) diff --git a/fetch-repos.sh b/fetch-repos.sh index 4416f87bfe..0bfae82854 100755 --- a/fetch-repos.sh +++ b/fetch-repos.sh @@ -29,7 +29,7 @@ QONNX_COMMIT="6ca8f8e0af84e49facac5cdc34735eaf6e938300" FINN_EXP_COMMIT="0aa7e1c44b20cf085b6fe42cff360f0a832afd2c" -BREVITAS_COMMIT="d30ba0d6b3db4a333072624fa3d10827a686488d" +BREVITAS_COMMIT="9bb26bf2798de210a267d1e4aed4c20087e0e8a5" PYVERILATOR_COMMIT="766e457465f5c0dd315490d7b9cc5d74f9a76f4f" CNPY_COMMIT="4e8810b1a8637695171ed346ce68f6984e585ef4" HLSLIB_COMMIT="c17aa478ae574971d115afa9fa4d9c215857d1ac" diff --git a/tests/brevitas/test_brevitas_cnv.py b/tests/brevitas/test_brevitas_cnv.py index 1a96815105..c8adafdce9 100644 --- a/tests/brevitas/test_brevitas_cnv.py +++ b/tests/brevitas/test_brevitas_cnv.py @@ -33,7 +33,7 @@ import numpy as np import os import torch -from brevitas.export import export_finn_onnx, export_qonnx +from brevitas.export import export_qonnx from qonnx.core.modelwrapper import ModelWrapper from qonnx.transformation.fold_constants import FoldConstants from qonnx.transformation.general import GiveUniqueNodeNames, RemoveStaticGraphInputs @@ -50,21 +50,15 @@ @pytest.mark.brevitas_export @pytest.mark.parametrize("abits", [1, 2]) @pytest.mark.parametrize("wbits", [1, 2]) -@pytest.mark.parametrize("QONNX_export", [False, True]) -def test_brevitas_cnv_export_exec(wbits, abits, QONNX_export): +def test_brevitas_cnv_export_exec(wbits, abits): if wbits > abits: pytest.skip("No wbits > abits cases at the moment") cnv = get_test_model_trained("CNV", wbits, abits) ishape = (1, 3, 32, 32) - if QONNX_export: - export_qonnx(cnv, torch.randn(ishape), export_onnx_path) - qonnx_cleanup(export_onnx_path, out_file=export_onnx_path) - model = ModelWrapper(export_onnx_path) - model = model.transform(ConvertQONNXtoFINN()) - model.save(export_onnx_path) - else: - export_finn_onnx(cnv, torch.randn(ishape), export_onnx_path) + export_qonnx(cnv, torch.randn(ishape), export_onnx_path) + qonnx_cleanup(export_onnx_path, out_file=export_onnx_path) model = ModelWrapper(export_onnx_path) + model = model.transform(ConvertQONNXtoFINN()) model = model.transform(GiveUniqueNodeNames()) model = model.transform(InferShapes()) model = model.transform(FoldConstants()) diff --git a/tests/brevitas/test_brevitas_debug.py b/tests/brevitas/test_brevitas_debug.py index 547c026e21..d6879a727b 100644 --- a/tests/brevitas/test_brevitas_debug.py +++ b/tests/brevitas/test_brevitas_debug.py @@ -34,12 +34,9 @@ import onnx.numpy_helper as nph import os import torch -from brevitas.export import export_finn_onnx, export_qonnx +from brevitas.export import export_qonnx from pkgutil import get_data from qonnx.core.modelwrapper import ModelWrapper -from qonnx.transformation.fold_constants import FoldConstants -from qonnx.transformation.general import RemoveStaticGraphInputs -from qonnx.transformation.infer_shapes import InferShapes from qonnx.util.cleanup import cleanup as qonnx_cleanup import finn.core.onnx_exec as oxe @@ -48,41 +45,23 @@ @pytest.mark.brevitas_export -@pytest.mark.parametrize("QONNX_export", [False, True]) @pytest.mark.parametrize("QONNX_FINN_conversion", [False, True]) -def test_brevitas_debug(QONNX_export, QONNX_FINN_conversion): - if (not QONNX_export) and QONNX_FINN_conversion: - pytest.skip("This test configuration is not valid and is thus skipped.") +def test_brevitas_debug(QONNX_FINN_conversion): finn_onnx = "test_brevitas_debug.onnx" fc = get_test_model_trained("TFC", 2, 2) ishape = (1, 1, 28, 28) - if QONNX_export: - dbg_hook = bo.enable_debug(fc, proxy_level=True) - export_qonnx(fc, torch.randn(ishape), finn_onnx) - # DebugMarkers have the brevitas.onnx domain, so that needs adjusting - model = ModelWrapper(finn_onnx) - dbg_nodes = model.get_nodes_by_op_type("DebugMarker") - for dbg_node in dbg_nodes: - dbg_node.domain = "qonnx.custom_op.general" - model.save(finn_onnx) - qonnx_cleanup(finn_onnx, out_file=finn_onnx) - if QONNX_FINN_conversion: - model = ModelWrapper(finn_onnx) - model = model.transform(ConvertQONNXtoFINN()) - model.save(finn_onnx) - else: - dbg_hook = bo.enable_debug(fc) - export_finn_onnx(fc, torch.randn(ishape), finn_onnx) + dbg_hook = bo.enable_debug(fc, proxy_level=True) + export_qonnx(fc, torch.randn(ishape), finn_onnx) + # DebugMarkers have the brevitas.onnx domain, so that needs adjusting + model = ModelWrapper(finn_onnx) + dbg_nodes = model.get_nodes_by_op_type("DebugMarker") + for dbg_node in dbg_nodes: + dbg_node.domain = "qonnx.custom_op.general" + model.save(finn_onnx) + qonnx_cleanup(finn_onnx, out_file=finn_onnx) + if QONNX_FINN_conversion: model = ModelWrapper(finn_onnx) - # DebugMarkers have the brevitas.onnx domain, so that needs adjusting - # ToDo: We should probably have transformation pass, which does this - # domain conversion for us? - dbg_nodes = model.get_nodes_by_op_type("DebugMarker") - for dbg_node in dbg_nodes: - dbg_node.domain = "qonnx.custom_op.general" - model = model.transform(InferShapes()) - model = model.transform(FoldConstants()) - model = model.transform(RemoveStaticGraphInputs()) + model = model.transform(ConvertQONNXtoFINN()) model.save(finn_onnx) model = ModelWrapper(finn_onnx) assert len(model.graph.input) == 1 @@ -106,17 +85,12 @@ def test_brevitas_debug(QONNX_export, QONNX_FINN_conversion): names_common = names_brevitas.intersection(names_finn) # The different exports return debug markers in different numbers and places print(len(names_common)) - if QONNX_export and not QONNX_FINN_conversion: + if not QONNX_FINN_conversion: assert len(names_common) == 12 - elif QONNX_export and QONNX_FINN_conversion: - assert len(names_common) == 8 else: - assert len(names_common) == 16 + assert len(names_common) == 8 for dbg_name in names_common: - if QONNX_export: - tensor_pytorch = dbg_hook.values[dbg_name].value.detach().numpy() - else: - tensor_pytorch = dbg_hook.values[dbg_name].detach().numpy() + tensor_pytorch = dbg_hook.values[dbg_name].value.detach().numpy() tensor_finn = output_dict[dbg_name] assert np.isclose(tensor_finn, tensor_pytorch, atol=1e-5).all() os.remove(finn_onnx) diff --git a/tests/brevitas/test_brevitas_fc.py b/tests/brevitas/test_brevitas_fc.py index 3aaa96f9a5..842d099f57 100644 --- a/tests/brevitas/test_brevitas_fc.py +++ b/tests/brevitas/test_brevitas_fc.py @@ -32,7 +32,7 @@ import onnx import onnx.numpy_helper as nph import torch -from brevitas.export import export_finn_onnx, export_qonnx +from brevitas.export import export_qonnx from pkgutil import get_data from qonnx.core.modelwrapper import ModelWrapper from qonnx.transformation.fold_constants import FoldConstants @@ -55,26 +55,19 @@ @pytest.mark.parametrize("wbits", [1, 2]) # network topology / size @pytest.mark.parametrize("size", ["TFC", "SFC", "LFC"]) -# QONNX export -@pytest.mark.parametrize("QONNX_export", [False, True]) -def test_brevitas_fc_onnx_export_and_exec(size, wbits, abits, QONNX_export): +def test_brevitas_fc_onnx_export_and_exec(size, wbits, abits): if size == "LFC" and wbits == 2 and abits == 2: pytest.skip("No LFC-w2a2 present at the moment") if wbits > abits: pytest.skip("No wbits > abits cases at the moment") - nname = "%s_%dW%dA_QONNX-%d" % (size, wbits, abits, QONNX_export) + nname = "%s_%dW%dA" % (size, wbits, abits) finn_onnx = export_onnx_path + "/%s.onnx" % nname fc = get_test_model_trained(size, wbits, abits) ishape = (1, 1, 28, 28) - if QONNX_export: - export_qonnx(fc, torch.randn(ishape), finn_onnx) - qonnx_cleanup(finn_onnx, out_file=finn_onnx) - model = ModelWrapper(finn_onnx) - model = model.transform(ConvertQONNXtoFINN()) - model.save(finn_onnx) - else: - export_finn_onnx(fc, torch.randn(ishape), finn_onnx) + export_qonnx(fc, torch.randn(ishape), finn_onnx) + qonnx_cleanup(finn_onnx, out_file=finn_onnx) model = ModelWrapper(finn_onnx) + model = model.transform(ConvertQONNXtoFINN()) model = model.transform(InferShapes()) model = model.transform(FoldConstants()) model = model.transform(RemoveStaticGraphInputs()) diff --git a/tests/brevitas/test_brevitas_non_scaled_quanthardtanh_export.py b/tests/brevitas/test_brevitas_non_scaled_quanthardtanh_export.py index 2911303501..08a193714a 100644 --- a/tests/brevitas/test_brevitas_non_scaled_quanthardtanh_export.py +++ b/tests/brevitas/test_brevitas_non_scaled_quanthardtanh_export.py @@ -35,7 +35,7 @@ from brevitas.core.quant import QuantType from brevitas.core.restrict_val import RestrictValueType from brevitas.core.scaling import ScalingImplType -from brevitas.export import export_finn_onnx, export_qonnx +from brevitas.export import export_qonnx from brevitas.nn import QuantHardTanh from qonnx.core.modelwrapper import ModelWrapper from qonnx.transformation.infer_shapes import InferShapes @@ -51,8 +51,7 @@ @pytest.mark.parametrize("abits", [1, 2, 4, 8]) @pytest.mark.parametrize("narrow_range", [False, True]) @pytest.mark.parametrize("max_val", [1.0, 1 - 2 ** (-7)]) -@pytest.mark.parametrize("QONNX_export", [False, True]) -def test_brevitas_act_export_qhardtanh_nonscaled(abits, narrow_range, max_val, QONNX_export): +def test_brevitas_act_export_qhardtanh_nonscaled(abits, narrow_range, max_val): def get_quant_type(bit_width): if bit_width is None: return QuantType.FP @@ -73,16 +72,11 @@ def get_quant_type(bit_width): scaling_impl_type=ScalingImplType.CONST, narrow_range=narrow_range, ) - if QONNX_export: - m_path = export_onnx_path - export_qonnx(b_act, torch.randn(ishape), m_path) - qonnx_cleanup(m_path, out_file=m_path) - model = ModelWrapper(m_path) - model = model.transform(ConvertQONNXtoFINN()) - model.save(m_path) - else: - export_finn_onnx(b_act, torch.randn(ishape), export_onnx_path) - model = ModelWrapper(export_onnx_path) + m_path = export_onnx_path + export_qonnx(b_act, torch.randn(ishape), m_path) + qonnx_cleanup(m_path, out_file=m_path) + model = ModelWrapper(m_path) + model = model.transform(ConvertQONNXtoFINN()) model = model.transform(InferShapes()) inp_tensor = np.random.uniform(low=min_val, high=max_val, size=ishape).astype(np.float32) idict = {model.graph.input[0].name: inp_tensor} diff --git a/tests/brevitas/test_brevitas_qconv2d.py b/tests/brevitas/test_brevitas_qconv2d.py index faeb3ff48e..4b27671891 100644 --- a/tests/brevitas/test_brevitas_qconv2d.py +++ b/tests/brevitas/test_brevitas_qconv2d.py @@ -35,7 +35,7 @@ from brevitas.core.restrict_val import RestrictValueType from brevitas.core.scaling import ScalingImplType from brevitas.core.stats import StatsOp -from brevitas.export import export_finn_onnx, export_qonnx +from brevitas.export import export_qonnx from brevitas.nn import QuantConv2d from qonnx.core.datatype import DataType from qonnx.core.modelwrapper import ModelWrapper @@ -53,8 +53,7 @@ @pytest.mark.parametrize("dw", [False, True]) @pytest.mark.parametrize("bias", [True, False]) @pytest.mark.parametrize("in_channels", [32]) -@pytest.mark.parametrize("QONNX_export", [False, True]) -def test_brevitas_QConv2d(dw, bias, in_channels, QONNX_export): +def test_brevitas_QConv2d(dw, bias, in_channels): ishape = (1, 32, 111, 111) if dw is True: groups = in_channels @@ -93,16 +92,11 @@ def test_brevitas_QConv2d(dw, bias, in_channels, QONNX_export): weight_tensor = gen_finn_dt_tensor(DataType["INT4"], w_shape) b_conv.weight = torch.nn.Parameter(torch.from_numpy(weight_tensor).float()) b_conv.eval() - if QONNX_export: - m_path = export_onnx_path - export_qonnx(b_conv, torch.randn(ishape), m_path) - qonnx_cleanup(m_path, out_file=m_path) - model = ModelWrapper(m_path) - model = model.transform(ConvertQONNXtoFINN()) - model.save(m_path) - else: - export_finn_onnx(b_conv, torch.randn(ishape), export_onnx_path) - model = ModelWrapper(export_onnx_path) + m_path = export_onnx_path + export_qonnx(b_conv, torch.randn(ishape), m_path) + qonnx_cleanup(m_path, out_file=m_path) + model = ModelWrapper(m_path) + model = model.transform(ConvertQONNXtoFINN()) model = model.transform(InferShapes()) inp_tensor = np.random.uniform(low=-1.0, high=1.0, size=ishape).astype(np.float32) idict = {model.graph.input[0].name: inp_tensor} diff --git a/tests/brevitas/test_brevitas_qlinear.py b/tests/brevitas/test_brevitas_qlinear.py index 551345f649..a6ea077e7a 100644 --- a/tests/brevitas/test_brevitas_qlinear.py +++ b/tests/brevitas/test_brevitas_qlinear.py @@ -32,7 +32,7 @@ import os import torch from brevitas.core.quant import QuantType -from brevitas.export import export_finn_onnx, export_qonnx +from brevitas.export import export_qonnx from brevitas.nn import QuantLinear from qonnx.core.datatype import DataType from qonnx.core.modelwrapper import ModelWrapper @@ -52,8 +52,7 @@ @pytest.mark.parametrize("in_features", [3]) @pytest.mark.parametrize("w_bits", [4]) @pytest.mark.parametrize("i_dtype", [DataType["UINT4"]]) -@pytest.mark.parametrize("QONNX_export", [False, True]) -def test_brevitas_qlinear(bias, out_features, in_features, w_bits, i_dtype, QONNX_export): +def test_brevitas_qlinear(bias, out_features, in_features, w_bits, i_dtype): i_shape = (1, in_features) w_shape = (out_features, in_features) b_linear = QuantLinear( @@ -68,16 +67,11 @@ def test_brevitas_qlinear(bias, out_features, in_features, w_bits, i_dtype, QONN weight_tensor_fp = np.random.uniform(low=-1.0, high=1.0, size=w_shape).astype(np.float32) b_linear.weight.data = torch.from_numpy(weight_tensor_fp) b_linear.eval() - if QONNX_export: - m_path = export_onnx_path - export_qonnx(b_linear, torch.randn(i_shape), m_path) - qonnx_cleanup(m_path, out_file=m_path) - model = ModelWrapper(m_path) - model = model.transform(ConvertQONNXtoFINN()) - model.save(m_path) - else: - export_finn_onnx(b_linear, torch.randn(i_shape), export_onnx_path) - model = ModelWrapper(export_onnx_path) + m_path = export_onnx_path + export_qonnx(b_linear, torch.randn(i_shape), m_path) + qonnx_cleanup(m_path, out_file=m_path) + model = ModelWrapper(m_path) + model = model.transform(ConvertQONNXtoFINN()) model = model.transform(InferShapes()) inp_tensor = gen_finn_dt_tensor(i_dtype, i_shape) idict = {model.graph.input[0].name: inp_tensor} diff --git a/tests/brevitas/test_brevitas_relu_act_export.py b/tests/brevitas/test_brevitas_relu_act_export.py index 9e1fcbdc2f..2254670202 100644 --- a/tests/brevitas/test_brevitas_relu_act_export.py +++ b/tests/brevitas/test_brevitas_relu_act_export.py @@ -33,7 +33,7 @@ import os import torch from brevitas.core.scaling import ScalingImplType -from brevitas.export import export_finn_onnx, export_qonnx +from brevitas.export import export_qonnx from brevitas.nn import QuantReLU from qonnx.core.modelwrapper import ModelWrapper from qonnx.transformation.infer_shapes import InferShapes @@ -48,25 +48,18 @@ @pytest.mark.brevitas_export @pytest.mark.parametrize("abits", [2, 4, 8]) @pytest.mark.parametrize("ishape", [(1, 15), (1, 32, 1, 1)]) -@pytest.mark.parametrize("QONNX_export", [False, True]) def test_brevitas_act_export_relu( abits, ishape, - QONNX_export, ): b_act = QuantReLU( bit_width=abits, ) - if QONNX_export: - m_path = export_onnx_path - export_qonnx(b_act, torch.randn(ishape), m_path) - qonnx_cleanup(m_path, out_file=m_path) - model = ModelWrapper(m_path) - model = model.transform(ConvertQONNXtoFINN()) - model.save(m_path) - else: - export_finn_onnx(b_act, torch.randn(ishape), export_onnx_path) - model = ModelWrapper(export_onnx_path) + m_path = export_onnx_path + export_qonnx(b_act, torch.randn(ishape), m_path) + qonnx_cleanup(m_path, out_file=m_path) + model = ModelWrapper(m_path) + model = model.transform(ConvertQONNXtoFINN()) model = model.transform(InferShapes()) inp_tensor = np.random.uniform(low=-1.0, high=6.0, size=ishape).astype(np.float32) idict = {model.graph.input[0].name: inp_tensor} @@ -83,11 +76,9 @@ def test_brevitas_act_export_relu( @pytest.mark.brevitas_export @pytest.mark.parametrize("abits", [2, 4, 8]) @pytest.mark.parametrize("ishape", [(1, 15, 4, 4), (1, 32, 1, 1)]) -@pytest.mark.parametrize("QONNX_export", [False, True]) def test_brevitas_act_export_relu_channel( abits, ishape, - QONNX_export, ): ch = ishape[1] b_act = QuantReLU( @@ -97,16 +88,11 @@ def test_brevitas_act_export_relu_channel( scaling_per_output_channel=True, per_channel_broadcastable_shape=(1, ch, 1, 1), ) - if QONNX_export: - m_path = export_onnx_path - export_qonnx(b_act, torch.randn(ishape), m_path) - qonnx_cleanup(m_path, out_file=m_path) - model = ModelWrapper(m_path) - model = model.transform(ConvertQONNXtoFINN()) - model.save(m_path) - else: - export_finn_onnx(b_act, torch.randn(ishape), export_onnx_path) - model = ModelWrapper(export_onnx_path) + m_path = export_onnx_path + export_qonnx(b_act, torch.randn(ishape), m_path) + qonnx_cleanup(m_path, out_file=m_path) + model = ModelWrapper(m_path) + model = model.transform(ConvertQONNXtoFINN()) model = model.transform(InferShapes()) inp_tensor = np.random.uniform(low=-1.0, high=6.0, size=ishape).astype(np.float32) idict = {model.graph.input[0].name: inp_tensor} diff --git a/tests/brevitas/test_brevitas_scaled_qhardtanh_export.py b/tests/brevitas/test_brevitas_scaled_qhardtanh_export.py index 72a15810aa..e7d87faed8 100644 --- a/tests/brevitas/test_brevitas_scaled_qhardtanh_export.py +++ b/tests/brevitas/test_brevitas_scaled_qhardtanh_export.py @@ -35,7 +35,7 @@ from brevitas.core.quant import QuantType from brevitas.core.restrict_val import RestrictValueType from brevitas.core.scaling import ScalingImplType -from brevitas.export import export_finn_onnx, export_qonnx +from brevitas.export import export_qonnx from brevitas.nn import QuantHardTanh from qonnx.core.modelwrapper import ModelWrapper from qonnx.transformation.infer_shapes import InferShapes @@ -53,9 +53,8 @@ @pytest.mark.parametrize("min_val", [-1.0, -(1 - 2 ** (-7)), -2]) @pytest.mark.parametrize("max_val", [1.0, 1 - 2 ** (-7), 2]) @pytest.mark.parametrize("scaling_impl_type", [ScalingImplType.CONST, ScalingImplType.PARAMETER]) -@pytest.mark.parametrize("QONNX_export", [False, True]) def test_brevitas_act_export_qhardtanh_scaled( - abits, narrow_range, min_val, max_val, scaling_impl_type, QONNX_export + abits, narrow_range, min_val, max_val, scaling_impl_type ): def get_quant_type(bit_width): if bit_width is None: @@ -86,16 +85,11 @@ def get_quant_type(bit_width): ) } b_act.load_state_dict(checkpoint) - if QONNX_export: - m_path = export_onnx_path - export_qonnx(b_act, torch.randn(ishape), m_path) - qonnx_cleanup(m_path, out_file=m_path) - model = ModelWrapper(m_path) - model = model.transform(ConvertQONNXtoFINN()) - model.save(m_path) - else: - export_finn_onnx(b_act, torch.randn(ishape), export_onnx_path) - model = ModelWrapper(export_onnx_path) + m_path = export_onnx_path + export_qonnx(b_act, torch.randn(ishape), m_path) + qonnx_cleanup(m_path, out_file=m_path) + model = ModelWrapper(m_path) + model = model.transform(ConvertQONNXtoFINN()) model = model.transform(InferShapes()) inp_tensor = np.random.uniform(low=min_val, high=max_val, size=ishape).astype(np.float32) idict = {model.graph.input[0].name: inp_tensor} From f2872c7fbe3ced9c9441da7e5a07383e2b757fcf Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Thu, 29 Jun 2023 11:42:14 +0100 Subject: [PATCH 189/665] Add missing itertools library import Signed-off-by: Fionn O'Donohoe --- tests/end2end/test_end2end_bnn_pynq.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index 14616522ec..564a1ee7cb 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -30,6 +30,8 @@ import numpy as np +import itertools + # as of Feb'20 there is a bug that segfaults ONNX shape inference if we # import pytorch before onnx, so we make sure to import onnx first import onnx # NOQA From 14192c643cdee0cfe26cbf070a443845750ff746 Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 4 Jul 2023 08:59:25 +0100 Subject: [PATCH 190/665] [Tests] Remove finn onnx export from end2end bnn tests --- tests/end2end/test_end2end_bnn_pynq.py | 159 ++++++++++--------------- 1 file changed, 66 insertions(+), 93 deletions(-) diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index b08028e7cb..87c1d6005c 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -36,7 +36,7 @@ import os import torch import warnings -from brevitas.export import export_finn_onnx, export_qonnx +from brevitas.export import export_qonnx from dataset_loading import cifar, mnist from qonnx.core.datatype import DataType from qonnx.core.modelwrapper import ModelWrapper @@ -106,12 +106,11 @@ rtlsim_trace = False -def get_checkpoint_name(topology, wbits, abits, QONNX_export, step): - return build_dir + "/end2end_%s_w%da%d_QONNX-%d_%s.onnx" % ( +def get_checkpoint_name(topology, wbits, abits, step): + return build_dir + "/end2end_%s_w%da%d_%s.onnx" % ( topology, wbits, abits, - QONNX_export, step, ) @@ -293,28 +292,24 @@ def topology2dataset(topology): @pytest.mark.parametrize("wbits", [1, 2]) @pytest.mark.parametrize("abits", [1, 2]) @pytest.mark.parametrize("topology", ["lfc", "tfc", "cnv"]) -@pytest.mark.parametrize("QONNX_export", [False, True]) @pytest.mark.end2end class TestEnd2End: - def test_export(self, topology, wbits, abits, QONNX_export): + def test_export(self, topology, wbits, abits): if wbits > abits: pytest.skip("No wbits > abits end2end network configs for now") if topology == "lfc" and not (wbits == 1 and abits == 1): pytest.skip("Skipping certain lfc configs") (model, ishape) = get_trained_network_and_ishape(topology, wbits, abits) - chkpt_name = get_checkpoint_name(topology, wbits, abits, QONNX_export, "export") - if QONNX_export: - export_qonnx(model, torch.randn(ishape), chkpt_name, opset_version=13) - qonnx_cleanup(chkpt_name, out_file=chkpt_name) - model = ModelWrapper(chkpt_name) - model = model.transform(ConvertQONNXtoFINN()) - model.save(chkpt_name) - else: - export_finn_onnx(model, torch.randn(ishape), chkpt_name) + chkpt_name = get_checkpoint_name(topology, wbits, abits, "export") + export_qonnx(model, torch.randn(ishape), chkpt_name, opset_version=13) + qonnx_cleanup(chkpt_name, out_file=chkpt_name) + model = ModelWrapper(chkpt_name) + model = model.transform(ConvertQONNXtoFINN()) + model.save(chkpt_name) assert os.path.isfile(chkpt_name) - def test_import_and_tidy(self, topology, wbits, abits, QONNX_export): - prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, QONNX_export, "export") + def test_import_and_tidy(self, topology, wbits, abits): + prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, "export") model = load_test_checkpoint_or_skip(prev_chkpt_name) model = model.transform(InferShapes()) model = model.transform(FoldConstants()) @@ -322,20 +317,22 @@ def test_import_and_tidy(self, topology, wbits, abits, QONNX_export): model = model.transform(GiveReadableTensorNames()) model = model.transform(InferDataTypes()) model = model.transform(RemoveStaticGraphInputs()) - chkpt = get_checkpoint_name(topology, wbits, abits, QONNX_export, "import_and_tidy") + chkpt = get_checkpoint_name(topology, wbits, abits, "import_and_tidy") model.save(chkpt) - def test_add_pre_and_postproc(self, topology, wbits, abits, QONNX_export): - prev_chkpt_name = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "import_and_tidy" - ) + def test_add_pre_and_postproc(self, topology, wbits, abits): + prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, "import_and_tidy") model = load_test_checkpoint_or_skip(prev_chkpt_name) global_inp_name = model.graph.input[0].name ishape = model.get_tensor_shape(global_inp_name) # preprocessing: torchvision's ToTensor divides uint8 inputs by 255 totensor_pyt = ToTensor() - chkpt_preproc_name = get_checkpoint_name(topology, wbits, abits, QONNX_export, "preproc") - export_finn_onnx(totensor_pyt, torch.randn(ishape), chkpt_preproc_name, opset_version=13) + chkpt_preproc_name = get_checkpoint_name(topology, wbits, abits, "preproc") + export_qonnx(totensor_pyt, torch.randn(ishape), chkpt_preproc_name, opset_version=13) + qonnx_cleanup(chkpt_preproc_name, out_file=chkpt_preproc_name) + pre_model = ModelWrapper(chkpt_preproc_name) + pre_model = pre_model.transform(ConvertQONNXtoFINN()) + pre_model.save(chkpt_preproc_name) assert os.path.isfile(chkpt_preproc_name) # join preprocessing and core model pre_model = ModelWrapper(chkpt_preproc_name) @@ -347,7 +344,7 @@ def test_add_pre_and_postproc(self, topology, wbits, abits, QONNX_export): model.set_tensor_datatype(global_inp_name, DataType["UINT8"]) # postprocessing: insert Top-1 node at the end model = model.transform(InsertTopK(k=1)) - chkpt_name = get_checkpoint_name(topology, wbits, abits, QONNX_export, "pre_post") + chkpt_name = get_checkpoint_name(topology, wbits, abits, "pre_post") # tidy-up again model = model.transform(InferShapes()) model = model.transform(FoldConstants()) @@ -358,8 +355,8 @@ def test_add_pre_and_postproc(self, topology, wbits, abits, QONNX_export): model.save(chkpt_name) assert os.path.isfile(chkpt_name) - def test_streamline(self, topology, wbits, abits, QONNX_export): - prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, QONNX_export, "pre_post") + def test_streamline(self, topology, wbits, abits): + prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, "pre_post") model = load_test_checkpoint_or_skip(prev_chkpt_name) model = model.transform(absorb.AbsorbSignBiasIntoMultiThreshold()) # move past any reshapes to be able to streamline input scaling @@ -375,10 +372,10 @@ def test_streamline(self, topology, wbits, abits, QONNX_export): model = model.transform(absorb.AbsorbScalarMulAddIntoTopK()) model = model.transform(InferDataLayouts()) model = model.transform(RemoveUnusedTensors()) - model.save(get_checkpoint_name(topology, wbits, abits, QONNX_export, "streamline")) + model.save(get_checkpoint_name(topology, wbits, abits, "streamline")) - def test_convert_to_hls_layers(self, topology, wbits, abits, QONNX_export): - prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, QONNX_export, "streamline") + def test_convert_to_hls_layers(self, topology, wbits, abits): + prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, "streamline") model = load_test_checkpoint_or_skip(prev_chkpt_name) if topology == "tfc" and wbits == 1 and abits == 1: # use standalone thresholds for tfc-w1a1 to also exercise that option @@ -400,9 +397,7 @@ def test_convert_to_hls_layers(self, topology, wbits, abits, QONNX_export): model = model.transform(absorb.AbsorbConsecutiveTransposes()) model = model.transform(GiveUniqueNodeNames()) model = model.transform(InferDataLayouts()) - model.save( - get_checkpoint_name(topology, wbits, abits, QONNX_export, "convert_to_hls_layers") - ) + model.save(get_checkpoint_name(topology, wbits, abits, "convert_to_hls_layers")) exp_layer_counts = { "tfc": [ ("Reshape", 1), @@ -439,57 +434,45 @@ def test_convert_to_hls_layers(self, topology, wbits, abits, QONNX_export): for op_type, exp_count in exp_layer_counts: assert len(model.get_nodes_by_op_type(op_type)) == exp_count - def test_create_dataflow_partition(self, topology, wbits, abits, QONNX_export): - prev_chkpt_name = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "convert_to_hls_layers" - ) + def test_create_dataflow_partition(self, topology, wbits, abits): + prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, "convert_to_hls_layers") model = load_test_checkpoint_or_skip(prev_chkpt_name) parent_model = model.transform(CreateDataflowPartition()) - parent_model_chkpt = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "dataflow_parent" - ) + parent_model_chkpt = get_checkpoint_name(topology, wbits, abits, "dataflow_parent") parent_model.save(parent_model_chkpt) sdp_node = parent_model.get_nodes_by_op_type("StreamingDataflowPartition")[0] sdp_node = getCustomOp(sdp_node) dataflow_model_filename = sdp_node.get_nodeattr("model") dataflow_model = load_test_checkpoint_or_skip(dataflow_model_filename) - dataflow_model_chkpt = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "dataflow_model" - ) + dataflow_model_chkpt = get_checkpoint_name(topology, wbits, abits, "dataflow_model") dataflow_model.save(dataflow_model_chkpt) - def test_fold(self, topology, wbits, abits, QONNX_export): - prev_chkpt_name = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "dataflow_model" - ) + def test_fold(self, topology, wbits, abits): + prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, "dataflow_model") model = load_test_checkpoint_or_skip(prev_chkpt_name) folding_fxn = get_folding_function(topology, wbits, abits) model = folding_fxn(model) - model.save(get_checkpoint_name(topology, wbits, abits, QONNX_export, "fold")) + model.save(get_checkpoint_name(topology, wbits, abits, "fold")) - def test_minimize_bit_width(self, topology, wbits, abits, QONNX_export): - prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, QONNX_export, "fold") + def test_minimize_bit_width(self, topology, wbits, abits): + prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, "fold") model = load_test_checkpoint_or_skip(prev_chkpt_name) model = model.transform(MinimizeAccumulatorWidth()) model = model.transform(MinimizeWeightBitWidth()) - curr_chkpt_name = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "minimize_bit_width" - ) + curr_chkpt_name = get_checkpoint_name(topology, wbits, abits, "minimize_bit_width") model.save(curr_chkpt_name) @pytest.mark.slow @pytest.mark.vivado - def test_cppsim(self, topology, wbits, abits, QONNX_export): - prev_chkpt_name = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "minimize_bit_width" - ) + def test_cppsim(self, topology, wbits, abits): + prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, "minimize_bit_width") model = load_test_checkpoint_or_skip(prev_chkpt_name) model = model.transform(PrepareCppSim()) model = model.transform(CompileCppSim()) model = model.transform(SetExecMode("cppsim")) - cppsim_chkpt = get_checkpoint_name(topology, wbits, abits, QONNX_export, "cppsim") + cppsim_chkpt = get_checkpoint_name(topology, wbits, abits, "cppsim") model.save(cppsim_chkpt) - parent_chkpt = get_checkpoint_name(topology, wbits, abits, QONNX_export, "dataflow_parent") + parent_chkpt = get_checkpoint_name(topology, wbits, abits, "dataflow_parent") (input_tensor_npy, output_tensor_npy) = get_golden_io_pair( topology, wbits, abits, return_topk=1 ) @@ -499,36 +482,34 @@ def test_cppsim(self, topology, wbits, abits, QONNX_export): @pytest.mark.slow @pytest.mark.vivado @pytest.mark.parametrize("kind", ["zynq", "alveo"]) - def test_ipgen(self, topology, wbits, abits, QONNX_export, kind): + def test_ipgen(self, topology, wbits, abits, kind): if kind == "alveo" and ("VITIS_PATH" not in os.environ): pytest.skip("VITIS_PATH not set") - prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, QONNX_export, "fold") + prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, "fold") model = load_test_checkpoint_or_skip(prev_chkpt_name) test_fpga_part = get_build_env(kind, target_clk_ns)["part"] model = model.transform(GiveUniqueNodeNames()) model = model.transform(PrepareIP(test_fpga_part, target_clk_ns)) model = model.transform(HLSSynthIP()) - model.save(get_checkpoint_name(topology, wbits, abits, QONNX_export, "ipgen_" + kind)) + model.save(get_checkpoint_name(topology, wbits, abits, "ipgen_" + kind)) @pytest.mark.slow @pytest.mark.vivado @pytest.mark.parametrize("kind", ["zynq", "alveo"]) - def test_set_fifo_depths(self, topology, wbits, abits, QONNX_export, kind): - prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, QONNX_export, "ipgen_" + kind) + def test_set_fifo_depths(self, topology, wbits, abits, kind): + prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, "ipgen_" + kind) model = load_test_checkpoint_or_skip(prev_chkpt_name) test_fpga_part = get_build_env(kind, target_clk_ns)["part"] model = model.transform(InsertAndSetFIFODepths(test_fpga_part, target_clk_ns)) fifo_layers = model.get_nodes_by_op_type("StreamingFIFO") assert len(fifo_layers) > 0 - model.save(get_checkpoint_name(topology, wbits, abits, QONNX_export, "fifodepth_" + kind)) + model.save(get_checkpoint_name(topology, wbits, abits, "fifodepth_" + kind)) @pytest.mark.slow @pytest.mark.vivado @pytest.mark.parametrize("kind", ["zynq"]) - def test_ipstitch_rtlsim(self, topology, wbits, abits, QONNX_export, kind): - prev_chkpt_name = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "fifodepth_" + kind - ) + def test_ipstitch_rtlsim(self, topology, wbits, abits, kind): + prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, "fifodepth_" + kind) model = load_test_checkpoint_or_skip(prev_chkpt_name) test_fpga_part = get_build_env(kind, target_clk_ns)["part"] model = model.transform(InsertDWC()) @@ -547,11 +528,9 @@ def test_ipstitch_rtlsim(self, topology, wbits, abits, QONNX_export, kind): if rtlsim_trace: model.set_metadata_prop("rtlsim_trace", "%s_w%da%d.vcd" % (topology, wbits, abits)) os.environ["RTLSIM_TRACE_DEPTH"] = "3" - rtlsim_chkpt = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "ipstitch_rtlsim_" + kind - ) + rtlsim_chkpt = get_checkpoint_name(topology, wbits, abits, "ipstitch_rtlsim_" + kind) model.save(rtlsim_chkpt) - parent_chkpt = get_checkpoint_name(topology, wbits, abits, QONNX_export, "dataflow_parent") + parent_chkpt = get_checkpoint_name(topology, wbits, abits, "dataflow_parent") (input_tensor_npy, output_tensor_npy) = get_golden_io_pair( topology, wbits, abits, return_topk=1 ) @@ -561,10 +540,8 @@ def test_ipstitch_rtlsim(self, topology, wbits, abits, QONNX_export, kind): @pytest.mark.slow @pytest.mark.vivado @pytest.mark.parametrize("kind", ["zynq"]) - def test_throughput_rtlsim(self, topology, wbits, abits, QONNX_export, kind): - prev_chkpt_name = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "ipstitch_rtlsim_" + kind - ) + def test_throughput_rtlsim(self, topology, wbits, abits, kind): + prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, "ipstitch_rtlsim_" + kind) model = load_test_checkpoint_or_skip(prev_chkpt_name) n_nodes = len(model.graph.node) perf_est = model.analysis(dataflow_performance) @@ -580,16 +557,14 @@ def test_throughput_rtlsim(self, topology, wbits, abits, QONNX_export, kind): @pytest.mark.slow @pytest.mark.vivado @pytest.mark.parametrize("kind", ["zynq"]) - def test_validate_top1(self, topology, wbits, abits, QONNX_export, kind): + def test_validate_top1(self, topology, wbits, abits, kind): if "TEST_END2END_VALIDATE_TOP1" not in os.environ: pytest.skip("TEST_END2END_VALIDATE_TOP1 not set") - prepostproc_chkpt = get_checkpoint_name(topology, wbits, abits, QONNX_export, "pre_post") - streamline_chkpt = get_checkpoint_name(topology, wbits, abits, QONNX_export, "streamline") - parent_chkpt = get_checkpoint_name(topology, wbits, abits, QONNX_export, "dataflow_parent") - cppsim_chkpt = get_checkpoint_name(topology, wbits, abits, QONNX_export, "cppsim") - rtlsim_chkpt = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "ipstitch_rtlsim_" + kind - ) + prepostproc_chkpt = get_checkpoint_name(topology, wbits, abits, "pre_post") + streamline_chkpt = get_checkpoint_name(topology, wbits, abits, "streamline") + parent_chkpt = get_checkpoint_name(topology, wbits, abits, "dataflow_parent") + cppsim_chkpt = get_checkpoint_name(topology, wbits, abits, "cppsim") + rtlsim_chkpt = get_checkpoint_name(topology, wbits, abits, "ipstitch_rtlsim_" + kind) dataset = topology2dataset(topology) assert measure_top1_accuracy(prepostproc_chkpt, dataset) > 80 assert measure_top1_accuracy(streamline_chkpt, dataset) > 80 @@ -600,27 +575,25 @@ def test_validate_top1(self, topology, wbits, abits, QONNX_export, kind): @pytest.mark.vivado @pytest.mark.vitis @pytest.mark.parametrize("kind", ["zynq", "alveo"]) - def test_build(self, topology, wbits, abits, QONNX_export, kind): + def test_build(self, topology, wbits, abits, kind): if kind == "alveo" and ("VITIS_PATH" not in os.environ): pytest.skip("VITIS_PATH not set") - prev_chkpt_name = get_checkpoint_name( - topology, wbits, abits, QONNX_export, "fifodepth_" + kind - ) + prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, "fifodepth_" + kind) model = load_test_checkpoint_or_skip(prev_chkpt_name) cfg = get_build_env(kind, target_clk_ns) model = model.transform(cfg["build_fxn"]) model = model.transform(AnnotateResources("synth")) - model.save(get_checkpoint_name(topology, wbits, abits, QONNX_export, "build_" + kind)) + model.save(get_checkpoint_name(topology, wbits, abits, "build_" + kind)) @pytest.mark.slow @pytest.mark.vivado @pytest.mark.vitis @pytest.mark.parametrize("kind", ["zynq", "alveo"]) - def test_make_pynq_driver(self, topology, wbits, abits, QONNX_export, kind): + def test_make_pynq_driver(self, topology, wbits, abits, kind): if kind == "alveo" and ("VITIS_PATH" not in os.environ): pytest.skip("VITIS_PATH not set") - prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, QONNX_export, "build_" + kind) + prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, "build_" + kind) model = load_test_checkpoint_or_skip(prev_chkpt_name) kind_to_driver_platform = {"zynq": "zynq-iodma", "alveo": "alveo"} model = model.transform(MakePYNQDriver(kind_to_driver_platform[kind])) - model.save(get_checkpoint_name(topology, wbits, abits, QONNX_export, "driver_" + kind)) + model.save(get_checkpoint_name(topology, wbits, abits, "driver_" + kind)) From 41d6056b4962594251347d2369b5d9cce43d8d26 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 5 Jul 2023 09:13:13 +0100 Subject: [PATCH 191/665] [GHA] Update docker image workflow to only target dev --- .github/workflows/docker-image.yml | 2 -- 1 file changed, 2 deletions(-) diff --git a/.github/workflows/docker-image.yml b/.github/workflows/docker-image.yml index 00c25a4a31..f9a251a8c7 100644 --- a/.github/workflows/docker-image.yml +++ b/.github/workflows/docker-image.yml @@ -1,8 +1,6 @@ name: DockerImage on: - pull_request: - branches: [ dev ] push: branches: [ dev ] From 85f37d4a56f4c2c255ab778bb224135345dda919 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 5 Jul 2023 12:18:42 +0100 Subject: [PATCH 192/665] [Tests/Deps] Update qonnx commit and update tests --- fetch-repos.sh | 2 +- .../qonnx/infer_quant_avg_pool_2d.py | 3 +- tests/end2end/test_end2end_cybsec_mlp.py | 94 +++++++------------ .../test_convert_to_hls_layers_cnv.py | 11 ++- .../test_convert_to_hls_layers_fc.py | 13 ++- tests/transformation/test_qonnx_to_finn.py | 31 +----- 6 files changed, 56 insertions(+), 98 deletions(-) diff --git a/fetch-repos.sh b/fetch-repos.sh index 0bfae82854..651f06452b 100755 --- a/fetch-repos.sh +++ b/fetch-repos.sh @@ -27,7 +27,7 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -QONNX_COMMIT="6ca8f8e0af84e49facac5cdc34735eaf6e938300" +QONNX_COMMIT="0aec35a16948155e81c1640b71650206e733db3e" FINN_EXP_COMMIT="0aa7e1c44b20cf085b6fe42cff360f0a832afd2c" BREVITAS_COMMIT="9bb26bf2798de210a267d1e4aed4c20087e0e8a5" PYVERILATOR_COMMIT="766e457465f5c0dd315490d7b9cc5d74f9a76f4f" diff --git a/src/finn/transformation/qonnx/infer_quant_avg_pool_2d.py b/src/finn/transformation/qonnx/infer_quant_avg_pool_2d.py index 72d473419a..52eb55355a 100644 --- a/src/finn/transformation/qonnx/infer_quant_avg_pool_2d.py +++ b/src/finn/transformation/qonnx/infer_quant_avg_pool_2d.py @@ -165,7 +165,8 @@ def apply(self, model): # Trunc node rounding_mode = get_by_name(t_node.attribute, "rounding_mode") - if rounding_mode is None or rounding_mode.s != b"FLOOR": + normalized_mode_string = rounding_mode.s.upper() + if rounding_mode is None or normalized_mode_string != b"FLOOR": raise ValueError( "The Trunc node must have the rounding_mode " "set to 'FLOOR'." ) diff --git a/tests/end2end/test_end2end_cybsec_mlp.py b/tests/end2end/test_end2end_cybsec_mlp.py index 6e758d2d2d..7b73700909 100644 --- a/tests/end2end/test_end2end_cybsec_mlp.py +++ b/tests/end2end/test_end2end_cybsec_mlp.py @@ -37,9 +37,8 @@ import torch import torch.nn as nn from brevitas.core.quant import QuantType -from brevitas.export import export_finn_onnx, export_qonnx +from brevitas.export import export_qonnx from brevitas.nn import QuantIdentity, QuantLinear, QuantReLU -from brevitas.quant_tensor import QuantTensor from qonnx.core.datatype import DataType from qonnx.core.modelwrapper import ModelWrapper from qonnx.util.cleanup import cleanup as qonnx_cleanup @@ -55,13 +54,13 @@ build_dir = os.environ["FINN_BUILD_DIR"] -def get_checkpoint_name(step, QONNX_export): +def get_checkpoint_name(step): if step == "build": # checkpoint for build step is an entire dir - return build_dir + "/end2end_cybsecmlp_build_QONNX-%d" % (QONNX_export) + return build_dir + "/end2end_cybsecmlp_build" else: # other checkpoints are onnx files - return build_dir + "/end2end_cybsecmlp_QONNX-%d_%s.onnx" % (QONNX_export, step) + return build_dir + "/end2end_cybsecmlp_%s.onnx" % step class CybSecMLPForExport(nn.Module): @@ -82,9 +81,8 @@ def forward(self, x): return out_final -@pytest.mark.parametrize("QONNX_export", [False, True]) @pytest.mark.end2end -def test_end2end_cybsec_mlp_export(QONNX_export): +def test_end2end_cybsec_mlp_export(): assets_dir = pk.resource_filename("finn.qnn-data", "cybsec-mlp/") # load up trained net in Brevitas input_size = 593 @@ -116,72 +114,45 @@ def test_end2end_cybsec_mlp_export(QONNX_export): W_new = np.pad(W_orig, [(0, 0), (0, 7)]) model[0].weight.data = torch.from_numpy(W_new) model_for_export = CybSecMLPForExport(model) - export_onnx_path = get_checkpoint_name("export", QONNX_export) + export_onnx_path = get_checkpoint_name("export") input_shape = (1, 600) - # create a QuantTensor instance to mark the input as bipolar during export - input_a = np.random.randint(0, 1, size=input_shape).astype(np.float32) - input_a = 2 * input_a - 1 - scale = 1.0 - input_t = torch.from_numpy(input_a * scale) - input_qt = QuantTensor( - input_t, scale=torch.tensor(scale), bit_width=torch.tensor(1.0), signed=True - ) - if QONNX_export: - # With the onnx export from Brevitas we need to manually set - # the FINN DataType at the input - export_qonnx(model_for_export, torch.randn(input_shape), export_path=export_onnx_path) - model = ModelWrapper(export_onnx_path) - model.set_tensor_datatype(model.graph.input[0].name, DataType["BIPOLAR"]) - model.save(export_onnx_path) - qonnx_cleanup(export_onnx_path, out_file=export_onnx_path) - model = ModelWrapper(export_onnx_path) - model = model.transform(ConvertQONNXtoFINN()) - model.save(export_onnx_path) - else: - export_finn_onnx( - model_for_export, - export_path=export_onnx_path, - input_t=input_qt, - input_names=["onnx::Mul_0"], - ) + # With the onnx export from Brevitas we need to manually set + # the FINN DataType at the input + export_qonnx(model_for_export, torch.randn(input_shape), export_path=export_onnx_path) + model = ModelWrapper(export_onnx_path) + model.set_tensor_datatype(model.graph.input[0].name, DataType["BIPOLAR"]) + model.save(export_onnx_path) + qonnx_cleanup(export_onnx_path, out_file=export_onnx_path) + model = ModelWrapper(export_onnx_path) + model = model.transform(ConvertQONNXtoFINN()) assert os.path.isfile(export_onnx_path) # fix input datatype - finn_model = ModelWrapper(export_onnx_path) - finnonnx_in_tensor_name = finn_model.graph.input[0].name - assert tuple(finn_model.get_tensor_shape(finnonnx_in_tensor_name)) == (1, 600) + finnonnx_in_tensor_name = model.graph.input[0].name + assert tuple(model.get_tensor_shape(finnonnx_in_tensor_name)) == (1, 600) # verify a few exported ops - if QONNX_export: - # The first "Mul" node doesn't exist in the QONNX export, - # because the QuantTensor scale is not exported. - # However, this node would have been unity scale anyways and - # the models are still equivalent. - assert finn_model.graph.node[0].op_type == "Add" - assert finn_model.graph.node[1].op_type == "Div" - assert finn_model.graph.node[2].op_type == "MatMul" - assert finn_model.graph.node[-1].op_type == "MultiThreshold" - else: - assert finn_model.graph.node[0].op_type == "Mul" - assert finn_model.get_initializer(finn_model.graph.node[0].input[1]) == 1.0 - assert finn_model.graph.node[1].op_type == "Add" - assert finn_model.graph.node[2].op_type == "Div" - assert finn_model.graph.node[3].op_type == "MatMul" - assert finn_model.graph.node[-1].op_type == "MultiThreshold" + # The first "Mul" node doesn't exist in the QONNX export, + # because the QuantTensor scale is not exported. + # However, this node would have been unity scale anyways and + # the models are still equivalent. + assert model.graph.node[0].op_type == "Add" + assert model.graph.node[1].op_type == "Div" + assert model.graph.node[2].op_type == "MatMul" + assert model.graph.node[-1].op_type == "MultiThreshold" # verify datatypes on some tensors - assert finn_model.get_tensor_datatype(finnonnx_in_tensor_name) == DataType["BIPOLAR"] - first_matmul_w_name = finn_model.get_nodes_by_op_type("MatMul")[0].input[1] - assert finn_model.get_tensor_datatype(first_matmul_w_name) == DataType["INT2"] + assert model.get_tensor_datatype(finnonnx_in_tensor_name) == DataType["BIPOLAR"] + first_matmul_w_name = model.get_nodes_by_op_type("MatMul")[0].input[1] + assert model.get_tensor_datatype(first_matmul_w_name) == DataType["INT2"] @pytest.mark.slow @pytest.mark.vivado @pytest.mark.end2end -@pytest.mark.parametrize("QONNX_export", [False, True]) -def test_end2end_cybsec_mlp_build(QONNX_export): - model_file = get_checkpoint_name("export", QONNX_export) +def test_end2end_cybsec_mlp_build(): + model_file = get_checkpoint_name("export") load_test_checkpoint_or_skip(model_file) build_env = get_build_env(build_kind, target_clk_ns) - output_dir = make_build_dir(f"test_end2end_cybsec_mlp_build_QONNX-{QONNX_export}") + output_dir = make_build_dir("test_end2end_cybsec_mlp_build") cfg = build.DataflowBuildConfig( output_dir=output_dir, @@ -219,4 +190,5 @@ def test_end2end_cybsec_mlp_build(QONNX_export): est_res_dict = json.load(f) assert est_res_dict["total"]["LUT"] == 7904.0 assert est_res_dict["total"]["BRAM_18K"] == 36.0 - shutil.copytree(output_dir + "/deploy", get_checkpoint_name("build", QONNX_export)) + shutil.copytree(output_dir + "/deploy", get_checkpoint_name("build")) + shutil.rmtree(get_checkpoint_name("build")) diff --git a/tests/fpgadataflow/test_convert_to_hls_layers_cnv.py b/tests/fpgadataflow/test_convert_to_hls_layers_cnv.py index 296b4cf350..c4f3807aa0 100644 --- a/tests/fpgadataflow/test_convert_to_hls_layers_cnv.py +++ b/tests/fpgadataflow/test_convert_to_hls_layers_cnv.py @@ -33,7 +33,7 @@ import numpy as np import os import torch -from brevitas.export import export_finn_onnx +from brevitas.export import export_qonnx from qonnx.core.modelwrapper import ModelWrapper from qonnx.custom_op.registry import getCustomOp from qonnx.transformation.bipolar_to_xnor import ConvertBipolarMatMulToXnorPopcount @@ -46,6 +46,7 @@ from qonnx.transformation.infer_data_layouts import InferDataLayouts from qonnx.transformation.infer_shapes import InferShapes from qonnx.transformation.lower_convs_to_matmul import LowerConvsToMatMul +from qonnx.util.cleanup import cleanup as qonnx_cleanup import finn.core.onnx_exec as oxe import finn.transformation.fpgadataflow.convert_to_hls_layers as to_hls @@ -53,6 +54,7 @@ from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.qonnx.convert_qonnx_to_finn import ConvertQONNXtoFINN from finn.transformation.streamline import Streamline from finn.transformation.streamline.reorder import MakeMaxPoolNHWC from finn.util.test import get_test_model_trained @@ -66,8 +68,10 @@ @pytest.mark.parametrize("fused_activation", [True, False]) def test_convert_to_hls_layers_cnv_w1a1(fused_activation): cnv = get_test_model_trained("CNV", 1, 1) - export_finn_onnx(cnv, torch.randn(1, 3, 32, 32), export_onnx_path_cnv) + export_qonnx(cnv, torch.randn(1, 3, 32, 32), export_onnx_path_cnv) + qonnx_cleanup(export_onnx_path_cnv, out_file=export_onnx_path_cnv) model = ModelWrapper(export_onnx_path_cnv) + model = model.transform(ConvertQONNXtoFINN()) model = model.transform(InferShapes()) model = model.transform(FoldConstants()) model = model.transform(GiveUniqueNodeNames()) @@ -81,7 +85,6 @@ def test_convert_to_hls_layers_cnv_w1a1(fused_activation): model = model.transform(ConvertBipolarMatMulToXnorPopcount()) model = model.transform(Streamline()) model = model.transform(InferDataLayouts()) - # model.save("golden.onnx") # load one of the test vectors fn = pk.resource_filename("finn.qnn-data", "cifar10/cifar10-test-data-class3.npz") input_tensor = np.load(fn)["arr_0"].astype(np.float32) @@ -134,11 +137,9 @@ def test_convert_to_hls_layers_cnv_w1a1(fused_activation): assert len(swg_nodes) == 6 mp_nodes = model.get_nodes_by_op_type("StreamingMaxPool_Batch") assert len(mp_nodes) == 2 - # model.save("cnv-pre-compile.onnx") model = model.transform(PrepareCppSim()) model = model.transform(CompileCppSim()) model = model.transform(SetExecMode("cppsim")) - # model.save("cnv-post-compile.onnx") produced_ctx = oxe.execute_onnx(model, input_dict, True) produced = produced_ctx[model.graph.output[0].name] assert np.isclose(expected, produced, atol=1e-3).all() diff --git a/tests/fpgadataflow/test_convert_to_hls_layers_fc.py b/tests/fpgadataflow/test_convert_to_hls_layers_fc.py index e9caeddb44..8a7b2509a4 100644 --- a/tests/fpgadataflow/test_convert_to_hls_layers_fc.py +++ b/tests/fpgadataflow/test_convert_to_hls_layers_fc.py @@ -33,7 +33,7 @@ import onnx.numpy_helper as nph import os import torch -from brevitas.export import export_finn_onnx +from brevitas.export import export_qonnx from pkgutil import get_data from qonnx.core.modelwrapper import ModelWrapper from qonnx.custom_op.registry import getCustomOp @@ -45,6 +45,7 @@ GiveUniqueParameterTensors, ) from qonnx.transformation.infer_shapes import InferShapes +from qonnx.util.cleanup import cleanup as qonnx_cleanup import finn.core.onnx_exec as oxe import finn.transformation.fpgadataflow.convert_to_hls_layers as to_hls @@ -52,6 +53,7 @@ from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.qonnx.convert_qonnx_to_finn import ConvertQONNXtoFINN from finn.transformation.streamline import Streamline from finn.transformation.streamline.round_thresholds import RoundAndClipThresholds from finn.util.test import get_test_model_trained @@ -63,8 +65,10 @@ @pytest.mark.vivado def test_convert_to_hls_layers_tfc_w1a1(): tfc = get_test_model_trained("TFC", 1, 1) - export_finn_onnx(tfc, torch.randn(1, 1, 28, 28), export_onnx_path) + export_qonnx(tfc, torch.randn(1, 1, 28, 28), export_onnx_path) + qonnx_cleanup(export_onnx_path, out_file=export_onnx_path) model = ModelWrapper(export_onnx_path) + model = model.transform(ConvertQONNXtoFINN()) model = model.transform(InferShapes()) model = model.transform(FoldConstants()) model = model.transform(GiveUniqueNodeNames()) @@ -135,8 +139,11 @@ def test_convert_to_hls_layers_tfc_w1a1(): @pytest.mark.vivado def test_convert_to_hls_layers_tfc_w1a2(): tfc = get_test_model_trained("TFC", 1, 2) - export_finn_onnx(tfc, torch.randn(1, 1, 28, 28), export_onnx_path) + export_qonnx(tfc, torch.randn(1, 1, 28, 28), export_onnx_path) + qonnx_cleanup(export_onnx_path, out_file=export_onnx_path) model = ModelWrapper(export_onnx_path) + model = model.transform(ConvertQONNXtoFINN()) + model.save(export_onnx_path) model = model.transform(InferShapes()) model = model.transform(FoldConstants()) model = model.transform(GiveUniqueNodeNames()) diff --git a/tests/transformation/test_qonnx_to_finn.py b/tests/transformation/test_qonnx_to_finn.py index 10fcb79cc7..0c68bd44b4 100644 --- a/tests/transformation/test_qonnx_to_finn.py +++ b/tests/transformation/test_qonnx_to_finn.py @@ -35,12 +35,9 @@ import onnx import onnx.numpy_helper as nph import torch -from brevitas.export import export_finn_onnx, export_qonnx +from brevitas.export import export_qonnx from pkgutil import get_data from qonnx.core.modelwrapper import ModelWrapper -from qonnx.transformation.fold_constants import FoldConstants -from qonnx.transformation.general import GiveUniqueNodeNames, RemoveStaticGraphInputs -from qonnx.transformation.infer_shapes import InferShapes from qonnx.util.cleanup import cleanup from tempfile import TemporaryDirectory @@ -106,32 +103,12 @@ def test_QONNX_to_FINN(model_name, wbits, abits): brev_model, in_shape, input_tensor = get_brev_model_and_sample_inputs(model_name, wbits, abits) temp_dir = TemporaryDirectory() qonnx_base_path = temp_dir.name + "/qonnx_{}.onnx" - finn_base_path = temp_dir.name + "/finn_{}.onnx" # Get Brevitas output torch_input_tensor = torch.from_numpy(input_tensor).float() brev_output = brev_model.forward(torch_input_tensor).detach().numpy() - # Get "clean" FINN model and its output - _ = export_finn_onnx(brev_model, torch.randn(in_shape), finn_base_path.format("raw")) - model = ModelWrapper(finn_base_path.format("raw")) - model = model.transform(GiveUniqueNodeNames()) - model = model.transform(InferShapes()) - model = model.transform(FoldConstants()) - model = model.transform(RemoveStaticGraphInputs()) - model.save(finn_base_path.format("clean")) - - model = ModelWrapper(finn_base_path.format("clean")) - input_dict = {model.graph.input[0].name: input_tensor} - output_dict = oxe.execute_onnx(model, input_dict, False) - finn_export_output = output_dict[model.graph.output[0].name] - # This test always fails on MobileNet for some reason - if model_name != "mobilenet": - assert np.isclose( - brev_output, finn_export_output, atol=ATOL - ).all(), "The output of the Brevitas model and the FINN model should match." - - # Get the equivalent QONNX model + # Get QONNX model _ = export_qonnx(brev_model, torch.randn(in_shape), qonnx_base_path.format("raw")) cleanup(qonnx_base_path.format("raw"), out_file=qonnx_base_path.format("clean")) @@ -146,7 +123,7 @@ def test_QONNX_to_FINN(model_name, wbits, abits): # This test always fails on MobileNet for some reason if model_name != "mobilenet": assert np.isclose( - qonnx_export_output, finn_export_output, atol=ATOL + brev_output, qonnx_export_output, atol=ATOL ).all(), "The output of the FINN model and the QONNX model should match." # Run QONNX to FINN conversion @@ -159,7 +136,7 @@ def test_QONNX_to_FINN(model_name, wbits, abits): input_dict = {model.graph.input[0].name: input_tensor} output_dict = oxe.execute_onnx(model, input_dict, False) test_output = output_dict[model.graph.output[0].name] - assert np.isclose(test_output, finn_export_output, atol=ATOL).all(), ( + assert np.isclose(test_output, qonnx_export_output, atol=ATOL).all(), ( "The output of the FINN model " "and the QONNX -> FINN converted model should match." ) From 90468e7f69fcb9ade5ee4b2fcce9cd52ab4a696f Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 5 Jul 2023 14:47:42 +0100 Subject: [PATCH 193/665] [Tests] Fix mobilenet qonnx to finn onnx conversion test --- tests/transformation/test_qonnx_to_finn.py | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/tests/transformation/test_qonnx_to_finn.py b/tests/transformation/test_qonnx_to_finn.py index 0c68bd44b4..345aba6016 100644 --- a/tests/transformation/test_qonnx_to_finn.py +++ b/tests/transformation/test_qonnx_to_finn.py @@ -88,9 +88,6 @@ def analysis_testing_for_no_quant_nodes(model): @pytest.mark.parametrize("wbits", [1, 2]) @pytest.mark.parametrize("model_name", ["TFC", "SFC", "LFC", "CNV", "mobilenet"]) def test_QONNX_to_FINN(model_name, wbits, abits): - if model_name == "mobilenet": - pytest.xfail("MobileNet test is temporarily excluded from QONNX testing.") - if wbits > abits: pytest.skip("No wbits > abits cases at the moment") if model_name == "LFC" and wbits == 2 and abits == 2: @@ -99,7 +96,7 @@ def test_QONNX_to_FINN(model_name, wbits, abits): pytest.skip("Mobilenet only runs at W2A2, though it's technically W4A4.") # Get test config and model - ATOL = 1e-7 + ATOL = 1e-6 brev_model, in_shape, input_tensor = get_brev_model_and_sample_inputs(model_name, wbits, abits) temp_dir = TemporaryDirectory() qonnx_base_path = temp_dir.name + "/qonnx_{}.onnx" @@ -120,11 +117,6 @@ def test_QONNX_to_FINN(model_name, wbits, abits): assert np.isclose( brev_output, qonnx_export_output, atol=ATOL ).all(), "The output of the Brevitas model and the QONNX model should match." - # This test always fails on MobileNet for some reason - if model_name != "mobilenet": - assert np.isclose( - brev_output, qonnx_export_output, atol=ATOL - ).all(), "The output of the FINN model and the QONNX model should match." # Run QONNX to FINN conversion model = ModelWrapper(qonnx_base_path.format("clean")) From 0cd757fbdabea18779f5374842b45a4fd755db10 Mon Sep 17 00:00:00 2001 From: auphelia Date: Thu, 6 Jul 2023 15:50:01 +0100 Subject: [PATCH 194/665] [Tests] Mark mobilenet export as xfail --- tests/transformation/test_qonnx_to_finn.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/transformation/test_qonnx_to_finn.py b/tests/transformation/test_qonnx_to_finn.py index 345aba6016..5bbcb1f9d4 100644 --- a/tests/transformation/test_qonnx_to_finn.py +++ b/tests/transformation/test_qonnx_to_finn.py @@ -88,6 +88,8 @@ def analysis_testing_for_no_quant_nodes(model): @pytest.mark.parametrize("wbits", [1, 2]) @pytest.mark.parametrize("model_name", ["TFC", "SFC", "LFC", "CNV", "mobilenet"]) def test_QONNX_to_FINN(model_name, wbits, abits): + if model_name == "mobilenet": + pytest.xfail("MobileNet test is temporarily excluded from QONNX testing.") if wbits > abits: pytest.skip("No wbits > abits cases at the moment") if model_name == "LFC" and wbits == 2 and abits == 2: From a48b5037871468e8a3e890b4719258c7dd1736e2 Mon Sep 17 00:00:00 2001 From: auphelia Date: Thu, 6 Jul 2023 16:50:29 +0100 Subject: [PATCH 195/665] [Tests] Update tests to only use qonnx export --- tests/brevitas/test_brevitas_mobilenet.py | 14 ++++++++++---- .../brevitas/test_brevitas_validate_mobilenet.py | 15 +++++++++------ tests/end2end/test_end2end_mobilenet_v1.py | 12 +++++++++--- .../streamline/test_sign_to_thres.py | 8 ++++++-- .../streamline/test_streamline_cnv.py | 8 ++++++-- .../streamline/test_streamline_fc.py | 8 ++++++-- .../test_batchnorm_to_affine_bnn_pynq.py | 12 +++++++++--- .../transformation/test_infer_data_layouts_cnv.py | 8 ++++++-- tests/transformation/test_infer_datatypes_lfc.py | 8 ++++++-- 9 files changed, 67 insertions(+), 26 deletions(-) diff --git a/tests/brevitas/test_brevitas_mobilenet.py b/tests/brevitas/test_brevitas_mobilenet.py index fa391efcab..f98e85bb85 100644 --- a/tests/brevitas/test_brevitas_mobilenet.py +++ b/tests/brevitas/test_brevitas_mobilenet.py @@ -30,7 +30,7 @@ import numpy as np import torch -from brevitas.export import export_finn_onnx +from brevitas.export import export_qonnx from PIL import Image from qonnx.core.datatype import DataType from qonnx.core.modelwrapper import ModelWrapper @@ -45,16 +45,17 @@ from qonnx.transformation.infer_shapes import InferShapes from qonnx.transformation.insert_topk import InsertTopK from qonnx.transformation.merge_onnx_models import MergeONNXModels +from qonnx.util.cleanup import cleanup as qonnx_cleanup import finn.core.onnx_exec as oxe import finn.transformation.streamline.absorb as absorb +from finn.transformation.qonnx.convert_qonnx_to_finn import ConvertQONNXtoFINN from finn.util.basic import get_finn_root, make_build_dir from finn.util.pytorch import NormalizePreProc from finn.util.test import crop_center, get_test_model_trained, resize_smaller_side @pytest.mark.brevitas_export -@pytest.mark.xfail def test_brevitas_mobilenet(): # get single image as input and prepare image img = Image.open(get_finn_root() + "/tests/brevitas/king_charles.jpg") @@ -76,8 +77,10 @@ def test_brevitas_mobilenet(): std = 0.226 ch = 3 preproc = NormalizePreProc(mean, std, ch) - export_finn_onnx(preproc, torch.randn(1, 3, 224, 224), preproc_onnx) + export_qonnx(preproc, torch.randn(1, 3, 224, 224), preproc_onnx) + qonnx_cleanup(preproc_onnx, out_file=preproc_onnx) preproc_model = ModelWrapper(preproc_onnx) + preproc_model = preproc_model.transform(ConvertQONNXtoFINN()) # set input finn datatype to UINT8 preproc_model.set_tensor_datatype(preproc_model.graph.input[0].name, DataType["UINT8"]) preproc_model = preproc_model.transform(InferShapes()) @@ -87,7 +90,8 @@ def test_brevitas_mobilenet(): finn_onnx = export_onnx_path + "/quant_mobilenet_v1_4b_exported.onnx" mobilenet = get_test_model_trained("mobilenet", 4, 4) - export_finn_onnx(mobilenet, torch.randn(1, 3, 224, 224), finn_onnx) + export_qonnx(mobilenet, torch.randn(1, 3, 224, 224), finn_onnx) + qonnx_cleanup(finn_onnx, out_file=finn_onnx) # do forward pass in PyTorch/Brevitas input_tensor = preproc.forward(img_torch) @@ -98,7 +102,9 @@ def test_brevitas_mobilenet(): expected_top5_prob = [] for index in expected_top5: expected_top5_prob.append(expected_topk[index]) + model = ModelWrapper(finn_onnx) + model = model.transform(ConvertQONNXtoFINN()) model = model.transform(InferShapes()) model = model.transform(FoldConstants()) model = model.transform(InsertTopK()) diff --git a/tests/brevitas/test_brevitas_validate_mobilenet.py b/tests/brevitas/test_brevitas_validate_mobilenet.py index f3f7df0e3d..18f8fa9a41 100644 --- a/tests/brevitas/test_brevitas_validate_mobilenet.py +++ b/tests/brevitas/test_brevitas_validate_mobilenet.py @@ -35,7 +35,7 @@ import torch import torchvision.datasets as datasets import torchvision.transforms as transforms -from brevitas.export import export_finn_onnx +from brevitas.export import export_qonnx from qonnx.core.modelwrapper import ModelWrapper from qonnx.transformation.fold_constants import FoldConstants from qonnx.transformation.general import ( @@ -49,10 +49,12 @@ from qonnx.transformation.infer_shapes import InferShapes from qonnx.transformation.insert_topk import InsertTopK from qonnx.transformation.merge_onnx_models import MergeONNXModels +from qonnx.util.cleanup import cleanup as qonnx_cleanup import finn.core.onnx_exec as oxe import finn.transformation.streamline.absorb as absorb import finn.util.imagenet as imagenet_util +from finn.transformation.qonnx.convert_qonnx_to_finn import ConvertQONNXtoFINN from finn.util.basic import make_build_dir from finn.util.pytorch import NormalizePreProc from finn.util.test import get_test_model_trained @@ -102,9 +104,6 @@ def test_brevitas_mobilenet_preproc(): @pytest.mark.brevitas_export @pytest.mark.slow -# marked as XFAIL until Brevitas export issues are resolved: -# https://github.com/Xilinx/brevitas/issues/173 -@pytest.mark.xfail def test_brevitas_compare_exported_mobilenet(): if "IMAGENET_VAL_PATH" not in os.environ.keys(): pytest.skip("Can't do validation without IMAGENET_VAL_PATH") @@ -114,8 +113,10 @@ def test_brevitas_compare_exported_mobilenet(): # export preprocessing preproc_onnx = export_onnx_path + "/quant_mobilenet_v1_4b_preproc.onnx" preproc = NormalizePreProc(mean, std, ch) - export_finn_onnx(preproc, torch.randn(1, 3, 224, 224), preproc_onnx) + export_qonnx(preproc, torch.randn(1, 3, 224, 224), preproc_onnx) + qonnx_cleanup(preproc_onnx, out_file=preproc_onnx) preproc_model = ModelWrapper(preproc_onnx) + preproc_model = preproc_model.transform(ConvertQONNXtoFINN()) preproc_model = preproc_model.transform(InferShapes()) preproc_model = preproc_model.transform(GiveUniqueNodeNames()) preproc_model = preproc_model.transform(GiveUniqueParameterTensors()) @@ -125,8 +126,10 @@ def test_brevitas_compare_exported_mobilenet(): mobilenet = get_test_model_trained("mobilenet", 4, 4) if debug_mode: dbg_hook = bo.enable_debug(mobilenet) - export_finn_onnx(mobilenet, torch.randn(1, 3, 224, 224), finn_onnx) + export_qonnx(mobilenet, torch.randn(1, 3, 224, 224), finn_onnx) + qonnx_cleanup(finn_onnx, out_file=finn_onnx) model = ModelWrapper(finn_onnx) + model = model.transform(ConvertQONNXtoFINN()) model = model.transform(InferShapes()) model = model.transform(FoldConstants()) model = model.transform(RemoveStaticGraphInputs()) diff --git a/tests/end2end/test_end2end_mobilenet_v1.py b/tests/end2end/test_end2end_mobilenet_v1.py index e53022e74b..2d25a2bf0d 100644 --- a/tests/end2end/test_end2end_mobilenet_v1.py +++ b/tests/end2end/test_end2end_mobilenet_v1.py @@ -31,7 +31,7 @@ import os import time import torch -from brevitas.export import export_finn_onnx +from brevitas.export import export_qonnx from PIL import Image from qonnx.core.datatype import DataType from qonnx.core.modelwrapper import ModelWrapper @@ -52,6 +52,7 @@ from qonnx.transformation.lower_convs_to_matmul import LowerConvsToMatMul from qonnx.transformation.merge_onnx_models import MergeONNXModels from qonnx.transformation.remove import RemoveIdentityOps +from qonnx.util.cleanup import cleanup as qonnx_cleanup import finn.transformation.fpgadataflow.convert_to_hls_layers as to_hls import finn.transformation.streamline.absorb as absorb @@ -63,6 +64,7 @@ ) from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.qonnx.convert_qonnx_to_finn import ConvertQONNXtoFINN from finn.transformation.streamline import Streamline from finn.transformation.streamline.collapse_repeated import CollapseRepeatedMul from finn.transformation.streamline.round_thresholds import RoundAndClipThresholds @@ -95,8 +97,10 @@ def test_end2end_mobilenet_export(): std = 0.226 ch = 3 preproc = NormalizePreProc(mean, std, ch) - export_finn_onnx(preproc, torch.randn(1, 3, 224, 224), preproc_onnx) + export_qonnx(preproc, torch.randn(1, 3, 224, 224), preproc_onnx) + qonnx_cleanup(preproc_onnx, out_file=preproc_onnx) preproc_model = ModelWrapper(preproc_onnx) + preproc_model = preproc_model.transform(ConvertQONNXtoFINN()) # set input finn datatype to UINT8 preproc_model.set_tensor_datatype(preproc_model.graph.input[0].name, DataType["UINT8"]) preproc_model = preproc_model.transform(InferShapes()) @@ -109,7 +113,8 @@ def test_end2end_mobilenet_export(): # export mobilenet finn_onnx = build_dir + "/end2end_mobilenet_export.onnx" mobilenet = get_test_model_trained("mobilenet", 4, 4) - export_finn_onnx(mobilenet, torch.randn(1, 3, 224, 224), finn_onnx) + export_qonnx(mobilenet, torch.randn(1, 3, 224, 224), finn_onnx) + qonnx_cleanup(finn_onnx, out_file=finn_onnx) # calculate golden output with pytorch/brevitas and save as .npy # get single image as input and prepare image @@ -145,6 +150,7 @@ def test_end2end_mobilenet_export(): def test_end2end_mobilenet_tidy_and_merge_with_preproc(): preproc_model = load_test_checkpoint_or_skip(build_dir + "/end2end_mobilenet_preproc.onnx") model = load_test_checkpoint_or_skip(build_dir + "/end2end_mobilenet_export.onnx") + model = model.transform(ConvertQONNXtoFINN()) model = model.transform(InferShapes()) model = model.transform(FoldConstants()) model = model.transform(InsertTopK()) diff --git a/tests/transformation/streamline/test_sign_to_thres.py b/tests/transformation/streamline/test_sign_to_thres.py index 72e400346d..1386592563 100644 --- a/tests/transformation/streamline/test_sign_to_thres.py +++ b/tests/transformation/streamline/test_sign_to_thres.py @@ -32,13 +32,15 @@ import onnx.numpy_helper as nph import os import torch -from brevitas.export import export_finn_onnx +from brevitas.export import export_qonnx from pkgutil import get_data from qonnx.core.modelwrapper import ModelWrapper from qonnx.transformation.fold_constants import FoldConstants from qonnx.transformation.infer_shapes import InferShapes +from qonnx.util.cleanup import cleanup as qonnx_cleanup import finn.core.onnx_exec as oxe +from finn.transformation.qonnx.convert_qonnx_to_finn import ConvertQONNXtoFINN from finn.transformation.streamline import ConvertSignToThres from finn.util.test import get_test_model_trained @@ -48,8 +50,10 @@ @pytest.mark.streamline def test_sign_to_thres(): lfc = get_test_model_trained("LFC", 1, 1) - export_finn_onnx(lfc, torch.randn(1, 1, 28, 28), export_onnx_path) + export_qonnx(lfc, torch.randn(1, 1, 28, 28), export_onnx_path) + qonnx_cleanup(export_onnx_path, out_file=export_onnx_path) model = ModelWrapper(export_onnx_path) + model = model.transform(ConvertQONNXtoFINN()) model = model.transform(InferShapes()) model = model.transform(FoldConstants()) new_model = model.transform(ConvertSignToThres()) diff --git a/tests/transformation/streamline/test_streamline_cnv.py b/tests/transformation/streamline/test_streamline_cnv.py index c5d8e2517f..86e4356ae4 100644 --- a/tests/transformation/streamline/test_streamline_cnv.py +++ b/tests/transformation/streamline/test_streamline_cnv.py @@ -32,7 +32,7 @@ import numpy as np import torch -from brevitas.export import export_finn_onnx +from brevitas.export import export_qonnx from qonnx.core.modelwrapper import ModelWrapper from qonnx.transformation.fold_constants import FoldConstants from qonnx.transformation.general import ( @@ -43,8 +43,10 @@ RemoveUnusedTensors, ) from qonnx.transformation.infer_shapes import InferShapes +from qonnx.util.cleanup import cleanup as qonnx_cleanup import finn.core.onnx_exec as oxe +from finn.transformation.qonnx.convert_qonnx_to_finn import ConvertQONNXtoFINN from finn.transformation.streamline import Streamline from finn.util.basic import make_build_dir from finn.util.test import get_test_model_trained @@ -65,8 +67,10 @@ def test_streamline_cnv(size, wbits, abits): nname = "%s_%dW%dA" % (size, wbits, abits) finn_onnx = export_onnx_path + "/%s.onnx" % nname fc = get_test_model_trained(size, wbits, abits) - export_finn_onnx(fc, torch.randn(1, 3, 32, 32), finn_onnx) + export_qonnx(fc, torch.randn(1, 3, 32, 32), finn_onnx) + qonnx_cleanup(finn_onnx, out_file=finn_onnx) model = ModelWrapper(finn_onnx) + model = model.transform(ConvertQONNXtoFINN()) model = model.transform(InferShapes()) model = model.transform(FoldConstants()) model = model.transform(GiveUniqueNodeNames()) diff --git a/tests/transformation/streamline/test_streamline_fc.py b/tests/transformation/streamline/test_streamline_fc.py index 07c3a0f3cb..edc4a96fe2 100644 --- a/tests/transformation/streamline/test_streamline_fc.py +++ b/tests/transformation/streamline/test_streamline_fc.py @@ -32,7 +32,7 @@ import onnx import onnx.numpy_helper as nph import torch -from brevitas.export import export_finn_onnx +from brevitas.export import export_qonnx from pkgutil import get_data from qonnx.core.modelwrapper import ModelWrapper from qonnx.transformation.fold_constants import FoldConstants @@ -44,8 +44,10 @@ RemoveUnusedTensors, ) from qonnx.transformation.infer_shapes import InferShapes +from qonnx.util.cleanup import cleanup as qonnx_cleanup import finn.core.onnx_exec as oxe +from finn.transformation.qonnx.convert_qonnx_to_finn import ConvertQONNXtoFINN from finn.transformation.streamline import Streamline from finn.util.basic import make_build_dir from finn.util.test import get_test_model_trained @@ -68,8 +70,10 @@ def test_streamline_fc(size, wbits, abits): nname = "%s_%dW%dA" % (size, wbits, abits) finn_onnx = export_onnx_path + "/%s.onnx" % nname fc = get_test_model_trained(size, wbits, abits) - export_finn_onnx(fc, torch.randn(1, 1, 28, 28), finn_onnx) + export_qonnx(fc, torch.randn(1, 1, 28, 28), finn_onnx) + qonnx_cleanup(finn_onnx, out_file=finn_onnx) model = ModelWrapper(finn_onnx) + model = model.transform(ConvertQONNXtoFINN()) model = model.transform(InferShapes()) model = model.transform(FoldConstants()) model = model.transform(GiveUniqueNodeNames()) diff --git a/tests/transformation/test_batchnorm_to_affine_bnn_pynq.py b/tests/transformation/test_batchnorm_to_affine_bnn_pynq.py index 60e81ffe81..b95c26d25f 100644 --- a/tests/transformation/test_batchnorm_to_affine_bnn_pynq.py +++ b/tests/transformation/test_batchnorm_to_affine_bnn_pynq.py @@ -35,14 +35,16 @@ import onnx.numpy_helper as nph import os import torch -from brevitas.export import export_finn_onnx +from brevitas.export import export_qonnx from pkgutil import get_data from qonnx.core.modelwrapper import ModelWrapper from qonnx.transformation.batchnorm_to_affine import BatchNormToAffine from qonnx.transformation.fold_constants import FoldConstants from qonnx.transformation.infer_shapes import InferShapes +from qonnx.util.cleanup import cleanup as qonnx_cleanup import finn.core.onnx_exec as oxe +from finn.transformation.qonnx.convert_qonnx_to_finn import ConvertQONNXtoFINN from finn.util.test import get_test_model_trained export_onnx_path = "test_output_bn2affine.onnx" @@ -51,8 +53,10 @@ @pytest.mark.transform def test_batchnorm_to_affine_cnv_w1a1(): lfc = get_test_model_trained("CNV", 1, 1) - export_finn_onnx(lfc, torch.randn(1, 3, 32, 32), export_onnx_path) + export_qonnx(lfc, torch.randn(1, 3, 32, 32), export_onnx_path) + qonnx_cleanup(export_onnx_path, out_file=export_onnx_path) model = ModelWrapper(export_onnx_path) + model = model.transform(ConvertQONNXtoFINN()) model = model.transform(InferShapes()) model = model.transform(FoldConstants()) fn = pk.resource_filename("finn.qnn-data", "cifar10/cifar10-test-data-class3.npz") @@ -76,8 +80,10 @@ def test_batchnorm_to_affine_cnv_w1a1(): @pytest.mark.transform def test_batchnorm_to_affine_lfc_w1a1(): lfc = get_test_model_trained("LFC", 1, 1) - export_finn_onnx(lfc, torch.randn(1, 1, 28, 28), export_onnx_path) + export_qonnx(lfc, torch.randn(1, 1, 28, 28), export_onnx_path) + qonnx_cleanup(export_onnx_path, out_file=export_onnx_path) model = ModelWrapper(export_onnx_path) + model = model.transform(ConvertQONNXtoFINN()) model = model.transform(InferShapes()) model = model.transform(FoldConstants()) new_model = model.transform(BatchNormToAffine()) diff --git a/tests/transformation/test_infer_data_layouts_cnv.py b/tests/transformation/test_infer_data_layouts_cnv.py index a5a9d34aaf..25bf890271 100644 --- a/tests/transformation/test_infer_data_layouts_cnv.py +++ b/tests/transformation/test_infer_data_layouts_cnv.py @@ -31,7 +31,7 @@ import os import qonnx.core.data_layout as DataLayout import torch -from brevitas.export import export_finn_onnx +from brevitas.export import export_qonnx from qonnx.core.modelwrapper import ModelWrapper from qonnx.transformation.bipolar_to_xnor import ConvertBipolarMatMulToXnorPopcount from qonnx.transformation.fold_constants import FoldConstants @@ -43,9 +43,11 @@ from qonnx.transformation.infer_data_layouts import InferDataLayouts from qonnx.transformation.infer_shapes import InferShapes from qonnx.transformation.lower_convs_to_matmul import LowerConvsToMatMul +from qonnx.util.cleanup import cleanup as qonnx_cleanup import finn.transformation.fpgadataflow.convert_to_hls_layers as to_hls import finn.transformation.streamline.absorb as absorb +from finn.transformation.qonnx.convert_qonnx_to_finn import ConvertQONNXtoFINN from finn.transformation.streamline import Streamline from finn.transformation.streamline.reorder import MakeMaxPoolNHWC from finn.util.test import get_test_model_trained @@ -56,8 +58,10 @@ @pytest.mark.transform def test_infer_data_layouts_cnv(): cnv = get_test_model_trained("CNV", 1, 1) - export_finn_onnx(cnv, torch.randn(1, 3, 32, 32), export_onnx_path_cnv) + export_qonnx(cnv, torch.randn(1, 3, 32, 32), export_onnx_path_cnv) + qonnx_cleanup(export_onnx_path_cnv, out_file=export_onnx_path_cnv) model = ModelWrapper(export_onnx_path_cnv) + model = model.transform(ConvertQONNXtoFINN()) model = model.transform(InferShapes()) model = model.transform(FoldConstants()) model = model.transform(GiveUniqueNodeNames()) diff --git a/tests/transformation/test_infer_datatypes_lfc.py b/tests/transformation/test_infer_datatypes_lfc.py index 173532cb76..b9d9dc558f 100644 --- a/tests/transformation/test_infer_datatypes_lfc.py +++ b/tests/transformation/test_infer_datatypes_lfc.py @@ -30,14 +30,16 @@ import os import torch -from brevitas.export import export_finn_onnx +from brevitas.export import export_qonnx from qonnx.core.datatype import DataType from qonnx.core.modelwrapper import ModelWrapper from qonnx.transformation.fold_constants import FoldConstants from qonnx.transformation.general import GiveReadableTensorNames, GiveUniqueNodeNames from qonnx.transformation.infer_datatypes import InferDataTypes from qonnx.transformation.infer_shapes import InferShapes +from qonnx.util.cleanup import cleanup as qonnx_cleanup +from finn.transformation.qonnx.convert_qonnx_to_finn import ConvertQONNXtoFINN from finn.util.test import get_test_model_trained export_onnx_path = "test_infer_datatypes.onnx" @@ -46,8 +48,10 @@ @pytest.mark.transform def test_infer_datatypes_lfc(): lfc = get_test_model_trained("LFC", 1, 1) - export_finn_onnx(lfc, torch.randn(1, 1, 28, 28), export_onnx_path) + export_qonnx(lfc, torch.randn(1, 1, 28, 28), export_onnx_path) + qonnx_cleanup(export_onnx_path, out_file=export_onnx_path) model = ModelWrapper(export_onnx_path) + model = model.transform(ConvertQONNXtoFINN()) model = model.transform(InferShapes()) model = model.transform(FoldConstants()) model = model.transform(GiveUniqueNodeNames()) From 391cd76ee3edb6e802d9b565a99993c775cc2194 Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 7 Jul 2023 12:07:42 +0100 Subject: [PATCH 196/665] [deps] Bump clize to 5.0.1 and sigtools to 4.0.1 --- requirements.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/requirements.txt b/requirements.txt index e3f74c23f9..1427d4f1ee 100644 --- a/requirements.txt +++ b/requirements.txt @@ -1,5 +1,5 @@ bitstring==3.1.7 -clize==4.1.1 +clize==5.0.1 dataclasses-json==0.5.7 gspread==3.6.0 ipython==8.12.2 @@ -13,7 +13,7 @@ psutil==5.9.4 pyscaffold==4.4 scipy==1.10.1 setupext-janitor>=1.1.2 -sigtools==2.0.3 +sigtools==4.0.1 toposort==1.7.0 vcdvcd==1.0.5 wget==3.2 From 7924bf7271b41dd808feac0e8c5017222490f553 Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 7 Jul 2023 14:31:14 +0100 Subject: [PATCH 197/665] [NBs] Update notebooks to only use QONNX export --- ...1_brevitas_network_import_via_QONNX.ipynb} | 4 +- ...revitas_network_import_via_FINN-ONNX.ipynb | 321 ------------------ .../bnn-pynq/cnv_end2end_example.ipynb | 21 +- .../bnn-pynq/tfc_end2end_example.ipynb | 23 +- .../1-train-mlp-with-brevitas.ipynb | 29 +- .../2-import-into-finn-and-verify.ipynb | 2 +- tests/brevitas/test_brevitas_mobilenet.py | 1 + tests/notebooks/test_jupyter_notebooks.py | 3 +- 8 files changed, 52 insertions(+), 352 deletions(-) rename notebooks/basics/{1b_brevitas_network_import_via_QONNX.ipynb => 1_brevitas_network_import_via_QONNX.ipynb} (97%) delete mode 100644 notebooks/basics/1a_brevitas_network_import_via_FINN-ONNX.ipynb diff --git a/notebooks/basics/1b_brevitas_network_import_via_QONNX.ipynb b/notebooks/basics/1_brevitas_network_import_via_QONNX.ipynb similarity index 97% rename from notebooks/basics/1b_brevitas_network_import_via_QONNX.ipynb rename to notebooks/basics/1_brevitas_network_import_via_QONNX.ipynb index 58fa3fc7e1..f15f716e7f 100644 --- a/notebooks/basics/1b_brevitas_network_import_via_QONNX.ipynb +++ b/notebooks/basics/1_brevitas_network_import_via_QONNX.ipynb @@ -6,7 +6,7 @@ "source": [ "# Importing Brevitas networks into FINN with the QONNX interchange format\n", "\n", - "**Note: This notebook is very similar to the 1a notebook, in that it shows the same concepts for the QONNX ingestion as 1a does for FINN-ONNX. Section 1 is identical in both notebooks.**\n", + "**Note: Previously it was possible to directly export the FINN-ONNX interchange format from Brevitas to pass to the FINN compiler. This support is deprecated and FINN uses the export to the QONNX format as a front end, internally FINN uses still the FINN-ONNX format.**\n", "\n", "In this notebook we'll go through an example of how to import a Brevitas-trained QNN into FINN. The steps will be as follows:\n", "\n", @@ -318,7 +318,7 @@ "name": "python", "nbconvert_exporter": "python", "pygments_lexer": "ipython3", - "version": "3.8.5" + "version": "3.10.6" } }, "nbformat": 4, diff --git a/notebooks/basics/1a_brevitas_network_import_via_FINN-ONNX.ipynb b/notebooks/basics/1a_brevitas_network_import_via_FINN-ONNX.ipynb deleted file mode 100644 index 756faf149d..0000000000 --- a/notebooks/basics/1a_brevitas_network_import_via_FINN-ONNX.ipynb +++ /dev/null @@ -1,321 +0,0 @@ -{ - "cells": [ - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "# Importing Brevitas networks into FINN with the FINN-ONNX interchange format\n", - "\n", - "**Note: This notebook is very similar to the 1b notebook, in that it shows the same concepts for the FINN-ONNX ingestion as 1b does for QONNX. Section 1 is identical in both notebooks.**\n", - "\n", - "In this notebook we'll go through an example of how to import a Brevitas-trained QNN into FINN. The steps will be as follows:\n", - "\n", - "1. Load up the trained PyTorch model\n", - "2. Call Brevitas FINN-ONNX export and visualize with Netron\n", - "3. Import into FINN and call cleanup transformations\n", - "\n", - "We'll use the following utility functions to print the source code for function calls (`showSrc()`) and to visualize a network using netron (`showInNetron()`) in the Jupyter notebook:" - ] - }, - { - "cell_type": "code", - "execution_count": null, - "metadata": {}, - "outputs": [], - "source": [ - "import onnx\n", - "from finn.util.visualization import showSrc, showInNetron" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "## 1. Load up the trained PyTorch model\n", - "\n", - "The FINN Docker image comes with several [example Brevitas networks](https://github.com/Xilinx/brevitas/tree/master/src/brevitas_examples/bnn_pynq), and we'll use the LFC-w1a1 model as the example network here. This is a binarized fully connected network trained on the MNIST dataset. Let's start by looking at what the PyTorch network definition looks like:" - ] - }, - { - "cell_type": "code", - "execution_count": null, - "metadata": {}, - "outputs": [], - "source": [ - "from brevitas_examples import bnn_pynq\n", - "showSrc(bnn_pynq.models.FC)" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "We can see that the network topology is constructed using a few helper functions that generate the quantized linear layers and quantized activations. The bitwidth of the layers is actually parametrized in the constructor, so let's instantiate a 1-bit weights and activations version of this network. We also have pretrained weights for this network, which we will load into the model." - ] - }, - { - "cell_type": "code", - "execution_count": null, - "metadata": {}, - "outputs": [], - "source": [ - "from finn.util.test import get_test_model\n", - "lfc = get_test_model(netname = \"LFC\", wbits = 1, abits = 1, pretrained = True)\n", - "lfc" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "We have now instantiated our trained PyTorch network. Let's try to run an example MNIST image through the network using PyTorch." - ] - }, - { - "cell_type": "code", - "execution_count": null, - "metadata": {}, - "outputs": [], - "source": [ - "import torch\n", - "import matplotlib.pyplot as plt\n", - "from pkgutil import get_data\n", - "import onnx\n", - "import onnx.numpy_helper as nph\n", - "raw_i = get_data(\"qonnx.data\", \"onnx/mnist-conv/test_data_set_0/input_0.pb\")\n", - "input_tensor = onnx.load_tensor_from_string(raw_i)\n", - "input_tensor_npy = nph.to_array(input_tensor)\n", - "input_tensor_pyt = torch.from_numpy(input_tensor_npy).float()\n", - "imgplot = plt.imshow(input_tensor_npy.reshape(28,28), cmap='gray')" - ] - }, - { - "cell_type": "code", - "execution_count": null, - "metadata": {}, - "outputs": [], - "source": [ - "from torch.nn.functional import softmax\n", - "# do forward pass in PyTorch/Brevitas\n", - "produced = lfc.forward(input_tensor_pyt).detach()\n", - "probabilities = softmax(produced, dim=-1).flatten()\n", - "probabilities" - ] - }, - { - "cell_type": "code", - "execution_count": null, - "metadata": {}, - "outputs": [], - "source": [ - "import numpy as np\n", - "objects = [str(x) for x in range(10)]\n", - "y_pos = np.arange(len(objects))\n", - "plt.bar(y_pos, probabilities, align='center', alpha=0.5)\n", - "plt.xticks(y_pos, objects)\n", - "plt.ylabel('Predicted Probability')\n", - "plt.title('LFC-w1a1 Predictions for Image')\n", - "plt.show()" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "## 2. Call Brevitas FINN-ONNX export and visualize with Netron\n", - "\n", - "Brevitas comes with built-in FINN-ONNX export functionality. This is similar to the regular ONNX export capabilities of PyTorch, with a few differences:\n", - "\n", - "1. The weight quantization logic is not exported as part of the graph; rather, the quantized weights themselves are exported.\n", - "2. Special quantization annotations are used to preserve the low-bit quantization information. ONNX (at the time of writing) supports 8-bit quantization as the minimum bitwidth, whereas FINN-ONNX quantization annotations can go down to binary/bipolar quantization.\n", - "3. Low-bit quantized activation functions are exported as MultiThreshold operators.\n", - "\n", - "It's actually quite straightforward to export ONNX from our Brevitas model as follows:" - ] - }, - { - "cell_type": "code", - "execution_count": null, - "metadata": {}, - "outputs": [], - "source": [ - "from brevitas.export import export_finn_onnx\n", - "export_onnx_path = \"/tmp/LFCW1A1_finn-onnx.onnx\"\n", - "input_shape = (1, 1, 28, 28)\n", - "export_finn_onnx(lfc, torch.randn(input_shape), export_onnx_path);" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "Let's examine what the exported ONNX model looks like. For this, we will use the Netron visualizer:" - ] - }, - { - "cell_type": "code", - "execution_count": null, - "metadata": {}, - "outputs": [], - "source": [ - "showInNetron(export_onnx_path)" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "When running this notebook in the FINN Docker container, you should be able to see an interactive visualization of the imported network above, and click on individual nodes to inspect their parameters. If you look at any of the MatMul nodes, you should be able to see that the weights are all {-1, +1} values, and the activations are Sign functions." - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "## 3. Import into FINN and call cleanup transformations\n", - "\n", - "We will now import this ONNX model into FINN using the ModelWrapper, and examine some of the graph attributes from Python." - ] - }, - { - "cell_type": "code", - "execution_count": null, - "metadata": {}, - "outputs": [], - "source": [ - "from qonnx.core.modelwrapper import ModelWrapper\n", - "model = ModelWrapper(export_onnx_path)\n", - "model.graph.node[8]" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "The ModelWrapper exposes a range of other useful functions as well. For instance, by convention the second input of the MatMul node will be a pre-initialized weight tensor, which we can view using the following:" - ] - }, - { - "cell_type": "code", - "execution_count": null, - "metadata": {}, - "outputs": [], - "source": [ - "model.get_initializer(model.graph.node[8].input[1])" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "We can also examine the quantization annotations and shapes of various tensors using the convenience functions provided by ModelWrapper." - ] - }, - { - "cell_type": "code", - "execution_count": null, - "metadata": {}, - "outputs": [], - "source": [ - "model.get_tensor_datatype(model.graph.node[8].input[1]).name" - ] - }, - { - "cell_type": "code", - "execution_count": null, - "metadata": {}, - "outputs": [], - "source": [ - "model.get_tensor_shape(model.graph.node[8].input[1])" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "If we want to operate further on this model in FINN, it is a good idea to execute certain \"cleanup\" transformations on this graph. Here, we will run shape inference and constant folding on this graph, and visualize the resulting graph in Netron again." - ] - }, - { - "cell_type": "code", - "execution_count": null, - "metadata": {}, - "outputs": [], - "source": [ - "from qonnx.transformation.fold_constants import FoldConstants\n", - "from qonnx.transformation.infer_shapes import InferShapes\n", - "model = model.transform(InferShapes())\n", - "model = model.transform(FoldConstants())\n", - "export_onnx_path_transformed = \"/tmp/LFCW1A1-finn-onnx-clean.onnx\"\n", - "model.save(export_onnx_path_transformed)" - ] - }, - { - "cell_type": "code", - "execution_count": null, - "metadata": {}, - "outputs": [], - "source": [ - "showInNetron(export_onnx_path_transformed)" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "We can see that the resulting graph has become smaller and simpler. Specifically, the input reshaping is now a single Reshape node instead of the Shape -> Gather -> Unsqueeze -> Concat -> Reshape sequence. We can now use the internal ONNX execution capabilities of FINN to ensure that we still get the same output from this model as we did with PyTorch." - ] - }, - { - "cell_type": "code", - "execution_count": null, - "metadata": {}, - "outputs": [], - "source": [ - "import finn.core.onnx_exec as oxe\n", - "input_dict = {\"0\": nph.to_array(input_tensor)}\n", - "output_dict = oxe.execute_onnx(model, input_dict)\n", - "produced_finn = output_dict[list(output_dict.keys())[0]]\n", - "\n", - "produced_finn" - ] - }, - { - "cell_type": "code", - "execution_count": null, - "metadata": {}, - "outputs": [], - "source": [ - "np.isclose(produced, produced_finn).all()" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "We have succesfully verified that the transformed and cleaned-up FINN graph still produces the same output, and can now use this model for further processing in FINN." - ] - } - ], - "metadata": { - "kernelspec": { - "display_name": "Python 3 (ipykernel)", - "language": "python", - "name": "python3" - }, - "language_info": { - "codemirror_mode": { - "name": "ipython", - "version": 3 - }, - "file_extension": ".py", - "mimetype": "text/x-python", - "name": "python", - "nbconvert_exporter": "python", - "pygments_lexer": "ipython3", - "version": "3.8.5" - } - }, - "nbformat": 4, - "nbformat_minor": 2 -} diff --git a/notebooks/end2end_example/bnn-pynq/cnv_end2end_example.ipynb b/notebooks/end2end_example/bnn-pynq/cnv_end2end_example.ipynb index 73e9f4e6e1..a0dbbf4834 100644 --- a/notebooks/end2end_example/bnn-pynq/cnv_end2end_example.ipynb +++ b/notebooks/end2end_example/bnn-pynq/cnv_end2end_example.ipynb @@ -72,7 +72,7 @@ "source": [ "## 1. Brevitas Export, FINN Import and Tidy-Up\n", "\n", - "Similar to what we did in the TFC-w1a1 end-to-end notebook, we will start by exporting the [pretrained CNV-w1a1 network](https://github.com/Xilinx/brevitas/tree/master/src/brevitas_examples/bnn_pynq) to ONNX, importing that into FINN and running the \"tidy-up\" transformations to have a first look at the topology." + "Similar to what we did in the TFC-w1a1 end-to-end notebook, we will start by exporting the [pretrained CNV-w1a1 network](https://github.com/Xilinx/brevitas/tree/master/src/brevitas_examples/bnn_pynq) to ONNX, importing that into FINN and running the \"tidy-up\" transformations to have a first look at the topology. The network will be exported in QONNX format and then converted into the FINN-ONNX format to prepare it for the FINN compiler." ] }, { @@ -84,15 +84,20 @@ "import torch\n", "import onnx\n", "from finn.util.test import get_test_model_trained\n", - "from brevitas.export import export_finn_onnx\n", + "from brevitas.export import export_qonnx\n", + "from qonnx.util.cleanup import cleanup as qonnx_cleanup\n", "from qonnx.core.modelwrapper import ModelWrapper\n", + "from finn.transformation.qonnx.convert_qonnx_to_finn import ConvertQONNXtoFINN\n", "from qonnx.transformation.infer_shapes import InferShapes\n", "from qonnx.transformation.fold_constants import FoldConstants\n", "from qonnx.transformation.general import GiveReadableTensorNames, GiveUniqueNodeNames, RemoveStaticGraphInputs\n", "\n", "cnv = get_test_model_trained(\"CNV\", 1, 1)\n", - "export_finn_onnx(cnv, torch.randn(1, 3, 32, 32), build_dir + \"/end2end_cnv_w1a1_export.onnx\")\n", - "model = ModelWrapper(build_dir + \"/end2end_cnv_w1a1_export.onnx\")\n", + "export_onnx_path = build_dir + \"/end2end_cnv_w1a1_export.onnx\"\n", + "export_qonnx(cnv, torch.randn(1, 3, 32, 32), export_onnx_path)\n", + "qonnx_cleanup(export_onnx_path, out_file=export_onnx_path)\n", + "model = ModelWrapper(export_onnx_path)\n", + "model = model.transform(ConvertQONNXtoFINN())\n", "model = model.transform(InferShapes())\n", "model = model.transform(FoldConstants())\n", "model = model.transform(GiveUniqueNodeNames())\n", @@ -149,10 +154,12 @@ "# preprocessing: torchvision's ToTensor divides uint8 inputs by 255\n", "totensor_pyt = ToTensor()\n", "chkpt_preproc_name = build_dir+\"/end2end_cnv_w1a1_preproc.onnx\"\n", - "export_finn_onnx(totensor_pyt, torch.randn(ishape), chkpt_preproc_name)\n", + "export_qonnx(totensor_pyt, torch.randn(ishape), chkpt_preproc_name)\n", + "qonnx_cleanup(chkpt_preproc_name, out_file=chkpt_preproc_name)\n", + "pre_model = ModelWrapper(chkpt_preproc_name)\n", + "pre_model = pre_model.transform(ConvertQONNXtoFINN())\n", "\n", "# join preprocessing and core model\n", - "pre_model = ModelWrapper(chkpt_preproc_name)\n", "model = model.transform(MergeONNXModels(pre_model))\n", "# add input quantization annotation: UINT8 for all BNN-PYNQ models\n", "global_inp_name = model.graph.input[0].name\n", @@ -633,7 +640,7 @@ "name": "python", "nbconvert_exporter": "python", "pygments_lexer": "ipython3", - "version": "3.8.5" + "version": "3.10.6" } }, "nbformat": 4, diff --git a/notebooks/end2end_example/bnn-pynq/tfc_end2end_example.ipynb b/notebooks/end2end_example/bnn-pynq/tfc_end2end_example.ipynb index f99944e31f..a5c97328a5 100644 --- a/notebooks/end2end_example/bnn-pynq/tfc_end2end_example.ipynb +++ b/notebooks/end2end_example/bnn-pynq/tfc_end2end_example.ipynb @@ -84,17 +84,20 @@ "import torch\n", "import onnx\n", "from finn.util.test import get_test_model_trained\n", - "from brevitas.export import export_finn_onnx\n", + "from brevitas.export import export_qonnx\n", + "from qonnx.util.cleanup import cleanup as qonnx_cleanup\n", "\n", "tfc = get_test_model_trained(\"TFC\", 1, 1)\n", - "export_finn_onnx(tfc, torch.randn(1, 1, 28, 28), build_dir+\"/tfc_w1_a1.onnx\"); # semicolon added to suppress log" + "export_onnx_path = build_dir+\"/tfc_w1_a1.onnx\"\n", + "export_qonnx(tfc, torch.randn(1, 1, 28, 28), build_dir+\"/tfc_w1_a1.onnx\"); # semicolon added to suppress log\n", + "qonnx_cleanup(export_onnx_path, out_file=export_onnx_path)" ] }, { "cell_type": "markdown", "metadata": {}, "source": [ - "The model was now exported, loaded with the pretrained weights and saved under the name \"tfc_w1_a1.onnx\".\n", + "The model was now exported in QONNX format, loaded with the pretrained weights and saved under the name \"tfc_w1_a1.onnx\".\n", "To visualize the exported model, Netron can be used. Netron is a visualizer for neural networks and allows interactive investigation of network properties. For example, you can click on the individual nodes and view the properties." ] }, @@ -111,7 +114,7 @@ "cell_type": "markdown", "metadata": {}, "source": [ - "Now that we have the model in .onnx format, we can work with it using FINN. For that, `ModelWrapper` is used. It is a wrapper around the ONNX model which provides several helper functions to make it easier to work with the model. 'ModelWrapper' is imported from the [QONNX repo](https://github.com/fastmachinelearning/qonnx), this repository contains several functionality that is used in FINN." + "Now that we have the model in .onnx format, we can work with it using FINN. For that, `ModelWrapper` is used. It is a wrapper around the ONNX model which provides several helper functions to make it easier to work with the model. 'ModelWrapper' is imported from the [QONNX repo](https://github.com/fastmachinelearning/qonnx), this repository contains several functionality that is used in FINN. The model was exported in QONNX format, to feed it into the FINN flow, our first step is to convert it to the FINN-ONNX format." ] }, { @@ -121,7 +124,9 @@ "outputs": [], "source": [ "from qonnx.core.modelwrapper import ModelWrapper\n", - "model = ModelWrapper(build_dir+\"/tfc_w1_a1.onnx\")" + "from finn.transformation.qonnx.convert_qonnx_to_finn import ConvertQONNXtoFINN\n", + "model = ModelWrapper(build_dir+\"/tfc_w1_a1.onnx\")\n", + "model = model.transform(ConvertQONNXtoFINN())" ] }, { @@ -268,10 +273,12 @@ "# preprocessing: torchvision's ToTensor divides uint8 inputs by 255\n", "totensor_pyt = ToTensor()\n", "chkpt_preproc_name = build_dir+\"/tfc_w1_a1_preproc.onnx\"\n", - "export_finn_onnx(totensor_pyt, torch.randn(ishape), chkpt_preproc_name)\n", + "export_qonnx(totensor_pyt, torch.randn(ishape), chkpt_preproc_name)\n", + "qonnx_cleanup(chkpt_preproc_name, out_file=chkpt_preproc_name)\n", + "pre_model = ModelWrapper(chkpt_preproc_name)\n", + "pre_model = pre_model.transform(ConvertQONNXtoFINN())\n", "\n", "# join preprocessing and core model\n", - "pre_model = ModelWrapper(chkpt_preproc_name)\n", "model = model.transform(MergeONNXModels(pre_model))\n", "# add input quantization annotation: UINT8 for all BNN-PYNQ models\n", "global_inp_name = model.graph.input[0].name\n", @@ -1007,7 +1014,7 @@ "name": "python", "nbconvert_exporter": "python", "pygments_lexer": "ipython3", - "version": "3.8.5" + "version": "3.10.6" } }, "nbformat": 4, diff --git a/notebooks/end2end_example/cybersecurity/1-train-mlp-with-brevitas.ipynb b/notebooks/end2end_example/cybersecurity/1-train-mlp-with-brevitas.ipynb index 0f90b8ee78..2885100512 100644 --- a/notebooks/end2end_example/cybersecurity/1-train-mlp-with-brevitas.ipynb +++ b/notebooks/end2end_example/cybersecurity/1-train-mlp-with-brevitas.ipynb @@ -53,7 +53,7 @@ " * [(Option 1) Train the Model from Scratch](#train_scratch)\n", " * [(Option 2) Load Pre-Trained Parameters](#load_pretrained)\n", "* [Network Surgery Before Export](#network_surgery)\n", - "* [Export to FINN-ONNX](#export_finn_onnx)" + "* [Export to QONNX and Conversion to FINN-ONNX](#export_qonnx)" ] }, { @@ -667,12 +667,12 @@ "cell_type": "markdown", "metadata": {}, "source": [ - "# Export to FINN-ONNX \n", + "# Export to QONNX and Conversion to FINN-ONNX \n", "\n", "\n", "[ONNX](https://onnx.ai/) is an open format built to represent machine learning models, and the FINN compiler expects an ONNX model as input. We'll now export our network into ONNX to be imported and used in FINN for the next notebooks. Note that the particular ONNX representation used for FINN differs from standard ONNX, you can read more about this [here](https://finn.readthedocs.io/en/latest/internals.html#intermediate-representation-finn-onnx).\n", "\n", - "You can see below how we export a trained network in Brevitas into a FINN-compatible ONNX representation. Note how we create a `QuantTensor` instance with dummy data to tell Brevitas how our inputs look like, which will be used to set the input quantization annotation on the exported model." + "You can see below how we export a trained network in Brevitas into a FINN-compatible ONNX representation (QONNX). QONNX is the format we can export from Brevitas, to feed it into the FINN compiler, we will need to make a conversion to the FINN-ONNX format which is the intermediate representation the compiler works on. The conversion of the FINN-ONNX format is a FINN compiler transformation and to be able to apply it to our model, we will need to wrap it into [ModelWrapper](https://finn.readthedocs.io/en/latest/internals.html#modelwrapper). This is a wrapper around the ONNX model which provides several helper functions to make it easier to work with the model. Then we can call the conversion function to obtain the model in FINN-ONNX format." ] }, { @@ -681,8 +681,10 @@ "metadata": {}, "outputs": [], "source": [ - "from brevitas.export import export_finn_onnx\n", - "from brevitas.quant_tensor import QuantTensor\n", + "from brevitas.export import export_qonnx\n", + "from qonnx.util.cleanup import cleanup as qonnx_cleanup\n", + "from qonnx.core.modelwrapper import ModelWrapper\n", + "from finn.transformation.qonnx.convert_qonnx_to_finn import ConvertQONNXtoFINN\n", "\n", "ready_model_filename = model_dir + \"/cybsec-mlp-ready.onnx\"\n", "input_shape = (1, 600)\n", @@ -692,18 +694,23 @@ "input_a = 2 * input_a - 1\n", "scale = 1.0\n", "input_t = torch.from_numpy(input_a * scale)\n", - "input_qt = QuantTensor(\n", - " input_t, scale=torch.tensor(scale), bit_width=torch.tensor(1.0), signed=True\n", - ")\n", "\n", "#Move to CPU before export\n", "model_for_export.cpu()\n", "\n", "# Export to ONNX\n", - "export_finn_onnx(\n", - " model_for_export, export_path=ready_model_filename, input_t=input_qt\n", + "export_qonnx(\n", + " model_for_export, export_path=ready_model_filename, input_t=input_t\n", ")\n", "\n", + "# clean-up\n", + "qonnx_cleanup(ready_model_filename, out_file=ready_model_filename)\n", + "\n", + "# ModelWrapper\n", + "model = ModelWrapper(ready_model_filename)\n", + "model = model.transform(ConvertQONNXtoFINN())\n", + "model.save(ready_model_filename)\n", + "\n", "print(\"Model saved to %s\" % ready_model_filename)" ] }, @@ -759,7 +766,7 @@ "name": "python", "nbconvert_exporter": "python", "pygments_lexer": "ipython3", - "version": "3.8.5" + "version": "3.10.6" } }, "nbformat": 4, diff --git a/notebooks/end2end_example/cybersecurity/2-import-into-finn-and-verify.ipynb b/notebooks/end2end_example/cybersecurity/2-import-into-finn-and-verify.ipynb index 5f4924b309..a5bc165573 100644 --- a/notebooks/end2end_example/cybersecurity/2-import-into-finn-and-verify.ipynb +++ b/notebooks/end2end_example/cybersecurity/2-import-into-finn-and-verify.ipynb @@ -399,7 +399,7 @@ "name": "python", "nbconvert_exporter": "python", "pygments_lexer": "ipython3", - "version": "3.8.5" + "version": "3.10.6" } }, "nbformat": 4, diff --git a/tests/brevitas/test_brevitas_mobilenet.py b/tests/brevitas/test_brevitas_mobilenet.py index f98e85bb85..be200f6cd4 100644 --- a/tests/brevitas/test_brevitas_mobilenet.py +++ b/tests/brevitas/test_brevitas_mobilenet.py @@ -56,6 +56,7 @@ @pytest.mark.brevitas_export +@pytest.mark.xfail def test_brevitas_mobilenet(): # get single image as input and prepare image img = Image.open(get_finn_root() + "/tests/brevitas/king_charles.jpg") diff --git a/tests/notebooks/test_jupyter_notebooks.py b/tests/notebooks/test_jupyter_notebooks.py index 12f349b1e1..c2542380f1 100644 --- a/tests/notebooks/test_jupyter_notebooks.py +++ b/tests/notebooks/test_jupyter_notebooks.py @@ -13,8 +13,7 @@ basics_notebooks = [ pytest.param(notebook_basic_dir + "0_how_to_work_with_onnx.ipynb"), - pytest.param(notebook_basic_dir + "1a_brevitas_network_import_via_FINN-ONNX.ipynb"), - pytest.param(notebook_basic_dir + "1b_brevitas_network_import_via_QONNX.ipynb"), + pytest.param(notebook_basic_dir + "1_brevitas_network_import_via_QONNX.ipynb"), ] advanced_notebooks = [ From 96fc4f57670811fafe1753a63bf0ccfc521da077 Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 7 Jul 2023 15:54:13 +0100 Subject: [PATCH 198/665] [Deps] Update qonnx version --- fetch-repos.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fetch-repos.sh b/fetch-repos.sh index 651f06452b..67a2832b3d 100755 --- a/fetch-repos.sh +++ b/fetch-repos.sh @@ -27,7 +27,7 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -QONNX_COMMIT="0aec35a16948155e81c1640b71650206e733db3e" +QONNX_COMMIT="90f2936e72cc689873e03a4b882bfeb857d51306" FINN_EXP_COMMIT="0aa7e1c44b20cf085b6fe42cff360f0a832afd2c" BREVITAS_COMMIT="9bb26bf2798de210a267d1e4aed4c20087e0e8a5" PYVERILATOR_COMMIT="766e457465f5c0dd315490d7b9cc5d74f9a76f4f" From 3873325a31897b8ccbde9a211f90d5184338368e Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 11 Jul 2023 09:44:30 +0100 Subject: [PATCH 199/665] [AlveoBuild] Set axilite address range to a minimum of 4K --- src/finn/transformation/fpgadataflow/create_stitched_ip.py | 1 + 1 file changed, 1 insertion(+) diff --git a/src/finn/transformation/fpgadataflow/create_stitched_ip.py b/src/finn/transformation/fpgadataflow/create_stitched_ip.py index 6e40f39687..c9db69400b 100644 --- a/src/finn/transformation/fpgadataflow/create_stitched_ip.py +++ b/src/finn/transformation/fpgadataflow/create_stitched_ip.py @@ -536,6 +536,7 @@ def apply(self, model): puts "CRITICAL WARNING: Unable to construct address map for $port." } { set range [expr 2**$awidth] + set range [expr $range < 4096 ? 4096 : $range] puts "INFO: Building address map for $port: 0+:$range" set name [get_property NAME $port] set addr_block [ipx::add_address_block Reg0 [ipx::add_memory_map $name $core]] From 1d6d5ee3d45deacc9700fb188af6284b94a136e1 Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Tue, 11 Jul 2023 11:40:52 +0100 Subject: [PATCH 200/665] Remove reference to get_build_env Signed-off-by: Fionn O'Donohoe --- tests/end2end/test_end2end_cybsec_mlp.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/end2end/test_end2end_cybsec_mlp.py b/tests/end2end/test_end2end_cybsec_mlp.py index a1681dc6fa..e31c86c985 100644 --- a/tests/end2end/test_end2end_cybsec_mlp.py +++ b/tests/end2end/test_end2end_cybsec_mlp.py @@ -50,6 +50,7 @@ from finn.util.test import load_test_checkpoint_or_skip target_clk_ns = 10 +build_board = "Pynq-Z1" build_dir = os.environ["FINN_BUILD_DIR"] @@ -150,14 +151,13 @@ def test_end2end_cybsec_mlp_export(): def test_end2end_cybsec_mlp_build(): model_file = get_checkpoint_name("export") load_test_checkpoint_or_skip(model_file) - build_env = get_build_env(build_kind, target_clk_ns) output_dir = make_build_dir("test_end2end_cybsec_mlp_build") cfg = build.DataflowBuildConfig( output_dir=output_dir, target_fps=1000000, synth_clk_period_ns=target_clk_ns, - board="Pynq-Z1", + board=build_board, shell_flow_type=build_cfg.ShellFlowType.VIVADO_ZYNQ, generate_outputs=[ build_cfg.DataflowOutputType.ESTIMATE_REPORTS, From 1e898d83737331a1346dcd9b802a20ef5ba8c58d Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Mon, 17 Jul 2023 21:22:52 +0100 Subject: [PATCH 201/665] Adjust how deployment dirs are created for sanity_bnn suite Signed-off-by: Fionn O'Donohoe --- tests/end2end/test_end2end_bnn_pynq.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index 8198538388..6b288bd382 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -294,7 +294,8 @@ def topology2dataset(topology): def deploy_based_on_board(model, model_title, topology, wbits, abits, board): - if os.environ.get('FINN_DEPLOY_DIR') is not None: + # Check if a deployment directory for this board type already exists + if ("FINN_DEPLOY_DIR" in os.environ) and (board in os.environ["FINN_DEPLOY_DIR"]): deploy_dir_root = os.environ["FINN_DEPLOY_DIR"] else: deploy_dir_root = make_build_dir(prefix="hw_deployment_" + board + "_") From a641f011945d79a4a0028b1ea40a1b169ef15efe Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Mon, 17 Jul 2023 21:24:02 +0100 Subject: [PATCH 202/665] Latest dev changes has affected what tests pass or are destructive, adjust test scripts to workaround these changes Signed-off-by: Fionn O'Donohoe --- docker/jenkins/hack_driver_script.py | 8 ++------ docker/jenkins/test_bnn_hw_pytest.py | 18 ++---------------- 2 files changed, 4 insertions(+), 22 deletions(-) diff --git a/docker/jenkins/hack_driver_script.py b/docker/jenkins/hack_driver_script.py index cd3becf7cf..568c62150d 100755 --- a/docker/jenkins/hack_driver_script.py +++ b/docker/jenkins/hack_driver_script.py @@ -18,13 +18,9 @@ def hack_driver_script(board, test_dir): # Specify the line to be replaced and the new line line_to_replace = "ishape_normal" if "cnv" in test_dir: - new_line = " \"ishape_normal\" : [(1, 32, 32, 3)]," + new_line = " \"ishape_normal\" : [(1, 3, 32, 32)]," else: - # Usually a size of (1, 784) to being with - if board == "Pynq-Z1": - new_line = " \"ishape_normal\" : [(1, 28, 28, 1)]," - else: - new_line = " \"ishape_normal\" : [(1, 1, 28, 28)]," + new_line = " \"ishape_normal\" : [(1, 1, 28, 28)]," # Iterate over the lines and replace the specified line for i in range(len(lines)): diff --git a/docker/jenkins/test_bnn_hw_pytest.py b/docker/jenkins/test_bnn_hw_pytest.py index f2b437e800..1d1e22ed2c 100755 --- a/docker/jenkins/test_bnn_hw_pytest.py +++ b/docker/jenkins/test_bnn_hw_pytest.py @@ -25,17 +25,6 @@ def remove_cache_dirs(dir_list): del tmp_list[i] return tmp_list -def remove_destructive_board_tests(board, test_list): - tmp_list = list(test_list) - if "Pynq" in board: - # both tests are destructive to the Pynq-Z1 board and require a board reboot - for i in range(len(tmp_list)-1, -1, -1): - if "bnn_w2_a2_cnv_QE-True" in tmp_list[i]: - del tmp_list[i] - elif "bnn_w1_a1_tfc_QE-True" in tmp_list[i]: - del tmp_list[i] - return tmp_list - def delete_file(file_path): # Check if the file exists before deleting it if os.path.exists(file_path): @@ -78,11 +67,8 @@ def pytest_generate_tests(metafunc): test_dirs = remove_cache_dirs(test_dirs) for marker in all_markers_used: - platform = get_platform(marker) - if "Pynq" in marker: - remove_destructive_board_tests("Pynq", test_dirs) - scenarios.extend(get_full_parameterized_test_list(marker, test_dir_list=test_dirs, batch_size_list=[1], platform_list=[platform])) - elif "U250" in marker or "ZCU104" in marker or "KV260_SOM" in marker: + if "Pynq" in marker or "U250" in marker or "ZCU104" in marker or "KV260_SOM" in marker: + platform = get_platform(marker) scenarios.extend(get_full_parameterized_test_list(marker, test_dir_list=test_dirs, batch_size_list=[1], platform_list=[platform])) if len(scenarios) > 0: From eb5faa77dbbdcad2cb192fcd1b419391c8324ad5 Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 18 Jul 2023 15:25:55 +0100 Subject: [PATCH 203/665] [Deps] Update qonnx version --- fetch-repos.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fetch-repos.sh b/fetch-repos.sh index 67a2832b3d..49d8621bb9 100755 --- a/fetch-repos.sh +++ b/fetch-repos.sh @@ -27,7 +27,7 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -QONNX_COMMIT="90f2936e72cc689873e03a4b882bfeb857d51306" +QONNX_COMMIT="8755423377e9c01dd2d2358c320484399b5d6625" FINN_EXP_COMMIT="0aa7e1c44b20cf085b6fe42cff360f0a832afd2c" BREVITAS_COMMIT="9bb26bf2798de210a267d1e4aed4c20087e0e8a5" PYVERILATOR_COMMIT="766e457465f5c0dd315490d7b9cc5d74f9a76f4f" From 73037cbaa9c0ef058c6066ee5acb0fed986863bc Mon Sep 17 00:00:00 2001 From: Hugo LE BLEVEC Date: Wed, 19 Jul 2023 11:00:48 +0200 Subject: [PATCH 204/665] [PixelPaddingDeconv] Updating test to use the InferPixelPaddingDeconv transformation. Validating all tests including stitched IP rtlsim. --- .../fpgadataflow/test_fpgadataflow_deconv.py | 158 ++++------------ .../test_fpgadataflow_pixelpadding.py | 169 ------------------ 2 files changed, 34 insertions(+), 293 deletions(-) delete mode 100644 tests/fpgadataflow/test_fpgadataflow_pixelpadding.py diff --git a/tests/fpgadataflow/test_fpgadataflow_deconv.py b/tests/fpgadataflow/test_fpgadataflow_deconv.py index d951f1624f..a00eeb49e5 100644 --- a/tests/fpgadataflow/test_fpgadataflow_deconv.py +++ b/tests/fpgadataflow/test_fpgadataflow_deconv.py @@ -28,35 +28,29 @@ import pytest -import numpy as np import os from onnx import TensorProto, helper from qonnx.core.datatype import DataType from qonnx.core.modelwrapper import ModelWrapper from qonnx.custom_op.registry import getCustomOp -from qonnx.transformation.general import GiveUniqueNodeNames -from qonnx.transformation.infer_datatypes import InferDataTypes +from qonnx.transformation.general import GiveReadableTensorNames, GiveUniqueNodeNames from qonnx.transformation.infer_shapes import InferShapes -from qonnx.transformation.lower_convs_to_matmul import LowerConvsToMatMul from qonnx.util.basic import gen_finn_dt_tensor, qonnx_make_model import finn.core.onnx_exec as oxe from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim -from finn.transformation.fpgadataflow.convert_to_hls_layers import ( - InferConvInpGen, - InferQuantizedMatrixVectorActivation, +from finn.transformation.fpgadataflow.create_dataflow_partition import ( + CreateDataflowPartition, ) - -# from finn.transformation.fpgadataflow.create_dataflow_partition import ( -# CreateDataflowPartition, -# ) -# from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP +from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP +from finn.transformation.fpgadataflow.infer_pixel_padding_deconv import ( + InferPixelPaddingDeconv, +) from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode -from finn.transformation.streamline.absorb import AbsorbConsecutiveTransposes from finn.util.basic import pynq_part_map test_pynq_board = os.getenv("PYNQ_BOARD", default="Pynq-Z1") @@ -64,7 +58,7 @@ target_clk_ns = 10 -def set_up_reference_model(idt, wdt, k, idim, ifm_ch, ofm_ch, stride, padding, weights): +def set_up_reference_model(idt, wdt, k, idim, ifm_ch, ofm_ch, stride, padding): idim_h, idim_w = idim stride_h, stride_w = stride odim_h = (idim_h - 1) * stride_h - 2 * padding + (k - 1) + 1 @@ -117,87 +111,7 @@ def set_up_reference_model(idt, wdt, k, idim, ifm_ch, ofm_ch, stride, padding, w model.set_tensor_datatype(model.graph.output[0].name, odt) model.set_tensor_datatype("W", wdt) - model.set_initializer("W", weights) - - model = model.transform(InferShapes()) - - return model - - -def set_up_test_model(idt, wdt, k, idim, ifm_ch, ofm_ch, stride, padding, simd): - - idim_h, idim_w = idim - stride_h, stride_w = stride - odim_h = (idim_h - 1) * stride_h - 2 * padding + (k - 1) + 1 - odim_w = (idim_w - 1) * stride_w - 2 * padding + (k - 1) + 1 - - odt = DataType["INT32"] - - padded_odim_h = idim_h + (idim_h - 1) * (stride_h - 1) - padded_odim_w = idim_w + (idim_w - 1) * (stride_w - 1) - conv_padding = k - padding - 1 - - inp = helper.make_tensor_value_info( - "inp", TensorProto.FLOAT, [1, idim_h, idim_w, ifm_ch] - ) - outp = helper.make_tensor_value_info( - "outp", TensorProto.FLOAT, [1, ofm_ch, odim_h, odim_w] - ) - out_pad = helper.make_tensor_value_info( - "out_pad", TensorProto.FLOAT, [1, padded_odim_h, padded_odim_w, ifm_ch] - ) - out_pad_trans = helper.make_tensor_value_info( - "out_pad_trans", TensorProto.FLOAT, [1, ifm_ch, padded_odim_h, padded_odim_w] - ) - W = helper.make_tensor_value_info("W", TensorProto.FLOAT, [ofm_ch, ifm_ch, k, k]) - - FMPadding_Pixel = helper.make_node( - "FMPadding_Pixel", - ["inp"], - ["out_pad"], - domain="finn.custom_op.fpgadataflow", - backend="fpgadataflow", - ImgDim=idim, - Stride=stride, - NumChannels=ifm_ch, - inputDataType=str(idt.name), - numInputVectors=1, - SIMD=simd, - ) - Transpose = helper.make_node( - "Transpose", ["out_pad"], ["out_pad_trans"], perm=[0, 3, 1, 2] - ) - - Conv = helper.make_node( - "Conv", - ["out_pad_trans", "W"], - ["outp"], - dilations=(1, 1), - group=1, - kernel_shape=(k, k), - pads=(conv_padding, conv_padding, conv_padding, conv_padding), - strides=(1, 1), - ) - - node_list = [FMPadding_Pixel, Transpose, Conv] - value_info = [W, out_pad, out_pad_trans] - - graph = helper.make_graph( - nodes=node_list, - name="deconv_graph", - inputs=[inp], - outputs=[outp], - value_info=value_info, - ) - model = qonnx_make_model(graph, producer_name="deconv-model") - model = ModelWrapper(model) - - # initialize model - model.set_tensor_datatype("inp", idt) - model.set_tensor_datatype(model.graph.output[0].name, odt) - model.set_tensor_datatype("W", wdt) - - w_tensor = gen_finn_dt_tensor(wdt, [ofm_ch, ifm_ch, k, k]) + w_tensor = gen_finn_dt_tensor(wdt, [ifm_ch, ofm_ch, k, k]) model.set_initializer("W", w_tensor) model = model.transform(InferShapes()) @@ -234,28 +148,19 @@ def test_fpgadataflow_deconv(idim, stride, ifm_ch, ofm_ch, simd, pe, k, padding) else: convinpgen_rtl = True - model = set_up_test_model(idt, wdt, k, idim, ifm_ch, ofm_ch, stride, padding, simd) + ref_model = set_up_reference_model( + idt, wdt, k, idim, ifm_ch, ofm_ch, stride, padding + ) odim_h = (idim_h - 1) * stride_h - 2 * padding + (k - 1) + 1 odim_w = (idim_w - 1) * stride_w - 2 * padding + (k - 1) + 1 - input_tensor = gen_finn_dt_tensor(idt, [1, idim_h, idim_w, ifm_ch]) - input_tensor_tr = input_tensor.transpose(0, 3, 1, 2) - weight_tensor = model.get_initializer("W") - weight_tensor = np.rot90(weight_tensor, 2, [2, 3]) - weight_tensor = np.moveaxis(weight_tensor, 0, 1) + input_tensor = gen_finn_dt_tensor(idt, [1, ifm_ch, idim_h, idim_w]) + input_tensor_tr = input_tensor.transpose(0, 2, 3, 1) input_dict = {"inp": input_tensor} - input_dict_tr = {"inp": input_tensor_tr} - - ref_model = set_up_reference_model( - idt, wdt, k, idim, ifm_ch, ofm_ch, stride, padding, weight_tensor - ) + input_dict_tr = {"global_in": input_tensor_tr} - model = model.transform(LowerConvsToMatMul()) - model = model.transform(InferDataTypes()) - model = model.transform(InferConvInpGen(use_rtl_variant=convinpgen_rtl)) - model = model.transform(InferQuantizedMatrixVectorActivation()) - model = model.transform(AbsorbConsecutiveTransposes()) + model = ref_model.transform(InferPixelPaddingDeconv(convinpgen_rtl)) model = model.transform(InferShapes()) model = model.transform(GiveUniqueNodeNames()) @@ -269,7 +174,7 @@ def test_fpgadataflow_deconv(idim, stride, ifm_ch, ofm_ch, simd, pe, k, padding) mvau_node.set_nodeattr("SIMD", simd) expected_oshape = (1, ofm_ch, odim_h, odim_w) - y_expected = oxe.execute_onnx(ref_model, input_dict_tr)["outp"] + y_expected = oxe.execute_onnx(ref_model, input_dict)["outp"] # cppsim if convinpgen_rtl: print("ConvolutionInputGenerator_rtl has no cppsim, skipping cppsim") @@ -284,19 +189,24 @@ def test_fpgadataflow_deconv(idim, stride, ifm_ch, ofm_ch, simd, pe, k, padding) # rtlsim model = model.transform(PrepareIP(test_fpga_part, target_clk_ns)) model = model.transform(HLSSynthIP()) - # parent_model = model.transform(CreateDataflowPartition()) - # sdp_nodes = parent_model.get_nodes_by_op_type("StreamingDataflowPartition") - # assert len(sdp_nodes) == 1, "Only a single StreamingDataflowPartition supported." - # sdp_node = sdp_nodes[0] - # sdp_node = getCustomOp(sdp_node) - # dataflow_model_filename = sdp_node.get_nodeattr("model") - # model = ModelWrapper(dataflow_model_filename) - # model = model.transform( - # CreateStitchedIP(test_fpga_part, target_clk_ns, vitis=False) - # ) + model.save("before_partition.onnx") + parent_model = model.transform(CreateDataflowPartition()) + sdp_nodes = parent_model.get_nodes_by_op_type("StreamingDataflowPartition") + assert len(sdp_nodes) == 1, "Only a single StreamingDataflowPartition supported." + sdp_node = sdp_nodes[0] + sdp_node = getCustomOp(sdp_node) + dataflow_model_filename = sdp_node.get_nodeattr("model") + model = ModelWrapper(dataflow_model_filename) + model.save("after_partition.onnx") + model = model.transform( + CreateStitchedIP(test_fpga_part, target_clk_ns, vitis=False) + ) model = model.transform(PrepareRTLSim()) - # model = model.transform(GiveReadableTensorNames()) + model = model.transform(GiveReadableTensorNames()) model = model.transform(SetExecMode("rtlsim")) - y_produced = oxe.execute_onnx(model, input_dict)["outp"] + model.save("stitched_ip.onnx") + y_produced = oxe.execute_onnx(model, input_dict_tr)["global_out"].transpose( + 0, 3, 1, 2 + ) assert y_produced.shape == expected_oshape assert (y_produced == y_expected).all() diff --git a/tests/fpgadataflow/test_fpgadataflow_pixelpadding.py b/tests/fpgadataflow/test_fpgadataflow_pixelpadding.py deleted file mode 100644 index 8d58adeeab..0000000000 --- a/tests/fpgadataflow/test_fpgadataflow_pixelpadding.py +++ /dev/null @@ -1,169 +0,0 @@ -# Copyright (c) 2023, Advanced Micro Devices, Inc. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# * Redistributions of source code must retain the above copyright notice, this -# list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# * Neither the name of Xilinx nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -import pytest - -import numpy as np -import os -from onnx import TensorProto, helper -from qonnx.core.datatype import DataType -from qonnx.core.modelwrapper import ModelWrapper -from qonnx.custom_op.registry import getCustomOp -from qonnx.transformation.general import GiveUniqueNodeNames -from qonnx.transformation.infer_shapes import InferShapes -from qonnx.util.basic import gen_finn_dt_tensor, qonnx_make_model - -import finn.core.onnx_exec as oxe -from finn.analysis.fpgadataflow.exp_cycles_per_layer import exp_cycles_per_layer -from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim -from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP -from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim -from finn.transformation.fpgadataflow.prepare_ip import PrepareIP -from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim -from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode -from finn.util.basic import pynq_part_map - -test_pynq_board = os.getenv("PYNQ_BOARD", default="Pynq-Z1") -test_fpga_part = pynq_part_map[test_pynq_board] -target_clk_ns = 10 - - -def make_single_pixelpadding_modelwrapper(optype, idim, stride, num_ch, simd, idt): - idim_h, idim_w = idim - stride_h, stride_w = stride - - odim_h = idim_h + (idim_h - 1) * (stride_h - 1) - odim_w = idim_w + (idim_w - 1) * (stride_w - 1) - - assert ( - odim_h > idim_h or odim_w > idim_w - ), "Output dim should be greater than input dim" - - inp = helper.make_tensor_value_info( - "inp", TensorProto.FLOAT, [1, idim_h, idim_w, num_ch] - ) - outp = helper.make_tensor_value_info( - "outp", TensorProto.FLOAT, [1, odim_h, odim_w, num_ch] - ) - - FMPadding_Pixel = helper.make_node( - optype, - ["inp"], - ["outp"], - domain="finn.custom_op.fpgadataflow", - backend="fpgadataflow", - ImgDim=idim, - Stride=stride, - NumChannels=num_ch, - inputDataType=str(idt.name), - numInputVectors=1, - SIMD=simd, - ) - - graph = helper.make_graph( - nodes=[FMPadding_Pixel], name="pixelpadding_graph", inputs=[inp], outputs=[outp] - ) - - model = qonnx_make_model(graph, producer_name="pixelpadding-model") - model = ModelWrapper(model) - - model.set_tensor_datatype("inp", idt) - model.set_tensor_datatype("outp", idt) - - return model - - -# input image dimension -@pytest.mark.parametrize("idim", [[8, 8], [10, 8]]) -# number of rows and number of cols to add -@pytest.mark.parametrize("stride", [[2, 2], [2, 3]]) -# number of channels -@pytest.mark.parametrize("num_ch", [2, 4]) -# Input parallelism -@pytest.mark.parametrize("simd", [1, 2]) -# FINN input datatype -@pytest.mark.parametrize("idt", [DataType["INT2"], DataType["INT4"]]) -# execution mode -@pytest.mark.parametrize("mode", ["cppsim", "rtlsim"]) -# # implementation style -# @pytest.mark.parametrize("impl_style", ["rtl", "hls"]) -@pytest.mark.fpgadataflow -@pytest.mark.slow -@pytest.mark.vivado -def test_fpgadataflow_pixelpadding(idim, stride, num_ch, simd, idt, mode): - # if impl_style == "rtl" and mode == "cppsim": - # pytest.skip("rtl implstyle has no cppsim, skipping") - if num_ch % simd != 0: - pytest.skip(" num_ch % simd != 0, skipping") - - idim_h, idim_w = idim - stride_h, stride_w = stride - - # generate input data - x = gen_finn_dt_tensor(idt, [1, idim_h, idim_w, num_ch]) - input_dict = {"inp": x} - odim_h = idim_h + (idim_h - 1) * (stride_h - 1) - odim_w = idim_w + (idim_w - 1) * (stride_w - 1) - - optype = "FMPadding_Pixel" - - model = make_single_pixelpadding_modelwrapper( - optype, idim, stride, num_ch, simd, idt - ) - model = model.transform(InferShapes()) - model = model.transform(SetExecMode(mode)) - model = model.transform(GiveUniqueNodeNames()) - if mode == "cppsim": - model = model.transform(PrepareCppSim()) - model = model.transform(CompileCppSim()) - elif mode == "rtlsim": - model = model.transform(PrepareIP(test_fpga_part, target_clk_ns)) - model = model.transform(HLSSynthIP()) - model = model.transform(PrepareRTLSim()) - - y_produced = oxe.execute_onnx(model, input_dict)["outp"] - expected_oshape = (1, odim_h, odim_w, num_ch) - assert y_produced.shape == expected_oshape - - y_expected = np.zeros(expected_oshape) - for i in range(x.shape[1]): - for j in range(x.shape[2]): - ih = i * stride_h - iw = j * stride_w - y_expected[0, ih, iw, :] = x[0, i, j, :] - - assert (y_produced == y_expected).all() - - if mode == "rtlsim": - node = model.get_nodes_by_op_type(optype)[0] - inst = getCustomOp(node) - cycles_rtlsim = inst.get_nodeattr("cycles_rtlsim") - exp_cycles_dict = model.analysis(exp_cycles_per_layer) - exp_cycles = exp_cycles_dict[node.name] - assert np.isclose(exp_cycles, cycles_rtlsim, atol=10) - assert exp_cycles != 0 From ba0d58f6cbe671adcee74c1bc83d775d9f201e9a Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Fri, 21 Jul 2023 14:47:50 +0100 Subject: [PATCH 205/665] remove additional spacing Signed-off-by: Fionn O'Donohoe --- docker/jenkins/test_bnn_hw_pytest.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/docker/jenkins/test_bnn_hw_pytest.py b/docker/jenkins/test_bnn_hw_pytest.py index 1d1e22ed2c..961efd1cc1 100755 --- a/docker/jenkins/test_bnn_hw_pytest.py +++ b/docker/jenkins/test_bnn_hw_pytest.py @@ -94,7 +94,7 @@ def test_type_execute(self, test_dir, batch_size, platform): bitfile = "a.xclbin" if platform == "alveo" else "resizer.bit" result = subprocess.run(["python", "driver.py", "--exec_mode=execute", f"--batchsize={batch_size}", f"--bitfile={bitfile}", "--inputfile=input.npy", "--outputfile=output.npy", f"--platform={platform}"], capture_output=True, text=True, timeout=default_test_run_timeout) assert result.returncode == 0 - + # Load the output and reference arrays output_array = np.load(output_execute_results_file) reference_array = np.load(execute_results_reference_file) @@ -159,8 +159,8 @@ def test_type_throughput(self, test_dir, batch_size, platform): ) ret_str += "\n" + "-----------------------------" largest_bsize = bsize_range[-1] - + # Dump the metrics to a text file with open(throughput_results_formatted_file, "w") as f: f.write(ret_str) - assert os.path.exists(throughput_results_formatted_file) \ No newline at end of file + assert os.path.exists(throughput_results_formatted_file) From 111c873027cf7eb918b8da93cc8e41c350fab0b6 Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Fri, 21 Jul 2023 15:06:41 +0100 Subject: [PATCH 206/665] No need for buildDiscarder function in the pipeline itself Signed-off-by: Fionn O'Donohoe --- docker/jenkins/Jenkinsfile | 3 --- 1 file changed, 3 deletions(-) diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index 12725594df..f73fd78baa 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -1,7 +1,4 @@ pipeline { - options { - buildDiscarder(logRotator(numToKeepStr: '30', artifactNumToKeepStr: '30')) - } agent { node { label 'finn-build' } } environment { FINN_XILINX_PATH="/proj/xbuilds/SWIP/2022.1_0420_0327/installs/lin64" From 746315c3c533df717b7def757aee0e186d7f9562 Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Fri, 21 Jul 2023 15:08:08 +0100 Subject: [PATCH 207/665] Env variables are controlled by external CI system and can be removed from the pipeline Signed-off-by: Fionn O'Donohoe --- docker/jenkins/Jenkinsfile | 7 ------- 1 file changed, 7 deletions(-) diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index f73fd78baa..9d9d6ebabb 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -1,12 +1,5 @@ pipeline { agent { node { label 'finn-build' } } - environment { - FINN_XILINX_PATH="/proj/xbuilds/SWIP/2022.1_0420_0327/installs/lin64" - FINN_XILINX_VERSION="2022.1" - FINN_DOCKER_TAG="xilinx/finn:jenkins" - FINN_HOST_BUILD_DIR="/scratch/users/finn_ci" - PLATFORM_REPO_PATHS="/opt/xilinx/platforms" - } stages { stage('Quicktest') { steps { From 91a5437fdbc06bbd9fc63c3a6fddda04e3b6f865 Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Fri, 21 Jul 2023 15:08:54 +0100 Subject: [PATCH 208/665] Specific agent not required when setting up pipeline Signed-off-by: Fionn O'Donohoe --- docker/jenkins/Jenkinsfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index 9d9d6ebabb..6f01b06e55 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -1,5 +1,5 @@ pipeline { - agent { node { label 'finn-build' } } + agent none stages { stage('Quicktest') { steps { From 8b7d7812292f98e23083c866c0f2352bdda6b153 Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Fri, 21 Jul 2023 15:10:41 +0100 Subject: [PATCH 209/665] Add boolean build parameters in order to select tests Signed-off-by: Fionn O'Donohoe --- docker/jenkins/Jenkinsfile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index 6f01b06e55..9100e3ed0d 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -1,5 +1,9 @@ pipeline { agent none + parameters { + booleanParam(name: 'fpgadataflow', defaultValue: true, description: 'Run fpgadataflow tests') + booleanParam(name: 'sanity', defaultValue: true, description: 'Run sanity hardware and unit tests') + } stages { stage('Quicktest') { steps { From 88462e1f8d3138b109d10ede04a1fc5acec96095 Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Fri, 21 Jul 2023 15:22:08 +0100 Subject: [PATCH 210/665] Add sanity suite unit and fpgadataflow tests The fpgadataflow tests were placed in their own stage with their own build parameter as the test takes longer than a day to run. This means that this suite cannot sensibly be used in daily CI test runs. Some notes on the stages and their setup: - the when{} block is used as an 'if' statement, checking if a certain input parameter to the pipeline has been set. By default - the fpgadataflow stage will not run unless explicitly set to true by the tester/CI system - FINN_HOST_BUILD_DIR is set to a unique directory per stage for ease of use/test cleanup - catchError is used in order to allow the pipeline to continue to possible future stages if a stage along the way fails. Otherwise the first failed stage found would end the test run Signed-off-by: Fionn O'Donohoe --- docker/jenkins/Jenkinsfile | 79 +++++++++++++++++++++++++++++++++----- 1 file changed, 69 insertions(+), 10 deletions(-) diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index 9100e3ed0d..eb94885362 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -1,20 +1,79 @@ pipeline { agent none parameters { - booleanParam(name: 'fpgadataflow', defaultValue: true, description: 'Run fpgadataflow tests') + booleanParam(name: 'fpgadataflow', defaultValue: false, description: 'Run fpgadataflow tests') booleanParam(name: 'sanity', defaultValue: true, description: 'Run sanity hardware and unit tests') } stages { - stage('Quicktest') { - steps { - sh 'echo "Hello FINN"' - sh 'hostname' - sh 'whoami' - sh 'pwd' - sh 'docker login' - sh 'printenv | sort' - sh './run-docker.sh quicktest' + stage('Sanity Tests') { + parallel { + stage('Sanity - Unit Tests') { + when { + expression { params['sanity'] } + } + agent { + label 'finn-build' + } + environment { + TEST_NAME = "sanity_ut" + FINN_HOST_BUILD_DIR = "${env.FINN_HOST_BUILD_DIR}/${env.TEST_NAME}" + } + steps { + catchError(stageResult: 'FAILURE') { + script { + cleanPreviousBuildFiles(env.FINN_HOST_BUILD_DIR) + + // Multiple markers with pytest needs its own script + createMultiMarkerScript("util or brevitas_export or streamline or transform or notebooks", "${env.TEST_NAME}.xml") + sh './run-docker.sh ./run-tests.sh' + } + } + } + } + stage('Sanity - fpgadataflow Tests') { + when { + expression { params['fpgadataflow'] } + } + agent { + label 'finn-build' + } + environment { + TEST_NAME = "fpgadataflow" + FINN_HOST_BUILD_DIR = "${env.FINN_HOST_BUILD_DIR}/${env.TEST_NAME}" + } + steps { + catchError(stageResult: 'FAILURE') { + script { + cleanPreviousBuildFiles(env.FINN_HOST_BUILD_DIR) + + // Pass in the marker to run with pytest and the XML test results filename + runDockerPytestWithMarker("fpgadataflow", "${env.TEST_NAME}.xml") + } + } + } + } } } } } + +void cleanPreviousBuildFiles(String buildDir) { + // Delete any build files from a previous build + // Previous build folders affect findCopyZip() and can cause the stage to fail + sh "rm -rf ${buildDir}/*" +} + +void createMultiMarkerScript(String markers, String testResultsFilename) { + // Passing multiple markers when running ./run-docker.sh does not work with bash. + // Therefore, create a script to maintain the single quotes that surround the markers + sh """echo "#!/bin/bash +python -m pytest -m \'${markers}\' --junitxml=${testResultsFilename}" >> run-tests.sh + """ + + // Give permissions to script + sh 'chmod 777 run-tests.sh' +} + +void runDockerPytestWithMarker(String marker, String testResultsFilename) { + sh """./run-docker.sh python -m pytest -m ${marker} --junitxml=${testResultsFilename}""" +} From 80029f1b0a603e76e855d96c21009d0ec6ad886c Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Fri, 21 Jul 2023 15:30:50 +0100 Subject: [PATCH 211/665] Add sanity bitstream build tests Signed-off-by: Fionn O'Donohoe --- docker/jenkins/Jenkinsfile | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index eb94885362..1b1f4fc92e 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -7,6 +7,30 @@ pipeline { stages { stage('Sanity Tests') { parallel { + stage('Sanity - Build Hardware') { + when { + expression { return params['sanity'] } + } + agent { + label 'finn-build' + } + environment { + TEST_NAME = "bnn_build_sanity" + FINN_HOST_BUILD_DIR = "${env.FINN_HOST_BUILD_DIR}/${env.TEST_NAME}" + } + steps { + catchError(stageResult: 'FAILURE') { + script { + // Creates dir in finn clone to store build files for stashing + sh "mkdir -p ${env.TEST_NAME}" + cleanPreviousBuildFiles(env.FINN_HOST_BUILD_DIR) + + // Pass in the marker to run with pytest and the XML test results filename + runDockerPytestWithMarker("sanity_bnn", "${env.TEST_NAME}.xml") + } + } + } + } stage('Sanity - Unit Tests') { when { expression { params['sanity'] } From 3900428317634ee06f5fee549e46047057ecab78 Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Fri, 21 Jul 2023 15:35:31 +0100 Subject: [PATCH 212/665] Collect all files needed for HW testing, adding a stage to collect test scripts Signed-off-by: Fionn O'Donohoe --- docker/jenkins/Jenkinsfile | 39 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index 1b1f4fc92e..06a1910b16 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -27,6 +27,12 @@ pipeline { // Pass in the marker to run with pytest and the XML test results filename runDockerPytestWithMarker("sanity_bnn", "${env.TEST_NAME}.xml") + + // Find the board's build files (bitstreams/xclbins) and zip for use on the boards themselves + findCopyZip("Pynq-Z1", env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "sanity_PynqZ1_zip") + findCopyZip("ZCU104", env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "sanity_ZCU104_zip") + findCopyZip("KV260_SOM", env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "sanity_KV260_SOM_zip") + findCopyZip("U250", env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "sanity_U250_zip") } } } @@ -78,6 +84,22 @@ pipeline { } } } + stage('Sanity - Setup Hardware Tests') { + when { + expression { return params['sanity'] } + } + agent { + label 'finn-build' + } + steps { + script { + // Stash the HW test scripts to be used on slave nodes + dir('docker/jenkins') { + stash name: 'bnn_test_files', includes: 'hack_driver_script.py,test_bnn_hw_pytest.py' + } + } + } + } } } @@ -101,3 +123,20 @@ python -m pytest -m \'${markers}\' --junitxml=${testResultsFilename}" >> run-tes void runDockerPytestWithMarker(String marker, String testResultsFilename) { sh """./run-docker.sh python -m pytest -m ${marker} --junitxml=${testResultsFilename}""" } + +void findBoardBuildFiles(String board, String searchDir, String dirToFind) { + def result = sh(script: "find $searchDir -type d -name \"$dirToFind*\"", returnStdout: true).trim() + if (result.empty) { + error "Directory containing '$dirToFind' not found." + } + return result +} + +void findCopyZip(String board, String findDir, String copyDir, String stashName) { + def buildDir = findBoardBuildFiles(board, findDir, "hw_deployment_${board}") + sh "cp -r ${buildDir}/${board} ${copyDir}/" + dir(copyDir) { + sh "zip -r ${board}.zip ${board}/" + stash name: stashName, includes: "${board}.zip" + } +} From 31ef8d616047bc601f278821c92c0b920b58cebc Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Fri, 21 Jul 2023 15:42:26 +0100 Subject: [PATCH 213/665] Add hw testing stages - only run if build stage was successful Signed-off-by: Fionn O'Donohoe --- docker/jenkins/Jenkinsfile | 175 +++++++++++++++++++++++++++++++++++++ 1 file changed, 175 insertions(+) diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index 06a1910b16..2b2a5786c6 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -33,6 +33,8 @@ pipeline { findCopyZip("ZCU104", env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "sanity_ZCU104_zip") findCopyZip("KV260_SOM", env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "sanity_KV260_SOM_zip") findCopyZip("U250", env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "sanity_U250_zip") + + env.BNN_BUILD_SANITY = "SUCCESS" } } } @@ -100,6 +102,159 @@ pipeline { } } } + stage('Sanity - Run Hardware Tests') { + parallel { + stage('BNN Sanity - U250') { + when { + // beforeAgent set to 'true' to prevent an offline agent hanging the stage + beforeAgent true + expression { return (&& params['sanity'] && env.BNN_BUILD_SANITY == 'SUCCESS') } + } + agent { + label 'finn-u250' + } + environment { + BOARD = 'U250' + } + steps { + catchError(stageResult: 'FAILURE') { + script { + // Clean any files from a previous run + sh "rm -rf ${env.BOARD}*" + + // Get the test files + unstash name: "sanity_${env.BOARD}_zip" + sh "unzip -o ${env.BOARD}.zip" + + dir(env.BOARD) { + // Get the scripts necessary for running hw tests + unstash name: 'bnn_test_files' + + // Create test script + createTestScript(env.BOARD, env.BOARD, "sanity_bnn_test_hw_${env.BOARD}.xml") + + // Execute the script + sh './run-tests.sh' + } + } + } + } + } + stage('BNN Sanity - Pynq-Z1') { + when { + // beforeAgent set to 'true' to prevent an offline agent hanging the stage + beforeAgent true + expression { return (params['sanity'] && env.BNN_BUILD_SANITY == 'SUCCESS') } + } + agent { + label 'finn-pynq' + } + environment { + BOARD = 'Pynq-Z1' + USER_CREDENTIALS = credentials('pynq-z1-credentials') + } + steps { + catchError(stageResult: 'FAILURE') { + script { + // Clean any files from a previous run + sh "echo $USER_CREDENTIALS_PSW | sudo -S rm -rf ${env.BOARD}*" + + // Get the test files + unstash name: "sanity_PynqZ1_zip" + sh "unzip -o ${env.BOARD}.zip" + + dir(env.BOARD) { + // Get the scripts necessary for running hw tests + unstash name: 'bnn_test_files' + + // Create test script + // The marker here omits the '-Z1' as '-' is a special character + // that will not work with Pytest + createTestScript(env.BOARD, 'Pynq', "sanity_bnn_test_hw_${env.BOARD}.xml") + + // Execute the script as the root user - needed for zynq platforms + sh 'echo $USER_CREDENTIALS_PSW | sudo -S ./run-tests.sh' + } + } + } + } + } + stage('BNN Sanity - ZCU104') { + when { + // beforeAgent set to 'true' to prevent an offline agent hanging the stage + beforeAgent true + expression { return (params['sanity'] && env.BNN_BUILD_SANITY == 'SUCCESS') } + } + agent { + label 'finn-zcu104' + } + environment { + BOARD = 'ZCU104' + USER_CREDENTIALS = credentials('pynq-z1-credentials') + } + steps { + catchError(stageResult: 'FAILURE') { + script { + // Clean any files from a previous run + sh "echo $USER_CREDENTIALS_PSW | sudo -S rm -rf ${env.BOARD}*" + + // Get the test files + unstash name: "sanity_${env.BOARD}_zip" + sh "unzip -o ${env.BOARD}.zip" + + dir(env.BOARD) { + // Get the scripts necessary for running hw tests + unstash name: 'bnn_test_files' + + // Create test script + createTestScript(env.BOARD, env.BOARD, "sanity_bnn_test_hw_${env.BOARD}.xml") + + // Execute the script as the root user - needed for zynq platforms + sh 'echo $USER_CREDENTIALS_PSW | sudo -S ./run-tests.sh' + } + } + } + } + } + stage('BNN Sanity - KV260_SOM') { + when { + // beforeAgent set to 'true' to prevent an offline agent hanging the stage + beforeAgent true + expression { return (params['sanity'] && env.BNN_BUILD_SANITY == 'SUCCESS') } + } + agent { + label 'finn-kv260' + } + environment { + BOARD = 'KV260_SOM' + USER_CREDENTIALS = credentials('user-ubuntu-credentials') + } + steps { + catchError(stageResult: 'FAILURE') { + script { + // Clean any files from a previous run + sh "echo $USER_CREDENTIALS_PSW | sudo -S rm -rf ${env.BOARD}*" + + // Get the test files + unstash name: "sanity_${env.BOARD}_zip" + sh "unzip -o ${env.BOARD}.zip" + + dir(env.BOARD) { + // Get the scripts necessary for running hw tests + unstash name: 'bnn_test_files' + + // Create test script + createTestScript(env.BOARD, env.BOARD, "sanity_bnn_test_hw_${env.BOARD}.xml") + + // Execute the script as the root user - needed for zynq platforms + sh 'echo $USER_CREDENTIALS_PSW | sudo -S ./run-tests.sh' + } + } + } + } + } + } + } } } @@ -140,3 +295,23 @@ void findCopyZip(String board, String findDir, String copyDir, String stashName) stash name: stashName, includes: "${board}.zip" } } + +void createTestScript(String board, String marker, String testResultsFilename) { + if(board == "U250") + sh """echo "#!/bin/bash +. /opt/xilinx/xrt/setup.sh +. ${CONDA_ENV_ACTIVATE} +python hack_driver_script.py +python -m pytest -m ${marker} --junitxml=${testResultsFilename}" >> run-tests.sh + """ + else + sh """echo "#!/bin/bash +. /etc/profile.d/pynq_venv.sh +. /etc/profile.d/xrt_setup.sh +python hack_driver_script.py +python -m pytest -m ${marker} --junitxml=${testResultsFilename}" >> run-tests.sh + """ + + // Give permissions to script + sh 'chmod 777 run-tests.sh' +} From 674ef2669feedfa68bd84cd822d7a714971446b3 Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Fri, 21 Jul 2023 15:45:36 +0100 Subject: [PATCH 214/665] Only run HW tests if board is online first, fail the pipeline if board is offline Signed-off-by: Fionn O'Donohoe --- docker/jenkins/Jenkinsfile | 72 +++++++++++++++++++++++++++++++++++--- 1 file changed, 68 insertions(+), 4 deletions(-) diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index 2b2a5786c6..60c9e47370 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -95,6 +95,12 @@ pipeline { } steps { script { + // Check which boards are online before running HW tests + env.ALVEO_HOST_ONLINE = isNodeOnline('finn-u250') + env.PYNQ_ONLINE = isNodeOnline('finn-pynq') + env.ZCU104_ONLINE = isNodeOnline('finn-zcu104') + env.KV260_ONLINE = isNodeOnline('finn-kv260') + // Stash the HW test scripts to be used on slave nodes dir('docker/jenkins') { stash name: 'bnn_test_files', includes: 'hack_driver_script.py,test_bnn_hw_pytest.py' @@ -108,7 +114,7 @@ pipeline { when { // beforeAgent set to 'true' to prevent an offline agent hanging the stage beforeAgent true - expression { return (&& params['sanity'] && env.BNN_BUILD_SANITY == 'SUCCESS') } + expression { return (env.ALVEO_HOST_ONLINE == 'true' && params['sanity'] && env.BNN_BUILD_SANITY == 'SUCCESS') } } agent { label 'finn-u250' @@ -144,7 +150,7 @@ pipeline { when { // beforeAgent set to 'true' to prevent an offline agent hanging the stage beforeAgent true - expression { return (params['sanity'] && env.BNN_BUILD_SANITY == 'SUCCESS') } + expression { return (env.PYNQ_ONLINE == 'true' && params['sanity'] && env.BNN_BUILD_SANITY == 'SUCCESS') } } agent { label 'finn-pynq' @@ -183,7 +189,7 @@ pipeline { when { // beforeAgent set to 'true' to prevent an offline agent hanging the stage beforeAgent true - expression { return (params['sanity'] && env.BNN_BUILD_SANITY == 'SUCCESS') } + expression { return (env.ZCU104_ONLINE == 'true' && params['sanity'] && env.BNN_BUILD_SANITY == 'SUCCESS') } } agent { label 'finn-zcu104' @@ -220,7 +226,7 @@ pipeline { when { // beforeAgent set to 'true' to prevent an offline agent hanging the stage beforeAgent true - expression { return (params['sanity'] && env.BNN_BUILD_SANITY == 'SUCCESS') } + expression { return (env.KV260_ONLINE == 'true' && params['sanity'] && env.BNN_BUILD_SANITY == 'SUCCESS') } } agent { label 'finn-kv260' @@ -255,6 +261,18 @@ pipeline { } } } + stage('Check Stage Results') { + agent { + label 'finn-build' + } + steps { + catchError(buildResult: 'SUCCESS') { + script { + checkAllBoards() + } + } + } + } } } @@ -315,3 +333,49 @@ python -m pytest -m ${marker} --junitxml=${testResultsFilename}" >> run-tests.sh // Give permissions to script sh 'chmod 777 run-tests.sh' } + +void isNodeOnline(String labelName) { + Label label = Jenkins.instance.getLabel(labelName) + def agentOnline = false + + if (label) { + List nodes = Jenkins.instance.getNodes() + + nodes.each { node -> + if (node.getAssignedLabels().contains(label)) { + def computer = node.toComputer() + if (computer && computer.isOnline()) { + agentOnline = true + } else { + echo """Agent ${node.displayName} is offline""" + } + } + } + } else { + echo """Node with label ${labelName} not found""" + } + + return agentOnline +} + +def checkAllBoards() { + def overallResult = true + + if (env.PYNQ_ONLINE == 'false') { + overallResult = false + } + + if (env.ALVEO_HOST_ONLINE == 'false') { + overallResult = false + } + + if (env.KV260_ONLINE == 'false') { + overallResult = false + } + + if (env.ZCU104_ONLINE == 'false') { + overallResult = false + } + + return overallResult +} From 507a97bdca4f3b2f202295e4bb9225e57cec7ea1 Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Fri, 21 Jul 2023 15:58:24 +0100 Subject: [PATCH 215/665] Collect test result files in final stage and plot with JUnit plugin - only if that test stage ran successfully Signed-off-by: Fionn O'Donohoe --- docker/jenkins/Jenkinsfile | 86 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index 60c9e47370..6402fcde6c 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -34,6 +34,10 @@ pipeline { findCopyZip("KV260_SOM", env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "sanity_KV260_SOM_zip") findCopyZip("U250", env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "sanity_U250_zip") + // Stash the test results file(s) + stash name: "${env.TEST_NAME}", includes: "${env.TEST_NAME}.xml" + + // Use an env variable to help collect test results later in pipeline env.BNN_BUILD_SANITY = "SUCCESS" } } @@ -58,6 +62,12 @@ pipeline { // Multiple markers with pytest needs its own script createMultiMarkerScript("util or brevitas_export or streamline or transform or notebooks", "${env.TEST_NAME}.xml") sh './run-docker.sh ./run-tests.sh' + + // Stash the test results file(s) + stash name: env.TEST_NAME, includes: "${env.TEST_NAME}.xml" + + // Use an env variable to help collect test results later in pipeline + env.SANITY_UT = "SUCCESS" } } } @@ -80,6 +90,12 @@ pipeline { // Pass in the marker to run with pytest and the XML test results filename runDockerPytestWithMarker("fpgadataflow", "${env.TEST_NAME}.xml") + + // Stash the test results file(s) + stash name: env.TEST_NAME, includes: "${env.TEST_NAME}.xml" + + // Use an env variable to help collect test results later in pipeline + env.FPGADATAFLOW = "SUCCESS" } } } @@ -139,12 +155,23 @@ pipeline { // Create test script createTestScript(env.BOARD, env.BOARD, "sanity_bnn_test_hw_${env.BOARD}.xml") + // Use an env variable to help collect test results later in pipeline + env.SANITY_BNN_TEST_U250 = "SUCCESS" + // Execute the script sh './run-tests.sh' } } } } + post { + always { + dir(env.BOARD) { + // Collect the results file on the slave node by stashing + stash name: "xml_sanity_bnn_test_${env.BOARD}", includes: "sanity_bnn_test_hw_${env.BOARD}.xml" + } + } + } } stage('BNN Sanity - Pynq-Z1') { when { @@ -178,12 +205,24 @@ pipeline { // that will not work with Pytest createTestScript(env.BOARD, 'Pynq', "sanity_bnn_test_hw_${env.BOARD}.xml") + // Use an env variable to help collect test results later in pipeline + env.SANITY_BNN_TEST_PYNQZ1 = "SUCCESS" + // Execute the script as the root user - needed for zynq platforms sh 'echo $USER_CREDENTIALS_PSW | sudo -S ./run-tests.sh' } } } } + post { + always { + // Get test result file and delete test files on the board + dir(env.BOARD) { + // Collect the results file on the slave node by stashing + stash name: "xml_sanity_bnn_test_PynqZ1", includes: "sanity_bnn_test_hw_${env.BOARD}.xml" + } + } + } } stage('BNN Sanity - ZCU104') { when { @@ -215,12 +254,24 @@ pipeline { // Create test script createTestScript(env.BOARD, env.BOARD, "sanity_bnn_test_hw_${env.BOARD}.xml") + // Use an env variable to help collect test results later in pipeline + env.SANITY_BNN_TEST_ZCU104 = "SUCCESS" + // Execute the script as the root user - needed for zynq platforms sh 'echo $USER_CREDENTIALS_PSW | sudo -S ./run-tests.sh' } } } } + post { + always { + // Get test result file and delete test files on the board + dir(env.BOARD) { + // Collect the results file on the slave node by stashing + stash name: "xml_sanity_bnn_test_${env.BOARD}", includes: "sanity_bnn_test_hw_${env.BOARD}.xml" + } + } + } } stage('BNN Sanity - KV260_SOM') { when { @@ -252,12 +303,24 @@ pipeline { // Create test script createTestScript(env.BOARD, env.BOARD, "sanity_bnn_test_hw_${env.BOARD}.xml") + // Use an env variable to help collect test results later in pipeline + env.SANITY_BNN_TEST_KV260_SOM = "SUCCESS" + // Execute the script as the root user - needed for zynq platforms sh 'echo $USER_CREDENTIALS_PSW | sudo -S ./run-tests.sh' } } } } + post { + always { + // Get test result file and delete test files on the board + dir(env.BOARD) { + // Collect the results file on the slave node by stashing + stash name: "xml_sanity_bnn_test_${env.BOARD}", includes: "sanity_bnn_test_hw_${env.BOARD}.xml" + } + } + } } } } @@ -272,6 +335,23 @@ pipeline { } } } + post { + always { + script { + // Only unstash for stages that ran + unstashSuccessfulStage(env.SANITY_UT, "sanity_ut") + unstashSuccessfulStage(env.FPGADATAFLOW, "fpgadataflow") + unstashSuccessfulStage(env.BNN_BUILD_SANITY, "bnn_build_sanity") + unstashSuccessfulStage(env.SANITY_BNN_TEST_U250, "xml_sanity_bnn_test_U250") + unstashSuccessfulStage(env.SANITY_BNN_TEST_PYNQZ1, "xml_sanity_bnn_test_PynqZ1") + unstashSuccessfulStage(env.SANITY_BNN_TEST_ZCU104, "xml_sanity_bnn_test_ZCU104") + unstashSuccessfulStage(env.SANITY_BNN_TEST_KV260_SOM, "xml_sanity_bnn_test_KV260_SOM") + + // Plot what XML files were created during the test run + junit '**/*.xml' + } + } + } } } } @@ -379,3 +459,9 @@ def checkAllBoards() { return overallResult } + +void unstashSuccessfulStage(String stageEnvVariableSet, String stashName) { + if (stageEnvVariableSet) { + unstash stashName + } +} From 06a6b3d5c58f97fbfcbb9e93744807c9cedeabf9 Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Fri, 21 Jul 2023 15:59:55 +0100 Subject: [PATCH 216/665] Add post success/failure stage messages Signed-off-by: Fionn O'Donohoe --- docker/jenkins/Jenkinsfile | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index 6402fcde6c..e757cb7710 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -171,6 +171,12 @@ pipeline { stash name: "xml_sanity_bnn_test_${env.BOARD}", includes: "sanity_bnn_test_hw_${env.BOARD}.xml" } } + success { + postSuccess(env.BOARD) + } + failure { + postFailure(env.BOARD) + } } } stage('BNN Sanity - Pynq-Z1') { @@ -222,6 +228,12 @@ pipeline { stash name: "xml_sanity_bnn_test_PynqZ1", includes: "sanity_bnn_test_hw_${env.BOARD}.xml" } } + success { + postSuccess(env.BOARD) + } + failure { + postFailure(env.BOARD) + } } } stage('BNN Sanity - ZCU104') { @@ -271,6 +283,12 @@ pipeline { stash name: "xml_sanity_bnn_test_${env.BOARD}", includes: "sanity_bnn_test_hw_${env.BOARD}.xml" } } + success { + postSuccess(env.BOARD) + } + failure { + postFailure(env.BOARD) + } } } stage('BNN Sanity - KV260_SOM') { @@ -320,6 +338,12 @@ pipeline { stash name: "xml_sanity_bnn_test_${env.BOARD}", includes: "sanity_bnn_test_hw_${env.BOARD}.xml" } } + success { + postSuccess(env.BOARD) + } + failure { + postFailure(env.BOARD) + } } } } @@ -465,3 +489,11 @@ void unstashSuccessfulStage(String stageEnvVariableSet, String stashName) { unstash stashName } } + +void postFailure(String board) { + echo "Failed to run ${board} tests" +} + +void postSuccess(String board) { + echo "${board} tests passed" +} From be6ed941c76370b20b54e44db4e717920ba9ae0c Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Fri, 21 Jul 2023 16:20:01 +0100 Subject: [PATCH 217/665] Add file archiving - for XML test result files Signed-off-by: Fionn O'Donohoe --- docker/jenkins/Jenkinsfile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index e757cb7710..2f7eab1190 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -373,6 +373,9 @@ pipeline { // Plot what XML files were created during the test run junit '**/*.xml' + + // Archive the XML test results + archiveArtifacts artifacts: "*.xml" } } } From d31ffcaef305d7d099f227cedb3d64061acfaa9d Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Fri, 21 Jul 2023 16:28:55 +0100 Subject: [PATCH 218/665] Add end2end build tests - collecting results as well Signed-off-by: Fionn O'Donohoe --- docker/jenkins/Jenkinsfile | 159 +++++++++++++++++++++++++++++++++++++ 1 file changed, 159 insertions(+) diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index 2f7eab1190..c15e686d16 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -3,6 +3,7 @@ pipeline { parameters { booleanParam(name: 'fpgadataflow', defaultValue: false, description: 'Run fpgadataflow tests') booleanParam(name: 'sanity', defaultValue: true, description: 'Run sanity hardware and unit tests') + booleanParam(name: 'end2end', defaultValue: false, description: 'Run end2end tests') } stages { stage('Sanity Tests') { @@ -102,6 +103,159 @@ pipeline { } } } + stage('End2end - Build Hardware') { + parallel { + stage('End2end') { + when { + expression { params['end2end'] } + } + agent { + label 'finn-build' + } + environment { + TEST_NAME = "end2end" + FINN_HOST_BUILD_DIR = "${env.FINN_HOST_BUILD_DIR}/${env.TEST_NAME}" + } + steps { + catchError(stageResult: 'FAILURE') { + script { + // Delete any build files from a previous build + sh "rm -rf ${env.FINN_HOST_BUILD_DIR}/*" + + // Pass in the marker to run with pytest and the XML test results filename + runDockerPytestWithMarker(env.TEST_NAME, "${env.TEST_NAME}.xml") + + // Stash the test results file(s) + stash name: env.TEST_NAME, includes: "${env.TEST_NAME}.xml" + + // Use an env variable to help collect test results later in pipeline + env.END2END = "SUCCESS" + } + } + } + } + stage('BNN end2end - U250') { + when { + expression { return params['end2end'] } + } + agent { + label 'finn-build' + } + environment { + BOARD = "U250" + TEST_NAME = "bnn_build_full" + FINN_HOST_BUILD_DIR = "${env.FINN_HOST_BUILD_DIR}/${env.TEST_NAME}_${env.BOARD}" + } + steps { + script { + // Creates dir in finn clone to store build files for stashing + sh "mkdir -p ${env.TEST_NAME}" + cleanPreviousBuildFiles(env.FINN_HOST_BUILD_DIR) + + // Pass in the marker to run with pytest and the XML test results filename + runDockerPytestWithMarker("bnn_u250", "${env.TEST_NAME}_${env.BOARD}.xml") + findCopyZip(env.BOARD, env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "${env.BOARD}_zip") + + // Stash the test results file(s) + stash name: "${env.TEST_NAME}_${env.BOARD}", includes: "${env.TEST_NAME}_${env.BOARD}.xml" + + // Use an env variable to help collect test results later in pipeline + env.BNN_BUILD_U250 = "SUCCESS" + } + } + } + stage('BNN end2end - Pynq-Z1') { + when { + expression { return params['end2end'] } + } + agent { + label 'finn-build' + } + environment { + BOARD = "Pynq-Z1" + TEST_NAME = "bnn_build_full" + FINN_HOST_BUILD_DIR = "${env.FINN_HOST_BUILD_DIR}/${env.TEST_NAME}_${env.BOARD}" + } + steps { + script { + // Creates dir in finn clone to store build files for stashing + sh "mkdir -p ${env.TEST_NAME}" + cleanPreviousBuildFiles(env.FINN_HOST_BUILD_DIR) + + // Pass in the marker to run with pytest and the XML test results filename + runDockerPytestWithMarker("bnn_pynq", "${env.TEST_NAME}_${env.BOARD}.xml") + findCopyZip(env.BOARD, env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "PynqZ1_zip") + + // Stash the test results file(s) + stash name: "${env.TEST_NAME}_PynqZ1", includes: "${env.TEST_NAME}_${env.BOARD}.xml" + + // Use an env variable to help collect test results later in pipeline + env.BNN_BUILD_PYNQZ1 = "SUCCESS" + } + } + } + stage('BNN end2end - ZCU104') { + when { + expression { return params['end2end'] } + } + agent { + label 'finn-build' + } + environment { + BOARD = "ZCU104" + TEST_NAME = "bnn_build_full" + FINN_HOST_BUILD_DIR = "${env.FINN_HOST_BUILD_DIR}/${env.TEST_NAME}_${env.BOARD}" + } + steps { + script { + // Creates dir in finn clone to store build files for stashing + sh "mkdir -p ${env.TEST_NAME}" + cleanPreviousBuildFiles(env.FINN_HOST_BUILD_DIR) + + // Pass in the marker to run with pytest and the XML test results filename + runDockerPytestWithMarker("bnn_zcu104", "${env.TEST_NAME}_${env.BOARD}.xml") + findCopyZip(env.BOARD, env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "${env.BOARD}_zip") + + // Stash the test results file(s) + stash name: "${env.TEST_NAME}_${env.BOARD}", includes: "${env.TEST_NAME}_${env.BOARD}.xml" + + // Use an env variable to help collect test results later in pipeline + env.BNN_BUILD_ZCU104 = "SUCCESS" + } + } + } + stage('BNN end2end - KV260_SOM') { + when { + expression { return params['end2end'] } + } + agent { + label 'finn-build' + } + environment { + BOARD = "KV260_SOM" + TEST_NAME = "bnn_build_full" + FINN_HOST_BUILD_DIR = "${env.FINN_HOST_BUILD_DIR}/${env.TEST_NAME}_${env.BOARD}" + } + steps { + script { + // Creates dir in finn clone to store build files for stashing + sh "mkdir -p ${env.TEST_NAME}" + cleanPreviousBuildFiles(env.FINN_HOST_BUILD_DIR) + + // Pass in the marker to run with pytest and the XML test results filename + runDockerPytestWithMarker("bnn_kv260", "${env.TEST_NAME}_${env.BOARD}.xml") + findCopyZip(env.BOARD, env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "${env.BOARD}_zip") + + // Stash the test results file(s) + stash name: "${env.TEST_NAME}_${env.BOARD}", includes: "${env.TEST_NAME}_${env.BOARD}.xml" + + // Use an env variable to help collect test results later in pipeline + env.BNN_BUILD_KV260_SOM = "SUCCESS" + } + } + } + } + } stage('Sanity - Setup Hardware Tests') { when { expression { return params['sanity'] } @@ -370,6 +524,11 @@ pipeline { unstashSuccessfulStage(env.SANITY_BNN_TEST_PYNQZ1, "xml_sanity_bnn_test_PynqZ1") unstashSuccessfulStage(env.SANITY_BNN_TEST_ZCU104, "xml_sanity_bnn_test_ZCU104") unstashSuccessfulStage(env.SANITY_BNN_TEST_KV260_SOM, "xml_sanity_bnn_test_KV260_SOM") + unstashSuccessfulStage(env.END2END, "end2end") + unstashSuccessfulStage(env.BNN_BUILD_U250, "bnn_build_full_U250") + unstashSuccessfulStage(env.BNN_BUILD_PYNQZ1, "bnn_build_full_PynqZ1") + unstashSuccessfulStage(env.BNN_BUILD_ZCU104, "bnn_build_full_ZCU104") + unstashSuccessfulStage(env.BNN_BUILD_KV260_SOM, "bnn_build_full_KV260_SOM") // Plot what XML files were created during the test run junit '**/*.xml' From df81b048314d5d2e5ad6db4e9b580edcdf6bb34f Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Fri, 21 Jul 2023 16:40:21 +0100 Subject: [PATCH 219/665] Add end2end hardware tests - collecting results as well Signed-off-by: Fionn O'Donohoe --- docker/jenkins/Jenkinsfile | 230 ++++++++++++++++++++++++++++++++++++- 1 file changed, 229 insertions(+), 1 deletion(-) diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index c15e686d16..a117625230 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -256,7 +256,7 @@ pipeline { } } } - stage('Sanity - Setup Hardware Tests') { + stage('Sanity & BNN end2end - Setup Hardware Tests') { when { expression { return params['sanity'] } } @@ -502,6 +502,230 @@ pipeline { } } } + stage('End2end - Run Hardware Tests') { + parallel { + stage('BNN end2end - U250') { + when { + // beforeAgent set to 'true' to prevent an offline agent hanging the stage + beforeAgent true + expression { return (env.ALVEO_HOST_ONLINE == 'true' && params['end2end'] && env.BNN_BUILD_U250 == 'SUCCESS') } + } + agent { + label 'finn-u250' + } + environment { + BOARD = 'U250' + } + steps { + catchError(stageResult: 'FAILURE') { + script { + // Clean any files from a previous run + sh "rm -rf ${env.BOARD}*" + + // Get the test files + unstash name: "${env.BOARD}_zip" + sh "unzip -o ${env.BOARD}.zip" + + dir(env.BOARD) { + // Get the scripts necessary for running hw tests + unstash name: 'bnn_test_files' + + // Create test script + createTestScript(env.BOARD, env.BOARD, "bnn_test_hw_${env.BOARD}.xml") + + // Use an env variable to help collect test results later in pipeline + env.BNN_TEST_U250 = "SUCCESS" + + // Execute the script + sh './run-tests.sh' + } + } + } + } + post { + always { + dir(env.BOARD) { + // Collect the results file on the slave node by stashing + stash name: "xml_bnn_test_${env.BOARD}", includes: "bnn_test_hw_${env.BOARD}.xml" + } + } + success { + postSuccess(env.BOARD) + } + failure { + postFailure(env.BOARD) + } + } + } + stage('BNN end2end - Pynq-Z1') { + when { + // beforeAgent set to 'true' to prevent an offline agent hanging the stage + beforeAgent true + expression { return (env.PYNQ_ONLINE == 'true' && params['end2end'] && env.BNN_BUILD_PYNQZ1 == 'SUCCESS') } + } + agent { + label 'finn-pynq' + } + environment { + BOARD = 'Pynq-Z1' + USER_CREDENTIALS = credentials('pynq-z1-credentials') + } + steps { + catchError(stageResult: 'FAILURE') { + script { + // Clean any files from a previous run + sh "echo $USER_CREDENTIALS_PSW | sudo -S rm -rf ${env.BOARD}*" + + // Get the test files + unstash name: "PynqZ1_zip" + sh "unzip -o ${env.BOARD}.zip" + + dir(env.BOARD) { + // Get the scripts necessary for running hw tests + unstash name: 'bnn_test_files' + + // Create test script + // The marker here omits the '-Z1' as '-' is a special character + // that will not work with Pytest + createTestScript(env.BOARD, 'Pynq', "bnn_test_hw_${env.BOARD}.xml") + + // Use an env variable to help collect test results later in pipeline + env.BNN_TEST_PYNQZ1 = "SUCCESS" + + // Execute the script as the root user - needed for zynq platforms + sh 'echo $USER_CREDENTIALS_PSW | sudo -S ./run-tests.sh' + } + } + } + } + post { + always { + // Get test result file and delete test files on the board + dir(env.BOARD) { + // Collect the results file on the slave node by stashing + stash name: "xml_bnn_test_PynqZ1", includes: "bnn_test_hw_${env.BOARD}.xml" + } + } + success { + postSuccess(env.BOARD) + } + failure { + postFailure(env.BOARD) + } + } + } + stage('BNN end2end - ZCU104') { + when { + // beforeAgent set to 'true' to prevent an offline agent hanging the stage + beforeAgent true + expression { return (env.ZCU104_ONLINE == 'true' && params['end2end'] && env.BNN_BUILD_ZCU104 == 'SUCCESS') } + } + agent { + label 'finn-zcu104' + } + environment { + BOARD = 'ZCU104' + USER_CREDENTIALS = credentials('pynq-z1-credentials') + } + steps { + catchError(stageResult: 'FAILURE') { + script { + // Clean any files from a previous run + sh "echo $USER_CREDENTIALS_PSW | sudo -S rm -rf ${env.BOARD}*" + + // Get the test files + unstash name: "${env.BOARD}_zip" + sh "unzip -o ${env.BOARD}.zip" + + dir(env.BOARD) { + // Get the scripts necessary for running hw tests + unstash name: 'bnn_test_files' + + // Create test script + createTestScript(env.BOARD, env.BOARD, "bnn_test_hw_${env.BOARD}.xml") + + // Use an env variable to help collect test results later in pipeline + env.BNN_TEST_ZCU104 = "SUCCESS" + + // Execute the script as the root user - needed for zynq platforms + sh 'echo $USER_CREDENTIALS_PSW | sudo -S ./run-tests.sh' + } + } + } + } + post { + always { + // Get test result file and delete test files on the board + dir(env.BOARD) { + // Collect the results file on the slave node by stashing + stash name: "xml_bnn_test_${env.BOARD}", includes: "bnn_test_hw_${env.BOARD}.xml" + } + } + success { + postSuccess(env.BOARD) + } + failure { + postFailure(env.BOARD) + } + } + } + stage('BNN end2end - KV260_SOM') { + when { + // beforeAgent set to 'true' to prevent an offline agent hanging the stage + beforeAgent true + expression { return (env.KV260_ONLINE == 'true' && params['end2end'] && env.BNN_BUILD_KV260_SOM == 'SUCCESS') } + } + agent { + label 'finn-kv260' + } + environment { + BOARD = 'KV260_SOM' + USER_CREDENTIALS = credentials('user-ubuntu-credentials') + } + steps { + catchError(stageResult: 'FAILURE') { + script { + // Clean any files from a previous run + sh "echo $USER_CREDENTIALS_PSW | sudo -S rm -rf ${env.BOARD}*" + + // Get the test files + unstash name: "${env.BOARD}_zip" + sh "unzip -o ${env.BOARD}.zip" + + dir(env.BOARD) { + // Get the scripts necessary for running hw tests + unstash name: 'bnn_test_files' + + // Create test script + createTestScript(env.BOARD, env.BOARD, "bnn_test_hw_${env.BOARD}.xml") + + // Use an env variable to help collect test results later in pipeline + env.BNN_TEST_KV260_SOM = "SUCCESS" + + // Execute the script as the root user - needed for zynq platforms + sh 'echo $USER_CREDENTIALS_PSW | sudo -S ./run-tests.sh' + } + } + } + } + post { + always { + // Get test result file and delete test files on the board + dir(env.BOARD) { + // Collect the results file on the slave node by stashing + stash name: "xml_bnn_test_${env.BOARD}", includes: "bnn_test_hw_${env.BOARD}.xml" + } + } + success { + postSuccess(env.BOARD) + } + failure { + postFailure(env.BOARD) + } + } + } + } + } stage('Check Stage Results') { agent { label 'finn-build' @@ -529,6 +753,10 @@ pipeline { unstashSuccessfulStage(env.BNN_BUILD_PYNQZ1, "bnn_build_full_PynqZ1") unstashSuccessfulStage(env.BNN_BUILD_ZCU104, "bnn_build_full_ZCU104") unstashSuccessfulStage(env.BNN_BUILD_KV260_SOM, "bnn_build_full_KV260_SOM") + unstashSuccessfulStage(env.BNN_TEST_U250, "xml_bnn_test_U250") + unstashSuccessfulStage(env.BNN_TEST_PYNQZ1, "xml_bnn_test_PynqZ1") + unstashSuccessfulStage(env.BNN_TEST_ZCU104, "xml_bnn_test_ZCU104") + unstashSuccessfulStage(env.BNN_TEST_KV260_SOM, "xml_bnn_test_KV260_SOM") // Plot what XML files were created during the test run junit '**/*.xml' From feb4b277c679c96e1528e8753e85431a336881cb Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Fri, 21 Jul 2023 16:42:33 +0100 Subject: [PATCH 220/665] Add catchError for end2end bnn build stages to allow pipeline to continue on error Signed-off-by: Fionn O'Donohoe --- docker/jenkins/Jenkinsfile | 96 +++++++++++++++++++++----------------- 1 file changed, 52 insertions(+), 44 deletions(-) diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index a117625230..1fc80a6feb 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -147,20 +147,22 @@ pipeline { FINN_HOST_BUILD_DIR = "${env.FINN_HOST_BUILD_DIR}/${env.TEST_NAME}_${env.BOARD}" } steps { - script { - // Creates dir in finn clone to store build files for stashing - sh "mkdir -p ${env.TEST_NAME}" - cleanPreviousBuildFiles(env.FINN_HOST_BUILD_DIR) + catchError(stageResult: 'FAILURE') { + script { + // Creates dir in finn clone to store build files for stashing + sh "mkdir -p ${env.TEST_NAME}" + cleanPreviousBuildFiles(env.FINN_HOST_BUILD_DIR) - // Pass in the marker to run with pytest and the XML test results filename - runDockerPytestWithMarker("bnn_u250", "${env.TEST_NAME}_${env.BOARD}.xml") - findCopyZip(env.BOARD, env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "${env.BOARD}_zip") + // Pass in the marker to run with pytest and the XML test results filename + runDockerPytestWithMarker("bnn_u250", "${env.TEST_NAME}_${env.BOARD}.xml") + findCopyZip(env.BOARD, env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "${env.BOARD}_zip") - // Stash the test results file(s) - stash name: "${env.TEST_NAME}_${env.BOARD}", includes: "${env.TEST_NAME}_${env.BOARD}.xml" + // Stash the test results file(s) + stash name: "${env.TEST_NAME}_${env.BOARD}", includes: "${env.TEST_NAME}_${env.BOARD}.xml" - // Use an env variable to help collect test results later in pipeline - env.BNN_BUILD_U250 = "SUCCESS" + // Use an env variable to help collect test results later in pipeline + env.BNN_BUILD_U250 = "SUCCESS" + } } } } @@ -177,20 +179,22 @@ pipeline { FINN_HOST_BUILD_DIR = "${env.FINN_HOST_BUILD_DIR}/${env.TEST_NAME}_${env.BOARD}" } steps { - script { - // Creates dir in finn clone to store build files for stashing - sh "mkdir -p ${env.TEST_NAME}" - cleanPreviousBuildFiles(env.FINN_HOST_BUILD_DIR) + catchError(stageResult: 'FAILURE') { + script { + // Creates dir in finn clone to store build files for stashing + sh "mkdir -p ${env.TEST_NAME}" + cleanPreviousBuildFiles(env.FINN_HOST_BUILD_DIR) - // Pass in the marker to run with pytest and the XML test results filename - runDockerPytestWithMarker("bnn_pynq", "${env.TEST_NAME}_${env.BOARD}.xml") - findCopyZip(env.BOARD, env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "PynqZ1_zip") + // Pass in the marker to run with pytest and the XML test results filename + runDockerPytestWithMarker("bnn_pynq", "${env.TEST_NAME}_${env.BOARD}.xml") + findCopyZip(env.BOARD, env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "PynqZ1_zip") - // Stash the test results file(s) - stash name: "${env.TEST_NAME}_PynqZ1", includes: "${env.TEST_NAME}_${env.BOARD}.xml" + // Stash the test results file(s) + stash name: "${env.TEST_NAME}_PynqZ1", includes: "${env.TEST_NAME}_${env.BOARD}.xml" - // Use an env variable to help collect test results later in pipeline - env.BNN_BUILD_PYNQZ1 = "SUCCESS" + // Use an env variable to help collect test results later in pipeline + env.BNN_BUILD_PYNQZ1 = "SUCCESS" + } } } } @@ -207,20 +211,22 @@ pipeline { FINN_HOST_BUILD_DIR = "${env.FINN_HOST_BUILD_DIR}/${env.TEST_NAME}_${env.BOARD}" } steps { - script { - // Creates dir in finn clone to store build files for stashing - sh "mkdir -p ${env.TEST_NAME}" - cleanPreviousBuildFiles(env.FINN_HOST_BUILD_DIR) + catchError(stageResult: 'FAILURE') { + script { + // Creates dir in finn clone to store build files for stashing + sh "mkdir -p ${env.TEST_NAME}" + cleanPreviousBuildFiles(env.FINN_HOST_BUILD_DIR) - // Pass in the marker to run with pytest and the XML test results filename - runDockerPytestWithMarker("bnn_zcu104", "${env.TEST_NAME}_${env.BOARD}.xml") - findCopyZip(env.BOARD, env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "${env.BOARD}_zip") + // Pass in the marker to run with pytest and the XML test results filename + runDockerPytestWithMarker("bnn_zcu104", "${env.TEST_NAME}_${env.BOARD}.xml") + findCopyZip(env.BOARD, env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "${env.BOARD}_zip") - // Stash the test results file(s) - stash name: "${env.TEST_NAME}_${env.BOARD}", includes: "${env.TEST_NAME}_${env.BOARD}.xml" + // Stash the test results file(s) + stash name: "${env.TEST_NAME}_${env.BOARD}", includes: "${env.TEST_NAME}_${env.BOARD}.xml" - // Use an env variable to help collect test results later in pipeline - env.BNN_BUILD_ZCU104 = "SUCCESS" + // Use an env variable to help collect test results later in pipeline + env.BNN_BUILD_ZCU104 = "SUCCESS" + } } } } @@ -237,20 +243,22 @@ pipeline { FINN_HOST_BUILD_DIR = "${env.FINN_HOST_BUILD_DIR}/${env.TEST_NAME}_${env.BOARD}" } steps { - script { - // Creates dir in finn clone to store build files for stashing - sh "mkdir -p ${env.TEST_NAME}" - cleanPreviousBuildFiles(env.FINN_HOST_BUILD_DIR) + catchError(stageResult: 'FAILURE') { + script { + // Creates dir in finn clone to store build files for stashing + sh "mkdir -p ${env.TEST_NAME}" + cleanPreviousBuildFiles(env.FINN_HOST_BUILD_DIR) - // Pass in the marker to run with pytest and the XML test results filename - runDockerPytestWithMarker("bnn_kv260", "${env.TEST_NAME}_${env.BOARD}.xml") - findCopyZip(env.BOARD, env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "${env.BOARD}_zip") + // Pass in the marker to run with pytest and the XML test results filename + runDockerPytestWithMarker("bnn_kv260", "${env.TEST_NAME}_${env.BOARD}.xml") + findCopyZip(env.BOARD, env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "${env.BOARD}_zip") - // Stash the test results file(s) - stash name: "${env.TEST_NAME}_${env.BOARD}", includes: "${env.TEST_NAME}_${env.BOARD}.xml" + // Stash the test results file(s) + stash name: "${env.TEST_NAME}_${env.BOARD}", includes: "${env.TEST_NAME}_${env.BOARD}.xml" - // Use an env variable to help collect test results later in pipeline - env.BNN_BUILD_KV260_SOM = "SUCCESS" + // Use an env variable to help collect test results later in pipeline + env.BNN_BUILD_KV260_SOM = "SUCCESS" + } } } } From 7e258a84e79980484156f29701a768d835597524 Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Fri, 21 Jul 2023 17:19:35 +0100 Subject: [PATCH 221/665] Add pytest-html library and add to all tests in Jenkinsfile. Archive the results as well Signed-off-by: Fionn O'Donohoe --- docker/Dockerfile.finn | 1 + docker/jenkins/Jenkinsfile | 76 +++++++++++++++++++------------------- 2 files changed, 39 insertions(+), 38 deletions(-) diff --git a/docker/Dockerfile.finn b/docker/Dockerfile.finn index d69ccc9725..69425df1ee 100644 --- a/docker/Dockerfile.finn +++ b/docker/Dockerfile.finn @@ -102,6 +102,7 @@ RUN pip install pandas==1.5.3 RUN pip install scikit-learn==1.2.1 RUN pip install tqdm==4.64.1 RUN pip install -e git+https://github.com/fbcotter/dataset_loading.git@0.0.4#egg=dataset_loading +RUN pip install pytest-html==3.2.0 # extra dependencies from other FINN deps # installed in Docker image to make entrypoint script go faster diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index 1fc80a6feb..d8869eeb5b 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -27,7 +27,7 @@ pipeline { cleanPreviousBuildFiles(env.FINN_HOST_BUILD_DIR) // Pass in the marker to run with pytest and the XML test results filename - runDockerPytestWithMarker("sanity_bnn", "${env.TEST_NAME}.xml") + runDockerPytestWithMarker("sanity_bnn", "${env.TEST_NAME}") // Find the board's build files (bitstreams/xclbins) and zip for use on the boards themselves findCopyZip("Pynq-Z1", env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "sanity_PynqZ1_zip") @@ -36,7 +36,7 @@ pipeline { findCopyZip("U250", env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "sanity_U250_zip") // Stash the test results file(s) - stash name: "${env.TEST_NAME}", includes: "${env.TEST_NAME}.xml" + stash name: "${env.TEST_NAME}", includes: "${env.TEST_NAME}.xml,${env.TEST_NAME}.html" // Use an env variable to help collect test results later in pipeline env.BNN_BUILD_SANITY = "SUCCESS" @@ -61,11 +61,11 @@ pipeline { cleanPreviousBuildFiles(env.FINN_HOST_BUILD_DIR) // Multiple markers with pytest needs its own script - createMultiMarkerScript("util or brevitas_export or streamline or transform or notebooks", "${env.TEST_NAME}.xml") + createMultiMarkerScript("util or brevitas_export or streamline or transform or notebooks", "${env.TEST_NAME}") sh './run-docker.sh ./run-tests.sh' // Stash the test results file(s) - stash name: env.TEST_NAME, includes: "${env.TEST_NAME}.xml" + stash name: env.TEST_NAME, includes: "${env.TEST_NAME}.xml,${env.TEST_NAME}.html" // Use an env variable to help collect test results later in pipeline env.SANITY_UT = "SUCCESS" @@ -90,10 +90,10 @@ pipeline { cleanPreviousBuildFiles(env.FINN_HOST_BUILD_DIR) // Pass in the marker to run with pytest and the XML test results filename - runDockerPytestWithMarker("fpgadataflow", "${env.TEST_NAME}.xml") + runDockerPytestWithMarker("fpgadataflow", "${env.TEST_NAME}") // Stash the test results file(s) - stash name: env.TEST_NAME, includes: "${env.TEST_NAME}.xml" + stash name: env.TEST_NAME, includes: "${env.TEST_NAME}.xml,${env.TEST_NAME}.html" // Use an env variable to help collect test results later in pipeline env.FPGADATAFLOW = "SUCCESS" @@ -123,10 +123,10 @@ pipeline { sh "rm -rf ${env.FINN_HOST_BUILD_DIR}/*" // Pass in the marker to run with pytest and the XML test results filename - runDockerPytestWithMarker(env.TEST_NAME, "${env.TEST_NAME}.xml") + runDockerPytestWithMarker(env.TEST_NAME, "${env.TEST_NAME}") // Stash the test results file(s) - stash name: env.TEST_NAME, includes: "${env.TEST_NAME}.xml" + stash name: env.TEST_NAME, includes: "${env.TEST_NAME}.xml,${env.TEST_NAME}.html" // Use an env variable to help collect test results later in pipeline env.END2END = "SUCCESS" @@ -154,11 +154,11 @@ pipeline { cleanPreviousBuildFiles(env.FINN_HOST_BUILD_DIR) // Pass in the marker to run with pytest and the XML test results filename - runDockerPytestWithMarker("bnn_u250", "${env.TEST_NAME}_${env.BOARD}.xml") + runDockerPytestWithMarker("bnn_u250", "${env.TEST_NAME}_${env.BOARD}") findCopyZip(env.BOARD, env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "${env.BOARD}_zip") // Stash the test results file(s) - stash name: "${env.TEST_NAME}_${env.BOARD}", includes: "${env.TEST_NAME}_${env.BOARD}.xml" + stash name: "${env.TEST_NAME}_${env.BOARD}", includes: "${env.TEST_NAME}_${env.BOARD}.xml,${env.TEST_NAME}_${env.BOARD}.html" // Use an env variable to help collect test results later in pipeline env.BNN_BUILD_U250 = "SUCCESS" @@ -186,11 +186,11 @@ pipeline { cleanPreviousBuildFiles(env.FINN_HOST_BUILD_DIR) // Pass in the marker to run with pytest and the XML test results filename - runDockerPytestWithMarker("bnn_pynq", "${env.TEST_NAME}_${env.BOARD}.xml") + runDockerPytestWithMarker("bnn_pynq", "${env.TEST_NAME}_${env.BOARD}") findCopyZip(env.BOARD, env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "PynqZ1_zip") // Stash the test results file(s) - stash name: "${env.TEST_NAME}_PynqZ1", includes: "${env.TEST_NAME}_${env.BOARD}.xml" + stash name: "${env.TEST_NAME}_PynqZ1", includes: "${env.TEST_NAME}_${env.BOARD}.xml,${env.TEST_NAME}_${env.BOARD}.html" // Use an env variable to help collect test results later in pipeline env.BNN_BUILD_PYNQZ1 = "SUCCESS" @@ -218,11 +218,11 @@ pipeline { cleanPreviousBuildFiles(env.FINN_HOST_BUILD_DIR) // Pass in the marker to run with pytest and the XML test results filename - runDockerPytestWithMarker("bnn_zcu104", "${env.TEST_NAME}_${env.BOARD}.xml") + runDockerPytestWithMarker("bnn_zcu104", "${env.TEST_NAME}_${env.BOARD}") findCopyZip(env.BOARD, env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "${env.BOARD}_zip") // Stash the test results file(s) - stash name: "${env.TEST_NAME}_${env.BOARD}", includes: "${env.TEST_NAME}_${env.BOARD}.xml" + stash name: "${env.TEST_NAME}_${env.BOARD}", includes: "${env.TEST_NAME}_${env.BOARD}.xml,${env.TEST_NAME}_${env.BOARD}.html" // Use an env variable to help collect test results later in pipeline env.BNN_BUILD_ZCU104 = "SUCCESS" @@ -250,11 +250,11 @@ pipeline { cleanPreviousBuildFiles(env.FINN_HOST_BUILD_DIR) // Pass in the marker to run with pytest and the XML test results filename - runDockerPytestWithMarker("bnn_kv260", "${env.TEST_NAME}_${env.BOARD}.xml") + runDockerPytestWithMarker("bnn_kv260", "${env.TEST_NAME}_${env.BOARD}") findCopyZip(env.BOARD, env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "${env.BOARD}_zip") // Stash the test results file(s) - stash name: "${env.TEST_NAME}_${env.BOARD}", includes: "${env.TEST_NAME}_${env.BOARD}.xml" + stash name: "${env.TEST_NAME}_${env.BOARD}", includes: "${env.TEST_NAME}_${env.BOARD}.xml,${env.TEST_NAME}_${env.BOARD}.html" // Use an env variable to help collect test results later in pipeline env.BNN_BUILD_KV260_SOM = "SUCCESS" @@ -315,7 +315,7 @@ pipeline { unstash name: 'bnn_test_files' // Create test script - createTestScript(env.BOARD, env.BOARD, "sanity_bnn_test_hw_${env.BOARD}.xml") + createTestScript(env.BOARD, env.BOARD, "sanity_bnn_test_hw_${env.BOARD}") // Use an env variable to help collect test results later in pipeline env.SANITY_BNN_TEST_U250 = "SUCCESS" @@ -330,7 +330,7 @@ pipeline { always { dir(env.BOARD) { // Collect the results file on the slave node by stashing - stash name: "xml_sanity_bnn_test_${env.BOARD}", includes: "sanity_bnn_test_hw_${env.BOARD}.xml" + stash name: "xml_sanity_bnn_test_${env.BOARD}", includes: "sanity_bnn_test_hw_${env.BOARD}.xml,sanity_bnn_test_hw_${env.BOARD}.html" } } success { @@ -371,7 +371,7 @@ pipeline { // Create test script // The marker here omits the '-Z1' as '-' is a special character // that will not work with Pytest - createTestScript(env.BOARD, 'Pynq', "sanity_bnn_test_hw_${env.BOARD}.xml") + createTestScript(env.BOARD, 'Pynq', "sanity_bnn_test_hw_${env.BOARD}") // Use an env variable to help collect test results later in pipeline env.SANITY_BNN_TEST_PYNQZ1 = "SUCCESS" @@ -387,7 +387,7 @@ pipeline { // Get test result file and delete test files on the board dir(env.BOARD) { // Collect the results file on the slave node by stashing - stash name: "xml_sanity_bnn_test_PynqZ1", includes: "sanity_bnn_test_hw_${env.BOARD}.xml" + stash name: "xml_sanity_bnn_test_PynqZ1", includes: "sanity_bnn_test_hw_${env.BOARD}.xml,sanity_bnn_test_hw_${env.BOARD}.html" } } success { @@ -426,7 +426,7 @@ pipeline { unstash name: 'bnn_test_files' // Create test script - createTestScript(env.BOARD, env.BOARD, "sanity_bnn_test_hw_${env.BOARD}.xml") + createTestScript(env.BOARD, env.BOARD, "sanity_bnn_test_hw_${env.BOARD}") // Use an env variable to help collect test results later in pipeline env.SANITY_BNN_TEST_ZCU104 = "SUCCESS" @@ -442,7 +442,7 @@ pipeline { // Get test result file and delete test files on the board dir(env.BOARD) { // Collect the results file on the slave node by stashing - stash name: "xml_sanity_bnn_test_${env.BOARD}", includes: "sanity_bnn_test_hw_${env.BOARD}.xml" + stash name: "xml_sanity_bnn_test_${env.BOARD}", includes: "sanity_bnn_test_hw_${env.BOARD}.xml,sanity_bnn_test_hw_${env.BOARD}.html" } } success { @@ -481,7 +481,7 @@ pipeline { unstash name: 'bnn_test_files' // Create test script - createTestScript(env.BOARD, env.BOARD, "sanity_bnn_test_hw_${env.BOARD}.xml") + createTestScript(env.BOARD, env.BOARD, "sanity_bnn_test_hw_${env.BOARD}") // Use an env variable to help collect test results later in pipeline env.SANITY_BNN_TEST_KV260_SOM = "SUCCESS" @@ -497,7 +497,7 @@ pipeline { // Get test result file and delete test files on the board dir(env.BOARD) { // Collect the results file on the slave node by stashing - stash name: "xml_sanity_bnn_test_${env.BOARD}", includes: "sanity_bnn_test_hw_${env.BOARD}.xml" + stash name: "xml_sanity_bnn_test_${env.BOARD}", includes: "sanity_bnn_test_hw_${env.BOARD}.xml,sanity_bnn_test_hw_${env.BOARD}.html" } } success { @@ -539,7 +539,7 @@ pipeline { unstash name: 'bnn_test_files' // Create test script - createTestScript(env.BOARD, env.BOARD, "bnn_test_hw_${env.BOARD}.xml") + createTestScript(env.BOARD, env.BOARD, "bnn_test_hw_${env.BOARD}") // Use an env variable to help collect test results later in pipeline env.BNN_TEST_U250 = "SUCCESS" @@ -554,7 +554,7 @@ pipeline { always { dir(env.BOARD) { // Collect the results file on the slave node by stashing - stash name: "xml_bnn_test_${env.BOARD}", includes: "bnn_test_hw_${env.BOARD}.xml" + stash name: "xml_bnn_test_${env.BOARD}", includes: "bnn_test_hw_${env.BOARD}.xml,bnn_test_hw_${env.BOARD}.html" } } success { @@ -595,7 +595,7 @@ pipeline { // Create test script // The marker here omits the '-Z1' as '-' is a special character // that will not work with Pytest - createTestScript(env.BOARD, 'Pynq', "bnn_test_hw_${env.BOARD}.xml") + createTestScript(env.BOARD, 'Pynq', "bnn_test_hw_${env.BOARD}") // Use an env variable to help collect test results later in pipeline env.BNN_TEST_PYNQZ1 = "SUCCESS" @@ -611,7 +611,7 @@ pipeline { // Get test result file and delete test files on the board dir(env.BOARD) { // Collect the results file on the slave node by stashing - stash name: "xml_bnn_test_PynqZ1", includes: "bnn_test_hw_${env.BOARD}.xml" + stash name: "xml_bnn_test_PynqZ1", includes: "bnn_test_hw_${env.BOARD}.xml,bnn_test_hw_${env.BOARD}.html" } } success { @@ -650,7 +650,7 @@ pipeline { unstash name: 'bnn_test_files' // Create test script - createTestScript(env.BOARD, env.BOARD, "bnn_test_hw_${env.BOARD}.xml") + createTestScript(env.BOARD, env.BOARD, "bnn_test_hw_${env.BOARD}") // Use an env variable to help collect test results later in pipeline env.BNN_TEST_ZCU104 = "SUCCESS" @@ -666,7 +666,7 @@ pipeline { // Get test result file and delete test files on the board dir(env.BOARD) { // Collect the results file on the slave node by stashing - stash name: "xml_bnn_test_${env.BOARD}", includes: "bnn_test_hw_${env.BOARD}.xml" + stash name: "xml_bnn_test_${env.BOARD}", includes: "bnn_test_hw_${env.BOARD}.xml,bnn_test_hw_${env.BOARD}.html" } } success { @@ -705,7 +705,7 @@ pipeline { unstash name: 'bnn_test_files' // Create test script - createTestScript(env.BOARD, env.BOARD, "bnn_test_hw_${env.BOARD}.xml") + createTestScript(env.BOARD, env.BOARD, "bnn_test_hw_${env.BOARD}") // Use an env variable to help collect test results later in pipeline env.BNN_TEST_KV260_SOM = "SUCCESS" @@ -721,7 +721,7 @@ pipeline { // Get test result file and delete test files on the board dir(env.BOARD) { // Collect the results file on the slave node by stashing - stash name: "xml_bnn_test_${env.BOARD}", includes: "bnn_test_hw_${env.BOARD}.xml" + stash name: "xml_bnn_test_${env.BOARD}", includes: "bnn_test_hw_${env.BOARD}.xml,bnn_test_hw_${env.BOARD}.html" } } success { @@ -769,8 +769,8 @@ pipeline { // Plot what XML files were created during the test run junit '**/*.xml' - // Archive the XML test results - archiveArtifacts artifacts: "*.xml" + // Archive the XML & HTML test results + archiveArtifacts artifacts: "*.xml *.html" } } } @@ -788,7 +788,7 @@ void createMultiMarkerScript(String markers, String testResultsFilename) { // Passing multiple markers when running ./run-docker.sh does not work with bash. // Therefore, create a script to maintain the single quotes that surround the markers sh """echo "#!/bin/bash -python -m pytest -m \'${markers}\' --junitxml=${testResultsFilename}" >> run-tests.sh +python -m pytest -m \'${markers}\' --junitxml=${testResultsFilename}.xml --html=${testResultsFilename}.html --self-contained-html" >> run-tests.sh """ // Give permissions to script @@ -796,7 +796,7 @@ python -m pytest -m \'${markers}\' --junitxml=${testResultsFilename}" >> run-tes } void runDockerPytestWithMarker(String marker, String testResultsFilename) { - sh """./run-docker.sh python -m pytest -m ${marker} --junitxml=${testResultsFilename}""" + sh """./run-docker.sh python -m pytest -m ${marker} --junitxml=${testResultsFilename}.xml --html=${testResultsFilename}.html --self-contained-html""" } void findBoardBuildFiles(String board, String searchDir, String dirToFind) { @@ -822,14 +822,14 @@ void createTestScript(String board, String marker, String testResultsFilename) { . /opt/xilinx/xrt/setup.sh . ${CONDA_ENV_ACTIVATE} python hack_driver_script.py -python -m pytest -m ${marker} --junitxml=${testResultsFilename}" >> run-tests.sh +python -m pytest -m ${marker} --junitxml=${testResultsFilename}.xml --html=${testResultsFilename}.html --self-contained-html" >> run-tests.sh """ else sh """echo "#!/bin/bash . /etc/profile.d/pynq_venv.sh . /etc/profile.d/xrt_setup.sh python hack_driver_script.py -python -m pytest -m ${marker} --junitxml=${testResultsFilename}" >> run-tests.sh +python -m pytest -m ${marker} --junitxml=${testResultsFilename}.xml --html=${testResultsFilename}.html --self-contained-html" >> run-tests.sh """ // Give permissions to script From 6b5e7680781fde8fbbcd7a529cbf1ca6c52f1b58 Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Fri, 21 Jul 2023 17:39:59 +0100 Subject: [PATCH 222/665] Add pytest-html-merger library to combine individual HTML files created in the jenkins pipeline Signed-off-by: Fionn O'Donohoe --- docker/Dockerfile.finn | 1 + docker/jenkins/Jenkinsfile | 50 ++++++++++++++++++++++---------------- 2 files changed, 30 insertions(+), 21 deletions(-) diff --git a/docker/Dockerfile.finn b/docker/Dockerfile.finn index 69425df1ee..91a22952ff 100644 --- a/docker/Dockerfile.finn +++ b/docker/Dockerfile.finn @@ -103,6 +103,7 @@ RUN pip install scikit-learn==1.2.1 RUN pip install tqdm==4.64.1 RUN pip install -e git+https://github.com/fbcotter/dataset_loading.git@0.0.4#egg=dataset_loading RUN pip install pytest-html==3.2.0 +RUN pip install pytest-html-merger==0.0.8 # extra dependencies from other FINN deps # installed in Docker image to make entrypoint script go faster diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index d8869eeb5b..f782569643 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -748,29 +748,37 @@ pipeline { post { always { script { - // Only unstash for stages that ran - unstashSuccessfulStage(env.SANITY_UT, "sanity_ut") - unstashSuccessfulStage(env.FPGADATAFLOW, "fpgadataflow") - unstashSuccessfulStage(env.BNN_BUILD_SANITY, "bnn_build_sanity") - unstashSuccessfulStage(env.SANITY_BNN_TEST_U250, "xml_sanity_bnn_test_U250") - unstashSuccessfulStage(env.SANITY_BNN_TEST_PYNQZ1, "xml_sanity_bnn_test_PynqZ1") - unstashSuccessfulStage(env.SANITY_BNN_TEST_ZCU104, "xml_sanity_bnn_test_ZCU104") - unstashSuccessfulStage(env.SANITY_BNN_TEST_KV260_SOM, "xml_sanity_bnn_test_KV260_SOM") - unstashSuccessfulStage(env.END2END, "end2end") - unstashSuccessfulStage(env.BNN_BUILD_U250, "bnn_build_full_U250") - unstashSuccessfulStage(env.BNN_BUILD_PYNQZ1, "bnn_build_full_PynqZ1") - unstashSuccessfulStage(env.BNN_BUILD_ZCU104, "bnn_build_full_ZCU104") - unstashSuccessfulStage(env.BNN_BUILD_KV260_SOM, "bnn_build_full_KV260_SOM") - unstashSuccessfulStage(env.BNN_TEST_U250, "xml_bnn_test_U250") - unstashSuccessfulStage(env.BNN_TEST_PYNQZ1, "xml_bnn_test_PynqZ1") - unstashSuccessfulStage(env.BNN_TEST_ZCU104, "xml_bnn_test_ZCU104") - unstashSuccessfulStage(env.BNN_TEST_KV260_SOM, "xml_bnn_test_KV260_SOM") - - // Plot what XML files were created during the test run - junit '**/*.xml' + sh 'mkdir -p reports' + cleanPreviousBuildFiles('reports') + dir('reports') { + // Only unstash for stages that ran + unstashSuccessfulStage(env.SANITY_UT, "sanity_ut") + unstashSuccessfulStage(env.FPGADATAFLOW, "fpgadataflow") + unstashSuccessfulStage(env.BNN_BUILD_SANITY, "bnn_build_sanity") + unstashSuccessfulStage(env.SANITY_BNN_TEST_U250, "xml_sanity_bnn_test_U250") + unstashSuccessfulStage(env.SANITY_BNN_TEST_PYNQZ1, "xml_sanity_bnn_test_PynqZ1") + unstashSuccessfulStage(env.SANITY_BNN_TEST_ZCU104, "xml_sanity_bnn_test_ZCU104") + unstashSuccessfulStage(env.SANITY_BNN_TEST_KV260_SOM, "xml_sanity_bnn_test_KV260_SOM") + unstashSuccessfulStage(env.END2END, "end2end") + unstashSuccessfulStage(env.BNN_BUILD_U250, "bnn_build_full_U250") + unstashSuccessfulStage(env.BNN_BUILD_PYNQZ1, "bnn_build_full_PynqZ1") + unstashSuccessfulStage(env.BNN_BUILD_ZCU104, "bnn_build_full_ZCU104") + unstashSuccessfulStage(env.BNN_BUILD_KV260_SOM, "bnn_build_full_KV260_SOM") + unstashSuccessfulStage(env.BNN_TEST_U250, "xml_bnn_test_U250") + unstashSuccessfulStage(env.BNN_TEST_PYNQZ1, "xml_bnn_test_PynqZ1") + unstashSuccessfulStage(env.BNN_TEST_ZCU104, "xml_bnn_test_ZCU104") + unstashSuccessfulStage(env.BNN_TEST_KV260_SOM, "xml_bnn_test_KV260_SOM") + } + + // Combine individual HTML files to one single report + sh './run-docker.sh pytest_html_merger -i reports/ -o reports/test_report_final.html' // Archive the XML & HTML test results - archiveArtifacts artifacts: "*.xml *.html" + archiveArtifacts artifacts: "reports/*.xml" + archiveArtifacts artifacts: "reports/*.html" + + // Plot what XML files were created during the test run + junit 'reports/*.xml' } } } From fb9218e15b8ad0b8bacf4af610c5df1fb50e52c0 Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Fri, 21 Jul 2023 17:56:08 +0100 Subject: [PATCH 223/665] Add code coverage for sanity unit tests and for fpgadataflow tests. Archive the results Signed-off-by: Fionn O'Donohoe --- docker/Dockerfile.finn | 1 + docker/jenkins/Jenkinsfile | 31 ++++++++++++++++++++----------- 2 files changed, 21 insertions(+), 11 deletions(-) diff --git a/docker/Dockerfile.finn b/docker/Dockerfile.finn index 91a22952ff..e11e8136fd 100644 --- a/docker/Dockerfile.finn +++ b/docker/Dockerfile.finn @@ -104,6 +104,7 @@ RUN pip install tqdm==4.64.1 RUN pip install -e git+https://github.com/fbcotter/dataset_loading.git@0.0.4#egg=dataset_loading RUN pip install pytest-html==3.2.0 RUN pip install pytest-html-merger==0.0.8 +RUN pip install pytest-cov==4.1.0 # extra dependencies from other FINN deps # installed in Docker image to make entrypoint script go faster diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index f782569643..b7998ae5b9 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -27,7 +27,7 @@ pipeline { cleanPreviousBuildFiles(env.FINN_HOST_BUILD_DIR) // Pass in the marker to run with pytest and the XML test results filename - runDockerPytestWithMarker("sanity_bnn", "${env.TEST_NAME}") + runDockerPytestWithMarker("sanity_bnn", "${env.TEST_NAME}", '') // Find the board's build files (bitstreams/xclbins) and zip for use on the boards themselves findCopyZip("Pynq-Z1", env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "sanity_PynqZ1_zip") @@ -61,7 +61,7 @@ pipeline { cleanPreviousBuildFiles(env.FINN_HOST_BUILD_DIR) // Multiple markers with pytest needs its own script - createMultiMarkerScript("util or brevitas_export or streamline or transform or notebooks", "${env.TEST_NAME}") + createMultiMarkerScript("util or brevitas_export or streamline or transform or notebooks", "${env.TEST_NAME}", "--cov --cov-report=html:coverage_sanity_ut") sh './run-docker.sh ./run-tests.sh' // Stash the test results file(s) @@ -90,7 +90,7 @@ pipeline { cleanPreviousBuildFiles(env.FINN_HOST_BUILD_DIR) // Pass in the marker to run with pytest and the XML test results filename - runDockerPytestWithMarker("fpgadataflow", "${env.TEST_NAME}") + runDockerPytestWithMarker("fpgadataflow", "${env.TEST_NAME}", "--cov --cov-report=html:coverage_fpgadataflow") // Stash the test results file(s) stash name: env.TEST_NAME, includes: "${env.TEST_NAME}.xml,${env.TEST_NAME}.html" @@ -123,7 +123,7 @@ pipeline { sh "rm -rf ${env.FINN_HOST_BUILD_DIR}/*" // Pass in the marker to run with pytest and the XML test results filename - runDockerPytestWithMarker(env.TEST_NAME, "${env.TEST_NAME}") + runDockerPytestWithMarker(env.TEST_NAME, "${env.TEST_NAME}", '') // Stash the test results file(s) stash name: env.TEST_NAME, includes: "${env.TEST_NAME}.xml,${env.TEST_NAME}.html" @@ -154,7 +154,7 @@ pipeline { cleanPreviousBuildFiles(env.FINN_HOST_BUILD_DIR) // Pass in the marker to run with pytest and the XML test results filename - runDockerPytestWithMarker("bnn_u250", "${env.TEST_NAME}_${env.BOARD}") + runDockerPytestWithMarker("bnn_u250", "${env.TEST_NAME}_${env.BOARD}", '') findCopyZip(env.BOARD, env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "${env.BOARD}_zip") // Stash the test results file(s) @@ -186,7 +186,7 @@ pipeline { cleanPreviousBuildFiles(env.FINN_HOST_BUILD_DIR) // Pass in the marker to run with pytest and the XML test results filename - runDockerPytestWithMarker("bnn_pynq", "${env.TEST_NAME}_${env.BOARD}") + runDockerPytestWithMarker("bnn_pynq", "${env.TEST_NAME}_${env.BOARD}", '') findCopyZip(env.BOARD, env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "PynqZ1_zip") // Stash the test results file(s) @@ -218,7 +218,7 @@ pipeline { cleanPreviousBuildFiles(env.FINN_HOST_BUILD_DIR) // Pass in the marker to run with pytest and the XML test results filename - runDockerPytestWithMarker("bnn_zcu104", "${env.TEST_NAME}_${env.BOARD}") + runDockerPytestWithMarker("bnn_zcu104", "${env.TEST_NAME}_${env.BOARD}", '') findCopyZip(env.BOARD, env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "${env.BOARD}_zip") // Stash the test results file(s) @@ -250,7 +250,7 @@ pipeline { cleanPreviousBuildFiles(env.FINN_HOST_BUILD_DIR) // Pass in the marker to run with pytest and the XML test results filename - runDockerPytestWithMarker("bnn_kv260", "${env.TEST_NAME}_${env.BOARD}") + runDockerPytestWithMarker("bnn_kv260", "${env.TEST_NAME}_${env.BOARD}", '') findCopyZip(env.BOARD, env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "${env.BOARD}_zip") // Stash the test results file(s) @@ -777,6 +777,9 @@ pipeline { archiveArtifacts artifacts: "reports/*.xml" archiveArtifacts artifacts: "reports/*.html" + archiveSuccessfulStage(env.SANITY_UT, "coverage_sanity_ut") + archiveSuccessfulStage(env.FPGADATAFLOW, "coverage_fpgadataflow") + // Plot what XML files were created during the test run junit 'reports/*.xml' } @@ -796,15 +799,15 @@ void createMultiMarkerScript(String markers, String testResultsFilename) { // Passing multiple markers when running ./run-docker.sh does not work with bash. // Therefore, create a script to maintain the single quotes that surround the markers sh """echo "#!/bin/bash -python -m pytest -m \'${markers}\' --junitxml=${testResultsFilename}.xml --html=${testResultsFilename}.html --self-contained-html" >> run-tests.sh +python -m pytest -m \'${markers}\' --junitxml=${testResultsFilename}.xml --html=${testResultsFilename}.html --self-contained-html ${additionalOptions}" >> run-tests.sh """ // Give permissions to script sh 'chmod 777 run-tests.sh' } -void runDockerPytestWithMarker(String marker, String testResultsFilename) { - sh """./run-docker.sh python -m pytest -m ${marker} --junitxml=${testResultsFilename}.xml --html=${testResultsFilename}.html --self-contained-html""" +void runDockerPytestWithMarker(String marker, String testResultsFilename, String additionalOptions) { + sh """./run-docker.sh python -m pytest -m ${marker} --junitxml=${testResultsFilename}.xml --html=${testResultsFilename}.html --self-contained-html ${additionalOptions}""" } void findBoardBuildFiles(String board, String searchDir, String dirToFind) { @@ -896,6 +899,12 @@ void unstashSuccessfulStage(String stageEnvVariableSet, String stashName) { } } +void archiveSuccessfulStage(String stageEnvVariableSet, String folder) { + if (stageEnvVariableSet) { + archiveArtifacts artifacts: "${folder}/**/*" + } +} + void postFailure(String board) { echo "Failed to run ${board} tests" } From c28e8f026d64b871dc4cedf349b4f990b5ddc4df Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Tue, 25 Jul 2023 13:09:15 +0100 Subject: [PATCH 224/665] Forgot to add additionalOptions as a function input Signed-off-by: Fionn O'Donohoe --- docker/jenkins/Jenkinsfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index b7998ae5b9..98baad74ec 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -795,7 +795,7 @@ void cleanPreviousBuildFiles(String buildDir) { sh "rm -rf ${buildDir}/*" } -void createMultiMarkerScript(String markers, String testResultsFilename) { +void createMultiMarkerScript(String markers, String testResultsFilename, String additionalOptions) { // Passing multiple markers when running ./run-docker.sh does not work with bash. // Therefore, create a script to maintain the single quotes that surround the markers sh """echo "#!/bin/bash From 0a2b850da0b957db687615565de8f44f98ef4718 Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Tue, 25 Jul 2023 13:18:09 +0100 Subject: [PATCH 225/665] Remove postFailure() and postSuccess() functions. This is an attempt to reduce the method count used in the pipeline as the current size causes the "groovyjarjarasm.asm.MethodTooLargeException: Method too large" error. As a result the pipeline does not run at all. This is a well known limitation. Removing unneccessary functions shrinks the method count and allows the Jenkinsfile to run. Signed-off-by: Fionn O'Donohoe --- docker/jenkins/Jenkinsfile | 56 -------------------------------------- 1 file changed, 56 deletions(-) diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index 98baad74ec..1ab8e81f46 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -333,12 +333,6 @@ pipeline { stash name: "xml_sanity_bnn_test_${env.BOARD}", includes: "sanity_bnn_test_hw_${env.BOARD}.xml,sanity_bnn_test_hw_${env.BOARD}.html" } } - success { - postSuccess(env.BOARD) - } - failure { - postFailure(env.BOARD) - } } } stage('BNN Sanity - Pynq-Z1') { @@ -390,12 +384,6 @@ pipeline { stash name: "xml_sanity_bnn_test_PynqZ1", includes: "sanity_bnn_test_hw_${env.BOARD}.xml,sanity_bnn_test_hw_${env.BOARD}.html" } } - success { - postSuccess(env.BOARD) - } - failure { - postFailure(env.BOARD) - } } } stage('BNN Sanity - ZCU104') { @@ -445,12 +433,6 @@ pipeline { stash name: "xml_sanity_bnn_test_${env.BOARD}", includes: "sanity_bnn_test_hw_${env.BOARD}.xml,sanity_bnn_test_hw_${env.BOARD}.html" } } - success { - postSuccess(env.BOARD) - } - failure { - postFailure(env.BOARD) - } } } stage('BNN Sanity - KV260_SOM') { @@ -500,12 +482,6 @@ pipeline { stash name: "xml_sanity_bnn_test_${env.BOARD}", includes: "sanity_bnn_test_hw_${env.BOARD}.xml,sanity_bnn_test_hw_${env.BOARD}.html" } } - success { - postSuccess(env.BOARD) - } - failure { - postFailure(env.BOARD) - } } } } @@ -557,12 +533,6 @@ pipeline { stash name: "xml_bnn_test_${env.BOARD}", includes: "bnn_test_hw_${env.BOARD}.xml,bnn_test_hw_${env.BOARD}.html" } } - success { - postSuccess(env.BOARD) - } - failure { - postFailure(env.BOARD) - } } } stage('BNN end2end - Pynq-Z1') { @@ -614,12 +584,6 @@ pipeline { stash name: "xml_bnn_test_PynqZ1", includes: "bnn_test_hw_${env.BOARD}.xml,bnn_test_hw_${env.BOARD}.html" } } - success { - postSuccess(env.BOARD) - } - failure { - postFailure(env.BOARD) - } } } stage('BNN end2end - ZCU104') { @@ -669,12 +633,6 @@ pipeline { stash name: "xml_bnn_test_${env.BOARD}", includes: "bnn_test_hw_${env.BOARD}.xml,bnn_test_hw_${env.BOARD}.html" } } - success { - postSuccess(env.BOARD) - } - failure { - postFailure(env.BOARD) - } } } stage('BNN end2end - KV260_SOM') { @@ -724,12 +682,6 @@ pipeline { stash name: "xml_bnn_test_${env.BOARD}", includes: "bnn_test_hw_${env.BOARD}.xml,bnn_test_hw_${env.BOARD}.html" } } - success { - postSuccess(env.BOARD) - } - failure { - postFailure(env.BOARD) - } } } } @@ -904,11 +856,3 @@ void archiveSuccessfulStage(String stageEnvVariableSet, String folder) { archiveArtifacts artifacts: "${folder}/**/*" } } - -void postFailure(String board) { - echo "Failed to run ${board} tests" -} - -void postSuccess(String board) { - echo "${board} tests passed" -} From 61cba651c155c258fe5a529a2be5d2b3fdf2d3d0 Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Wed, 26 Jul 2023 15:46:15 +0100 Subject: [PATCH 226/665] Remove driver hack from BNN testing Signed-off-by: Fionn O'Donohoe --- docker/jenkins/Jenkinsfile | 4 +-- docker/jenkins/hack_driver_script.py | 49 ---------------------------- 2 files changed, 1 insertion(+), 52 deletions(-) delete mode 100755 docker/jenkins/hack_driver_script.py diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index 2f7eab1190..c19cb97dec 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -119,7 +119,7 @@ pipeline { // Stash the HW test scripts to be used on slave nodes dir('docker/jenkins') { - stash name: 'bnn_test_files', includes: 'hack_driver_script.py,test_bnn_hw_pytest.py' + stash name: 'bnn_test_files', includes: 'test_bnn_hw_pytest.py' } } } @@ -426,14 +426,12 @@ void createTestScript(String board, String marker, String testResultsFilename) { sh """echo "#!/bin/bash . /opt/xilinx/xrt/setup.sh . ${CONDA_ENV_ACTIVATE} -python hack_driver_script.py python -m pytest -m ${marker} --junitxml=${testResultsFilename}" >> run-tests.sh """ else sh """echo "#!/bin/bash . /etc/profile.d/pynq_venv.sh . /etc/profile.d/xrt_setup.sh -python hack_driver_script.py python -m pytest -m ${marker} --junitxml=${testResultsFilename}" >> run-tests.sh """ diff --git a/docker/jenkins/hack_driver_script.py b/docker/jenkins/hack_driver_script.py deleted file mode 100755 index 568c62150d..0000000000 --- a/docker/jenkins/hack_driver_script.py +++ /dev/null @@ -1,49 +0,0 @@ -import os - -def remove_cache_dirs(dir_list): - tmp_list = list(dir_list) - for i in range(len(tmp_list)-1, -1, -1): - if ".pytest_cache" in tmp_list[i]: - del tmp_list[i] - elif "__pycache__" in tmp_list[i]: - del tmp_list[i] - return tmp_list - -def hack_driver_script(board, test_dir): - test_script_file = "driver.py" - # Read the contents of the test script file - with open(test_script_file, "r") as f: - lines = f.readlines() - - # Specify the line to be replaced and the new line - line_to_replace = "ishape_normal" - if "cnv" in test_dir: - new_line = " \"ishape_normal\" : [(1, 3, 32, 32)]," - else: - new_line = " \"ishape_normal\" : [(1, 1, 28, 28)]," - - # Iterate over the lines and replace the specified line - for i in range(len(lines)): - if line_to_replace in lines[i]: - lines[i] = new_line + "\n" - break # Only replace the first occurrence - - # Write the modified contents back to the test script file - with open(test_script_file, "w") as f: - f.writelines(lines) - -if __name__ == "__main__": - current_dir = os.getcwd() - board = os.path.basename(current_dir) - - # Get list of local directories - removing the Python cache directories - local_dirs = [name for name in os.listdir(current_dir) if os.path.isdir(os.path.join(current_dir, name))] - local_dirs = remove_cache_dirs(local_dirs) - - # Now create the full paths for each relative path - local_dirs_full_path = [os.path.join(current_dir, name) for name in local_dirs if os.path.isdir(os.path.join(current_dir, name))] - - # Change the driver.py script for each of the test directories - for dir in local_dirs_full_path: - os.chdir(dir) - hack_driver_script(board, dir) From 10d34b5fea8904f949c4ddab98cd5c0a1321fa10 Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Wed, 26 Jul 2023 15:49:32 +0100 Subject: [PATCH 227/665] Add input tensor data reshaping and transposing for BNN networks Signed-off-by: Fionn O'Donohoe --- tests/end2end/test_end2end_bnn_pynq.py | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index 6b288bd382..59fbb0c1cb 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -321,7 +321,22 @@ def deploy_based_on_board(model, model_title, topology, wbits, abits, board): (input_tensor_npy, output_tensor_npy) = get_golden_io_pair( topology, wbits, abits, return_topk=1 ) - np.save(os.path.join(deployment_dir, "input.npy"), input_tensor_npy) + + # Some changes are required in order to prepare the input tensor data for hardware + # testing. The ONNX graphs for these models contain nodes that manipulate the input + # tensor shape which FINN considers when creating the model. The same input tensor + # shaping needs to be done here on the input data. + # For the convolutional models, the graph contains the Transpose node. The Brevitas + # model works in NCHW layout but the FINN kernels are optimized for NHWC. + # The FC models contain a Reshape node, which FINN uses, so we therefore have to + # reshape the input tensor data to match the reshaping in the model + if topology == "cnv": + input_tensor_npy = input_tensor_npy.transpose(0, 3, 2, 1) + else: + input_shape = input_tensor_npy.shape + input_tensor_npy = (input_shape[0], np.prod(input_shape[1:])) + + np.save(os.path.join(deployment_dir, "input.npy"), input_tensor_npy.copy()) np.save(os.path.join(deployment_dir, "output_reference.npy"), output_tensor_npy) # driver.py and python libraries From 363a0874b6ab42e746f7cb89d36fcebf485a4a03 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 26 Jul 2023 18:22:16 +0100 Subject: [PATCH 228/665] [Deps] Update omx version --- fetch-repos.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fetch-repos.sh b/fetch-repos.sh index 49d8621bb9..9e3ee3ef99 100755 --- a/fetch-repos.sh +++ b/fetch-repos.sh @@ -33,7 +33,7 @@ BREVITAS_COMMIT="9bb26bf2798de210a267d1e4aed4c20087e0e8a5" PYVERILATOR_COMMIT="766e457465f5c0dd315490d7b9cc5d74f9a76f4f" CNPY_COMMIT="4e8810b1a8637695171ed346ce68f6984e585ef4" HLSLIB_COMMIT="c17aa478ae574971d115afa9fa4d9c215857d1ac" -OMX_COMMIT="d1065a788219ca0eb54d5e57600b1f9d7f67d4cc" +OMX_COMMIT="0b59762f9e4c4f7e5aa535ee9bc29f292434ca7a" AVNET_BDF_COMMIT="2d49cfc25766f07792c0b314489f21fe916b639b" XIL_BDF_COMMIT="8cf4bb674a919ac34e3d99d8d71a9e60af93d14e" KV260_BDF_COMMIT="98e0d3efc901f0b974006bc4370c2a7ad8856c79" From fe0915258bc9278a7d83ddbe27fc811ce604ae67 Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Fri, 28 Jul 2023 15:10:26 +0100 Subject: [PATCH 229/665] Add markers for BNN test suites to quiesce warnings when running pytest Signed-off-by: Fionn O'Donohoe --- setup.cfg | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/setup.cfg b/setup.cfg index fb070a436e..a70eaeb2f3 100644 --- a/setup.cfg +++ b/setup.cfg @@ -130,6 +130,11 @@ markers = fpgadataflow: mark tests related to hls layers end2end: mark tests that run the end2end flow notebooks: mark tests that execute all Jupyter notebooks + sanity_bnn: mark tests that execute the sanity BNN test + bnn_u250: mark tests that execute U250 BNN tests + bnn_kv260: mark tests that execute KV260 BNN tests + bnn_pynq: mark tests that execute Pynq-Z1 BNN tests + bnn_zcu104: mark tests that execute ZCU104 BNN tests norecursedirs = dist build From d7370db4fcde4cfb41af7a34e2494a7482fee6af Mon Sep 17 00:00:00 2001 From: Fionn O'Donohoe Date: Fri, 28 Jul 2023 15:49:12 +0100 Subject: [PATCH 230/665] Add pytest library version and associates plugins for HTML report capturing Newer version of pytest caused an issue when gathering HTML reports: ModuleNotFoundError: No module named 'py.xml'; 'py' is not a package Apparently this is not a pytest bug but due to a related plugin and is caused by depending on the py package but not declaring it as a dependency. The exact versions of the libraries specified in this commit allow for HTML report gathering. This was tested in docker and on hardware in 2 virtual environments: virtual_env and conda (zynq and alveo environments respectively) Signed-off-by: Fionn O'Donohoe --- docker/Dockerfile.finn | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/docker/Dockerfile.finn b/docker/Dockerfile.finn index e11e8136fd..06dc109808 100644 --- a/docker/Dockerfile.finn +++ b/docker/Dockerfile.finn @@ -102,7 +102,11 @@ RUN pip install pandas==1.5.3 RUN pip install scikit-learn==1.2.1 RUN pip install tqdm==4.64.1 RUN pip install -e git+https://github.com/fbcotter/dataset_loading.git@0.0.4#egg=dataset_loading -RUN pip install pytest-html==3.2.0 +# these versions of pytest and associated plugins allow for stable collection of +# test reports and code coverage reports in HTML +RUN pip install pytest==6.2.5 +RUN pip install pytest-metadata==1.7.0 +RUN pip install pytest-html==3.0.0 RUN pip install pytest-html-merger==0.0.8 RUN pip install pytest-cov==4.1.0 From 5615d8d3b89f1b11d90cc3225a2703d7e2f3e8e9 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Mon, 31 Jul 2023 12:25:17 +0100 Subject: [PATCH 231/665] [custom op]: set output datatype MVAU given no activation function --- src/finn/custom_op/fpgadataflow/matrixvectoractivation.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index 204a41e21c..b125745708 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -664,6 +664,8 @@ def minimize_accumulator_width(self, model): # for no-activation nodes, output dt = acc dt self.set_nodeattr("outputDataType", adt.name) self.set_nodeattr("accDataType", adt.name) + if self.get_nodeattr("noActivation"): + self.set_nodeattr("outputDataType", adt.name) return DataType[self.get_nodeattr("accDataType")] def minimize_weight_bit_width(self, model): From 153c2d4e8f15bfab81d6dca4261fee72739419b8 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Mon, 31 Jul 2023 12:25:43 +0100 Subject: [PATCH 232/665] [custom op]: update tensor datatype for consistency --- src/finn/custom_op/fpgadataflow/thresholding_batch.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/finn/custom_op/fpgadataflow/thresholding_batch.py b/src/finn/custom_op/fpgadataflow/thresholding_batch.py index 3bcc5c05cf..72ee2f7af6 100644 --- a/src/finn/custom_op/fpgadataflow/thresholding_batch.py +++ b/src/finn/custom_op/fpgadataflow/thresholding_batch.py @@ -211,6 +211,8 @@ def minimize_accumulator_width(self, model): threshold_tensor ).all(), "Thresholds can't be expressed with type %s" % str(tdt) self.set_nodeattr("weightDataType", tdt.name) + # Update QONNX DataType of tensor for consistency + model.set_tensor_datatype(self.onnx_node.input[1], tdt) return DataType[self.get_nodeattr("weightDataType")] def get_instream_width(self, ind=0): From f367a5aa3f2fc1bafe17ae5982057830964dffc0 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Mon, 31 Jul 2023 12:26:32 +0100 Subject: [PATCH 233/665] [minimize acc width]: apply InferDataTypes to propagate changes in each loop iteration --- .../fpgadataflow/minimize_accumulator_width.py | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/finn/transformation/fpgadataflow/minimize_accumulator_width.py b/src/finn/transformation/fpgadataflow/minimize_accumulator_width.py index bc020ca428..8d04d5b817 100644 --- a/src/finn/transformation/fpgadataflow/minimize_accumulator_width.py +++ b/src/finn/transformation/fpgadataflow/minimize_accumulator_width.py @@ -28,6 +28,7 @@ from qonnx.custom_op.registry import getCustomOp from qonnx.transformation.base import Transformation +from qonnx.transformation.infer_datatypes import InferDataTypes from finn.util.fpgadataflow import is_fpgadataflow_node @@ -41,9 +42,15 @@ def __init__(self): super().__init__() def apply(self, model): - for node in model.graph.node: + for node_id in range(len(model.graph.node)): + # Since InferDataTypes potentially changes node attributes in each loop iterations, + # the for-loop cannot loop over a list of a snapshot of the graph's node protos + node = model.graph.node[node_id] if is_fpgadataflow_node(node) is True: inst = getCustomOp(node) if hasattr(inst, "minimize_accumulator_width"): inst.minimize_accumulator_width(model) + # Since this transformation is applied iteratively, we have to ensure that + # we propagate the new datatype to other layers + model = model.transform(InferDataTypes()) return (model, False) From 763fa48bbef716c1ff15cdb2423c073d2aa52aef Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Mon, 31 Jul 2023 17:57:57 +0100 Subject: [PATCH 234/665] [custom op]: set outputDataType in case of no activation --- src/finn/custom_op/fpgadataflow/vectorvectoractivation.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index f817751852..9a9c6714fe 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -190,6 +190,8 @@ def minimize_accumulator_width(self, model): adt = DataType[new_adt_name] # for no-activation nodes, output dt = acc dt self.set_nodeattr("outputDataType", adt.name) + if self.get_nodeattr("noActivation"): + self.set_nodeattr("outputDataType", adt.name) self.set_nodeattr("accDataType", adt.name) return DataType[self.get_nodeattr("accDataType")] From 04fd18e3ebe2e3240474f5208258e2fd8ea48dc8 Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 1 Aug 2023 10:50:58 +0100 Subject: [PATCH 235/665] [CustomOp] Remove outdated stream depth pragma from decoupled mode --- src/finn/custom_op/fpgadataflow/matrixvectoractivation.py | 3 --- src/finn/custom_op/fpgadataflow/vectorvectoractivation.py | 3 --- 2 files changed, 6 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index 204a41e21c..7c180534b1 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -1274,9 +1274,6 @@ def pragmas(self): self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE axis port=weights_" + self.hls_sname() ) - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS stream depth=8 variable=weights_" + self.hls_sname() - ) else: raise Exception( diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index f817751852..58a85b29ee 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -979,9 +979,6 @@ def pragmas(self): self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE axis port=weights_" + self.hls_sname() ) - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS stream depth=8 variable=weights_" + self.hls_sname() - ) else: raise Exception( """Please set mem_mode to "const", "decoupled", or external, From 2c929b959ab1e5696a4d982bf6f35a40d72a61eb Mon Sep 17 00:00:00 2001 From: Felix Jentzsch Date: Tue, 1 Aug 2023 19:33:49 +0200 Subject: [PATCH 236/665] Fix verilator_fifosim for RTL SWG component --- src/finn/util/pyverilator.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/finn/util/pyverilator.py b/src/finn/util/pyverilator.py index 86cf2eed14..73c8755bfb 100644 --- a/src/finn/util/pyverilator.py +++ b/src/finn/util/pyverilator.py @@ -188,7 +188,8 @@ def verilator_fifosim(model, n_inputs, max_iters=100000000): xpm_memory = f"{vivado_path}/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" xpm_cdc = f"{vivado_path}/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" xpm_fifo = f"{vivado_path}/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" - verilog_file_arg = ["finn_design_wrapper.v", xpm_memory, xpm_cdc, xpm_fifo] + swg_pkg = os.environ["FINN_ROOT"] + "/finn-rtllib/swg/swg_pkg.sv" + verilog_file_arg = [swg_pkg, "finn_design_wrapper.v", xpm_memory, xpm_cdc, xpm_fifo] verilator_args = [ "perl", From d2c682759de2c874116946000fdf207a2cdab5c9 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 2 Aug 2023 16:06:54 +0100 Subject: [PATCH 237/665] [Util] Update Alveo platforms --- src/finn/util/basic.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/finn/util/basic.py b/src/finn/util/basic.py index 3bc5b803db..05f748d3bb 100644 --- a/src/finn/util/basic.py +++ b/src/finn/util/basic.py @@ -62,10 +62,10 @@ alveo_part_map["U280"] = "xcu280-fsvh2892-2L-e" alveo_default_platform = dict() -alveo_default_platform["U50"] = "xilinx_u50_gen3x16_xdma_201920_3" -alveo_default_platform["U200"] = "xilinx_u200_xdma_201830_2" -alveo_default_platform["U250"] = "xilinx_u250_gen3x16_xdma_2_1_202010_1" -alveo_default_platform["U280"] = "xilinx_u280_xdma_201920_3" +alveo_default_platform["U50"] = "xilinx_u50_gen3x16_xdma_5_202210_1" +alveo_default_platform["U200"] = "xilinx_u200_gen3x16_xdma_2_202110_1" +alveo_default_platform["U250"] = "xilinx_u250_gen3x16_xdma_4_1_202210_1" +alveo_default_platform["U280"] = "xilinx_u280_gen3x16_xdma_1_202211_1" def get_rtlsim_trace_depth(): From a4c15df9964cfb6f7e83e6e52316b7e59758ceb6 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 2 Aug 2023 18:05:10 +0100 Subject: [PATCH 238/665] [Linting] Run pre-commit on files --- .../custom_op/fpgadataflow/fmpadding_pixel.py | 4 +-- .../infer_pixel_padding_deconv.py | 33 ++++--------------- tests/brevitas/test_brevitas_deconv.py | 4 +-- .../fpgadataflow/test_fpgadataflow_deconv.py | 16 +++------ 4 files changed, 13 insertions(+), 44 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/fmpadding_pixel.py b/src/finn/custom_op/fpgadataflow/fmpadding_pixel.py index d56b8d2943..d271297f82 100644 --- a/src/finn/custom_op/fpgadataflow/fmpadding_pixel.py +++ b/src/finn/custom_op/fpgadataflow/fmpadding_pixel.py @@ -288,9 +288,7 @@ def pragmas(self): self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE axis port=out name=out_" + self.hls_sname() ) - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE ap_ctrl_none port=return" - ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") def execute_node(self, context, graph): mode = self.get_nodeattr("exec_mode") diff --git a/src/finn/transformation/fpgadataflow/infer_pixel_padding_deconv.py b/src/finn/transformation/fpgadataflow/infer_pixel_padding_deconv.py index 4acd79d362..0f48565bf9 100644 --- a/src/finn/transformation/fpgadataflow/infer_pixel_padding_deconv.py +++ b/src/finn/transformation/fpgadataflow/infer_pixel_padding_deconv.py @@ -28,10 +28,7 @@ def apply(self, model): idt = model.get_tensor_datatype(deconv_input) odt = model.get_tensor_datatype(deconv_output) if not idt.is_integer(): - warnings.warn( - "%s : Input is not int. Can't infer PixelPaddingDeconv." - % n.name - ) + warnings.warn("%s : Input is not int. Can't infer PixelPaddingDeconv." % n.name) continue # extract conv transpose parameters k_h = get_by_name(n.attribute, "kernel_shape").ints[0] @@ -86,13 +83,9 @@ def apply(self, model): # Im2Col node belongs to a depthwise convolution dw = False if group == ifm_ch and ofm_ch == ifm_ch: - W_sparse = np.zeros( - (ifm_ch, ofm_ch, k_h, k_w) - ) # (IFM, OFM, k_H, k_W) + W_sparse = np.zeros((ifm_ch, ofm_ch, k_h, k_w)) # (IFM, OFM, k_H, k_W) for ch in range(ofm_ch): - W_sparse[ch][ch] = W_conv[ch][ - 0 - ] # W_conv = [IFM, OFM, k_H, k_W] + W_sparse[ch][ch] = W_conv[ch][0] # W_conv = [IFM, OFM, k_H, k_W] W_conv = W_sparse.astype(np.float32) # we need to store information of the # sparsity of the weight matrix. For this @@ -148,13 +141,7 @@ def apply(self, model): padding = 0 # k_h=k_w==1: pointwise convolution, thus no im2col needed - if ( - k_h == 1 - and k_w == 1 - and padding == 0 - and stride_h == 1 - and stride_w == 1 - ): + if k_h == 1 and k_w == 1 and padding == 0 and stride_h == 1 and stride_w == 1: need_im2col = False if need_im2col: @@ -208,17 +195,13 @@ def apply(self, model): stride=[1, 1], kernel_size=[k_h, k_w], pad_amount=conv_padding, - input_shape="(1,{},{},{})".format( - padded_odim_h, padded_odim_w, ifm_ch - ), + input_shape="(1,{},{},{})".format(padded_odim_h, padded_odim_w, ifm_ch), depthwise=dw, dilations=dilation, ) # do matmul - matmul_node = helper.make_node( - "MatMul", [matmul_input, weight_name], [matmul_out] - ) + matmul_node = helper.make_node("MatMul", [matmul_input, weight_name], [matmul_out]) # NHWC -> NCHW out_trans_node = helper.make_node( "Transpose", [matmul_out], [deconv_output], perm=[0, 3, 1, 2] @@ -237,8 +220,6 @@ def apply(self, model): # remove old nodes graph.node.remove(n) - model = model.transform( - InferConvInpGen(use_rtl_variant=self.use_convinpgen_rtl_variant) - ) + model = model.transform(InferConvInpGen(use_rtl_variant=self.use_convinpgen_rtl_variant)) model = model.transform(InferQuantizedMatrixVectorActivation()) return (model, graph_modified) diff --git a/tests/brevitas/test_brevitas_deconv.py b/tests/brevitas/test_brevitas_deconv.py index 75b740ec56..7b93f0367d 100644 --- a/tests/brevitas/test_brevitas_deconv.py +++ b/tests/brevitas/test_brevitas_deconv.py @@ -66,9 +66,7 @@ def test_brevitas_QTransposeConv(ifm_ch, ofm_ch, mh, mw, padding, stride, kw, bi bias=bias, ) # outp = el(inp) # expects NCHW data format - export_qonnx( - b_deconv.cpu(), input_t=inp.cpu(), export_path=export_path, opset_version=11 - ) + export_qonnx(b_deconv.cpu(), input_t=inp.cpu(), export_path=export_path, opset_version=11) model = ModelWrapper(export_path) qonnx_cleanup(model) model = model.transform(ConvertQONNXtoFINN()) diff --git a/tests/fpgadataflow/test_fpgadataflow_deconv.py b/tests/fpgadataflow/test_fpgadataflow_deconv.py index a00eeb49e5..6f99f90dc2 100644 --- a/tests/fpgadataflow/test_fpgadataflow_deconv.py +++ b/tests/fpgadataflow/test_fpgadataflow_deconv.py @@ -75,9 +75,7 @@ def set_up_reference_model(idt, wdt, k, idim, ifm_ch, ofm_ch, stride, padding): idim_w, ], ) - outp = helper.make_tensor_value_info( - "outp", TensorProto.FLOAT, [1, ofm_ch, odim_h, odim_w] - ) + outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, [1, ofm_ch, odim_h, odim_w]) W = helper.make_tensor_value_info("W", TensorProto.FLOAT, [ifm_ch, ofm_ch, k, k]) @@ -148,9 +146,7 @@ def test_fpgadataflow_deconv(idim, stride, ifm_ch, ofm_ch, simd, pe, k, padding) else: convinpgen_rtl = True - ref_model = set_up_reference_model( - idt, wdt, k, idim, ifm_ch, ofm_ch, stride, padding - ) + ref_model = set_up_reference_model(idt, wdt, k, idim, ifm_ch, ofm_ch, stride, padding) odim_h = (idim_h - 1) * stride_h - 2 * padding + (k - 1) + 1 odim_w = (idim_w - 1) * stride_w - 2 * padding + (k - 1) + 1 @@ -198,15 +194,11 @@ def test_fpgadataflow_deconv(idim, stride, ifm_ch, ofm_ch, simd, pe, k, padding) dataflow_model_filename = sdp_node.get_nodeattr("model") model = ModelWrapper(dataflow_model_filename) model.save("after_partition.onnx") - model = model.transform( - CreateStitchedIP(test_fpga_part, target_clk_ns, vitis=False) - ) + model = model.transform(CreateStitchedIP(test_fpga_part, target_clk_ns, vitis=False)) model = model.transform(PrepareRTLSim()) model = model.transform(GiveReadableTensorNames()) model = model.transform(SetExecMode("rtlsim")) model.save("stitched_ip.onnx") - y_produced = oxe.execute_onnx(model, input_dict_tr)["global_out"].transpose( - 0, 3, 1, 2 - ) + y_produced = oxe.execute_onnx(model, input_dict_tr)["global_out"].transpose(0, 3, 1, 2) assert y_produced.shape == expected_oshape assert (y_produced == y_expected).all() From c024c398fa2c85686e37d171f17969636615da3e Mon Sep 17 00:00:00 2001 From: Hugo Le Blevec Date: Thu, 3 Aug 2023 15:38:51 +0200 Subject: [PATCH 239/665] [MoveScalarMulPastConvTranspose] Creating new streamlining transformation to push scalar Mul nodes past ConvTranspose nodes, with associated unit test --- src/finn/transformation/streamline/reorder.py | 49 ++++++++ .../test_move_scalar_past_convtranspose.py | 105 ++++++++++++++++++ 2 files changed, 154 insertions(+) create mode 100644 tests/transformation/streamline/test_move_scalar_past_convtranspose.py diff --git a/src/finn/transformation/streamline/reorder.py b/src/finn/transformation/streamline/reorder.py index 2e6aebf093..8ac2d7dad6 100644 --- a/src/finn/transformation/streamline/reorder.py +++ b/src/finn/transformation/streamline/reorder.py @@ -338,6 +338,55 @@ def apply(self, model): return (model, graph_modified) +class MoveScalarMulPastConvTranspose(Transformation): + """Move scalar mul operations past ConvTranspose operations. We want to have muls + next to each other such that they can be collapsed into a single mul.""" + + def apply(self, model): + graph = model.graph + node_ind = 0 + graph_modified = False + for n in graph.node: + node_ind += 1 + if n.op_type == "Mul" and not model.is_fork_node(n) and not model.is_join_node(n): + consumer = model.find_consumer(n.output[0]) + if ( + consumer is not None + and consumer.op_type == "ConvTranspose" + and not model.is_join_node(consumer) + ): + mul_weight_name = n.input[1] + A = model.get_initializer(mul_weight_name) + if A is None: + warnings.warn("Mul param is not constant, skipping") + continue + conv_node = consumer + mul_node = n + start_name = mul_node.input[0] + conv_in_name = conv_node.input[0] + conv_in_shape = model.get_tensor_shape(conv_in_name) + conv_out_name = conv_node.output[0] + conv_out_shape = model.get_tensor_shape(conv_out_name) + if all(x == 1 for x in A.shape): + # if the mul is scalar, we can simply swap the order of ops + # rewire mul input to be conv input + conv_node.input[0] = start_name + model.set_tensor_shape(start_name, conv_in_shape) + # use old conv input tensor as conv output + conv_node.output[0] = conv_in_name + model.set_tensor_shape(conv_in_name, conv_out_shape) + # use new conv output as new mul node input + mul_node.input[0] = conv_in_name + # use old conv output as new mul node output + mul_node.output[0] = conv_out_name + # move add node past conv node + graph.node.remove(mul_node) + graph.node.insert(node_ind, mul_node) + graph_modified = True + model = model.transform(InferShapes()) + return (model, graph_modified) + + class MoveMulPastDWConv(Transformation): """Move channelwise mul operations past depthwise conv operations. We want to have muls next to each other such that they can be collapsed into a single mul.""" diff --git a/tests/transformation/streamline/test_move_scalar_past_convtranspose.py b/tests/transformation/streamline/test_move_scalar_past_convtranspose.py new file mode 100644 index 0000000000..1e894c9cb2 --- /dev/null +++ b/tests/transformation/streamline/test_move_scalar_past_convtranspose.py @@ -0,0 +1,105 @@ +# Copyright (c) 2020, Xilinx +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +import pytest + +import numpy as np +import onnx.helper as oh +from onnx import TensorProto +from qonnx.core.modelwrapper import ModelWrapper +from qonnx.transformation.infer_shapes import InferShapes +from qonnx.util.basic import qonnx_make_model + +import finn.core.onnx_exec as ox +from finn.transformation.streamline.reorder import MoveScalarMulPastConvTranspose + + +@pytest.mark.streamline +# input image dimension +@pytest.mark.parametrize("idim", [[8, 8], [10, 8]]) +# number of rows and number of cols to add +@pytest.mark.parametrize("stride", [[2, 2], [2, 3]]) +# number of channels +@pytest.mark.parametrize("ifm_ch", [2, 4]) +# number of channels +@pytest.mark.parametrize("ofm_ch", [2, 4]) +# kernel size +@pytest.mark.parametrize("k", [2, 4]) +# padding +@pytest.mark.parametrize("padding", [False, True]) +def test_move_scalar_past_conv(idim, stride, ifm_ch, ofm_ch, k, padding): + idim_h, idim_w = idim + stride_h, stride_w = stride + + odim_h = (idim_h - 1) * stride_h - 2 * padding + (k - 1) + 1 + odim_w = (idim_w - 1) * stride_w - 2 * padding + (k - 1) + 1 + + input_shape = [1, ifm_ch, idim_h, idim_w] + output_shape = [1, ofm_ch, odim_h, odim_w] + + conv_param_shape = [ifm_ch, ofm_ch, k, k] + + conv_config = {} + conv_config["dilations"] = [1, 1] + conv_config["group"] = 1 + conv_config["kernel_shape"] = [k, k] + if padding: + conv_config["pads"] = [1, 1, 1, 1] + else: + conv_config["pads"] = [0, 0, 0, 0] + conv_config["strides"] = [stride_h, stride_w] + + top_in = oh.make_tensor_value_info("top_in", TensorProto.FLOAT, input_shape) + top_out = oh.make_tensor_value_info("top_out", TensorProto.FLOAT, output_shape) + + value_info = [oh.make_tensor_value_info("p1", TensorProto.FLOAT, [1])] + value_info += [oh.make_tensor_value_info("p2", TensorProto.FLOAT, conv_param_shape)] + + modelproto = qonnx_make_model( + oh.make_graph( + name="test", + inputs=[top_in], + outputs=[top_out], + value_info=value_info, + nodes=[ + oh.make_node("Mul", ["top_in", "p1"], ["t1"]), + oh.make_node("ConvTranspose", ["t1", "p2"], ["top_out"], **conv_config), + ], + ) + ) + model = ModelWrapper(modelproto) + model = model.transform(InferShapes()) + + np.random.seed(0) + model.set_initializer("p1", *np.random.rand(1).astype(np.float32)) + model.set_initializer("p2", np.random.rand(*conv_param_shape).astype(np.float32)) + new_model = model.transform(MoveScalarMulPastConvTranspose()) + inp_dict = {"top_in": np.random.rand(*input_shape).astype(np.float32)} + + assert ox.compare_execution(model, new_model, inp_dict) + assert new_model.graph.node[0].op_type == "ConvTranspose" + assert new_model.graph.node[1].op_type == "Mul" From 121e893f73edabc370a102f3227b322db918e253 Mon Sep 17 00:00:00 2001 From: icolbert Date: Tue, 9 May 2023 14:11:09 -0700 Subject: [PATCH 240/665] [MVAU] Handling minimize acc bw for no-activation nodes --- .../fpgadataflow/matrixvectoractivation.py | 28 ++++++++++++++----- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index 7c180534b1..2f99ddca77 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -655,14 +655,28 @@ def minimize_accumulator_width(self, model): adt = DataType.get_smallest_possible(-acc_max - 1) else: adt = DataType.get_smallest_possible(acc_max) - # if this is the last node in the graph, then ensure the datatype is - # divisibly by 8 bits + # if this is the last node in the graph, then ensure the datatype of the + # output is divisible by 8 if model.find_direct_successors(self.onnx_node) is None: - bw = roundup_to_integer_multiple(adt.bitwidth(), 8) - new_adt_name = adt.name.replace(str(adt.bitwidth()), str(bw)) - adt = DataType[new_adt_name] - # for no-activation nodes, output dt = acc dt - self.set_nodeattr("outputDataType", adt.name) + if self.get_nodeattr("noActivation"): + bw = roundup_to_integer_multiple(adt.bitwidth(), 8) + new_adt_name = adt.name.replace(str(adt.bitwidth()), str(bw)) + adt = DataType[new_adt_name] + # for no-activation nodes, output dt = acc dt + self.set_nodeattr("outputDataType", adt.name) + else: + odt = DataType[self.get_nodeattr("outputDataType")] + bw = roundup_to_integer_multiple(odt.bitwidth(), 8) + new_odt_name = odt.name.replace(str(odt.bitwidth()), str(bw)) + if bw != odt.bitwidth(): + warn_str = "outputDataType changing for %s: %s -> %s " % ( + self.onnx_node.name, + odt.name, + new_odt_name, + ) + warnings.warn(warn_str) + odt = DataType[new_odt_name] + self.set_nodeattr("outputDataType", odt.name) self.set_nodeattr("accDataType", adt.name) return DataType[self.get_nodeattr("accDataType")] From 93d9cdb3b38d706222cc122d17638b9a9828a24e Mon Sep 17 00:00:00 2001 From: icolbert Date: Tue, 9 May 2023 14:11:35 -0700 Subject: [PATCH 241/665] [VVAU] Handling minimize acc bw for no-activation nodes --- .../fpgadataflow/vectorvectoractivation.py | 28 ++++++++++++++----- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index 58a85b29ee..773c49915f 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -182,14 +182,28 @@ def minimize_accumulator_width(self, model): adt = DataType.get_smallest_possible(-acc_max - 1) else: adt = DataType.get_smallest_possible(acc_max) - # if this is the last node in the graph, then ensure the datatype is - # divisibly by 8 bits + # if this is the last node in the graph, then ensure the datatype of the + # output is divisible by 8 if model.find_direct_successors(self.onnx_node) is None: - bw = roundup_to_integer_multiple(adt.bitwidth(), 8) - new_adt_name = adt.name.replace(str(adt.bitwidth()), str(bw)) - adt = DataType[new_adt_name] - # for no-activation nodes, output dt = acc dt - self.set_nodeattr("outputDataType", adt.name) + if self.get_nodeattr("noActivation"): + bw = roundup_to_integer_multiple(adt.bitwidth(), 8) + new_adt_name = adt.name.replace(str(adt.bitwidth()), str(bw)) + adt = DataType[new_adt_name] + # for no-activation nodes, output dt = acc dt + self.set_nodeattr("outputDataType", adt.name) + else: + odt = DataType[self.get_nodeattr("outputDataType")] + bw = roundup_to_integer_multiple(odt.bitwidth(), 8) + new_odt_name = odt.name.replace(str(odt.bitwidth()), str(bw)) + if bw != odt.bitwidth(): + warn_str = "outputDataType changing for %s: %s -> %s " % ( + self.onnx_node.name, + odt.name, + new_odt_name, + ) + warnings.warn(warn_str) + odt = DataType[new_odt_name] + self.set_nodeattr("outputDataType", odt.name) self.set_nodeattr("accDataType", adt.name) return DataType[self.get_nodeattr("accDataType")] From 0123d2629d0c89f384a5243b22a96a5a33daeac7 Mon Sep 17 00:00:00 2001 From: icolbert Date: Wed, 31 May 2023 09:36:11 -0700 Subject: [PATCH 242/665] [MVAU] Fixing to maintain prior functionality --- src/finn/custom_op/fpgadataflow/matrixvectoractivation.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index 2f99ddca77..cef336bdd4 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -667,7 +667,10 @@ def minimize_accumulator_width(self, model): else: odt = DataType[self.get_nodeattr("outputDataType")] bw = roundup_to_integer_multiple(odt.bitwidth(), 8) - new_odt_name = odt.name.replace(str(odt.bitwidth()), str(bw)) + # NOTE: keeping previous functionality of converting outputDataType + # to accDataType on the last node. May want to preserve outputDataType + # in the future by replacing adt with odt below. + new_odt_name = adt.name.replace(str(adt.bitwidth()), str(bw)) if bw != odt.bitwidth(): warn_str = "outputDataType changing for %s: %s -> %s " % ( self.onnx_node.name, From aa345e333df5c81ab28f134063b67d4ca7ccb14f Mon Sep 17 00:00:00 2001 From: icolbert Date: Wed, 31 May 2023 09:36:24 -0700 Subject: [PATCH 243/665] [VVAU] Fixing to maintain prior functionality --- src/finn/custom_op/fpgadataflow/vectorvectoractivation.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index 773c49915f..29bf9651f0 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -194,7 +194,10 @@ def minimize_accumulator_width(self, model): else: odt = DataType[self.get_nodeattr("outputDataType")] bw = roundup_to_integer_multiple(odt.bitwidth(), 8) - new_odt_name = odt.name.replace(str(odt.bitwidth()), str(bw)) + # NOTE: keeping previous functionality of converting outputDataType + # to accDataType on the last node. May want to preserve outputDataType + # in the future by replacing adt with odt below. + new_odt_name = adt.name.replace(str(adt.bitwidth()), str(bw)) if bw != odt.bitwidth(): warn_str = "outputDataType changing for %s: %s -> %s " % ( self.onnx_node.name, From 3f05b634b6a837159bb4a0f1ccc83b97f1705e8f Mon Sep 17 00:00:00 2001 From: icolbert Date: Wed, 31 May 2023 09:38:25 -0700 Subject: [PATCH 244/665] Updating unit test to check correct functionality --- tests/fpgadataflow/test_minimize_bit_width.py | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/tests/fpgadataflow/test_minimize_bit_width.py b/tests/fpgadataflow/test_minimize_bit_width.py index 805578018c..ad7b1cdf86 100644 --- a/tests/fpgadataflow/test_minimize_bit_width.py +++ b/tests/fpgadataflow/test_minimize_bit_width.py @@ -297,10 +297,11 @@ def test_minimize_accumulator_width(wdt: DataType, idt: DataType, tdt: DataType, assert cur_adt.bitwidth() <= exp_adt.bitwidth(), "Mismatched accumulation data types" if model.find_direct_successors(inst.onnx_node) is None: assert ( - cur_adt.bitwidth() % 8 - ) == 0, "bit width of last node needs to be divisible by 8" - assert ( - cur_adt.bitwidth() == cur_odt.bitwidth() - ), "outputDataType and accDataType should be equal" + cur_odt.bitwidth() % 8 + ) == 0, "output bit width of last node needs to be divisible by 8" + if inst.get_nodeattr("noActivation"): + assert ( + cur_adt.bitwidth() == cur_odt.bitwidth() + ), "outputDataType and accDataType should be equal" else: assert cur_odt.bitwidth() == idt.bitwidth(), "outputDataType should not be changed" From d853ab50ab2c2811f9001b003d9f527082100bfe Mon Sep 17 00:00:00 2001 From: icolbert Date: Wed, 7 Jun 2023 10:54:46 -0700 Subject: [PATCH 245/665] [MVAU] updating minimize_accumulator logic --- .../fpgadataflow/matrixvectoractivation.py | 50 +++++++++++-------- 1 file changed, 28 insertions(+), 22 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index cef336bdd4..1d6a6f5576 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -655,31 +655,37 @@ def minimize_accumulator_width(self, model): adt = DataType.get_smallest_possible(-acc_max - 1) else: adt = DataType.get_smallest_possible(acc_max) - # if this is the last node in the graph, then ensure the datatype of the - # output is divisible by 8 - if model.find_direct_successors(self.onnx_node) is None: - if self.get_nodeattr("noActivation"): + + is_last_node = model.find_direct_successors(self.onnx_node) is None + + # if no activation, output and accumulator datatypes are the same + if self.get_nodeattr("noActivation"): + # if last node, we need to round the accumulator datatype (adt) + # up to the nearest 8 and set the output datatype (odt) + if is_last_node: bw = roundup_to_integer_multiple(adt.bitwidth(), 8) new_adt_name = adt.name.replace(str(adt.bitwidth()), str(bw)) adt = DataType[new_adt_name] - # for no-activation nodes, output dt = acc dt - self.set_nodeattr("outputDataType", adt.name) - else: - odt = DataType[self.get_nodeattr("outputDataType")] - bw = roundup_to_integer_multiple(odt.bitwidth(), 8) - # NOTE: keeping previous functionality of converting outputDataType - # to accDataType on the last node. May want to preserve outputDataType - # in the future by replacing adt with odt below. - new_odt_name = adt.name.replace(str(adt.bitwidth()), str(bw)) - if bw != odt.bitwidth(): - warn_str = "outputDataType changing for %s: %s -> %s " % ( - self.onnx_node.name, - odt.name, - new_odt_name, - ) - warnings.warn(warn_str) - odt = DataType[new_odt_name] - self.set_nodeattr("outputDataType", odt.name) + self.set_nodeattr("outputDataType", adt.name) + + # if last node has activation, then ensure the output datatype is divisible by 8 + if not self.get_nodeattr("noActivation") and is_last_node: + odt = DataType[self.get_nodeattr("outputDataType")] + bw = roundup_to_integer_multiple(odt.bitwidth(), 8) + # NOTE: keeping previous functionality of converting odt to adt on the last + # node, could preserve odt in the future by replacing adt with odt. This + # may yield unfavorable functionality for Bipolar and/or Ternary datatypes + new_odt_name = adt.name.replace(str(adt.bitwidth()), str(bw)) + if bw != odt.bitwidth(): + warn_str = "outputDataType changing for %s: %s -> %s " % ( + self.onnx_node.name, + odt.name, + new_odt_name, + ) + warnings.warn(warn_str) + odt = DataType[new_odt_name] + self.set_nodeattr("outputDataType", odt.name) + self.set_nodeattr("accDataType", adt.name) return DataType[self.get_nodeattr("accDataType")] From a3ee3a37289ceef2395c1867aca5edbe8813a27b Mon Sep 17 00:00:00 2001 From: icolbert Date: Wed, 7 Jun 2023 10:54:57 -0700 Subject: [PATCH 246/665] [VVAU] updating minimize_accumulator logic --- .../fpgadataflow/vectorvectoractivation.py | 51 ++++++++++--------- 1 file changed, 28 insertions(+), 23 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index 29bf9651f0..09e749be57 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -182,32 +182,37 @@ def minimize_accumulator_width(self, model): adt = DataType.get_smallest_possible(-acc_max - 1) else: adt = DataType.get_smallest_possible(acc_max) - # if this is the last node in the graph, then ensure the datatype of the - # output is divisible by 8 - if model.find_direct_successors(self.onnx_node) is None: - if self.get_nodeattr("noActivation"): + + is_last_node = model.find_direct_successors(self.onnx_node) is None + + # if no activation, output and accumulator datatypes are the same + if self.get_nodeattr("noActivation"): + # if last node, we need to round the accumulator datatype (adt) + # up to the nearest 8 and set the output datatype (odt) + if is_last_node: bw = roundup_to_integer_multiple(adt.bitwidth(), 8) new_adt_name = adt.name.replace(str(adt.bitwidth()), str(bw)) adt = DataType[new_adt_name] - # for no-activation nodes, output dt = acc dt - self.set_nodeattr("outputDataType", adt.name) - else: - odt = DataType[self.get_nodeattr("outputDataType")] - bw = roundup_to_integer_multiple(odt.bitwidth(), 8) - # NOTE: keeping previous functionality of converting outputDataType - # to accDataType on the last node. May want to preserve outputDataType - # in the future by replacing adt with odt below. - new_odt_name = adt.name.replace(str(adt.bitwidth()), str(bw)) - if bw != odt.bitwidth(): - warn_str = "outputDataType changing for %s: %s -> %s " % ( - self.onnx_node.name, - odt.name, - new_odt_name, - ) - warnings.warn(warn_str) - odt = DataType[new_odt_name] - self.set_nodeattr("outputDataType", odt.name) - self.set_nodeattr("accDataType", adt.name) + self.set_nodeattr("outputDataType", adt.name) + + # if last node has activation, then ensure the output datatype is divisible by 8 + if not self.get_nodeattr("noActivation") and is_last_node: + odt = DataType[self.get_nodeattr("outputDataType")] + bw = roundup_to_integer_multiple(odt.bitwidth(), 8) + # NOTE: keeping previous functionality of converting odt to adt on the last + # node, could preserve odt in the future by replacing adt with odt. This + # may yield unfavorable functionality for Bipolar and/or Ternary datatypes + new_odt_name = adt.name.replace(str(adt.bitwidth()), str(bw)) + if bw != odt.bitwidth(): + warn_str = "outputDataType changing for %s: %s -> %s " % ( + self.onnx_node.name, + odt.name, + new_odt_name, + ) + warnings.warn(warn_str) + odt = DataType[new_odt_name] + self.set_nodeattr("outputDataType", odt.name) + return DataType[self.get_nodeattr("accDataType")] def minimize_weight_bit_width(self, model): From f172adc8fcc19338756b8b936a78a2de5620e142 Mon Sep 17 00:00:00 2001 From: icolbert Date: Thu, 8 Jun 2023 10:37:14 -0700 Subject: [PATCH 247/665] [VVAU] fixing bug with setting accDataType --- src/finn/custom_op/fpgadataflow/vectorvectoractivation.py | 1 + 1 file changed, 1 insertion(+) diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index 09e749be57..af2591f703 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -213,6 +213,7 @@ def minimize_accumulator_width(self, model): odt = DataType[new_odt_name] self.set_nodeattr("outputDataType", odt.name) + self.set_nodeattr("accDataType", adt.name) return DataType[self.get_nodeattr("accDataType")] def minimize_weight_bit_width(self, model): From 1e5cbc8d65690f8c3c684506fd5f3778e017a027 Mon Sep 17 00:00:00 2001 From: icolbert Date: Thu, 8 Jun 2023 10:37:59 -0700 Subject: [PATCH 248/665] Fixing test_minimize_bit_width unit test --- tests/fpgadataflow/test_minimize_bit_width.py | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/tests/fpgadataflow/test_minimize_bit_width.py b/tests/fpgadataflow/test_minimize_bit_width.py index ad7b1cdf86..0427bbd4d8 100644 --- a/tests/fpgadataflow/test_minimize_bit_width.py +++ b/tests/fpgadataflow/test_minimize_bit_width.py @@ -294,14 +294,12 @@ def test_minimize_accumulator_width(wdt: DataType, idt: DataType, tdt: DataType, # bit width minimization logic in the MVAU and VVAU is exact and should be # less than or equal to this calculation exp_adt = calculate_accumulator_bit_width(inst, model) - assert cur_adt.bitwidth() <= exp_adt.bitwidth(), "Mismatched accumulation data types" - if model.find_direct_successors(inst.onnx_node) is None: + assert ( + cur_adt.bitwidth() <= exp_adt.bitwidth() + ), "Mismatched accumulation data types" + + # if there is no activation, outputDataType = accDataType + if inst.get_nodeattr("noActivation"): assert ( - cur_odt.bitwidth() % 8 - ) == 0, "output bit width of last node needs to be divisible by 8" - if inst.get_nodeattr("noActivation"): - assert ( - cur_adt.bitwidth() == cur_odt.bitwidth() - ), "outputDataType and accDataType should be equal" - else: - assert cur_odt.bitwidth() == idt.bitwidth(), "outputDataType should not be changed" + cur_adt.bitwidth() == cur_odt.bitwidth() + ), "outputDataType and accDataType should be equal" From d9e4654c79b4461189fe6381163f17eaf8037597 Mon Sep 17 00:00:00 2001 From: icolbert Date: Wed, 14 Jun 2023 18:20:37 -0700 Subject: [PATCH 249/665] [MVAU] Updating minimize_accumulator_width logic --- .../fpgadataflow/matrixvectoractivation.py | 92 ++++++------------- 1 file changed, 29 insertions(+), 63 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index 1d6a6f5576..ccf5b00918 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -589,11 +589,14 @@ def minimize_accumulator_width(self, model): # for the bipolar case they need to be converted to bipolar if self.get_nodeattr("binaryXnorMode"): weights = 2 * weights - 1 + + thresholds = None if len(self.onnx_node.input) > 2: thresholds = model.get_initializer(self.onnx_node.input[2]) - else: - thresholds = None + idt = self.get_input_datatype() + + (acc_min, acc_max) = calculate_matvec_accumulator_range(weights, idt) # if runtime-writeable weights, then the values of the weights can # change and we need to use the worst-case values from the datatypes if self.get_nodeattr("runtime_writeable_weights"): @@ -604,11 +607,7 @@ def minimize_accumulator_width(self, model): upper_range = calculate_matvec_accumulator_range(upper_worst, idt) acc_min = min(min(lower_range), min(upper_range)) acc_max = max(max(upper_range), max(upper_range)) - # if not runtime-writeable weights, then we can calculate the min - # and max values of the accumulation range using knowledge of the - # weights and input data types since they are fixed - else: - (acc_min, acc_max) = calculate_matvec_accumulator_range(weights, idt) + # if the thresholds can be used to determine range, then adjust the range # according to the known values of the thresholds if thresholds is not None: @@ -617,76 +616,43 @@ def minimize_accumulator_width(self, model): min_threshold = thresholds.min() max_threshold = thresholds.max() # clip threshold values - clip_upper = None - clip_lower = None - if max_threshold > acc_max + 1: - clip_upper = acc_max + 1 - if min_threshold < acc_min: - clip_lower = acc_min - if (clip_lower is not None) or (clip_upper is not None): + if max_threshold > acc_max or min_threshold < acc_min: warnings.warn("Clipping some thresholds in %s" % self.onnx_node.name) - thresholds = np.clip(thresholds, clip_lower, clip_upper) + thresholds = np.clip(thresholds, acc_min, acc_max) model.set_initializer(self.onnx_node.input[2], thresholds) threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds) min_threshold = thresholds.min() max_threshold = thresholds.max() - # get range required by threshold values - tdt_min = min(acc_min, min_threshold) - tdt_max = max(acc_max, max_threshold) - if tdt_min < 0: - if abs(tdt_min) > tdt_max: - tdt = DataType.get_smallest_possible(tdt_min) - else: - tdt = DataType.get_smallest_possible(-tdt_max - 1) - else: - tdt = DataType.get_smallest_possible(tdt_max) - assert np.vectorize(tdt.allowed)( + acc_min = min(min_threshold, acc_min) + acc_max = max(max_threshold, acc_max) + + # if the acc_range is always greater than 0, then acc_max <= 2^P - 1 + if acc_min >= 0: + acc_bit_width = np.log2(acc_max + 1) + acc_bit_width = math.ceil(acc_bit_width) + adt = DataType[f"UINT{acc_bit_width}"] + # if the acc_range is signed, then acc_min >= -2^{P-1} and acc_max <= + # 2^{P - 1} - 1, which means 2^{P - 1} >= max(-acc_min, 1 + acc_max) + else: + _acc_max = max(-acc_min, 1 + acc_max) + acc_bit_width = np.log2(_acc_max) + 1 + acc_bit_width = math.ceil(acc_bit_width) + adt = DataType[f"INT{acc_bit_width}"] + + # if activation, assert that the thresholds can be expressed with adt + if thresholds is not None: + assert np.vectorize(adt.allowed)( threshold_tensor ).all(), "Thresholds in %s can't be expressed with type %s" % ( self.onnx_node.name, - str(tdt), + str(adt), ) - adt = tdt # Set activation datatype to the threshold datatype - else: - if acc_min < 0: - if abs(acc_min) > acc_max: - adt = DataType.get_smallest_possible(acc_min) - else: - adt = DataType.get_smallest_possible(-acc_max - 1) - else: - adt = DataType.get_smallest_possible(acc_max) - - is_last_node = model.find_direct_successors(self.onnx_node) is None # if no activation, output and accumulator datatypes are the same if self.get_nodeattr("noActivation"): - # if last node, we need to round the accumulator datatype (adt) - # up to the nearest 8 and set the output datatype (odt) - if is_last_node: - bw = roundup_to_integer_multiple(adt.bitwidth(), 8) - new_adt_name = adt.name.replace(str(adt.bitwidth()), str(bw)) - adt = DataType[new_adt_name] self.set_nodeattr("outputDataType", adt.name) - - # if last node has activation, then ensure the output datatype is divisible by 8 - if not self.get_nodeattr("noActivation") and is_last_node: - odt = DataType[self.get_nodeattr("outputDataType")] - bw = roundup_to_integer_multiple(odt.bitwidth(), 8) - # NOTE: keeping previous functionality of converting odt to adt on the last - # node, could preserve odt in the future by replacing adt with odt. This - # may yield unfavorable functionality for Bipolar and/or Ternary datatypes - new_odt_name = adt.name.replace(str(adt.bitwidth()), str(bw)) - if bw != odt.bitwidth(): - warn_str = "outputDataType changing for %s: %s -> %s " % ( - self.onnx_node.name, - odt.name, - new_odt_name, - ) - warnings.warn(warn_str) - odt = DataType[new_odt_name] - self.set_nodeattr("outputDataType", odt.name) - self.set_nodeattr("accDataType", adt.name) + return DataType[self.get_nodeattr("accDataType")] def minimize_weight_bit_width(self, model): From 4dc169463ec0586380d2f19b1ae39e3c7d64955d Mon Sep 17 00:00:00 2001 From: icolbert Date: Wed, 14 Jun 2023 18:20:48 -0700 Subject: [PATCH 250/665] [VVAU] Updating minimize_accumulator_width logic --- .../fpgadataflow/vectorvectoractivation.py | 87 ++++++------------- 1 file changed, 26 insertions(+), 61 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index af2591f703..035b6f28ec 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -121,6 +121,8 @@ def minimize_accumulator_width(self, model): else: thresholds = None idt = self.get_input_datatype() + + (acc_min, acc_max) = calculate_matvec_accumulator_range(weights, idt) # if runtime-writeable weights, then the values of the weights can # change and we need to use the worst-case values from the datatypes if self.get_nodeattr("runtime_writeable_weights"): @@ -131,11 +133,7 @@ def minimize_accumulator_width(self, model): upper_range = calculate_matvec_accumulator_range(upper_worst, idt) acc_min = min(min(lower_range), min(upper_range)) acc_max = max(max(upper_range), max(upper_range)) - # if not runtime-writeable weights, then we can calculate the min - # and max values of the accumulation range using knowledge of the - # weights and input data types since they are fixed - else: - (acc_min, acc_max) = calculate_matvec_accumulator_range(weights, idt) + # if the thresholds can be used to determine range, then adjust the range # according to the known values of the thresholds if thresholds is not None: @@ -144,76 +142,43 @@ def minimize_accumulator_width(self, model): min_threshold = thresholds.min() max_threshold = thresholds.max() # clip threshold values - clip_upper = None - clip_lower = None - if max_threshold > acc_max + 1: - clip_upper = acc_max + 1 - if min_threshold < acc_min: - clip_lower = acc_min - if (clip_lower is not None) or (clip_upper is not None): + if max_threshold > acc_max or min_threshold < acc_min: warnings.warn("Clipping some thresholds in %s" % self.onnx_node.name) - thresholds = np.clip(thresholds, clip_lower, clip_upper) + thresholds = np.clip(thresholds, acc_min, acc_max) model.set_initializer(self.onnx_node.input[2], thresholds) threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds) min_threshold = thresholds.min() max_threshold = thresholds.max() - # get range required by threshold values - tdt_min = min(acc_min, min_threshold) - tdt_max = max(acc_max, max_threshold) - if tdt_min < 0: - if abs(tdt_min) > tdt_max: - tdt = DataType.get_smallest_possible(tdt_min) - else: - tdt = DataType.get_smallest_possible(-tdt_max - 1) - else: - tdt = DataType.get_smallest_possible(tdt_max) - assert np.vectorize(tdt.allowed)( + acc_min = min(min_threshold, acc_min) + acc_max = max(max_threshold, acc_max) + + # if the acc_range is always greater than 0, then acc_max <= 2^P - 1 + if acc_min >= 0: + acc_bit_width = np.log2(acc_max + 1) + acc_bit_width = math.ceil(acc_bit_width) + adt = DataType[f"UINT{acc_bit_width}"] + # if the acc_range is signed, then acc_min >= -2^{P-1} and acc_max <= + # 2^{P - 1} - 1, which means 2^{P - 1} >= max(-acc_min, 1 + acc_max) + else: + _acc_max = max(-acc_min, 1 + acc_max) + acc_bit_width = np.log2(_acc_max) + 1 + acc_bit_width = math.ceil(acc_bit_width) + adt = DataType[f"INT{acc_bit_width}"] + + # if activation, assert that the thresholds can be expressed with adt + if thresholds is not None: + assert np.vectorize(adt.allowed)( threshold_tensor ).all(), "Thresholds in %s can't be expressed with type %s" % ( self.onnx_node.name, - str(tdt), + str(adt), ) - adt = tdt # Set activation datatype to the threshold datatype - else: - if acc_min < 0: - if abs(acc_min) > acc_max: - adt = DataType.get_smallest_possible(acc_min) - else: - adt = DataType.get_smallest_possible(-acc_max - 1) - else: - adt = DataType.get_smallest_possible(acc_max) - - is_last_node = model.find_direct_successors(self.onnx_node) is None # if no activation, output and accumulator datatypes are the same if self.get_nodeattr("noActivation"): - # if last node, we need to round the accumulator datatype (adt) - # up to the nearest 8 and set the output datatype (odt) - if is_last_node: - bw = roundup_to_integer_multiple(adt.bitwidth(), 8) - new_adt_name = adt.name.replace(str(adt.bitwidth()), str(bw)) - adt = DataType[new_adt_name] self.set_nodeattr("outputDataType", adt.name) - - # if last node has activation, then ensure the output datatype is divisible by 8 - if not self.get_nodeattr("noActivation") and is_last_node: - odt = DataType[self.get_nodeattr("outputDataType")] - bw = roundup_to_integer_multiple(odt.bitwidth(), 8) - # NOTE: keeping previous functionality of converting odt to adt on the last - # node, could preserve odt in the future by replacing adt with odt. This - # may yield unfavorable functionality for Bipolar and/or Ternary datatypes - new_odt_name = adt.name.replace(str(adt.bitwidth()), str(bw)) - if bw != odt.bitwidth(): - warn_str = "outputDataType changing for %s: %s -> %s " % ( - self.onnx_node.name, - odt.name, - new_odt_name, - ) - warnings.warn(warn_str) - odt = DataType[new_odt_name] - self.set_nodeattr("outputDataType", odt.name) - self.set_nodeattr("accDataType", adt.name) + return DataType[self.get_nodeattr("accDataType")] def minimize_weight_bit_width(self, model): From 7d5a8b6b2103b6ebd931a0b9d0479808007d5c4d Mon Sep 17 00:00:00 2001 From: icolbert Date: Thu, 3 Aug 2023 07:53:34 -0700 Subject: [PATCH 251/665] Pre-commit fixes --- tests/fpgadataflow/test_minimize_bit_width.py | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/tests/fpgadataflow/test_minimize_bit_width.py b/tests/fpgadataflow/test_minimize_bit_width.py index 0427bbd4d8..4be0a260b7 100644 --- a/tests/fpgadataflow/test_minimize_bit_width.py +++ b/tests/fpgadataflow/test_minimize_bit_width.py @@ -294,9 +294,7 @@ def test_minimize_accumulator_width(wdt: DataType, idt: DataType, tdt: DataType, # bit width minimization logic in the MVAU and VVAU is exact and should be # less than or equal to this calculation exp_adt = calculate_accumulator_bit_width(inst, model) - assert ( - cur_adt.bitwidth() <= exp_adt.bitwidth() - ), "Mismatched accumulation data types" + assert cur_adt.bitwidth() <= exp_adt.bitwidth(), "Mismatched accumulation data types" # if there is no activation, outputDataType = accDataType if inst.get_nodeattr("noActivation"): From f11856f3c5db5825722bfd977f644c01f5ad6139 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Fri, 4 Aug 2023 10:27:30 +0100 Subject: [PATCH 252/665] [Deps] Update qonnx version to include qcdq2qonnx changes Signed-off-by: aziz bahri --- fetch-repos.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fetch-repos.sh b/fetch-repos.sh index 9e3ee3ef99..5b07d11273 100755 --- a/fetch-repos.sh +++ b/fetch-repos.sh @@ -27,7 +27,7 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -QONNX_COMMIT="8755423377e9c01dd2d2358c320484399b5d6625" +QONNX_COMMIT="04e24583fb5c1895744801480db3ced8a5b6a914" FINN_EXP_COMMIT="0aa7e1c44b20cf085b6fe42cff360f0a832afd2c" BREVITAS_COMMIT="9bb26bf2798de210a267d1e4aed4c20087e0e8a5" PYVERILATOR_COMMIT="766e457465f5c0dd315490d7b9cc5d74f9a76f4f" From d07655968644a0c7a19a04986fca3984a2ea43ab Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 4 Aug 2023 14:14:48 +0100 Subject: [PATCH 253/665] [MVAU/VVAU] DataType divisibility by 8 for last node if no activation --- src/finn/custom_op/fpgadataflow/matrixvectoractivation.py | 7 +++++++ src/finn/custom_op/fpgadataflow/vectorvectoractivation.py | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index ccf5b00918..7eb56db382 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -650,6 +650,13 @@ def minimize_accumulator_width(self, model): # if no activation, output and accumulator datatypes are the same if self.get_nodeattr("noActivation"): + # if this is the last node in the graph, then ensure the datatype is + # divisibly by 8 bits + if model.find_direct_successors(self.onnx_node) is None: + bw = roundup_to_integer_multiple(adt.bitwidth(), 8) + new_adt_name = adt.name.replace(str(adt.bitwidth()), str(bw)) + adt = DataType[new_adt_name] + # for no-activation nodes, output dt = acc dt self.set_nodeattr("outputDataType", adt.name) self.set_nodeattr("accDataType", adt.name) diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index 035b6f28ec..bd5bb75f1d 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -176,6 +176,13 @@ def minimize_accumulator_width(self, model): # if no activation, output and accumulator datatypes are the same if self.get_nodeattr("noActivation"): + # if this is the last node in the graph, then ensure the datatype is + # divisibly by 8 bits + if model.find_direct_successors(self.onnx_node) is None: + bw = roundup_to_integer_multiple(adt.bitwidth(), 8) + new_adt_name = adt.name.replace(str(adt.bitwidth()), str(bw)) + adt = DataType[new_adt_name] + # for no-activation nodes, output dt = acc dt self.set_nodeattr("outputDataType", adt.name) self.set_nodeattr("accDataType", adt.name) From f713ab09794a66e9cddae605055666064b855caf Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 4 Aug 2023 16:39:16 +0100 Subject: [PATCH 254/665] [Tests] Include divisibility by 8 in minimize bit width testing --- tests/fpgadataflow/test_minimize_bit_width.py | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/tests/fpgadataflow/test_minimize_bit_width.py b/tests/fpgadataflow/test_minimize_bit_width.py index 4be0a260b7..0e704230e7 100644 --- a/tests/fpgadataflow/test_minimize_bit_width.py +++ b/tests/fpgadataflow/test_minimize_bit_width.py @@ -296,8 +296,13 @@ def test_minimize_accumulator_width(wdt: DataType, idt: DataType, tdt: DataType, exp_adt = calculate_accumulator_bit_width(inst, model) assert cur_adt.bitwidth() <= exp_adt.bitwidth(), "Mismatched accumulation data types" - # if there is no activation, outputDataType = accDataType + # if there is no activation, outputDataType = accDataType and if it is the last node + # it needs to be divisible by 8 if inst.get_nodeattr("noActivation"): assert ( cur_adt.bitwidth() == cur_odt.bitwidth() ), "outputDataType and accDataType should be equal" + if model.find_direct_successors(inst.onnx_node) is None: + assert ( + cur_adt.bitwidth() % 8 + ) == 0, "bit width of last node needs to be divisible by 8" From f52871dfe71df725ef85eeb66b6ff9ca7dff1d2d Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 4 Aug 2023 17:11:37 +0100 Subject: [PATCH 255/665] [Custom Op] Delete obsolete lines after merging with dev --- src/finn/custom_op/fpgadataflow/vectorvectoractivation.py | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index db31090f44..bd5bb75f1d 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -184,8 +184,6 @@ def minimize_accumulator_width(self, model): adt = DataType[new_adt_name] # for no-activation nodes, output dt = acc dt self.set_nodeattr("outputDataType", adt.name) - if self.get_nodeattr("noActivation"): - self.set_nodeattr("outputDataType", adt.name) self.set_nodeattr("accDataType", adt.name) return DataType[self.get_nodeattr("accDataType")] From 8357c102633a1ce25666f600d30b66ad6f94dfdf Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 8 Aug 2023 10:42:52 +0100 Subject: [PATCH 256/665] [Lint] Run pre-commit over files --- docker/jenkins/test_bnn_hw_pytest.py | 76 +++++++++++++++++------ tests/end2end/test_end2end_bnn_pynq.py | 83 +++++++++++++++++++------- 2 files changed, 122 insertions(+), 37 deletions(-) diff --git a/docker/jenkins/test_bnn_hw_pytest.py b/docker/jenkins/test_bnn_hw_pytest.py index 961efd1cc1..c8f4fbf74d 100755 --- a/docker/jenkins/test_bnn_hw_pytest.py +++ b/docker/jenkins/test_bnn_hw_pytest.py @@ -1,14 +1,15 @@ -import os -import numpy as np -from scipy.stats import linregress -import subprocess import pytest + import itertools import logging +import numpy as np +import os +import subprocess +from scipy.stats import linregress # no __init__ constructors allowed in Pytest - so use global variables instead base_dir_global = os.getcwd() -default_test_run_timeout = 30 # seconds +default_test_run_timeout = 30 # seconds output_execute_results_file = "output.npy" execute_results_reference_file = "output_reference.npy" output_throughput_results_file = "nw_metrics.txt" @@ -18,13 +19,14 @@ def remove_cache_dirs(dir_list): tmp_list = list(dir_list) - for i in range(len(tmp_list)-1, -1, -1): + for i in range(len(tmp_list) - 1, -1, -1): if ".pytest_cache" in tmp_list[i]: del tmp_list[i] elif "__pycache__" in tmp_list[i]: del tmp_list[i] return tmp_list + def delete_file(file_path): # Check if the file exists before deleting it if os.path.exists(file_path): @@ -36,16 +38,21 @@ def delete_file(file_path): else: logger.info(f"File '{file_path}' does not exist. Continuing with the script.") + def get_platform(board_str): return "alveo" if "U250" in board_str else "zynq-iodma" + def get_full_parameterized_test_list(marker, test_dir_list, batch_size_list, platform_list): test_cases = [ - (f'{marker}_{param1}_batchSize-{param2}_platform-{param3}', { - 'test_dir': param1, - 'batch_size': param2, - 'platform': param3, - }) + ( + f"{marker}_{param1}_batchSize-{param2}_platform-{param3}", + { + "test_dir": param1, + "batch_size": param2, + "platform": param3, + }, + ) for param1, param2, param3 in itertools.product( test_dir_list, batch_size_list, @@ -54,6 +61,7 @@ def get_full_parameterized_test_list(marker, test_dir_list, batch_size_list, pla ] return test_cases + def pytest_generate_tests(metafunc): idlist = [] argvalues = [] @@ -61,15 +69,21 @@ def pytest_generate_tests(metafunc): # Separate the full list of markers used on command line. # This allows a user to select multiple markers - all_markers_used = metafunc.config.getoption("-m").split(" ") + all_markers_used = metafunc.config.getoption("-m").split(" ") current_dir = os.getcwd() - test_dirs = [name for name in os.listdir(current_dir) if os.path.isdir(os.path.join(current_dir, name))] + test_dirs = [ + name for name in os.listdir(current_dir) if os.path.isdir(os.path.join(current_dir, name)) + ] test_dirs = remove_cache_dirs(test_dirs) for marker in all_markers_used: if "Pynq" in marker or "U250" in marker or "ZCU104" in marker or "KV260_SOM" in marker: platform = get_platform(marker) - scenarios.extend(get_full_parameterized_test_list(marker, test_dir_list=test_dirs, batch_size_list=[1], platform_list=[platform])) + scenarios.extend( + get_full_parameterized_test_list( + marker, test_dir_list=test_dirs, batch_size_list=[1], platform_list=[platform] + ) + ) if len(scenarios) > 0: for scenario in scenarios: @@ -92,7 +106,21 @@ def test_type_execute(self, test_dir, batch_size, platform): # Run test option: execute bitfile = "a.xclbin" if platform == "alveo" else "resizer.bit" - result = subprocess.run(["python", "driver.py", "--exec_mode=execute", f"--batchsize={batch_size}", f"--bitfile={bitfile}", "--inputfile=input.npy", "--outputfile=output.npy", f"--platform={platform}"], capture_output=True, text=True, timeout=default_test_run_timeout) + result = subprocess.run( + [ + "python", + "driver.py", + "--exec_mode=execute", + f"--batchsize={batch_size}", + f"--bitfile={bitfile}", + "--inputfile=input.npy", + "--outputfile=output.npy", + f"--platform={platform}", + ], + capture_output=True, + text=True, + timeout=default_test_run_timeout, + ) assert result.returncode == 0 # Load the output and reference arrays @@ -112,7 +140,21 @@ def test_type_throughput(self, test_dir, batch_size, platform): # Run test option: throughput bitfile = "a.xclbin" if platform == "alveo" else "resizer.bit" - result = subprocess.run(["python", "driver.py", "--exec_mode=throughput_test", f"--batchsize={batch_size}", f"--bitfile={bitfile}", "--inputfile=input.npy", "--outputfile=output.npy", f"--platform={platform}"], capture_output=True, text=True, timeout=default_test_run_timeout) + result = subprocess.run( + [ + "python", + "driver.py", + "--exec_mode=throughput_test", + f"--batchsize={batch_size}", + f"--bitfile={bitfile}", + "--inputfile=input.npy", + "--outputfile=output.npy", + f"--platform={platform}", + ], + capture_output=True, + text=True, + timeout=default_test_run_timeout, + ) assert result.returncode == 0 # Check if nw_metrics.txt now exists after test run @@ -158,7 +200,7 @@ def test_type_throughput(self, test_dir, batch_size, platform): np.round(v["DRAM_out_bandwidth[MB/s]"], 2), ) ret_str += "\n" + "-----------------------------" - largest_bsize = bsize_range[-1] + # largest_bsize = bsize_range[-1] # Dump the metrics to a text file with open(throughput_results_formatted_file, "w") as f: diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index 59fbb0c1cb..07e977a266 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -28,9 +28,8 @@ import pytest -import numpy as np - import itertools +import numpy as np # as of Feb'20 there is a bug that segfaults ONNX shape inference if we # import pytorch before onnx, so we make sure to import onnx first @@ -41,7 +40,6 @@ from brevitas.export import export_qonnx from dataset_loading import cifar, mnist from distutils.dir_util import copy_tree -from shutil import copy from qonnx.core.datatype import DataType from qonnx.core.modelwrapper import ModelWrapper from qonnx.custom_op.registry import getCustomOp @@ -60,6 +58,7 @@ from qonnx.transformation.lower_convs_to_matmul import LowerConvsToMatMul from qonnx.transformation.merge_onnx_models import MergeONNXModels from qonnx.util.cleanup import cleanup as qonnx_cleanup +from shutil import copy import finn.transformation.fpgadataflow.convert_to_hls_layers as to_hls import finn.transformation.streamline.absorb as absorb @@ -348,12 +347,15 @@ def deploy_based_on_board(model, model_title, topology, wbits, abits, board): # parameters that make up inputs to test case(s) def get_full_parameterized_test_list(marker, wbits_list, abits_list, topology_list, board_list): test_cases = [ - (f'{marker}_w{param1}_a{param2}_{param3}_{param4}', { - 'wbits': param1, - 'abits': param2, - 'topology': param3, - 'board': param4, - }) + ( + f"{marker}_w{param1}_a{param2}_{param3}_{param4}", + { + "wbits": param1, + "abits": param2, + "topology": param3, + "board": param4, + }, + ) for param1, param2, param3, param4 in itertools.product( wbits_list, abits_list, @@ -376,21 +378,63 @@ def pytest_generate_tests(metafunc): # Separate the full list of markers used on command line. # This allows a user to select multiple markers - all_markers_used = metafunc.config.getoption("-m").split(" ") + all_markers_used = metafunc.config.getoption("-m").split(" ") for marker in all_markers_used: if "sanity_bnn" in marker: - # Define a set of sanity tests that target each of the supported boards with fixed parameters - scenarios.extend(get_full_parameterized_test_list("sanity_bnn", wbits_list=[1], abits_list=[1], topology_list=["lfc"], board_list=[test_support_board_map[0]])) - scenarios.extend(get_full_parameterized_test_list("sanity_bnn", wbits_list=[1], abits_list=[2], topology_list=["cnv"], board_list=[test_support_board_map[1]])) - scenarios.extend(get_full_parameterized_test_list("sanity_bnn", wbits_list=[2], abits_list=[2], topology_list=["tfc"], board_list=[test_support_board_map[2]])) - scenarios.extend(get_full_parameterized_test_list("sanity_bnn", wbits_list=[2], abits_list=[2], topology_list=["cnv"], board_list=[test_support_board_map[3]])) + # Define a set of sanity tests that target each of + # the supported boards with fixed parameters + scenarios.extend( + get_full_parameterized_test_list( + "sanity_bnn", + wbits_list=[1], + abits_list=[1], + topology_list=["lfc"], + board_list=[test_support_board_map[0]], + ) + ) + scenarios.extend( + get_full_parameterized_test_list( + "sanity_bnn", + wbits_list=[1], + abits_list=[2], + topology_list=["cnv"], + board_list=[test_support_board_map[1]], + ) + ) + scenarios.extend( + get_full_parameterized_test_list( + "sanity_bnn", + wbits_list=[2], + abits_list=[2], + topology_list=["tfc"], + board_list=[test_support_board_map[2]], + ) + ) + scenarios.extend( + get_full_parameterized_test_list( + "sanity_bnn", + wbits_list=[2], + abits_list=[2], + topology_list=["cnv"], + board_list=[test_support_board_map[3]], + ) + ) if "bnn_" in marker: # Target the full set of parameters for a single board # Extract the board name from the marker used, as it is in the form of 'bnn_' - bnn_board = next((element for element in test_support_board_map if marker.split("_")[1] in element.lower()), None) - test_cases = get_full_parameterized_test_list("bnn", wbits, abits, topology, [bnn_board]) + bnn_board = next( + ( + element + for element in test_support_board_map + if marker.split("_")[1] in element.lower() + ), + None, + ) + test_cases = get_full_parameterized_test_list( + "bnn", wbits, abits, topology, [bnn_board] + ) scenarios.extend(test_cases) if len(scenarios) > 0: @@ -401,6 +445,7 @@ def pytest_generate_tests(metafunc): argvalues.append([x[1] for x in items]) metafunc.parametrize(argnames, argvalues, ids=idlist, scope="class") + @pytest.mark.sanity_bnn @pytest.mark.bnn_pynq @pytest.mark.bnn_zcu104 @@ -706,9 +751,7 @@ def test_make_pynq_driver(self, topology, wbits, abits, board): model.save(get_checkpoint_name(topology, wbits, abits, "driver_" + board)) def test_deploy(self, topology, wbits, abits, board): - prev_chkpt_name = get_checkpoint_name( - topology, wbits, abits, "driver_" + board - ) + prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, "driver_" + board) model = load_test_checkpoint_or_skip(prev_chkpt_name) model_title = "%s_w%d_a%d_%s" % ("bnn", wbits, abits, topology) deploy_based_on_board(model, model_title, topology, wbits, abits, board) From 3df0c17191cafd2c5e90f0aa2f310626b1297e67 Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 8 Aug 2023 11:39:08 +0100 Subject: [PATCH 257/665] [GHA] exclude bnn_pynq from quicktest --- docker/quicktest.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docker/quicktest.sh b/docker/quicktest.sh index 466fcfb09d..814cec03d1 100755 --- a/docker/quicktest.sh +++ b/docker/quicktest.sh @@ -6,7 +6,7 @@ cd $FINN_ROOT # check if command line argument is empty or not present if [ -z $1 ]; then echo "Running quicktest: not (vivado or slow or board) with pytest-xdist" - python setup.py test --addopts "-m 'not (vivado or slow or vitis or board or notebooks)' --dist=loadfile -n $PYTEST_PARALLEL" + python setup.py test --addopts "-m 'not (vivado or slow or vitis or board or notebooks or bnn_pynq)' --dist=loadfile -n $PYTEST_PARALLEL" elif [ $1 = "main" ]; then echo "Running main test suite: not (rtlsim or end2end) with pytest-xdist" python setup.py test --addopts "-k 'not (rtlsim or end2end)' --dist=loadfile -n $PYTEST_PARALLEL" From 066d0277ff70bb7cf990baacc563788467a5c836 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 9 Aug 2023 14:34:29 +0100 Subject: [PATCH 258/665] [CI] Split Jenkinsfiles into CI and testing --- docker/jenkins/Jenkinsfile_CI | 46 +++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 docker/jenkins/Jenkinsfile_CI diff --git a/docker/jenkins/Jenkinsfile_CI b/docker/jenkins/Jenkinsfile_CI new file mode 100644 index 0000000000..2954877c2a --- /dev/null +++ b/docker/jenkins/Jenkinsfile_CI @@ -0,0 +1,46 @@ +node { + def app + stage('Clone repository') { + /* Let's make sure we have the repository cloned to our workspace */ + checkout scm + } + withEnv([ + "FINN_XILINX_PATH=/proj/xbuilds/SWIP/2022.2_1014_8888/installs/lin64", + "FINN_XILINX_VERSION=2022.2", + "FINN_DOCKER_TAG=xilinx/finn:jenkins", + "FINN_HOST_BUILD_DIR=/scratch/users/finn_ci", + "PLATFORM_REPO_PATHS=/opt/xilinx/platforms" + ]){ + parallel firstBranch: { + stage('Brevitas export') { + dir("${env.WORKSPACE}") { + sh("bash run-docker.sh python setup.py test --addopts -mbrevitas_export") + } + } + }, secondBranch: { + stage('Streamlining transformations') { + dir("${env.WORKSPACE}") { + sh("bash run-docker.sh python setup.py test --addopts -mstreamline") + } + } + }, thirdBranch: { + stage('Util functions') { + dir("${env.WORKSPACE}") { + sh("bash run-docker.sh python setup.py test --addopts -mutil") + } + } + }, fourthBranch: { + stage('General transformations') { + dir("${env.WORKSPACE}") { + sh("bash run-docker.sh python setup.py test --addopts -mtransform") + } + } + }, fifthBranch: { + stage('Fpgadataflow transformations and simulations') { + dir("${env.WORKSPACE}") { + sh("bash run-docker.sh python setup.py test --addopts -mfpgadataflow") + } + } + } + } +} From 6f84ed9466f5cc8ef1041236c0c3369b786a90dc Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 9 Aug 2023 14:44:51 +0100 Subject: [PATCH 259/665] [Tests] Rename board map for tests --- src/finn/util/basic.py | 4 ++-- tests/end2end/test_end2end_bnn_pynq.py | 16 ++++++---------- 2 files changed, 8 insertions(+), 12 deletions(-) diff --git a/src/finn/util/basic.py b/src/finn/util/basic.py index 7dd04996ba..a184a53862 100644 --- a/src/finn/util/basic.py +++ b/src/finn/util/basic.py @@ -31,8 +31,8 @@ import sys import tempfile -# supported boards -test_support_board_map = ["Pynq-Z1", "KV260_SOM", "ZCU104", "U250"] +# test boards +test_board_map = ["Pynq-Z1", "KV260_SOM", "ZCU104", "U250"] # mapping from PYNQ board names to FPGA part names pynq_part_map = dict() diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index 07e977a266..0343b9082b 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -92,7 +92,7 @@ MakeMaxPoolNHWC, MoveScalarLinearPastInvariants, ) -from finn.util.basic import get_finn_root, make_build_dir, test_support_board_map +from finn.util.basic import get_finn_root, make_build_dir, test_board_map from finn.util.pytorch import ToTensor from finn.util.test import ( execute_parent, @@ -390,7 +390,7 @@ def pytest_generate_tests(metafunc): wbits_list=[1], abits_list=[1], topology_list=["lfc"], - board_list=[test_support_board_map[0]], + board_list=[test_board_map[0]], ) ) scenarios.extend( @@ -399,7 +399,7 @@ def pytest_generate_tests(metafunc): wbits_list=[1], abits_list=[2], topology_list=["cnv"], - board_list=[test_support_board_map[1]], + board_list=[test_board_map[1]], ) ) scenarios.extend( @@ -408,7 +408,7 @@ def pytest_generate_tests(metafunc): wbits_list=[2], abits_list=[2], topology_list=["tfc"], - board_list=[test_support_board_map[2]], + board_list=[test_board_map[2]], ) ) scenarios.extend( @@ -417,7 +417,7 @@ def pytest_generate_tests(metafunc): wbits_list=[2], abits_list=[2], topology_list=["cnv"], - board_list=[test_support_board_map[3]], + board_list=[test_board_map[3]], ) ) @@ -425,11 +425,7 @@ def pytest_generate_tests(metafunc): # Target the full set of parameters for a single board # Extract the board name from the marker used, as it is in the form of 'bnn_' bnn_board = next( - ( - element - for element in test_support_board_map - if marker.split("_")[1] in element.lower() - ), + (element for element in test_board_map if marker.split("_")[1] in element.lower()), None, ) test_cases = get_full_parameterized_test_list( From e080625d0b41f1ad8972ab2b1bf7b0ae899be174 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 9 Aug 2023 17:16:09 +0100 Subject: [PATCH 260/665] [Tests] Fix bug in reshaping input npy for remote execution --- tests/end2end/test_end2end_bnn_pynq.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index 0343b9082b..d98c06f7d0 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -333,7 +333,8 @@ def deploy_based_on_board(model, model_title, topology, wbits, abits, board): input_tensor_npy = input_tensor_npy.transpose(0, 3, 2, 1) else: input_shape = input_tensor_npy.shape - input_tensor_npy = (input_shape[0], np.prod(input_shape[1:])) + new_input_shape = (input_shape[0], np.prod(input_shape[1:])) + input_tensor_npy = input_tensor_npy.reshape(new_input_shape) np.save(os.path.join(deployment_dir, "input.npy"), input_tensor_npy.copy()) np.save(os.path.join(deployment_dir, "output_reference.npy"), output_tensor_npy) From 7486217214047068b8bba4e734970b375dbca40c Mon Sep 17 00:00:00 2001 From: hlebleve Date: Thu, 17 Aug 2023 11:17:39 +0200 Subject: [PATCH 261/665] Updating QONNX qnd FINN-HLSIB repo versions to match dependencies --- fetch-repos.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fetch-repos.sh b/fetch-repos.sh index 9e3ee3ef99..45cedff678 100755 --- a/fetch-repos.sh +++ b/fetch-repos.sh @@ -27,12 +27,12 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -QONNX_COMMIT="8755423377e9c01dd2d2358c320484399b5d6625" +QONNX_COMMIT="ca897bc6e972d94ef158f1d87cc84e29fd0133f3" FINN_EXP_COMMIT="0aa7e1c44b20cf085b6fe42cff360f0a832afd2c" BREVITAS_COMMIT="9bb26bf2798de210a267d1e4aed4c20087e0e8a5" PYVERILATOR_COMMIT="766e457465f5c0dd315490d7b9cc5d74f9a76f4f" CNPY_COMMIT="4e8810b1a8637695171ed346ce68f6984e585ef4" -HLSLIB_COMMIT="c17aa478ae574971d115afa9fa4d9c215857d1ac" +HLSLIB_COMMIT="a77a7462286bc09e6e30e4c0185a0699d5704213" OMX_COMMIT="0b59762f9e4c4f7e5aa535ee9bc29f292434ca7a" AVNET_BDF_COMMIT="2d49cfc25766f07792c0b314489f21fe916b639b" XIL_BDF_COMMIT="8cf4bb674a919ac34e3d99d8d71a9e60af93d14e" From 9a411ec1e7aee9c40245e48b2f480f6b3743a26c Mon Sep 17 00:00:00 2001 From: hlebleve Date: Thu, 17 Aug 2023 16:39:44 +0200 Subject: [PATCH 262/665] Updating QONNX qnd FINN-HLSIB repo versions to match dependencies --- fetch-repos.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fetch-repos.sh b/fetch-repos.sh index 45cedff678..a88ebae1c3 100755 --- a/fetch-repos.sh +++ b/fetch-repos.sh @@ -32,7 +32,7 @@ FINN_EXP_COMMIT="0aa7e1c44b20cf085b6fe42cff360f0a832afd2c" BREVITAS_COMMIT="9bb26bf2798de210a267d1e4aed4c20087e0e8a5" PYVERILATOR_COMMIT="766e457465f5c0dd315490d7b9cc5d74f9a76f4f" CNPY_COMMIT="4e8810b1a8637695171ed346ce68f6984e585ef4" -HLSLIB_COMMIT="a77a7462286bc09e6e30e4c0185a0699d5704213" +HLSLIB_COMMIT="16e5847a5e3ef76cffe84c8fad2f010d593457d3" OMX_COMMIT="0b59762f9e4c4f7e5aa535ee9bc29f292434ca7a" AVNET_BDF_COMMIT="2d49cfc25766f07792c0b314489f21fe916b639b" XIL_BDF_COMMIT="8cf4bb674a919ac34e3d99d8d71a9e60af93d14e" From fe09f06d9cf35994269db2f667472167f05d6165 Mon Sep 17 00:00:00 2001 From: johnnoel Date: Wed, 23 Aug 2023 09:51:42 +0100 Subject: [PATCH 263/665] [CI] Fix bug with build parameters and result flags sharing common names --- docker/jenkins/Jenkinsfile | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index 7ca9aedafc..f4f0533c3f 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -96,7 +96,7 @@ pipeline { stash name: env.TEST_NAME, includes: "${env.TEST_NAME}.xml,${env.TEST_NAME}.html" // Use an env variable to help collect test results later in pipeline - env.FPGADATAFLOW = "SUCCESS" + env.FPGADATAFLOW_RESULT = "SUCCESS" } } } @@ -129,7 +129,7 @@ pipeline { stash name: env.TEST_NAME, includes: "${env.TEST_NAME}.xml,${env.TEST_NAME}.html" // Use an env variable to help collect test results later in pipeline - env.END2END = "SUCCESS" + env.END2END_RESULT = "SUCCESS" } } } @@ -705,13 +705,13 @@ pipeline { dir('reports') { // Only unstash for stages that ran unstashSuccessfulStage(env.SANITY_UT, "sanity_ut") - unstashSuccessfulStage(env.FPGADATAFLOW, "fpgadataflow") + unstashSuccessfulStage(env.FPGADATAFLOW_RESULT, "fpgadataflow") unstashSuccessfulStage(env.BNN_BUILD_SANITY, "bnn_build_sanity") unstashSuccessfulStage(env.SANITY_BNN_TEST_U250, "xml_sanity_bnn_test_U250") unstashSuccessfulStage(env.SANITY_BNN_TEST_PYNQZ1, "xml_sanity_bnn_test_PynqZ1") unstashSuccessfulStage(env.SANITY_BNN_TEST_ZCU104, "xml_sanity_bnn_test_ZCU104") unstashSuccessfulStage(env.SANITY_BNN_TEST_KV260_SOM, "xml_sanity_bnn_test_KV260_SOM") - unstashSuccessfulStage(env.END2END, "end2end") + unstashSuccessfulStage(env.END2END_RESULT, "end2end") unstashSuccessfulStage(env.BNN_BUILD_U250, "bnn_build_full_U250") unstashSuccessfulStage(env.BNN_BUILD_PYNQZ1, "bnn_build_full_PynqZ1") unstashSuccessfulStage(env.BNN_BUILD_ZCU104, "bnn_build_full_ZCU104") @@ -730,7 +730,7 @@ pipeline { archiveArtifacts artifacts: "reports/*.html" archiveSuccessfulStage(env.SANITY_UT, "coverage_sanity_ut") - archiveSuccessfulStage(env.FPGADATAFLOW, "coverage_fpgadataflow") + archiveSuccessfulStage(env.FPGADATAFLOW_RESULT, "coverage_fpgadataflow") // Plot what XML files were created during the test run junit 'reports/*.xml' From db99ec811957310b68c5818e506c3374402dd16f Mon Sep 17 00:00:00 2001 From: johnnoel Date: Wed, 2 Aug 2023 11:13:31 +0100 Subject: [PATCH 264/665] Add support to pull in a .Xilinx directory to allow beta devices to be enabled inside docker container See https://docs.xilinx.com/r/en-US/ug835-vivado-tcl-commands/Tcl-Initialization-Scripts for information on using tcl init scripts --- docker/finn_entrypoint.sh | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/docker/finn_entrypoint.sh b/docker/finn_entrypoint.sh index 4e0266ca6b..b441c9359a 100644 --- a/docker/finn_entrypoint.sh +++ b/docker/finn_entrypoint.sh @@ -114,6 +114,27 @@ else yecho "If you need Vitis HLS, ensure HLS_PATH is set correctly and mounted into the Docker container." fi +if [ -d "$FINN_ROOT/.Xilinx" ]; then + mkdir "$HOME/.Xilinx" + if [ -f "$FINN_ROOT/.Xilinx/HLS_init.tcl" ]; then + cp "$FINN_ROOT/.Xilinx/HLS_init.tcl" "$HOME/.Xilinx/" + else + yecho "Unable to find $FINN_ROOT/.Xilinx/HLS_init.tcl" + fi + + if [ -f "$FINN_ROOT/.Xilinx/Vivado/Vivado_init.tcl" ]; then + mkdir "$HOME/.Xilinx/Vivado/" + cp "$FINN_ROOT/.Xilinx/Vivado/Vivado_init.tcl" "$HOME/.Xilinx/Vivado/" + else + yecho "Unable to find $FINN_ROOT/.Xilinx/Vivado/Vivado_init.tcl" + fi +else + yecho "Unable to find $FINN_ROOT/.Xilinx" + yecho "Functionality dependent on beta devices will not be available." + yecho "If you need to enable a beta device, ensure .Xilinx/HLS_init.tcl and/or .Xilinx/Vivado/Vivado_init.tcl " + yecho "are set correctly and mounted into the Docker container." +fi + export PATH=$PATH:$HOME/.local/bin # execute the provided command(s) as root exec "$@" From 26e3306796d3d0daac94b87c9d4d01676ecf134e Mon Sep 17 00:00:00 2001 From: auphelia Date: Thu, 24 Aug 2023 15:40:48 +0100 Subject: [PATCH 265/665] [NBs] Add first draft of advanced builder settings notebook --- .../4_advanced_builder_settings.ipynb | 789 ++++++++++++++++++ 1 file changed, 789 insertions(+) create mode 100644 notebooks/advanced/4_advanced_builder_settings.ipynb diff --git a/notebooks/advanced/4_advanced_builder_settings.ipynb b/notebooks/advanced/4_advanced_builder_settings.ipynb new file mode 100644 index 0000000000..ce02ab618e --- /dev/null +++ b/notebooks/advanced/4_advanced_builder_settings.ipynb @@ -0,0 +1,789 @@ +{ + "cells": [ + { + "cell_type": "markdown", + "id": "8fcff912", + "metadata": {}, + "source": [ + "# Advanced Builder settings\n", + "\n", + "**Live FINN tutorial:** We recommend clicking **Cell -> Run All** when you start reading this notebook for \"latency hiding\".\n", + "\n", + "\"drawing\"\n", + "\n", + "In this notebook, we'll use the FINN compiler to generate an FPGA accelerator with a streaming dataflow architecture from small convolutional network trained on CIFAR-10. The key idea in such architectures is to parallelize across layers as well as within layers by dedicating a proportionate amount of compute resources to each layer, illustrated on the figure to the left. You can read more about the general concept in the [FINN](https://arxiv.org/pdf/1612.07119) and [FINN-R](https://dl.acm.org/doi/pdf/10.1145/3242897) papers. This is done by mapping each layer to a Vitis HLS description, parallelizing each layer's implementation to the appropriate degree and using on-chip FIFOs to link up the layers to create the full accelerator.\n", + "\n", + "These implementations offer a good balance of performance and flexibility, but building them by hand is difficult and time-consuming. This is where the FINN compiler comes in: it can build streaming dataflow accelerators from an ONNX description to match the desired throughput." + ] + }, + { + "cell_type": "markdown", + "id": "a830e730", + "metadata": {}, + "source": [ + "In this tutorial, we will have a more detailed look into the FINN builder tool and explore different options to customize your FINN design. We assume that you have already completed the [Cybersecurity notebooks](../end2end_example/cybersecurity) and that you have a basic understanding of how the FINN compiler works and how to use the FINN builder tool." + ] + }, + { + "cell_type": "markdown", + "id": "5ec9a0db", + "metadata": {}, + "source": [ + "## Outline\n", + "---------------\n", + "\n", + "1. [Introduction to the CNV-w2a2 network](#intro_cnv)\n", + "2. [Recap default builder flow](#recap_builder)\n", + "3. [How to make a custom build step](#custom_step)\n", + "4. [Folding configuration json](#folding_config)\n", + "5. [Additional builder arguments](#builder_arg)\n", + " 1. [Verification steps](#verify)\n", + " 2. [Examples for additional builder arguments](#example_args)\n", + " 3. [Other builder arguments](#other_args)" + ] + }, + { + "cell_type": "markdown", + "id": "5dbed63f", + "metadata": {}, + "source": [ + "## Introduction to the CNV-w2a2 network \n", + "\n", + "The particular quantized neural network (QNN) we will be targeting in this notebook is referred to as CNV-w2a2 and it classifies 32x32 RGB images into one of ten CIFAR-10 classes. All weights and activations in this network are quantized to two bit, with the exception of the input (which is RGB with 8 bits per channel) and the final output (which is 32-bit numbers). It is similar to the convolutional neural network used in the [cnv_end2end_example](../end2end_example/bnn-pynq/cnv_end2end_example.ipynb) Jupyter notebook.\n", + "\n", + "\n", + "You'll have a chance to interactively examine the layers that make up the network in Netron in a moment, so that's enough about the network for now. \n" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "ce459f3c", + "metadata": {}, + "outputs": [], + "source": [ + "from finn.util.basic import make_build_dir\n", + "from finn.util.visualization import showInNetron, showSrc\n", + "import os\n", + " \n", + "build_dir = os.environ['FINN_ROOT'] + \"/notebooks/advanced\"" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "fe262964", + "metadata": {}, + "outputs": [], + "source": [ + "import torch\n", + "from finn.util.test import get_test_model_trained\n", + "from brevitas.export import export_qonnx\n", + "from qonnx.util.cleanup import cleanup as qonnx_cleanup\n", + "from qonnx.core.modelwrapper import ModelWrapper\n", + "from qonnx.core.datatype import DataType\n", + "\n", + "cnv = get_test_model_trained(\"CNV\", 2, 2)\n", + "export_onnx_path = build_dir + \"/end2end_cnv_w2a2_export.onnx\"\n", + "export_qonnx(cnv, torch.randn(1, 3, 32, 32), export_onnx_path)\n", + "qonnx_cleanup(export_onnx_path, out_file=export_onnx_path)\n", + "#model = ModelWrapper(export_onnx_path)\n", + "#model.set_tensor_datatype(model.graph.input[0].name, DataType[\"UINT8\"])\n", + "#model.save(build_dir + \"/end2end_cnv_w2a2_tidy.onnx\")" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "87f59da6", + "metadata": {}, + "outputs": [], + "source": [ + "showInNetron(build_dir+\"/end2end_cnv_w2a2_export.onnx\")" + ] + }, + { + "cell_type": "markdown", + "id": "c764ed76", + "metadata": {}, + "source": [ + "## Quick recap, how to setup up default builder flow for resource estimations " + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "9007705a", + "metadata": {}, + "outputs": [], + "source": [ + "import finn.builder.build_dataflow as build\n", + "import finn.builder.build_dataflow_config as build_cfg\n", + "import os\n", + "import shutil\n", + "\n", + "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/advanced\"\n", + "model_file = model_dir + \"/end2end_cnv_w2a2_export.onnx\"\n", + "\n", + "estimates_output_dir = \"output_estimates_only\"\n", + "\n", + "#Delete previous run results if exist\n", + "if os.path.exists(estimates_output_dir):\n", + " shutil.rmtree(estimates_output_dir)\n", + " print(\"Previous run results deleted!\")\n", + "\n", + "\n", + "cfg_estimates = build.DataflowBuildConfig(\n", + " output_dir = estimates_output_dir,\n", + " mvau_wwidth_max = 80,\n", + " target_fps = 1000000,\n", + " synth_clk_period_ns = 10.0,\n", + " fpga_part = \"xc7z020clg400-1\",\n", + " steps = build_cfg.estimate_only_dataflow_steps,\n", + " generate_outputs=[\n", + " build_cfg.DataflowOutputType.ESTIMATE_REPORTS,\n", + " ]\n", + ")" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "02e4c0f0", + "metadata": {}, + "outputs": [], + "source": [ + "%%time\n", + "build.build_dataflow_cfg(model_file, cfg_estimates)" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "72de8d4c", + "metadata": {}, + "outputs": [], + "source": [ + "showInNetron(build_dir+\"/output_estimates_only/intermediate_models/step_convert_to_hls.onnx\")" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "f3fe1186", + "metadata": {}, + "outputs": [], + "source": [ + "print(\"\\n\".join(build_cfg.estimate_only_dataflow_steps))" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "029da0da", + "metadata": {}, + "outputs": [], + "source": [ + "import finn.builder.build_dataflow_steps as build_dataflow_steps\n", + "showSrc(build_dataflow_steps.step_tidy_up)" + ] + }, + { + "cell_type": "markdown", + "id": "e9c2c97f", + "metadata": {}, + "source": [ + "## How to make a custom build step " + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "b9d43cc8", + "metadata": {}, + "outputs": [], + "source": [ + "from finn.util.pytorch import ToTensor\n", + "from qonnx.transformation.merge_onnx_models import MergeONNXModels\n", + "\n", + "def custom_step_add_pre_proc(model: ModelWrapper, cfg: build.DataflowBuildConfig):\n", + " ishape = model.get_tensor_shape(model.graph.input[0].name)\n", + " # preprocessing: torchvision's ToTensor divides uint8 inputs by 255\n", + " preproc = ToTensor()\n", + " export_qonnx(preproc, torch.randn(ishape), \"preproc.onnx\", opset_version=11)\n", + " preproc_model = ModelWrapper(\"preproc.onnx\")\n", + " # set input finn datatype to UINT8\n", + " preproc_model.set_tensor_datatype(preproc_model.graph.input[0].name, DataType[\"UINT8\"])\n", + " model = model.transform(MergeONNXModels(preproc_model))\n", + " return model\n", + " " + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "6f00b465", + "metadata": {}, + "outputs": [], + "source": [ + "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/advanced\"\n", + "model_file = model_dir + \"/end2end_cnv_w2a2_export.onnx\"\n", + "\n", + "estimates_output_dir = \"output_pre_proc\"\n", + "\n", + "#Delete previous run results if exist\n", + "if os.path.exists(estimates_output_dir):\n", + " shutil.rmtree(estimates_output_dir)\n", + " print(\"Previous run results deleted!\")\n", + "\n", + "build_steps = [\n", + " custom_step_add_pre_proc,\n", + " \"step_qonnx_to_finn\",\n", + " \"step_tidy_up\",\n", + " \"step_streamline\",\n", + " \"step_convert_to_hls\",\n", + " \"step_create_dataflow_partition\",\n", + " \"step_target_fps_parallelization\",\n", + " \"step_apply_folding_config\",\n", + " \"step_minimize_bit_width\",\n", + " \"step_generate_estimate_reports\",\n", + "]\n", + "\n", + "cfg_estimates = build.DataflowBuildConfig(\n", + " output_dir = estimates_output_dir,\n", + " mvau_wwidth_max = 80,\n", + " target_fps = 1000000,\n", + " synth_clk_period_ns = 10.0,\n", + " fpga_part = \"xc7z020clg400-1\",\n", + " steps = build_steps,\n", + " generate_outputs=[\n", + " build_cfg.DataflowOutputType.ESTIMATE_REPORTS,\n", + " ]\n", + ")" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "d3a2bcea", + "metadata": {}, + "outputs": [], + "source": [ + "%%time\n", + "build.build_dataflow_cfg(model_file, cfg_estimates)" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "87e5651e", + "metadata": {}, + "outputs": [], + "source": [ + "showInNetron(build_dir+\"/output_pre_proc/intermediate_models/custom_step_add_pre_proc.onnx\")" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "8c6f1bd0", + "metadata": {}, + "outputs": [], + "source": [ + "from qonnx.transformation.insert_topk import InsertTopK\n", + "\n", + "def custom_step_add_post_proc(model: ModelWrapper, cfg: build.DataflowBuildConfig):\n", + " model = model.transform(InsertTopK(k=1))\n", + " return model" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "57adbb44", + "metadata": {}, + "outputs": [], + "source": [ + "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/advanced\"\n", + "model_file = model_dir + \"/end2end_cnv_w2a2_export.onnx\"\n", + "\n", + "estimates_output_dir = \"output_pre_and_post_proc\"\n", + "\n", + "#Delete previous run results if exist\n", + "if os.path.exists(estimates_output_dir):\n", + " shutil.rmtree(estimates_output_dir)\n", + " print(\"Previous run results deleted!\")\n", + "\n", + "build_steps = [\n", + " custom_step_add_pre_proc,\n", + " custom_step_add_post_proc,\n", + " \"step_qonnx_to_finn\",\n", + " \"step_tidy_up\",\n", + " \"step_streamline\",\n", + " \"step_convert_to_hls\",\n", + " \"step_create_dataflow_partition\",\n", + " \"step_target_fps_parallelization\",\n", + " \"step_apply_folding_config\",\n", + " \"step_minimize_bit_width\",\n", + " \"step_generate_estimate_reports\",\n", + "]\n", + "\n", + "cfg_estimates = build.DataflowBuildConfig(\n", + " output_dir = estimates_output_dir,\n", + " mvau_wwidth_max = 80,\n", + " target_fps = 1000000,\n", + " synth_clk_period_ns = 10.0,\n", + " fpga_part = \"xc7z020clg400-1\",\n", + " steps = build_steps,\n", + " generate_outputs=[\n", + " build_cfg.DataflowOutputType.ESTIMATE_REPORTS,\n", + " ]\n", + ")" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "b0598b81", + "metadata": {}, + "outputs": [], + "source": [ + "%%time\n", + "build.build_dataflow_cfg(model_file, cfg_estimates)" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "44127417", + "metadata": {}, + "outputs": [], + "source": [ + "showInNetron(build_dir+\"/output_pre_and_post_proc/intermediate_models/step_convert_to_hls.onnx\")" + ] + }, + { + "cell_type": "markdown", + "id": "5ffbadd1", + "metadata": {}, + "source": [ + "## Folding configuration json " + ] + }, + { + "cell_type": "markdown", + "id": "c164040f", + "metadata": {}, + "source": [ + "To learn about the influence of folding factors/parallelism in FINN, please have a look at this notebook: " + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "f75f5634", + "metadata": {}, + "outputs": [], + "source": [ + "import json\n", + "\n", + "with open(build_dir+\"/output_pre_and_post_proc/auto_folding_config.json\", 'r') as json_file:\n", + " json_object = json.load(json_file)\n", + "\n", + "print(json.dumps(json_object, indent=1))" + ] + }, + { + "cell_type": "markdown", + "id": "ba856c28", + "metadata": {}, + "source": [ + "Hardware configuration for each layer\n", + "\n", + "FIFO depths\n", + "\n", + "Type of memory/compute resources to be used\n", + "\n", + "Parallelism along different dimensions (“PE”, ”SIMD”)\n", + "\n", + "Baked-in, decoupled or external parameters\n", + "\n", + "Influences almost all flows\n", + "\n", + "step_apply_folding_config\n", + "\n", + "Values tuned for performance & footprint\n", + "\n", + "Many additional constraints not visible from .json" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "f7f42774", + "metadata": {}, + "outputs": [], + "source": [ + "with open(build_dir+\"/output_pre_and_post_proc/report/estimate_layer_resources.json\", 'r') as json_file:\n", + " json_object = json.load(json_file)\n", + "\n", + "print(json.dumps(json_object[\"total\"], indent=1))" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "cdd9f706", + "metadata": {}, + "outputs": [], + "source": [ + "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/advanced\"\n", + "model_file = model_dir + \"/end2end_cnv_w2a2_export.onnx\"\n", + "\n", + "estimates_output_dir = \"output_all_lutram\"\n", + "\n", + "#Delete previous run results if exist\n", + "if os.path.exists(estimates_output_dir):\n", + " shutil.rmtree(estimates_output_dir)\n", + " print(\"Previous run results deleted!\")\n", + "\n", + "build_steps = [\n", + " custom_step_add_pre_proc,\n", + " custom_step_add_post_proc,\n", + " \"step_qonnx_to_finn\",\n", + " \"step_tidy_up\",\n", + " \"step_streamline\",\n", + " \"step_convert_to_hls\",\n", + " \"step_create_dataflow_partition\",\n", + " \"step_apply_folding_config\",\n", + " \"step_minimize_bit_width\",\n", + " \"step_generate_estimate_reports\",\n", + "]\n", + "\n", + "cfg_estimates = build.DataflowBuildConfig(\n", + " output_dir = estimates_output_dir,\n", + " mvau_wwidth_max = 80,\n", + " synth_clk_period_ns = 10.0,\n", + " fpga_part = \"xc7z020clg400-1\",\n", + " steps = build_steps,\n", + " folding_config_file = \"folding_config_all_lutram.json\",\n", + " generate_outputs=[\n", + " build_cfg.DataflowOutputType.ESTIMATE_REPORTS,\n", + " ]\n", + ")" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "99b647c0", + "metadata": {}, + "outputs": [], + "source": [ + "%%time\n", + "build.build_dataflow_cfg(model_file, cfg_estimates)" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "cc680178", + "metadata": {}, + "outputs": [], + "source": [ + "showInNetron(build_dir+\"/output_all_lutram/intermediate_models/step_generate_estimate_reports.onnx\")" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "695ecfb1", + "metadata": {}, + "outputs": [], + "source": [ + "with open(build_dir+\"/output_all_lutram/report/estimate_layer_resources.json\", 'r') as json_file:\n", + " json_object = json.load(json_file)\n", + "\n", + "print(json.dumps(json_object[\"total\"], indent=1))" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "59e8aaaa", + "metadata": {}, + "outputs": [], + "source": [ + "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/advanced\"\n", + "model_file = model_dir + \"/end2end_cnv_w2a2_export.onnx\"\n", + "\n", + "estimates_output_dir = \"output_all_bram\"\n", + "\n", + "#Delete previous run results if exist\n", + "if os.path.exists(estimates_output_dir):\n", + " shutil.rmtree(estimates_output_dir)\n", + " print(\"Previous run results deleted!\")\n", + "\n", + "build_steps = [\n", + " custom_step_add_pre_proc,\n", + " custom_step_add_post_proc,\n", + " \"step_qonnx_to_finn\",\n", + " \"step_tidy_up\",\n", + " \"step_streamline\",\n", + " \"step_convert_to_hls\",\n", + " \"step_create_dataflow_partition\",\n", + " \"step_apply_folding_config\",\n", + " \"step_minimize_bit_width\",\n", + " \"step_generate_estimate_reports\",\n", + "]\n", + "\n", + "cfg_estimates = build.DataflowBuildConfig(\n", + " output_dir = estimates_output_dir,\n", + " mvau_wwidth_max = 80,\n", + " synth_clk_period_ns = 10.0,\n", + " fpga_part = \"xc7z020clg400-1\",\n", + " steps = build_steps,\n", + " folding_config_file = \"folding_config_all_bram.json\",\n", + " generate_outputs=[\n", + " build_cfg.DataflowOutputType.ESTIMATE_REPORTS,\n", + " ]\n", + ")" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "2cdc1aa0", + "metadata": {}, + "outputs": [], + "source": [ + "%%time\n", + "build.build_dataflow_cfg(model_file, cfg_estimates)" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "cd0388fd", + "metadata": {}, + "outputs": [], + "source": [ + "showInNetron(build_dir+\"/output_all_bram/intermediate_models/step_generate_estimate_reports.onnx\")" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "e60a3efb", + "metadata": {}, + "outputs": [], + "source": [ + "with open(build_dir+\"/output_all_bram/report/estimate_layer_resources.json\", 'r') as json_file:\n", + " json_object = json.load(json_file)\n", + "\n", + "print(json.dumps(json_object[\"total\"], indent=1))" + ] + }, + { + "cell_type": "markdown", + "id": "4a675834", + "metadata": {}, + "source": [ + "## Additional builder arguments " + ] + }, + { + "cell_type": "markdown", + "id": "e0c167f4", + "metadata": {}, + "source": [ + "### Verification steps " + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "4fe7318e", + "metadata": {}, + "outputs": [], + "source": [ + "import finn.builder.build_dataflow_steps as build_dataflow_steps\n", + "showSrc(build_dataflow_steps.step_tidy_up)" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "ce1aa025", + "metadata": {}, + "outputs": [], + "source": [ + "showSrc(build_cfg.VerificationStepType)" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "e157d03c", + "metadata": {}, + "outputs": [], + "source": [ + "# Get golden io pair from Brevitas and save as .npy files\n", + "from finn.util.test import get_trained_network_and_ishape, get_example_input, get_topk\n", + "import numpy as np\n", + "\n", + "\n", + "(brevitas_model, ishape) = get_trained_network_and_ishape(\"cnv\", 2, 2)\n", + "input_tensor_npy = get_example_input(\"cnv\")\n", + "input_tensor_torch = torch.from_numpy(input_tensor_npy).float()\n", + "input_tensor_torch = ToTensor().forward(input_tensor_torch).detach()\n", + "output_tensor_npy = brevitas_model.forward(input_tensor_torch).detach().numpy()\n", + "output_tensor_npy = get_topk(output_tensor_npy, k=1)\n", + "\n", + "np.save(\"input.npy\", input_tensor_npy)\n", + "np.save(\"expected_output.npy\", output_tensor_npy)" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "5cd3032b", + "metadata": {}, + "outputs": [], + "source": [ + "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/advanced\"\n", + "model_file = model_dir + \"/end2end_cnv_w2a2_export.onnx\"\n", + "\n", + "estimates_output_dir = \"output_with_verification\"\n", + "\n", + "#Delete previous run results if exist\n", + "if os.path.exists(estimates_output_dir):\n", + " shutil.rmtree(estimates_output_dir)\n", + " print(\"Previous run results deleted!\")\n", + "\n", + "build_steps = [\n", + " custom_step_add_pre_proc,\n", + " custom_step_add_post_proc,\n", + " \"step_qonnx_to_finn\",\n", + " \"step_tidy_up\",\n", + " \"step_streamline\",\n", + " \"step_convert_to_hls\",\n", + " \"step_create_dataflow_partition\",\n", + " \"step_apply_folding_config\",\n", + " \"step_minimize_bit_width\",\n", + " \"step_generate_estimate_reports\",\n", + "]\n", + "\n", + "cfg_estimates = build.DataflowBuildConfig(\n", + " output_dir = estimates_output_dir,\n", + " mvau_wwidth_max = 80,\n", + " target_fps = 1000000,\n", + " synth_clk_period_ns = 10.0,\n", + " fpga_part = \"xc7z020clg400-1\",\n", + " steps = build_steps,\n", + " generate_outputs=[\n", + " build_cfg.DataflowOutputType.ESTIMATE_REPORTS,\n", + " ],\n", + " verify_steps=[\n", + " build_cfg.VerificationStepType.QONNX_TO_FINN_PYTHON,\n", + " build_cfg.VerificationStepType.TIDY_UP_PYTHON,\n", + " build_cfg.VerificationStepType.STREAMLINED_PYTHON,\n", + " ]\n", + ")" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "a3a46e76", + "metadata": {}, + "outputs": [], + "source": [ + "%%time\n", + "build.build_dataflow_cfg(model_file, cfg_estimates)" + ] + }, + { + "cell_type": "markdown", + "id": "f0b30546", + "metadata": {}, + "source": [ + "### Examples for additional builder arguments " + ] + }, + { + "cell_type": "markdown", + "id": "ddfb40e4", + "metadata": {}, + "source": [ + "#### Standalone Thresholds" + ] + }, + { + "cell_type": "markdown", + "id": "b710fd28", + "metadata": {}, + "source": [ + "#### RTL Convolutional Input Generator" + ] + }, + { + "cell_type": "markdown", + "id": "4609f94d", + "metadata": {}, + "source": [ + "### Other builder arguments " + ] + }, + { + "cell_type": "markdown", + "id": "37b6853d", + "metadata": {}, + "source": [ + "Let's have a look at the additional builder arguments. We want to only filter out the FINN specific arguments." + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "e9f6aa29", + "metadata": {}, + "outputs": [], + "source": [ + "# Filter out methods\n", + "builder_args = [m for m in dir(build_cfg.DataflowBuildConfig) if not m.startswith('_')]\n", + "print(\"\\n\".join(builder_args))" + ] + }, + { + "cell_type": "markdown", + "id": "b12ab370", + "metadata": {}, + "source": [ + "There are attributes that come from the dataclasses-json class: to_dict, to_json, schema, from_json, from_dict. These are not FINN builder specific. Some of the arguments we have seen already in the Cybersecurity notebook and in this notebook, e.g. target_fps, fpga_part, folding_config_file, ...\n", + "Please have a look here and scroll through the available builder arguments: https://github.com/Xilinx/finn/blob/dev/src/finn/builder/build_dataflow_config.py#L155" + ] + } + ], + "metadata": { + "kernelspec": { + "display_name": "Python 3 (ipykernel)", + "language": "python", + "name": "python3" + }, + "language_info": { + "codemirror_mode": { + "name": "ipython", + "version": 3 + }, + "file_extension": ".py", + "mimetype": "text/x-python", + "name": "python", + "nbconvert_exporter": "python", + "pygments_lexer": "ipython3", + "version": "3.10.6" + } + }, + "nbformat": 4, + "nbformat_minor": 5 +} From 316d23a03dc70b260093a3811e7156e1ca1a7c06 Mon Sep 17 00:00:00 2001 From: auphelia Date: Thu, 24 Aug 2023 16:59:11 +0100 Subject: [PATCH 266/665] [NBs] Checking in advanced nb --- .../4_advanced_builder_settings.ipynb | 269 +++++++++++++++++- 1 file changed, 256 insertions(+), 13 deletions(-) diff --git a/notebooks/advanced/4_advanced_builder_settings.ipynb b/notebooks/advanced/4_advanced_builder_settings.ipynb index ce02ab618e..5936118089 100644 --- a/notebooks/advanced/4_advanced_builder_settings.ipynb +++ b/notebooks/advanced/4_advanced_builder_settings.ipynb @@ -34,7 +34,8 @@ "\n", "1. [Introduction to the CNV-w2a2 network](#intro_cnv)\n", "2. [Recap default builder flow](#recap_builder)\n", - "3. [How to make a custom build step](#custom_step)\n", + "3. [Build steps](#build_step)\n", + " 1. [How to make a custom build step](#custom_step)\n", "4. [Folding configuration json](#folding_config)\n", "5. [Additional builder arguments](#builder_arg)\n", " 1. [Verification steps](#verify)\n", @@ -86,10 +87,7 @@ "cnv = get_test_model_trained(\"CNV\", 2, 2)\n", "export_onnx_path = build_dir + \"/end2end_cnv_w2a2_export.onnx\"\n", "export_qonnx(cnv, torch.randn(1, 3, 32, 32), export_onnx_path)\n", - "qonnx_cleanup(export_onnx_path, out_file=export_onnx_path)\n", - "#model = ModelWrapper(export_onnx_path)\n", - "#model.set_tensor_datatype(model.graph.input[0].name, DataType[\"UINT8\"])\n", - "#model.save(build_dir + \"/end2end_cnv_w2a2_tidy.onnx\")" + "qonnx_cleanup(export_onnx_path, out_file=export_onnx_path)" ] }, { @@ -154,7 +152,7 @@ "outputs": [], "source": [ "%%time\n", - "build.build_dataflow_cfg(model_file, cfg_estimates)" + "build.build_dataflow_cfg(model_file, cfg_estimates);" ] }, { @@ -167,6 +165,14 @@ "showInNetron(build_dir+\"/output_estimates_only/intermediate_models/step_convert_to_hls.onnx\")" ] }, + { + "cell_type": "markdown", + "id": "7e561a91", + "metadata": {}, + "source": [ + "## Build steps " + ] + }, { "cell_type": "code", "execution_count": null, @@ -177,6 +183,25 @@ "print(\"\\n\".join(build_cfg.estimate_only_dataflow_steps))" ] }, + { + "cell_type": "markdown", + "id": "dd3ef987", + "metadata": {}, + "source": [ + "You can have a closer look at each step by either using the `showSrc()` function or by accessing the doc string." + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "313fac18", + "metadata": {}, + "outputs": [], + "source": [ + "import finn.builder.build_dataflow_steps as build_dataflow_steps\n", + "print(build_dataflow_steps.step_tidy_up.__doc__)" + ] + }, { "cell_type": "code", "execution_count": null, @@ -193,7 +218,7 @@ "id": "e9c2c97f", "metadata": {}, "source": [ - "## How to make a custom build step " + "### How to make a custom build step " ] }, { @@ -349,7 +374,7 @@ "outputs": [], "source": [ "%%time\n", - "build.build_dataflow_cfg(model_file, cfg_estimates)" + "build.build_dataflow_cfg(model_file, cfg_estimates);" ] }, { @@ -388,9 +413,9 @@ "import json\n", "\n", "with open(build_dir+\"/output_pre_and_post_proc/auto_folding_config.json\", 'r') as json_file:\n", - " json_object = json.load(json_file)\n", + " folding_config = json.load(json_file)\n", "\n", - "print(json.dumps(json_object, indent=1))" + "print(json.dumps(folding_config, indent=1))" ] }, { @@ -430,6 +455,38 @@ "print(json.dumps(json_object[\"total\"], indent=1))" ] }, + { + "cell_type": "markdown", + "id": "d4d177dc", + "metadata": {}, + "source": [ + "You can manually change, here we generate two new folding configurations with either all lutram or all bram" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "112af6fd", + "metadata": {}, + "outputs": [], + "source": [ + "# Set all ram_style to LUT RAM\n", + "for key in folding_config:\n", + " if \"ram_style\" in folding_config[key]:\n", + " folding_config[key][\"ram_style\"] = \"distributed\" \n", + "# Save as .json \n", + "with open(\"folding_config_all_lutram.json\", \"w\") as jsonFile:\n", + " json.dump(folding_config, jsonFile)\n", + " \n", + "# Set all ram_style to BRAM\n", + "for key in folding_config:\n", + " if \"ram_style\" in folding_config[key]:\n", + " folding_config[key][\"ram_style\"] = \"block\" \n", + "# Save as .json \n", + "with open(\"folding_config_all_bram.json\", \"w\") as jsonFile:\n", + " json.dump(folding_config, jsonFile)" + ] + }, { "cell_type": "code", "execution_count": null, @@ -481,7 +538,7 @@ "outputs": [], "source": [ "%%time\n", - "build.build_dataflow_cfg(model_file, cfg_estimates)" + "build.build_dataflow_cfg(model_file, cfg_estimates);" ] }, { @@ -558,7 +615,7 @@ "outputs": [], "source": [ "%%time\n", - "build.build_dataflow_cfg(model_file, cfg_estimates)" + "build.build_dataflow_cfg(model_file, cfg_estimates);" ] }, { @@ -669,6 +726,7 @@ " \"step_streamline\",\n", " \"step_convert_to_hls\",\n", " \"step_create_dataflow_partition\",\n", + " \"step_target_fps_parallelization\",\n", " \"step_apply_folding_config\",\n", " \"step_minimize_bit_width\",\n", " \"step_generate_estimate_reports\",\n", @@ -700,7 +758,7 @@ "outputs": [], "source": [ "%%time\n", - "build.build_dataflow_cfg(model_file, cfg_estimates)" + "build.build_dataflow_cfg(model_file, cfg_estimates);" ] }, { @@ -719,6 +777,80 @@ "#### Standalone Thresholds" ] }, + { + "cell_type": "markdown", + "id": "bddbd686", + "metadata": {}, + "source": [ + " picture of im2col + matmul + multithreshold" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "de55871e", + "metadata": {}, + "outputs": [], + "source": [ + "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/advanced\"\n", + "model_file = model_dir + \"/end2end_cnv_w2a2_export.onnx\"\n", + "\n", + "estimates_output_dir = \"output_standalone_thresholds\"\n", + "\n", + "#Delete previous run results if exist\n", + "if os.path.exists(estimates_output_dir):\n", + " shutil.rmtree(estimates_output_dir)\n", + " print(\"Previous run results deleted!\")\n", + "\n", + "build_steps = [\n", + " custom_step_add_pre_proc,\n", + " custom_step_add_post_proc,\n", + " \"step_qonnx_to_finn\",\n", + " \"step_tidy_up\",\n", + " \"step_streamline\",\n", + " \"step_convert_to_hls\",\n", + " \"step_create_dataflow_partition\",\n", + " \"step_target_fps_parallelization\",\n", + " \"step_apply_folding_config\",\n", + " \"step_minimize_bit_width\",\n", + " \"step_generate_estimate_reports\",\n", + "]\n", + "\n", + "cfg_estimates = build.DataflowBuildConfig(\n", + " output_dir = estimates_output_dir,\n", + " mvau_wwidth_max = 80,\n", + " target_fps = 1000000,\n", + " synth_clk_period_ns = 10.0,\n", + " fpga_part = \"xc7z020clg400-1\",\n", + " standalone_thresholds = True,\n", + " steps = build_steps,\n", + " generate_outputs=[\n", + " build_cfg.DataflowOutputType.ESTIMATE_REPORTS,\n", + " ],\n", + ")" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "c143f97a", + "metadata": {}, + "outputs": [], + "source": [ + "%%time\n", + "build.build_dataflow_cfg(model_file, cfg_estimates);" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "ba36f07b", + "metadata": {}, + "outputs": [], + "source": [ + "showInNetron(build_dir+\"/output_standalone_thresholds/intermediate_models/step_generate_estimate_reports.onnx\")" + ] + }, { "cell_type": "markdown", "id": "b710fd28", @@ -727,6 +859,72 @@ "#### RTL Convolutional Input Generator" ] }, + { + "cell_type": "code", + "execution_count": null, + "id": "8249280d", + "metadata": {}, + "outputs": [], + "source": [ + "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/advanced\"\n", + "model_file = model_dir + \"/end2end_cnv_w2a2_export.onnx\"\n", + "\n", + "estimates_output_dir = \"output_rtl_swg\"\n", + "\n", + "#Delete previous run results if exist\n", + "if os.path.exists(estimates_output_dir):\n", + " shutil.rmtree(estimates_output_dir)\n", + " print(\"Previous run results deleted!\")\n", + "\n", + "build_steps = [\n", + " custom_step_add_pre_proc,\n", + " custom_step_add_post_proc,\n", + " \"step_qonnx_to_finn\",\n", + " \"step_tidy_up\",\n", + " \"step_streamline\",\n", + " \"step_convert_to_hls\",\n", + " \"step_create_dataflow_partition\",\n", + " \"step_target_fps_parallelization\",\n", + " \"step_apply_folding_config\",\n", + " \"step_minimize_bit_width\",\n", + " \"step_generate_estimate_reports\",\n", + "]\n", + "\n", + "cfg_estimates = build.DataflowBuildConfig(\n", + " output_dir = estimates_output_dir,\n", + " mvau_wwidth_max = 80,\n", + " target_fps = 1000000,\n", + " synth_clk_period_ns = 10.0,\n", + " fpga_part = \"xc7z020clg400-1\",\n", + " force_rtl_conv_inp_gen = True,\n", + " steps = build_steps,\n", + " generate_outputs=[\n", + " build_cfg.DataflowOutputType.ESTIMATE_REPORTS,\n", + " ],\n", + ")" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "64e83b16", + "metadata": {}, + "outputs": [], + "source": [ + "%%time\n", + "build.build_dataflow_cfg(model_file, cfg_estimates);" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "09c45dcd", + "metadata": {}, + "outputs": [], + "source": [ + "showInNetron(build_dir+\"/output_rtl_swg/intermediate_models/step_generate_estimate_reports.onnx\")" + ] + }, { "cell_type": "markdown", "id": "4609f94d", @@ -763,6 +961,51 @@ "There are attributes that come from the dataclasses-json class: to_dict, to_json, schema, from_json, from_dict. These are not FINN builder specific. Some of the arguments we have seen already in the Cybersecurity notebook and in this notebook, e.g. target_fps, fpga_part, folding_config_file, ...\n", "Please have a look here and scroll through the available builder arguments: https://github.com/Xilinx/finn/blob/dev/src/finn/builder/build_dataflow_config.py#L155" ] + }, + { + "cell_type": "markdown", + "id": "9aba0493", + "metadata": {}, + "source": [ + "So far, in this notebook, we only looked at configurations up to the generation of estimate reports so far, a lot of these builder arguments actually become relevant at a later stage in the FINN flow." + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "ec39b9f2", + "metadata": {}, + "outputs": [], + "source": [ + "print(\"\\n\".join(build_cfg.default_build_dataflow_steps))" + ] + }, + { + "cell_type": "markdown", + "id": "76df000f", + "metadata": {}, + "source": [ + "You can have a closer look at each step by either using the `showSrc()` function or by accessing the doc string." + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "caf49f03", + "metadata": {}, + "outputs": [], + "source": [ + "import finn.builder.build_dataflow_steps as build_dataflow_steps\n", + "print(build_dataflow_steps.step_create_dataflow_partition.__doc__)" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "1ec10985", + "metadata": {}, + "outputs": [], + "source": [] } ], "metadata": { From b368ee0b1a79e165a9bd4b0585c4aea44041fb5c Mon Sep 17 00:00:00 2001 From: hlebleve Date: Fri, 25 Aug 2023 14:16:48 +0200 Subject: [PATCH 267/665] [InferPixelPaddingDeconv] Adding safety check to verify that groups=1, as depthwise deconvolution is not yet supported --- .../infer_pixel_padding_deconv.py | 29 +++++-------------- 1 file changed, 7 insertions(+), 22 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/infer_pixel_padding_deconv.py b/src/finn/transformation/fpgadataflow/infer_pixel_padding_deconv.py index 0f48565bf9..aa579dcdb6 100644 --- a/src/finn/transformation/fpgadataflow/infer_pixel_padding_deconv.py +++ b/src/finn/transformation/fpgadataflow/infer_pixel_padding_deconv.py @@ -36,6 +36,12 @@ def apply(self, model): stride_h = get_by_name(n.attribute, "strides").ints[0] stride_w = get_by_name(n.attribute, "strides").ints[1] group = get_by_name(n.attribute, "group").i + if group != 1: + warnings.warn( + "%s : Only group=1 is currently supported. Can't infer PixelPaddingDeconv." + % n.name + ) + continue weight_name = n.input[1] W_conv = model.get_initializer(weight_name) ifm_ch = model.get_tensor_shape(n.input[0])[1] # assume NCHW @@ -77,27 +83,6 @@ def apply(self, model): assert ( ifm_dim_h == 1 or ifm_dim_w == 1 ), "Padding is assumed to be 1D, image is 2D" - - # if depthwise conv create sparse matrix and variable "dw" - # to store as attribute in Im2Col that indicates that the created - # Im2Col node belongs to a depthwise convolution - dw = False - if group == ifm_ch and ofm_ch == ifm_ch: - W_sparse = np.zeros((ifm_ch, ofm_ch, k_h, k_w)) # (IFM, OFM, k_H, k_W) - for ch in range(ofm_ch): - W_sparse[ch][ch] = W_conv[ch][0] # W_conv = [IFM, OFM, k_H, k_W] - W_conv = W_sparse.astype(np.float32) - # we need to store information of the - # sparsity of the weight matrix. For this - # we use the sparsity annotation of the - # weight tensor - sparsity = {"dw": {"kernel_shape": [k_h, k_w]}} - model.set_tensor_sparsity(weight_name, sparsity) - # additionally create variable "dw" to store - # as attribute in Im2Col that indicates that the created - # Im2Col node belongs to a depthwise convolution - dw = True - # reuse ConvTranspose weights for new matmul weights # conv weights are [IFM][OFM][k][k] # We need to rotate the weights and make them [OFM][IFM][k][k] @@ -196,7 +181,7 @@ def apply(self, model): kernel_size=[k_h, k_w], pad_amount=conv_padding, input_shape="(1,{},{},{})".format(padded_odim_h, padded_odim_w, ifm_ch), - depthwise=dw, + depthwise=False, dilations=dilation, ) From 033fdc30267ed34c6aee2ccb88c4828acc995aa7 Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 28 Aug 2023 22:04:43 +0100 Subject: [PATCH 268/665] [NB] First two sections of advanced nb --- .../4_advanced_builder_settings.ipynb | 268 +++++++++++++++++- 1 file changed, 256 insertions(+), 12 deletions(-) diff --git a/notebooks/advanced/4_advanced_builder_settings.ipynb b/notebooks/advanced/4_advanced_builder_settings.ipynb index 5936118089..63f69a6385 100644 --- a/notebooks/advanced/4_advanced_builder_settings.ipynb +++ b/notebooks/advanced/4_advanced_builder_settings.ipynb @@ -11,8 +11,7 @@ "\n", "\"drawing\"\n", "\n", - "In this notebook, we'll use the FINN compiler to generate an FPGA accelerator with a streaming dataflow architecture from small convolutional network trained on CIFAR-10. The key idea in such architectures is to parallelize across layers as well as within layers by dedicating a proportionate amount of compute resources to each layer, illustrated on the figure to the left. You can read more about the general concept in the [FINN](https://arxiv.org/pdf/1612.07119) and [FINN-R](https://dl.acm.org/doi/pdf/10.1145/3242897) papers. This is done by mapping each layer to a Vitis HLS description, parallelizing each layer's implementation to the appropriate degree and using on-chip FIFOs to link up the layers to create the full accelerator.\n", - "\n", + "In this notebook, we'll use the FINN compiler to generate an FPGA accelerator with a streaming dataflow architecture from small convolutional network trained on CIFAR-10. The key idea in streaming dataflow architectures is to parallelize across layers as well as within layers by dedicating a proportionate amount of compute resources to each layer, illustrated on the figure to the left. You can read more about the general concept in the [FINN](https://arxiv.org/pdf/1612.07119) and [FINN-R](https://dl.acm.org/doi/pdf/10.1145/3242897) papers. This is done by mapping each layer to a Vitis HLS description, parallelizing each layer's implementation to the appropriate degree and using on-chip FIFOs to link up the layers to create the full accelerator.\n", "These implementations offer a good balance of performance and flexibility, but building them by hand is difficult and time-consuming. This is where the FINN compiler comes in: it can build streaming dataflow accelerators from an ONNX description to match the desired throughput." ] }, @@ -53,7 +52,7 @@ "The particular quantized neural network (QNN) we will be targeting in this notebook is referred to as CNV-w2a2 and it classifies 32x32 RGB images into one of ten CIFAR-10 classes. All weights and activations in this network are quantized to two bit, with the exception of the input (which is RGB with 8 bits per channel) and the final output (which is 32-bit numbers). It is similar to the convolutional neural network used in the [cnv_end2end_example](../end2end_example/bnn-pynq/cnv_end2end_example.ipynb) Jupyter notebook.\n", "\n", "\n", - "You'll have a chance to interactively examine the layers that make up the network in Netron in a moment, so that's enough about the network for now. \n" + "You'll have a chance to interactively examine the layers that make up the network in Netron. We start by setting the build directory to the directory this notebook is in and importing helper functions to use in the notebook to examine ONNX graphs and source code." ] }, { @@ -63,13 +62,21 @@ "metadata": {}, "outputs": [], "source": [ - "from finn.util.basic import make_build_dir\n", + "#from finn.util.basic import make_build_dir\n", "from finn.util.visualization import showInNetron, showSrc\n", "import os\n", " \n", "build_dir = os.environ['FINN_ROOT'] + \"/notebooks/advanced\"" ] }, + { + "cell_type": "markdown", + "id": "7fc6444c", + "metadata": {}, + "source": [ + "In the next step, we will export the trained network directly from Brevitas to the QONNX format. QONNX is the intermediate representation (IR) that is used as the frontend to the FINN compiler. Please note that the internal representation of the network is still the FINN-ONNX format. [QONNX and FINN-ONNX](https://finn.readthedocs.io/en/latest/internals.html#intermediate-representation-qonnx-and-finn-onnx) are extensions to the ONNX format to represent quantization, especially below 8 bit, in ONNX graphs. The main difference is that quantization in QONNX graphs is represented using dedicated quantization nodes ([more about QONNX](https://github.com/fastmachinelearning/qonnx)) while the quantization in FINN-ONNX is an annotation attached to the tensors." + ] + }, { "cell_type": "code", "execution_count": null, @@ -81,8 +88,6 @@ "from finn.util.test import get_test_model_trained\n", "from brevitas.export import export_qonnx\n", "from qonnx.util.cleanup import cleanup as qonnx_cleanup\n", - "from qonnx.core.modelwrapper import ModelWrapper\n", - "from qonnx.core.datatype import DataType\n", "\n", "cnv = get_test_model_trained(\"CNV\", 2, 2)\n", "export_onnx_path = build_dir + \"/end2end_cnv_w2a2_export.onnx\"\n", @@ -90,6 +95,14 @@ "qonnx_cleanup(export_onnx_path, out_file=export_onnx_path)" ] }, + { + "cell_type": "markdown", + "id": "d24b632f", + "metadata": {}, + "source": [ + "After the export, we call a clean up function on the model. This makes sure, that for example all shapes in the network are inferred, constant folding was applied and all tensors and nodes have unique names. In the next step, we can visualize the graph using Netron. When scrolling through the graph, you can see the Quant nodes that indicate the quantization in the network. In the [first step](https://github.com/Xilinx/finn/blob/main/src/finn/builder/build_dataflow_steps.py#L260) of the FINN builder flow, the network gets converted from the QONNX format to the FINN-ONNX format. That means these Quant nodes will not be present in the graph anymore and instead the quantization will be attached as an annotation to the tensors." + ] + }, { "cell_type": "code", "execution_count": null, @@ -108,6 +121,14 @@ "## Quick recap, how to setup up default builder flow for resource estimations " ] }, + { + "cell_type": "markdown", + "id": "a26e5418", + "metadata": {}, + "source": [ + "As a quick recap, let's set up the builder like we have done in the cybersecurity example to get the resource estimates for our example network." + ] + }, { "cell_type": "code", "execution_count": null, @@ -155,16 +176,130 @@ "build.build_dataflow_cfg(model_file, cfg_estimates);" ] }, + { + "cell_type": "markdown", + "id": "4fa0b9f5", + "metadata": {}, + "source": [ + "The output directory was created and we can extract information about our model and also how it was processed in the FINN compiler from the generated files. Let's focus on the intermediate models for now. You can find them in the output directory in the folder \"intermediate_models\"." + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "05a941ef", + "metadata": {}, + "outputs": [], + "source": [ + "!ls -t -r output_estimates_only/intermediate_models" + ] + }, + { + "cell_type": "markdown", + "id": "d746eff3", + "metadata": {}, + "source": [ + "After each FINN builder step, the graph is saved as .onnx file. In the cell above we sort the intermediate models by time in descending order (`ls -t -r`) to visualize the builder flow. As you can see after the conversion to the FINN-ONNX format (`step_qonnx_to_finn`), the graph is prepared by tidy up and streamlining (`step_tidy_up` and `step_streamline`) and then the high level nodes are converted to HLS layers (`step_convert_to_hls`). Then there is a partition created from all layers that were converted to HLS layers (`step_create_dataflow_partition`), then optimizations are applied (`step_target_fps_parallelization`, `step_apply_folding_config` and `step_minimize_bit_width`). In the final step of this example we generate resource and performance reports for the network (`step_generate_estimate_reports`). Use the code below to investigate the network after each step." + ] + }, { "cell_type": "code", "execution_count": null, "id": "72de8d4c", "metadata": {}, "outputs": [], + "source": [ + "model_to_investigate = \"step_qonnx_to_finn.onnx\"\n", + "showInNetron(build_dir+\"/output_estimates_only/intermediate_models/\"+model_to_investigate)" + ] + }, + { + "cell_type": "markdown", + "id": "bccebd0d", + "metadata": {}, + "source": [ + "The analysis of these .onnx files can help us identifying points in the flow in which we might need to intervene and provide the compiler with additional information. When investigating the network after the conversion to HLS layers, we can see that there is layers that were not converted. We can see this by clicking on the different nodes. HLS layers have the module `finn.custom_op.fpgadataflow`." + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "6d86463a", + "metadata": {}, + "outputs": [], "source": [ "showInNetron(build_dir+\"/output_estimates_only/intermediate_models/step_convert_to_hls.onnx\")" ] }, + { + "cell_type": "markdown", + "id": "2719cc09", + "metadata": {}, + "source": [ + "As you can see in the graph, the first two nodes (a MultiThreshold and Transpose node) and the last two nodes (a Mul and Add node) are not converted into HLS layers. FINN currently only converts integer only operations into HLS layers, this means only when the input, output & weights are quantized the node will be converted." + ] + }, + { + "cell_type": "markdown", + "id": "ff7fa549", + "metadata": {}, + "source": [ + "
    \n", + "Important notice: We are working on supporting additional data types and this limitation might disappear in the near future.\n", + "
    " + ] + }, + { + "cell_type": "markdown", + "id": "6e6d942e", + "metadata": {}, + "source": [ + "When we click on the `global_in` in the graph, we can see that the quantization annotation does not contain a data type. If no data type is set and it can not be derived from the preceeding node, the FINN compiler automatically assumes that the data type is floating point. This is why the first node does not get converted into an HLS layer, the input is assumed to be floating point." + ] + }, + { + "cell_type": "markdown", + "id": "8b8994e6", + "metadata": {}, + "source": [ + "The solution to the problem depends on the actual data input.\n", + "1. The data set is quantized and `global_in` is an integer: We set the data type of the tensor `global_in` before passing the model to the FINN compiler using [helper functions of ModelWrapper](https://finn.readthedocs.io/en/latest/internals.html#helper-functions-for-tensors).\n", + "2. The data set is not quantized: we can either execute the first layer in software (e.g. as part of the Python driver) or we can add a preprocessing step into the graph." + ] + }, + { + "cell_type": "markdown", + "id": "7504dce7", + "metadata": {}, + "source": [ + "Even though in the example of the CNVw2a2, the inputs are 32x32 RGB images, so the input values are 8 bit (UINT8) \"quantized\", the input to the exported model is floating point. For training in Brevitas, these values were normalized between 0 and 1.0 and so the exported model expects floating point values as input. \n", + "This means we are in scenario 2. In the next section we will develop a custom step for the FINN builder flow to add preprocessing to our network.\n", + "\n", + "But before we move to the next section, let's take a look at the last two nodes in the graph that were not converted to HLS layers." + ] + }, + { + "cell_type": "markdown", + "id": "f9c2696b", + "metadata": {}, + "source": [ + "We have two nodes at the end of the graph that we were not able to convert: a floating poing scalar multiplication and addition. These operations are \"left-over\" from streamlining and cannot be merged into a succeeding thresholding operation. \n", + "\n", + "Our example is a network for image classification, so that we know that the output is a vector of 10 values that give a probability for each of the classes in the CIFAR-10 data set. If we are only interested in the Top-1 result of the classification, we can add a post-processing step which inserts a TopK node in the graph. \n", + "\n", + "Since the last two layers are scalar operations, they have the same influence on all probability values in the output vector and we can safely merge them into the TopK node. " + ] + }, + { + "cell_type": "markdown", + "id": "4fc8fbf5", + "metadata": {}, + "source": [ + "These pre-processing and post-processing steps are network dependent and we will need to write **custom steps** that can then be executed using the FINN builder tool.\n", + "\n", + "In the next section we will first look into how a standard build step inside FINN looks like and then we will write our own custom steps for pre- and post-processing and add them to the builder configuration." + ] + }, { "cell_type": "markdown", "id": "7e561a91", @@ -173,6 +308,14 @@ "## Build steps " ] }, + { + "cell_type": "markdown", + "id": "fb18b21d", + "metadata": {}, + "source": [ + "The following steps are executed when using the `estimates_only`-flow." + ] + }, { "cell_type": "code", "execution_count": null, @@ -213,6 +356,14 @@ "showSrc(build_dataflow_steps.step_tidy_up)" ] }, + { + "cell_type": "markdown", + "id": "2809f6a7", + "metadata": {}, + "source": [ + "Each steps gets the model and the build configuration as input arguments. Then a certain sequence of transformations is applied to the model. In some of the steps, verification can be run to ensure that the applied transformations have not changed the behaviour of the network. In the end the modified model is returned." + ] + }, { "cell_type": "markdown", "id": "e9c2c97f", @@ -221,6 +372,14 @@ "### How to make a custom build step " ] }, + { + "cell_type": "markdown", + "id": "537a44e7", + "metadata": {}, + "source": [ + "When writing our own custom steps, we use the same pattern. See below the code for the pre-processing for the example network." + ] + }, { "cell_type": "code", "execution_count": null, @@ -230,6 +389,8 @@ "source": [ "from finn.util.pytorch import ToTensor\n", "from qonnx.transformation.merge_onnx_models import MergeONNXModels\n", + "from qonnx.core.modelwrapper import ModelWrapper\n", + "from qonnx.core.datatype import DataType\n", "\n", "def custom_step_add_pre_proc(model: ModelWrapper, cfg: build.DataflowBuildConfig):\n", " ishape = model.get_tensor_shape(model.graph.input[0].name)\n", @@ -239,11 +400,22 @@ " preproc_model = ModelWrapper(\"preproc.onnx\")\n", " # set input finn datatype to UINT8\n", " preproc_model.set_tensor_datatype(preproc_model.graph.input[0].name, DataType[\"UINT8\"])\n", + " # merge pre-processing onnx model with cnv model (passed as input argument)\n", " model = model.transform(MergeONNXModels(preproc_model))\n", " return model\n", " " ] }, + { + "cell_type": "markdown", + "id": "7a6798aa", + "metadata": {}, + "source": [ + "In the next step we can modify the builder configuration to execute a custom sequence of builder steps, including the newly implemented pre-processing custom step.\n", + "\n", + "For that we create a list `build_steps` which contains next to the standard steps from the `estimate_only` flow, also the new custom step to add the pre-processing. This list then gets passed in the build configuration." + ] + }, { "cell_type": "code", "execution_count": null, @@ -254,11 +426,11 @@ "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/advanced\"\n", "model_file = model_dir + \"/end2end_cnv_w2a2_export.onnx\"\n", "\n", - "estimates_output_dir = \"output_pre_proc\"\n", + "output_dir = \"output_pre_proc\"\n", "\n", "#Delete previous run results if exist\n", - "if os.path.exists(estimates_output_dir):\n", - " shutil.rmtree(estimates_output_dir)\n", + "if os.path.exists(output_dir):\n", + " shutil.rmtree(output_dir)\n", " print(\"Previous run results deleted!\")\n", "\n", "build_steps = [\n", @@ -275,7 +447,7 @@ "]\n", "\n", "cfg_estimates = build.DataflowBuildConfig(\n", - " output_dir = estimates_output_dir,\n", + " output_dir = output_dir,\n", " mvau_wwidth_max = 80,\n", " target_fps = 1000000,\n", " synth_clk_period_ns = 10.0,\n", @@ -298,6 +470,24 @@ "build.build_dataflow_cfg(model_file, cfg_estimates)" ] }, + { + "cell_type": "code", + "execution_count": null, + "id": "51b7dbd5", + "metadata": {}, + "outputs": [], + "source": [ + "!ls -t -r output_pre_proc/intermediate_models" + ] + }, + { + "cell_type": "markdown", + "id": "4690049f", + "metadata": {}, + "source": [ + "An intermediate .onnx file after the execution of the custom step was automatically created, let's have a look at the graph." + ] + }, { "cell_type": "code", "execution_count": null, @@ -308,6 +498,16 @@ "showInNetron(build_dir+\"/output_pre_proc/intermediate_models/custom_step_add_pre_proc.onnx\")" ] }, + { + "cell_type": "markdown", + "id": "90c6bef9", + "metadata": {}, + "source": [ + "The graph is in QONNX format and a division by 255 is inserted in the beginning. We can now use the CIFAR-10 images directly as input to the graph and the new `global_in` tensor is UINT8.\n", + "\n", + "You can already have a look on how the intermediate models have changed by modifying the code in the cell above. Before we go into more detail, we will add another custom step to insert the post-processing. In this case this means the insertion of a TopK node." + ] + }, { "cell_type": "code", "execution_count": null, @@ -332,7 +532,7 @@ "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/advanced\"\n", "model_file = model_dir + \"/end2end_cnv_w2a2_export.onnx\"\n", "\n", - "estimates_output_dir = \"output_pre_and_post_proc\"\n", + "output_dir = \"output_pre_and_post_proc\"\n", "\n", "#Delete previous run results if exist\n", "if os.path.exists(estimates_output_dir):\n", @@ -354,7 +554,7 @@ "]\n", "\n", "cfg_estimates = build.DataflowBuildConfig(\n", - " output_dir = estimates_output_dir,\n", + " output_dir = output_dir,\n", " mvau_wwidth_max = 80,\n", " target_fps = 1000000,\n", " synth_clk_period_ns = 10.0,\n", @@ -377,16 +577,60 @@ "build.build_dataflow_cfg(model_file, cfg_estimates);" ] }, + { + "cell_type": "code", + "execution_count": null, + "id": "95230896", + "metadata": {}, + "outputs": [], + "source": [ + "!ls -t -r output_pre_and_post_proc/intermediate_models" + ] + }, + { + "cell_type": "markdown", + "id": "3a0263b1", + "metadata": {}, + "source": [ + "You can use the code in the cell below to investigate the generated intermediate models. " + ] + }, { "cell_type": "code", "execution_count": null, "id": "44127417", "metadata": {}, "outputs": [], + "source": [ + "showInNetron(build_dir+\"/output_pre_and_post_proc/intermediate_models/custom_step_add_post_proc.onnx\")" + ] + }, + { + "cell_type": "markdown", + "id": "5cc97505", + "metadata": {}, + "source": [ + "Let's have a look at the model after the conversion to hls, to verify that now all layers are correctly converted." + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "63131e3e", + "metadata": {}, + "outputs": [], "source": [ "showInNetron(build_dir+\"/output_pre_and_post_proc/intermediate_models/step_convert_to_hls.onnx\")" ] }, + { + "cell_type": "markdown", + "id": "8fd0af6b", + "metadata": {}, + "source": [ + "The model contains now a `Thresholding` layer in the beginning and a `LabelSelect_Batch` layer at the end. Please note, that there is still a `Transpose` node as the first layer of the graph, but we can solve this by converting the input data to the NHWC format before streaming it into the FINN accelerator." + ] + }, { "cell_type": "markdown", "id": "5ffbadd1", From 68726ac8a329473bc183af993eacb66c17a0c88a Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 29 Aug 2023 18:15:58 +0100 Subject: [PATCH 269/665] [NB] Add section about folding configurations to advanced nb --- .../4_advanced_builder_settings.ipynb | 135 ++++++++++++++---- 1 file changed, 104 insertions(+), 31 deletions(-) diff --git a/notebooks/advanced/4_advanced_builder_settings.ipynb b/notebooks/advanced/4_advanced_builder_settings.ipynb index 63f69a6385..1e17f640ef 100644 --- a/notebooks/advanced/4_advanced_builder_settings.ipynb +++ b/notebooks/advanced/4_advanced_builder_settings.ipynb @@ -11,7 +11,7 @@ "\n", "\"drawing\"\n", "\n", - "In this notebook, we'll use the FINN compiler to generate an FPGA accelerator with a streaming dataflow architecture from small convolutional network trained on CIFAR-10. The key idea in streaming dataflow architectures is to parallelize across layers as well as within layers by dedicating a proportionate amount of compute resources to each layer, illustrated on the figure to the left. You can read more about the general concept in the [FINN](https://arxiv.org/pdf/1612.07119) and [FINN-R](https://dl.acm.org/doi/pdf/10.1145/3242897) papers. This is done by mapping each layer to a Vitis HLS description, parallelizing each layer's implementation to the appropriate degree and using on-chip FIFOs to link up the layers to create the full accelerator.\n", + "In this notebook, we'll use the FINN compiler to generate an FPGA accelerator with a streaming dataflow architecture from a small convolutional network trained on CIFAR-10. The key idea in streaming dataflow architectures is to parallelize across layers as well as within layers by dedicating a proportionate amount of compute resources to each layer, illustrated on the figure to the left. You can read more about the general concept in the [FINN](https://arxiv.org/pdf/1612.07119) and [FINN-R](https://dl.acm.org/doi/pdf/10.1145/3242897) papers. This is done by mapping each layer to a Vitis HLS description, parallelizing each layer's implementation to the appropriate degree and using on-chip FIFOs to link up the layers to create the full accelerator.\n", "These implementations offer a good balance of performance and flexibility, but building them by hand is difficult and time-consuming. This is where the FINN compiler comes in: it can build streaming dataflow accelerators from an ONNX description to match the desired throughput." ] }, @@ -62,7 +62,6 @@ "metadata": {}, "outputs": [], "source": [ - "#from finn.util.basic import make_build_dir\n", "from finn.util.visualization import showInNetron, showSrc\n", "import os\n", " \n", @@ -218,7 +217,7 @@ "id": "bccebd0d", "metadata": {}, "source": [ - "The analysis of these .onnx files can help us identifying points in the flow in which we might need to intervene and provide the compiler with additional information. When investigating the network after the conversion to HLS layers, we can see that there is layers that were not converted. We can see this by clicking on the different nodes. HLS layers have the module `finn.custom_op.fpgadataflow`." + "The analysis of these .onnx files can help us identifying points in the flow in which we might need to intervene and provide the compiler with additional information. When investigating the network after the conversion to HLS layers, we can see that there are layers that were not converted. We can see this by clicking on the different nodes. HLS layers have the module `finn.custom_op.fpgadataflow`." ] }, { @@ -236,7 +235,7 @@ "id": "2719cc09", "metadata": {}, "source": [ - "As you can see in the graph, the first two nodes (a MultiThreshold and Transpose node) and the last two nodes (a Mul and Add node) are not converted into HLS layers. FINN currently only converts integer only operations into HLS layers, this means only when the input, output & weights are quantized the node will be converted." + "As you can see in the graph, the first two nodes (a MultiThreshold and Transpose node) and the last two nodes (a Mul and Add node) are not converted into HLS layers. FINN currently only converts integer only operations into HLS layers, this means only when the input, output & weights are quantized to integer the node will be converted." ] }, { @@ -285,7 +284,7 @@ "source": [ "We have two nodes at the end of the graph that we were not able to convert: a floating poing scalar multiplication and addition. These operations are \"left-over\" from streamlining and cannot be merged into a succeeding thresholding operation. \n", "\n", - "Our example is a network for image classification, so that we know that the output is a vector of 10 values that give a probability for each of the classes in the CIFAR-10 data set. If we are only interested in the Top-1 result of the classification, we can add a post-processing step which inserts a TopK node in the graph. \n", + "Our example is a network for image classification, so the output is a vector of 10 values that give a probability for each of the classes in the CIFAR-10 data set. If we are only interested in the Top-1 result of the classification, we can add a post-processing step which inserts a TopK node in the graph. \n", "\n", "Since the last two layers are scalar operations, they have the same influence on all probability values in the output vector and we can safely merge them into the TopK node. " ] @@ -361,7 +360,7 @@ "id": "2809f6a7", "metadata": {}, "source": [ - "Each steps gets the model and the build configuration as input arguments. Then a certain sequence of transformations is applied to the model. In some of the steps, verification can be run to ensure that the applied transformations have not changed the behaviour of the network. In the end the modified model is returned." + "Each steps gets the model (`model: ModelWrapper`) and the build configuration (`cfg: DataflowBuildConfig`) as input arguments. Then a certain sequence of transformations is applied to the model. In some of the steps, verification can be run to ensure that the applied transformations have not changed the behaviour of the network. In the end the modified model is returned." ] }, { @@ -602,7 +601,8 @@ "metadata": {}, "outputs": [], "source": [ - "showInNetron(build_dir+\"/output_pre_and_post_proc/intermediate_models/custom_step_add_post_proc.onnx\")" + "model_to_investigate = \"custom_step_add_post_proc.onnx\"\n", + "showInNetron(build_dir+\"/output_pre_and_post_proc/intermediate_models/\"+model_to_investigate)" ] }, { @@ -644,7 +644,17 @@ "id": "c164040f", "metadata": {}, "source": [ - "To learn about the influence of folding factors/parallelism in FINN, please have a look at this notebook: " + "The FINN compiler allows the user to implement a network in streaming dataflow architecture, this means every layer is implemented individually and the data is streamed through the accelerator. We can customize each layer for specific performance and resource requirements by adjusting the parallelism and resource type of each layer. In the FINN context we refer to this customization of parallelism in each layer as folding. To learn more details about the influence of folding factors/parallelism in FINN, please have a look at our [folding tutorial](3_folding.ipynb).\n", + "\n", + "In this section, we will look into the interface over which we can influence the customization of each layer using the FINN builder tool: A json file containing the folding configuration." + ] + }, + { + "cell_type": "markdown", + "id": "1299b86d", + "metadata": {}, + "source": [ + "Depending on the invoked step, the FINN compiler can produce or consume a .json file containing the folding configuration for each layer. In the cell below, we will have a look at the automatically generated .json file, which is produced by `step_target_fps_parallelization`. We use this then as starting point to manipulate the folding configuration and feed it back into the builder tool." ] }, { @@ -664,26 +674,28 @@ }, { "cell_type": "markdown", - "id": "ba856c28", + "id": "8de787a7", "metadata": {}, "source": [ - "Hardware configuration for each layer\n", - "\n", - "FIFO depths\n", - "\n", - "Type of memory/compute resources to be used\n", - "\n", - "Parallelism along different dimensions (“PE”, ”SIMD”)\n", - "\n", - "Baked-in, decoupled or external parameters\n", - "\n", - "Influences almost all flows\n", - "\n", - "step_apply_folding_config\n", - "\n", - "Values tuned for performance & footprint\n", - "\n", - "Many additional constraints not visible from .json" + "As you can see from the printed cell above, the keys in the .json file are the node names of the layers in our network. For each of the layers, some node attributes are listed:\n", + "* `PE` and `SIMD` are the folding parameters that determine the parallelism of each layer, depending on the layer they can be set to different values, for details refer to [this table](https://finn-dev.readthedocs.io/en/latest/internals.html#constraints-to-folding-factors-per-layer).\n", + "* `ram_style` determines which memory resource will be used for the layer.\n", + " * `auto`: Vivado will make the decision if the implementation is using LUTRAM or BRAM\n", + " * `distributed`: LUTRAM will be used\n", + " * `block`: BRAM will be used\n", + " * `ultra`: URAM will be used, if available on the selected board\n", + "* `mem_mode`: determines if the parameter memory will be implemented as part of the HLS code (`const`) or instantiated separately and connected with the layer over a memory streamer unit (`decoupled`). You can find more details in this part of the documentation: https://finn-dev.readthedocs.io/en/latest/internals.html#matrixvectoractivation-mem-mode . It is also possible to set the mem_mode to external which allows for the implementation for external weights.\n", + "* `resType`: This is a node attribute for the MVAU layer and can be set to `lut` or `dsp`. Please note that selecting `dsp` will not enable the optimized RTL variant of the MVAU but rather generate HLS code utilizing DSPs, this is not optimal yet but can give an additional parameter for design space exploration.\n", + "* `runtime_writeable_weights`: FINN offers the option to implement the weights as \"runtime writable\", this means you can write the weight values from the driver via an axilite interface." + ] + }, + { + "cell_type": "markdown", + "id": "fd1519fe", + "metadata": {}, + "source": [ + "In the following part of the tutorial, we will use the auto generated json file as starting point to create two new json files which explore the `ram_style` attribute. We will use one of the generated reports from the FINN builder to see the impact of these changes.\n", + "For that, we will extract the total resources from the *estimate_layer_resources.json* report in the following cell." ] }, { @@ -699,12 +711,22 @@ "print(json.dumps(json_object[\"total\"], indent=1))" ] }, + { + "cell_type": "markdown", + "id": "0be3b0e1", + "metadata": {}, + "source": [ + "The FINN compiler estimates the network to use ~500 BRAM blocks and ~100k LUTs." + ] + }, { "cell_type": "markdown", "id": "d4d177dc", "metadata": {}, "source": [ - "You can manually change, here we generate two new folding configurations with either all lutram or all bram" + "We will use the `auto_folding_config.json` and create two folding configuration from that file:\n", + "* All `ram_style` attributes set to `distributed`\n", + "* All `ram_style` attributes set to `block`" ] }, { @@ -714,6 +736,9 @@ "metadata": {}, "outputs": [], "source": [ + "with open(build_dir+\"/output_pre_and_post_proc/auto_folding_config.json\", 'r') as json_file:\n", + " folding_config = json.load(json_file)\n", + "\n", "# Set all ram_style to LUT RAM\n", "for key in folding_config:\n", " if \"ram_style\" in folding_config[key]:\n", @@ -731,6 +756,14 @@ " json.dump(folding_config, jsonFile)" ] }, + { + "cell_type": "markdown", + "id": "0e64a499", + "metadata": {}, + "source": [ + "After generating these files, we will invoke the builder flow. To enable the FINN builder to take the generated folding configuration as input, we will need to set the additional builder argument `folding_config_file` and we will change the `build_steps` to not run `step_target_fps_parallelization`. The build step does not necessarily need to be excluded, but since we pass a separate folding configuration, the output from that step would be overwritten anyways, so we skip it for a faster execution." + ] + }, { "cell_type": "code", "execution_count": null, @@ -741,7 +774,7 @@ "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/advanced\"\n", "model_file = model_dir + \"/end2end_cnv_w2a2_export.onnx\"\n", "\n", - "estimates_output_dir = \"output_all_lutram\"\n", + "output_dir = \"output_all_lutram\"\n", "\n", "#Delete previous run results if exist\n", "if os.path.exists(estimates_output_dir):\n", @@ -762,7 +795,7 @@ "]\n", "\n", "cfg_estimates = build.DataflowBuildConfig(\n", - " output_dir = estimates_output_dir,\n", + " output_dir = output_dir,\n", " mvau_wwidth_max = 80,\n", " synth_clk_period_ns = 10.0,\n", " fpga_part = \"xc7z020clg400-1\",\n", @@ -785,6 +818,14 @@ "build.build_dataflow_cfg(model_file, cfg_estimates);" ] }, + { + "cell_type": "markdown", + "id": "e705767d", + "metadata": {}, + "source": [ + "We can now have a look at the produced model, when clicking on the individual nodes, you can see that all layers have the node attribute `ram_style` set to `distributed`." + ] + }, { "cell_type": "code", "execution_count": null, @@ -808,6 +849,22 @@ "print(json.dumps(json_object[\"total\"], indent=1))" ] }, + { + "cell_type": "markdown", + "id": "55208c70", + "metadata": {}, + "source": [ + "The estimation report shows that BRAM utilization is down to zero and the LUT count went up to around 150k." + ] + }, + { + "cell_type": "markdown", + "id": "11b8430a", + "metadata": {}, + "source": [ + "Let's do the same with the folding configuration which sets all memory resources to use BRAM." + ] + }, { "cell_type": "code", "execution_count": null, @@ -818,7 +875,7 @@ "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/advanced\"\n", "model_file = model_dir + \"/end2end_cnv_w2a2_export.onnx\"\n", "\n", - "estimates_output_dir = \"output_all_bram\"\n", + "output_dir = \"output_all_bram\"\n", "\n", "#Delete previous run results if exist\n", "if os.path.exists(estimates_output_dir):\n", @@ -839,7 +896,7 @@ "]\n", "\n", "cfg_estimates = build.DataflowBuildConfig(\n", - " output_dir = estimates_output_dir,\n", + " output_dir = output_dir,\n", " mvau_wwidth_max = 80,\n", " synth_clk_period_ns = 10.0,\n", " fpga_part = \"xc7z020clg400-1\",\n", @@ -885,6 +942,22 @@ "print(json.dumps(json_object[\"total\"], indent=1))" ] }, + { + "cell_type": "markdown", + "id": "97f87780", + "metadata": {}, + "source": [ + "The initial implementation already had a high utilization of BRAM, but the estimations went now up to 522 BRAMs while the LUT count went down to ~99k." + ] + }, + { + "cell_type": "markdown", + "id": "e65a8ded", + "metadata": {}, + "source": [ + "You can use this example as a starting point to manipulate the folding configuration yourself. Instead of using the above code, you can also manually open one of the example .json files and set the values differently. Please be aware that the node attributes can not be set to arbitrary values. Especially the folding factors need to fulfil [certain constraints](https://finn-dev.readthedocs.io/en/latest/internals.html#constraints-to-folding-factors-per-layer). The other settings for node attributes, can be best looked up in the individual custom operator classes: [e.g. for MVAU](https://github.com/Xilinx/finn/blob/dev/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py#L64)" + ] + }, { "cell_type": "markdown", "id": "4a675834", From 45e8c37faa7d542dddb0a6439f3085aaf83e4c96 Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 29 Aug 2023 21:25:17 +0100 Subject: [PATCH 270/665] [nb] Add details about verification section in advanced nb --- .../4_advanced_builder_settings.ipynb | 180 +++++++++++++++--- 1 file changed, 151 insertions(+), 29 deletions(-) diff --git a/notebooks/advanced/4_advanced_builder_settings.ipynb b/notebooks/advanced/4_advanced_builder_settings.ipynb index 1e17f640ef..16c4e1a8fa 100644 --- a/notebooks/advanced/4_advanced_builder_settings.ipynb +++ b/notebooks/advanced/4_advanced_builder_settings.ipynb @@ -7,8 +7,6 @@ "source": [ "# Advanced Builder settings\n", "\n", - "**Live FINN tutorial:** We recommend clicking **Cell -> Run All** when you start reading this notebook for \"latency hiding\".\n", - "\n", "\"drawing\"\n", "\n", "In this notebook, we'll use the FINN compiler to generate an FPGA accelerator with a streaming dataflow architecture from a small convolutional network trained on CIFAR-10. The key idea in streaming dataflow architectures is to parallelize across layers as well as within layers by dedicating a proportionate amount of compute resources to each layer, illustrated on the figure to the left. You can read more about the general concept in the [FINN](https://arxiv.org/pdf/1612.07119) and [FINN-R](https://dl.acm.org/doi/pdf/10.1145/3242897) papers. This is done by mapping each layer to a Vitis HLS description, parallelizing each layer's implementation to the appropriate degree and using on-chip FIFOs to link up the layers to create the full accelerator.\n", @@ -135,6 +133,8 @@ "metadata": {}, "outputs": [], "source": [ + "## Quick recap on how to setup the default builder flow for resource estimations\n", + "\n", "import finn.builder.build_dataflow as build\n", "import finn.builder.build_dataflow_config as build_cfg\n", "import os\n", @@ -422,6 +422,8 @@ "metadata": {}, "outputs": [], "source": [ + "## Builder flow with custom step for pre-processing\n", + "\n", "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/advanced\"\n", "model_file = model_dir + \"/end2end_cnv_w2a2_export.onnx\"\n", "\n", @@ -528,14 +530,16 @@ "metadata": {}, "outputs": [], "source": [ + "## Builder flow with custom step for pre-processing and post-processing\n", + "\n", "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/advanced\"\n", "model_file = model_dir + \"/end2end_cnv_w2a2_export.onnx\"\n", "\n", "output_dir = \"output_pre_and_post_proc\"\n", "\n", "#Delete previous run results if exist\n", - "if os.path.exists(estimates_output_dir):\n", - " shutil.rmtree(estimates_output_dir)\n", + "if os.path.exists(output_dir):\n", + " shutil.rmtree(output_dir)\n", " print(\"Previous run results deleted!\")\n", "\n", "build_steps = [\n", @@ -771,14 +775,17 @@ "metadata": {}, "outputs": [], "source": [ + "## Build flow with custom folding configuration\n", + "## folding_config_file = \"folding_config_all_lutram.json\"\n", + "\n", "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/advanced\"\n", "model_file = model_dir + \"/end2end_cnv_w2a2_export.onnx\"\n", "\n", "output_dir = \"output_all_lutram\"\n", "\n", "#Delete previous run results if exist\n", - "if os.path.exists(estimates_output_dir):\n", - " shutil.rmtree(estimates_output_dir)\n", + "if os.path.exists(output_dir):\n", + " shutil.rmtree(output_dir)\n", " print(\"Previous run results deleted!\")\n", "\n", "build_steps = [\n", @@ -872,14 +879,17 @@ "metadata": {}, "outputs": [], "source": [ + "## Build flow with custom folding configuration\n", + "## folding_config_file = \"folding_config_all_bram.json\"\n", + "\n", "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/advanced\"\n", "model_file = model_dir + \"/end2end_cnv_w2a2_export.onnx\"\n", "\n", "output_dir = \"output_all_bram\"\n", "\n", "#Delete previous run results if exist\n", - "if os.path.exists(estimates_output_dir):\n", - " shutil.rmtree(estimates_output_dir)\n", + "if os.path.exists(output_dir):\n", + " shutil.rmtree(output_dir)\n", " print(\"Previous run results deleted!\")\n", "\n", "build_steps = [\n", @@ -966,6 +976,22 @@ "## Additional builder arguments " ] }, + { + "cell_type": "markdown", + "id": "f7012b9a", + "metadata": {}, + "source": [ + "In this section, we will have a peak into additional builder arguments the FINN compiler exposes. We will not be able to cover all but you will be able to have a look at a list and we encourage you to take your time to look into the different options there are to customize the FINN builder configuration." + ] + }, + { + "cell_type": "markdown", + "id": "467d8829", + "metadata": {}, + "source": [ + "We start by enabling the verification flow in the builder. The FINN compiler applies multiple transformations to the model before it gets turned into hardware, so we need to make sure that the functional behavior of the network does not change." + ] + }, { "cell_type": "markdown", "id": "e0c167f4", @@ -974,6 +1000,14 @@ "### Verification steps " ] }, + { + "cell_type": "markdown", + "id": "308d52ba", + "metadata": {}, + "source": [ + "Earlier in the tutorial, we had a look at how build steps are written. When investigating the `step_tidy_up`, we can see that before the changed model is returned a verification step can be run. In the case of `step_tidy_up` it is the step `\"initial python\"` that can be initiated by setting `VerificationStepType.TIDY_UP_PYTHON`." + ] + }, { "cell_type": "code", "execution_count": null, @@ -985,6 +1019,14 @@ "showSrc(build_dataflow_steps.step_tidy_up)" ] }, + { + "cell_type": "markdown", + "id": "2bbb84fb", + "metadata": {}, + "source": [ + "Some of the default build steps have automatic verification enabled, when the corresponding verification step is set." + ] + }, { "cell_type": "code", "execution_count": null, @@ -995,6 +1037,14 @@ "showSrc(build_cfg.VerificationStepType)" ] }, + { + "cell_type": "markdown", + "id": "da1a2b88", + "metadata": {}, + "source": [ + "In the cells below, we will use an example input from the CIFAR-10 data set and use the forward pass in Brevitas to generate a reference output. We save the input as `input.npy` and the reference output as `expected_output.npy`." + ] + }, { "cell_type": "code", "execution_count": null, @@ -1018,6 +1068,14 @@ "np.save(\"expected_output.npy\", output_tensor_npy)" ] }, + { + "cell_type": "markdown", + "id": "d03450e7", + "metadata": {}, + "source": [ + "In the next step we set up the builder flow again, this time we will set the build argument `verify_steps` and pass a list of verification steps." + ] + }, { "cell_type": "code", "execution_count": null, @@ -1025,14 +1083,17 @@ "metadata": {}, "outputs": [], "source": [ + "## Build flow with additional builder arguments enabled\n", + "## verification steps\n", + "\n", "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/advanced\"\n", "model_file = model_dir + \"/end2end_cnv_w2a2_export.onnx\"\n", "\n", - "estimates_output_dir = \"output_with_verification\"\n", + "output_dir = \"output_with_verification\"\n", "\n", "#Delete previous run results if exist\n", - "if os.path.exists(estimates_output_dir):\n", - " shutil.rmtree(estimates_output_dir)\n", + "if os.path.exists(output_dir):\n", + " shutil.rmtree(output_dir)\n", " print(\"Previous run results deleted!\")\n", "\n", "build_steps = [\n", @@ -1050,7 +1111,7 @@ "]\n", "\n", "cfg_estimates = build.DataflowBuildConfig(\n", - " output_dir = estimates_output_dir,\n", + " output_dir = output_dir,\n", " mvau_wwidth_max = 80,\n", " target_fps = 1000000,\n", " synth_clk_period_ns = 10.0,\n", @@ -1067,6 +1128,14 @@ ")" ] }, + { + "cell_type": "markdown", + "id": "1d05b985", + "metadata": {}, + "source": [ + "When execution the code below, the verification will be invoked in the background. After the execution we can check if the verification was successful by investigating the output directory." + ] + }, { "cell_type": "code", "execution_count": null, @@ -1078,6 +1147,61 @@ "build.build_dataflow_cfg(model_file, cfg_estimates);" ] }, + { + "cell_type": "markdown", + "id": "ca1d571d", + "metadata": {}, + "source": [ + "The output directory has now an additional directory called `verification_output`." + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "ca74d537", + "metadata": {}, + "outputs": [], + "source": [ + "!ls output_with_verification" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "908ecda4", + "metadata": {}, + "outputs": [], + "source": [ + "!ls output_with_verification/verification_output" + ] + }, + { + "cell_type": "markdown", + "id": "bcbc6f49", + "metadata": {}, + "source": [ + "The directory contains three .npy files. These files are the saved output files from the different verification steps. The suffix indicates if the array matches with the expected output. In our case, the suffix is for all verification steps `_SUCCESS`. Since the outputs are saved as .npy, we can open and investigate the files simply in Python." + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "7a1b6ca9", + "metadata": {}, + "outputs": [], + "source": [ + "verify_initial_python = np.load(\"output_with_verification/verification_output/verify_initial_python_0_SUCCESS.npy\")\n", + "print(\"The output of the verification step after the step_tidy_up is: \" + str(verify_initial_python))" + ] + }, + { + "cell_type": "markdown", + "id": "6558e19e", + "metadata": {}, + "source": [ + "If the generated output does not match the expected output, these files can be used for debugging." + ] + }, { "cell_type": "markdown", "id": "f0b30546", @@ -1109,14 +1233,17 @@ "metadata": {}, "outputs": [], "source": [ + "## Build flow with additional builder arguments enabled\n", + "## standalone_thresholds = True\n", + "\n", "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/advanced\"\n", "model_file = model_dir + \"/end2end_cnv_w2a2_export.onnx\"\n", "\n", - "estimates_output_dir = \"output_standalone_thresholds\"\n", + "output_dir = \"output_standalone_thresholds\"\n", "\n", "#Delete previous run results if exist\n", - "if os.path.exists(estimates_output_dir):\n", - " shutil.rmtree(estimates_output_dir)\n", + "if os.path.exists(output_dir):\n", + " shutil.rmtree(output_dir)\n", " print(\"Previous run results deleted!\")\n", "\n", "build_steps = [\n", @@ -1134,7 +1261,7 @@ "]\n", "\n", "cfg_estimates = build.DataflowBuildConfig(\n", - " output_dir = estimates_output_dir,\n", + " output_dir = output_dir,\n", " mvau_wwidth_max = 80,\n", " target_fps = 1000000,\n", " synth_clk_period_ns = 10.0,\n", @@ -1183,14 +1310,17 @@ "metadata": {}, "outputs": [], "source": [ + "## Build flow with additional builder arguments enabled\n", + "## force_rtl_conv_inp_gen = True\n", + "\n", "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/advanced\"\n", "model_file = model_dir + \"/end2end_cnv_w2a2_export.onnx\"\n", "\n", - "estimates_output_dir = \"output_rtl_swg\"\n", + "output_dir = \"output_rtl_swg\"\n", "\n", "#Delete previous run results if exist\n", - "if os.path.exists(estimates_output_dir):\n", - " shutil.rmtree(estimates_output_dir)\n", + "if os.path.exists(output_dir):\n", + " shutil.rmtree(output_dir)\n", " print(\"Previous run results deleted!\")\n", "\n", "build_steps = [\n", @@ -1208,7 +1338,7 @@ "]\n", "\n", "cfg_estimates = build.DataflowBuildConfig(\n", - " output_dir = estimates_output_dir,\n", + " output_dir = output_dir,\n", " mvau_wwidth_max = 80,\n", " target_fps = 1000000,\n", " synth_clk_period_ns = 10.0,\n", @@ -1275,7 +1405,7 @@ "id": "b12ab370", "metadata": {}, "source": [ - "There are attributes that come from the dataclasses-json class: to_dict, to_json, schema, from_json, from_dict. These are not FINN builder specific. Some of the arguments we have seen already in the Cybersecurity notebook and in this notebook, e.g. target_fps, fpga_part, folding_config_file, ...\n", + "There are attributes that come from the dataclasses-json class: `to_dict`, `to_json`, `schema`, `from_json`, `from_dict`. These are not FINN builder specific. Some of the arguments we have seen already in the Cybersecurity notebook and in this notebook, e.g. target_fps, fpga_part, folding_config_file, ...\n", "Please have a look here and scroll through the available builder arguments: https://github.com/Xilinx/finn/blob/dev/src/finn/builder/build_dataflow_config.py#L155" ] }, @@ -1315,14 +1445,6 @@ "import finn.builder.build_dataflow_steps as build_dataflow_steps\n", "print(build_dataflow_steps.step_create_dataflow_partition.__doc__)" ] - }, - { - "cell_type": "code", - "execution_count": null, - "id": "1ec10985", - "metadata": {}, - "outputs": [], - "source": [] } ], "metadata": { From e72c9dd0f3274833536c319ce791076811d4989b Mon Sep 17 00:00:00 2001 From: auphelia Date: Thu, 31 Aug 2023 15:50:19 +0100 Subject: [PATCH 271/665] [nb] Clean up advanced nb --- .../4_advanced_builder_settings.ipynb | 179 +++++++++--------- 1 file changed, 86 insertions(+), 93 deletions(-) diff --git a/notebooks/advanced/4_advanced_builder_settings.ipynb b/notebooks/advanced/4_advanced_builder_settings.ipynb index 16c4e1a8fa..1136dba9f4 100644 --- a/notebooks/advanced/4_advanced_builder_settings.ipynb +++ b/notebooks/advanced/4_advanced_builder_settings.ipynb @@ -36,8 +36,8 @@ "4. [Folding configuration json](#folding_config)\n", "5. [Additional builder arguments](#builder_arg)\n", " 1. [Verification steps](#verify)\n", - " 2. [Examples for additional builder arguments](#example_args)\n", - " 3. [Other builder arguments](#other_args)" + " 2. [Other builder arguments](#other_args)\n", + " 3. [Examples for additional builder arguments](#example_args)" ] }, { @@ -284,9 +284,9 @@ "source": [ "We have two nodes at the end of the graph that we were not able to convert: a floating poing scalar multiplication and addition. These operations are \"left-over\" from streamlining and cannot be merged into a succeeding thresholding operation. \n", "\n", - "Our example is a network for image classification, so the output is a vector of 10 values that give a probability for each of the classes in the CIFAR-10 data set. If we are only interested in the Top-1 result of the classification, we can add a post-processing step which inserts a TopK node in the graph. \n", + "Our example is a network for image classification, so the output is a vector of 10 values that give a predicition score for each of the classes in the CIFAR-10 data set. If we are only interested in the Top-1 result of the classification, we can add a post-processing step which inserts a TopK node in the graph. \n", "\n", - "Since the last two layers are scalar operations, they have the same influence on all probability values in the output vector and we can safely merge them into the TopK node. " + "Since the last two layers are scalar operations, they have the same influence on all predicition scores in the output vector and we can safely merge them into the TopK node. " ] }, { @@ -683,12 +683,13 @@ "source": [ "As you can see from the printed cell above, the keys in the .json file are the node names of the layers in our network. For each of the layers, some node attributes are listed:\n", "* `PE` and `SIMD` are the folding parameters that determine the parallelism of each layer, depending on the layer they can be set to different values, for details refer to [this table](https://finn-dev.readthedocs.io/en/latest/internals.html#constraints-to-folding-factors-per-layer).\n", - "* `ram_style` determines which memory resource will be used for the layer.\n", + "* `mem_mode`: determines if the parameter memory will be implemented as part of the HLS code (`const`) or instantiated separately and connected with the layer over a memory streamer unit (`decoupled`). You can find more details in this part of the documentation: https://finn-dev.readthedocs.io/en/latest/internals.html#matrixvectoractivation-mem-mode . It is also possible to set the mem_mode to external which allows for the implementation for external weights.\n", + "* `ram_style`: when selecting `decoupled` mode, the FINN compiler allows us to determine which memory resource will be used for the layer. The argument `ram_style` is set to the selected memory type:\n", " * `auto`: Vivado will make the decision if the implementation is using LUTRAM or BRAM\n", " * `distributed`: LUTRAM will be used\n", " * `block`: BRAM will be used\n", " * `ultra`: URAM will be used, if available on the selected board\n", - "* `mem_mode`: determines if the parameter memory will be implemented as part of the HLS code (`const`) or instantiated separately and connected with the layer over a memory streamer unit (`decoupled`). You can find more details in this part of the documentation: https://finn-dev.readthedocs.io/en/latest/internals.html#matrixvectoractivation-mem-mode . It is also possible to set the mem_mode to external which allows for the implementation for external weights.\n", + "\n", "* `resType`: This is a node attribute for the MVAU layer and can be set to `lut` or `dsp`. Please note that selecting `dsp` will not enable the optimized RTL variant of the MVAU but rather generate HLS code utilizing DSPs, this is not optimal yet but can give an additional parameter for design space exploration.\n", "* `runtime_writeable_weights`: FINN offers the option to implement the weights as \"runtime writable\", this means you can write the weight values from the driver via an axilite interface." ] @@ -1204,32 +1205,98 @@ }, { "cell_type": "markdown", - "id": "f0b30546", + "id": "4609f94d", "metadata": {}, "source": [ - "### Examples for additional builder arguments " + "### Other builder arguments " ] }, { "cell_type": "markdown", - "id": "ddfb40e4", + "id": "37b6853d", "metadata": {}, "source": [ - "#### Standalone Thresholds" + "Let's have a look at the additional builder arguments. We want to only filter out the FINN specific arguments." + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "e9f6aa29", + "metadata": {}, + "outputs": [], + "source": [ + "# Filter out methods\n", + "builder_args = [m for m in dir(build_cfg.DataflowBuildConfig) if not m.startswith('_')]\n", + "print(\"\\n\".join(builder_args))" + ] + }, + { + "cell_type": "markdown", + "id": "b12ab370", + "metadata": {}, + "source": [ + "There are attributes that come from the dataclasses-json class: `to_dict`, `to_json`, `schema`, `from_json`, `from_dict`. These are not FINN builder specific. Some of the arguments we have seen already in the Cybersecurity notebook and in this notebook, e.g. target_fps, fpga_part, folding_config_file, ...\n", + "Please have a look here and scroll through the available builder arguments: https://github.com/Xilinx/finn/blob/dev/src/finn/builder/build_dataflow_config.py#L155" + ] + }, + { + "cell_type": "markdown", + "id": "9aba0493", + "metadata": {}, + "source": [ + "So far, in this notebook, we only looked at configurations up to the generation of estimate reports, a lot of these builder arguments actually become relevant at a later stage in the FINN flow." + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "ec39b9f2", + "metadata": {}, + "outputs": [], + "source": [ + "print(\"\\n\".join(build_cfg.default_build_dataflow_steps))" ] }, { "cell_type": "markdown", - "id": "bddbd686", + "id": "76df000f", "metadata": {}, "source": [ - " picture of im2col + matmul + multithreshold" + "You can have a closer look at each step by either using the `showSrc()` function or by accessing the doc string." + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "caf49f03", + "metadata": {}, + "outputs": [], + "source": [ + "import finn.builder.build_dataflow_steps as build_dataflow_steps\n", + "print(build_dataflow_steps.step_create_dataflow_partition.__doc__)" + ] + }, + { + "cell_type": "markdown", + "id": "3b98eb65", + "metadata": {}, + "source": [ + "### Examples for additional builder arguments " + ] + }, + { + "cell_type": "markdown", + "id": "0dbdab42", + "metadata": {}, + "source": [ + "#### Standalone Thresholds" ] }, { "cell_type": "code", "execution_count": null, - "id": "de55871e", + "id": "2619ebde", "metadata": {}, "outputs": [], "source": [ @@ -1277,7 +1344,7 @@ { "cell_type": "code", "execution_count": null, - "id": "c143f97a", + "id": "b2e9bc42", "metadata": {}, "outputs": [], "source": [ @@ -1288,7 +1355,7 @@ { "cell_type": "code", "execution_count": null, - "id": "ba36f07b", + "id": "32ae296e", "metadata": {}, "outputs": [], "source": [ @@ -1297,7 +1364,7 @@ }, { "cell_type": "markdown", - "id": "b710fd28", + "id": "074d8253", "metadata": {}, "source": [ "#### RTL Convolutional Input Generator" @@ -1306,7 +1373,7 @@ { "cell_type": "code", "execution_count": null, - "id": "8249280d", + "id": "ab0c4974", "metadata": {}, "outputs": [], "source": [ @@ -1354,7 +1421,7 @@ { "cell_type": "code", "execution_count": null, - "id": "64e83b16", + "id": "19fe4d85", "metadata": {}, "outputs": [], "source": [ @@ -1365,86 +1432,12 @@ { "cell_type": "code", "execution_count": null, - "id": "09c45dcd", + "id": "4c1f1ce9", "metadata": {}, "outputs": [], "source": [ "showInNetron(build_dir+\"/output_rtl_swg/intermediate_models/step_generate_estimate_reports.onnx\")" ] - }, - { - "cell_type": "markdown", - "id": "4609f94d", - "metadata": {}, - "source": [ - "### Other builder arguments " - ] - }, - { - "cell_type": "markdown", - "id": "37b6853d", - "metadata": {}, - "source": [ - "Let's have a look at the additional builder arguments. We want to only filter out the FINN specific arguments." - ] - }, - { - "cell_type": "code", - "execution_count": null, - "id": "e9f6aa29", - "metadata": {}, - "outputs": [], - "source": [ - "# Filter out methods\n", - "builder_args = [m for m in dir(build_cfg.DataflowBuildConfig) if not m.startswith('_')]\n", - "print(\"\\n\".join(builder_args))" - ] - }, - { - "cell_type": "markdown", - "id": "b12ab370", - "metadata": {}, - "source": [ - "There are attributes that come from the dataclasses-json class: `to_dict`, `to_json`, `schema`, `from_json`, `from_dict`. These are not FINN builder specific. Some of the arguments we have seen already in the Cybersecurity notebook and in this notebook, e.g. target_fps, fpga_part, folding_config_file, ...\n", - "Please have a look here and scroll through the available builder arguments: https://github.com/Xilinx/finn/blob/dev/src/finn/builder/build_dataflow_config.py#L155" - ] - }, - { - "cell_type": "markdown", - "id": "9aba0493", - "metadata": {}, - "source": [ - "So far, in this notebook, we only looked at configurations up to the generation of estimate reports so far, a lot of these builder arguments actually become relevant at a later stage in the FINN flow." - ] - }, - { - "cell_type": "code", - "execution_count": null, - "id": "ec39b9f2", - "metadata": {}, - "outputs": [], - "source": [ - "print(\"\\n\".join(build_cfg.default_build_dataflow_steps))" - ] - }, - { - "cell_type": "markdown", - "id": "76df000f", - "metadata": {}, - "source": [ - "You can have a closer look at each step by either using the `showSrc()` function or by accessing the doc string." - ] - }, - { - "cell_type": "code", - "execution_count": null, - "id": "caf49f03", - "metadata": {}, - "outputs": [], - "source": [ - "import finn.builder.build_dataflow_steps as build_dataflow_steps\n", - "print(build_dataflow_steps.step_create_dataflow_partition.__doc__)" - ] } ], "metadata": { From 79212877f4818eb322b76066741a7ac31a62a7fb Mon Sep 17 00:00:00 2001 From: auphelia Date: Sat, 2 Sep 2023 17:43:35 +0100 Subject: [PATCH 272/665] [NB] Rework end part of advanced builder tutorial --- .../4_advanced_builder_settings.ipynb | 182 ++++++++++++++++-- 1 file changed, 168 insertions(+), 14 deletions(-) diff --git a/notebooks/advanced/4_advanced_builder_settings.ipynb b/notebooks/advanced/4_advanced_builder_settings.ipynb index 1136dba9f4..aa244e4983 100644 --- a/notebooks/advanced/4_advanced_builder_settings.ipynb +++ b/notebooks/advanced/4_advanced_builder_settings.ipynb @@ -37,7 +37,7 @@ "5. [Additional builder arguments](#builder_arg)\n", " 1. [Verification steps](#verify)\n", " 2. [Other builder arguments](#other_args)\n", - " 3. [Examples for additional builder arguments](#example_args)" + " 3. [Examples for additional builder arguments & bitfile generation](#example_args)" ] }, { @@ -684,7 +684,7 @@ "As you can see from the printed cell above, the keys in the .json file are the node names of the layers in our network. For each of the layers, some node attributes are listed:\n", "* `PE` and `SIMD` are the folding parameters that determine the parallelism of each layer, depending on the layer they can be set to different values, for details refer to [this table](https://finn-dev.readthedocs.io/en/latest/internals.html#constraints-to-folding-factors-per-layer).\n", "* `mem_mode`: determines if the parameter memory will be implemented as part of the HLS code (`const`) or instantiated separately and connected with the layer over a memory streamer unit (`decoupled`). You can find more details in this part of the documentation: https://finn-dev.readthedocs.io/en/latest/internals.html#matrixvectoractivation-mem-mode . It is also possible to set the mem_mode to external which allows for the implementation for external weights.\n", - "* `ram_style`: when selecting `decoupled` mode, the FINN compiler allows us to determine which memory resource will be used for the layer. The argument `ram_style` is set to the selected memory type:\n", + "* `ram_style`: when selecting `decoupled` mode, the FINN compiler allows us to choose which memory resource will be used for the layer. The argument `ram_style` is set to the selected memory type:\n", " * `auto`: Vivado will make the decision if the implementation is using LUTRAM or BRAM\n", " * `distributed`: LUTRAM will be used\n", " * `block`: BRAM will be used\n", @@ -1216,7 +1216,8 @@ "id": "37b6853d", "metadata": {}, "source": [ - "Let's have a look at the additional builder arguments. We want to only filter out the FINN specific arguments." + "Next to the enablement of the verification flows, the FINN builder has numerous additional builder arguments to further customize your network. \n", + "Let's have a look at the options for the arguments. We want to only filter out the FINN specific arguments." ] }, { @@ -1236,8 +1237,9 @@ "id": "b12ab370", "metadata": {}, "source": [ - "There are attributes that come from the dataclasses-json class: `to_dict`, `to_json`, `schema`, `from_json`, `from_dict`. These are not FINN builder specific. Some of the arguments we have seen already in the Cybersecurity notebook and in this notebook, e.g. target_fps, fpga_part, folding_config_file, ...\n", - "Please have a look here and scroll through the available builder arguments: https://github.com/Xilinx/finn/blob/dev/src/finn/builder/build_dataflow_config.py#L155" + "There are attributes that come from the dataclasses-json class: `to_dict`, `to_json`, `schema`, `from_json`, `from_dict`. This class is used for the implementation of the FINN builder. In this tutorial, we are mainly interested in the FINN specific arguments. \n", + "\n", + "Some of these arguments we have seen already in the Cybersecurity notebook and in this notebook, e.g. target_fps, fpga_part and folding_config_file. In the code of the FINN builder, the function of each builder argument is documents, you can have a look [here](https://github.com/Xilinx/finn/blob/dev/src/finn/builder/build_dataflow_config.py#L155) and scroll through the available builder arguments." ] }, { @@ -1245,7 +1247,9 @@ "id": "9aba0493", "metadata": {}, "source": [ - "So far, in this notebook, we only looked at configurations up to the generation of estimate reports, a lot of these builder arguments actually become relevant at a later stage in the FINN flow." + "So far, in this notebook, we only looked at configurations up to the generation of estimate reports, a lot of these builder arguments actually become relevant at a later stage in the FINN flow.\n", + "\n", + "Let's have a look at the default build dataflow steps for the complete FINN flow." ] }, { @@ -1258,6 +1262,15 @@ "print(\"\\n\".join(build_cfg.default_build_dataflow_steps))" ] }, + { + "cell_type": "markdown", + "id": "b9bc5715", + "metadata": {}, + "source": [ + "You can see that after the generation of the estimate reports, the code generation and the ip generation is invoked (`step_hls_codegen` and `step_hls_ipgen`). The FIFO depths are determined and the FIFOs are inserted in the network (`step_set_fifo_depths`), we can then create an IP design of our whole network by stitching the IPs from each layer together (`step_create_stitched_ip`). At this point we have an implementation of the neural network that we can integrate within a bigger FPGA design, we can run performance measurements using simulation (`step_measure_rtlsim_performance`) and out-of-context synthesis (`step_out_of_context_synthesis`) for it.\n", + "The FINN builder also provides automatic system integration for Zynq and Alveo devices, this can be invoked by running `step_synthesize_bitfile`, `step_make_pynq_driver` and `step_deployment_package`." + ] + }, { "cell_type": "markdown", "id": "76df000f", @@ -1274,7 +1287,25 @@ "outputs": [], "source": [ "import finn.builder.build_dataflow_steps as build_dataflow_steps\n", - "print(build_dataflow_steps.step_create_dataflow_partition.__doc__)" + "print(build_dataflow_steps.step_hls_codegen.__doc__)" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "c84a9fbc", + "metadata": {}, + "outputs": [], + "source": [ + "showSrc(build_dataflow_steps.step_hls_codegen)" + ] + }, + { + "cell_type": "markdown", + "id": "c249f141", + "metadata": {}, + "source": [ + "This concludes the advanced builder settings tutorial. Below you can find code that can help you investigating more of the builder arguments and invoking the whole flow to generate a bitfile." ] }, { @@ -1282,7 +1313,7 @@ "id": "3b98eb65", "metadata": {}, "source": [ - "### Examples for additional builder arguments " + "### Examples for additional builder arguments & bitfile generation " ] }, { @@ -1293,6 +1324,21 @@ "#### Standalone Thresholds" ] }, + { + "cell_type": "markdown", + "id": "e21ff36f", + "metadata": {}, + "source": [ + "In FINN, convolutions are expressed with three components:\n", + "* An Im2Col operation\n", + "* A matrix multiplication\n", + "* A MultiThreshold operation\n", + "\n", + "When converting these nodes into HLS layers, by default the MatMul and the MultiThreshold gets converted into **one** component called Matrix-Vector-Activation Unit (MVAU). But the FINN compiler allows us to implement the activation separately. This gives an additional possibility for customization because we can adjust the folding parameters of the standalone threshold unit independently. \n", + "\n", + "If you would like to enable this feature, you can set the build argument `standalone_thresholds` to `True`. In the code below this feature is enabled and you can have a look at the generated .onnx file. Please note that you need to uncomment the code first." + ] + }, { "cell_type": "code", "execution_count": null, @@ -1348,8 +1394,8 @@ "metadata": {}, "outputs": [], "source": [ - "%%time\n", - "build.build_dataflow_cfg(model_file, cfg_estimates);" + "#%%time\n", + "#build.build_dataflow_cfg(model_file, cfg_estimates);" ] }, { @@ -1359,7 +1405,7 @@ "metadata": {}, "outputs": [], "source": [ - "showInNetron(build_dir+\"/output_standalone_thresholds/intermediate_models/step_generate_estimate_reports.onnx\")" + "#showInNetron(build_dir+\"/output_standalone_thresholds/intermediate_models/step_generate_estimate_reports.onnx\")" ] }, { @@ -1370,6 +1416,26 @@ "#### RTL Convolutional Input Generator" ] }, + { + "cell_type": "markdown", + "id": "b85e5ac7", + "metadata": {}, + "source": [ + "Recently, we have worked on the *Operator Hardening* in the FINN compiler. This means that we implement core building blocks in RTL instead of using HLS.\n", + "One of these components is already available in the FINN compiler, you can enable the RTL implementation of the ConvolutionInputGenerator (aka Sliding Window Generator) by setting the build argument `force_rtl_conv_inp_gen` to `True`.\n", + "In the code below this feature is enabled and you can have a look at the generated .onnx file. Please note that you need to uncomment the code first." + ] + }, + { + "cell_type": "markdown", + "id": "2a90b63f", + "metadata": {}, + "source": [ + "
    \n", + "Important notice: We are actively working on the integration of RTL components in the FINN flow, the enablement like shown below might change in the future.\n", + "
    " + ] + }, { "cell_type": "code", "execution_count": null, @@ -1425,8 +1491,8 @@ "metadata": {}, "outputs": [], "source": [ - "%%time\n", - "build.build_dataflow_cfg(model_file, cfg_estimates);" + "#%%time\n", + "#build.build_dataflow_cfg(model_file, cfg_estimates);" ] }, { @@ -1436,7 +1502,95 @@ "metadata": {}, "outputs": [], "source": [ - "showInNetron(build_dir+\"/output_rtl_swg/intermediate_models/step_generate_estimate_reports.onnx\")" + "#showInNetron(build_dir+\"/output_rtl_swg/intermediate_models/step_generate_estimate_reports.onnx\")" + ] + }, + { + "cell_type": "markdown", + "id": "601eb5f8", + "metadata": {}, + "source": [ + "#### Run the whole flow" + ] + }, + { + "cell_type": "markdown", + "id": "42aa929b", + "metadata": {}, + "source": [ + "The code below can be used to invoke the full builder flow and obtain more output products, be aware that this runs synthesis and bitfile generation and it might take up to an hour. Please note that you need to uncomment the code first." + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "4efd46f4", + "metadata": {}, + "outputs": [], + "source": [ + "## Build flow with hardware build\n", + "\n", + "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/advanced\"\n", + "model_file = model_dir + \"/end2end_cnv_w2a2_export.onnx\"\n", + "\n", + "output_dir = \"output_bitfile\"\n", + "\n", + "#Delete previous run results if exist\n", + "if os.path.exists(output_dir):\n", + " shutil.rmtree(output_dir)\n", + " print(\"Previous run results deleted!\")\n", + "\n", + "build_steps = [\n", + " custom_step_add_pre_proc,\n", + " custom_step_add_post_proc,\n", + " \"step_qonnx_to_finn\",\n", + " \"step_tidy_up\",\n", + " \"step_streamline\",\n", + " \"step_convert_to_hls\",\n", + " \"step_create_dataflow_partition\",\n", + " \"step_target_fps_parallelization\",\n", + " \"step_apply_folding_config\",\n", + " \"step_minimize_bit_width\",\n", + " \"step_generate_estimate_reports\",\n", + " \"step_hls_codegen\",\n", + " \"step_hls_ipgen\",\n", + " \"step_set_fifo_depths\",\n", + " \"step_create_stitched_ip\",\n", + " \"step_measure_rtlsim_performance\",\n", + " \"step_out_of_context_synthesis\",\n", + " \"step_synthesize_bitfile\",\n", + " \"step_make_pynq_driver\",\n", + " \"step_deployment_package\",\n", + "]\n", + "\n", + "cfg_build = build.DataflowBuildConfig(\n", + " output_dir = output_dir,\n", + " mvau_wwidth_max = 80,\n", + " target_fps = 1000000,\n", + " synth_clk_period_ns = 10.0,\n", + " fpga_part = \"xc7z020clg400-1\",\n", + " steps = build_steps,\n", + " generate_outputs=[\n", + " build_cfg.DataflowOutputType.ESTIMATE_REPORTS,\n", + " build_cfg.DataflowOutputType.STITCHED_IP,\n", + " build_cfg.DataflowOutputType.RTLSIM_PERFORMANCE,\n", + " build_cfg.DataflowOutputType.OOC_SYNTH,\n", + " build_cfg.DataflowOutputType.BITFILE,\n", + " build_cfg.DataflowOutputType.PYNQ_DRIVER,\n", + " build_cfg.DataflowOutputType.DEPLOYMENT_PACKAGE,\n", + " ],\n", + ")" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "c7ff6c19", + "metadata": {}, + "outputs": [], + "source": [ + "%%time\n", + "build.build_dataflow_cfg(model_file, cfg_build);" ] } ], From 3295c9bdd60fa1e8a99ae32de456e84ff7decda6 Mon Sep 17 00:00:00 2001 From: auphelia Date: Sat, 2 Sep 2023 22:30:47 +0100 Subject: [PATCH 273/665] [nb] Comment last build flow run --- notebooks/advanced/4_advanced_builder_settings.ipynb | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/notebooks/advanced/4_advanced_builder_settings.ipynb b/notebooks/advanced/4_advanced_builder_settings.ipynb index aa244e4983..8e0e3ef8cf 100644 --- a/notebooks/advanced/4_advanced_builder_settings.ipynb +++ b/notebooks/advanced/4_advanced_builder_settings.ipynb @@ -1518,7 +1518,7 @@ "id": "42aa929b", "metadata": {}, "source": [ - "The code below can be used to invoke the full builder flow and obtain more output products, be aware that this runs synthesis and bitfile generation and it might take up to an hour. Please note that you need to uncomment the code first." + "The code below can be used to invoke the full builder flow and obtain more output products, be aware that this runs synthesis and bitfile generation and it might take over an hour. Please note that you need to uncomment the code first." ] }, { @@ -1566,7 +1566,7 @@ "cfg_build = build.DataflowBuildConfig(\n", " output_dir = output_dir,\n", " mvau_wwidth_max = 80,\n", - " target_fps = 1000000,\n", + " target_fps = 100,\n", " synth_clk_period_ns = 10.0,\n", " fpga_part = \"xc7z020clg400-1\",\n", " steps = build_steps,\n", @@ -1589,8 +1589,8 @@ "metadata": {}, "outputs": [], "source": [ - "%%time\n", - "build.build_dataflow_cfg(model_file, cfg_build);" + "#%%time\n", + "#build.build_dataflow_cfg(model_file, cfg_build);" ] } ], From c7cbe5e5f478fe73caf7aa3c1ffac53a519dc33e Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 18 Sep 2023 10:27:51 +0100 Subject: [PATCH 274/665] [nb] Update final build flow --- .../4_advanced_builder_settings.ipynb | 40 +++++++++++++++---- 1 file changed, 32 insertions(+), 8 deletions(-) diff --git a/notebooks/advanced/4_advanced_builder_settings.ipynb b/notebooks/advanced/4_advanced_builder_settings.ipynb index 8e0e3ef8cf..38bc19a6ca 100644 --- a/notebooks/advanced/4_advanced_builder_settings.ipynb +++ b/notebooks/advanced/4_advanced_builder_settings.ipynb @@ -154,7 +154,7 @@ "cfg_estimates = build.DataflowBuildConfig(\n", " output_dir = estimates_output_dir,\n", " mvau_wwidth_max = 80,\n", - " target_fps = 1000000,\n", + " target_fps = 10000,\n", " synth_clk_period_ns = 10.0,\n", " fpga_part = \"xc7z020clg400-1\",\n", " steps = build_cfg.estimate_only_dataflow_steps,\n", @@ -450,7 +450,7 @@ "cfg_estimates = build.DataflowBuildConfig(\n", " output_dir = output_dir,\n", " mvau_wwidth_max = 80,\n", - " target_fps = 1000000,\n", + " target_fps = 10000,\n", " synth_clk_period_ns = 10.0,\n", " fpga_part = \"xc7z020clg400-1\",\n", " steps = build_steps,\n", @@ -559,7 +559,7 @@ "cfg_estimates = build.DataflowBuildConfig(\n", " output_dir = output_dir,\n", " mvau_wwidth_max = 80,\n", - " target_fps = 1000000,\n", + " target_fps = 10000,\n", " synth_clk_period_ns = 10.0,\n", " fpga_part = \"xc7z020clg400-1\",\n", " steps = build_steps,\n", @@ -1114,7 +1114,7 @@ "cfg_estimates = build.DataflowBuildConfig(\n", " output_dir = output_dir,\n", " mvau_wwidth_max = 80,\n", - " target_fps = 1000000,\n", + " target_fps = 10000,\n", " synth_clk_period_ns = 10.0,\n", " fpga_part = \"xc7z020clg400-1\",\n", " steps = build_steps,\n", @@ -1376,7 +1376,7 @@ "cfg_estimates = build.DataflowBuildConfig(\n", " output_dir = output_dir,\n", " mvau_wwidth_max = 80,\n", - " target_fps = 1000000,\n", + " target_fps = 10000,\n", " synth_clk_period_ns = 10.0,\n", " fpga_part = \"xc7z020clg400-1\",\n", " standalone_thresholds = True,\n", @@ -1473,7 +1473,7 @@ "cfg_estimates = build.DataflowBuildConfig(\n", " output_dir = output_dir,\n", " mvau_wwidth_max = 80,\n", - " target_fps = 1000000,\n", + " target_fps = 10000,\n", " synth_clk_period_ns = 10.0,\n", " fpga_part = \"xc7z020clg400-1\",\n", " force_rtl_conv_inp_gen = True,\n", @@ -1521,6 +1521,24 @@ "The code below can be used to invoke the full builder flow and obtain more output products, be aware that this runs synthesis and bitfile generation and it might take over an hour. Please note that you need to uncomment the code first." ] }, + { + "cell_type": "markdown", + "id": "ffa2a352", + "metadata": {}, + "source": [ + "For an optimized design, we download the folding configuration for cnv-w2a2 on the Pynq-Z1 board from [finn-examples](https://github.com/Xilinx/finn-examples). And will pass it to the build flow. Please also note below that we now pass the board as argument to the builder (`board = \"Pynq-Z1\"`) instead of just the fpga part. This time we will select all possible outputs to generate. Please be aware that running the full build might take a few hours." + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "765e5ee7", + "metadata": {}, + "outputs": [], + "source": [ + "!wget https://raw.githubusercontent.com/Xilinx/finn-examples/main/build/bnn-pynq/folding_config/cnv-w2a2_folding_config.json" + ] + }, { "cell_type": "code", "execution_count": null, @@ -1528,6 +1546,11 @@ "metadata": {}, "outputs": [], "source": [ + "import finn.builder.build_dataflow as build\n", + "import finn.builder.build_dataflow_config as build_cfg\n", + "import os\n", + "import shutil\n", + "\n", "## Build flow with hardware build\n", "\n", "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/advanced\"\n", @@ -1566,9 +1589,10 @@ "cfg_build = build.DataflowBuildConfig(\n", " output_dir = output_dir,\n", " mvau_wwidth_max = 80,\n", - " target_fps = 100,\n", " synth_clk_period_ns = 10.0,\n", - " fpga_part = \"xc7z020clg400-1\",\n", + " folding_config_file = \"cnv-w2a2_folding_config.json\",\n", + " board = \"Pynq-Z1\",\n", + " shell_flow_type = build_cfg.ShellFlowType.VIVADO_ZYNQ,\n", " steps = build_steps,\n", " generate_outputs=[\n", " build_cfg.DataflowOutputType.ESTIMATE_REPORTS,\n", From ed163af32f0a43382f19145138432a042840bc55 Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 18 Sep 2023 10:37:34 +0100 Subject: [PATCH 275/665] [Tests] Integrate advanced notebook into test suite --- tests/notebooks/test_jupyter_notebooks.py | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/notebooks/test_jupyter_notebooks.py b/tests/notebooks/test_jupyter_notebooks.py index c2542380f1..e1415b9066 100644 --- a/tests/notebooks/test_jupyter_notebooks.py +++ b/tests/notebooks/test_jupyter_notebooks.py @@ -21,6 +21,7 @@ pytest.param(notebook_advanced_dir + "1_custom_transformation_pass.ipynb"), pytest.param(notebook_advanced_dir + "2_custom_op.ipynb"), pytest.param(notebook_advanced_dir + "3_folding.ipynb"), + pytest.param(notebook_advanced_dir + "4_advanced_builder_settings.ipynb"), ] cyber_notebooks = [ From 2d42e9b8650942aad6a52fb7378548238fcc43ff Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 18 Sep 2023 11:01:15 +0100 Subject: [PATCH 276/665] [NBs] Make paths in advanced notebook absolute for testing --- notebooks/advanced/4_advanced_builder_settings.ipynb | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/notebooks/advanced/4_advanced_builder_settings.ipynb b/notebooks/advanced/4_advanced_builder_settings.ipynb index 38bc19a6ca..4af48ac233 100644 --- a/notebooks/advanced/4_advanced_builder_settings.ipynb +++ b/notebooks/advanced/4_advanced_builder_settings.ipynb @@ -190,7 +190,7 @@ "metadata": {}, "outputs": [], "source": [ - "!ls -t -r output_estimates_only/intermediate_models" + "!ls -t -r {build_dir}/output_estimates_only/intermediate_models" ] }, { @@ -478,7 +478,7 @@ "metadata": {}, "outputs": [], "source": [ - "!ls -t -r output_pre_proc/intermediate_models" + "!ls -t -r {build_dir}/output_pre_proc/intermediate_models" ] }, { @@ -587,7 +587,7 @@ "metadata": {}, "outputs": [], "source": [ - "!ls -t -r output_pre_and_post_proc/intermediate_models" + "!ls -t -r {build_dir}/output_pre_and_post_proc/intermediate_models" ] }, { @@ -1163,7 +1163,7 @@ "metadata": {}, "outputs": [], "source": [ - "!ls output_with_verification" + "!ls {build_dir}/output_with_verification" ] }, { @@ -1173,7 +1173,7 @@ "metadata": {}, "outputs": [], "source": [ - "!ls output_with_verification/verification_output" + "!ls {build_dir}/output_with_verification/verification_output" ] }, { From bbda540140427aa1d43a7f78c7e79332bc4e7bbe Mon Sep 17 00:00:00 2001 From: johnnoel Date: Fri, 22 Sep 2023 16:03:46 +0100 Subject: [PATCH 277/665] Update .Xilinx messaging --- docker/finn_entrypoint.sh | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/docker/finn_entrypoint.sh b/docker/finn_entrypoint.sh index b441c9359a..6b33a4c9bc 100644 --- a/docker/finn_entrypoint.sh +++ b/docker/finn_entrypoint.sh @@ -118,6 +118,7 @@ if [ -d "$FINN_ROOT/.Xilinx" ]; then mkdir "$HOME/.Xilinx" if [ -f "$FINN_ROOT/.Xilinx/HLS_init.tcl" ]; then cp "$FINN_ROOT/.Xilinx/HLS_init.tcl" "$HOME/.Xilinx/" + gecho "Found HLS_init.tcl and copied to $HOME/.Xilinx/HLS_init.tcl" else yecho "Unable to find $FINN_ROOT/.Xilinx/HLS_init.tcl" fi @@ -125,14 +126,13 @@ if [ -d "$FINN_ROOT/.Xilinx" ]; then if [ -f "$FINN_ROOT/.Xilinx/Vivado/Vivado_init.tcl" ]; then mkdir "$HOME/.Xilinx/Vivado/" cp "$FINN_ROOT/.Xilinx/Vivado/Vivado_init.tcl" "$HOME/.Xilinx/Vivado/" + gecho "Found Vivado_init.tcl and copied to $HOME/.Xilinx/Vivado/Vivado_init.tcl" else yecho "Unable to find $FINN_ROOT/.Xilinx/Vivado/Vivado_init.tcl" fi else - yecho "Unable to find $FINN_ROOT/.Xilinx" - yecho "Functionality dependent on beta devices will not be available." - yecho "If you need to enable a beta device, ensure .Xilinx/HLS_init.tcl and/or .Xilinx/Vivado/Vivado_init.tcl " - yecho "are set correctly and mounted into the Docker container." + echo "If you need to enable a beta device, ensure .Xilinx/HLS_init.tcl and/or .Xilinx/Vivado/Vivado_init.tcl are set correctly and mounted" + echo "See https://docs.xilinx.com/r/en-US/ug835-vivado-tcl-commands/Tcl-Initialization-Scripts" fi export PATH=$PATH:$HOME/.local/bin From 161544ae8765b6fe29ef37e5184ab8eca6eee7a1 Mon Sep 17 00:00:00 2001 From: johnnoel Date: Fri, 29 Sep 2023 11:16:57 +0100 Subject: [PATCH 278/665] Move successful archive step to parallel stage instead of post --- docker/jenkins/Jenkinsfile | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index f4f0533c3f..1f86ac1ef6 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -69,6 +69,9 @@ pipeline { // Use an env variable to help collect test results later in pipeline env.SANITY_UT = "SUCCESS" + + // Archive coverage report if successful + archiveSuccessfulStage(env.SANITY_UT, "coverage_sanity_ut") } } } @@ -97,6 +100,9 @@ pipeline { // Use an env variable to help collect test results later in pipeline env.FPGADATAFLOW_RESULT = "SUCCESS" + + // Archive coverage report if successful + archiveSuccessfulStage(env.FPGADATAFLOW_RESULT, "coverage_fpgadataflow") } } } @@ -729,9 +735,6 @@ pipeline { archiveArtifacts artifacts: "reports/*.xml" archiveArtifacts artifacts: "reports/*.html" - archiveSuccessfulStage(env.SANITY_UT, "coverage_sanity_ut") - archiveSuccessfulStage(env.FPGADATAFLOW_RESULT, "coverage_fpgadataflow") - // Plot what XML files were created during the test run junit 'reports/*.xml' } From dd7806eff7b80212440d115886f16c26773de1a6 Mon Sep 17 00:00:00 2001 From: johnnoel Date: Mon, 2 Oct 2023 16:37:06 +0100 Subject: [PATCH 279/665] [CI] Append a space to FINN_DOCKER_EXTRA to avoid malformed docker commands Jenkins unexpectedly trims trailing spaces from env variables. This leads to badly formed inputs for docker. Appending an extra space solves this issues and causes no further problems. --- run-docker.sh | 3 +++ 1 file changed, 3 insertions(+) diff --git a/run-docker.sh b/run-docker.sh index c24dcec724..8df03636bb 100755 --- a/run-docker.sh +++ b/run-docker.sh @@ -100,6 +100,9 @@ SCRIPTPATH=$(dirname "$SCRIPT") DOCKER_INTERACTIVE="" +# Catch FINN_DOCKER_EXTRA options being passed in without a trailing space +FINN_DOCKER_EXTRA+=" " + if [ "$1" = "test" ]; then gecho "Running test suite (all tests)" DOCKER_CMD="python setup.py test" From 457400b5328c73ef3babfc1cd7e3560b94d8b84a Mon Sep 17 00:00:00 2001 From: hlebleve Date: Thu, 5 Oct 2023 09:50:17 +0200 Subject: [PATCH 280/665] Updating InferPixelPaddingDeconv to just do the lowering and not the full conversion to HLS layers --- .../infer_pixel_padding_deconv.py | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/infer_pixel_padding_deconv.py b/src/finn/transformation/fpgadataflow/infer_pixel_padding_deconv.py index aa579dcdb6..404795a80d 100644 --- a/src/finn/transformation/fpgadataflow/infer_pixel_padding_deconv.py +++ b/src/finn/transformation/fpgadataflow/infer_pixel_padding_deconv.py @@ -5,10 +5,10 @@ from qonnx.transformation.lower_convs_to_matmul import _auto_pad_to_explicit_padding from qonnx.util.basic import get_by_name -from finn.transformation.fpgadataflow.convert_to_hls_layers import ( - InferConvInpGen, - InferQuantizedMatrixVectorActivation, -) +# from finn.transformation.fpgadataflow.convert_to_hls_layers import ( +# InferConvInpGen, +# InferQuantizedMatrixVectorActivation, +# ) class InferPixelPaddingDeconv(Transformation): @@ -27,9 +27,10 @@ def apply(self, model): deconv_output = n.output[0] idt = model.get_tensor_datatype(deconv_input) odt = model.get_tensor_datatype(deconv_output) - if not idt.is_integer(): - warnings.warn("%s : Input is not int. Can't infer PixelPaddingDeconv." % n.name) - continue + # if not idt.is_integer(): + # warnings.warn("%s : Input is not int. + # Can't infer PixelPaddingDeconv." % n.name) + # continue # extract conv transpose parameters k_h = get_by_name(n.attribute, "kernel_shape").ints[0] k_w = get_by_name(n.attribute, "kernel_shape").ints[1] @@ -205,6 +206,6 @@ def apply(self, model): # remove old nodes graph.node.remove(n) - model = model.transform(InferConvInpGen(use_rtl_variant=self.use_convinpgen_rtl_variant)) - model = model.transform(InferQuantizedMatrixVectorActivation()) + # model = model.transform(InferConvInpGen(use_rtl_variant=self.use_convinpgen_rtl_variant)) + # model = model.transform(InferQuantizedMatrixVectorActivation()) return (model, graph_modified) From aba05c5632e02e56e4ed6b660c3c317b64fd7186 Mon Sep 17 00:00:00 2001 From: hlebleve Date: Thu, 5 Oct 2023 09:54:45 +0200 Subject: [PATCH 281/665] Updating QONNX commit has --- fetch-repos.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fetch-repos.sh b/fetch-repos.sh index a88ebae1c3..b5622016b5 100755 --- a/fetch-repos.sh +++ b/fetch-repos.sh @@ -27,7 +27,7 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -QONNX_COMMIT="ca897bc6e972d94ef158f1d87cc84e29fd0133f3" +QONNX_COMMIT="47e4357faf66b5b0d1bf77bf908bb47752421e5b" FINN_EXP_COMMIT="0aa7e1c44b20cf085b6fe42cff360f0a832afd2c" BREVITAS_COMMIT="9bb26bf2798de210a267d1e4aed4c20087e0e8a5" PYVERILATOR_COMMIT="766e457465f5c0dd315490d7b9cc5d74f9a76f4f" From 56b155fb60651ac8d9bf1d68603808ce78bb0fee Mon Sep 17 00:00:00 2001 From: johnnoel Date: Thu, 5 Oct 2023 15:31:39 +0100 Subject: [PATCH 282/665] [CI] Address PR comments --- docker/jenkins/Jenkinsfile | 36 +++++++++++++++++++++++------------- 1 file changed, 23 insertions(+), 13 deletions(-) diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index 1f86ac1ef6..2d7ea5e918 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -126,7 +126,7 @@ pipeline { catchError(stageResult: 'FAILURE') { script { // Delete any build files from a previous build - sh "rm -rf ${env.FINN_HOST_BUILD_DIR}/*" + cleanPreviousBuildFiles(env.FINN_HOST_BUILD_DIR) // Pass in the marker to run with pytest and the XML test results filename runDockerPytestWithMarker(env.TEST_NAME, "${env.TEST_NAME}", '') @@ -310,7 +310,7 @@ pipeline { catchError(stageResult: 'FAILURE') { script { // Clean any files from a previous run - sh "rm -rf ${env.BOARD}*" + cleanPreviousBuildFiles("${env.BOARD}*") // Get the test files unstash name: "sanity_${env.BOARD}_zip" @@ -358,7 +358,7 @@ pipeline { catchError(stageResult: 'FAILURE') { script { // Clean any files from a previous run - sh "echo $USER_CREDENTIALS_PSW | sudo -S rm -rf ${env.BOARD}*" + cleanPreviousBoardBuildFiles("${env.BOARD}*") // Get the test files unstash name: "sanity_PynqZ1_zip" @@ -409,7 +409,7 @@ pipeline { catchError(stageResult: 'FAILURE') { script { // Clean any files from a previous run - sh "echo $USER_CREDENTIALS_PSW | sudo -S rm -rf ${env.BOARD}*" + cleanPreviousBoardBuildFiles("${env.BOARD}*") // Get the test files unstash name: "sanity_${env.BOARD}_zip" @@ -458,7 +458,7 @@ pipeline { catchError(stageResult: 'FAILURE') { script { // Clean any files from a previous run - sh "echo $USER_CREDENTIALS_PSW | sudo -S rm -rf ${env.BOARD}*" + cleanPreviousBoardBuildFiles("${env.BOARD}*") // Get the test files unstash name: "sanity_${env.BOARD}_zip" @@ -510,7 +510,7 @@ pipeline { catchError(stageResult: 'FAILURE') { script { // Clean any files from a previous run - sh "rm -rf ${env.BOARD}*" + cleanPreviousBuildFiles("${env.BOARD}*") // Get the test files unstash name: "${env.BOARD}_zip" @@ -558,7 +558,7 @@ pipeline { catchError(stageResult: 'FAILURE') { script { // Clean any files from a previous run - sh "echo $USER_CREDENTIALS_PSW | sudo -S rm -rf ${env.BOARD}*" + cleanPreviousBoardBuildFiles("${env.BOARD}*") // Get the test files unstash name: "PynqZ1_zip" @@ -609,7 +609,7 @@ pipeline { catchError(stageResult: 'FAILURE') { script { // Clean any files from a previous run - sh "echo $USER_CREDENTIALS_PSW | sudo -S rm -rf ${env.BOARD}*" + cleanPreviousBoardBuildFiles("${env.BOARD}*") // Get the test files unstash name: "${env.BOARD}_zip" @@ -658,7 +658,7 @@ pipeline { catchError(stageResult: 'FAILURE') { script { // Clean any files from a previous run - sh "echo $USER_CREDENTIALS_PSW | sudo -S rm -rf ${env.BOARD}*" + cleanPreviousBoardBuildFiles("${env.BOARD}*") // Get the test files unstash name: "${env.BOARD}_zip" @@ -747,7 +747,17 @@ pipeline { void cleanPreviousBuildFiles(String buildDir) { // Delete any build files from a previous build // Previous build folders affect findCopyZip() and can cause the stage to fail - sh "rm -rf ${buildDir}/*" + if (!buildDir.empty) { + sh "rm -rf ${buildDir}" + } +} + +void cleanPreviousBoardBuildFiles(String boardDir) { + // Delete any board build files + // Specifically used on Pynq boards which require sudo to delete + if (!boardDir.empty) { + sh "echo $USER_CREDENTIALS_PSW | sudo -S rm -rf ${boardDir}*" + } } void createMultiMarkerScript(String markers, String testResultsFilename, String additionalOptions) { @@ -765,7 +775,7 @@ void runDockerPytestWithMarker(String marker, String testResultsFilename, String sh """./run-docker.sh python -m pytest -m ${marker} --junitxml=${testResultsFilename}.xml --html=${testResultsFilename}.html --self-contained-html ${additionalOptions}""" } -void findBoardBuildFiles(String board, String searchDir, String dirToFind) { +def findBoardBuildFiles(String searchDir, String dirToFind) { def result = sh(script: "find $searchDir -type d -name \"$dirToFind*\"", returnStdout: true).trim() if (result.empty) { error "Directory containing '$dirToFind' not found." @@ -774,7 +784,7 @@ void findBoardBuildFiles(String board, String searchDir, String dirToFind) { } void findCopyZip(String board, String findDir, String copyDir, String stashName) { - def buildDir = findBoardBuildFiles(board, findDir, "hw_deployment_${board}") + def buildDir = findBoardBuildFiles(findDir, "hw_deployment_${board}") sh "cp -r ${buildDir}/${board} ${copyDir}/" dir(copyDir) { sh "zip -r ${board}.zip ${board}/" @@ -802,7 +812,7 @@ python -m pytest -m ${marker} --junitxml=${testResultsFilename}.xml --html=${tes sh 'chmod 777 run-tests.sh' } -void isNodeOnline(String labelName) { +def isNodeOnline(String labelName) { Label label = Jenkins.instance.getLabel(labelName) def agentOnline = false From 206737f9bbb2ff90a8ead03422cc7aac2e3dc7ac Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 6 Oct 2023 14:21:55 +0100 Subject: [PATCH 283/665] [Fix] Deprecate pkg-resources and update setuptools --- .isort.cfg | 2 +- .../bnn-pynq/cnv_end2end_example.ipynb | 11 ++++++----- requirements.txt | 2 ++ setup.py | 10 ---------- .../transformation/fpgadataflow/create_stitched_ip.py | 4 +--- .../transformation/fpgadataflow/make_pynq_driver.py | 11 +++++------ src/finn/util/pyverilator.py | 6 ++---- src/finn/util/test.py | 8 ++++---- tests/brevitas/test_brevitas_cnv.py | 8 ++++---- tests/end2end/test_end2end_cybsec_mlp.py | 4 +--- tests/end2end/test_ext_weights.py | 7 ++----- tests/fpgadataflow/test_convert_to_hls_layers_cnv.py | 8 ++++---- .../transformation/streamline/test_streamline_cnv.py | 8 ++++---- .../test_batchnorm_to_affine_bnn_pynq.py | 8 ++++---- tests/transformation/test_qonnx_to_finn.py | 8 ++++---- tests/util/test_build_dataflow.py | 4 +--- 16 files changed, 45 insertions(+), 64 deletions(-) diff --git a/.isort.cfg b/.isort.cfg index 6cfe1c8919..5378b88fad 100644 --- a/.isort.cfg +++ b/.isort.cfg @@ -2,7 +2,7 @@ line_length=88 indent=' ' skip=.tox,.venv,build,dist -known_standard_library=setuptools,pkg_resources +known_standard_library=setuptools known_test=pytest known_first_party=finn sections=FUTURE,STDLIB,TEST,THIRDPARTY,FIRSTPARTY,LOCALFOLDER diff --git a/notebooks/end2end_example/bnn-pynq/cnv_end2end_example.ipynb b/notebooks/end2end_example/bnn-pynq/cnv_end2end_example.ipynb index a0dbbf4834..9e9d52e476 100644 --- a/notebooks/end2end_example/bnn-pynq/cnv_end2end_example.ipynb +++ b/notebooks/end2end_example/bnn-pynq/cnv_end2end_example.ipynb @@ -516,12 +516,13 @@ "metadata": {}, "outputs": [], "source": [ - "import pkg_resources as pk\n", + "import importlib_resources\n", "import matplotlib.pyplot as plt\n", "import numpy as np\n", "\n", - "fn = pk.resource_filename(\"finn.qnn-data\", \"cifar10/cifar10-test-data-class3.npz\")\n", - "x = np.load(fn)[\"arr_0\"]\n", + "ref = importlib_resources.files(\"finn.qnn-data\") / \"cifar10/cifar10-test-data-class3.npz\"\n", + "with importlib_resources.as_file(ref) as fn:\n", + " x = np.load(fn)[\"arr_0\"]\n", "x = x.reshape(3, 32,32).transpose(1, 2, 0)\n", "plt.imshow(x)" ] @@ -640,9 +641,9 @@ "name": "python", "nbconvert_exporter": "python", "pygments_lexer": "ipython3", - "version": "3.10.6" + "version": "3.10.12" } }, "nbformat": 4, - "nbformat_minor": 2 + "nbformat_minor": 4 } diff --git a/requirements.txt b/requirements.txt index 1427d4f1ee..e03eff2c98 100644 --- a/requirements.txt +++ b/requirements.txt @@ -2,6 +2,7 @@ bitstring==3.1.7 clize==5.0.1 dataclasses-json==0.5.7 gspread==3.6.0 +importlib-resources==6.1.0 ipython==8.12.2 numpy==1.24.1 onnx==1.13.0 @@ -13,6 +14,7 @@ psutil==5.9.4 pyscaffold==4.4 scipy==1.10.1 setupext-janitor>=1.1.2 +setuptools==68.2.2 sigtools==4.0.1 toposort==1.7.0 vcdvcd==1.0.5 diff --git a/setup.py b/setup.py index 8fd781462c..7457bb9b38 100644 --- a/setup.py +++ b/setup.py @@ -35,17 +35,7 @@ PyScaffold helps you to put up the scaffold of your new Python project. Learn more under: https://pyscaffold.org/ """ -from pkg_resources import VersionConflict, require from setuptools import setup -import sys - -try: - require("setuptools>=38.3") -except VersionConflict: - print("Error: version of setuptools is too old (<38.3)!") - sys.exit(1) - - if __name__ == "__main__": setup(use_pyscaffold=True) diff --git a/src/finn/transformation/fpgadataflow/create_stitched_ip.py b/src/finn/transformation/fpgadataflow/create_stitched_ip.py index c9db69400b..9a653fe404 100644 --- a/src/finn/transformation/fpgadataflow/create_stitched_ip.py +++ b/src/finn/transformation/fpgadataflow/create_stitched_ip.py @@ -26,8 +26,6 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import pkg_resources as pk - import json import multiprocessing as mp import os @@ -499,7 +497,7 @@ def apply(self, model): "[ipx::get_file_groups xilinx_simulationcheckpoint]" % block_name ) # add a rudimentary driver mdd to get correct ranges in xparameters.h later on - example_data_dir = pk.resource_filename("finn.qnn-data", "mdd-data/") + example_data_dir = os.environ["FINN_ROOT"] + "/src/finn/qnn-data/mdd-data" copytree(example_data_dir, vivado_stitch_proj_dir + "/data") ##### diff --git a/src/finn/transformation/fpgadataflow/make_pynq_driver.py b/src/finn/transformation/fpgadataflow/make_pynq_driver.py index 5a0e47c130..6d1fa290b4 100644 --- a/src/finn/transformation/fpgadataflow/make_pynq_driver.py +++ b/src/finn/transformation/fpgadataflow/make_pynq_driver.py @@ -26,9 +26,6 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -import pkg_resources as pk - import numpy as np import os import qonnx @@ -89,8 +86,8 @@ def apply(self, model): model.set_metadata_prop("pynq_driver_dir", pynq_driver_dir) # create the base FINN driver -- same for all accels - driver_base_template = pk.resource_filename( - "finn.qnn-data", "templates/driver/driver_base.py" + driver_base_template = ( + os.environ["FINN_ROOT"] + "/src/finn/qnn-data/templates/driver/driver_base.py" ) driver_base_py = pynq_driver_dir + "/driver_base.py" shutil.copy(driver_base_template, driver_base_py) @@ -268,7 +265,9 @@ def apply(self, model): # add validate.py to run full top-1 test (only for suitable networks) validate_py = pynq_driver_dir + "/validate.py" - validate_template = pk.resource_filename("finn.qnn-data", "templates/driver/validate.py") + validate_template = ( + os.environ["FINN_ROOT"] + "/src/finn/qnn-data/templates/driver/validate.py" + ) shutil.copy(validate_template, validate_py) # generate weight files for runtime-writable layers diff --git a/src/finn/util/pyverilator.py b/src/finn/util/pyverilator.py index 73c8755bfb..318ba7045e 100644 --- a/src/finn/util/pyverilator.py +++ b/src/finn/util/pyverilator.py @@ -26,8 +26,6 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import pkg_resources as pk - import numpy as np import os import shutil @@ -94,7 +92,7 @@ def file_to_basename(x): # use custom version of axis infrastructure vh # to enable Verilator to simulate AMD/Xilinx components (e.g DWC) - custom_vh = pk.resource_filename("finn.qnn-data", "verilog/custom_axis_infrastructure.vh") + custom_vh = os.environ["FINN_ROOT"] + "/src/finn/qnn-data/verilog/custom_axis_infrastructure.vh" shutil.copy(custom_vh, verilog_header_dir + "/axis_infrastructure_v1_1_0.vh") for fn in all_verilog_srcs: if fn.endswith(".vh"): @@ -131,7 +129,7 @@ def verilator_fifosim(model, n_inputs, max_iters=100000000): vivado_stitch_proj_dir = prepare_stitched_ip_for_verilator(model) verilog_header_dir = vivado_stitch_proj_dir + "/pyverilator_vh" build_dir = make_build_dir("verilator_fifosim_") - fifosim_cpp_fname = pk.resource_filename("finn.qnn-data", "cpp/verilator_fifosim.cpp") + fifosim_cpp_fname = os.environ["FINN_ROOT"] + "/src/finn/qnn-data/cpp/verilator_fifosim.cpp" with open(fifosim_cpp_fname, "r") as f: fifosim_cpp_template = f.read() assert len(model.graph.input) == 1, "Only a single input stream is supported" diff --git a/src/finn/util/test.py b/src/finn/util/test.py index 1f36486048..5ff884f62d 100644 --- a/src/finn/util/test.py +++ b/src/finn/util/test.py @@ -26,10 +26,9 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import pkg_resources as pk - import pytest +import importlib_resources as importlib import numpy as np import onnx import onnx.numpy_helper as nph @@ -137,8 +136,9 @@ def get_example_input(topology): onnx_tensor = onnx.load_tensor_from_string(raw_i) return nph.to_array(onnx_tensor) elif topology == "cnv": - fn = pk.resource_filename("finn.qnn-data", "cifar10/cifar10-test-data-class3.npz") - input_tensor = np.load(fn)["arr_0"].astype(np.float32) + ref = importlib.files("finn.qnn-data") / "cifar10/cifar10-test-data-class3.npz" + with importlib.as_file(ref) as fn: + input_tensor = np.load(fn)["arr_0"].astype(np.float32) return input_tensor else: raise Exception("Unknown topology, can't return example input") diff --git a/tests/brevitas/test_brevitas_cnv.py b/tests/brevitas/test_brevitas_cnv.py index c8adafdce9..3950a5b6a7 100644 --- a/tests/brevitas/test_brevitas_cnv.py +++ b/tests/brevitas/test_brevitas_cnv.py @@ -26,10 +26,9 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import pkg_resources as pk - import pytest +import importlib_resources as importlib import numpy as np import os import torch @@ -65,8 +64,9 @@ def test_brevitas_cnv_export_exec(wbits, abits): model = model.transform(RemoveStaticGraphInputs()) assert len(model.graph.input) == 1 assert len(model.graph.output) == 1 - fn = pk.resource_filename("finn.qnn-data", "cifar10/cifar10-test-data-class3.npz") - input_tensor = np.load(fn)["arr_0"].astype(np.float32) + ref = importlib.files("finn.qnn-data") / "cifar10/cifar10-test-data-class3.npz" + with importlib.as_file(ref) as fn: + input_tensor = np.load(fn)["arr_0"].astype(np.float32) input_tensor = input_tensor / 255 assert input_tensor.shape == (1, 3, 32, 32) # run using FINN-based execution diff --git a/tests/end2end/test_end2end_cybsec_mlp.py b/tests/end2end/test_end2end_cybsec_mlp.py index 7b73700909..12267aed47 100644 --- a/tests/end2end/test_end2end_cybsec_mlp.py +++ b/tests/end2end/test_end2end_cybsec_mlp.py @@ -26,8 +26,6 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import pkg_resources as pk - import pytest import json @@ -83,7 +81,7 @@ def forward(self, x): @pytest.mark.end2end def test_end2end_cybsec_mlp_export(): - assets_dir = pk.resource_filename("finn.qnn-data", "cybsec-mlp/") + assets_dir = os.environ["FINN_ROOT"] + "/src/finn/qnn-data/cybsec-mlp" # load up trained net in Brevitas input_size = 593 hidden1 = 64 diff --git a/tests/end2end/test_ext_weights.py b/tests/end2end/test_ext_weights.py index bef2e0ffa7..c91019ba99 100644 --- a/tests/end2end/test_ext_weights.py +++ b/tests/end2end/test_ext_weights.py @@ -26,8 +26,6 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import pkg_resources as pk - import pytest import os @@ -84,9 +82,8 @@ def test_end2end_ext_weights_build(): model_file = get_checkpoint_name("download") load_test_checkpoint_or_skip(model_file) build_env = get_build_env(build_kind, target_clk_ns) - folding_config_file = pk.resource_filename( - "finn.qnn-data", "test_ext_weights/tfc-w1a1-extw.json" - ) + test_data = os.environ["FINN_ROOT"] + "/src/finn/qnn-data/test_ext_weights" + folding_config_file = test_data + "/tfc-w1a1-extw.json" output_dir = make_build_dir("test_end2end_ext_weights_build") cfg = build.DataflowBuildConfig( output_dir=output_dir, diff --git a/tests/fpgadataflow/test_convert_to_hls_layers_cnv.py b/tests/fpgadataflow/test_convert_to_hls_layers_cnv.py index c4f3807aa0..c9cb4f0802 100644 --- a/tests/fpgadataflow/test_convert_to_hls_layers_cnv.py +++ b/tests/fpgadataflow/test_convert_to_hls_layers_cnv.py @@ -26,10 +26,9 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import pkg_resources as pk - import pytest +import importlib_resources as importlib import numpy as np import os import torch @@ -86,8 +85,9 @@ def test_convert_to_hls_layers_cnv_w1a1(fused_activation): model = model.transform(Streamline()) model = model.transform(InferDataLayouts()) # load one of the test vectors - fn = pk.resource_filename("finn.qnn-data", "cifar10/cifar10-test-data-class3.npz") - input_tensor = np.load(fn)["arr_0"].astype(np.float32) + ref = importlib.files("finn.qnn-data") / "cifar10/cifar10-test-data-class3.npz" + with importlib.as_file(ref) as fn: + input_tensor = np.load(fn)["arr_0"].astype(np.float32) input_tensor = input_tensor / 255 assert input_tensor.shape == (1, 3, 32, 32) # generate expected value from streamlined net diff --git a/tests/transformation/streamline/test_streamline_cnv.py b/tests/transformation/streamline/test_streamline_cnv.py index 86e4356ae4..8a91a49278 100644 --- a/tests/transformation/streamline/test_streamline_cnv.py +++ b/tests/transformation/streamline/test_streamline_cnv.py @@ -26,10 +26,9 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import pkg_resources as pk - import pytest +import importlib_resources as importlib import numpy as np import torch from brevitas.export import export_qonnx @@ -78,8 +77,9 @@ def test_streamline_cnv(size, wbits, abits): model = model.transform(GiveReadableTensorNames()) model = model.transform(RemoveStaticGraphInputs()) # load one of the test vectors - fn = pk.resource_filename("finn.qnn-data", "cifar10/cifar10-test-data-class3.npz") - input_tensor = np.load(fn)["arr_0"].astype(np.float32) + ref = importlib.files("finn.qnn-data") / "cifar10/cifar10-test-data-class3.npz" + with importlib.as_file(ref) as fn: + input_tensor = np.load(fn)["arr_0"].astype(np.float32) input_tensor = input_tensor / 255 assert input_tensor.shape == (1, 3, 32, 32) # run using FINN-based execution diff --git a/tests/transformation/test_batchnorm_to_affine_bnn_pynq.py b/tests/transformation/test_batchnorm_to_affine_bnn_pynq.py index b95c26d25f..fd5033674b 100644 --- a/tests/transformation/test_batchnorm_to_affine_bnn_pynq.py +++ b/tests/transformation/test_batchnorm_to_affine_bnn_pynq.py @@ -26,10 +26,9 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import pkg_resources as pk - import pytest +import importlib_resources as importlib import numpy as np import onnx import onnx.numpy_helper as nph @@ -59,8 +58,9 @@ def test_batchnorm_to_affine_cnv_w1a1(): model = model.transform(ConvertQONNXtoFINN()) model = model.transform(InferShapes()) model = model.transform(FoldConstants()) - fn = pk.resource_filename("finn.qnn-data", "cifar10/cifar10-test-data-class3.npz") - input_tensor = np.load(fn)["arr_0"].astype(np.float32) + ref = importlib.files("finn.qnn-data") / "cifar10/cifar10-test-data-class3.npz" + with importlib.as_file(ref) as fn: + input_tensor = np.load(fn)["arr_0"].astype(np.float32) input_tensor = input_tensor / 255 assert input_tensor.shape == (1, 3, 32, 32) input_dict = {"0": input_tensor} diff --git a/tests/transformation/test_qonnx_to_finn.py b/tests/transformation/test_qonnx_to_finn.py index 5bbcb1f9d4..939082b87b 100644 --- a/tests/transformation/test_qonnx_to_finn.py +++ b/tests/transformation/test_qonnx_to_finn.py @@ -27,10 +27,9 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import pkg_resources as pk - import pytest +import importlib_resources as importlib import numpy as np import onnx import onnx.numpy_helper as nph @@ -55,8 +54,9 @@ def get_brev_model_and_sample_inputs(model_name, wbits, abits): brev_model = get_test_model_trained(model_name, wbits, abits) elif model_name == "CNV": in_shape = (1, 3, 32, 32) - fn = pk.resource_filename("finn.qnn-data", "cifar10/cifar10-test-data-class3.npz") - input_tensor = np.load(fn)["arr_0"].astype(np.float32) + ref = importlib.files("finn.qnn-data") / "cifar10/cifar10-test-data-class3.npz" + with importlib.as_file(ref) as fn: + input_tensor = np.load(fn)["arr_0"].astype(np.float32) input_tensor = input_tensor / 255 brev_model = get_test_model_trained(model_name, wbits, abits) elif model_name == "mobilenet": diff --git a/tests/util/test_build_dataflow.py b/tests/util/test_build_dataflow.py index 02136b31a2..3649d6709e 100644 --- a/tests/util/test_build_dataflow.py +++ b/tests/util/test_build_dataflow.py @@ -26,8 +26,6 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import pkg_resources as pk - import pytest import numpy as np @@ -44,7 +42,7 @@ def test_end2end_build_dataflow_directory(): test_dir = make_build_dir("test_build_dataflow_directory_") target_dir = test_dir + "/build_dataflow" - example_data_dir = pk.resource_filename("finn.qnn-data", "build_dataflow/") + example_data_dir = os.environ["FINN_ROOT"] + "/src/finn/qnn-data/build_dataflow" copytree(example_data_dir, target_dir) build_dataflow_directory(target_dir) # check the generated files From aac2704561e21d857e2d9651c284bc324ab6dfbc Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 6 Oct 2023 15:44:39 +0100 Subject: [PATCH 284/665] [Setup] Removing pyscaffold from requirements --- setup.cfg | 2 -- setup.py | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/setup.cfg b/setup.cfg index fb070a436e..e69ce4f829 100644 --- a/setup.cfg +++ b/setup.cfg @@ -56,8 +56,6 @@ packages = find_namespace: include_package_data = True package_dir = =src -# DON'T CHANGE THE FOLLOWING LINE! IT WILL BE UPDATED BY PYSCAFFOLD! -setup_requires = pyscaffold>=3.2a0,<3.3a0 # The usage of test_requires is discouraged, see `Dependency Management` docs # tests_require = pytest; pytest-cov # Require a specific Python version, e.g. Python 2.7 or >= 3.4 diff --git a/setup.py b/setup.py index 7457bb9b38..9a06632af1 100644 --- a/setup.py +++ b/setup.py @@ -38,4 +38,4 @@ from setuptools import setup if __name__ == "__main__": - setup(use_pyscaffold=True) + setup() From d8a4048d731af9dbf424745d94122d96a2a675ed Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 6 Oct 2023 15:51:47 +0100 Subject: [PATCH 285/665] [Setup] Removing direct calls of setup.py --- docker/quicktest.sh | 8 ++++---- run-docker.sh | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/docker/quicktest.sh b/docker/quicktest.sh index 466fcfb09d..a990246b49 100755 --- a/docker/quicktest.sh +++ b/docker/quicktest.sh @@ -6,16 +6,16 @@ cd $FINN_ROOT # check if command line argument is empty or not present if [ -z $1 ]; then echo "Running quicktest: not (vivado or slow or board) with pytest-xdist" - python setup.py test --addopts "-m 'not (vivado or slow or vitis or board or notebooks)' --dist=loadfile -n $PYTEST_PARALLEL" + pytest -m 'not (vivado or slow or vitis or board or notebooks)' --dist=loadfile -n $PYTEST_PARALLEL elif [ $1 = "main" ]; then echo "Running main test suite: not (rtlsim or end2end) with pytest-xdist" - python setup.py test --addopts "-k 'not (rtlsim or end2end)' --dist=loadfile -n $PYTEST_PARALLEL" + pytest -k 'not (rtlsim or end2end)' --dist=loadfile -n $PYTEST_PARALLEL elif [ $1 = "rtlsim" ]; then echo "Running rtlsim test suite with pytest-parallel" - python setup.py test --addopts "-k rtlsim --workers $PYTEST_PARALLEL" + pytest -k rtlsim --workers $PYTEST_PARALLEL elif [ $1 = "end2end" ]; then echo "Running end2end test suite with no parallelism" - python setup.py test --addopts "-k end2end" + pytest -k end2end elif [ $1 = "full" ]; then echo "Running full test suite, each step with appropriate parallelism" $0 main; diff --git a/run-docker.sh b/run-docker.sh index c24dcec724..cb23595365 100755 --- a/run-docker.sh +++ b/run-docker.sh @@ -102,7 +102,7 @@ DOCKER_INTERACTIVE="" if [ "$1" = "test" ]; then gecho "Running test suite (all tests)" - DOCKER_CMD="python setup.py test" + DOCKER_CMD="pytest" elif [ "$1" = "quicktest" ]; then gecho "Running test suite (non-Vivado, non-slow tests)" DOCKER_CMD="quicktest.sh" From 13313c293eb00d2eb88edcaf68386fdf52152aeb Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 6 Oct 2023 17:21:45 +0100 Subject: [PATCH 286/665] [CI/docs] hotfix for Jenkins and docs to not use setup.py --- docker/jenkins/Jenkinsfile | 10 +++++----- docs/finn/developers.rst | 4 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index 2954877c2a..6be8845ab7 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -14,31 +14,31 @@ node { parallel firstBranch: { stage('Brevitas export') { dir("${env.WORKSPACE}") { - sh("bash run-docker.sh python setup.py test --addopts -mbrevitas_export") + sh("bash run-docker.sh pytest -mbrevitas_export") } } }, secondBranch: { stage('Streamlining transformations') { dir("${env.WORKSPACE}") { - sh("bash run-docker.sh python setup.py test --addopts -mstreamline") + sh("bash run-docker.sh pytest -mstreamline") } } }, thirdBranch: { stage('Util functions') { dir("${env.WORKSPACE}") { - sh("bash run-docker.sh python setup.py test --addopts -mutil") + sh("bash run-docker.sh pytest -mutil") } } }, fourthBranch: { stage('General transformations') { dir("${env.WORKSPACE}") { - sh("bash run-docker.sh python setup.py test --addopts -mtransform") + sh("bash run-docker.sh pytest -mtransform") } } }, fifthBranch: { stage('Fpgadataflow transformations and simulations') { dir("${env.WORKSPACE}") { - sh("bash run-docker.sh python setup.py test --addopts -mfpgadataflow") + sh("bash run-docker.sh pytest -mfpgadataflow") } } } diff --git a/docs/finn/developers.rst b/docs/finn/developers.rst index f9252f764c..1e1c48e2b5 100644 --- a/docs/finn/developers.rst +++ b/docs/finn/developers.rst @@ -159,8 +159,8 @@ from the FINN root directory as follows: If you want to run tests in parallel (e.g. to take advantage of a multi-core CPU) you can use: -* pytest-parallel for any rtlsim tests, e.g. `python setup.py test --addopts "-k rtlsim --workers auto"` -* pytest-xdist for anything else, make sure to add `--dist=loadfile` if you have tests in the same file that have dependencies on each other e.g. `python setup.py test --addopts "-k mytest -n auto --dist=loadfile"` +* pytest-parallel for any rtlsim tests, e.g. `pytest -k rtlsim --workers auto` +* pytest-xdist for anything else, make sure to add `--dist=loadfile` if you have tests in the same file that have dependencies on each other e.g. `pytest -k mytest -n auto --dist=loadfile` Finally, the full test suite with appropriate parallelization can be run inside the container by: From b2e04731c238056f49ff820f4ac26bfc99d4a609 Mon Sep 17 00:00:00 2001 From: johnnoel Date: Tue, 10 Oct 2023 16:20:22 +0100 Subject: [PATCH 287/665] [CI] exclude bnn_pynq from quicktest --- docker/quicktest.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docker/quicktest.sh b/docker/quicktest.sh index a990246b49..3684e3a0d4 100755 --- a/docker/quicktest.sh +++ b/docker/quicktest.sh @@ -6,7 +6,7 @@ cd $FINN_ROOT # check if command line argument is empty or not present if [ -z $1 ]; then echo "Running quicktest: not (vivado or slow or board) with pytest-xdist" - pytest -m 'not (vivado or slow or vitis or board or notebooks)' --dist=loadfile -n $PYTEST_PARALLEL + pytest -m 'not (vivado or slow or vitis or board or notebooks or bnn_pynq)' --dist=loadfile -n $PYTEST_PARALLEL elif [ $1 = "main" ]; then echo "Running main test suite: not (rtlsim or end2end) with pytest-xdist" pytest -k 'not (rtlsim or end2end)' --dist=loadfile -n $PYTEST_PARALLEL From 98e94f72e9c2b53dc63d30aa4d3bea466a178c19 Mon Sep 17 00:00:00 2001 From: johnnoel Date: Tue, 10 Oct 2023 17:49:26 +0100 Subject: [PATCH 288/665] [CI] fixing linting, lingering line left behind after resolving merge conflict --- tests/end2end/test_ext_weights.py | 1 - 1 file changed, 1 deletion(-) diff --git a/tests/end2end/test_ext_weights.py b/tests/end2end/test_ext_weights.py index 25fb5e91e9..2f5f136d3a 100644 --- a/tests/end2end/test_ext_weights.py +++ b/tests/end2end/test_ext_weights.py @@ -80,7 +80,6 @@ def test_end2end_ext_weights_download(): def test_end2end_ext_weights_build(): model_file = get_checkpoint_name("download") load_test_checkpoint_or_skip(model_file) - build_env = get_build_env(build_kind, target_clk_ns) test_data = os.environ["FINN_ROOT"] + "/src/finn/qnn-data/test_ext_weights" folding_config_file = test_data + "/tfc-w1a1-extw.json" output_dir = make_build_dir("test_end2end_ext_weights_build") From 5eb535a7c86a84d7195b8059765ea33f075c761b Mon Sep 17 00:00:00 2001 From: johnnoel Date: Wed, 11 Oct 2023 14:34:10 +0100 Subject: [PATCH 289/665] [NB] make all output paths absolute in advanced notebook --- .../4_advanced_builder_settings.ipynb | 20 +++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/notebooks/advanced/4_advanced_builder_settings.ipynb b/notebooks/advanced/4_advanced_builder_settings.ipynb index 4af48ac233..e748d85a1c 100644 --- a/notebooks/advanced/4_advanced_builder_settings.ipynb +++ b/notebooks/advanced/4_advanced_builder_settings.ipynb @@ -143,7 +143,7 @@ "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/advanced\"\n", "model_file = model_dir + \"/end2end_cnv_w2a2_export.onnx\"\n", "\n", - "estimates_output_dir = \"output_estimates_only\"\n", + "estimates_output_dir = build_dir + \"/output_estimates_only\"\n", "\n", "#Delete previous run results if exist\n", "if os.path.exists(estimates_output_dir):\n", @@ -427,7 +427,7 @@ "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/advanced\"\n", "model_file = model_dir + \"/end2end_cnv_w2a2_export.onnx\"\n", "\n", - "output_dir = \"output_pre_proc\"\n", + "output_dir = build_dir + \"/output_pre_proc\"\n", "\n", "#Delete previous run results if exist\n", "if os.path.exists(output_dir):\n", @@ -535,7 +535,7 @@ "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/advanced\"\n", "model_file = model_dir + \"/end2end_cnv_w2a2_export.onnx\"\n", "\n", - "output_dir = \"output_pre_and_post_proc\"\n", + "output_dir = build_dir + \"/output_pre_and_post_proc\"\n", "\n", "#Delete previous run results if exist\n", "if os.path.exists(output_dir):\n", @@ -782,7 +782,7 @@ "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/advanced\"\n", "model_file = model_dir + \"/end2end_cnv_w2a2_export.onnx\"\n", "\n", - "output_dir = \"output_all_lutram\"\n", + "output_dir = build_dir + \"/output_all_lutram\"\n", "\n", "#Delete previous run results if exist\n", "if os.path.exists(output_dir):\n", @@ -886,7 +886,7 @@ "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/advanced\"\n", "model_file = model_dir + \"/end2end_cnv_w2a2_export.onnx\"\n", "\n", - "output_dir = \"output_all_bram\"\n", + "output_dir = build_dir + \"/output_all_bram\"\n", "\n", "#Delete previous run results if exist\n", "if os.path.exists(output_dir):\n", @@ -1090,7 +1090,7 @@ "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/advanced\"\n", "model_file = model_dir + \"/end2end_cnv_w2a2_export.onnx\"\n", "\n", - "output_dir = \"output_with_verification\"\n", + "output_dir = build_dir + \"/output_with_verification\"\n", "\n", "#Delete previous run results if exist\n", "if os.path.exists(output_dir):\n", @@ -1191,7 +1191,7 @@ "metadata": {}, "outputs": [], "source": [ - "verify_initial_python = np.load(\"output_with_verification/verification_output/verify_initial_python_0_SUCCESS.npy\")\n", + "verify_initial_python = np.load(build_dir + \"/output_with_verification/verification_output/verify_initial_python_0_SUCCESS.npy\")\n", "print(\"The output of the verification step after the step_tidy_up is: \" + str(verify_initial_python))" ] }, @@ -1352,7 +1352,7 @@ "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/advanced\"\n", "model_file = model_dir + \"/end2end_cnv_w2a2_export.onnx\"\n", "\n", - "output_dir = \"output_standalone_thresholds\"\n", + "output_dir = build_dir + \"/output_standalone_thresholds\"\n", "\n", "#Delete previous run results if exist\n", "if os.path.exists(output_dir):\n", @@ -1449,7 +1449,7 @@ "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/advanced\"\n", "model_file = model_dir + \"/end2end_cnv_w2a2_export.onnx\"\n", "\n", - "output_dir = \"output_rtl_swg\"\n", + "output_dir = build_dir + \"/output_rtl_swg\"\n", "\n", "#Delete previous run results if exist\n", "if os.path.exists(output_dir):\n", @@ -1556,7 +1556,7 @@ "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/advanced\"\n", "model_file = model_dir + \"/end2end_cnv_w2a2_export.onnx\"\n", "\n", - "output_dir = \"output_bitfile\"\n", + "output_dir = build_dir + \"/output_bitfile\"\n", "\n", "#Delete previous run results if exist\n", "if os.path.exists(output_dir):\n", From 99e9b7366a5ab0238319c314ef81b1bb9f2d988a Mon Sep 17 00:00:00 2001 From: johnnoel Date: Thu, 12 Oct 2023 11:19:59 +0100 Subject: [PATCH 290/665] [CI] remove reference to unused hack script --- docker/jenkins/Jenkinsfile | 2 -- 1 file changed, 2 deletions(-) diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index 2d7ea5e918..47f855f433 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -797,14 +797,12 @@ void createTestScript(String board, String marker, String testResultsFilename) { sh """echo "#!/bin/bash . /opt/xilinx/xrt/setup.sh . ${CONDA_ENV_ACTIVATE} -python hack_driver_script.py python -m pytest -m ${marker} --junitxml=${testResultsFilename}.xml --html=${testResultsFilename}.html --self-contained-html" >> run-tests.sh """ else sh """echo "#!/bin/bash . /etc/profile.d/pynq_venv.sh . /etc/profile.d/xrt_setup.sh -python hack_driver_script.py python -m pytest -m ${marker} --junitxml=${testResultsFilename}.xml --html=${testResultsFilename}.html --self-contained-html" >> run-tests.sh """ From d454d6004948d02d96b0b6bc3badc488d287eeeb Mon Sep 17 00:00:00 2001 From: hlebleve Date: Fri, 13 Oct 2023 16:33:13 +0200 Subject: [PATCH 291/665] Rewriting the test script to account for the change in InferConvInpGen. Adding support for FMPadding_Pixel in SetFolding --- .../fpgadataflow/infer_pixel_padding_deconv.py | 12 ------------ src/finn/transformation/fpgadataflow/set_folding.py | 2 +- tests/fpgadataflow/test_fpgadataflow_deconv.py | 12 ++++++++++-- 3 files changed, 11 insertions(+), 15 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/infer_pixel_padding_deconv.py b/src/finn/transformation/fpgadataflow/infer_pixel_padding_deconv.py index 404795a80d..3b4b0e8a5a 100644 --- a/src/finn/transformation/fpgadataflow/infer_pixel_padding_deconv.py +++ b/src/finn/transformation/fpgadataflow/infer_pixel_padding_deconv.py @@ -5,11 +5,6 @@ from qonnx.transformation.lower_convs_to_matmul import _auto_pad_to_explicit_padding from qonnx.util.basic import get_by_name -# from finn.transformation.fpgadataflow.convert_to_hls_layers import ( -# InferConvInpGen, -# InferQuantizedMatrixVectorActivation, -# ) - class InferPixelPaddingDeconv(Transformation): def __init__(self, use_convinpgen_rtl_variant=False): @@ -27,11 +22,6 @@ def apply(self, model): deconv_output = n.output[0] idt = model.get_tensor_datatype(deconv_input) odt = model.get_tensor_datatype(deconv_output) - # if not idt.is_integer(): - # warnings.warn("%s : Input is not int. - # Can't infer PixelPaddingDeconv." % n.name) - # continue - # extract conv transpose parameters k_h = get_by_name(n.attribute, "kernel_shape").ints[0] k_w = get_by_name(n.attribute, "kernel_shape").ints[1] stride_h = get_by_name(n.attribute, "strides").ints[0] @@ -206,6 +196,4 @@ def apply(self, model): # remove old nodes graph.node.remove(n) - # model = model.transform(InferConvInpGen(use_rtl_variant=self.use_convinpgen_rtl_variant)) - # model = model.transform(InferQuantizedMatrixVectorActivation()) return (model, graph_modified) diff --git a/src/finn/transformation/fpgadataflow/set_folding.py b/src/finn/transformation/fpgadataflow/set_folding.py index eca1053f8f..dcedc51aba 100644 --- a/src/finn/transformation/fpgadataflow/set_folding.py +++ b/src/finn/transformation/fpgadataflow/set_folding.py @@ -112,7 +112,7 @@ def apply(self, model): simd_ops = [ "DownSampler", "FMPadding_Batch", - "ConvolutionInputGenerator", + "FMPadding_Pixel" "ConvolutionInputGenerator", "ConvolutionInputGenerator1D", "ConvolutionInputGenerator_rtl", ] diff --git a/tests/fpgadataflow/test_fpgadataflow_deconv.py b/tests/fpgadataflow/test_fpgadataflow_deconv.py index 6f99f90dc2..51d30e7f7b 100644 --- a/tests/fpgadataflow/test_fpgadataflow_deconv.py +++ b/tests/fpgadataflow/test_fpgadataflow_deconv.py @@ -39,6 +39,10 @@ import finn.core.onnx_exec as oxe from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim +from finn.transformation.fpgadataflow.convert_to_hls_layers import ( + InferConvInpGen, + InferQuantizedMatrixVectorActivation, +) from finn.transformation.fpgadataflow.create_dataflow_partition import ( CreateDataflowPartition, ) @@ -133,11 +137,13 @@ def set_up_reference_model(idt, wdt, k, idim, ifm_ch, ofm_ch, stride, padding): @pytest.mark.parametrize("k", [2, 4]) # padding @pytest.mark.parametrize("padding", [0, 1]) +@pytest.mark.parametrize("idt", [DataType["INT4"], DataType["INT8"]]) @pytest.mark.fpgadataflow @pytest.mark.slow @pytest.mark.vivado -def test_fpgadataflow_deconv(idim, stride, ifm_ch, ofm_ch, simd, pe, k, padding): - idt = wdt = DataType["INT4"] +def test_fpgadataflow_deconv(idim, stride, ifm_ch, ofm_ch, simd, pe, k, padding, idt): + # idt = wdt = DataType["INT4"] + wdt = idt idim_h, idim_w = idim stride_h, stride_w = stride @@ -157,6 +163,8 @@ def test_fpgadataflow_deconv(idim, stride, ifm_ch, ofm_ch, simd, pe, k, padding) input_dict_tr = {"global_in": input_tensor_tr} model = ref_model.transform(InferPixelPaddingDeconv(convinpgen_rtl)) + model = model.transform(InferConvInpGen(use_rtl_variant=convinpgen_rtl)) + model = model.transform(InferQuantizedMatrixVectorActivation()) model = model.transform(InferShapes()) model = model.transform(GiveUniqueNodeNames()) From 07e3b39efc2dd9e82c3ffb239d1de934f564b84d Mon Sep 17 00:00:00 2001 From: johnnoel Date: Mon, 16 Oct 2023 16:12:45 +0100 Subject: [PATCH 292/665] [Tests] fix end2end bnn_pynq cnv transpose --- tests/end2end/test_end2end_bnn_pynq.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index d98c06f7d0..b296dad827 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -330,7 +330,7 @@ def deploy_based_on_board(model, model_title, topology, wbits, abits, board): # The FC models contain a Reshape node, which FINN uses, so we therefore have to # reshape the input tensor data to match the reshaping in the model if topology == "cnv": - input_tensor_npy = input_tensor_npy.transpose(0, 3, 2, 1) + input_tensor_npy = input_tensor_npy.transpose(0, 2, 3, 1) else: input_shape = input_tensor_npy.shape new_input_shape = (input_shape[0], np.prod(input_shape[1:])) From 1bf20d50e156ea251f378caee128689346cab2b3 Mon Sep 17 00:00:00 2001 From: johnnoel Date: Wed, 18 Oct 2023 14:38:38 +0100 Subject: [PATCH 293/665] [Tests] Disabling end2end_bnn_pynq U250 tests failing due to routing on 2022.2 tools --- tests/end2end/test_end2end_bnn_pynq.py | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index b296dad827..8ac2493d1e 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -728,6 +728,19 @@ def test_build(self, topology, wbits, abits, board): build_data = get_build_env(board, target_clk_ns) if build_data["kind"] == "alveo" and ("VITIS_PATH" not in os.environ): pytest.skip("VITIS_PATH not set") + if board == "U250" and wbits == 1 and abits == 1: + if topology == "lfc" or topology == "tfc": + pytest.xfail( + "bnn_w" + + str(wbits) + + "_a" + + str(abits) + + "_" + + topology + + "_" + + board + + " test_build currently disabled, see CR-1171874" + ) prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, "fifodepth_" + board) model = load_test_checkpoint_or_skip(prev_chkpt_name) model = model.transform(build_data["build_fxn"]) From 5a5f0780cc6e0be72e2a106d8386b389f3b1b1cc Mon Sep 17 00:00:00 2001 From: hlebleve Date: Fri, 20 Oct 2023 14:30:23 +0200 Subject: [PATCH 294/665] Correcting typo and removing unecessary RTL option from InferPixelPaddingDeconv. --- .../transformation/fpgadataflow/infer_pixel_padding_deconv.py | 3 +-- src/finn/transformation/fpgadataflow/set_folding.py | 3 ++- tests/fpgadataflow/test_fpgadataflow_deconv.py | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/infer_pixel_padding_deconv.py b/src/finn/transformation/fpgadataflow/infer_pixel_padding_deconv.py index 3b4b0e8a5a..8642f5e0ef 100644 --- a/src/finn/transformation/fpgadataflow/infer_pixel_padding_deconv.py +++ b/src/finn/transformation/fpgadataflow/infer_pixel_padding_deconv.py @@ -7,9 +7,8 @@ class InferPixelPaddingDeconv(Transformation): - def __init__(self, use_convinpgen_rtl_variant=False): + def __init__(self): super().__init__() - self.use_convinpgen_rtl_variant = use_convinpgen_rtl_variant def apply(self, model): graph = model.graph diff --git a/src/finn/transformation/fpgadataflow/set_folding.py b/src/finn/transformation/fpgadataflow/set_folding.py index dcedc51aba..4045a28e16 100644 --- a/src/finn/transformation/fpgadataflow/set_folding.py +++ b/src/finn/transformation/fpgadataflow/set_folding.py @@ -112,7 +112,8 @@ def apply(self, model): simd_ops = [ "DownSampler", "FMPadding_Batch", - "FMPadding_Pixel" "ConvolutionInputGenerator", + "FMPadding_Pixel", + "ConvolutionInputGenerator", "ConvolutionInputGenerator1D", "ConvolutionInputGenerator_rtl", ] diff --git a/tests/fpgadataflow/test_fpgadataflow_deconv.py b/tests/fpgadataflow/test_fpgadataflow_deconv.py index 51d30e7f7b..227555701c 100644 --- a/tests/fpgadataflow/test_fpgadataflow_deconv.py +++ b/tests/fpgadataflow/test_fpgadataflow_deconv.py @@ -162,7 +162,7 @@ def test_fpgadataflow_deconv(idim, stride, ifm_ch, ofm_ch, simd, pe, k, padding, input_dict = {"inp": input_tensor} input_dict_tr = {"global_in": input_tensor_tr} - model = ref_model.transform(InferPixelPaddingDeconv(convinpgen_rtl)) + model = ref_model.transform(InferPixelPaddingDeconv()) model = model.transform(InferConvInpGen(use_rtl_variant=convinpgen_rtl)) model = model.transform(InferQuantizedMatrixVectorActivation()) model = model.transform(InferShapes()) From 4f51ed68a1dcd7dd44007c2cf0c6af05b21cd327 Mon Sep 17 00:00:00 2001 From: johnnoel Date: Mon, 23 Oct 2023 11:00:49 +0100 Subject: [PATCH 295/665] [CI] Use virtual env instead of Conda for Jenkins testing --- docker/jenkins/Jenkinsfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index 47f855f433..b19cbbccf1 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -796,7 +796,7 @@ void createTestScript(String board, String marker, String testResultsFilename) { if(board == "U250") sh """echo "#!/bin/bash . /opt/xilinx/xrt/setup.sh -. ${CONDA_ENV_ACTIVATE} +. ${VENV_ACTIVATE} python -m pytest -m ${marker} --junitxml=${testResultsFilename}.xml --html=${testResultsFilename}.html --self-contained-html" >> run-tests.sh """ else From 1093276f33651324eb8e2ed0779a1e1915b7158f Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 24 Oct 2023 18:12:52 +0100 Subject: [PATCH 296/665] [Jenkinsfile] Update Jenkinsfile_CI with pytest command --- docker/jenkins/Jenkinsfile_CI | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/docker/jenkins/Jenkinsfile_CI b/docker/jenkins/Jenkinsfile_CI index 2954877c2a..f04ea0a49d 100644 --- a/docker/jenkins/Jenkinsfile_CI +++ b/docker/jenkins/Jenkinsfile_CI @@ -14,31 +14,31 @@ node { parallel firstBranch: { stage('Brevitas export') { dir("${env.WORKSPACE}") { - sh("bash run-docker.sh python setup.py test --addopts -mbrevitas_export") + sh("bash run-docker.sh pytest --addopts -mbrevitas_export") } } }, secondBranch: { stage('Streamlining transformations') { dir("${env.WORKSPACE}") { - sh("bash run-docker.sh python setup.py test --addopts -mstreamline") + sh("bash run-docker.sh pytest --addopts -mstreamline") } } }, thirdBranch: { stage('Util functions') { dir("${env.WORKSPACE}") { - sh("bash run-docker.sh python setup.py test --addopts -mutil") + sh("bash run-docker.sh pytest --addopts -mutil") } } }, fourthBranch: { stage('General transformations') { dir("${env.WORKSPACE}") { - sh("bash run-docker.sh python setup.py test --addopts -mtransform") + sh("bash run-docker.sh pytest --addopts -mtransform") } } }, fifthBranch: { stage('Fpgadataflow transformations and simulations') { dir("${env.WORKSPACE}") { - sh("bash run-docker.sh python setup.py test --addopts -mfpgadataflow") + sh("bash run-docker.sh pytest --addopts -mfpgadataflow") } } } From 6e86f9c2a1acc465e803d9cd9ecc2ce80c184e70 Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 24 Oct 2023 18:15:58 +0100 Subject: [PATCH 297/665] [Jenkins] Delete obsolete option in pytest command --- docker/jenkins/Jenkinsfile_CI | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/docker/jenkins/Jenkinsfile_CI b/docker/jenkins/Jenkinsfile_CI index f04ea0a49d..6be8845ab7 100644 --- a/docker/jenkins/Jenkinsfile_CI +++ b/docker/jenkins/Jenkinsfile_CI @@ -14,31 +14,31 @@ node { parallel firstBranch: { stage('Brevitas export') { dir("${env.WORKSPACE}") { - sh("bash run-docker.sh pytest --addopts -mbrevitas_export") + sh("bash run-docker.sh pytest -mbrevitas_export") } } }, secondBranch: { stage('Streamlining transformations') { dir("${env.WORKSPACE}") { - sh("bash run-docker.sh pytest --addopts -mstreamline") + sh("bash run-docker.sh pytest -mstreamline") } } }, thirdBranch: { stage('Util functions') { dir("${env.WORKSPACE}") { - sh("bash run-docker.sh pytest --addopts -mutil") + sh("bash run-docker.sh pytest -mutil") } } }, fourthBranch: { stage('General transformations') { dir("${env.WORKSPACE}") { - sh("bash run-docker.sh pytest --addopts -mtransform") + sh("bash run-docker.sh pytest -mtransform") } } }, fifthBranch: { stage('Fpgadataflow transformations and simulations') { dir("${env.WORKSPACE}") { - sh("bash run-docker.sh pytest --addopts -mfpgadataflow") + sh("bash run-docker.sh pytest -mfpgadataflow") } } } From bd7f3b3b1a8fd29482caf3f027414ce8d1b2a619 Mon Sep 17 00:00:00 2001 From: johnnoel Date: Wed, 25 Oct 2023 16:03:18 +0100 Subject: [PATCH 298/665] [Jenkins] Add node label to Jenkinsfile_CI to target specific machine if available --- docker/jenkins/Jenkinsfile_CI | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docker/jenkins/Jenkinsfile_CI b/docker/jenkins/Jenkinsfile_CI index 6be8845ab7..5e7d5f1475 100644 --- a/docker/jenkins/Jenkinsfile_CI +++ b/docker/jenkins/Jenkinsfile_CI @@ -1,4 +1,4 @@ -node { +node('finn-build || built-in') { def app stage('Clone repository') { /* Let's make sure we have the repository cloned to our workspace */ From 057e810d0f780ee2ec26c9702eef5bd858a8b23e Mon Sep 17 00:00:00 2001 From: Linus Jungemann Date: Tue, 31 Oct 2023 13:18:07 +0100 Subject: [PATCH 299/665] Add support for the Alveo U55C card and allow to choose the device to be used in the driver --- .../qnn-data/templates/driver/driver_base.py | 32 +++++---- .../fpgadataflow/template_driver.py | 6 +- .../fpgadataflow/vitis_build.py | 65 ++++++++++++------- src/finn/util/basic.py | 5 +- src/finn/util/platforms.py | 62 +++++++++++++++--- 5 files changed, 126 insertions(+), 44 deletions(-) diff --git a/src/finn/qnn-data/templates/driver/driver_base.py b/src/finn/qnn-data/templates/driver/driver_base.py index f701122885..e0d0552a9e 100644 --- a/src/finn/qnn-data/templates/driver/driver_base.py +++ b/src/finn/qnn-data/templates/driver/driver_base.py @@ -78,6 +78,7 @@ def __init__( Path to runtime weights folder. """ super().__init__(bitfile_name, download=download, device=device) + self.device = device self.runtime_weight_dir = runtime_weight_dir self._io_shape_dict = io_shape_dict self.ibuf_packed_device = None @@ -129,7 +130,8 @@ def load_external_weights(self): for w_filename in w_filenames: if w_filename.endswith(".npy"): - weight_tensor = np.load(self.runtime_weight_dir + "/" + w_filename) + weight_tensor = np.load( + self.runtime_weight_dir + "/" + w_filename) else: continue @@ -182,14 +184,16 @@ def load_runtime_weights(self, flush_accel=True, verify=True): dat = f.read() else: continue - layer_w = np.fromiter([int(x, 16) for x in dat.strip().split()], dtype=np.uint32) + layer_w = np.fromiter([int(x, 16) + for x in dat.strip().split()], dtype=np.uint32) sdp_ind = int(w_filename.split("_")[0]) layer_ind = int(w_filename.split("_")[1]) rt_weight_dict[(sdp_ind, layer_ind)] = layer_w for sdp_ind, layer_ind in rt_weight_dict.keys(): cand_if_name = "StreamingDataflowPartition_%d" % sdp_ind if cand_if_name in self.ip_dict.keys(): - layer_mmio = getattr(self, "StreamingDataflowPartition_%d" % sdp_ind).mmio + layer_mmio = getattr( + self, "StreamingDataflowPartition_%d" % sdp_ind).mmio layer_w = rt_weight_dict[(sdp_ind, layer_ind)] layer_mmio.write_mm(0, layer_w.tobytes()) if verify: @@ -262,12 +266,12 @@ def batch_size(self, value): self.obuf_packed = [] for i in range(self.num_inputs): new_packed_ibuf = allocate( - shape=self.ishape_packed(i), dtype=np.uint8, cacheable=cacheable + shape=self.ishape_packed(i), dtype=np.uint8, cacheable=cacheable, target=self.device ) self.ibuf_packed_device.append(new_packed_ibuf) for o in range(self.num_outputs): new_packed_obuf = allocate( - shape=self.oshape_packed(o), dtype=np.uint8, cacheable=cacheable + shape=self.oshape_packed(o), dtype=np.uint8, cacheable=cacheable, target=self.device ) self.obuf_packed_device.append(new_packed_obuf) self.obuf_packed.append(np.empty_like(new_packed_obuf)) @@ -338,18 +342,21 @@ def execute_on_buffers(self, asynch=False, batch_size=None): assert batch_size <= self.batch_size, "Specified batch_size is too large." if self.platform == "zynq-iodma": for o in range(self.num_outputs): - assert self.odma[o].read(0x00) & 0x4 != 0, "Output DMA %d is not idle" % (o) + assert self.odma[o].read( + 0x00) & 0x4 != 0, "Output DMA %d is not idle" % (o) # manually launch IODMAs since signatures are missing for iwdma, iwbuf, iwdma_name in self.external_weights: iwdma.write(0x10, iwbuf.device_address) iwdma.write(0x1C, batch_size) iwdma.write(0x00, 1) for o in range(self.num_outputs): - self.odma[o].write(0x10, self.obuf_packed_device[o].device_address) + self.odma[o].write( + 0x10, self.obuf_packed_device[o].device_address) self.odma[o].write(0x1C, batch_size) self.odma[o].write(0x00, 1) for i in range(self.num_inputs): - self.idma[i].write(0x10, self.ibuf_packed_device[i].device_address) + self.idma[i].write( + 0x10, self.ibuf_packed_device[i].device_address) self.idma[i].write(0x1C, batch_size) self.idma[i].write(0x00, 1) elif self.platform == "alveo": @@ -360,7 +367,8 @@ def execute_on_buffers(self, asynch=False, batch_size=None): for iwdma, iwbuf, iwdma_name in self.external_weights: iwdma.start(iwbuf, batch_size) for o in range(self.num_outputs): - self.odma_handle[o] = self.odma[o].start(self.obuf_packed_device[o], batch_size) + self.odma_handle[o] = self.odma[o].start( + self.obuf_packed_device[o], batch_size) else: raise Exception("Unrecognized platform: %s" % self.platform) # blocking behavior depends on asynch parameter @@ -376,7 +384,8 @@ def wait_until_finished(self): while status & 0x2 == 0: status = self.odma[o].read(0x00) elif self.platform == "alveo": - assert all([x is not None for x in self.odma_handle]), "No odma_handle to wait on" + assert all([x is not None for x in self.odma_handle] + ), "No odma_handle to wait on" for o in range(self.num_outputs): self.odma_handle[o].wait() self.odma_handle[o] = None @@ -390,7 +399,8 @@ def execute(self, input_npy): # if single input, convert to list to normalize how we process the input if not type(input_npy) is list: input_npy = [input_npy] - assert self.num_inputs == len(input_npy), "Not all accelerator inputs are specified." + assert self.num_inputs == len( + input_npy), "Not all accelerator inputs are specified." for i in range(self.num_inputs): ibuf_folded = self.fold_input(input_npy[i], ind=i) ibuf_packed = self.pack_input(ibuf_folded, ind=i) diff --git a/src/finn/transformation/fpgadataflow/template_driver.py b/src/finn/transformation/fpgadataflow/template_driver.py index 158825191e..a65e060ed9 100644 --- a/src/finn/transformation/fpgadataflow/template_driver.py +++ b/src/finn/transformation/fpgadataflow/template_driver.py @@ -62,6 +62,7 @@ import os from qonnx.core.datatype import DataType from driver_base import FINNExampleOverlay +from pynq.pl_server.device import Device # dictionary describing the I/O of the FINN-generated accelerator io_shape_dict = { @@ -90,6 +91,7 @@ parser.add_argument('--exec_mode', help='Please select functional verification ("execute") or throughput test ("throughput_test")', default="execute") parser.add_argument('--platform', help='Target platform: zynq-iodma alveo', default="$PLATFORM$") parser.add_argument('--batchsize', help='number of samples for inference', type=int, default=1) + parser.add_argument('--device', help='FPGA device to be used', type=int, default=0) parser.add_argument('--bitfile', help='name of bitfile (i.e. "resizer.bit")', default="resizer.bit") parser.add_argument('--inputfile', help='name(s) of input npy file(s) (i.e. "input.npy")', nargs="*", type=str, default=["input.npy"]) parser.add_argument('--outputfile', help='name(s) of output npy file(s) (i.e. "output.npy")', nargs="*", type=str, default=["output.npy"]) @@ -103,12 +105,14 @@ inputfile = args.inputfile outputfile = args.outputfile runtime_weight_dir = args.runtime_weight_dir + devID = args.device + device = Device.devices[devID] # instantiate FINN accelerator driver and pass batchsize and bitfile accel = FINNExampleOverlay( bitfile_name = bitfile, platform = platform, io_shape_dict = io_shape_dict, batch_size = batch_size, - runtime_weight_dir = runtime_weight_dir + runtime_weight_dir = runtime_weight_dir, device=device ) # for the remote execution the data from the input npy file has to be loaded, diff --git a/src/finn/transformation/fpgadataflow/vitis_build.py b/src/finn/transformation/fpgadataflow/vitis_build.py index 2fc0b2f3bb..8224db934f 100644 --- a/src/finn/transformation/fpgadataflow/vitis_build.py +++ b/src/finn/transformation/fpgadataflow/vitis_build.py @@ -89,13 +89,15 @@ def apply(self, model): _check_vitis_envvars() vivado_proj_dir = model.get_metadata_prop("vivado_stitch_proj") stitched_ip_dir = vivado_proj_dir + "/ip" - interfaces = json.loads(model.get_metadata_prop("vivado_stitch_ifnames")) + interfaces = json.loads( + model.get_metadata_prop("vivado_stitch_ifnames")) args_string = [] arg_id = 0 # NOTE: this assumes the graph is Vitis-compatible: max one axi lite interface # developed from instructions in UG1393 (v2019.2) and package_xo documentation # package_xo is responsible for generating the kernel xml - assert len(interfaces["axilite"]) <= 1, "CreateVitisXO supports max 1 AXI lite interface" + assert len( + interfaces["axilite"]) <= 1, "CreateVitisXO supports max 1 AXI lite interface" axilite_intf_name = None if len(interfaces["axilite"]) == 1: axilite_intf_name = interfaces["axilite"][0] @@ -110,12 +112,14 @@ def apply(self, model): ) arg_id += 1 args_string.append( - "{numReps:0:%s:%s:0x4:0x1C:uint:0}" % (str(arg_id), axilite_intf_name) + "{numReps:0:%s:%s:0x4:0x1C:uint:0}" % ( + str(arg_id), axilite_intf_name) ) arg_id += 1 else: args_string.append( - "{numReps:0:%s:%s:0x4:0x10:uint:0}" % (str(arg_id), axilite_intf_name) + "{numReps:0:%s:%s:0x4:0x10:uint:0}" % ( + str(arg_id), axilite_intf_name) ) arg_id += 1 for intf in interfaces["s_axis"] + interfaces["m_axis"]: @@ -152,7 +156,8 @@ def apply(self, model): f.write("vivado -mode batch -source gen_xo.tcl\n") f.write("cd {}\n".format(working_dir)) bash_command = ["bash", package_xo_sh] - process_compile = subprocess.Popen(bash_command, stdout=subprocess.PIPE) + process_compile = subprocess.Popen( + bash_command, stdout=subprocess.PIPE) process_compile.communicate() assert os.path.isfile(xo_path), ( "Vitis .xo file not created, check logs under %s" % vivado_proj_dir @@ -212,26 +217,30 @@ def apply(self, model): # check top-level in/out list instead if producer is None: instance_names[node.name] = "idma" + str(idma_idx) - config.append("nk=%s:1:%s" % (node.name, instance_names[node.name])) + config.append("nk=%s:1:%s" % + (node.name, instance_names[node.name])) idma_idx += 1 elif consumer == []: instance_names[node.name] = "odma" + str(odma_idx) - config.append("nk=%s:1:%s" % (node.name, instance_names[node.name])) + config.append("nk=%s:1:%s" % + (node.name, instance_names[node.name])) odma_idx += 1 else: instance_names[node.name] = node.name - config.append("nk=%s:1:%s" % (node.name, instance_names[node.name])) + config.append("nk=%s:1:%s" % + (node.name, instance_names[node.name])) sdp_node.set_nodeattr("instance_name", instance_names[node.name]) # explicitly assign SLRs if the slr attribute is not -1 node_slr = sdp_node.get_nodeattr("slr") if node_slr != -1: - config.append("slr=%s:SLR%d" % (instance_names[node.name], node_slr)) + config.append("slr=%s:SLR%d" % + (instance_names[node.name], node_slr)) # assign memory banks if producer is None or consumer is None: node_mem_port = sdp_node.get_nodeattr("mem_port") if node_mem_port == "": # configure good defaults based on board - if "u50" in self.platform or "u280" in self.platform: + if "u50" in self.platform or "u280" in self.platform or "u55c" in self.platform: # Use HBM where available (also U50 does not have DDR) mem_type = "HBM" mem_idx = 0 @@ -250,7 +259,8 @@ def apply(self, model): mem_type = "DDR" mem_idx = 1 node_mem_port = "%s[%d]" % (mem_type, mem_idx) - config.append("sp=%s.m_axi_gmem0:%s" % (instance_names[node.name], node_mem_port)) + config.append("sp=%s.m_axi_gmem0:%s" % + (instance_names[node.name], node_mem_port)) # connect streams if producer is not None: for i in range(len(node.input)): @@ -274,11 +284,16 @@ def apply(self, model): # add Vivado physopt directives if desired if self.strategy == VitisOptStrategy.PERFORMANCE_BEST: config.append("[vivado]") - config.append("prop=run.impl_1.STEPS.OPT_DESIGN.ARGS.DIRECTIVE=ExploreWithRemap") - config.append("prop=run.impl_1.STEPS.PLACE_DESIGN.ARGS.DIRECTIVE=Explore") - config.append("prop=run.impl_1.STEPS.PHYS_OPT_DESIGN.IS_ENABLED=true") - config.append("prop=run.impl_1.STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE=Explore") - config.append("prop=run.impl_1.STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE=Explore") + config.append( + "prop=run.impl_1.STEPS.OPT_DESIGN.ARGS.DIRECTIVE=ExploreWithRemap") + config.append( + "prop=run.impl_1.STEPS.PLACE_DESIGN.ARGS.DIRECTIVE=Explore") + config.append( + "prop=run.impl_1.STEPS.PHYS_OPT_DESIGN.IS_ENABLED=true") + config.append( + "prop=run.impl_1.STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE=Explore") + config.append( + "prop=run.impl_1.STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE=Explore") config = "\n".join(config) + "\n" with open(link_dir + "/config.txt", "w") as f: @@ -315,7 +330,8 @@ def apply(self, model): ) f.write("cd {}\n".format(working_dir)) bash_command = ["bash", script] - process_compile = subprocess.Popen(bash_command, stdout=subprocess.PIPE) + process_compile = subprocess.Popen( + bash_command, stdout=subprocess.PIPE) process_compile.communicate() # TODO rename xclbin appropriately here? xclbin = link_dir + "/a.xclbin" @@ -330,7 +346,8 @@ def apply(self, model): with open(gen_rep_xml_sh, "w") as f: f.write("#!/bin/bash \n") f.write("cd {}\n".format(link_dir)) - f.write("vivado -mode batch -source %s\n" % (link_dir + "/gen_report_xml.tcl")) + f.write("vivado -mode batch -source %s\n" % + (link_dir + "/gen_report_xml.tcl")) f.write("cd {}\n".format(working_dir)) bash_command = ["bash", gen_rep_xml_sh] process_genxml = subprocess.Popen(bash_command, stdout=subprocess.PIPE) @@ -390,7 +407,8 @@ def apply(self, model): model = model.transform(Floorplan(floorplan=self.floorplan_file)) model = model.transform( - CreateDataflowPartition(partition_model_dir=self.partition_model_dir) + CreateDataflowPartition( + partition_model_dir=self.partition_model_dir) ) model = model.transform(GiveUniqueNodeNames()) model = model.transform(GiveReadableTensorNames()) @@ -406,12 +424,15 @@ def apply(self, model): kernel_model = kernel_model.transform(RemoveUnusedTensors()) kernel_model = kernel_model.transform(GiveUniqueNodeNames(prefix)) kernel_model.save(dataflow_model_filename) - kernel_model = kernel_model.transform(PrepareIP(self.fpga_part, self.period_ns)) + kernel_model = kernel_model.transform( + PrepareIP(self.fpga_part, self.period_ns)) kernel_model = kernel_model.transform(HLSSynthIP()) kernel_model = kernel_model.transform( - CreateStitchedIP(self.fpga_part, self.period_ns, sdp_node.onnx_node.name, True) + CreateStitchedIP(self.fpga_part, self.period_ns, + sdp_node.onnx_node.name, True) ) - kernel_model = kernel_model.transform(CreateVitisXO(sdp_node.onnx_node.name)) + kernel_model = kernel_model.transform( + CreateVitisXO(sdp_node.onnx_node.name)) kernel_model.set_metadata_prop("platform", "alveo") kernel_model.save(dataflow_model_filename) # Assemble design from kernels diff --git a/src/finn/util/basic.py b/src/finn/util/basic.py index a184a53862..f4a116810e 100644 --- a/src/finn/util/basic.py +++ b/src/finn/util/basic.py @@ -63,12 +63,14 @@ alveo_part_map["U200"] = "xcu200-fsgd2104-2-e" alveo_part_map["U250"] = "xcu250-figd2104-2L-e" alveo_part_map["U280"] = "xcu280-fsvh2892-2L-e" +alveo_part_map["U55C"] = "xcu55c-fsvh2892-2L-e" alveo_default_platform = dict() alveo_default_platform["U50"] = "xilinx_u50_gen3x16_xdma_5_202210_1" alveo_default_platform["U200"] = "xilinx_u200_gen3x16_xdma_2_202110_1" alveo_default_platform["U250"] = "xilinx_u250_gen3x16_xdma_4_1_202210_1" alveo_default_platform["U280"] = "xilinx_u280_gen3x16_xdma_1_202211_1" +alveo_default_platform["U55C"] = "xilinx_u55c_gen3x16_xdma_3_202210_1" def get_rtlsim_trace_depth(): @@ -180,7 +182,8 @@ def build(self, code_gen_dir): f.write("#!/bin/bash \n") f.write(bash_compile + "\n") bash_command = ["bash", self.compile_script] - process_compile = subprocess.Popen(bash_command, stdout=subprocess.PIPE) + process_compile = subprocess.Popen( + bash_command, stdout=subprocess.PIPE) process_compile.communicate() diff --git a/src/finn/util/platforms.py b/src/finn/util/platforms.py index 77dc591445..56173f5935 100644 --- a/src/finn/util/platforms.py +++ b/src/finn/util/platforms.py @@ -104,7 +104,8 @@ def compute_resources(self): def guide_resources(self): guide = [] # TODO: assert limits is of correct size - guide_res = (np.tile(np.array(self.compute_resources), (self.ndevices, 1))).astype(int) + guide_res = (np.tile(np.array(self.compute_resources), + (self.ndevices, 1))).astype(int) for i in range(self.nslr * self.ndevices): # when in multi-FPGA mode, subtract cost of UDP connection from eth_slr local_slr = i % self.nslr @@ -146,7 +147,8 @@ def resource_count_dict(self): @property def compute_connection_cost(self): - x = np.full((self.nslr * self.ndevices, self.nslr * self.ndevices), DONT_CARE) + x = np.full((self.nslr * self.ndevices, + self.nslr * self.ndevices), DONT_CARE) # build connection cost matrix for one device's SLRs xlocal = np.full((self.nslr, self.nslr), DONT_CARE) for i in range(self.nslr): @@ -157,16 +159,20 @@ def compute_connection_cost(self): xlocal[i][j] = 1 # tile connection cost matrices for entire system for i in range(self.ndevices): - x[i * self.nslr : (i + 1) * self.nslr, i * self.nslr : (i + 1) * self.nslr] = xlocal + x[i * self.nslr: (i + 1) * self.nslr, i * + self.nslr: (i + 1) * self.nslr] = xlocal # set cost for ethernet connections, assuming daisy-chaining for i in range(self.ndevices - 1): - x[i * self.nslr + self.eth_slr][(i + 1) * self.nslr + self.eth_slr] = 10 - x[(i + 1) * self.nslr + self.eth_slr][i * self.nslr + self.eth_slr] = 10 + x[i * self.nslr + + self.eth_slr][(i + 1) * self.nslr + self.eth_slr] = 10 + x[(i + 1) * self.nslr + self.eth_slr][i * + self.nslr + self.eth_slr] = 10 return x @property def compute_connection_resource(self): - sll = np.full((self.nslr * self.ndevices, self.nslr * self.ndevices), 0) + sll = np.full((self.nslr * self.ndevices, + self.nslr * self.ndevices), 0) # build connection resource matrix for one device's SLRs slllocal = np.full((self.nslr, self.nslr), -1) for i in range(self.nslr): @@ -178,9 +184,11 @@ def compute_connection_resource(self): slllocal[i][j] = self.sll_count[i][j] # tile connection cost matrices for entire system for i in range(self.ndevices): - sll[i * self.nslr : (i + 1) * self.nslr, i * self.nslr : (i + 1) * self.nslr] = slllocal + sll[i * self.nslr: (i + 1) * self.nslr, i * + self.nslr: (i + 1) * self.nslr] = slllocal # set cost for ethernet connections, assuming daisy-chaining - eth = np.full((self.nslr * self.ndevices, self.nslr * self.ndevices), 0) + eth = np.full((self.nslr * self.ndevices, + self.nslr * self.ndevices), 0) # no Eth throughput constraints from one SLR to itself for i in range(self.ndevices * self.nslr): eth[i][i] = -1 @@ -202,7 +210,8 @@ def compute_connection_resource(self): # constrain for SLLs between SLRs on same device is_offchip = i // self.nslr != j // self.nslr constraints_line.append( - (-1 if is_offchip else sll[i][j], eth[i][j] if is_offchip else -1) + (-1 if is_offchip else sll[i][j], + eth[i][j] if is_offchip else -1) ) constraints.append(constraints_line) return constraints @@ -461,11 +470,46 @@ def compute_resources(self): ] +class Alveo_NxU55C_Platform(Platform): + def __init__( + self, + ndevices=1, + limits=DEFAULT_RES_LIMITS, + avg_constraints=DEFAULT_AVG_CONSTRAINTS, + ): + sll_counts = [[0, 5000, 0], [5000, 0, 5000], [0, 5000, 0]] + super(Alveo_NxU50_Platform, self).__init__( + nslr=2, + ndevices=ndevices, + sll_count=sll_counts, + ddr_slr=[], + hbm_slr=0, + eth_slr=2, + eth_gbps=100, + limits=limits, + avg_constraints=avg_constraints, + ) + + @property + def compute_resources(self): + # according to UG1120 + # return [[369000, 746000, 2*507, 320, 2733], + # [333000, 675000, 2*468, 320, 2877], + # [367000, 729000, 2*512, 320, 2880]] + # observed from Vivado: + return [ + [400800, 2 * 400800, 2 * 600, 320, 2736], + [382080, 2 * 382080, 2 * 576, 320, 2880], + [380640, 2 * 380640, 2 * 576, 320, 2880], + ] + + platforms = dict() platforms["U50"] = Alveo_NxU50_Platform platforms["U200"] = Alveo_NxU200_Platform platforms["U250"] = Alveo_NxU250_Platform platforms["U280"] = Alveo_NxU280_Platform +platforms["U55C"] = Alveo_NxU55C_Platform platforms["Pynq-Z1"] = Zynq7020_Platform platforms["Pynq-Z2"] = Zynq7020_Platform platforms["Ultra96"] = ZU3EG_Platform From 5c87f661c98420471bfdd8e72766147d90d35c04 Mon Sep 17 00:00:00 2001 From: Linus Jungemann Date: Tue, 7 Nov 2023 13:21:30 +0100 Subject: [PATCH 300/665] Change formatting and fix wrong super call --- .../qnn-data/templates/driver/driver_base.py | 27 +++----- .../fpgadataflow/vitis_build.py | 63 +++++++------------ src/finn/util/basic.py | 3 +- src/finn/util/platforms.py | 29 +++------ 4 files changed, 41 insertions(+), 81 deletions(-) diff --git a/src/finn/qnn-data/templates/driver/driver_base.py b/src/finn/qnn-data/templates/driver/driver_base.py index e0d0552a9e..1eafaef657 100644 --- a/src/finn/qnn-data/templates/driver/driver_base.py +++ b/src/finn/qnn-data/templates/driver/driver_base.py @@ -130,8 +130,7 @@ def load_external_weights(self): for w_filename in w_filenames: if w_filename.endswith(".npy"): - weight_tensor = np.load( - self.runtime_weight_dir + "/" + w_filename) + weight_tensor = np.load(self.runtime_weight_dir + "/" + w_filename) else: continue @@ -184,16 +183,14 @@ def load_runtime_weights(self, flush_accel=True, verify=True): dat = f.read() else: continue - layer_w = np.fromiter([int(x, 16) - for x in dat.strip().split()], dtype=np.uint32) + layer_w = np.fromiter([int(x, 16) for x in dat.strip().split()], dtype=np.uint32) sdp_ind = int(w_filename.split("_")[0]) layer_ind = int(w_filename.split("_")[1]) rt_weight_dict[(sdp_ind, layer_ind)] = layer_w for sdp_ind, layer_ind in rt_weight_dict.keys(): cand_if_name = "StreamingDataflowPartition_%d" % sdp_ind if cand_if_name in self.ip_dict.keys(): - layer_mmio = getattr( - self, "StreamingDataflowPartition_%d" % sdp_ind).mmio + layer_mmio = getattr(self, "StreamingDataflowPartition_%d" % sdp_ind).mmio layer_w = rt_weight_dict[(sdp_ind, layer_ind)] layer_mmio.write_mm(0, layer_w.tobytes()) if verify: @@ -342,21 +339,18 @@ def execute_on_buffers(self, asynch=False, batch_size=None): assert batch_size <= self.batch_size, "Specified batch_size is too large." if self.platform == "zynq-iodma": for o in range(self.num_outputs): - assert self.odma[o].read( - 0x00) & 0x4 != 0, "Output DMA %d is not idle" % (o) + assert self.odma[o].read(0x00) & 0x4 != 0, "Output DMA %d is not idle" % (o) # manually launch IODMAs since signatures are missing for iwdma, iwbuf, iwdma_name in self.external_weights: iwdma.write(0x10, iwbuf.device_address) iwdma.write(0x1C, batch_size) iwdma.write(0x00, 1) for o in range(self.num_outputs): - self.odma[o].write( - 0x10, self.obuf_packed_device[o].device_address) + self.odma[o].write(0x10, self.obuf_packed_device[o].device_address) self.odma[o].write(0x1C, batch_size) self.odma[o].write(0x00, 1) for i in range(self.num_inputs): - self.idma[i].write( - 0x10, self.ibuf_packed_device[i].device_address) + self.idma[i].write(0x10, self.ibuf_packed_device[i].device_address) self.idma[i].write(0x1C, batch_size) self.idma[i].write(0x00, 1) elif self.platform == "alveo": @@ -367,8 +361,7 @@ def execute_on_buffers(self, asynch=False, batch_size=None): for iwdma, iwbuf, iwdma_name in self.external_weights: iwdma.start(iwbuf, batch_size) for o in range(self.num_outputs): - self.odma_handle[o] = self.odma[o].start( - self.obuf_packed_device[o], batch_size) + self.odma_handle[o] = self.odma[o].start(self.obuf_packed_device[o], batch_size) else: raise Exception("Unrecognized platform: %s" % self.platform) # blocking behavior depends on asynch parameter @@ -384,8 +377,7 @@ def wait_until_finished(self): while status & 0x2 == 0: status = self.odma[o].read(0x00) elif self.platform == "alveo": - assert all([x is not None for x in self.odma_handle] - ), "No odma_handle to wait on" + assert all([x is not None for x in self.odma_handle]), "No odma_handle to wait on" for o in range(self.num_outputs): self.odma_handle[o].wait() self.odma_handle[o] = None @@ -399,8 +391,7 @@ def execute(self, input_npy): # if single input, convert to list to normalize how we process the input if not type(input_npy) is list: input_npy = [input_npy] - assert self.num_inputs == len( - input_npy), "Not all accelerator inputs are specified." + assert self.num_inputs == len(input_npy), "Not all accelerator inputs are specified." for i in range(self.num_inputs): ibuf_folded = self.fold_input(input_npy[i], ind=i) ibuf_packed = self.pack_input(ibuf_folded, ind=i) diff --git a/src/finn/transformation/fpgadataflow/vitis_build.py b/src/finn/transformation/fpgadataflow/vitis_build.py index 8224db934f..a102660001 100644 --- a/src/finn/transformation/fpgadataflow/vitis_build.py +++ b/src/finn/transformation/fpgadataflow/vitis_build.py @@ -89,15 +89,13 @@ def apply(self, model): _check_vitis_envvars() vivado_proj_dir = model.get_metadata_prop("vivado_stitch_proj") stitched_ip_dir = vivado_proj_dir + "/ip" - interfaces = json.loads( - model.get_metadata_prop("vivado_stitch_ifnames")) + interfaces = json.loads(model.get_metadata_prop("vivado_stitch_ifnames")) args_string = [] arg_id = 0 # NOTE: this assumes the graph is Vitis-compatible: max one axi lite interface # developed from instructions in UG1393 (v2019.2) and package_xo documentation # package_xo is responsible for generating the kernel xml - assert len( - interfaces["axilite"]) <= 1, "CreateVitisXO supports max 1 AXI lite interface" + assert len(interfaces["axilite"]) <= 1, "CreateVitisXO supports max 1 AXI lite interface" axilite_intf_name = None if len(interfaces["axilite"]) == 1: axilite_intf_name = interfaces["axilite"][0] @@ -112,14 +110,12 @@ def apply(self, model): ) arg_id += 1 args_string.append( - "{numReps:0:%s:%s:0x4:0x1C:uint:0}" % ( - str(arg_id), axilite_intf_name) + "{numReps:0:%s:%s:0x4:0x1C:uint:0}" % (str(arg_id), axilite_intf_name) ) arg_id += 1 else: args_string.append( - "{numReps:0:%s:%s:0x4:0x10:uint:0}" % ( - str(arg_id), axilite_intf_name) + "{numReps:0:%s:%s:0x4:0x10:uint:0}" % (str(arg_id), axilite_intf_name) ) arg_id += 1 for intf in interfaces["s_axis"] + interfaces["m_axis"]: @@ -156,8 +152,7 @@ def apply(self, model): f.write("vivado -mode batch -source gen_xo.tcl\n") f.write("cd {}\n".format(working_dir)) bash_command = ["bash", package_xo_sh] - process_compile = subprocess.Popen( - bash_command, stdout=subprocess.PIPE) + process_compile = subprocess.Popen(bash_command, stdout=subprocess.PIPE) process_compile.communicate() assert os.path.isfile(xo_path), ( "Vitis .xo file not created, check logs under %s" % vivado_proj_dir @@ -217,24 +212,20 @@ def apply(self, model): # check top-level in/out list instead if producer is None: instance_names[node.name] = "idma" + str(idma_idx) - config.append("nk=%s:1:%s" % - (node.name, instance_names[node.name])) + config.append("nk=%s:1:%s" % (node.name, instance_names[node.name])) idma_idx += 1 elif consumer == []: instance_names[node.name] = "odma" + str(odma_idx) - config.append("nk=%s:1:%s" % - (node.name, instance_names[node.name])) + config.append("nk=%s:1:%s" % (node.name, instance_names[node.name])) odma_idx += 1 else: instance_names[node.name] = node.name - config.append("nk=%s:1:%s" % - (node.name, instance_names[node.name])) + config.append("nk=%s:1:%s" % (node.name, instance_names[node.name])) sdp_node.set_nodeattr("instance_name", instance_names[node.name]) # explicitly assign SLRs if the slr attribute is not -1 node_slr = sdp_node.get_nodeattr("slr") if node_slr != -1: - config.append("slr=%s:SLR%d" % - (instance_names[node.name], node_slr)) + config.append("slr=%s:SLR%d" % (instance_names[node.name], node_slr)) # assign memory banks if producer is None or consumer is None: node_mem_port = sdp_node.get_nodeattr("mem_port") @@ -259,8 +250,7 @@ def apply(self, model): mem_type = "DDR" mem_idx = 1 node_mem_port = "%s[%d]" % (mem_type, mem_idx) - config.append("sp=%s.m_axi_gmem0:%s" % - (instance_names[node.name], node_mem_port)) + config.append("sp=%s.m_axi_gmem0:%s" % (instance_names[node.name], node_mem_port)) # connect streams if producer is not None: for i in range(len(node.input)): @@ -284,16 +274,11 @@ def apply(self, model): # add Vivado physopt directives if desired if self.strategy == VitisOptStrategy.PERFORMANCE_BEST: config.append("[vivado]") - config.append( - "prop=run.impl_1.STEPS.OPT_DESIGN.ARGS.DIRECTIVE=ExploreWithRemap") - config.append( - "prop=run.impl_1.STEPS.PLACE_DESIGN.ARGS.DIRECTIVE=Explore") - config.append( - "prop=run.impl_1.STEPS.PHYS_OPT_DESIGN.IS_ENABLED=true") - config.append( - "prop=run.impl_1.STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE=Explore") - config.append( - "prop=run.impl_1.STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE=Explore") + config.append("prop=run.impl_1.STEPS.OPT_DESIGN.ARGS.DIRECTIVE=ExploreWithRemap") + config.append("prop=run.impl_1.STEPS.PLACE_DESIGN.ARGS.DIRECTIVE=Explore") + config.append("prop=run.impl_1.STEPS.PHYS_OPT_DESIGN.IS_ENABLED=true") + config.append("prop=run.impl_1.STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE=Explore") + config.append("prop=run.impl_1.STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE=Explore") config = "\n".join(config) + "\n" with open(link_dir + "/config.txt", "w") as f: @@ -330,8 +315,7 @@ def apply(self, model): ) f.write("cd {}\n".format(working_dir)) bash_command = ["bash", script] - process_compile = subprocess.Popen( - bash_command, stdout=subprocess.PIPE) + process_compile = subprocess.Popen(bash_command, stdout=subprocess.PIPE) process_compile.communicate() # TODO rename xclbin appropriately here? xclbin = link_dir + "/a.xclbin" @@ -346,8 +330,7 @@ def apply(self, model): with open(gen_rep_xml_sh, "w") as f: f.write("#!/bin/bash \n") f.write("cd {}\n".format(link_dir)) - f.write("vivado -mode batch -source %s\n" % - (link_dir + "/gen_report_xml.tcl")) + f.write("vivado -mode batch -source %s\n" % (link_dir + "/gen_report_xml.tcl")) f.write("cd {}\n".format(working_dir)) bash_command = ["bash", gen_rep_xml_sh] process_genxml = subprocess.Popen(bash_command, stdout=subprocess.PIPE) @@ -407,8 +390,7 @@ def apply(self, model): model = model.transform(Floorplan(floorplan=self.floorplan_file)) model = model.transform( - CreateDataflowPartition( - partition_model_dir=self.partition_model_dir) + CreateDataflowPartition(partition_model_dir=self.partition_model_dir) ) model = model.transform(GiveUniqueNodeNames()) model = model.transform(GiveReadableTensorNames()) @@ -424,15 +406,12 @@ def apply(self, model): kernel_model = kernel_model.transform(RemoveUnusedTensors()) kernel_model = kernel_model.transform(GiveUniqueNodeNames(prefix)) kernel_model.save(dataflow_model_filename) - kernel_model = kernel_model.transform( - PrepareIP(self.fpga_part, self.period_ns)) + kernel_model = kernel_model.transform(PrepareIP(self.fpga_part, self.period_ns)) kernel_model = kernel_model.transform(HLSSynthIP()) kernel_model = kernel_model.transform( - CreateStitchedIP(self.fpga_part, self.period_ns, - sdp_node.onnx_node.name, True) + CreateStitchedIP(self.fpga_part, self.period_ns, sdp_node.onnx_node.name, True) ) - kernel_model = kernel_model.transform( - CreateVitisXO(sdp_node.onnx_node.name)) + kernel_model = kernel_model.transform(CreateVitisXO(sdp_node.onnx_node.name)) kernel_model.set_metadata_prop("platform", "alveo") kernel_model.save(dataflow_model_filename) # Assemble design from kernels diff --git a/src/finn/util/basic.py b/src/finn/util/basic.py index f4a116810e..ea6aab7fd8 100644 --- a/src/finn/util/basic.py +++ b/src/finn/util/basic.py @@ -182,8 +182,7 @@ def build(self, code_gen_dir): f.write("#!/bin/bash \n") f.write(bash_compile + "\n") bash_command = ["bash", self.compile_script] - process_compile = subprocess.Popen( - bash_command, stdout=subprocess.PIPE) + process_compile = subprocess.Popen(bash_command, stdout=subprocess.PIPE) process_compile.communicate() diff --git a/src/finn/util/platforms.py b/src/finn/util/platforms.py index 56173f5935..ce00bc398a 100644 --- a/src/finn/util/platforms.py +++ b/src/finn/util/platforms.py @@ -104,8 +104,7 @@ def compute_resources(self): def guide_resources(self): guide = [] # TODO: assert limits is of correct size - guide_res = (np.tile(np.array(self.compute_resources), - (self.ndevices, 1))).astype(int) + guide_res = (np.tile(np.array(self.compute_resources), (self.ndevices, 1))).astype(int) for i in range(self.nslr * self.ndevices): # when in multi-FPGA mode, subtract cost of UDP connection from eth_slr local_slr = i % self.nslr @@ -147,8 +146,7 @@ def resource_count_dict(self): @property def compute_connection_cost(self): - x = np.full((self.nslr * self.ndevices, - self.nslr * self.ndevices), DONT_CARE) + x = np.full((self.nslr * self.ndevices, self.nslr * self.ndevices), DONT_CARE) # build connection cost matrix for one device's SLRs xlocal = np.full((self.nslr, self.nslr), DONT_CARE) for i in range(self.nslr): @@ -159,20 +157,16 @@ def compute_connection_cost(self): xlocal[i][j] = 1 # tile connection cost matrices for entire system for i in range(self.ndevices): - x[i * self.nslr: (i + 1) * self.nslr, i * - self.nslr: (i + 1) * self.nslr] = xlocal + x[i * self.nslr : (i + 1) * self.nslr, i * self.nslr : (i + 1) * self.nslr] = xlocal # set cost for ethernet connections, assuming daisy-chaining for i in range(self.ndevices - 1): - x[i * self.nslr + - self.eth_slr][(i + 1) * self.nslr + self.eth_slr] = 10 - x[(i + 1) * self.nslr + self.eth_slr][i * - self.nslr + self.eth_slr] = 10 + x[i * self.nslr + self.eth_slr][(i + 1) * self.nslr + self.eth_slr] = 10 + x[(i + 1) * self.nslr + self.eth_slr][i * self.nslr + self.eth_slr] = 10 return x @property def compute_connection_resource(self): - sll = np.full((self.nslr * self.ndevices, - self.nslr * self.ndevices), 0) + sll = np.full((self.nslr * self.ndevices, self.nslr * self.ndevices), 0) # build connection resource matrix for one device's SLRs slllocal = np.full((self.nslr, self.nslr), -1) for i in range(self.nslr): @@ -184,11 +178,9 @@ def compute_connection_resource(self): slllocal[i][j] = self.sll_count[i][j] # tile connection cost matrices for entire system for i in range(self.ndevices): - sll[i * self.nslr: (i + 1) * self.nslr, i * - self.nslr: (i + 1) * self.nslr] = slllocal + sll[i * self.nslr : (i + 1) * self.nslr, i * self.nslr : (i + 1) * self.nslr] = slllocal # set cost for ethernet connections, assuming daisy-chaining - eth = np.full((self.nslr * self.ndevices, - self.nslr * self.ndevices), 0) + eth = np.full((self.nslr * self.ndevices, self.nslr * self.ndevices), 0) # no Eth throughput constraints from one SLR to itself for i in range(self.ndevices * self.nslr): eth[i][i] = -1 @@ -210,8 +202,7 @@ def compute_connection_resource(self): # constrain for SLLs between SLRs on same device is_offchip = i // self.nslr != j // self.nslr constraints_line.append( - (-1 if is_offchip else sll[i][j], - eth[i][j] if is_offchip else -1) + (-1 if is_offchip else sll[i][j], eth[i][j] if is_offchip else -1) ) constraints.append(constraints_line) return constraints @@ -478,7 +469,7 @@ def __init__( avg_constraints=DEFAULT_AVG_CONSTRAINTS, ): sll_counts = [[0, 5000, 0], [5000, 0, 5000], [0, 5000, 0]] - super(Alveo_NxU50_Platform, self).__init__( + super(Alveo_NxU55C_Platform, self).__init__( nslr=2, ndevices=ndevices, sll_count=sll_counts, From d1d6f39cce4f8344d922e904efc45e7bb9a8d872 Mon Sep 17 00:00:00 2001 From: johnnoel Date: Tue, 7 Nov 2023 15:54:56 +0000 Subject: [PATCH 301/665] [Util] Revert U250 platform to 2_1 and reenable lfc/tfc U250 tests --- src/finn/util/basic.py | 2 +- tests/end2end/test_end2end_bnn_pynq.py | 13 ------------- 2 files changed, 1 insertion(+), 14 deletions(-) diff --git a/src/finn/util/basic.py b/src/finn/util/basic.py index 199e0bcbe5..edc84cb2bc 100644 --- a/src/finn/util/basic.py +++ b/src/finn/util/basic.py @@ -71,7 +71,7 @@ alveo_default_platform = dict() alveo_default_platform["U50"] = "xilinx_u50_gen3x16_xdma_5_202210_1" alveo_default_platform["U200"] = "xilinx_u200_gen3x16_xdma_2_202110_1" -alveo_default_platform["U250"] = "xilinx_u250_gen3x16_xdma_4_1_202210_1" +alveo_default_platform["U250"] = "xilinx_u250_gen3x16_xdma_2_1_202010_1" alveo_default_platform["U280"] = "xilinx_u280_gen3x16_xdma_1_202211_1" diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index 8ac2493d1e..b296dad827 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -728,19 +728,6 @@ def test_build(self, topology, wbits, abits, board): build_data = get_build_env(board, target_clk_ns) if build_data["kind"] == "alveo" and ("VITIS_PATH" not in os.environ): pytest.skip("VITIS_PATH not set") - if board == "U250" and wbits == 1 and abits == 1: - if topology == "lfc" or topology == "tfc": - pytest.xfail( - "bnn_w" - + str(wbits) - + "_a" - + str(abits) - + "_" - + topology - + "_" - + board - + " test_build currently disabled, see CR-1171874" - ) prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, "fifodepth_" + board) model = load_test_checkpoint_or_skip(prev_chkpt_name) model = model.transform(build_data["build_fxn"]) From 0ec575246ee274469b96c32379367db566058cd2 Mon Sep 17 00:00:00 2001 From: johnnoel Date: Wed, 8 Nov 2023 14:01:52 +0000 Subject: [PATCH 302/665] [Driver] Workaround for pynq on alveo bug Pynq on alveo uses tinynumpy under the hood which has a bug when converting between tinynumpy.ndarray and numpy.ndarray. Workaround is to first convert to list and then to numpy.ndarray. --- src/finn/qnn-data/templates/driver/driver_base.py | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/finn/qnn-data/templates/driver/driver_base.py b/src/finn/qnn-data/templates/driver/driver_base.py index f701122885..acf18cd850 100644 --- a/src/finn/qnn-data/templates/driver/driver_base.py +++ b/src/finn/qnn-data/templates/driver/driver_base.py @@ -193,7 +193,15 @@ def load_runtime_weights(self, flush_accel=True, verify=True): layer_w = rt_weight_dict[(sdp_ind, layer_ind)] layer_mmio.write_mm(0, layer_w.tobytes()) if verify: - new_w = np.copy(layer_mmio.array[: layer_w.shape[0]]) + if self.platform == "alveo": + # Pynq for Alveo uses tinynumpy under the hood. There is a bug when going + # from a tinynumpy.ndarray to numpy.ndarray. To work around this, we first + # convert the tinynumpy.ndarray to a list and then copy the list to a + # numpy.ndarray. This shouldn't affect the non-alveo platforms so no need to + # check platform. + new_w = np.copy(list(layer_mmio.array[: layer_w.shape[0]]), dtype=layer_w.dtype) + else: + new_w = np.copy(layer_mmio.array[: layer_w.shape[0]]) assert (layer_w == new_w).all() if flush_accel: # run accelerator to flush any stale weights from weight streamer FIFOs From 2a2afc66a594238dfce52e128ba44419d1b50a53 Mon Sep 17 00:00:00 2001 From: johnnoel Date: Wed, 8 Nov 2023 14:32:39 +0000 Subject: [PATCH 303/665] [Linting] Fix linting --- src/finn/qnn-data/templates/driver/driver_base.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/finn/qnn-data/templates/driver/driver_base.py b/src/finn/qnn-data/templates/driver/driver_base.py index acf18cd850..850fdc8993 100644 --- a/src/finn/qnn-data/templates/driver/driver_base.py +++ b/src/finn/qnn-data/templates/driver/driver_base.py @@ -199,7 +199,9 @@ def load_runtime_weights(self, flush_accel=True, verify=True): # convert the tinynumpy.ndarray to a list and then copy the list to a # numpy.ndarray. This shouldn't affect the non-alveo platforms so no need to # check platform. - new_w = np.copy(list(layer_mmio.array[: layer_w.shape[0]]), dtype=layer_w.dtype) + new_w = np.copy( + list(layer_mmio.array[: layer_w.shape[0]]), dtype=layer_w.dtype + ) else: new_w = np.copy(layer_mmio.array[: layer_w.shape[0]]) assert (layer_w == new_w).all() From 9b7f21f22bdbaeeaa984eca9c1ece751ebb5f3b0 Mon Sep 17 00:00:00 2001 From: Linus Jungemann Date: Wed, 8 Nov 2023 16:40:09 +0100 Subject: [PATCH 304/665] Remove unneccessary assignment --- src/finn/qnn-data/templates/driver/driver_base.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/finn/qnn-data/templates/driver/driver_base.py b/src/finn/qnn-data/templates/driver/driver_base.py index 1eafaef657..0d4df2484a 100644 --- a/src/finn/qnn-data/templates/driver/driver_base.py +++ b/src/finn/qnn-data/templates/driver/driver_base.py @@ -78,7 +78,7 @@ def __init__( Path to runtime weights folder. """ super().__init__(bitfile_name, download=download, device=device) - self.device = device + self.runtime_weight_dir = runtime_weight_dir self._io_shape_dict = io_shape_dict self.ibuf_packed_device = None From e1cc6dd73a71c0b1830703828bdf4298740255ca Mon Sep 17 00:00:00 2001 From: Linus Jungemann Date: Wed, 8 Nov 2023 16:42:10 +0100 Subject: [PATCH 305/665] Revert "Remove unneccessary assignment" This reverts commit 9b7f21f22bdbaeeaa984eca9c1ece751ebb5f3b0. --- src/finn/qnn-data/templates/driver/driver_base.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/finn/qnn-data/templates/driver/driver_base.py b/src/finn/qnn-data/templates/driver/driver_base.py index 0d4df2484a..1eafaef657 100644 --- a/src/finn/qnn-data/templates/driver/driver_base.py +++ b/src/finn/qnn-data/templates/driver/driver_base.py @@ -78,7 +78,7 @@ def __init__( Path to runtime weights folder. """ super().__init__(bitfile_name, download=download, device=device) - + self.device = device self.runtime_weight_dir = runtime_weight_dir self._io_shape_dict = io_shape_dict self.ibuf_packed_device = None From 86a96e99a18b6d3d9f8836d9d9e75df632697c61 Mon Sep 17 00:00:00 2001 From: johnnoel Date: Wed, 8 Nov 2023 16:24:49 +0000 Subject: [PATCH 306/665] [Driver] Update comment --- src/finn/qnn-data/templates/driver/driver_base.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/finn/qnn-data/templates/driver/driver_base.py b/src/finn/qnn-data/templates/driver/driver_base.py index 850fdc8993..373f8badd9 100644 --- a/src/finn/qnn-data/templates/driver/driver_base.py +++ b/src/finn/qnn-data/templates/driver/driver_base.py @@ -197,8 +197,7 @@ def load_runtime_weights(self, flush_accel=True, verify=True): # Pynq for Alveo uses tinynumpy under the hood. There is a bug when going # from a tinynumpy.ndarray to numpy.ndarray. To work around this, we first # convert the tinynumpy.ndarray to a list and then copy the list to a - # numpy.ndarray. This shouldn't affect the non-alveo platforms so no need to - # check platform. + # numpy.ndarray. new_w = np.copy( list(layer_mmio.array[: layer_w.shape[0]]), dtype=layer_w.dtype ) From f86c16bd0abb9ca3dacd3073b5e29e4ea32b1698 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 8 Nov 2023 16:58:45 +0000 Subject: [PATCH 307/665] [Tests] Fix Deconv Brevitas export test --- tests/brevitas/test_brevitas_deconv.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/brevitas/test_brevitas_deconv.py b/tests/brevitas/test_brevitas_deconv.py index 7b93f0367d..0808122b7d 100644 --- a/tests/brevitas/test_brevitas_deconv.py +++ b/tests/brevitas/test_brevitas_deconv.py @@ -34,7 +34,7 @@ from brevitas.export import export_qonnx from qonnx.core.modelwrapper import ModelWrapper from qonnx.transformation.infer_shapes import InferShapes -from qonnx.util.cleanup import cleanup_model as qonnx_cleanup +from qonnx.util.cleanup import cleanup as qonnx_cleanup import finn.core.onnx_exec as oxe from finn.transformation.qonnx.convert_qonnx_to_finn import ConvertQONNXtoFINN @@ -66,9 +66,9 @@ def test_brevitas_QTransposeConv(ifm_ch, ofm_ch, mh, mw, padding, stride, kw, bi bias=bias, ) # outp = el(inp) # expects NCHW data format - export_qonnx(b_deconv.cpu(), input_t=inp.cpu(), export_path=export_path, opset_version=11) + export_qonnx(b_deconv, input_t=inp, export_path=export_path, opset_version=11) + qonnx_cleanup(export_path, out_file=export_path) model = ModelWrapper(export_path) - qonnx_cleanup(model) model = model.transform(ConvertQONNXtoFINN()) model = model.transform(InferShapes()) inp_tensor = np.random.uniform(low=-1.0, high=1.0, size=ishape).astype(np.float32) From f72f65febe0e2154b1f9af851ef7ad17414d4c54 Mon Sep 17 00:00:00 2001 From: Linus Jungemann Date: Thu, 9 Nov 2023 09:06:53 +0100 Subject: [PATCH 308/665] Change compute_resources based on UG1120 --- src/finn/util/platforms.py | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/src/finn/util/platforms.py b/src/finn/util/platforms.py index ce00bc398a..8856ce0ab8 100644 --- a/src/finn/util/platforms.py +++ b/src/finn/util/platforms.py @@ -470,12 +470,12 @@ def __init__( ): sll_counts = [[0, 5000, 0], [5000, 0, 5000], [0, 5000, 0]] super(Alveo_NxU55C_Platform, self).__init__( - nslr=2, + nslr=3, ndevices=ndevices, sll_count=sll_counts, ddr_slr=[], hbm_slr=0, - eth_slr=2, + eth_slr=1, eth_gbps=100, limits=limits, avg_constraints=avg_constraints, @@ -484,14 +484,10 @@ def __init__( @property def compute_resources(self): # according to UG1120 - # return [[369000, 746000, 2*507, 320, 2733], - # [333000, 675000, 2*468, 320, 2877], - # [367000, 729000, 2*512, 320, 2880]] - # observed from Vivado: return [ - [400800, 2 * 400800, 2 * 600, 320, 2736], - [382080, 2 * 382080, 2 * 576, 320, 2880], - [380640, 2 * 380640, 2 * 576, 320, 2880], + [386000, 773000, 2 * 600, 320, 2664], + [364000, 729000, 2 * 576, 320, 2784], + [381000, 763000, 2 * 600, 320, 2856], ] From dfffaea14fd5de364150c4f89a1a53102ec4a122 Mon Sep 17 00:00:00 2001 From: Linus Jungemann Date: Thu, 9 Nov 2023 09:09:30 +0100 Subject: [PATCH 309/665] Fix accidental revert of wrong commit --- src/finn/qnn-data/templates/driver/driver_base.py | 1 - 1 file changed, 1 deletion(-) diff --git a/src/finn/qnn-data/templates/driver/driver_base.py b/src/finn/qnn-data/templates/driver/driver_base.py index 1eafaef657..55ab94d289 100644 --- a/src/finn/qnn-data/templates/driver/driver_base.py +++ b/src/finn/qnn-data/templates/driver/driver_base.py @@ -78,7 +78,6 @@ def __init__( Path to runtime weights folder. """ super().__init__(bitfile_name, download=download, device=device) - self.device = device self.runtime_weight_dir = runtime_weight_dir self._io_shape_dict = io_shape_dict self.ibuf_packed_device = None From 4e0df8f045b7d74ada29e9852bf4f91bc39e297c Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 10 Nov 2023 18:02:35 +0000 Subject: [PATCH 310/665] [CustomOp-Refactor] Initial draft of splitting HLSCustomOp class in HWCustomOp with HLS and RTL Backend using FMPadding --- src/finn/custom_op/fpgadataflow/__init__.py | 6 +- src/finn/custom_op/fpgadataflow/fmpadding.py | 164 ++++++ .../custom_op/fpgadataflow/hls/__init__.py | 35 ++ .../fpgadataflow/hls/fmpadding_hls.py | 291 +++++++++++ src/finn/custom_op/fpgadataflow/hlsbackend.py | 419 +++++++++++++++ src/finn/custom_op/fpgadataflow/hwcustomop.py | 481 ++++++++++++++++++ .../custom_op/fpgadataflow/rtl/__init__.py | 35 ++ .../fpgadataflow/rtl/fmpadding_rtl.py | 257 ++++++++++ src/finn/custom_op/fpgadataflow/rtlbackend.py | 61 +++ .../fpgadataflow/specialize_layers.py | 71 +++ 10 files changed, 1819 insertions(+), 1 deletion(-) create mode 100644 src/finn/custom_op/fpgadataflow/fmpadding.py create mode 100644 src/finn/custom_op/fpgadataflow/hls/__init__.py create mode 100644 src/finn/custom_op/fpgadataflow/hls/fmpadding_hls.py create mode 100644 src/finn/custom_op/fpgadataflow/hlsbackend.py create mode 100644 src/finn/custom_op/fpgadataflow/hwcustomop.py create mode 100644 src/finn/custom_op/fpgadataflow/rtl/__init__.py create mode 100644 src/finn/custom_op/fpgadataflow/rtl/fmpadding_rtl.py create mode 100644 src/finn/custom_op/fpgadataflow/rtlbackend.py create mode 100644 src/finn/transformation/fpgadataflow/specialize_layers.py diff --git a/src/finn/custom_op/fpgadataflow/__init__.py b/src/finn/custom_op/fpgadataflow/__init__.py index 56d4230a3a..ce05998fcc 100644 --- a/src/finn/custom_op/fpgadataflow/__init__.py +++ b/src/finn/custom_op/fpgadataflow/__init__.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2020-2022, Xilinx, Inc. +# Copyright (C) 2023, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -42,6 +43,7 @@ from finn.custom_op.fpgadataflow.downsampler import DownSampler from finn.custom_op.fpgadataflow.duplicatestreams_batch import DuplicateStreams_Batch from finn.custom_op.fpgadataflow.eltwise import StreamingEltwise +from finn.custom_op.fpgadataflow.fmpadding import FMPadding from finn.custom_op.fpgadataflow.fmpadding_batch import FMPadding_Batch from finn.custom_op.fpgadataflow.fmpadding_rtl import FMPadding_rtl from finn.custom_op.fpgadataflow.globalaccpool_batch import GlobalAccPool_Batch @@ -93,3 +95,5 @@ custom_op["CheckSum"] = CheckSum custom_op["StreamingEltwise"] = StreamingEltwise custom_op["FMPadding_rtl"] = FMPadding_rtl + +custom_op["FMPadding"] = FMPadding diff --git a/src/finn/custom_op/fpgadataflow/fmpadding.py b/src/finn/custom_op/fpgadataflow/fmpadding.py new file mode 100644 index 0000000000..0324984c3f --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/fmpadding.py @@ -0,0 +1,164 @@ +# Copyright (C) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import numpy as np +import warnings +from qonnx.core.datatype import DataType + +from finn.custom_op.fpgadataflow.hwcustomop import HWCustomOp + + +class FMPadding(HWCustomOp): + """Abstraction layer for HW impplementation of FMPadding. + Pads input image by given amount.""" + + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) + + def get_nodeattr_types(self): + my_attrs = { + # spatial size of input images + "ImgDim": ("ints", True, []), # [H, W] = [Y, X] + # total padding (per dimension) to apply + "Padding": ( + "ints", + True, + [1, 1, 1, 1], + ), # [H_begin, W_begin, H_end, W_end] = [Y_begin, X_begin, Y_end, X_end] + # number of channels in input image + "NumChannels": ("i", True, 0), + # SIMD Input parallelism + "SIMD": ("i", False, 1), + # FINN input datatype + "inputDataType": ("s", True, ""), + # shape describing input vecs per execution + "numInputVectors": ("i", False, 1), + } + my_attrs.update(super().get_nodeattr_types()) + return my_attrs + + def get_padded_odim(self): + "Return the padded spatial size of the output." + idim_h, idim_w = self.get_nodeattr("ImgDim") + pad = self.get_nodeattr("Padding") + pad_h = pad[0] + pad[2] + pad_w = pad[1] + pad[3] + odim_h = idim_h + pad_h + odim_w = idim_w + pad_w + return [odim_h, odim_w] + + def get_exp_cycles(self): + odim_h, odim_w = self.get_padded_odim() + channels = self.get_nodeattr("NumChannels") + simd = self.get_nodeattr("SIMD") + batch_size = self.get_nodeattr("numInputVectors") + exp_cycles = (channels / simd) * batch_size * odim_h * odim_w + return int(exp_cycles) + + def get_normal_input_shape(self, ind=0): + idim_h, idim_w = self.get_nodeattr("ImgDim") + num_ch = self.get_nodeattr("NumChannels") + ishape = (1, idim_h, idim_w, num_ch) + return ishape + + def get_normal_output_shape(self, ind=0): + odim_h, odim_w = self.get_padded_odim() + num_ch = self.get_nodeattr("NumChannels") + + oshape = (1, odim_h, odim_w, num_ch) + return oshape + + def get_folded_input_shape(self, ind=0): + normal_ishape = list(self.get_normal_input_shape()) + ifm_ch = self.get_nodeattr("NumChannels") + simd = self.get_nodeattr("SIMD") + assert ifm_ch % simd == 0, "SIMD must divide input channels" + fold = int(normal_ishape[-1] / simd) + folded_ishape = normal_ishape[:-1] + [fold, simd] + return tuple(folded_ishape) + + def get_folded_output_shape(self, ind=0): + normal_oshape = list(self.get_normal_output_shape()) + ifm_ch = self.get_nodeattr("NumChannels") + simd = self.get_nodeattr("SIMD") + assert ifm_ch % simd == 0, "SIMD must divide input channels" + fold = int(normal_oshape[-1] / simd) + folded_oshape = normal_oshape[:-1] + [fold, simd] + return tuple(folded_oshape) + + def make_shape_compatible_op(self, model): + exp_ishape = self.get_normal_input_shape() + oshape = self.get_normal_output_shape() + ishape = tuple(model.get_tensor_shape(self.onnx_node.input[0])) + assert ishape == exp_ishape, "Unexpect input shape for FMPadding." + return super().make_const_shape_op(oshape) + + def infer_node_datatype(self, model): + node = self.onnx_node + idt = model.get_tensor_datatype(node.input[0]) + if idt != self.get_input_datatype(): + warn_str = "inputDataType changing for %s: %s -> %s " % ( + node.name, + str(self.get_input_datatype()), + str(idt), + ) + warnings.warn(warn_str) + self.set_nodeattr("inputDataType", idt.name) + model.set_tensor_datatype(node.output[0], idt) + + def verify_node(self): + pass + + def get_input_datatype(self, ind=0): + """Returns FINN DataType of input.""" + ret = DataType[self.get_nodeattr("inputDataType")] + # the hlslib op always pads with zeros, so ensure that the DataType + # is able to represent zeros + assert ret.allowed(0), "FMPadding_Batch DataType must support zero" + return ret + + def get_output_datatype(self, ind=0): + """Returns FINN DataType of output. (Same as input datatype)""" + return self.get_input_datatype() + + def get_instream_width(self, ind=0): + ibits = self.get_input_datatype().bitwidth() + simd = self.get_nodeattr("SIMD") + return ibits * simd + + def get_outstream_width(self, ind=0): + obits = self.get_output_datatype().bitwidth() + simd = self.get_nodeattr("SIMD") + return obits * simd + + def get_number_output_values(self): + folded_oshape = self.get_folded_output_shape() + return np.prod(folded_oshape[:-1]) + + def execute_node(self, context, graph): + pass diff --git a/src/finn/custom_op/fpgadataflow/hls/__init__.py b/src/finn/custom_op/fpgadataflow/hls/__init__.py new file mode 100644 index 0000000000..f381639fba --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/hls/__init__.py @@ -0,0 +1,35 @@ +# Copyright (C) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from finn.custom_op.fpgadataflow.hls.fmpadding_hls import FMPadding_hls + +custom_op = dict() + +# make sure new HLSCustomOp subclasses are imported here so that they get +# registered and plug in correctly into the infrastructure +custom_op["FMPadding_hls"] = FMPadding_hls diff --git a/src/finn/custom_op/fpgadataflow/hls/fmpadding_hls.py b/src/finn/custom_op/fpgadataflow/hls/fmpadding_hls.py new file mode 100644 index 0000000000..3b0b870e23 --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/hls/fmpadding_hls.py @@ -0,0 +1,291 @@ +# Copyright (C) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import numpy as np +import os +from qonnx.core.datatype import DataType + +from finn.custom_op.fpgadataflow.fmpadding import FMPadding +from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend +from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy + + +class FMPadding_hls(FMPadding, HLSBackend): + """Corresponds to finn-hlslib FMPadding_Batch function. + Pads input image by given amount.""" + + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) + + def get_nodeattr_types(self): + my_attrs = {} + my_attrs.update(FMPadding.get_nodeattr_types(self)) + my_attrs.update(HLSBackend.get_nodeattr_types(self)) + return my_attrs + + def global_includes(self): + self.code_gen_dict["$GLOBALS$"] = ['#include "streamtools.h"'] + + def defines(self, var): + idim_h, idim_w = self.get_nodeattr("ImgDim") + odim_h, odim_w = self.get_padded_odim() + pad = self.get_nodeattr("Padding") + pad_h = pad[0] + pad[2] + pad_w = pad[1] + pad[3] + is_square_img = idim_h == idim_w + is_square_pad = pad_h == pad_w + + if is_square_img and is_square_pad: + self.code_gen_dict["$DEFINES$"] = [ + """#define ImgDim1 {}\n#define OutputDim1 {}\n + #define PaddingBefore1 {}\n#define PaddingBehind1 {}\n + #define NumChannels1 {}\n#define SIMD1 {}\n + #define numReps {}\n""".format( + idim_h, + odim_h, + pad[0], + pad[2], + self.get_nodeattr("NumChannels"), + self.get_nodeattr("SIMD"), + self.get_nodeattr("numInputVectors"), + ) + ] + else: + self.code_gen_dict["$DEFINES$"] = [ + """ + #define OutputDim1_x {}\n + #define OutputDim1_y {}\n + #define PaddingLeft1 {}\n + #define PaddingRight1 {}\n + #define PaddingTop1 {}\n + #define PaddingBottom1 {}\n + #define NumChannels1 {}\n + #define SIMD1 {}\n + #define numReps {}\n + """.format( + odim_w, + odim_h, + pad[1], + pad[3], + pad[0], + pad[2], + self.get_nodeattr("NumChannels"), + self.get_nodeattr("SIMD"), + self.get_nodeattr("numInputVectors"), + ) + ] + + def read_npy_data(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_input_datatype() + if dtype == DataType["BIPOLAR"]: + # use binary for bipolar storage + dtype = DataType["BINARY"] + elem_bits = dtype.bitwidth() + packed_bits = self.get_instream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "float" + npy_in = "%s/input_0.npy" % code_gen_dir + self.code_gen_dict["$READNPYDATA$"] = [] + self.code_gen_dict["$READNPYDATA$"].append( + 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) + ) + + def strm_decl(self): + self.code_gen_dict["$STREAMDECLARATIONS$"] = [] + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> in0_{} ("in0_{}");'.format( + self.get_instream_width(), self.hls_sname(), self.hls_sname() + ) + ) + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> out_{} ("out_{}");'.format( + self.get_outstream_width(), self.hls_sname(), self.hls_sname() + ) + ) + + def docompute(self): + in_t = self.get_input_datatype().get_hls_datatype_str() + idim_h, idim_w = self.get_nodeattr("ImgDim") + pad = self.get_nodeattr("Padding") + pad_h = pad[0] + pad[2] + pad_w = pad[1] + pad[3] + is_square_img = idim_h == idim_w + is_square_pad = pad_h == pad_w + + if is_square_img and is_square_pad: + hls_call = "FMPadding_Batch" + self.code_gen_dict["$DOCOMPUTE$"] = [ + """{} (in0_{}, out_{}, numReps);""".format( + hls_call, in_t, self.hls_sname(), self.hls_sname() + ) + ] + else: + hls_call = "FMPadding_nonsquare_Batch" + self.code_gen_dict["$DOCOMPUTE$"] = [ + """{} (in0_{}, out_{}, numReps);""".format( + hls_call, in_t, self.hls_sname(), self.hls_sname() + ) + ] + + def dataoutstrm(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_output_datatype() + if dtype == DataType["BIPOLAR"]: + # use binary for bipolar storage + dtype = DataType["BINARY"] + elem_bits = dtype.bitwidth() + packed_bits = self.get_outstream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "float" + npy_out = "%s/output.npy" % code_gen_dir + oshape = self.get_folded_output_shape() + oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") + + self.code_gen_dict["$DATAOUTSTREAM$"] = [ + 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + self.hls_sname(), + oshape_cpp_str, + npy_out, + ) + ] + + def save_as_npy(self): + self.code_gen_dict["$SAVEASCNPY$"] = [] + + def blackboxfunction(self): + packed_bits = self.get_instream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ + "void %s(hls::stream<%s > &in0_%s, hls::stream<%s > &out_%s)" + % ( + self.onnx_node.name, + packed_hls_type, + self.hls_sname(), + packed_hls_type, + self.hls_sname(), + ) + ] + + def pragmas(self): + self.code_gen_dict["$PRAGMAS$"] = [ + "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() + ] + self.code_gen_dict["$PRAGMAS$"].append( + "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() + ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") + + def execute_node(self, context, graph): + mode = self.get_nodeattr("exec_mode") + node = self.onnx_node + exp_ishape = self.get_normal_input_shape() + exp_oshape = self.get_normal_output_shape() + folded_ishape = self.get_folded_input_shape() + + if mode == "cppsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + elif mode == "rtlsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + + inp = context[node.input[0]] + assert str(inp.dtype) == "float32", "Input datatype is not float32" + assert ( + inp.shape == exp_ishape + ), """Input shape doesn't + match expected shape (1, ImgDim_h, ImgDim_w, NumChannels).""" + export_idt = self.get_input_datatype() + + reshaped_input = inp.reshape(folded_ishape) + np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input) + + if mode == "cppsim": + # execute the precompiled model + super().exec_precompiled_singlenode_model() + # load output npy file + super().npy_to_dynamic_output(context) + assert ( + context[node.output[0]].shape == exp_oshape + ), "cppsim did not produce expected output shape" + elif mode == "rtlsim": + sim = self.get_rtlsim() + nbits = self.get_instream_width() + rtlsim_inp = npy_to_rtlsim_input( + "{}/input_0.npy".format(code_gen_dir), export_idt, nbits + ) + super().reset_rtlsim(sim) + super().toggle_clk(sim) + rtlsim_output = self.rtlsim(sim, rtlsim_inp) + odt = export_idt + target_bits = odt.bitwidth() + packed_bits = self.get_outstream_width() + out_npy_path = "{}/output.npy".format(code_gen_dir) + out_shape = self.get_folded_output_shape() + rtlsim_output_to_npy( + rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits + ) + # load and reshape output + output = np.load(out_npy_path) + output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) + context[node.output[0]] = output + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + assert ( + context[node.output[0]].shape == exp_oshape + ), """Output shape doesn't match expected shape + (1, OutputDim_H, OutputDim_W, NumChannels).""" diff --git a/src/finn/custom_op/fpgadataflow/hlsbackend.py b/src/finn/custom_op/fpgadataflow/hlsbackend.py new file mode 100644 index 0000000000..403b992a05 --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/hlsbackend.py @@ -0,0 +1,419 @@ +# Copyright (C) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import numpy as np +import os +import subprocess +from abc import ABC, abstractmethod +from qonnx.core.datatype import DataType + +from finn.custom_op.fpgadataflow import templates +from finn.util.basic import CppBuilder, get_rtlsim_trace_depth, make_build_dir +from finn.util.hls import CallHLS +from finn.util.pyverilator import make_single_source_file + +try: + from pyverilator import PyVerilator +except ModuleNotFoundError: + PyVerilator = None + + +class HLSBackend(ABC): + """HLSBackend class all custom ops that correspond to a finn-hlslib + function are using functionality of. Contains different functions every HLS + custom node should have. Some as abstract methods, these have to be filled + when writing a new HLS custom op node.""" + + def get_nodeattr_types(self): + return { + "code_gen_dir_cppsim": ("s", False, ""), + "executable_path": ("s", False, ""), + "res_hls": ("s", False, ""), + } + + def get_all_verilog_paths(self): + "Return list of all folders containing Verilog code for this node." + + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + assert ( + code_gen_dir != "" + ), """Node attribute "code_gen_dir_ipgen" is + not set. Please run HLSSynthIP first.""" + verilog_path = "{}/project_{}/sol1/impl/verilog/".format(code_gen_dir, self.onnx_node.name) + # default impl only returns the HLS verilog codegen dir + return [verilog_path] + + def get_all_verilog_filenames(self, abspath=False): + "Return list of all Verilog files used for this node." + + verilog_files = [] + verilog_paths = self.get_all_verilog_paths() + for verilog_path in verilog_paths: + for f in os.listdir(verilog_path): + if f.endswith(".v"): + if abspath: + verilog_files += [verilog_path + "/" + f] + else: + verilog_files += [f] + return verilog_files + + def prepare_rtlsim(self): + """Creates a Verilator emulation library for the RTL code generated + for this node, sets the rtlsim_so attribute to its path and returns + a PyVerilator wrapper around it.""" + + if PyVerilator is None: + raise ImportError("Installation of PyVerilator is required.") + + verilog_files = self.get_all_verilog_filenames(abspath=True) + single_src_dir = make_build_dir("rtlsim_" + self.onnx_node.name + "_") + tmp_build_dir = make_build_dir("pyverilator_" + self.onnx_node.name + "_") + target_file = single_src_dir + "/" + self.get_verilog_top_module_name() + ".v" + make_single_source_file(verilog_files, target_file) + + # build the Verilator emu library + sim = PyVerilator.build( + self.get_verilog_top_module_name() + ".v", + build_dir=tmp_build_dir, + verilog_path=[single_src_dir], + trace_depth=get_rtlsim_trace_depth(), + top_module_name=self.get_verilog_top_module_name(), + ) + # save generated lib filename in attribute + self.set_nodeattr("rtlsim_so", sim.lib._name) + return sim + + def code_generation_ipgen(self, model, fpgapart, clk): + """Generates c++ code and tcl script for ip generation.""" + node = self.onnx_node + + # generate top cpp file for ip generation + path = self.get_nodeattr("code_gen_dir_ipgen") + self.code_gen_dict["$AP_INT_MAX_W$"] = [str(self.get_ap_int_max_w())] + self.generate_params(model, path) + self.global_includes() + self.defines("ipgen") + self.blackboxfunction() + self.pragmas() + self.docompute() + + template = templates.ipgen_template + + for key in self.code_gen_dict: + # transform list into long string separated by '\n' + code_gen_line = "\n".join(self.code_gen_dict[key]) + template = template.replace(key, code_gen_line) + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + f = open(os.path.join(code_gen_dir, "top_{}.cpp".format(node.name)), "w") + f.write(template) + f.close() + self.code_gen_dict.clear() + + # generate tcl script for ip generation + self.code_gen_dict["$PROJECTNAME$"] = ["project_{}".format(node.name)] + self.code_gen_dict["$HWSRCDIR$"] = [code_gen_dir] + self.code_gen_dict["$FPGAPART$"] = [fpgapart] + self.code_gen_dict["$TOPFXN$"] = [node.name] + self.code_gen_dict["$CLKPERIOD$"] = [str(clk)] + self.code_gen_dict["$DEFAULT_DIRECTIVES$"] = self.ipgen_default_directives() + self.code_gen_dict["$EXTRA_DIRECTIVES$"] = self.ipgen_extra_directives() + + template = templates.ipgentcl_template + + for key in self.code_gen_dict: + # transform list into long string separated by '\n' + code_gen_line = "\n".join(self.code_gen_dict[key]) + template = template.replace(key, code_gen_line) + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + f = open(os.path.join(code_gen_dir, "hls_syn_{}.tcl".format(node.name)), "w") + f.write(template) + f.close() + self.code_gen_dict.clear() + + def ipgen_default_directives(self): + """Return list of default HLS synthesis directives""" + + default_directives = [ + "set_param hls.enable_hidden_option_error false", + "config_compile -disable_unroll_code_size_check -pipeline_style flp", + "config_interface -m_axi_addr64", + "config_rtl -module_auto_prefix", + "config_rtl -deadlock_detection none", + ] + return default_directives + + def ipgen_extra_directives(self): + "Return a list of extra tcl directives for HLS synthesis." + return [] + + def ipgen_singlenode_code(self): + """Builds the bash script for IP generation using the CallHLS utility.""" + node = self.onnx_node + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + builder = CallHLS() + builder.append_tcl(code_gen_dir + "/hls_syn_{}.tcl".format(node.name)) + builder.set_ipgen_path(code_gen_dir + "/project_{}".format(node.name)) + builder.build(code_gen_dir) + ipgen_path = builder.ipgen_path + assert os.path.isdir(ipgen_path), "IPGen failed: %s not found" % (ipgen_path) + self.set_nodeattr("ipgen_path", ipgen_path) + ip_path = ipgen_path + "/sol1/impl/ip" + assert os.path.isdir(ip_path), "IPGen failed: %s not found. Check log under %s" % ( + ip_path, + code_gen_dir, + ) + self.set_nodeattr("ip_path", ip_path) + vlnv = "xilinx.com:hls:%s:1.0" % node.name + self.set_nodeattr("ip_vlnv", vlnv) + + def code_generation_cppsim(self, model): + """Generates c++ code for simulation (cppsim).""" + node = self.onnx_node + path = self.get_nodeattr("code_gen_dir_cppsim") + self.code_gen_dict["$AP_INT_MAX_W$"] = [str(self.get_ap_int_max_w())] + self.generate_params(model, path) + self.global_includes() + self.defines("cppsim") + self.read_npy_data() + self.strm_decl() + self.pragmas() + self.docompute() + self.dataoutstrm() + self.save_as_npy() + + template = templates.docompute_template + + for key in self.code_gen_dict: + # transform list into long string separated by '\n' + code_gen_line = "\n".join(self.code_gen_dict[key]) + template = template.replace(key, code_gen_line) + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + f = open(os.path.join(code_gen_dir, "execute_{}.cpp".format(node.op_type)), "w") + f.write(template) + f.close() + self.code_gen_dict.clear() + + def code_generation_ipi(self): + """Constructs and returns the TCL for node instantiation in Vivado IPI.""" + vlnv = self.get_nodeattr("ip_vlnv") + cmd = ["create_bd_cell -type ip -vlnv %s %s" % (vlnv, self.onnx_node.name)] + return cmd + + def compile_singlenode_code(self): + """Builds the bash script for compilation using the CppBuilder from + finn.util.basic and executes the script to produce the executable.""" + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + builder = CppBuilder() + # to enable additional debug features please uncommand the next line + # builder.append_includes("-DDEBUG") + builder.append_includes("-I$FINN_ROOT/src/finn/qnn-data/cpp") + builder.append_includes("-I$FINN_ROOT/deps/cnpy/") + builder.append_includes("-I$FINN_ROOT/deps/finn-hlslib") + builder.append_includes("-I$FINN_ROOT/custom_hls") + builder.append_includes("-I{}/include".format(os.environ["HLS_PATH"])) + builder.append_includes("--std=c++14") + builder.append_includes("-O3") + builder.append_sources(code_gen_dir + "/*.cpp") + builder.append_sources("$FINN_ROOT/deps/cnpy/cnpy.cpp") + builder.append_includes("-lz") + builder.set_executable_path(code_gen_dir + "/node_model") + builder.build(code_gen_dir) + self.set_nodeattr("executable_path", builder.executable_path) + + def dynamic_input_to_npy(self, context, count, target_dir=""): + """Saves input (given context) into .npy files. + + Count indicates the number of inputs that have to be saved.""" + node = self.onnx_node + if target_dir == "": + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + if code_gen_dir == "": + raise Exception( + """ + Found no codegen dir for this node, did you run the prepare_cppsim transformation? + """ + ) + target_dir = code_gen_dir + # create a npy file for each input of the node (in_ind is input index) + # assuming dynamic inputs start from 0 + for in_ind in range(count): + current_input_name = node.input[in_ind] + input_array = context[current_input_name] + if in_ind == 0: + expected_inp_shape = self.get_folded_input_shape() + idt = self.get_input_datatype() + else: + expected_inp_shape = self.get_folded_input_shape(in_ind) + idt = self.get_input_datatype(in_ind) + reshaped_input = input_array.reshape(expected_inp_shape) + if idt == DataType["BIPOLAR"]: + # store bipolar activations as binary + reshaped_input = (reshaped_input + 1) / 2 + # make copy before saving the array + reshaped_input = reshaped_input.copy() + np.save( + os.path.join(target_dir, "input_{}.npy".format(in_ind)), + reshaped_input, + ) + + def npy_to_dynamic_output(self, context): + """Reads the output from an output.npy file generated from cppsim and + places its content into the context dictionary.""" + node = self.onnx_node + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + output = np.load("{}/output.npy".format(code_gen_dir)) + exp_shape = self.get_normal_output_shape() + context[node.output[0]] = output.reshape(exp_shape) + + def npy_to_dynamic_outputs(self, context, npy_list): + """Reads the output from .npy files generated from cppsim and places + their content into the context dictionary. + npy_list is a list specifying which files to read, and its order must + match the order of node outputs.""" + node = self.onnx_node + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + for i in range(len(npy_list)): + output = np.load("{}/{}".format(code_gen_dir, npy_list[i])) + if i == 0: + exp_shape = self.get_normal_output_shape() + else: + exp_shape = self.get_normal_output_shape(i) + context[node.output[i]] = output.reshape(exp_shape) + + def exec_precompiled_singlenode_model(self): + """Executes precompiled executable.""" + executable_path = self.get_nodeattr("executable_path") + if executable_path == "": + raise Exception( + """ +Found no executable for this node, did you run the codegen and +compilation transformations? + """ + ) + process_execute = subprocess.Popen(executable_path, stdout=subprocess.PIPE) + process_execute.communicate() + + def hls_sname(self): + """Get the naming convention used by Vitis HLS for stream signals + Example: the TDATA for a stream called "out" would be out_V_TDATA. + """ + return "V" + + def execute_node(self, context, graph): + """Executes single node using cppsim or rtlsim.""" + mode = self.get_nodeattr("exec_mode") + if mode == "cppsim": + # save input(s) + self.dynamic_input_to_npy(context, 1) + # execute the precompiled model + self.exec_precompiled_singlenode_model() + # load output npy file + self.npy_to_dynamic_output(context) + elif mode == "rtlsim": + pass + + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + + @abstractmethod + def global_includes(self): + """Function to set the global includes for c++ code that has to be generated + for cppsim or rtlsim, is member function of HLSBackend class but has to + be filled by every node.""" + pass + + @abstractmethod + def defines(self, var): + """Function to set the define commands for c++ code that has to be generated + for cppsim or rtlsim, is member function of HLSBackend class but has to + be filled by every node. + + var: makes it possible to reuse the function for different c++ code generation. + I.e. if set to "ipgen" in MatrixVectorActivation additional PRAGMA defines are + added.""" + pass + + @abstractmethod + def read_npy_data(self): + """Function to generate the commands for reading data from .npy file in c++, + is member function of HLSBackend class but has to be filled by every node.""" + pass + + @abstractmethod + def strm_decl(self): + """Function to generate the commands for the stream declaration in c++, + is member function of HLSBackend class but has to be filled + by every node.""" + pass + + @abstractmethod + def docompute(self): + """Function to generate the commands for the computational part of the + c++ code, is member function of HLSBackend class but has to be filled + by every node.""" + pass + + @abstractmethod + def dataoutstrm(self): + """Function to generate the commands for reading out data from c++ and convert + into npy format, is member function of HLSBackend class but has to be filled + by every node.""" + pass + + @abstractmethod + def save_as_npy(self): + """Function to generate the commands for saving data in .npy file in c++, + is member function of HLSBackend class but has to be filled by every node.""" + pass + + @abstractmethod + def blackboxfunction(self): + """Function to generate a blackbock function in c++ from which an IP block + will be generated, is member function of HLSBackend class but has to be filled + by every node.""" + pass + + @abstractmethod + def pragmas(self): + """Function to generate the pragma commands in c++, is member function of + HLSBackend class but has to be filled by every node.""" + pass + + def get_ap_int_max_w(self): + """Return the maximum width of any ap_int used in this module. Used to set the + AP_INT_MAX_W definition for HLS.""" + instream = self.get_instream_width() + outstream = self.get_outstream_width() + ret = max([instream, outstream]) + assert ret <= 32768, "AP_INT_MAX_W=%d is larger than allowed maximum of 32768" % ret + return ret diff --git a/src/finn/custom_op/fpgadataflow/hwcustomop.py b/src/finn/custom_op/fpgadataflow/hwcustomop.py new file mode 100644 index 0000000000..bf89bcc0b4 --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/hwcustomop.py @@ -0,0 +1,481 @@ +# Copyright (C) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import numpy as np +import os +import warnings +from abc import abstractmethod +from pyverilator.util.axi_utils import _read_signal, reset_rtlsim, rtlsim_multi_io +from qonnx.custom_op.base import CustomOp +from qonnx.util.basic import roundup_to_integer_multiple + +from finn.util.basic import pyverilate_get_liveness_threshold_cycles + +try: + from pyverilator import PyVerilator +except ModuleNotFoundError: + PyVerilator = None + + +class HWCustomOp(CustomOp): + """HWCustomOp class all custom ops that can be implemented with either + HLS or RTL backend are based on. Contains different functions every fpgadataflow + custom node should have. Some as abstract methods, these have to be filled + when writing a new fpgadataflow custom op node.""" + + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) + self.code_gen_dict = {} + + def get_nodeattr_types(self): + return { + "backend": ("s", True, "fpgadataflow"), + "preferred_impl_style": ("s", False, "", {"", "hls", "rtl"}), + "code_gen_dir_ipgen": ("s", False, ""), + "ipgen_path": ("s", False, ""), + "ip_path": ("s", False, ""), + "ip_vlnv": ("s", False, ""), + "exec_mode": ("s", False, "", {"", "rtlsim", "cppsim"}), + "cycles_rtlsim": ("i", False, 0), + "cycles_estimate": ("i", False, 0), + "rtlsim_trace": ("s", False, ""), + "res_estimate": ("s", False, ""), + "res_synth": ("s", False, ""), + "rtlsim_so": ("s", False, ""), + # partitioning info + # ID of SLR to which the Op is attached in Vitis builds + # Set to -1 as 'don't care' + "slr": ("i", False, -1), + # Vitis memory port to which any AXI-MM interface + # of this Op should be attached in Vitis builds + # E.g.: "DDR[0]", "HBM[0]", "PLRAM[0]" + "mem_port": ("s", False, ""), + # Partition to which the Op belongs; all Ops with the + # same partition_id are stitched together + # Users should avoid setting this attribute manually + # and instead use the floorplan transform to set + # partition IDs from Vitis design rules and SLR IDs + "partition_id": ("i", False, 0), + # ID of FPGA device to which this Op is allocated, in + # a multi-FPGA setting + "device_id": ("i", False, 0), + # input and output FIFO depths for multi-I/O nodes + "inFIFODepths": ("ints", False, [2]), + "outFIFODepths": ("ints", False, [2]), + "output_hook": ("s", False, ""), + # accumulated characteristic function over two periods + "io_chrc_in": ("t", False, np.asarray([], dtype=np.int32)), + "io_chrc_out": ("t", False, np.asarray([], dtype=np.int32)), + # the period for which the characterization was run + "io_chrc_period": ("i", False, 0), + # amount of zero padding inserted during chrc. + "io_chrc_pads_in": ("ints", False, []), + "io_chrc_pads_out": ("ints", False, []), + } + + def get_verilog_top_module_name(self): + "Return the Verilog top module name for this node." + + node = self.onnx_node + prefixed_top_name = node.name + + return prefixed_top_name + + def get_verilog_top_module_intf_names(self): + """Return a dict of names of input and output interfaces. + The keys reflect the protocols each interface implements: + 'clk', 'rst', 'm_axis', 's_axis', 'aximm', 'axilite'. + Values are lists of tuples (axis, aximm) or names (axilite): + 'axis' tuples correspond to the list of node inputs in order, + each tuple is (interface_name, interface_width_bits). + axilite always assumed to be 32 bits and is not tuple (name only). + Each block must have at most one aximm and one axilite.""" + intf_names = {} + intf_names["clk"] = ["ap_clk"] + intf_names["rst"] = ["ap_rst_n"] + sname = self.hls_sname() + intf_names["s_axis"] = [("in0_" + sname, self.get_instream_width_padded())] + intf_names["m_axis"] = [("out_" + sname, self.get_outstream_width_padded())] + intf_names["aximm"] = [] + intf_names["axilite"] = [] + intf_names["ap_none"] = [] + return intf_names + + def get_verilog_top_filename(self): + "Return the Verilog top module filename for this node." + + verilog_file = "{}/project_{}/sol1/impl/verilog/{}.v".format( + self.get_nodeattr("code_gen_dir_ipgen"), + self.onnx_node.name, + self.get_verilog_top_module_name(), + ) + return verilog_file + + def get_rtlsim(self): + """Return a PyVerilator wrapper for the Verilator emulation library + for this node.""" + + rtlsim_so = self.get_nodeattr("rtlsim_so") + assert os.path.isfile(rtlsim_so), "Cannot find rtlsim library." + # create PyVerilator wrapper + sim = PyVerilator(rtlsim_so) + return sim + + def node_res_estimation(self): + """Returns summarized resource estimation of BRAMs and LUTs + of the node as a dictionary.""" + ret = dict() + ret["BRAM_18K"] = self.bram_estimation() + ret["BRAM_efficiency"] = self.bram_efficiency_estimation() + ret["LUT"] = self.lut_estimation() + ret["URAM"] = self.uram_estimation() + ret["URAM_efficiency"] = self.uram_efficiency_estimation() + ret["DSP"] = self.dsp_estimation() + return ret + + def bram_efficiency_estimation(self): + """Function for BRAM efficiency estimation: actual parameter storage + needed divided by the allocated BRAM storage (from estimation)""" + return 1 + + def uram_efficiency_estimation(self): + """Function for URAM efficiency estimation: actual parameter storage + needed divided by the allocated URAM storage (from estimation)""" + return 1 + + def bram_estimation(self): + """Function for BRAM resource estimation, is member function of + HLSCustomOp class but has to be filled by every node""" + return 0 + + def uram_estimation(self): + """Function for UltraRAM resource estimation, is member function of + HLSCustomOp class but has to be filled by every node""" + return 0 + + def lut_estimation(self): + """Function for LUT resource estimation, is member function of + HLSCustomOp class but has to be filled by every node""" + return 0 + + def dsp_estimation(self): + """Function for DSP resource estimation, is member function of + HLSCustomOp class but has to be filled by every node""" + return 0 + + def get_exp_cycles(self): + """Function for estimation of expected cycles for set folding, + is member function of HLSCustomOp class but has to be filled + by every node""" + return 0 + + def get_op_and_param_counts(self): + """Return a dictionary with number of ops needed per inference for + this layer as well as parameter count (weights, thresholds, etc.). + Entries should be in the format: + {op_ : , param_: }.""" + return {} + + def reset_rtlsim(self, sim): + """Sets reset input in pyverilator to zero, toggles the clock and set it + back to one""" + sim.io.ap_rst_n = 0 + sim.io.ap_clk = 1 + sim.io.ap_clk = 0 + sim.io.ap_rst_n = 1 + + def toggle_clk(self, sim): + """Toggles the clock input in pyverilator once.""" + sim.io.ap_clk = 1 + sim.io.ap_clk = 0 + + def rtlsim(self, sim, inp, inp2=None): + """Runs the pyverilator simulation by passing the input values to the simulation, + toggle the clock and observing the execution time. Function contains also an + observation loop that can abort the simulation if no output value is produced + after 100 cycles.""" + + trace_file = self.get_nodeattr("rtlsim_trace") + if trace_file != "": + if trace_file == "default": + trace_file = self.onnx_node.name + ".vcd" + sim.start_vcd_trace(trace_file) + inputs = inp + outputs = [] + sname = self.hls_sname() + o_ready = "out_" + sname + "_TREADY" + o_valid = "out_" + sname + "_TVALID" + o_data = "out_" + sname + "_TDATA" + in0_ready = "in0_" + sname + "_TREADY" + in0_valid = "in0_" + sname + "_TVALID" + in0_data = "in0_" + sname + "_TDATA" + in1_ready = "in1_" + sname + "_TREADY" + in1_valid = "in1_" + sname + "_TVALID" + in1_data = "in1_" + sname + "_TDATA" + + sim.io[o_ready] = 1 + + # observe if output is completely calculated + # observation_count will contain the number of cycles the calculation ran + num_out_values = self.get_number_output_values() + output_observed = False + observation_count = 0 + + # avoid infinite looping of simulation by aborting when there is no change in + # output values after 100 cycles + no_change_count = 0 + old_outputs = outputs + liveness_threshold = pyverilate_get_liveness_threshold_cycles() + + while not (output_observed): + sim.io[in0_valid] = 1 if len(inputs) > 0 else 0 + sim.io[in0_data] = inputs[0] if len(inputs) > 0 else 0 + if sim.io[in0_ready] == 1 and sim.io[in0_valid] == 1: + inputs = inputs[1:] + + if inp2 is not None: + sim.io[in1_valid] = 1 if len(inp2) > 0 else 0 + sim.io[in1_data] = inp2[0] if len(inp2) > 0 else 0 + if sim.io[in1_ready] == 1 and sim.io[in1_valid] == 1: + inp2 = inp2[1:] + + if sim.io[o_valid] == 1 and sim.io[o_ready] == 1: + outputs = outputs + [sim.io[o_data]] + sim.io.ap_clk = 1 + sim.io.ap_clk = 0 + + observation_count = observation_count + 1 + no_change_count = no_change_count + 1 + + if len(outputs) == num_out_values: + self.set_nodeattr("cycles_rtlsim", observation_count) + output_observed = True + + if no_change_count == liveness_threshold: + if old_outputs == outputs: + if trace_file != "": + sim.flush_vcd_trace() + sim.stop_vcd_trace() + raise Exception( + "Error in simulation! Takes too long to produce output. " + "Consider setting the LIVENESS_THRESHOLD env.var. to a " + "larger value." + ) + else: + no_change_count = 0 + old_outputs = outputs + if trace_file != "": + sim.flush_vcd_trace() + sim.stop_vcd_trace() + return outputs + + def rtlsim_multi_io(self, sim, io_dict): + "Run rtlsim for this node, supports multiple i/o streams." + + # signal name + sname = "_" + self.hls_sname() + "_" + + trace_file = self.get_nodeattr("rtlsim_trace") + if trace_file == "default": + trace_file = self.onnx_node.name + ".vcd" + num_out_values = self.get_number_output_values() + total_cycle_count = rtlsim_multi_io( + sim, + io_dict, + num_out_values, + trace_file=trace_file, + sname=sname, + liveness_threshold=pyverilate_get_liveness_threshold_cycles(), + ) + self.set_nodeattr("cycles_rtlsim", total_cycle_count) + + def generate_params(self, model, path): + """Function to generate parameters (i.e. weights and thresholds), + is member function of HLSCustomOp class but has to be filled + by every node.""" + pass + + @abstractmethod + def get_number_output_values(self): + """Function to get the number of expected output values, + is member function of HLSCustomOp class but has to be filled + by every node.""" + pass + + def get_input_datatype(self, ind=0): + """Returns FINN DataType of input stream ind.""" + raise Exception("get_input_datatype not implemented for this op") + + def get_output_datatype(self, ind=0): + """Returns FINN DataType of output stream ind.""" + raise Exception("get_output_datatype not implemented for this op") + + def get_normal_input_shape(self, ind=0): + """Returns normal input shape if implemented.""" + raise Exception("get_normal_input_shape not implemented for this op") + + def get_normal_output_shape(self, ind=0): + """Returns folded output shape if implemented.""" + raise Exception("get_normal_output_shape not implemented for this op") + + def get_folded_input_shape(self, ind=0): + """Returns folded input shape (according to synapse folding), if implemented.""" + raise Exception("get_folded_input_shape not implemented for this op") + + def get_folded_output_shape(self, ind=0): + """Returns folded output shape (according to neuron folding), if implemented.""" + raise Exception("get_folded_output_shape not implemented for this op") + + def get_instream_width(self, ind=0): + """Returns input stream width, if implemented.""" + raise Exception("get_instream_width not implemented for this op") + + def get_outstream_width(self, ind=0): + """Returns output stream width, if implemented.""" + raise Exception("get_outstream_width not implemented for this op") + + def get_instream_width_padded(self, ind=0): + """Returns input stream width padded to a multiple of 8. This is required + by the AXI Stream spec.""" + in_width = self.get_instream_width(ind=ind) + return roundup_to_integer_multiple(in_width, 8) + + def get_outstream_width_padded(self, ind=0): + """Returns output stream width padded to a multiple of 8. This is required + by the AXI Stream spec.""" + out_width = self.get_outstream_width(ind=ind) + return roundup_to_integer_multiple(out_width, 8) + + def derive_characteristic_fxns(self, period, override_rtlsim_dict=None): + """Return the unconstrained characteristic functions for this node.""" + # ensure rtlsim is ready + assert self.get_nodeattr("rtlsim_so") != "", "rtlsim not ready for " + self.onnx_node.name + if self.get_nodeattr("io_chrc_period") > 0: + warnings.warn("Skipping node %s: already has FIFO characteristic" % self.onnx_node.name) + return + exp_cycles = self.get_exp_cycles() + n_inps = np.prod(self.get_folded_input_shape()[:-1]) + n_outs = np.prod(self.get_folded_output_shape()[:-1]) + if exp_cycles == 0: + # try to come up with an optimistic estimate + exp_cycles = min(n_inps, n_outs) + assert ( + exp_cycles <= period + ), "Period %d too short to characterize %s : expects min %d cycles" % ( + period, + self.onnx_node.name, + exp_cycles, + ) + sim = self.get_rtlsim() + # signal name + sname = "_" + self.hls_sname() + "_" + if override_rtlsim_dict is not None: + io_dict = override_rtlsim_dict + else: + io_dict = { + "inputs": { + "in0": [0 for i in range(n_inps)], + }, + "outputs": {"out": []}, + } + + # extra dicts to keep track of cycle-by-cycle transaction behavior + # note that we restrict key names to filter out weight streams etc + txns_in = {key: [] for (key, value) in io_dict["inputs"].items() if "in" in key} + txns_out = {key: [] for (key, value) in io_dict["outputs"].items() if "out" in key} + + def monitor_txns(sim_obj): + for inp in txns_in: + in_ready = _read_signal(sim, inp + sname + "TREADY") == 1 + in_valid = _read_signal(sim, inp + sname + "TVALID") == 1 + if in_ready and in_valid: + txns_in[inp].append(1) + else: + txns_in[inp].append(0) + for outp in txns_out: + if ( + _read_signal(sim, outp + sname + "TREADY") == 1 + and _read_signal(sim, outp + sname + "TVALID") == 1 + ): + txns_out[outp].append(1) + else: + txns_out[outp].append(0) + + reset_rtlsim(sim) + total_cycle_count = rtlsim_multi_io( + sim, + io_dict, + n_outs, + sname=sname, + liveness_threshold=period, + hook_preclk=monitor_txns, + ) + assert ( + total_cycle_count <= period + ), """Total cycle count from rtl simulation is higher than + specified period, please set the period higher than {}""".format( + total_cycle_count + ) + self.set_nodeattr("io_chrc_period", period) + + def accumulate_char_fxn(chrc): + p = len(chrc) + ret = [] + for t in range(2 * p): + if t == 0: + ret.append(chrc[0]) + else: + ret.append(ret[-1] + chrc[t % p]) + return np.asarray(ret, dtype=np.int32) + + all_txns_in = np.empty((len(txns_in.keys()), 2 * period), dtype=np.int32) + all_txns_out = np.empty((len(txns_out.keys()), 2 * period), dtype=np.int32) + all_pad_in = [] + all_pad_out = [] + for in_idx, in_strm_nm in enumerate(txns_in.keys()): + txn_in = txns_in[in_strm_nm] + if len(txn_in) < period: + pad_in = period - len(txn_in) + txn_in += [0 for x in range(pad_in)] + txn_in = accumulate_char_fxn(txn_in) + all_txns_in[in_idx, :] = txn_in + all_pad_in.append(pad_in) + + for out_idx, out_strm_nm in enumerate(txns_out.keys()): + txn_out = txns_out[out_strm_nm] + if len(txn_out) < period: + pad_out = period - len(txn_out) + txn_out += [0 for x in range(pad_out)] + txn_out = accumulate_char_fxn(txn_out) + all_txns_out[out_idx, :] = txn_out + all_pad_out.append(pad_out) + + self.set_nodeattr("io_chrc_in", all_txns_in) + self.set_nodeattr("io_chrc_out", all_txns_out) + self.set_nodeattr("io_chrc_pads_in", all_pad_in) + self.set_nodeattr("io_chrc_pads_out", all_pad_out) diff --git a/src/finn/custom_op/fpgadataflow/rtl/__init__.py b/src/finn/custom_op/fpgadataflow/rtl/__init__.py new file mode 100644 index 0000000000..7c9b2eaf22 --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/rtl/__init__.py @@ -0,0 +1,35 @@ +# Copyright (C) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from finn.custom_op.fpgadataflow.rtl.fmpadding_rtl import FMPadding_rtl + +custom_op = dict() + +# make sure new HLSCustomOp subclasses are imported here so that they get +# registered and plug in correctly into the infrastructure +custom_op["FMPadding_rtl"] = FMPadding_rtl diff --git a/src/finn/custom_op/fpgadataflow/rtl/fmpadding_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/fmpadding_rtl.py new file mode 100644 index 0000000000..3c8a1ad777 --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/rtl/fmpadding_rtl.py @@ -0,0 +1,257 @@ +# Copyright (C) 2022, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import math +import numpy as np +import os +import shutil +from qonnx.util.basic import roundup_to_integer_multiple + +from finn.custom_op.fpgadataflow.fmpadding import FMPadding +from finn.custom_op.fpgadataflow.rtlbackend import RTLBackend +from finn.util.basic import get_rtlsim_trace_depth, make_build_dir +from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy + +try: + from pyverilator import PyVerilator +except ModuleNotFoundError: + PyVerilator = None + + +class FMPadding_rtl(FMPadding, RTLBackend): + """CustomOp wrapper for the finn-rtllib fmpadding_axi component + Supports adjusting the padding amount and spatial feature sizes at + runtime.""" + + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) + + def get_nodeattr_types(self): + my_attrs = { + # Enable reprogrammable implementation to change FM dimensions, + # stride, or dilation during runtime + "dynamic_mode": ("i", False, 0, {0, 1}), + # attribute to save top module name - not user configurable + "gen_top_module": ("s", False, ""), + } + my_attrs.update(FMPadding.get_nodeattr_types(self)) + my_attrs.update(RTLBackend.get_nodeattr_types(self)) + return my_attrs + + def get_verilog_top_module_intf_names(self): + # Overload default HLSCustomOp implementation to add axilite control IF + intf_names = super().get_verilog_top_module_intf_names() + if self.get_nodeattr("dynamic_mode"): + intf_names["axilite"] = ["s_axilite"] + return intf_names + + def execute_node(self, context, graph): + mode = self.get_nodeattr("exec_mode") + node = self.onnx_node + exp_ishape = self.get_normal_input_shape() + exp_oshape = self.get_normal_output_shape() + folded_ishape = self.get_folded_input_shape() + + if mode == "cppsim": + raise Exception("cppsim not possible for FMPadding_rtl, please set exec_mode to rtlsim") + elif mode == "rtlsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + + inp = context[node.input[0]] + assert str(inp.dtype) == "float32", "Input datatype is not float32" + assert ( + inp.shape == exp_ishape + ), """Input shape doesn't + match expected shape (1, ImgDim_h, ImgDim_w, NumChannels).""" + export_idt = self.get_input_datatype() + + reshaped_input = inp.reshape(folded_ishape) + np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input) + + sim = self.get_rtlsim() + nbits = self.get_instream_width() + rtlsim_inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) + super().reset_rtlsim(sim) + super().toggle_clk(sim) + rtlsim_output = self.rtlsim(sim, rtlsim_inp) + odt = export_idt + target_bits = odt.bitwidth() + packed_bits = self.get_outstream_width() + out_npy_path = "{}/output.npy".format(code_gen_dir) + out_shape = self.get_folded_output_shape() + rtlsim_output_to_npy(rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits) + # load and reshape output + output = np.load(out_npy_path) + output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) + context[node.output[0]] = output + + assert ( + context[node.output[0]].shape == exp_oshape + ), """Output shape doesn't match expected shape + (1, OutputDim_H, OutputDim_W, NumChannels).""" + + def get_template_values(self, ifm_dims, pads, chans, simd, idt): + dimY, dimX = ifm_dims + padT, padL, padB, padR = pads + y_counter_bits = int(math.ceil(math.log2(padT + dimY + padB + 1))) + x_counter_bits = int(math.ceil(math.log2(padL + dimX + padR + 1))) + topname = self.get_verilog_top_module_name() + stream_bits = idt.bitwidth() * simd + stream_bits = int(roundup_to_integer_multiple(stream_bits, 8)) + code_gen_dict = { + "XCOUNTER_BITS": int(x_counter_bits), + "YCOUNTER_BITS": int(y_counter_bits), + "NUM_CHANNELS": int(chans), + "SIMD": int(simd), + "ELEM_BITS": idt.bitwidth(), + "TOP_MODULE_NAME": topname, + "INIT_XON": int(padL), + "INIT_XOFF": int(padL + dimX), + "INIT_XEND": int(padL + dimX + padR - 1), + "INIT_YON": int(padT), + "INIT_YOFF": int(padT + dimY), + "INIT_YEND": int(padT + dimY + padB - 1), + "STREAM_BITS": int(stream_bits), + } + return code_gen_dict + + def get_dynamic_config(self, ifm_dims=None, pads=None): + """Returns a configuration dict to re-configure FM dimension and + padding amounts during runtime.""" + + if ifm_dims is None: + ifm_dims = self.get_nodeattr("ImgDim") + if pads is None: + pads = self.get_nodeattr("Padding") + chans = self.get_nodeattr("NumChannels") + simd = self.get_nodeattr("SIMD") + idt = self.get_input_datatype() + code_gen_dict = self.get_template_values(ifm_dims, pads, chans, simd, idt) + config = { + "XON": (0 * 4, (code_gen_dict["INIT_XON"])), + "XOFF": (1 * 4, (code_gen_dict["INIT_XOFF"])), + "XEND": (2 * 4, (code_gen_dict["INIT_XEND"])), + "YON": (3 * 4, (code_gen_dict["INIT_YON"])), + "YOFF": (4 * 4, (code_gen_dict["INIT_YOFF"])), + "YEND": (5 * 4, (code_gen_dict["INIT_YEND"])), + } + return config + + def generate_hdl(self): + rtlsrc = os.environ["FINN_ROOT"] + "/finn-rtllib/fmpadding/hdl" + template_path = rtlsrc + "/fmpadding_template.v" + dims = self.get_nodeattr("ImgDim") + pads = self.get_nodeattr("Padding") + chans = self.get_nodeattr("NumChannels") + simd = self.get_nodeattr("SIMD") + idt = self.get_input_datatype() + code_gen_dict = self.get_template_values(dims, pads, chans, simd, idt) + # save top module name so we can refer to it after this node has been renamed + # (e.g. by GiveUniqueNodeNames(prefix) during MakeZynqProject) + self.set_nodeattr("gen_top_module", self.get_verilog_top_module_name()) + + # apply code generation to templates + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + with open(template_path, "r") as f: + template = f.read() + for key_name in code_gen_dict: + key = "$%s$" % key_name + template = template.replace(key, str(code_gen_dict[key_name])) + + with open( + os.path.join(code_gen_dir, self.get_verilog_top_module_name() + ".v"), + "w", + ) as f: + f.write(template) + + sv_files = ["fmpadding_axi.sv", "fmpadding.sv", "axi2we.sv"] + for sv_file in sv_files: + shutil.copy(rtlsrc + "/" + sv_file, code_gen_dir) + # set ipgen_path and ip_path so that HLS-Synth transformation + # and stich_ip transformation do not complain + self.set_nodeattr("ipgen_path", code_gen_dir) + self.set_nodeattr("ip_path", code_gen_dir) + + def prepare_rtlsim(self): + """Creates a Verilator emulation library for the RTL code generated + for this node, sets the rtlsim_so attribute to its path and returns + a PyVerilator wrapper around it.""" + # Modified to use generated (System-)Verilog instead of HLS output products + + if PyVerilator is None: + raise ImportError("Installation of PyVerilator is required.") + + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + verilog_paths = [code_gen_dir] + verilog_files = [ + "fmpadding_axi.sv", + "fmpadding.sv", + "axi2we.sv", + self.get_nodeattr("gen_top_module") + ".v", + ] + + # build the Verilator emu library + sim = PyVerilator.build( + verilog_files, + build_dir=make_build_dir("pyverilator_" + self.onnx_node.name + "_"), + verilog_path=verilog_paths, + trace_depth=get_rtlsim_trace_depth(), + top_module_name=self.get_verilog_top_module_name(), + ) + # save generated lib filename in attribute + self.set_nodeattr("rtlsim_so", sim.lib._name) + return sim + + def code_generation_ipi(self): + """Constructs and returns the TCL for node instantiation in Vivado IPI.""" + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + + sourcefiles = [ + "fmpadding_axi.sv", + "fmpadding.sv", + "axi2we.sv", + self.get_nodeattr("gen_top_module") + ".v", + ] + + sourcefiles = [os.path.join(code_gen_dir, f) for f in sourcefiles] + + cmd = [] + for f in sourcefiles: + cmd += ["add_files -norecurse %s" % (f)] + cmd += [ + "create_bd_cell -type module -reference %s %s" + % (self.get_nodeattr("gen_top_module"), self.onnx_node.name) + ] + return cmd diff --git a/src/finn/custom_op/fpgadataflow/rtlbackend.py b/src/finn/custom_op/fpgadataflow/rtlbackend.py new file mode 100644 index 0000000000..4c1977852c --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/rtlbackend.py @@ -0,0 +1,61 @@ +# Copyright (c) 2020, Xilinx +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from abc import ABC, abstractmethod + + +class RTLBackend(ABC): + """RTLBackend class all custom ops that correspond to a module in finn-rtllib + are using functionality of. Contains different functions every RTL + custom node should have. Some as abstract methods, these have to be filled + when writing a new RTL custom op node.""" + + def get_nodeattr_types(self): + return {} + + @abstractmethod + def generate_hdl(self): + pass + + @abstractmethod + def prepare_rtlsim(self): + pass + + @abstractmethod + def code_generation_ipi(self): + pass + + def code_generation_ipgen(self, model, fpgapart, clk): + self.generate_hdl() + + # TODO: Implement alternative + def hls_sname(self): + """Get the naming convention used by Vitis HLS for stream signals + Example: the TDATA for a stream called "out" would be out_V_TDATA. + """ + return "V" diff --git a/src/finn/transformation/fpgadataflow/specialize_layers.py b/src/finn/transformation/fpgadataflow/specialize_layers.py new file mode 100644 index 0000000000..4c926ad9b1 --- /dev/null +++ b/src/finn/transformation/fpgadataflow/specialize_layers.py @@ -0,0 +1,71 @@ +# Copyright (C) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + +from onnx import helper +from qonnx.custom_op.registry import getCustomOp +from qonnx.transformation.base import Transformation +from qonnx.transformation.infer_datatypes import InferDataTypes +from qonnx.transformation.infer_shapes import InferShapes + + +class SpecializeFMPadding(Transformation): + """Convert FMPadding layer to FMPadding_hls or FMPadding_rtl.""" + + def apply(self, model): + graph = model.graph + node_ind = 0 + graph_modified = False + for node in graph.node: + node_ind += 1 + if node.op_type == "FMPadding": + pad_input = node.input[0] + pad_output = node.output[0] + pad_inst = getCustomOp(node) + impl_style = pad_inst.get_nodeattr("preferred_impl_style") + if impl_style == "": + impl_style = "rtl" + optype = node.op_type + "_" + impl_style + new_node = helper.make_node( + optype, + [pad_input], + [pad_output], + domain="finn.custom_op.fpgadataflow." + impl_style, + ) + # add all attributes + for attribute in node.attribute: + if attribute.name != "preferred_impl_style": + new_node.attribute.append(attribute) + graph.node.insert(node_ind, new_node) + # remove old nodes + graph.node.remove(node) + graph_modified = True + if graph_modified: + model = model.transform(InferShapes()) + model = model.transform(InferDataTypes()) + return (model, graph_modified) From 61e3de2c0a4afae6b32e8cfbf1ead7258141d260 Mon Sep 17 00:00:00 2001 From: auphelia Date: Thu, 16 Nov 2023 17:44:21 +0000 Subject: [PATCH 311/665] [AddStreams] Initial commit for AddStreams with new class hierarchy --- src/finn/custom_op/fpgadataflow/__init__.py | 2 + src/finn/custom_op/fpgadataflow/addstreams.py | 162 ++++++++++ .../custom_op/fpgadataflow/hls/__init__.py | 2 + .../fpgadataflow/hls/addstreams_hls.py | 281 ++++++++++++++++++ .../fpgadataflow/specialize_layers.py | 47 ++- 5 files changed, 493 insertions(+), 1 deletion(-) create mode 100644 src/finn/custom_op/fpgadataflow/addstreams.py create mode 100644 src/finn/custom_op/fpgadataflow/hls/addstreams_hls.py diff --git a/src/finn/custom_op/fpgadataflow/__init__.py b/src/finn/custom_op/fpgadataflow/__init__.py index ce05998fcc..c7bf09d0c2 100644 --- a/src/finn/custom_op/fpgadataflow/__init__.py +++ b/src/finn/custom_op/fpgadataflow/__init__.py @@ -27,6 +27,7 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from finn.custom_op.fpgadataflow.addstreams import AddStreams from finn.custom_op.fpgadataflow.addstreams_batch import AddStreams_Batch from finn.custom_op.fpgadataflow.channelwise_op_batch import ChannelwiseOp_Batch from finn.custom_op.fpgadataflow.checksum import CheckSum @@ -97,3 +98,4 @@ custom_op["FMPadding_rtl"] = FMPadding_rtl custom_op["FMPadding"] = FMPadding +custom_op["AddStreams"] = AddStreams diff --git a/src/finn/custom_op/fpgadataflow/addstreams.py b/src/finn/custom_op/fpgadataflow/addstreams.py new file mode 100644 index 0000000000..0f1336c6e1 --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/addstreams.py @@ -0,0 +1,162 @@ +# Copyright (C) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import numpy as np +import warnings +from qonnx.core.datatype import DataType + +from finn.custom_op.fpgadataflow.hwcustomop import HWCustomOp + + +class AddStreams(HWCustomOp): + """Abstraction layer for HW implementation of AddStreams.""" + + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) + + def get_nodeattr_types(self): + my_attrs = super().get_nodeattr_types() + my_attrs.update( + { + "NumChannels": ("i", True, ""), + "PE": ("i", True, ""), + # FINN DataTypes for inputs; output datatype inferred from input + "inputDataType": ("s", True, ""), + # number of input vectors, examples: + # [1] is a single vector (like a FC layer with batch=1) + # [4] is four vectors (like a FC layer with batch=4) + # [1, 4, 4] is four * four vectors (like a conv layer with batch=1) + "numInputVectors": ("ints", False, [1]), + "inFIFODepths": ("ints", False, [2, 2]), + } + ) + return my_attrs + + def get_normal_input_shape(self, ind=0): + ich = self.get_nodeattr("NumChannels") + vecs = list(self.get_nodeattr("numInputVectors")) + ishape = tuple(vecs + [ich]) + return ishape + + def get_folded_input_shape(self, ind=0): + ich = self.get_nodeattr("NumChannels") + pe = self.get_nodeattr("PE") + assert ich % pe == 0, "PE must divide NumChannels" + vecs = list(self.get_nodeattr("numInputVectors")) + ishape = tuple(vecs + [ich // pe, pe]) + return ishape + + def get_normal_output_shape(self, ind=0): + return self.get_normal_input_shape() + + def get_folded_output_shape(self, ind=0): + return self.get_folded_input_shape() + + def make_shape_compatible_op(self, model): + exp_ishape = self.get_normal_input_shape() + oshape = self.get_normal_output_shape() + ishape = tuple(model.get_tensor_shape(self.onnx_node.input[0])) + assert ishape == exp_ishape, "Unexpected input1 shape." + ishape = tuple(model.get_tensor_shape(self.onnx_node.input[1])) + assert ishape == exp_ishape, "Unexpected input2 shape." + return super().make_const_shape_op(oshape) + + def infer_node_datatype(self, model): + node = self.onnx_node + idt = model.get_tensor_datatype(node.input[0]) + if idt != self.get_input_datatype(): + warn_str = "inputDataType changing for %s: %s -> %s " % ( + node.name, + str(self.get_input_datatype()), + str(idt), + ) + warnings.warn(warn_str) + self.set_nodeattr("inputDataType", idt.name) + # enforce output data type (calculated based on idt) + odt = self.get_output_datatype() + model.set_tensor_datatype(self.onnx_node.output[0], odt) + + def verify_node(self): + pass + + def get_input_datatype(self, ind=0): + """Returns FINN DataType of input.""" + return DataType[self.get_nodeattr("inputDataType")] + + def get_output_datatype(self, ind=0): + """Returns FINN DataType of output.""" + # we need to set output datatype to the next larger int or uint + # enhancement: consider specifying w/ explicit outputDataType attribute + # to allow overflow and use the same idt if user wants + idt = DataType[self.get_nodeattr("inputDataType")] + if idt.signed(): + return DataType.get_smallest_possible(2 * idt.min()) + else: + return DataType.get_smallest_possible(2 * idt.max()) + + def get_instream_width(self, ind=0): + """Returns input stream width.""" + ibits = self.get_input_datatype().bitwidth() + pe = self.get_nodeattr("PE") + in_width = pe * ibits + return in_width + + def get_outstream_width(self, ind=0): + """Returns output stream width.""" + obits = self.get_output_datatype().bitwidth() + pe = self.get_nodeattr("PE") + out_width = pe * obits + return out_width + + def get_number_output_values(self): + return np.prod(self.get_folded_output_shape()[:-1]) + + def get_exp_cycles(self): + # Channels/PE * batch size * fmdim * fmdim + return np.prod(self.get_folded_output_shape()[:-1]) + + def execute_node(self, context, graph): + pass + + def get_verilog_top_module_intf_names(self): + intf_names = super().get_verilog_top_module_intf_names() + sname = self.hls_sname() + swidth = self.get_instream_width_padded() + intf_names["s_axis"] = [(x + "_" + sname, swidth) for x in ["in0", "in1"]] + return intf_names + + def derive_characteristic_fxns(self, period): + n_inps = np.prod(self.get_folded_input_shape()[:-1]) + io_dict = { + "inputs": { + "in0": [0 for i in range(n_inps)], + "in1": [0 for i in range(n_inps)], + }, + "outputs": {"out": []}, + } + super().derive_characteristic_fxns(period, override_rtlsim_dict=io_dict) diff --git a/src/finn/custom_op/fpgadataflow/hls/__init__.py b/src/finn/custom_op/fpgadataflow/hls/__init__.py index f381639fba..f978a8616c 100644 --- a/src/finn/custom_op/fpgadataflow/hls/__init__.py +++ b/src/finn/custom_op/fpgadataflow/hls/__init__.py @@ -26,6 +26,7 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from finn.custom_op.fpgadataflow.hls.addstreams_hls import AddStreams_hls from finn.custom_op.fpgadataflow.hls.fmpadding_hls import FMPadding_hls custom_op = dict() @@ -33,3 +34,4 @@ # make sure new HLSCustomOp subclasses are imported here so that they get # registered and plug in correctly into the infrastructure custom_op["FMPadding_hls"] = FMPadding_hls +custom_op["AddStreams_hls"] = AddStreams_hls diff --git a/src/finn/custom_op/fpgadataflow/hls/addstreams_hls.py b/src/finn/custom_op/fpgadataflow/hls/addstreams_hls.py new file mode 100644 index 0000000000..1a40970b77 --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/hls/addstreams_hls.py @@ -0,0 +1,281 @@ +# Copyright (C) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import numpy as np +import os + +from finn.custom_op.fpgadataflow.addstreams import AddStreams +from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend +from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy + + +class AddStreams_hls(AddStreams, HLSBackend): + """Class that corresponds to finn-hlslib AddStreams_Batch function.""" + + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) + + def get_nodeattr_types(self): + my_attrs = {} + my_attrs.update(AddStreams.get_nodeattr_types(self)) + my_attrs.update(HLSBackend.get_nodeattr_types(self)) + return my_attrs + + def verify_node(self): + info_messages = [] + # verify that "backend" is set to "fpgadataflow" + backend_value = self.get_nodeattr("backend") + if backend_value == "fpgadataflow": + info_messages.append("Attribute backend is set correctly") + else: + info_messages.append('Attribute backend should be set to "fpgadataflow"') + + # verify that all necessary attributes exist + try: + self.get_nodeattr("code_gen_dir_cppsim") + self.get_nodeattr("executable_path") + self.get_nodeattr("NumChannels") + self.get_nodeattr("PE") + self.get_nodeattr("inputDataType") + info_messages.append("All necessary attributes exist") + except Exception: + info_messages.append("""The required LabelSelect_Batch attributes do not exist.""") + + return info_messages + + def execute_node(self, context, graph): + mode = self.get_nodeattr("exec_mode") + node = self.onnx_node + exp_ishape = self.get_normal_input_shape() + exp_oshape = self.get_normal_output_shape() + folded_ishape = self.get_folded_input_shape() + + if mode == "cppsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + elif mode == "rtlsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + + inp = context[node.input[0]] + assert str(inp.dtype) == "float32", "Input datatype is not float32" + assert inp.shape == exp_ishape, """Input0 shape doesn't match expected shape .""" + export_idt = self.get_input_datatype() + # reshape input into folded form + inp = inp.reshape(folded_ishape) + # make copy before saving array + reshaped_input = inp.copy() + np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input) + + # exact same thing for input1 + inp = context[node.input[1]] + assert str(inp.dtype) == "float32", "Input datatype is not float32" + assert inp.shape == exp_ishape, """Input1 shape doesn't match expected shape .""" + export_idt = self.get_input_datatype() + # reshape input into folded form + inp = inp.reshape(folded_ishape) + # make copy before saving array + reshaped_input = inp.copy() + np.save(os.path.join(code_gen_dir, "input_1.npy"), reshaped_input) + + if mode == "cppsim": + # execute the precompiled model + super().exec_precompiled_singlenode_model() + # load output npy file + super().npy_to_dynamic_output(context) + assert ( + context[node.output[0]].shape == exp_oshape + ), "cppsim did not produce expected output shape" + elif mode == "rtlsim": + sim = self.get_rtlsim() + nbits = self.get_instream_width() + rtlsim_inp0 = npy_to_rtlsim_input( + "{}/input_0.npy".format(code_gen_dir), export_idt, nbits + ) + rtlsim_inp1 = npy_to_rtlsim_input( + "{}/input_1.npy".format(code_gen_dir), export_idt, nbits + ) + super().reset_rtlsim(sim) + super().toggle_clk(sim) + rtlsim_output = self.rtlsim(sim, rtlsim_inp0, rtlsim_inp1) + odt = self.get_output_datatype() + target_bits = odt.bitwidth() + packed_bits = self.get_outstream_width() + out_npy_path = "{}/output.npy".format(code_gen_dir) + out_shape = self.get_folded_output_shape() + rtlsim_output_to_npy( + rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits + ) + # load and reshape output + output = np.load(out_npy_path) + output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) + context[node.output[0]] = output + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + + assert ( + context[node.output[0]].shape == exp_oshape + ), """Output shape doesn't match expected shape.""" + + def global_includes(self): + self.code_gen_dict["$GLOBALS$"] = ['#include "streamtools.h"'] + + def defines(self, var): + self.code_gen_dict["$DEFINES$"] = [] + + def read_npy_data(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_input_datatype() + elem_bits = dtype.bitwidth() + packed_bits = self.get_instream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "float" + self.code_gen_dict["$READNPYDATA$"] = [] + npy_in = "%s/input_0.npy" % code_gen_dir + self.code_gen_dict["$READNPYDATA$"].append( + 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) + ) + npy_in = "%s/input_1.npy" % code_gen_dir + self.code_gen_dict["$READNPYDATA$"].append( + 'npy2apintstream<%s, %s, %d, %s>("%s", in1_%s);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) + ) + + def strm_decl(self): + self.code_gen_dict["$STREAMDECLARATIONS$"] = [] + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> in0_{} ("in0_{}");'.format( + self.get_instream_width(), self.hls_sname(), self.hls_sname() + ) + ) + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> in1_{} ("in1_{}");'.format( + self.get_instream_width(), self.hls_sname(), self.hls_sname() + ) + ) + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> out_{} ("out_{}");'.format( + self.get_outstream_width(), self.hls_sname(), self.hls_sname() + ) + ) + + def docompute(self): + hls_call = "AddStreams_Batch" + self.code_gen_dict["$DOCOMPUTE$"] = [ + """{}<{}, {}, {}, {}, {}> (in0_{}, in1_{}, out_{}, 1);""".format( + hls_call, + self.get_nodeattr("PE"), + self.get_input_datatype().get_hls_datatype_str(), + self.get_input_datatype().get_hls_datatype_str(), + self.get_output_datatype().get_hls_datatype_str(), + self.get_number_output_values(), + self.hls_sname(), + self.hls_sname(), + self.hls_sname(), + ) + ] + + def dataoutstrm(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_output_datatype() + elem_bits = dtype.bitwidth() + packed_bits = self.get_outstream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "float" + npy_out = "%s/output.npy" % code_gen_dir + oshape = self.get_folded_output_shape() + oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") + + self.code_gen_dict["$DATAOUTSTREAM$"] = [ + 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + self.hls_sname(), + oshape_cpp_str, + npy_out, + ) + ] + + def save_as_npy(self): + self.code_gen_dict["$SAVEASCNPY$"] = [] + + def blackboxfunction(self): + self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ + """void {}(hls::stream> &in0_{}, hls::stream> &in1_{}, + hls::stream> &out_{})""".format( + self.onnx_node.name, + self.get_nodeattr("PE") * self.get_input_datatype().bitwidth(), + self.hls_sname(), + self.get_nodeattr("PE") * self.get_input_datatype().bitwidth(), + self.hls_sname(), + self.get_nodeattr("PE") * self.get_output_datatype().bitwidth(), + self.hls_sname(), + ) + ] + + def pragmas(self): + self.code_gen_dict["$PRAGMAS$"] = [ + "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() + ] + self.code_gen_dict["$PRAGMAS$"].append( + "#pragma HLS INTERFACE axis port=in1_" + self.hls_sname() + ) + self.code_gen_dict["$PRAGMAS$"].append( + "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() + ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") diff --git a/src/finn/transformation/fpgadataflow/specialize_layers.py b/src/finn/transformation/fpgadataflow/specialize_layers.py index 4c926ad9b1..d45d1dc600 100644 --- a/src/finn/transformation/fpgadataflow/specialize_layers.py +++ b/src/finn/transformation/fpgadataflow/specialize_layers.py @@ -26,7 +26,7 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - +import warnings from onnx import helper from qonnx.custom_op.registry import getCustomOp from qonnx.transformation.base import Transformation @@ -69,3 +69,48 @@ def apply(self, model): model = model.transform(InferShapes()) model = model.transform(InferDataTypes()) return (model, graph_modified) + + +class SpecializeAddStreams(Transformation): + """Convert AddStreams layer to Addstreams_hls. There is no RTL variant of this node""" + + def apply(self, model): + graph = model.graph + node_ind = 0 + graph_modified = False + for node in graph.node: + node_ind += 1 + if node.op_type == "AddStreams": + add_input0 = node.input[0] + add_input1 = node.input[1] + add_output = node.output[0] + add_inst = getCustomOp(node) + impl_style = add_inst.get_nodeattr("preferred_impl_style") + if impl_style == "rtl": + warn_str = """There is no RTL variant of %s. Node %s will automatically be + set to HLS variant.""" % ( + node.op_type, + node.name, + ) + warnings.warn(warn_str) + if impl_style == "" or impl_style == "rtl": + impl_style = "hls" + optype = node.op_type + "_" + impl_style + new_node = helper.make_node( + optype, + [add_input0, add_input1], + [add_output], + domain="finn.custom_op.fpgadataflow." + impl_style, + ) + # add all attributes + for attribute in node.attribute: + if attribute.name != "preferred_impl_style": + new_node.attribute.append(attribute) + graph.node.insert(node_ind, new_node) + # remove old nodes + graph.node.remove(node) + graph_modified = True + if graph_modified: + model = model.transform(InferShapes()) + model = model.transform(InferDataTypes()) + return (model, graph_modified) From 7182be4346ea1680d63c711d5fd47719217b7f7d Mon Sep 17 00:00:00 2001 From: auphelia Date: Thu, 16 Nov 2023 17:46:01 +0000 Subject: [PATCH 312/665] [Tests] Update fmpadding and addstreams tests for new flow --- .../test_fpgadataflow_addstreams.py | 11 ++++++++--- .../fpgadataflow/test_fpgadataflow_fmpadding.py | 17 ++++++++++------- 2 files changed, 18 insertions(+), 10 deletions(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_addstreams.py b/tests/fpgadataflow/test_fpgadataflow_addstreams.py index 1ad2c26610..9b9c4a1e85 100644 --- a/tests/fpgadataflow/test_fpgadataflow_addstreams.py +++ b/tests/fpgadataflow/test_fpgadataflow_addstreams.py @@ -1,4 +1,4 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2023, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -44,6 +44,7 @@ from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.fpgadataflow.specialize_layers import SpecializeAddStreams def make_addstreams_modelwrapper(ch, pe, idt): @@ -52,7 +53,7 @@ def make_addstreams_modelwrapper(ch, pe, idt): outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, [1, ch]) addstreams_node = helper.make_node( - "AddStreams_Batch", + "AddStreams", ["inp1", "inp2"], ["outp"], domain="finn.custom_op.fpgadataflow", @@ -60,6 +61,7 @@ def make_addstreams_modelwrapper(ch, pe, idt): NumChannels=ch, PE=pe, inputDataType=idt.name, + preferred_impl_style="hls", ) graph = helper.make_graph( nodes=[addstreams_node], @@ -103,6 +105,9 @@ def test_fpgadataflow_addstreams(idt, ch, fold, exec_mode): x2 = gen_finn_dt_tensor(idt, (1, ch)) model = make_addstreams_modelwrapper(ch, pe, idt) + model.save("addstreams_hw.onnx") + model = model.transform(SpecializeAddStreams()) + model.save("addstreams_hls.onnx") if exec_mode == "cppsim": model = model.transform(PrepareCppSim()) @@ -130,7 +135,7 @@ def test_fpgadataflow_addstreams(idt, ch, fold, exec_mode): assert (y_produced == y_expected).all(), exec_mode + " failed" if exec_mode == "rtlsim": - node = model.get_nodes_by_op_type("AddStreams_Batch")[0] + node = model.get_nodes_by_op_type("AddStreams_hls")[0] inst = getCustomOp(node) cycles_rtlsim = inst.get_nodeattr("cycles_rtlsim") exp_cycles_dict = model.analysis(exp_cycles_per_layer) diff --git a/tests/fpgadataflow/test_fpgadataflow_fmpadding.py b/tests/fpgadataflow/test_fpgadataflow_fmpadding.py index c871811c5e..4a4c46f3c3 100644 --- a/tests/fpgadataflow/test_fpgadataflow_fmpadding.py +++ b/tests/fpgadataflow/test_fpgadataflow_fmpadding.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2020-2022, Xilinx, Inc. +# Copyright (C) 2023, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -46,6 +47,7 @@ from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.fpgadataflow.specialize_layers import SpecializeFMPadding from finn.util.basic import pynq_part_map test_pynq_board = os.getenv("PYNQ_BOARD", default="Pynq-Z1") @@ -53,7 +55,7 @@ target_clk_ns = 10 -def make_single_fmpadding_modelwrapper(optype, idim, padding, num_ch, simd, idt): +def make_single_fmpadding_modelwrapper(impl_style, idim, padding, num_ch, simd, idt): pad_h = padding[0] + padding[2] pad_w = padding[1] + padding[3] idim_h, idim_w = idim @@ -66,7 +68,7 @@ def make_single_fmpadding_modelwrapper(optype, idim, padding, num_ch, simd, idt) outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, [1, odim_h, odim_w, num_ch]) FMPadding = helper.make_node( - optype, + "FMPadding", ["inp"], ["outp"], domain="finn.custom_op.fpgadataflow", @@ -77,6 +79,7 @@ def make_single_fmpadding_modelwrapper(optype, idim, padding, num_ch, simd, idt) inputDataType=str(idt.name), numInputVectors=1, SIMD=simd, + preferred_impl_style=impl_style, ) graph = helper.make_graph( @@ -125,9 +128,8 @@ def test_fpgadataflow_fmpadding(idim, pad, num_ch, simd, idt, mode, impl_style): odim_h = idim_h + pad_h odim_w = idim_w + pad_w - optype = {"hls": "FMPadding_Batch", "rtl": "FMPadding_rtl"}[impl_style] - - model = make_single_fmpadding_modelwrapper(optype, idim, pad, num_ch, simd, idt) + model = make_single_fmpadding_modelwrapper(impl_style, idim, pad, num_ch, simd, idt) + model = model.transform(SpecializeFMPadding()) model = model.transform(InferShapes()) model = model.transform(SetExecMode(mode)) model = model.transform(GiveUniqueNodeNames()) @@ -148,7 +150,8 @@ def test_fpgadataflow_fmpadding(idim, pad, num_ch, simd, idt, mode, impl_style): assert (y_produced == y_expected).all() if mode == "rtlsim": - node = model.get_nodes_by_op_type(optype)[0] + op_type = "FMPadding_" + impl_style + node = model.get_nodes_by_op_type(op_type)[0] inst = getCustomOp(node) cycles_rtlsim = inst.get_nodeattr("cycles_rtlsim") exp_cycles_dict = model.analysis(exp_cycles_per_layer) From 8ef196009bf2c52cf05cfe7764830069fb8b3da9 Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 17 Nov 2023 11:02:34 +0000 Subject: [PATCH 313/665] [Deps] Update finn-experimental commit --- fetch-repos.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fetch-repos.sh b/fetch-repos.sh index 0d4a1bef34..c0c4557526 100755 --- a/fetch-repos.sh +++ b/fetch-repos.sh @@ -28,7 +28,7 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. QONNX_COMMIT="04e24583fb5c1895744801480db3ced8a5b6a914" -FINN_EXP_COMMIT="0aa7e1c44b20cf085b6fe42cff360f0a832afd2c" +FINN_EXP_COMMIT="30bcef80297e19f99f546582289b4511cce75a35" BREVITAS_COMMIT="9bb26bf2798de210a267d1e4aed4c20087e0e8a5" PYVERILATOR_COMMIT="766e457465f5c0dd315490d7b9cc5d74f9a76f4f" CNPY_COMMIT="4e8810b1a8637695171ed346ce68f6984e585ef4" From 88845109d97e8f0c47193748c5d712ba6f22a0fb Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 17 Nov 2023 11:03:40 +0000 Subject: [PATCH 314/665] [Floorplan] Fix incorrect break and indent --- src/finn/transformation/fpgadataflow/floorplan.py | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/floorplan.py b/src/finn/transformation/fpgadataflow/floorplan.py index d43aabcf55..336b3f80d0 100644 --- a/src/finn/transformation/fpgadataflow/floorplan.py +++ b/src/finn/transformation/fpgadataflow/floorplan.py @@ -170,12 +170,11 @@ def apply(self, model): else: partition_id = pre_inst.get_nodeattr("partition_id") node_inst.set_nodeattr("partition_id", partition_id) - break - else: - # no matching, new partition - node_inst.set_nodeattr("partition_id", partition_cnt) - partition_cnt += 1 + else: + # no matching, new partition + node_inst.set_nodeattr("partition_id", partition_cnt) + partition_cnt += 1 # save the updated floorplan floorplan = model.analysis(floorplan_params) From 297fa3dbaa327d4eeeb26f789e5312a8dd3511f4 Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 17 Nov 2023 11:13:14 +0000 Subject: [PATCH 315/665] [Deps] Update finn-experimental commit to main --- fetch-repos.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fetch-repos.sh b/fetch-repos.sh index c0c4557526..6e904b3959 100755 --- a/fetch-repos.sh +++ b/fetch-repos.sh @@ -28,7 +28,7 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. QONNX_COMMIT="04e24583fb5c1895744801480db3ced8a5b6a914" -FINN_EXP_COMMIT="30bcef80297e19f99f546582289b4511cce75a35" +FINN_EXP_COMMIT="de99347e936d51715f5356a1b6c64e37b91c23c2" BREVITAS_COMMIT="9bb26bf2798de210a267d1e4aed4c20087e0e8a5" PYVERILATOR_COMMIT="766e457465f5c0dd315490d7b9cc5d74f9a76f4f" CNPY_COMMIT="4e8810b1a8637695171ed346ce68f6984e585ef4" From 1a1e64834aa33dc8d2a8616dd666173e0b719537 Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 20 Nov 2023 15:08:09 +0000 Subject: [PATCH 316/665] [NB] Explicitly set input data type for cybersecurity example --- .../cybersecurity/1-train-mlp-with-brevitas.ipynb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/notebooks/end2end_example/cybersecurity/1-train-mlp-with-brevitas.ipynb b/notebooks/end2end_example/cybersecurity/1-train-mlp-with-brevitas.ipynb index 2885100512..7644173284 100644 --- a/notebooks/end2end_example/cybersecurity/1-train-mlp-with-brevitas.ipynb +++ b/notebooks/end2end_example/cybersecurity/1-train-mlp-with-brevitas.ipynb @@ -684,6 +684,7 @@ "from brevitas.export import export_qonnx\n", "from qonnx.util.cleanup import cleanup as qonnx_cleanup\n", "from qonnx.core.modelwrapper import ModelWrapper\n", + "from qonnx.core.datatype import DataType\n", "from finn.transformation.qonnx.convert_qonnx_to_finn import ConvertQONNXtoFINN\n", "\n", "ready_model_filename = model_dir + \"/cybsec-mlp-ready.onnx\"\n", @@ -708,6 +709,8 @@ "\n", "# ModelWrapper\n", "model = ModelWrapper(ready_model_filename)\n", + "# Setting the input datatype explicitly because it doesn't get derived from the export function\n", + "model.set_tensor_datatype(model.graph.input[0].name, DataType[\"BIPOLAR\"])\n", "model = model.transform(ConvertQONNXtoFINN())\n", "model.save(ready_model_filename)\n", "\n", From 4c80cf8ff633356f8732be7f08ab30f6089522e7 Mon Sep 17 00:00:00 2001 From: Felix Jentzsch Date: Mon, 20 Nov 2023 19:21:34 +0100 Subject: [PATCH 317/665] [RTL SWG] Support SIMD < C in window-parallel mode --- docs/finn/internals.rst | 9 ++- .../convolutioninputgenerator_rtl.py | 75 +++++++++++-------- ...est_fpgadataflow_convinputgenerator_rtl.py | 4 +- 3 files changed, 54 insertions(+), 34 deletions(-) diff --git a/docs/finn/internals.rst b/docs/finn/internals.rst index 652c94ac24..a3d18bed77 100644 --- a/docs/finn/internals.rst +++ b/docs/finn/internals.rst @@ -311,6 +311,13 @@ Depending on the amount of parallelism requested, one of two implementation styl - 1 - default - depthwise-agnostic + * - < C + - 1 + - 1 + - 1 + - K + - parallel + - depthwise only * - C - 1 - 1 @@ -343,4 +350,4 @@ The RTL SWG is supported by the basic automatic folding algorithm in FINN (:py:m **MVAU:** Although it is recommended to unfold SIMD first, SIMD and PE can be set independently. Full (and balanced) parallelism is achieved by using the SWG in parallel window mode and setting MVAU SIMD and PE to their maximum values (SIMD = MW = C_in * K, PE = MH = C_out). -**VVAU:** While the VVAU HLS component supports SIMD unfolding independently from PE, the RTL SWG requires full unfolding across the channel dimension (SIMD of the SWG = PE of the VVAU) before enabling window-parallelism. Unlike the MVAU, the VVAU can't accept datawidth-converted input from a fully-parallel SWG in this case due to the depthwise data layout. As a result, the VVAU should be unfolded by PE first (up to PE = C), followed by SIMD (up to SIMD = K). +**VVAU:** The VVAU component supports SIMD unfolding (up to SIMD = K) independently from PE unfolding (up to PE = C), but can't accept a datawidth-converted input from a fully-parallel SWG in case PE is not fully unfolded due to the depthwise data layout. Therefore, it is required to set SIMD of the SWG = PE of the VVAU when window-parallelism is enabled. In this scenario, VVAU SIMD < K is supported via an automatically inserted DWC. diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py index a55cdcc0be..92c368fd0b 100755 --- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py +++ b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py @@ -237,12 +237,11 @@ def get_buffer_depth(self): mmv_in = 1 mmv_out = 1 channel_factor = int(ifm_ch / simd) - - # compute minimal buffer length (assuming it holds 1 complete window) - buffer_min_size = ((k_h - 1) * dilation_h * w + (k_w - 1) * dilation_w + 1) * channel_factor - impl_style = self.select_impl_style() if impl_style == "default": + buffer_min_size = ( + (k_h - 1) * dilation_h * w + (k_w - 1) * dilation_w + 1 + ) * channel_factor # add additional buffer space in case of stride > 1 # this minimizes cycle count as it allows an earlier pre-load of inputs buffer_depth = ( @@ -257,6 +256,9 @@ def get_buffer_depth(self): ) ) elif impl_style == "parallel": + buffer_min_size = ( + (k_h - 1) * dilation_h * w + (k_w - 1) * dilation_w + ) * channel_factor + 1 buffer_depth = buffer_min_size + 1 return buffer_depth @@ -676,6 +678,7 @@ def prepare_codegen_parallel(self): dilation = self.get_nodeattr("Dilation") simd = self.get_nodeattr("SIMD") M = self.get_nodeattr("M") + depthwise = self.get_nodeattr("depthwise") k_h, k_w = k h, w = ifm_dim @@ -691,7 +694,7 @@ def prepare_codegen_parallel(self): channel_factor = int(ifm_ch / simd) # compute minimal buffer length (assuming it holds 1 complete window) - buffer_min_size = ((k_h - 1) * dilation_h * w + (k_w - 1) * dilation_w + 1) * channel_factor + buffer_min_size = ((k_h - 1) * dilation_h * w + (k_w - 1) * dilation_w) * channel_factor + 1 buffer_actual_size = self.get_buffer_depth() code_gen_dict["$BUF_ELEM_TOTAL$"] = [str(buffer_actual_size)] @@ -710,32 +713,32 @@ def prepare_codegen_parallel(self): ] # re-use default controller loop structure - code_gen_dict["$IS_DEPTHWISE$"] = ["0"] + code_gen_dict["$IS_DEPTHWISE$"] = ["1"] if depthwise else ["0"] loop_h_iterations = out_dim_h - loop_w_iterations = out_dim_w # now the innermost loop - loop_kh_iterations = 1 + loop_w_iterations = out_dim_w + loop_kh_iterations = channel_factor loop_kw_iterations = 1 loop_simd_iterations = 1 - if loop_w_iterations == 1: - code_gen_dict["$INNERMOST_STATE$"] = ["STATE_LOOP_H"] - loop_h_iterations -= 1 # -1 because state is initial state + if loop_kh_iterations == 1: + if loop_w_iterations == 1: + code_gen_dict["$INNERMOST_STATE$"] = ["STATE_LOOP_H"] + loop_h_iterations -= 1 # -1 because state is initial state + else: + code_gen_dict["$INNERMOST_STATE$"] = ["STATE_LOOP_W"] + loop_w_iterations -= 1 # -1 because state is initial state else: - code_gen_dict["$INNERMOST_STATE$"] = ["STATE_LOOP_W"] - loop_w_iterations -= 1 # -1 because state is initial state + code_gen_dict["$INNERMOST_STATE$"] = ["STATE_LOOP_KH"] + loop_kh_iterations -= 1 # -1 because state is initial state # set head and tail address increment values - addr_incr_end_window = -buffer_min_size + stride_w * channel_factor + 1 - addr_incr_end_row = ( - -buffer_min_size - + ((skip_columns + kernel_width) * channel_factor) # remaining line - + ((stride_h - 1) * w * channel_factor) # skip lines - + 1 - ) - - tail_incr_w = addr_incr_end_window + buffer_min_size - 1 - tail_incr_h = addr_incr_end_row + buffer_min_size - 1 - tail_incr_last_window = stride_w + tail_incr_w = (stride_w - 1) * channel_factor + 1 + tail_incr_h = ( + (skip_columns + (kernel_width - 1)) * channel_factor + 1 + ) + ( # remaining line + (stride_h - 1) * w * channel_factor + ) # skip lines + tail_incr_last_window = stride_w * channel_factor addr_incr_end_simd = 1 addr_incr_end_window_elem = 1 @@ -810,15 +813,21 @@ def prepare_codegen_parallel(self): for ky in range(k_h): reg_fifo = [] for kx in range(k_w): - reg_fifo.append(px_idx) - px_idx += 1 + for c in range(channel_factor): + if c < (channel_factor - 1): + if not (ky == 0 and kx == 0): + reg_fifo.append(-1) + px_idx += 1 + else: + reg_fifo.append(px_idx) + px_idx += 1 if kx < (k_w - 1): - reg_fifo.extend([-1] * (dilation_w - 1)) - px_idx += dilation_w - 1 + reg_fifo.extend([-1] * ((dilation_w - 1) * channel_factor)) + px_idx += (dilation_w - 1) * channel_factor reg_fifos.append(reg_fifo) if ky < (k_h - 1): - line_buffer_len = (w - kernel_width) + w * (dilation_h - 1) + line_buffer_len = ((w - kernel_width) + w * (dilation_h - 1)) * channel_factor bram_fifos_depth.append(line_buffer_len) px_idx += line_buffer_len @@ -926,6 +935,7 @@ def select_impl_style(self): """Selects implementation style based on folding configuration.""" simd = self.get_nodeattr("SIMD") M = self.get_nodeattr("M") + depthwise = self.get_nodeattr("depthwise") ifm_ch = self.get_nodeattr("IFMChannels") ifm_dim = self.get_nodeattr("IFMDim") stride = self.get_nodeattr("Stride") @@ -950,7 +960,6 @@ def select_impl_style(self): if self.get_nodeattr("parallel_window"): # mmv_in = M * 1 mmv_out = M * k_h * k_w - assert ifm_ch == simd, "Constraint violated: SIMD must be equal to IFMChannels" else: # mmv_in = 1 mmv_out = 1 @@ -959,7 +968,11 @@ def select_impl_style(self): # choose implementation style if mmv_out > 1 or (k_h == 1 and k_w == 1): impl_style = "parallel" - assert ifm_ch == simd, "Constraint violated: SIMD must be equal to IFMChannels" + if depthwise: + # allow SIMD < IFM_CH in depthwise mode (VVAU supports the resulting data layout) + assert ifm_ch % simd == 0, "Constraint violated: SIMD must divide IFMChannels" + else: + assert ifm_ch == simd, "Constraint violated: SIMD must be equal to IFMChannels" else: impl_style = "default" diff --git a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py index 53d7be0ebb..9b7e1d022c 100755 --- a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py +++ b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py @@ -196,8 +196,8 @@ def test_fpgadataflow_slidingwindow_rtl( pytest.skip("Not all combinations for stride > k edge case supported in default mode") if k_h == 1 and k_w == 1 and simd != ifm_ch: pytest.skip("1x1 Kernel only supported in parallel mode (SIMD=C)") - if parallel_window and simd != ifm_ch: - pytest.skip("Parallel window requires SIMD=C") + if parallel_window and simd != ifm_ch and not dw: + pytest.skip("Parallel window requires SIMD=C for non-depthwise case") ofm_dim_h = compute_conv_output_dim(ifm_dim_h, k_h, stride_h, 0, dilation_h) ofm_dim_w = compute_conv_output_dim(ifm_dim_w, k_w, stride_w, 0, dilation_w) From b89dd623f1d2d4997df2b4e826b80424d16c14b0 Mon Sep 17 00:00:00 2001 From: Felix Jentzsch Date: Tue, 21 Nov 2023 19:48:40 +0100 Subject: [PATCH 318/665] Apply to 1x1 kernel, simplify logic, fix edge cases --- finn-rtllib/swg/swg_template_parallel.sv | 14 +------- .../convolutioninputgenerator_rtl.py | 32 +++++++------------ ...est_fpgadataflow_convinputgenerator_rtl.py | 6 ++-- 3 files changed, 15 insertions(+), 37 deletions(-) diff --git a/finn-rtllib/swg/swg_template_parallel.sv b/finn-rtllib/swg/swg_template_parallel.sv index 83a525ff36..b92f27b2ca 100644 --- a/finn-rtllib/swg/swg_template_parallel.sv +++ b/finn-rtllib/swg/swg_template_parallel.sv @@ -136,7 +136,6 @@ module $TOP_MODULE_NAME$_impl #( // counters/address registers logic signed [$clog2(LAST_READ_ELEM+1)+1-1:0] Newest_buffered_elem = -1; logic [$clog2(LAST_READ_ELEM+1)+1-1:0] Current_elem = FIRST_WRITE_ELEM; - logic [$clog2(LAST_READ_ELEM+1)+1-1:0] First_elem_next_window = 0; // control registers/signals logic Writing_done = 0; @@ -146,13 +145,7 @@ module $TOP_MODULE_NAME$_impl #( uwire write_blocked = write_cmd && !out_V_V_TREADY && !Write_done; uwire reading_done = Newest_buffered_elem == LAST_READ_ELEM; - uwire read_cmd = - !reading_done && ( // if there is still an input element left to read - Writing_done || ( // if writing is done (e.g. for skipped rows at FM end due to stride) - $signed(((Newest_buffered_elem - ($signed(BUF_ELEM_TOTAL) - 1)))) < $signed(First_elem_next_window) && - $signed(((Newest_buffered_elem - ($signed(BUF_ELEM_TOTAL) - 1)))) < $signed(Current_elem) - ) // (over-)write to buffer if oldest buffered element will no longer be needed - ); + uwire read_cmd = !reading_done && (Writing_done || Newest_buffered_elem <= $signed(Current_elem)); uwire read_ok = read_cmd && in0_V_V_TVALID && !write_blocked; // includes waiting on W if W-only cycle: wait only on W no R/W to wait for @@ -186,7 +179,6 @@ module $TOP_MODULE_NAME$_impl #( if(!ap_rst_n) begin Newest_buffered_elem <= -1; Current_elem <= FIRST_WRITE_ELEM; - First_elem_next_window <= 0; Writing_done <= 0; end else begin @@ -199,14 +191,11 @@ module $TOP_MODULE_NAME$_impl #( // todo: allow for read overlapping between feature maps (i.e., reading first elements from next FM while still writing last window of current FM) Newest_buffered_elem <= -1; Current_elem <= FIRST_WRITE_ELEM; - First_elem_next_window <= 0; Writing_done <= 0; end end if (write_ok) begin - First_elem_next_window <= First_elem_next_window + tail_incr; - // check if this is the last write cycle (Writing_done will be true afterwards) if (Current_elem == LAST_WRITE_ELEM) begin Writing_done <= 1; @@ -215,7 +204,6 @@ module $TOP_MODULE_NAME$_impl #( // start processing of next FM if reading is done already, or completes in the same cycle Newest_buffered_elem <= -1; Current_elem <= FIRST_WRITE_ELEM; - First_elem_next_window <= 0; Writing_done <= 0; end end diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py index 92c368fd0b..734f75a973 100755 --- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py +++ b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py @@ -678,7 +678,6 @@ def prepare_codegen_parallel(self): dilation = self.get_nodeattr("Dilation") simd = self.get_nodeattr("SIMD") M = self.get_nodeattr("M") - depthwise = self.get_nodeattr("depthwise") k_h, k_w = k h, w = ifm_dim @@ -713,7 +712,6 @@ def prepare_codegen_parallel(self): ] # re-use default controller loop structure - code_gen_dict["$IS_DEPTHWISE$"] = ["1"] if depthwise else ["0"] loop_h_iterations = out_dim_h loop_w_iterations = out_dim_w loop_kh_iterations = channel_factor @@ -731,20 +729,14 @@ def prepare_codegen_parallel(self): code_gen_dict["$INNERMOST_STATE$"] = ["STATE_LOOP_KH"] loop_kh_iterations -= 1 # -1 because state is initial state - # set head and tail address increment values - tail_incr_w = (stride_w - 1) * channel_factor + 1 - tail_incr_h = ( - (skip_columns + (kernel_width - 1)) * channel_factor + 1 - ) + ( # remaining line - (stride_h - 1) * w * channel_factor - ) # skip lines - tail_incr_last_window = stride_w * channel_factor - + # set head address increment values addr_incr_end_simd = 1 addr_incr_end_window_elem = 1 addr_incr_end_window_row = 1 - addr_incr_end_window = tail_incr_w - addr_incr_end_row = tail_incr_h + addr_incr_end_window = (stride_w - 1) * channel_factor + 1 + addr_incr_end_row = ((skip_columns + (kernel_width - 1)) * channel_factor + 1) + ( + (stride_h - 1) * w * channel_factor + ) # add init value for CURRENT_ELEM counter = last elem of first window code_gen_dict["$FIRST_WRITE_ELEM$"] = [str(buffer_min_size - 1)] @@ -775,9 +767,6 @@ def prepare_codegen_parallel(self): abs(addr_incr_end_window_row) + 1, abs(addr_incr_end_window) + 1, abs(addr_incr_end_row) + 1, - abs(tail_incr_w) + 1, - abs(tail_incr_h) + 1, - abs(tail_incr_last_window) + 1, ) ) ) @@ -787,9 +776,11 @@ def prepare_codegen_parallel(self): code_gen_dict["$HEAD_INCR_KH$"] = [str(addr_incr_end_window_row)] code_gen_dict["$HEAD_INCR_W$"] = [str(addr_incr_end_window)] code_gen_dict["$HEAD_INCR_H$"] = [str(addr_incr_end_row)] - code_gen_dict["$TAIL_INCR_W$"] = [str(tail_incr_w)] - code_gen_dict["$TAIL_INCR_H$"] = [str(tail_incr_h)] - code_gen_dict["$TAIL_INCR_LAST$"] = [str(tail_incr_last_window)] + # not used, set to zero: + code_gen_dict["$TAIL_INCR_W$"] = ["0"] + code_gen_dict["$TAIL_INCR_H$"] = ["0"] + code_gen_dict["$TAIL_INCR_LAST$"] = ["0"] + code_gen_dict["$IS_DEPTHWISE$"] = ["0"] code_gen_dict["$SIMD$"] = [str(simd)] code_gen_dict["$MMV_IN$"] = [str(mmv_in)] @@ -968,8 +959,9 @@ def select_impl_style(self): # choose implementation style if mmv_out > 1 or (k_h == 1 and k_w == 1): impl_style = "parallel" - if depthwise: + if depthwise or (k_h == 1 and k_w == 1): # allow SIMD < IFM_CH in depthwise mode (VVAU supports the resulting data layout) + # also allowed for 1x1 kernel since depthwise and non-depthwise are equivalent assert ifm_ch % simd == 0, "Constraint violated: SIMD must divide IFMChannels" else: assert ifm_ch == simd, "Constraint violated: SIMD must be equal to IFMChannels" diff --git a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py index 9b7e1d022c..62b7abe536 100755 --- a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py +++ b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py @@ -192,11 +192,9 @@ def test_fpgadataflow_slidingwindow_rtl( pytest.skip("Illegal convolution configuration: kernel or stride > FM dimension") if (k_h == 1 and dilation_h != 1) or (k_w == 1 and dilation_w != 1): pytest.skip("Illegal convolution configuration: dilation for unitary kernel dim") - if (stride_h > k_h) or (stride_w > k_w) and not parallel_window: + if ((stride_h > k_h) or (stride_w > k_w)) and not (parallel_window or (k_h == 1 and k_w == 1)): pytest.skip("Not all combinations for stride > k edge case supported in default mode") - if k_h == 1 and k_w == 1 and simd != ifm_ch: - pytest.skip("1x1 Kernel only supported in parallel mode (SIMD=C)") - if parallel_window and simd != ifm_ch and not dw: + if parallel_window and simd != ifm_ch and not (dw or (k_h == 1 and k_w == 1)): pytest.skip("Parallel window requires SIMD=C for non-depthwise case") ofm_dim_h = compute_conv_output_dim(ifm_dim_h, k_h, stride_h, 0, dilation_h) From 2af8d3a6fef5ceec2319052df398f15d7732978f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thomas=20B=2E=20Preu=C3=9Fer?= Date: Tue, 21 Nov 2023 20:20:58 +0000 Subject: [PATCH 319/665] AXI stream data width converter for integer ratios. --- finn-rtllib/dwc/hdl/dwc_axi.sv | 158 ++++++++++++++++++++++++ finn-rtllib/dwc/sim/dwc_axi_tb.sv | 195 ++++++++++++++++++++++++++++++ 2 files changed, 353 insertions(+) create mode 100644 finn-rtllib/dwc/hdl/dwc_axi.sv create mode 100644 finn-rtllib/dwc/sim/dwc_axi_tb.sv diff --git a/finn-rtllib/dwc/hdl/dwc_axi.sv b/finn-rtllib/dwc/hdl/dwc_axi.sv new file mode 100644 index 0000000000..ea52b9ed24 --- /dev/null +++ b/finn-rtllib/dwc/hdl/dwc_axi.sv @@ -0,0 +1,158 @@ +/****************************************************************************** + * Copyright (C) 2023, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * @brief AXI Stream Data Width Converter. + * @author Thomas B. Preußer + *****************************************************************************/ +module dwc_axi #( + int unsigned IBITS, + int unsigned OBITS +)( + //- Global Control ------------------ + input logic clk, + input logic rst, + + //- AXI Stream - Input -------------- + output logic s_axis_tready, + input logic s_axis_tvalid, + input logic [IBITS-1:0] s_axis_tdata, + + //- AXI Stream - Output ------------- + input logic m_axis_tready, + output logic m_axis_tvalid, + output logic [OBITS-1:0] m_axis_tdata +); + + if(IBITS == OBITS) begin : genNoop + assign s_axis_tready = m_axis_tready; + assign m_axis_tvalid = s_axis_tvalid; + assign m_axis_tdata = s_axis_tdata; + end : genNoop + else if(IBITS < OBITS) begin : genUp + + // Sanity Checking: integer upscaling + initial begin + if(OBITS % IBITS) begin + $error("Output width %0d is not a multiple of input width %0d.", OBITS, IBITS); + $finish; + end + end + + // Parallelizing Shift Register A and Sidestep Buffer B on Input Path + localparam int unsigned K = OBITS / IBITS; + typedef logic [IBITS-1:0] dat_t; + dat_t [K-1:0] ADat = 'x; + logic [$clog2(K):0] ACnt = K-1; // (empty) K-1, ..., 0, -1 (full/valid) + dat_t BDat = 'x; + logic BRdy = 1; + always_ff @(posedge clk) begin + if(rst) begin + ADat <= 'x; + ACnt <= K-1; + BDat <= 'x; + BRdy <= 1; + end + else begin + automatic type(ACnt) acnt = (m_axis_tvalid && m_axis_tready)? K-1 : ACnt; + automatic logic rdy = !m_axis_tvalid || m_axis_tready; + if((s_axis_tvalid || !BRdy) && rdy) begin + ADat <= { BRdy? s_axis_tdata : BDat, ADat[K-1:1] }; + acnt--; + end + ACnt <= acnt; + + if(BRdy) BDat <= s_axis_tdata; + BRdy <= rdy || (BRdy && !s_axis_tvalid); + end + end + + // Output Assignments + assign s_axis_tready = BRdy; + assign m_axis_tvalid = ACnt[$left(ACnt)]; + assign m_axis_tdata = ADat; + + end : genUp + else begin : genDown + + // Sanity Checking: integer downscaling + initial begin + if(IBITS % OBITS) begin + $error("Input width %0d is not a multiple of output width %0d.", IBITS, OBITS); + $finish; + end + end + + // Serializing Shift Register A and Sidestep Buffer B on Output Path + localparam int unsigned K = IBITS / OBITS; + typedef logic [OBITS-1:0] dat_t; + dat_t [ K-1:0] ADat = 'x; + logic [$clog2(K):0] ACnt = 1; // (full) -K+1, ..., -1, 0, 1 (empty/not valid) + dat_t BDat = 'x; + logic BRdy = 1; + dat_t CDat = 'x; + logic CVld = 0; + always_ff @(posedge clk) begin + if(rst) begin + ADat <= 'x; + ACnt <= 1; + BDat <= 'x; + BRdy <= 1; + CDat <= 'x; + CVld <= 0; + end + else begin + automatic type(ACnt) acnt = ACnt; + automatic logic ainc = 0; + if(s_axis_tready) begin + ADat <= s_axis_tdata; + acnt = s_axis_tvalid? -K+1 : 1; + end + else if(BRdy) begin + ADat <= { {OBITS{1'bx}}, ADat[K-1:1] }; + ainc = BRdy; + end; + ACnt <= acnt + ainc; + + if(BRdy) BDat <= ADat[0]; + BRdy <= !CVld || m_axis_tready || (BRdy && !ACnt[$left(ACnt)] && ACnt[0]); + + if(!CVld || m_axis_tready) CDat <= BRdy? ADat[0] : BDat; + CVld <= (CVld && !m_axis_tready) || !BRdy || ACnt[$left(ACnt)] || !ACnt[0]; + end + end + + // Output Assignments + assign s_axis_tready = BRdy && !ACnt[$left(ACnt)]; + assign m_axis_tvalid = CVld; + assign m_axis_tdata = CDat; + + end : genDown + +endmodule : dwc_axi diff --git a/finn-rtllib/dwc/sim/dwc_axi_tb.sv b/finn-rtllib/dwc/sim/dwc_axi_tb.sv new file mode 100644 index 0000000000..6bc3249685 --- /dev/null +++ b/finn-rtllib/dwc/sim/dwc_axi_tb.sv @@ -0,0 +1,195 @@ +/****************************************************************************** + * Copyright (C) 2023, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * @brief Testbench for AXI Stream Data Width Converter. + * @author Thomas B. Preußer + *****************************************************************************/ +module dwc_axi_tb; + + localparam int unsigned DBITS = 4; + localparam int unsigned K = 3; + typedef logic [DBITS-1:0] dat_t; + + // Global Control + logic clk = 0; + always #5ns clk = !clk; + logic rst = 1; + initial begin + repeat(8) @(posedge clk); + rst <= 0; + end + + if(1) begin : blkUp + localparam int unsigned IBITS = DBITS; + localparam int unsigned OBITS = K * DBITS; + + //- AXI Stream - Input -------------- + uwire s_axis_tready; + logic s_axis_tvalid; + dat_t s_axis_tdata; + + //- AXI Stream - Output ------------- + logic m_axis_tready; + uwire m_axis_tvalid; + dat_t [K-1:0] m_axis_tdata; + + dwc_axi #(.IBITS(IBITS), .OBITS(OBITS)) dut ( + .clk, .rst, + .s_axis_tready, .s_axis_tvalid, .s_axis_tdata, + .m_axis_tready, .m_axis_tvalid, .m_axis_tdata + ); + + // Stimulus: Feed + dat_t Q[$]; + initial begin + s_axis_tvalid = 0; + s_axis_tdata = 'x; + @(posedge clk iff !rst); + + repeat(57600) begin + automatic type(s_axis_tdata) dat; + std::randomize(dat); + + while($urandom()%7 < 2) @(posedge clk); + + s_axis_tvalid <= 1; + s_axis_tdata <= dat; + @(posedge clk iff s_axis_tready); + Q.push_back(dat); + + s_axis_tvalid <= 0; + s_axis_tdata <= 'x; + end + + repeat(16) @(posedge clk); + $finish; + end + + // Output Sink + initial begin + m_axis_tready = 0; + @(posedge clk iff !rst); + + forever begin + automatic dat_t [K-1:0] dat; + + while($urandom()%9 < 1) @(posedge clk); + + m_axis_tready <= 1; + @(posedge clk iff m_axis_tvalid); + assert(Q.size >= K) else begin + $error("Spurious output."); + $stop; + end + for(int unsigned i = 0; i < K; i++) dat[i] = Q.pop_front(); + assert(m_axis_tdata == dat) else begin + $error("Output mismatch."); + $stop; + end + + m_axis_tready <= 0; + end + end + end : blkUp + + if(1) begin : blkDown + localparam int unsigned IBITS = K * DBITS; + localparam int unsigned OBITS = DBITS; + + //- AXI Stream - Input -------------- + uwire s_axis_tready; + logic s_axis_tvalid; + dat_t [K-1:0] s_axis_tdata; + + //- AXI Stream - Output ------------- + logic m_axis_tready; + uwire m_axis_tvalid; + dat_t m_axis_tdata; + + dwc_axi #(.IBITS(IBITS), .OBITS(OBITS)) dut ( + .clk, .rst, + .s_axis_tready, .s_axis_tvalid, .s_axis_tdata, + .m_axis_tready, .m_axis_tvalid, .m_axis_tdata + ); + + // Stimulus: Feed + dat_t Q[$]; + initial begin + s_axis_tvalid = 0; + s_axis_tdata = 'x; + @(posedge clk iff !rst); + + repeat(57600) begin + automatic dat_t [K-1:0] dat; + std::randomize(dat); + + while($urandom()%7 < 2) @(posedge clk); + + s_axis_tvalid <= 1; + s_axis_tdata <= dat; + @(posedge clk iff s_axis_tready); + for(int unsigned i = 0; i < K; i++) Q.push_back(dat[i]); + + s_axis_tvalid <= 0; + s_axis_tdata <= 'x; + end + + repeat(16) @(posedge clk); + $finish; + end + + // Output Sink + initial begin + m_axis_tready = 0; + @(posedge clk iff !rst); + + forever begin + automatic dat_t dat; + + while($urandom()%9 < 1) @(posedge clk); + + m_axis_tready <= 1; + @(posedge clk iff m_axis_tvalid); + assert(Q.size) else begin + $error("Spurious output."); + $stop; + end + dat = Q.pop_front(); + assert(m_axis_tdata == dat) else begin + $error("Output mismatch: 0x%0x instead of 0x%0x", m_axis_tdata, dat); + $stop; + end + + m_axis_tready <= 0; + end + end + end : blkDown + +endmodule : dwc_axi_tb From a25f5d469668fec173db6c212324a7d49e0247d2 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 22 Nov 2023 11:32:07 +0000 Subject: [PATCH 320/665] [rtllib] Rename clk, rst in dwc module and first draft of verilog wrapper --- finn-rtllib/dwc/hdl/dwc_axi.sv | 12 +++--- finn-rtllib/dwc/hdl/dwc_template.v | 66 ++++++++++++++++++++++++++++++ 2 files changed, 72 insertions(+), 6 deletions(-) create mode 100644 finn-rtllib/dwc/hdl/dwc_template.v diff --git a/finn-rtllib/dwc/hdl/dwc_axi.sv b/finn-rtllib/dwc/hdl/dwc_axi.sv index ea52b9ed24..5381b57ac4 100644 --- a/finn-rtllib/dwc/hdl/dwc_axi.sv +++ b/finn-rtllib/dwc/hdl/dwc_axi.sv @@ -36,8 +36,8 @@ module dwc_axi #( int unsigned OBITS )( //- Global Control ------------------ - input logic clk, - input logic rst, + input logic ap_clk, + input logic ap_rst_n, //- AXI Stream - Input -------------- output logic s_axis_tready, @@ -72,8 +72,8 @@ module dwc_axi #( logic [$clog2(K):0] ACnt = K-1; // (empty) K-1, ..., 0, -1 (full/valid) dat_t BDat = 'x; logic BRdy = 1; - always_ff @(posedge clk) begin - if(rst) begin + always_ff @(posedge ap_clk) begin + if(ap_rst_n) begin ADat <= 'x; ACnt <= K-1; BDat <= 'x; @@ -118,8 +118,8 @@ module dwc_axi #( logic BRdy = 1; dat_t CDat = 'x; logic CVld = 0; - always_ff @(posedge clk) begin - if(rst) begin + always_ff @(posedge ap_clk) begin + if(ap_rst_n) begin ADat <= 'x; ACnt <= 1; BDat <= 'x; diff --git a/finn-rtllib/dwc/hdl/dwc_template.v b/finn-rtllib/dwc/hdl/dwc_template.v new file mode 100644 index 0000000000..27f6c70dff --- /dev/null +++ b/finn-rtllib/dwc/hdl/dwc_template.v @@ -0,0 +1,66 @@ +/****************************************************************************** + * Copyright (C) 2023, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *****************************************************************************/ + +module $TOP_MODULE_NAME$( +//- Global Control ------------------ +(* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out_V" *) +input ap_clk, +input ap_rst_n, + +//- AXI Stream - Input -------------- +output in0_V_TREADY, +input in0_V_TVALID, +input [$IBITS$-1:0] in0_V_TDATA, + +//- AXI Stream - Output ------------- +input out_V_TREADY, +output out_V_TVALID, +output [$OBITS$-1:0] out_V_TDATA +); + + +dwc_axi #( +.IBITS($IBITS$), +.OBITS($OBITS$) +) +$TOP_MODULE_NAME$_impl +( + .ap_clk(ap_clk), + .ap_rst_n(ap_rst_n), + .s_axis_tready(in0_V_TREADY), + .s_axis_tvalid(in0_V_TVALID), + .s_axis_tdata(in0_V_TDATA), + .m_axis_tready(out_V_TREADY), + .m_axis_tvalid(out_V_TVALID), + .m_axis_tdata(out_V_TDATA) +); + +endmodule From 048317a70cd782ad34148bddac94752bb88ecf1e Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 22 Nov 2023 11:34:02 +0000 Subject: [PATCH 321/665] [CustomOp] Initial draft of custom op for dwc rtl component --- src/finn/custom_op/fpgadataflow/__init__.py | 4 + .../streamingdatawidthconverter_rtl.py | 359 ++++++++++++++++++ 2 files changed, 363 insertions(+) create mode 100644 src/finn/custom_op/fpgadataflow/streamingdatawidthconverter_rtl.py diff --git a/src/finn/custom_op/fpgadataflow/__init__.py b/src/finn/custom_op/fpgadataflow/__init__.py index 56d4230a3a..c120667d81 100644 --- a/src/finn/custom_op/fpgadataflow/__init__.py +++ b/src/finn/custom_op/fpgadataflow/__init__.py @@ -56,6 +56,9 @@ from finn.custom_op.fpgadataflow.streamingdatawidthconverter_batch import ( StreamingDataWidthConverter_Batch, ) +from finn.custom_op.fpgadataflow.streamingdatawidthconverter_rtl import ( + StreamingDataWidthConverter_rtl, +) from finn.custom_op.fpgadataflow.streamingfifo import StreamingFIFO from finn.custom_op.fpgadataflow.streamingmaxpool_batch import StreamingMaxPool_Batch from finn.custom_op.fpgadataflow.thresholding_batch import Thresholding_Batch @@ -75,6 +78,7 @@ custom_op["ConvolutionInputGenerator_rtl"] = ConvolutionInputGenerator_rtl custom_op["TLastMarker"] = TLastMarker custom_op["StreamingDataWidthConverter_Batch"] = StreamingDataWidthConverter_Batch +custom_op["StreamingDataWidthConverter_rtl"] = StreamingDataWidthConverter_rtl custom_op["StreamingFIFO"] = StreamingFIFO custom_op["GlobalAccPool_Batch"] = GlobalAccPool_Batch custom_op["Pool_Batch"] = Pool_Batch diff --git a/src/finn/custom_op/fpgadataflow/streamingdatawidthconverter_rtl.py b/src/finn/custom_op/fpgadataflow/streamingdatawidthconverter_rtl.py new file mode 100644 index 0000000000..e89bfd2526 --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/streamingdatawidthconverter_rtl.py @@ -0,0 +1,359 @@ +# Copyright (C) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import numpy as np +import os +import shutil +import warnings +from qonnx.core.datatype import DataType + +from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp +from finn.util.basic import get_rtlsim_trace_depth, make_build_dir +from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy + +try: + from pyverilator import PyVerilator +except ModuleNotFoundError: + PyVerilator = None + + +class StreamingDataWidthConverter_rtl(HLSCustomOp): + """Class that corresponds to finn-rtllib datawidth converter + module.""" + + def get_nodeattr_types(self): + my_attrs = { + # shape of input/output tensors + "shape": ("ints", True, []), + # bit width of input and output streams + "inWidth": ("i", True, 0), + "outWidth": ("i", True, 0), + # FINN DataTypes for inputs/outputs + "dataType": ("s", True, ""), + # attribute to save top module name - not user configurable + "gen_top_module": ("s", False, ""), + } + my_attrs.update(super().get_nodeattr_types()) + return my_attrs + + def get_input_datatype(self, ind=0): + """Returns FINN DataType of input.""" + return DataType[self.get_nodeattr("dataType")] + + def get_output_datatype(self, ind=0): + """Returns FINN DataType of output.""" + return DataType[self.get_nodeattr("dataType")] + + def get_normal_input_shape(self, ind=0): + ishape = self.get_nodeattr("shape") + return ishape + + def get_normal_output_shape(self, ind=0): + oshape = self.get_nodeattr("shape") + return oshape + + def check_divisible_iowidths(self): + iwidth = self.get_nodeattr("inWidth") + owidth = self.get_nodeattr("outWidth") + # the rtl module only supports + # stream widths that are divisible by + # integer width ratios + iwidth_d = iwidth % owidth == 0 + owidth_d = owidth % iwidth == 0 + assert ( + iwidth_d or owidth_d + ), """RTL implementation of DWC requires + stream widths that are integer width ratios + from each other. Input width is set to %s + and output width is set to %s """ % ( + iwidth, + owidth, + ) + + def get_folded_input_shape(self, ind=0): + self.check_divisible_iowidths() + iwidth = self.get_nodeattr("inWidth") + ishape = self.get_normal_input_shape() + dummy_t = np.random.randn(*ishape) + ibits = self.get_input_datatype().bitwidth() + assert ( + iwidth % ibits == 0 + ), """DWC input width must be divisible by + input element bitwidth""" + ielems = int(iwidth // ibits) + ichannels = ishape[-1] + new_shape = [] + for i in ishape[:-1]: + new_shape.append(i) + new_shape.append(int(ichannels // ielems)) + new_shape.append(ielems) + dummy_t = dummy_t.reshape(new_shape) + return dummy_t.shape + + def get_folded_output_shape(self, ind=0): + self.check_divisible_iowidths() + owidth = self.get_nodeattr("outWidth") + oshape = self.get_normal_output_shape() + dummy_t = np.random.randn(*oshape) + obits = self.get_output_datatype().bitwidth() + assert ( + owidth % obits == 0 + ), """DWC output width must be divisible by + input element bitwidth""" + oelems = int(owidth // obits) + ochannels = oshape[-1] + new_shape = [] + for i in oshape[:-1]: + new_shape.append(i) + new_shape.append(int(ochannels // oelems)) + new_shape.append(oelems) + dummy_t = dummy_t.reshape(new_shape) + + return dummy_t.shape + + def get_number_output_values(self): + folded_oshape = self.get_folded_output_shape() + return np.prod(folded_oshape[:-1]) + + def get_instream_width(self, ind=0): + in_width = self.get_nodeattr("inWidth") + return in_width + + def get_outstream_width(self, ind=0): + out_width = self.get_nodeattr("outWidth") + return out_width + + def make_shape_compatible_op(self, model): + exp_ishape = self.get_normal_input_shape() + oshape = self.get_normal_output_shape() + ishape = tuple(model.get_tensor_shape(self.onnx_node.input[0])) + assert ishape == tuple(exp_ishape), "Unexpect input shape for StreamingDWC." + return super().make_const_shape_op(oshape) + + def infer_node_datatype(self, model): + node = self.onnx_node + idt = model.get_tensor_datatype(node.input[0]) + if idt != self.get_input_datatype(): + warn_str = "inputDataType changing for %s: %s -> %s " % ( + node.name, + str(self.get_input_datatype()), + str(idt), + ) + warnings.warn(warn_str) + self.set_nodeattr("dataType", idt.name) + # data type stays the same + model.set_tensor_datatype(node.output[0], idt) + + def verify_node(self): + pass + + def execute_node(self, context, graph): + mode = self.get_nodeattr("exec_mode") + node = self.onnx_node + exp_ishape = self.get_normal_input_shape() + exp_oshape = self.get_normal_output_shape() + folded_ishape = self.get_folded_input_shape() + + if mode == "cppsim": + raise Exception( + """cppsim not possible for StreamingDataWidthConverter_rtl, + please set exec_mode to rtlsim""" + ) + elif mode == "rtlsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + + inp = context[node.input[0]] + assert str(inp.dtype) == "float32", "Input datatype is not float32" + assert inp.shape == tuple( + exp_ishape + ), """Input shape doesn't + match expected shape.""" + export_idt = self.get_input_datatype() + + reshaped_input = inp.reshape(folded_ishape) + np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input) + + sim = self.get_rtlsim() + nbits = self.get_instream_width() + rtlsim_inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) + super().reset_rtlsim(sim) + super().toggle_clk(sim) + rtlsim_output = self.rtlsim(sim, rtlsim_inp) + odt = export_idt + target_bits = odt.bitwidth() + packed_bits = self.get_outstream_width() + out_npy_path = "{}/output.npy".format(code_gen_dir) + out_shape = self.get_folded_output_shape() + rtlsim_output_to_npy(rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits) + # load and reshape output + output = np.load(out_npy_path) + output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) + context[node.output[0]] = output + + assert context[node.output[0]].shape == tuple( + exp_oshape + ), """Output shape doesn't match expected shape.""" + + def get_template_values(self): + topname = self.get_verilog_top_module_name() + ibits = self.get_instream_width() + obits = self.get_outstream_width() + code_gen_dict = { + "IBITS": int(ibits), + "OBITS": int(obits), + "TOP_MODULE_NAME": topname, + } + return code_gen_dict + + def generate_hdl(self): + rtlsrc = os.environ["FINN_ROOT"] + "/finn-rtllib/dwc/hdl" + template_path = rtlsrc + "/dwc_template.v" + code_gen_dict = self.get_template_values() + # save top module name so we can refer to it after this node has been renamed + # (e.g. by GiveUniqueNodeNames(prefix) during MakeZynqProject) + self.set_nodeattr("gen_top_module", self.get_verilog_top_module_name()) + + # apply code generation to templates + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + with open(template_path, "r") as f: + template = f.read() + for key_name in code_gen_dict: + key = "$%s$" % key_name + template = template.replace(key, str(code_gen_dict[key_name])) + + with open( + os.path.join(code_gen_dir, self.get_verilog_top_module_name() + ".v"), + "w", + ) as f: + f.write(template) + + sv_files = ["dwc_axi.sv"] + for sv_file in sv_files: + shutil.copy(rtlsrc + "/" + sv_file, code_gen_dir) + # set ipgen_path and ip_path so that HLS-Synth transformation + # and stich_ip transformation do not complain + self.set_nodeattr("ipgen_path", code_gen_dir) + self.set_nodeattr("ip_path", code_gen_dir) + + def prepare_rtlsim(self): + """Creates a Verilator emulation library for the RTL code generated + for this node, sets the rtlsim_so attribute to its path and returns + a PyVerilator wrapper around it.""" + # Modified to use generated (System-)Verilog instead of HLS output products + + if PyVerilator is None: + raise ImportError("Installation of PyVerilator is required.") + + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + verilog_paths = [code_gen_dir] + verilog_files = [ + "dwc_axi.sv", + self.get_nodeattr("gen_top_module") + ".v", + ] + + # build the Verilator emu library + sim = PyVerilator.build( + verilog_files, + build_dir=make_build_dir("pyverilator_" + self.onnx_node.name + "_"), + verilog_path=verilog_paths, + trace_depth=get_rtlsim_trace_depth(), + top_module_name=self.get_verilog_top_module_name(), + ) + # save generated lib filename in attribute + self.set_nodeattr("rtlsim_so", sim.lib._name) + return sim + + def code_generation_ipi(self): + """Constructs and returns the TCL for node instantiation in Vivado IPI.""" + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + + sourcefiles = [ + "dwc_axi.sv", + self.get_nodeattr("gen_top_module") + ".v", + ] + + sourcefiles = [os.path.join(code_gen_dir, f) for f in sourcefiles] + + cmd = [] + for f in sourcefiles: + cmd += ["add_files -norecurse %s" % (f)] + cmd += [ + "create_bd_cell -type module -reference %s %s" + % (self.get_nodeattr("gen_top_module"), self.onnx_node.name) + ] + return cmd + + def code_generation_ipgen(self, model, fpgapart, clk): + """Normally: Generates C++ code and tcl script for IP generation. + Here: Generates (System-)Verilog code for IP generation.""" + self.generate_hdl() + + def ipgen_singlenode_code(self): + """Normally: Builds the bash script for IP generation.""" + pass + + def code_generation_cppsim(self, model): + """Normally: Generates C++ code for simulation (cppsim).""" + pass + + def compile_singlenode_code(self): + pass + + def global_includes(self): + pass + + def defines(self, var): + pass + + def read_npy_data(self): + pass + + def strm_decl(self): + pass + + def docompute(self): + pass + + def dataoutstrm(self): + pass + + def save_as_npy(self): + pass + + def blackboxfunction(self): + pass + + def pragmas(self): + pass From 0d01a86e0b9b824b811972110d690479d70aead0 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 22 Nov 2023 12:04:58 +0000 Subject: [PATCH 322/665] [Transformation] Extend InsertDWC to derive rtl variant when selected --- .../transformation/fpgadataflow/insert_dwc.py | 35 ++++++++++++++----- 1 file changed, 27 insertions(+), 8 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/insert_dwc.py b/src/finn/transformation/fpgadataflow/insert_dwc.py index 140d154b1a..fb21cc822d 100644 --- a/src/finn/transformation/fpgadataflow/insert_dwc.py +++ b/src/finn/transformation/fpgadataflow/insert_dwc.py @@ -1,3 +1,4 @@ +import warnings from onnx import TensorProto from onnx import helper as oh from qonnx.custom_op.registry import getCustomOp @@ -33,8 +34,9 @@ def _suitable_node(node): class InsertDWC(Transformation): """Add data width converters between layers where necessary.""" - def __init__(self): + def __init__(self, use_rtl_variant=False): super().__init__() + self.use_rtl_variant = use_rtl_variant def apply(self, model): graph = model.graph @@ -80,11 +82,20 @@ def apply(self, model): dwc_in_width = n0.get_outstream_width() # determine dwc outwidth dwc_out_width = n1.get_instream_width() - # use hls mode by default since it supports more configs - # vivado mode can be manually enabled by user, but does not - # support e.g. node-by-node rtlsim neded for - # characterization-based FIFO sizing - impl_style = "hls" + if self.use_rtl_variant: + # check if rtl variant can be used + iwidth_d = dwc_in_width % dwc_out_width == 0 + owidth_d = dwc_out_width % dwc_in_width == 0 + if iwidth_d or owidth_d: + node_optype = "StreamingDataWidthConverter_rtl" + else: + warnings.warn( + "DWC cannot be implemented as RTL variant, default to hls" + ) + node_optype = "StreamingDataWidthConverter_Batch" + self.use_rtl_variant = False + else: + node_optype = "StreamingDataWidthConverter_Batch" # determine shape for dwc dwc_shape = n0.get_normal_output_shape() @@ -100,7 +111,7 @@ def apply(self, model): graph.value_info.append(dwc_output_tensor) dwc_node = oh.make_node( - "StreamingDataWidthConverter_Batch", + node_optype, [output_name], [dwc_output_tensor.name], domain="finn.custom_op.fpgadataflow", @@ -109,8 +120,16 @@ def apply(self, model): inWidth=dwc_in_width, outWidth=dwc_out_width, dataType=str(dtype.name), - impl_style=impl_style, ) + # if not rtl variant is selected + # use hls mode by default since it supports more configs + # vivado mode can be manually enabled by user, but does not + # support e.g. node-by-node rtlsim neded for + # characterization-based FIFO sizing + if not self.use_rtl_variant: + impl_attr = oh.make_attribute("impl_style", "hls") + dwc_node.attribute.append(impl_attr) + # insert dwc graph.node.insert(node_ind + 1, dwc_node) From b1fcf88843752eb47c87204aa69a5640797c41e6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thomas=20B=2E=20Preu=C3=9Fer?= Date: Wed, 22 Nov 2023 13:57:18 +0000 Subject: [PATCH 323/665] Fix clock association and polarity of reset. --- finn-rtllib/dwc/hdl/dwc_axi.sv | 10 +++--- finn-rtllib/dwc/hdl/dwc_template.v | 55 +++++++++++++++--------------- finn-rtllib/dwc/sim/dwc_axi_tb.sv | 4 +-- 3 files changed, 35 insertions(+), 34 deletions(-) diff --git a/finn-rtllib/dwc/hdl/dwc_axi.sv b/finn-rtllib/dwc/hdl/dwc_axi.sv index 5381b57ac4..7aa915289f 100644 --- a/finn-rtllib/dwc/hdl/dwc_axi.sv +++ b/finn-rtllib/dwc/hdl/dwc_axi.sv @@ -49,6 +49,8 @@ module dwc_axi #( output logic m_axis_tvalid, output logic [OBITS-1:0] m_axis_tdata ); + uwire clk = ap_clk; + uwire rst = !ap_rst_n; if(IBITS == OBITS) begin : genNoop assign s_axis_tready = m_axis_tready; @@ -72,8 +74,8 @@ module dwc_axi #( logic [$clog2(K):0] ACnt = K-1; // (empty) K-1, ..., 0, -1 (full/valid) dat_t BDat = 'x; logic BRdy = 1; - always_ff @(posedge ap_clk) begin - if(ap_rst_n) begin + always_ff @(posedge clk) begin + if(rst) begin ADat <= 'x; ACnt <= K-1; BDat <= 'x; @@ -118,8 +120,8 @@ module dwc_axi #( logic BRdy = 1; dat_t CDat = 'x; logic CVld = 0; - always_ff @(posedge ap_clk) begin - if(ap_rst_n) begin + always_ff @(posedge clk) begin + if(rst) begin ADat <= 'x; ACnt <= 1; BDat <= 'x; diff --git a/finn-rtllib/dwc/hdl/dwc_template.v b/finn-rtllib/dwc/hdl/dwc_template.v index 27f6c70dff..9541913c9f 100644 --- a/finn-rtllib/dwc/hdl/dwc_template.v +++ b/finn-rtllib/dwc/hdl/dwc_template.v @@ -30,37 +30,36 @@ *****************************************************************************/ module $TOP_MODULE_NAME$( -//- Global Control ------------------ -(* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out_V" *) -input ap_clk, -input ap_rst_n, + //- Global Control ------------------ + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *) + (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out_V, ASSOCIATED_RESET ap_rst_n" *) + input ap_clk, + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) + input ap_rst_n, -//- AXI Stream - Input -------------- -output in0_V_TREADY, -input in0_V_TVALID, -input [$IBITS$-1:0] in0_V_TDATA, + //- AXI Stream - Input -------------- + output in0_V_TREADY, + input in0_V_TVALID, + input [$IBITS$-1:0] in0_V_TDATA, -//- AXI Stream - Output ------------- -input out_V_TREADY, -output out_V_TVALID, -output [$OBITS$-1:0] out_V_TDATA + //- AXI Stream - Output ------------- + input out_V_TREADY, + output out_V_TVALID, + output [$OBITS$-1:0] out_V_TDATA ); - -dwc_axi #( -.IBITS($IBITS$), -.OBITS($OBITS$) -) -$TOP_MODULE_NAME$_impl -( - .ap_clk(ap_clk), - .ap_rst_n(ap_rst_n), - .s_axis_tready(in0_V_TREADY), - .s_axis_tvalid(in0_V_TVALID), - .s_axis_tdata(in0_V_TDATA), - .m_axis_tready(out_V_TREADY), - .m_axis_tvalid(out_V_TVALID), - .m_axis_tdata(out_V_TDATA) -); + dwc_axi #( + .IBITS($IBITS$), + .OBITS($OBITS$) + ) impl ( + .ap_clk(ap_clk), + .ap_rst_n(ap_rst_n), + .s_axis_tready(in0_V_TREADY), + .s_axis_tvalid(in0_V_TVALID), + .s_axis_tdata(in0_V_TDATA), + .m_axis_tready(out_V_TREADY), + .m_axis_tvalid(out_V_TVALID), + .m_axis_tdata(out_V_TDATA) + ); endmodule diff --git a/finn-rtllib/dwc/sim/dwc_axi_tb.sv b/finn-rtllib/dwc/sim/dwc_axi_tb.sv index 6bc3249685..b47e5b2f83 100644 --- a/finn-rtllib/dwc/sim/dwc_axi_tb.sv +++ b/finn-rtllib/dwc/sim/dwc_axi_tb.sv @@ -61,7 +61,7 @@ module dwc_axi_tb; dat_t [K-1:0] m_axis_tdata; dwc_axi #(.IBITS(IBITS), .OBITS(OBITS)) dut ( - .clk, .rst, + .ap_clk(clk), .ap_rst_n(!rst), .s_axis_tready, .s_axis_tvalid, .s_axis_tdata, .m_axis_tready, .m_axis_tvalid, .m_axis_tdata ); @@ -134,7 +134,7 @@ module dwc_axi_tb; dat_t m_axis_tdata; dwc_axi #(.IBITS(IBITS), .OBITS(OBITS)) dut ( - .clk, .rst, + .ap_clk(clk), .ap_rst_n(!rst), .s_axis_tready, .s_axis_tvalid, .s_axis_tdata, .m_axis_tready, .m_axis_tvalid, .m_axis_tdata ); From 2ad42b06e297a2e4b504a92f83111ec20ee01a5a Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 22 Nov 2023 15:12:49 +0000 Subject: [PATCH 324/665] [Test] Extend dwc testing to test rtl variant of node --- tests/fpgadataflow/test_fpgadataflow_dwc.py | 31 +++++++++++++++++---- 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_dwc.py b/tests/fpgadataflow/test_fpgadataflow_dwc.py index eb6e0651d9..f3302132af 100644 --- a/tests/fpgadataflow/test_fpgadataflow_dwc.py +++ b/tests/fpgadataflow/test_fpgadataflow_dwc.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2020-2022, Xilinx, Inc. +# Copyright (C) 2023, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -41,12 +42,17 @@ from finn.transformation.fpgadataflow.prepare_ip import PrepareIP -def make_single_dwc_modelwrapper(shape, inWidth, outWidth, finn_dtype, impl_style): +def make_single_dwc_modelwrapper(shape, inWidth, outWidth, finn_dtype, impl_style, use_rtl_variant): inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, shape) outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, shape) + if use_rtl_variant: + optype = "StreamingDataWidthConverter_rtl" + else: + optype = "StreamingDataWidthConverter_Batch" + DWC_node = helper.make_node( - "StreamingDataWidthConverter_Batch", + optype, ["inp"], ["outp"], domain="finn.custom_op.fpgadataflow", @@ -55,8 +61,12 @@ def make_single_dwc_modelwrapper(shape, inWidth, outWidth, finn_dtype, impl_styl inWidth=inWidth, outWidth=outWidth, dataType=str(finn_dtype.name), - impl_style=impl_style, + rtlsim_trace="dwc.vcd", ) + if not use_rtl_variant: + # add additional attribute + impl_attr = helper.make_attribute("impl_style", impl_style) + DWC_node.attribute.append(impl_attr) graph = helper.make_graph(nodes=[DWC_node], name="dwc_graph", inputs=[inp], outputs=[outp]) @@ -85,18 +95,27 @@ def prepare_inputs(input_tensor, dt): ([1, 2, 8], 8, 16, DataType["INT2"], "vivado"), ], ) +@pytest.mark.parametrize("use_rtl_variant", [0, 1]) @pytest.mark.fpgadataflow @pytest.mark.slow @pytest.mark.vivado -def test_fpgadataflow_dwc_rtlsim(config): +def test_fpgadataflow_dwc_rtlsim(config, use_rtl_variant): shape, inWidth, outWidth, finn_dtype, impl_style = config + + if use_rtl_variant: + iwidth_d = inWidth % outWidth == 0 + owidth_d = outWidth % inWidth == 0 + if not (iwidth_d or owidth_d): + pytest.skip("RTL variant only supports stream widths that are divisible by int ratios") test_fpga_part = "xc7z020clg400-1" target_clk_ns = 10.0 # generate input data x = gen_finn_dt_tensor(finn_dtype, shape) input_dict = prepare_inputs(x, finn_dtype) - model = make_single_dwc_modelwrapper(shape, inWidth, outWidth, finn_dtype, impl_style) + model = make_single_dwc_modelwrapper( + shape, inWidth, outWidth, finn_dtype, impl_style, use_rtl_variant + ) model = model.transform(InsertFIFO(create_shallow_fifos=True)) model = model.transform(GiveUniqueNodeNames()) model = model.transform(PrepareIP(test_fpga_part, 5)) From 64175ca2c8fb6f9b15b0f116570f2e7e4301e842 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 22 Nov 2023 15:18:54 +0000 Subject: [PATCH 325/665] [Transformation] Use RTL DWC by default --- src/finn/transformation/fpgadataflow/insert_dwc.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/finn/transformation/fpgadataflow/insert_dwc.py b/src/finn/transformation/fpgadataflow/insert_dwc.py index fb21cc822d..bf0254c1a7 100644 --- a/src/finn/transformation/fpgadataflow/insert_dwc.py +++ b/src/finn/transformation/fpgadataflow/insert_dwc.py @@ -34,7 +34,7 @@ def _suitable_node(node): class InsertDWC(Transformation): """Add data width converters between layers where necessary.""" - def __init__(self, use_rtl_variant=False): + def __init__(self, use_rtl_variant=True): super().__init__() self.use_rtl_variant = use_rtl_variant From 156be025eb05d513f38659958c2b1607ecf9f06a Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 24 Nov 2023 10:28:00 +0000 Subject: [PATCH 326/665] [Tests] Update export to qonnx export --- tests/fpgadataflow/test_fpgadataflow_lookup.py | 16 ++++++++++++---- .../fpgadataflow/test_fpgadataflow_upsampler.py | 14 +++++++++----- 2 files changed, 21 insertions(+), 9 deletions(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_lookup.py b/tests/fpgadataflow/test_fpgadataflow_lookup.py index 7951007045..d2861261b6 100644 --- a/tests/fpgadataflow/test_fpgadataflow_lookup.py +++ b/tests/fpgadataflow/test_fpgadataflow_lookup.py @@ -1,4 +1,5 @@ -# Copyright (c) 2021, Xilinx +# Copyright (C) 2021-2022, Xilinx, Inc. +# Copyright (C) 2023, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -30,7 +31,7 @@ import numpy as np import torch -from brevitas.export import FINNManager +from brevitas.export import export_qonnx from qonnx.core.datatype import DataType from qonnx.core.modelwrapper import ModelWrapper from qonnx.custom_op.registry import getCustomOp @@ -38,6 +39,7 @@ from qonnx.transformation.infer_datatypes import InferDataTypes from qonnx.transformation.infer_shapes import InferShapes from qonnx.util.basic import gen_finn_dt_tensor +from qonnx.util.cleanup import cleanup as qonnx_cleanup from torch import nn from finn.core.onnx_exec import execute_onnx @@ -49,6 +51,9 @@ from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.qonnx.convert_qonnx_to_finn import ConvertQONNXtoFINN + +export_onnx_path = "test_lookup.onnx" def make_lookup_model(embeddings, ishape, idt, edt): @@ -65,8 +70,11 @@ def forward(self, x): torch_model = LookupModel(num_embeddings, embedding_dim) input_t = torch.zeros(ishape, dtype=torch.int64) - ret = FINNManager.export(torch_model, input_t=input_t, opset_version=11) - model = ModelWrapper(ret) + export_qonnx(torch_model, input_t, export_onnx_path, opset_version=11) + qonnx_cleanup(export_onnx_path, out_file=export_onnx_path) + model = ModelWrapper(export_onnx_path) + model = model.transform(ConvertQONNXtoFINN()) + model = model.transform(InferShapes()) iname = model.graph.input[0].name ename = model.graph.node[0].input[0] model.set_tensor_datatype(iname, idt) diff --git a/tests/fpgadataflow/test_fpgadataflow_upsampler.py b/tests/fpgadataflow/test_fpgadataflow_upsampler.py index a08d31f7b0..70d81c7d31 100644 --- a/tests/fpgadataflow/test_fpgadataflow_upsampler.py +++ b/tests/fpgadataflow/test_fpgadataflow_upsampler.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2020-2022, Xilinx, Inc. +# Copyright (C) 2023, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -32,7 +33,7 @@ import os import shutil import torch -from brevitas.export import FINNManager +from brevitas.export import export_qonnx from qonnx.core.datatype import DataType from qonnx.core.modelwrapper import ModelWrapper from qonnx.transformation.base import Transformation @@ -41,6 +42,7 @@ from qonnx.transformation.infer_datatypes import InferDataTypes from qonnx.transformation.infer_shapes import InferShapes from qonnx.transformation.make_input_chanlast import MakeInputChannelsLast +from qonnx.util.cleanup import cleanup as qonnx_cleanup from torch import nn import finn.core.onnx_exec as oxe @@ -52,6 +54,7 @@ from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.qonnx.convert_qonnx_to_finn import ConvertQONNXtoFINN from finn.util.basic import make_build_dir tmpdir = os.environ["FINN_BUILD_DIR"] @@ -154,10 +157,11 @@ def test_fpgadataflow_upsampler(dt, IFMDim, scale, NumChannels, exec_mode, is_1d # Get golden PyTorch and ONNX inputs golden_torch_float = torch_model(test_in) export_path = f"{tmpdir}/Upsample_exported.onnx" - FINNManager.export( - torch_model, input_shape=input_shape, export_path=export_path, opset_version=11 - ) + export_qonnx(torch_model, torch.randn(input_shape), export_path, opset_version=11) + qonnx_cleanup(export_path, out_file=export_path) model = ModelWrapper(export_path) + model = model.transform(ConvertQONNXtoFINN()) + model = model.transform(InferShapes()) input_dict = {model.graph.input[0].name: test_in.numpy().astype(np.int32)} input_dict = {model.graph.input[0].name: test_in.numpy()} golden_output_dict = oxe.execute_onnx(model, input_dict, True) From b2766d75c75fba88857472bb9732698343e37264 Mon Sep 17 00:00:00 2001 From: Felix Jentzsch Date: Fri, 24 Nov 2023 12:37:22 +0100 Subject: [PATCH 327/665] Add Singularity support --- .github/workflows/singularity-quicktest.yml | 47 +++++++++++++++++++++ docker/Dockerfile.finn | 4 +- docker/finn_entrypoint.sh | 4 +- docs/finn/getting_started.rst | 1 + run-docker.sh | 33 ++++++++++----- 5 files changed, 77 insertions(+), 12 deletions(-) create mode 100644 .github/workflows/singularity-quicktest.yml diff --git a/.github/workflows/singularity-quicktest.yml b/.github/workflows/singularity-quicktest.yml new file mode 100644 index 0000000000..349b403a3a --- /dev/null +++ b/.github/workflows/singularity-quicktest.yml @@ -0,0 +1,47 @@ +name: SingularityQuicktest + +on: + pull_request: + branches: [ apptainer_testing ] + push: + branches: [ apptainer_testing ] + +jobs: + build_quicktest_singularity: + name: Build and quicktest Singularity container + runs-on: ubuntu-22.04 + steps: + - name: Reclaim storage + run: | + docker image prune -a -f + sudo rm -rf /usr/share/dotnet + sudo rm -rf /usr/local/lib/android + - name: Checkout + uses: actions/checkout@v3 + - name: Set up Docker + uses: docker/setup-buildx-action@v2 + with: + driver: docker + - name: Set up Singularity + run: | + sudo add-apt-repository -y ppa:apptainer/ppa + sudo apt update + sudo apt install -y apptainer + alias singularity="apptainer" + - name: Build Docker image + uses: docker/build-push-action@v4 + with: + file: docker/Dockerfile.finn + context: . + load: true + no-cache: true + tags: finn_docker_export:latest + - name: Build Singularity image + run: | + mkdir $GITHUB_WORKSPACE/singularity_tmp + export APPTAINER_TMPDIR=$GITHUB_WORKSPACE/singularity_tmp + singularity build --disable-cache finn_singularity_image.sif docker-daemon://finn_docker_export:latest + - name: Run quicktest + run: | + export FINN_SINGULARITY=finn_singularity_image.sif + ./run-docker.sh quicktest diff --git a/docker/Dockerfile.finn b/docker/Dockerfile.finn index 06dc109808..9d7ca809db 100644 --- a/docker/Dockerfile.finn +++ b/docker/Dockerfile.finn @@ -60,7 +60,9 @@ RUN apt-get update && \ lsb-core \ python3 \ python-is-python3 \ - python3-pip + python3-pip \ + python3-setuptools-scm \ + python3-venv RUN echo "StrictHostKeyChecking no" >> /etc/ssh/ssh_config RUN locale-gen "en_US.UTF-8" diff --git a/docker/finn_entrypoint.sh b/docker/finn_entrypoint.sh index 6b33a4c9bc..971f92beb6 100644 --- a/docker/finn_entrypoint.sh +++ b/docker/finn_entrypoint.sh @@ -56,7 +56,9 @@ recho () { # qonnx (using workaround for https://github.com/pypa/pip/issues/7953) # to be fixed in future Ubuntu versions (https://bugs.launchpad.net/ubuntu/+source/setuptools/+bug/1994016) -pip install --no-build-isolation --no-warn-script-location -e ${FINN_ROOT}/deps/qonnx +mv ${FINN_ROOT}/deps/qonnx/pyproject.toml ${FINN_ROOT}/deps/qonnx/pyproject.tmp +pip install --user -e ${FINN_ROOT}/deps/qonnx +mv ${FINN_ROOT}/deps/qonnx/pyproject.tmp ${FINN_ROOT}/deps/qonnx/pyproject.toml # finn-experimental pip install --user -e ${FINN_ROOT}/deps/finn-experimental # brevitas diff --git a/docs/finn/getting_started.rst b/docs/finn/getting_started.rst index c575ca7e3b..2edac294d9 100644 --- a/docs/finn/getting_started.rst +++ b/docs/finn/getting_started.rst @@ -116,6 +116,7 @@ These are summarized below: * (optional) ``FINN_SKIP_DEP_REPOS`` (default "0") skips the download of FINN dependency repos (uses the ones already downloaded under deps/. * (optional) ``NVIDIA_VISIBLE_DEVICES`` (default "") specifies specific Nvidia GPUs to use in Docker container. Possible values are a comma-separated list of GPU UUID(s) or index(es) e.g. ``0,1,2``, ``all``, ``none``, or void/empty/unset. * (optional) ``DOCKER_BUILDKIT`` (default "1") enables `Docker BuildKit `_ for faster Docker image rebuilding (recommended). +* (optional) ``FINN_SINGULARITY`` (default "") points to a pre-built Singularity image to use instead of the Docker image. Singularity support is experimental and intended only for systems where Docker is unavailable. Does not support GPUs. General FINN Docker tips ************************ diff --git a/run-docker.sh b/run-docker.sh index 58d7d97084..f03dd145be 100755 --- a/run-docker.sh +++ b/run-docker.sh @@ -97,6 +97,7 @@ SCRIPTPATH=$(dirname "$SCRIPT") : ${OHMYXILINX="${SCRIPTPATH}/deps/oh-my-xilinx"} : ${NVIDIA_VISIBLE_DEVICES=""} : ${DOCKER_BUILDKIT="1"} +: ${FINN_SINGULARITY=""} DOCKER_INTERACTIVE="" @@ -119,8 +120,10 @@ elif [ "$1" = "notebook" ]; then DOCKER_CMD="jupyter notebook --allow-root --no-browser --ip=0.0.0.0 --port $JUPYTER_PORT $JUPYTER_PASSWD_ARG notebooks" FINN_DOCKER_EXTRA+="-e JUPYTER_PORT=$JUPYTER_PORT " FINN_DOCKER_EXTRA+="-e NETRON_PORT=$NETRON_PORT " - FINN_DOCKER_EXTRA+="-p $JUPYTER_PORT:$JUPYTER_PORT " - FINN_DOCKER_EXTRA+="-p $NETRON_PORT:$NETRON_PORT " + if [ -z "$FINN_SINGULARITY" ]; then + FINN_DOCKER_EXTRA+="-p $JUPYTER_PORT:$JUPYTER_PORT " + FINN_DOCKER_EXTRA+="-p $NETRON_PORT:$NETRON_PORT " + fi elif [ "$1" = "build_dataflow" ]; then BUILD_DATAFLOW_DIR=$(readlink -f "$2") FINN_DOCKER_EXTRA+="-v $BUILD_DATAFLOW_DIR:$BUILD_DATAFLOW_DIR " @@ -146,7 +149,7 @@ else fi -if [ "$FINN_DOCKER_GPU" != 0 ];then +if [ "$FINN_DOCKER_GPU" != 0 ] && [ -z "$FINN_SINGULARITY" ];then gecho "nvidia-docker detected, enabling GPUs" if [ ! -z "$NVIDIA_VISIBLE_DEVICES" ];then FINN_DOCKER_EXTRA+="--runtime nvidia -e NVIDIA_VISIBLE_DEVICES=$NVIDIA_VISIBLE_DEVICES " @@ -177,7 +180,7 @@ if [ "$FINN_SKIP_DEP_REPOS" = "0" ]; then fi # Build the FINN Docker image -if [ "$FINN_DOCKER_PREBUILT" = "0" ]; then +if [ "$FINN_DOCKER_PREBUILT" = "0" ] && [ -z "$FINN_SINGULARITY" ]; then # Need to ensure this is done within the finn/ root folder: OLD_PWD=$(pwd) cd $SCRIPTPATH @@ -187,9 +190,8 @@ fi # Launch container with current directory mounted # important to pass the --init flag here for correct Vivado operation, see: # https://stackoverflow.com/questions/55733058/vivado-synthesis-hangs-in-docker-container-spawned-by-jenkins -DOCKER_EXEC="docker run -t --rm $DOCKER_INTERACTIVE --tty --init " -DOCKER_EXEC+="--hostname $DOCKER_INST_NAME " -DOCKER_EXEC+="-e SHELL=/bin/bash " +DOCKER_BASE="docker run -t --rm $DOCKER_INTERACTIVE --tty --init --hostname $DOCKER_INST_NAME " +DOCKER_EXEC="-e SHELL=/bin/bash " DOCKER_EXEC+="-w $SCRIPTPATH " DOCKER_EXEC+="-v $SCRIPTPATH:$SCRIPTPATH " DOCKER_EXEC+="-v $FINN_HOST_BUILD_DIR:$FINN_HOST_BUILD_DIR " @@ -207,7 +209,7 @@ DOCKER_EXEC+="-e NUM_DEFAULT_WORKERS=$NUM_DEFAULT_WORKERS " # Workaround for FlexLM issue, see: # https://community.flexera.com/t5/InstallAnywhere-Forum/Issues-when-running-Xilinx-tools-or-Other-vendor-tools-in-docker/m-p/245820#M10647 DOCKER_EXEC+="-e LD_PRELOAD=/lib/x86_64-linux-gnu/libudev.so.1 " -if [ "$FINN_DOCKER_RUN_AS_ROOT" = "0" ];then +if [ "$FINN_DOCKER_RUN_AS_ROOT" = "0" ] && [ -z "$FINN_SINGULARITY" ];then DOCKER_EXEC+="-v /etc/group:/etc/group:ro " DOCKER_EXEC+="-v /etc/passwd:/etc/passwd:ro " DOCKER_EXEC+="-v /etc/shadow:/etc/shadow:ro " @@ -247,6 +249,17 @@ if [ ! -z "$FINN_XILINX_PATH" ];then fi fi DOCKER_EXEC+="$FINN_DOCKER_EXTRA " -DOCKER_EXEC+="$FINN_DOCKER_TAG $DOCKER_CMD" -$DOCKER_EXEC +if [ -z "$FINN_SINGULARITY" ];then + CMD_TO_RUN="$DOCKER_BASE $DOCKER_EXEC $FINN_DOCKER_TAG $DOCKER_CMD" +else + SINGULARITY_BASE="singularity exec" + # Replace command options for Singularity + SINGULARITY_EXEC="${DOCKER_EXEC//"-e "/"--env "}" + SINGULARITY_EXEC="${SINGULARITY_EXEC//"-v "/"-B "}" + SINGULARITY_EXEC="${SINGULARITY_EXEC//"-w "/"--pwd "}" + CMD_TO_RUN="$SINGULARITY_BASE $SINGULARITY_EXEC $FINN_SINGULARITY /usr/local/bin/finn_entrypoint.sh $DOCKER_CMD" + gecho "FINN_SINGULARITY is set, launching Singularity container instead of Docker" +fi + +$CMD_TO_RUN From 94f2001715b6f148b3fa5f5831914b038a337909 Mon Sep 17 00:00:00 2001 From: Felix Jentzsch Date: Fri, 24 Nov 2023 12:38:57 +0100 Subject: [PATCH 328/665] [Singularity] Trigger GHA on dev branch --- .github/workflows/singularity-quicktest.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/singularity-quicktest.yml b/.github/workflows/singularity-quicktest.yml index 349b403a3a..4fd8ec38ae 100644 --- a/.github/workflows/singularity-quicktest.yml +++ b/.github/workflows/singularity-quicktest.yml @@ -2,9 +2,9 @@ name: SingularityQuicktest on: pull_request: - branches: [ apptainer_testing ] + branches: [ dev ] push: - branches: [ apptainer_testing ] + branches: [ dev ] jobs: build_quicktest_singularity: From 9fd482e7d3a340b5e48bc83841b6f5daefdb22b8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thomas=20B=2E=20Preu=C3=9Fer?= Date: Fri, 24 Nov 2023 16:51:14 +0000 Subject: [PATCH 329/665] Extended AXI-lite data bus to next full byte boundary. --- finn-rtllib/dwc/hdl/dwc.sv | 158 +++++++++++++++++++++++++++++ finn-rtllib/dwc/hdl/dwc_axi.sv | 125 +++-------------------- finn-rtllib/dwc/hdl/dwc_template.v | 16 ++- finn-rtllib/dwc/sim/dwc_axi_tb.sv | 2 +- 4 files changed, 185 insertions(+), 116 deletions(-) create mode 100644 finn-rtllib/dwc/hdl/dwc.sv diff --git a/finn-rtllib/dwc/hdl/dwc.sv b/finn-rtllib/dwc/hdl/dwc.sv new file mode 100644 index 0000000000..13b0cb34c4 --- /dev/null +++ b/finn-rtllib/dwc/hdl/dwc.sv @@ -0,0 +1,158 @@ +/****************************************************************************** + * Copyright (C) 2023, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * @brief Stream Data Width Converter. + * @author Thomas B. Preußer + *****************************************************************************/ +module dwc #( + int unsigned IBITS, + int unsigned OBITS +)( + //- Global Control ------------------ + input logic clk, + input logic rst, + + //- AXI Stream - Input -------------- + output logic irdy, + input logic ivld, + input logic [IBITS-1:0] idat, + + //- AXI Stream - Output ------------- + input logic ordy, + output logic ovld, + output logic [OBITS-1:0] odat +); + + if(IBITS == OBITS) begin : genNoop + assign irdy = ordy; + assign ovld = ivld; + assign odat = idat; + end : genNoop + else if(IBITS < OBITS) begin : genUp + + // Sanity Checking: integer upscaling + initial begin + if(OBITS % IBITS) begin + $error("Output width %0d is not a multiple of input width %0d.", OBITS, IBITS); + $finish; + end + end + + // Parallelizing Shift Register A and Sidestep Buffer B on Input Path + localparam int unsigned K = OBITS / IBITS; + typedef logic [IBITS-1:0] dat_t; + dat_t [K-1:0] ADat = 'x; + logic [$clog2(K):0] ACnt = K-1; // (empty) K-1, ..., 0, -1 (full/valid) + dat_t BDat = 'x; + logic BRdy = 1; + always_ff @(posedge clk) begin + if(rst) begin + ADat <= 'x; + ACnt <= K-1; + BDat <= 'x; + BRdy <= 1; + end + else begin + automatic type(ACnt) acnt = (ovld && ordy)? K-1 : ACnt; + automatic logic rdy = !ovld || ordy; + if((ivld || !BRdy) && rdy) begin + ADat <= { BRdy? idat : BDat, ADat[K-1:1] }; + acnt--; + end + ACnt <= acnt; + + if(BRdy) BDat <= idat; + BRdy <= rdy || (BRdy && !ivld); + end + end + + // Output Assignments + assign irdy = BRdy; + assign ovld = ACnt[$left(ACnt)]; + assign odat = ADat; + + end : genUp + else begin : genDown + + // Sanity Checking: integer downscaling + initial begin + if(IBITS % OBITS) begin + $error("Input width %0d is not a multiple of output width %0d.", IBITS, OBITS); + $finish; + end + end + + // Serializing Shift Register A and Sidestep Buffer B on Output Path + localparam int unsigned K = IBITS / OBITS; + typedef logic [OBITS-1:0] dat_t; + dat_t [ K-1:0] ADat = 'x; + logic [$clog2(K):0] ACnt = 1; // (full) -K+1, ..., -1, 0, 1 (empty/not valid) + dat_t BDat = 'x; + logic BRdy = 1; + dat_t CDat = 'x; + logic CVld = 0; + always_ff @(posedge clk) begin + if(rst) begin + ADat <= 'x; + ACnt <= 1; + BDat <= 'x; + BRdy <= 1; + CDat <= 'x; + CVld <= 0; + end + else begin + automatic type(ACnt) acnt = ACnt; + automatic logic ainc = 0; + if(irdy) begin + ADat <= idat; + acnt = ivld? -K+1 : 1; + end + else if(BRdy) begin + ADat <= { {OBITS{1'bx}}, ADat[K-1:1] }; + ainc = BRdy; + end; + ACnt <= acnt + ainc; + + if(BRdy) BDat <= ADat[0]; + BRdy <= !CVld || ordy || (BRdy && !ACnt[$left(ACnt)] && ACnt[0]); + + if(!CVld || ordy) CDat <= BRdy? ADat[0] : BDat; + CVld <= (CVld && !ordy) || !BRdy || ACnt[$left(ACnt)] || !ACnt[0]; + end + end + + // Output Assignments + assign irdy = BRdy && !ACnt[$left(ACnt)]; + assign ovld = CVld; + assign odat = CDat; + + end : genDown + +endmodule : dwc diff --git a/finn-rtllib/dwc/hdl/dwc_axi.sv b/finn-rtllib/dwc/hdl/dwc_axi.sv index 7aa915289f..dfe02fcb48 100644 --- a/finn-rtllib/dwc/hdl/dwc_axi.sv +++ b/finn-rtllib/dwc/hdl/dwc_axi.sv @@ -28,12 +28,15 @@ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * @brief AXI Stream Data Width Converter. + * @brief AXI Stream Adapter for Data Width Converter. * @author Thomas B. Preußer *****************************************************************************/ module dwc_axi #( int unsigned IBITS, - int unsigned OBITS + int unsigned OBITS, + + localparam int unsigned AXI_IBITS = (IBITS+7)/8 * 8, + localparam int unsigned AXI_OBITS = (OBITS+7)/8 * 8 )( //- Global Control ------------------ input logic ap_clk, @@ -42,119 +45,21 @@ module dwc_axi #( //- AXI Stream - Input -------------- output logic s_axis_tready, input logic s_axis_tvalid, - input logic [IBITS-1:0] s_axis_tdata, + input logic [AXI_IBITS-1:0] s_axis_tdata, //- AXI Stream - Output ------------- input logic m_axis_tready, output logic m_axis_tvalid, - output logic [OBITS-1:0] m_axis_tdata + output logic [AXI_OBITS-1:0] m_axis_tdata ); - uwire clk = ap_clk; - uwire rst = !ap_rst_n; - - if(IBITS == OBITS) begin : genNoop - assign s_axis_tready = m_axis_tready; - assign m_axis_tvalid = s_axis_tvalid; - assign m_axis_tdata = s_axis_tdata; - end : genNoop - else if(IBITS < OBITS) begin : genUp - - // Sanity Checking: integer upscaling - initial begin - if(OBITS % IBITS) begin - $error("Output width %0d is not a multiple of input width %0d.", OBITS, IBITS); - $finish; - end - end - - // Parallelizing Shift Register A and Sidestep Buffer B on Input Path - localparam int unsigned K = OBITS / IBITS; - typedef logic [IBITS-1:0] dat_t; - dat_t [K-1:0] ADat = 'x; - logic [$clog2(K):0] ACnt = K-1; // (empty) K-1, ..., 0, -1 (full/valid) - dat_t BDat = 'x; - logic BRdy = 1; - always_ff @(posedge clk) begin - if(rst) begin - ADat <= 'x; - ACnt <= K-1; - BDat <= 'x; - BRdy <= 1; - end - else begin - automatic type(ACnt) acnt = (m_axis_tvalid && m_axis_tready)? K-1 : ACnt; - automatic logic rdy = !m_axis_tvalid || m_axis_tready; - if((s_axis_tvalid || !BRdy) && rdy) begin - ADat <= { BRdy? s_axis_tdata : BDat, ADat[K-1:1] }; - acnt--; - end - ACnt <= acnt; - - if(BRdy) BDat <= s_axis_tdata; - BRdy <= rdy || (BRdy && !s_axis_tvalid); - end - end - - // Output Assignments - assign s_axis_tready = BRdy; - assign m_axis_tvalid = ACnt[$left(ACnt)]; - assign m_axis_tdata = ADat; - - end : genUp - else begin : genDown - - // Sanity Checking: integer downscaling - initial begin - if(IBITS % OBITS) begin - $error("Input width %0d is not a multiple of output width %0d.", IBITS, OBITS); - $finish; - end - end - - // Serializing Shift Register A and Sidestep Buffer B on Output Path - localparam int unsigned K = IBITS / OBITS; - typedef logic [OBITS-1:0] dat_t; - dat_t [ K-1:0] ADat = 'x; - logic [$clog2(K):0] ACnt = 1; // (full) -K+1, ..., -1, 0, 1 (empty/not valid) - dat_t BDat = 'x; - logic BRdy = 1; - dat_t CDat = 'x; - logic CVld = 0; - always_ff @(posedge clk) begin - if(rst) begin - ADat <= 'x; - ACnt <= 1; - BDat <= 'x; - BRdy <= 1; - CDat <= 'x; - CVld <= 0; - end - else begin - automatic type(ACnt) acnt = ACnt; - automatic logic ainc = 0; - if(s_axis_tready) begin - ADat <= s_axis_tdata; - acnt = s_axis_tvalid? -K+1 : 1; - end - else if(BRdy) begin - ADat <= { {OBITS{1'bx}}, ADat[K-1:1] }; - ainc = BRdy; - end; - ACnt <= acnt + ainc; - - if(BRdy) BDat <= ADat[0]; - BRdy <= !CVld || m_axis_tready || (BRdy && !ACnt[$left(ACnt)] && ACnt[0]); - - if(!CVld || m_axis_tready) CDat <= BRdy? ADat[0] : BDat; - CVld <= (CVld && !m_axis_tready) || !BRdy || ACnt[$left(ACnt)] || !ACnt[0]; - end - end - - // Output Assignments - assign s_axis_tready = BRdy && !ACnt[$left(ACnt)]; - assign m_axis_tvalid = CVld; - assign m_axis_tdata = CDat; - end : genDown + dwc #(.IBITS(IBITS), .OBITS(OBITS)) core ( + .clk(ap_clk), .rst(!ap_rst_n), + .irdy(s_axis_tready), .ivld(s_axis_tvalid), .idat(s_axis_tdata[IBITS-1:0]), + .ordy(m_axis_tready), .ovld(m_axis_tvalid), .odat(m_axis_tdata[OBITS-1:0]) + ); + if(OBITS < AXI_OBITS) begin + assign m_axis_tdata[AXI_OBITS-1:OBITS] = '0; + end endmodule : dwc_axi diff --git a/finn-rtllib/dwc/hdl/dwc_template.v b/finn-rtllib/dwc/hdl/dwc_template.v index 9541913c9f..01a0254040 100644 --- a/finn-rtllib/dwc/hdl/dwc_template.v +++ b/finn-rtllib/dwc/hdl/dwc_template.v @@ -29,7 +29,13 @@ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ -module $TOP_MODULE_NAME$( +module $TOP_MODULE_NAME$ #( + parameter IBITS = $IBITS$, + parameter OBITS = $OBITS$, + + parameter AXI_IBITS = (IBITS+7)/8 * 8, + parameter AXI_OBITS = (OBITS+7)/8 * 8 +)( //- Global Control ------------------ (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *) (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out_V, ASSOCIATED_RESET ap_rst_n" *) @@ -40,17 +46,17 @@ module $TOP_MODULE_NAME$( //- AXI Stream - Input -------------- output in0_V_TREADY, input in0_V_TVALID, - input [$IBITS$-1:0] in0_V_TDATA, + input [AXI_IBITS-1:0] in0_V_TDATA, //- AXI Stream - Output ------------- input out_V_TREADY, output out_V_TVALID, - output [$OBITS$-1:0] out_V_TDATA + output [AXI_OBITS-1:0] out_V_TDATA ); dwc_axi #( - .IBITS($IBITS$), - .OBITS($OBITS$) + .IBITS(IBITS), + .OBITS(OBITS) ) impl ( .ap_clk(ap_clk), .ap_rst_n(ap_rst_n), diff --git a/finn-rtllib/dwc/sim/dwc_axi_tb.sv b/finn-rtllib/dwc/sim/dwc_axi_tb.sv index b47e5b2f83..64435c1900 100644 --- a/finn-rtllib/dwc/sim/dwc_axi_tb.sv +++ b/finn-rtllib/dwc/sim/dwc_axi_tb.sv @@ -33,7 +33,7 @@ *****************************************************************************/ module dwc_axi_tb; - localparam int unsigned DBITS = 4; + localparam int unsigned DBITS = 8; localparam int unsigned K = 3; typedef logic [DBITS-1:0] dat_t; From 529c335fadd2d738dbb568e305a7c5834c42f714 Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 24 Nov 2023 16:59:33 +0000 Subject: [PATCH 330/665] [DWC] Add additional sv file to list of files to copy --- .../custom_op/fpgadataflow/streamingdatawidthconverter_rtl.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/finn/custom_op/fpgadataflow/streamingdatawidthconverter_rtl.py b/src/finn/custom_op/fpgadataflow/streamingdatawidthconverter_rtl.py index e89bfd2526..4f592bafaa 100644 --- a/src/finn/custom_op/fpgadataflow/streamingdatawidthconverter_rtl.py +++ b/src/finn/custom_op/fpgadataflow/streamingdatawidthconverter_rtl.py @@ -259,7 +259,7 @@ def generate_hdl(self): ) as f: f.write(template) - sv_files = ["dwc_axi.sv"] + sv_files = ["dwc_axi.sv", "dwc.sv"] for sv_file in sv_files: shutil.copy(rtlsrc + "/" + sv_file, code_gen_dir) # set ipgen_path and ip_path so that HLS-Synth transformation @@ -280,6 +280,7 @@ def prepare_rtlsim(self): verilog_paths = [code_gen_dir] verilog_files = [ "dwc_axi.sv", + "dwc.sv", self.get_nodeattr("gen_top_module") + ".v", ] @@ -301,6 +302,7 @@ def code_generation_ipi(self): sourcefiles = [ "dwc_axi.sv", + "dwc.sv", self.get_nodeattr("gen_top_module") + ".v", ] From 9edcdc6eb23011e4b402fc0fdd9f8e5ed2bdb7d2 Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 28 Nov 2023 15:57:20 +0000 Subject: [PATCH 331/665] [Tests] Remove saving of waveform for dwc test --- tests/fpgadataflow/test_fpgadataflow_dwc.py | 1 - 1 file changed, 1 deletion(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_dwc.py b/tests/fpgadataflow/test_fpgadataflow_dwc.py index f3302132af..47332f069b 100644 --- a/tests/fpgadataflow/test_fpgadataflow_dwc.py +++ b/tests/fpgadataflow/test_fpgadataflow_dwc.py @@ -61,7 +61,6 @@ def make_single_dwc_modelwrapper(shape, inWidth, outWidth, finn_dtype, impl_styl inWidth=inWidth, outWidth=outWidth, dataType=str(finn_dtype.name), - rtlsim_trace="dwc.vcd", ) if not use_rtl_variant: # add additional attribute From e742430dee1d0a53d27a7a9c095968a71484d0f5 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 29 Nov 2023 11:47:21 +0000 Subject: [PATCH 332/665] [Transform] Generalize SpecializeLayers tranform --- .../fpgadataflow/specialize_layers.py | 168 +++++++++++------- .../test_fpgadataflow_addstreams.py | 4 +- .../test_fpgadataflow_fmpadding.py | 4 +- 3 files changed, 107 insertions(+), 69 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/specialize_layers.py b/src/finn/transformation/fpgadataflow/specialize_layers.py index d45d1dc600..4b2687faee 100644 --- a/src/finn/transformation/fpgadataflow/specialize_layers.py +++ b/src/finn/transformation/fpgadataflow/specialize_layers.py @@ -33,83 +33,121 @@ from qonnx.transformation.infer_datatypes import InferDataTypes from qonnx.transformation.infer_shapes import InferShapes +from finn.custom_op.fpgadataflow.hls import custom_op as hls_variants +from finn.custom_op.fpgadataflow.rtl import custom_op as rtl_variants -class SpecializeFMPadding(Transformation): - """Convert FMPadding layer to FMPadding_hls or FMPadding_rtl.""" +restricted_layers = [] +restricted_layers.append("MatrixVectorActivation") +restricted_layers.append("VectorVectorActivation") - def apply(self, model): - graph = model.graph - node_ind = 0 - graph_modified = False - for node in graph.node: - node_ind += 1 - if node.op_type == "FMPadding": - pad_input = node.input[0] - pad_output = node.output[0] - pad_inst = getCustomOp(node) - impl_style = pad_inst.get_nodeattr("preferred_impl_style") - if impl_style == "": - impl_style = "rtl" - optype = node.op_type + "_" + impl_style - new_node = helper.make_node( - optype, - [pad_input], - [pad_output], - domain="finn.custom_op.fpgadataflow." + impl_style, + +def _determine_impl_style(node): + optype = node.op_type + + # if rtl variant has specific restrictions + # use always the hls variant for now + if optype in restricted_layers: + return "hls" + + # check if there is an HLS or RTL variant or both + hls_variant = optype + "_hls" in hls_variants.keys() + rtl_variant = optype + "_rtl" in rtl_variants.keys() + + # check if user has specified a preferred_impl_style + inst = getCustomOp(node) + impl_style = inst.get_nodeattr("preferred_impl_style") + + # if impl_style not set, for "simple" layers always try + # to use rtl variant if available + if impl_style == "": + if rtl_variant: + return "rtl" + # but if no rtl variant, set impl_style to hls + elif hls_variant: + return "hls" + # if there is neither an rtl nor hls variant + # throw error + else: + raise Exception( + """Node {} with optype {} has no hw implementation variant)""".format( + node.name, optype ) - # add all attributes - for attribute in node.attribute: - if attribute.name != "preferred_impl_style": - new_node.attribute.append(attribute) - graph.node.insert(node_ind, new_node) - # remove old nodes - graph.node.remove(node) - graph_modified = True - if graph_modified: - model = model.transform(InferShapes()) - model = model.transform(InferDataTypes()) - return (model, graph_modified) + ) + + # check if user setting can be fulfilled + # otherwise change impl_style + if impl_style == "hls": + if hls_variant: + return "hls" + elif rtl_variant: + warn_str = """There is no HLS variant of %s. Node %s will automatically be + set to RTL variant.""" % ( + node.op_type, + node.name, + ) + warnings.warn(warn_str) + return "rtl" + else: + raise Exception( + """Node {} with optype {} has no hw implementation variant)""".format( + node.name, optype + ) + ) + elif impl_style == "rtl": + if rtl_variant: + return "rtl" + elif hls_variant: + warn_str = """There is no RTL variant of %s. Node %s will automatically be + set to HLS variant.""" % ( + node.op_type, + node.name, + ) + warnings.warn(warn_str) + return "hls" + else: + raise Exception( + """Node {} with optype {} has no hw implementation variant)""".format( + node.name, optype + ) + ) + else: + raise Exception( + """Invalid value for attribute preferred_impl_style! Is currently set to: {} + has to be set to one of the following value ("hls", "rtl")""".format( + impl_style + ) + ) -class SpecializeAddStreams(Transformation): - """Convert AddStreams layer to Addstreams_hls. There is no RTL variant of this node""" +class SpecializeLayers(Transformation): + """Specialize all layers to either HLS or RTL variants""" def apply(self, model): graph = model.graph node_ind = 0 graph_modified = False for node in graph.node: + # Skip nodes that are not hw layers + if not node.domain == "finn.custom_op.fpgadataflow": + continue node_ind += 1 - if node.op_type == "AddStreams": - add_input0 = node.input[0] - add_input1 = node.input[1] - add_output = node.output[0] - add_inst = getCustomOp(node) - impl_style = add_inst.get_nodeattr("preferred_impl_style") - if impl_style == "rtl": - warn_str = """There is no RTL variant of %s. Node %s will automatically be - set to HLS variant.""" % ( - node.op_type, - node.name, - ) - warnings.warn(warn_str) - if impl_style == "" or impl_style == "rtl": - impl_style = "hls" - optype = node.op_type + "_" + impl_style - new_node = helper.make_node( - optype, - [add_input0, add_input1], - [add_output], - domain="finn.custom_op.fpgadataflow." + impl_style, - ) - # add all attributes - for attribute in node.attribute: - if attribute.name != "preferred_impl_style": - new_node.attribute.append(attribute) - graph.node.insert(node_ind, new_node) - # remove old nodes - graph.node.remove(node) - graph_modified = True + impl_style = _determine_impl_style(node) + optype = node.op_type + "_" + impl_style + + new_node = helper.make_node( + optype, + node.input, + node.output, + domain="finn.custom_op.fpgadataflow." + impl_style, + ) + # add all attributes + for attribute in node.attribute: + if attribute.name != "preferred_impl_style": + new_node.attribute.append(attribute) + graph.node.insert(node_ind, new_node) + # remove old nodes + graph.node.remove(node) + graph_modified = True if graph_modified: model = model.transform(InferShapes()) model = model.transform(InferDataTypes()) diff --git a/tests/fpgadataflow/test_fpgadataflow_addstreams.py b/tests/fpgadataflow/test_fpgadataflow_addstreams.py index 9b9c4a1e85..ba3afe9c86 100644 --- a/tests/fpgadataflow/test_fpgadataflow_addstreams.py +++ b/tests/fpgadataflow/test_fpgadataflow_addstreams.py @@ -44,7 +44,7 @@ from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode -from finn.transformation.fpgadataflow.specialize_layers import SpecializeAddStreams +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers def make_addstreams_modelwrapper(ch, pe, idt): @@ -106,7 +106,7 @@ def test_fpgadataflow_addstreams(idt, ch, fold, exec_mode): model = make_addstreams_modelwrapper(ch, pe, idt) model.save("addstreams_hw.onnx") - model = model.transform(SpecializeAddStreams()) + model = model.transform(SpecializeLayers()) model.save("addstreams_hls.onnx") if exec_mode == "cppsim": diff --git a/tests/fpgadataflow/test_fpgadataflow_fmpadding.py b/tests/fpgadataflow/test_fpgadataflow_fmpadding.py index 4a4c46f3c3..3717f92e5d 100644 --- a/tests/fpgadataflow/test_fpgadataflow_fmpadding.py +++ b/tests/fpgadataflow/test_fpgadataflow_fmpadding.py @@ -47,7 +47,7 @@ from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode -from finn.transformation.fpgadataflow.specialize_layers import SpecializeFMPadding +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers from finn.util.basic import pynq_part_map test_pynq_board = os.getenv("PYNQ_BOARD", default="Pynq-Z1") @@ -129,7 +129,7 @@ def test_fpgadataflow_fmpadding(idim, pad, num_ch, simd, idt, mode, impl_style): odim_w = idim_w + pad_w model = make_single_fmpadding_modelwrapper(impl_style, idim, pad, num_ch, simd, idt) - model = model.transform(SpecializeFMPadding()) + model = model.transform(SpecializeLayers()) model = model.transform(InferShapes()) model = model.transform(SetExecMode(mode)) model = model.transform(GiveUniqueNodeNames()) From 14d306d74ce383ff38464fb410b3947611b30b2f Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 29 Nov 2023 14:07:38 +0000 Subject: [PATCH 333/665] [CustomOp] Initial draft of channelwise op in new class hierarchy --- src/finn/custom_op/fpgadataflow/__init__.py | 2 + .../custom_op/fpgadataflow/channelwise_op.py | 200 ++++++++ .../custom_op/fpgadataflow/hls/__init__.py | 2 + .../fpgadataflow/hls/channelwise_op_hls.py | 467 ++++++++++++++++++ .../test_fpgadataflow_channelwise_ops.py | 12 +- 5 files changed, 679 insertions(+), 4 deletions(-) create mode 100644 src/finn/custom_op/fpgadataflow/channelwise_op.py create mode 100644 src/finn/custom_op/fpgadataflow/hls/channelwise_op_hls.py diff --git a/src/finn/custom_op/fpgadataflow/__init__.py b/src/finn/custom_op/fpgadataflow/__init__.py index c433d83162..8f5ff0ac92 100644 --- a/src/finn/custom_op/fpgadataflow/__init__.py +++ b/src/finn/custom_op/fpgadataflow/__init__.py @@ -29,6 +29,7 @@ from finn.custom_op.fpgadataflow.addstreams import AddStreams from finn.custom_op.fpgadataflow.addstreams_batch import AddStreams_Batch +from finn.custom_op.fpgadataflow.channelwise_op import ChannelwiseOp from finn.custom_op.fpgadataflow.channelwise_op_batch import ChannelwiseOp_Batch from finn.custom_op.fpgadataflow.checksum import CheckSum from finn.custom_op.fpgadataflow.concat import StreamingConcat @@ -103,3 +104,4 @@ custom_op["FMPadding"] = FMPadding custom_op["AddStreams"] = AddStreams +custom_op["ChannelwiseOp"] = ChannelwiseOp diff --git a/src/finn/custom_op/fpgadataflow/channelwise_op.py b/src/finn/custom_op/fpgadataflow/channelwise_op.py new file mode 100644 index 0000000000..5d1d8febc1 --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/channelwise_op.py @@ -0,0 +1,200 @@ +# Copyright (C) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import numpy as np +import warnings +from qonnx.core.datatype import DataType + +from finn.custom_op.fpgadataflow.hwcustomop import HWCustomOp + +# ONNX i/o tensor shape assumptions for channelwise ops: +# input 0 is the input tensor, shape (..., NumChannels) +# input 1 is the channelwise parameter tensor, shape (NumChannels, params_per_channel) +# output 0 is the output tensor, shape (..., NumChannels) - same as input +# the ... here can be any shape (representing groups of vectors) + + +def get_smallest_possible(vals): + """Returns smallest (fewest bits) possible DataType that can represent + value. Prefers unsigned integers where possible.""" + vals = np.array(vals, dtype=np.float64) + for v in vals: + assert int(v) == v, "Error float value" + + for k in DataType.get_accumulator_dt_cands(): + dt = DataType[k] + + if dt in [DataType["BIPOLAR"], DataType["TERNARY"], DataType["FLOAT32"]]: + # not currently supported + continue + + if (dt.min() <= vals).all() and (vals <= dt.max()).all(): + return dt + + warnings.warn( + """InferChannelwiseLinearLayer: Output values may not be + representable with supported data types. + Setting maximum width data type available. + This will lead to errors if there are no constrains on the input + """ + ) + + if (0 <= vals).all(): + return DataType["UINT64"] + else: + return DataType["INT64"] + + +class ChannelwiseOp(HWCustomOp): + """Abstraction layer for HW implementation of ChannelwiseOp.""" + + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) + + def get_nodeattr_types(self): + my_attrs = { + # channelwise "map" function to apply: + # one of cmp_le, cmp_ge, add, mul + "Func": ("s", False, "cmp_le", {"cmp_le", "cmp_ge", "add", "mul"}), + "PE": ("i", True, 0), + "NumChannels": ("i", True, 0), + # string defining memory resource type for parameters + "ram_style": ("s", False, "distributed", {"distributed", "block"}), + # FINN DataTypes for inputs, weights, outputs + "inputDataType": ("s", True, ""), + "paramDataType": ("s", True, ""), + "outputDataType": ("s", True, ""), + # number of input vectors, examples: + # [1] is a single vector (like a FC layer with batch=1) + # [4] is four vectors (like a FC layer with batch=4) + # [1, 4, 4] is four * four vectors (like a conv layer with batch=1) + "numInputVectors": ("ints", False, [1]), + } + my_attrs.update(super().get_nodeattr_types()) + return my_attrs + + def calc_tmem(self): + """Calculates and returns TMEM, the depth of the memory used + to store the channelwise op parameters.""" + chn = self.get_nodeattr("NumChannels") + pe = self.get_nodeattr("PE") + return chn // pe + + def make_shape_compatible_op(self, model): + oshape = self.get_normal_output_shape() + # implement tensor with correct shape + return super().make_const_shape_op(oshape) + + def infer_node_datatype(self, model): + node = self.onnx_node + # check input datatype against property + idt = model.get_tensor_datatype(node.input[0]) + + exp_idt_name = self.get_nodeattr("inputDataType") + if exp_idt_name != idt.name: + func = self.get_nodeattr("Func") + assert func in ["add", "mul"], "Bad input DataType for ChannelwiseOp layer" + + self.set_nodeattr("inputDataType", idt.name) + # update the func in ['add','mul'] cases + + # get parameter ranges + param = model.get_initializer(node.input[1]) + param_min = min(param.flatten()) + param_max = max(param.flatten()) + + # set function and determine output data type + if func == "add": + out_min = idt.min() + param_min + out_max = idt.max() + param_max + odt = get_smallest_possible([out_min, out_max]) + elif func == "mul": + possible_limits = [] + possible_limits += [idt.min() * param_min] + possible_limits += [idt.min() * param_max] + possible_limits += [idt.max() * param_min] + possible_limits += [idt.max() * param_max] + odt = get_smallest_possible(possible_limits) + + self.set_nodeattr("outputDataType", odt.name) + + # set output datatype from property + odt = self.get_output_datatype() + model.set_tensor_datatype(node.output[0], odt) + + def verify_node(self): + pass + + def get_input_datatype(self, ind=0): + """Returns FINN DataType of input.""" + return DataType[self.get_nodeattr("inputDataType")] + + def get_output_datatype(self, ind=0): + """Returns FINN DataType of output.""" + return DataType[self.get_nodeattr("outputDataType")] + + def get_instream_width(self, ind=0): + i_bits = self.get_input_datatype().bitwidth() + return i_bits * self.get_nodeattr("PE") + + def get_outstream_width(self, ind=0): + o_bits = self.get_output_datatype().bitwidth() + return o_bits * self.get_nodeattr("PE") + + def get_folded_input_shape(self, ind=0): + ich = self.get_nodeattr("NumChannels") + pe = self.get_nodeattr("PE") + fold = ich // pe + vecs = list(self.get_nodeattr("numInputVectors")) + folded_input_shape = tuple(vecs + [fold, pe]) + return folded_input_shape + + def get_folded_output_shape(self, ind=0): + # same shape as input + return self.get_folded_input_shape() + + def get_normal_input_shape(self, ind=0): + ich = self.get_nodeattr("NumChannels") + vecs = list(self.get_nodeattr("numInputVectors")) + normal_input_shape = tuple(vecs + [ich]) + return normal_input_shape + + def get_normal_output_shape(self, ind=0): + # same shape as input + return self.get_normal_input_shape() + + def get_number_output_values(self): + nf = np.prod(self.get_folded_output_shape()[:-1]) + return nf + + def get_exp_cycles(self): + # Channels/PE * batch size * fmdim * fmdim + return np.prod(self.get_folded_output_shape()[:-1]) + + def execute_node(self, context, graph): + pass diff --git a/src/finn/custom_op/fpgadataflow/hls/__init__.py b/src/finn/custom_op/fpgadataflow/hls/__init__.py index f978a8616c..b5745c641d 100644 --- a/src/finn/custom_op/fpgadataflow/hls/__init__.py +++ b/src/finn/custom_op/fpgadataflow/hls/__init__.py @@ -27,6 +27,7 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from finn.custom_op.fpgadataflow.hls.addstreams_hls import AddStreams_hls +from finn.custom_op.fpgadataflow.hls.channelwise_op_hls import ChannelwiseOp_hls from finn.custom_op.fpgadataflow.hls.fmpadding_hls import FMPadding_hls custom_op = dict() @@ -35,3 +36,4 @@ # registered and plug in correctly into the infrastructure custom_op["FMPadding_hls"] = FMPadding_hls custom_op["AddStreams_hls"] = AddStreams_hls +custom_op["ChannelwiseOp_hls"] = ChannelwiseOp_hls diff --git a/src/finn/custom_op/fpgadataflow/hls/channelwise_op_hls.py b/src/finn/custom_op/fpgadataflow/hls/channelwise_op_hls.py new file mode 100644 index 0000000000..d816b6f15a --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/hls/channelwise_op_hls.py @@ -0,0 +1,467 @@ +# Copyright (C) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import numpy as np +import os +from math import ceil +from qonnx.core.datatype import DataType + +from finn.custom_op.fpgadataflow.channelwise_op import ChannelwiseOp +from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend +from finn.util.data_packing import ( + npy_to_rtlsim_input, + numpy_to_hls_code, + rtlsim_output_to_npy, +) + +# ONNX i/o tensor shape assumptions for channelwise ops: +# input 0 is the input tensor, shape (..., NumChannels) +# input 1 is the channelwise parameter tensor, shape (NumChannels, params_per_channel) +# output 0 is the output tensor, shape (..., NumChannels) - same as input +# the ... here can be any shape (representing groups of vectors) + + +class ChannelwiseOp_hls(ChannelwiseOp, HLSBackend): + """Class that corresponds to finn-hls Thresholding_Batch function. + It can implement a variety of channel-wise parametrized operations, + including Add, Mul and multi-thresholding. + """ + + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) + + def get_nodeattr_types(self): + my_attrs = {} + my_attrs.update(ChannelwiseOp.get_nodeattr_types(self)) + my_attrs.update(HLSBackend.get_nodeattr_types(self)) + return my_attrs + + def verify_node(self): + info_messages = [] + # verify that "backend" is set to "fpgadataflow" + backend_value = self.get_nodeattr("backend") + if backend_value == "fpgadataflow": + info_messages.append("Attribute backend is set correctly") + else: + info_messages.append('Attribute backend should be set to "fpgadataflow"') + + # verify that all necessary attributes exist + # TODO collect automatically from get_nodeattr_types + try: + self.get_nodeattr("code_gen_dir_cppsim") + self.get_nodeattr("executable_path") + self.get_nodeattr("NumChannels") + self.get_nodeattr("PE") + self.get_nodeattr("inputDataType") + self.get_nodeattr("paramDataType") + self.get_nodeattr("outputDataType") + info_messages.append("All necessary attributes exist") + except Exception: + info_messages.append("""The required Threshold_Batch attributes do not exist.""") + + return info_messages + + def bram_estimation(self): + """Calculates BRAM cost if resource set to BRAM""" + style = self.get_nodeattr("ram_style") + P = self.get_nodeattr("PE") + idt = self.get_input_datatype() + A = idt.bitwidth() + tmem = self.calc_tmem() + + if style == "block" and tmem > 1: + return int(ceil(A * P / 16)) * int(ceil(tmem / 1024)) + else: + return 0 + + def lut_estimation(self): + """Calculates LUT cost, taking memory resource type into account""" + # TODO add in/out FIFO contributions + style = self.get_nodeattr("ram_style") + P = self.get_nodeattr("PE") + idt = self.get_input_datatype() + A = idt.bitwidth() + tmem = self.calc_tmem() + # cost of comparators + comparator_cost = A * P + # cost of LUTRAM + if style == "distributed" and tmem > 1: + lutram_cost = P * A * int(ceil(tmem / 64)) + else: + lutram_cost = 0 + # total cost + return comparator_cost + lutram_cost + + def get_exp_cycles(self): + # Channels/PE * batch size * fmdim * fmdim + return np.prod(self.get_folded_output_shape()[:-1]) + + def get_template_param_values(self): + """Returns the template parameter values according to input, output and weight + data types.""" + ret = dict() + inp_hls_str = self.get_input_datatype().get_hls_datatype_str() + out_hls_str = self.get_output_datatype().get_hls_datatype_str() + # fill in TSrcI + ret["TSrcI"] = "Slice<%s>" % inp_hls_str + # fill in TDstI + ret["TDstI"] = "Slice<%s>" % out_hls_str + + return ret + + def get_hls_compatible_parameter_tensor(self, orig_param_vector): + """Convert the original numpy weight matrix orig_weight_matrix into + a form suitable for passing to the hlslib call: + * ensure chn % PE == 0 + * interleave rows between PEs + * reshape into (PE, TMEM) and return + """ + chn = self.get_nodeattr("NumChannels") + pe = self.get_nodeattr("PE") + tmem = chn // pe + assert chn % pe == 0, "Requirement NumChannels divisable by PE is violated." + assert ( + orig_param_vector.ndim == 1 + ), """Parameter vector dimension is {}. + Expected dimension: 1.""".format( + orig_param_vector.ndim + ) + + # if not self.get_input_datatype().signed(): + # # ensure all thresholds are nonnegative + # assert (orig_param_vector >= 0).all() + + # ensure all thresholds are integer + assert (orig_param_vector.astype(np.int32) == orig_param_vector).all() + ret = orig_param_vector + + assert ret.shape[0] == chn, "Cardinality of parameter vector is not as expected (chn)" + + # distribute rows between PEs + ret = ret.reshape(tmem, pe).transpose() + assert ( + ret.shape[0] == pe + ), """First dimension after distribution of the + rows between PEs is not as expected (pe)""" + assert ( + ret.shape[1] == tmem + ), """Second dimension after distribution of the + rows between PEs is not as expected (tmem)""" + + return ret.reshape(1, pe, tmem) + + def generate_params(self, model, path): + code_gen_dir = path + # save thresholds in params.h + parameters = model.get_initializer(self.onnx_node.input[1]) + parameter_tensor = self.get_hls_compatible_parameter_tensor(parameters) + pdt = DataType[self.get_nodeattr("paramDataType")] + + parameters_hls_code = numpy_to_hls_code(parameter_tensor, pdt, "parameters", False, True) + # get input data type + export_idt = self.get_input_datatype() + if self.get_input_datatype() == DataType["BIPOLAR"]: + export_idt = DataType["BINARY"] + idt_hls = export_idt.get_hls_datatype_str() + + # write parameters into params.h + f_params = open("{}/params.h".format(code_gen_dir), "w") + pdt_hls = pdt.get_hls_datatype_str() + # use binary to export bipolar activations + export_odt = self.get_output_datatype() + if self.get_output_datatype() == DataType["BIPOLAR"]: + export_odt = DataType["BINARY"] + odt_hls = export_odt.get_hls_datatype_str() + # get desired function + func = self.get_nodeattr("Func") + if func == "cmp_le": + func_str = "comp::less_equal<%s, %s>" % (idt_hls, pdt_hls) + elif func == "cmp_ge": + func_str = "comp::greater_equal<%s, %s>" % (idt_hls, pdt_hls) + elif func == "add": + func_str = "comp::add<%s, %s, %s>" % (odt_hls, odt_hls, odt_hls) + elif func == "mul": + func_str = "comp::mul<%s, %s, %s>" % (odt_hls, odt_hls, odt_hls) + else: + raise Exception( + """Invalid value for attribute Func! Is currently set to: {} + has to be set to one of the following value + ("cmp_le", "cmp_ge", "add", "mul")""".format( + func + ) + ) + f_params.write( + "static ChannelWiseOperation<{},{},{},{},{},{}> threshs \ + = ".format( + self.calc_tmem(), + self.get_nodeattr("PE"), + idt_hls, + pdt_hls, + odt_hls, + func_str, + ) + ) + f_params.write(parameters_hls_code) + f_params.close() + + def execute_node(self, context, graph): + mode = self.get_nodeattr("exec_mode") + node = self.onnx_node + + # TODO ensure codegen dir exists + if mode == "cppsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + elif mode == "rtlsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + + # create a npy file fore each input of the node (in_ind is input index) + in_ind = 0 + for inputs in node.input: + # it is assumed that the first input of the node is the data input + # the second input are the weights + # the third input are the thresholds + if in_ind == 0: + assert ( + str(context[inputs].dtype) == "float32" + ), """Input datatype is + not float32 as expected.""" + expected_inp_shape = self.get_folded_input_shape() + reshaped_input = context[inputs].reshape(expected_inp_shape) + export_idt = self.get_input_datatype() + # make copy before saving the array + reshaped_input = reshaped_input.copy() + np.save( + os.path.join(code_gen_dir, "input_{}.npy".format(in_ind)), + reshaped_input, + ) + elif in_ind > 2: + raise Exception("Unexpected input found for ChannelwiseOp_Batch") + in_ind += 1 + + if mode == "cppsim": + # execute the precompiled model + super().exec_precompiled_singlenode_model() + # load output npy file + super().npy_to_dynamic_output(context) + # reinterpret binary output as bipolar where needed + if self.get_output_datatype() == DataType["BIPOLAR"]: + out = context[node.output[0]] + out = 2 * out - 1 + context[node.output[0]] = out + assert ( + context[node.output[0]].shape == self.get_normal_output_shape() + ), """Output shape is not as expected""" + elif mode == "rtlsim": + sim = self.get_rtlsim() + nbits = self.get_instream_width() + inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) + super().reset_rtlsim(sim) + super().toggle_clk(sim) + output = self.rtlsim(sim, inp) + odt = self.get_output_datatype() + target_bits = odt.bitwidth() + packed_bits = self.get_outstream_width() + out_npy_path = "{}/output.npy".format(code_gen_dir) + out_shape = self.get_folded_output_shape() + rtlsim_output_to_npy(output, out_npy_path, odt, out_shape, packed_bits, target_bits) + + # load and reshape output + output = np.load(out_npy_path) + oshape = self.get_normal_output_shape() + output = np.asarray([output], dtype=np.float32).reshape(*oshape) + context[node.output[0]] = output + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + + def global_includes(self): + self.code_gen_dict["$GLOBALS$"] = ['#include "activations.hpp"'] + self.code_gen_dict["$GLOBALS$"] += ['#include "params.h"'] + + def defines(self, var): + numInputVectors = list(self.get_nodeattr("numInputVectors")) + numReps = numInputVectors[0] + self.code_gen_dict["$DEFINES$"] = [ + """#define NumChannels1 {}\n#define PE1 {}\n#define numReps {}""".format( + self.get_nodeattr("NumChannels"), + self.get_nodeattr("PE"), + numReps, + ) + ] + + def read_npy_data(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_input_datatype() + elem_bits = dtype.bitwidth() + packed_bits = self.get_instream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "float" + npy_in = "%s/input_0.npy" % code_gen_dir + self.code_gen_dict["$READNPYDATA$"] = [] + # note: the innermost dim is reversed for the input + self.code_gen_dict["$READNPYDATA$"].append( + 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s, false);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) + ) + + def strm_decl(self): + self.code_gen_dict["$STREAMDECLARATIONS$"] = [] + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> in0_{} ("in0_{}");'.format( + self.get_instream_width(), self.hls_sname(), self.hls_sname() + ) + ) + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> out_{} ("out_{}");'.format( + self.get_outstream_width(), self.hls_sname(), self.hls_sname() + ) + ) + + def docompute(self): + tmpl_args = self.get_template_param_values() + # TODO: why put some template parameters into defines and not others? + # should ImgDim be defined or just filled in here like we do now? + ishape = self.get_folded_input_shape() + if len(ishape) == 3: + spatial_dim = 1 + elif len(ishape) == 5: + spatial_dim = ishape[1] * ishape[2] + else: + raise Exception("""Unexpeted input shape""") + self.code_gen_dict["$DOCOMPUTE$"] = [ + """Thresholding_Batch<{}, NumChannels1, PE1, {}, {}> + (in0_{}, out_{}, threshs, numReps);""".format( + spatial_dim, + tmpl_args["TSrcI"], + tmpl_args["TDstI"], + self.hls_sname(), + self.hls_sname(), + ) + ] + + def dataoutstrm(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_output_datatype() + if dtype == DataType["BIPOLAR"]: + # use binary for bipolar storage + dtype = DataType["BINARY"] + elem_bits = dtype.bitwidth() + packed_bits = self.get_outstream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "float" + npy_out = "%s/output.npy" % code_gen_dir + shape = self.get_folded_output_shape() + shape_cpp_str = str(shape).replace("(", "{").replace(")", "}") + + # note: the innermost dim is not reversed for the output + self.code_gen_dict["$DATAOUTSTREAM$"] = [ + 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s", false);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + self.hls_sname(), + shape_cpp_str, + npy_out, + ) + ] + + def save_as_npy(self): + self.code_gen_dict["$SAVEASCNPY$"] = [] + + def blackboxfunction(self): + self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ + """void {}(hls::stream> &in0_{}, + hls::stream> &out_{} + )""".format( + self.onnx_node.name, + self.get_instream_width(), + self.hls_sname(), + self.get_outstream_width(), + self.hls_sname(), + ) + ] + + def pragmas(self): + self.code_gen_dict["$PRAGMAS$"] = [ + "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() + ] + self.code_gen_dict["$PRAGMAS$"].append( + "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() + ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") + + # the channelwise parameter tensor is acc_type [PE][TMEM][N_PARAMS_PER_CHANNEL] + # partition for parallel access along PE and N_PARAMS_PER_CHANNEL + # dimensions (dims 1 and 3) + self.code_gen_dict["$PRAGMAS$"].append( + ("#pragma HLS ARRAY_PARTITION variable=threshs.parameters " "complete dim=1") + ) + # set resource type + ram_style = self.get_nodeattr("ram_style") + pe = self.get_nodeattr("PE") + ich = self.get_nodeattr("NumChannels") + # if PE less than NumChannels, assign cores according to ram_style; + # otherwise if PE == NumChannels, Vivado HLS will unroll to FFs + if pe < ich: + if ram_style == "distributed": + self.code_gen_dict["$PRAGMAS$"].append( + ("#pragma HLS RESOURCE variable=threshs.parameters " "core=ROM_2P_LUTRAM") + ) + elif ram_style == "block": + self.code_gen_dict["$PRAGMAS$"].append( + ("#pragma HLS RESOURCE variable=threshs.parameters " "core=ROM_2P_BRAM") + ) + else: + raise Exception( + """Invalid value for attribute ram_style! Is currently set to: {} + has to be set to one of ("block", "distributed")""".format( + ram_style + ) + ) diff --git a/tests/fpgadataflow/test_fpgadataflow_channelwise_ops.py b/tests/fpgadataflow/test_fpgadataflow_channelwise_ops.py index 186a6af42c..af9628c644 100644 --- a/tests/fpgadataflow/test_fpgadataflow_channelwise_ops.py +++ b/tests/fpgadataflow/test_fpgadataflow_channelwise_ops.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (c) 2020-2022, Xilinx, Inc. +# Copyright (C) 2023, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -45,6 +46,7 @@ from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers def make_modelwrapper(C, pe, idt, odt, pdt, func, vecs): @@ -56,7 +58,7 @@ def make_modelwrapper(C, pe, idt, odt, pdt, func, vecs): node_inp_list = ["inp", "const"] node = helper.make_node( - "ChannelwiseOp_Batch", + "ChannelwiseOp", node_inp_list, ["outp"], domain="finn.custom_op.fpgadataflow", @@ -68,6 +70,7 @@ def make_modelwrapper(C, pe, idt, odt, pdt, func, vecs): outputDataType=odt.name, paramDataType=pdt.name, numInputVectors=vecs, + preferred_impl_style="hls", ) graph = helper.make_graph(nodes=[node], name="graph", inputs=[inp], outputs=[outp]) @@ -115,6 +118,7 @@ def test_fpgadataflow_channelwise_ops(idt, act, pdt, nf, ich, func, vecs, exec_m odt = act model = make_modelwrapper(C, pe, idt, odt, pdt, func, vecs) + model = model.transform(SpecializeLayers()) if exec_mode == "cppsim": model = model.transform(PrepareCppSim()) @@ -150,9 +154,9 @@ def test_fpgadataflow_channelwise_ops(idt, act, pdt, nf, ich, func, vecs, exec_m if exec_mode == "rtlsim": hls_synt_res_est = model.analysis(hls_synth_res_estimation) - assert "ChannelwiseOp_Batch_0" in hls_synt_res_est + assert "ChannelwiseOp_hls_0" in hls_synt_res_est - node = model.get_nodes_by_op_type("ChannelwiseOp_Batch")[0] + node = model.get_nodes_by_op_type("ChannelwiseOp_hls")[0] inst = getCustomOp(node) cycles_rtlsim = inst.get_nodeattr("cycles_rtlsim") exp_cycles_dict = model.analysis(exp_cycles_per_layer) From 3bf09c95410427b52b32c85ffc45837eec0b9a61 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 29 Nov 2023 14:51:56 +0000 Subject: [PATCH 334/665] [CustomOp] Initial draft of DuplicateStreams in new class hierarchy --- src/finn/custom_op/fpgadataflow/__init__.py | 2 + .../fpgadataflow/duplicatestreams.py | 168 ++++++++++ .../custom_op/fpgadataflow/hls/__init__.py | 4 +- .../fpgadataflow/hls/duplicatestreams_hls.py | 316 ++++++++++++++++++ .../test_fpgadataflow_duplicatestreams.py | 18 +- 5 files changed, 501 insertions(+), 7 deletions(-) create mode 100644 src/finn/custom_op/fpgadataflow/duplicatestreams.py create mode 100644 src/finn/custom_op/fpgadataflow/hls/duplicatestreams_hls.py diff --git a/src/finn/custom_op/fpgadataflow/__init__.py b/src/finn/custom_op/fpgadataflow/__init__.py index 8f5ff0ac92..305faaacf9 100644 --- a/src/finn/custom_op/fpgadataflow/__init__.py +++ b/src/finn/custom_op/fpgadataflow/__init__.py @@ -43,6 +43,7 @@ ConvolutionInputGenerator_rtl, ) from finn.custom_op.fpgadataflow.downsampler import DownSampler +from finn.custom_op.fpgadataflow.duplicatestreams import DuplicateStreams from finn.custom_op.fpgadataflow.duplicatestreams_batch import DuplicateStreams_Batch from finn.custom_op.fpgadataflow.eltwise import StreamingEltwise from finn.custom_op.fpgadataflow.fmpadding import FMPadding @@ -105,3 +106,4 @@ custom_op["FMPadding"] = FMPadding custom_op["AddStreams"] = AddStreams custom_op["ChannelwiseOp"] = ChannelwiseOp +custom_op["DuplicateStreams"] = DuplicateStreams diff --git a/src/finn/custom_op/fpgadataflow/duplicatestreams.py b/src/finn/custom_op/fpgadataflow/duplicatestreams.py new file mode 100644 index 0000000000..a4cf72df03 --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/duplicatestreams.py @@ -0,0 +1,168 @@ +# Copyright (C) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import numpy as np +import warnings +from qonnx.core.datatype import DataType + +from finn.custom_op.fpgadataflow.hwcustomop import HWCustomOp + + +class DuplicateStreams(HWCustomOp): + """Abstraction layer for HW implementation of DuplicateStreams""" + + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) + + def get_nodeattr_types(self): + my_attrs = { + "NumChannels": ("i", True, 0), + "PE": ("i", True, 0), + # how many duplicated output streams to create + "NumOutputStreams": ("i", True, 0), + # FINN DataTypes for input + "inputDataType": ("s", True, ""), + # number of input vectors, examples: + # [1] is a single vector (like a FC layer with batch=1) + # [4] is four vectors (like a FC layer with batch=4) + # [1, 4, 4] is four * four vectors (like a conv layer with batch=1) + "numInputVectors": ("ints", False, [1]), + } + my_attrs.update(super().get_nodeattr_types()) + return my_attrs + + def get_num_output_streams(self): + return self.get_nodeattr("NumOutputStreams") + + def get_normal_input_shape(self, ind=0): + ch = self.get_nodeattr("NumChannels") + vecs = list(self.get_nodeattr("numInputVectors")) + ishape = tuple(vecs + [ch]) + return ishape + + def get_folded_input_shape(self, ind=0): + ch = self.get_nodeattr("NumChannels") + pe = self.get_nodeattr("PE") + vecs = list(self.get_nodeattr("numInputVectors")) + assert ch % pe == 0, "PE must divide NumChannels" + folds = int(ch / pe) + folded_ishape = tuple(vecs + [folds, pe]) + return folded_ishape + + def get_normal_output_shape(self, ind=0): + # since the output shape of both out streams are the same + # return independently from index + return self.get_normal_input_shape() + + def get_folded_output_shape(self, ind=0): + # since the output shape of both out streams are the same + # return independently from index + return self.get_folded_input_shape() + + def make_shape_compatible_op(self, model): + exp_ishape = self.get_normal_input_shape() + ishape = tuple(model.get_tensor_shape(self.onnx_node.input[0])) + assert ishape == exp_ishape, "Unexpected input shape." + num_out = self.get_num_output_streams() + assert len(self.onnx_node.output) == num_out, "Unexpected number of outputs" + + oshape = self.get_normal_output_shape() + ret = super().make_const_shape_op(oshape) + ret.output[:] = self.onnx_node.output + return ret + + def infer_node_datatype(self, model): + node = self.onnx_node + idt = model.get_tensor_datatype(node.input[0]) + if idt != self.get_input_datatype(): + warn_str = "inputDataType changing for %s: %s -> %s " % ( + node.name, + str(self.get_input_datatype()), + str(idt), + ) + warnings.warn(warn_str) + self.set_nodeattr("inputDataType", idt.name) + odt = self.get_output_datatype() + for my_out in self.onnx_node.output: + model.set_tensor_datatype(my_out, odt) + + def verify_node(self): + pass + + def get_input_datatype(self, ind=0): + """Returns FINN DataType of input.""" + return DataType[self.get_nodeattr("inputDataType")] + + def get_output_datatype(self, ind=0): + """Returns FINN DataType of output.""" + return DataType[self.get_nodeattr("inputDataType")] + + def get_instream_width(self, ind=0): + """Returns input stream width.""" + ibits = self.get_input_datatype().bitwidth() + pe = self.get_nodeattr("PE") + in_width = pe * ibits + return in_width + + def get_outstream_width(self, ind=0): + """Returns output stream width.""" + obits = self.get_output_datatype().bitwidth() + pe = self.get_nodeattr("PE") + out_width = pe * obits + return out_width + + def get_number_output_values(self): + return self.get_num_output_streams() * np.prod(self.get_folded_output_shape()[1:-1]) + + def get_exp_cycles(self): + # Channels/PE * batch size * fmdim * fmdim + return np.prod(self.get_folded_output_shape()[:-1]) + + def execute_node(self, context, graph): + pass + + def get_verilog_top_module_intf_names(self): + intf_names = super().get_verilog_top_module_intf_names() + n_outputs = self.get_num_output_streams() + sname = self.hls_sname() + intf_names["m_axis"] = [] + for i in range(n_outputs): + intf_names["m_axis"].append( + ("out%d_%s" % (i, sname), self.get_outstream_width_padded()) + ) + return intf_names + + def derive_characteristic_fxns(self, period): + n_inps = np.prod(self.get_folded_input_shape()[:-1]) + io_dict = { + "inputs": { + "in0": [0 for i in range(n_inps)], + }, + "outputs": {"out0": [], "out1": []}, + } + super().derive_characteristic_fxns(period, override_rtlsim_dict=io_dict) diff --git a/src/finn/custom_op/fpgadataflow/hls/__init__.py b/src/finn/custom_op/fpgadataflow/hls/__init__.py index b5745c641d..450cf21f77 100644 --- a/src/finn/custom_op/fpgadataflow/hls/__init__.py +++ b/src/finn/custom_op/fpgadataflow/hls/__init__.py @@ -28,12 +28,14 @@ from finn.custom_op.fpgadataflow.hls.addstreams_hls import AddStreams_hls from finn.custom_op.fpgadataflow.hls.channelwise_op_hls import ChannelwiseOp_hls +from finn.custom_op.fpgadataflow.hls.duplicatestreams_hls import DuplicateStreams_hls from finn.custom_op.fpgadataflow.hls.fmpadding_hls import FMPadding_hls custom_op = dict() # make sure new HLSCustomOp subclasses are imported here so that they get # registered and plug in correctly into the infrastructure -custom_op["FMPadding_hls"] = FMPadding_hls custom_op["AddStreams_hls"] = AddStreams_hls +custom_op["DuplicateStreams_hls"] = DuplicateStreams_hls custom_op["ChannelwiseOp_hls"] = ChannelwiseOp_hls +custom_op["FMPadding_hls"] = FMPadding_hls diff --git a/src/finn/custom_op/fpgadataflow/hls/duplicatestreams_hls.py b/src/finn/custom_op/fpgadataflow/hls/duplicatestreams_hls.py new file mode 100644 index 0000000000..4468ca152c --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/hls/duplicatestreams_hls.py @@ -0,0 +1,316 @@ +# Copyright (C) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import numpy as np +import os + +from finn.custom_op.fpgadataflow.duplicatestreams import DuplicateStreams +from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend +from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy + + +class DuplicateStreams_hls(DuplicateStreams, HLSBackend): + """Class that corresponds to finn-hlslib function of the same name.""" + + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) + + def get_nodeattr_types(self): + my_attrs = {} + my_attrs.update(DuplicateStreams.get_nodeattr_types(self)) + my_attrs.update(HLSBackend.get_nodeattr_types(self)) + return my_attrs + + def verify_node(self): + info_messages = [] + # verify that "backend" is set to "fpgadataflow" + backend_value = self.get_nodeattr("backend") + if backend_value == "fpgadataflow": + info_messages.append("Attribute backend is set correctly") + else: + info_messages.append('Attribute backend should be set to "fpgadataflow"') + + # verify that all necessary attributes exist + try: + self.get_nodeattr("code_gen_dir_cppsim") + self.get_nodeattr("executable_path") + self.get_nodeattr("NumChannels") + self.get_nodeattr("PE") + self.get_nodeattr("NumOutputStreams") + self.get_nodeattr("inputDataType") + info_messages.append("All necessary attributes exist") + except Exception: + info_messages.append("""The required GlobalAccPool_Batch attributes do not exist.""") + + return info_messages + + def get_exp_cycles(self): + # Channels/PE * batch size * fmdim * fmdim + return np.prod(self.get_folded_output_shape()[:-1]) + + def generate_params(self, model, path): + n_outputs = self.get_num_output_streams() + inp_streams = [] + commands = [] + o_stream_w = self.get_outstream_width() + i_stream_w = self.get_instream_width() + in_stream = "hls::stream > &in0" % (i_stream_w) + inp_streams.append(in_stream) + commands.append("ap_uint<%d> e = in0.read();" % i_stream_w) + iters = self.get_number_output_values() // self.get_num_output_streams() + for i in range(n_outputs): + out_stream = "hls::stream > &out%d" % (o_stream_w, i) + inp_streams.append(out_stream) + cmd = "out%d.write(e);" % i + commands.append(cmd) + + impl_hls_code = [] + impl_hls_code.append("void DuplicateStreamsCustom(") + impl_hls_code.append(",".join(inp_streams)) + impl_hls_code.append(") {") + impl_hls_code.append("for(unsigned int i = 0; i < %d; i++) {" % iters) + impl_hls_code.append("#pragma HLS PIPELINE II=1") + impl_hls_code.append("\n".join(commands)) + impl_hls_code.append("}") + impl_hls_code.append("}") + impl_hls_code = "\n".join(impl_hls_code) + + impl_filename = "{}/duplicate_impl.hpp".format(path) + f_impl = open(impl_filename, "w") + f_impl.write(impl_hls_code) + f_impl.close() + + def execute_node(self, context, graph): + mode = self.get_nodeattr("exec_mode") + node = self.onnx_node + exp_ishape = self.get_normal_input_shape() + exp_oshape = self.get_normal_output_shape() + folded_ishape = self.get_folded_input_shape() + n_outputs = self.get_num_output_streams() + + if mode == "cppsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + elif mode == "rtlsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + + inp = context[node.input[0]] + assert str(inp.dtype) == "float32", "Input datatype is not float32" + assert inp.shape == exp_ishape, """Input shape doesn't match expected shape .""" + export_idt = self.get_input_datatype() + # reshape input into folded form + inp = inp.reshape(folded_ishape) + # make copy before saving array + reshaped_input = inp.copy() + np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input) + + if mode == "cppsim": + # execute the precompiled model + super().exec_precompiled_singlenode_model() + # load output npy file + super().npy_to_dynamic_outputs(context, ["output%d.npy" % i for i in range(n_outputs)]) + for i in range(n_outputs): + assert ( + context[node.output[i]].shape == exp_oshape + ), "cppsim \ + did not produce expected output shape" + elif mode == "rtlsim": + sim = self.get_rtlsim() + nbits = self.get_instream_width() + rtlsim_inp = npy_to_rtlsim_input( + "{}/input_0.npy".format(code_gen_dir), export_idt, nbits + ) + super().reset_rtlsim(sim) + super().toggle_clk(sim) + rtlsim_dict = { + "inputs": {"in0": rtlsim_inp}, + "outputs": {}, + } + for i in range(n_outputs): + rtlsim_dict["outputs"]["out%d" % i] = [] + self.rtlsim_multi_io(sim, rtlsim_dict) + odt = self.get_output_datatype() + target_bits = odt.bitwidth() + packed_bits = self.get_outstream_width() + out_shape = self.get_folded_output_shape() + for i in range(n_outputs): + out_npy_path = "%s/output%d.npy" % (code_gen_dir, i) + rtlsim_output_to_npy( + rtlsim_dict["outputs"]["out%d" % i], + out_npy_path, + odt, + out_shape, + packed_bits, + target_bits, + ) + # load and reshape output 0 + output = np.load(out_npy_path) + output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) + context[node.output[i]] = output + + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + + assert ( + context[node.output[0]].shape == exp_oshape + ), """Output0 shape doesn't match expected shape.""" + assert ( + context[node.output[1]].shape == exp_oshape + ), """Output1 shape doesn't match expected shape.""" + + def global_includes(self): + self.code_gen_dict["$GLOBALS$"] = ['#include "duplicate_impl.hpp"'] + + def defines(self, var): + self.code_gen_dict["$DEFINES$"] = [] + + def read_npy_data(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_input_datatype() + elem_bits = dtype.bitwidth() + packed_bits = self.get_instream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "float" + npy_in = "%s/input_0.npy" % code_gen_dir + self.code_gen_dict["$READNPYDATA$"] = [] + self.code_gen_dict["$READNPYDATA$"].append( + 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) + ) + + def strm_decl(self): + n_outputs = self.get_num_output_streams() + self.code_gen_dict["$STREAMDECLARATIONS$"] = [] + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> in0_{} ("in0_{}");'.format( + self.get_instream_width(), self.hls_sname(), self.hls_sname() + ) + ) + for i in range(n_outputs): + out_name = "out%d_%s" % (i, self.hls_sname()) + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> %s ("%s");' + % (self.get_outstream_width(), out_name, out_name) + ) + + def docompute(self): + n_outputs = self.get_num_output_streams() + ostreams = [] + for i in range(n_outputs): + ostreams.append("out%d_%s" % (i, self.hls_sname())) + dc = "DuplicateStreamsCustom(in0_%s, %s);" % ( + self.hls_sname(), + ",".join(ostreams), + ) + self.code_gen_dict["$DOCOMPUTE$"] = [dc] + + def dataoutstrm(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_output_datatype() + elem_bits = dtype.bitwidth() + packed_bits = self.get_outstream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "float" + n_outputs = self.get_num_output_streams() + oshape = self.get_folded_output_shape() + oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") + outstrm_code = [] + + for i in range(n_outputs): + out_name = "out%d_%s" % (i, self.hls_sname()) + npy_out = "%s/output%d.npy" % (code_gen_dir, i) + outstrm_code.append( + 'apintstream2npy<%s, %s, %d, %s>(%s, %s, "%s");' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + out_name, + oshape_cpp_str, + npy_out, + ) + ) + + self.code_gen_dict["$DATAOUTSTREAM$"] = outstrm_code + + def save_as_npy(self): + self.code_gen_dict["$SAVEASCNPY$"] = [] + + def blackboxfunction(self): + n_outputs = self.get_num_output_streams() + inp_streams = [] + o_stream_w = self.get_outstream_width() + i_stream_w = self.get_instream_width() + in_stream = "hls::stream > &in0_%s" % (i_stream_w, self.hls_sname()) + inp_streams.append(in_stream) + for i in range(n_outputs): + out_stream = "hls::stream > &out%d_%s" % ( + o_stream_w, + i, + self.hls_sname(), + ) + inp_streams.append(out_stream) + + self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ + """void {}({})""".format( + self.onnx_node.name, + ",".join(inp_streams), + ) + ] + + def pragmas(self): + n_outputs = self.get_num_output_streams() + self.code_gen_dict["$PRAGMAS$"] = [ + "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() + ] + for i in range(n_outputs): + self.code_gen_dict["$PRAGMAS$"].append( + "#pragma HLS INTERFACE axis port=out%d_%s" % (i, self.hls_sname()) + ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") diff --git a/tests/fpgadataflow/test_fpgadataflow_duplicatestreams.py b/tests/fpgadataflow/test_fpgadataflow_duplicatestreams.py index 27bab93fb6..ac96380da3 100644 --- a/tests/fpgadataflow/test_fpgadataflow_duplicatestreams.py +++ b/tests/fpgadataflow/test_fpgadataflow_duplicatestreams.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (c) 2020-2022, Xilinx +# Copyright (C) 2023, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -46,9 +47,10 @@ from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers -def make_dupstreams_modelwrapper(ch, pe, idim, idt, n_dupl): +def make_dupstreams_modelwrapper(ch, pe, idim, idt, n_dupl, impl_style): shape = [1, idim, idim, ch] inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, shape) out_names = [] @@ -59,7 +61,7 @@ def make_dupstreams_modelwrapper(ch, pe, idim, idt, n_dupl): out_vi.append(helper.make_tensor_value_info(outp_name, TensorProto.FLOAT, shape)) dupstrm_node = helper.make_node( - "DuplicateStreams_Batch", + "DuplicateStreams", ["inp"], out_names, domain="finn.custom_op.fpgadataflow", @@ -69,6 +71,7 @@ def make_dupstreams_modelwrapper(ch, pe, idim, idt, n_dupl): PE=pe, inputDataType=idt.name, numInputVectors=[1, idim, idim], + preferred_impl_style=impl_style, ) graph = helper.make_graph(nodes=[dupstrm_node], name="graph", inputs=[inp], outputs=out_vi) @@ -99,9 +102,11 @@ def prepare_inputs(input_tensor, idt): @pytest.mark.parametrize("n_dupl", [2, 3]) # execution mode @pytest.mark.parametrize("exec_mode", ["cppsim", "rtlsim"]) +# impl_style +@pytest.mark.parametrize("impl_style", ["hls"]) @pytest.mark.fpgadataflow @pytest.mark.vivado -def test_fpgadataflow_duplicatestreams(idt, ch, fold, imdim, n_dupl, exec_mode): +def test_fpgadataflow_duplicatestreams(idt, ch, fold, imdim, n_dupl, exec_mode, impl_style): if fold == -1: pe = 1 else: @@ -111,7 +116,8 @@ def test_fpgadataflow_duplicatestreams(idt, ch, fold, imdim, n_dupl, exec_mode): # generate input data x = gen_finn_dt_tensor(idt, (1, imdim, imdim, ch)) - model = make_dupstreams_modelwrapper(ch, pe, imdim, idt, n_dupl) + model = make_dupstreams_modelwrapper(ch, pe, imdim, idt, n_dupl, impl_style) + model = model.transform(SpecializeLayers()) if exec_mode == "cppsim": model = model.transform(PrepareCppSim()) @@ -136,7 +142,7 @@ def test_fpgadataflow_duplicatestreams(idt, ch, fold, imdim, n_dupl, exec_mode): assert (y == expected_y).all(), exec_mode + " failed" if exec_mode == "rtlsim": - node = model.get_nodes_by_op_type("DuplicateStreams_Batch")[0] + node = model.get_nodes_by_op_type("DuplicateStreams_hls")[0] inst = getCustomOp(node) cycles_rtlsim = inst.get_nodeattr("cycles_rtlsim") exp_cycles_dict = model.analysis(exp_cycles_per_layer) From 43fa39747030b0a54d8d4e81067b5eea0a110a6c Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 29 Nov 2023 15:26:46 +0000 Subject: [PATCH 335/665] [CustomOp] Initial draft of GlobalAccPool in new class hierarchy --- src/finn/custom_op/fpgadataflow/__init__.py | 2 + .../custom_op/fpgadataflow/globalaccpool.py | 155 +++++++++++ .../custom_op/fpgadataflow/hls/__init__.py | 4 +- .../fpgadataflow/hls/globalaccpool_hls.py | 255 ++++++++++++++++++ .../test_fpgadataflow_globalaccpool.py | 18 +- 5 files changed, 427 insertions(+), 7 deletions(-) create mode 100644 src/finn/custom_op/fpgadataflow/globalaccpool.py create mode 100644 src/finn/custom_op/fpgadataflow/hls/globalaccpool_hls.py diff --git a/src/finn/custom_op/fpgadataflow/__init__.py b/src/finn/custom_op/fpgadataflow/__init__.py index 305faaacf9..b939ea0c56 100644 --- a/src/finn/custom_op/fpgadataflow/__init__.py +++ b/src/finn/custom_op/fpgadataflow/__init__.py @@ -49,6 +49,7 @@ from finn.custom_op.fpgadataflow.fmpadding import FMPadding from finn.custom_op.fpgadataflow.fmpadding_batch import FMPadding_Batch from finn.custom_op.fpgadataflow.fmpadding_rtl import FMPadding_rtl +from finn.custom_op.fpgadataflow.globalaccpool import GlobalAccPool from finn.custom_op.fpgadataflow.globalaccpool_batch import GlobalAccPool_Batch from finn.custom_op.fpgadataflow.iodma import IODMA from finn.custom_op.fpgadataflow.labelselect_batch import LabelSelect_Batch @@ -107,3 +108,4 @@ custom_op["AddStreams"] = AddStreams custom_op["ChannelwiseOp"] = ChannelwiseOp custom_op["DuplicateStreams"] = DuplicateStreams +custom_op["GlobalAccPool"] = GlobalAccPool diff --git a/src/finn/custom_op/fpgadataflow/globalaccpool.py b/src/finn/custom_op/fpgadataflow/globalaccpool.py new file mode 100644 index 0000000000..c90385e9f0 --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/globalaccpool.py @@ -0,0 +1,155 @@ +# Copyright (C) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import numpy as np +import warnings +from qonnx.core.datatype import DataType + +from finn.custom_op.fpgadataflow.hwcustomop import HWCustomOp + + +class GlobalAccPool(HWCustomOp): + """Abstraction layer for HW implementation of GlobalAccPool""" + + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) + + def get_nodeattr_types(self): + my_attrs = { + "NumChannels": ("i", True, 0), + "PE": ("i", True, 0), + # FINN DataTypes for input + "inputDataType": ("s", True, ""), + # number of input vectors, examples: + # [1] is a single vector (like a FC layer with batch=1) + # [4] is four vectors (like a FC layer with batch=4) + # [1, 4, 4] is four * four vectors (like a conv layer with batch=1) + "numInputVectors": ("ints", False, [1]), + } + my_attrs.update(super().get_nodeattr_types()) + return my_attrs + + def get_normal_input_shape(self, ind=0): + ch = self.get_nodeattr("NumChannels") + vecs = list(self.get_nodeattr("numInputVectors")) + ishape = tuple(vecs + [ch]) + return ishape + + def get_folded_input_shape(self, ind=0): + ch = self.get_nodeattr("NumChannels") + pe = self.get_nodeattr("PE") + vecs = list(self.get_nodeattr("numInputVectors")) + assert ch % pe == 0, "PE must divide NumChannels" + folds = int(ch / pe) + folded_ishape = tuple(vecs + [folds, pe]) + return folded_ishape + + def get_normal_output_shape(self, ind=0): + ch = self.get_nodeattr("NumChannels") + vecs = list(self.get_nodeattr("numInputVectors")) + if len(vecs) == 1: + oshape = tuple(vecs + [ch]) + elif len(vecs) == 3: + oshape = tuple([vecs[0]] + [1, 1, ch]) + return oshape + + def get_folded_output_shape(self, ind=0): + ch = self.get_nodeattr("NumChannels") + pe = self.get_nodeattr("PE") + unfolded_shape = list(self.get_normal_output_shape()) + assert ch % pe == 0, "PE must divide NumChannels" + folds = int(ch / pe) + oshape = tuple(unfolded_shape[:-1] + [folds, pe]) + return oshape + + def make_shape_compatible_op(self, model): + exp_ishape = self.get_normal_input_shape() + oshape = self.get_normal_output_shape() + ishape = tuple(model.get_tensor_shape(self.onnx_node.input[0])) + assert ishape == exp_ishape, "Unexpected input shape." + return super().make_const_shape_op(oshape) + + def infer_node_datatype(self, model): + node = self.onnx_node + idt = model.get_tensor_datatype(node.input[0]) + if idt != self.get_input_datatype(): + warn_str = "inputDataType changing for %s: %s -> %s " % ( + node.name, + str(self.get_input_datatype()), + str(idt), + ) + warnings.warn(warn_str) + self.set_nodeattr("inputDataType", idt.name) + odt = self.get_output_datatype() + model.set_tensor_datatype(self.onnx_node.output[0], odt) + + def verify_node(self): + pass + + def get_input_datatype(self, ind=0): + """Returns FINN DataType of input.""" + return DataType[self.get_nodeattr("inputDataType")] + + def get_output_datatype(self, ind=0): + """Returns FINN DataType of output.""" + # determine data type from image size and input type + idt = DataType[self.get_nodeattr("inputDataType")] + vecs = list(self.get_nodeattr("numInputVectors")) + npixels = vecs[-1] * vecs[-2] + if idt.signed(): + extreme_value = npixels * idt.min() + else: + extreme_value = npixels * idt.max() + return DataType.get_smallest_possible(extreme_value) + + def get_instream_width(self, ind=0): + """Returns input stream width.""" + ibits = self.get_input_datatype().bitwidth() + pe = self.get_nodeattr("PE") + in_width = pe * ibits + return in_width + + def get_outstream_width(self, ind=0): + """Returns output stream width.""" + obits = self.get_output_datatype().bitwidth() + pe = self.get_nodeattr("PE") + out_width = pe * obits + return out_width + + def get_number_output_values(self): + return np.prod(self.get_folded_output_shape()[1:-1]) + + def get_exp_cycles(self): + # Channels/PE * batch size * idim * idim + Channels/PE + ch = self.get_nodeattr("NumChannels") + pe = self.get_nodeattr("PE") + folds = int(ch / pe) + return int(np.prod(self.get_folded_input_shape()[:-1]) + folds) + + def execute_node(self, context, graph): + pass diff --git a/src/finn/custom_op/fpgadataflow/hls/__init__.py b/src/finn/custom_op/fpgadataflow/hls/__init__.py index 450cf21f77..075449d589 100644 --- a/src/finn/custom_op/fpgadataflow/hls/__init__.py +++ b/src/finn/custom_op/fpgadataflow/hls/__init__.py @@ -30,12 +30,14 @@ from finn.custom_op.fpgadataflow.hls.channelwise_op_hls import ChannelwiseOp_hls from finn.custom_op.fpgadataflow.hls.duplicatestreams_hls import DuplicateStreams_hls from finn.custom_op.fpgadataflow.hls.fmpadding_hls import FMPadding_hls +from finn.custom_op.fpgadataflow.hls.globalaccpool_hls import GlobalAccPool_hls custom_op = dict() # make sure new HLSCustomOp subclasses are imported here so that they get # registered and plug in correctly into the infrastructure custom_op["AddStreams_hls"] = AddStreams_hls -custom_op["DuplicateStreams_hls"] = DuplicateStreams_hls custom_op["ChannelwiseOp_hls"] = ChannelwiseOp_hls +custom_op["DuplicateStreams_hls"] = DuplicateStreams_hls custom_op["FMPadding_hls"] = FMPadding_hls +custom_op["GlobalAccPool_hls"] = GlobalAccPool_hls diff --git a/src/finn/custom_op/fpgadataflow/hls/globalaccpool_hls.py b/src/finn/custom_op/fpgadataflow/hls/globalaccpool_hls.py new file mode 100644 index 0000000000..4814c09e59 --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/hls/globalaccpool_hls.py @@ -0,0 +1,255 @@ +# Copyright (C) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import numpy as np +import os + +from finn.custom_op.fpgadataflow.globalaccpool import GlobalAccPool +from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend +from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy + + +class GlobalAccPool_hls(GlobalAccPool, HLSBackend): + """Class that corresponds to finn-hlslib AccPool_Batch function.""" + + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) + + def get_nodeattr_types(self): + my_attrs = {} + my_attrs.update(GlobalAccPool.get_nodeattr_types(self)) + my_attrs.update(HLSBackend.get_nodeattr_types(self)) + return my_attrs + + def verify_node(self): + info_messages = [] + # verify that "backend" is set to "fpgadataflow" + backend_value = self.get_nodeattr("backend") + if backend_value == "fpgadataflow": + info_messages.append("Attribute backend is set correctly") + else: + info_messages.append('Attribute backend should be set to "fpgadataflow"') + + # verify that all necessary attributes exist + try: + self.get_nodeattr("code_gen_dir_cppsim") + self.get_nodeattr("executable_path") + self.get_nodeattr("NumChannels") + self.get_nodeattr("PE") + self.get_nodeattr("inputDataType") + info_messages.append("All necessary attributes exist") + except Exception: + info_messages.append("""The required GlobalAccPool_Batch attributes do not exist.""") + + # verify that input data is 2D + if len(self.get_nodeattr("numInputVectors")) != 3: + info_messages.append("""GlobalAccPool_Batch requires 2D data input.""") + raise Exception + + return info_messages + + def get_exp_cycles(self): + # Channels/PE * batch size * idim * idim + Channels/PE + ch = self.get_nodeattr("NumChannels") + pe = self.get_nodeattr("PE") + folds = int(ch / pe) + return int(np.prod(self.get_folded_input_shape()[:-1]) + folds) + + def execute_node(self, context, graph): + mode = self.get_nodeattr("exec_mode") + node = self.onnx_node + exp_ishape = self.get_normal_input_shape() + exp_oshape = self.get_normal_output_shape() + folded_ishape = self.get_folded_input_shape() + + if mode == "cppsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + elif mode == "rtlsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + + inp = context[node.input[0]] + assert str(inp.dtype) == "float32", "Input datatype is not float32" + assert inp.shape == exp_ishape, """Input shape doesn't match expected shape .""" + export_idt = self.get_input_datatype() + # reshape input into folded form + inp = inp.reshape(folded_ishape) + # make copy before saving array + reshaped_input = inp.copy() + np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input) + + if mode == "cppsim": + # execute the precompiled model + super().exec_precompiled_singlenode_model() + # load output npy file + super().npy_to_dynamic_output(context) + assert ( + context[node.output[0]].shape == exp_oshape + ), "cppsim \ + did not produce expected output shape" + elif mode == "rtlsim": + sim = self.get_rtlsim() + nbits = self.get_instream_width() + rtlsim_inp = npy_to_rtlsim_input( + "{}/input_0.npy".format(code_gen_dir), export_idt, nbits + ) + super().reset_rtlsim(sim) + super().toggle_clk(sim) + rtlsim_output = self.rtlsim(sim, rtlsim_inp) + odt = self.get_output_datatype() + target_bits = odt.bitwidth() + packed_bits = self.get_outstream_width() + out_npy_path = "{}/output.npy".format(code_gen_dir) + out_shape = self.get_folded_output_shape() + rtlsim_output_to_npy( + rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits + ) + # load and reshape output + output = np.load(out_npy_path) + output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) + context[node.output[0]] = output + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + + assert ( + context[node.output[0]].shape == exp_oshape + ), """Output shape doesn't match expected shape.""" + + def global_includes(self): + self.code_gen_dict["$GLOBALS$"] = ['#include "maxpool.h"'] + + def defines(self, var): + self.code_gen_dict["$DEFINES$"] = [] + + def read_npy_data(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_input_datatype() + elem_bits = dtype.bitwidth() + packed_bits = self.get_instream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "float" + npy_in = "%s/input_0.npy" % code_gen_dir + self.code_gen_dict["$READNPYDATA$"] = [] + self.code_gen_dict["$READNPYDATA$"].append( + 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) + ) + + def strm_decl(self): + self.code_gen_dict["$STREAMDECLARATIONS$"] = [] + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> in0_{} ("in0_{}");'.format( + self.get_instream_width(), self.hls_sname(), self.hls_sname() + ) + ) + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> out_{} ("out_{}");'.format( + self.get_outstream_width(), self.hls_sname(), self.hls_sname() + ) + ) + + def docompute(self): + self.code_gen_dict["$DOCOMPUTE$"] = [ + """AccPool_Batch<{}, {}, {}, {}, {}> (in0_{}, out_{}, 1);""".format( + self.get_normal_input_shape()[1], + self.get_nodeattr("NumChannels"), + self.get_input_datatype().get_hls_datatype_str(), + self.get_nodeattr("PE"), + self.get_output_datatype().get_hls_datatype_str(), + self.hls_sname(), + self.hls_sname(), + ) + ] + + def dataoutstrm(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_output_datatype() + elem_bits = dtype.bitwidth() + packed_bits = self.get_outstream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "float" + npy_out = "%s/output.npy" % code_gen_dir + oshape = self.get_folded_output_shape() + oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") + + self.code_gen_dict["$DATAOUTSTREAM$"] = [ + 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + self.hls_sname(), + oshape_cpp_str, + npy_out, + ) + ] + + def save_as_npy(self): + self.code_gen_dict["$SAVEASCNPY$"] = [] + + def blackboxfunction(self): + self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ + """void {}(hls::stream> &in0_{}, + hls::stream> &out_{})""".format( + self.onnx_node.name, + self.get_instream_width(), + self.hls_sname(), + self.get_outstream_width(), + self.hls_sname(), + ) + ] + + def pragmas(self): + self.code_gen_dict["$PRAGMAS$"] = [ + "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() + ] + self.code_gen_dict["$PRAGMAS$"].append( + "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() + ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") diff --git a/tests/fpgadataflow/test_fpgadataflow_globalaccpool.py b/tests/fpgadataflow/test_fpgadataflow_globalaccpool.py index 1b3d87c11f..a70db28c63 100644 --- a/tests/fpgadataflow/test_fpgadataflow_globalaccpool.py +++ b/tests/fpgadataflow/test_fpgadataflow_globalaccpool.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (c) 2020-2022, Xilinx +# Copyright (C) 2023, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -44,14 +45,15 @@ from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers -def make_accpool_modelwrapper(ch, pe, idim, idt): +def make_accpool_modelwrapper(ch, pe, idim, idt, impl_style): inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, [1, idim, idim, ch]) outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, [1, 1, 1, ch]) accpool_node = helper.make_node( - "GlobalAccPool_Batch", + "GlobalAccPool", ["inp"], ["outp"], domain="finn.custom_op.fpgadataflow", @@ -60,6 +62,7 @@ def make_accpool_modelwrapper(ch, pe, idim, idt): PE=pe, inputDataType=idt.name, numInputVectors=[1, idim, idim], + preferred_impl_style=impl_style, ) graph = helper.make_graph(nodes=[accpool_node], name="graph", inputs=[inp], outputs=[outp]) @@ -85,9 +88,11 @@ def prepare_inputs(input_tensor, idt): @pytest.mark.parametrize("imdim", [7]) # execution mode @pytest.mark.parametrize("exec_mode", ["cppsim", "rtlsim"]) +# impl_style +@pytest.mark.parametrize("impl_style", ["hls"]) @pytest.mark.fpgadataflow @pytest.mark.vivado -def test_fpgadataflow_globalaccpool(idt, ch, fold, imdim, exec_mode): +def test_fpgadataflow_globalaccpool(idt, ch, fold, imdim, exec_mode, impl_style): if fold == -1: pe = 1 else: @@ -97,7 +102,8 @@ def test_fpgadataflow_globalaccpool(idt, ch, fold, imdim, exec_mode): # generate input data x = gen_finn_dt_tensor(idt, (1, imdim, imdim, ch)) - model = make_accpool_modelwrapper(ch, pe, imdim, idt) + model = make_accpool_modelwrapper(ch, pe, imdim, idt, impl_style) + model = model.transform(SpecializeLayers()) if exec_mode == "cppsim": model = model.transform(PrepareCppSim()) @@ -120,7 +126,7 @@ def test_fpgadataflow_globalaccpool(idt, ch, fold, imdim, exec_mode): assert (y == expected_y).all(), exec_mode + " failed" if exec_mode == "rtlsim": - node = model.get_nodes_by_op_type("GlobalAccPool_Batch")[0] + node = model.get_nodes_by_op_type("GlobalAccPool_hls")[0] inst = getCustomOp(node) cycles_rtlsim = inst.get_nodeattr("cycles_rtlsim") exp_cycles_dict = model.analysis(exp_cycles_per_layer) From e1911670ab26e865677aaeae3c819e7da86f1107 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 29 Nov 2023 15:27:56 +0000 Subject: [PATCH 336/665] [CustomOp] Delete duplication of exp_cycles func --- src/finn/custom_op/fpgadataflow/hls/channelwise_op_hls.py | 4 ---- .../custom_op/fpgadataflow/hls/duplicatestreams_hls.py | 4 ---- src/finn/custom_op/fpgadataflow/hls/globalaccpool_hls.py | 7 ------- 3 files changed, 15 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/hls/channelwise_op_hls.py b/src/finn/custom_op/fpgadataflow/hls/channelwise_op_hls.py index d816b6f15a..e7c263c084 100644 --- a/src/finn/custom_op/fpgadataflow/hls/channelwise_op_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/channelwise_op_hls.py @@ -117,10 +117,6 @@ def lut_estimation(self): # total cost return comparator_cost + lutram_cost - def get_exp_cycles(self): - # Channels/PE * batch size * fmdim * fmdim - return np.prod(self.get_folded_output_shape()[:-1]) - def get_template_param_values(self): """Returns the template parameter values according to input, output and weight data types.""" diff --git a/src/finn/custom_op/fpgadataflow/hls/duplicatestreams_hls.py b/src/finn/custom_op/fpgadataflow/hls/duplicatestreams_hls.py index 4468ca152c..de0fadb26c 100644 --- a/src/finn/custom_op/fpgadataflow/hls/duplicatestreams_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/duplicatestreams_hls.py @@ -69,10 +69,6 @@ def verify_node(self): return info_messages - def get_exp_cycles(self): - # Channels/PE * batch size * fmdim * fmdim - return np.prod(self.get_folded_output_shape()[:-1]) - def generate_params(self, model, path): n_outputs = self.get_num_output_streams() inp_streams = [] diff --git a/src/finn/custom_op/fpgadataflow/hls/globalaccpool_hls.py b/src/finn/custom_op/fpgadataflow/hls/globalaccpool_hls.py index 4814c09e59..93398b1dc9 100644 --- a/src/finn/custom_op/fpgadataflow/hls/globalaccpool_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/globalaccpool_hls.py @@ -73,13 +73,6 @@ def verify_node(self): return info_messages - def get_exp_cycles(self): - # Channels/PE * batch size * idim * idim + Channels/PE - ch = self.get_nodeattr("NumChannels") - pe = self.get_nodeattr("PE") - folds = int(ch / pe) - return int(np.prod(self.get_folded_input_shape()[:-1]) + folds) - def execute_node(self, context, graph): mode = self.get_nodeattr("exec_mode") node = self.onnx_node From 76da5ab3f990fcc36062dbfaf4862ee23b2aadb2 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 29 Nov 2023 16:45:57 +0000 Subject: [PATCH 337/665] [CustomOp] Initial draft of LabelSelect in new class hierarchy --- src/finn/custom_op/fpgadataflow/__init__.py | 2 + .../custom_op/fpgadataflow/hls/__init__.py | 2 + .../fpgadataflow/hls/labelselect_hls.py | 262 ++++++++++++++++++ .../custom_op/fpgadataflow/labelselect.py | 146 ++++++++++ .../test_fpgadataflow_labelselect.py | 16 +- 5 files changed, 423 insertions(+), 5 deletions(-) create mode 100644 src/finn/custom_op/fpgadataflow/hls/labelselect_hls.py create mode 100644 src/finn/custom_op/fpgadataflow/labelselect.py diff --git a/src/finn/custom_op/fpgadataflow/__init__.py b/src/finn/custom_op/fpgadataflow/__init__.py index b939ea0c56..f51acf7136 100644 --- a/src/finn/custom_op/fpgadataflow/__init__.py +++ b/src/finn/custom_op/fpgadataflow/__init__.py @@ -52,6 +52,7 @@ from finn.custom_op.fpgadataflow.globalaccpool import GlobalAccPool from finn.custom_op.fpgadataflow.globalaccpool_batch import GlobalAccPool_Batch from finn.custom_op.fpgadataflow.iodma import IODMA +from finn.custom_op.fpgadataflow.labelselect import LabelSelect from finn.custom_op.fpgadataflow.labelselect_batch import LabelSelect_Batch from finn.custom_op.fpgadataflow.lookup import Lookup from finn.custom_op.fpgadataflow.matrixvectoractivation import MatrixVectorActivation @@ -109,3 +110,4 @@ custom_op["ChannelwiseOp"] = ChannelwiseOp custom_op["DuplicateStreams"] = DuplicateStreams custom_op["GlobalAccPool"] = GlobalAccPool +custom_op["LabelSelect"] = LabelSelect diff --git a/src/finn/custom_op/fpgadataflow/hls/__init__.py b/src/finn/custom_op/fpgadataflow/hls/__init__.py index 075449d589..66a5d7b53c 100644 --- a/src/finn/custom_op/fpgadataflow/hls/__init__.py +++ b/src/finn/custom_op/fpgadataflow/hls/__init__.py @@ -31,6 +31,7 @@ from finn.custom_op.fpgadataflow.hls.duplicatestreams_hls import DuplicateStreams_hls from finn.custom_op.fpgadataflow.hls.fmpadding_hls import FMPadding_hls from finn.custom_op.fpgadataflow.hls.globalaccpool_hls import GlobalAccPool_hls +from finn.custom_op.fpgadataflow.hls.labelselect_hls import LabelSelect_hls custom_op = dict() @@ -41,3 +42,4 @@ custom_op["DuplicateStreams_hls"] = DuplicateStreams_hls custom_op["FMPadding_hls"] = FMPadding_hls custom_op["GlobalAccPool_hls"] = GlobalAccPool_hls +custom_op["LabelSelect_hls"] = LabelSelect_hls diff --git a/src/finn/custom_op/fpgadataflow/hls/labelselect_hls.py b/src/finn/custom_op/fpgadataflow/hls/labelselect_hls.py new file mode 100644 index 0000000000..701d061987 --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/hls/labelselect_hls.py @@ -0,0 +1,262 @@ +# Copyright (C) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import numpy as np +import os + +from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend +from finn.custom_op.fpgadataflow.labelselect import LabelSelect +from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy + + +class LabelSelect_hls(LabelSelect, HLSBackend): + """Class that corresponds to finn-hlslib LabelSelect_Batch function.""" + + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) + + def get_nodeattr_types(self): + my_attrs = {} + my_attrs.update(LabelSelect.get_nodeattr_types(self)) + my_attrs.update(HLSBackend.get_nodeattr_types(self)) + return my_attrs + + def verify_node(self): + info_messages = [] + # verify that "backend" is set to "fpgadataflow" + backend_value = self.get_nodeattr("backend") + if backend_value == "fpgadataflow": + info_messages.append("Attribute backend is set correctly") + else: + info_messages.append('Attribute backend should be set to "fpgadataflow"') + + # verify that all necessary attributes exist + try: + self.get_nodeattr("code_gen_dir_cppsim") + self.get_nodeattr("executable_path") + self.get_nodeattr("Labels") + self.get_nodeattr("PE") + self.get_nodeattr("K") + self.get_nodeattr("inputDataType") + self.get_nodeattr("outputDataType") + info_messages.append("All necessary attributes exist") + except Exception: + info_messages.append("""The required LabelSelect_Batch attributes do not exist.""") + + # verify that input data is 1D + if len(self.get_nodeattr("numInputVectors")) > 1: + info_messages.append("""LabelSelect_Batch requires 1D data input.""") + raise Exception + + return info_messages + + def execute_node(self, context, graph): + mode = self.get_nodeattr("exec_mode") + node = self.onnx_node + exp_ishape = self.get_normal_input_shape() + exp_oshape = self.get_normal_output_shape() + folded_ishape = self.get_folded_input_shape() + + if mode == "cppsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + elif mode == "rtlsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + + inp = context[node.input[0]] + assert str(inp.dtype) == "float32", "Input datatype is not float32" + assert inp.shape == exp_ishape, """Input shape doesn't match expected shape .""" + export_idt = self.get_input_datatype() + # reshape input into folded form + inp = inp.reshape(folded_ishape) + # make copy before saving array + reshaped_input = inp.copy() + np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input) + + if mode == "cppsim": + # execute the precompiled model + super().exec_precompiled_singlenode_model() + # load output npy file + super().npy_to_dynamic_output(context) + assert ( + context[node.output[0]].shape == exp_oshape + ), "cppsim \ + did not produce expected output shape" + elif mode == "rtlsim": + sim = self.get_rtlsim() + nbits = self.get_instream_width() + rtlsim_inp = npy_to_rtlsim_input( + "{}/input_0.npy".format(code_gen_dir), export_idt, nbits + ) + super().reset_rtlsim(sim) + super().toggle_clk(sim) + rtlsim_output = self.rtlsim(sim, rtlsim_inp) + odt = self.get_output_datatype() + target_bits = odt.bitwidth() + packed_bits = self.get_outstream_width() + out_npy_path = "{}/output.npy".format(code_gen_dir) + out_shape = self.get_folded_output_shape() + rtlsim_output_to_npy( + rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits + ) + # load and reshape output + output = np.load(out_npy_path) + output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) + context[node.output[0]] = output + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + + assert ( + context[node.output[0]].shape == exp_oshape + ), """Output shape doesn't match expected shape.""" + # TopK ind output normally uses TensorProto.INT64, which + # can cause issues for the node-by-node simulation in FINN + # (as the custom DataType system always assumes float containers) + # so cast the output to int64 + ret = context[node.output[0]] + context[node.output[0]] = ret.astype(np.int64) + + def global_includes(self): + self.code_gen_dict["$GLOBALS$"] = ['#include "maxpool.h"'] + + def defines(self, var): + self.code_gen_dict["$DEFINES$"] = [] + + def read_npy_data(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_input_datatype() + elem_bits = dtype.bitwidth() + packed_bits = self.get_instream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "float" + npy_in = "%s/input_0.npy" % code_gen_dir + self.code_gen_dict["$READNPYDATA$"] = [] + + # Calling npy2apintstream with reverse_inner = false to have LE packing + # as required by HLS fxn LabelSelect_Batch + # Also notice that StreamingDataWidthConverter_Batch performs LE packing + + self.code_gen_dict["$READNPYDATA$"].append( + 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s, false);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) + ) + + def strm_decl(self): + self.code_gen_dict["$STREAMDECLARATIONS$"] = [] + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> in0_{} ("in0_{}");'.format( + self.get_instream_width(), self.hls_sname(), self.hls_sname() + ) + ) + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> out_{} ("out_{}");'.format( + self.get_outstream_width(), self.hls_sname(), self.hls_sname() + ) + ) + + def docompute(self): + self.code_gen_dict["$DOCOMPUTE$"] = [ + """LabelSelect_Batch<{}, {}, {}, {}, {} > (in0_{}, out_{}, 1);""".format( + self.get_nodeattr("Labels"), + self.get_nodeattr("PE"), + self.get_nodeattr("K"), + self.get_input_datatype().get_hls_datatype_str(), + self.get_output_datatype().get_hls_datatype_str(), + self.hls_sname(), + self.hls_sname(), + ) + ] + + def dataoutstrm(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_output_datatype() + elem_bits = dtype.bitwidth() + packed_bits = self.get_outstream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "float" + npy_out = "%s/output.npy" % code_gen_dir + oshape = self.get_folded_output_shape() + oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") + + self.code_gen_dict["$DATAOUTSTREAM$"] = [ + 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + self.hls_sname(), + oshape_cpp_str, + npy_out, + ) + ] + + def save_as_npy(self): + self.code_gen_dict["$SAVEASCNPY$"] = [] + + def blackboxfunction(self): + self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ + """void {}(hls::stream> &in0_{}, + hls::stream > &out_{})""".format( + self.onnx_node.name, + self.get_nodeattr("PE"), + self.get_input_datatype().bitwidth(), + self.hls_sname(), + self.get_output_datatype().bitwidth(), + self.hls_sname(), + ) + ] + + def pragmas(self): + self.code_gen_dict["$PRAGMAS$"] = [ + "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() + ] + self.code_gen_dict["$PRAGMAS$"].append( + "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() + ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") diff --git a/src/finn/custom_op/fpgadataflow/labelselect.py b/src/finn/custom_op/fpgadataflow/labelselect.py new file mode 100644 index 0000000000..77b50e0fc6 --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/labelselect.py @@ -0,0 +1,146 @@ +# Copyright (C) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from qonnx.core.datatype import DataType +from qonnx.util.basic import roundup_to_integer_multiple + +from finn.custom_op.fpgadataflow.hwcustomop import HWCustomOp + + +class LabelSelect(HWCustomOp): + """Abstraction layer for HW implementation of LabelSelect""" + + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) + odt_name = self.get_nodeattr("outputDataType") + if odt_name == "": + # If not provided compute min size + labels = self.get_nodeattr("Labels") + odt = DataType.get_smallest_possible(labels - 1) + # ensure a datatype divisible by 8-bits in case this is the last node + bw = roundup_to_integer_multiple(odt.bitwidth(), 8) + new_odt_name = odt.name.replace(str(odt.bitwidth()), str(bw)) + odt = DataType[new_odt_name] + odt_name = odt.name + self.set_nodeattr("outputDataType", odt_name) + + def get_nodeattr_types(self): + my_attrs = { + "Labels": ("i", True, 0), + "PE": ("i", True, 0), + "K": ("i", True, 0), + # FINN DataTypes for input + "inputDataType": ("s", True, ""), + "outputDataType": ("s", False, ""), + # number of input vectors, examples: + # [1] is a single vector (like a FC layer with batch=1) + # [4] is four vectors (like a FC layer with batch=4) + # [1, 4, 4] is four * four vectors (like a conv layer with batch=1) + "numInputVectors": ("ints", False, [1]), + } + my_attrs.update(super().get_nodeattr_types()) + return my_attrs + + def get_normal_input_shape(self, ind=0): + nlabels = self.get_nodeattr("Labels") + vecs = list(self.get_nodeattr("numInputVectors")) + ishape = tuple(vecs + [nlabels]) + return ishape + + def get_folded_input_shape(self, ind=0): + nlabels = self.get_nodeattr("Labels") + pe = self.get_nodeattr("PE") + vecs = list(self.get_nodeattr("numInputVectors")) + assert nlabels % pe == 0, "PE must divide Labels" + folds = int(nlabels / pe) + folded_ishape = tuple(vecs + [folds, pe]) + return folded_ishape + + def get_normal_output_shape(self, ind=0): + k = self.get_nodeattr("K") + vecs = list(self.get_nodeattr("numInputVectors")) + oshape = tuple(vecs + [k]) + return oshape + + def get_folded_output_shape(self, ind=0): + k = self.get_nodeattr("K") + vecs = list(self.get_nodeattr("numInputVectors")) + oshape = tuple(vecs + [k, 1]) + return oshape + + def make_shape_compatible_op(self, model): + exp_ishape = self.get_normal_input_shape() + oshape = self.get_normal_output_shape() + ishape = tuple(model.get_tensor_shape(self.onnx_node.input[0])) + assert ishape == exp_ishape, "Unexpected input shape." + return super().make_const_shape_op(oshape) + + def infer_node_datatype(self, model): + node = self.onnx_node + # check input datatype against property + idt = model.get_tensor_datatype(node.input[0]) + self.set_nodeattr("inputDataType", idt.name) + + odt = self.get_output_datatype() + model.set_tensor_datatype(self.onnx_node.output[0], odt) + + def verify_node(self): + pass + + def get_input_datatype(self, ind=0): + """Returns FINN DataType of input.""" + ret = DataType[self.get_nodeattr("inputDataType")] + return ret + + def get_output_datatype(self, ind=0): + """Returns FINN DataType of output.""" + ret = DataType[self.get_nodeattr("outputDataType")] + return ret + + def get_instream_width(self, ind=0): + """Returns input stream width.""" + ibits = self.get_input_datatype().bitwidth() + pe = self.get_nodeattr("PE") + in_width = pe * ibits + return in_width + + def get_outstream_width(self, ind=0): + """Returns output stream width.""" + return self.get_output_datatype().bitwidth() + + def get_number_output_values(self): + return self.get_nodeattr("K") + + def execute_node(self, context, graph): + pass + + def get_exp_cycles(self): + nlabels = self.get_nodeattr("Labels") + pe = self.get_nodeattr("PE") + exp_cycles = nlabels / pe + return int(exp_cycles) diff --git a/tests/fpgadataflow/test_fpgadataflow_labelselect.py b/tests/fpgadataflow/test_fpgadataflow_labelselect.py index efd093b0b3..244d8c8a54 100644 --- a/tests/fpgadataflow/test_fpgadataflow_labelselect.py +++ b/tests/fpgadataflow/test_fpgadataflow_labelselect.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (c) 2020-2022, Xilinx +# Copyright (C) 2023, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -42,15 +43,16 @@ from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers from finn.util.test import soft_verify_topk -def make_labelselect_modelwrapper(labels, pe, k, idt): +def make_labelselect_modelwrapper(labels, pe, k, idt, impl_style): inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, [1, labels]) outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, [1, k]) labelselect_node = helper.make_node( - "LabelSelect_Batch", + "LabelSelect", ["inp"], ["outp"], domain="finn.custom_op.fpgadataflow", @@ -59,6 +61,7 @@ def make_labelselect_modelwrapper(labels, pe, k, idt): PE=pe, K=k, inputDataType=idt.name, + preferred_impl_style=impl_style, ) graph = helper.make_graph( nodes=[labelselect_node], @@ -90,9 +93,11 @@ def prepare_inputs(input_tensor, idt): @pytest.mark.parametrize("k", [1, 5]) # execution mode @pytest.mark.parametrize("exec_mode", ["cppsim", "rtlsim"]) +# impl style +@pytest.mark.parametrize("impl_style", ["hls"]) @pytest.mark.fpgadataflow @pytest.mark.vivado -def test_fpgadataflow_labelselect(idt, labels, fold, k, exec_mode): +def test_fpgadataflow_labelselect(idt, labels, fold, k, exec_mode, impl_style): np.random.seed(0) if fold == -1: pe = 1 @@ -106,7 +111,8 @@ def test_fpgadataflow_labelselect(idt, labels, fold, k, exec_mode): # generate input data x = gen_finn_dt_tensor(idt, (1, labels)) - model = make_labelselect_modelwrapper(labels, pe, k, idt) + model = make_labelselect_modelwrapper(labels, pe, k, idt, impl_style) + model = model.transform(SpecializeLayers()) if exec_mode == "cppsim": model = model.transform(PrepareCppSim()) From a53dd8573c5bac57a84be0f26170ffd03afacf6e Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 29 Nov 2023 18:02:53 +0000 Subject: [PATCH 338/665] [LabelSelect] Fix elem_type for make shape compatible for LabelSelect --- src/finn/custom_op/fpgadataflow/labelselect.py | 11 ++++++++++- tests/fpgadataflow/test_fpgadataflow_labelselect.py | 2 +- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/labelselect.py b/src/finn/custom_op/fpgadataflow/labelselect.py index 77b50e0fc6..6b924034e4 100644 --- a/src/finn/custom_op/fpgadataflow/labelselect.py +++ b/src/finn/custom_op/fpgadataflow/labelselect.py @@ -26,6 +26,7 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from onnx import TensorProto, helper from qonnx.core.datatype import DataType from qonnx.util.basic import roundup_to_integer_multiple @@ -98,7 +99,15 @@ def make_shape_compatible_op(self, model): oshape = self.get_normal_output_shape() ishape = tuple(model.get_tensor_shape(self.onnx_node.input[0])) assert ishape == exp_ishape, "Unexpected input shape." - return super().make_const_shape_op(oshape) + return helper.make_node( + "RandomNormal", + inputs=[], + outputs=[self.onnx_node.output[0]], + mean=0.0, + scale=1.0, + dtype=TensorProto.INT64, + shape=list(oshape), + ) def infer_node_datatype(self, model): node = self.onnx_node diff --git a/tests/fpgadataflow/test_fpgadataflow_labelselect.py b/tests/fpgadataflow/test_fpgadataflow_labelselect.py index 244d8c8a54..d9c3f54e63 100644 --- a/tests/fpgadataflow/test_fpgadataflow_labelselect.py +++ b/tests/fpgadataflow/test_fpgadataflow_labelselect.py @@ -49,7 +49,7 @@ def make_labelselect_modelwrapper(labels, pe, k, idt, impl_style): inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, [1, labels]) - outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, [1, k]) + outp = helper.make_tensor_value_info("outp", TensorProto.INT64, [1, k]) labelselect_node = helper.make_node( "LabelSelect", From e42f4160cdb79c53260badb93560a09f8f827b62 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 29 Nov 2023 18:06:05 +0000 Subject: [PATCH 339/665] [Transform] Initial draft for conversion to hw layers and test case --- .../fpgadataflow/convert_to_hw_layers.py | 505 ++++++++++++++++++ .../test_convert_to_hw_layers_synthetic.py | 223 ++++++++ 2 files changed, 728 insertions(+) create mode 100644 src/finn/transformation/fpgadataflow/convert_to_hw_layers.py create mode 100644 tests/fpgadataflow/test_convert_to_hw_layers_synthetic.py diff --git a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py new file mode 100644 index 0000000000..e3813eb709 --- /dev/null +++ b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py @@ -0,0 +1,505 @@ +# Copyright (C) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + +import numpy as np +import qonnx.core.data_layout as DataLayout +import warnings +from onnx import TensorProto, helper +from qonnx.core.datatype import DataType +from qonnx.transformation.base import Transformation +from qonnx.transformation.general import SortGraph +from qonnx.transformation.infer_datatypes import InferDataTypes +from qonnx.transformation.infer_shapes import InferShapes +from qonnx.util.onnx import nchw_to_nhwc + + +class InferAddStreamsLayer(Transformation): + """Convert any Add into a AddStreams HW layer.""" + + def apply(self, model): + graph = model.graph + node_ind = 0 + graph_modified = False + for node in graph.node: + node_ind += 1 + if node.op_type == "Add": + in0 = node.input[0] + in1 = node.input[1] + result = node.output[0] + in0_shape = model.get_tensor_shape(in0) + in1_shape = model.get_tensor_shape(in1) + in0_static = not (model.get_initializer(in0) is None) + in1_static = not (model.get_initializer(in1) is None) + + # skip if different shapes on inputs + if in0_shape != in1_shape: + continue + # skip if any of inputs have initializers + # (this node is meant for adding two dynamic streams) + if in0_static or in1_static: + continue + + idt0 = model.get_tensor_datatype(in0) + idt1 = model.get_tensor_datatype(in1) + + # skip if different data types on inputs + if idt0 != idt1: + continue + + idt = idt0 + + # skip conversion for layers with float input + if not idt.is_integer(): + continue + + # check layout and convert if necessary + in0_layout = model.get_tensor_layout(in0) + in1_layout = model.get_tensor_layout(in1) + result_layout = model.get_tensor_layout(result) + + if in0_layout == DataLayout.NCHW: + in0 = nchw_to_nhwc(in0, model, node_ind) + node_ind += 1 + in0_shape = model.get_tensor_shape(in0) + + if in1_layout == DataLayout.NCHW: + in1 = nchw_to_nhwc(in1, model, node_ind) + node_ind += 1 + in1_shape = model.get_tensor_shape(in1) + + # keep track of where we need to insert the HW Op + # it has to be ahead of the output transform + insert_point = node_ind + + if result_layout == DataLayout.NCHW: + result = nchw_to_nhwc(result, model, node_ind, reverse=True) + node_ind += 1 + + # now safe to assume num_channels is size of last dimension + num_channels = int(in0_shape[-1]) + # create node with no parallelization first + pe = 1 + + # create and insert new AddStreams node + new_node = helper.make_node( + "AddStreams", + [in0, in1], + [result], + domain="finn.custom_op.fpgadataflow", + backend="fpgadataflow", + NumChannels=num_channels, + PE=pe, + inputDataType=idt.name, + numInputVectors=in0_shape[:-1], + name="AddStreams_" + node.name, + ) + graph.node.insert(insert_point, new_node) + # remove old node + graph.node.remove(node) + graph_modified = True + + if graph_modified: + model = model.transform(InferShapes()) + model = model.transform(InferDataTypes()) + return (model, graph_modified) + + +class InferDuplicateStreamsLayer(Transformation): + """Insert a DuplicateStreams HW layer for any tensor with fanout == 2""" + + def apply(self, model): + graph = model.graph + node_ind = 0 + graph_modified = False + for node in graph.node: + node_ind += 1 + successors = model.find_consumers(node.output[0]) + if successors is not None and len(successors) >= 2: + output_tensor = node.output[0] + n_outputs = len(successors) + + dt = model.get_tensor_datatype(output_tensor) + + # skip conversion for layers with float input + if not dt.is_integer(): + continue + + # create clone tensors + out_shape = model.get_tensor_shape(output_tensor) + out_tensor_clones = [] + for i in range(n_outputs): + clone = helper.make_tensor_value_info( + model.make_new_valueinfo_name(), TensorProto.FLOAT, out_shape + ) + model.graph.value_info.append(clone) + out_tensor_clones += [clone.name] + + num_ch = int(out_shape[-1]) + vecs = out_shape[:-1] + + # create node with no parallelization first + pe = 1 + + dup_node = helper.make_node( + "DuplicateStreams", + [output_tensor], + out_tensor_clones, + domain="finn.custom_op.fpgadataflow", + backend="fpgadataflow", + NumChannels=num_ch, + PE=pe, + inputDataType=dt.name, + numInputVectors=vecs, + NumOutputStreams=n_outputs, + outFIFODepths=[2] * n_outputs, + name="DuplicateStreams_" + node.name, + ) + + graph.node.insert(node_ind, dup_node) + + # connect successors to out tensor clone + clone_idx = 0 + for successor in successors: + for i, succ_input in enumerate(successor.input): + if succ_input == output_tensor: + successor.input[i] = out_tensor_clones[clone_idx] + clone_idx += 1 + # if one node has multiple connections to the same output + # find_direct_successors will return one node per input + # so break the inner loop will result in correct behaviour + break + + graph_modified = True + + if graph_modified: + model = model.transform(SortGraph()) + model = model.transform(InferShapes()) + model = model.transform(InferDataTypes()) + return (model, graph_modified) + + +class InferChannelwiseLinearLayer(Transformation): + """Convert any channel-wise Add/Mul into a HW layer.""" + + def get_smallest_possible(self, vals): + """Returns smallest (fewest bits) possible DataType that can represent + value. Prefers unsigned integers where possible.""" + vals = np.array(vals, dtype=np.float64) + for v in vals: + assert int(v) == v, "Error float value" + + for k in DataType.get_accumulator_dt_cands(): + dt = DataType[k] + + if dt in [DataType["BIPOLAR"], DataType["TERNARY"], DataType["FLOAT32"]]: + # not currently supported + continue + + if (dt.min() <= vals).all() and (vals <= dt.max()).all(): + return dt + + warnings.warn( + """InferChannelwiseLinearLayer: Output values may not be + representable with supported data types. + Setting maximum width data type available. + This will lead to errors if there are no constrains on the input + """ + ) + + if (0 <= vals).all(): + return DataType["UINT64"] + else: + return DataType["INT64"] + + def apply(self, model): + graph = model.graph + node_ind = 0 + graph_modified = False + for node in graph.node: + node_ind += 1 + if node.op_type == "Add" or node.op_type == "Mul": + # assuming input[0] is dynamic + ll_input = node.input[0] + ll_output = node.output[0] + ll_in_shape = model.get_tensor_shape(ll_input) + + # check if input 1 has an initializer + ll_const = node.input[1] + if ll_const is not None: + ll_cinit = model.get_initializer(ll_const) + if ll_cinit is None: + # input 1 is also dynamic + continue + else: + continue + + # get number of channels and channel index from input + ll_in_layout = model.get_tensor_layout(ll_input) + if ll_in_layout == DataLayout.NHWC or ll_in_layout == DataLayout.NC: + ch_index = -1 + ch = ll_in_shape[-1] + elif ll_in_layout == DataLayout.NCHW: + ch_index = 1 + ch = ll_in_shape[1] + else: + continue + + # check if the shape of initializer is compatible + ll_cinit_shape = list(ll_cinit.shape) + if np.prod(ll_cinit_shape) == 1: + warnings.warn("Broadcasting " + str(node.op_type) + "(" + node.name + ")") + ll_cinit = np.full((ch), ll_cinit.flatten()[0]) + elif np.prod(ll_cinit_shape) != ch or ll_cinit_shape[ch_index] != ch: + # parameter shape not compatible with Channelwise + continue + + # check initializer contains integers as floats + if not (ll_cinit.astype(np.int32) == ll_cinit).all(): + continue + # all initializer conditions are met + + # check inputs + idt = model.get_tensor_datatype(ll_input) + if not idt.is_integer(): + # skip conversion for layers with float input + continue + + # check layout of inputs/outputs, and convert if needed + # check layout and convert if necessary + if ll_in_layout == DataLayout.NCHW: + ll_input = nchw_to_nhwc(ll_input, model, node_ind) + node_ind += 1 + ll_in_shape = model.get_tensor_shape(ll_input) + + # keep track of where we need to insert the HW Op + # it has to be ahead of the output transform + insert_point = node_ind + ll_output_layout = model.get_tensor_layout(ll_output) + if ll_output_layout == DataLayout.NCHW: + ll_output = nchw_to_nhwc(ll_output, model, node_ind, reverse=True) + node_ind += 1 + + # get parameter data type + param_min = min(ll_cinit.flatten()) + param_max = max(ll_cinit.flatten()) + pdt = self.get_smallest_possible([param_min, param_max]) + + # set function and determine output data type + if node.op_type == "Add": + func = "add" + out_min = idt.min() + param_min + out_max = idt.max() + param_max + odt = self.get_smallest_possible([out_min, out_max]) + elif node.op_type == "Mul": + func = "mul" + possible_limits = [] + possible_limits += [idt.min() * param_min] + possible_limits += [idt.min() * param_max] + possible_limits += [idt.max() * param_min] + possible_limits += [idt.max() * param_max] + odt = self.get_smallest_possible(possible_limits) + + model.set_initializer(ll_const, ll_cinit.reshape(ch)) + model.set_tensor_datatype(ll_output, odt) + + # create node with no parallelization first + pe = 1 + assert ch % pe == 0, "Requirement IFC divisable by PE is violated." + # create and insert node + new_node = helper.make_node( + "ChannelwiseOp", + [ll_input, ll_const], + [ll_output], + domain="finn.custom_op.fpgadataflow", + backend="fpgadataflow", + Func=func, + NumChannels=ch, + PE=pe, + inputDataType=idt.name, + paramDataType=pdt.name, + outputDataType=odt.name, + numInputVectors=list(ll_in_shape[:-1]), + name="ChannelwiseOp_" + node.name, + ) + graph.node.insert(insert_point, new_node) + # remove old node + graph.node.remove(node) + graph_modified = True + + if graph_modified: + model = model.transform(InferShapes()) + model = model.transform(InferDataTypes()) + return (model, graph_modified) + + +class InferLabelSelectLayer(Transformation): + """Convert any TopK into a LabelSelect HW layer.""" + + def apply(self, model): + graph = model.graph + node_ind = 0 + graph_modified = False + for node in graph.node: + node_ind += 1 + if node.op_type == "TopK": + fc_input = node.input[0] + k_input = node.input[1] + val_output = node.output[0] + idx_output = node.output[1] + fc_in_shape = model.get_tensor_shape(fc_input) + + idt = model.get_tensor_datatype(fc_input) + + # skip conversion for layers with float input + if not idt.is_integer(): + continue + + # skip conversion for if value output is connected (not supported) + if model.find_consumer(val_output) is not None: + continue + + num_labels = int(fc_in_shape[-1]) + num_inp_vecs = list(fc_in_shape[:-1]) + # create node with no parallelization first + pe = 1 + + k = model.get_initializer(k_input)[0] + + # create and insert new LabelSelect node + new_node = helper.make_node( + "LabelSelect", + [fc_input], + [idx_output], + domain="finn.custom_op.fpgadataflow", + backend="fpgadataflow", + Labels=num_labels, + PE=pe, + K=k, + inputDataType=idt.name, + numInputVectors=num_inp_vecs, + name="LabelSelect_" + node.name, + ) + graph.node.insert(node_ind, new_node) + # remove old node + graph.node.remove(node) + graph_modified = True + + if graph_modified: + model = model.transform(InferShapes()) + model = model.transform(InferDataTypes()) + return (model, graph_modified) + + +class InferGlobalAccPoolLayer(Transformation): + """Convert any GlobalAveragePool into a GlobalAccPool HW layer and a scalar Mul.""" + + def apply(self, model): + graph = model.graph + node_ind = 0 + graph_modified = False + for node in graph.node: + node_ind += 1 + if node.op_type == "GlobalAveragePool": + in0 = node.input[0] + result = node.output[0] + in0_shape = model.get_tensor_shape(in0) + + idt = model.get_tensor_datatype(in0) + + # skip conversion for layers with float input + if not idt.is_integer(): + continue + + # check layout and convert if necessary + in0_layout = model.get_tensor_layout(in0) + result_layout = model.get_tensor_layout(result) + + if in0_layout == DataLayout.NCHW: + in0 = nchw_to_nhwc(in0, model, node_ind) + node_ind += 1 + in0_shape = model.get_tensor_shape(in0) + + # keep track of where we need to insert the HW Op + # it has to be ahead of the output transform + insert_point = node_ind + + if result_layout == DataLayout.NCHW: + result = nchw_to_nhwc(result, model, node_ind, reverse=True) + node_ind += 1 + + num_ch = int(in0_shape[-1]) + vecs = in0_shape[:-1] + # create node with no parallelization first + pe = 1 + + # create an additional tensor of the same shape and layout as result + out_shape = model.get_tensor_shape(result) + pool_out = helper.make_tensor_value_info( + model.make_new_valueinfo_name(), TensorProto.FLOAT, out_shape + ) + model.graph.value_info.append(pool_out) + pool_out = pool_out.name + model.set_tensor_layout(pool_out, model.get_tensor_layout(result)) + + new_pool = helper.make_node( + "GlobalAccPool", + [in0], + [pool_out], + domain="finn.custom_op.fpgadataflow", + backend="fpgadataflow", + NumChannels=num_ch, + PE=pe, + inputDataType=idt.name, + numInputVectors=vecs, + name="GlobalAccPool_" + node.name, + ) + + mul_value = helper.make_tensor_value_info( + model.make_new_valueinfo_name(), TensorProto.FLOAT, [1] + ) + model.graph.value_info.append(mul_value) + model.set_initializer( + mul_value.name, np.array(1 / (vecs[1] * vecs[2]), dtype=np.float32) + ) + new_mul = helper.make_node( + "Mul", + [pool_out, mul_value.name], + [result], + ) + graph.node.insert(insert_point, new_pool) + graph.node.insert(insert_point + 1, new_mul) + node_ind += 1 + # remove old node + graph.node.remove(node) + graph_modified = True + + if graph_modified: + model = model.transform(InferShapes()) + model = model.transform(InferDataTypes()) + return (model, graph_modified) diff --git a/tests/fpgadataflow/test_convert_to_hw_layers_synthetic.py b/tests/fpgadataflow/test_convert_to_hw_layers_synthetic.py new file mode 100644 index 0000000000..be8bce7fc3 --- /dev/null +++ b/tests/fpgadataflow/test_convert_to_hw_layers_synthetic.py @@ -0,0 +1,223 @@ +# Copyright (C) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import pytest + +import numpy as np +import os +from onnx import TensorProto, helper +from qonnx.core.datatype import DataType +from qonnx.core.modelwrapper import ModelWrapper +from qonnx.transformation.fold_constants import FoldConstants +from qonnx.transformation.general import ( + GiveReadableTensorNames, + GiveUniqueNodeNames, + SortGraph, +) +from qonnx.transformation.infer_data_layouts import InferDataLayouts +from qonnx.transformation.infer_datatypes import InferDataTypes +from qonnx.transformation.infer_shapes import InferShapes +from qonnx.transformation.insert_topk import InsertTopK +from qonnx.util.basic import gen_finn_dt_tensor, qonnx_make_model + +import finn.core.onnx_exec as oxe +import finn.transformation.fpgadataflow.convert_to_hw_layers as to_hw +from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim +from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim +from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers +from finn.transformation.streamline.absorb import ( + AbsorbConsecutiveTransposes, + AbsorbScalarMulAddIntoTopK, +) +from finn.transformation.streamline.collapse_repeated import ( + CollapseRepeatedAdd, + CollapseRepeatedMul, +) +from finn.transformation.streamline.reorder import ( + MoveAddPastMul, + MoveScalarLinearPastInvariants, +) +from finn.util.test import soft_verify_topk + +export_onnx_path = "test_output_synthetic.onnx" + +# construct a synthetic graph to test: +# topk insertion, topk conversion to hls, add conversion to hls +# graph should just be a sum + + +def make_model(ch, ifmdim): + shape = [1, ch, ifmdim, ifmdim] + inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, shape) + inp1_add0_ct = helper.make_tensor_value_info("inp1_add0_ct", TensorProto.FLOAT, [1]) + inp1_add = helper.make_tensor_value_info("inp1_add", TensorProto.FLOAT, shape) + inp1_add_ct = helper.make_tensor_value_info("inp1_add_ct", TensorProto.FLOAT, [1]) + inp2_add = helper.make_tensor_value_info("inp2_add", TensorProto.FLOAT, shape) + inp2_add_ct = helper.make_tensor_value_info("inp2_add_ct", TensorProto.FLOAT, [1]) + inp1_mul = helper.make_tensor_value_info("inp1_mul", TensorProto.FLOAT, shape) + inp1_mul_ct = helper.make_tensor_value_info("inp1_mul_ct", TensorProto.FLOAT, [1]) + inp2_mul = helper.make_tensor_value_info("inp2_mul", TensorProto.FLOAT, shape) + inp2_mul_ct = helper.make_tensor_value_info("inp2_mul_ct", TensorProto.FLOAT, [1]) + eltwise_add = helper.make_tensor_value_info("eltwise_add", TensorProto.FLOAT, shape) + pool = helper.make_tensor_value_info("pool", TensorProto.FLOAT, [1, ch, 1, 1]) + reshape_ct = helper.make_tensor_value_info("reshape_ct", TensorProto.INT64, [2]) + outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, [1, ch]) + + add0_node = helper.make_node("Add", [inp.name, inp1_add0_ct.name], ["out_add0"]) + add1_node = helper.make_node("Add", ["out_add0", inp1_add_ct.name], [inp1_add.name]) + add2_node = helper.make_node("Add", ["out_add0", inp2_add_ct.name], [inp2_add.name]) + mul1_node = helper.make_node("Mul", [inp1_add.name, inp1_mul_ct.name], [inp1_mul.name]) + mul2_node = helper.make_node("Mul", [inp2_add.name, inp2_mul_ct.name], [inp2_mul.name]) + eltwise_add_node = helper.make_node("Add", [inp1_mul.name, inp2_mul.name], [eltwise_add.name]) + globalavgpool_node = helper.make_node("GlobalAveragePool", [eltwise_add.name], [pool.name]) + reshape_node = helper.make_node("Reshape", [pool.name, reshape_ct.name], [outp.name]) + + graph = helper.make_graph( + nodes=[ + add0_node, + add1_node, + add2_node, + mul1_node, + mul2_node, + eltwise_add_node, + globalavgpool_node, + reshape_node, + ], + name="graph", + inputs=[inp], + outputs=[outp], + ) + + model = qonnx_make_model(graph, producer_name="add-model") + model = ModelWrapper(model) + + # set initializers for scalar add/mul nodes + model.set_initializer(add0_node.input[1], np.array([0.0], dtype=np.float32)) + model.set_initializer(add1_node.input[1], np.array([7.0], dtype=np.float32)) + model.set_initializer(add2_node.input[1], np.array([8.0], dtype=np.float32)) + model.set_initializer(mul1_node.input[1], np.array([2.0], dtype=np.float32)) + model.set_initializer(mul2_node.input[1], np.array([2.0], dtype=np.float32)) + model.set_initializer(reshape_node.input[1], np.array([1, -1], dtype=np.int64)) + + return model + + +# data types +@pytest.mark.parametrize("idt", [DataType["UINT2"]]) +# channels +@pytest.mark.parametrize("ch", [16]) +# ifmdim +@pytest.mark.parametrize("ifmdim", [5]) +@pytest.mark.fpgadataflow +@pytest.mark.vivado +@pytest.mark.slow +def test_convert_to_hls_layers_synthetic(ch, ifmdim, idt): + model = make_model(ch, ifmdim) + model.save(export_onnx_path) + model = ModelWrapper(export_onnx_path, fix_float64=True) + model = model.transform(InferShapes()) + model = model.transform(FoldConstants()) + model = model.transform(GiveUniqueNodeNames()) + model = model.transform(GiveReadableTensorNames()) + model = model.transform(InferDataLayouts()) + # generate test vectors of correct shape + if ifmdim == -1: + input_tensor_shape = (1, ch) + else: + input_tensor_shape = (1, ch, ifmdim, ifmdim) + + x = gen_finn_dt_tensor(idt, input_tensor_shape) + + # generate expected value from streamlined net + input_dict = {model.graph.input[0].name: x} + + output_dict = oxe.execute_onnx(model, input_dict, True) + produced_sum = output_dict[model.graph.output[0].name] + chw_mul = model.get_initializer(model.graph.node[-1].input[1]) + chw_mul = 1 + expected_sum = chw_mul * np.sum(2 * (2 * x + 15.0), axis=(2, 3)) / (ifmdim * ifmdim) + assert (produced_sum.flatten() == expected_sum.flatten()).all() + + model = model.transform(InferDataLayouts()) + + # convert to hls + model.set_tensor_datatype(model.graph.input[0].name, idt) + # extra streamlining + model = model.transform(MoveScalarLinearPastInvariants()) + model = model.transform(MoveAddPastMul()) + model = model.transform(CollapseRepeatedMul()) + model = model.transform(CollapseRepeatedAdd()) + # insert top-k node, which should absorb linear ops before it + + model = model.transform(InferShapes()) + model = model.transform(InferDataLayouts()) + model = model.transform(InferDataTypes()) + + model = model.transform(to_hw.InferChannelwiseLinearLayer()) + model = model.transform(to_hw.InferAddStreamsLayer()) + model = model.transform(to_hw.InferGlobalAccPoolLayer()) + model = model.transform(MoveScalarLinearPastInvariants()) + model = model.transform(InsertTopK()) + model = model.transform(AbsorbScalarMulAddIntoTopK()) + model = model.transform(InferDataTypes()) + model = model.transform(to_hw.InferLabelSelectLayer()) + model = model.transform(AbsorbConsecutiveTransposes()) + model = model.transform(InferDataTypes()) + # model = model.transform(to_hw.InferLabelSelectLayer()) + model = model.transform(to_hw.InferDuplicateStreamsLayer()) + + model = model.transform(SortGraph()) + + # check topology status + + finn_nodes = model.get_finn_nodes() + assert len(finn_nodes) == 9 + add_nodes = model.get_nodes_by_op_type("AddStreams") + assert len(add_nodes) == 1 + pool_nodes = model.get_nodes_by_op_type("GlobalAccPool") + assert len(pool_nodes) == 1 + label_nodes = model.get_nodes_by_op_type("LabelSelect") + assert len(label_nodes) == 1 + channelwise_nodes = model.get_nodes_by_op_type("ChannelwiseOp") + assert len(channelwise_nodes) == 5 + dup_nodes = model.get_nodes_by_op_type("DuplicateStreams") + assert len(dup_nodes) == 1 + + model = model.transform(SpecializeLayers()) + + model = model.transform(PrepareCppSim()) + model = model.transform(CompileCppSim()) + model = model.transform(SetExecMode("cppsim")) + + output_dict = oxe.execute_onnx(model, input_dict, True) + produced_topk_hls = output_dict[model.graph.output[0].name] + topk_input = output_dict[model.graph.node[-1].input[0]] + assert soft_verify_topk(topk_input, produced_topk_hls, 5) + + os.remove(export_onnx_path) From c854276ca282563ac4cc7216b878ad8a77e4f7ad Mon Sep 17 00:00:00 2001 From: auphelia Date: Thu, 30 Nov 2023 12:17:37 +0000 Subject: [PATCH 340/665] [AddStreams] Add execution for hw abstraction layer --- src/finn/custom_op/fpgadataflow/addstreams.py | 11 ++++++++++- .../test_fpgadataflow_addstreams.py | 19 +++++++++++-------- 2 files changed, 21 insertions(+), 9 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/addstreams.py b/src/finn/custom_op/fpgadataflow/addstreams.py index 0f1336c6e1..ac61786ac1 100644 --- a/src/finn/custom_op/fpgadataflow/addstreams.py +++ b/src/finn/custom_op/fpgadataflow/addstreams.py @@ -141,7 +141,16 @@ def get_exp_cycles(self): return np.prod(self.get_folded_output_shape()[:-1]) def execute_node(self, context, graph): - pass + # simulate behavior using Python + node = self.onnx_node + inp0_values = context[node.input[0]] + inp1_values = context[node.input[1]] + oshape = context[node.output[0]].shape + ishape0 = inp0_values.shape + ishape1 = inp1_values.shape + assert ishape0 == ishape1, "Shapes of inputs should be the same for Addstreams" + result = inp0_values + inp1_values + context[node.output[0]] = np.asarray(result, dtype=np.float32).reshape(oshape) def get_verilog_top_module_intf_names(self): intf_names = super().get_verilog_top_module_intf_names() diff --git a/tests/fpgadataflow/test_fpgadataflow_addstreams.py b/tests/fpgadataflow/test_fpgadataflow_addstreams.py index ba3afe9c86..530d94e13b 100644 --- a/tests/fpgadataflow/test_fpgadataflow_addstreams.py +++ b/tests/fpgadataflow/test_fpgadataflow_addstreams.py @@ -105,9 +105,18 @@ def test_fpgadataflow_addstreams(idt, ch, fold, exec_mode): x2 = gen_finn_dt_tensor(idt, (1, ch)) model = make_addstreams_modelwrapper(ch, pe, idt) - model.save("addstreams_hw.onnx") + + # prepare input data + input_dict = prepare_inputs(x1, x2) + oshape = model.get_tensor_shape("outp") + y = x1 + x2 + y_expected = y.reshape(oshape) + + # test verification flow before specializing layer + y_produced = oxe.execute_onnx(model, input_dict)["outp"] + assert (y_produced == y_expected).all(), "Execution of hw layer failed" + model = model.transform(SpecializeLayers()) - model.save("addstreams_hls.onnx") if exec_mode == "cppsim": model = model.transform(PrepareCppSim()) @@ -122,12 +131,6 @@ def test_fpgadataflow_addstreams(idt, ch, fold, exec_mode): else: raise Exception("Unknown exec_mode") - # prepare input data - input_dict = prepare_inputs(x1, x2) - - oshape = model.get_tensor_shape("outp") - y = x1 + x2 - y_expected = y.reshape(oshape) # execute model y_produced = oxe.execute_onnx(model, input_dict)["outp"] y_produced = y_produced.reshape(y_expected.shape) From 445360d1b0d3d8030bc6fdf492b8c7de47ddada6 Mon Sep 17 00:00:00 2001 From: auphelia Date: Thu, 30 Nov 2023 12:25:59 +0000 Subject: [PATCH 341/665] [ChannelwiseOp] Add execution for hw abstraction layer --- .../custom_op/fpgadataflow/channelwise_op.py | 36 +++++++++++++++++- .../test_fpgadataflow_channelwise_ops.py | 37 ++++++++++++------- 2 files changed, 58 insertions(+), 15 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/channelwise_op.py b/src/finn/custom_op/fpgadataflow/channelwise_op.py index 5d1d8febc1..9bf4ebdf62 100644 --- a/src/finn/custom_op/fpgadataflow/channelwise_op.py +++ b/src/finn/custom_op/fpgadataflow/channelwise_op.py @@ -27,8 +27,11 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import numpy as np +import onnxruntime as rt import warnings +from onnx import TensorProto, helper from qonnx.core.datatype import DataType +from qonnx.util.basic import qonnx_make_model from finn.custom_op.fpgadataflow.hwcustomop import HWCustomOp @@ -197,4 +200,35 @@ def get_exp_cycles(self): return np.prod(self.get_folded_output_shape()[:-1]) def execute_node(self, context, graph): - pass + # create a standard onnx node to help calculate the result + # depending on Func node attribute either a Mul or an Add node + node = self.onnx_node + func = self.get_nodeattr("Func") + inp_values = context[node.input[0]] + param_values = context[node.input[1]] + oshape = context[node.output[0]].shape + ishape = inp_values.shape + pshape = param_values.shape + inp = helper.make_tensor_value_info(node.input[0], TensorProto.FLOAT, ishape) + param = helper.make_tensor_value_info(node.input[1], TensorProto.FLOAT, pshape) + outp = helper.make_tensor_value_info(node.output[0], TensorProto.FLOAT, oshape) + node_func = helper.make_node( + func.capitalize(), + inputs=node.input, + outputs=[node.output[0]], + ) + graph_func = helper.make_graph( + nodes=[node_func], + name="single-add-exec", + inputs=[inp, param], + outputs=[outp], + ) + + opset_version = self.onnx_opset_version + opset_imports = [helper.make_opsetid("", opset_version)] + onnx_kwargs = {"opset_imports": opset_imports} + model_func = qonnx_make_model(graph_func, **onnx_kwargs) + idict = {node.input[0]: inp_values, node.input[1]: param_values} + sess = rt.InferenceSession(model_func.SerializeToString()) + result = sess.run(None, idict) + context[node.output[0]] = np.asarray(result, dtype=np.float32).reshape(oshape) diff --git a/tests/fpgadataflow/test_fpgadataflow_channelwise_ops.py b/tests/fpgadataflow/test_fpgadataflow_channelwise_ops.py index af9628c644..d5fa7c779f 100644 --- a/tests/fpgadataflow/test_fpgadataflow_channelwise_ops.py +++ b/tests/fpgadataflow/test_fpgadataflow_channelwise_ops.py @@ -112,12 +112,33 @@ def test_fpgadataflow_channelwise_ops(idt, act, pdt, nf, ich, func, vecs, exec_m # generate input and param data x = gen_finn_dt_tensor(idt, tuple(vecs + [ich])) - # C = np.random.randint(idt.min(), idt.max() + 1, ich).astype(np.float32) C = gen_finn_dt_tensor(pdt, (ich)) odt = act + # create model model = make_modelwrapper(C, pe, idt, odt, pdt, func, vecs) + + # package input data as dictionary + input_dict = {"inp": x} + + oshape = model.get_tensor_shape("outp") + + C_reshaped = np.broadcast_to(C.flatten(), x.shape) + if func == "add": + y = x + C_reshaped + elif func == "mul": + y = x * C_reshaped + + y_expected = y.reshape(oshape) + + # verify hw abstraction layer + y_produced = oxe.execute_onnx(model, input_dict)["outp"] + + y_produced = y_produced.reshape(y_expected.shape) + + assert (y_produced == y_expected).all(), "HW layer execution failed" + model = model.transform(SpecializeLayers()) if exec_mode == "cppsim": @@ -133,24 +154,12 @@ def test_fpgadataflow_channelwise_ops(idt, act, pdt, nf, ich, func, vecs, exec_m else: raise Exception("Unknown exec_mode") - # package input data as dictionary - input_dict = {"inp": x} - - oshape = model.get_tensor_shape("outp") - - C_reshaped = np.broadcast_to(C.flatten(), x.shape) - if func == "add": - y = x + C_reshaped - elif func == "mul": - y = x * C_reshaped - - y_expected = y.reshape(oshape) # execute model y_produced = oxe.execute_onnx(model, input_dict)["outp"] y_produced = y_produced.reshape(y_expected.shape) - assert (y_produced == y_expected).all(), "cppsim failed" + assert (y_produced == y_expected).all(), exec_mode + " failed" if exec_mode == "rtlsim": hls_synt_res_est = model.analysis(hls_synth_res_estimation) From 67f922670f9693d3851b913357ab2ce83b448e4c Mon Sep 17 00:00:00 2001 From: auphelia Date: Thu, 30 Nov 2023 13:55:49 +0000 Subject: [PATCH 342/665] [DuplicateStreams] Add execution for hw abstraction layer --- .../custom_op/fpgadataflow/duplicatestreams.py | 11 ++++++++++- .../test_fpgadataflow_duplicatestreams.py | 14 +++++++++++--- 2 files changed, 21 insertions(+), 4 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/duplicatestreams.py b/src/finn/custom_op/fpgadataflow/duplicatestreams.py index a4cf72df03..8943ffc9e3 100644 --- a/src/finn/custom_op/fpgadataflow/duplicatestreams.py +++ b/src/finn/custom_op/fpgadataflow/duplicatestreams.py @@ -144,7 +144,16 @@ def get_exp_cycles(self): return np.prod(self.get_folded_output_shape()[:-1]) def execute_node(self, context, graph): - pass + # passing input to both outputs to make + # abstraction layer executable + node = self.onnx_node + inp = context[node.input[0]] + exp_shape = self.get_normal_input_shape() + + output = inp + output = np.asarray([output], dtype=np.float32).reshape(*exp_shape) + for outp in node.output: + context[outp] = output def get_verilog_top_module_intf_names(self): intf_names = super().get_verilog_top_module_intf_names() diff --git a/tests/fpgadataflow/test_fpgadataflow_duplicatestreams.py b/tests/fpgadataflow/test_fpgadataflow_duplicatestreams.py index ac96380da3..62b9265466 100644 --- a/tests/fpgadataflow/test_fpgadataflow_duplicatestreams.py +++ b/tests/fpgadataflow/test_fpgadataflow_duplicatestreams.py @@ -117,6 +117,17 @@ def test_fpgadataflow_duplicatestreams(idt, ch, fold, imdim, n_dupl, exec_mode, x = gen_finn_dt_tensor(idt, (1, imdim, imdim, ch)) model = make_dupstreams_modelwrapper(ch, pe, imdim, idt, n_dupl, impl_style) + + # prepare input data and execute + input_dict = prepare_inputs(x, idt) + + # check behavior of hw abstraction layer + output_dict = oxe.execute_onnx(model, input_dict) + expected_y = x + for i in range(n_dupl): + y = output_dict["outp%d" % i] + assert (y == expected_y).all(), "HW layer execution failed" + model = model.transform(SpecializeLayers()) if exec_mode == "cppsim": @@ -132,11 +143,8 @@ def test_fpgadataflow_duplicatestreams(idt, ch, fold, imdim, n_dupl, exec_mode, else: raise Exception("Unknown exec_mode") - # prepare input data and execute - input_dict = prepare_inputs(x, idt) output_dict = oxe.execute_onnx(model, input_dict) - expected_y = x for i in range(n_dupl): y = output_dict["outp%d" % i] assert (y == expected_y).all(), exec_mode + " failed" From 95b1ec5c21cb3289e99e165e49e2a3676c936604 Mon Sep 17 00:00:00 2001 From: auphelia Date: Thu, 30 Nov 2023 14:01:26 +0000 Subject: [PATCH 343/665] [GlobalAccPool] Add execution for hw abstraction layer --- src/finn/custom_op/fpgadataflow/globalaccpool.py | 7 ++++++- .../fpgadataflow/test_fpgadataflow_globalaccpool.py | 12 +++++++++--- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/globalaccpool.py b/src/finn/custom_op/fpgadataflow/globalaccpool.py index c90385e9f0..4008cdc7c9 100644 --- a/src/finn/custom_op/fpgadataflow/globalaccpool.py +++ b/src/finn/custom_op/fpgadataflow/globalaccpool.py @@ -152,4 +152,9 @@ def get_exp_cycles(self): return int(np.prod(self.get_folded_input_shape()[:-1]) + folds) def execute_node(self, context, graph): - pass + # simulate behavior with Python functionality + node = self.onnx_node + inp_values = context[node.input[0]] + oshape = context[node.output[0]].shape + result = np.apply_over_axes(np.sum, inp_values, [1, 2]) + context[node.output[0]] = np.asarray(result, dtype=np.float32).reshape(oshape) diff --git a/tests/fpgadataflow/test_fpgadataflow_globalaccpool.py b/tests/fpgadataflow/test_fpgadataflow_globalaccpool.py index a70db28c63..9c2802aade 100644 --- a/tests/fpgadataflow/test_fpgadataflow_globalaccpool.py +++ b/tests/fpgadataflow/test_fpgadataflow_globalaccpool.py @@ -102,7 +102,16 @@ def test_fpgadataflow_globalaccpool(idt, ch, fold, imdim, exec_mode, impl_style) # generate input data x = gen_finn_dt_tensor(idt, (1, imdim, imdim, ch)) + # prepare input data and execute + input_dict = prepare_inputs(x, idt) + expected_y = np.sum(x, axis=(1, 2)).flatten() + model = make_accpool_modelwrapper(ch, pe, imdim, idt, impl_style) + + y = oxe.execute_onnx(model, input_dict)["outp"] + + assert (y == expected_y).all(), "HW layer verification failed" + model = model.transform(SpecializeLayers()) if exec_mode == "cppsim": @@ -118,10 +127,7 @@ def test_fpgadataflow_globalaccpool(idt, ch, fold, imdim, exec_mode, impl_style) else: raise Exception("Unknown exec_mode") - # prepare input data and execute - input_dict = prepare_inputs(x, idt) y = oxe.execute_onnx(model, input_dict)["outp"] - expected_y = np.sum(x, axis=(1, 2)).flatten() assert (y == expected_y).all(), exec_mode + " failed" From 05d3dbfab4c1e48b44543d39eb46d05dcccd8814 Mon Sep 17 00:00:00 2001 From: auphelia Date: Thu, 30 Nov 2023 14:05:01 +0000 Subject: [PATCH 344/665] [LabelSelect] Add execution for hw abstraction layer --- .../custom_op/fpgadataflow/labelselect.py | 37 +++++++++++++++++-- .../test_fpgadataflow_labelselect.py | 8 +++- 2 files changed, 40 insertions(+), 5 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/labelselect.py b/src/finn/custom_op/fpgadataflow/labelselect.py index 6b924034e4..f4b098cff7 100644 --- a/src/finn/custom_op/fpgadataflow/labelselect.py +++ b/src/finn/custom_op/fpgadataflow/labelselect.py @@ -25,10 +25,11 @@ # CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - +import numpy as np +import onnxruntime as rt from onnx import TensorProto, helper from qonnx.core.datatype import DataType -from qonnx.util.basic import roundup_to_integer_multiple +from qonnx.util.basic import qonnx_make_model, roundup_to_integer_multiple from finn.custom_op.fpgadataflow.hwcustomop import HWCustomOp @@ -146,7 +147,37 @@ def get_number_output_values(self): return self.get_nodeattr("K") def execute_node(self, context, graph): - pass + # create a standard add node to help calculate the result + node = self.onnx_node + k = self.get_nodeattr("K") + + inp_values = context[node.input[0]] + oshape = context[node.output[0]].shape + ishape = inp_values.shape + inp = helper.make_tensor_value_info(node.input[0], TensorProto.FLOAT, ishape) + k_inp = helper.make_tensor_value_info("k_inp", TensorProto.INT64, [1]) + outp = helper.make_tensor_value_info(node.output[0], TensorProto.INT64, oshape) + val_outp = helper.make_tensor_value_info("val_outp", TensorProto.FLOAT, oshape) + node_topk = helper.make_node( + "TopK", + inputs=[node.input[0], "k_inp"], + outputs=["val_outp", node.output[0]], + ) + graph_topk = helper.make_graph( + nodes=[node_topk], + name="single-add-exec", + inputs=[inp, k_inp], + outputs=[val_outp, outp], + ) + + opset_version = self.onnx_opset_version + opset_imports = [helper.make_opsetid("", opset_version)] + onnx_kwargs = {"opset_imports": opset_imports} + model_topk = qonnx_make_model(graph_topk, **onnx_kwargs) + idict = {node.input[0]: inp_values, "k_inp": [k]} + sess = rt.InferenceSession(model_topk.SerializeToString()) + result = sess.run(None, idict) + context[node.output[0]] = np.asarray(result[1], dtype=np.float32).reshape(oshape) def get_exp_cycles(self): nlabels = self.get_nodeattr("Labels") diff --git a/tests/fpgadataflow/test_fpgadataflow_labelselect.py b/tests/fpgadataflow/test_fpgadataflow_labelselect.py index d9c3f54e63..98ded66ca7 100644 --- a/tests/fpgadataflow/test_fpgadataflow_labelselect.py +++ b/tests/fpgadataflow/test_fpgadataflow_labelselect.py @@ -110,8 +110,14 @@ def test_fpgadataflow_labelselect(idt, labels, fold, k, exec_mode, impl_style): # generate input data x = gen_finn_dt_tensor(idt, (1, labels)) + input_dict = prepare_inputs(x, idt) model = make_labelselect_modelwrapper(labels, pe, k, idt, impl_style) + + y = oxe.execute_onnx(model, input_dict)["outp"] + + assert soft_verify_topk(x, y, k), "HW layer execution failed" + model = model.transform(SpecializeLayers()) if exec_mode == "cppsim": @@ -127,8 +133,6 @@ def test_fpgadataflow_labelselect(idt, labels, fold, k, exec_mode, impl_style): else: raise Exception("Unknown exec_mode") - # prepare input data and execute - input_dict = prepare_inputs(x, idt) y = oxe.execute_onnx(model, input_dict)["outp"] assert soft_verify_topk(x, y, k), exec_mode + " failed" From 55449a8f5356757ffbb901980eebebea042efa59 Mon Sep 17 00:00:00 2001 From: auphelia Date: Thu, 30 Nov 2023 14:10:09 +0000 Subject: [PATCH 345/665] [Tests] Expand conversion to hw layers tests by functional verification --- .../test_convert_to_hw_layers_synthetic.py | 26 +++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/tests/fpgadataflow/test_convert_to_hw_layers_synthetic.py b/tests/fpgadataflow/test_convert_to_hw_layers_synthetic.py index be8bce7fc3..02a53485ad 100644 --- a/tests/fpgadataflow/test_convert_to_hw_layers_synthetic.py +++ b/tests/fpgadataflow/test_convert_to_hw_layers_synthetic.py @@ -189,7 +189,6 @@ def test_convert_to_hls_layers_synthetic(ch, ifmdim, idt): model = model.transform(to_hw.InferLabelSelectLayer()) model = model.transform(AbsorbConsecutiveTransposes()) model = model.transform(InferDataTypes()) - # model = model.transform(to_hw.InferLabelSelectLayer()) model = model.transform(to_hw.InferDuplicateStreamsLayer()) model = model.transform(SortGraph()) @@ -209,14 +208,37 @@ def test_convert_to_hls_layers_synthetic(ch, ifmdim, idt): dup_nodes = model.get_nodes_by_op_type("DuplicateStreams") assert len(dup_nodes) == 1 + output_hw = oxe.execute_onnx(model, input_dict, True) + model = model.transform(SpecializeLayers()) + # check topology status + + finn_nodes = model.get_finn_nodes() + assert len(finn_nodes) == 9 + add_nodes = model.get_nodes_by_op_type("AddStreams_hls") + assert len(add_nodes) == 1 + pool_nodes = model.get_nodes_by_op_type("GlobalAccPool_hls") + assert len(pool_nodes) == 1 + label_nodes = model.get_nodes_by_op_type("LabelSelect_hls") + assert len(label_nodes) == 1 + channelwise_nodes = model.get_nodes_by_op_type("ChannelwiseOp_hls") + assert len(channelwise_nodes) == 5 + dup_nodes = model.get_nodes_by_op_type("DuplicateStreams_hls") + assert len(dup_nodes) == 1 + model = model.transform(PrepareCppSim()) model = model.transform(CompileCppSim()) model = model.transform(SetExecMode("cppsim")) output_dict = oxe.execute_onnx(model, input_dict, True) - produced_topk_hls = output_dict[model.graph.output[0].name] + + # verify execution + outp_name = model.graph.output[0].name + # comparison before and after layer specialization + assert (output_dict[outp_name] == output_hw[outp_name]).all() + # comparison with golden output + produced_topk_hls = output_dict[outp_name] topk_input = output_dict[model.graph.node[-1].input[0]] assert soft_verify_topk(topk_input, produced_topk_hls, 5) From 9eb113f5e7f4f8246fe54ddf4a9844e4b0571c3e Mon Sep 17 00:00:00 2001 From: auphelia Date: Thu, 30 Nov 2023 14:46:38 +0000 Subject: [PATCH 346/665] [FMPadding] Add execution for hw abstraction layer --- src/finn/custom_op/fpgadataflow/fmpadding.py | 10 +++++++++- tests/fpgadataflow/test_fpgadataflow_fmpadding.py | 14 ++++++++++---- 2 files changed, 19 insertions(+), 5 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/fmpadding.py b/src/finn/custom_op/fpgadataflow/fmpadding.py index 0324984c3f..5767028ea7 100644 --- a/src/finn/custom_op/fpgadataflow/fmpadding.py +++ b/src/finn/custom_op/fpgadataflow/fmpadding.py @@ -161,4 +161,12 @@ def get_number_output_values(self): return np.prod(folded_oshape[:-1]) def execute_node(self, context, graph): - pass + # simulate behavior with Python functionality + node = self.onnx_node + pad = self.get_nodeattr("Padding") + inp_values = context[node.input[0]] + oshape = context[node.output[0]].shape + result = np.pad( + inp_values, ((0, 0), (pad[0], pad[2]), (pad[1], pad[3]), (0, 0)), "constant" + ) + context[node.output[0]] = np.asarray(result, dtype=np.float32).reshape(oshape) diff --git a/tests/fpgadataflow/test_fpgadataflow_fmpadding.py b/tests/fpgadataflow/test_fpgadataflow_fmpadding.py index 3717f92e5d..12c84e7221 100644 --- a/tests/fpgadataflow/test_fpgadataflow_fmpadding.py +++ b/tests/fpgadataflow/test_fpgadataflow_fmpadding.py @@ -128,8 +128,17 @@ def test_fpgadataflow_fmpadding(idim, pad, num_ch, simd, idt, mode, impl_style): odim_h = idim_h + pad_h odim_w = idim_w + pad_w + y_expected = np.pad(x, ((0, 0), (pad[0], pad[2]), (pad[1], pad[3]), (0, 0)), "constant") + expected_oshape = (1, odim_h, odim_w, num_ch) + model = make_single_fmpadding_modelwrapper(impl_style, idim, pad, num_ch, simd, idt) + + y_produced = oxe.execute_onnx(model, input_dict)["outp"] + assert y_produced.shape == expected_oshape + assert (y_produced == y_expected).all(), "HW layer execution failed" + model = model.transform(SpecializeLayers()) + model = model.transform(InferShapes()) model = model.transform(SetExecMode(mode)) model = model.transform(GiveUniqueNodeNames()) @@ -142,11 +151,8 @@ def test_fpgadataflow_fmpadding(idim, pad, num_ch, simd, idt, mode, impl_style): model = model.transform(PrepareRTLSim()) y_produced = oxe.execute_onnx(model, input_dict)["outp"] - expected_oshape = (1, odim_h, odim_w, num_ch) - assert y_produced.shape == expected_oshape - - y_expected = np.pad(x, ((0, 0), (pad[0], pad[2]), (pad[1], pad[3]), (0, 0)), "constant") + assert y_produced.shape == expected_oshape assert (y_produced == y_expected).all() if mode == "rtlsim": From 0b78eef851839965294228cd975d496f43868b27 Mon Sep 17 00:00:00 2001 From: auphelia Date: Thu, 30 Nov 2023 15:27:06 +0000 Subject: [PATCH 347/665] [Tests] Add hw conversion test for channelwise layer --- .../test_convert_to_hw_channelwise_layer.py | 143 ++++++++++++++++++ 1 file changed, 143 insertions(+) create mode 100644 tests/fpgadataflow/test_convert_to_hw_channelwise_layer.py diff --git a/tests/fpgadataflow/test_convert_to_hw_channelwise_layer.py b/tests/fpgadataflow/test_convert_to_hw_channelwise_layer.py new file mode 100644 index 0000000000..4b063f8505 --- /dev/null +++ b/tests/fpgadataflow/test_convert_to_hw_channelwise_layer.py @@ -0,0 +1,143 @@ +# Copyright (C) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import pytest + +import numpy as np +from onnx import TensorProto, helper +from qonnx.core.datatype import DataType +from qonnx.core.modelwrapper import ModelWrapper +from qonnx.transformation.general import GiveUniqueNodeNames +from qonnx.transformation.infer_data_layouts import InferDataLayouts +from qonnx.transformation.infer_shapes import InferShapes +from qonnx.util.basic import gen_finn_dt_tensor, qonnx_make_model + +import finn.core.onnx_exec as oxe +import finn.transformation.fpgadataflow.convert_to_hw_layers as to_hw +from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim +from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP +from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim +from finn.transformation.fpgadataflow.prepare_ip import PrepareIP +from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim +from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers + + +def prepare_inputs(input_tensor): + return {"inp": input_tensor} + + +def make_single_channelwise_modelwrapper(onnx_op_name, ishape, idt, pdt, pshape): + inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, ishape) + outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, ishape) + p0 = helper.make_tensor_value_info("p0", TensorProto.FLOAT, pshape) + + model = qonnx_make_model( + helper.make_graph( + name="test", + inputs=[inp], + outputs=[outp], + value_info=[p0], + nodes=[helper.make_node(onnx_op_name, ["inp", "p0"], ["outp"])], + ) + ) + + model = ModelWrapper(model) + model.set_initializer("p0", gen_finn_dt_tensor(pdt, pshape)) + model.set_tensor_datatype("inp", idt) + model.transform(InferDataLayouts(), make_deepcopy=False) + model.transform(InferShapes(), make_deepcopy=False) + return model + + +# parameter datatype +@pytest.mark.parametrize("pdt", [DataType["BIPOLAR"], DataType["UINT4"], DataType["INT2"]]) +# input datatype +@pytest.mark.parametrize("idt", [DataType["INT32"], DataType["UINT4"], DataType["INT4"]]) +# function +@pytest.mark.parametrize("onnx_op_name", ["Add", "Mul"]) +# vector parameter or scalar parameter (broadcast) +@pytest.mark.parametrize("scalar_param", [True, False]) +# execution mode +@pytest.mark.parametrize("exec_mode", ["cppsim", "rtlsim"]) +@pytest.mark.fpgadataflow +@pytest.mark.vivado +@pytest.mark.slow +def test_convert_to_hw_channelwise_layer(pdt, idt, onnx_op_name, scalar_param, exec_mode): + ifm_ch = 16 + ifm_dim = 5 + ishape = (1, ifm_ch, ifm_dim, ifm_dim) + if scalar_param: + pshape = (1,) + else: + pshape = (1, ifm_ch, 1, 1) + + np.random.seed(0) + model = make_single_channelwise_modelwrapper(onnx_op_name, ishape, idt, pdt, pshape) + + # Since the aren't Data types with a bit width of a non power of 2, + # there are cases where the input won't use it full range. + if idt == DataType["INT32"]: + x = gen_finn_dt_tensor(DataType["INT16"], (1, ifm_ch, ifm_dim, ifm_dim)) + elif idt == DataType["UINT32"]: + x = gen_finn_dt_tensor(DataType["UINT16"], (1, ifm_ch, ifm_dim, ifm_dim)) + else: + x = gen_finn_dt_tensor(idt, (1, ifm_ch, ifm_dim, ifm_dim)) + + input_dict = prepare_inputs(x) + y_expected = oxe.execute_onnx(model, input_dict)["outp"] + + model = model.transform(to_hw.InferChannelwiseLinearLayer()) + model = model.transform(GiveUniqueNodeNames()) + + ctx_produced = oxe.execute_onnx(model, input_dict, return_full_exec_context=True) + y_produced = ctx_produced["outp"] + + assert (y_produced == y_expected).all() + assert model.graph.node[1].op_type == "ChannelwiseOp" + + model = model.transform(SpecializeLayers()) + + if exec_mode == "cppsim": + model = model.transform(PrepareCppSim()) + model = model.transform(CompileCppSim()) + model = model.transform(SetExecMode("cppsim")) + elif exec_mode == "rtlsim": + model = model.transform(SetExecMode("rtlsim")) + model = model.transform(GiveUniqueNodeNames()) + model = model.transform(PrepareIP("xc7z020clg400-1", 5)) + model = model.transform(HLSSynthIP()) + model = model.transform(PrepareRTLSim()) + else: + raise Exception("Unknown exec_mode") + + ctx_produced = oxe.execute_onnx(model, input_dict, return_full_exec_context=True) + y_produced = ctx_produced["outp"] + + assert (y_produced == y_expected).all() + assert model.graph.node[1].op_type == "ChannelwiseOp_hls" From 30fc1aef45e0c13c7a8e600f38d12ecd84e3bd28 Mon Sep 17 00:00:00 2001 From: auphelia Date: Thu, 30 Nov 2023 17:46:27 +0000 Subject: [PATCH 348/665] [CustomOp] Initial draft of streamingmaxpool in new class hierarchy --- src/finn/custom_op/fpgadataflow/__init__.py | 2 + .../custom_op/fpgadataflow/hls/__init__.py | 2 + .../fpgadataflow/hls/streamingmaxpool_hls.py | 300 ++++++++++++++++++ .../fpgadataflow/streamingmaxpool.py | 229 +++++++++++++ .../fpgadataflow/convert_to_hw_layers.py | 56 ++++ .../test_fpgadataflow_streamingmaxpool.py | 18 +- 6 files changed, 602 insertions(+), 5 deletions(-) create mode 100755 src/finn/custom_op/fpgadataflow/hls/streamingmaxpool_hls.py create mode 100755 src/finn/custom_op/fpgadataflow/streamingmaxpool.py diff --git a/src/finn/custom_op/fpgadataflow/__init__.py b/src/finn/custom_op/fpgadataflow/__init__.py index f51acf7136..0a92b99fd4 100644 --- a/src/finn/custom_op/fpgadataflow/__init__.py +++ b/src/finn/custom_op/fpgadataflow/__init__.py @@ -67,6 +67,7 @@ StreamingDataWidthConverter_rtl, ) from finn.custom_op.fpgadataflow.streamingfifo import StreamingFIFO +from finn.custom_op.fpgadataflow.streamingmaxpool import StreamingMaxPool from finn.custom_op.fpgadataflow.streamingmaxpool_batch import StreamingMaxPool_Batch from finn.custom_op.fpgadataflow.thresholding_batch import Thresholding_Batch from finn.custom_op.fpgadataflow.tlastmarker import TLastMarker @@ -111,3 +112,4 @@ custom_op["DuplicateStreams"] = DuplicateStreams custom_op["GlobalAccPool"] = GlobalAccPool custom_op["LabelSelect"] = LabelSelect +custom_op["StreamingMaxPool"] = StreamingMaxPool diff --git a/src/finn/custom_op/fpgadataflow/hls/__init__.py b/src/finn/custom_op/fpgadataflow/hls/__init__.py index 66a5d7b53c..96d0e6f6a9 100644 --- a/src/finn/custom_op/fpgadataflow/hls/__init__.py +++ b/src/finn/custom_op/fpgadataflow/hls/__init__.py @@ -32,6 +32,7 @@ from finn.custom_op.fpgadataflow.hls.fmpadding_hls import FMPadding_hls from finn.custom_op.fpgadataflow.hls.globalaccpool_hls import GlobalAccPool_hls from finn.custom_op.fpgadataflow.hls.labelselect_hls import LabelSelect_hls +from finn.custom_op.fpgadataflow.hls.streamingmaxpool_hls import StreamingMaxPool_hls custom_op = dict() @@ -43,3 +44,4 @@ custom_op["FMPadding_hls"] = FMPadding_hls custom_op["GlobalAccPool_hls"] = GlobalAccPool_hls custom_op["LabelSelect_hls"] = LabelSelect_hls +custom_op["StreamingMaxPool_hls"] = StreamingMaxPool_hls diff --git a/src/finn/custom_op/fpgadataflow/hls/streamingmaxpool_hls.py b/src/finn/custom_op/fpgadataflow/hls/streamingmaxpool_hls.py new file mode 100755 index 0000000000..eb3284a343 --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/hls/streamingmaxpool_hls.py @@ -0,0 +1,300 @@ +# Copyright (C) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import numpy as np +import os +from qonnx.core.datatype import DataType +from qonnx.custom_op.general.maxpoolnhwc import compute_pool_output_dim + +from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend +from finn.custom_op.fpgadataflow.streamingmaxpool import StreamingMaxPool +from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy + + +class StreamingMaxPool_hls(StreamingMaxPool, HLSBackend): + """Class that corresponds to finn-hlslib StreamingMaxPool_batch function.""" + + def get_nodeattr_types(self): + my_attrs = {} + my_attrs.update(StreamingMaxPool.get_nodeattr_types(self)) + my_attrs.update(HLSBackend.get_nodeattr_types(self)) + return my_attrs + + def verify_node(self): + info_messages = [] + # verify that "backend" is set to "fpgadataflow" + backend_value = self.get_nodeattr("backend") + if backend_value == "fpgadataflow": + info_messages.append("Attribute backend is set correctly") + else: + info_messages.append('Attribute backend should be set to "fpgadataflow"') + + # verify the number of inputs + if len(self.onnx_node.input) == 1: + info_messages.append("The number of inputs is correct") + else: + info_messages.append("""StreamingMaxPool_Batch needs 1 data input""") + + return info_messages + + def global_includes(self): + self.code_gen_dict["$GLOBALS$"] = ['#include "maxpool.h"'] + + def defines(self, var): + numReps = 1 + ifm_dim, k, ifm_ch = self.get_1d_attrs_normalized() + ceil_mode = self.get_nodeattr("CeilMode") + output_size = compute_pool_output_dim(ifm_dim[1], k[1], k[1], 0, ceil_mode) + + if self.is_1d(): + self.code_gen_dict["$DEFINES$"] = [ + """#define ImgDim {}\n #define PoolDim {}\n + #define NumChannels {}\n #define PE {}\n #define OutputSize {} + \n #define numReps {}""".format( + ifm_dim[1], + k[1], + self.get_nodeattr("NumChannels"), + self.get_nodeattr("PE"), + output_size, + numReps, + ) + ] + else: + self.code_gen_dict["$DEFINES$"] = [ + """#define ImgDim {}\n #define PoolDim {}\n + #define NumChannels {}\n #define numReps {}""".format( + ifm_dim[1], + k[1], + self.get_nodeattr("NumChannels"), + numReps, + ) + ] + + def read_npy_data(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_input_datatype() + if dtype == DataType["BIPOLAR"]: + # use binary for bipolar storage + dtype = DataType["BINARY"] + elem_bits = dtype.bitwidth() + packed_bits = self.get_instream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "float" + npy_in = "%s/input_0.npy" % code_gen_dir + self.code_gen_dict["$READNPYDATA$"] = [] + self.code_gen_dict["$READNPYDATA$"].append( + 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) + ) + + def strm_decl(self): + self.code_gen_dict["$STREAMDECLARATIONS$"] = [] + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> in0_{} ("in0_{}");'.format( + self.get_instream_width(), self.hls_sname(), self.hls_sname() + ) + ) + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> out_{} ("out_{}");'.format( + self.get_outstream_width(), self.hls_sname(), self.hls_sname() + ) + ) + + def docompute(self): + dtype = self.get_input_datatype() + if dtype.bitwidth() == 1: + if self.is_1d(): + raise Exception("Binary 1d MaxPool not implemented on HLS backend") + else: + op = "StreamingMaxPool" + self.code_gen_dict["$DOCOMPUTE$"] = [ + "%s(in0_%s, out_%s);" + % (op, self.hls_sname(), self.hls_sname()) + ] + else: + dtype = self.get_input_datatype() + dtype_hls = dtype.get_hls_datatype_str() + minval_str = str(int(dtype.min())) + if self.is_1d(): + op = "StreamingMaxPool_Precision_1d" + self.code_gen_dict["$DOCOMPUTE$"] = [ + """%s(in0_%s, out_%s);""" + % (op, dtype_hls, minval_str, self.hls_sname(), self.hls_sname()) + ] + else: + op = "StreamingMaxPool_Precision" + self.code_gen_dict["$DOCOMPUTE$"] = [ + "%s(in0_%s, out_%s);" + % (op, dtype_hls, minval_str, self.hls_sname(), self.hls_sname()) + ] + + def dataoutstrm(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_output_datatype() + if dtype == DataType["BIPOLAR"]: + # use binary for bipolar storage + dtype = DataType["BINARY"] + elem_bits = dtype.bitwidth() + packed_bits = self.get_outstream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "float" + npy_out = "%s/output.npy" % code_gen_dir + oshape = self.get_folded_output_shape() + oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") + + self.code_gen_dict["$DATAOUTSTREAM$"] = [ + 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + self.hls_sname(), + oshape_cpp_str, + npy_out, + ) + ] + + def save_as_npy(self): + self.code_gen_dict["$SAVEASCNPY$"] = [] + + def blackboxfunction(self): + packed_bits = self.get_instream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ + "void %s(hls::stream<%s > &in0_%s, hls::stream<%s > &out_%s)" + % ( + self.onnx_node.name, + packed_hls_type, + self.hls_sname(), + packed_hls_type, + self.hls_sname(), + ) + ] + + def pragmas(self): + self.code_gen_dict["$PRAGMAS$"] = [ + "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() + ] + self.code_gen_dict["$PRAGMAS$"].append( + "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() + ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") + + def execute_node(self, context, graph): + mode = self.get_nodeattr("exec_mode") + node = self.onnx_node + exp_ishape = self.get_normal_input_shape() + exp_oshape = self.get_normal_output_shape() + folded_ishape = self.get_folded_input_shape() + + # TODO ensure codegen dir exists + if mode == "cppsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + elif mode == "rtlsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + + inp = context[node.input[0]] + assert str(inp.dtype) == "float32", "Input datatype is not float32" + assert ( + inp.shape == exp_ishape + ), """Input shape doesn't + match expected shape (1, ifm_dim, ifm_dim, ifm_ch).""" + if self.get_input_datatype() == DataType["BIPOLAR"]: + # store bipolar activations as binary + inp = (inp + 1) / 2 + export_idt = DataType["BINARY"] + else: + export_idt = self.get_input_datatype() + + reshaped_input = inp.reshape(folded_ishape) + np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input) + + if mode == "cppsim": + # execute the precompiled model + super().exec_precompiled_singlenode_model() + # load output npy file + super().npy_to_dynamic_output(context) + assert ( + context[node.output[0]].shape == exp_oshape + ), "cppsim \ + did not produce expected output shape" + elif mode == "rtlsim": + sim = self.get_rtlsim() + nbits = self.get_instream_width() + rtlsim_inp = npy_to_rtlsim_input( + "{}/input_0.npy".format(code_gen_dir), export_idt, nbits + ) + super().reset_rtlsim(sim) + super().toggle_clk(sim) + rtlsim_output = self.rtlsim(sim, rtlsim_inp) + odt = export_idt + target_bits = odt.bitwidth() + packed_bits = self.get_outstream_width() + out_npy_path = "{}/output.npy".format(code_gen_dir) + out_shape = self.get_folded_output_shape() + rtlsim_output_to_npy( + rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits + ) + # load and reshape output + output = np.load(out_npy_path) + output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) + context[node.output[0]] = output + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + # binary -> bipolar if needed + if self.get_output_datatype() == DataType["BIPOLAR"]: + out = context[node.output[0]] + out = 2 * out - 1 + context[node.output[0]] = out + assert ( + context[node.output[0]].shape == exp_oshape + ), """Output + shape doesn't match expected shape (1, ofm_dim, ofm_dim, ifm_ch).""" diff --git a/src/finn/custom_op/fpgadataflow/streamingmaxpool.py b/src/finn/custom_op/fpgadataflow/streamingmaxpool.py new file mode 100755 index 0000000000..0f85a22993 --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/streamingmaxpool.py @@ -0,0 +1,229 @@ +# Copyright (C) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import numpy as np +import onnxruntime as rt +import warnings +from onnx import TensorProto, helper +from qonnx.core.datatype import DataType +from qonnx.custom_op.general.maxpoolnhwc import compute_pool_output_dim +from qonnx.util.basic import qonnx_make_model + +from finn.custom_op.fpgadataflow.hwcustomop import HWCustomOp + +# TODO: consider splitting this into separate implementations for 1D and 2D +# similar to what we do for ConvolutionInputGenerator + + +class StreamingMaxPool(HWCustomOp): + """Abstraction layer for HW implementation of StreamingMaxPool""" + + def get_nodeattr_types(self): + my_attrs = { + "ImgDim": ("ints", True, []), # [H, W] = [Y, X] + "PoolDim": ("ints", True, []), # [H, W] = [Y, X] + "NumChannels": ("i", True, 0), + # parallelism control - only supported for 1D maxpool + "PE": ("i", False, 0), + # round up (instead of down) output size - only supported for 1D maxpool + "CeilMode": ("i", False, 0), + # FINN DataTypes for inputs/outputs + "dataType": ("s", True, ""), + } + my_attrs.update(super().get_nodeattr_types()) + return my_attrs + + def get_input_datatype(self, ind=0): + """Returns FINN DataType of input.""" + return DataType[self.get_nodeattr("dataType")] + + def get_output_datatype(self, ind=0): + """Returns FINN DataType of output.""" + return DataType[self.get_nodeattr("dataType")] + + def get_1d_attrs_normalized(self): + # support both (1, D) and (D, 1) cases transparently: + # assume the dummy ('1') dimension is the Y-dimension, i.e. + # images and kernels (and their attributes) of dimension + # [H, W] = [Y, X] = [D, 1] or [1, D] are always mapped to [1, D] + ifm_dim = self.get_nodeattr("ImgDim") + k = self.get_nodeattr("PoolDim") + ifm_ch = self.get_nodeattr("NumChannels") + if ifm_dim[1] == 1: + ifm_dim = ifm_dim[::-1] + k = k[::-1] + return (ifm_dim, k, ifm_ch) + + def is_1d(self): + ifm_dim, k, ifm_ch = self.get_1d_attrs_normalized() + return (ifm_dim[0] == 1) and (k[0] == 1) + + def get_normal_input_shape(self, ind=0): + ifm_dim_h, ifm_dim_w = self.get_nodeattr("ImgDim") + ifm_ch = self.get_nodeattr("NumChannels") + ishape = (1, ifm_dim_h, ifm_dim_w, ifm_ch) + return ishape + + def get_folded_input_shape(self, ind=0): + ifm_dim_h, ifm_dim_w = self.get_nodeattr("ImgDim") + ifm_ch = self.get_nodeattr("NumChannels") + pe = self.get_nodeattr("PE") + nf = int(ifm_ch / pe) + if self.is_1d(): + folded_ishape = (1, ifm_dim_h, ifm_dim_w, nf, pe) + else: + folded_ishape = (1, ifm_dim_h, ifm_dim_w, 1, ifm_ch) + return folded_ishape + + def get_normal_output_shape(self, ind=0): + ifm_dim_h, ifm_dim_w = self.get_nodeattr("ImgDim") + k_h, k_w = tuple(self.get_nodeattr("PoolDim")) + ifm_ch = self.get_nodeattr("NumChannels") + ceil_mode = self.get_nodeattr("CeilMode") + if not self.is_1d(): + assert ifm_dim_h % k_h == 0, "StreamingMaxPool needs ImgDim_h % PoolDim_h == 0" + assert ifm_dim_w % k_w == 0, "StreamingMaxPool needs ImgDim_w % PoolDim_w == 0" + ofm_dim_h = compute_pool_output_dim(ifm_dim_h, k_h, k_h, 0, ceil_mode) + ofm_dim_w = compute_pool_output_dim(ifm_dim_w, k_w, k_w, 0, ceil_mode) + oshape = (1, ofm_dim_h, ofm_dim_w, ifm_ch) + return oshape + + def get_folded_output_shape(self, ind=0): + # even though there is no folding in the current hlslib op, + # insert a time multiplexing axis to remain compatible with the + # shapes produced by the rest of the dataflow pipeline + ifm_ch = self.get_nodeattr("NumChannels") + pe = self.get_nodeattr("PE") + nf = int(ifm_ch / pe) + ret = list(self.get_normal_output_shape()) + if self.is_1d(): + ret[-1] = nf + ret.append(pe) + else: + ret.insert(-1, 1) + return tuple(ret) + + def get_number_output_values(self): + folded_oshape = self.get_folded_output_shape() + return np.prod(folded_oshape[:-1]) + + def get_exp_cycles(self): + # derived from StreamingMaxPool_Batch loop nest + ifm_dim, k, ifm_ch = self.get_1d_attrs_normalized() + + warnings.warn( + """Estimated latency for layer {} can be lower than + actual latency!""".format( + self.onnx_node.name + ) + ) + if self.is_1d(): + _, _, _, nf, _ = self.get_folded_output_shape() + ceil_mode = self.get_nodeattr("CeilMode") + ofm_dim = compute_pool_output_dim(ifm_dim[1], k[1], k[1], 0, ceil_mode) + exp_cycles = ofm_dim * nf * (k[1] + 1) + return int(exp_cycles) + else: + # TODO: adjust inaccurate formula + return int(ifm_dim[1] * ifm_dim[1] * (1 + 1 / (k[1] * k[1]))) + + def get_instream_width(self, ind=0): + dt_bits = self.get_input_datatype().bitwidth() + pe = self.get_nodeattr("PE") + ifm_ch = self.get_nodeattr("NumChannels") + if self.is_1d(): + in_width = int(dt_bits * pe) + else: + in_width = int(dt_bits * ifm_ch) + return in_width + + def get_outstream_width(self, ind=0): + """For streaming maxpool out stream width is the same as in stream width""" + return self.get_instream_width() + + def make_shape_compatible_op(self, model): + exp_ishape = self.get_normal_input_shape() + oshape = self.get_normal_output_shape() + ishape = tuple(model.get_tensor_shape(self.onnx_node.input[0])) + assert ishape == exp_ishape, "Unexpect input shape for StreamingMaxPool." + return super().make_const_shape_op(oshape) + + def infer_node_datatype(self, model): + node = self.onnx_node + idt = model.get_tensor_datatype(node.input[0]) + if idt != self.get_input_datatype(): + warn_str = "inputDataType changing for %s: %s -> %s " % ( + node.name, + str(self.get_input_datatype()), + str(idt), + ) + warnings.warn(warn_str) + self.set_nodeattr("dataType", idt.name) + # data type stays the same + model.set_tensor_datatype(node.output[0], idt) + + def verify_node(self): + pass + + def execute_node(self, context, graph): + # create a standard add node to help calculate the result + node = self.onnx_node + kernel_shape = self.get_nodeattr("PoolDim") + inp_values = context[node.input[0]] + dummy_out = context[node.output[0]] + # convert i/o NHWC -> NCHW + inp_values = np.transpose(inp_values, (0, 3, 1, 2)) + dummy_out = np.transpose(dummy_out, (0, 3, 1, 2)) + # execute as regular MaxPool + inp = helper.make_tensor_value_info(node.input[0], TensorProto.FLOAT, inp_values.shape) + outp = helper.make_tensor_value_info(node.output[0], TensorProto.FLOAT, dummy_out.shape) + node_mp = helper.make_node( + "MaxPool", + inputs=[node.input[0]], + outputs=[node.output[0]], + kernel_shape=kernel_shape, + strides=kernel_shape, + ) + graph_mp = helper.make_graph( + nodes=[node_mp], + name="single-mp-exec", + inputs=[inp], + outputs=[outp], + ) + + opset_version = self.onnx_opset_version + opset_imports = [helper.make_opsetid("", opset_version)] + onnx_kwargs = {"opset_imports": opset_imports} + model_mp = qonnx_make_model(graph_mp, **onnx_kwargs) + idict = {node.input[0]: inp_values} + sess = rt.InferenceSession(model_mp.SerializeToString()) + result = sess.run(None, idict) + result = np.asarray(result, dtype=np.float32).reshape(dummy_out.shape) + # convert output NCHW -> NHWC + result = np.transpose(result, (0, 2, 3, 1)) + context[node.output[0]] = result diff --git a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py index e3813eb709..7a896f5c96 100644 --- a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py +++ b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py @@ -32,6 +32,7 @@ import warnings from onnx import TensorProto, helper from qonnx.core.datatype import DataType +from qonnx.custom_op.registry import getCustomOp from qonnx.transformation.base import Transformation from qonnx.transformation.general import SortGraph from qonnx.transformation.infer_datatypes import InferDataTypes @@ -39,6 +40,61 @@ from qonnx.util.onnx import nchw_to_nhwc +class InferStreamingMaxPool(Transformation): + """Convert MaxPoolNHWC layers to StreamingMaxPool HW layers.""" + + def apply(self, model): + graph = model.graph + node_ind = 0 + graph_modified = False + for node in graph.node: + node_ind += 1 + if node.op_type == "MaxPoolNHWC": + mp_input = node.input[0] + mp_output = node.output[0] + mp_in_shape = model.get_tensor_shape(mp_input) + # mp_out_shape = model.get_tensor_shape(mp_output) + dt = model.get_tensor_datatype(mp_input) + mp_inst = getCustomOp(node) + k_h, k_w = mp_inst.get_nodeattr("kernel_shape") + ifm_ch = mp_in_shape[-1] + ifm_dim_h = mp_in_shape[1] + ifm_dim_w = mp_in_shape[2] + pe = 1 + ceil_mode = mp_inst.get_nodeattr("ceil_mode") + is_1d = (ifm_dim_h == 1 and k_h == 1) or (ifm_dim_w == 1 and k_w == 1) + is_divisable = (ifm_dim_h % k_h == 0) or (ifm_dim_w % k_w == 0) + is_bipolar = dt == DataType["BIPOLAR"] + pass_1d = is_1d and (not is_bipolar) + pass_2d = (not is_1d) and is_divisable + if pass_1d or pass_2d: + # create equivalent StreamingMaxPool_Batch node + new_node = helper.make_node( + "StreamingMaxPool", + [mp_input], + [mp_output], + domain="finn.custom_op.fpgadataflow", + backend="fpgadataflow", + PoolDim=(k_h, k_w), + NumChannels=ifm_ch, + ImgDim=(ifm_dim_h, ifm_dim_w), + dataType=dt.name, + PE=pe, + CeilMode=ceil_mode, + name="StreamingMaxPool_" + node.name, + ) + graph.node.insert(node_ind, new_node) + # remove old nodes + graph.node.remove(node) + graph_modified = True + else: + warnings.warn(node.name + ": could not convert to HW") + if graph_modified: + model = model.transform(InferShapes()) + model = model.transform(InferDataTypes()) + return (model, graph_modified) + + class InferAddStreamsLayer(Transformation): """Convert any Add into a AddStreams HW layer.""" diff --git a/tests/fpgadataflow/test_fpgadataflow_streamingmaxpool.py b/tests/fpgadataflow/test_fpgadataflow_streamingmaxpool.py index 67a40d96f3..643187cf66 100644 --- a/tests/fpgadataflow/test_fpgadataflow_streamingmaxpool.py +++ b/tests/fpgadataflow/test_fpgadataflow_streamingmaxpool.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (c) 2020-2022, Xilinx +# Copyright (C) 2023, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -40,12 +41,13 @@ import finn.core.onnx_exec as oxe from finn.analysis.fpgadataflow.exp_cycles_per_layer import exp_cycles_per_layer from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim -from finn.transformation.fpgadataflow.convert_to_hls_layers import InferStreamingMaxPool +from finn.transformation.fpgadataflow.convert_to_hw_layers import InferStreamingMaxPool from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers def make_single_maxpoolnhwc_modelwrapper(k, ifm_ch, ifm_dim, ofm_dim, idt, ceil_mode): @@ -138,10 +140,16 @@ def test_fpgadataflow_streamingmaxpool(idt, dim_1d, k, ifm_dim, ifm_ch, pe, ceil model = golden.transform(InferStreamingMaxPool()) model = model.transform(InferShapes()) - assert model.graph.node[0].op_type == "StreamingMaxPool_Batch" + assert model.graph.node[0].op_type == "StreamingMaxPool" + + # execute model + y_produced = oxe.execute_onnx(model, input_dict)["outp"] + assert (y_produced == y_expected).all() + + model = model.transform(SpecializeLayers()) # Ensure PE value is set - streamingmaxpool_node = model.get_nodes_by_op_type("StreamingMaxPool_Batch")[0] + streamingmaxpool_node = model.get_nodes_by_op_type("StreamingMaxPool_hls")[0] getCustomOp(streamingmaxpool_node).set_nodeattr("PE", pe) if exec_mode == "cppsim": @@ -162,7 +170,7 @@ def test_fpgadataflow_streamingmaxpool(idt, dim_1d, k, ifm_dim, ifm_ch, pe, ceil assert (y_produced == y_expected).all() if exec_mode == "rtlsim": - node = model.get_nodes_by_op_type("StreamingMaxPool_Batch")[0] + node = model.get_nodes_by_op_type("StreamingMaxPool_hls")[0] # inst = getCustomOp(node) # cycles_rtlsim = inst.get_nodeattr("cycles_rtlsim") exp_cycles_dict = model.analysis(exp_cycles_per_layer) From 30c027e49c73d35e9230f83c8f8f91c2c4ca068a Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 1 Dec 2023 12:09:33 +0000 Subject: [PATCH 349/665] [StreamingMaxPool] Fix execution hw layer for 1d case --- src/finn/custom_op/fpgadataflow/streamingmaxpool.py | 5 +++++ tests/fpgadataflow/test_fpgadataflow_streamingmaxpool.py | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/src/finn/custom_op/fpgadataflow/streamingmaxpool.py b/src/finn/custom_op/fpgadataflow/streamingmaxpool.py index 0f85a22993..1c2622c3d2 100755 --- a/src/finn/custom_op/fpgadataflow/streamingmaxpool.py +++ b/src/finn/custom_op/fpgadataflow/streamingmaxpool.py @@ -199,6 +199,11 @@ def execute_node(self, context, graph): # convert i/o NHWC -> NCHW inp_values = np.transpose(inp_values, (0, 3, 1, 2)) dummy_out = np.transpose(dummy_out, (0, 3, 1, 2)) + # handle 1d case + ishape = inp_values.shape + if ishape[2] == 1 or ishape[3] == 1: + inp_values = inp_values.reshape(ishape[0], ishape[1], ishape[2] * ishape[3]) + kernel_shape = [kernel_shape[0] * kernel_shape[1]] # execute as regular MaxPool inp = helper.make_tensor_value_info(node.input[0], TensorProto.FLOAT, inp_values.shape) outp = helper.make_tensor_value_info(node.output[0], TensorProto.FLOAT, dummy_out.shape) diff --git a/tests/fpgadataflow/test_fpgadataflow_streamingmaxpool.py b/tests/fpgadataflow/test_fpgadataflow_streamingmaxpool.py index 643187cf66..0df7181a60 100644 --- a/tests/fpgadataflow/test_fpgadataflow_streamingmaxpool.py +++ b/tests/fpgadataflow/test_fpgadataflow_streamingmaxpool.py @@ -94,7 +94,7 @@ def prepare_inputs(input_tensor): # input dimension @pytest.mark.parametrize("ifm_dim", [4, 10]) # input channels -@pytest.mark.parametrize("ifm_ch", [1, 3]) # 1,3 +@pytest.mark.parametrize("ifm_ch", [1, 3]) # pe @pytest.mark.parametrize("pe", [1, 3]) # ceil mode From b95c142bb9321c4986f2238a4e9ce1d4a8882b46 Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 1 Dec 2023 14:21:48 +0000 Subject: [PATCH 350/665] [StreamingMaxPool] Fix bug in execution and restrict conversion to hw layer --- src/finn/custom_op/fpgadataflow/streamingmaxpool.py | 2 ++ .../transformation/fpgadataflow/convert_to_hw_layers.py | 7 ++++++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/src/finn/custom_op/fpgadataflow/streamingmaxpool.py b/src/finn/custom_op/fpgadataflow/streamingmaxpool.py index 1c2622c3d2..59a8f092d0 100755 --- a/src/finn/custom_op/fpgadataflow/streamingmaxpool.py +++ b/src/finn/custom_op/fpgadataflow/streamingmaxpool.py @@ -194,6 +194,7 @@ def execute_node(self, context, graph): # create a standard add node to help calculate the result node = self.onnx_node kernel_shape = self.get_nodeattr("PoolDim") + ceil_mode = self.get_nodeattr("CeilMode") inp_values = context[node.input[0]] dummy_out = context[node.output[0]] # convert i/o NHWC -> NCHW @@ -213,6 +214,7 @@ def execute_node(self, context, graph): outputs=[node.output[0]], kernel_shape=kernel_shape, strides=kernel_shape, + ceil_mode=ceil_mode, ) graph_mp = helper.make_graph( nodes=[node_mp], diff --git a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py index 7a896f5c96..289b4edd5c 100644 --- a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py +++ b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py @@ -53,10 +53,15 @@ def apply(self, model): mp_input = node.input[0] mp_output = node.output[0] mp_in_shape = model.get_tensor_shape(mp_input) - # mp_out_shape = model.get_tensor_shape(mp_output) dt = model.get_tensor_datatype(mp_input) mp_inst = getCustomOp(node) k_h, k_w = mp_inst.get_nodeattr("kernel_shape") + s_h, s_w = mp_inst.get_nodeattr("strides") + if k_h != s_h or k_w != s_w: + warn_str = """Stride is not equal to kernel. Node cannot be converted to + StreamingMaxPool layer.""" + warnings.warn(warn_str) + continue ifm_ch = mp_in_shape[-1] ifm_dim_h = mp_in_shape[1] ifm_dim_w = mp_in_shape[2] From 0b0beebb49cce5dbc1ac0607387717a12ebe77cc Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 1 Dec 2023 15:43:55 +0000 Subject: [PATCH 351/665] [Upsampler] Initial draft of upsampler in new class hierarchy --- src/finn/custom_op/fpgadataflow/__init__.py | 4 +- .../custom_op/fpgadataflow/hls/__init__.py | 2 + .../fpgadataflow/hls/upsampler_hls.py | 254 +++++++++++++ src/finn/custom_op/fpgadataflow/upsampler.py | 246 +++--------- .../custom_op/fpgadataflow/upsampler_batch.py | 351 ++++++++++++++++++ .../fpgadataflow/convert_to_hw_layers.py | 98 +++++ .../test_fpgadataflow_upsampler.py | 43 +-- 7 files changed, 765 insertions(+), 233 deletions(-) create mode 100644 src/finn/custom_op/fpgadataflow/hls/upsampler_hls.py create mode 100644 src/finn/custom_op/fpgadataflow/upsampler_batch.py diff --git a/src/finn/custom_op/fpgadataflow/__init__.py b/src/finn/custom_op/fpgadataflow/__init__.py index 0a92b99fd4..9e90616ff8 100644 --- a/src/finn/custom_op/fpgadataflow/__init__.py +++ b/src/finn/custom_op/fpgadataflow/__init__.py @@ -71,7 +71,8 @@ from finn.custom_op.fpgadataflow.streamingmaxpool_batch import StreamingMaxPool_Batch from finn.custom_op.fpgadataflow.thresholding_batch import Thresholding_Batch from finn.custom_op.fpgadataflow.tlastmarker import TLastMarker -from finn.custom_op.fpgadataflow.upsampler import UpsampleNearestNeighbour_Batch +from finn.custom_op.fpgadataflow.upsampler import UpsampleNearestNeighbour +from finn.custom_op.fpgadataflow.upsampler_batch import UpsampleNearestNeighbour_Batch from finn.custom_op.fpgadataflow.vectorvectoractivation import VectorVectorActivation custom_op = dict() @@ -113,3 +114,4 @@ custom_op["GlobalAccPool"] = GlobalAccPool custom_op["LabelSelect"] = LabelSelect custom_op["StreamingMaxPool"] = StreamingMaxPool +custom_op["UpsampleNearestNeighbour"] = UpsampleNearestNeighbour diff --git a/src/finn/custom_op/fpgadataflow/hls/__init__.py b/src/finn/custom_op/fpgadataflow/hls/__init__.py index 96d0e6f6a9..f800054bfd 100644 --- a/src/finn/custom_op/fpgadataflow/hls/__init__.py +++ b/src/finn/custom_op/fpgadataflow/hls/__init__.py @@ -33,6 +33,7 @@ from finn.custom_op.fpgadataflow.hls.globalaccpool_hls import GlobalAccPool_hls from finn.custom_op.fpgadataflow.hls.labelselect_hls import LabelSelect_hls from finn.custom_op.fpgadataflow.hls.streamingmaxpool_hls import StreamingMaxPool_hls +from finn.custom_op.fpgadataflow.hls.upsampler_hls import UpsampleNearestNeighbour_hls custom_op = dict() @@ -45,3 +46,4 @@ custom_op["GlobalAccPool_hls"] = GlobalAccPool_hls custom_op["LabelSelect_hls"] = LabelSelect_hls custom_op["StreamingMaxPool_hls"] = StreamingMaxPool_hls +custom_op["UpsampleNearestNeighbour_hls"] = UpsampleNearestNeighbour_hls diff --git a/src/finn/custom_op/fpgadataflow/hls/upsampler_hls.py b/src/finn/custom_op/fpgadataflow/hls/upsampler_hls.py new file mode 100644 index 0000000000..89a474a5d3 --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/hls/upsampler_hls.py @@ -0,0 +1,254 @@ +# Copyright (C) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import numpy as np +from qonnx.core.datatype import DataType + +from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend +from finn.custom_op.fpgadataflow.upsampler import UpsampleNearestNeighbour +from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy + + +class UpsampleNearestNeighbour_hls(UpsampleNearestNeighbour, HLSBackend): + """ + Corresponds to finn-hlslib UpsampleNearestNeighbour_Batch function. + Upsampling is done with the Nearest Neighbour algorithm. + The layer expects square feature maps for the in and output. + """ + + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) + + def get_nodeattr_types(self): + my_attrs = {} + my_attrs.update(UpsampleNearestNeighbour.get_nodeattr_types(self)) + my_attrs.update(HLSBackend.get_nodeattr_types(self)) + return my_attrs + + def verify_node(self): + pass + + def global_includes(self): + self.code_gen_dict["$GLOBALS$"] = ['#include "upsample.hpp"'] + + def defines(self, var): + self.code_gen_dict["$DEFINES$"] = [] + + ifm_ch = self.get_nodeattr("NumChannels") + self.code_gen_dict["$DEFINES$"] += ["#define IFMChannels {}".format(ifm_ch)] + + ibits = self.get_input_datatype().bitwidth() + self.code_gen_dict["$DEFINES$"] += ["#define Input_precision {}".format(ibits)] + + idim = self.get_nodeattr("IFMDim") + self.code_gen_dict["$DEFINES$"] += ["#define IFMDim {}".format(idim)] + + odim = self.get_nodeattr("OFMDim") + self.code_gen_dict["$DEFINES$"] += ["#define OFMDim {}".format(odim)] + + batch_size = self.get_nodeattr("numInputVectors") + self.code_gen_dict["$DEFINES$"] += ["#define numReps {}".format(batch_size)] + + def read_npy_data(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_input_datatype() + if dtype == DataType["BIPOLAR"]: + # use binary for bipolar storage + dtype = DataType["BINARY"] + elem_bits = dtype.bitwidth() + packed_bits = self.get_instream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "float" + npy_in = "%s/input_0.npy" % code_gen_dir + self.code_gen_dict["$READNPYDATA$"] = [] + self.code_gen_dict["$READNPYDATA$"].append( + 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) + ) + + def strm_decl(self): + self.code_gen_dict["$STREAMDECLARATIONS$"] = [] + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> in0_{} ("in0_{}");'.format( + self.get_instream_width(), self.hls_sname(), self.hls_sname() + ) + ) + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> out_{} ("out_{}");'.format( + self.get_outstream_width(), self.hls_sname(), self.hls_sname() + ) + ) + + def docompute(self): + is_2d = self.get_nodeattr("DimMode") == 0 + batch = self.get_nodeattr("numInputVectors") + if is_2d: + self.code_gen_dict["$DOCOMPUTE$"] = [ + """UpsampleNearestNeighbour_Batch > (in0_%s, out_%s, numReps);""" + % (self.hls_sname(), self.hls_sname()) + ] + else: + assert batch == 1, "1D upsampler currently needs numReps=1" + self.code_gen_dict["$DOCOMPUTE$"] = [ + """UpsampleNearestNeighbour_1D > (in0_%s, out_%s);""" + % (self.hls_sname(), self.hls_sname()) + ] + + def dataoutstrm(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_output_datatype() + if dtype == DataType["BIPOLAR"]: + # use binary for bipolar storage + dtype = DataType["BINARY"] + elem_bits = dtype.bitwidth() + packed_bits = self.get_outstream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "float" + npy_out = "%s/output.npy" % code_gen_dir + oshape = self.get_folded_output_shape() + oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") + + self.code_gen_dict["$DATAOUTSTREAM$"] = [ + 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + self.hls_sname(), + oshape_cpp_str, + npy_out, + ) + ] + + def save_as_npy(self): + self.code_gen_dict["$SAVEASCNPY$"] = [] + + def blackboxfunction(self): + packed_bits = self.get_instream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ + "void %s(hls::stream<%s > &in0_%s, hls::stream<%s > &out_%s)" + % ( + self.onnx_node.name, + packed_hls_type, + self.hls_sname(), + packed_hls_type, + self.hls_sname(), + ) + ] + + def pragmas(self): + self.code_gen_dict["$PRAGMAS$"] = [ + "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() + ] + self.code_gen_dict["$PRAGMAS$"].append( + "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() + ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") + + def execute_node(self, context, graph): + mode = self.get_nodeattr("exec_mode") + node = self.onnx_node + exp_ishape = self.get_normal_input_shape() + exp_oshape = self.get_normal_output_shape() + folded_oshape = self.get_folded_output_shape() + + if mode == "cppsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + elif mode == "rtlsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + + inp = context[node.input[0]] + assert str(inp.dtype) == "float32", "Input datatype is not float32" + assert ( + inp.shape == exp_ishape + ), """Input shape doesn't + match expected shape (numInputVectors, ImgDim, ImgDim, NumChannels).""" + export_idt = self.get_input_datatype() + self.dynamic_input_to_npy(context, 1, target_dir=code_gen_dir) + + if mode == "cppsim": + # execute the precompiled model + super().exec_precompiled_singlenode_model() + # load output npy file + super().npy_to_dynamic_output(context) + assert ( + context[node.output[0]].shape == folded_oshape + ), "cppsim did not produce expected folded output shape" + context[node.output[0]] = context[node.output[0]].reshape(*exp_oshape) + elif mode == "rtlsim": + sim = self.get_rtlsim() + nbits = self.get_instream_width() + rtlsim_inp = npy_to_rtlsim_input( + "{}/input_0.npy".format(code_gen_dir), export_idt, nbits + ) + super().reset_rtlsim(sim) + super().toggle_clk(sim) + rtlsim_output = self.rtlsim(sim, rtlsim_inp) + odt = export_idt + target_bits = odt.bitwidth() + packed_bits = self.get_outstream_width() + out_npy_path = "{}/output.npy".format(code_gen_dir) + out_shape = self.get_folded_output_shape() + rtlsim_output_to_npy( + rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits + ) + # load and reshape output + output = np.load(out_npy_path) + output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) + context[node.output[0]] = output + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + assert ( + context[node.output[0]].shape == exp_oshape + ), """Output shape doesn't match expected shape + (1, OutputDim, OutputDim, NumChannels).""" diff --git a/src/finn/custom_op/fpgadataflow/upsampler.py b/src/finn/custom_op/fpgadataflow/upsampler.py index 9c0db1f3df..b0264ffa8a 100644 --- a/src/finn/custom_op/fpgadataflow/upsampler.py +++ b/src/finn/custom_op/fpgadataflow/upsampler.py @@ -1,4 +1,4 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2023, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -27,19 +27,17 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import numpy as np +import onnxruntime as rt import warnings +from onnx import TensorProto, helper from qonnx.core.datatype import DataType +from qonnx.util.basic import qonnx_make_model -from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp -from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy +from finn.custom_op.fpgadataflow.hwcustomop import HWCustomOp -class UpsampleNearestNeighbour_Batch(HLSCustomOp): - """ - Corresponds to finn-hlslib UpsampleNearestNeighbour_Batch function. - Upsampling is done with the Nearest Neighbour algorithm. - The layer expects square feature maps for the in and output. - """ +class UpsampleNearestNeighbour(HWCustomOp): + """Abstraction layer for HW implementation of UpsampleNearestNeighbour.""" def __init__(self, onnx_node, **kwargs): super().__init__(onnx_node, **kwargs) @@ -150,202 +148,44 @@ def get_number_output_values(self): folded_oshape = self.get_folded_output_shape() return np.prod(folded_oshape[:-1]) - def global_includes(self): - self.code_gen_dict["$GLOBALS$"] = ['#include "upsample.hpp"'] - - def defines(self, var): - self.code_gen_dict["$DEFINES$"] = [] - - ifm_ch = self.get_nodeattr("NumChannels") - self.code_gen_dict["$DEFINES$"] += ["#define IFMChannels {}".format(ifm_ch)] - - ibits = self.get_input_datatype().bitwidth() - self.code_gen_dict["$DEFINES$"] += ["#define Input_precision {}".format(ibits)] - - idim = self.get_nodeattr("IFMDim") - self.code_gen_dict["$DEFINES$"] += ["#define IFMDim {}".format(idim)] - - odim = self.get_nodeattr("OFMDim") - self.code_gen_dict["$DEFINES$"] += ["#define OFMDim {}".format(odim)] - - batch_size = self.get_nodeattr("numInputVectors") - self.code_gen_dict["$DEFINES$"] += ["#define numReps {}".format(batch_size)] - - def read_npy_data(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_input_datatype() - if dtype == DataType["BIPOLAR"]: - # use binary for bipolar storage - dtype = DataType["BINARY"] - elem_bits = dtype.bitwidth() - packed_bits = self.get_instream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_in = "%s/input_0.npy" % code_gen_dir - self.code_gen_dict["$READNPYDATA$"] = [] - self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - npy_in, - self.hls_sname(), - ) - ) - - def strm_decl(self): - self.code_gen_dict["$STREAMDECLARATIONS$"] = [] - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0_{} ("in0_{}");'.format( - self.get_instream_width(), self.hls_sname(), self.hls_sname() - ) - ) - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out_{} ("out_{}");'.format( - self.get_outstream_width(), self.hls_sname(), self.hls_sname() - ) - ) - - def docompute(self): - is_2d = self.get_nodeattr("DimMode") == 0 - batch = self.get_nodeattr("numInputVectors") - if is_2d: - self.code_gen_dict["$DOCOMPUTE$"] = [ - """UpsampleNearestNeighbour_Batch > (in0_%s, out_%s, numReps);""" - % (self.hls_sname(), self.hls_sname()) - ] - else: - assert batch == 1, "1D upsampler currently needs numReps=1" - self.code_gen_dict["$DOCOMPUTE$"] = [ - """UpsampleNearestNeighbour_1D > (in0_%s, out_%s);""" - % (self.hls_sname(), self.hls_sname()) - ] - - def dataoutstrm(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_output_datatype() - if dtype == DataType["BIPOLAR"]: - # use binary for bipolar storage - dtype = DataType["BINARY"] - elem_bits = dtype.bitwidth() - packed_bits = self.get_outstream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_out = "%s/output.npy" % code_gen_dir - oshape = self.get_folded_output_shape() - oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") - - self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - self.hls_sname(), - oshape_cpp_str, - npy_out, - ) - ] - - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - - def blackboxfunction(self): - packed_bits = self.get_instream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - "void %s(hls::stream<%s > &in0_%s, hls::stream<%s > &out_%s)" - % ( - self.onnx_node.name, - packed_hls_type, - self.hls_sname(), - packed_hls_type, - self.hls_sname(), - ) - ] - - def pragmas(self): - self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() - ] - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() - ) - self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") - def execute_node(self, context, graph): - mode = self.get_nodeattr("exec_mode") + # create a standard add node to help calculate the result node = self.onnx_node - exp_ishape = self.get_normal_input_shape() - exp_oshape = self.get_normal_output_shape() - folded_oshape = self.get_folded_output_shape() - - if mode == "cppsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - elif mode == "rtlsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + inp_values = context[node.input[0]] + ishape = inp_values.shape + odim = self.get_nodeattr("OFMDim") + idim = self.get_nodeattr("IFMDim") + if ishape[1] == ishape[2]: + scales_val = [1, int(round(odim / idim)), int(round(odim / idim)), 1] + elif ishape[1] > 1 and ishape[2] == 1: + scales_val = [1, int(round(odim / idim)), 1, 1] else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) + warnings.warn( + """HW abstraction layer for Upsample cannot be executed. + Upsampling only supported for 1D H, or 2D square scaling""" ) + oshape = context[node.output[0]].shape + inp = helper.make_tensor_value_info(node.input[0], TensorProto.FLOAT, ishape) + scales = helper.make_tensor_value_info("scales", TensorProto.FLOAT, [4]) + outp = helper.make_tensor_value_info(node.output[0], TensorProto.FLOAT, oshape) + node_resize = helper.make_node( + "Resize", + inputs=[node.input[0], "", "scales"], + outputs=[node.output[0]], + mode="nearest", + ) + graph_resize = helper.make_graph( + nodes=[node_resize], + name="single-resize-exec", + inputs=[inp, scales], + outputs=[outp], + ) - inp = context[node.input[0]] - assert str(inp.dtype) == "float32", "Input datatype is not float32" - assert ( - inp.shape == exp_ishape - ), """Input shape doesn't - match expected shape (numInputVectors, ImgDim, ImgDim, NumChannels).""" - export_idt = self.get_input_datatype() - self.dynamic_input_to_npy(context, 1, target_dir=code_gen_dir) - - if mode == "cppsim": - # execute the precompiled model - super().exec_precompiled_singlenode_model() - # load output npy file - super().npy_to_dynamic_output(context) - assert ( - context[node.output[0]].shape == folded_oshape - ), "cppsim did not produce expected folded output shape" - context[node.output[0]] = context[node.output[0]].reshape(*exp_oshape) - elif mode == "rtlsim": - sim = self.get_rtlsim() - nbits = self.get_instream_width() - rtlsim_inp = npy_to_rtlsim_input( - "{}/input_0.npy".format(code_gen_dir), export_idt, nbits - ) - super().reset_rtlsim(sim) - super().toggle_clk(sim) - rtlsim_output = self.rtlsim(sim, rtlsim_inp) - odt = export_idt - target_bits = odt.bitwidth() - packed_bits = self.get_outstream_width() - out_npy_path = "{}/output.npy".format(code_gen_dir) - out_shape = self.get_folded_output_shape() - rtlsim_output_to_npy( - rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits - ) - # load and reshape output - output = np.load(out_npy_path) - output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) - context[node.output[0]] = output - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) - assert ( - context[node.output[0]].shape == exp_oshape - ), """Output shape doesn't match expected shape - (1, OutputDim, OutputDim, NumChannels).""" + opset_version = 13 + opset_imports = [helper.make_opsetid("", opset_version)] + onnx_kwargs = {"opset_imports": opset_imports} + model_resize = qonnx_make_model(graph_resize, **onnx_kwargs) + idict = {node.input[0]: inp_values, "scales": scales_val} + sess = rt.InferenceSession(model_resize.SerializeToString()) + result = sess.run(None, idict) + context[node.output[0]] = np.asarray(result, dtype=np.float32).reshape(oshape) diff --git a/src/finn/custom_op/fpgadataflow/upsampler_batch.py b/src/finn/custom_op/fpgadataflow/upsampler_batch.py new file mode 100644 index 0000000000..9c0db1f3df --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/upsampler_batch.py @@ -0,0 +1,351 @@ +# Copyright (c) 2020, Xilinx +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import numpy as np +import warnings +from qonnx.core.datatype import DataType + +from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp +from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy + + +class UpsampleNearestNeighbour_Batch(HLSCustomOp): + """ + Corresponds to finn-hlslib UpsampleNearestNeighbour_Batch function. + Upsampling is done with the Nearest Neighbour algorithm. + The layer expects square feature maps for the in and output. + """ + + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) + + def get_nodeattr_types(self): + my_attrs = { + # Size of the output feature map + "OFMDim": ("i", True, 0), + # Size of the input feature map + "IFMDim": ("i", True, 0), + # Amount of channels of the input feature map + "NumChannels": ("i", True, 0), + # FINN input datatype + "inputDataType": ("s", True, ""), + # Batch size + "numInputVectors": ("i", False, 1), + # Dimensionality mode: 0 = 2D square, 1 = 1D in H dim + "DimMode": ("i", False, 0), + } + my_attrs.update(super().get_nodeattr_types()) + return my_attrs + + def get_exp_cycles(self): + OFMDim = self.get_nodeattr("OFMDim") + batch_size = self.get_nodeattr("numInputVectors") + is_2d = self.get_nodeattr("DimMode") == 0 + reps = 1 + if is_2d: + OFMDim = OFMDim * OFMDim + reps = batch_size + exp_cycles = OFMDim * reps + return int(exp_cycles) + + def get_normal_input_shape(self, ind=0): + IFMDim = self.get_nodeattr("IFMDim") + num_ch = self.get_nodeattr("NumChannels") + batch = self.get_nodeattr("numInputVectors") + is_2d = self.get_nodeattr("DimMode") == 0 + if is_2d: + ishape = (batch, IFMDim, IFMDim, num_ch) + else: + ishape = (batch, IFMDim, 1, num_ch) + return ishape + + def get_normal_output_shape(self, ind=0): + OFMDim = self.get_nodeattr("OFMDim") + num_ch = self.get_nodeattr("NumChannels") + batch = self.get_nodeattr("numInputVectors") + is_2d = self.get_nodeattr("DimMode") == 0 + if is_2d: + oshape = (batch, OFMDim, OFMDim, num_ch) + else: + oshape = (batch, OFMDim, 1, num_ch) + return oshape + + def get_folded_input_shape(self, ind=0): + normal_ishape = list(self.get_normal_input_shape()) + return tuple(normal_ishape) + + def get_folded_output_shape(self, ind=0): + normal_oshape = list(self.get_normal_output_shape()) + return tuple(normal_oshape) + + def make_shape_compatible_op(self, model): + exp_ishape = self.get_normal_input_shape() + oshape = self.get_normal_output_shape() + ishape = tuple(model.get_tensor_shape(self.onnx_node.input[0])) + assert ishape == exp_ishape, "Unexpect input shape for UpsampleNearestNeighbour_Batch." + return super().make_const_shape_op(oshape) + + def infer_node_datatype(self, model): + node = self.onnx_node + # data type stays the same + idt = model.get_tensor_datatype(node.input[0]) + if idt != self.get_input_datatype(): + warn_str = "inputDataType changing for %s: %s -> %s " % ( + node.name, + str(self.get_input_datatype()), + str(idt), + ) + warnings.warn(warn_str) + self.set_nodeattr("inputDataType", idt.name) + model.set_tensor_datatype(node.output[0], idt) + + def verify_node(self): + pass + + def get_input_datatype(self, ind=0): + """Returns FINN DataType of input.""" + ret = DataType[self.get_nodeattr("inputDataType")] + return ret + + def get_output_datatype(self, ind=0): + """Returns FINN DataType of output. (Same as input datatype)""" + return self.get_input_datatype() + + def get_instream_width(self, ind=0): + ibits = self.get_input_datatype().bitwidth() + ifm_ch = self.get_nodeattr("NumChannels") + return ibits * ifm_ch + + def get_outstream_width(self, ind=0): + obits = self.get_output_datatype().bitwidth() + ifm_ch = self.get_nodeattr("NumChannels") + return obits * ifm_ch + + def get_number_output_values(self): + folded_oshape = self.get_folded_output_shape() + return np.prod(folded_oshape[:-1]) + + def global_includes(self): + self.code_gen_dict["$GLOBALS$"] = ['#include "upsample.hpp"'] + + def defines(self, var): + self.code_gen_dict["$DEFINES$"] = [] + + ifm_ch = self.get_nodeattr("NumChannels") + self.code_gen_dict["$DEFINES$"] += ["#define IFMChannels {}".format(ifm_ch)] + + ibits = self.get_input_datatype().bitwidth() + self.code_gen_dict["$DEFINES$"] += ["#define Input_precision {}".format(ibits)] + + idim = self.get_nodeattr("IFMDim") + self.code_gen_dict["$DEFINES$"] += ["#define IFMDim {}".format(idim)] + + odim = self.get_nodeattr("OFMDim") + self.code_gen_dict["$DEFINES$"] += ["#define OFMDim {}".format(odim)] + + batch_size = self.get_nodeattr("numInputVectors") + self.code_gen_dict["$DEFINES$"] += ["#define numReps {}".format(batch_size)] + + def read_npy_data(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_input_datatype() + if dtype == DataType["BIPOLAR"]: + # use binary for bipolar storage + dtype = DataType["BINARY"] + elem_bits = dtype.bitwidth() + packed_bits = self.get_instream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "float" + npy_in = "%s/input_0.npy" % code_gen_dir + self.code_gen_dict["$READNPYDATA$"] = [] + self.code_gen_dict["$READNPYDATA$"].append( + 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) + ) + + def strm_decl(self): + self.code_gen_dict["$STREAMDECLARATIONS$"] = [] + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> in0_{} ("in0_{}");'.format( + self.get_instream_width(), self.hls_sname(), self.hls_sname() + ) + ) + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> out_{} ("out_{}");'.format( + self.get_outstream_width(), self.hls_sname(), self.hls_sname() + ) + ) + + def docompute(self): + is_2d = self.get_nodeattr("DimMode") == 0 + batch = self.get_nodeattr("numInputVectors") + if is_2d: + self.code_gen_dict["$DOCOMPUTE$"] = [ + """UpsampleNearestNeighbour_Batch > (in0_%s, out_%s, numReps);""" + % (self.hls_sname(), self.hls_sname()) + ] + else: + assert batch == 1, "1D upsampler currently needs numReps=1" + self.code_gen_dict["$DOCOMPUTE$"] = [ + """UpsampleNearestNeighbour_1D > (in0_%s, out_%s);""" + % (self.hls_sname(), self.hls_sname()) + ] + + def dataoutstrm(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_output_datatype() + if dtype == DataType["BIPOLAR"]: + # use binary for bipolar storage + dtype = DataType["BINARY"] + elem_bits = dtype.bitwidth() + packed_bits = self.get_outstream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "float" + npy_out = "%s/output.npy" % code_gen_dir + oshape = self.get_folded_output_shape() + oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") + + self.code_gen_dict["$DATAOUTSTREAM$"] = [ + 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + self.hls_sname(), + oshape_cpp_str, + npy_out, + ) + ] + + def save_as_npy(self): + self.code_gen_dict["$SAVEASCNPY$"] = [] + + def blackboxfunction(self): + packed_bits = self.get_instream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ + "void %s(hls::stream<%s > &in0_%s, hls::stream<%s > &out_%s)" + % ( + self.onnx_node.name, + packed_hls_type, + self.hls_sname(), + packed_hls_type, + self.hls_sname(), + ) + ] + + def pragmas(self): + self.code_gen_dict["$PRAGMAS$"] = [ + "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() + ] + self.code_gen_dict["$PRAGMAS$"].append( + "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() + ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") + + def execute_node(self, context, graph): + mode = self.get_nodeattr("exec_mode") + node = self.onnx_node + exp_ishape = self.get_normal_input_shape() + exp_oshape = self.get_normal_output_shape() + folded_oshape = self.get_folded_output_shape() + + if mode == "cppsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + elif mode == "rtlsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + + inp = context[node.input[0]] + assert str(inp.dtype) == "float32", "Input datatype is not float32" + assert ( + inp.shape == exp_ishape + ), """Input shape doesn't + match expected shape (numInputVectors, ImgDim, ImgDim, NumChannels).""" + export_idt = self.get_input_datatype() + self.dynamic_input_to_npy(context, 1, target_dir=code_gen_dir) + + if mode == "cppsim": + # execute the precompiled model + super().exec_precompiled_singlenode_model() + # load output npy file + super().npy_to_dynamic_output(context) + assert ( + context[node.output[0]].shape == folded_oshape + ), "cppsim did not produce expected folded output shape" + context[node.output[0]] = context[node.output[0]].reshape(*exp_oshape) + elif mode == "rtlsim": + sim = self.get_rtlsim() + nbits = self.get_instream_width() + rtlsim_inp = npy_to_rtlsim_input( + "{}/input_0.npy".format(code_gen_dir), export_idt, nbits + ) + super().reset_rtlsim(sim) + super().toggle_clk(sim) + rtlsim_output = self.rtlsim(sim, rtlsim_inp) + odt = export_idt + target_bits = odt.bitwidth() + packed_bits = self.get_outstream_width() + out_npy_path = "{}/output.npy".format(code_gen_dir) + out_shape = self.get_folded_output_shape() + rtlsim_output_to_npy( + rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits + ) + # load and reshape output + output = np.load(out_npy_path) + output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) + context[node.output[0]] = output + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + assert ( + context[node.output[0]].shape == exp_oshape + ), """Output shape doesn't match expected shape + (1, OutputDim, OutputDim, NumChannels).""" diff --git a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py index 289b4edd5c..1c2dfeca96 100644 --- a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py +++ b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py @@ -37,9 +37,107 @@ from qonnx.transformation.general import SortGraph from qonnx.transformation.infer_datatypes import InferDataTypes from qonnx.transformation.infer_shapes import InferShapes +from qonnx.util.basic import get_by_name from qonnx.util.onnx import nchw_to_nhwc +class InferUpsample(Transformation): + """Convert Upsample and Resize nodes to layers to UpsampleNearestNeighbour nodes.""" + + def apply(self, model): + graph = model.graph + node_ind = 0 + graph_modified = False + for n in graph.node: + node_ind += 1 + if n.op_type == "Upsample" or n.op_type == "Resize": + # Extract mode and scales and input shape + mode = get_by_name(n.attribute, "mode").s.decode("ascii") + if n.op_type == "Upsample": + scales = model.get_initializer(n.input[1]) + else: + scales = model.get_initializer(n.input[2]) + in_shape = model.get_tensor_shape(n.input[0]) + + dt = model.get_tensor_datatype(n.input[0]) + if not dt.is_integer(): + warnings.warn( + "%s: Input not int. Can't infer UpsampleNearestNeighbour." % n.name + ) + continue + + if model.get_tensor_layout(n.input[0]) != DataLayout.NHWC: + warnings.warn( + "%s: Input not NHWC. Can't infer UpsampleNearestNeighbour." % n.name + ) + continue + + # Check that the parameters are okay + assert mode == "nearest", ( + "%s: Upsampling is only supported for the mode nearest." % n.name + ) + assert len(in_shape) == 4, "Upsampling is only supported for 4D inputs." + assert scales.shape == (4,), ( + "%s: Upsampling is only supported for 4D scales." % n.name + ) + assert (scales >= 1).all(), ( + n.name + ": Upsampling is only supported for scales " + "which are larger or equal 1 in all dimensions." + ) + + # Assumes nhwc layout for scales and input + is_scale_square_2d = scales[1] == scales[2] + is_scale_1d = scales[1] > 1 and scales[2] == 1 + assert is_scale_square_2d or is_scale_1d, ( + "%s: Upsampling only supported for 1D H, or 2D square scaling" % n.name + ) + assert scales[0] == scales[3] == 1, ( + n.name + ": Upsampling is only supported for scales with " + "the first and last dimensions being 1 in NHWC." + ) + spatial_scale = scales[1] + assert spatial_scale == int(spatial_scale), ( + "%s: Upsampling is only supported for integer scales." % n.name + ) + is_shape_square_2d = in_shape[1] == in_shape[2] + is_shape_1d = in_shape[1] > 1 and in_shape[2] == 1 + + assert is_shape_square_2d or is_shape_1d, ( + "%s: Upsampling is only supported for 1D H or 2D square inputs." % n.name + ) + + # Extract information for HW node + IFMDim = in_shape[1] + OFMDim = int(round(in_shape[1] * spatial_scale)) + NumChannels = in_shape[-1] + numInputVectors = in_shape[0] + inputDataType = dt.name + dim_mode = 0 if is_shape_square_2d else 1 + + # Insert the HWCustomOp node + Upsample_HW_node = helper.make_node( + "UpsampleNearestNeighbour", + [n.input[0]], + [n.output[0]], + domain="finn.custom_op.fpgadataflow", + backend="fpgadataflow", + OFMDim=OFMDim, + IFMDim=IFMDim, + NumChannels=NumChannels, + inputDataType=inputDataType, + numInputVectors=numInputVectors, + DimMode=dim_mode, + name="UpsampleNearestNeighbour_" + n.name, + ) + + # Remove the old node + graph.node.insert(node_ind, Upsample_HW_node) + # remove old nodes + graph.node.remove(n) + graph_modified = True + return (model, graph_modified) + + class InferStreamingMaxPool(Transformation): """Convert MaxPoolNHWC layers to StreamingMaxPool HW layers.""" diff --git a/tests/fpgadataflow/test_fpgadataflow_upsampler.py b/tests/fpgadataflow/test_fpgadataflow_upsampler.py index 70d81c7d31..b0da767eaa 100644 --- a/tests/fpgadataflow/test_fpgadataflow_upsampler.py +++ b/tests/fpgadataflow/test_fpgadataflow_upsampler.py @@ -48,12 +48,13 @@ import finn.core.onnx_exec as oxe import finn.transformation.streamline.absorb as absorb from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim -from finn.transformation.fpgadataflow.convert_to_hls_layers import InferUpsample +from finn.transformation.fpgadataflow.convert_to_hw_layers import InferUpsample from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers from finn.transformation.qonnx.convert_qonnx_to_finn import ConvertQONNXtoFINN from finn.util.basic import make_build_dir @@ -84,29 +85,6 @@ def apply(self, model): _to_chan_first_args = (0, 3, 1, 2) -class TransposeUpsampleIO(Transformation): - """ - Converts the inputs outputs for all Upsample and Resize nodes - from NCHW to NHWC. - """ - - def apply(self, model): - graph = model.graph - for n in graph.node: - if n.op_type == "Upsample" or n.op_type == "Resize": - # Set input shape - inp = n.input[0] - NCHW_shape = model.get_tensor_shape(inp) - NHWC_shape = [NCHW_shape[idx] for idx in _to_chan_last_args] - model.set_tensor_shape(inp, NHWC_shape) - # Set output shape - out = n.output[0] - NCHW_shape = model.get_tensor_shape(out) - NHWC_shape = [NCHW_shape[idx] for idx in _to_chan_last_args] - model.set_tensor_shape(out, NHWC_shape) - return model, False - - class PyTorchTestModel(nn.Module): def __init__(self, upscale_factor=2): super(PyTorchTestModel, self).__init__() @@ -173,7 +151,6 @@ def test_fpgadataflow_upsampler(dt, IFMDim, scale, NumChannels, exec_mode, is_1d # Prep model for execution model = ModelWrapper(export_path) - # model = model.transform(TransposeUpsampleIO()) model = model.transform(MakeInputChannelsLast()) model = model.transform(InferDataLayouts()) model = model.transform(absorb.AbsorbTransposeIntoResize()) @@ -186,8 +163,18 @@ def test_fpgadataflow_upsampler(dt, IFMDim, scale, NumChannels, exec_mode, is_1d # Check that all nodes are UpsampleNearestNeighbour_Batch nodes for n in model.get_finn_nodes(): - node_check = n.op_type == "UpsampleNearestNeighbour_Batch" - assert node_check, "All nodes should be UpsampleNearestNeighbour_Batch nodes." + node_check = n.op_type == "UpsampleNearestNeighbour" + assert node_check, "All nodes should be UpsampleNearestNeighbour nodes." + + test_in_transposed = test_in.numpy().transpose(_to_chan_last_args) + input_dict = {model.graph.input[0].name: test_in_transposed} + + # Run sim + output_dict = oxe.execute_onnx(model, input_dict, True) + test_result = output_dict[model.graph.output[0].name] + output_matches = np.isclose(golden_result, test_result, atol=atol).all() + + model = model.transform(SpecializeLayers()) # Prep sim if exec_mode == "cppsim": @@ -204,8 +191,6 @@ def test_fpgadataflow_upsampler(dt, IFMDim, scale, NumChannels, exec_mode, is_1d raise Exception("Unknown exec_mode") # Run sim - test_in_transposed = test_in.numpy().transpose(_to_chan_last_args) - input_dict = {model.graph.input[0].name: test_in_transposed} output_dict = oxe.execute_onnx(model, input_dict, True) test_result = output_dict[model.graph.output[0].name] output_matches = np.isclose(golden_result, test_result, atol=atol).all() From 807bad1f52a0672863e9182a6396186d5f2243e1 Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 1 Dec 2023 16:37:16 +0000 Subject: [PATCH 352/665] [Eltwise] Initial draft of upsampler in new class hierarchy --- src/finn/custom_op/fpgadataflow/__init__.py | 4 +- .../custom_op/fpgadataflow/hls/__init__.py | 2 + .../fpgadataflow/hls/streamingeltwise_hls.py | 336 ++++++++++++++++++ .../fpgadataflow/streamingeltwise.py | 216 +++++++++++ .../fpgadataflow/convert_to_hw_layers.py | 95 +++++ .../fpgadataflow/test_fpgadataflow_eltwise.py | 16 +- 6 files changed, 664 insertions(+), 5 deletions(-) create mode 100644 src/finn/custom_op/fpgadataflow/hls/streamingeltwise_hls.py create mode 100644 src/finn/custom_op/fpgadataflow/streamingeltwise.py diff --git a/src/finn/custom_op/fpgadataflow/__init__.py b/src/finn/custom_op/fpgadataflow/__init__.py index 9e90616ff8..6fe7993643 100644 --- a/src/finn/custom_op/fpgadataflow/__init__.py +++ b/src/finn/custom_op/fpgadataflow/__init__.py @@ -45,7 +45,6 @@ from finn.custom_op.fpgadataflow.downsampler import DownSampler from finn.custom_op.fpgadataflow.duplicatestreams import DuplicateStreams from finn.custom_op.fpgadataflow.duplicatestreams_batch import DuplicateStreams_Batch -from finn.custom_op.fpgadataflow.eltwise import StreamingEltwise from finn.custom_op.fpgadataflow.fmpadding import FMPadding from finn.custom_op.fpgadataflow.fmpadding_batch import FMPadding_Batch from finn.custom_op.fpgadataflow.fmpadding_rtl import FMPadding_rtl @@ -66,6 +65,7 @@ from finn.custom_op.fpgadataflow.streamingdatawidthconverter_rtl import ( StreamingDataWidthConverter_rtl, ) +from finn.custom_op.fpgadataflow.streamingeltwise import StreamingEltwise from finn.custom_op.fpgadataflow.streamingfifo import StreamingFIFO from finn.custom_op.fpgadataflow.streamingmaxpool import StreamingMaxPool from finn.custom_op.fpgadataflow.streamingmaxpool_batch import StreamingMaxPool_Batch @@ -104,7 +104,6 @@ custom_op["Lookup"] = Lookup custom_op["StreamingConcat"] = StreamingConcat custom_op["CheckSum"] = CheckSum -custom_op["StreamingEltwise"] = StreamingEltwise custom_op["FMPadding_rtl"] = FMPadding_rtl custom_op["FMPadding"] = FMPadding @@ -113,5 +112,6 @@ custom_op["DuplicateStreams"] = DuplicateStreams custom_op["GlobalAccPool"] = GlobalAccPool custom_op["LabelSelect"] = LabelSelect +custom_op["StreamingEltwise"] = StreamingEltwise custom_op["StreamingMaxPool"] = StreamingMaxPool custom_op["UpsampleNearestNeighbour"] = UpsampleNearestNeighbour diff --git a/src/finn/custom_op/fpgadataflow/hls/__init__.py b/src/finn/custom_op/fpgadataflow/hls/__init__.py index f800054bfd..df58decf81 100644 --- a/src/finn/custom_op/fpgadataflow/hls/__init__.py +++ b/src/finn/custom_op/fpgadataflow/hls/__init__.py @@ -32,6 +32,7 @@ from finn.custom_op.fpgadataflow.hls.fmpadding_hls import FMPadding_hls from finn.custom_op.fpgadataflow.hls.globalaccpool_hls import GlobalAccPool_hls from finn.custom_op.fpgadataflow.hls.labelselect_hls import LabelSelect_hls +from finn.custom_op.fpgadataflow.hls.streamingeltwise_hls import StreamingEltwise_hls from finn.custom_op.fpgadataflow.hls.streamingmaxpool_hls import StreamingMaxPool_hls from finn.custom_op.fpgadataflow.hls.upsampler_hls import UpsampleNearestNeighbour_hls @@ -45,5 +46,6 @@ custom_op["FMPadding_hls"] = FMPadding_hls custom_op["GlobalAccPool_hls"] = GlobalAccPool_hls custom_op["LabelSelect_hls"] = LabelSelect_hls +custom_op["StreamingEltwise_hls"] = StreamingEltwise_hls custom_op["StreamingMaxPool_hls"] = StreamingMaxPool_hls custom_op["UpsampleNearestNeighbour_hls"] = UpsampleNearestNeighbour_hls diff --git a/src/finn/custom_op/fpgadataflow/hls/streamingeltwise_hls.py b/src/finn/custom_op/fpgadataflow/hls/streamingeltwise_hls.py new file mode 100644 index 0000000000..2aec40f988 --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/hls/streamingeltwise_hls.py @@ -0,0 +1,336 @@ +# Copyright (C) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import numpy as np +import os + +from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend +from finn.custom_op.fpgadataflow.streamingeltwise import StreamingEltwise +from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy + + +class StreamingEltwise_hls(StreamingEltwise, HLSBackend): + """Class that corresponds to finn-hlslib StreamingEltwise function.""" + + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) + + def get_nodeattr_types(self): + my_attrs = {} + my_attrs.update(StreamingEltwise.get_nodeattr_types(self)) + my_attrs.update(HLSBackend.get_nodeattr_types(self)) + return my_attrs + + def verify_node(self): + info_messages = [] + # verify that "backend" is set to "fpgadataflow" + backend_value = self.get_nodeattr("backend") + if backend_value == "fpgadataflow": + info_messages.append("Attribute backend is set correctly") + else: + info_messages.append('Attribute backend should be set to "fpgadataflow"') + + # verify that all necessary attributes exist + try: + self.get_nodeattr("code_gen_dir_cppsim") + self.get_nodeattr("executable_path") + self.get_nodeattr("NumChannels") + self.get_nodeattr("PE") + self.get_nodeattr("inputDataType0") + self.get_nodeattr("inputDataType1") + self.get_nodeattr("eltwiseOp") + info_messages.append("All necessary attributes exist") + except Exception: + info_messages.append("""The required StreamingEltwise attributes do not exist.""") + + return info_messages + + def execute_node(self, context, graph): + mode = self.get_nodeattr("exec_mode") + node = self.onnx_node + exp_ishape = self.get_normal_input_shape() + exp_oshape = self.get_normal_output_shape() + folded_ishape = self.get_folded_input_shape() + + if mode == "cppsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + elif mode == "rtlsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + + inp = context[node.input[0]] + assert str(inp.dtype) == "float32", "Input datatype is not float32" + assert inp.shape == exp_ishape, """Input0 shape doesn't match expected shape .""" + export_idt0 = self.get_input_datatype(0) + # reshape input into folded form + inp = inp.reshape(folded_ishape) + # make copy before saving array + reshaped_input = inp.copy() + np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input) + + # exact same thing for input1 + inp = context[node.input[1]] + assert str(inp.dtype) == "float32", "Input datatype is not float32" + assert inp.shape == exp_ishape, """Input1 shape doesn't match expected shape .""" + export_idt1 = self.get_input_datatype(1) + # reshape input into folded form + inp = inp.reshape(folded_ishape) + # make copy before saving array + reshaped_input = inp.copy() + np.save(os.path.join(code_gen_dir, "input_1.npy"), reshaped_input) + + if mode == "cppsim": + # execute the precompiled model + super().exec_precompiled_singlenode_model() + # load output npy file + super().npy_to_dynamic_output(context) + assert ( + context[node.output[0]].shape == exp_oshape + ), "cppsim did not produce expected output shape" + elif mode == "rtlsim": + sim = self.get_rtlsim() + nbits0 = self.get_instream_width(0) + nbits1 = self.get_instream_width(1) + rtlsim_inp0 = npy_to_rtlsim_input( + "{}/input_0.npy".format(code_gen_dir), export_idt0, nbits0 + ) + rtlsim_inp1 = npy_to_rtlsim_input( + "{}/input_1.npy".format(code_gen_dir), export_idt1, nbits1 + ) + super().reset_rtlsim(sim) + super().toggle_clk(sim) + rtlsim_output = self.rtlsim(sim, rtlsim_inp0, rtlsim_inp1) + odt = self.get_output_datatype() + target_bits = odt.bitwidth() + packed_bits = self.get_outstream_width() + out_npy_path = "{}/output.npy".format(code_gen_dir) + out_shape = self.get_folded_output_shape() + rtlsim_output_to_npy( + rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits + ) + # load and reshape output + output = np.load(out_npy_path) + output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) + context[node.output[0]] = output + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + + assert ( + context[node.output[0]].shape == exp_oshape + ), """Output shape doesn't match expected shape.""" + + def global_includes(self): + self.code_gen_dict["$GLOBALS$"] = [ + '#include "eltwise.hpp"', + '#include "interpret.hpp"', + ] + + self.code_gen_dict["$GLOBALS$"].extend( + [ + "template", + "struct absdiff {", + "TO operator()(TI1 const &a, TI2 const &b) const {", + "#pragma HLS inline", + "return a>b? a-b : b-a;", + "}", + "};", + "template", + "struct sub {", + "TO operator()(TI1 const &a, TI2 const &b) const {", + "#pragma HLS inline", + "return a-b;", + "}", + "};", + "template", + "struct add {", + "TO operator()(TI1 const &a, TI2 const &b) const {", + "#pragma HLS inline", + "return a+b;", + "}", + "};", + ] + ) + + def defines(self, var): + self.code_gen_dict["$DEFINES$"] = [] + + def read_npy_data(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + idt0 = self.get_input_datatype(0) + idt1 = self.get_input_datatype(1) + elem_bits_0 = idt0.bitwidth() + elem_bits_1 = idt1.bitwidth() + packed_bits_0 = self.get_instream_width(0) + packed_hls_type_0 = "ap_uint<%d>" % packed_bits_0 + packed_bits_1 = self.get_instream_width(1) + packed_hls_type_1 = "ap_uint<%d>" % packed_bits_1 + elem_hls_type_0 = idt0.get_hls_datatype_str() + elem_hls_type_1 = idt1.get_hls_datatype_str() + npy_type = "float" + self.code_gen_dict["$READNPYDATA$"] = [] + npy_in = "%s/input_0.npy" % code_gen_dir + self.code_gen_dict["$READNPYDATA$"].append( + 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' + % ( + packed_hls_type_0, + elem_hls_type_0, + elem_bits_0, + npy_type, + npy_in, + self.hls_sname(), + ) + ) + npy_in = "%s/input_1.npy" % code_gen_dir + self.code_gen_dict["$READNPYDATA$"].append( + 'npy2apintstream<%s, %s, %d, %s>("%s", in1_%s);' + % ( + packed_hls_type_1, + elem_hls_type_1, + elem_bits_1, + npy_type, + npy_in, + self.hls_sname(), + ) + ) + + def strm_decl(self): + self.code_gen_dict["$STREAMDECLARATIONS$"] = [] + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> in0_{} ("in0_{}");'.format( + self.get_instream_width(0), self.hls_sname(), self.hls_sname() + ) + ) + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> in1_{} ("in1_{}");'.format( + self.get_instream_width(1), self.hls_sname(), self.hls_sname() + ) + ) + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> out_{} ("out_{}");'.format( + self.get_outstream_width(), self.hls_sname(), self.hls_sname() + ) + ) + + def docompute(self): + op = self.get_nodeattr("eltwiseOp") + idt0 = self.get_input_datatype(0) + idt1 = self.get_input_datatype(1) + odt = self.get_output_datatype() + elem_hls_type_0 = idt0.get_hls_datatype_str() + elem_hls_type_1 = idt1.get_hls_datatype_str() + out_hls_type = odt.get_hls_datatype_str() + slice_in0 = "Slice<%s>" % elem_hls_type_0 + slice_in1 = "Slice<%s>" % elem_hls_type_1 + slice_out = "Slice<%s>" % out_hls_type + eltwise_op_str = self.get_eltwise_op_lambda() + "%sEltwiseFunction<%s, %s, %s>()" % ( + op, + elem_hls_type_0, + elem_hls_type_1, + out_hls_type, + ) + self.code_gen_dict["$DOCOMPUTE$"] = [ + """{}<{}, {}, {}, {}, {}, {}>(in0_{}, in1_{}, out_{}, {});""".format( + "StreamingEltwise", + self.get_nodeattr("NumChannels"), + self.get_nodeattr("PE"), + int(np.prod(self.get_folded_output_shape()[:-2])), + slice_in0, + slice_in1, + slice_out, + self.hls_sname(), + self.hls_sname(), + self.hls_sname(), + eltwise_op_str, + ) + ] + + def dataoutstrm(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_output_datatype() + elem_bits = dtype.bitwidth() + packed_bits = self.get_outstream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "float" + npy_out = "%s/output.npy" % code_gen_dir + oshape = self.get_folded_output_shape() + oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") + + self.code_gen_dict["$DATAOUTSTREAM$"] = [ + 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + self.hls_sname(), + oshape_cpp_str, + npy_out, + ) + ] + + def save_as_npy(self): + self.code_gen_dict["$SAVEASCNPY$"] = [] + + def blackboxfunction(self): + self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ + """void {}(hls::stream> &in0_{}, hls::stream> &in1_{}, + hls::stream> &out_{})""".format( + self.onnx_node.name, + self.get_nodeattr("PE") * self.get_input_datatype(0).bitwidth(), + self.hls_sname(), + self.get_nodeattr("PE") * self.get_input_datatype(1).bitwidth(), + self.hls_sname(), + self.get_nodeattr("PE") * self.get_output_datatype().bitwidth(), + self.hls_sname(), + ) + ] + + def pragmas(self): + self.code_gen_dict["$PRAGMAS$"] = [ + "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() + ] + self.code_gen_dict["$PRAGMAS$"].append( + "#pragma HLS INTERFACE axis port=in1_" + self.hls_sname() + ) + self.code_gen_dict["$PRAGMAS$"].append( + "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() + ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") diff --git a/src/finn/custom_op/fpgadataflow/streamingeltwise.py b/src/finn/custom_op/fpgadataflow/streamingeltwise.py new file mode 100644 index 0000000000..4681c144f7 --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/streamingeltwise.py @@ -0,0 +1,216 @@ +# Copyright (c) 2022, Xilinx +# Copyright (C) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import numpy as np +import warnings +from qonnx.core.datatype import DataType + +from finn.custom_op.fpgadataflow.hwcustomop import HWCustomOp + + +class StreamingEltwise(HWCustomOp): + """Abstraction layer for HW implementation of StreamingEltwise""" + + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) + + def get_nodeattr_types(self): + my_attrs = super().get_nodeattr_types() + my_attrs.update( + { + "NumChannels": ("i", True, ""), + "PE": ("i", True, ""), + # FINN DataTypes for inputs; output datatype inferred from input + "inputDataType0": ("s", True, ""), + "inputDataType1": ("s", True, ""), + # type of EltwiseFunction for the operation + "eltwiseOp": ("s", True, "", ["Add", "Sub", "AbsDiff"]), + # number of input vectors, examples: + # [1] is a single vector (like a FC layer with batch=1) + # [4] is four vectors (like a FC layer with batch=4) + # [1, 4, 4] is four * four vectors (like a conv layer with batch=1) + "numInputVectors": ("ints", False, [1]), + "inFIFODepths": ("ints", False, [2, 2]), + } + ) + return my_attrs + + def get_eltwise_op_lambda(self): + eltwise_op = self.get_nodeattr("eltwiseOp") + idt0 = self.get_input_datatype(0) + idt1 = self.get_input_datatype(1) + odt = self.get_output_datatype() + tin0 = idt0.get_hls_datatype_str() + tin1 = idt1.get_hls_datatype_str() + tout = odt.get_hls_datatype_str() + eltwise_ops = { + # "Add": "[](auto a, auto b) { return a + b; }", + # "Sub": "[](auto a, auto b) { return a - b; }", + # "AbsDiff": "[](auto a, auto b) { return a>b? a-b : b-a; }", + "Add": f"add<{tin0}, {tin1}, {tout}>()", + "Sub": f"sub<{tin0}, {tin1}, {tout}>()", + "AbsDiff": f"absdiff<{tin0}, {tin1}, {tout}>()", + } + return eltwise_ops[eltwise_op] + + def get_normal_input_shape(self, ind=0): + ich = self.get_nodeattr("NumChannels") + vecs = list(self.get_nodeattr("numInputVectors")) + ishape = tuple(vecs + [ich]) + return ishape + + def get_folded_input_shape(self, ind=0): + ich = self.get_nodeattr("NumChannels") + pe = self.get_nodeattr("PE") + assert ich % pe == 0, "PE must divide NumChannels" + vecs = list(self.get_nodeattr("numInputVectors")) + ishape = tuple(vecs + [ich // pe, pe]) + return ishape + + def get_normal_output_shape(self, ind=0): + return self.get_normal_input_shape() + + def get_folded_output_shape(self, ind=0): + return self.get_folded_input_shape() + + def make_shape_compatible_op(self, model): + exp_ishape = self.get_normal_input_shape() + oshape = self.get_normal_output_shape() + ishape = tuple(model.get_tensor_shape(self.onnx_node.input[0])) + assert ishape == exp_ishape, "Unexpected input1 shape." + ishape = tuple(model.get_tensor_shape(self.onnx_node.input[1])) + assert ishape == exp_ishape, "Unexpected input2 shape." + return super().make_const_shape_op(oshape) + + def infer_node_datatype(self, model): + node = self.onnx_node + idt0 = model.get_tensor_datatype(node.input[0]) + if idt0 != self.get_input_datatype(0): + warn_str = "inputDataType0 changing for %s: %s -> %s " % ( + node.name, + str(self.get_input_datatype(0)), + str(idt0), + ) + warnings.warn(warn_str) + self.set_nodeattr("inputDataType0", idt0.name) + idt1 = model.get_tensor_datatype(node.input[1]) + if idt1 != self.get_input_datatype(1): + warn_str = "inputDataType1 changing for %s: %s -> %s " % ( + node.name, + str(self.get_input_datatype(1)), + str(idt1), + ) + warnings.warn(warn_str) + self.set_nodeattr("inputDataType1", idt1.name) + # enforce output data type (calculated based on idt) + odt = self.get_output_datatype() + model.set_tensor_datatype(self.onnx_node.output[0], odt) + + def verify_node(self): + pass + + def get_input_datatype(self, ind=0): + """Returns FINN DataType of input.""" + return DataType[self.get_nodeattr("inputDataType" + str(ind))] + + def get_output_datatype(self, ind=0): + """Returns FINN DataType of output.""" + op = self.get_nodeattr("eltwiseOp") + idt0 = self.get_input_datatype(0) + idt1 = self.get_input_datatype(1) + assert idt0.signed() == idt1.signed(), ( + "%s: Inputs must have same signedness" % self.onnx_node.name + ) + idt0_min, idt0_max = idt0.min(), idt0.max() + idt1_min, idt1_max = idt1.min(), idt1.max() + cands = [ + idt0_min - idt1_min, + idt0_min - idt1_max, + idt0_max - idt1_min, + idt0_max - idt1_max, + ] + largest_magnitude = max(map(abs, cands)) + if op == "Add": + if idt0.signed(): + return DataType.get_smallest_possible(idt0.min() + idt1.min()) + else: + return DataType.get_smallest_possible(idt0.max() + idt1.max()) + elif op == "Sub": + return DataType.get_smallest_possible(-largest_magnitude) + elif op == "AbsDiff": + return DataType.get_smallest_possible(largest_magnitude) + else: + raise Exception("%s: Unknown eltWiseOp = %s" % (self.onnx_node.name, op)) + + def get_instream_width(self, ind=0): + """Returns input stream width.""" + ibits = self.get_input_datatype(ind).bitwidth() + pe = self.get_nodeattr("PE") + in_width = pe * ibits + return in_width + + def get_outstream_width(self, ind=0): + """Returns output stream width.""" + obits = self.get_output_datatype().bitwidth() + pe = self.get_nodeattr("PE") + out_width = pe * obits + return out_width + + def get_number_output_values(self): + return np.prod(self.get_folded_output_shape()[:-1]) + + def get_exp_cycles(self): + # Channels/PE * batch size * fmdim * fmdim + return np.prod(self.get_folded_output_shape()[:-1]) + + def execute_node(self, context, graph): + # simulate behavior using Python + node = self.onnx_node + inp0_values = context[node.input[0]] + inp1_values = context[node.input[1]] + eltwiseOp = self.get_nodeattr("eltwiseOp") + oshape = context[node.output[0]].shape + ishape0 = inp0_values.shape + ishape1 = inp1_values.shape + assert ishape0 == ishape1, "Shapes of inputs should be the same for Streamingeltwise" + # subtraction + result = inp0_values - inp1_values + if eltwiseOp == "Sub": + context[node.output[0]] = np.asarray(result, dtype=np.float32).reshape(oshape) + elif eltwiseOp == "AbsDiff": + context[node.output[0]] = np.abs(np.asarray(result, dtype=np.float32)).reshape(oshape) + else: + raise Exception("%s: Unknown eltWiseOp = %s" % (node.name, eltwiseOp)) + + def get_verilog_top_module_intf_names(self): + intf_names = super().get_verilog_top_module_intf_names() + sname = self.hls_sname() + swidth = self.get_instream_width_padded() + intf_names["s_axis"] = [(x + "_" + sname, swidth) for x in ["in0", "in1"]] + return intf_names diff --git a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py index 1c2dfeca96..11bd3406d5 100644 --- a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py +++ b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py @@ -662,3 +662,98 @@ def apply(self, model): model = model.transform(InferShapes()) model = model.transform(InferDataTypes()) return (model, graph_modified) + + +class InferStreamingEltwise(Transformation): + """Convert eltwise Sub or Sub -> Abs to StreamingEltwise layer + with SubEltwise or AbsDiffEltwise op.""" + + def apply(self, model): + graph = model.graph + node_ind = 0 + graph_modified = False + for node in graph.node: + node_ind += 1 + if node.op_type == "Sub": + in0 = node.input[0] + in1 = node.input[1] + result = node.output[0] + in0_shape = model.get_tensor_shape(in0) + in1_shape = model.get_tensor_shape(in1) + in0_static = not (model.get_initializer(in0) is None) + in1_static = not (model.get_initializer(in1) is None) + + # skip if different shapes on inputs + if in0_shape != in1_shape: + continue + # skip if any of inputs have initializers + # (this node is meant for two dynamic streams) + if in0_static or in1_static: + continue + + idt0 = model.get_tensor_datatype(in0) + idt1 = model.get_tensor_datatype(in1) + + # skip conversion for layers with float input + if not (idt0.is_integer() and idt1.is_integer()): + continue + + eltwiseOp = "Sub" + nodes_to_remove = [node] + # look for a downstream Abs node + res_consumer = model.find_consumer(result) + if (res_consumer is not None) and (res_consumer.op_type == "Abs"): + eltwiseOp = "AbsDiff" + result = res_consumer.output[0] + nodes_to_remove.append(res_consumer) + + # check layout and convert if necessary + in0_layout = model.get_tensor_layout(in0) + in1_layout = model.get_tensor_layout(in1) + result_layout = model.get_tensor_layout(result) + + if in0_layout == DataLayout.NCHW: + in0 = nchw_to_nhwc(in0, model, node_ind) + node_ind += 1 + in0_shape = model.get_tensor_shape(in0) + + if in1_layout == DataLayout.NCHW: + in1 = nchw_to_nhwc(in1, model, node_ind) + node_ind += 1 + in1_shape = model.get_tensor_shape(in1) + + # keep track of where we need to insert the HW Op + # it has to be ahead of the output transform + insert_point = node_ind + + if result_layout == DataLayout.NCHW: + result = nchw_to_nhwc(result, model, node_ind, reverse=True) + node_ind += 1 + + # now safe to assume num_channels is size of last dimension + num_channels = int(in0_shape[-1]) + # create node with no parallelization first + pe = 1 + + # create and insert new Eltwise node + new_node = helper.make_node( + "StreamingEltwise", + [in0, in1], + [result], + domain="finn.custom_op.fpgadataflow", + backend="fpgadataflow", + NumChannels=num_channels, + PE=pe, + inputDataType0=idt0.name, + inputDataType1=idt1.name, + eltwiseOp=eltwiseOp, + numInputVectors=in0_shape[:-1], + name="StreamingEltwise_" + node.name, + ) + graph.node.insert(insert_point, new_node) + # remove old nodes + for nd in nodes_to_remove: + graph.node.remove(nd) + graph_modified = True + + return (model, graph_modified) diff --git a/tests/fpgadataflow/test_fpgadataflow_eltwise.py b/tests/fpgadataflow/test_fpgadataflow_eltwise.py index 6028a9b9f0..fbfcc8e28b 100644 --- a/tests/fpgadataflow/test_fpgadataflow_eltwise.py +++ b/tests/fpgadataflow/test_fpgadataflow_eltwise.py @@ -1,4 +1,5 @@ # Copyright (c) 2022, Xilinx +# Copyright (C) 2023, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -38,7 +39,7 @@ from qonnx.transformation.infer_shapes import InferShapes from qonnx.util.basic import gen_finn_dt_tensor -import finn.transformation.fpgadataflow.convert_to_hls_layers as to_hls +import finn.transformation.fpgadataflow.convert_to_hw_layers as to_hw from finn.analysis.fpgadataflow.exp_cycles_per_layer import exp_cycles_per_layer from finn.core.onnx_exec import execute_onnx from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim @@ -47,6 +48,7 @@ from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers def build_model(shp, dt0, dt1, do_abs): @@ -105,9 +107,17 @@ def test_fpgadataflow_eltwise(dt0, ch, fold, do_abs, exec_mode): in1 = gen_finn_dt_tensor(dt1, shp) idict = {"in0": in0, "in1": in1} y_expected = execute_onnx(model, idict)["out0"] - model = model.transform(to_hls.InferStreamingEltwise()) + model = model.transform(to_hw.InferStreamingEltwise()) assert len(model.graph.node) == 1 assert model.graph.node[0].op_type == "StreamingEltwise" + + y_produced = execute_onnx(model, idict)["out0"] + assert (y_produced == y_expected).all(), exec_mode + " failed" + + model = model.transform(SpecializeLayers()) + + assert len(model.graph.node) == 1 + assert model.graph.node[0].op_type == "StreamingEltwise_hls" getCustomOp(model.graph.node[0]).set_nodeattr("PE", pe) if exec_mode == "cppsim": model = model.transform(PrepareCppSim()) @@ -124,7 +134,7 @@ def test_fpgadataflow_eltwise(dt0, ch, fold, do_abs, exec_mode): y_produced = execute_onnx(model, idict)["out0"] assert (y_produced == y_expected).all(), exec_mode + " failed" if exec_mode == "rtlsim": - node = model.get_nodes_by_op_type("StreamingEltwise")[0] + node = model.get_nodes_by_op_type("StreamingEltwise_hls")[0] inst = getCustomOp(node) cycles_rtlsim = inst.get_nodeattr("cycles_rtlsim") exp_cycles_dict = model.analysis(exp_cycles_per_layer) From 1b82867313f3ecd16bff383c2f322c18cfda64bb Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 1 Dec 2023 16:38:58 +0000 Subject: [PATCH 353/665] [CustomOp] Cleanup after replacement of custom ops --- src/finn/custom_op/fpgadataflow/__init__.py | 18 - .../fpgadataflow/addstreams_batch.py | 392 ----------- .../fpgadataflow/channelwise_op_batch.py | 613 ------------------ .../fpgadataflow/duplicatestreams_batch.py | 429 ------------ src/finn/custom_op/fpgadataflow/eltwise.py | 484 -------------- .../custom_op/fpgadataflow/fmpadding_batch.py | 407 ------------ .../custom_op/fpgadataflow/fmpadding_rtl.py | 414 ------------ .../fpgadataflow/globalaccpool_batch.py | 352 ---------- .../fpgadataflow/labelselect_batch.py | 369 ----------- .../fpgadataflow/streamingmaxpool_batch.py | 441 ------------- 10 files changed, 3919 deletions(-) delete mode 100644 src/finn/custom_op/fpgadataflow/addstreams_batch.py delete mode 100644 src/finn/custom_op/fpgadataflow/channelwise_op_batch.py delete mode 100644 src/finn/custom_op/fpgadataflow/duplicatestreams_batch.py delete mode 100644 src/finn/custom_op/fpgadataflow/eltwise.py delete mode 100644 src/finn/custom_op/fpgadataflow/fmpadding_batch.py delete mode 100644 src/finn/custom_op/fpgadataflow/fmpadding_rtl.py delete mode 100644 src/finn/custom_op/fpgadataflow/globalaccpool_batch.py delete mode 100644 src/finn/custom_op/fpgadataflow/labelselect_batch.py delete mode 100755 src/finn/custom_op/fpgadataflow/streamingmaxpool_batch.py diff --git a/src/finn/custom_op/fpgadataflow/__init__.py b/src/finn/custom_op/fpgadataflow/__init__.py index 6fe7993643..249716ce29 100644 --- a/src/finn/custom_op/fpgadataflow/__init__.py +++ b/src/finn/custom_op/fpgadataflow/__init__.py @@ -28,9 +28,7 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from finn.custom_op.fpgadataflow.addstreams import AddStreams -from finn.custom_op.fpgadataflow.addstreams_batch import AddStreams_Batch from finn.custom_op.fpgadataflow.channelwise_op import ChannelwiseOp -from finn.custom_op.fpgadataflow.channelwise_op_batch import ChannelwiseOp_Batch from finn.custom_op.fpgadataflow.checksum import CheckSum from finn.custom_op.fpgadataflow.concat import StreamingConcat from finn.custom_op.fpgadataflow.convolutioninputgenerator import ( @@ -44,15 +42,10 @@ ) from finn.custom_op.fpgadataflow.downsampler import DownSampler from finn.custom_op.fpgadataflow.duplicatestreams import DuplicateStreams -from finn.custom_op.fpgadataflow.duplicatestreams_batch import DuplicateStreams_Batch from finn.custom_op.fpgadataflow.fmpadding import FMPadding -from finn.custom_op.fpgadataflow.fmpadding_batch import FMPadding_Batch -from finn.custom_op.fpgadataflow.fmpadding_rtl import FMPadding_rtl from finn.custom_op.fpgadataflow.globalaccpool import GlobalAccPool -from finn.custom_op.fpgadataflow.globalaccpool_batch import GlobalAccPool_Batch from finn.custom_op.fpgadataflow.iodma import IODMA from finn.custom_op.fpgadataflow.labelselect import LabelSelect -from finn.custom_op.fpgadataflow.labelselect_batch import LabelSelect_Batch from finn.custom_op.fpgadataflow.lookup import Lookup from finn.custom_op.fpgadataflow.matrixvectoractivation import MatrixVectorActivation from finn.custom_op.fpgadataflow.pool_batch import Pool_Batch @@ -68,11 +61,9 @@ from finn.custom_op.fpgadataflow.streamingeltwise import StreamingEltwise from finn.custom_op.fpgadataflow.streamingfifo import StreamingFIFO from finn.custom_op.fpgadataflow.streamingmaxpool import StreamingMaxPool -from finn.custom_op.fpgadataflow.streamingmaxpool_batch import StreamingMaxPool_Batch from finn.custom_op.fpgadataflow.thresholding_batch import Thresholding_Batch from finn.custom_op.fpgadataflow.tlastmarker import TLastMarker from finn.custom_op.fpgadataflow.upsampler import UpsampleNearestNeighbour -from finn.custom_op.fpgadataflow.upsampler_batch import UpsampleNearestNeighbour_Batch from finn.custom_op.fpgadataflow.vectorvectoractivation import VectorVectorActivation custom_op = dict() @@ -80,7 +71,6 @@ # make sure new HLSCustomOp subclasses are imported here so that they get # registered and plug in correctly into the infrastructure custom_op["DownSampler"] = DownSampler -custom_op["StreamingMaxPool_Batch"] = StreamingMaxPool_Batch custom_op["MatrixVectorActivation"] = MatrixVectorActivation custom_op["ConvolutionInputGenerator"] = ConvolutionInputGenerator custom_op["ConvolutionInputGenerator1D"] = ConvolutionInputGenerator1D @@ -89,22 +79,14 @@ custom_op["StreamingDataWidthConverter_Batch"] = StreamingDataWidthConverter_Batch custom_op["StreamingDataWidthConverter_rtl"] = StreamingDataWidthConverter_rtl custom_op["StreamingFIFO"] = StreamingFIFO -custom_op["GlobalAccPool_Batch"] = GlobalAccPool_Batch custom_op["Pool_Batch"] = Pool_Batch -custom_op["FMPadding_Batch"] = FMPadding_Batch custom_op["Thresholding_Batch"] = Thresholding_Batch -custom_op["AddStreams_Batch"] = AddStreams_Batch -custom_op["LabelSelect_Batch"] = LabelSelect_Batch -custom_op["DuplicateStreams_Batch"] = DuplicateStreams_Batch custom_op["VectorVectorActivation"] = VectorVectorActivation -custom_op["ChannelwiseOp_Batch"] = ChannelwiseOp_Batch custom_op["IODMA"] = IODMA custom_op["StreamingDataflowPartition"] = StreamingDataflowPartition -custom_op["UpsampleNearestNeighbour_Batch"] = UpsampleNearestNeighbour_Batch custom_op["Lookup"] = Lookup custom_op["StreamingConcat"] = StreamingConcat custom_op["CheckSum"] = CheckSum -custom_op["FMPadding_rtl"] = FMPadding_rtl custom_op["FMPadding"] = FMPadding custom_op["AddStreams"] = AddStreams diff --git a/src/finn/custom_op/fpgadataflow/addstreams_batch.py b/src/finn/custom_op/fpgadataflow/addstreams_batch.py deleted file mode 100644 index 51de1590ec..0000000000 --- a/src/finn/custom_op/fpgadataflow/addstreams_batch.py +++ /dev/null @@ -1,392 +0,0 @@ -# Copyright (c) 2020, Xilinx -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# * Redistributions of source code must retain the above copyright notice, this -# list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# * Neither the name of FINN nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -import numpy as np -import os -import warnings -from qonnx.core.datatype import DataType - -from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp -from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy - - -class AddStreams_Batch(HLSCustomOp): - """Class that corresponds to finn-hlslib AddStreams_Batch function.""" - - def __init__(self, onnx_node, **kwargs): - super().__init__(onnx_node, **kwargs) - - def get_nodeattr_types(self): - my_attrs = super().get_nodeattr_types() - my_attrs.update( - { - "NumChannels": ("i", True, ""), - "PE": ("i", True, ""), - # FINN DataTypes for inputs; output datatype inferred from input - "inputDataType": ("s", True, ""), - # number of input vectors, examples: - # [1] is a single vector (like a FC layer with batch=1) - # [4] is four vectors (like a FC layer with batch=4) - # [1, 4, 4] is four * four vectors (like a conv layer with batch=1) - "numInputVectors": ("ints", False, [1]), - "inFIFODepths": ("ints", False, [2, 2]), - } - ) - return my_attrs - - def get_normal_input_shape(self, ind=0): - ich = self.get_nodeattr("NumChannels") - vecs = list(self.get_nodeattr("numInputVectors")) - ishape = tuple(vecs + [ich]) - return ishape - - def get_folded_input_shape(self, ind=0): - ich = self.get_nodeattr("NumChannels") - pe = self.get_nodeattr("PE") - assert ich % pe == 0, "PE must divide NumChannels" - vecs = list(self.get_nodeattr("numInputVectors")) - ishape = tuple(vecs + [ich // pe, pe]) - return ishape - - def get_normal_output_shape(self, ind=0): - return self.get_normal_input_shape() - - def get_folded_output_shape(self, ind=0): - return self.get_folded_input_shape() - - def make_shape_compatible_op(self, model): - exp_ishape = self.get_normal_input_shape() - oshape = self.get_normal_output_shape() - ishape = tuple(model.get_tensor_shape(self.onnx_node.input[0])) - assert ishape == exp_ishape, "Unexpected input1 shape." - ishape = tuple(model.get_tensor_shape(self.onnx_node.input[1])) - assert ishape == exp_ishape, "Unexpected input2 shape." - return super().make_const_shape_op(oshape) - - def infer_node_datatype(self, model): - node = self.onnx_node - idt = model.get_tensor_datatype(node.input[0]) - if idt != self.get_input_datatype(): - warn_str = "inputDataType changing for %s: %s -> %s " % ( - node.name, - str(self.get_input_datatype()), - str(idt), - ) - warnings.warn(warn_str) - self.set_nodeattr("inputDataType", idt.name) - # enforce output data type (calculated based on idt) - odt = self.get_output_datatype() - model.set_tensor_datatype(self.onnx_node.output[0], odt) - - def verify_node(self): - info_messages = [] - # verify that "backend" is set to "fpgadataflow" - backend_value = self.get_nodeattr("backend") - if backend_value == "fpgadataflow": - info_messages.append("Attribute backend is set correctly") - else: - info_messages.append('Attribute backend should be set to "fpgadataflow"') - - # verify that all necessary attributes exist - try: - self.get_nodeattr("code_gen_dir_cppsim") - self.get_nodeattr("executable_path") - self.get_nodeattr("NumChannels") - self.get_nodeattr("PE") - self.get_nodeattr("inputDataType") - info_messages.append("All necessary attributes exist") - except Exception: - info_messages.append("""The required LabelSelect_Batch attributes do not exist.""") - - return info_messages - - def get_input_datatype(self, ind=0): - """Returns FINN DataType of input.""" - return DataType[self.get_nodeattr("inputDataType")] - - def get_output_datatype(self, ind=0): - """Returns FINN DataType of output.""" - # we need to set output datatype to the next larger int or uint - # enhancement: consider specifying w/ explicit outputDataType attribute - # to allow overflow and use the same idt if user wants - idt = DataType[self.get_nodeattr("inputDataType")] - if idt.signed(): - return DataType.get_smallest_possible(2 * idt.min()) - else: - return DataType.get_smallest_possible(2 * idt.max()) - - def get_instream_width(self, ind=0): - """Returns input stream width.""" - ibits = self.get_input_datatype().bitwidth() - pe = self.get_nodeattr("PE") - in_width = pe * ibits - return in_width - - def get_outstream_width(self, ind=0): - """Returns output stream width.""" - obits = self.get_output_datatype().bitwidth() - pe = self.get_nodeattr("PE") - out_width = pe * obits - return out_width - - def get_number_output_values(self): - return np.prod(self.get_folded_output_shape()[:-1]) - - def get_exp_cycles(self): - # Channels/PE * batch size * fmdim * fmdim - return np.prod(self.get_folded_output_shape()[:-1]) - - def execute_node(self, context, graph): - mode = self.get_nodeattr("exec_mode") - node = self.onnx_node - exp_ishape = self.get_normal_input_shape() - exp_oshape = self.get_normal_output_shape() - folded_ishape = self.get_folded_input_shape() - - if mode == "cppsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - elif mode == "rtlsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) - - inp = context[node.input[0]] - assert str(inp.dtype) == "float32", "Input datatype is not float32" - assert inp.shape == exp_ishape, """Input0 shape doesn't match expected shape .""" - export_idt = self.get_input_datatype() - # reshape input into folded form - inp = inp.reshape(folded_ishape) - # make copy before saving array - reshaped_input = inp.copy() - np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input) - - # exact same thing for input1 - inp = context[node.input[1]] - assert str(inp.dtype) == "float32", "Input datatype is not float32" - assert inp.shape == exp_ishape, """Input1 shape doesn't match expected shape .""" - export_idt = self.get_input_datatype() - # reshape input into folded form - inp = inp.reshape(folded_ishape) - # make copy before saving array - reshaped_input = inp.copy() - np.save(os.path.join(code_gen_dir, "input_1.npy"), reshaped_input) - - if mode == "cppsim": - # execute the precompiled model - super().exec_precompiled_singlenode_model() - # load output npy file - super().npy_to_dynamic_output(context) - assert ( - context[node.output[0]].shape == exp_oshape - ), "cppsim did not produce expected output shape" - elif mode == "rtlsim": - sim = self.get_rtlsim() - nbits = self.get_instream_width() - rtlsim_inp0 = npy_to_rtlsim_input( - "{}/input_0.npy".format(code_gen_dir), export_idt, nbits - ) - rtlsim_inp1 = npy_to_rtlsim_input( - "{}/input_1.npy".format(code_gen_dir), export_idt, nbits - ) - super().reset_rtlsim(sim) - super().toggle_clk(sim) - rtlsim_output = self.rtlsim(sim, rtlsim_inp0, rtlsim_inp1) - odt = self.get_output_datatype() - target_bits = odt.bitwidth() - packed_bits = self.get_outstream_width() - out_npy_path = "{}/output.npy".format(code_gen_dir) - out_shape = self.get_folded_output_shape() - rtlsim_output_to_npy( - rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits - ) - # load and reshape output - output = np.load(out_npy_path) - output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) - context[node.output[0]] = output - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) - - assert ( - context[node.output[0]].shape == exp_oshape - ), """Output shape doesn't match expected shape.""" - - def global_includes(self): - self.code_gen_dict["$GLOBALS$"] = ['#include "streamtools.h"'] - - def defines(self, var): - self.code_gen_dict["$DEFINES$"] = [] - - def read_npy_data(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_input_datatype() - elem_bits = dtype.bitwidth() - packed_bits = self.get_instream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - self.code_gen_dict["$READNPYDATA$"] = [] - npy_in = "%s/input_0.npy" % code_gen_dir - self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - npy_in, - self.hls_sname(), - ) - ) - npy_in = "%s/input_1.npy" % code_gen_dir - self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in1_%s);' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - npy_in, - self.hls_sname(), - ) - ) - - def strm_decl(self): - self.code_gen_dict["$STREAMDECLARATIONS$"] = [] - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0_{} ("in0_{}");'.format( - self.get_instream_width(), self.hls_sname(), self.hls_sname() - ) - ) - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in1_{} ("in1_{}");'.format( - self.get_instream_width(), self.hls_sname(), self.hls_sname() - ) - ) - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out_{} ("out_{}");'.format( - self.get_outstream_width(), self.hls_sname(), self.hls_sname() - ) - ) - - def docompute(self): - node = self.onnx_node - self.code_gen_dict["$DOCOMPUTE$"] = [ - """{}<{}, {}, {}, {}, {}> (in0_{}, in1_{}, out_{}, 1);""".format( - node.op_type, - self.get_nodeattr("PE"), - self.get_input_datatype().get_hls_datatype_str(), - self.get_input_datatype().get_hls_datatype_str(), - self.get_output_datatype().get_hls_datatype_str(), - self.get_number_output_values(), - self.hls_sname(), - self.hls_sname(), - self.hls_sname(), - ) - ] - - def dataoutstrm(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_output_datatype() - elem_bits = dtype.bitwidth() - packed_bits = self.get_outstream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_out = "%s/output.npy" % code_gen_dir - oshape = self.get_folded_output_shape() - oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") - - self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - self.hls_sname(), - oshape_cpp_str, - npy_out, - ) - ] - - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - - def blackboxfunction(self): - self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - """void {}(hls::stream> &in0_{}, hls::stream> &in1_{}, - hls::stream> &out_{})""".format( - self.onnx_node.name, - self.get_nodeattr("PE") * self.get_input_datatype().bitwidth(), - self.hls_sname(), - self.get_nodeattr("PE") * self.get_input_datatype().bitwidth(), - self.hls_sname(), - self.get_nodeattr("PE") * self.get_output_datatype().bitwidth(), - self.hls_sname(), - ) - ] - - def pragmas(self): - self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() - ] - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=in1_" + self.hls_sname() - ) - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() - ) - self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") - - def get_verilog_top_module_intf_names(self): - intf_names = super().get_verilog_top_module_intf_names() - sname = self.hls_sname() - swidth = self.get_instream_width_padded() - intf_names["s_axis"] = [(x + "_" + sname, swidth) for x in ["in0", "in1"]] - return intf_names - - def derive_characteristic_fxns(self, period): - n_inps = np.prod(self.get_folded_input_shape()[:-1]) - io_dict = { - "inputs": { - "in0": [0 for i in range(n_inps)], - "in1": [0 for i in range(n_inps)], - }, - "outputs": {"out": []}, - } - super().derive_characteristic_fxns(period, override_rtlsim_dict=io_dict) diff --git a/src/finn/custom_op/fpgadataflow/channelwise_op_batch.py b/src/finn/custom_op/fpgadataflow/channelwise_op_batch.py deleted file mode 100644 index 5e0063ac33..0000000000 --- a/src/finn/custom_op/fpgadataflow/channelwise_op_batch.py +++ /dev/null @@ -1,613 +0,0 @@ -# Copyright (c) 2020, Xilinx -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# * Redistributions of source code must retain the above copyright notice, this -# list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# * Neither the name of FINN nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -import numpy as np -import os -import warnings -from math import ceil -from qonnx.core.datatype import DataType - -from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp -from finn.util.data_packing import ( - npy_to_rtlsim_input, - numpy_to_hls_code, - rtlsim_output_to_npy, -) - -# ONNX i/o tensor shape assumptions for channelwise ops: -# input 0 is the input tensor, shape (..., NumChannels) -# input 1 is the channelwise parameter tensor, shape (NumChannels, params_per_channel) -# output 0 is the output tensor, shape (..., NumChannels) - same as input -# the ... here can be any shape (representing groups of vectors) - - -def get_smallest_possible(vals): - """Returns smallest (fewest bits) possible DataType that can represent - value. Prefers unsigned integers where possible.""" - vals = np.array(vals, dtype=np.float64) - for v in vals: - assert int(v) == v, "Error float value" - - for k in DataType.get_accumulator_dt_cands(): - dt = DataType[k] - - if dt in [DataType["BIPOLAR"], DataType["TERNARY"], DataType["FLOAT32"]]: - # not currently supported - continue - - if (dt.min() <= vals).all() and (vals <= dt.max()).all(): - return dt - - warnings.warn( - """InferChannelwiseLinearLayer: Output values may not be - representable with supported data types. - Setting maximum width data type available. - This will lead to errors if there are no constrains on the input - """ - ) - - if (0 <= vals).all(): - return DataType["UINT64"] - else: - return DataType["INT64"] - - -class ChannelwiseOp_Batch(HLSCustomOp): - """Class that corresponds to finn-hls Thresholding_Batch function. - It can implement a variety of channel-wise parametrized operations, - including Add, Mul and multi-thresholding. - """ - - def __init__(self, onnx_node, **kwargs): - super().__init__(onnx_node, **kwargs) - - def get_nodeattr_types(self): - my_attrs = { - # channelwise "map" function to apply: - # one of cmp_le, cmp_ge, add, mul - "Func": ("s", False, "cmp_le", {"cmp_le", "cmp_ge", "add", "mul"}), - "PE": ("i", True, 0), - "NumChannels": ("i", True, 0), - # string defining memory resource type for parameters - "ram_style": ("s", False, "distributed", {"distributed", "block"}), - # FINN DataTypes for inputs, weights, outputs - "inputDataType": ("s", True, ""), - "paramDataType": ("s", True, ""), - "outputDataType": ("s", True, ""), - # number of input vectors, examples: - # [1] is a single vector (like a FC layer with batch=1) - # [4] is four vectors (like a FC layer with batch=4) - # [1, 4, 4] is four * four vectors (like a conv layer with batch=1) - "numInputVectors": ("ints", False, [1]), - } - my_attrs.update(super().get_nodeattr_types()) - return my_attrs - - def calc_tmem(self): - """Calculates and returns TMEM, the depth of the memory used - to store the channelwise op parameters.""" - chn = self.get_nodeattr("NumChannels") - pe = self.get_nodeattr("PE") - return chn // pe - - def make_shape_compatible_op(self, model): - oshape = self.get_normal_output_shape() - # implement tensor with correct shape - return super().make_const_shape_op(oshape) - - def infer_node_datatype(self, model): - node = self.onnx_node - # check input datatype against property - idt = model.get_tensor_datatype(node.input[0]) - - exp_idt_name = self.get_nodeattr("inputDataType") - if exp_idt_name != idt.name: - func = self.get_nodeattr("Func") - assert func in ["add", "mul"], "Bad input DataType for ChannelwiseOp layer" - - self.set_nodeattr("inputDataType", idt.name) - # update the func in ['add','mul'] cases - - # get parameter ranges - param = model.get_initializer(node.input[1]) - param_min = min(param.flatten()) - param_max = max(param.flatten()) - - # set function and determine output data type - if func == "add": - out_min = idt.min() + param_min - out_max = idt.max() + param_max - odt = get_smallest_possible([out_min, out_max]) - elif func == "mul": - possible_limits = [] - possible_limits += [idt.min() * param_min] - possible_limits += [idt.min() * param_max] - possible_limits += [idt.max() * param_min] - possible_limits += [idt.max() * param_max] - odt = get_smallest_possible(possible_limits) - - self.set_nodeattr("outputDataType", odt.name) - - # set output datatype from property - odt = self.get_output_datatype() - model.set_tensor_datatype(node.output[0], odt) - - def verify_node(self): - info_messages = [] - # verify that "backend" is set to "fpgadataflow" - backend_value = self.get_nodeattr("backend") - if backend_value == "fpgadataflow": - info_messages.append("Attribute backend is set correctly") - else: - info_messages.append('Attribute backend should be set to "fpgadataflow"') - - # verify that all necessary attributes exist - # TODO collect automatically from get_nodeattr_types - try: - self.get_nodeattr("code_gen_dir_cppsim") - self.get_nodeattr("executable_path") - self.get_nodeattr("NumChannels") - self.get_nodeattr("PE") - self.get_nodeattr("inputDataType") - self.get_nodeattr("paramDataType") - self.get_nodeattr("outputDataType") - info_messages.append("All necessary attributes exist") - except Exception: - info_messages.append("""The required Threshold_Batch attributes do not exist.""") - - return info_messages - - def bram_estimation(self): - """Calculates BRAM cost if resource set to BRAM""" - style = self.get_nodeattr("ram_style") - P = self.get_nodeattr("PE") - idt = self.get_input_datatype() - A = idt.bitwidth() - tmem = self.calc_tmem() - - if style == "block" and tmem > 1: - return int(ceil(A * P / 16)) * int(ceil(tmem / 1024)) - else: - return 0 - - def lut_estimation(self): - """Calculates LUT cost, taking memory resource type into account""" - # TODO add in/out FIFO contributions - style = self.get_nodeattr("ram_style") - P = self.get_nodeattr("PE") - idt = self.get_input_datatype() - A = idt.bitwidth() - tmem = self.calc_tmem() - # cost of comparators - comparator_cost = A * P - # cost of LUTRAM - if style == "distributed" and tmem > 1: - lutram_cost = P * A * int(ceil(tmem / 64)) - else: - lutram_cost = 0 - # total cost - return comparator_cost + lutram_cost - - def get_input_datatype(self, ind=0): - """Returns FINN DataType of input.""" - return DataType[self.get_nodeattr("inputDataType")] - - def get_output_datatype(self, ind=0): - """Returns FINN DataType of output.""" - return DataType[self.get_nodeattr("outputDataType")] - - def get_instream_width(self, ind=0): - i_bits = self.get_input_datatype().bitwidth() - return i_bits * self.get_nodeattr("PE") - - def get_outstream_width(self, ind=0): - o_bits = self.get_output_datatype().bitwidth() - return o_bits * self.get_nodeattr("PE") - - def get_folded_input_shape(self, ind=0): - ich = self.get_nodeattr("NumChannels") - pe = self.get_nodeattr("PE") - fold = ich // pe - vecs = list(self.get_nodeattr("numInputVectors")) - folded_input_shape = tuple(vecs + [fold, pe]) - return folded_input_shape - - def get_folded_output_shape(self, ind=0): - # same shape as input - return self.get_folded_input_shape() - - def get_normal_input_shape(self, ind=0): - ich = self.get_nodeattr("NumChannels") - vecs = list(self.get_nodeattr("numInputVectors")) - normal_input_shape = tuple(vecs + [ich]) - return normal_input_shape - - def get_normal_output_shape(self, ind=0): - # same shape as input - return self.get_normal_input_shape() - - def get_number_output_values(self): - nf = np.prod(self.get_folded_output_shape()[:-1]) - return nf - - def get_exp_cycles(self): - # Channels/PE * batch size * fmdim * fmdim - return np.prod(self.get_folded_output_shape()[:-1]) - - def get_template_param_values(self): - """Returns the template parameter values according to input, output and weight - data types.""" - ret = dict() - inp_hls_str = self.get_input_datatype().get_hls_datatype_str() - out_hls_str = self.get_output_datatype().get_hls_datatype_str() - # fill in TSrcI - ret["TSrcI"] = "Slice<%s>" % inp_hls_str - # fill in TDstI - ret["TDstI"] = "Slice<%s>" % out_hls_str - - return ret - - def get_hls_compatible_parameter_tensor(self, orig_param_vector): - """Convert the original numpy weight matrix orig_weight_matrix into - a form suitable for passing to the hlslib call: - * ensure chn % PE == 0 - * interleave rows between PEs - * reshape into (PE, TMEM) and return - """ - chn = self.get_nodeattr("NumChannels") - pe = self.get_nodeattr("PE") - tmem = chn // pe - assert chn % pe == 0, "Requirement NumChannels divisable by PE is violated." - assert ( - orig_param_vector.ndim == 1 - ), """Parameter vector dimension is {}. - Expected dimension: 1.""".format( - orig_param_vector.ndim - ) - - # if not self.get_input_datatype().signed(): - # # ensure all thresholds are nonnegative - # assert (orig_param_vector >= 0).all() - - # ensure all thresholds are integer - assert (orig_param_vector.astype(np.int32) == orig_param_vector).all() - ret = orig_param_vector - - assert ret.shape[0] == chn, "Cardinality of parameter vector is not as expected (chn)" - - # distribute rows between PEs - ret = ret.reshape(tmem, pe).transpose() - assert ( - ret.shape[0] == pe - ), """First dimension after distribution of the - rows between PEs is not as expected (pe)""" - assert ( - ret.shape[1] == tmem - ), """Second dimension after distribution of the - rows between PEs is not as expected (tmem)""" - - return ret.reshape(1, pe, tmem) - - def generate_params(self, model, path): - code_gen_dir = path - # save thresholds in params.h - parameters = model.get_initializer(self.onnx_node.input[1]) - parameter_tensor = self.get_hls_compatible_parameter_tensor(parameters) - pdt = DataType[self.get_nodeattr("paramDataType")] - - parameters_hls_code = numpy_to_hls_code(parameter_tensor, pdt, "parameters", False, True) - # get input data type - export_idt = self.get_input_datatype() - if self.get_input_datatype() == DataType["BIPOLAR"]: - export_idt = DataType["BINARY"] - idt_hls = export_idt.get_hls_datatype_str() - - # write parameters into params.h - f_params = open("{}/params.h".format(code_gen_dir), "w") - pdt_hls = pdt.get_hls_datatype_str() - # use binary to export bipolar activations - export_odt = self.get_output_datatype() - if self.get_output_datatype() == DataType["BIPOLAR"]: - export_odt = DataType["BINARY"] - odt_hls = export_odt.get_hls_datatype_str() - # get desired function - func = self.get_nodeattr("Func") - if func == "cmp_le": - func_str = "comp::less_equal<%s, %s>" % (idt_hls, pdt_hls) - elif func == "cmp_ge": - func_str = "comp::greater_equal<%s, %s>" % (idt_hls, pdt_hls) - elif func == "add": - func_str = "comp::add<%s, %s, %s>" % (odt_hls, odt_hls, odt_hls) - elif func == "mul": - func_str = "comp::mul<%s, %s, %s>" % (odt_hls, odt_hls, odt_hls) - else: - raise Exception( - """Invalid value for attribute Func! Is currently set to: {} - has to be set to one of the following value - ("cmp_le", "cmp_ge", "add", "mul")""".format( - func - ) - ) - f_params.write( - "static ChannelWiseOperation<{},{},{},{},{},{}> threshs \ - = ".format( - self.calc_tmem(), - self.get_nodeattr("PE"), - idt_hls, - pdt_hls, - odt_hls, - func_str, - ) - ) - f_params.write(parameters_hls_code) - f_params.close() - - def execute_node(self, context, graph): - mode = self.get_nodeattr("exec_mode") - node = self.onnx_node - - # TODO ensure codegen dir exists - if mode == "cppsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - elif mode == "rtlsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) - - # create a npy file fore each input of the node (in_ind is input index) - in_ind = 0 - for inputs in node.input: - # it is assumed that the first input of the node is the data input - # the second input are the weights - # the third input are the thresholds - if in_ind == 0: - assert ( - str(context[inputs].dtype) == "float32" - ), """Input datatype is - not float32 as expected.""" - expected_inp_shape = self.get_folded_input_shape() - reshaped_input = context[inputs].reshape(expected_inp_shape) - export_idt = self.get_input_datatype() - # make copy before saving the array - reshaped_input = reshaped_input.copy() - np.save( - os.path.join(code_gen_dir, "input_{}.npy".format(in_ind)), - reshaped_input, - ) - elif in_ind > 2: - raise Exception("Unexpected input found for ChannelwiseOp_Batch") - in_ind += 1 - - if mode == "cppsim": - # execute the precompiled model - super().exec_precompiled_singlenode_model() - # load output npy file - super().npy_to_dynamic_output(context) - # reinterpret binary output as bipolar where needed - if self.get_output_datatype() == DataType["BIPOLAR"]: - out = context[node.output[0]] - out = 2 * out - 1 - context[node.output[0]] = out - assert ( - context[node.output[0]].shape == self.get_normal_output_shape() - ), """Output shape is not as expected""" - elif mode == "rtlsim": - sim = self.get_rtlsim() - nbits = self.get_instream_width() - inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) - super().reset_rtlsim(sim) - super().toggle_clk(sim) - output = self.rtlsim(sim, inp) - odt = self.get_output_datatype() - target_bits = odt.bitwidth() - packed_bits = self.get_outstream_width() - out_npy_path = "{}/output.npy".format(code_gen_dir) - out_shape = self.get_folded_output_shape() - rtlsim_output_to_npy(output, out_npy_path, odt, out_shape, packed_bits, target_bits) - - # load and reshape output - output = np.load(out_npy_path) - oshape = self.get_normal_output_shape() - output = np.asarray([output], dtype=np.float32).reshape(*oshape) - context[node.output[0]] = output - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) - - def global_includes(self): - self.code_gen_dict["$GLOBALS$"] = ['#include "activations.hpp"'] - self.code_gen_dict["$GLOBALS$"] += ['#include "params.h"'] - - # TODO check and add whatever missing - def defines(self, var): - numInputVectors = list(self.get_nodeattr("numInputVectors")) - numReps = numInputVectors[0] - self.code_gen_dict["$DEFINES$"] = [ - """#define NumChannels1 {}\n#define PE1 {}\n#define numReps {}""".format( - self.get_nodeattr("NumChannels"), - self.get_nodeattr("PE"), - numReps, - ) - ] - - def read_npy_data(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_input_datatype() - elem_bits = dtype.bitwidth() - packed_bits = self.get_instream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_in = "%s/input_0.npy" % code_gen_dir - self.code_gen_dict["$READNPYDATA$"] = [] - # note: the innermost dim is reversed for the input - self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s, false);' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - npy_in, - self.hls_sname(), - ) - ) - - def strm_decl(self): - self.code_gen_dict["$STREAMDECLARATIONS$"] = [] - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0_{} ("in0_{}");'.format( - self.get_instream_width(), self.hls_sname(), self.hls_sname() - ) - ) - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out_{} ("out_{}");'.format( - self.get_outstream_width(), self.hls_sname(), self.hls_sname() - ) - ) - - def docompute(self): - tmpl_args = self.get_template_param_values() - # TODO: why put some template parameters into defines and not others? - # should ImgDim be defined or just filled in here like we do now? - ishape = self.get_folded_input_shape() - if len(ishape) == 3: - spatial_dim = 1 - elif len(ishape) == 5: - spatial_dim = ishape[1] * ishape[2] - else: - raise Exception("""Unexpeted input shape""") - self.code_gen_dict["$DOCOMPUTE$"] = [ - """Thresholding_Batch<{}, NumChannels1, PE1, {}, {}> - (in0_{}, out_{}, threshs, numReps);""".format( - spatial_dim, - tmpl_args["TSrcI"], - tmpl_args["TDstI"], - self.hls_sname(), - self.hls_sname(), - ) - ] - - def dataoutstrm(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_output_datatype() - if dtype == DataType["BIPOLAR"]: - # use binary for bipolar storage - dtype = DataType["BINARY"] - elem_bits = dtype.bitwidth() - packed_bits = self.get_outstream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_out = "%s/output.npy" % code_gen_dir - shape = self.get_folded_output_shape() - shape_cpp_str = str(shape).replace("(", "{").replace(")", "}") - - # note: the innermost dim is not reversed for the output - self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s", false);' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - self.hls_sname(), - shape_cpp_str, - npy_out, - ) - ] - - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - - def blackboxfunction(self): - self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - """void {}(hls::stream> &in0_{}, - hls::stream> &out_{} - )""".format( - self.onnx_node.name, - self.get_instream_width(), - self.hls_sname(), - self.get_outstream_width(), - self.hls_sname(), - ) - ] - - def pragmas(self): - self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() - ] - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() - ) - self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") - - # the channelwise parameter tensor is acc_type [PE][TMEM][N_PARAMS_PER_CHANNEL] - # partition for parallel access along PE and N_PARAMS_PER_CHANNEL - # dimensions (dims 1 and 3) - self.code_gen_dict["$PRAGMAS$"].append( - ("#pragma HLS ARRAY_PARTITION variable=threshs.parameters " "complete dim=1") - ) - # self.code_gen_dict["$PRAGMAS$"].append( - # ( - # "#pragma HLS ARRAY_PARTITION variable=threshs.parameters " - # "complete dim=3" - # ) - # ) - - # set resource type - ram_style = self.get_nodeattr("ram_style") - pe = self.get_nodeattr("PE") - ich = self.get_nodeattr("NumChannels") - # if PE less than NumChannels, assign cores according to ram_style; - # otherwise if PE == NumChannels, Vivado HLS will unroll to FFs - if pe < ich: - if ram_style == "distributed": - self.code_gen_dict["$PRAGMAS$"].append( - ("#pragma HLS RESOURCE variable=threshs.parameters " "core=ROM_2P_LUTRAM") - ) - elif ram_style == "block": - self.code_gen_dict["$PRAGMAS$"].append( - ("#pragma HLS RESOURCE variable=threshs.parameters " "core=ROM_2P_BRAM") - ) - else: - raise Exception( - """Invalid value for attribute ram_style! Is currently set to: {} - has to be set to one of ("block", "distributed")""".format( - ram_style - ) - ) diff --git a/src/finn/custom_op/fpgadataflow/duplicatestreams_batch.py b/src/finn/custom_op/fpgadataflow/duplicatestreams_batch.py deleted file mode 100644 index 1f2d1b79be..0000000000 --- a/src/finn/custom_op/fpgadataflow/duplicatestreams_batch.py +++ /dev/null @@ -1,429 +0,0 @@ -# Copyright (c) 2020, Xilinx -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# * Redistributions of source code must retain the above copyright notice, this -# list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# * Neither the name of FINN nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -import numpy as np -import os -import warnings -from qonnx.core.datatype import DataType - -from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp -from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy - - -class DuplicateStreams_Batch(HLSCustomOp): - """Class that corresponds to finn-hlslib function of the same name.""" - - def __init__(self, onnx_node, **kwargs): - super().__init__(onnx_node, **kwargs) - - def get_nodeattr_types(self): - my_attrs = { - "NumChannels": ("i", True, 0), - "PE": ("i", True, 0), - # how many duplicated output streams to create - "NumOutputStreams": ("i", True, 0), - # FINN DataTypes for input - "inputDataType": ("s", True, ""), - # number of input vectors, examples: - # [1] is a single vector (like a FC layer with batch=1) - # [4] is four vectors (like a FC layer with batch=4) - # [1, 4, 4] is four * four vectors (like a conv layer with batch=1) - "numInputVectors": ("ints", False, [1]), - } - my_attrs.update(super().get_nodeattr_types()) - return my_attrs - - def get_num_output_streams(self): - return self.get_nodeattr("NumOutputStreams") - - def get_normal_input_shape(self, ind=0): - ch = self.get_nodeattr("NumChannels") - vecs = list(self.get_nodeattr("numInputVectors")) - ishape = tuple(vecs + [ch]) - return ishape - - def get_folded_input_shape(self, ind=0): - ch = self.get_nodeattr("NumChannels") - pe = self.get_nodeattr("PE") - vecs = list(self.get_nodeattr("numInputVectors")) - assert ch % pe == 0, "PE must divide NumChannels" - folds = int(ch / pe) - folded_ishape = tuple(vecs + [folds, pe]) - return folded_ishape - - def get_normal_output_shape(self, ind=0): - # since the output shape of both out streams are the same - # return independently from index - return self.get_normal_input_shape() - - def get_folded_output_shape(self, ind=0): - # since the output shape of both out streams are the same - # return independently from index - return self.get_folded_input_shape() - - def make_shape_compatible_op(self, model): - exp_ishape = self.get_normal_input_shape() - ishape = tuple(model.get_tensor_shape(self.onnx_node.input[0])) - assert ishape == exp_ishape, "Unexpected input shape." - num_out = self.get_num_output_streams() - assert len(self.onnx_node.output) == num_out, "Unexpected number of outputs" - - oshape = self.get_normal_output_shape() - ret = super().make_const_shape_op(oshape) - ret.output[:] = self.onnx_node.output - return ret - - def infer_node_datatype(self, model): - node = self.onnx_node - idt = model.get_tensor_datatype(node.input[0]) - if idt != self.get_input_datatype(): - warn_str = "inputDataType changing for %s: %s -> %s " % ( - node.name, - str(self.get_input_datatype()), - str(idt), - ) - warnings.warn(warn_str) - self.set_nodeattr("inputDataType", idt.name) - odt = self.get_output_datatype() - for my_out in self.onnx_node.output: - model.set_tensor_datatype(my_out, odt) - - def verify_node(self): - info_messages = [] - # verify that "backend" is set to "fpgadataflow" - backend_value = self.get_nodeattr("backend") - if backend_value == "fpgadataflow": - info_messages.append("Attribute backend is set correctly") - else: - info_messages.append('Attribute backend should be set to "fpgadataflow"') - - # verify that all necessary attributes exist - try: - self.get_nodeattr("code_gen_dir_cppsim") - self.get_nodeattr("executable_path") - self.get_nodeattr("NumChannels") - self.get_nodeattr("PE") - self.get_nodeattr("NumOutputStreams") - self.get_nodeattr("inputDataType") - info_messages.append("All necessary attributes exist") - except Exception: - info_messages.append("""The required GlobalAccPool_Batch attributes do not exist.""") - - return info_messages - - def get_input_datatype(self, ind=0): - """Returns FINN DataType of input.""" - return DataType[self.get_nodeattr("inputDataType")] - - def get_output_datatype(self, ind=0): - """Returns FINN DataType of output.""" - return DataType[self.get_nodeattr("inputDataType")] - - def get_instream_width(self, ind=0): - """Returns input stream width.""" - ibits = self.get_input_datatype().bitwidth() - pe = self.get_nodeattr("PE") - in_width = pe * ibits - return in_width - - def get_outstream_width(self, ind=0): - """Returns output stream width.""" - obits = self.get_output_datatype().bitwidth() - pe = self.get_nodeattr("PE") - out_width = pe * obits - return out_width - - def get_number_output_values(self): - return self.get_num_output_streams() * np.prod(self.get_folded_output_shape()[1:-1]) - - def get_exp_cycles(self): - # Channels/PE * batch size * fmdim * fmdim - return np.prod(self.get_folded_output_shape()[:-1]) - - def generate_params(self, model, path): - n_outputs = self.get_num_output_streams() - inp_streams = [] - commands = [] - o_stream_w = self.get_outstream_width() - i_stream_w = self.get_instream_width() - in_stream = "hls::stream > &in0" % (i_stream_w) - inp_streams.append(in_stream) - commands.append("ap_uint<%d> e = in0.read();" % i_stream_w) - iters = self.get_number_output_values() // self.get_num_output_streams() - for i in range(n_outputs): - out_stream = "hls::stream > &out%d" % (o_stream_w, i) - inp_streams.append(out_stream) - cmd = "out%d.write(e);" % i - commands.append(cmd) - - impl_hls_code = [] - impl_hls_code.append("void DuplicateStreamsCustom(") - impl_hls_code.append(",".join(inp_streams)) - impl_hls_code.append(") {") - impl_hls_code.append("for(unsigned int i = 0; i < %d; i++) {" % iters) - impl_hls_code.append("#pragma HLS PIPELINE II=1") - impl_hls_code.append("\n".join(commands)) - impl_hls_code.append("}") - impl_hls_code.append("}") - impl_hls_code = "\n".join(impl_hls_code) - - impl_filename = "{}/duplicate_impl.hpp".format(path) - f_impl = open(impl_filename, "w") - f_impl.write(impl_hls_code) - f_impl.close() - - def execute_node(self, context, graph): - mode = self.get_nodeattr("exec_mode") - node = self.onnx_node - exp_ishape = self.get_normal_input_shape() - exp_oshape = self.get_normal_output_shape() - folded_ishape = self.get_folded_input_shape() - n_outputs = self.get_num_output_streams() - - if mode == "cppsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - elif mode == "rtlsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) - - inp = context[node.input[0]] - assert str(inp.dtype) == "float32", "Input datatype is not float32" - assert inp.shape == exp_ishape, """Input shape doesn't match expected shape .""" - export_idt = self.get_input_datatype() - # reshape input into folded form - inp = inp.reshape(folded_ishape) - # make copy before saving array - reshaped_input = inp.copy() - np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input) - - if mode == "cppsim": - # execute the precompiled model - super().exec_precompiled_singlenode_model() - # load output npy file - super().npy_to_dynamic_outputs(context, ["output%d.npy" % i for i in range(n_outputs)]) - for i in range(n_outputs): - assert ( - context[node.output[i]].shape == exp_oshape - ), "cppsim \ - did not produce expected output shape" - elif mode == "rtlsim": - sim = self.get_rtlsim() - nbits = self.get_instream_width() - rtlsim_inp = npy_to_rtlsim_input( - "{}/input_0.npy".format(code_gen_dir), export_idt, nbits - ) - super().reset_rtlsim(sim) - super().toggle_clk(sim) - rtlsim_dict = { - "inputs": {"in0": rtlsim_inp}, - "outputs": {}, - } - for i in range(n_outputs): - rtlsim_dict["outputs"]["out%d" % i] = [] - self.rtlsim_multi_io(sim, rtlsim_dict) - odt = self.get_output_datatype() - target_bits = odt.bitwidth() - packed_bits = self.get_outstream_width() - out_shape = self.get_folded_output_shape() - for i in range(n_outputs): - out_npy_path = "%s/output%d.npy" % (code_gen_dir, i) - rtlsim_output_to_npy( - rtlsim_dict["outputs"]["out%d" % i], - out_npy_path, - odt, - out_shape, - packed_bits, - target_bits, - ) - # load and reshape output 0 - output = np.load(out_npy_path) - output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) - context[node.output[i]] = output - - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) - - assert ( - context[node.output[0]].shape == exp_oshape - ), """Output0 shape doesn't match expected shape.""" - assert ( - context[node.output[1]].shape == exp_oshape - ), """Output1 shape doesn't match expected shape.""" - - def global_includes(self): - self.code_gen_dict["$GLOBALS$"] = ['#include "duplicate_impl.hpp"'] - - def defines(self, var): - self.code_gen_dict["$DEFINES$"] = [] - - def read_npy_data(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_input_datatype() - elem_bits = dtype.bitwidth() - packed_bits = self.get_instream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_in = "%s/input_0.npy" % code_gen_dir - self.code_gen_dict["$READNPYDATA$"] = [] - self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - npy_in, - self.hls_sname(), - ) - ) - - def strm_decl(self): - n_outputs = self.get_num_output_streams() - self.code_gen_dict["$STREAMDECLARATIONS$"] = [] - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0_{} ("in0_{}");'.format( - self.get_instream_width(), self.hls_sname(), self.hls_sname() - ) - ) - for i in range(n_outputs): - out_name = "out%d_%s" % (i, self.hls_sname()) - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> %s ("%s");' - % (self.get_outstream_width(), out_name, out_name) - ) - - def docompute(self): - n_outputs = self.get_num_output_streams() - ostreams = [] - for i in range(n_outputs): - ostreams.append("out%d_%s" % (i, self.hls_sname())) - dc = "DuplicateStreamsCustom(in0_%s, %s);" % ( - self.hls_sname(), - ",".join(ostreams), - ) - self.code_gen_dict["$DOCOMPUTE$"] = [dc] - - def dataoutstrm(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_output_datatype() - elem_bits = dtype.bitwidth() - packed_bits = self.get_outstream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - n_outputs = self.get_num_output_streams() - oshape = self.get_folded_output_shape() - oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") - outstrm_code = [] - - for i in range(n_outputs): - out_name = "out%d_%s" % (i, self.hls_sname()) - npy_out = "%s/output%d.npy" % (code_gen_dir, i) - outstrm_code.append( - 'apintstream2npy<%s, %s, %d, %s>(%s, %s, "%s");' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - out_name, - oshape_cpp_str, - npy_out, - ) - ) - - self.code_gen_dict["$DATAOUTSTREAM$"] = outstrm_code - - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - - def blackboxfunction(self): - n_outputs = self.get_num_output_streams() - inp_streams = [] - o_stream_w = self.get_outstream_width() - i_stream_w = self.get_instream_width() - in_stream = "hls::stream > &in0_%s" % (i_stream_w, self.hls_sname()) - inp_streams.append(in_stream) - for i in range(n_outputs): - out_stream = "hls::stream > &out%d_%s" % ( - o_stream_w, - i, - self.hls_sname(), - ) - inp_streams.append(out_stream) - - self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - """void {}({})""".format( - self.onnx_node.name, - ",".join(inp_streams), - ) - ] - - def pragmas(self): - n_outputs = self.get_num_output_streams() - self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() - ] - for i in range(n_outputs): - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out%d_%s" % (i, self.hls_sname()) - ) - self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") - - def get_verilog_top_module_intf_names(self): - intf_names = super().get_verilog_top_module_intf_names() - n_outputs = self.get_num_output_streams() - sname = self.hls_sname() - intf_names["m_axis"] = [] - for i in range(n_outputs): - intf_names["m_axis"].append( - ("out%d_%s" % (i, sname), self.get_outstream_width_padded()) - ) - return intf_names - - def derive_characteristic_fxns(self, period): - n_inps = np.prod(self.get_folded_input_shape()[:-1]) - io_dict = { - "inputs": { - "in0": [0 for i in range(n_inps)], - }, - "outputs": {"out0": [], "out1": []}, - } - super().derive_characteristic_fxns(period, override_rtlsim_dict=io_dict) diff --git a/src/finn/custom_op/fpgadataflow/eltwise.py b/src/finn/custom_op/fpgadataflow/eltwise.py deleted file mode 100644 index ab1dc00118..0000000000 --- a/src/finn/custom_op/fpgadataflow/eltwise.py +++ /dev/null @@ -1,484 +0,0 @@ -# Copyright (c) 2022, Xilinx -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# * Redistributions of source code must retain the above copyright notice, this -# list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# * Neither the name of FINN nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -import numpy as np -import os -import warnings -from qonnx.core.datatype import DataType - -from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp -from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy - - -class StreamingEltwise(HLSCustomOp): - """Class that corresponds to finn-hlslib StreamingEltwise function.""" - - def __init__(self, onnx_node, **kwargs): - super().__init__(onnx_node, **kwargs) - - def get_nodeattr_types(self): - my_attrs = super().get_nodeattr_types() - my_attrs.update( - { - "NumChannels": ("i", True, ""), - "PE": ("i", True, ""), - # FINN DataTypes for inputs; output datatype inferred from input - "inputDataType0": ("s", True, ""), - "inputDataType1": ("s", True, ""), - # type of EltwiseFunction for the operation - "eltwiseOp": ("s", True, "", ["Add", "Sub", "AbsDiff"]), - # number of input vectors, examples: - # [1] is a single vector (like a FC layer with batch=1) - # [4] is four vectors (like a FC layer with batch=4) - # [1, 4, 4] is four * four vectors (like a conv layer with batch=1) - "numInputVectors": ("ints", False, [1]), - "inFIFODepths": ("ints", False, [2, 2]), - } - ) - return my_attrs - - def get_eltwise_op_lambda(self): - eltwise_op = self.get_nodeattr("eltwiseOp") - idt0 = self.get_input_datatype(0) - idt1 = self.get_input_datatype(1) - odt = self.get_output_datatype() - tin0 = idt0.get_hls_datatype_str() - tin1 = idt1.get_hls_datatype_str() - tout = odt.get_hls_datatype_str() - eltwise_ops = { - # "Add": "[](auto a, auto b) { return a + b; }", - # "Sub": "[](auto a, auto b) { return a - b; }", - # "AbsDiff": "[](auto a, auto b) { return a>b? a-b : b-a; }", - "Add": f"add<{tin0}, {tin1}, {tout}>()", - "Sub": f"sub<{tin0}, {tin1}, {tout}>()", - "AbsDiff": f"absdiff<{tin0}, {tin1}, {tout}>()", - } - return eltwise_ops[eltwise_op] - - def get_normal_input_shape(self, ind=0): - ich = self.get_nodeattr("NumChannels") - vecs = list(self.get_nodeattr("numInputVectors")) - ishape = tuple(vecs + [ich]) - return ishape - - def get_folded_input_shape(self, ind=0): - ich = self.get_nodeattr("NumChannels") - pe = self.get_nodeattr("PE") - assert ich % pe == 0, "PE must divide NumChannels" - vecs = list(self.get_nodeattr("numInputVectors")) - ishape = tuple(vecs + [ich // pe, pe]) - return ishape - - def get_normal_output_shape(self, ind=0): - return self.get_normal_input_shape() - - def get_folded_output_shape(self, ind=0): - return self.get_folded_input_shape() - - def make_shape_compatible_op(self, model): - exp_ishape = self.get_normal_input_shape() - oshape = self.get_normal_output_shape() - ishape = tuple(model.get_tensor_shape(self.onnx_node.input[0])) - assert ishape == exp_ishape, "Unexpected input1 shape." - ishape = tuple(model.get_tensor_shape(self.onnx_node.input[1])) - assert ishape == exp_ishape, "Unexpected input2 shape." - return super().make_const_shape_op(oshape) - - def infer_node_datatype(self, model): - node = self.onnx_node - idt0 = model.get_tensor_datatype(node.input[0]) - if idt0 != self.get_input_datatype(0): - warn_str = "inputDataType0 changing for %s: %s -> %s " % ( - node.name, - str(self.get_input_datatype(0)), - str(idt0), - ) - warnings.warn(warn_str) - self.set_nodeattr("inputDataType0", idt0.name) - idt1 = model.get_tensor_datatype(node.input[1]) - if idt1 != self.get_input_datatype(1): - warn_str = "inputDataType1 changing for %s: %s -> %s " % ( - node.name, - str(self.get_input_datatype(1)), - str(idt1), - ) - warnings.warn(warn_str) - self.set_nodeattr("inputDataType1", idt1.name) - # enforce output data type (calculated based on idt) - odt = self.get_output_datatype() - model.set_tensor_datatype(self.onnx_node.output[0], odt) - - def verify_node(self): - info_messages = [] - # verify that "backend" is set to "fpgadataflow" - backend_value = self.get_nodeattr("backend") - if backend_value == "fpgadataflow": - info_messages.append("Attribute backend is set correctly") - else: - info_messages.append('Attribute backend should be set to "fpgadataflow"') - - # verify that all necessary attributes exist - try: - self.get_nodeattr("code_gen_dir_cppsim") - self.get_nodeattr("executable_path") - self.get_nodeattr("NumChannels") - self.get_nodeattr("PE") - self.get_nodeattr("inputDataType0") - self.get_nodeattr("inputDataType1") - self.get_nodeattr("eltwiseOp") - info_messages.append("All necessary attributes exist") - except Exception: - info_messages.append("""The required StreamingEltwise attributes do not exist.""") - - return info_messages - - def get_input_datatype(self, ind=0): - """Returns FINN DataType of input.""" - return DataType[self.get_nodeattr("inputDataType" + str(ind))] - - def get_output_datatype(self, ind=0): - """Returns FINN DataType of output.""" - op = self.get_nodeattr("eltwiseOp") - idt0 = self.get_input_datatype(0) - idt1 = self.get_input_datatype(1) - assert idt0.signed() == idt1.signed(), ( - "%s: Inputs must have same signedness" % self.onnx_node.name - ) - idt0_min, idt0_max = idt0.min(), idt0.max() - idt1_min, idt1_max = idt1.min(), idt1.max() - cands = [ - idt0_min - idt1_min, - idt0_min - idt1_max, - idt0_max - idt1_min, - idt0_max - idt1_max, - ] - largest_magnitude = max(map(abs, cands)) - if op == "Add": - if idt0.signed(): - return DataType.get_smallest_possible(idt0.min() + idt1.min()) - else: - return DataType.get_smallest_possible(idt0.max() + idt1.max()) - elif op == "Sub": - return DataType.get_smallest_possible(-largest_magnitude) - elif op == "AbsDiff": - return DataType.get_smallest_possible(largest_magnitude) - else: - raise Exception("%s: Unknown eltWiseOp = %s" % (self.onnx_node.name, op)) - - def get_instream_width(self, ind=0): - """Returns input stream width.""" - ibits = self.get_input_datatype(ind).bitwidth() - pe = self.get_nodeattr("PE") - in_width = pe * ibits - return in_width - - def get_outstream_width(self, ind=0): - """Returns output stream width.""" - obits = self.get_output_datatype().bitwidth() - pe = self.get_nodeattr("PE") - out_width = pe * obits - return out_width - - def get_number_output_values(self): - return np.prod(self.get_folded_output_shape()[:-1]) - - def get_exp_cycles(self): - # Channels/PE * batch size * fmdim * fmdim - return np.prod(self.get_folded_output_shape()[:-1]) - - def execute_node(self, context, graph): - mode = self.get_nodeattr("exec_mode") - node = self.onnx_node - exp_ishape = self.get_normal_input_shape() - exp_oshape = self.get_normal_output_shape() - folded_ishape = self.get_folded_input_shape() - - if mode == "cppsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - elif mode == "rtlsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) - - inp = context[node.input[0]] - assert str(inp.dtype) == "float32", "Input datatype is not float32" - assert inp.shape == exp_ishape, """Input0 shape doesn't match expected shape .""" - export_idt0 = self.get_input_datatype(0) - # reshape input into folded form - inp = inp.reshape(folded_ishape) - # make copy before saving array - reshaped_input = inp.copy() - np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input) - - # exact same thing for input1 - inp = context[node.input[1]] - assert str(inp.dtype) == "float32", "Input datatype is not float32" - assert inp.shape == exp_ishape, """Input1 shape doesn't match expected shape .""" - export_idt1 = self.get_input_datatype(1) - # reshape input into folded form - inp = inp.reshape(folded_ishape) - # make copy before saving array - reshaped_input = inp.copy() - np.save(os.path.join(code_gen_dir, "input_1.npy"), reshaped_input) - - if mode == "cppsim": - # execute the precompiled model - super().exec_precompiled_singlenode_model() - # load output npy file - super().npy_to_dynamic_output(context) - assert ( - context[node.output[0]].shape == exp_oshape - ), "cppsim did not produce expected output shape" - elif mode == "rtlsim": - sim = self.get_rtlsim() - nbits0 = self.get_instream_width(0) - nbits1 = self.get_instream_width(1) - rtlsim_inp0 = npy_to_rtlsim_input( - "{}/input_0.npy".format(code_gen_dir), export_idt0, nbits0 - ) - rtlsim_inp1 = npy_to_rtlsim_input( - "{}/input_1.npy".format(code_gen_dir), export_idt1, nbits1 - ) - super().reset_rtlsim(sim) - super().toggle_clk(sim) - rtlsim_output = self.rtlsim(sim, rtlsim_inp0, rtlsim_inp1) - odt = self.get_output_datatype() - target_bits = odt.bitwidth() - packed_bits = self.get_outstream_width() - out_npy_path = "{}/output.npy".format(code_gen_dir) - out_shape = self.get_folded_output_shape() - rtlsim_output_to_npy( - rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits - ) - # load and reshape output - output = np.load(out_npy_path) - output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) - context[node.output[0]] = output - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) - - assert ( - context[node.output[0]].shape == exp_oshape - ), """Output shape doesn't match expected shape.""" - - def global_includes(self): - self.code_gen_dict["$GLOBALS$"] = [ - '#include "eltwise.hpp"', - '#include "interpret.hpp"', - ] - - self.code_gen_dict["$GLOBALS$"].extend( - [ - "template", - "struct absdiff {", - "TO operator()(TI1 const &a, TI2 const &b) const {", - "#pragma HLS inline", - "return a>b? a-b : b-a;", - "}", - "};", - "template", - "struct sub {", - "TO operator()(TI1 const &a, TI2 const &b) const {", - "#pragma HLS inline", - "return a-b;", - "}", - "};", - "template", - "struct add {", - "TO operator()(TI1 const &a, TI2 const &b) const {", - "#pragma HLS inline", - "return a+b;", - "}", - "};", - ] - ) - - def defines(self, var): - self.code_gen_dict["$DEFINES$"] = [] - - def read_npy_data(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - idt0 = self.get_input_datatype(0) - idt1 = self.get_input_datatype(1) - elem_bits_0 = idt0.bitwidth() - elem_bits_1 = idt1.bitwidth() - packed_bits_0 = self.get_instream_width(0) - packed_hls_type_0 = "ap_uint<%d>" % packed_bits_0 - packed_bits_1 = self.get_instream_width(1) - packed_hls_type_1 = "ap_uint<%d>" % packed_bits_1 - elem_hls_type_0 = idt0.get_hls_datatype_str() - elem_hls_type_1 = idt1.get_hls_datatype_str() - npy_type = "float" - self.code_gen_dict["$READNPYDATA$"] = [] - npy_in = "%s/input_0.npy" % code_gen_dir - self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' - % ( - packed_hls_type_0, - elem_hls_type_0, - elem_bits_0, - npy_type, - npy_in, - self.hls_sname(), - ) - ) - npy_in = "%s/input_1.npy" % code_gen_dir - self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in1_%s);' - % ( - packed_hls_type_1, - elem_hls_type_1, - elem_bits_1, - npy_type, - npy_in, - self.hls_sname(), - ) - ) - - def strm_decl(self): - self.code_gen_dict["$STREAMDECLARATIONS$"] = [] - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0_{} ("in0_{}");'.format( - self.get_instream_width(0), self.hls_sname(), self.hls_sname() - ) - ) - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in1_{} ("in1_{}");'.format( - self.get_instream_width(1), self.hls_sname(), self.hls_sname() - ) - ) - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out_{} ("out_{}");'.format( - self.get_outstream_width(), self.hls_sname(), self.hls_sname() - ) - ) - - def docompute(self): - op = self.get_nodeattr("eltwiseOp") - idt0 = self.get_input_datatype(0) - idt1 = self.get_input_datatype(1) - odt = self.get_output_datatype() - elem_hls_type_0 = idt0.get_hls_datatype_str() - elem_hls_type_1 = idt1.get_hls_datatype_str() - out_hls_type = odt.get_hls_datatype_str() - slice_in0 = "Slice<%s>" % elem_hls_type_0 - slice_in1 = "Slice<%s>" % elem_hls_type_1 - slice_out = "Slice<%s>" % out_hls_type - eltwise_op_str = self.get_eltwise_op_lambda() - "%sEltwiseFunction<%s, %s, %s>()" % ( - op, - elem_hls_type_0, - elem_hls_type_1, - out_hls_type, - ) - self.code_gen_dict["$DOCOMPUTE$"] = [ - """{}<{}, {}, {}, {}, {}, {}>(in0_{}, in1_{}, out_{}, {});""".format( - "StreamingEltwise", - self.get_nodeattr("NumChannels"), - self.get_nodeattr("PE"), - int(np.prod(self.get_folded_output_shape()[:-2])), - slice_in0, - slice_in1, - slice_out, - self.hls_sname(), - self.hls_sname(), - self.hls_sname(), - eltwise_op_str, - ) - ] - - def dataoutstrm(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_output_datatype() - elem_bits = dtype.bitwidth() - packed_bits = self.get_outstream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_out = "%s/output.npy" % code_gen_dir - oshape = self.get_folded_output_shape() - oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") - - self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - self.hls_sname(), - oshape_cpp_str, - npy_out, - ) - ] - - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - - def blackboxfunction(self): - self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - """void {}(hls::stream> &in0_{}, hls::stream> &in1_{}, - hls::stream> &out_{})""".format( - self.onnx_node.name, - self.get_nodeattr("PE") * self.get_input_datatype(0).bitwidth(), - self.hls_sname(), - self.get_nodeattr("PE") * self.get_input_datatype(1).bitwidth(), - self.hls_sname(), - self.get_nodeattr("PE") * self.get_output_datatype().bitwidth(), - self.hls_sname(), - ) - ] - - def pragmas(self): - self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() - ] - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=in1_" + self.hls_sname() - ) - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() - ) - self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") - - def get_verilog_top_module_intf_names(self): - intf_names = super().get_verilog_top_module_intf_names() - sname = self.hls_sname() - swidth = self.get_instream_width_padded() - intf_names["s_axis"] = [(x + "_" + sname, swidth) for x in ["in0", "in1"]] - return intf_names diff --git a/src/finn/custom_op/fpgadataflow/fmpadding_batch.py b/src/finn/custom_op/fpgadataflow/fmpadding_batch.py deleted file mode 100644 index 5bd5e07916..0000000000 --- a/src/finn/custom_op/fpgadataflow/fmpadding_batch.py +++ /dev/null @@ -1,407 +0,0 @@ -# Copyright (c) 2020, Xilinx -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# * Redistributions of source code must retain the above copyright notice, this -# list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# * Neither the name of FINN nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -import numpy as np -import os -import warnings -from qonnx.core.datatype import DataType - -from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp -from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy - - -class FMPadding_Batch(HLSCustomOp): - """Corresponds to finn-hlslib FMPadding_Batch function. - Pads input image by given amount.""" - - def __init__(self, onnx_node, **kwargs): - super().__init__(onnx_node, **kwargs) - - def get_nodeattr_types(self): - my_attrs = { - # spatial size of input images - "ImgDim": ("ints", True, []), # [H, W] = [Y, X] - # total padding (per dimension) to apply - "Padding": ( - "ints", - True, - [1, 1, 1, 1], - ), # [H_begin, W_begin, H_end, W_end] = [Y_begin, X_begin, Y_end, X_end] - # number of channels in input image - "NumChannels": ("i", True, 0), - # SIMD Input parallelism - "SIMD": ("i", False, 1), - # FINN input datatype - "inputDataType": ("s", True, ""), - # shape describing input vecs per execution - "numInputVectors": ("i", False, 1), - } - my_attrs.update(super().get_nodeattr_types()) - return my_attrs - - def get_padded_odim(self): - "Return the padded spatial size of the output." - idim_h, idim_w = self.get_nodeattr("ImgDim") - pad = self.get_nodeattr("Padding") - pad_h = pad[0] + pad[2] - pad_w = pad[1] + pad[3] - odim_h = idim_h + pad_h - odim_w = idim_w + pad_w - return [odim_h, odim_w] - - def get_exp_cycles(self): - odim_h, odim_w = self.get_padded_odim() - channels = self.get_nodeattr("NumChannels") - simd = self.get_nodeattr("SIMD") - batch_size = self.get_nodeattr("numInputVectors") - exp_cycles = (channels / simd) * batch_size * odim_h * odim_w - return int(exp_cycles) - - def get_normal_input_shape(self, ind=0): - idim_h, idim_w = self.get_nodeattr("ImgDim") - num_ch = self.get_nodeattr("NumChannels") - ishape = (1, idim_h, idim_w, num_ch) - return ishape - - def get_normal_output_shape(self, ind=0): - odim_h, odim_w = self.get_padded_odim() - num_ch = self.get_nodeattr("NumChannels") - - oshape = (1, odim_h, odim_w, num_ch) - return oshape - - def get_folded_input_shape(self, ind=0): - normal_ishape = list(self.get_normal_input_shape()) - ifm_ch = self.get_nodeattr("NumChannels") - simd = self.get_nodeattr("SIMD") - assert ifm_ch % simd == 0, "SIMD must divide input channels" - fold = int(normal_ishape[-1] / simd) - folded_ishape = normal_ishape[:-1] + [fold, simd] - return tuple(folded_ishape) - - def get_folded_output_shape(self, ind=0): - normal_oshape = list(self.get_normal_output_shape()) - ifm_ch = self.get_nodeattr("NumChannels") - simd = self.get_nodeattr("SIMD") - assert ifm_ch % simd == 0, "SIMD must divide input channels" - fold = int(normal_oshape[-1] / simd) - folded_oshape = normal_oshape[:-1] + [fold, simd] - return tuple(folded_oshape) - - def make_shape_compatible_op(self, model): - exp_ishape = self.get_normal_input_shape() - oshape = self.get_normal_output_shape() - ishape = tuple(model.get_tensor_shape(self.onnx_node.input[0])) - assert ishape == exp_ishape, "Unexpect input shape for SameResize." - return super().make_const_shape_op(oshape) - - def infer_node_datatype(self, model): - node = self.onnx_node - idt = model.get_tensor_datatype(node.input[0]) - if idt != self.get_input_datatype(): - warn_str = "inputDataType changing for %s: %s -> %s " % ( - node.name, - str(self.get_input_datatype()), - str(idt), - ) - warnings.warn(warn_str) - self.set_nodeattr("inputDataType", idt.name) - model.set_tensor_datatype(node.output[0], idt) - - def verify_node(self): - pass - - def get_input_datatype(self, ind=0): - """Returns FINN DataType of input.""" - ret = DataType[self.get_nodeattr("inputDataType")] - # the hlslib op always pads with zeros, so ensure that the DataType - # is able to represent zeros - assert ret.allowed(0), "FMPadding_Batch DataType must support zero" - return ret - - def get_output_datatype(self, ind=0): - """Returns FINN DataType of output. (Same as input datatype)""" - return self.get_input_datatype() - - def get_instream_width(self, ind=0): - ibits = self.get_input_datatype().bitwidth() - simd = self.get_nodeattr("SIMD") - return ibits * simd - - def get_outstream_width(self, ind=0): - obits = self.get_output_datatype().bitwidth() - simd = self.get_nodeattr("SIMD") - return obits * simd - - def get_number_output_values(self): - folded_oshape = self.get_folded_output_shape() - return np.prod(folded_oshape[:-1]) - - def global_includes(self): - self.code_gen_dict["$GLOBALS$"] = ['#include "streamtools.h"'] - - def defines(self, var): - idim_h, idim_w = self.get_nodeattr("ImgDim") - odim_h, odim_w = self.get_padded_odim() - pad = self.get_nodeattr("Padding") - pad_h = pad[0] + pad[2] - pad_w = pad[1] + pad[3] - is_square_img = idim_h == idim_w - is_square_pad = pad_h == pad_w - - if is_square_img and is_square_pad: - self.code_gen_dict["$DEFINES$"] = [ - """#define ImgDim1 {}\n#define OutputDim1 {}\n - #define PaddingBefore1 {}\n#define PaddingBehind1 {}\n - #define NumChannels1 {}\n#define SIMD1 {}\n - #define numReps {}\n""".format( - idim_h, - odim_h, - pad[0], - pad[2], - self.get_nodeattr("NumChannels"), - self.get_nodeattr("SIMD"), - self.get_nodeattr("numInputVectors"), - ) - ] - else: - self.code_gen_dict["$DEFINES$"] = [ - """ - #define OutputDim1_x {}\n - #define OutputDim1_y {}\n - #define PaddingLeft1 {}\n - #define PaddingRight1 {}\n - #define PaddingTop1 {}\n - #define PaddingBottom1 {}\n - #define NumChannels1 {}\n - #define SIMD1 {}\n - #define numReps {}\n - """.format( - odim_w, - odim_h, - pad[1], - pad[3], - pad[0], - pad[2], - self.get_nodeattr("NumChannels"), - self.get_nodeattr("SIMD"), - self.get_nodeattr("numInputVectors"), - ) - ] - - def read_npy_data(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_input_datatype() - if dtype == DataType["BIPOLAR"]: - # use binary for bipolar storage - dtype = DataType["BINARY"] - elem_bits = dtype.bitwidth() - packed_bits = self.get_instream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_in = "%s/input_0.npy" % code_gen_dir - self.code_gen_dict["$READNPYDATA$"] = [] - self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - npy_in, - self.hls_sname(), - ) - ) - - def strm_decl(self): - self.code_gen_dict["$STREAMDECLARATIONS$"] = [] - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0_{} ("in0_{}");'.format( - self.get_instream_width(), self.hls_sname(), self.hls_sname() - ) - ) - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out_{} ("out_{}");'.format( - self.get_outstream_width(), self.hls_sname(), self.hls_sname() - ) - ) - - def docompute(self): - in_t = self.get_input_datatype().get_hls_datatype_str() - node = self.onnx_node - - idim_h, idim_w = self.get_nodeattr("ImgDim") - pad = self.get_nodeattr("Padding") - pad_h = pad[0] + pad[2] - pad_w = pad[1] + pad[3] - is_square_img = idim_h == idim_w - is_square_pad = pad_h == pad_w - - if is_square_img and is_square_pad: - hls_call = node.op_type - self.code_gen_dict["$DOCOMPUTE$"] = [ - """{} (in0_{}, out_{}, numReps);""".format( - hls_call, in_t, self.hls_sname(), self.hls_sname() - ) - ] - else: - hls_call = "FMPadding_nonsquare_Batch" - self.code_gen_dict["$DOCOMPUTE$"] = [ - """{} (in0_{}, out_{}, numReps);""".format( - hls_call, in_t, self.hls_sname(), self.hls_sname() - ) - ] - - def dataoutstrm(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_output_datatype() - if dtype == DataType["BIPOLAR"]: - # use binary for bipolar storage - dtype = DataType["BINARY"] - elem_bits = dtype.bitwidth() - packed_bits = self.get_outstream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_out = "%s/output.npy" % code_gen_dir - oshape = self.get_folded_output_shape() - oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") - - self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - self.hls_sname(), - oshape_cpp_str, - npy_out, - ) - ] - - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - - def blackboxfunction(self): - packed_bits = self.get_instream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - "void %s(hls::stream<%s > &in0_%s, hls::stream<%s > &out_%s)" - % ( - self.onnx_node.name, - packed_hls_type, - self.hls_sname(), - packed_hls_type, - self.hls_sname(), - ) - ] - - def pragmas(self): - self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() - ] - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() - ) - self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") - - def execute_node(self, context, graph): - mode = self.get_nodeattr("exec_mode") - node = self.onnx_node - exp_ishape = self.get_normal_input_shape() - exp_oshape = self.get_normal_output_shape() - folded_ishape = self.get_folded_input_shape() - - if mode == "cppsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - elif mode == "rtlsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) - - inp = context[node.input[0]] - assert str(inp.dtype) == "float32", "Input datatype is not float32" - assert ( - inp.shape == exp_ishape - ), """Input shape doesn't - match expected shape (1, ImgDim_h, ImgDim_w, NumChannels).""" - export_idt = self.get_input_datatype() - - reshaped_input = inp.reshape(folded_ishape) - np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input) - - if mode == "cppsim": - # execute the precompiled model - super().exec_precompiled_singlenode_model() - # load output npy file - super().npy_to_dynamic_output(context) - assert ( - context[node.output[0]].shape == exp_oshape - ), "cppsim did not produce expected output shape" - elif mode == "rtlsim": - sim = self.get_rtlsim() - nbits = self.get_instream_width() - rtlsim_inp = npy_to_rtlsim_input( - "{}/input_0.npy".format(code_gen_dir), export_idt, nbits - ) - super().reset_rtlsim(sim) - super().toggle_clk(sim) - rtlsim_output = self.rtlsim(sim, rtlsim_inp) - odt = export_idt - target_bits = odt.bitwidth() - packed_bits = self.get_outstream_width() - out_npy_path = "{}/output.npy".format(code_gen_dir) - out_shape = self.get_folded_output_shape() - rtlsim_output_to_npy( - rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits - ) - # load and reshape output - output = np.load(out_npy_path) - output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) - context[node.output[0]] = output - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) - assert ( - context[node.output[0]].shape == exp_oshape - ), """Output shape doesn't match expected shape - (1, OutputDim_H, OutputDim_W, NumChannels).""" diff --git a/src/finn/custom_op/fpgadataflow/fmpadding_rtl.py b/src/finn/custom_op/fpgadataflow/fmpadding_rtl.py deleted file mode 100644 index d79c214730..0000000000 --- a/src/finn/custom_op/fpgadataflow/fmpadding_rtl.py +++ /dev/null @@ -1,414 +0,0 @@ -# Copyright (C) 2022, Advanced Micro Devices, Inc. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# * Redistributions of source code must retain the above copyright notice, this -# list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# * Neither the name of FINN nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -import math -import numpy as np -import os -import shutil -import warnings -from qonnx.core.datatype import DataType -from qonnx.util.basic import roundup_to_integer_multiple - -from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp -from finn.util.basic import get_rtlsim_trace_depth, make_build_dir -from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy - -try: - from pyverilator import PyVerilator -except ModuleNotFoundError: - PyVerilator = None - - -class FMPadding_rtl(HLSCustomOp): - """CustomOp wrapper for the finn-rtllib fmpadding_axi component - Supports adjusting the padding amount and spatial feature sizes at - runtime.""" - - def __init__(self, onnx_node, **kwargs): - super().__init__(onnx_node, **kwargs) - - def get_nodeattr_types(self): - my_attrs = { - # spatial size of input images - "ImgDim": ("ints", True, []), # [H, W] = [Y, X] - # total padding (per dimension) to apply - "Padding": ( - "ints", - True, - [1, 1, 1, 1], - ), # [H_begin, W_begin, H_end, W_end] = [Y_begin, X_begin, Y_end, X_end] - # number of channels in input image - "NumChannels": ("i", True, 0), - # SIMD Input parallelism - "SIMD": ("i", False, 1), - # FINN input datatype - "inputDataType": ("s", True, ""), - # shape describing input vecs per execution - "numInputVectors": ("i", False, 1), - # Enable reprogrammable implementation to change FM dimensions, - # stride, or dilation during runtime - "dynamic_mode": ("i", False, 0, {0, 1}), - # attribute to save top module name - not user configurable - "gen_top_module": ("s", False, ""), - } - my_attrs.update(super().get_nodeattr_types()) - return my_attrs - - def get_padded_odim(self): - "Return the padded spatial size of the output." - idim_h, idim_w = self.get_nodeattr("ImgDim") - pad = self.get_nodeattr("Padding") - pad_h = pad[0] + pad[2] - pad_w = pad[1] + pad[3] - odim_h = idim_h + pad_h - odim_w = idim_w + pad_w - return [odim_h, odim_w] - - def get_exp_cycles(self): - odim_h, odim_w = self.get_padded_odim() - channels = self.get_nodeattr("NumChannels") - simd = self.get_nodeattr("SIMD") - batch_size = self.get_nodeattr("numInputVectors") - exp_cycles = (channels / simd) * batch_size * odim_h * odim_w - return int(exp_cycles) - - def get_normal_input_shape(self, ind=0): - idim_h, idim_w = self.get_nodeattr("ImgDim") - num_ch = self.get_nodeattr("NumChannels") - ishape = (1, idim_h, idim_w, num_ch) - return ishape - - def get_normal_output_shape(self, ind=0): - odim_h, odim_w = self.get_padded_odim() - num_ch = self.get_nodeattr("NumChannels") - - oshape = (1, odim_h, odim_w, num_ch) - return oshape - - def get_folded_input_shape(self, ind=0): - normal_ishape = list(self.get_normal_input_shape()) - ifm_ch = self.get_nodeattr("NumChannels") - simd = self.get_nodeattr("SIMD") - assert ifm_ch % simd == 0, "SIMD must divide input channels" - fold = int(normal_ishape[-1] / simd) - folded_ishape = normal_ishape[:-1] + [fold, simd] - return tuple(folded_ishape) - - def get_folded_output_shape(self, ind=0): - normal_oshape = list(self.get_normal_output_shape()) - ifm_ch = self.get_nodeattr("NumChannels") - simd = self.get_nodeattr("SIMD") - assert ifm_ch % simd == 0, "SIMD must divide input channels" - fold = int(normal_oshape[-1] / simd) - folded_oshape = normal_oshape[:-1] + [fold, simd] - return tuple(folded_oshape) - - def make_shape_compatible_op(self, model): - exp_ishape = self.get_normal_input_shape() - oshape = self.get_normal_output_shape() - ishape = tuple(model.get_tensor_shape(self.onnx_node.input[0])) - assert ishape == exp_ishape, "Unexpected input shape for FMPadding_rtl." - return super().make_const_shape_op(oshape) - - def infer_node_datatype(self, model): - node = self.onnx_node - idt = model.get_tensor_datatype(node.input[0]) - if idt != self.get_input_datatype(): - warn_str = "inputDataType changing for %s: %s -> %s " % ( - node.name, - str(self.get_input_datatype()), - str(idt), - ) - warnings.warn(warn_str) - self.set_nodeattr("inputDataType", idt.name) - model.set_tensor_datatype(node.output[0], idt) - - def verify_node(self): - pass - - def get_input_datatype(self, ind=0): - """Returns FINN DataType of input.""" - ret = DataType[self.get_nodeattr("inputDataType")] - # the hlslib op always pads with zeros, so ensure that the DataType - # is able to represent zeros - assert ret.allowed(0), "FMPadding_rtl DataType must support zero" - return ret - - def get_output_datatype(self, ind=0): - """Returns FINN DataType of output. (Same as input datatype)""" - return self.get_input_datatype() - - def get_instream_width(self, ind=0): - ibits = self.get_input_datatype().bitwidth() - simd = self.get_nodeattr("SIMD") - return ibits * simd - - def get_outstream_width(self, ind=0): - obits = self.get_output_datatype().bitwidth() - simd = self.get_nodeattr("SIMD") - return obits * simd - - def get_number_output_values(self): - folded_oshape = self.get_folded_output_shape() - return np.prod(folded_oshape[:-1]) - - def get_verilog_top_module_intf_names(self): - # Overload default HLSCustomOp implementation to add axilite control IF - intf_names = super().get_verilog_top_module_intf_names() - if self.get_nodeattr("dynamic_mode"): - intf_names["axilite"] = ["s_axilite"] - return intf_names - - def execute_node(self, context, graph): - mode = self.get_nodeattr("exec_mode") - node = self.onnx_node - exp_ishape = self.get_normal_input_shape() - exp_oshape = self.get_normal_output_shape() - folded_ishape = self.get_folded_input_shape() - - if mode == "cppsim": - raise Exception("cppsim not possible for FMPadding_rtl, please set exec_mode to rtlsim") - elif mode == "rtlsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) - - inp = context[node.input[0]] - assert str(inp.dtype) == "float32", "Input datatype is not float32" - assert ( - inp.shape == exp_ishape - ), """Input shape doesn't - match expected shape (1, ImgDim_h, ImgDim_w, NumChannels).""" - export_idt = self.get_input_datatype() - - reshaped_input = inp.reshape(folded_ishape) - np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input) - - sim = self.get_rtlsim() - nbits = self.get_instream_width() - rtlsim_inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) - super().reset_rtlsim(sim) - super().toggle_clk(sim) - rtlsim_output = self.rtlsim(sim, rtlsim_inp) - odt = export_idt - target_bits = odt.bitwidth() - packed_bits = self.get_outstream_width() - out_npy_path = "{}/output.npy".format(code_gen_dir) - out_shape = self.get_folded_output_shape() - rtlsim_output_to_npy(rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits) - # load and reshape output - output = np.load(out_npy_path) - output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) - context[node.output[0]] = output - - assert ( - context[node.output[0]].shape == exp_oshape - ), """Output shape doesn't match expected shape - (1, OutputDim_H, OutputDim_W, NumChannels).""" - - def get_template_values(self, ifm_dims, pads, chans, simd, idt): - dimY, dimX = ifm_dims - padT, padL, padB, padR = pads - y_counter_bits = int(math.ceil(math.log2(padT + dimY + padB + 1))) - x_counter_bits = int(math.ceil(math.log2(padL + dimX + padR + 1))) - topname = self.get_verilog_top_module_name() - stream_bits = idt.bitwidth() * simd - stream_bits = int(roundup_to_integer_multiple(stream_bits, 8)) - code_gen_dict = { - "XCOUNTER_BITS": int(x_counter_bits), - "YCOUNTER_BITS": int(y_counter_bits), - "NUM_CHANNELS": int(chans), - "SIMD": int(simd), - "ELEM_BITS": idt.bitwidth(), - "TOP_MODULE_NAME": topname, - "INIT_XON": int(padL), - "INIT_XOFF": int(padL + dimX), - "INIT_XEND": int(padL + dimX + padR - 1), - "INIT_YON": int(padT), - "INIT_YOFF": int(padT + dimY), - "INIT_YEND": int(padT + dimY + padB - 1), - "STREAM_BITS": int(stream_bits), - } - return code_gen_dict - - def get_dynamic_config(self, ifm_dims=None, pads=None): - """Returns a configuration dict to re-configure FM dimension and - padding amounts during runtime.""" - - if ifm_dims is None: - ifm_dims = self.get_nodeattr("ImgDim") - if pads is None: - pads = self.get_nodeattr("Padding") - chans = self.get_nodeattr("NumChannels") - simd = self.get_nodeattr("SIMD") - idt = self.get_input_datatype() - code_gen_dict = self.get_template_values(ifm_dims, pads, chans, simd, idt) - config = { - "XON": (0 * 4, (code_gen_dict["INIT_XON"])), - "XOFF": (1 * 4, (code_gen_dict["INIT_XOFF"])), - "XEND": (2 * 4, (code_gen_dict["INIT_XEND"])), - "YON": (3 * 4, (code_gen_dict["INIT_YON"])), - "YOFF": (4 * 4, (code_gen_dict["INIT_YOFF"])), - "YEND": (5 * 4, (code_gen_dict["INIT_YEND"])), - } - return config - - def generate_hdl(self): - rtlsrc = os.environ["FINN_ROOT"] + "/finn-rtllib/fmpadding/hdl" - template_path = rtlsrc + "/fmpadding_template.v" - dims = self.get_nodeattr("ImgDim") - pads = self.get_nodeattr("Padding") - chans = self.get_nodeattr("NumChannels") - simd = self.get_nodeattr("SIMD") - idt = self.get_input_datatype() - code_gen_dict = self.get_template_values(dims, pads, chans, simd, idt) - # save top module name so we can refer to it after this node has been renamed - # (e.g. by GiveUniqueNodeNames(prefix) during MakeZynqProject) - self.set_nodeattr("gen_top_module", self.get_verilog_top_module_name()) - - # apply code generation to templates - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - with open(template_path, "r") as f: - template = f.read() - for key_name in code_gen_dict: - key = "$%s$" % key_name - template = template.replace(key, str(code_gen_dict[key_name])) - - with open( - os.path.join(code_gen_dir, self.get_verilog_top_module_name() + ".v"), - "w", - ) as f: - f.write(template) - - sv_files = ["fmpadding_axi.sv", "fmpadding.sv", "axi2we.sv"] - for sv_file in sv_files: - shutil.copy(rtlsrc + "/" + sv_file, code_gen_dir) - # set ipgen_path and ip_path so that HLS-Synth transformation - # and stich_ip transformation do not complain - self.set_nodeattr("ipgen_path", code_gen_dir) - self.set_nodeattr("ip_path", code_gen_dir) - - def prepare_rtlsim(self): - """Creates a Verilator emulation library for the RTL code generated - for this node, sets the rtlsim_so attribute to its path and returns - a PyVerilator wrapper around it.""" - # Modified to use generated (System-)Verilog instead of HLS output products - - if PyVerilator is None: - raise ImportError("Installation of PyVerilator is required.") - - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - verilog_paths = [code_gen_dir] - verilog_files = [ - "fmpadding_axi.sv", - "fmpadding.sv", - "axi2we.sv", - self.get_nodeattr("gen_top_module") + ".v", - ] - - # build the Verilator emu library - sim = PyVerilator.build( - verilog_files, - build_dir=make_build_dir("pyverilator_" + self.onnx_node.name + "_"), - verilog_path=verilog_paths, - trace_depth=get_rtlsim_trace_depth(), - top_module_name=self.get_verilog_top_module_name(), - ) - # save generated lib filename in attribute - self.set_nodeattr("rtlsim_so", sim.lib._name) - return sim - - def code_generation_ipi(self): - """Constructs and returns the TCL for node instantiation in Vivado IPI.""" - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - - sourcefiles = [ - "fmpadding_axi.sv", - "fmpadding.sv", - "axi2we.sv", - self.get_nodeattr("gen_top_module") + ".v", - ] - - sourcefiles = [os.path.join(code_gen_dir, f) for f in sourcefiles] - - cmd = [] - for f in sourcefiles: - cmd += ["add_files -norecurse %s" % (f)] - cmd += [ - "create_bd_cell -type module -reference %s %s" - % (self.get_nodeattr("gen_top_module"), self.onnx_node.name) - ] - return cmd - - def code_generation_ipgen(self, model, fpgapart, clk): - """Normally: Generates C++ code and tcl script for IP generation. - Here: Generates (System-)Verilog code for IP generation.""" - self.generate_hdl() - - def ipgen_singlenode_code(self): - """Normally: Builds the bash script for IP generation.""" - pass - - def code_generation_cppsim(self, model): - """Normally: Generates C++ code for simulation (cppsim).""" - pass - - def compile_singlenode_code(self): - pass - - def global_includes(self): - pass - - def defines(self, var): - pass - - def read_npy_data(self): - pass - - def strm_decl(self): - pass - - def docompute(self): - pass - - def dataoutstrm(self): - pass - - def save_as_npy(self): - pass - - def blackboxfunction(self): - pass - - def pragmas(self): - pass diff --git a/src/finn/custom_op/fpgadataflow/globalaccpool_batch.py b/src/finn/custom_op/fpgadataflow/globalaccpool_batch.py deleted file mode 100644 index 5ed440dace..0000000000 --- a/src/finn/custom_op/fpgadataflow/globalaccpool_batch.py +++ /dev/null @@ -1,352 +0,0 @@ -# Copyright (c) 2020, Xilinx -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# * Redistributions of source code must retain the above copyright notice, this -# list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# * Neither the name of FINN nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -import numpy as np -import os -import warnings -from qonnx.core.datatype import DataType - -from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp -from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy - - -class GlobalAccPool_Batch(HLSCustomOp): - """Class that corresponds to finn-hlslib AccPool_Batch function.""" - - def __init__(self, onnx_node, **kwargs): - super().__init__(onnx_node, **kwargs) - - def get_nodeattr_types(self): - my_attrs = { - "NumChannels": ("i", True, 0), - "PE": ("i", True, 0), - # FINN DataTypes for input - "inputDataType": ("s", True, ""), - # number of input vectors, examples: - # [1] is a single vector (like a FC layer with batch=1) - # [4] is four vectors (like a FC layer with batch=4) - # [1, 4, 4] is four * four vectors (like a conv layer with batch=1) - "numInputVectors": ("ints", False, [1]), - } - my_attrs.update(super().get_nodeattr_types()) - return my_attrs - - def get_normal_input_shape(self, ind=0): - ch = self.get_nodeattr("NumChannels") - vecs = list(self.get_nodeattr("numInputVectors")) - ishape = tuple(vecs + [ch]) - return ishape - - def get_folded_input_shape(self, ind=0): - ch = self.get_nodeattr("NumChannels") - pe = self.get_nodeattr("PE") - vecs = list(self.get_nodeattr("numInputVectors")) - assert ch % pe == 0, "PE must divide NumChannels" - folds = int(ch / pe) - folded_ishape = tuple(vecs + [folds, pe]) - return folded_ishape - - def get_normal_output_shape(self, ind=0): - ch = self.get_nodeattr("NumChannels") - vecs = list(self.get_nodeattr("numInputVectors")) - if len(vecs) == 1: - oshape = tuple(vecs + [ch]) - elif len(vecs) == 3: - oshape = tuple([vecs[0]] + [1, 1, ch]) - return oshape - - def get_folded_output_shape(self, ind=0): - ch = self.get_nodeattr("NumChannels") - pe = self.get_nodeattr("PE") - unfolded_shape = list(self.get_normal_output_shape()) - assert ch % pe == 0, "PE must divide NumChannels" - folds = int(ch / pe) - oshape = tuple(unfolded_shape[:-1] + [folds, pe]) - return oshape - - def make_shape_compatible_op(self, model): - exp_ishape = self.get_normal_input_shape() - oshape = self.get_normal_output_shape() - ishape = tuple(model.get_tensor_shape(self.onnx_node.input[0])) - assert ishape == exp_ishape, "Unexpected input shape." - return super().make_const_shape_op(oshape) - - def infer_node_datatype(self, model): - node = self.onnx_node - idt = model.get_tensor_datatype(node.input[0]) - if idt != self.get_input_datatype(): - warn_str = "inputDataType changing for %s: %s -> %s " % ( - node.name, - str(self.get_input_datatype()), - str(idt), - ) - warnings.warn(warn_str) - self.set_nodeattr("inputDataType", idt.name) - odt = self.get_output_datatype() - model.set_tensor_datatype(self.onnx_node.output[0], odt) - - def verify_node(self): - info_messages = [] - # verify that "backend" is set to "fpgadataflow" - backend_value = self.get_nodeattr("backend") - if backend_value == "fpgadataflow": - info_messages.append("Attribute backend is set correctly") - else: - info_messages.append('Attribute backend should be set to "fpgadataflow"') - - # verify that all necessary attributes exist - try: - self.get_nodeattr("code_gen_dir_cppsim") - self.get_nodeattr("executable_path") - self.get_nodeattr("NumChannels") - self.get_nodeattr("PE") - self.get_nodeattr("inputDataType") - info_messages.append("All necessary attributes exist") - except Exception: - info_messages.append("""The required GlobalAccPool_Batch attributes do not exist.""") - - # verify that input data is 2D - if len(self.get_nodeattr("numInputVectors")) != 3: - info_messages.append("""GlobalAccPool_Batch requires 2D data input.""") - raise Exception - - return info_messages - - def get_input_datatype(self, ind=0): - """Returns FINN DataType of input.""" - return DataType[self.get_nodeattr("inputDataType")] - - def get_output_datatype(self, ind=0): - """Returns FINN DataType of output.""" - # determine data type from image size and input type - idt = DataType[self.get_nodeattr("inputDataType")] - vecs = list(self.get_nodeattr("numInputVectors")) - npixels = vecs[-1] * vecs[-2] - if idt.signed(): - extreme_value = npixels * idt.min() - else: - extreme_value = npixels * idt.max() - return DataType.get_smallest_possible(extreme_value) - - def get_instream_width(self, ind=0): - """Returns input stream width.""" - ibits = self.get_input_datatype().bitwidth() - pe = self.get_nodeattr("PE") - in_width = pe * ibits - return in_width - - def get_outstream_width(self, ind=0): - """Returns output stream width.""" - obits = self.get_output_datatype().bitwidth() - pe = self.get_nodeattr("PE") - out_width = pe * obits - return out_width - - def get_number_output_values(self): - return np.prod(self.get_folded_output_shape()[1:-1]) - - def get_exp_cycles(self): - # Channels/PE * batch size * idim * idim + Channels/PE - ch = self.get_nodeattr("NumChannels") - pe = self.get_nodeattr("PE") - folds = int(ch / pe) - return int(np.prod(self.get_folded_input_shape()[:-1]) + folds) - - def execute_node(self, context, graph): - mode = self.get_nodeattr("exec_mode") - node = self.onnx_node - exp_ishape = self.get_normal_input_shape() - exp_oshape = self.get_normal_output_shape() - folded_ishape = self.get_folded_input_shape() - - if mode == "cppsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - elif mode == "rtlsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) - - inp = context[node.input[0]] - assert str(inp.dtype) == "float32", "Input datatype is not float32" - assert inp.shape == exp_ishape, """Input shape doesn't match expected shape .""" - export_idt = self.get_input_datatype() - # reshape input into folded form - inp = inp.reshape(folded_ishape) - # make copy before saving array - reshaped_input = inp.copy() - np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input) - - if mode == "cppsim": - # execute the precompiled model - super().exec_precompiled_singlenode_model() - # load output npy file - super().npy_to_dynamic_output(context) - assert ( - context[node.output[0]].shape == exp_oshape - ), "cppsim \ - did not produce expected output shape" - elif mode == "rtlsim": - sim = self.get_rtlsim() - nbits = self.get_instream_width() - rtlsim_inp = npy_to_rtlsim_input( - "{}/input_0.npy".format(code_gen_dir), export_idt, nbits - ) - super().reset_rtlsim(sim) - super().toggle_clk(sim) - rtlsim_output = self.rtlsim(sim, rtlsim_inp) - odt = self.get_output_datatype() - target_bits = odt.bitwidth() - packed_bits = self.get_outstream_width() - out_npy_path = "{}/output.npy".format(code_gen_dir) - out_shape = self.get_folded_output_shape() - rtlsim_output_to_npy( - rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits - ) - # load and reshape output - output = np.load(out_npy_path) - output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) - context[node.output[0]] = output - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) - - assert ( - context[node.output[0]].shape == exp_oshape - ), """Output shape doesn't match expected shape.""" - - def global_includes(self): - self.code_gen_dict["$GLOBALS$"] = ['#include "maxpool.h"'] - - def defines(self, var): - self.code_gen_dict["$DEFINES$"] = [] - - def read_npy_data(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_input_datatype() - elem_bits = dtype.bitwidth() - packed_bits = self.get_instream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_in = "%s/input_0.npy" % code_gen_dir - self.code_gen_dict["$READNPYDATA$"] = [] - self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - npy_in, - self.hls_sname(), - ) - ) - - def strm_decl(self): - self.code_gen_dict["$STREAMDECLARATIONS$"] = [] - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0_{} ("in0_{}");'.format( - self.get_instream_width(), self.hls_sname(), self.hls_sname() - ) - ) - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out_{} ("out_{}");'.format( - self.get_outstream_width(), self.hls_sname(), self.hls_sname() - ) - ) - - def docompute(self): - self.code_gen_dict["$DOCOMPUTE$"] = [ - """AccPool_Batch<{}, {}, {}, {}, {}> (in0_{}, out_{}, 1);""".format( - self.get_normal_input_shape()[1], - self.get_nodeattr("NumChannels"), - self.get_input_datatype().get_hls_datatype_str(), - self.get_nodeattr("PE"), - self.get_output_datatype().get_hls_datatype_str(), - self.hls_sname(), - self.hls_sname(), - ) - ] - - def dataoutstrm(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_output_datatype() - elem_bits = dtype.bitwidth() - packed_bits = self.get_outstream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_out = "%s/output.npy" % code_gen_dir - oshape = self.get_folded_output_shape() - oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") - - self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - self.hls_sname(), - oshape_cpp_str, - npy_out, - ) - ] - - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - - def blackboxfunction(self): - self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - """void {}(hls::stream> &in0_{}, - hls::stream> &out_{})""".format( - self.onnx_node.name, - self.get_instream_width(), - self.hls_sname(), - self.get_outstream_width(), - self.hls_sname(), - ) - ] - - def pragmas(self): - self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() - ] - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() - ) - self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") diff --git a/src/finn/custom_op/fpgadataflow/labelselect_batch.py b/src/finn/custom_op/fpgadataflow/labelselect_batch.py deleted file mode 100644 index 60d3eb9154..0000000000 --- a/src/finn/custom_op/fpgadataflow/labelselect_batch.py +++ /dev/null @@ -1,369 +0,0 @@ -# Copyright (c) 2020, Xilinx -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# * Redistributions of source code must retain the above copyright notice, this -# list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# * Neither the name of FINN nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -import numpy as np -import os -from onnx import TensorProto, helper -from qonnx.core.datatype import DataType -from qonnx.util.basic import roundup_to_integer_multiple - -from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp -from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy - - -class LabelSelect_Batch(HLSCustomOp): - """Class that corresponds to finn-hlslib LabelSelect_Batch function.""" - - def __init__(self, onnx_node, **kwargs): - super().__init__(onnx_node, **kwargs) - odt_name = self.get_nodeattr("outputDataType") - if odt_name == "": - # If not provided compute min size - labels = self.get_nodeattr("Labels") - odt = DataType.get_smallest_possible(labels - 1) - # ensure a datatype divisible by 8-bits in case this is the last node - bw = roundup_to_integer_multiple(odt.bitwidth(), 8) - new_odt_name = odt.name.replace(str(odt.bitwidth()), str(bw)) - odt = DataType[new_odt_name] - odt_name = odt.name - self.set_nodeattr("outputDataType", odt_name) - - def get_nodeattr_types(self): - my_attrs = { - "Labels": ("i", True, 0), - "PE": ("i", True, 0), - "K": ("i", True, 0), - # FINN DataTypes for input - "inputDataType": ("s", True, ""), - "outputDataType": ("s", False, ""), - # number of input vectors, examples: - # [1] is a single vector (like a FC layer with batch=1) - # [4] is four vectors (like a FC layer with batch=4) - # [1, 4, 4] is four * four vectors (like a conv layer with batch=1) - "numInputVectors": ("ints", False, [1]), - } - my_attrs.update(super().get_nodeattr_types()) - return my_attrs - - def get_normal_input_shape(self, ind=0): - nlabels = self.get_nodeattr("Labels") - vecs = list(self.get_nodeattr("numInputVectors")) - ishape = tuple(vecs + [nlabels]) - return ishape - - def get_folded_input_shape(self, ind=0): - nlabels = self.get_nodeattr("Labels") - pe = self.get_nodeattr("PE") - vecs = list(self.get_nodeattr("numInputVectors")) - assert nlabels % pe == 0, "PE must divide Labels" - folds = int(nlabels / pe) - folded_ishape = tuple(vecs + [folds, pe]) - return folded_ishape - - def get_normal_output_shape(self, ind=0): - k = self.get_nodeattr("K") - vecs = list(self.get_nodeattr("numInputVectors")) - oshape = tuple(vecs + [k]) - return oshape - - def get_folded_output_shape(self, ind=0): - k = self.get_nodeattr("K") - vecs = list(self.get_nodeattr("numInputVectors")) - oshape = tuple(vecs + [k, 1]) - return oshape - - def make_shape_compatible_op(self, model): - exp_ishape = self.get_normal_input_shape() - oshape = self.get_normal_output_shape() - ishape = tuple(model.get_tensor_shape(self.onnx_node.input[0])) - assert ishape == exp_ishape, "Unexpected input shape." - return helper.make_node( - "RandomNormal", - inputs=[], - outputs=[self.onnx_node.output[0]], - mean=0.0, - scale=1.0, - dtype=TensorProto.INT64, - shape=list(oshape), - ) - - def infer_node_datatype(self, model): - node = self.onnx_node - # check input datatype against property - idt = model.get_tensor_datatype(node.input[0]) - self.set_nodeattr("inputDataType", idt.name) - - odt = self.get_output_datatype() - model.set_tensor_datatype(self.onnx_node.output[0], odt) - - def verify_node(self): - info_messages = [] - # verify that "backend" is set to "fpgadataflow" - backend_value = self.get_nodeattr("backend") - if backend_value == "fpgadataflow": - info_messages.append("Attribute backend is set correctly") - else: - info_messages.append('Attribute backend should be set to "fpgadataflow"') - - # verify that all necessary attributes exist - try: - self.get_nodeattr("code_gen_dir_cppsim") - self.get_nodeattr("executable_path") - self.get_nodeattr("Labels") - self.get_nodeattr("PE") - self.get_nodeattr("K") - self.get_nodeattr("inputDataType") - self.get_nodeattr("outputDataType") - info_messages.append("All necessary attributes exist") - except Exception: - info_messages.append("""The required LabelSelect_Batch attributes do not exist.""") - - # verify that input data is 1D - if len(self.get_nodeattr("numInputVectors")) > 1: - info_messages.append("""LabelSelect_Batch requires 1D data input.""") - raise Exception - - return info_messages - - def get_input_datatype(self, ind=0): - """Returns FINN DataType of input.""" - ret = DataType[self.get_nodeattr("inputDataType")] - return ret - - def get_output_datatype(self, ind=0): - """Returns FINN DataType of output.""" - ret = DataType[self.get_nodeattr("outputDataType")] - return ret - - def get_instream_width(self, ind=0): - """Returns input stream width.""" - ibits = self.get_input_datatype().bitwidth() - pe = self.get_nodeattr("PE") - in_width = pe * ibits - return in_width - - def get_outstream_width(self, ind=0): - """Returns output stream width.""" - return self.get_output_datatype().bitwidth() - - def get_number_output_values(self): - return self.get_nodeattr("K") - - def execute_node(self, context, graph): - mode = self.get_nodeattr("exec_mode") - node = self.onnx_node - exp_ishape = self.get_normal_input_shape() - exp_oshape = self.get_normal_output_shape() - folded_ishape = self.get_folded_input_shape() - - if mode == "cppsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - elif mode == "rtlsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) - - inp = context[node.input[0]] - assert str(inp.dtype) == "float32", "Input datatype is not float32" - assert inp.shape == exp_ishape, """Input shape doesn't match expected shape .""" - export_idt = self.get_input_datatype() - # reshape input into folded form - inp = inp.reshape(folded_ishape) - # make copy before saving array - reshaped_input = inp.copy() - np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input) - - if mode == "cppsim": - # execute the precompiled model - super().exec_precompiled_singlenode_model() - # load output npy file - super().npy_to_dynamic_output(context) - assert ( - context[node.output[0]].shape == exp_oshape - ), "cppsim \ - did not produce expected output shape" - elif mode == "rtlsim": - sim = self.get_rtlsim() - nbits = self.get_instream_width() - rtlsim_inp = npy_to_rtlsim_input( - "{}/input_0.npy".format(code_gen_dir), export_idt, nbits - ) - super().reset_rtlsim(sim) - super().toggle_clk(sim) - rtlsim_output = self.rtlsim(sim, rtlsim_inp) - odt = self.get_output_datatype() - target_bits = odt.bitwidth() - packed_bits = self.get_outstream_width() - out_npy_path = "{}/output.npy".format(code_gen_dir) - out_shape = self.get_folded_output_shape() - rtlsim_output_to_npy( - rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits - ) - # load and reshape output - output = np.load(out_npy_path) - output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) - context[node.output[0]] = output - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) - - assert ( - context[node.output[0]].shape == exp_oshape - ), """Output shape doesn't match expected shape.""" - # TopK ind output normally uses TensorProto.INT64, which - # can cause issues for the node-by-node simulation in FINN - # (as the custom DataType system always assumes float containers) - # so cast the output to int64 - ret = context[node.output[0]] - context[node.output[0]] = ret.astype(np.int64) - - def global_includes(self): - self.code_gen_dict["$GLOBALS$"] = ['#include "maxpool.h"'] - - def defines(self, var): - self.code_gen_dict["$DEFINES$"] = [] - - def read_npy_data(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_input_datatype() - elem_bits = dtype.bitwidth() - packed_bits = self.get_instream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_in = "%s/input_0.npy" % code_gen_dir - self.code_gen_dict["$READNPYDATA$"] = [] - - # Calling npy2apintstream with reverse_inner = false to have LE packing - # as required by HLS fxn LabelSelect_Batch - # Also notice that StreamingDataWidthConverter_Batch performs LE packing - - self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s, false);' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - npy_in, - self.hls_sname(), - ) - ) - - def strm_decl(self): - self.code_gen_dict["$STREAMDECLARATIONS$"] = [] - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0_{} ("in0_{}");'.format( - self.get_instream_width(), self.hls_sname(), self.hls_sname() - ) - ) - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out_{} ("out_{}");'.format( - self.get_outstream_width(), self.hls_sname(), self.hls_sname() - ) - ) - - def docompute(self): - node = self.onnx_node - self.code_gen_dict["$DOCOMPUTE$"] = [ - """{}<{}, {}, {}, {}, {} > (in0_{}, out_{}, 1);""".format( - node.op_type, - self.get_nodeattr("Labels"), - self.get_nodeattr("PE"), - self.get_nodeattr("K"), - self.get_input_datatype().get_hls_datatype_str(), - self.get_output_datatype().get_hls_datatype_str(), - self.hls_sname(), - self.hls_sname(), - ) - ] - - def dataoutstrm(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_output_datatype() - elem_bits = dtype.bitwidth() - packed_bits = self.get_outstream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_out = "%s/output.npy" % code_gen_dir - oshape = self.get_folded_output_shape() - oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") - - self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - self.hls_sname(), - oshape_cpp_str, - npy_out, - ) - ] - - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - - def blackboxfunction(self): - self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - """void {}(hls::stream> &in0_{}, - hls::stream > &out_{})""".format( - self.onnx_node.name, - self.get_nodeattr("PE"), - self.get_input_datatype().bitwidth(), - self.hls_sname(), - self.get_output_datatype().bitwidth(), - self.hls_sname(), - ) - ] - - def pragmas(self): - self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() - ] - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() - ) - self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") - - def get_exp_cycles(self): - nlabels = self.get_nodeattr("Labels") - pe = self.get_nodeattr("PE") - exp_cycles = nlabels / pe - return int(exp_cycles) diff --git a/src/finn/custom_op/fpgadataflow/streamingmaxpool_batch.py b/src/finn/custom_op/fpgadataflow/streamingmaxpool_batch.py deleted file mode 100755 index 8f294da4ac..0000000000 --- a/src/finn/custom_op/fpgadataflow/streamingmaxpool_batch.py +++ /dev/null @@ -1,441 +0,0 @@ -# Copyright (c) 2020, Xilinx -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# * Redistributions of source code must retain the above copyright notice, this -# list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# * Neither the name of FINN nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -import numpy as np -import os -import warnings -from qonnx.core.datatype import DataType -from qonnx.custom_op.general.maxpoolnhwc import compute_pool_output_dim - -from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp -from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy - -# TODO: consider splitting this into separate implementations for 1D and 2D -# similar to what we do for ConvolutionInputGenerator - - -class StreamingMaxPool_Batch(HLSCustomOp): - """Class that corresponds to finn-hlslib StreamingMaxPool_batch function.""" - - def get_nodeattr_types(self): - my_attrs = { - "ImgDim": ("ints", True, []), # [H, W] = [Y, X] - "PoolDim": ("ints", True, []), # [H, W] = [Y, X] - "NumChannels": ("i", True, 0), - # parallelism control - only supported for 1D maxpool - "PE": ("i", False, 0), - # round up (instead of down) output size - only supported for 1D maxpool - "CeilMode": ("i", False, 0), - # FINN DataTypes for inputs/outputs - "dataType": ("s", True, ""), - } - my_attrs.update(super().get_nodeattr_types()) - return my_attrs - - def get_input_datatype(self, ind=0): - """Returns FINN DataType of input.""" - return DataType[self.get_nodeattr("dataType")] - - def get_output_datatype(self, ind=0): - """Returns FINN DataType of output.""" - return DataType[self.get_nodeattr("dataType")] - - def get_1d_attrs_normalized(self): - # support both (1, D) and (D, 1) cases transparently: - # assume the dummy ('1') dimension is the Y-dimension, i.e. - # images and kernels (and their attributes) of dimension - # [H, W] = [Y, X] = [D, 1] or [1, D] are always mapped to [1, D] - ifm_dim = self.get_nodeattr("ImgDim") - k = self.get_nodeattr("PoolDim") - ifm_ch = self.get_nodeattr("NumChannels") - if ifm_dim[1] == 1: - ifm_dim = ifm_dim[::-1] - k = k[::-1] - return (ifm_dim, k, ifm_ch) - - def is_1d(self): - ifm_dim, k, ifm_ch = self.get_1d_attrs_normalized() - return (ifm_dim[0] == 1) and (k[0] == 1) - - def get_normal_input_shape(self, ind=0): - ifm_dim_h, ifm_dim_w = self.get_nodeattr("ImgDim") - ifm_ch = self.get_nodeattr("NumChannels") - ishape = (1, ifm_dim_h, ifm_dim_w, ifm_ch) - return ishape - - def get_folded_input_shape(self, ind=0): - ifm_dim_h, ifm_dim_w = self.get_nodeattr("ImgDim") - ifm_ch = self.get_nodeattr("NumChannels") - pe = self.get_nodeattr("PE") - nf = int(ifm_ch / pe) - if self.is_1d(): - folded_ishape = (1, ifm_dim_h, ifm_dim_w, nf, pe) - else: - folded_ishape = (1, ifm_dim_h, ifm_dim_w, 1, ifm_ch) - return folded_ishape - - def get_normal_output_shape(self, ind=0): - ifm_dim_h, ifm_dim_w = self.get_nodeattr("ImgDim") - k_h, k_w = tuple(self.get_nodeattr("PoolDim")) - ifm_ch = self.get_nodeattr("NumChannels") - ceil_mode = self.get_nodeattr("CeilMode") - if not self.is_1d(): - assert ifm_dim_h % k_h == 0, "StreamingMaxPool needs ImgDim_h % PoolDim_h == 0" - assert ifm_dim_w % k_w == 0, "StreamingMaxPool needs ImgDim_w % PoolDim_w == 0" - ofm_dim_h = compute_pool_output_dim(ifm_dim_h, k_h, k_h, 0, ceil_mode) - ofm_dim_w = compute_pool_output_dim(ifm_dim_w, k_w, k_w, 0, ceil_mode) - oshape = (1, ofm_dim_h, ofm_dim_w, ifm_ch) - return oshape - - def get_folded_output_shape(self, ind=0): - # even though there is no folding in the current hlslib op, - # insert a time multiplexing axis to remain compatible with the - # shapes produced by the rest of the dataflow pipeline - ifm_ch = self.get_nodeattr("NumChannels") - pe = self.get_nodeattr("PE") - nf = int(ifm_ch / pe) - ret = list(self.get_normal_output_shape()) - if self.is_1d(): - ret[-1] = nf - ret.append(pe) - else: - ret.insert(-1, 1) - return tuple(ret) - - def get_number_output_values(self): - folded_oshape = self.get_folded_output_shape() - return np.prod(folded_oshape[:-1]) - - def get_exp_cycles(self): - # derived from StreamingMaxPool_Batch loop nest - ifm_dim, k, ifm_ch = self.get_1d_attrs_normalized() - - warnings.warn( - """Estimated latency for layer {} can be lower than - actual latency!""".format( - self.onnx_node.name - ) - ) - if self.is_1d(): - _, _, _, nf, _ = self.get_folded_output_shape() - ceil_mode = self.get_nodeattr("CeilMode") - ofm_dim = compute_pool_output_dim(ifm_dim[1], k[1], k[1], 0, ceil_mode) - exp_cycles = ofm_dim * nf * (k[1] + 1) - return int(exp_cycles) - else: - # TODO: adjust inaccurate formula - return int(ifm_dim[1] * ifm_dim[1] * (1 + 1 / (k[1] * k[1]))) - - def get_instream_width(self, ind=0): - dt_bits = self.get_input_datatype().bitwidth() - pe = self.get_nodeattr("PE") - ifm_ch = self.get_nodeattr("NumChannels") - if self.is_1d(): - in_width = int(dt_bits * pe) - else: - in_width = int(dt_bits * ifm_ch) - return in_width - - def get_outstream_width(self, ind=0): - """For streaming maxpool out stream width is the same as in stream width""" - return self.get_instream_width() - - def make_shape_compatible_op(self, model): - exp_ishape = self.get_normal_input_shape() - oshape = self.get_normal_output_shape() - ishape = tuple(model.get_tensor_shape(self.onnx_node.input[0])) - assert ishape == exp_ishape, "Unexpect input shape for StreamingMaxPool." - return super().make_const_shape_op(oshape) - - def infer_node_datatype(self, model): - node = self.onnx_node - idt = model.get_tensor_datatype(node.input[0]) - if idt != self.get_input_datatype(): - warn_str = "inputDataType changing for %s: %s -> %s " % ( - node.name, - str(self.get_input_datatype()), - str(idt), - ) - warnings.warn(warn_str) - self.set_nodeattr("dataType", idt.name) - # data type stays the same - model.set_tensor_datatype(node.output[0], idt) - - def verify_node(self): - info_messages = [] - # verify that "backend" is set to "fpgadataflow" - backend_value = self.get_nodeattr("backend") - if backend_value == "fpgadataflow": - info_messages.append("Attribute backend is set correctly") - else: - info_messages.append('Attribute backend should be set to "fpgadataflow"') - - # verify the number of inputs - if len(self.onnx_node.input) == 1: - info_messages.append("The number of inputs is correct") - else: - info_messages.append("""StreamingMaxPool_Batch needs 1 data input""") - - return info_messages - - def global_includes(self): - self.code_gen_dict["$GLOBALS$"] = ['#include "maxpool.h"'] - - def defines(self, var): - numReps = 1 - ifm_dim, k, ifm_ch = self.get_1d_attrs_normalized() - ceil_mode = self.get_nodeattr("CeilMode") - output_size = compute_pool_output_dim(ifm_dim[1], k[1], k[1], 0, ceil_mode) - - if self.is_1d(): - self.code_gen_dict["$DEFINES$"] = [ - """#define ImgDim {}\n #define PoolDim {}\n - #define NumChannels {}\n #define PE {}\n #define OutputSize {} - \n #define numReps {}""".format( - ifm_dim[1], - k[1], - self.get_nodeattr("NumChannels"), - self.get_nodeattr("PE"), - output_size, - numReps, - ) - ] - else: - self.code_gen_dict["$DEFINES$"] = [ - """#define ImgDim {}\n #define PoolDim {}\n - #define NumChannels {}\n #define numReps {}""".format( - ifm_dim[1], - k[1], - self.get_nodeattr("NumChannels"), - numReps, - ) - ] - - def read_npy_data(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_input_datatype() - if dtype == DataType["BIPOLAR"]: - # use binary for bipolar storage - dtype = DataType["BINARY"] - elem_bits = dtype.bitwidth() - packed_bits = self.get_instream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_in = "%s/input_0.npy" % code_gen_dir - self.code_gen_dict["$READNPYDATA$"] = [] - self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - npy_in, - self.hls_sname(), - ) - ) - - def strm_decl(self): - self.code_gen_dict["$STREAMDECLARATIONS$"] = [] - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0_{} ("in0_{}");'.format( - self.get_instream_width(), self.hls_sname(), self.hls_sname() - ) - ) - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out_{} ("out_{}");'.format( - self.get_outstream_width(), self.hls_sname(), self.hls_sname() - ) - ) - - def docompute(self): - dtype = self.get_input_datatype() - if dtype.bitwidth() == 1: - if self.is_1d(): - raise Exception("Binary 1d MaxPool not implemented on HLS backend") - else: - op = "StreamingMaxPool" - self.code_gen_dict["$DOCOMPUTE$"] = [ - "%s(in0_%s, out_%s);" - % (op, self.hls_sname(), self.hls_sname()) - ] - else: - dtype = self.get_input_datatype() - dtype_hls = dtype.get_hls_datatype_str() - minval_str = str(int(dtype.min())) - if self.is_1d(): - op = "StreamingMaxPool_Precision_1d" - self.code_gen_dict["$DOCOMPUTE$"] = [ - """%s(in0_%s, out_%s);""" - % (op, dtype_hls, minval_str, self.hls_sname(), self.hls_sname()) - ] - else: - op = "StreamingMaxPool_Precision" - self.code_gen_dict["$DOCOMPUTE$"] = [ - "%s(in0_%s, out_%s);" - % (op, dtype_hls, minval_str, self.hls_sname(), self.hls_sname()) - ] - - def dataoutstrm(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_output_datatype() - if dtype == DataType["BIPOLAR"]: - # use binary for bipolar storage - dtype = DataType["BINARY"] - elem_bits = dtype.bitwidth() - packed_bits = self.get_outstream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_out = "%s/output.npy" % code_gen_dir - oshape = self.get_folded_output_shape() - oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") - - self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - self.hls_sname(), - oshape_cpp_str, - npy_out, - ) - ] - - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - - def blackboxfunction(self): - packed_bits = self.get_instream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - "void %s(hls::stream<%s > &in0_%s, hls::stream<%s > &out_%s)" - % ( - self.onnx_node.name, - packed_hls_type, - self.hls_sname(), - packed_hls_type, - self.hls_sname(), - ) - ] - - def pragmas(self): - self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() - ] - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() - ) - self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") - - def execute_node(self, context, graph): - mode = self.get_nodeattr("exec_mode") - node = self.onnx_node - exp_ishape = self.get_normal_input_shape() - exp_oshape = self.get_normal_output_shape() - folded_ishape = self.get_folded_input_shape() - - # TODO ensure codegen dir exists - if mode == "cppsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - elif mode == "rtlsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) - - inp = context[node.input[0]] - assert str(inp.dtype) == "float32", "Input datatype is not float32" - assert ( - inp.shape == exp_ishape - ), """Input shape doesn't - match expected shape (1, ifm_dim, ifm_dim, ifm_ch).""" - if self.get_input_datatype() == DataType["BIPOLAR"]: - # store bipolar activations as binary - inp = (inp + 1) / 2 - export_idt = DataType["BINARY"] - else: - export_idt = self.get_input_datatype() - - reshaped_input = inp.reshape(folded_ishape) - np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input) - - if mode == "cppsim": - # execute the precompiled model - super().exec_precompiled_singlenode_model() - # load output npy file - super().npy_to_dynamic_output(context) - assert ( - context[node.output[0]].shape == exp_oshape - ), "cppsim \ - did not produce expected output shape" - elif mode == "rtlsim": - sim = self.get_rtlsim() - nbits = self.get_instream_width() - rtlsim_inp = npy_to_rtlsim_input( - "{}/input_0.npy".format(code_gen_dir), export_idt, nbits - ) - super().reset_rtlsim(sim) - super().toggle_clk(sim) - rtlsim_output = self.rtlsim(sim, rtlsim_inp) - odt = export_idt - target_bits = odt.bitwidth() - packed_bits = self.get_outstream_width() - out_npy_path = "{}/output.npy".format(code_gen_dir) - out_shape = self.get_folded_output_shape() - rtlsim_output_to_npy( - rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits - ) - # load and reshape output - output = np.load(out_npy_path) - output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) - context[node.output[0]] = output - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) - # binary -> bipolar if needed - if self.get_output_datatype() == DataType["BIPOLAR"]: - out = context[node.output[0]] - out = 2 * out - 1 - context[node.output[0]] = out - assert ( - context[node.output[0]].shape == exp_oshape - ), """Output - shape doesn't match expected shape (1, ofm_dim, ofm_dim, ifm_ch).""" From 6c51d5e7633791f7ba65f8969a5f0ed7d2c0125a Mon Sep 17 00:00:00 2001 From: Hugo LE BLEVEC Date: Tue, 19 Dec 2023 16:36:52 +0100 Subject: [PATCH 354/665] Update to Brevitas commit hash to a version that contains espcn code --- fetch-repos.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fetch-repos.sh b/fetch-repos.sh index 87b1ae91c7..63819c418f 100755 --- a/fetch-repos.sh +++ b/fetch-repos.sh @@ -29,7 +29,7 @@ QONNX_COMMIT="47e4357faf66b5b0d1bf77bf908bb47752421e5b" FINN_EXP_COMMIT="0aa7e1c44b20cf085b6fe42cff360f0a832afd2c" -BREVITAS_COMMIT="9bb26bf2798de210a267d1e4aed4c20087e0e8a5" +BREVITAS_COMMIT="84f42259ec869eb151af4cb8a8b23ad925f493db" PYVERILATOR_COMMIT="766e457465f5c0dd315490d7b9cc5d74f9a76f4f" CNPY_COMMIT="4e8810b1a8637695171ed346ce68f6984e585ef4" HLSLIB_COMMIT="16e5847a5e3ef76cffe84c8fad2f010d593457d3" From 1f73702cab37dc0ee758ae93dd8f86873f76a4eb Mon Sep 17 00:00:00 2001 From: Tim Paine <3105306+timkpaine@users.noreply.github.com> Date: Tue, 19 Dec 2023 15:58:06 -0500 Subject: [PATCH 355/665] [Docs] Fix minor typos `run_docker.sh` -> `run-docker.sh` --- docs/finn/getting_started.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/docs/finn/getting_started.rst b/docs/finn/getting_started.rst index 9b3111b70e..61f0c4a58e 100644 --- a/docs/finn/getting_started.rst +++ b/docs/finn/getting_started.rst @@ -59,7 +59,7 @@ Simply running sh run-docker.sh without any additional arguments will create a D :: - bash ./run_docker.sh + bash ./run-docker.sh Launch a Build with ``build_dataflow`` @@ -70,8 +70,8 @@ or a user-defined flow from the command line as follows: :: - bash ./run_docker.sh build_dataflow - bash ./run_docker.sh build_custom + bash ./run-docker.sh build_dataflow + bash ./run-docker.sh build_custom Launch Jupyter notebooks From 86b883ace1fcbe8d6fb1db4b3d39896a99dbd4d2 Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 2 Jan 2024 15:23:58 +0000 Subject: [PATCH 356/665] [Tests] Fix copyright header in test case --- .../streamline/test_move_scalar_past_convtranspose.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tests/transformation/streamline/test_move_scalar_past_convtranspose.py b/tests/transformation/streamline/test_move_scalar_past_convtranspose.py index 1e894c9cb2..7da22abd87 100644 --- a/tests/transformation/streamline/test_move_scalar_past_convtranspose.py +++ b/tests/transformation/streamline/test_move_scalar_past_convtranspose.py @@ -1,4 +1,4 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2023, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -97,6 +97,7 @@ def test_move_scalar_past_conv(idim, stride, ifm_ch, ofm_ch, k, padding): np.random.seed(0) model.set_initializer("p1", *np.random.rand(1).astype(np.float32)) model.set_initializer("p2", np.random.rand(*conv_param_shape).astype(np.float32)) + new_model = model.transform(MoveScalarMulPastConvTranspose()) inp_dict = {"top_in": np.random.rand(*input_shape).astype(np.float32)} From d8fbfd9df598834f0aa58a09709fdd02e043f930 Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 2 Jan 2024 15:39:32 +0000 Subject: [PATCH 357/665] [Tests] Change assertion to pytest skip in brevitas export test --- tests/brevitas/test_brevitas_deconv.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tests/brevitas/test_brevitas_deconv.py b/tests/brevitas/test_brevitas_deconv.py index 0808122b7d..dfcecc9187 100644 --- a/tests/brevitas/test_brevitas_deconv.py +++ b/tests/brevitas/test_brevitas_deconv.py @@ -54,7 +54,8 @@ def test_brevitas_QTransposeConv(ifm_ch, ofm_ch, mh, mw, padding, stride, kw, bias): kh = kw oh = stride * (mh - 1) - (2 * padding) + kh - assert oh % mh == 0, "Needs to be evenly divisible." + if oh % mh != 0: + pytest.skip("Skip test because oh needs to be divisible by mh") ishape = (1, ifm_ch, mh, mw) # NCHW inp = torch.randn(ishape) b_deconv = qnn.QuantConvTranspose2d( From 2c2f38730c24ee265107820311e24339c90a7d5e Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 2 Jan 2024 17:30:09 +0000 Subject: [PATCH 358/665] [pixelpad] Omit redundant code and reduce test cases --- .../custom_op/fpgadataflow/fmpadding_pixel.py | 76 ++++++------------- .../fpgadataflow/test_fpgadataflow_deconv.py | 11 ++- 2 files changed, 29 insertions(+), 58 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/fmpadding_pixel.py b/src/finn/custom_op/fpgadataflow/fmpadding_pixel.py index d271297f82..e3ba400e9d 100644 --- a/src/finn/custom_op/fpgadataflow/fmpadding_pixel.py +++ b/src/finn/custom_op/fpgadataflow/fmpadding_pixel.py @@ -158,40 +158,23 @@ def global_includes(self): def defines(self, var): odim_h, odim_w = self.get_padded_odim() stride_h, stride_w = self.get_nodeattr("Stride") - is_square_img = odim_h == odim_w - is_square_stride = stride_h == stride_w - if is_square_img and is_square_stride: - self.code_gen_dict["$DEFINES$"] = [ - """ - #define OutputDim {}\n - #define Stride {}\n - #define NumChannels {}\n - #define SIMD {}\n - """.format( - odim_h, - stride_h, - self.get_nodeattr("NumChannels"), - self.get_nodeattr("SIMD"), - ) - ] - else: - self.code_gen_dict["$DEFINES$"] = [ - """ - #define OutputDim_x {}\n - #define OutputDim_y {}\n - #define Stride_x {}\n - #define Stride_y {}\n - #define NumChannels {}\n - #define SIMD {}\n - """.format( - odim_w, - odim_h, - stride_w, - stride_h, - self.get_nodeattr("NumChannels"), - self.get_nodeattr("SIMD"), - ) - ] + self.code_gen_dict["$DEFINES$"] = [ + """ + #define OutputDim_x {}\n + #define OutputDim_y {}\n + #define Stride_x {}\n + #define Stride_y {}\n + #define NumChannels {}\n + #define SIMD {}\n + """.format( + odim_w, + odim_h, + stride_w, + stride_h, + self.get_nodeattr("NumChannels"), + self.get_nodeattr("SIMD"), + ) + ] def read_npy_data(self): code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") @@ -224,24 +207,13 @@ def docompute(self): in_t = self.get_input_datatype().get_hls_datatype_str() odim_h, odim_w = self.get_padded_odim() stride_h, stride_w = self.get_nodeattr("Stride") - is_square_img = odim_h == odim_w - is_square_stride = stride_h == stride_w - - if is_square_img and is_square_stride: - hls_call = "FMPadding_Pixel" - self.code_gen_dict["$DOCOMPUTE$"] = [ - """{} (in0, out);""".format( - hls_call, in_t - ) - ] - else: - hls_call = "FMPadding_Pixel_Nonsquare" - self.code_gen_dict["$DOCOMPUTE$"] = [ - """{} (in0, out);""".format( - hls_call, in_t - ) - ] + hls_call = "FMPadding_Pixel_Nonsquare" + self.code_gen_dict["$DOCOMPUTE$"] = [ + """{} (in0, out);""".format( + hls_call, in_t + ) + ] def dataoutstrm(self): code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") diff --git a/tests/fpgadataflow/test_fpgadataflow_deconv.py b/tests/fpgadataflow/test_fpgadataflow_deconv.py index 227555701c..a78e7cf758 100644 --- a/tests/fpgadataflow/test_fpgadataflow_deconv.py +++ b/tests/fpgadataflow/test_fpgadataflow_deconv.py @@ -126,23 +126,22 @@ def set_up_reference_model(idt, wdt, k, idim, ifm_ch, ofm_ch, stride, padding): # number of rows and number of cols to add @pytest.mark.parametrize("stride", [[2, 2], [2, 3]]) # number of channels -@pytest.mark.parametrize("ifm_ch", [2, 4]) +@pytest.mark.parametrize("ifm_ch", [2]) # number of channels -@pytest.mark.parametrize("ofm_ch", [2, 4]) +@pytest.mark.parametrize("ofm_ch", [4]) # Input parallelism @pytest.mark.parametrize("simd", [1, 2]) # PE @pytest.mark.parametrize("pe", [1, 2]) # kernel size -@pytest.mark.parametrize("k", [2, 4]) +@pytest.mark.parametrize("k", [2]) # padding @pytest.mark.parametrize("padding", [0, 1]) -@pytest.mark.parametrize("idt", [DataType["INT4"], DataType["INT8"]]) @pytest.mark.fpgadataflow @pytest.mark.slow @pytest.mark.vivado -def test_fpgadataflow_deconv(idim, stride, ifm_ch, ofm_ch, simd, pe, k, padding, idt): - # idt = wdt = DataType["INT4"] +def test_fpgadataflow_deconv(idim, stride, ifm_ch, ofm_ch, simd, pe, k, padding): + idt = wdt = DataType["INT4"] wdt = idt idim_h, idim_w = idim stride_h, stride_w = stride From c8b80df26396ec63d70bc6a8b1fc41fe0dfebc05 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 3 Jan 2024 10:47:32 +0000 Subject: [PATCH 359/665] [Tests] Refactoring of deconv test --- .../fpgadataflow/test_fpgadataflow_deconv.py | 46 +++++++------------ 1 file changed, 16 insertions(+), 30 deletions(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_deconv.py b/tests/fpgadataflow/test_fpgadataflow_deconv.py index a78e7cf758..d5edec9b35 100644 --- a/tests/fpgadataflow/test_fpgadataflow_deconv.py +++ b/tests/fpgadataflow/test_fpgadataflow_deconv.py @@ -33,7 +33,7 @@ from qonnx.core.datatype import DataType from qonnx.core.modelwrapper import ModelWrapper from qonnx.custom_op.registry import getCustomOp -from qonnx.transformation.general import GiveReadableTensorNames, GiveUniqueNodeNames +from qonnx.transformation.general import GiveUniqueNodeNames from qonnx.transformation.infer_shapes import InferShapes from qonnx.util.basic import gen_finn_dt_tensor, qonnx_make_model @@ -43,10 +43,6 @@ InferConvInpGen, InferQuantizedMatrixVectorActivation, ) -from finn.transformation.fpgadataflow.create_dataflow_partition import ( - CreateDataflowPartition, -) -from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP from finn.transformation.fpgadataflow.infer_pixel_padding_deconv import ( InferPixelPaddingDeconv, @@ -137,10 +133,12 @@ def set_up_reference_model(idt, wdt, k, idim, ifm_ch, ofm_ch, stride, padding): @pytest.mark.parametrize("k", [2]) # padding @pytest.mark.parametrize("padding", [0, 1]) +# exec mode +@pytest.mark.parametrize("exec_mode", ["cppsim", "rtlsim"]) @pytest.mark.fpgadataflow @pytest.mark.slow @pytest.mark.vivado -def test_fpgadataflow_deconv(idim, stride, ifm_ch, ofm_ch, simd, pe, k, padding): +def test_fpgadataflow_deconv(idim, stride, ifm_ch, ofm_ch, simd, pe, k, padding, exec_mode): idt = wdt = DataType["INT4"] wdt = idt idim_h, idim_w = idim @@ -151,15 +149,16 @@ def test_fpgadataflow_deconv(idim, stride, ifm_ch, ofm_ch, simd, pe, k, padding) else: convinpgen_rtl = True + if exec_mode == "cppsim" and convinpgen_rtl: + pytest.skip("ConvolutionInputGenerator_rtl has no cppsim, skipping cppsim") + ref_model = set_up_reference_model(idt, wdt, k, idim, ifm_ch, ofm_ch, stride, padding) odim_h = (idim_h - 1) * stride_h - 2 * padding + (k - 1) + 1 odim_w = (idim_w - 1) * stride_w - 2 * padding + (k - 1) + 1 input_tensor = gen_finn_dt_tensor(idt, [1, ifm_ch, idim_h, idim_w]) - input_tensor_tr = input_tensor.transpose(0, 2, 3, 1) input_dict = {"inp": input_tensor} - input_dict_tr = {"global_in": input_tensor_tr} model = ref_model.transform(InferPixelPaddingDeconv()) model = model.transform(InferConvInpGen(use_rtl_variant=convinpgen_rtl)) @@ -179,9 +178,7 @@ def test_fpgadataflow_deconv(idim, stride, ifm_ch, ofm_ch, simd, pe, k, padding) expected_oshape = (1, ofm_ch, odim_h, odim_w) y_expected = oxe.execute_onnx(ref_model, input_dict)["outp"] # cppsim - if convinpgen_rtl: - print("ConvolutionInputGenerator_rtl has no cppsim, skipping cppsim") - else: + if exec_mode == "cppsim": model = model.transform(PrepareCppSim()) model = model.transform(CompileCppSim()) model = model.transform(SetExecMode("cppsim")) @@ -190,22 +187,11 @@ def test_fpgadataflow_deconv(idim, stride, ifm_ch, ofm_ch, simd, pe, k, padding) assert (y_produced == y_expected).all() # rtlsim - model = model.transform(PrepareIP(test_fpga_part, target_clk_ns)) - model = model.transform(HLSSynthIP()) - model.save("before_partition.onnx") - parent_model = model.transform(CreateDataflowPartition()) - sdp_nodes = parent_model.get_nodes_by_op_type("StreamingDataflowPartition") - assert len(sdp_nodes) == 1, "Only a single StreamingDataflowPartition supported." - sdp_node = sdp_nodes[0] - sdp_node = getCustomOp(sdp_node) - dataflow_model_filename = sdp_node.get_nodeattr("model") - model = ModelWrapper(dataflow_model_filename) - model.save("after_partition.onnx") - model = model.transform(CreateStitchedIP(test_fpga_part, target_clk_ns, vitis=False)) - model = model.transform(PrepareRTLSim()) - model = model.transform(GiveReadableTensorNames()) - model = model.transform(SetExecMode("rtlsim")) - model.save("stitched_ip.onnx") - y_produced = oxe.execute_onnx(model, input_dict_tr)["global_out"].transpose(0, 3, 1, 2) - assert y_produced.shape == expected_oshape - assert (y_produced == y_expected).all() + else: + model = model.transform(PrepareIP(test_fpga_part, target_clk_ns)) + model = model.transform(HLSSynthIP()) + model = model.transform(PrepareRTLSim()) + model = model.transform(SetExecMode("rtlsim")) + y_produced = oxe.execute_onnx(model, input_dict)["outp"] + assert y_produced.shape == expected_oshape + assert (y_produced == y_expected).all() From 859e674cada6b8819ba020f024d53b3cf0927a24 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 3 Jan 2024 10:59:29 +0000 Subject: [PATCH 360/665] [Docs] Update readthedocs config file --- .readthedocs.yaml | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/.readthedocs.yaml b/.readthedocs.yaml index 478957be11..8feb27485b 100644 --- a/.readthedocs.yaml +++ b/.readthedocs.yaml @@ -1,4 +1,5 @@ -# Copyright (c) 2021, Xilinx +# Copyright (c) 2021-2022, Xilinx +# Copyright (C) 2023-2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -31,6 +32,12 @@ version: 2 +# Set the version of Python and other tools you might need +build: + os: ubuntu-22.04 + tools: + python: "3.8" + sphinx: configuration: docs/finn/conf.py From 17d9237d2d8e394a649d01001ae176a673110874 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 3 Jan 2024 11:03:28 +0000 Subject: [PATCH 361/665] [Docs] Update syntax in rtd config file --- .readthedocs.yaml | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/.readthedocs.yaml b/.readthedocs.yaml index 8feb27485b..cb5031cb9c 100644 --- a/.readthedocs.yaml +++ b/.readthedocs.yaml @@ -42,9 +42,5 @@ sphinx: configuration: docs/finn/conf.py python: - version: 3.8 install: - - method: pip - path: . - extra_requirements: - - docs + - requirements: requirements.txt From 5d6cf699f255f1ae40428f32eeaabda24750e174 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 3 Jan 2024 11:08:52 +0000 Subject: [PATCH 362/665] [Docs] Add sphinx theme to requirements --- requirements.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/requirements.txt b/requirements.txt index e03eff2c98..1beddf701a 100644 --- a/requirements.txt +++ b/requirements.txt @@ -16,6 +16,7 @@ scipy==1.10.1 setupext-janitor>=1.1.2 setuptools==68.2.2 sigtools==4.0.1 +sphinx_rtd_theme==0.5.0 toposort==1.7.0 vcdvcd==1.0.5 wget==3.2 From 9dc0ee6cc7ada63d96b67360884b7e2ef0b04221 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 3 Jan 2024 11:14:43 +0000 Subject: [PATCH 363/665] [Docs] Separate docs requirements in docs folder --- .readthedocs.yaml | 2 +- docs/requirements.txt | 13 +++++++++++++ requirements.txt | 1 - 3 files changed, 14 insertions(+), 2 deletions(-) create mode 100644 docs/requirements.txt diff --git a/.readthedocs.yaml b/.readthedocs.yaml index cb5031cb9c..575a60c69d 100644 --- a/.readthedocs.yaml +++ b/.readthedocs.yaml @@ -43,4 +43,4 @@ sphinx: python: install: - - requirements: requirements.txt + - requirements: docs/requirements.txt diff --git a/docs/requirements.txt b/docs/requirements.txt new file mode 100644 index 0000000000..26c05d0025 --- /dev/null +++ b/docs/requirements.txt @@ -0,0 +1,13 @@ +brevitas@git+https://github.com/Xilinx/brevitas@master#egg=brevitas_examples +dataclasses-json==0.5.7 +docutils==0.17.1 +gspread==3.6.0 +IPython +netron +pytest +pyverilator@git+https://github.com/maltanar/pyverilator@master#egg=pyverilator +qonnx@git+https://github.com/fastmachinelearning/qonnx@main#egg=qonnx +sphinx_rtd_theme==0.5.0 +torch +torchvision +vcdvcd diff --git a/requirements.txt b/requirements.txt index 1beddf701a..e03eff2c98 100644 --- a/requirements.txt +++ b/requirements.txt @@ -16,7 +16,6 @@ scipy==1.10.1 setupext-janitor>=1.1.2 setuptools==68.2.2 sigtools==4.0.1 -sphinx_rtd_theme==0.5.0 toposort==1.7.0 vcdvcd==1.0.5 wget==3.2 From c741faee3fcbe29772aa475e2faa7b03d5d71238 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 3 Jan 2024 15:42:10 +0000 Subject: [PATCH 364/665] [PixelPadding] Add batchsize for expected cycles calc --- src/finn/custom_op/fpgadataflow/fmpadding_pixel.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/finn/custom_op/fpgadataflow/fmpadding_pixel.py b/src/finn/custom_op/fpgadataflow/fmpadding_pixel.py index e3ba400e9d..bc686bc6d2 100644 --- a/src/finn/custom_op/fpgadataflow/fmpadding_pixel.py +++ b/src/finn/custom_op/fpgadataflow/fmpadding_pixel.py @@ -70,7 +70,8 @@ def get_exp_cycles(self): odim_h, odim_w = self.get_padded_odim() channels = self.get_nodeattr("NumChannels") simd = self.get_nodeattr("SIMD") - exp_cycles = (channels / simd) * odim_h * odim_w + batch_size = self.get_nodeattr("numInputVectors") + exp_cycles = (channels / simd) * batch_size * odim_h * odim_w return int(exp_cycles) def get_normal_input_shape(self, ind=0): From 14929f41e948881a0ce20040c25ff2957928c7a0 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 3 Jan 2024 15:43:58 +0000 Subject: [PATCH 365/665] [Deconv] Update test and add comments to transformation --- .../infer_pixel_padding_deconv.py | 25 ++++++++++++------- .../fpgadataflow/test_fpgadataflow_deconv.py | 22 +++++++++++----- 2 files changed, 32 insertions(+), 15 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/infer_pixel_padding_deconv.py b/src/finn/transformation/fpgadataflow/infer_pixel_padding_deconv.py index 8642f5e0ef..8dbf7071fc 100644 --- a/src/finn/transformation/fpgadataflow/infer_pixel_padding_deconv.py +++ b/src/finn/transformation/fpgadataflow/infer_pixel_padding_deconv.py @@ -7,8 +7,14 @@ class InferPixelPaddingDeconv(Transformation): - def __init__(self): - super().__init__() + """ + Lowering and conversion of ConvTranspose (NCHW) nodes to + FMPadding_Pixel + Im2Col + MatMul (NHWC) surrounded by Transpose nodes + note: this transformation produces a mix of hw layers and non hw layers + to implement this on an FPGA the Im2Col and MatMul nodes need to be converted to hw layers + after applying this transformation and the resulting transpose nodes need to be streamlined. + See deconv test case under tests/fpgadataflow for an example. + """ def apply(self, model): graph = model.graph @@ -17,6 +23,14 @@ def apply(self, model): for n in graph.node: node_ind += 1 if n.op_type == "ConvTranspose": + # conversion currently only supported for group=1 + group = get_by_name(n.attribute, "group").i + if group != 1: + warnings.warn( + "%s : Only group=1 is currently supported. Can't infer PixelPaddingDeconv." + % n.name + ) + continue deconv_input = n.input[0] deconv_output = n.output[0] idt = model.get_tensor_datatype(deconv_input) @@ -25,13 +39,6 @@ def apply(self, model): k_w = get_by_name(n.attribute, "kernel_shape").ints[1] stride_h = get_by_name(n.attribute, "strides").ints[0] stride_w = get_by_name(n.attribute, "strides").ints[1] - group = get_by_name(n.attribute, "group").i - if group != 1: - warnings.warn( - "%s : Only group=1 is currently supported. Can't infer PixelPaddingDeconv." - % n.name - ) - continue weight_name = n.input[1] W_conv = model.get_initializer(weight_name) ifm_ch = model.get_tensor_shape(n.input[0])[1] # assume NCHW diff --git a/tests/fpgadataflow/test_fpgadataflow_deconv.py b/tests/fpgadataflow/test_fpgadataflow_deconv.py index d5edec9b35..6c25be0f85 100644 --- a/tests/fpgadataflow/test_fpgadataflow_deconv.py +++ b/tests/fpgadataflow/test_fpgadataflow_deconv.py @@ -28,6 +28,7 @@ import pytest +import numpy as np import os from onnx import TensorProto, helper from qonnx.core.datatype import DataType @@ -38,6 +39,7 @@ from qonnx.util.basic import gen_finn_dt_tensor, qonnx_make_model import finn.core.onnx_exec as oxe +from finn.analysis.fpgadataflow.exp_cycles_per_layer import exp_cycles_per_layer from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim from finn.transformation.fpgadataflow.convert_to_hls_layers import ( InferConvInpGen, @@ -177,14 +179,12 @@ def test_fpgadataflow_deconv(idim, stride, ifm_ch, ofm_ch, simd, pe, k, padding, expected_oshape = (1, ofm_ch, odim_h, odim_w) y_expected = oxe.execute_onnx(ref_model, input_dict)["outp"] + # cppsim if exec_mode == "cppsim": model = model.transform(PrepareCppSim()) model = model.transform(CompileCppSim()) model = model.transform(SetExecMode("cppsim")) - y_produced = oxe.execute_onnx(model, input_dict)["outp"] - assert y_produced.shape == expected_oshape - assert (y_produced == y_expected).all() # rtlsim else: @@ -192,6 +192,16 @@ def test_fpgadataflow_deconv(idim, stride, ifm_ch, ofm_ch, simd, pe, k, padding, model = model.transform(HLSSynthIP()) model = model.transform(PrepareRTLSim()) model = model.transform(SetExecMode("rtlsim")) - y_produced = oxe.execute_onnx(model, input_dict)["outp"] - assert y_produced.shape == expected_oshape - assert (y_produced == y_expected).all() + + y_produced = oxe.execute_onnx(model, input_dict)["outp"] + assert y_produced.shape == expected_oshape + assert (y_produced == y_expected).all() + + if exec_mode == "rtlsim": + node = model.get_nodes_by_op_type("FMPadding_Pixel")[0] + inst = getCustomOp(node) + cycles_rtlsim = inst.get_nodeattr("cycles_rtlsim") + exp_cycles_dict = model.analysis(exp_cycles_per_layer) + exp_cycles = exp_cycles_dict[node.name] + assert np.isclose(exp_cycles, cycles_rtlsim, atol=10) + assert exp_cycles != 0 From eddbd270806da2d8e4a6febd5d5be89e887267e3 Mon Sep 17 00:00:00 2001 From: Felix Jentzsch Date: Thu, 4 Jan 2024 08:52:17 +0100 Subject: [PATCH 366/665] [RTL SWG] Use sliced vector assignment to avoid Verilator limitation --- finn-rtllib/swg/swg_common.sv | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/finn-rtllib/swg/swg_common.sv b/finn-rtllib/swg/swg_common.sv index f2cdc333ca..c1d388550a 100644 --- a/finn-rtllib/swg/swg_common.sv +++ b/finn-rtllib/swg/swg_common.sv @@ -195,8 +195,7 @@ for (genvar e=0; e0; i--) - Data[i] <= Data[i-1]; + if (DEPTH > 1) Data[DEPTH-1:1] <= Data[DEPTH-2:0]; Data[0] <= shift_in; end end From 01c0ee550ca9659852f95a0c69da72d65d842bae Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 9 Jan 2024 09:54:26 +0000 Subject: [PATCH 367/665] [Issue template] Change link to get in touch with community --- .github/ISSUE_TEMPLATE/config.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/ISSUE_TEMPLATE/config.yml b/.github/ISSUE_TEMPLATE/config.yml index 57e3d54952..91433f3093 100644 --- a/.github/ISSUE_TEMPLATE/config.yml +++ b/.github/ISSUE_TEMPLATE/config.yml @@ -4,5 +4,5 @@ contact_links: url: https://finn.readthedocs.io/en/latest/getting_started.html about: Documentation about how to get up and running with FINN. - name: Ask for help and get in touch with the community - url: https://gitter.im/xilinx-finn/community - about: Check out our gitter channel, if you have a question about FINN or a general problem that is likely not a bug. + url: https://github.com/Xilinx/finn/discussions + about: Check out our GitHub Discussions, if you have a question about FINN or a general problem that is likely not a bug. From 4770a30a07e2fd3dc8ccbb43c81067d439454853 Mon Sep 17 00:00:00 2001 From: auphelia Date: Thu, 11 Jan 2024 14:06:40 +0000 Subject: [PATCH 368/665] [CustomOp] Initial draft of lookup in new class hierarchy --- src/finn/custom_op/fpgadataflow/__init__.py | 2 +- .../custom_op/fpgadataflow/hls/__init__.py | 2 + .../custom_op/fpgadataflow/hls/lookup_hls.py | 353 ++++++++++++++++++ src/finn/custom_op/fpgadataflow/lookup.py | 344 ++--------------- .../fpgadataflow/convert_to_hw_layers.py | 55 ++- .../fpgadataflow/test_fpgadataflow_lookup.py | 20 +- 6 files changed, 458 insertions(+), 318 deletions(-) create mode 100644 src/finn/custom_op/fpgadataflow/hls/lookup_hls.py diff --git a/src/finn/custom_op/fpgadataflow/__init__.py b/src/finn/custom_op/fpgadataflow/__init__.py index 68f565144f..bc9b9ae649 100644 --- a/src/finn/custom_op/fpgadataflow/__init__.py +++ b/src/finn/custom_op/fpgadataflow/__init__.py @@ -86,7 +86,6 @@ custom_op["VectorVectorActivation"] = VectorVectorActivation custom_op["IODMA"] = IODMA custom_op["StreamingDataflowPartition"] = StreamingDataflowPartition -custom_op["Lookup"] = Lookup custom_op["StreamingConcat"] = StreamingConcat custom_op["CheckSum"] = CheckSum @@ -96,6 +95,7 @@ custom_op["DuplicateStreams"] = DuplicateStreams custom_op["GlobalAccPool"] = GlobalAccPool custom_op["LabelSelect"] = LabelSelect +custom_op["Lookup"] = Lookup custom_op["StreamingEltwise"] = StreamingEltwise custom_op["StreamingMaxPool"] = StreamingMaxPool custom_op["UpsampleNearestNeighbour"] = UpsampleNearestNeighbour diff --git a/src/finn/custom_op/fpgadataflow/hls/__init__.py b/src/finn/custom_op/fpgadataflow/hls/__init__.py index df58decf81..38d28a66d6 100644 --- a/src/finn/custom_op/fpgadataflow/hls/__init__.py +++ b/src/finn/custom_op/fpgadataflow/hls/__init__.py @@ -32,6 +32,7 @@ from finn.custom_op.fpgadataflow.hls.fmpadding_hls import FMPadding_hls from finn.custom_op.fpgadataflow.hls.globalaccpool_hls import GlobalAccPool_hls from finn.custom_op.fpgadataflow.hls.labelselect_hls import LabelSelect_hls +from finn.custom_op.fpgadataflow.hls.lookup_hls import Lookup_hls from finn.custom_op.fpgadataflow.hls.streamingeltwise_hls import StreamingEltwise_hls from finn.custom_op.fpgadataflow.hls.streamingmaxpool_hls import StreamingMaxPool_hls from finn.custom_op.fpgadataflow.hls.upsampler_hls import UpsampleNearestNeighbour_hls @@ -46,6 +47,7 @@ custom_op["FMPadding_hls"] = FMPadding_hls custom_op["GlobalAccPool_hls"] = GlobalAccPool_hls custom_op["LabelSelect_hls"] = LabelSelect_hls +custom_op["Lookup_hls"] = Lookup_hls custom_op["StreamingEltwise_hls"] = StreamingEltwise_hls custom_op["StreamingMaxPool_hls"] = StreamingMaxPool_hls custom_op["UpsampleNearestNeighbour_hls"] = UpsampleNearestNeighbour_hls diff --git a/src/finn/custom_op/fpgadataflow/hls/lookup_hls.py b/src/finn/custom_op/fpgadataflow/hls/lookup_hls.py new file mode 100644 index 0000000000..885d3039a4 --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/hls/lookup_hls.py @@ -0,0 +1,353 @@ +# Copyright (C) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import numpy as np +import os +from math import ceil, log2 +from qonnx.core.datatype import DataType + +from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend +from finn.custom_op.fpgadataflow.lookup import Lookup +from finn.util.data_packing import ( + npy_to_rtlsim_input, + numpy_to_hls_code, + pack_innermost_dim_as_hex_string, + rtlsim_output_to_npy, +) + + +class Lookup_hls(Lookup, HLSBackend): + "Streaming elementwise HLS lookup, mapping indices to values." + + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) + + def get_nodeattr_types(self): + my_attrs = {} + my_attrs.update(Lookup.get_nodeattr_types(self)) + my_attrs.update(HLSBackend.get_nodeattr_types(self)) + return my_attrs + + def global_includes(self): + mem_mode = self.get_nodeattr("mem_mode") + global_incls = [] + global_incls.append('#include "lookup.hpp"') + if mem_mode == "const": + global_incls.append('#include "embeddings.hpp"') + self.code_gen_dict["$GLOBALS$"] = global_incls + + def defines(self, var): + n_inputs = np.prod(self.get_folded_input_shape()[:-1]) + dtype = self.get_input_datatype() + elem_hls_type = dtype.get_hls_datatype_str() + emb_type = DataType[self.get_nodeattr("EmbeddingType")] + emb_hls_type = emb_type.get_hls_datatype_str() + emb_dim = self.get_nodeattr("EmbeddingDim") + mem_mode = self.get_nodeattr("mem_mode") + my_defines = [] + my_defines.append("#define NumInputs %d" % n_inputs) + if mem_mode == "external": + ext_mem_width = self.get_nodeattr("ext_mem_width") + ext_mem_emb_size = self.get_folded_output_shape()[-2] + ext_mem_emb_align = ceil(log2(ext_mem_emb_size)) + my_defines.append("#define MemBits %d" % ext_mem_width) + my_defines.append("#define EmbeddingSize %d" % ext_mem_emb_size) + my_defines.append("#define EmbeddingAlign %d" % ext_mem_emb_align) + my_defines.append("#define T_SRC %s" % elem_hls_type) + my_defines.append("#define T_DST ap_uint") + elif mem_mode == "const": + my_defines.append("#define NumEmbeddings %d" % self.get_nodeattr("NumEmbeddings")) + my_defines.append("#define EmbeddingDim %d" % emb_dim) + my_defines.append("#define InputType %s" % elem_hls_type) + my_defines.append("#define EmbeddingType %s" % emb_hls_type) + self.code_gen_dict["$DEFINES$"] = my_defines + + def read_npy_data(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_input_datatype() + if dtype == DataType["BIPOLAR"]: + # use binary for bipolar storage + dtype = DataType["BINARY"] + elem_bits = dtype.bitwidth() + packed_bits = self.get_instream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "int64_t" + npy_in = "%s/input_0.npy" % code_gen_dir + self.code_gen_dict["$READNPYDATA$"] = [] + self.code_gen_dict["$READNPYDATA$"].append( + 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) + ) + + def dataoutstrm(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_output_datatype() + if dtype == DataType["BIPOLAR"]: + # use binary for bipolar storage + dtype = DataType["BINARY"] + elem_bits = dtype.bitwidth() + packed_bits = self.get_outstream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "float" + npy_out = "%s/output.npy" % code_gen_dir + oshape = self.get_folded_output_shape() + oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") + + self.code_gen_dict["$DATAOUTSTREAM$"] = [ + 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s", %s);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + self.hls_sname(), + oshape_cpp_str, + npy_out, + "false", + ) + ] + + def save_as_npy(self): + self.code_gen_dict["$SAVEASCNPY$"] = [] + + def strm_decl(self): + self.code_gen_dict["$STREAMDECLARATIONS$"] = [] + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> in0_{} ("in0_{}");'.format( + self.get_instream_width(), self.hls_sname(), self.hls_sname() + ) + ) + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> out_{} ("out_{}");'.format( + self.get_outstream_width(), self.hls_sname(), self.hls_sname() + ) + ) + + def docompute(self): + mem_mode = self.get_nodeattr("mem_mode") + if mem_mode == "const": + self.code_gen_dict["$DOCOMPUTE$"] = [ + """StreamingLookup(in0_%s, out_%s, embeddings);""" + % (self.hls_sname(), self.hls_sname()) + ] + elif mem_mode == "external": + self.code_gen_dict["$DOCOMPUTE$"] = [ + """StreamingLookup_ext(in0_%s, out_%s, mem, size, oob_count, + oob_irq);""" + % (self.hls_sname(), self.hls_sname()) + ] + + def blackboxfunction(self): + mem_mode = self.get_nodeattr("mem_mode") + ibits = self.get_instream_width() + packed_input_hls_type = "ap_uint<%d>" % ibits + obits = self.get_outstream_width() + packed_output_hls_type = "ap_uint<%d>" % obits + if mem_mode == "const": + self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ + "void %s(hls::stream<%s > &in0_%s, hls::stream<%s > &out_%s)" + % ( + self.onnx_node.name, + packed_input_hls_type, + self.hls_sname(), + packed_output_hls_type, + self.hls_sname(), + ) + ] + elif mem_mode == "external": + self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ + "void " + + self.onnx_node.name + + "(hls::stream &in0_%s, hls::stream &out_%s, " + % (self.hls_sname(), self.hls_sname()) + + "T_DST const *const mem, unsigned const size, " + + "unsigned &oob_count, bool &oob_irq)" + ] + + def pragmas(self): + mem_mode = self.get_nodeattr("mem_mode") + my_pragmas = ["#pragma HLS INTERFACE axis port=in0_" + self.hls_sname()] + my_pragmas.append("#pragma HLS INTERFACE axis port=out_" + self.hls_sname()) + my_pragmas.append("#pragma HLS INTERFACE ap_ctrl_none port=return") + if mem_mode == "const": + my_pragmas.append("#pragma HLS BIND_STORAGE variable=embeddings type=ROM_2P impl=BRAM") + elif mem_mode == "external": + my_pragmas.append("#pragma HLS INTERFACE m_axi offset=slave port=mem") + my_pragmas.append("#pragma HLS INTERFACE s_axilite port=mem bundle=control") + my_pragmas.append("#pragma HLS INTERFACE s_axilite port=size bundle=control") + my_pragmas.append("#pragma HLS INTERFACE s_axilite port=oob_count bundle=control") + my_pragmas.append("#pragma HLS INTERFACE ap_none port=oob_irq") + else: + raise Exception("Unrecognized mem_mode: " + mem_mode) + self.code_gen_dict["$PRAGMAS$"] = my_pragmas + + def generate_params(self, model, path): + mem_mode = self.get_nodeattr("mem_mode") + embeddings = model.get_initializer(self.onnx_node.input[1]) + if mem_mode == "const": + code_gen_dir = path + weight_filename = "{}/embeddings.hpp".format(code_gen_dir) + edt = DataType[self.get_nodeattr("EmbeddingType")] + # obits = self.get_outstream_width() + # packed_output_hls_type = "ap_uint<%d>" % obits + assert np.vectorize(edt.allowed)( + embeddings + ).all(), "Embeddings can't be expressed with type %s" % str(edt) + # reverse innertmost dim in embeddings to remain compatible with + # how we normally encode the data in FINN + embeddings_rev = np.flip(embeddings, -1) + embeddings_hls_code = numpy_to_hls_code(embeddings_rev, edt, "embeddings", True, False) + f_thresh = open(weight_filename, "w") + f_thresh.write(embeddings_hls_code) + f_thresh.close() + elif mem_mode == "external": + edt = DataType[self.get_nodeattr("EmbeddingType")] + ext_mem_width = self.get_nodeattr("ext_mem_width") + assert edt.bitwidth() == 8, ( + "Lookup with mem_mode=external " + + "only works with 8-bit embeddings but found " + + str(edt) + ) + emb_dim = self.get_nodeattr("EmbeddingDim") + # need to zero-pad embeddings in external mode for burst alignment + # compute how much padding we need + emb_elems_per_ext_mem_width = self.get_folded_output_shape()[-1] + ext_mem_emb_size = self.get_folded_output_shape()[-2] + ext_mem_emb_align = ceil(log2(ext_mem_emb_size)) + align_factor = int((ext_mem_width / 8) * 2**ext_mem_emb_align) + pad_amount = align_factor - emb_dim + embeddings_padded = np.pad(embeddings, [(0, 0), (0, pad_amount)]) + # reshape for packing the innermost dim + embeddings_padded = embeddings_padded.reshape(-1, emb_elems_per_ext_mem_width) + weight_filename = "%s/%s.dat" % (path, self.onnx_node.name) + ret = pack_innermost_dim_as_hex_string( + embeddings_padded, edt, ext_mem_width, True, prefix="" + ) + with open(weight_filename, "w") as f: + for current_line in ret: + f.write(current_line + "\n") + else: + raise Exception("Unrecognized mem_mode: " + mem_mode) + + def execute_node(self, context, graph): + mode = self.get_nodeattr("exec_mode") + node = self.onnx_node + exp_ishape = tuple(self.get_normal_input_shape()) + exp_oshape = tuple(self.get_normal_output_shape()) + folded_ishape = tuple(self.get_folded_input_shape()) + folded_oshape = tuple(self.get_folded_output_shape()) + mem_mode = self.get_nodeattr("mem_mode") + assert ( + mem_mode == "const" + ), "Only mem_mode=const is supported for simulation of Lookup layer" + + if mode == "cppsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + elif mode == "rtlsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + + inp = context[node.input[0]] + assert inp.dtype == np.int64, "Inputs must be contained in int64 ndarray" + assert inp.shape == exp_ishape, """Input shape doesn't match expected shape.""" + export_idt = self.get_input_datatype() + odt = self.get_output_datatype() + + reshaped_input = inp.reshape(folded_ishape) + np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input) + + if mode == "cppsim": + # execute the precompiled model + super().exec_precompiled_singlenode_model() + # load output npy file + super().npy_to_dynamic_output(context) + assert ( + context[node.output[0]].shape == folded_oshape + ), "cppsim did not produce expected folded output shape" + context[node.output[0]] = context[node.output[0]].reshape(*exp_oshape) + elif mode == "rtlsim": + sim = self.get_rtlsim() + nbits = self.get_instream_width() + rtlsim_inp = npy_to_rtlsim_input( + "{}/input_0.npy".format(code_gen_dir), export_idt, nbits + ) + super().reset_rtlsim(sim) + super().toggle_clk(sim) + rtlsim_output = self.rtlsim(sim, rtlsim_inp) + target_bits = odt.bitwidth() + packed_bits = self.get_outstream_width() + out_npy_path = "{}/output.npy".format(code_gen_dir) + out_shape = self.get_folded_output_shape() + rtlsim_output_to_npy( + rtlsim_output, + out_npy_path, + odt, + out_shape, + packed_bits, + target_bits, + reverse_inner=True, + ) + # load and reshape output + output = np.load(out_npy_path) + output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) + context[node.output[0]] = output + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + assert ( + context[node.output[0]].shape == exp_oshape + ), """Output shape doesn't match expected shape.""" + + def get_ap_int_max_w(self): + parent_max = super().get_ap_int_max_w() + mem_mode = self.get_nodeattr("mem_mode") + ext_mem_width = self.get_nodeattr("ext_mem_width") + if mem_mode == "external": + return max(ext_mem_width, parent_max) + else: + return parent_max diff --git a/src/finn/custom_op/fpgadataflow/lookup.py b/src/finn/custom_op/fpgadataflow/lookup.py index 2dfca90ed9..367bda1f07 100644 --- a/src/finn/custom_op/fpgadataflow/lookup.py +++ b/src/finn/custom_op/fpgadataflow/lookup.py @@ -1,4 +1,4 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2023, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -27,22 +27,19 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import numpy as np -import os +import onnxruntime as rt import warnings -from math import ceil, log2 +from math import ceil +from onnx import TensorProto, helper from qonnx.core.datatype import DataType +from qonnx.util.basic import qonnx_make_model -from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp -from finn.util.data_packing import ( - npy_to_rtlsim_input, - numpy_to_hls_code, - pack_innermost_dim_as_hex_string, - rtlsim_output_to_npy, -) +from finn.custom_op.fpgadataflow.hwcustomop import HWCustomOp -class Lookup(HLSCustomOp): - "Streaming elementwise HLS lookup, mapping indices to values." +class Lookup(HWCustomOp): + """Abstraction layer for HW implementation of streaming elementwise lookup, + mapping indices to values.""" def __init__(self, onnx_node, **kwargs): super().__init__(onnx_node, **kwargs) @@ -156,295 +153,37 @@ def get_number_output_values(self): folded_oshape = self.get_folded_output_shape() return np.prod(folded_oshape[:-1]) - def global_includes(self): - mem_mode = self.get_nodeattr("mem_mode") - global_incls = [] - global_incls.append('#include "lookup.hpp"') - if mem_mode == "const": - global_incls.append('#include "embeddings.hpp"') - self.code_gen_dict["$GLOBALS$"] = global_incls - - def defines(self, var): - n_inputs = np.prod(self.get_folded_input_shape()[:-1]) - dtype = self.get_input_datatype() - elem_hls_type = dtype.get_hls_datatype_str() - emb_type = DataType[self.get_nodeattr("EmbeddingType")] - emb_hls_type = emb_type.get_hls_datatype_str() - emb_dim = self.get_nodeattr("EmbeddingDim") - mem_mode = self.get_nodeattr("mem_mode") - my_defines = [] - my_defines.append("#define NumInputs %d" % n_inputs) - if mem_mode == "external": - ext_mem_width = self.get_nodeattr("ext_mem_width") - ext_mem_emb_size = self.get_folded_output_shape()[-2] - ext_mem_emb_align = ceil(log2(ext_mem_emb_size)) - my_defines.append("#define MemBits %d" % ext_mem_width) - my_defines.append("#define EmbeddingSize %d" % ext_mem_emb_size) - my_defines.append("#define EmbeddingAlign %d" % ext_mem_emb_align) - my_defines.append("#define T_SRC %s" % elem_hls_type) - my_defines.append("#define T_DST ap_uint") - elif mem_mode == "const": - my_defines.append("#define NumEmbeddings %d" % self.get_nodeattr("NumEmbeddings")) - my_defines.append("#define EmbeddingDim %d" % emb_dim) - my_defines.append("#define InputType %s" % elem_hls_type) - my_defines.append("#define EmbeddingType %s" % emb_hls_type) - self.code_gen_dict["$DEFINES$"] = my_defines - - def read_npy_data(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_input_datatype() - if dtype == DataType["BIPOLAR"]: - # use binary for bipolar storage - dtype = DataType["BINARY"] - elem_bits = dtype.bitwidth() - packed_bits = self.get_instream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "int64_t" - npy_in = "%s/input_0.npy" % code_gen_dir - self.code_gen_dict["$READNPYDATA$"] = [] - self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - npy_in, - self.hls_sname(), - ) - ) - - def dataoutstrm(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_output_datatype() - if dtype == DataType["BIPOLAR"]: - # use binary for bipolar storage - dtype = DataType["BINARY"] - elem_bits = dtype.bitwidth() - packed_bits = self.get_outstream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_out = "%s/output.npy" % code_gen_dir - oshape = self.get_folded_output_shape() - oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") - - self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s", %s);' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - self.hls_sname(), - oshape_cpp_str, - npy_out, - "false", - ) - ] - - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - - def strm_decl(self): - self.code_gen_dict["$STREAMDECLARATIONS$"] = [] - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0_{} ("in0_{}");'.format( - self.get_instream_width(), self.hls_sname(), self.hls_sname() - ) - ) - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out_{} ("out_{}");'.format( - self.get_outstream_width(), self.hls_sname(), self.hls_sname() - ) - ) - - def docompute(self): - mem_mode = self.get_nodeattr("mem_mode") - if mem_mode == "const": - self.code_gen_dict["$DOCOMPUTE$"] = [ - """StreamingLookup(in0_%s, out_%s, embeddings);""" - % (self.hls_sname(), self.hls_sname()) - ] - elif mem_mode == "external": - self.code_gen_dict["$DOCOMPUTE$"] = [ - """StreamingLookup_ext(in0_%s, out_%s, mem, size, oob_count, - oob_irq);""" - % (self.hls_sname(), self.hls_sname()) - ] - - def blackboxfunction(self): - mem_mode = self.get_nodeattr("mem_mode") - ibits = self.get_instream_width() - packed_input_hls_type = "ap_uint<%d>" % ibits - obits = self.get_outstream_width() - packed_output_hls_type = "ap_uint<%d>" % obits - if mem_mode == "const": - self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - "void %s(hls::stream<%s > &in0_%s, hls::stream<%s > &out_%s)" - % ( - self.onnx_node.name, - packed_input_hls_type, - self.hls_sname(), - packed_output_hls_type, - self.hls_sname(), - ) - ] - elif mem_mode == "external": - self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - "void " - + self.onnx_node.name - + "(hls::stream &in0_%s, hls::stream &out_%s, " - % (self.hls_sname(), self.hls_sname()) - + "T_DST const *const mem, unsigned const size, " - + "unsigned &oob_count, bool &oob_irq)" - ] - - def pragmas(self): - mem_mode = self.get_nodeattr("mem_mode") - my_pragmas = ["#pragma HLS INTERFACE axis port=in0_" + self.hls_sname()] - my_pragmas.append("#pragma HLS INTERFACE axis port=out_" + self.hls_sname()) - my_pragmas.append("#pragma HLS INTERFACE ap_ctrl_none port=return") - if mem_mode == "const": - my_pragmas.append("#pragma HLS BIND_STORAGE variable=embeddings type=ROM_2P impl=BRAM") - elif mem_mode == "external": - my_pragmas.append("#pragma HLS INTERFACE m_axi offset=slave port=mem") - my_pragmas.append("#pragma HLS INTERFACE s_axilite port=mem bundle=control") - my_pragmas.append("#pragma HLS INTERFACE s_axilite port=size bundle=control") - my_pragmas.append("#pragma HLS INTERFACE s_axilite port=oob_count bundle=control") - my_pragmas.append("#pragma HLS INTERFACE ap_none port=oob_irq") - else: - raise Exception("Unrecognized mem_mode: " + mem_mode) - self.code_gen_dict["$PRAGMAS$"] = my_pragmas - - def generate_params(self, model, path): - mem_mode = self.get_nodeattr("mem_mode") - embeddings = model.get_initializer(self.onnx_node.input[1]) - if mem_mode == "const": - code_gen_dir = path - weight_filename = "{}/embeddings.hpp".format(code_gen_dir) - edt = DataType[self.get_nodeattr("EmbeddingType")] - # obits = self.get_outstream_width() - # packed_output_hls_type = "ap_uint<%d>" % obits - assert np.vectorize(edt.allowed)( - embeddings - ).all(), "Embeddings can't be expressed with type %s" % str(edt) - # reverse innertmost dim in embeddings to remain compatible with - # how we normally encode the data in FINN - embeddings_rev = np.flip(embeddings, -1) - embeddings_hls_code = numpy_to_hls_code(embeddings_rev, edt, "embeddings", True, False) - f_thresh = open(weight_filename, "w") - f_thresh.write(embeddings_hls_code) - f_thresh.close() - elif mem_mode == "external": - edt = DataType[self.get_nodeattr("EmbeddingType")] - ext_mem_width = self.get_nodeattr("ext_mem_width") - assert edt.bitwidth() == 8, ( - "Lookup with mem_mode=external " - + "only works with 8-bit embeddings but found " - + str(edt) - ) - emb_dim = self.get_nodeattr("EmbeddingDim") - # need to zero-pad embeddings in external mode for burst alignment - # compute how much padding we need - emb_elems_per_ext_mem_width = self.get_folded_output_shape()[-1] - ext_mem_emb_size = self.get_folded_output_shape()[-2] - ext_mem_emb_align = ceil(log2(ext_mem_emb_size)) - align_factor = int((ext_mem_width / 8) * 2**ext_mem_emb_align) - pad_amount = align_factor - emb_dim - embeddings_padded = np.pad(embeddings, [(0, 0), (0, pad_amount)]) - # reshape for packing the innermost dim - embeddings_padded = embeddings_padded.reshape(-1, emb_elems_per_ext_mem_width) - weight_filename = "%s/%s.dat" % (path, self.onnx_node.name) - ret = pack_innermost_dim_as_hex_string( - embeddings_padded, edt, ext_mem_width, True, prefix="" - ) - with open(weight_filename, "w") as f: - for current_line in ret: - f.write(current_line + "\n") - else: - raise Exception("Unrecognized mem_mode: " + mem_mode) - def execute_node(self, context, graph): - mode = self.get_nodeattr("exec_mode") + # create a standard add node to help calculate the result node = self.onnx_node - exp_ishape = tuple(self.get_normal_input_shape()) - exp_oshape = tuple(self.get_normal_output_shape()) - folded_ishape = tuple(self.get_folded_input_shape()) - folded_oshape = tuple(self.get_folded_output_shape()) - mem_mode = self.get_nodeattr("mem_mode") - assert ( - mem_mode == "const" - ), "Only mem_mode=const is supported for simulation of Lookup layer" - - if mode == "cppsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - elif mode == "rtlsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) - - inp = context[node.input[0]] - assert inp.dtype == np.int64, "Inputs must be contained in int64 ndarray" - assert inp.shape == exp_ishape, """Input shape doesn't match expected shape.""" - export_idt = self.get_input_datatype() - odt = self.get_output_datatype() + inp_values = context[node.input[0]] + ishape = inp_values.shape + data_values = context[node.input[1]] + dshape = data_values.shape + oshape = context[node.output[0]].shape + inp = helper.make_tensor_value_info(node.input[0], TensorProto.INT64, ishape) + data = helper.make_tensor_value_info(node.input[1], TensorProto.FLOAT, dshape) + outp = helper.make_tensor_value_info(node.output[0], TensorProto.FLOAT, oshape) + node_gather = helper.make_node( + "Gather", + inputs=[node.input[1], node.input[0]], + outputs=[node.output[0]], + ) + graph_gather = helper.make_graph( + nodes=[node_gather], + name="single-gather-exec", + inputs=[data, inp], + outputs=[outp], + ) - reshaped_input = inp.reshape(folded_ishape) - np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input) - - if mode == "cppsim": - # execute the precompiled model - super().exec_precompiled_singlenode_model() - # load output npy file - super().npy_to_dynamic_output(context) - assert ( - context[node.output[0]].shape == folded_oshape - ), "cppsim did not produce expected folded output shape" - context[node.output[0]] = context[node.output[0]].reshape(*exp_oshape) - elif mode == "rtlsim": - sim = self.get_rtlsim() - nbits = self.get_instream_width() - rtlsim_inp = npy_to_rtlsim_input( - "{}/input_0.npy".format(code_gen_dir), export_idt, nbits - ) - super().reset_rtlsim(sim) - super().toggle_clk(sim) - rtlsim_output = self.rtlsim(sim, rtlsim_inp) - target_bits = odt.bitwidth() - packed_bits = self.get_outstream_width() - out_npy_path = "{}/output.npy".format(code_gen_dir) - out_shape = self.get_folded_output_shape() - rtlsim_output_to_npy( - rtlsim_output, - out_npy_path, - odt, - out_shape, - packed_bits, - target_bits, - reverse_inner=True, - ) - # load and reshape output - output = np.load(out_npy_path) - output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) - context[node.output[0]] = output - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) - assert ( - context[node.output[0]].shape == exp_oshape - ), """Output shape doesn't match expected shape.""" + opset_version = 13 + opset_imports = [helper.make_opsetid("", opset_version)] + onnx_kwargs = {"opset_imports": opset_imports} + model_gather = qonnx_make_model(graph_gather, **onnx_kwargs) + idict = {node.input[0]: inp_values, node.input[1]: data_values} + sess = rt.InferenceSession(model_gather.SerializeToString()) + result = sess.run(None, idict) + context[node.output[0]] = np.asarray(result, dtype=np.float32).reshape(oshape) def bram_estimation(self): mem_mode = self.get_nodeattr("mem_mode") @@ -466,15 +205,6 @@ def bram_efficiency_estimation(self): bram16_est_capacity = bram16_est * 18 * 1024 return ebits / bram16_est_capacity - def get_ap_int_max_w(self): - parent_max = super().get_ap_int_max_w() - mem_mode = self.get_nodeattr("mem_mode") - ext_mem_width = self.get_nodeattr("ext_mem_width") - if mem_mode == "external": - return max(ext_mem_width, parent_max) - else: - return parent_max - def get_verilog_top_module_intf_names(self): intf_names = super().get_verilog_top_module_intf_names() mem_mode = self.get_nodeattr("mem_mode") diff --git a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py index 11bd3406d5..16ed2cfd9a 100644 --- a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py +++ b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py @@ -1,4 +1,4 @@ -# Copyright (C) 2023, Advanced Micro Devices, Inc. +# Copyright (C) 2023-2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -664,6 +664,59 @@ def apply(self, model): return (model, graph_modified) +class InferLookupLayer(Transformation): + """Convert Gather nodes with constant op0 into Lookup HW layers.""" + + def apply(self, model): + graph = model.graph + node_ind = 0 + graph_modified = False + for node in graph.node: + node_ind += 1 + if node.op_type == "Gather": + emb_name = node.input[0] + embs = model.get_initializer(emb_name) + axis = get_by_name(node.attribute, "axis") + # skip conversion if input0 is not constant + if embs is None: + continue + # skip conversion if axis != 0 + if axis is not None and axis.i != 0: + continue + ind_name = node.input[1] + ind_dtype = model.get_tensor_datatype(ind_name) + emb_dtype = model.get_tensor_datatype(emb_name) + # skip conversion if inputs are not unsigned integers + if (not ind_dtype.is_integer()) or ind_dtype.signed(): + continue + num_embs, emb_dim = embs.shape + out_name = node.output[0] + ishape = model.get_tensor_shape(node.input[1]) + # create and insert new Lookup node + new_node = helper.make_node( + "Lookup", + [ind_name, emb_name], + [out_name], + domain="finn.custom_op.fpgadataflow", + backend="fpgadataflow", + name="Lookup_" + node.name, + NumEmbeddings=num_embs, + EmbeddingDim=emb_dim, + EmbeddingType=emb_dtype.name, + InputType=ind_dtype.name, + InputShape=list(ishape), + ) + graph.node.insert(node_ind, new_node) + # remove old node + graph.node.remove(node) + graph_modified = True + + if graph_modified: + model = model.transform(InferShapes()) + model = model.transform(InferDataTypes()) + return (model, graph_modified) + + class InferStreamingEltwise(Transformation): """Convert eltwise Sub or Sub -> Abs to StreamingEltwise layer with SubEltwise or AbsDiffEltwise op.""" diff --git a/tests/fpgadataflow/test_fpgadataflow_lookup.py b/tests/fpgadataflow/test_fpgadataflow_lookup.py index d2861261b6..cb15fa3ae5 100644 --- a/tests/fpgadataflow/test_fpgadataflow_lookup.py +++ b/tests/fpgadataflow/test_fpgadataflow_lookup.py @@ -1,5 +1,5 @@ # Copyright (C) 2021-2022, Xilinx, Inc. -# Copyright (C) 2023, Advanced Micro Devices, Inc. +# Copyright (C) 2023-2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -44,13 +44,14 @@ from finn.core.onnx_exec import execute_onnx from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim -from finn.transformation.fpgadataflow.convert_to_hls_layers import InferLookupLayer +from finn.transformation.fpgadataflow.convert_to_hw_layers import InferLookupLayer from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers from finn.transformation.qonnx.convert_qonnx_to_finn import ConvertQONNXtoFINN export_onnx_path = "test_lookup.onnx" @@ -121,12 +122,17 @@ def test_fpgadataflow_lookup(edt, embedding_cfg, exec_mode): ret = execute_onnx(model, {iname: itensor}) exp_out = np.take(embeddings, itensor, axis=0) assert (exp_out == ret[oname]).all() - # call transformation to convert to HLS and verify conversion + # call transformation to convert to HW layer and verify conversion model = model.transform(InferLookupLayer()) assert model.graph.node[0].op_type == "Lookup" assert model.graph.node[0].input[0] == iname assert model.graph.node[0].input[1] == ename assert model.graph.node[0].output[0] == oname + ret_hw = execute_onnx(model, {iname: itensor}) + assert (exp_out == ret_hw[oname]).all() + # call transformation to convert abstraction layer into HLS layer + model = model.transform(SpecializeLayers()) + assert model.graph.node[0].op_type == "Lookup_hls" if exec_mode == "cppsim": model = model.transform(GiveUniqueNodeNames()) model = model.transform(PrepareCppSim()) @@ -166,14 +172,10 @@ def test_fpgadataflow_lookup_external(): assert tuple(model.get_tensor_shape(ename)) == eshape assert tuple(model.get_tensor_shape(oname)) == exp_oshape assert (model.get_initializer(ename) == embeddings).all() - # itensor = gen_finn_dt_tensor(idt, ishape).astype(np.int64) - # itensor = np.clip(itensor, 0, num_embeddings - 1) - # ret = execute_onnx(model, {iname: itensor}) - # exp_out = np.take(embeddings, itensor, axis=0) - # assert (exp_out == ret[oname]).all() - # call transformation to convert to HLS and verify conversion model = model.transform(InferLookupLayer()) assert model.graph.node[0].op_type == "Lookup" + model = model.transform(SpecializeLayers()) + assert model.graph.node[0].op_type == "Lookup_hls" assert model.graph.node[0].input[0] == iname assert model.graph.node[0].input[1] == ename assert model.graph.node[0].output[0] == oname From 68e1442361583b394166c3da60aef938806a7038 Mon Sep 17 00:00:00 2001 From: auphelia Date: Thu, 11 Jan 2024 14:10:55 +0000 Subject: [PATCH 369/665] Delete old upsampler custom op and fix typo in comment --- src/finn/custom_op/fpgadataflow/upsampler.py | 2 +- .../custom_op/fpgadataflow/upsampler_batch.py | 351 ------------------ 2 files changed, 1 insertion(+), 352 deletions(-) delete mode 100644 src/finn/custom_op/fpgadataflow/upsampler_batch.py diff --git a/src/finn/custom_op/fpgadataflow/upsampler.py b/src/finn/custom_op/fpgadataflow/upsampler.py index b0264ffa8a..3348394e05 100644 --- a/src/finn/custom_op/fpgadataflow/upsampler.py +++ b/src/finn/custom_op/fpgadataflow/upsampler.py @@ -149,7 +149,7 @@ def get_number_output_values(self): return np.prod(folded_oshape[:-1]) def execute_node(self, context, graph): - # create a standard add node to help calculate the result + # create a standard resize node to help calculate the result node = self.onnx_node inp_values = context[node.input[0]] ishape = inp_values.shape diff --git a/src/finn/custom_op/fpgadataflow/upsampler_batch.py b/src/finn/custom_op/fpgadataflow/upsampler_batch.py deleted file mode 100644 index 9c0db1f3df..0000000000 --- a/src/finn/custom_op/fpgadataflow/upsampler_batch.py +++ /dev/null @@ -1,351 +0,0 @@ -# Copyright (c) 2020, Xilinx -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# * Redistributions of source code must retain the above copyright notice, this -# list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# * Neither the name of FINN nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -import numpy as np -import warnings -from qonnx.core.datatype import DataType - -from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp -from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy - - -class UpsampleNearestNeighbour_Batch(HLSCustomOp): - """ - Corresponds to finn-hlslib UpsampleNearestNeighbour_Batch function. - Upsampling is done with the Nearest Neighbour algorithm. - The layer expects square feature maps for the in and output. - """ - - def __init__(self, onnx_node, **kwargs): - super().__init__(onnx_node, **kwargs) - - def get_nodeattr_types(self): - my_attrs = { - # Size of the output feature map - "OFMDim": ("i", True, 0), - # Size of the input feature map - "IFMDim": ("i", True, 0), - # Amount of channels of the input feature map - "NumChannels": ("i", True, 0), - # FINN input datatype - "inputDataType": ("s", True, ""), - # Batch size - "numInputVectors": ("i", False, 1), - # Dimensionality mode: 0 = 2D square, 1 = 1D in H dim - "DimMode": ("i", False, 0), - } - my_attrs.update(super().get_nodeattr_types()) - return my_attrs - - def get_exp_cycles(self): - OFMDim = self.get_nodeattr("OFMDim") - batch_size = self.get_nodeattr("numInputVectors") - is_2d = self.get_nodeattr("DimMode") == 0 - reps = 1 - if is_2d: - OFMDim = OFMDim * OFMDim - reps = batch_size - exp_cycles = OFMDim * reps - return int(exp_cycles) - - def get_normal_input_shape(self, ind=0): - IFMDim = self.get_nodeattr("IFMDim") - num_ch = self.get_nodeattr("NumChannels") - batch = self.get_nodeattr("numInputVectors") - is_2d = self.get_nodeattr("DimMode") == 0 - if is_2d: - ishape = (batch, IFMDim, IFMDim, num_ch) - else: - ishape = (batch, IFMDim, 1, num_ch) - return ishape - - def get_normal_output_shape(self, ind=0): - OFMDim = self.get_nodeattr("OFMDim") - num_ch = self.get_nodeattr("NumChannels") - batch = self.get_nodeattr("numInputVectors") - is_2d = self.get_nodeattr("DimMode") == 0 - if is_2d: - oshape = (batch, OFMDim, OFMDim, num_ch) - else: - oshape = (batch, OFMDim, 1, num_ch) - return oshape - - def get_folded_input_shape(self, ind=0): - normal_ishape = list(self.get_normal_input_shape()) - return tuple(normal_ishape) - - def get_folded_output_shape(self, ind=0): - normal_oshape = list(self.get_normal_output_shape()) - return tuple(normal_oshape) - - def make_shape_compatible_op(self, model): - exp_ishape = self.get_normal_input_shape() - oshape = self.get_normal_output_shape() - ishape = tuple(model.get_tensor_shape(self.onnx_node.input[0])) - assert ishape == exp_ishape, "Unexpect input shape for UpsampleNearestNeighbour_Batch." - return super().make_const_shape_op(oshape) - - def infer_node_datatype(self, model): - node = self.onnx_node - # data type stays the same - idt = model.get_tensor_datatype(node.input[0]) - if idt != self.get_input_datatype(): - warn_str = "inputDataType changing for %s: %s -> %s " % ( - node.name, - str(self.get_input_datatype()), - str(idt), - ) - warnings.warn(warn_str) - self.set_nodeattr("inputDataType", idt.name) - model.set_tensor_datatype(node.output[0], idt) - - def verify_node(self): - pass - - def get_input_datatype(self, ind=0): - """Returns FINN DataType of input.""" - ret = DataType[self.get_nodeattr("inputDataType")] - return ret - - def get_output_datatype(self, ind=0): - """Returns FINN DataType of output. (Same as input datatype)""" - return self.get_input_datatype() - - def get_instream_width(self, ind=0): - ibits = self.get_input_datatype().bitwidth() - ifm_ch = self.get_nodeattr("NumChannels") - return ibits * ifm_ch - - def get_outstream_width(self, ind=0): - obits = self.get_output_datatype().bitwidth() - ifm_ch = self.get_nodeattr("NumChannels") - return obits * ifm_ch - - def get_number_output_values(self): - folded_oshape = self.get_folded_output_shape() - return np.prod(folded_oshape[:-1]) - - def global_includes(self): - self.code_gen_dict["$GLOBALS$"] = ['#include "upsample.hpp"'] - - def defines(self, var): - self.code_gen_dict["$DEFINES$"] = [] - - ifm_ch = self.get_nodeattr("NumChannels") - self.code_gen_dict["$DEFINES$"] += ["#define IFMChannels {}".format(ifm_ch)] - - ibits = self.get_input_datatype().bitwidth() - self.code_gen_dict["$DEFINES$"] += ["#define Input_precision {}".format(ibits)] - - idim = self.get_nodeattr("IFMDim") - self.code_gen_dict["$DEFINES$"] += ["#define IFMDim {}".format(idim)] - - odim = self.get_nodeattr("OFMDim") - self.code_gen_dict["$DEFINES$"] += ["#define OFMDim {}".format(odim)] - - batch_size = self.get_nodeattr("numInputVectors") - self.code_gen_dict["$DEFINES$"] += ["#define numReps {}".format(batch_size)] - - def read_npy_data(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_input_datatype() - if dtype == DataType["BIPOLAR"]: - # use binary for bipolar storage - dtype = DataType["BINARY"] - elem_bits = dtype.bitwidth() - packed_bits = self.get_instream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_in = "%s/input_0.npy" % code_gen_dir - self.code_gen_dict["$READNPYDATA$"] = [] - self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - npy_in, - self.hls_sname(), - ) - ) - - def strm_decl(self): - self.code_gen_dict["$STREAMDECLARATIONS$"] = [] - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0_{} ("in0_{}");'.format( - self.get_instream_width(), self.hls_sname(), self.hls_sname() - ) - ) - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out_{} ("out_{}");'.format( - self.get_outstream_width(), self.hls_sname(), self.hls_sname() - ) - ) - - def docompute(self): - is_2d = self.get_nodeattr("DimMode") == 0 - batch = self.get_nodeattr("numInputVectors") - if is_2d: - self.code_gen_dict["$DOCOMPUTE$"] = [ - """UpsampleNearestNeighbour_Batch > (in0_%s, out_%s, numReps);""" - % (self.hls_sname(), self.hls_sname()) - ] - else: - assert batch == 1, "1D upsampler currently needs numReps=1" - self.code_gen_dict["$DOCOMPUTE$"] = [ - """UpsampleNearestNeighbour_1D > (in0_%s, out_%s);""" - % (self.hls_sname(), self.hls_sname()) - ] - - def dataoutstrm(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_output_datatype() - if dtype == DataType["BIPOLAR"]: - # use binary for bipolar storage - dtype = DataType["BINARY"] - elem_bits = dtype.bitwidth() - packed_bits = self.get_outstream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_out = "%s/output.npy" % code_gen_dir - oshape = self.get_folded_output_shape() - oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") - - self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - self.hls_sname(), - oshape_cpp_str, - npy_out, - ) - ] - - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - - def blackboxfunction(self): - packed_bits = self.get_instream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - "void %s(hls::stream<%s > &in0_%s, hls::stream<%s > &out_%s)" - % ( - self.onnx_node.name, - packed_hls_type, - self.hls_sname(), - packed_hls_type, - self.hls_sname(), - ) - ] - - def pragmas(self): - self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() - ] - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() - ) - self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") - - def execute_node(self, context, graph): - mode = self.get_nodeattr("exec_mode") - node = self.onnx_node - exp_ishape = self.get_normal_input_shape() - exp_oshape = self.get_normal_output_shape() - folded_oshape = self.get_folded_output_shape() - - if mode == "cppsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - elif mode == "rtlsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) - - inp = context[node.input[0]] - assert str(inp.dtype) == "float32", "Input datatype is not float32" - assert ( - inp.shape == exp_ishape - ), """Input shape doesn't - match expected shape (numInputVectors, ImgDim, ImgDim, NumChannels).""" - export_idt = self.get_input_datatype() - self.dynamic_input_to_npy(context, 1, target_dir=code_gen_dir) - - if mode == "cppsim": - # execute the precompiled model - super().exec_precompiled_singlenode_model() - # load output npy file - super().npy_to_dynamic_output(context) - assert ( - context[node.output[0]].shape == folded_oshape - ), "cppsim did not produce expected folded output shape" - context[node.output[0]] = context[node.output[0]].reshape(*exp_oshape) - elif mode == "rtlsim": - sim = self.get_rtlsim() - nbits = self.get_instream_width() - rtlsim_inp = npy_to_rtlsim_input( - "{}/input_0.npy".format(code_gen_dir), export_idt, nbits - ) - super().reset_rtlsim(sim) - super().toggle_clk(sim) - rtlsim_output = self.rtlsim(sim, rtlsim_inp) - odt = export_idt - target_bits = odt.bitwidth() - packed_bits = self.get_outstream_width() - out_npy_path = "{}/output.npy".format(code_gen_dir) - out_shape = self.get_folded_output_shape() - rtlsim_output_to_npy( - rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits - ) - # load and reshape output - output = np.load(out_npy_path) - output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) - context[node.output[0]] = output - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) - assert ( - context[node.output[0]].shape == exp_oshape - ), """Output shape doesn't match expected shape - (1, OutputDim, OutputDim, NumChannels).""" From 9674cba6c3d5f3c0292e121e0e9d8957b65316a2 Mon Sep 17 00:00:00 2001 From: auphelia Date: Thu, 11 Jan 2024 14:15:15 +0000 Subject: [PATCH 370/665] [Tests] Temporarily marking hls conversion tests as xfail --- tests/end2end/test_end2end_mobilenet_v1.py | 1 + tests/transformation/test_infer_data_layouts_cnv.py | 1 + 2 files changed, 2 insertions(+) diff --git a/tests/end2end/test_end2end_mobilenet_v1.py b/tests/end2end/test_end2end_mobilenet_v1.py index 2d25a2bf0d..512558eb09 100644 --- a/tests/end2end/test_end2end_mobilenet_v1.py +++ b/tests/end2end/test_end2end_mobilenet_v1.py @@ -211,6 +211,7 @@ def test_end2end_mobilenet_lowering(): @pytest.mark.end2end +@pytest.mark.xfail def test_end2end_mobilenet_convert_to_hls_layers(): model = load_test_checkpoint_or_skip(build_dir + "/end2end_mobilenet_lowered.onnx") model = model.transform(to_hls.InferPool_Batch()) diff --git a/tests/transformation/test_infer_data_layouts_cnv.py b/tests/transformation/test_infer_data_layouts_cnv.py index 25bf890271..2d7fc54f94 100644 --- a/tests/transformation/test_infer_data_layouts_cnv.py +++ b/tests/transformation/test_infer_data_layouts_cnv.py @@ -56,6 +56,7 @@ @pytest.mark.transform +@pytest.mark.xfail def test_infer_data_layouts_cnv(): cnv = get_test_model_trained("CNV", 1, 1) export_qonnx(cnv, torch.randn(1, 3, 32, 32), export_onnx_path_cnv) From d9819a24d4289bebb6ae61bda7ed3899c44ab0f8 Mon Sep 17 00:00:00 2001 From: auphelia Date: Thu, 11 Jan 2024 16:27:21 +0000 Subject: [PATCH 371/665] [CustomOp] Initial draft of dwc in new class hierarchy --- src/finn/custom_op/fpgadataflow/__init__.py | 12 +- .../custom_op/fpgadataflow/hls/__init__.py | 4 + .../hls/streamingdatawidthconverter_hls.py | 271 +++++++++ .../custom_op/fpgadataflow/rtl/__init__.py | 4 + .../streamingdatawidthconverter_rtl.py | 157 +---- .../streamingdatawidthconverter.py | 216 +++++++ .../streamingdatawidthconverter_batch.py | 540 ------------------ .../transformation/fpgadataflow/floorplan.py | 2 +- .../transformation/fpgadataflow/insert_dwc.py | 60 +- .../fpgadataflow/specialize_layers.py | 30 + tests/fpgadataflow/test_fpgadataflow_dwc.py | 108 +++- 11 files changed, 648 insertions(+), 756 deletions(-) create mode 100644 src/finn/custom_op/fpgadataflow/hls/streamingdatawidthconverter_hls.py rename src/finn/custom_op/fpgadataflow/{ => rtl}/streamingdatawidthconverter_rtl.py (63%) create mode 100644 src/finn/custom_op/fpgadataflow/streamingdatawidthconverter.py delete mode 100644 src/finn/custom_op/fpgadataflow/streamingdatawidthconverter_batch.py diff --git a/src/finn/custom_op/fpgadataflow/__init__.py b/src/finn/custom_op/fpgadataflow/__init__.py index bc9b9ae649..e4b645bbc2 100644 --- a/src/finn/custom_op/fpgadataflow/__init__.py +++ b/src/finn/custom_op/fpgadataflow/__init__.py @@ -1,5 +1,5 @@ # Copyright (C) 2020-2022, Xilinx, Inc. -# Copyright (C) 2023, Advanced Micro Devices, Inc. +# Copyright (C) 2023-2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -53,11 +53,8 @@ from finn.custom_op.fpgadataflow.streamingdataflowpartition import ( StreamingDataflowPartition, ) -from finn.custom_op.fpgadataflow.streamingdatawidthconverter_batch import ( - StreamingDataWidthConverter_Batch, -) -from finn.custom_op.fpgadataflow.streamingdatawidthconverter_rtl import ( - StreamingDataWidthConverter_rtl, +from finn.custom_op.fpgadataflow.streamingdatawidthconverter import ( + StreamingDataWidthConverter, ) from finn.custom_op.fpgadataflow.streamingeltwise import StreamingEltwise from finn.custom_op.fpgadataflow.streamingfifo import StreamingFIFO @@ -77,8 +74,6 @@ custom_op["ConvolutionInputGenerator1D"] = ConvolutionInputGenerator1D custom_op["ConvolutionInputGenerator_rtl"] = ConvolutionInputGenerator_rtl custom_op["TLastMarker"] = TLastMarker -custom_op["StreamingDataWidthConverter_Batch"] = StreamingDataWidthConverter_Batch -custom_op["StreamingDataWidthConverter_rtl"] = StreamingDataWidthConverter_rtl custom_op["StreamingFIFO"] = StreamingFIFO custom_op["Pool_Batch"] = Pool_Batch custom_op["FMPadding_Pixel"] = FMPadding_Pixel @@ -96,6 +91,7 @@ custom_op["GlobalAccPool"] = GlobalAccPool custom_op["LabelSelect"] = LabelSelect custom_op["Lookup"] = Lookup +custom_op["StreamingDataWidthConverter"] = StreamingDataWidthConverter custom_op["StreamingEltwise"] = StreamingEltwise custom_op["StreamingMaxPool"] = StreamingMaxPool custom_op["UpsampleNearestNeighbour"] = UpsampleNearestNeighbour diff --git a/src/finn/custom_op/fpgadataflow/hls/__init__.py b/src/finn/custom_op/fpgadataflow/hls/__init__.py index 38d28a66d6..1803b00023 100644 --- a/src/finn/custom_op/fpgadataflow/hls/__init__.py +++ b/src/finn/custom_op/fpgadataflow/hls/__init__.py @@ -33,6 +33,9 @@ from finn.custom_op.fpgadataflow.hls.globalaccpool_hls import GlobalAccPool_hls from finn.custom_op.fpgadataflow.hls.labelselect_hls import LabelSelect_hls from finn.custom_op.fpgadataflow.hls.lookup_hls import Lookup_hls +from finn.custom_op.fpgadataflow.hls.streamingdatawidthconverter_hls import ( + StreamingDataWidthConverter_hls, +) from finn.custom_op.fpgadataflow.hls.streamingeltwise_hls import StreamingEltwise_hls from finn.custom_op.fpgadataflow.hls.streamingmaxpool_hls import StreamingMaxPool_hls from finn.custom_op.fpgadataflow.hls.upsampler_hls import UpsampleNearestNeighbour_hls @@ -49,5 +52,6 @@ custom_op["LabelSelect_hls"] = LabelSelect_hls custom_op["Lookup_hls"] = Lookup_hls custom_op["StreamingEltwise_hls"] = StreamingEltwise_hls +custom_op["StreamingDataWidthConverter_hls"] = StreamingDataWidthConverter_hls custom_op["StreamingMaxPool_hls"] = StreamingMaxPool_hls custom_op["UpsampleNearestNeighbour_hls"] = UpsampleNearestNeighbour_hls diff --git a/src/finn/custom_op/fpgadataflow/hls/streamingdatawidthconverter_hls.py b/src/finn/custom_op/fpgadataflow/hls/streamingdatawidthconverter_hls.py new file mode 100644 index 0000000000..be096e63c7 --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/hls/streamingdatawidthconverter_hls.py @@ -0,0 +1,271 @@ +# Copyright (C) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import numpy as np +import os +from qonnx.core.datatype import DataType + +from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend +from finn.custom_op.fpgadataflow.streamingdatawidthconverter import ( + StreamingDataWidthConverter, +) +from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy + +# does not do anything at the ONNX node-by-node level, and input-output +# tensor shapes are the same. performs data width conversion at the rtlsim level + + +class StreamingDataWidthConverter_hls(StreamingDataWidthConverter, HLSBackend): + """Class that corresponds to finn-hlslib StreamingDataWidthConverter_Batch + function.""" + + def get_nodeattr_types(self): + my_attrs = {} + my_attrs.update(StreamingDataWidthConverter.get_nodeattr_types(self)) + my_attrs.update(HLSBackend.get_nodeattr_types(self)) + return my_attrs + + def global_includes(self): + self.code_gen_dict["$GLOBALS$"] = ['#include "streamtools.h"'] + + def defines(self, var): + numReps = 1 + numInWords = int(np.prod(self.get_folded_input_shape()[:-1])) + inWidth = self.get_nodeattr("inWidth") + outWidth = self.get_nodeattr("outWidth") + self.code_gen_dict["$DEFINES$"] = [ + "#define InWidth %d " % inWidth, + "#define OutWidth %d " % outWidth, + "#define NumInWords %d " % numInWords, + "#define numReps %d" % numReps, + ] + if self.needs_lcm(): + lcmWidth = self.get_iowidth_lcm() + assert numInWords % (lcmWidth / inWidth) == 0, "Error in DWC LCM calculation" + numLCMToOut = numInWords // (lcmWidth / inWidth) + self.code_gen_dict["$DEFINES$"].append("#define LCMWidth %d" % lcmWidth) + self.code_gen_dict["$DEFINES$"].append("#define NumLCMToOut %d" % (numLCMToOut)) + + def read_npy_data(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_input_datatype() + if dtype == DataType["BIPOLAR"]: + # use binary for bipolar storage + dtype = DataType["BINARY"] + elem_bits = dtype.bitwidth() + packed_bits = self.get_instream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "float" + npy_in = "%s/input_0.npy" % code_gen_dir + self.code_gen_dict["$READNPYDATA$"] = [] + self.code_gen_dict["$READNPYDATA$"].append( + 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) + ) + + def strm_decl(self): + self.code_gen_dict["$STREAMDECLARATIONS$"] = [] + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> in0_{} ("in0_{}");'.format( + self.get_instream_width(), self.hls_sname(), self.hls_sname() + ) + ) + if self.needs_lcm(): + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> intermediate ("intermediate");'.format( + self.get_iowidth_lcm() + ) + ) + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> out_{} ("out_{}");'.format( + self.get_outstream_width(), self.hls_sname(), self.hls_sname() + ) + ) + + def docompute(self): + # TODO continue with fxns below, they are copy-pasted + op = "StreamingDataWidthConverter_Batch" + if self.needs_lcm(): + self.code_gen_dict["$DOCOMPUTE$"] = [ + 'hls::stream> intermediate ("intermediate");'.format( + self.get_iowidth_lcm() + ), + "%s(in0_%s, intermediate, numReps);" + % (op, self.hls_sname()), + "%s(intermediate, out_%s, numReps);" + % (op, self.hls_sname()), + ] + else: + self.code_gen_dict["$DOCOMPUTE$"] = [ + "%s(in0_%s, out_%s, numReps);" + % (op, self.hls_sname(), self.hls_sname()) + ] + + def dataoutstrm(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_output_datatype() + if dtype == DataType["BIPOLAR"]: + # use binary for bipolar storage + dtype = DataType["BINARY"] + elem_bits = dtype.bitwidth() + packed_bits = self.get_outstream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "float" + npy_out = "%s/output.npy" % code_gen_dir + oshape = self.get_folded_output_shape() + oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") + + self.code_gen_dict["$DATAOUTSTREAM$"] = [ + 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + self.hls_sname(), + oshape_cpp_str, + npy_out, + ) + ] + + def save_as_npy(self): + self.code_gen_dict["$SAVEASCNPY$"] = [] + + def blackboxfunction(self): + in_packed_bits = self.get_instream_width() + in_packed_hls_type = "ap_uint<%d>" % in_packed_bits + out_packed_bits = self.get_outstream_width() + out_packed_hls_type = "ap_uint<%d>" % out_packed_bits + self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ + "void %s(hls::stream<%s > &in0_%s, hls::stream<%s > &out_%s)" + % ( + self.onnx_node.name, + in_packed_hls_type, + self.hls_sname(), + out_packed_hls_type, + self.hls_sname(), + ) + ] + + def pragmas(self): + self.code_gen_dict["$PRAGMAS$"] = [ + "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() + ] + self.code_gen_dict["$PRAGMAS$"].append( + "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() + ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") + if self.needs_lcm(): + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS DATAFLOW disable_start_propagation") + + def execute_node(self, context, graph): + mode = self.get_nodeattr("exec_mode") + node = self.onnx_node + exp_shape = self.get_normal_input_shape() + folded_ishape = self.get_folded_input_shape() + + # TODO ensure codegen dir exists + if mode == "cppsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + elif mode == "rtlsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + + inp = context[node.input[0]] + assert str(inp.dtype) == "float32", "Input datatype is not float32" + assert inp.shape == tuple(exp_shape), "Input shape does not match expected shape." + + if self.get_input_datatype() == DataType["BIPOLAR"]: + # store bipolar activations as binary + inp = (inp + 1) / 2 + export_idt = DataType["BINARY"] + else: + export_idt = self.get_input_datatype() + # reshape input into folded shape + reshaped_input = inp.reshape(folded_ishape) + # make copy before saving array + reshaped_input = reshaped_input.copy() + np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input) + + if mode == "cppsim": + output = inp + output = np.asarray([output], dtype=np.float32).reshape(*exp_shape) + context[node.output[0]] = output + + elif mode == "rtlsim": + sim = self.get_rtlsim() + nbits = self.get_instream_width() + rtlsim_inp = npy_to_rtlsim_input( + "{}/input_0.npy".format(code_gen_dir), export_idt, nbits + ) + super().reset_rtlsim(sim) + super().toggle_clk(sim) + rtlsim_output = self.rtlsim(sim, rtlsim_inp) + odt = export_idt + target_bits = odt.bitwidth() + packed_bits = self.get_outstream_width() + out_npy_path = "{}/output.npy".format(code_gen_dir) + out_shape = self.get_folded_output_shape() + rtlsim_output_to_npy( + rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits + ) + # load and reshape output + output = np.load(out_npy_path) + output = np.asarray([output], dtype=np.float32).reshape(exp_shape) + context[node.output[0]] = output + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to "rtlsim" """.format( + mode + ) + ) + # binary -> bipolar if needed + if self.get_output_datatype() == DataType["BIPOLAR"]: + out = context[node.output[0]] + out = 2 * out - 1 + context[node.output[0]] = out + assert context[node.output[0]].shape == tuple( + exp_shape + ), """Output + shape doesn't match expected shape, should be same as input shape""" diff --git a/src/finn/custom_op/fpgadataflow/rtl/__init__.py b/src/finn/custom_op/fpgadataflow/rtl/__init__.py index 7c9b2eaf22..81110d8b9f 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/__init__.py +++ b/src/finn/custom_op/fpgadataflow/rtl/__init__.py @@ -27,9 +27,13 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from finn.custom_op.fpgadataflow.rtl.fmpadding_rtl import FMPadding_rtl +from finn.custom_op.fpgadataflow.rtl.streamingdatawidthconverter_rtl import ( + StreamingDataWidthConverter_rtl, +) custom_op = dict() # make sure new HLSCustomOp subclasses are imported here so that they get # registered and plug in correctly into the infrastructure custom_op["FMPadding_rtl"] = FMPadding_rtl +custom_op["StreamingDataWidthConverter_rtl"] = StreamingDataWidthConverter_rtl diff --git a/src/finn/custom_op/fpgadataflow/streamingdatawidthconverter_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/streamingdatawidthconverter_rtl.py similarity index 63% rename from src/finn/custom_op/fpgadataflow/streamingdatawidthconverter_rtl.py rename to src/finn/custom_op/fpgadataflow/rtl/streamingdatawidthconverter_rtl.py index 4f592bafaa..2d17897afe 100644 --- a/src/finn/custom_op/fpgadataflow/streamingdatawidthconverter_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/streamingdatawidthconverter_rtl.py @@ -1,4 +1,4 @@ -# Copyright (C) 2023, Advanced Micro Devices, Inc. +# Copyright (C) 2023-2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -29,10 +29,11 @@ import numpy as np import os import shutil -import warnings -from qonnx.core.datatype import DataType -from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp +from finn.custom_op.fpgadataflow.rtlbackend import RTLBackend +from finn.custom_op.fpgadataflow.streamingdatawidthconverter import ( + StreamingDataWidthConverter, +) from finn.util.basic import get_rtlsim_trace_depth, make_build_dir from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy @@ -42,41 +43,19 @@ PyVerilator = None -class StreamingDataWidthConverter_rtl(HLSCustomOp): +class StreamingDataWidthConverter_rtl(StreamingDataWidthConverter, RTLBackend): """Class that corresponds to finn-rtllib datawidth converter module.""" def get_nodeattr_types(self): my_attrs = { - # shape of input/output tensors - "shape": ("ints", True, []), - # bit width of input and output streams - "inWidth": ("i", True, 0), - "outWidth": ("i", True, 0), - # FINN DataTypes for inputs/outputs - "dataType": ("s", True, ""), # attribute to save top module name - not user configurable "gen_top_module": ("s", False, ""), } - my_attrs.update(super().get_nodeattr_types()) + my_attrs.update(StreamingDataWidthConverter.get_nodeattr_types(self)) + my_attrs.update(RTLBackend.get_nodeattr_types(self)) return my_attrs - def get_input_datatype(self, ind=0): - """Returns FINN DataType of input.""" - return DataType[self.get_nodeattr("dataType")] - - def get_output_datatype(self, ind=0): - """Returns FINN DataType of output.""" - return DataType[self.get_nodeattr("dataType")] - - def get_normal_input_shape(self, ind=0): - ishape = self.get_nodeattr("shape") - return ishape - - def get_normal_output_shape(self, ind=0): - oshape = self.get_nodeattr("shape") - return oshape - def check_divisible_iowidths(self): iwidth = self.get_nodeattr("inWidth") owidth = self.get_nodeattr("outWidth") @@ -95,83 +74,6 @@ def check_divisible_iowidths(self): owidth, ) - def get_folded_input_shape(self, ind=0): - self.check_divisible_iowidths() - iwidth = self.get_nodeattr("inWidth") - ishape = self.get_normal_input_shape() - dummy_t = np.random.randn(*ishape) - ibits = self.get_input_datatype().bitwidth() - assert ( - iwidth % ibits == 0 - ), """DWC input width must be divisible by - input element bitwidth""" - ielems = int(iwidth // ibits) - ichannels = ishape[-1] - new_shape = [] - for i in ishape[:-1]: - new_shape.append(i) - new_shape.append(int(ichannels // ielems)) - new_shape.append(ielems) - dummy_t = dummy_t.reshape(new_shape) - return dummy_t.shape - - def get_folded_output_shape(self, ind=0): - self.check_divisible_iowidths() - owidth = self.get_nodeattr("outWidth") - oshape = self.get_normal_output_shape() - dummy_t = np.random.randn(*oshape) - obits = self.get_output_datatype().bitwidth() - assert ( - owidth % obits == 0 - ), """DWC output width must be divisible by - input element bitwidth""" - oelems = int(owidth // obits) - ochannels = oshape[-1] - new_shape = [] - for i in oshape[:-1]: - new_shape.append(i) - new_shape.append(int(ochannels // oelems)) - new_shape.append(oelems) - dummy_t = dummy_t.reshape(new_shape) - - return dummy_t.shape - - def get_number_output_values(self): - folded_oshape = self.get_folded_output_shape() - return np.prod(folded_oshape[:-1]) - - def get_instream_width(self, ind=0): - in_width = self.get_nodeattr("inWidth") - return in_width - - def get_outstream_width(self, ind=0): - out_width = self.get_nodeattr("outWidth") - return out_width - - def make_shape_compatible_op(self, model): - exp_ishape = self.get_normal_input_shape() - oshape = self.get_normal_output_shape() - ishape = tuple(model.get_tensor_shape(self.onnx_node.input[0])) - assert ishape == tuple(exp_ishape), "Unexpect input shape for StreamingDWC." - return super().make_const_shape_op(oshape) - - def infer_node_datatype(self, model): - node = self.onnx_node - idt = model.get_tensor_datatype(node.input[0]) - if idt != self.get_input_datatype(): - warn_str = "inputDataType changing for %s: %s -> %s " % ( - node.name, - str(self.get_input_datatype()), - str(idt), - ) - warnings.warn(warn_str) - self.set_nodeattr("dataType", idt.name) - # data type stays the same - model.set_tensor_datatype(node.output[0], idt) - - def verify_node(self): - pass - def execute_node(self, context, graph): mode = self.get_nodeattr("exec_mode") node = self.onnx_node @@ -316,46 +218,3 @@ def code_generation_ipi(self): % (self.get_nodeattr("gen_top_module"), self.onnx_node.name) ] return cmd - - def code_generation_ipgen(self, model, fpgapart, clk): - """Normally: Generates C++ code and tcl script for IP generation. - Here: Generates (System-)Verilog code for IP generation.""" - self.generate_hdl() - - def ipgen_singlenode_code(self): - """Normally: Builds the bash script for IP generation.""" - pass - - def code_generation_cppsim(self, model): - """Normally: Generates C++ code for simulation (cppsim).""" - pass - - def compile_singlenode_code(self): - pass - - def global_includes(self): - pass - - def defines(self, var): - pass - - def read_npy_data(self): - pass - - def strm_decl(self): - pass - - def docompute(self): - pass - - def dataoutstrm(self): - pass - - def save_as_npy(self): - pass - - def blackboxfunction(self): - pass - - def pragmas(self): - pass diff --git a/src/finn/custom_op/fpgadataflow/streamingdatawidthconverter.py b/src/finn/custom_op/fpgadataflow/streamingdatawidthconverter.py new file mode 100644 index 0000000000..4921caeb00 --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/streamingdatawidthconverter.py @@ -0,0 +1,216 @@ +# Copyright (C) 2023-2024, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import math +import numpy as np +import warnings +from qonnx.core.datatype import DataType + +from finn.custom_op.fpgadataflow.hwcustomop import HWCustomOp + +# does not do anything at the ONNX node-by-node level, and input-output +# tensor shapes are the same. performs data width conversion at the rtlsim level + + +class StreamingDataWidthConverter(HWCustomOp): + """Abstraction layer for HW implementation of StreamingDataWidthConverter""" + + def get_nodeattr_types(self): + my_attrs = { + # shape of input/output tensors + "shape": ("ints", True, []), + # bit width of input and output streams + "inWidth": ("i", True, 0), + "outWidth": ("i", True, 0), + # FINN DataTypes for inputs/outputs + "dataType": ("s", True, ""), + } + my_attrs.update(super().get_nodeattr_types()) + return my_attrs + + def get_input_datatype(self, ind=0): + """Returns FINN DataType of input.""" + return DataType[self.get_nodeattr("dataType")] + + def get_output_datatype(self, ind=0): + """Returns FINN DataType of output.""" + return DataType[self.get_nodeattr("dataType")] + + def get_normal_input_shape(self, ind=0): + ishape = self.get_nodeattr("shape") + return ishape + + def get_normal_output_shape(self, ind=0): + oshape = self.get_nodeattr("shape") + return oshape + + def get_iowidth_lcm(self): + iwidth = self.get_nodeattr("inWidth") + owidth = self.get_nodeattr("outWidth") + return int(np.lcm(iwidth, owidth)) + + def needs_lcm(self): + iwidth = self.get_nodeattr("inWidth") + owidth = self.get_nodeattr("outWidth") + maxwidth = max(iwidth, owidth) + minwidth = min(iwidth, owidth) + return maxwidth % minwidth != 0 + + def check_divisible_iowidths(self): + pass + + def get_folded_input_shape(self, ind=0): + self.check_divisible_iowidths() + iwidth = self.get_nodeattr("inWidth") + ishape = self.get_normal_input_shape() + dummy_t = np.random.randn(*ishape) + ibits = self.get_input_datatype().bitwidth() + assert ( + iwidth % ibits == 0 + ), """DWC input width must be divisible by + input element bitwidth""" + ielems = int(iwidth // ibits) + ichannels = ishape[-1] + new_shape = [] + for i in ishape[:-1]: + new_shape.append(i) + new_shape.append(int(ichannels // ielems)) + new_shape.append(ielems) + dummy_t = dummy_t.reshape(new_shape) + return dummy_t.shape + + def get_folded_output_shape(self, ind=0): + self.check_divisible_iowidths() + owidth = self.get_nodeattr("outWidth") + oshape = self.get_normal_output_shape() + dummy_t = np.random.randn(*oshape) + obits = self.get_output_datatype().bitwidth() + assert ( + owidth % obits == 0 + ), """DWC output width must be divisible by + input element bitwidth""" + oelems = int(owidth // obits) + ochannels = oshape[-1] + new_shape = [] + for i in oshape[:-1]: + new_shape.append(i) + new_shape.append(int(ochannels // oelems)) + new_shape.append(oelems) + dummy_t = dummy_t.reshape(new_shape) + + return dummy_t.shape + + def get_number_output_values(self): + folded_oshape = self.get_folded_output_shape() + return np.prod(folded_oshape[:-1]) + + def get_instream_width(self, ind=0): + in_width = self.get_nodeattr("inWidth") + return in_width + + def get_outstream_width(self, ind=0): + out_width = self.get_nodeattr("outWidth") + return out_width + + def make_shape_compatible_op(self, model): + exp_ishape = self.get_normal_input_shape() + oshape = self.get_normal_output_shape() + ishape = tuple(model.get_tensor_shape(self.onnx_node.input[0])) + assert ishape == tuple(exp_ishape), "Unexpect input shape for StreamingDWC." + return super().make_const_shape_op(oshape) + + def infer_node_datatype(self, model): + node = self.onnx_node + idt = model.get_tensor_datatype(node.input[0]) + if idt != self.get_input_datatype(): + warn_str = "inputDataType changing for %s: %s -> %s " % ( + node.name, + str(self.get_input_datatype()), + str(idt), + ) + warnings.warn(warn_str) + self.set_nodeattr("dataType", idt.name) + # data type stays the same + model.set_tensor_datatype(node.output[0], idt) + + def verify_node(self): + info_messages = [] + # verify that "backend" is set to "fpgadataflow" + backend_value = self.get_nodeattr("backend") + if backend_value == "fpgadataflow": + info_messages.append("Attribute backend is set correctly") + else: + info_messages.append('Attribute backend should be set to "fpgadataflow"') + + # verify the number of inputs + if len(self.onnx_node.input) == 1: + info_messages.append("The number of inputs is correct") + else: + info_messages.append("""StreamingDWC needs 1 data input""") + + return info_messages + + def execute_node(self, context, graph): + node = self.onnx_node + exp_shape = self.get_normal_input_shape() + inp = context[node.input[0]] + assert str(inp.dtype) == "float32", "Input datatype is not float32" + assert inp.shape == tuple(exp_shape), "Input shape does not match expected shape." + + output = inp + output = np.asarray([output], dtype=np.float32).reshape(*exp_shape) + context[node.output[0]] = output + + def lut_estimation(self): + """Calculates resource estimations for LUTs""" + inw = self.get_instream_width() + outw = self.get_outstream_width() + + minw = min(inw, outw) + maxw = max(inw, outw) + + # sometimes widths aren't directly divisible + # this requires going up from input width to least common multiple + # then down to output width + intw = abs(maxw * minw) // math.gcd(maxw, minw) + + # we assume a shift-based implementation + # even if we don't use LUTs explicitly, we make some unavailable + # to other logic because they're tied into the DWC control sets + + cnt_luts = 0 + cset_luts = 0 + + if inw != intw: + cnt_luts += abs(math.ceil(math.log(inw / intw, 2))) + cset_luts += intw + if intw != outw: + cnt_luts += abs(math.ceil(math.log(intw / outw, 2))) + cset_luts += outw + + return int(cnt_luts + cset_luts) diff --git a/src/finn/custom_op/fpgadataflow/streamingdatawidthconverter_batch.py b/src/finn/custom_op/fpgadataflow/streamingdatawidthconverter_batch.py deleted file mode 100644 index baf4aed502..0000000000 --- a/src/finn/custom_op/fpgadataflow/streamingdatawidthconverter_batch.py +++ /dev/null @@ -1,540 +0,0 @@ -# Copyright (c) 2020, Xilinx -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# * Redistributions of source code must retain the above copyright notice, this -# list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# * Neither the name of FINN nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -import math -import numpy as np -import os -import warnings -from qonnx.core.datatype import DataType - -from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp -from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy - -# does not do anything at the ONNX node-by-node level, and input-output -# tensor shapes are the same. performs data width conversion at the rtlsim level - - -class StreamingDataWidthConverter_Batch(HLSCustomOp): - """Class that corresponds to finn-hlslib StreamingDataWidthConverter_Batch - function.""" - - def get_nodeattr_types(self): - my_attrs = { - # shape of input/output tensors - "shape": ("ints", True, []), - # bit width of input and output streams - "inWidth": ("i", True, 0), - "outWidth": ("i", True, 0), - # FINN DataTypes for inputs/outputs - "dataType": ("s", True, ""), - # Toggle between hls or IPI implementation - # hls - use the hls generated IP during stitching - # vivado - use the AXI Infrastructure DWC - "impl_style": ("s", False, "hls", {"hls", "vivado"}), - } - my_attrs.update(super().get_nodeattr_types()) - return my_attrs - - def get_input_datatype(self, ind=0): - """Returns FINN DataType of input.""" - return DataType[self.get_nodeattr("dataType")] - - def get_output_datatype(self, ind=0): - """Returns FINN DataType of output.""" - return DataType[self.get_nodeattr("dataType")] - - def get_normal_input_shape(self, ind=0): - ishape = self.get_nodeattr("shape") - return ishape - - def get_normal_output_shape(self, ind=0): - oshape = self.get_nodeattr("shape") - return oshape - - def check_divisible_iowidths(self): - impl_style = self.get_nodeattr("impl_style") - iwidth = self.get_nodeattr("inWidth") - owidth = self.get_nodeattr("outWidth") - if impl_style == "vivado": - # the AXIS IP we use in vivado mode only supports - # stream widths that are divisible by 8 - iwidth_d8 = iwidth % 8 == 0 - owidth_d8 = owidth % 8 == 0 - assert ( - iwidth_d8 and owidth_d8 - ), """DWC impl_style=vivado requires - stream widths that are divisible by 8: (%d, %d)""" % ( - iwidth, - owidth, - ) - - def get_iowidth_lcm(self): - iwidth = self.get_nodeattr("inWidth") - owidth = self.get_nodeattr("outWidth") - return int(np.lcm(iwidth, owidth)) - - def needs_lcm(self): - iwidth = self.get_nodeattr("inWidth") - owidth = self.get_nodeattr("outWidth") - maxwidth = max(iwidth, owidth) - minwidth = min(iwidth, owidth) - impl_style = self.get_nodeattr("impl_style") - return (impl_style == "hls") and (maxwidth % minwidth != 0) - - def get_folded_input_shape(self, ind=0): - self.check_divisible_iowidths() - iwidth = self.get_nodeattr("inWidth") - ishape = self.get_normal_input_shape() - dummy_t = np.random.randn(*ishape) - ibits = self.get_input_datatype().bitwidth() - assert ( - iwidth % ibits == 0 - ), """DWC input width must be divisible by - input element bitwidth""" - ielems = int(iwidth // ibits) - ichannels = ishape[-1] - new_shape = [] - for i in ishape[:-1]: - new_shape.append(i) - new_shape.append(int(ichannels // ielems)) - new_shape.append(ielems) - dummy_t = dummy_t.reshape(new_shape) - return dummy_t.shape - - def get_folded_output_shape(self, ind=0): - self.check_divisible_iowidths() - owidth = self.get_nodeattr("outWidth") - oshape = self.get_normal_output_shape() - dummy_t = np.random.randn(*oshape) - obits = self.get_output_datatype().bitwidth() - assert ( - owidth % obits == 0 - ), """DWC output width must be divisible by - input element bitwidth""" - oelems = int(owidth // obits) - ochannels = oshape[-1] - new_shape = [] - for i in oshape[:-1]: - new_shape.append(i) - new_shape.append(int(ochannels // oelems)) - new_shape.append(oelems) - dummy_t = dummy_t.reshape(new_shape) - - return dummy_t.shape - - def get_number_output_values(self): - folded_oshape = self.get_folded_output_shape() - return np.prod(folded_oshape[:-1]) - - def get_instream_width(self, ind=0): - in_width = self.get_nodeattr("inWidth") - return in_width - - def get_outstream_width(self, ind=0): - out_width = self.get_nodeattr("outWidth") - return out_width - - def make_shape_compatible_op(self, model): - exp_ishape = self.get_normal_input_shape() - oshape = self.get_normal_output_shape() - ishape = tuple(model.get_tensor_shape(self.onnx_node.input[0])) - assert ishape == tuple(exp_ishape), "Unexpect input shape for StreamingDWC." - return super().make_const_shape_op(oshape) - - def infer_node_datatype(self, model): - node = self.onnx_node - idt = model.get_tensor_datatype(node.input[0]) - if idt != self.get_input_datatype(): - warn_str = "inputDataType changing for %s: %s -> %s " % ( - node.name, - str(self.get_input_datatype()), - str(idt), - ) - warnings.warn(warn_str) - self.set_nodeattr("dataType", idt.name) - # data type stays the same - model.set_tensor_datatype(node.output[0], idt) - - def verify_node(self): - info_messages = [] - # verify that "backend" is set to "fpgadataflow" - backend_value = self.get_nodeattr("backend") - if backend_value == "fpgadataflow": - info_messages.append("Attribute backend is set correctly") - else: - info_messages.append('Attribute backend should be set to "fpgadataflow"') - - # verify the number of inputs - if len(self.onnx_node.input) == 1: - info_messages.append("The number of inputs is correct") - else: - info_messages.append("""StreamingDWC needs 1 data input""") - - return info_messages - - def global_includes(self): - self.code_gen_dict["$GLOBALS$"] = ['#include "streamtools.h"'] - - def defines(self, var): - numReps = 1 - numInWords = int(np.prod(self.get_folded_input_shape()[:-1])) - inWidth = self.get_nodeattr("inWidth") - outWidth = self.get_nodeattr("outWidth") - self.code_gen_dict["$DEFINES$"] = [ - "#define InWidth %d " % inWidth, - "#define OutWidth %d " % outWidth, - "#define NumInWords %d " % numInWords, - "#define numReps %d" % numReps, - ] - if self.needs_lcm(): - lcmWidth = self.get_iowidth_lcm() - assert numInWords % (lcmWidth / inWidth) == 0, "Error in DWC LCM calculation" - numLCMToOut = numInWords // (lcmWidth / inWidth) - self.code_gen_dict["$DEFINES$"].append("#define LCMWidth %d" % lcmWidth) - self.code_gen_dict["$DEFINES$"].append("#define NumLCMToOut %d" % (numLCMToOut)) - - def read_npy_data(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_input_datatype() - if dtype == DataType["BIPOLAR"]: - # use binary for bipolar storage - dtype = DataType["BINARY"] - elem_bits = dtype.bitwidth() - packed_bits = self.get_instream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_in = "%s/input_0.npy" % code_gen_dir - self.code_gen_dict["$READNPYDATA$"] = [] - self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - npy_in, - self.hls_sname(), - ) - ) - - def strm_decl(self): - self.code_gen_dict["$STREAMDECLARATIONS$"] = [] - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0_{} ("in0_{}");'.format( - self.get_instream_width(), self.hls_sname(), self.hls_sname() - ) - ) - if self.needs_lcm(): - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> intermediate ("intermediate");'.format( - self.get_iowidth_lcm() - ) - ) - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out_{} ("out_{}");'.format( - self.get_outstream_width(), self.hls_sname(), self.hls_sname() - ) - ) - - def docompute(self): - # TODO continue with fxns below, they are copy-pasted - op = "StreamingDataWidthConverter_Batch" - if self.needs_lcm(): - self.code_gen_dict["$DOCOMPUTE$"] = [ - 'hls::stream> intermediate ("intermediate");'.format( - self.get_iowidth_lcm() - ), - "%s(in0_%s, intermediate, numReps);" - % (op, self.hls_sname()), - "%s(intermediate, out_%s, numReps);" - % (op, self.hls_sname()), - ] - else: - self.code_gen_dict["$DOCOMPUTE$"] = [ - "%s(in0_%s, out_%s, numReps);" - % (op, self.hls_sname(), self.hls_sname()) - ] - - def dataoutstrm(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_output_datatype() - if dtype == DataType["BIPOLAR"]: - # use binary for bipolar storage - dtype = DataType["BINARY"] - elem_bits = dtype.bitwidth() - packed_bits = self.get_outstream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_out = "%s/output.npy" % code_gen_dir - oshape = self.get_folded_output_shape() - oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") - - self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - self.hls_sname(), - oshape_cpp_str, - npy_out, - ) - ] - - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - - def blackboxfunction(self): - in_packed_bits = self.get_instream_width() - in_packed_hls_type = "ap_uint<%d>" % in_packed_bits - out_packed_bits = self.get_outstream_width() - out_packed_hls_type = "ap_uint<%d>" % out_packed_bits - self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - "void %s(hls::stream<%s > &in0_%s, hls::stream<%s > &out_%s)" - % ( - self.onnx_node.name, - in_packed_hls_type, - self.hls_sname(), - out_packed_hls_type, - self.hls_sname(), - ) - ] - - def pragmas(self): - self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() - ] - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() - ) - self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") - if self.needs_lcm(): - self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS DATAFLOW disable_start_propagation") - - def execute_node(self, context, graph): - mode = self.get_nodeattr("exec_mode") - impl_style = self.get_nodeattr("impl_style") - node = self.onnx_node - exp_shape = self.get_normal_input_shape() - folded_ishape = self.get_folded_input_shape() - - # TODO ensure codegen dir exists - if mode == "cppsim": - assert impl_style == "hls", "DWC cppsim only possible when impl_style==hls" - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - elif mode == "rtlsim": - assert impl_style == "hls", "DWC rtlsim only possible when impl_style==hls" - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) - - inp = context[node.input[0]] - assert str(inp.dtype) == "float32", "Input datatype is not float32" - assert inp.shape == tuple(exp_shape), "Input shape does not match expected shape." - - if self.get_input_datatype() == DataType["BIPOLAR"]: - # store bipolar activations as binary - inp = (inp + 1) / 2 - export_idt = DataType["BINARY"] - else: - export_idt = self.get_input_datatype() - # reshape input into folded shape - reshaped_input = inp.reshape(folded_ishape) - # make copy before saving array - reshaped_input = reshaped_input.copy() - np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input) - - if mode == "cppsim": - output = inp - output = np.asarray([output], dtype=np.float32).reshape(*exp_shape) - context[node.output[0]] = output - - elif mode == "rtlsim": - sim = self.get_rtlsim() - nbits = self.get_instream_width() - rtlsim_inp = npy_to_rtlsim_input( - "{}/input_0.npy".format(code_gen_dir), export_idt, nbits - ) - super().reset_rtlsim(sim) - super().toggle_clk(sim) - rtlsim_output = self.rtlsim(sim, rtlsim_inp) - odt = export_idt - target_bits = odt.bitwidth() - packed_bits = self.get_outstream_width() - out_npy_path = "{}/output.npy".format(code_gen_dir) - out_shape = self.get_folded_output_shape() - rtlsim_output_to_npy( - rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits - ) - # load and reshape output - output = np.load(out_npy_path) - output = np.asarray([output], dtype=np.float32).reshape(exp_shape) - context[node.output[0]] = output - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to "rtlsim" """.format( - mode - ) - ) - # binary -> bipolar if needed - if self.get_output_datatype() == DataType["BIPOLAR"]: - out = context[node.output[0]] - out = 2 * out - 1 - context[node.output[0]] = out - assert context[node.output[0]].shape == tuple( - exp_shape - ), """Output - shape doesn't match expected shape, should be same as input shape""" - - def code_generation_ipi(self): - impl_style = self.get_nodeattr("impl_style") - if impl_style == "hls": - return super().code_generation_ipi() - elif impl_style == "vivado": - cmd = [] - node_name = self.onnx_node.name - # create a hierarchy for this layer, with the same port names - clk_name = self.get_verilog_top_module_intf_names()["clk"][0] - rst_name = self.get_verilog_top_module_intf_names()["rst"][0] - dout_name = self.get_verilog_top_module_intf_names()["m_axis"][0][0] - din_name = self.get_verilog_top_module_intf_names()["s_axis"][0][0] - cmd.append("create_bd_cell -type hier %s" % node_name) - cmd.append("create_bd_pin -dir I -type clk /%s/%s" % (node_name, clk_name)) - cmd.append("create_bd_pin -dir I -type rst /%s/%s" % (node_name, rst_name)) - cmd.append( - "create_bd_intf_pin -mode Master " - "-vlnv xilinx.com:interface:axis_rtl:1.0 /%s/%s" % (node_name, dout_name) - ) - cmd.append( - "create_bd_intf_pin -mode Slave " - "-vlnv xilinx.com:interface:axis_rtl:1.0 /%s/%s" % (node_name, din_name) - ) - # instantiate and configure DWC - cmd.append( - "create_bd_cell -type ip " - "-vlnv xilinx.com:ip:axis_dwidth_converter:1.1 /%s/dwc" % node_name - ) - cmd.append( - "set_property -dict " - "[list CONFIG.S_TDATA_NUM_BYTES.VALUE_SRC USER] " - "[get_bd_cells /%s/dwc]" % node_name - ) - cmd.append( - "set_property -dict " - "[list CONFIG.S_TDATA_NUM_BYTES {%d}] [get_bd_cells /%s/dwc]" - % (np.ceil(self.get_instream_width() / 8), node_name) - ) - cmd.append( - "set_property -dict " - "[list CONFIG.M_TDATA_NUM_BYTES {%d}] [get_bd_cells /%s/dwc]" - % (np.ceil(self.get_outstream_width() / 8), node_name) - ) - cmd.append( - "connect_bd_intf_net [get_bd_intf_pins %s/dwc/M_AXIS] " - "[get_bd_intf_pins %s/%s]" % (node_name, node_name, dout_name) - ) - cmd.append( - "connect_bd_intf_net [get_bd_intf_pins %s/dwc/S_AXIS] " - "[get_bd_intf_pins %s/%s]" % (node_name, node_name, din_name) - ) - cmd.append( - "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/dwc/aresetn]" - % (node_name, rst_name, node_name) - ) - cmd.append( - "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/dwc/aclk]" - % (node_name, clk_name, node_name) - ) - return cmd - else: - raise Exception( - "DWC implementation style %s not supported, please use hls or vivado" % impl_style - ) - - def lut_estimation(self): - """Calculates resource estimations for LUTs""" - inw = self.get_instream_width() - outw = self.get_outstream_width() - - minw = min(inw, outw) - maxw = max(inw, outw) - - # sometimes withs aren't directly divisible - # this requires going up from input width to least common multiple - # then down to output width - intw = abs(maxw * minw) // math.gcd(maxw, minw) - - # we assume a shift-based implementation - # even if we don't use LUTs explicitly, we make some unavailable - # to other logic because they're tied into the DWC control sets - - cnt_luts = 0 - cset_luts = 0 - - if inw != intw: - cnt_luts += abs(math.ceil(math.log(inw / intw, 2))) - cset_luts += intw - if intw != outw: - cnt_luts += abs(math.ceil(math.log(intw / outw, 2))) - cset_luts += outw - - return int(cnt_luts + cset_luts) - - def prepare_rtlsim(self): - assert self.get_nodeattr("impl_style") != "vivado", ( - "StreamingDataWidthConverter impl_style " - "cannot be vivado for rtlsim. Only impl_style=rtl supported." - ) - super().prepare_rtlsim() - - def code_generation_ipgen(self, model, fpgapart, clk): - # no codegen required for impl_style=vivado since - # that uses premade, configurable AXIS IP - if self.get_nodeattr("impl_style") == "hls": - super().code_generation_ipgen(model, fpgapart, clk) - - def ipgen_singlenode_code(self): - # no IP generation required for impl_style=vivado since - # that uses premade, configurable AXIS IP - if self.get_nodeattr("impl_style") == "hls": - super().ipgen_singlenode_code() - else: - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - # set ipgen_path and ip_path so that HLSSynthIP - # and CreatedStitchedIP transformations do not complain - self.set_nodeattr("ipgen_path", code_gen_dir) - self.set_nodeattr("ip_path", code_gen_dir) diff --git a/src/finn/transformation/fpgadataflow/floorplan.py b/src/finn/transformation/fpgadataflow/floorplan.py index 336b3f80d0..fce2c2264c 100644 --- a/src/finn/transformation/fpgadataflow/floorplan.py +++ b/src/finn/transformation/fpgadataflow/floorplan.py @@ -81,7 +81,7 @@ def apply(self, model): if node_slr == -1: unassigned_nodes += 1 node_inst.set_nodeattr("slr", default_slr) - if node.op_type == "StreamingDataWidthConverter_Batch": + if node.op_type.startswith("StreamingDataWidthConverter"): # if we have SLR assignment already. use that if node_slr != -1: continue diff --git a/src/finn/transformation/fpgadataflow/insert_dwc.py b/src/finn/transformation/fpgadataflow/insert_dwc.py index bf0254c1a7..ee4311a5a1 100644 --- a/src/finn/transformation/fpgadataflow/insert_dwc.py +++ b/src/finn/transformation/fpgadataflow/insert_dwc.py @@ -1,4 +1,31 @@ -import warnings +# Copyright (C) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + from onnx import TensorProto from onnx import helper as oh from qonnx.custom_op.registry import getCustomOp @@ -8,7 +35,7 @@ def _is_dwc_node(node): - if node.op_type == "StreamingDataWidthConverter_Batch": + if node.op_type.startswith("StreamingDataWidthConverter"): return True else: return False @@ -34,9 +61,8 @@ def _suitable_node(node): class InsertDWC(Transformation): """Add data width converters between layers where necessary.""" - def __init__(self, use_rtl_variant=True): + def __init__(self): super().__init__() - self.use_rtl_variant = use_rtl_variant def apply(self, model): graph = model.graph @@ -50,7 +76,7 @@ def apply(self, model): if consumers == []: continue assert len(consumers) == 1, ( - n.name + ": HLS node with fan-out higher than 1 cannot be stitched" + n.name + ": HW node with fan-out higher than 1 cannot be stitched" ) consumer = consumers[0] if _suitable_node(consumer) is True: @@ -82,20 +108,7 @@ def apply(self, model): dwc_in_width = n0.get_outstream_width() # determine dwc outwidth dwc_out_width = n1.get_instream_width() - if self.use_rtl_variant: - # check if rtl variant can be used - iwidth_d = dwc_in_width % dwc_out_width == 0 - owidth_d = dwc_out_width % dwc_in_width == 0 - if iwidth_d or owidth_d: - node_optype = "StreamingDataWidthConverter_rtl" - else: - warnings.warn( - "DWC cannot be implemented as RTL variant, default to hls" - ) - node_optype = "StreamingDataWidthConverter_Batch" - self.use_rtl_variant = False - else: - node_optype = "StreamingDataWidthConverter_Batch" + node_optype = "StreamingDataWidthConverter" # determine shape for dwc dwc_shape = n0.get_normal_output_shape() @@ -121,15 +134,6 @@ def apply(self, model): outWidth=dwc_out_width, dataType=str(dtype.name), ) - # if not rtl variant is selected - # use hls mode by default since it supports more configs - # vivado mode can be manually enabled by user, but does not - # support e.g. node-by-node rtlsim neded for - # characterization-based FIFO sizing - if not self.use_rtl_variant: - impl_attr = oh.make_attribute("impl_style", "hls") - dwc_node.attribute.append(impl_attr) - # insert dwc graph.node.insert(node_ind + 1, dwc_node) diff --git a/src/finn/transformation/fpgadataflow/specialize_layers.py b/src/finn/transformation/fpgadataflow/specialize_layers.py index 4b2687faee..eff40f83f3 100644 --- a/src/finn/transformation/fpgadataflow/specialize_layers.py +++ b/src/finn/transformation/fpgadataflow/specialize_layers.py @@ -60,6 +60,8 @@ def _determine_impl_style(node): # if impl_style not set, for "simple" layers always try # to use rtl variant if available if impl_style == "": + if optype == "StreamingDataWidthConverter": + return _dwc_determine_impl_style(node) if rtl_variant: return "rtl" # but if no rtl variant, set impl_style to hls @@ -94,6 +96,20 @@ def _determine_impl_style(node): ) ) elif impl_style == "rtl": + # rtl dwc does not support every inWidth to outWidth ratio + if optype == "StreamingDataWidthConverter": + if _dwc_determine_impl_style(node) != "rtl": + warn_str = """RTL implementation of DWC requires + stream widths that are integer width ratios + from each other. Node %s will automatically be + set to HLS variant.""" % ( + node.name, + ) + warnings.warn(warn_str) + return "hls" + else: + # user setting can be fulfilled + return "rtl" if rtl_variant: return "rtl" elif hls_variant: @@ -119,6 +135,20 @@ def _determine_impl_style(node): ) +def _dwc_determine_impl_style(node): + # when possible use rtl variant + dwc = getCustomOp(node) + dwc_in_width = dwc.get_nodeattr("inWidth") + dwc_out_width = dwc.get_nodeattr("outWidth") + # check if rtl variant can be used + iwidth_d = dwc_in_width % dwc_out_width == 0 + owidth_d = dwc_out_width % dwc_in_width == 0 + if iwidth_d or owidth_d: + return "rtl" + else: + return "hls" + + class SpecializeLayers(Transformation): """Specialize all layers to either HLS or RTL variants""" diff --git a/tests/fpgadataflow/test_fpgadataflow_dwc.py b/tests/fpgadataflow/test_fpgadataflow_dwc.py index 47332f069b..706b3d2065 100644 --- a/tests/fpgadataflow/test_fpgadataflow_dwc.py +++ b/tests/fpgadataflow/test_fpgadataflow_dwc.py @@ -1,5 +1,5 @@ # Copyright (C) 2020-2022, Xilinx, Inc. -# Copyright (C) 2023, Advanced Micro Devices, Inc. +# Copyright (C) 2023-2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -36,20 +36,22 @@ from qonnx.util.basic import gen_finn_dt_tensor, qonnx_make_model import finn.core.onnx_exec as oxe +from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP from finn.transformation.fpgadataflow.insert_fifo import InsertFIFO +from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim from finn.transformation.fpgadataflow.prepare_ip import PrepareIP +from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim +from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers -def make_single_dwc_modelwrapper(shape, inWidth, outWidth, finn_dtype, impl_style, use_rtl_variant): +def make_single_dwc_modelwrapper(shape, inWidth, outWidth, finn_dtype): inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, shape) outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, shape) - if use_rtl_variant: - optype = "StreamingDataWidthConverter_rtl" - else: - optype = "StreamingDataWidthConverter_Batch" + optype = "StreamingDataWidthConverter" DWC_node = helper.make_node( optype, @@ -62,10 +64,6 @@ def make_single_dwc_modelwrapper(shape, inWidth, outWidth, finn_dtype, impl_styl outWidth=outWidth, dataType=str(finn_dtype.name), ) - if not use_rtl_variant: - # add additional attribute - impl_attr = helper.make_attribute("impl_style", impl_style) - DWC_node.attribute.append(impl_attr) graph = helper.make_graph(nodes=[DWC_node], name="dwc_graph", inputs=[inp], outputs=[outp]) @@ -85,39 +83,89 @@ def prepare_inputs(input_tensor, dt): @pytest.mark.parametrize( "config", [ - ([1, 24], 6, 4, DataType["INT2"], "hls"), - ([1, 24], 4, 6, DataType["INT2"], "hls"), - ([1, 4], 2, 4, DataType["BIPOLAR"], "hls"), - ([1, 2, 8], 2, 4, DataType["BIPOLAR"], "hls"), - ([1, 4], 4, 2, DataType["INT2"], "hls"), - ([1, 2, 8], 4, 4, DataType["INT2"], "hls"), - ([1, 2, 8], 8, 16, DataType["INT2"], "vivado"), + ([1, 24], 6, 4, DataType["INT2"]), + ([1, 24], 4, 6, DataType["INT2"]), + ([1, 4], 2, 4, DataType["BIPOLAR"]), + ([1, 2, 8], 2, 4, DataType["BIPOLAR"]), + ([1, 4], 4, 2, DataType["INT2"]), + ([1, 2, 8], 4, 4, DataType["INT2"]), + ([1, 2, 8], 8, 16, DataType["INT2"]), ], ) -@pytest.mark.parametrize("use_rtl_variant", [0, 1]) +@pytest.mark.parametrize("exec_mode", ["cppsim", "rtlsim"]) @pytest.mark.fpgadataflow @pytest.mark.slow @pytest.mark.vivado -def test_fpgadataflow_dwc_rtlsim(config, use_rtl_variant): - shape, inWidth, outWidth, finn_dtype, impl_style = config - - if use_rtl_variant: - iwidth_d = inWidth % outWidth == 0 - owidth_d = outWidth % inWidth == 0 - if not (iwidth_d or owidth_d): - pytest.skip("RTL variant only supports stream widths that are divisible by int ratios") +def test_fpgadataflow_dwc_rtlsim(config, exec_mode): + shape, inWidth, outWidth, finn_dtype = config + + test_fpga_part = "xc7z020clg400-1" + # generate input data + x = gen_finn_dt_tensor(finn_dtype, shape) + input_dict = prepare_inputs(x, finn_dtype) + + model = make_single_dwc_modelwrapper(shape, inWidth, outWidth, finn_dtype) + # verify abstraction level execution + y = oxe.execute_onnx(model, input_dict)["outp"] + assert ( + y == x + ).all(), """The output values are not the same as the + input values anymore.""" + assert y.shape == tuple(shape), """The output shape is incorrect.""" + + model = model.transform(SpecializeLayers()) + if exec_mode == "cppsim": + if model.graph.node[0].op_type == "StreamingDataWidthConverter_rtl": + pytest.skip("cppsim not supported for RTL DWC") + else: + model = model.transform(GiveUniqueNodeNames()) + model = model.transform(PrepareCppSim()) + model = model.transform(CompileCppSim()) + model = model.transform(SetExecMode("cppsim")) + elif exec_mode == "rtlsim": + model = model.transform(GiveUniqueNodeNames()) + model = model.transform(PrepareIP(test_fpga_part, 5)) + model = model.transform(HLSSynthIP()) + model = model.transform(SetExecMode("rtlsim")) + model = model.transform(PrepareRTLSim()) + y = oxe.execute_onnx(model, input_dict)["outp"] + + assert ( + y == x + ).all(), """The output values are not the same as the + input values anymore.""" + assert y.shape == tuple(shape), """The output shape is incorrect.""" + + +@pytest.mark.parametrize( + "config", + [ + ([1, 24], 6, 4, DataType["INT2"]), + ([1, 24], 4, 6, DataType["INT2"]), + ([1, 4], 2, 4, DataType["BIPOLAR"]), + ([1, 2, 8], 2, 4, DataType["BIPOLAR"]), + ([1, 4], 4, 2, DataType["INT2"]), + ([1, 2, 8], 4, 4, DataType["INT2"]), + ([1, 2, 8], 8, 16, DataType["INT2"]), + ], +) +@pytest.mark.fpgadataflow +@pytest.mark.slow +@pytest.mark.vivado +def test_fpgadataflow_dwc_stitched_rtlsim(config): + shape, inWidth, outWidth, finn_dtype = config + test_fpga_part = "xc7z020clg400-1" target_clk_ns = 10.0 # generate input data x = gen_finn_dt_tensor(finn_dtype, shape) input_dict = prepare_inputs(x, finn_dtype) - model = make_single_dwc_modelwrapper( - shape, inWidth, outWidth, finn_dtype, impl_style, use_rtl_variant - ) + model = make_single_dwc_modelwrapper(shape, inWidth, outWidth, finn_dtype) + model = model.transform(SpecializeLayers()) model = model.transform(InsertFIFO(create_shallow_fifos=True)) model = model.transform(GiveUniqueNodeNames()) - model = model.transform(PrepareIP(test_fpga_part, 5)) + model = model.transform(PrepareIP(test_fpga_part, target_clk_ns)) model = model.transform(HLSSynthIP()) model = model.transform(CreateStitchedIP(test_fpga_part, target_clk_ns)) model.set_metadata_prop("exec_mode", "rtlsim") From b7eb38c72a6ecbe21cb829fcfd54243a825de8eb Mon Sep 17 00:00:00 2001 From: johnnoel Date: Fri, 12 Jan 2024 10:26:50 +0000 Subject: [PATCH 372/665] [Tests] Fix end2end cybsec_mlp test --- tests/end2end/test_end2end_cybsec_mlp.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/end2end/test_end2end_cybsec_mlp.py b/tests/end2end/test_end2end_cybsec_mlp.py index 2de55db0d9..1cd38eb83a 100644 --- a/tests/end2end/test_end2end_cybsec_mlp.py +++ b/tests/end2end/test_end2end_cybsec_mlp.py @@ -185,7 +185,7 @@ def test_end2end_cybsec_mlp_build(): assert est_cycles_dict["MatrixVectorActivation_1"] == 64 with open(est_res_report, "r") as f: est_res_dict = json.load(f) - assert est_res_dict["total"]["LUT"] == 7904.0 + assert est_res_dict["total"]["LUT"] == 7899.0 assert est_res_dict["total"]["BRAM_18K"] == 36.0 shutil.copytree(output_dir + "/deploy", get_checkpoint_name("build")) shutil.rmtree(get_checkpoint_name("build")) From 798de70f961fb1b13c1886a77aab10e0366a0c5f Mon Sep 17 00:00:00 2001 From: johnnoel Date: Mon, 15 Jan 2024 10:11:55 +0000 Subject: [PATCH 373/665] [CI] Extract HW testing from main Jenkins pipeline and create a seperate HW pipeline --- docker/jenkins/Jenkinsfile | 442 +----------------------- docker/jenkins/Jenkinsfile_HW | 615 ++++++++++++++++++++++++++++++++++ 2 files changed, 625 insertions(+), 432 deletions(-) create mode 100644 docker/jenkins/Jenkinsfile_HW diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index b19cbbccf1..2e4741193c 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -30,10 +30,10 @@ pipeline { runDockerPytestWithMarker("sanity_bnn", "${env.TEST_NAME}", '') // Find the board's build files (bitstreams/xclbins) and zip for use on the boards themselves - findCopyZip("Pynq-Z1", env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "sanity_PynqZ1_zip") - findCopyZip("ZCU104", env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "sanity_ZCU104_zip") - findCopyZip("KV260_SOM", env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "sanity_KV260_SOM_zip") - findCopyZip("U250", env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "sanity_U250_zip") + findCopyZip("Pynq-Z1", env.FINN_HOST_BUILD_DIR, env.TEST_NAME) + findCopyZip("ZCU104", env.FINN_HOST_BUILD_DIR, env.TEST_NAME) + findCopyZip("KV260_SOM", env.FINN_HOST_BUILD_DIR, env.TEST_NAME) + findCopyZip("U250", env.FINN_HOST_BUILD_DIR, env.TEST_NAME) // Stash the test results file(s) stash name: "${env.TEST_NAME}", includes: "${env.TEST_NAME}.xml,${env.TEST_NAME}.html" @@ -161,7 +161,7 @@ pipeline { // Pass in the marker to run with pytest and the XML test results filename runDockerPytestWithMarker("bnn_u250", "${env.TEST_NAME}_${env.BOARD}", '') - findCopyZip(env.BOARD, env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "${env.BOARD}_zip") + findCopyZip(env.BOARD, env.FINN_HOST_BUILD_DIR, env.TEST_NAME) // Stash the test results file(s) stash name: "${env.TEST_NAME}_${env.BOARD}", includes: "${env.TEST_NAME}_${env.BOARD}.xml,${env.TEST_NAME}_${env.BOARD}.html" @@ -193,7 +193,7 @@ pipeline { // Pass in the marker to run with pytest and the XML test results filename runDockerPytestWithMarker("bnn_pynq", "${env.TEST_NAME}_${env.BOARD}", '') - findCopyZip(env.BOARD, env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "PynqZ1_zip") + findCopyZip(env.BOARD, env.FINN_HOST_BUILD_DIR, env.TEST_NAME) // Stash the test results file(s) stash name: "${env.TEST_NAME}_PynqZ1", includes: "${env.TEST_NAME}_${env.BOARD}.xml,${env.TEST_NAME}_${env.BOARD}.html" @@ -225,7 +225,7 @@ pipeline { // Pass in the marker to run with pytest and the XML test results filename runDockerPytestWithMarker("bnn_zcu104", "${env.TEST_NAME}_${env.BOARD}", '') - findCopyZip(env.BOARD, env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "${env.BOARD}_zip") + findCopyZip(env.BOARD, env.FINN_HOST_BUILD_DIR, env.TEST_NAME) // Stash the test results file(s) stash name: "${env.TEST_NAME}_${env.BOARD}", includes: "${env.TEST_NAME}_${env.BOARD}.xml,${env.TEST_NAME}_${env.BOARD}.html" @@ -257,7 +257,7 @@ pipeline { // Pass in the marker to run with pytest and the XML test results filename runDockerPytestWithMarker("bnn_kv260", "${env.TEST_NAME}_${env.BOARD}", '') - findCopyZip(env.BOARD, env.FINN_HOST_BUILD_DIR, env.TEST_NAME, "${env.BOARD}_zip") + findCopyZip(env.BOARD, env.FINN_HOST_BUILD_DIR, env.TEST_NAME) // Stash the test results file(s) stash name: "${env.TEST_NAME}_${env.BOARD}", includes: "${env.TEST_NAME}_${env.BOARD}.xml,${env.TEST_NAME}_${env.BOARD}.html" @@ -270,428 +270,6 @@ pipeline { } } } - stage('Sanity & BNN end2end - Setup Hardware Tests') { - when { - expression { return params['sanity'] } - } - agent { - label 'finn-build' - } - steps { - script { - // Check which boards are online before running HW tests - env.ALVEO_HOST_ONLINE = isNodeOnline('finn-u250') - env.PYNQ_ONLINE = isNodeOnline('finn-pynq') - env.ZCU104_ONLINE = isNodeOnline('finn-zcu104') - env.KV260_ONLINE = isNodeOnline('finn-kv260') - - // Stash the HW test scripts to be used on slave nodes - dir('docker/jenkins') { - stash name: 'bnn_test_files', includes: 'test_bnn_hw_pytest.py' - } - } - } - } - stage('Sanity - Run Hardware Tests') { - parallel { - stage('BNN Sanity - U250') { - when { - // beforeAgent set to 'true' to prevent an offline agent hanging the stage - beforeAgent true - expression { return (env.ALVEO_HOST_ONLINE == 'true' && params['sanity'] && env.BNN_BUILD_SANITY == 'SUCCESS') } - } - agent { - label 'finn-u250' - } - environment { - BOARD = 'U250' - } - steps { - catchError(stageResult: 'FAILURE') { - script { - // Clean any files from a previous run - cleanPreviousBuildFiles("${env.BOARD}*") - - // Get the test files - unstash name: "sanity_${env.BOARD}_zip" - sh "unzip -o ${env.BOARD}.zip" - - dir(env.BOARD) { - // Get the scripts necessary for running hw tests - unstash name: 'bnn_test_files' - - // Create test script - createTestScript(env.BOARD, env.BOARD, "sanity_bnn_test_hw_${env.BOARD}") - - // Use an env variable to help collect test results later in pipeline - env.SANITY_BNN_TEST_U250 = "SUCCESS" - - // Execute the script - sh './run-tests.sh' - } - } - } - } - post { - always { - dir(env.BOARD) { - // Collect the results file on the slave node by stashing - stash name: "xml_sanity_bnn_test_${env.BOARD}", includes: "sanity_bnn_test_hw_${env.BOARD}.xml,sanity_bnn_test_hw_${env.BOARD}.html" - } - } - } - } - stage('BNN Sanity - Pynq-Z1') { - when { - // beforeAgent set to 'true' to prevent an offline agent hanging the stage - beforeAgent true - expression { return (env.PYNQ_ONLINE == 'true' && params['sanity'] && env.BNN_BUILD_SANITY == 'SUCCESS') } - } - agent { - label 'finn-pynq' - } - environment { - BOARD = 'Pynq-Z1' - USER_CREDENTIALS = credentials('pynq-z1-credentials') - } - steps { - catchError(stageResult: 'FAILURE') { - script { - // Clean any files from a previous run - cleanPreviousBoardBuildFiles("${env.BOARD}*") - - // Get the test files - unstash name: "sanity_PynqZ1_zip" - sh "unzip -o ${env.BOARD}.zip" - - dir(env.BOARD) { - // Get the scripts necessary for running hw tests - unstash name: 'bnn_test_files' - - // Create test script - // The marker here omits the '-Z1' as '-' is a special character - // that will not work with Pytest - createTestScript(env.BOARD, 'Pynq', "sanity_bnn_test_hw_${env.BOARD}") - - // Use an env variable to help collect test results later in pipeline - env.SANITY_BNN_TEST_PYNQZ1 = "SUCCESS" - - // Execute the script as the root user - needed for zynq platforms - sh 'echo $USER_CREDENTIALS_PSW | sudo -S ./run-tests.sh' - } - } - } - } - post { - always { - // Get test result file and delete test files on the board - dir(env.BOARD) { - // Collect the results file on the slave node by stashing - stash name: "xml_sanity_bnn_test_PynqZ1", includes: "sanity_bnn_test_hw_${env.BOARD}.xml,sanity_bnn_test_hw_${env.BOARD}.html" - } - } - } - } - stage('BNN Sanity - ZCU104') { - when { - // beforeAgent set to 'true' to prevent an offline agent hanging the stage - beforeAgent true - expression { return (env.ZCU104_ONLINE == 'true' && params['sanity'] && env.BNN_BUILD_SANITY == 'SUCCESS') } - } - agent { - label 'finn-zcu104' - } - environment { - BOARD = 'ZCU104' - USER_CREDENTIALS = credentials('pynq-z1-credentials') - } - steps { - catchError(stageResult: 'FAILURE') { - script { - // Clean any files from a previous run - cleanPreviousBoardBuildFiles("${env.BOARD}*") - - // Get the test files - unstash name: "sanity_${env.BOARD}_zip" - sh "unzip -o ${env.BOARD}.zip" - - dir(env.BOARD) { - // Get the scripts necessary for running hw tests - unstash name: 'bnn_test_files' - - // Create test script - createTestScript(env.BOARD, env.BOARD, "sanity_bnn_test_hw_${env.BOARD}") - - // Use an env variable to help collect test results later in pipeline - env.SANITY_BNN_TEST_ZCU104 = "SUCCESS" - - // Execute the script as the root user - needed for zynq platforms - sh 'echo $USER_CREDENTIALS_PSW | sudo -S ./run-tests.sh' - } - } - } - } - post { - always { - // Get test result file and delete test files on the board - dir(env.BOARD) { - // Collect the results file on the slave node by stashing - stash name: "xml_sanity_bnn_test_${env.BOARD}", includes: "sanity_bnn_test_hw_${env.BOARD}.xml,sanity_bnn_test_hw_${env.BOARD}.html" - } - } - } - } - stage('BNN Sanity - KV260_SOM') { - when { - // beforeAgent set to 'true' to prevent an offline agent hanging the stage - beforeAgent true - expression { return (env.KV260_ONLINE == 'true' && params['sanity'] && env.BNN_BUILD_SANITY == 'SUCCESS') } - } - agent { - label 'finn-kv260' - } - environment { - BOARD = 'KV260_SOM' - USER_CREDENTIALS = credentials('user-ubuntu-credentials') - } - steps { - catchError(stageResult: 'FAILURE') { - script { - // Clean any files from a previous run - cleanPreviousBoardBuildFiles("${env.BOARD}*") - - // Get the test files - unstash name: "sanity_${env.BOARD}_zip" - sh "unzip -o ${env.BOARD}.zip" - - dir(env.BOARD) { - // Get the scripts necessary for running hw tests - unstash name: 'bnn_test_files' - - // Create test script - createTestScript(env.BOARD, env.BOARD, "sanity_bnn_test_hw_${env.BOARD}") - - // Use an env variable to help collect test results later in pipeline - env.SANITY_BNN_TEST_KV260_SOM = "SUCCESS" - - // Execute the script as the root user - needed for zynq platforms - sh 'echo $USER_CREDENTIALS_PSW | sudo -S ./run-tests.sh' - } - } - } - } - post { - always { - // Get test result file and delete test files on the board - dir(env.BOARD) { - // Collect the results file on the slave node by stashing - stash name: "xml_sanity_bnn_test_${env.BOARD}", includes: "sanity_bnn_test_hw_${env.BOARD}.xml,sanity_bnn_test_hw_${env.BOARD}.html" - } - } - } - } - } - } - stage('End2end - Run Hardware Tests') { - parallel { - stage('BNN end2end - U250') { - when { - // beforeAgent set to 'true' to prevent an offline agent hanging the stage - beforeAgent true - expression { return (env.ALVEO_HOST_ONLINE == 'true' && params['end2end'] && env.BNN_BUILD_U250 == 'SUCCESS') } - } - agent { - label 'finn-u250' - } - environment { - BOARD = 'U250' - } - steps { - catchError(stageResult: 'FAILURE') { - script { - // Clean any files from a previous run - cleanPreviousBuildFiles("${env.BOARD}*") - - // Get the test files - unstash name: "${env.BOARD}_zip" - sh "unzip -o ${env.BOARD}.zip" - - dir(env.BOARD) { - // Get the scripts necessary for running hw tests - unstash name: 'bnn_test_files' - - // Create test script - createTestScript(env.BOARD, env.BOARD, "bnn_test_hw_${env.BOARD}") - - // Use an env variable to help collect test results later in pipeline - env.BNN_TEST_U250 = "SUCCESS" - - // Execute the script - sh './run-tests.sh' - } - } - } - } - post { - always { - dir(env.BOARD) { - // Collect the results file on the slave node by stashing - stash name: "xml_bnn_test_${env.BOARD}", includes: "bnn_test_hw_${env.BOARD}.xml,bnn_test_hw_${env.BOARD}.html" - } - } - } - } - stage('BNN end2end - Pynq-Z1') { - when { - // beforeAgent set to 'true' to prevent an offline agent hanging the stage - beforeAgent true - expression { return (env.PYNQ_ONLINE == 'true' && params['end2end'] && env.BNN_BUILD_PYNQZ1 == 'SUCCESS') } - } - agent { - label 'finn-pynq' - } - environment { - BOARD = 'Pynq-Z1' - USER_CREDENTIALS = credentials('pynq-z1-credentials') - } - steps { - catchError(stageResult: 'FAILURE') { - script { - // Clean any files from a previous run - cleanPreviousBoardBuildFiles("${env.BOARD}*") - - // Get the test files - unstash name: "PynqZ1_zip" - sh "unzip -o ${env.BOARD}.zip" - - dir(env.BOARD) { - // Get the scripts necessary for running hw tests - unstash name: 'bnn_test_files' - - // Create test script - // The marker here omits the '-Z1' as '-' is a special character - // that will not work with Pytest - createTestScript(env.BOARD, 'Pynq', "bnn_test_hw_${env.BOARD}") - - // Use an env variable to help collect test results later in pipeline - env.BNN_TEST_PYNQZ1 = "SUCCESS" - - // Execute the script as the root user - needed for zynq platforms - sh 'echo $USER_CREDENTIALS_PSW | sudo -S ./run-tests.sh' - } - } - } - } - post { - always { - // Get test result file and delete test files on the board - dir(env.BOARD) { - // Collect the results file on the slave node by stashing - stash name: "xml_bnn_test_PynqZ1", includes: "bnn_test_hw_${env.BOARD}.xml,bnn_test_hw_${env.BOARD}.html" - } - } - } - } - stage('BNN end2end - ZCU104') { - when { - // beforeAgent set to 'true' to prevent an offline agent hanging the stage - beforeAgent true - expression { return (env.ZCU104_ONLINE == 'true' && params['end2end'] && env.BNN_BUILD_ZCU104 == 'SUCCESS') } - } - agent { - label 'finn-zcu104' - } - environment { - BOARD = 'ZCU104' - USER_CREDENTIALS = credentials('pynq-z1-credentials') - } - steps { - catchError(stageResult: 'FAILURE') { - script { - // Clean any files from a previous run - cleanPreviousBoardBuildFiles("${env.BOARD}*") - - // Get the test files - unstash name: "${env.BOARD}_zip" - sh "unzip -o ${env.BOARD}.zip" - - dir(env.BOARD) { - // Get the scripts necessary for running hw tests - unstash name: 'bnn_test_files' - - // Create test script - createTestScript(env.BOARD, env.BOARD, "bnn_test_hw_${env.BOARD}") - - // Use an env variable to help collect test results later in pipeline - env.BNN_TEST_ZCU104 = "SUCCESS" - - // Execute the script as the root user - needed for zynq platforms - sh 'echo $USER_CREDENTIALS_PSW | sudo -S ./run-tests.sh' - } - } - } - } - post { - always { - // Get test result file and delete test files on the board - dir(env.BOARD) { - // Collect the results file on the slave node by stashing - stash name: "xml_bnn_test_${env.BOARD}", includes: "bnn_test_hw_${env.BOARD}.xml,bnn_test_hw_${env.BOARD}.html" - } - } - } - } - stage('BNN end2end - KV260_SOM') { - when { - // beforeAgent set to 'true' to prevent an offline agent hanging the stage - beforeAgent true - expression { return (env.KV260_ONLINE == 'true' && params['end2end'] && env.BNN_BUILD_KV260_SOM == 'SUCCESS') } - } - agent { - label 'finn-kv260' - } - environment { - BOARD = 'KV260_SOM' - USER_CREDENTIALS = credentials('user-ubuntu-credentials') - } - steps { - catchError(stageResult: 'FAILURE') { - script { - // Clean any files from a previous run - cleanPreviousBoardBuildFiles("${env.BOARD}*") - - // Get the test files - unstash name: "${env.BOARD}_zip" - sh "unzip -o ${env.BOARD}.zip" - - dir(env.BOARD) { - // Get the scripts necessary for running hw tests - unstash name: 'bnn_test_files' - - // Create test script - createTestScript(env.BOARD, env.BOARD, "bnn_test_hw_${env.BOARD}") - - // Use an env variable to help collect test results later in pipeline - env.BNN_TEST_KV260_SOM = "SUCCESS" - - // Execute the script as the root user - needed for zynq platforms - sh 'echo $USER_CREDENTIALS_PSW | sudo -S ./run-tests.sh' - } - } - } - } - post { - always { - // Get test result file and delete test files on the board - dir(env.BOARD) { - // Collect the results file on the slave node by stashing - stash name: "xml_bnn_test_${env.BOARD}", includes: "bnn_test_hw_${env.BOARD}.xml,bnn_test_hw_${env.BOARD}.html" - } - } - } - } - } - } stage('Check Stage Results') { agent { label 'finn-build' @@ -783,12 +361,12 @@ def findBoardBuildFiles(String searchDir, String dirToFind) { return result } -void findCopyZip(String board, String findDir, String copyDir, String stashName) { +void findCopyZip(String board, String findDir, String copyDir) { def buildDir = findBoardBuildFiles(findDir, "hw_deployment_${board}") sh "cp -r ${buildDir}/${board} ${copyDir}/" dir(copyDir) { sh "zip -r ${board}.zip ${board}/" - stash name: stashName, includes: "${board}.zip" + sh "cp ${board}.zip ${env.FINN_HOST_BUILD_DIR}/${copyDir}/" } } diff --git a/docker/jenkins/Jenkinsfile_HW b/docker/jenkins/Jenkinsfile_HW new file mode 100644 index 0000000000..9de20afe23 --- /dev/null +++ b/docker/jenkins/Jenkinsfile_HW @@ -0,0 +1,615 @@ +pipeline { + agent none + stages { + stage('Sanity & BNN end2end - Setup Hardware Tests') { + agent { + label 'finn-build' + } + steps { + script { + // Check which boards are online before running HW tests + env.ALVEO_HOST_ONLINE = isNodeOnline('finn-u250') + env.PYNQ_ONLINE = isNodeOnline('finn-pynq') + env.ZCU104_ONLINE = isNodeOnline('finn-zcu104') + env.KV260_ONLINE = isNodeOnline('finn-kv260') + + // Stash the HW test scripts to be used on slave nodes + dir('docker/jenkins') { + stash name: 'bnn_test_files', includes: 'test_bnn_hw_pytest.py' + } + + dir("${env.ARTIFACT_DIR}"){ + stashBuildArtifacts('bnn_build_sanity') + stashBuildArtifacts('bnn_build_full') + } + } + } + } + stage('Sanity - Run Hardware Tests') { + parallel { + stage('BNN Sanity - U250') { + when { + // beforeAgent set to 'true' to prevent an offline agent hanging the stage + beforeAgent true + expression { return (env.ALVEO_HOST_ONLINE == 'true') } + } + agent { + label 'finn-u250' + } + environment { + BOARD = 'U250' + } + steps { + catchError(stageResult: 'FAILURE') { + script { + // Clean any files from a previous run + cleanPreviousBuildFiles("${env.BOARD}*") + + // Get the test files + unstash name: "bnn_build_sanity_${env.BOARD}_zip" + sh "unzip -o ${env.BOARD}.zip" + + dir(env.BOARD) { + // Get the scripts necessary for running hw tests + unstash name: 'bnn_test_files' + + // Create test script + createTestScript(env.BOARD, env.BOARD, "sanity_bnn_test_hw_${env.BOARD}") + + // Use an env variable to help collect test results later in pipeline + env.SANITY_BNN_TEST_U250 = "SUCCESS" + + // Execute the script + sh './run-tests.sh' + } + } + } + } + post { + always { + dir(env.BOARD) { + // Collect the results file on the slave node by stashing + stash name: "xml_sanity_bnn_test_${env.BOARD}", includes: "sanity_bnn_test_hw_${env.BOARD}.xml,sanity_bnn_test_hw_${env.BOARD}.html" + } + } + } + } + stage('BNN Sanity - Pynq-Z1') { + when { + // beforeAgent set to 'true' to prevent an offline agent hanging the stage + beforeAgent true + expression { return (env.PYNQ_ONLINE == 'true') } + } + agent { + label 'finn-pynq' + } + environment { + BOARD = 'Pynq-Z1' + USER_CREDENTIALS = credentials('pynq-z1-credentials') + } + steps { + catchError(stageResult: 'FAILURE') { + script { + // Clean any files from a previous run + cleanPreviousBoardBuildFiles("${env.BOARD}*") + + // Get the test files + unstash name: "bnn_build_sanity_${env.BOARD}_zip" + sh "unzip -o ${env.BOARD}.zip" + + dir(env.BOARD) { + // Get the scripts necessary for running hw tests + unstash name: 'bnn_test_files' + + // Create test script + // The marker here omits the '-Z1' as '-' is a special character + // that will not work with Pytest + createTestScript(env.BOARD, 'Pynq', "sanity_bnn_test_hw_${env.BOARD}") + + // Use an env variable to help collect test results later in pipeline + env.SANITY_BNN_TEST_PYNQZ1 = "SUCCESS" + + // Execute the script as the root user - needed for zynq platforms + sh 'echo $USER_CREDENTIALS_PSW | sudo -S ./run-tests.sh' + } + } + } + } + post { + always { + // Get test result file and delete test files on the board + dir(env.BOARD) { + // Collect the results file on the slave node by stashing + stash name: "xml_sanity_bnn_test_PynqZ1", includes: "sanity_bnn_test_hw_${env.BOARD}.xml,sanity_bnn_test_hw_${env.BOARD}.html" + } + } + } + } + stage('BNN Sanity - ZCU104') { + when { + // beforeAgent set to 'true' to prevent an offline agent hanging the stage + beforeAgent true + expression { return (env.ZCU104_ONLINE == 'true') } + } + agent { + label 'finn-zcu104' + } + environment { + BOARD = 'ZCU104' + USER_CREDENTIALS = credentials('pynq-z1-credentials') + } + steps { + catchError(stageResult: 'FAILURE') { + script { + // Clean any files from a previous run + cleanPreviousBoardBuildFiles("${env.BOARD}*") + + // Get the test files + unstash name: "bnn_build_sanity_${env.BOARD}_zip" + sh "unzip -o ${env.BOARD}.zip" + + dir(env.BOARD) { + // Get the scripts necessary for running hw tests + unstash name: 'bnn_test_files' + + // Create test script + createTestScript(env.BOARD, env.BOARD, "sanity_bnn_test_hw_${env.BOARD}") + + // Use an env variable to help collect test results later in pipeline + env.SANITY_BNN_TEST_ZCU104 = "SUCCESS" + + // Execute the script as the root user - needed for zynq platforms + sh 'echo $USER_CREDENTIALS_PSW | sudo -S ./run-tests.sh' + } + } + } + } + post { + always { + // Get test result file and delete test files on the board + dir(env.BOARD) { + // Collect the results file on the slave node by stashing + stash name: "xml_sanity_bnn_test_${env.BOARD}", includes: "sanity_bnn_test_hw_${env.BOARD}.xml,sanity_bnn_test_hw_${env.BOARD}.html" + } + } + } + } + stage('BNN Sanity - KV260_SOM') { + when { + // beforeAgent set to 'true' to prevent an offline agent hanging the stage + beforeAgent true + expression { return (env.KV260_ONLINE == 'true') } + } + agent { + label 'finn-kv260' + } + environment { + BOARD = 'KV260_SOM' + USER_CREDENTIALS = credentials('user-ubuntu-credentials') + } + steps { + catchError(stageResult: 'FAILURE') { + script { + // Clean any files from a previous run + cleanPreviousBoardBuildFiles("${env.BOARD}*") + + // Get the test files + unstash name: "bnn_build_sanity_${env.BOARD}_zip" + sh "unzip -o ${env.BOARD}.zip" + + dir(env.BOARD) { + // Get the scripts necessary for running hw tests + unstash name: 'bnn_test_files' + + // Create test script + createTestScript(env.BOARD, env.BOARD, "sanity_bnn_test_hw_${env.BOARD}") + + // Use an env variable to help collect test results later in pipeline + env.SANITY_BNN_TEST_KV260_SOM = "SUCCESS" + + // Execute the script as the root user - needed for zynq platforms + sh 'echo $USER_CREDENTIALS_PSW | sudo -S ./run-tests.sh' + } + } + } + } + post { + always { + // Get test result file and delete test files on the board + dir(env.BOARD) { + // Collect the results file on the slave node by stashing + stash name: "xml_sanity_bnn_test_${env.BOARD}", includes: "sanity_bnn_test_hw_${env.BOARD}.xml,sanity_bnn_test_hw_${env.BOARD}.html" + } + } + } + } + } + } + stage('End2end - Run Hardware Tests') { + parallel { + stage('BNN end2end - U250') { + when { + // beforeAgent set to 'true' to prevent an offline agent hanging the stage + beforeAgent true + expression { return (env.ALVEO_HOST_ONLINE == 'true') } + } + agent { + label 'finn-u250' + } + environment { + BOARD = 'U250' + } + steps { + catchError(stageResult: 'FAILURE') { + script { + // Clean any files from a previous run + cleanPreviousBuildFiles("${env.BOARD}*") + + // Get the test files + unstash name: "bnn_build_full_${env.BOARD}_zip" + sh "unzip -o ${env.BOARD}.zip" + + dir(env.BOARD) { + // Get the scripts necessary for running hw tests + unstash name: 'bnn_test_files' + + // Create test script + createTestScript(env.BOARD, env.BOARD, "bnn_test_hw_${env.BOARD}") + + // Use an env variable to help collect test results later in pipeline + env.BNN_TEST_U250 = "SUCCESS" + + // Execute the script + sh './run-tests.sh' + } + } + } + } + post { + always { + dir(env.BOARD) { + // Collect the results file on the slave node by stashing + stash name: "xml_bnn_test_${env.BOARD}", includes: "bnn_test_hw_${env.BOARD}.xml,bnn_test_hw_${env.BOARD}.html" + } + } + } + } + stage('BNN end2end - Pynq-Z1') { + when { + // beforeAgent set to 'true' to prevent an offline agent hanging the stage + beforeAgent true + expression { return (env.PYNQ_ONLINE == 'true') } + } + agent { + label 'finn-pynq' + } + environment { + BOARD = 'Pynq-Z1' + USER_CREDENTIALS = credentials('pynq-z1-credentials') + } + steps { + catchError(stageResult: 'FAILURE') { + script { + // Clean any files from a previous run + cleanPreviousBoardBuildFiles("${env.BOARD}*") + + // Get the test files + unstash name: "bnn_build_full_${env.BOARD}_zip" + sh "unzip -o ${env.BOARD}.zip" + + dir(env.BOARD) { + // Get the scripts necessary for running hw tests + unstash name: 'bnn_test_files' + + // Create test script + // The marker here omits the '-Z1' as '-' is a special character + // that will not work with Pytest + createTestScript(env.BOARD, 'Pynq', "bnn_test_hw_${env.BOARD}") + + // Use an env variable to help collect test results later in pipeline + env.BNN_TEST_PYNQZ1 = "SUCCESS" + + // Execute the script as the root user - needed for zynq platforms + sh 'echo $USER_CREDENTIALS_PSW | sudo -S ./run-tests.sh' + } + } + } + } + post { + always { + // Get test result file and delete test files on the board + dir(env.BOARD) { + // Collect the results file on the slave node by stashing + stash name: "xml_bnn_test_PynqZ1", includes: "bnn_test_hw_${env.BOARD}.xml,bnn_test_hw_${env.BOARD}.html" + } + } + } + } + stage('BNN end2end - ZCU104') { + when { + // beforeAgent set to 'true' to prevent an offline agent hanging the stage + beforeAgent true + expression { return (env.ZCU104_ONLINE == 'true') } + } + agent { + label 'finn-zcu104' + } + environment { + BOARD = 'ZCU104' + USER_CREDENTIALS = credentials('pynq-z1-credentials') + } + steps { + catchError(stageResult: 'FAILURE') { + script { + // Clean any files from a previous run + cleanPreviousBoardBuildFiles("${env.BOARD}*") + + // Get the test files + unstash name: "bnn_build_full_${env.BOARD}_zip" + sh "unzip -o ${env.BOARD}.zip" + + dir(env.BOARD) { + // Get the scripts necessary for running hw tests + unstash name: 'bnn_test_files' + + // Create test script + createTestScript(env.BOARD, env.BOARD, "bnn_test_hw_${env.BOARD}") + + // Use an env variable to help collect test results later in pipeline + env.BNN_TEST_ZCU104 = "SUCCESS" + + // Execute the script as the root user - needed for zynq platforms + sh 'echo $USER_CREDENTIALS_PSW | sudo -S ./run-tests.sh' + } + } + } + } + post { + always { + // Get test result file and delete test files on the board + dir(env.BOARD) { + // Collect the results file on the slave node by stashing + stash name: "xml_bnn_test_${env.BOARD}", includes: "bnn_test_hw_${env.BOARD}.xml,bnn_test_hw_${env.BOARD}.html" + } + } + } + } + stage('BNN end2end - KV260_SOM') { + when { + // beforeAgent set to 'true' to prevent an offline agent hanging the stage + beforeAgent true + expression { return (env.KV260_ONLINE == 'true') } + } + agent { + label 'finn-kv260' + } + environment { + BOARD = 'KV260_SOM' + USER_CREDENTIALS = credentials('user-ubuntu-credentials') + } + steps { + catchError(stageResult: 'FAILURE') { + script { + // Clean any files from a previous run + cleanPreviousBoardBuildFiles("${env.BOARD}*") + + // Get the test files + unstash name: "bnn_build_full_${env.BOARD}_zip" + sh "unzip -o ${env.BOARD}.zip" + + dir(env.BOARD) { + // Get the scripts necessary for running hw tests + unstash name: 'bnn_test_files' + + // Create test script + createTestScript(env.BOARD, env.BOARD, "bnn_test_hw_${env.BOARD}") + + // Use an env variable to help collect test results later in pipeline + env.BNN_TEST_KV260_SOM = "SUCCESS" + + // Execute the script as the root user - needed for zynq platforms + sh 'echo $USER_CREDENTIALS_PSW | sudo -S ./run-tests.sh' + } + } + } + } + post { + always { + // Get test result file and delete test files on the board + dir(env.BOARD) { + // Collect the results file on the slave node by stashing + stash name: "xml_bnn_test_${env.BOARD}", includes: "bnn_test_hw_${env.BOARD}.xml,bnn_test_hw_${env.BOARD}.html" + } + } + } + } + } + } + // stage('Check Stage Results') { + // agent { + // label 'finn-build' + // } + // steps { + // catchError(buildResult: 'SUCCESS') { + // script { + // checkAllBoards() + // } + // } + // } + // post { + // always { + // script { + // sh 'mkdir -p reports' + // cleanPreviousBuildFiles('reports') + // dir('reports') { + // // Only unstash for stages that ran + // unstashSuccessfulStage(env.SANITY_UT, "sanity_ut") + // unstashSuccessfulStage(env.FPGADATAFLOW_RESULT, "fpgadataflow") + // unstashSuccessfulStage(env.BNN_BUILD_SANITY, "bnn_build_sanity") + // unstashSuccessfulStage(env.SANITY_BNN_TEST_U250, "xml_sanity_bnn_test_U250") + // unstashSuccessfulStage(env.SANITY_BNN_TEST_PYNQZ1, "xml_sanity_bnn_test_PynqZ1") + // unstashSuccessfulStage(env.SANITY_BNN_TEST_ZCU104, "xml_sanity_bnn_test_ZCU104") + // unstashSuccessfulStage(env.SANITY_BNN_TEST_KV260_SOM, "xml_sanity_bnn_test_KV260_SOM") + // unstashSuccessfulStage(env.END2END_RESULT, "end2end") + // unstashSuccessfulStage(env.BNN_BUILD_U250, "bnn_build_full_U250") + // unstashSuccessfulStage(env.BNN_BUILD_PYNQZ1, "bnn_build_full_PynqZ1") + // unstashSuccessfulStage(env.BNN_BUILD_ZCU104, "bnn_build_full_ZCU104") + // unstashSuccessfulStage(env.BNN_BUILD_KV260_SOM, "bnn_build_full_KV260_SOM") + // unstashSuccessfulStage(env.BNN_TEST_U250, "xml_bnn_test_U250") + // unstashSuccessfulStage(env.BNN_TEST_PYNQZ1, "xml_bnn_test_PynqZ1") + // unstashSuccessfulStage(env.BNN_TEST_ZCU104, "xml_bnn_test_ZCU104") + // unstashSuccessfulStage(env.BNN_TEST_KV260_SOM, "xml_bnn_test_KV260_SOM") + // } + + // // Combine individual HTML files to one single report + // sh './run-docker.sh pytest_html_merger -i reports/ -o reports/test_report_final.html' + + // // Archive the XML & HTML test results + // archiveArtifacts artifacts: "reports/*.xml" + // archiveArtifacts artifacts: "reports/*.html" + + // // Plot what XML files were created during the test run + // junit 'reports/*.xml' + // } + // } + // } + // } + } +} + +void cleanPreviousBuildFiles(String buildDir) { + // Delete any build files from a previous build + // Previous build folders affect findCopyZip() and can cause the stage to fail + if (!buildDir.empty) { + sh "rm -rf ${buildDir}" + } +} + +void cleanPreviousBoardBuildFiles(String boardDir) { + // Delete any board build files + // Specifically used on Pynq boards which require sudo to delete + if (!boardDir.empty) { + sh "echo $USER_CREDENTIALS_PSW | sudo -S rm -rf ${boardDir}*" + } +} + +void createMultiMarkerScript(String markers, String testResultsFilename, String additionalOptions) { + // Passing multiple markers when running ./run-docker.sh does not work with bash. + // Therefore, create a script to maintain the single quotes that surround the markers + sh """echo "#!/bin/bash +python -m pytest -m \'${markers}\' --junitxml=${testResultsFilename}.xml --html=${testResultsFilename}.html --self-contained-html ${additionalOptions}" >> run-tests.sh + """ + + // Give permissions to script + sh 'chmod 777 run-tests.sh' +} + +void runDockerPytestWithMarker(String marker, String testResultsFilename, String additionalOptions) { + sh """./run-docker.sh python -m pytest -m ${marker} --junitxml=${testResultsFilename}.xml --html=${testResultsFilename}.html --self-contained-html ${additionalOptions}""" +} + +def findBoardBuildFiles(String searchDir, String dirToFind) { + def result = sh(script: "find $searchDir -type d -name \"$dirToFind*\"", returnStdout: true).trim() + if (result.empty) { + error "Directory containing '$dirToFind' not found." + } + return result +} + +void findCopyZip(String board, String findDir, String copyDir, String stashName) { + def buildDir = findBoardBuildFiles(findDir, "hw_deployment_${board}") + sh "cp -r ${buildDir}/${board} ${copyDir}/" + dir(copyDir) { + sh "zip -r ${board}.zip ${board}/" + stash name: stashName, includes: "${board}.zip" + } +} + +void createTestScript(String board, String marker, String testResultsFilename) { + if(board == "U250") + sh """echo "#!/bin/bash +. /opt/xilinx/xrt/setup.sh +. ${VENV_ACTIVATE} +python -m pytest -m ${marker} --junitxml=${testResultsFilename}.xml --html=${testResultsFilename}.html --self-contained-html" >> run-tests.sh + """ + else + sh """echo "#!/bin/bash +. /etc/profile.d/pynq_venv.sh +. /etc/profile.d/xrt_setup.sh +python -m pytest -m ${marker} --junitxml=${testResultsFilename}.xml --html=${testResultsFilename}.html --self-contained-html" >> run-tests.sh + """ + + // Give permissions to script + sh 'chmod 777 run-tests.sh' +} + +def isNodeOnline(String labelName) { + Label label = Jenkins.instance.getLabel(labelName) + def agentOnline = false + + if (label) { + List nodes = Jenkins.instance.getNodes() + + nodes.each { node -> + if (node.getAssignedLabels().contains(label)) { + def computer = node.toComputer() + if (computer && computer.isOnline()) { + agentOnline = true + } else { + echo """Agent ${node.displayName} is offline""" + } + } + } + } else { + echo """Node with label ${labelName} not found""" + } + + return agentOnline +} + +def checkAllBoards() { + def overallResult = true + + if (env.PYNQ_ONLINE == 'false') { + overallResult = false + } + + if (env.ALVEO_HOST_ONLINE == 'false') { + overallResult = false + } + + if (env.KV260_ONLINE == 'false') { + overallResult = false + } + + if (env.ZCU104_ONLINE == 'false') { + overallResult = false + } + + return overallResult +} + +void unstashSuccessfulStage(String stageEnvVariableSet, String stashName) { + if (stageEnvVariableSet) { + unstash stashName + } +} + +void archiveSuccessfulStage(String stageEnvVariableSet, String folder) { + if (stageEnvVariableSet) { + archiveArtifacts artifacts: "${folder}/**/*" + } +} + +void stashBuildArtifacts(String testDir) { + dir("$testDir") { + def files = findFiles() + files.each { f -> + def file = f.toString() + def extIndex = file.lastIndexOf(".") + def boardName = file.substring(0, extIndex) + echo "stashing ${testDir}/${f} to ${testDir}_${boardName}_zip" + stash name: "${testDir}_${boardName}_zip", includes: "${f}" + } + } +} \ No newline at end of file From 50c795f3db055e7c7149655221e05a3f9761c7a5 Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 15 Jan 2024 14:21:11 +0000 Subject: [PATCH 374/665] [CustomOp] Initial draft of downsampler in new class hierarchy --- src/finn/custom_op/fpgadataflow/__init__.py | 2 +- .../custom_op/fpgadataflow/downsampler.py | 251 ++++-------------- .../custom_op/fpgadataflow/hls/__init__.py | 2 + .../fpgadataflow/hls/downsampler_hls.py | 244 +++++++++++++++++ .../fpgadataflow/convert_to_hw_layers.py | 119 +++++++++ .../test_fpgadataflow_downsampler.py | 10 +- 6 files changed, 428 insertions(+), 200 deletions(-) create mode 100644 src/finn/custom_op/fpgadataflow/hls/downsampler_hls.py diff --git a/src/finn/custom_op/fpgadataflow/__init__.py b/src/finn/custom_op/fpgadataflow/__init__.py index e4b645bbc2..157dfa5c53 100644 --- a/src/finn/custom_op/fpgadataflow/__init__.py +++ b/src/finn/custom_op/fpgadataflow/__init__.py @@ -68,7 +68,6 @@ # make sure new HLSCustomOp subclasses are imported here so that they get # registered and plug in correctly into the infrastructure -custom_op["DownSampler"] = DownSampler custom_op["MatrixVectorActivation"] = MatrixVectorActivation custom_op["ConvolutionInputGenerator"] = ConvolutionInputGenerator custom_op["ConvolutionInputGenerator1D"] = ConvolutionInputGenerator1D @@ -87,6 +86,7 @@ custom_op["FMPadding"] = FMPadding custom_op["AddStreams"] = AddStreams custom_op["ChannelwiseOp"] = ChannelwiseOp +custom_op["DownSampler"] = DownSampler custom_op["DuplicateStreams"] = DuplicateStreams custom_op["GlobalAccPool"] = GlobalAccPool custom_op["LabelSelect"] = LabelSelect diff --git a/src/finn/custom_op/fpgadataflow/downsampler.py b/src/finn/custom_op/fpgadataflow/downsampler.py index e2cea6da6b..4f919d1b50 100644 --- a/src/finn/custom_op/fpgadataflow/downsampler.py +++ b/src/finn/custom_op/fpgadataflow/downsampler.py @@ -1,4 +1,4 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2023, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -27,16 +27,18 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import numpy as np -import os import warnings +from onnx import TensorProto, helper from qonnx.core.datatype import DataType +from qonnx.core.modelwrapper import ModelWrapper +from qonnx.custom_op.registry import getCustomOp +from qonnx.util.basic import qonnx_make_model -from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp -from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy +from finn.custom_op.fpgadataflow.hwcustomop import HWCustomOp -class DownSampler(HLSCustomOp): - """Corresponds to finn-hlslib ConvolutionInputGenerator_*_kernel1 function. +class DownSampler(HWCustomOp): + """Abstraction layer for HW implementation of DownSampling Basically performs a down sampling of the image removing rows and columns.""" def __init__(self, onnx_node, **kwargs): @@ -174,197 +176,54 @@ def get_number_output_values(self): folded_oshape = self.get_folded_output_shape() return np.prod(folded_oshape[:-1]) - def global_includes(self): - self.code_gen_dict["$GLOBALS$"] = ['#include "slidingwindow.h"'] - - def defines(self, var): - self.code_gen_dict["$DEFINES$"] = [] - - ifm_ch = self.get_nodeattr("NumChannels") - self.code_gen_dict["$DEFINES$"] += ["#define IFMChannels {}".format(ifm_ch)] - - ibits = self.get_input_datatype().bitwidth() - self.code_gen_dict["$DEFINES$"] += ["#define Input_precision {}".format(ibits)] - - idim = self.get_nodeattr("ImgDim") - self.code_gen_dict["$DEFINES$"] += ["#define IFMDim {}".format(idim)] - - simd = self.get_nodeattr("SIMD") - self.code_gen_dict["$DEFINES$"] += ["#define SIMD {}".format(simd)] - - stride = self.get_nodeattr("Stride") - self.code_gen_dict["$DEFINES$"] += ["#define Stride {}".format(stride)] - - batch_size = self.get_nodeattr("numInputVectors") - self.code_gen_dict["$DEFINES$"] += ["#define numReps {}".format(batch_size)] - - def read_npy_data(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_input_datatype() - if dtype == DataType["BIPOLAR"]: - # use binary for bipolar storage - dtype = DataType["BINARY"] - elem_bits = dtype.bitwidth() - packed_bits = self.get_instream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_in = "%s/input_0.npy" % code_gen_dir - self.code_gen_dict["$READNPYDATA$"] = [] - self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - npy_in, - self.hls_sname(), - ) - ) - - def strm_decl(self): - self.code_gen_dict["$STREAMDECLARATIONS$"] = [] - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0_{} ("in0_{}");'.format( - self.get_instream_width(), self.hls_sname(), self.hls_sname() - ) - ) - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out_{} ("out_{}");'.format( - self.get_outstream_width(), self.hls_sname(), self.hls_sname() - ) - ) - - def docompute(self): - dim_var = "1D" if (self.get_nodeattr("is1D") == 1) else "2D" - sname = self.hls_sname() - self.code_gen_dict["$DOCOMPUTE$"] = [ - f"""ConvolutionInputGenerator_{dim_var}_kernel1 (in0_{sname}, out_{sname}, numReps);""" - ] - - def dataoutstrm(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_output_datatype() - if dtype == DataType["BIPOLAR"]: - # use binary for bipolar storage - dtype = DataType["BINARY"] - elem_bits = dtype.bitwidth() - packed_bits = self.get_outstream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_out = "%s/output.npy" % code_gen_dir - oshape = self.get_folded_output_shape() - oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") - - self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - self.hls_sname(), - oshape_cpp_str, - npy_out, - ) - ] - - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - - def blackboxfunction(self): - packed_bits = self.get_instream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - "void %s(hls::stream<%s > &in0_%s, hls::stream<%s > &out_%s)" - % ( - self.onnx_node.name, - packed_hls_type, - self.hls_sname(), - packed_hls_type, - self.hls_sname(), - ) - ] - - def pragmas(self): - self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() - ] - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() - ) - self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") - def execute_node(self, context, graph): - mode = self.get_nodeattr("exec_mode") + # using Im2Col node to calculate output node = self.onnx_node - exp_ishape = self.get_normal_input_shape() - exp_oshape = self.get_normal_output_shape() - folded_ishape = self.get_folded_input_shape() - - if mode == "cppsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - elif mode == "rtlsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + ifm_dim = self.get_nodeattr("ImgDim") + stride = self.get_nodeattr("Stride") + ifm_ch = self.get_nodeattr("NumChannels") + # check if 1D or 2D case + if self.get_nodeattr("is1D"): + if self.get_nodeattr("is1D_unitx"): + ifm_dim_w = 1 + sw = 1 + ifm_dim_h = ifm_dim + sh = stride + else: + ifm_dim_h = 1 + sh = 1 + ifm_dim_w = ifm_dim + sw = stride else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) - - inp = context[node.input[0]] - assert str(inp.dtype) == "float32", "Input datatype is not float32" - assert ( - inp.shape == exp_ishape - ), """Input shape doesn't - match expected shape (numInputVectors, ImgDim, ImgDim, NumChannels).""" - export_idt = self.get_input_datatype() - - reshaped_input = inp.reshape(folded_ishape) - np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input) + ifm_dim_h = ifm_dim_w = ifm_dim + sh = sw = stride + inp_values = context[node.input[0]] + oshape = context[node.output[0]].shape + ishape = inp_values.shape + inp = helper.make_tensor_value_info(node.input[0], TensorProto.FLOAT, ishape) + outp = helper.make_tensor_value_info(node.output[0], TensorProto.FLOAT, oshape) + im2col_node = helper.make_node( + "Im2Col", + [node.input[0]], + [node.output[0]], + domain="qonnx.custom_op.general", + stride=[sh, sw], + kernel_size=[1, 1], + input_shape="(1,{},{},{})".format(ifm_dim_h, ifm_dim_w, ifm_ch), + ) + graph_im2col = helper.make_graph( + nodes=[im2col_node], + name="single-im2col-exec", + inputs=[inp], + outputs=[outp], + ) - if mode == "cppsim": - # execute the precompiled model - super().exec_precompiled_singlenode_model() - # load output npy file - super().npy_to_dynamic_output(context) - assert ( - context[node.output[0]].shape == exp_oshape - ), "cppsim did not produce expected output shape" - elif mode == "rtlsim": - sim = self.get_rtlsim() - nbits = self.get_instream_width() - rtlsim_inp = npy_to_rtlsim_input( - "{}/input_0.npy".format(code_gen_dir), export_idt, nbits - ) - super().reset_rtlsim(sim) - super().toggle_clk(sim) - rtlsim_output = self.rtlsim(sim, rtlsim_inp) - odt = export_idt - target_bits = odt.bitwidth() - packed_bits = self.get_outstream_width() - out_npy_path = "{}/output.npy".format(code_gen_dir) - out_shape = self.get_folded_output_shape() - rtlsim_output_to_npy( - rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits - ) - # load and reshape output - output = np.load(out_npy_path) - output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) - context[node.output[0]] = output - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) - assert ( - context[node.output[0]].shape == exp_oshape - ), """Output shape doesn't match expected shape - (1, OutputDim, OutputDim, NumChannels).""" + opset_version = self.onnx_opset_version + opset_imports = [helper.make_opsetid("", opset_version)] + onnx_kwargs = {"opset_imports": opset_imports} + model_im2col = ModelWrapper(qonnx_make_model(graph_im2col, **onnx_kwargs)) + model_im2col.set_tensor_datatype(node.input[0], self.get_input_datatype()) + # use execution function from Im2Col node + # this automatically updates the execution context + inst = getCustomOp(im2col_node) + inst.execute_node(context, model_im2col.graph) diff --git a/src/finn/custom_op/fpgadataflow/hls/__init__.py b/src/finn/custom_op/fpgadataflow/hls/__init__.py index 1803b00023..8b1ca6e719 100644 --- a/src/finn/custom_op/fpgadataflow/hls/__init__.py +++ b/src/finn/custom_op/fpgadataflow/hls/__init__.py @@ -28,6 +28,7 @@ from finn.custom_op.fpgadataflow.hls.addstreams_hls import AddStreams_hls from finn.custom_op.fpgadataflow.hls.channelwise_op_hls import ChannelwiseOp_hls +from finn.custom_op.fpgadataflow.hls.downsampler_hls import DownSampler_hls from finn.custom_op.fpgadataflow.hls.duplicatestreams_hls import DuplicateStreams_hls from finn.custom_op.fpgadataflow.hls.fmpadding_hls import FMPadding_hls from finn.custom_op.fpgadataflow.hls.globalaccpool_hls import GlobalAccPool_hls @@ -46,6 +47,7 @@ # registered and plug in correctly into the infrastructure custom_op["AddStreams_hls"] = AddStreams_hls custom_op["ChannelwiseOp_hls"] = ChannelwiseOp_hls +custom_op["DownSampler_hls"] = DownSampler_hls custom_op["DuplicateStreams_hls"] = DuplicateStreams_hls custom_op["FMPadding_hls"] = FMPadding_hls custom_op["GlobalAccPool_hls"] = GlobalAccPool_hls diff --git a/src/finn/custom_op/fpgadataflow/hls/downsampler_hls.py b/src/finn/custom_op/fpgadataflow/hls/downsampler_hls.py new file mode 100644 index 0000000000..d5bd0877a4 --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/hls/downsampler_hls.py @@ -0,0 +1,244 @@ +# Copyright (C) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import numpy as np +import os +from qonnx.core.datatype import DataType + +from finn.custom_op.fpgadataflow.downsampler import DownSampler +from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend +from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy + + +class DownSampler_hls(DownSampler, HLSBackend): + """Corresponds to finn-hlslib ConvolutionInputGenerator_*_kernel1 function. + Basically performs a down sampling of the image removing rows and columns.""" + + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) + + def get_nodeattr_types(self): + my_attrs = {} + my_attrs.update(DownSampler.get_nodeattr_types(self)) + my_attrs.update(HLSBackend.get_nodeattr_types(self)) + return my_attrs + + def global_includes(self): + self.code_gen_dict["$GLOBALS$"] = ['#include "slidingwindow.h"'] + + def defines(self, var): + self.code_gen_dict["$DEFINES$"] = [] + + ifm_ch = self.get_nodeattr("NumChannels") + self.code_gen_dict["$DEFINES$"] += ["#define IFMChannels {}".format(ifm_ch)] + + ibits = self.get_input_datatype().bitwidth() + self.code_gen_dict["$DEFINES$"] += ["#define Input_precision {}".format(ibits)] + + idim = self.get_nodeattr("ImgDim") + self.code_gen_dict["$DEFINES$"] += ["#define IFMDim {}".format(idim)] + + simd = self.get_nodeattr("SIMD") + self.code_gen_dict["$DEFINES$"] += ["#define SIMD {}".format(simd)] + + stride = self.get_nodeattr("Stride") + self.code_gen_dict["$DEFINES$"] += ["#define Stride {}".format(stride)] + + batch_size = self.get_nodeattr("numInputVectors") + self.code_gen_dict["$DEFINES$"] += ["#define numReps {}".format(batch_size)] + + def read_npy_data(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_input_datatype() + if dtype == DataType["BIPOLAR"]: + # use binary for bipolar storage + dtype = DataType["BINARY"] + elem_bits = dtype.bitwidth() + packed_bits = self.get_instream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "float" + npy_in = "%s/input_0.npy" % code_gen_dir + self.code_gen_dict["$READNPYDATA$"] = [] + self.code_gen_dict["$READNPYDATA$"].append( + 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) + ) + + def strm_decl(self): + self.code_gen_dict["$STREAMDECLARATIONS$"] = [] + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> in0_{} ("in0_{}");'.format( + self.get_instream_width(), self.hls_sname(), self.hls_sname() + ) + ) + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> out_{} ("out_{}");'.format( + self.get_outstream_width(), self.hls_sname(), self.hls_sname() + ) + ) + + def docompute(self): + dim_var = "1D" if (self.get_nodeattr("is1D") == 1) else "2D" + sname = self.hls_sname() + self.code_gen_dict["$DOCOMPUTE$"] = [ + f"""ConvolutionInputGenerator_{dim_var}_kernel1 (in0_{sname}, out_{sname}, numReps);""" + ] + + def dataoutstrm(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_output_datatype() + if dtype == DataType["BIPOLAR"]: + # use binary for bipolar storage + dtype = DataType["BINARY"] + elem_bits = dtype.bitwidth() + packed_bits = self.get_outstream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "float" + npy_out = "%s/output.npy" % code_gen_dir + oshape = self.get_folded_output_shape() + oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") + + self.code_gen_dict["$DATAOUTSTREAM$"] = [ + 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + self.hls_sname(), + oshape_cpp_str, + npy_out, + ) + ] + + def save_as_npy(self): + self.code_gen_dict["$SAVEASCNPY$"] = [] + + def blackboxfunction(self): + packed_bits = self.get_instream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ + "void %s(hls::stream<%s > &in0_%s, hls::stream<%s > &out_%s)" + % ( + self.onnx_node.name, + packed_hls_type, + self.hls_sname(), + packed_hls_type, + self.hls_sname(), + ) + ] + + def pragmas(self): + self.code_gen_dict["$PRAGMAS$"] = [ + "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() + ] + self.code_gen_dict["$PRAGMAS$"].append( + "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() + ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") + + def execute_node(self, context, graph): + mode = self.get_nodeattr("exec_mode") + node = self.onnx_node + exp_ishape = self.get_normal_input_shape() + exp_oshape = self.get_normal_output_shape() + folded_ishape = self.get_folded_input_shape() + + if mode == "cppsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + elif mode == "rtlsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + + inp = context[node.input[0]] + assert str(inp.dtype) == "float32", "Input datatype is not float32" + assert ( + inp.shape == exp_ishape + ), """Input shape doesn't + match expected shape (numInputVectors, ImgDim, ImgDim, NumChannels).""" + export_idt = self.get_input_datatype() + + reshaped_input = inp.reshape(folded_ishape) + np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input) + + if mode == "cppsim": + # execute the precompiled model + super().exec_precompiled_singlenode_model() + # load output npy file + super().npy_to_dynamic_output(context) + assert ( + context[node.output[0]].shape == exp_oshape + ), "cppsim did not produce expected output shape" + elif mode == "rtlsim": + sim = self.get_rtlsim() + nbits = self.get_instream_width() + rtlsim_inp = npy_to_rtlsim_input( + "{}/input_0.npy".format(code_gen_dir), export_idt, nbits + ) + super().reset_rtlsim(sim) + super().toggle_clk(sim) + rtlsim_output = self.rtlsim(sim, rtlsim_inp) + odt = export_idt + target_bits = odt.bitwidth() + packed_bits = self.get_outstream_width() + out_npy_path = "{}/output.npy".format(code_gen_dir) + out_shape = self.get_folded_output_shape() + rtlsim_output_to_npy( + rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits + ) + # load and reshape output + output = np.load(out_npy_path) + output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) + context[node.output[0]] = output + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + assert ( + context[node.output[0]].shape == exp_oshape + ), """Output shape doesn't match expected shape + (1, OutputDim, OutputDim, NumChannels).""" diff --git a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py index 16ed2cfd9a..a65c925f97 100644 --- a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py +++ b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py @@ -41,6 +41,125 @@ from qonnx.util.onnx import nchw_to_nhwc +class InferConvInpGen(Transformation): + """Convert Im2Col layers to ConvolutionInputGenerator layers.""" + + def __init__(self, use_rtl_variant=False): + super().__init__() + self.use_rtl_variant = use_rtl_variant + + def apply(self, model): + graph = model.graph + node_ind = 0 + graph_modified = False + for n in graph.node: + node_ind += 1 + if n.op_type == "Im2Col": + i2c_input = n.input[0] + i2c_output = n.output[0] + i2c_in_shape = model.get_tensor_shape(i2c_input) + dt = model.get_tensor_datatype(i2c_input) + if not dt.is_integer(): + warnings.warn("%s : Input is not int. Can't infer ConvInpGen." % n.name) + continue + i2c_inst = getCustomOp(n) + stride_h, stride_w = i2c_inst.get_nodeattr("stride") + k_h, k_w = i2c_inst.get_nodeattr("kernel_size") + pad_attr = i2c_inst.get_nodeattr("pad_amount") + pad_h = pad_attr[0] + pad_attr[2] + pad_w = pad_attr[1] + pad_attr[3] + dilation_h, dilation_w = i2c_inst.get_nodeattr("dilations") + # temporary checks until non-square conv support is finalized + pad_val = i2c_inst.get_nodeattr("pad_value") + ifm_ch = i2c_in_shape[-1] + ifm_dim_h = i2c_in_shape[1] + ifm_dim_w = i2c_in_shape[2] + + # default params for ConvolutionInputGenerator + ConvInpGen_node_idx = node_ind + ConvInpGen_input = i2c_input + ConvInpGen_idim_h = ifm_dim_h + ConvInpGen_idim_w = ifm_dim_w + + if pad_h > 0 or pad_w > 0: + assert pad_val == 0, ( + "%s : FMPadding_Batch doesn't currently support pad_val!= 0" % n.name + ) + + odim_padding_h = ifm_dim_h + pad_h + odim_padding_w = ifm_dim_w + pad_w + + padding_out = helper.make_tensor_value_info( + model.make_new_valueinfo_name(), + TensorProto.FLOAT, + (1, odim_padding_h, odim_padding_w, ifm_ch), + ) + graph.value_info.append(padding_out) + padding_out = padding_out.name + model.set_tensor_datatype(padding_out, dt) + + ConvInpGen_node_idx += 1 + ConvInpGen_input = padding_out + ConvInpGen_idim_h = odim_padding_h + ConvInpGen_idim_w = odim_padding_w + + padding_node = helper.make_node( + "FMPadding", + [i2c_input], + [padding_out], + domain="finn.custom_op.fpgadataflow", + backend="fpgadataflow", + ImgDim=[ifm_dim_h, ifm_dim_w], + Padding=pad_attr, + NumChannels=ifm_ch, + inputDataType=dt.name, + SIMD=ifm_ch, + name="FMPadding_Batch_" + n.name, + ) + graph.node.insert(node_ind, padding_node) + + is_kernel_pointwise = k_h == 1 and k_w == 1 + is_square_image = ConvInpGen_idim_h == ConvInpGen_idim_w + is_equal_stride = stride_h == stride_w + + # Ensure that only supported HLS nodes are inserted + if (stride_h > 1 or stride_w > 1) and is_kernel_pointwise: + downsample_1D = (ifm_dim_h == 1) or (ifm_dim_w == 1) + is1D_unitx = ifm_dim_w == 1 + downsample_2D = (not downsample_1D) and is_square_image and is_equal_stride + if not (downsample_1D or downsample_2D): + warnings.warn(f"Couldn't infer Downsample from {n.name},check config.") + continue + ConvInpGen_idim = max(ConvInpGen_idim_h, ConvInpGen_idim_w) + stride = max(stride_h, stride_w) + # create DownSampler node + ConvInpGen_node = helper.make_node( + "DownSampler", + [ConvInpGen_input], + [i2c_output], + domain="finn.custom_op.fpgadataflow", + backend="fpgadataflow", + ImgDim=ConvInpGen_idim, + NumChannels=ifm_ch, + SIMD=ifm_ch, + Stride=stride, + inputDataType=dt.name, + name="DownSampler_" + n.name, + is1D=downsample_1D, + is1D_unitx=is1D_unitx, + ) + graph.node.insert(ConvInpGen_node_idx, ConvInpGen_node) + else: + continue + # remove old nodes + graph.node.remove(n) + graph_modified = True + if graph_modified: + model = model.transform(InferShapes()) + model = model.transform(InferDataTypes()) + return (model, graph_modified) + + class InferUpsample(Transformation): """Convert Upsample and Resize nodes to layers to UpsampleNearestNeighbour nodes.""" diff --git a/tests/fpgadataflow/test_fpgadataflow_downsampler.py b/tests/fpgadataflow/test_fpgadataflow_downsampler.py index 8a3c1fe682..25717a4152 100644 --- a/tests/fpgadataflow/test_fpgadataflow_downsampler.py +++ b/tests/fpgadataflow/test_fpgadataflow_downsampler.py @@ -39,7 +39,7 @@ from qonnx.transformation.lower_convs_to_matmul import LowerConvsToMatMul from qonnx.util.basic import gen_finn_dt_tensor -import finn.transformation.fpgadataflow.convert_to_hls_layers as to_hls +import finn.transformation.fpgadataflow.convert_to_hw_layers as to_hw from finn.analysis.fpgadataflow.exp_cycles_per_layer import exp_cycles_per_layer from finn.core.onnx_exec import execute_onnx from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim @@ -48,6 +48,7 @@ from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers def build_model(is_1d, in_dim, k, stride, dt_in, dt_w, pad_half=0, flip_1d=False): @@ -126,8 +127,11 @@ def test_fpgadataflow_downsampler(is_1d, flip_1d, exec_mode): inp = gen_finn_dt_tensor(dt_in, model.get_tensor_shape("in0")) idict = {"in0": inp} y_expected = execute_onnx(model, idict)["out0"] - model = model.transform(to_hls.InferConvInpGen()) + model = model.transform(to_hw.InferConvInpGen()) assert len(model.get_nodes_by_op_type("DownSampler")) == 1 + y_produced = execute_onnx(model, idict)["out0"] + assert (y_produced == y_expected).all() + model = model.transform(SpecializeLayers()) if exec_mode == "cppsim": model = model.transform(SetExecMode("cppsim")) model = model.transform(PrepareCppSim()) @@ -143,7 +147,7 @@ def test_fpgadataflow_downsampler(is_1d, flip_1d, exec_mode): y_produced = execute_onnx(model, idict)["out0"] assert (y_produced == y_expected).all() if exec_mode == "rtlsim": - node = model.get_nodes_by_op_type("DownSampler")[0] + node = model.get_nodes_by_op_type("DownSampler_hls")[0] inst = getCustomOp(node) cycles_rtlsim = inst.get_nodeattr("cycles_rtlsim") exp_cycles_dict = model.analysis(exp_cycles_per_layer) From ee65a984bcdaace2c7dbb30ff63310655d9630d5 Mon Sep 17 00:00:00 2001 From: johnnoel Date: Mon, 15 Jan 2024 15:46:30 +0000 Subject: [PATCH 375/665] [CI] Clean up Jenkinsfiles --- docker/jenkins/Jenkinsfile | 137 +++++------------------------ docker/jenkins/Jenkinsfile_HW | 161 +++++++++------------------------- 2 files changed, 66 insertions(+), 232 deletions(-) diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index 2e4741193c..d3aa216c21 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -275,47 +275,30 @@ pipeline { label 'finn-build' } steps { - catchError(buildResult: 'SUCCESS') { - script { - checkAllBoards() - } - } - } - post { - always { - script { - sh 'mkdir -p reports' - cleanPreviousBuildFiles('reports') - dir('reports') { - // Only unstash for stages that ran - unstashSuccessfulStage(env.SANITY_UT, "sanity_ut") - unstashSuccessfulStage(env.FPGADATAFLOW_RESULT, "fpgadataflow") - unstashSuccessfulStage(env.BNN_BUILD_SANITY, "bnn_build_sanity") - unstashSuccessfulStage(env.SANITY_BNN_TEST_U250, "xml_sanity_bnn_test_U250") - unstashSuccessfulStage(env.SANITY_BNN_TEST_PYNQZ1, "xml_sanity_bnn_test_PynqZ1") - unstashSuccessfulStage(env.SANITY_BNN_TEST_ZCU104, "xml_sanity_bnn_test_ZCU104") - unstashSuccessfulStage(env.SANITY_BNN_TEST_KV260_SOM, "xml_sanity_bnn_test_KV260_SOM") - unstashSuccessfulStage(env.END2END_RESULT, "end2end") - unstashSuccessfulStage(env.BNN_BUILD_U250, "bnn_build_full_U250") - unstashSuccessfulStage(env.BNN_BUILD_PYNQZ1, "bnn_build_full_PynqZ1") - unstashSuccessfulStage(env.BNN_BUILD_ZCU104, "bnn_build_full_ZCU104") - unstashSuccessfulStage(env.BNN_BUILD_KV260_SOM, "bnn_build_full_KV260_SOM") - unstashSuccessfulStage(env.BNN_TEST_U250, "xml_bnn_test_U250") - unstashSuccessfulStage(env.BNN_TEST_PYNQZ1, "xml_bnn_test_PynqZ1") - unstashSuccessfulStage(env.BNN_TEST_ZCU104, "xml_bnn_test_ZCU104") - unstashSuccessfulStage(env.BNN_TEST_KV260_SOM, "xml_bnn_test_KV260_SOM") - } - - // Combine individual HTML files to one single report - sh './run-docker.sh pytest_html_merger -i reports/ -o reports/test_report_final.html' - - // Archive the XML & HTML test results - archiveArtifacts artifacts: "reports/*.xml" - archiveArtifacts artifacts: "reports/*.html" - - // Plot what XML files were created during the test run - junit 'reports/*.xml' - } + script { + sh 'mkdir -p reports' + cleanPreviousBuildFiles('reports') + dir('reports') { + // Only unstash for stages that ran + unstashSuccessfulStage(env.SANITY_UT, "sanity_ut") + unstashSuccessfulStage(env.FPGADATAFLOW_RESULT, "fpgadataflow") + unstashSuccessfulStage(env.BNN_BUILD_SANITY, "bnn_build_sanity") + unstashSuccessfulStage(env.END2END_RESULT, "end2end") + unstashSuccessfulStage(env.BNN_BUILD_U250, "bnn_build_full_U250") + unstashSuccessfulStage(env.BNN_BUILD_PYNQZ1, "bnn_build_full_PynqZ1") + unstashSuccessfulStage(env.BNN_BUILD_ZCU104, "bnn_build_full_ZCU104") + unstashSuccessfulStage(env.BNN_BUILD_KV260_SOM, "bnn_build_full_KV260_SOM") + } + + // Combine individual HTML files to one single report + sh './run-docker.sh pytest_html_merger -i reports/ -o reports/test_report_final.html' + + // Archive the XML & HTML test results + archiveArtifacts artifacts: "reports/*.xml" + archiveArtifacts artifacts: "reports/*.html" + + // Plot what XML files were created during the test run + junit 'reports/*.xml' } } } @@ -330,14 +313,6 @@ void cleanPreviousBuildFiles(String buildDir) { } } -void cleanPreviousBoardBuildFiles(String boardDir) { - // Delete any board build files - // Specifically used on Pynq boards which require sudo to delete - if (!boardDir.empty) { - sh "echo $USER_CREDENTIALS_PSW | sudo -S rm -rf ${boardDir}*" - } -} - void createMultiMarkerScript(String markers, String testResultsFilename, String additionalOptions) { // Passing multiple markers when running ./run-docker.sh does not work with bash. // Therefore, create a script to maintain the single quotes that surround the markers @@ -370,70 +345,6 @@ void findCopyZip(String board, String findDir, String copyDir) { } } -void createTestScript(String board, String marker, String testResultsFilename) { - if(board == "U250") - sh """echo "#!/bin/bash -. /opt/xilinx/xrt/setup.sh -. ${VENV_ACTIVATE} -python -m pytest -m ${marker} --junitxml=${testResultsFilename}.xml --html=${testResultsFilename}.html --self-contained-html" >> run-tests.sh - """ - else - sh """echo "#!/bin/bash -. /etc/profile.d/pynq_venv.sh -. /etc/profile.d/xrt_setup.sh -python -m pytest -m ${marker} --junitxml=${testResultsFilename}.xml --html=${testResultsFilename}.html --self-contained-html" >> run-tests.sh - """ - - // Give permissions to script - sh 'chmod 777 run-tests.sh' -} - -def isNodeOnline(String labelName) { - Label label = Jenkins.instance.getLabel(labelName) - def agentOnline = false - - if (label) { - List nodes = Jenkins.instance.getNodes() - - nodes.each { node -> - if (node.getAssignedLabels().contains(label)) { - def computer = node.toComputer() - if (computer && computer.isOnline()) { - agentOnline = true - } else { - echo """Agent ${node.displayName} is offline""" - } - } - } - } else { - echo """Node with label ${labelName} not found""" - } - - return agentOnline -} - -def checkAllBoards() { - def overallResult = true - - if (env.PYNQ_ONLINE == 'false') { - overallResult = false - } - - if (env.ALVEO_HOST_ONLINE == 'false') { - overallResult = false - } - - if (env.KV260_ONLINE == 'false') { - overallResult = false - } - - if (env.ZCU104_ONLINE == 'false') { - overallResult = false - } - - return overallResult -} - void unstashSuccessfulStage(String stageEnvVariableSet, String stashName) { if (stageEnvVariableSet) { unstash stashName diff --git a/docker/jenkins/Jenkinsfile_HW b/docker/jenkins/Jenkinsfile_HW index 9de20afe23..bfd31fb26b 100644 --- a/docker/jenkins/Jenkinsfile_HW +++ b/docker/jenkins/Jenkinsfile_HW @@ -13,11 +13,12 @@ pipeline { env.ZCU104_ONLINE = isNodeOnline('finn-zcu104') env.KV260_ONLINE = isNodeOnline('finn-kv260') - // Stash the HW test scripts to be used on slave nodes + // Stash the HW test scripts to be used on worker nodes dir('docker/jenkins') { stash name: 'bnn_test_files', includes: 'test_bnn_hw_pytest.py' } + // Collect build artifacts from network and stash for use on worker nodes dir("${env.ARTIFACT_DIR}"){ stashBuildArtifacts('bnn_build_sanity') stashBuildArtifacts('bnn_build_full') @@ -68,7 +69,7 @@ pipeline { post { always { dir(env.BOARD) { - // Collect the results file on the slave node by stashing + // Collect the results file on the worker node by stashing stash name: "xml_sanity_bnn_test_${env.BOARD}", includes: "sanity_bnn_test_hw_${env.BOARD}.xml,sanity_bnn_test_hw_${env.BOARD}.html" } } @@ -119,7 +120,7 @@ pipeline { always { // Get test result file and delete test files on the board dir(env.BOARD) { - // Collect the results file on the slave node by stashing + // Collect the results file on the worker node by stashing stash name: "xml_sanity_bnn_test_PynqZ1", includes: "sanity_bnn_test_hw_${env.BOARD}.xml,sanity_bnn_test_hw_${env.BOARD}.html" } } @@ -168,7 +169,7 @@ pipeline { always { // Get test result file and delete test files on the board dir(env.BOARD) { - // Collect the results file on the slave node by stashing + // Collect the results file on the worker node by stashing stash name: "xml_sanity_bnn_test_${env.BOARD}", includes: "sanity_bnn_test_hw_${env.BOARD}.xml,sanity_bnn_test_hw_${env.BOARD}.html" } } @@ -217,7 +218,7 @@ pipeline { always { // Get test result file and delete test files on the board dir(env.BOARD) { - // Collect the results file on the slave node by stashing + // Collect the results file on the worker node by stashing stash name: "xml_sanity_bnn_test_${env.BOARD}", includes: "sanity_bnn_test_hw_${env.BOARD}.xml,sanity_bnn_test_hw_${env.BOARD}.html" } } @@ -268,7 +269,7 @@ pipeline { post { always { dir(env.BOARD) { - // Collect the results file on the slave node by stashing + // Collect the results file on the worker node by stashing stash name: "xml_bnn_test_${env.BOARD}", includes: "bnn_test_hw_${env.BOARD}.xml,bnn_test_hw_${env.BOARD}.html" } } @@ -319,7 +320,7 @@ pipeline { always { // Get test result file and delete test files on the board dir(env.BOARD) { - // Collect the results file on the slave node by stashing + // Collect the results file on the worker node by stashing stash name: "xml_bnn_test_PynqZ1", includes: "bnn_test_hw_${env.BOARD}.xml,bnn_test_hw_${env.BOARD}.html" } } @@ -368,7 +369,7 @@ pipeline { always { // Get test result file and delete test files on the board dir(env.BOARD) { - // Collect the results file on the slave node by stashing + // Collect the results file on the worker node by stashing stash name: "xml_bnn_test_${env.BOARD}", includes: "bnn_test_hw_${env.BOARD}.xml,bnn_test_hw_${env.BOARD}.html" } } @@ -417,7 +418,7 @@ pipeline { always { // Get test result file and delete test files on the board dir(env.BOARD) { - // Collect the results file on the slave node by stashing + // Collect the results file on the worker node by stashing stash name: "xml_bnn_test_${env.BOARD}", includes: "bnn_test_hw_${env.BOARD}.xml,bnn_test_hw_${env.BOARD}.html" } } @@ -425,55 +426,38 @@ pipeline { } } } - // stage('Check Stage Results') { - // agent { - // label 'finn-build' - // } - // steps { - // catchError(buildResult: 'SUCCESS') { - // script { - // checkAllBoards() - // } - // } - // } - // post { - // always { - // script { - // sh 'mkdir -p reports' - // cleanPreviousBuildFiles('reports') - // dir('reports') { - // // Only unstash for stages that ran - // unstashSuccessfulStage(env.SANITY_UT, "sanity_ut") - // unstashSuccessfulStage(env.FPGADATAFLOW_RESULT, "fpgadataflow") - // unstashSuccessfulStage(env.BNN_BUILD_SANITY, "bnn_build_sanity") - // unstashSuccessfulStage(env.SANITY_BNN_TEST_U250, "xml_sanity_bnn_test_U250") - // unstashSuccessfulStage(env.SANITY_BNN_TEST_PYNQZ1, "xml_sanity_bnn_test_PynqZ1") - // unstashSuccessfulStage(env.SANITY_BNN_TEST_ZCU104, "xml_sanity_bnn_test_ZCU104") - // unstashSuccessfulStage(env.SANITY_BNN_TEST_KV260_SOM, "xml_sanity_bnn_test_KV260_SOM") - // unstashSuccessfulStage(env.END2END_RESULT, "end2end") - // unstashSuccessfulStage(env.BNN_BUILD_U250, "bnn_build_full_U250") - // unstashSuccessfulStage(env.BNN_BUILD_PYNQZ1, "bnn_build_full_PynqZ1") - // unstashSuccessfulStage(env.BNN_BUILD_ZCU104, "bnn_build_full_ZCU104") - // unstashSuccessfulStage(env.BNN_BUILD_KV260_SOM, "bnn_build_full_KV260_SOM") - // unstashSuccessfulStage(env.BNN_TEST_U250, "xml_bnn_test_U250") - // unstashSuccessfulStage(env.BNN_TEST_PYNQZ1, "xml_bnn_test_PynqZ1") - // unstashSuccessfulStage(env.BNN_TEST_ZCU104, "xml_bnn_test_ZCU104") - // unstashSuccessfulStage(env.BNN_TEST_KV260_SOM, "xml_bnn_test_KV260_SOM") - // } - - // // Combine individual HTML files to one single report - // sh './run-docker.sh pytest_html_merger -i reports/ -o reports/test_report_final.html' - - // // Archive the XML & HTML test results - // archiveArtifacts artifacts: "reports/*.xml" - // archiveArtifacts artifacts: "reports/*.html" - - // // Plot what XML files were created during the test run - // junit 'reports/*.xml' - // } - // } - // } - // } + stage('Check Stage Results') { + agent { + label 'finn-build' + } + steps { + script { + sh 'mkdir -p reports' + cleanPreviousBuildFiles('reports') + dir('reports') { + // Only unstash for stages that ran + unstashSuccessfulStage(env.SANITY_BNN_TEST_U250, "xml_sanity_bnn_test_U250") + unstashSuccessfulStage(env.SANITY_BNN_TEST_PYNQZ1, "xml_sanity_bnn_test_PynqZ1") + unstashSuccessfulStage(env.SANITY_BNN_TEST_ZCU104, "xml_sanity_bnn_test_ZCU104") + unstashSuccessfulStage(env.SANITY_BNN_TEST_KV260_SOM, "xml_sanity_bnn_test_KV260_SOM") + unstashSuccessfulStage(env.BNN_TEST_U250, "xml_bnn_test_U250") + unstashSuccessfulStage(env.BNN_TEST_PYNQZ1, "xml_bnn_test_PynqZ1") + unstashSuccessfulStage(env.BNN_TEST_ZCU104, "xml_bnn_test_ZCU104") + unstashSuccessfulStage(env.BNN_TEST_KV260_SOM, "xml_bnn_test_KV260_SOM") + } + + // Combine individual HTML files to one single report + sh './run-docker.sh pytest_html_merger -i reports/ -o reports/test_report_hw_final.html' + + // Archive the XML & HTML test results + archiveArtifacts artifacts: "reports/*.xml" + archiveArtifacts artifacts: "reports/*.html" + + // Plot what XML files were created during the test run + junit 'reports/*.xml' + } + } + } } } @@ -493,38 +477,6 @@ void cleanPreviousBoardBuildFiles(String boardDir) { } } -void createMultiMarkerScript(String markers, String testResultsFilename, String additionalOptions) { - // Passing multiple markers when running ./run-docker.sh does not work with bash. - // Therefore, create a script to maintain the single quotes that surround the markers - sh """echo "#!/bin/bash -python -m pytest -m \'${markers}\' --junitxml=${testResultsFilename}.xml --html=${testResultsFilename}.html --self-contained-html ${additionalOptions}" >> run-tests.sh - """ - - // Give permissions to script - sh 'chmod 777 run-tests.sh' -} - -void runDockerPytestWithMarker(String marker, String testResultsFilename, String additionalOptions) { - sh """./run-docker.sh python -m pytest -m ${marker} --junitxml=${testResultsFilename}.xml --html=${testResultsFilename}.html --self-contained-html ${additionalOptions}""" -} - -def findBoardBuildFiles(String searchDir, String dirToFind) { - def result = sh(script: "find $searchDir -type d -name \"$dirToFind*\"", returnStdout: true).trim() - if (result.empty) { - error "Directory containing '$dirToFind' not found." - } - return result -} - -void findCopyZip(String board, String findDir, String copyDir, String stashName) { - def buildDir = findBoardBuildFiles(findDir, "hw_deployment_${board}") - sh "cp -r ${buildDir}/${board} ${copyDir}/" - dir(copyDir) { - sh "zip -r ${board}.zip ${board}/" - stash name: stashName, includes: "${board}.zip" - } -} - void createTestScript(String board, String marker, String testResultsFilename) { if(board == "U250") sh """echo "#!/bin/bash @@ -567,40 +519,12 @@ def isNodeOnline(String labelName) { return agentOnline } -def checkAllBoards() { - def overallResult = true - - if (env.PYNQ_ONLINE == 'false') { - overallResult = false - } - - if (env.ALVEO_HOST_ONLINE == 'false') { - overallResult = false - } - - if (env.KV260_ONLINE == 'false') { - overallResult = false - } - - if (env.ZCU104_ONLINE == 'false') { - overallResult = false - } - - return overallResult -} - void unstashSuccessfulStage(String stageEnvVariableSet, String stashName) { if (stageEnvVariableSet) { unstash stashName } } -void archiveSuccessfulStage(String stageEnvVariableSet, String folder) { - if (stageEnvVariableSet) { - archiveArtifacts artifacts: "${folder}/**/*" - } -} - void stashBuildArtifacts(String testDir) { dir("$testDir") { def files = findFiles() @@ -608,7 +532,6 @@ void stashBuildArtifacts(String testDir) { def file = f.toString() def extIndex = file.lastIndexOf(".") def boardName = file.substring(0, extIndex) - echo "stashing ${testDir}/${f} to ${testDir}_${boardName}_zip" stash name: "${testDir}_${boardName}_zip", includes: "${f}" } } From 0e563436ab8be0beae95764cfaf6caa11fefc021 Mon Sep 17 00:00:00 2001 From: johnnoel Date: Mon, 15 Jan 2024 15:47:39 +0000 Subject: [PATCH 376/665] Fix linting --- docker/jenkins/Jenkinsfile_HW | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docker/jenkins/Jenkinsfile_HW b/docker/jenkins/Jenkinsfile_HW index bfd31fb26b..71a0bede87 100644 --- a/docker/jenkins/Jenkinsfile_HW +++ b/docker/jenkins/Jenkinsfile_HW @@ -535,4 +535,4 @@ void stashBuildArtifacts(String testDir) { stash name: "${testDir}_${boardName}_zip", includes: "${f}" } } -} \ No newline at end of file +} From e3ab5fcc49638f7dc2707ab8bb4f9d0337bc48f0 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Mon, 15 Jan 2024 16:12:48 +0000 Subject: [PATCH 377/665] [BTS] Binary Thresholding Search base Applying the original BTS pull request #687 by fionnodonohoe-xlnx to add updates and bug fixes --- .../finn.custom_op.fpgadataflow.rst | 8 + finn-rtllib/thresholding/component.xml | 1002 +++++++++++++++++ .../gui/thresholding_axi_v1_0.gtcl | 4 + finn-rtllib/thresholding/hdl/axilite_if.v | 210 ++++ finn-rtllib/thresholding/hdl/thresholding.sv | 358 ++++++ .../thresholding/hdl/thresholding_axi.sv | 164 +++ .../hdl/thresholding_template_wrapper.v | 120 ++ finn-rtllib/thresholding/sim/thresh_gen.sv | 45 + finn-rtllib/thresholding/sim/thresholding.tcl | 17 + .../thresholding/sim/thresholding_axi_tb.sv | 314 ++++++ .../thresholding/sim/thresholding_tb.sv | 274 +++++ .../xgui/thresholding_axi_v1_0.tcl | 187 +++ src/finn/custom_op/fpgadataflow/__init__.py | 4 + .../thresholding_binary_search.py | 579 ++++++++++ .../fpgadataflow/convert_to_hls_layers.py | 81 +- src/finn/util/basic.py | 19 + .../test_convert_to_hls_thresholding.py | 276 +++++ ...fpgadataflow_thresholding_binary_search.py | 287 +++++ tests/util/test_basic.py | 60 + 19 files changed, 3988 insertions(+), 21 deletions(-) create mode 100644 finn-rtllib/thresholding/component.xml create mode 100644 finn-rtllib/thresholding/gui/thresholding_axi_v1_0.gtcl create mode 100644 finn-rtllib/thresholding/hdl/axilite_if.v create mode 100644 finn-rtllib/thresholding/hdl/thresholding.sv create mode 100644 finn-rtllib/thresholding/hdl/thresholding_axi.sv create mode 100644 finn-rtllib/thresholding/hdl/thresholding_template_wrapper.v create mode 100644 finn-rtllib/thresholding/sim/thresh_gen.sv create mode 100644 finn-rtllib/thresholding/sim/thresholding.tcl create mode 100644 finn-rtllib/thresholding/sim/thresholding_axi_tb.sv create mode 100644 finn-rtllib/thresholding/sim/thresholding_tb.sv create mode 100644 finn-rtllib/thresholding/xgui/thresholding_axi_v1_0.tcl create mode 100755 src/finn/custom_op/fpgadataflow/thresholding_binary_search.py create mode 100755 tests/fpgadataflow/test_convert_to_hls_thresholding.py create mode 100755 tests/fpgadataflow/test_fpgadataflow_thresholding_binary_search.py create mode 100755 tests/util/test_basic.py diff --git a/docs/finn/source_code/finn.custom_op.fpgadataflow.rst b/docs/finn/source_code/finn.custom_op.fpgadataflow.rst index fdcf44c6d9..3627855cfb 100644 --- a/docs/finn/source_code/finn.custom_op.fpgadataflow.rst +++ b/docs/finn/source_code/finn.custom_op.fpgadataflow.rst @@ -203,6 +203,14 @@ finn.custom\_op.fpgadataflow.thresholding\_batch :undoc-members: :show-inheritance: +finn.custom\_op.fpgadataflow.thresholding\_binary\_search +----------------------------------------------------------- + +.. automodule:: finn.custom_op.fpgadataflow.thresholding_binary_search + :members: + :undoc-members: + :show-inheritance: + finn.custom\_op.fpgadataflow.tlastmarker ----------------------------------------------- diff --git a/finn-rtllib/thresholding/component.xml b/finn-rtllib/thresholding/component.xml new file mode 100644 index 0000000000..e28a3a2c2d --- /dev/null +++ b/finn-rtllib/thresholding/component.xml @@ -0,0 +1,1002 @@ + + + amd.com + finn + thresholding_axi + 1.0 + + + ap_clk + + + + + + + CLK + + + ap_clk + + + + + + ASSOCIATED_RESET + ap_rst_n + + + ASSOCIATED_BUSIF + s_axilite:s_axis:m_axis + + + FREQ_TOLERANCE_HZ + -1 + + + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + s_axilite + + + + + + + + + AWADDR + + + s_axilite_AWADDR + + + + + AWVALID + + + s_axilite_AWVALID + + + + + AWREADY + + + s_axilite_AWREADY + + + + + WDATA + + + s_axilite_WDATA + + + + + WSTRB + + + s_axilite_WSTRB + + + + + WVALID + + + s_axilite_WVALID + + + + + WREADY + + + s_axilite_WREADY + + + + + BRESP + + + s_axilite_BRESP + + + + + BVALID + + + s_axilite_BVALID + + + + + BREADY + + + s_axilite_BREADY + + + + + ARADDR + + + s_axilite_ARADDR + + + + + ARVALID + + + s_axilite_ARVALID + + + + + ARREADY + + + s_axilite_ARREADY + + + + + RDATA + + + s_axilite_RDATA + + + + + RRESP + + + s_axilite_RRESP + + + + + RVALID + + + s_axilite_RVALID + + + + + RREADY + + + s_axilite_RREADY + + + + + + ap_rst_n + + + + + + + RST + + + ap_rst_n + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axilite + s_axilite + + reg0 + reg0 + 0x0 + 4096 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + thresholding_axi_wrapper + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + fd0bd85b + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + thresholding_axi_wrapper + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + fd0bd85b + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + fc6b9b63 + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 8b0215cd + + + + + + + ap_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + ap_rst_n + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axilite_AWVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axilite_AWREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axilite_AWADDR + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axilite_WVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axilite_WREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axilite_WDATA + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axilite_WSTRB + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axilite_BVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axilite_BREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axilite_BRESP + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axilite_ARVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axilite_ARREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axilite_ARADDR + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axilite_RVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axilite_RREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axilite_RDATA + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axilite_RRESP + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tdata + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axis_tready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tdata + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + N + N + 4 + + + K + K + 16 + + + C + C + 1 + + + PE + Pe + 1 + + + SIGNED + Signed + true + + + FPARG + Fparg + false + + + BIAS + Bias + 0 + + + CF + Cf + 1 + + + ADDR_BITS + Addr Bits + 6 + + + O_BITS + O Bits + 4 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + hdl/thresholding.sv + systemVerilogSource + + + hdl/thresholding_axi.sv + systemVerilogSource + + + hdl/thresholding_axi_wrapper.v + verilogSource + CHECKSUM_7b8c102d + + + hdl/axilite_if.v + verilogSource + CHECKSUM_69d1ba26 + xil_defaultlib + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + hdl/thresholding.sv + systemVerilogSource + + + hdl/thresholding_axi.sv + systemVerilogSource + + + hdl/thresholding_axi_wrapper.v + verilogSource + + + hdl/axilite_if.v + verilogSource + USED_IN_ipstatic + xil_defaultlib + + + + xilinx_xpgui_view_fileset + + xgui/thresholding_axi_v1_0.tcl + tclSource + CHECKSUM_fc6b9b63 + XGUI_VERSION_2 + + + + xilinx_utilityxitfiles_view_fileset + + gui/thresholding_axi_v1_0.gtcl + GTCL + + + + MultiThreshold + + + N + Output Precision + 4 + + + K + Input Precision + 16 + + + C + Channels + 1 + + + PE + Pe + 1 + + + SIGNED + Signed Inputs + true + + + FPARG + Floating-Point Inputs + false + + + BIAS + Bias + 0 + + + CF + Channel Fold + 1 + + + + false + + + + + + ADDR_BITS + Address Bits + 6 + + + + false + + + + + + O_BITS + Output Value Width + 4 + + + + false + + + + + + Component_Name + thresholding_axi_wrapper_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /UserIP + + thresholding_axi + level_1 + package_project + 2 + + user.org:user:thresholding_axi_wrapper:1.0 + + 2023-06-27T05:47:20Z + + + + + + 2022.2 + + + + + + + + + + + + + + diff --git a/finn-rtllib/thresholding/gui/thresholding_axi_v1_0.gtcl b/finn-rtllib/thresholding/gui/thresholding_axi_v1_0.gtcl new file mode 100644 index 0000000000..90d73ede7e --- /dev/null +++ b/finn-rtllib/thresholding/gui/thresholding_axi_v1_0.gtcl @@ -0,0 +1,4 @@ +# This file is automatically written. Do not modify. +proc gen_USERPARAMETER_CF_VALUE {C PE } {expr $C/$PE} +proc gen_USERPARAMETER_ADDR_BITS_VALUE {C PE N } {expr int(ceil(log($C/$PE)/log(2))+ceil(log($PE)/log(2))+$N+2)} +proc gen_USERPARAMETER_O_BITS_VALUE {BIAS N } {expr int(ceil($BIAS >= 0? log(pow(2,$N)+$BIAS)/log(2) : 1+log(-$BIAS >= pow(2,$N-1)? -$BIAS : pow(2,$N)+$BIAS)/log(2)))} diff --git a/finn-rtllib/thresholding/hdl/axilite_if.v b/finn-rtllib/thresholding/hdl/axilite_if.v new file mode 100644 index 0000000000..bdd4de288e --- /dev/null +++ b/finn-rtllib/thresholding/hdl/axilite_if.v @@ -0,0 +1,210 @@ +/* + Copyright (c) 2020, Xilinx + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + * Neither the name of FINN nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +module axi4lite_if +#( + parameter ADDR_WIDTH = 32, + parameter DATA_WIDTH = 32,//AXI4 spec requires this to be strictly 32 or 64 + parameter IP_DATA_WIDTH = 64//can be any power-of-2 multiple of DATA_WIDTH +) +( +//system signals +input aclk, +input aresetn,//active low, asynchronous assertion and synchronous deassertion + +//Write channels +//write address +output reg awready, +input awvalid, +input [ADDR_WIDTH-1:0] awaddr, +input [2:0] awprot, +//write data +output reg wready, +input wvalid, +input [DATA_WIDTH-1:0] wdata, +input [(DATA_WIDTH/8)-1:0] wstrb, +//burst response +input bready, +output reg bvalid, +output reg [1:0] bresp,//NOTE: 00 = OKAY, 10 = SLVERR (write error) + +//Read channels +//read address +output reg arready, +input arvalid, +input [ADDR_WIDTH-1:0] araddr, +input [2:0] arprot, +//read data +input rready, +output reg rvalid, +output reg [1:0] rresp,//NOTE: 00 = OKAY, 10 = SLVERR (read error) +output reg [DATA_WIDTH-1:0] rdata, + +//IP-side interface +output reg ip_en, +output reg ip_wen, +output reg [ADDR_WIDTH-1:0] ip_addr, +output [IP_DATA_WIDTH-1:0] ip_wdata, +input ip_rack, +input [IP_DATA_WIDTH-1:0] ip_rdata +); + +localparam RESP_OKAY = 2'b00; +localparam RESP_SLVERR = 2'b10; +//get ceil(log2(ceil(IP_DATA_WIDTH/DATA_WIDTH))) +localparam NFOLDS_LOG = $clog2((IP_DATA_WIDTH + DATA_WIDTH - 1) / DATA_WIDTH); + +reg internal_ren; +reg internal_wen; +reg internal_wack; +reg [ADDR_WIDTH-1:0] internal_raddr; +reg [ADDR_WIDTH-1:0] internal_waddr; +reg [DATA_WIDTH-1:0] internal_wdata; +wire [DATA_WIDTH-1:0] internal_rdata; +reg internal_error = 0; + +//check DATA_WIDTH +initial begin + if(DATA_WIDTH != 32 & DATA_WIDTH != 64) begin + $display("AXI4Lite DATA_WIDTH must be 32 or 64"); + $finish; + end +end + +//transaction state machine +localparam STATE_IDLE = 0, + STATE_READ = 1, + STATE_WRITE = 2; + +reg [1:0] state; + +always @(posedge aclk or negedge aresetn) + if(~aresetn) + state <= STATE_IDLE; + else case(state) + STATE_IDLE: + if(awvalid & wvalid) + state <= STATE_WRITE; + else if(arvalid) + state <= STATE_READ; + STATE_READ: + if(rvalid & rready) + state <= STATE_IDLE; + STATE_WRITE: + if(bvalid & bready) + state <= STATE_IDLE; + default: state <= STATE_IDLE; + endcase + +//write-related internal signals +always @(*) begin + internal_waddr = awaddr >> $clog2(DATA_WIDTH/8); + internal_wdata = wdata; + internal_wen = (state == STATE_IDLE) & awvalid & wvalid; +end + +always @(posedge aclk) begin + awready <= internal_wen; + wready <= internal_wen; +end + +//read-related internal signals +always @(*) begin + internal_raddr = araddr >> $clog2(DATA_WIDTH/8); + internal_ren = (state == STATE_IDLE) & ~internal_wen & arvalid; +end + +always @(posedge aclk) + arready <= internal_ren; + +wire write_to_last_fold; + +always @(posedge aclk) begin + ip_wen <= write_to_last_fold; + ip_en <= internal_ren | write_to_last_fold; + if(internal_ren | write_to_last_fold) + ip_addr <= internal_ren ? (internal_raddr >> NFOLDS_LOG) : (internal_waddr >> NFOLDS_LOG); + internal_wack <= internal_wen; +end + +genvar i; +reg [(1<> (internal_rfold*DATA_WIDTH); + always @(posedge aclk) + if(internal_ren) + internal_rfold <= internal_raddr[NFOLDS_LOG-1:0]; + for(i=0; i<(1< + * + * @description + * Produces the N-bit count of those among 2^N-1 thresholds that are not + * larger than the corresponding input: + * y = Σ(T_i <= x) + * The result is computed by binary search. The runtime-configurable + * thresholds must be written in ascending order: + * i < j => T_i < T_j + * The design supports channel folding allowing each input to be processed + * with respect to a selectable set of thresholds. The corresponding + * threshold configuration relies on a channel address prefix. Inputs are + * accompanied by a channel selector. + * + * Parameter Layout as seen on AXI-Lite (row by row): + * | Base \ Offs | 0 1 2 ... 2^N-2 2^N-1 + * ---------+--------------------------------+------------------------------------ + * Chnl #0 | 0 | T_0 T_1 T_2 ... T_{2^N-2} 'x + * Chnl #1 | 2^N | T_0 T_1 T_2 ... T_{2^N-2} 'x + * Chnl #c | ((c/PE)*$clog2(PE) + c%PE)*2^N | T_0 T_1 T_2 ... T_{2^N-2} 'x + * + *****************************************************************************/ +module thresholding #( + int unsigned N, // output precision + int unsigned K, // input/threshold precision + int unsigned C, // number of channels + int unsigned PE, // parallel processing elements + + bit SIGNED = 1, // signed inputs + bit FPARG = 0, // floating-point inputs: [sign] | exponent | mantissa + int BIAS = 0, // offsetting the output [0, 2^N-1] -> [BIAS, 2^N-1 + BIAS] + + // Initial Thresholds + parameter THRESHOLDS_PATH = "", + bit USE_CONFIG = 1, + + // Force Use of On-Chip Memory Blocks + int unsigned DEPTH_TRIGGER_URAM = 0, // if non-zero, local mems of this depth or more go into URAM (prio) + int unsigned DEPTH_TRIGGER_BRAM = 0, // if non-zero, local mems of this depth or more go into BRAM + bit DEEP_PIPELINE = 0, + + localparam int unsigned CF = C/PE, // Channel fold + localparam int unsigned O_BITS = BIAS >= 0? + /* unsigned */ $clog2(2**N+BIAS) : + /* signed */ 1+$clog2(-BIAS >= 2**(N-1)? -BIAS : 2**N+BIAS) +)( + // Global Control + input logic clk, + input logic rst, + + // Threshold Configuration + input logic cfg_en, + input logic cfg_we, + input logic [$clog2(CF)+$clog2(PE)+N-1:0] cfg_a, + input logic [K-1:0] cfg_d, + output logic cfg_rack, + output logic [K-1:0] cfg_q, + + // Input Stream + output logic irdy, + input logic ivld, + input logic [PE-1:0][K-1:0] idat, + + // Output Stream + input logic ordy, + output logic ovld, + output logic [PE-1:0][O_BITS-1:0] odat +); + + // Parameter Constraints Checking + initial begin + if(CF*PE != C) begin + $error("Parallelism PE=%0d is not a multiple of channel count C=%0d.", PE, C); + $finish; + end + end + + // Operations within Pipeline + typedef enum logic [1:0] { + NOP = 2'b00, // No operation + TH = 2'b01, // Thresholding + WR = 2'b11, // Write (initialization) + RB = 2'b10, // Readback (validation) + CFG = 2'b1x // Config op (pointer-preserving) + } op_e; + + // Pipeline Link Type + typedef logic [$clog2(CF)+N-1:0] ptr_t; + typedef logic [K -1:0] val_t; + typedef struct packed { + op_e op; + ptr_t ptr; // WR/RB: address; TH: result + val_t val; // WR/RB: threshold value; TH: input value + } pipe_t; + + //----------------------------------------------------------------------- + // Pipeline Feed + // - configuration always takes precedence + // - number of pending thresholding ops capped to N+3 + // across pipeline and output FIFO: pipe:N + A:1 + B:1 + 1 + localparam int unsigned MAX_PENDING = (DEEP_PIPELINE+1)*N + 3; + pipe_t pipe[PE][N+1]; + if(1) begin : blkFeed + + // Thresholding Input Guard ensuring Output FIFO is never overrun + logic signed [$clog2(MAX_PENDING):0] GuardSem = MAX_PENDING-1; // MAX_PENDING-1, ..., 0, -1 + uwire th_full = GuardSem[$left(GuardSem)]; + always_ff @(posedge clk) begin + if(rst) GuardSem <= MAX_PENDING-1; + else begin + automatic logic dec = !(USE_CONFIG && cfg_en) && !th_full && ivld; + automatic logic inc = ovld && ordy; + GuardSem <= GuardSem + (inc == dec? 0 : inc? 1 : -1); + end + end + + // PE Configuration Address Decoding + uwire cfg_sel[PE]; + if(PE == 1) assign cfg_sel[0] = 1; + else begin + for(genvar pe = 0; pe < PE; pe++) begin + assign cfg_sel[pe] = USE_CONFIG && cfg_en && (cfg_a[N+:$clog2(PE)] == pe); + end + end + + uwire ptr_t iptr; + assign iptr[0+:N] = cfg_a[0+:N]; + if(CF > 1) begin + // Channel Fold Rotation + logic [$clog2(CF)-1:0] CnlCnt = 0; + logic CnlLst = 0; + always_ff @(posedge clk) begin + if(rst) begin + CnlCnt <= 0; + CnlLst <= 0; + end + else if(!(USE_CONFIG && cfg_en) && !th_full && ivld) begin + CnlCnt <= CnlCnt + (CnlLst? 1-CF : 1); + CnlLst <= CnlCnt == CF-2; + end + end + + assign iptr[N+:$clog2(CF)] = USE_CONFIG && cfg_en? cfg_a[N+$clog2(PE)+:$clog2(CF)] : CnlCnt; + end + + for(genvar pe = 0; pe < PE; pe++) begin + assign pipe[pe][0] = '{ + op: USE_CONFIG && cfg_en? + (!cfg_sel[pe]? NOP : cfg_we? WR : RB) : + (ivld && !th_full? TH : NOP), + ptr: iptr, + val: !(USE_CONFIG && cfg_en)? idat[pe] : cfg_we? cfg_d : 0 + }; + end + + assign irdy = !(USE_CONFIG && cfg_en) && !th_full; + end : blkFeed + + //----------------------------------------------------------------------- + // Free-Running Thresholding Pipeline + for(genvar stage = 0; stage < N; stage++) begin : genStages + + localparam int unsigned SN = N-1-stage; + for(genvar pe = 0; pe < PE; pe++) begin : genPE + uwire pipe_t p = pipe[pe][stage]; + uwire cs = (p.ptr[SN:0] == 2**SN-1); + + // Threshold Memory + val_t Thresh; // Read-out register + if(1) begin : blkThresh + localparam int unsigned DEPTH = CF * 2**stage; + localparam RAM_STYLE = + DEPTH_TRIGGER_URAM && (DEPTH >= DEPTH_TRIGGER_URAM)? "ultra" : + DEPTH_TRIGGER_BRAM && (DEPTH >= DEPTH_TRIGGER_BRAM)? "block" : + // If BRAM trigger defined, force distributed memory below if Vivado may be tempted to use BRAM nonetheless. + DEPTH_TRIGGER_BRAM && (DEPTH >= 64)? "distributed" : "auto"; + + (* RAM_STYLE = RAM_STYLE *) + val_t Threshs[DEPTH]; + if(THRESHOLDS_PATH != "") begin + localparam FILE = $sformatf("%s/threshs_%0d_%0d.dat", THRESHOLDS_PATH, pe, stage); + initial $readmemh(FILE, Threshs); + end + + if(USE_CONFIG) begin : genThreshMem + uwire we = (p.op ==? WR) && cs; + if((CF == 1) && (stage == 0)) begin + always @(posedge clk) begin + if(we) Threshs[0] <= p.val; + end + end + else begin + uwire [$clog2(CF)+stage-1:0] addr = p.ptr[$clog2(CF)+N-1:SN+1]; + always @(posedge clk) begin + if(we) Threshs[addr] <= p.val; + end + end + end : genThreshMem + + if((CF == 1) && (stage == 0)) begin + assign Thresh = Threshs[0]; + end + else begin + uwire [$clog2(CF)+stage-1:0] addr = p.ptr[$clog2(CF)+N-1:SN+1]; + always_ff @(posedge clk) begin + Thresh <= Threshs[addr]; + end + end + + end : blkThresh + + // Pipeline State + pipe_t P = '{ op: NOP, default: 'x }; + logic Reval = 0; + always_ff @(posedge clk) begin + if(rst) begin + P <= '{ op: NOP, default: 'x }; + Reval <= 0; + end + else begin + P <= p; + Reval <= (p.op ==? RB) && cs; + end + end + + logic cmp; + if(!SIGNED) assign cmp = $unsigned(Thresh) <= $unsigned(P.val); + else if(!FPARG) assign cmp = $signed(Thresh) <= $signed(P.val); + else begin : blkSignedFloat + uwire mag_eq = Thresh[K-2:0] == P.val[K-2:0]; + uwire mag_le = Thresh[K-2:0] <= P.val[K-2:0]; + always_comb begin + unique case({Thresh[K-1], P.val[K-1]}) + 2'b00: cmp = mag_le; + 2'b01: cmp = 0; + 2'b10: cmp = 1; + 2'b11: cmp = !mag_le || mag_eq; + default: cmp = 'x; + endcase + end + end : blkSignedFloat + + // Pipeline State Update + pipe_t pp; + always_comb begin + pp = P; + if(P.op !=? CFG) pp.ptr[SN] = cmp; + if(Reval) pp.val = Thresh; + end + + // Pipeline State Forward (potentially additional register) + pipe_t pf; + if(!DEEP_PIPELINE) assign pf = pp; + else begin + pipe_t Pf = '{ op: NOP, default: 'x }; + always_ff @(posedge clk) begin + if(rst) Pf <= '{ op: NOP, default: 'x }; + else Pf <= pp; + end + assign pf = Pf; + end + + assign pipe[pe][stage+1] = pf; + + end : genPE + end : genStages + + //----------------------------------------------------------------------- + // Configuration Readback + always_comb begin + cfg_rack = 0; + cfg_q = 0; + foreach(pipe[pe]) begin + automatic pipe_t p = pipe[pe][N]; + cfg_rack |= p.op ==? RB; + cfg_q |= p.val; + end + end + + //----------------------------------------------------------------------- + // Stream Output through FIFO + // - Depth of N + Output Reg to allow pipe to drain entirely under backpressure + // - Typically mapped to an SRL shift register + if(1) begin : blkStreamOutput + localparam int unsigned A_DEPTH = MAX_PENDING - 1; + logic [PE-1 : 0][N-1 : 0] ADat[A_DEPTH]; + logic signed [$clog2(A_DEPTH):0] APtr = '1; // -1, 0, 1, ..., A_DEPTH-1 + uwire avld = !APtr[$left(APtr)]; + + logic [PE-1:0][N-1:0] BDat = 'x; + logic BVld = 0; + + uwire aload = pipe[0][N].op ==? TH; + uwire bload = !BVld || ordy; + + always_ff @(posedge clk) begin + if(aload) begin + assert(APtr < $signed(A_DEPTH-1)) else begin + $error("Overrun after failing stream guard."); + $stop; + end + foreach(pipe[pe]) ADat[0][pe] <= pipe[pe][N].ptr; + for(int unsigned i = 1; i < A_DEPTH; i++) ADat[i] <= ADat[i-1]; + end + end + always_ff @(posedge clk) begin + if(rst) APtr <= '1; + else APtr <= APtr + (aload == (avld && bload)? 0 : aload? 1 : -1); + end + always_ff @(posedge clk) begin + if(rst) begin + BDat <= 'x; + BVld <= 0; + end + else if(bload) begin + BDat <= ADat[APtr]; + BVld <= avld; + end + end + + assign ovld = BVld; + for(genvar pe = 0; pe < PE; pe++) begin + assign odat[pe] = BDat[pe] + BIAS; + end + end : blkStreamOutput + +endmodule : thresholding diff --git a/finn-rtllib/thresholding/hdl/thresholding_axi.sv b/finn-rtllib/thresholding/hdl/thresholding_axi.sv new file mode 100644 index 0000000000..1f235b9486 --- /dev/null +++ b/finn-rtllib/thresholding/hdl/thresholding_axi.sv @@ -0,0 +1,164 @@ +/****************************************************************************** + * Copyright (C) 2022, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * @brief All-AXI interface adapter for thresholding module. + * @author Thomas B. Preußer + * + * @description + * This AXI adapter fits the core thresholding functionality: + * - with AXI stream data interfaces with flow control + * - with implicit round-robin channel rotation as used by FINN, and + * - performs aligned byte address to parameter word address translation. + *****************************************************************************/ + +module thresholding_axi #( + int unsigned N, // output precision + int unsigned K, // input/threshold precision + int unsigned C = 1, // Channels + int unsigned PE = 1, // Processing Parallelism, requires C = k*PE + + bit SIGNED = 1, // signed inputs + bit FPARG = 0, // floating-point inputs: [sign] | exponent | mantissa + int BIAS = 0, // offsetting the output [0, 2^N-1] -> [BIAS, 2^N-1 + BIAS] + + // Initial Thresholds + parameter THRESHOLDS_PATH = "", + + bit USE_AXILITE, // Implement AXI-Lite for threshold read/write + + // Force Use of On-Chip Memory Blocks + int unsigned DEPTH_TRIGGER_URAM = 0, // if non-zero, local mems of this depth or more go into URAM (prio) + int unsigned DEPTH_TRIGGER_BRAM = 0, // if non-zero, local mems of this depth or more go into BRAM + bit DEEP_PIPELINE = 0, + + localparam int unsigned CF = C/PE, // Channel Fold + localparam int unsigned ADDR_BITS = $clog2(CF) + $clog2(PE) + N + 2, + localparam int unsigned O_BITS = BIAS >= 0? + /* unsigned */ $clog2(2**N+BIAS) : + /* signed */ 1+$clog2(-BIAS >= 2**(N-1)? -BIAS : 2**N+BIAS) +)( + //- Global Control ------------------ + input logic ap_clk, + input logic ap_rst_n, + + //- AXI Lite ------------------------ + // Writing + input logic s_axilite_AWVALID, + output logic s_axilite_AWREADY, + input logic [ADDR_BITS-1:0] s_axilite_AWADDR, // lowest 2 bits (byte selectors) are ignored + + input logic s_axilite_WVALID, + output logic s_axilite_WREADY, + input logic [31:0] s_axilite_WDATA, + input logic [ 3:0] s_axilite_WSTRB, + + output logic s_axilite_BVALID, + input logic s_axilite_BREADY, + output logic [1:0] s_axilite_BRESP, + + // Reading + input logic s_axilite_ARVALID, + output logic s_axilite_ARREADY, + input logic [ADDR_BITS-1:0] s_axilite_ARADDR, + + output logic s_axilite_RVALID, + input logic s_axilite_RREADY, + output logic [31:0] s_axilite_RDATA, + output logic [ 1:0] s_axilite_RRESP, + + //- AXI Stream - Input -------------- + output logic s_axis_tready, + input logic s_axis_tvalid, + input logic [((PE*K+7)/8)*8-1:0] s_axis_tdata, + + //- AXI Stream - Output ------------- + input logic m_axis_tready, + output logic m_axis_tvalid, + output logic [((PE*O_BITS+7)/8)*8-1:0] m_axis_tdata +); + + //----------------------------------------------------------------------- + // AXI-lite Configuration Interface + uwire cfg_en; + uwire cfg_we; + uwire [ADDR_BITS-3:0] cfg_a; + uwire [K -1:0] cfg_d; + uwire cfg_rack; + uwire [K -1:0] cfg_q; + + if(USE_AXILITE) begin + uwire [ADDR_BITS-1:0] cfg_a0; + axi4lite_if #(.ADDR_WIDTH(ADDR_BITS), .DATA_WIDTH(32), .IP_DATA_WIDTH(K)) axi ( + .aclk(ap_clk), .aresetn(ap_rst_n), + + .awready(s_axilite_AWREADY), .awvalid(s_axilite_AWVALID), .awaddr(s_axilite_AWADDR), .awprot('x), + .wready(s_axilite_WREADY), .wvalid(s_axilite_WVALID), .wdata(s_axilite_WDATA), .wstrb(s_axilite_WSTRB), + .bready(s_axilite_BREADY), .bvalid(s_axilite_BVALID), .bresp(s_axilite_BRESP), + + .arready(s_axilite_ARREADY), .arvalid(s_axilite_ARVALID), .araddr(s_axilite_ARADDR), .arprot('x), + .rready(s_axilite_RREADY), .rvalid(s_axilite_RVALID), .rresp(s_axilite_RRESP), .rdata(s_axilite_RDATA), + + .ip_en(cfg_en), .ip_wen(cfg_we), .ip_addr(cfg_a0), .ip_wdata(cfg_d), + .ip_rack(cfg_rack), .ip_rdata(cfg_q) + ); + assign cfg_a = cfg_a0[ADDR_BITS-3:0]; + always_ff @(posedge ap_clk) begin + assert(!ap_rst_n || !cfg_en || (cfg_a0[ADDR_BITS-2+:2] === 3'h0)) else begin + $error("%m: Spurious high address bits."); + $stop; + end + end + end + else begin + assign cfg_en = 0; + assign cfg_we = 'x; + assign cfg_a = 'x; + assign cfg_d = 'x; + end + + //----------------------------------------------------------------------- + // Kernel Implementation + thresholding #( + .N(N), .K(K), .C(C), .PE(PE), + .SIGNED(SIGNED), .FPARG(FPARG), .BIAS(BIAS), + .THRESHOLDS_PATH(THRESHOLDS_PATH), .USE_CONFIG(USE_AXILITE), + .DEPTH_TRIGGER_URAM(DEPTH_TRIGGER_URAM), .DEPTH_TRIGGER_BRAM(DEPTH_TRIGGER_BRAM), + .DEEP_PIPELINE(DEEP_PIPELINE) + ) impl ( + .clk(ap_clk), .rst(!ap_rst_n), + + .cfg_en, .cfg_we, .cfg_a, .cfg_d, + .cfg_rack, .cfg_q, + + .irdy(s_axis_tready), .ivld(s_axis_tvalid), .idat(s_axis_tdata), + .ordy(m_axis_tready), .ovld(m_axis_tvalid), .odat(m_axis_tdata) + ); + +endmodule : thresholding_axi diff --git a/finn-rtllib/thresholding/hdl/thresholding_template_wrapper.v b/finn-rtllib/thresholding/hdl/thresholding_template_wrapper.v new file mode 100644 index 0000000000..3f0b012ef1 --- /dev/null +++ b/finn-rtllib/thresholding/hdl/thresholding_template_wrapper.v @@ -0,0 +1,120 @@ +/** + * Copyright (c) 2023, Xilinx + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of FINN nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * @author Thomas B. Preußer + * @brief Verilog wrapper for IP packaging. + */ + +module thresholding_template_wrapper #( + parameter N = $N$, // output precision + parameter K = $M$, // input/threshold precision + parameter C = $C$, // Channels + parameter PE = $PE$, // Processing Parallelism, requires C = k*PE + + parameter SIGNED = $SIGNED$, // signed inputs + parameter FPARG = 0, // floating-point inputs: [sign] | exponent | mantissa + parameter BIAS = $BIAS$, // offsetting the output [0, 2^N-1] -> [BIAS, 2^N-1 + BIAS] + + parameter THRESHOLDS_PATH = $THRESHOLDS_PATH$, // Directory with initial threshold data + parameter USE_AXILITE = $USE_AXILITE$, // Implement AXI-Lite for threshold read/write + + // Force Use of On-Chip Memory Blocks + parameter DEPTH_TRIGGER_URAM = $DEPTH_TRIGGER_URAM$, // if non-zero, local mems of this depth or more go into URAM (prio) + parameter DEPTH_TRIGGER_BRAM = $DEPTH_TRIGGER_BRAM$, // if non-zero, local mems of this depth or more go into BRAM + parameter DEEP_PIPELINE = $DEEP_PIPELINE$, // [bit] extra pipeline stages for easier timing closure + + parameter O_BITS = $O_BITS$ +)( + // Global Control + (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF s_axilite:in0_V:out_V, ASSOCIATED_RESET ap_rst_n" *) + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *) + input ap_clk, + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) + input ap_rst_n, + + //- AXI Lite ------------------------ + // Writing + input s_axilite_AWVALID, + output s_axilite_AWREADY, + input [$clog2(C/PE) + $clog2(PE) + N + 1:0] s_axilite_AWADDR, // lowest 2 bits (byte selectors) are ignored + + input s_axilite_WVALID, + output s_axilite_WREADY, + input [31:0] s_axilite_WDATA, + input [ 3:0] s_axilite_WSTRB, + + output s_axilite_BVALID, + input s_axilite_BREADY, + output [1:0] s_axilite_BRESP, + + // Reading + input s_axilite_ARVALID, + output s_axilite_ARREADY, + input [$clog2(C/PE) + $clog2(PE) + N + 1:0] s_axilite_ARADDR, + + output s_axilite_RVALID, + input s_axilite_RREADY, + output [31:0] s_axilite_RDATA, + output [ 1:0] s_axilite_RRESP, + + //- AXI Stream - Input -------------- + output in0_V_tready, + input in0_V_tvalid, + input [((PE*K+7)/8)*8-1:0] in0_V_tdata, + + //- AXI Stream - Output ------------- + input out_V_tready, + output out_V_tvalid, + output [((PE*O_BITS+7)/8)*8-1:0] out_V_tdata +); + + thresholding_axi #( + .N(N), .K(K), .C(C), .PE(PE), + .SIGNED(SIGNED), + .FPARG(FPARG), + .BIAS(BIAS), + .THRESHOLDS_PATH(THRESHOLDS_PATH), + .USE_AXILITE(USE_AXILITE), + .DEPTH_TRIGGER_URAM(DEPTH_TRIGGER_URAM), + .DEPTH_TRIGGER_BRAM(DEPTH_TRIGGER_BRAM), + .DEEP_PIPELINE(DEEP_PIPELINE) + ) core ( + .ap_clk(ap_clk), .ap_rst_n(ap_rst_n), + + .s_axilite_AWVALID(s_axilite_AWVALID), .s_axilite_AWREADY(s_axilite_AWREADY), .s_axilite_AWADDR(s_axilite_AWADDR), + .s_axilite_WVALID(s_axilite_WVALID), .s_axilite_WREADY(s_axilite_WREADY), .s_axilite_WDATA(s_axilite_WDATA), .s_axilite_WSTRB(s_axilite_WSTRB), + .s_axilite_BVALID(s_axilite_BVALID), .s_axilite_BREADY(s_axilite_BREADY), .s_axilite_BRESP(s_axilite_BRESP), + + .s_axilite_ARVALID(s_axilite_ARVALID), .s_axilite_ARREADY(s_axilite_ARREADY), .s_axilite_ARADDR(s_axilite_ARADDR), + .s_axilite_RVALID(s_axilite_RVALID), .s_axilite_RREADY(s_axilite_RREADY), .s_axilite_RDATA(s_axilite_RDATA), .s_axilite_RRESP(s_axilite_RRESP), + .s_axis_tready(in0_V_tready), .s_axis_tvalid(in0_V_tvalid), .s_axis_tdata(in0_V_tdata), + .m_axis_tready(out_V_tready), .m_axis_tvalid(out_V_tvalid), .m_axis_tdata(out_V_tdata) + ); + +endmodule // thresholding_template_wrapper diff --git a/finn-rtllib/thresholding/sim/thresh_gen.sv b/finn-rtllib/thresholding/sim/thresh_gen.sv new file mode 100644 index 0000000000..a8a18be691 --- /dev/null +++ b/finn-rtllib/thresholding/sim/thresh_gen.sv @@ -0,0 +1,45 @@ +module thresh_gen; + localparam int unsigned K = 9; + localparam int unsigned N = 4; + localparam int unsigned C = 6; + + typedef logic [K-1:0] thresh_t; + localparam thresh_t THRESHOLDS[C][2**N-1] = '{ + '{ 'h00, 'h01, 'h02, 'h03, 'h04, 'h05, 'h06, 'h07, 'h08, 'h09, 'h0a, 'h0b, 'h0c, 'h0d, 'h0e }, + '{ 'h10, 'h11, 'h12, 'h13, 'h14, 'h15, 'h16, 'h17, 'h18, 'h19, 'h1a, 'h1b, 'h1c, 'h1d, 'h1e }, + '{ 'h20, 'h21, 'h22, 'h23, 'h24, 'h25, 'h26, 'h27, 'h28, 'h29, 'h2a, 'h2b, 'h2c, 'h2d, 'h2e }, + '{ 'h30, 'h31, 'h32, 'h33, 'h34, 'h35, 'h36, 'h37, 'h38, 'h39, 'h3a, 'h3b, 'h3c, 'h3d, 'h3e }, + '{ 'h40, 'h41, 'h42, 'h43, 'h44, 'h45, 'h46, 'h47, 'h48, 'h49, 'h4a, 'h4b, 'h4c, 'h4d, 'h4e }, + '{ 'h50, 'h51, 'h52, 'h53, 'h54, 'h55, 'h56, 'h57, 'h58, 'h59, 'h5a, 'h5b, 'h5c, 'h5d, 'h5e } + }; + localparam THRESHOLDS_PATH = "."; + + localparam int unsigned PE = 2; + localparam int unsigned CF = C/PE; + + for(genvar stage = 0; stage < N; stage++) begin + localparam int unsigned SN = N-1-stage; + for(genvar pe = 0; pe < PE; pe++) begin + initial begin + automatic string file = $sformatf("%s/threshs_%0d_%0d.dat", THRESHOLDS_PATH, pe, stage); + + automatic thresh_t threshs[CF * 2**stage]; + for(int unsigned c = 0; c < CF; c++) begin + for(int unsigned i = 0; i < 2**stage; i++) begin + threshs[(c << stage) + i] = THRESHOLDS[c*PE + pe][(i<<(N-stage)) + 2**SN-1]; + end + end + + $writememh(file, threshs); + end + end + end + + // Quit after running all initializers + initial begin + #1ns; + $display("Generation done."); + $finish; + end + +endmodule : thresh_gen diff --git a/finn-rtllib/thresholding/sim/thresholding.tcl b/finn-rtllib/thresholding/sim/thresholding.tcl new file mode 100644 index 0000000000..82dc59deb1 --- /dev/null +++ b/finn-rtllib/thresholding/sim/thresholding.tcl @@ -0,0 +1,17 @@ +create_project -force thresholding thresholding.vivado -part xcvc1902-vsva2197-2MP-e-S +set_property board_part xilinx.com:vck190:part0:2.2 [current_project] + +read_verilog hdl/axilite_if.v +read_verilog -sv { hdl/thresholding.sv hdl/thresholding_axi.sv } + +set simset [current_fileset -simset] +set_property -name xsim.simulate.log_all_signals -value true -objects $simset +set_property -name xsim.simulate.runtime -value all -objects $simset +add_files -fileset $simset { sim/thresholding_tb.sv sim/thresholding_axi_tb.sv } + +foreach top { thresholding_tb thresholding_axi_tb } { + set_property top $top $simset + + launch_simulation + close_sim +} diff --git a/finn-rtllib/thresholding/sim/thresholding_axi_tb.sv b/finn-rtllib/thresholding/sim/thresholding_axi_tb.sv new file mode 100644 index 0000000000..918f539d15 --- /dev/null +++ b/finn-rtllib/thresholding/sim/thresholding_axi_tb.sv @@ -0,0 +1,314 @@ +/****************************************************************************** + * Copyright (C) 2022, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * @brief Testbench for thresholding_axi. + * @author Monica Chiosa + * + */ + +module thresholding_axi_tb #( + int unsigned N = 4, // output precision + int unsigned C = 6, // number of channels + int unsigned PE = 2, + real M0 = 7.3, // slope of the uniform thresholding line + real B0 = 3.1, // offset of the uniform thresholding line + bit THROTTLED = 1, + + localparam int unsigned CF = C/PE, // Channel Fold + localparam int unsigned ADDR_BITS = $clog2(CF) + $clog2(PE) + N + 2 +); + + //----------------------------------------------------------------------- + // Design Geometry + + // For each channel = [0,channel): + // M_channel = M0 + CX*channel + // B_channel = B0 + CX*channel + // Input/threshold precision computed according with the maximum posible value + localparam real CX = 1.375; + localparam int unsigned K = $clog2((2**N-1)*(M0+C*CX) + (B0+C*CX)); // unused sign + magnitude + localparam int unsigned C_BITS = C < 2? 1 : $clog2(C); + + localparam int unsigned MST_STRM_WROUNDS = 503; + + typedef int unsigned threshs_t[C][2**N-1]; + function threshs_t init_thresholds(); + automatic threshs_t res; + for(int unsigned c = 0; c < C; c++) begin + automatic real m = M0 + c*CX; + automatic real b = B0 + c*CX; + foreach(res[c][i]) begin + res[c][i] = int'($ceil(m*i + b)); + end + end + return res; + endfunction : init_thresholds + localparam threshs_t THRESHS = init_thresholds(); + + //----------------------------------------------------------------------- + // Clock and Reset Control + logic clk = 0; + always #5ns clk = !clk; + logic rst = 1; + initial begin + #10ns; + @(posedge clk); + rst <= 0; + end + + //----------------------------------------------------------------------- + // DUT + logic s_axilite_AWVALID; + uwire s_axilite_AWREADY; + logic [ADDR_BITS-1:0] s_axilite_AWADDR; // lowest 2 bits (byte selectors) are ignored + logic s_axilite_WVALID; + uwire s_axilite_WREADY; + logic [ 31:0] s_axilite_WDATA; + uwire s_axilite_BVALID; + logic s_axilite_BREADY; + uwire [ 1:0] s_axilite_BRESP; + logic s_axilite_ARVALID; + uwire s_axilite_ARREADY; + logic [ADDR_BITS-1:0] s_axilite_ARADDR; + uwire s_axilite_RVALID; + uwire s_axilite_RREADY = 1; + uwire [ 31:0] s_axilite_RDATA; + uwire [ 1:0] s_axilite_RRESP; + + uwire irdy; + logic ivld; + logic [PE-1:0][K-1:0] idat; + + logic ordy = 0; + uwire ovld; + uwire [PE-1:0][N-1:0] odat; + + thresholding_axi #(.N(N), .K(K), .C(C), .PE(PE), .SIGNED(0), .USE_AXILITE(1)) dut ( + .ap_clk(clk), .ap_rst_n(!rst), + + // Configuration + .s_axilite_AWVALID, .s_axilite_AWREADY, .s_axilite_AWADDR, + .s_axilite_WVALID, .s_axilite_WREADY, .s_axilite_WDATA, .s_axilite_WSTRB('1), + .s_axilite_BVALID, .s_axilite_BREADY, .s_axilite_BRESP, + .s_axilite_ARVALID, .s_axilite_ARREADY, .s_axilite_ARADDR, + .s_axilite_RVALID, .s_axilite_RREADY, .s_axilite_RDATA, .s_axilite_RRESP, + + // Stream Processing + .s_axis_tready(irdy), .s_axis_tvalid(ivld), .s_axis_tdata(idat), + .m_axis_tready(ordy), .m_axis_tvalid(ovld), .m_axis_tdata(odat) + ); + + //----------------------------------------------------------------------- + // Input Stimuli + typedef logic [PE-1:0][K-1:0] input_t; + typedef logic [$clog2(CF)+$clog2(PE)+N-1:0] addr_t; + input_t QW[$]; // Input Feed Tracing + addr_t QC[$]; + + int unsigned error_cnt = 0; + bit done = 0; + initial begin + // Report testbench details + $display("Testbench - tresholding K=%0d -> N=%0d", K, N); + for(int unsigned c = 0; c < C; c++) begin + $write("Channel #%0d: Thresholds = {", c); + for(int unsigned i = 0; i < 2**N-1; i++) $write(" %0d", THRESHS[c][i]); + $display(" }"); + end + + // Config + s_axilite_AWVALID = 0; + s_axilite_AWADDR = 'x; + s_axilite_WVALID = 0; + s_axilite_WDATA = 'x; + s_axilite_BREADY = 0; + s_axilite_ARVALID = 0; + s_axilite_ARADDR = 'x; + + // Stream Input + ivld = 0; + idat = 'x; + + @(posedge clk iff !rst); + + // Threshold Configuration + for(int unsigned c = 0; c < C; c+=PE) begin + automatic addr_t addr = 0; + if(CF > 1) addr[N+$clog2(PE)+:$clog2(CF)] = c/PE; + for(int unsigned pe = 0; pe < PE; pe++) begin + if(PE > 1) addr[N+:$clog2(PE)] = pe; + for(int unsigned t = 0; t < 2**N-1; t++) begin + addr[0+:N] = t; + fork + begin + s_axilite_AWVALID <= 1; + s_axilite_AWADDR <= { addr, 2'b00 }; + @(posedge clk iff s_axilite_AWREADY); + s_axilite_AWVALID <= 0; + s_axilite_AWADDR <= 'x; + end + begin + s_axilite_WVALID <= 1; + s_axilite_WDATA <= THRESHS[c+pe][t]; + @(posedge clk iff s_axilite_WREADY); + s_axilite_WVALID <= 0; + s_axilite_WDATA <= 'x; + end + begin + s_axilite_BREADY <= 1; + @(posedge clk iff s_axilite_BVALID); + assert(s_axilite_BRESP == '0) else begin + $error("Error on parameter write."); + $stop; + end + s_axilite_BREADY <= 0; + end + join + end + end + end + + fork + // Intermittent configuration readback + while(!done) begin + if(($urandom()%37) != 0) begin + s_axilite_ARVALID <= 0; + s_axilite_ARADDR <= 'x; + @(posedge clk); + end + else begin + automatic addr_t addr = $urandom()%(N-1); + if(PE > 1) addr[N+:$clog2(PE)] = $urandom()%PE; + if(CF > 1) addr[N+$clog2(PE)+:$clog2(CF)] = $urandom()%CF; + + s_axilite_ARVALID <= 1; + s_axilite_ARADDR <= { addr, 2'b00 }; + @(posedge clk iff s_axilite_ARREADY); + + QC.push_back(addr); + end + end + + // AXI4Stream MST Writes input values + repeat(MST_STRM_WROUNDS) begin + automatic input_t dat; + + while(THROTTLED && ($urandom()%7 == 0)) @(posedge clk); + + std::randomize(dat); + ivld <= 1; + idat <= dat; + @(posedge clk iff irdy); + ivld <= 0; + idat <= 'x; + QW.push_back(dat); + end + join_any + done <= 1; + repeat(N+6) @(posedge clk); + + assert(QW.size() == 0) else begin + $error("Missing %0d outputs.", QW.size()); + $stop; + end + assert(QC.size() == 0) else begin + $error("Missing %0d readback replies.", QC.size()); + $stop; + end + + $display("Test completed: %0d errors in %0d tests.", error_cnt, MST_STRM_WROUNDS); + $display("========================================="); + $finish; + end + + // Output Checker ------------------------------------------------------- + + // Configuration Readback + always_ff @(posedge clk iff s_axilite_RVALID) begin + assert(s_axilite_RRESP == '0) else begin + $error("Read back error."); + $stop; + end + assert(QC.size()) begin + automatic addr_t addr = QC.pop_front(); + automatic int unsigned cnl = + (CF == 1? 0 : addr[N+$clog2(PE)+:$clog2(CF)] * PE) + + (PE == 1? 0 : addr[N+:$clog2(PE)]); + automatic logic [K-1:0] exp = THRESHS[cnl][addr[0+:N]]; + assert(s_axilite_RDATA == exp) else begin + $error("Readback mismatch on #%0d.%0d: %0d instead of %0d", cnl, addr[0+:N], s_axilite_RDATA, exp); + $stop; + end + end + else begin + $error("Spurious readback output."); + $stop; + end + end + + // Stream Output + int unsigned OCnl = 0; + always @(posedge clk) begin + if(rst) begin + OCnl <= 0; + ordy <= 1'b0; + end + else begin + if(!ordy || ovld) ordy <= ($urandom()%5 != 0) || !THROTTLED; + + if(ordy && ovld) begin + assert(QW.size()) begin + automatic input_t x = QW.pop_front(); + + for(int unsigned pe = 0; pe < PE; pe++) begin + automatic int unsigned cnl = OCnl + pe; + + $display("Mapped CNL=%0d DAT=%3d -> #%2d", cnl, x[pe], odat[pe]); + assert( + ((odat[pe] == 0) || (THRESHS[cnl][odat[pe]-1] <= x[pe])) && + ((odat[pe] == 2**N-1) || (x[pe] < THRESHS[cnl][odat[pe]])) + ) else begin + $error("Output error on presumed input CNL=%0d DAT=0x%0x -> #%0d", cnl, x[pe], odat[pe]); + error_cnt++; + $stop; + end + end + end + else begin + $error("Spurious output."); + $stop; + end + + OCnl <= (OCnl + PE)%C; + end + end + end + +endmodule: thresholding_axi_tb diff --git a/finn-rtllib/thresholding/sim/thresholding_tb.sv b/finn-rtllib/thresholding/sim/thresholding_tb.sv new file mode 100644 index 0000000000..e42145f10e --- /dev/null +++ b/finn-rtllib/thresholding/sim/thresholding_tb.sv @@ -0,0 +1,274 @@ +/****************************************************************************** + * Copyright (C) 2022, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * @brief Testbench for thresholding_axi. + * @author Monica Chiosa + * + */ + +module thresholding_tb #( + int unsigned K = 10, // input precision + int unsigned N = 4, // output precision + int unsigned C = 6, // number of channels + int unsigned PE = 2, + + localparam int unsigned CF = C/PE // Channel Fold +); + localparam bit DEEP_PIPELINE = 1; + + localparam int unsigned MST_STRM_WROUNDS = 507; + localparam bit THROTTLED = 1; + + //----------------------------------------------------------------------- + // Clock and Reset Control + logic clk = 0; + always #5ns clk = !clk; + logic rst = 1; + initial begin + #10ns; + @(posedge clk); + rst <= 0; + end + + //----------------------------------------------------------------------- + // Parallel Instances differing in Data Type + typedef logic [K -1:0] val_t; + typedef val_t threshs_t[C][2**N-1]; + typedef val_t [PE-1:0] input_t; + typedef logic [$clog2(CF)+$clog2(PE)+N-1:0] addr_t; + logic [0:2] term = '0; + always_comb begin + if(&term) $finish; + end + for(genvar i = 0; i < 3; i++) begin : genTypes + localparam bit SIGNED = i>0; + localparam bit FPARG = i>1; + + //- DUT ------------------------- + logic cfg_en; + logic cfg_we; + logic [$clog2(C)+N-1:0] cfg_a; + logic [K-1:0] cfg_d; + uwire cfg_rack; + uwire [K-1:0] cfg_q; + + uwire irdy; + logic ivld; + logic [PE-1:0][K-1:0] idat; + + logic ordy = 0; + uwire ovld; + uwire [PE-1:0][N-1:0] odat; + + thresholding #(.N(N), .K(K), .C(C), .PE(PE), .SIGNED(SIGNED), .FPARG(FPARG), .USE_CONFIG(1), .DEEP_PIPELINE(DEEP_PIPELINE)) dut ( + .clk, .rst, + + // Configuration + .cfg_en, .cfg_we, .cfg_a, .cfg_d, + .cfg_rack, .cfg_q, + + // Stream Processing + .irdy, .ivld, .idat, + .ordy, .ovld, .odat + ); + + //- Stimulus Driver ------------- + threshs_t THRESHS; + function val_t sigord(input val_t x); + automatic val_t res = x; + if(SIGNED) begin + if(FPARG && x[K-1]) res[K-2:0] = ~x[K-2:0]; + res[K-1] = !x[K-1]; + end + return res; + endfunction : sigord + + input_t QW[$]; // Input tracing + addr_t QC[$]; // Readback tracking + int unsigned error_cnt = 0; + bit done = 0; + initial begin + + // Generate thresholds + std::randomize(THRESHS); + foreach(THRESHS[c]) begin + val_t row[2**N-1] = THRESHS[c]; + row.sort with (sigord(item)); + THRESHS[c] = row; + end + + // Report test case details + $display("[%0d] Thresholding %s%s%0d -> uint%0d", i, SIGNED? "s" : "u", FPARG? "fp" : "int", K, N); + for(int unsigned c = 0; c < C; c++) begin + $write("[%0d] Channel #%0d: Thresholds = {", i, c); + for(int unsigned i = 0; i < 2**N-1; i++) $write(" %0X", THRESHS[c][i]); + $display(" }"); + end + + // Config + cfg_en = 0; + cfg_we = 'x; + cfg_a = 'x; + cfg_d = 'x; + + // Stream Input + ivld = 0; + idat = 'x; + + @(posedge clk iff !rst); + + // Threshold Configuratin + cfg_en <= 1; + cfg_we <= 1; + for(int unsigned c = 0; c < C; c+=PE) begin + if(CF > 1) cfg_a[N+$clog2(PE)+:$clog2(CF)] <= c/PE; + for(int unsigned pe = 0; pe < PE; pe++) begin + if(PE > 1) cfg_a[N+:$clog2(PE)] = pe; + for(int unsigned t = 0; t < 2**N-1; t++) begin + cfg_a[0+:N] <= t; + cfg_d <= THRESHS[c+pe][t]; + @(posedge clk); + end + end + end + cfg_d <= 'x; + + fork + // Intermittent configuration readback + while(!done) begin + cfg_en <= 0; + cfg_we <= 'x; + cfg_a <= 'x; + @(posedge clk); + if(($urandom()%41) == 0) begin + automatic addr_t addr = $urandom()%(N-1); + if(PE > 1) addr[N+:$clog2(PE)] = $urandom()%PE; + if(CF > 1) addr[N+$clog2(PE)+:$clog2(CF)] = $urandom()%CF; + + cfg_en <= 1; + cfg_we <= 0; + cfg_a <= addr; + @(posedge clk); + QC.push_back(addr); + end + end + + // AXI4Stream MST Writes input values + repeat(MST_STRM_WROUNDS) begin + automatic input_t dat; + + while(THROTTLED && ($urandom()%7 == 0)) @(posedge clk); + + std::randomize(dat); + ivld <= 1; + idat <= dat; + @(posedge clk iff irdy); + ivld <= 0; + idat <= 'x; + QW.push_back(dat); + end + join_any + done <= 1; + repeat((DEEP_PIPELINE+1)*N+6) @(posedge clk); + + assert(QW.size() == 0) else begin + $error("[%0d] Missing %0d outputs.", i, QW.size()); + $stop; + end + assert(QC.size() == 0) else begin + $error("[%0d] Missing %0d readback replies.", i, QC.size()); + $stop; + end + + $display("[%0d] Test completed: %0d errors in %0d tests.", i, error_cnt, MST_STRM_WROUNDS); + $display("============================================="); + term[i] <= 1; + end + + //- Readback Checker -------------- + always_ff @(posedge clk iff cfg_rack) begin + assert(QC.size()) begin + automatic addr_t addr = QC.pop_front(); + automatic int unsigned cnl = + (CF == 1? 0 : addr[N+$clog2(PE)+:$clog2(CF)] * PE) + + (PE == 1? 0 : addr[N+:$clog2(PE)]); + automatic logic [K-1:0] exp = THRESHS[cnl][addr[0+:N]]; + assert(cfg_q == exp) else begin + $error("[%0d] Readback mismatch on #%0d.%0d: %0d instead of %0d", i, cnl, addr[0+:N], cfg_q, exp); + $stop; + end + end + else begin + $error("[%0d] Spurious readback output.", i); + $stop; + end + end + + // Output Checker + int unsigned OCnl = 0; + always @(posedge clk) begin + if(rst) begin + OCnl <= 0; + ordy <= 1'b0; + end + else begin + if(!ordy || ovld) ordy <= ($urandom()%5 != 0) || !THROTTLED; + + if(ordy && ovld) begin + assert(QW.size()) begin + automatic input_t x = QW.pop_front(); + + for(int unsigned pe = 0; pe < PE; pe++) begin + automatic int unsigned cnl = OCnl + pe; + + $display("[%0d] Mapped CNL=%0d DAT=%3x -> #%2d", i, cnl, x[pe], odat[pe]); + assert( + ((odat[pe] == 0) || (sigord(THRESHS[cnl][odat[pe]-1]) <= sigord(x[pe]))) && + ((odat[pe] == 2**N-1) || (sigord(x[pe]) < sigord(THRESHS[cnl][odat[pe]]))) + ) else begin + $error("[%0d] Output error on presumed input CNL=%0d DAT=0x%0x -> #%0d", i, cnl, x[pe], odat[pe]); + error_cnt++; + $stop; + end + end + end + else begin + $error("[%0d] Spurious output.", i); + $stop; + end + + OCnl <= (OCnl + PE)%C; + end + end + end + + end : genTypes + +endmodule: thresholding_tb diff --git a/finn-rtllib/thresholding/xgui/thresholding_axi_v1_0.tcl b/finn-rtllib/thresholding/xgui/thresholding_axi_v1_0.tcl new file mode 100644 index 0000000000..338304fa40 --- /dev/null +++ b/finn-rtllib/thresholding/xgui/thresholding_axi_v1_0.tcl @@ -0,0 +1,187 @@ + +# Loading additional proc with user specified bodies to compute parameter values. +source [file join [file dirname [file dirname [info script]]] gui/thresholding_axi_v1_0.gtcl] + +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "ADDR_BITS" -parent ${Page_0} + ipgui::add_param $IPINST -name "BIAS" -parent ${Page_0} + ipgui::add_param $IPINST -name "C" -parent ${Page_0} + ipgui::add_param $IPINST -name "CF" -parent ${Page_0} + ipgui::add_param $IPINST -name "FPARG" -parent ${Page_0} + ipgui::add_param $IPINST -name "K" -parent ${Page_0} + ipgui::add_param $IPINST -name "N" -parent ${Page_0} + ipgui::add_param $IPINST -name "O_BITS" -parent ${Page_0} + set PE [ipgui::add_param $IPINST -name "PE" -parent ${Page_0}] + set_property tooltip {PE Count} ${PE} + ipgui::add_param $IPINST -name "SIGNED" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.ADDR_BITS { PARAM_VALUE.ADDR_BITS PARAM_VALUE.C PARAM_VALUE.PE PARAM_VALUE.N } { + # Procedure called to update ADDR_BITS when any of the dependent parameters in the arguments change + + set ADDR_BITS ${PARAM_VALUE.ADDR_BITS} + set C ${PARAM_VALUE.C} + set PE ${PARAM_VALUE.PE} + set N ${PARAM_VALUE.N} + set values(C) [get_property value $C] + set values(PE) [get_property value $PE] + set values(N) [get_property value $N] + set_property value [gen_USERPARAMETER_ADDR_BITS_VALUE $values(C) $values(PE) $values(N)] $ADDR_BITS +} + +proc validate_PARAM_VALUE.ADDR_BITS { PARAM_VALUE.ADDR_BITS } { + # Procedure called to validate ADDR_BITS + return true +} + +proc update_PARAM_VALUE.CF { PARAM_VALUE.CF PARAM_VALUE.C PARAM_VALUE.PE } { + # Procedure called to update CF when any of the dependent parameters in the arguments change + + set CF ${PARAM_VALUE.CF} + set C ${PARAM_VALUE.C} + set PE ${PARAM_VALUE.PE} + set values(C) [get_property value $C] + set values(PE) [get_property value $PE] + set_property value [gen_USERPARAMETER_CF_VALUE $values(C) $values(PE)] $CF +} + +proc validate_PARAM_VALUE.CF { PARAM_VALUE.CF } { + # Procedure called to validate CF + return true +} + +proc update_PARAM_VALUE.O_BITS { PARAM_VALUE.O_BITS PARAM_VALUE.BIAS PARAM_VALUE.N } { + # Procedure called to update O_BITS when any of the dependent parameters in the arguments change + + set O_BITS ${PARAM_VALUE.O_BITS} + set BIAS ${PARAM_VALUE.BIAS} + set N ${PARAM_VALUE.N} + set values(BIAS) [get_property value $BIAS] + set values(N) [get_property value $N] + set_property value [gen_USERPARAMETER_O_BITS_VALUE $values(BIAS) $values(N)] $O_BITS +} + +proc validate_PARAM_VALUE.O_BITS { PARAM_VALUE.O_BITS } { + # Procedure called to validate O_BITS + return true +} + +proc update_PARAM_VALUE.BIAS { PARAM_VALUE.BIAS } { + # Procedure called to update BIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.BIAS { PARAM_VALUE.BIAS } { + # Procedure called to validate BIAS + return true +} + +proc update_PARAM_VALUE.C { PARAM_VALUE.C } { + # Procedure called to update C when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C { PARAM_VALUE.C } { + # Procedure called to validate C + return true +} + +proc update_PARAM_VALUE.FPARG { PARAM_VALUE.FPARG } { + # Procedure called to update FPARG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPARG { PARAM_VALUE.FPARG } { + # Procedure called to validate FPARG + return true +} + +proc update_PARAM_VALUE.K { PARAM_VALUE.K } { + # Procedure called to update K when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.K { PARAM_VALUE.K } { + # Procedure called to validate K + return true +} + +proc update_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to update N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to validate N + return true +} + +proc update_PARAM_VALUE.PE { PARAM_VALUE.PE } { + # Procedure called to update PE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PE { PARAM_VALUE.PE } { + # Procedure called to validate PE + return true +} + +proc update_PARAM_VALUE.SIGNED { PARAM_VALUE.SIGNED } { + # Procedure called to update SIGNED when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SIGNED { PARAM_VALUE.SIGNED } { + # Procedure called to validate SIGNED + return true +} + + +proc update_MODELPARAM_VALUE.N { MODELPARAM_VALUE.N PARAM_VALUE.N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.N}] ${MODELPARAM_VALUE.N} +} + +proc update_MODELPARAM_VALUE.K { MODELPARAM_VALUE.K PARAM_VALUE.K } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.K}] ${MODELPARAM_VALUE.K} +} + +proc update_MODELPARAM_VALUE.C { MODELPARAM_VALUE.C PARAM_VALUE.C } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C}] ${MODELPARAM_VALUE.C} +} + +proc update_MODELPARAM_VALUE.PE { MODELPARAM_VALUE.PE PARAM_VALUE.PE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PE}] ${MODELPARAM_VALUE.PE} +} + +proc update_MODELPARAM_VALUE.SIGNED { MODELPARAM_VALUE.SIGNED PARAM_VALUE.SIGNED } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SIGNED}] ${MODELPARAM_VALUE.SIGNED} +} + +proc update_MODELPARAM_VALUE.FPARG { MODELPARAM_VALUE.FPARG PARAM_VALUE.FPARG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPARG}] ${MODELPARAM_VALUE.FPARG} +} + +proc update_MODELPARAM_VALUE.BIAS { MODELPARAM_VALUE.BIAS PARAM_VALUE.BIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.BIAS}] ${MODELPARAM_VALUE.BIAS} +} + +proc update_MODELPARAM_VALUE.CF { MODELPARAM_VALUE.CF PARAM_VALUE.CF } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CF}] ${MODELPARAM_VALUE.CF} +} + +proc update_MODELPARAM_VALUE.ADDR_BITS { MODELPARAM_VALUE.ADDR_BITS PARAM_VALUE.ADDR_BITS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ADDR_BITS}] ${MODELPARAM_VALUE.ADDR_BITS} +} + +proc update_MODELPARAM_VALUE.O_BITS { MODELPARAM_VALUE.O_BITS PARAM_VALUE.O_BITS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.O_BITS}] ${MODELPARAM_VALUE.O_BITS} +} diff --git a/src/finn/custom_op/fpgadataflow/__init__.py b/src/finn/custom_op/fpgadataflow/__init__.py index d6c0794b00..c29a805b62 100644 --- a/src/finn/custom_op/fpgadataflow/__init__.py +++ b/src/finn/custom_op/fpgadataflow/__init__.py @@ -63,6 +63,9 @@ from finn.custom_op.fpgadataflow.streamingfifo import StreamingFIFO from finn.custom_op.fpgadataflow.streamingmaxpool_batch import StreamingMaxPool_Batch from finn.custom_op.fpgadataflow.thresholding_batch import Thresholding_Batch +from finn.custom_op.fpgadataflow.thresholding_binary_search import ( + Thresholding_Binary_Search, +) from finn.custom_op.fpgadataflow.tlastmarker import TLastMarker from finn.custom_op.fpgadataflow.upsampler import UpsampleNearestNeighbour_Batch from finn.custom_op.fpgadataflow.vectorvectoractivation import VectorVectorActivation @@ -86,6 +89,7 @@ custom_op["FMPadding_Batch"] = FMPadding_Batch custom_op["FMPadding_Pixel"] = FMPadding_Pixel custom_op["Thresholding_Batch"] = Thresholding_Batch +custom_op["Thresholding_Binary_Search"] = Thresholding_Binary_Search custom_op["AddStreams_Batch"] = AddStreams_Batch custom_op["LabelSelect_Batch"] = LabelSelect_Batch custom_op["DuplicateStreams_Batch"] = DuplicateStreams_Batch diff --git a/src/finn/custom_op/fpgadataflow/thresholding_binary_search.py b/src/finn/custom_op/fpgadataflow/thresholding_binary_search.py new file mode 100755 index 0000000000..d02b778823 --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/thresholding_binary_search.py @@ -0,0 +1,579 @@ +# Copyright (C) 2022, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import numpy as np +import os +import warnings +from qonnx.core.datatype import DataType +from qonnx.util.basic import interleave_matrix_outer_dim_from_partitions + +from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp +from finn.util.basic import find_next_power_of_2, get_rtlsim_trace_depth, make_build_dir +from finn.util.data_packing import ( + npy_to_rtlsim_input, + pack_innermost_dim_as_hex_string, + rtlsim_output_to_npy, +) + +try: + from pyverilator import PyVerilator +except ModuleNotFoundError: + PyVerilator = None + +"""@package thresholding_binary_search +- ONNX i/o tensor shape assumptions for Thresholding: +- input 0 is the input tensor, shape (..., NumChannels) +- input 1 is the threshold tensor, shape (NumChannels, n_thres) +- output 0 is the output tensor, shape (..., NumChannels) - same as input +- the '...' here can be any shape (representing groups of vectors) + +This module creates an RTL IP, HLS is not supported. See 'thresholding_batch' +for a HLS equivalent. +""" + + +class Thresholding_Binary_Search(HLSCustomOp): + """Class that corresponds to finn-rtllib 'thresholding' function.""" + + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) + + def get_nodeattr_types(self): + my_attrs = { + # parallelization; channels thresholded per cycle + "PE": ("i", True, 0), + # number of channels (each may have different thresholds) + "NumChannels": ("i", True, 0), + # number of steps in thresholding function. Used only in decoupled mode + "numSteps": ("i", True, 1), + # FINN DataTypes for inputs, outputs + "inputDataType": ("s", True, ""), + "weightDataType": ("s", True, ""), + "outputDataType": ("s", True, ""), + # number of input vectors, examples: + # [1] is a single vector (like a FC layer with batch=1) + # [4] is four vectors (like a FC layer with batch=4) + # [1, 4, 4] is four * four vectors (like a conv layer with batch=1) + "numInputVectors": ("ints", False, [1]), + # name of the top module in verilog template. Used by PyVerilator + # and IPI generation + "gen_top_module": ("s", False, ""), + # bias to be applied to outputs of the node + "activation_bias": ("i", False, 0), + } + my_attrs.update(super().get_nodeattr_types()) + return my_attrs + + def calc_tmem(self): + """Calculates and returns TMEM.""" + num_channels = self.get_nodeattr("NumChannels") + pe = self.get_nodeattr("PE") + return num_channels // pe + + def make_shape_compatible_op(self, model): + oshape = self.get_normal_output_shape() + return super().make_const_shape_op(oshape) + + def infer_node_datatype(self, model): + """Used for FINN DataType inference: set the output tensors' datatypes + accordingly for this node""" + node = self.onnx_node + idt = model.get_tensor_datatype(node.input[0]) + if idt != self.get_input_datatype(): + warn_str = "inputDataType changing for %s: %s -> %s " % ( + node.name, + str(self.get_input_datatype().name), + str(idt.name), + ) + warnings.warn(warn_str) + self.set_nodeattr("inputDataType", idt.name) + # set output datatype from property + odt = self.get_output_datatype() + model.set_tensor_datatype(node.output[0], odt) + + def verify_node(self): + """Required by the FINN nalysis module. Checks if custom ops in graph + are correctly built, with all attributes and inputs.""" + return [] + + def bram_estimation(self): + return 0 + + def lut_estimation(self): + return 0 + + def get_input_datatype(self, ind=0): + return DataType[self.get_nodeattr("inputDataType")] + + def get_output_datatype(self, ind=0): + return DataType[self.get_nodeattr("outputDataType")] + + def get_weight_datatype(self): + """The term 'weights' and 'thresholds' are used interchangably in this class.""" + return DataType[self.get_nodeattr("weightDataType")] + + def minimize_accumulator_width(self, model): + "Minimize threshold width ('accumulator width' here due to convention)" + thresholds = model.get_initializer(self.onnx_node.input[1]) + threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds) + min_threshold = thresholds.min() + max_threshold = thresholds.max() + min_input = self.get_input_datatype().min() + max_input = self.get_input_datatype().max() + # get range required by threshold values + tdt_min = min(min_input, min_threshold) + tdt_max = max(max_input, max_threshold) + if tdt_min < 0: + if abs(tdt_min) > tdt_max: + tdt = DataType.get_smallest_possible(tdt_min) + else: + tdt = DataType.get_smallest_possible(-tdt_max - 1) + else: + tdt = DataType.get_smallest_possible(tdt_max) + assert np.vectorize(tdt.allowed)( + threshold_tensor + ).all(), "Thresholds can't be expressed with type %s" % str(tdt) + self.set_nodeattr("weightDataType", tdt.name) + return DataType[self.get_nodeattr("weightDataType")] + + def get_instream_width(self, ind=0): + i_bits = self.get_input_datatype().bitwidth() + return i_bits * self.get_nodeattr("PE") + + def get_outstream_width(self, ind=0): + o_bits = self.get_output_datatype().bitwidth() + return o_bits * self.get_nodeattr("PE") + + def get_weightstream_width(self): + """Returns weight stream width""" + pe = self.get_nodeattr("PE") + wp = self.get_weight_datatype().bitwidth() + n_thres_steps = self.get_nodeattr("numSteps") + w_width = pe * wp * n_thres_steps + return w_width + + def get_folded_input_shape(self, ind=0): + fold = self.calc_tmem() + pe = self.get_nodeattr("PE") + vecs = list(self.get_nodeattr("numInputVectors")) + folded_input_shape = tuple(vecs + [fold, pe]) + return folded_input_shape + + def get_folded_output_shape(self, ind=0): + # same shape as input + return self.get_folded_input_shape() + + def get_normal_input_shape(self, ind=0): + num_channels = self.get_nodeattr("NumChannels") + vecs = list(self.get_nodeattr("numInputVectors")) + normal_input_shape = tuple(vecs + [num_channels]) + return normal_input_shape + + def get_normal_output_shape(self, ind=0): + # same shape as input + return self.get_normal_input_shape() + + def get_number_output_values(self): + return 0 + + def get_exp_cycles(self): + return 0 + + def get_hls_compatible_threshold_tensor(self, orig_thres_matrix): + """Convert the original numpy weight matrix orig_weight_matrix into + a form suitable for passing to the hlslib call: + * ensure MH % PE == 0 + * for unsigned inputs, ensure thresholds are positive + * interleave rows between PEs + * reshape into (PE, TMEM, n_thres_steps) and return + """ + mh = self.get_nodeattr("NumChannels") + pe = self.get_nodeattr("PE") + tmem = mh // pe + assert mh % pe == 0, "Requirement NumChannels divisable by PE is violated." + assert ( + orig_thres_matrix.ndim == 2 + ), """Threshold matrix dimension is + not as expected (2).""" + n_thres_steps = orig_thres_matrix.shape[1] + assert n_thres_steps == self.get_nodeattr( + "numSteps" + ), "Mismatch in threshold steps" + if not self.get_input_datatype().signed(): + # ensure all thresholds are nonnegative + assert (orig_thres_matrix >= 0).all() + # ensure all thresholds are integer + assert np.equal( + np.mod(orig_thres_matrix, 1), 0 + ).all(), "Need int threshold tensor" + ret = orig_thres_matrix + # ensure channels = mh , duplicating if necessary + if ret.shape[0] == 1: + ret = np.tile(ret, (mh, 1)) + assert ( + ret.shape[0] == mh + ), "Channels of threshold matrix are not as expected (mh)" + # distribute rows between PEs + ret = interleave_matrix_outer_dim_from_partitions(ret, pe) + assert ( + ret.shape[0] == pe + ), """First dimension after distribution of the + rows between PEs is not as expected (pe)""" + assert ( + ret.shape[1] == tmem + ), """Second dimension after distribution of the + rows between PEs is not as expected (tmem)""" + assert ( + ret.shape[2] == n_thres_steps + ), """Third dimension after distribution of the + rows between PEs is not as expected (n_thres_steps)""" + return ret.reshape(1, pe, tmem, n_thres_steps) + + def prepare_codegen_rtl_values(self): + """All dictionary values produced in this function are to replace + their key value(s) in the RTL template files""" + code_gen_dict = {} + + # Identify the module name + code_gen_dict["$MODULE_NAME_AXI_WRAPPER$"] = [ + self.get_verilog_top_module_name() + "_axi_wrapper" + ] + # Set the top module name - AXI wrapper + code_gen_dict["$TOP_MODULE$"] = code_gen_dict["$MODULE_NAME_AXI_WRAPPER$"] + + # Identify the module variables + output_data_type = self.get_nodeattr("outputDataType") # output precision + input_data_type = self.get_nodeattr( + "inputDataType" + ) # input/threshold precision + num_channels = self.get_nodeattr("NumChannels") # number of channels + bias = self.get_nodeattr("activation_bias") # activation bias value + pe = self.get_nodeattr("PE") + + code_gen_dict["$N$"] = [ + str(DataType[output_data_type].bitwidth()) + ] # output precision - convert bitwidth to string + code_gen_dict["$M$"] = [ + str(DataType[input_data_type].bitwidth()) + ] # input/threshold precision - convert bitwidth to string + code_gen_dict["$C$"] = [str(num_channels)] # number of channels + code_gen_dict["$BIAS$"] = [str(bias)] # activation bias value + code_gen_dict["$PE$"] = [str(pe)] # requires C = M*PE + + # Is the input datatype signed or unsigned? + # The thresholding core needs to know this when comparing weights to inputs + if self.get_input_datatype().signed(): + code_gen_dict["$SIGNED$"] = [str(1)] + else: + code_gen_dict["$SIGNED$"] = [str(0)] + + return code_gen_dict + + def get_rtl_file_list(self): + """Thresholding binary search RTL file list""" + return ["thresholding.sv", "thresholding_axi.sv", "thresholding_axi_wrapper.v"] + + def get_rtl_file_paths(self): + """Get full path of all RTL files""" + rtl_root_dir = os.environ["FINN_ROOT"] + "/finn-rtllib/thresholding/hdl/" + rtl_file_list = self.get_rtl_file_list() + rtl_file_paths = [rtl_root_dir + file for file in rtl_file_list] + return rtl_file_paths + + def get_rtl_template_data(self, path): + """Return RTL file contents as a template""" + with open(path, "r") as f: + template = f.read() + return template + + def fill_in_rtl_template_data(self, replace_dict, template_data): + """Use attribute values to finn in RTL template placeholders""" + template_data_cp = template_data + for key in replace_dict: + replacement_line = "\n".join(replace_dict[key]) + template_data_cp = template_data_cp.replace(key, replacement_line) + return template_data_cp + + def dump_rtl_data(self, dest_dir, filename, data): + """Dump filled-in-template RTL files for future synthesis step""" + with open(os.path.join(dest_dir, filename), "w") as f: + f.write(data) + return + + def generate_hdl(self): + """Prepare HDL files from templates for synthesis""" + # Generate a dictionary of values to put in RTL template + code_gen_dict = self.prepare_codegen_rtl_values() + + # Retrieve the destination directory for the final RTL files + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + + for rtl_file_path in self.get_rtl_file_paths(): + # read in original RTL template file + template_data = self.get_rtl_template_data(rtl_file_path) + # apply code generation to templates + data = self.fill_in_rtl_template_data(code_gen_dict, template_data) + # dump filled-in template to destination directory for compilation + file_only_path = rtl_file_path.split("/")[-1] + self.dump_rtl_data(code_gen_dir, file_only_path, data) + + # Before we return - set the 'gen_top_module' attribute for use later + # by PyVerilator and IPI generation + self.set_nodeattr("gen_top_module", code_gen_dict["$TOP_MODULE$"][0]) + return + + def code_generation_ipgen(self, model, fpgapart, clk): + self.generate_hdl() + + # set ipgen_path and ip_path so that HLS-Synth transformation + # and stich_ip transformation do not complain + # i.e. during the HLSSynthIP() transformation + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + self.set_nodeattr("ipgen_path", code_gen_dir) + self.set_nodeattr("ip_path", code_gen_dir) + return + + def prepare_rtlsim(self): + """Creates a Verilator emulation library for the RTL code generated + for this node, sets the rtlsim_so attribute to its path and returns + a PyVerilator wrapper around it.""" + + if PyVerilator is None: + raise ImportError("Installation of PyVerilator is required.") + + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + verilog_paths = [code_gen_dir] + verilog_files = self.get_rtl_file_list() + + # build the Verilator emulation library + sim = PyVerilator.build( + verilog_files, + build_dir=make_build_dir("pyverilator_" + self.onnx_node.name + "_"), + verilog_path=verilog_paths, + trace_depth=get_rtlsim_trace_depth(), + top_module_name=self.get_nodeattr("gen_top_module"), + ) + + # save generated lib filename in attribute + self.set_nodeattr("rtlsim_so", sim.lib._name) + return sim + + def execute_node(self, context, graph): + # Perform input checks + if self.get_nodeattr("exec_mode") != "rtlsim": + raise Exception( + "Invalid exec_mode value: {}; exec_mode must be set to '{}'".format( + self.get_nodeattr("exec_mode"), "rtlsim" + ) + ) + + node = self.onnx_node + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + + # create a npy file fore each input of the node (in_ind is input index) + in_ind = 0 + for inputs in node.input: + # it is assumed that the first input of the node is the data input + # the second input are the weights + # the third input are the thresholds + if in_ind == 0: + assert ( + str(context[inputs].dtype) == "float32" + ), """Input datatype is + not float32 as expected.""" + expected_inp_shape = self.get_folded_input_shape() + reshaped_input = context[inputs].reshape(expected_inp_shape) + + if self.get_input_datatype() == DataType["BIPOLAR"]: + # store bipolar activations as binary + reshaped_input = (reshaped_input + 1) / 2 + export_idt = DataType["BINARY"] + else: + export_idt = self.get_input_datatype() + + # make copy before saving the array + reshaped_input = reshaped_input.copy() + np.save( + os.path.join(code_gen_dir, "input_{}.npy".format(in_ind)), + reshaped_input, + ) + elif in_ind > 2: + raise Exception("Unexpected input found for Thresholding_Binary_Search") + in_ind += 1 + + # Create a PyVerilator wrapper of the RTLSim .so + sim = self.get_rtlsim() + nbits = self.get_instream_width() + inp = npy_to_rtlsim_input( + "{}/input_0.npy".format(code_gen_dir), export_idt, nbits + ) + + super().reset_rtlsim(sim) + super().toggle_clk(sim) + + wnbits = self.get_weightstream_width() + export_wdt = self.get_weight_datatype() + wei = npy_to_rtlsim_input( + "{}/thresholds.npy".format(code_gen_dir), export_wdt, wnbits + ) + num_w_reps = np.prod(self.get_nodeattr("numInputVectors")) + io_dict = { + "inputs": {"in0": inp, "weights": wei * num_w_reps}, + "outputs": {"s_axis": []}, + } + self.rtlsim_multi_io(sim, io_dict) + output = io_dict["outputs"]["out"] + + # Manage output data + odt = self.get_output_datatype() + target_bits = odt.bitwidth() + packed_bits = self.get_outstream_width() + out_npy_path = "{}/output.npy".format(code_gen_dir) + out_shape = self.get_folded_output_shape() + + rtlsim_output_to_npy( + output, out_npy_path, odt, out_shape, packed_bits, target_bits + ) + + # load and reshape output + output = np.load(out_npy_path) + oshape = self.get_normal_output_shape() + output = np.asarray([output], dtype=np.float32).reshape(*oshape) + context[node.output[0]] = output + return + + def code_generation_ipi(self): + """Constructs and returns the TCL commands for node instantiation as an RTL + block.""" + cmd = [] + rtl_file_list = self.get_rtl_file_list() + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + + for rtl_file in rtl_file_list: + cmd.append( + "add_files -norecurse %s" % (os.path.join(code_gen_dir, rtl_file)) + ) + + # Create an RTL block, not an IP core (-type ip) + cmd.append( + "create_bd_cell -type module -reference %s %s" + % (self.get_nodeattr("gen_top_module"), self.onnx_node.name) + ) + + return cmd + + def get_verilog_top_module_intf_names(self): + """Return a dict of names of input and output interfaces. + The keys reflect the protocols each interface implements: + 'clk', 'rst', 'm_axis', 's_axis', 'aximm', 'axilite'. + Values are lists of tuples (axis, aximm) or names (axilite): + 'axis' tuples correspond to the list of node inputs in order, + each tuple is (interface_name, interface_width_bits). + axilite always assumed to be 32 bits and is not tuple (name only). + Each block must have at most one aximm and one axilite.""" + + intf_names = super().get_verilog_top_module_intf_names() + intf_names["axilite"] = ["s_axilite"] + return intf_names + + def get_dynamic_config(self, model, address_stride=1): + """Returns a configuration dictionary containing axilite write commands + in order to program the thresholds into the RTL core during runtime. + The default address stride for the weights is 1 byte.""" + + thresholds = model.get_initializer(self.onnx_node.input[1]) + num_channels, num_weights_per_channel = thresholds.shape + + weight_addr_boundary = find_next_power_of_2(num_weights_per_channel) + # Make sure that the next power of 2 (output) is greater than the input + assert weight_addr_boundary >= num_weights_per_channel + + config = {} + channel_cntr = 0 + for channel in thresholds: + channel_start_addr = channel_cntr * weight_addr_boundary * address_stride + weight_cntr = 0 + addr = 0 + for weight in channel: + key_name = "{}_{}{}_{}{}".format( + "axilite", "ch", str(channel_cntr), "w", str(weight_cntr) + ) + config[key_name] = ( + channel_start_addr + addr, + int( + str( + pack_innermost_dim_as_hex_string( + [weight], + self.get_weight_datatype(), + self.get_weight_datatype().bitwidth(), + ) + ), + 0, + ), + ) + + weight_cntr += 1 + addr += address_stride + + channel_cntr += 1 + + return config + + def ipgen_singlenode_code(self): + """Normally: Builds the bash script for IP generation.""" + """This is needed for the HLSSynthIP() transformation. + This is an IP, not a HLS node, so therefore provide an empty hook + to prevent any HLS synthesis.""" + pass + + def global_includes(self): + pass + + def defines(self, var): + pass + + def read_npy_data(self): + pass + + def strm_decl(self): + pass + + def docompute(self): + pass + + def dataoutstrm(self): + pass + + def save_as_npy(self): + pass + + def blackboxfunction(self): + pass + + def pragmas(self): + pass diff --git a/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py b/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py index ef02453498..a50cbbaed1 100644 --- a/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py +++ b/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py @@ -1019,9 +1019,10 @@ def apply(self, model): class InferThresholdingLayer(Transformation): """Convert any MultiThreshold into a standalone thresholding HLS layer.""" - def __init__(self, mem_mode="const"): + def __init__(self, mem_mode="const", use_rtl_variant=False): super().__init__() self.mem_mode = mem_mode + self.use_rtl_variant = use_rtl_variant def apply(self, model): graph = model.graph @@ -1073,27 +1074,65 @@ def apply(self, model): ) actval = int(actval) assert (not odt.signed()) or (actval < 0), ( - node.name + ": Signed output requres actval < 0" - ) - # create and insert new Thresholding_Batch node - new_node = helper.make_node( - "Thresholding_Batch", - [thl_input, thl_threshold], - [thl_output], - domain="finn.custom_op.fpgadataflow", - backend="fpgadataflow", - NumChannels=ifc, - PE=pe, - numSteps=thl_thres_shape[1], - inputDataType=idt.name, - # weightDataType can be tightened by MinimizeAccumulatorWidth - weightDataType=idt.name, - outputDataType=odt.name, - numInputVectors=list(thl_in_shape[:-1]), - ActVal=actval, - mem_mode=self.mem_mode, - name="Thresholding_Batch_" + node.name, + node.name + ": Signed output requires actval < 0" ) + + # Ensure that RTL variant is not inserted for unsupported configuration + is_rtl_variant_compatible = True + + # Perform checks for RTL variant if chosen + if self.use_rtl_variant: + assert self.mem_mode == "decoupled", ( + """%s : RTL Thresholding only supports 'decoupled' memory + mode.""" + % node.name + ) + + if self.use_rtl_variant and is_rtl_variant_compatible: + new_node = helper.make_node( + "Thresholding_Binary_Search", + [thl_input, thl_threshold], + [thl_output], + domain="finn.custom_op.fpgadataflow", + backend="fpgadataflow", + NumChannels=ifc, + PE=pe, + numSteps=thl_thres_shape[1], + inputDataType=idt.name, + weightDataType=idt.name, + outputDataType=odt.name, + numInputVectors=list(thl_in_shape[:-1]), + activation_bias=actval, + mem_mode=self.mem_mode, + name="Thresholding_Binary_Search_" + node.name, + ) + else: + if self.use_rtl_variant: + warnings.warn( + """%s : RTL Thresholding requested for unsupported + configuration. Falling back to HLS implementation.""" + % node.name + ) + + # create and insert new Thresholding_Batch node + new_node = helper.make_node( + "Thresholding_Batch", + [thl_input, thl_threshold], + [thl_output], + domain="finn.custom_op.fpgadataflow", + backend="fpgadataflow", + NumChannels=ifc, + PE=pe, + numSteps=thl_thres_shape[1], + inputDataType=idt.name, + weightDataType=idt.name, + outputDataType=odt.name, + numInputVectors=list(thl_in_shape[:-1]), + ActVal=actval, + mem_mode=self.mem_mode, + name="Thresholding_Batch_" + node.name, + ) + graph.node.insert(insert_point, new_node) # remove old node graph.node.remove(node) diff --git a/src/finn/util/basic.py b/src/finn/util/basic.py index 1796738c58..5252422dcf 100644 --- a/src/finn/util/basic.py +++ b/src/finn/util/basic.py @@ -228,3 +228,22 @@ def is_exe(fpath): return exe_file return None + + +def find_next_power_of_2(n): + """For any integer 'n', find the next greatest power of 2""" + # Negative values will loop infinitely below - return 0 + if n <= 0: + return 0 + # If '1' is requested, output will be '0' in the loop below, avoid this now. + elif n == 1: + return 2 # i.e. 2**1 + + # decrement 'n' (to handle cases when `n` itself is a power of 2) + n = n - 1 + + # loop until only one bit is left + while n & n - 1: + # unset rightmost bit + n = n & n - 1 + return n << 1 diff --git a/tests/fpgadataflow/test_convert_to_hls_thresholding.py b/tests/fpgadataflow/test_convert_to_hls_thresholding.py new file mode 100755 index 0000000000..9c233bdd06 --- /dev/null +++ b/tests/fpgadataflow/test_convert_to_hls_thresholding.py @@ -0,0 +1,276 @@ +# Copyright (C) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import pytest + +import numpy as np +from onnx import TensorProto, helper +from pyverilator.util.axi_utils import axilite_write, reset_rtlsim +from qonnx.core.datatype import DataType +from qonnx.core.modelwrapper import ModelWrapper +from qonnx.custom_op.general.multithreshold import multithreshold +from qonnx.custom_op.registry import getCustomOp +from qonnx.transformation.general import GiveUniqueNodeNames +from qonnx.transformation.infer_datatypes import InferDataTypes +from qonnx.transformation.infer_shapes import InferShapes +from qonnx.util.basic import gen_finn_dt_tensor +from test_fpgadataflow_thresholding_binary_search import ( + make_single_thresholding_binary_search_modelwrapper, +) + +import finn.transformation.fpgadataflow.convert_to_hls_layers as to_hls +from finn.core.rtlsim_exec import rtlsim_exec +from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP +from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP +from finn.transformation.fpgadataflow.insert_fifo import InsertFIFO +from finn.transformation.fpgadataflow.prepare_ip import PrepareIP + +test_fpga_part = "xczu3eg-sbva484-1-e" +target_clk_ns = 5 + + +# Helper functions +def sort_thresholds_increasing(thresholds): + return np.sort(thresholds, axis=1) + + +def generate_random_threshold_values(input_data_type, num_input_channels, num_steps): + return np.random.randint( + input_data_type.min(), + input_data_type.max() + 1, + (num_input_channels, num_steps), + ).astype(np.float32) + + +def generate_pe_value(fold, num_input_channels): + if fold == -1: + fold = num_input_channels + pe = num_input_channels // fold + assert num_input_channels % pe == 0 + return pe + + +# n = batch, c = channel, h = height, w = width of feature map +# Standard = NCHW; FINN = NHWC +# Convert from NCHW to NHWC +def convert_np_array_to_finn_data_layout(data): + return np.transpose(data, (0, 2, 3, 1)) + + +# n = batch, c = channel, h = height, w = width of feature map +# Standard = NCHW; FINN = NHWC +# Convert from NHWC to NCHW +def convert_np_array_to_standard_data_layout(data): + return np.transpose(data, (0, 3, 1, 2)) + + +def make_single_multithresholding_modelwrapper( + thresholds, + pe, + input_data_type, + output_data_type, + activation_bias, + num_input_vecs, +): + NumChannels = thresholds.shape[0] + + inp = helper.make_tensor_value_info( + "inp", TensorProto.FLOAT, num_input_vecs + [NumChannels] + ) + outp = helper.make_tensor_value_info( + "outp", TensorProto.FLOAT, num_input_vecs + [NumChannels] + ) + + node_inp_list = ["inp", "thresh"] + + Multithresholding_node = helper.make_node( + "MultiThreshold", + node_inp_list, + ["outp"], + domain="qonnx.custom_op.general", + out_dtype=output_data_type.name, + out_bias=float(activation_bias), + out_scale=1.0, + ) + + graph = helper.make_graph( + nodes=[Multithresholding_node], + name="multithresholding_graph", + inputs=[inp], + outputs=[outp], + ) + + model = helper.make_model(graph, producer_name="multithresholding-model") + model = ModelWrapper(model) + model = model.transform(InferShapes()) + model = model.transform(InferDataTypes()) + model = model.transform(GiveUniqueNodeNames()) + + model.set_tensor_datatype("inp", input_data_type) + model.set_tensor_datatype("outp", output_data_type) + + model.set_tensor_datatype("thresh", input_data_type) + model.set_initializer("thresh", thresholds) + return model + + +# N.B. Fold values where C % PE != 0 fail +@pytest.mark.parametrize("activation", [DataType["INT4"], DataType["BIPOLAR"]]) +@pytest.mark.parametrize("input_data_type", [DataType["INT16"], DataType["UINT16"]]) +@pytest.mark.parametrize("fold", [-1, 1, 2, 4, 6]) +@pytest.mark.parametrize("num_input_channels", [16]) +@pytest.mark.fpgadataflow +@pytest.mark.vivado +def test_convert_to_hls_tbs_rtl_variant( + activation, + input_data_type, + fold, + num_input_channels, +): + # Handle inputs to the test + pe = generate_pe_value(fold, num_input_channels) + num_steps = activation.get_num_possible_values() - 1 + + # See convert_to_hls_layers::InferThresholdingLayer: + # assert (not odt.signed()) or (actval < 0) + # This implies that it expects a negative activation, BIPOLAR does not provide that + if activation == DataType["BIPOLAR"]: + pytest.skip( + "Only negative activations are supported for " + "RTL Thresholding Binary Search node" + ) + + # Other non-input parameters + num_input_vecs = [1, 2, 2] + output_data_type = activation + if output_data_type == DataType["BIPOLAR"]: + activation_bias = 0 + else: + activation_bias = output_data_type.min() + + # generate random input data + tensor_shape = tuple(num_input_vecs + [num_input_channels]) + x = gen_finn_dt_tensor(input_data_type, tensor_shape) + + # Generate random thresholds and sort in ascending order + thresholds = generate_random_threshold_values( + input_data_type, num_input_channels, num_steps + ) + + # provide non-decreasing/ascending thresholds + thresholds = sort_thresholds_increasing(thresholds) + + x_nhwc = convert_np_array_to_standard_data_layout(x) + y = multithreshold(x_nhwc, thresholds) + + # convert back to NHWC for comparison to hw outputs + y = convert_np_array_to_finn_data_layout(y) + if activation == DataType["BIPOLAR"]: + # binary to bipolar + y = 2 * y - 1 + else: + # signed offset + y += activation.min() + + # Generate model from input parameters to the test + model = make_single_thresholding_binary_search_modelwrapper( + thresholds, + pe, + input_data_type, + output_data_type, + activation_bias, + num_input_vecs, + ) + + model = model.transform(InsertFIFO(True)) + model = model.transform(GiveUniqueNodeNames()) + model = model.transform(PrepareIP(test_fpga_part, target_clk_ns)) + model = model.transform(HLSSynthIP()) + model = model.transform(CreateStitchedIP(test_fpga_part, target_clk_ns)) + + # Retrieve the axilite programming sequence for weights - for decoupled mode only + tbs_node = model.get_nodes_by_op_type("Thresholding_Binary_Search")[0] + tbs_inst = getCustomOp(tbs_node) + config = tbs_inst.get_dynamic_config(model, 4) + + # Reshape generated data (not from model) + oshape = model.get_tensor_shape("outp") + y_expected = y.reshape(oshape) + + # Helper function that delivers the hook to program the thresholds via AXI-Lite + def config_hook(config): + if config is None: + return None + + def write_thresh_config(sim): + # axi_name = "s_axilite_0_" # works + axi_name = getCustomOp( + model.get_nodes_by_op_type("Thresholding_Binary_Search")[0] + ).get_verilog_top_module_intf_names()["axilite"][0] + axi_name += "_0_" + + # Write config registers to the Threshold memory. + # The dictionary defines (addr, value) tuples. + for config_entry in config.values(): + addr = config_entry[0] + val = config_entry[1] + axilite_write(sim, addr, val, basename=axi_name) + + reset_rtlsim(sim) + + return write_thresh_config + + input_dict = {"inp": x} + rtlsim_exec(model, input_dict, pre_hook=config_hook(config)) + y_produced = input_dict["outp"] + assert (y_produced == y_expected).all() + + # Make a Multithreshold graph and convert to thresholding binary search node + new_model = make_single_multithresholding_modelwrapper( + thresholds, + pe, + input_data_type, + output_data_type, + activation_bias, + num_input_vecs, + ) + + # Recreate the model using the ConvertToHLS transform + new_model = new_model.transform( + to_hls.InferThresholdingLayer(mem_mode="decoupled", use_rtl_variant=True) + ) + new_model = new_model.transform(InsertFIFO(True)) + new_model = new_model.transform(GiveUniqueNodeNames()) + new_model = new_model.transform(PrepareIP(test_fpga_part, target_clk_ns)) + new_model = new_model.transform(HLSSynthIP()) + new_model = new_model.transform(CreateStitchedIP(test_fpga_part, target_clk_ns)) + + input_dict = {"inp": x} + rtlsim_exec(new_model, input_dict, pre_hook=config_hook(config)) + y_produced_new = input_dict["outp"] + assert (y_produced_new == y_expected).all() diff --git a/tests/fpgadataflow/test_fpgadataflow_thresholding_binary_search.py b/tests/fpgadataflow/test_fpgadataflow_thresholding_binary_search.py new file mode 100755 index 0000000000..24b60f5ea5 --- /dev/null +++ b/tests/fpgadataflow/test_fpgadataflow_thresholding_binary_search.py @@ -0,0 +1,287 @@ +# Copyright (C) 2022, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import pytest + +import numpy as np +from onnx import TensorProto, helper +from pyverilator.util.axi_utils import axilite_write, reset_rtlsim +from qonnx.core.datatype import DataType +from qonnx.core.modelwrapper import ModelWrapper +from qonnx.custom_op.general.multithreshold import multithreshold +from qonnx.custom_op.registry import getCustomOp +from qonnx.transformation.general import GiveUniqueNodeNames +from qonnx.util.basic import gen_finn_dt_tensor + +from finn.core.rtlsim_exec import rtlsim_exec +from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP +from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP +from finn.transformation.fpgadataflow.insert_fifo import InsertFIFO +from finn.transformation.fpgadataflow.prepare_ip import PrepareIP +from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim +from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode + +test_fpga_part = "xczu3eg-sbva484-1-e" +target_clk_ns = 5 + + +# Helper functions +def sort_thresholds_increasing(thresholds): + return np.sort(thresholds, axis=1) + + +def generate_random_threshold_values(input_data_type, num_input_channels, num_steps): + return np.random.randint( + input_data_type.min(), + input_data_type.max() + 1, + (num_input_channels, num_steps), + ).astype(np.float32) + + +def generate_pe_value(fold, num_input_channels): + if fold == -1: + fold = num_input_channels + pe = num_input_channels // fold + assert num_input_channels % pe == 0 + return pe + + +# n = batch, c = channel, h = height, w = width of feature map +# Standard = NCHW; FINN = NHWC +# Convert from NCHW to NHWC +def convert_np_array_to_finn_data_layout(data): + return np.transpose(data, (0, 2, 3, 1)) + + +# n = batch, c = channel, h = height, w = width of feature map +# Standard = NCHW; FINN = NHWC +# Convert from NHWC to NCHW +def convert_np_array_to_standard_data_layout(data): + return np.transpose(data, (0, 3, 1, 2)) + + +def make_single_thresholding_binary_search_modelwrapper( + thresholds, + pe, + input_data_type, + output_data_type, + activation_bias, + num_input_vecs, +): + + NumChannels = thresholds.shape[0] + + inp = helper.make_tensor_value_info( + "inp", TensorProto.FLOAT, num_input_vecs + [NumChannels] + ) + outp = helper.make_tensor_value_info( + "outp", TensorProto.FLOAT, num_input_vecs + [NumChannels] + ) + + node_inp_list = ["inp", "thresh"] + + Thresholding_node = helper.make_node( + "Thresholding_Binary_Search", + node_inp_list, + ["outp"], + domain="finn.custom_op.fpgadataflow", + backend="fpgadataflow", + NumChannels=NumChannels, + PE=pe, + numSteps=thresholds.shape[1], + inputDataType=input_data_type.name, + weightDataType=input_data_type.name, + outputDataType=output_data_type.name, + activation_bias=activation_bias, + numInputVectors=num_input_vecs, + ) + graph = helper.make_graph( + nodes=[Thresholding_node], + name="thresholding_graph", + inputs=[inp], + outputs=[outp], + ) + + model = helper.make_model(graph, producer_name="thresholding-model") + model = ModelWrapper(model) + + model.set_tensor_datatype("inp", input_data_type) + model.set_tensor_datatype("outp", output_data_type) + + model.set_tensor_datatype("thresh", input_data_type) + model.set_initializer("thresh", thresholds) + return model + + +# Test brief: Test that PrepareRTLSim() runs successfully. This function is not +# tested in test_fpgadataflow_thresholding_binary_search() +@pytest.mark.fpgadataflow +@pytest.mark.vivado +def test_fpgadataflow_thresholding_binary_search_prepare_rtlsim(): + input_data_type = DataType["INT16"] + act = DataType["INT4"] + fold = -1 + num_input_channels = 16 + + # Handle inputs to the test + pe = generate_pe_value(fold, num_input_channels) + num_steps = act.get_num_possible_values() - 1 + + # Generate random, non-decreasing thresholds + thresholds = generate_random_threshold_values( + input_data_type, num_input_channels, num_steps + ) + thresholds = sort_thresholds_increasing(thresholds) + + # Other non-input parameters + num_input_vecs = [1, 2, 2] + output_data_type = act + if output_data_type == DataType["BIPOLAR"]: + activation_bias = 0 + else: + activation_bias = output_data_type.min() + + # Generate model from input parameters to the test + model = make_single_thresholding_binary_search_modelwrapper( + thresholds, + pe, + input_data_type, + output_data_type, + activation_bias, + num_input_vecs, + ) + + model = model.transform(SetExecMode("rtlsim")) + model = model.transform(GiveUniqueNodeNames()) + model = model.transform(PrepareIP(test_fpga_part, target_clk_ns)) + model = model.transform(HLSSynthIP()) + model = model.transform(PrepareRTLSim()) + return + + +# Test brief: Create a Thresholding binary search layer using various parameters +# and test against a SW generated & simulated dataset +# N.B. Fold values where C % PE != 0 fail +@pytest.mark.parametrize("activation", [DataType["INT4"], DataType["BIPOLAR"]]) +@pytest.mark.parametrize("input_data_type", [DataType["INT16"], DataType["UINT16"]]) +@pytest.mark.parametrize("fold", [-1, 1, 2, 4, 6]) +@pytest.mark.parametrize("num_input_channels", [16]) +@pytest.mark.fpgadataflow +@pytest.mark.vivado +@pytest.mark.slow +def test_fpgadataflow_thresholding_binary_search( + activation, input_data_type, fold, num_input_channels +): + # Handle inputs to the test + pe = generate_pe_value(fold, num_input_channels) + num_steps = activation.get_num_possible_values() - 1 + + # Other non-input parameters + num_input_vecs = [1, 2, 2] + output_data_type = activation + if output_data_type == DataType["BIPOLAR"]: + activation_bias = 0 + else: + activation_bias = output_data_type.min() + + # generate random input data + tensor_shape = tuple(num_input_vecs + [num_input_channels]) + x = gen_finn_dt_tensor(input_data_type, tensor_shape) + + # Generate random thresholds and sort in ascending order + thresholds = generate_random_threshold_values( + input_data_type, num_input_channels, num_steps + ) + + # provide non-decreasing/ascending thresholds + thresholds = sort_thresholds_increasing(thresholds) + + x_nhwc = convert_np_array_to_standard_data_layout(x) + y = multithreshold(x_nhwc, thresholds) + + # convert back to NHWC for comparison to hw outputs + y = convert_np_array_to_finn_data_layout(y) + if activation == DataType["BIPOLAR"]: + # binary to bipolar + y = 2 * y - 1 + else: + # signed offset + y += activation.min() + + # Generate model from input parameters to the test + model = make_single_thresholding_binary_search_modelwrapper( + thresholds, + pe, + input_data_type, + output_data_type, + activation_bias, + num_input_vecs, + ) + + model = model.transform(InsertFIFO(True)) + model = model.transform(GiveUniqueNodeNames()) + model = model.transform(PrepareIP(test_fpga_part, target_clk_ns)) + model = model.transform(HLSSynthIP()) + model = model.transform(CreateStitchedIP(test_fpga_part, target_clk_ns)) + + # Retrieve the axilite programming sequence for weights - for decoupled mode only + tbs_node = model.get_nodes_by_op_type("Thresholding_Binary_Search")[0] + tbs_inst = getCustomOp(tbs_node) + config = tbs_inst.get_dynamic_config(model, 4) + + # Reshape generated data (not from model) + oshape = model.get_tensor_shape("outp") + y_expected = y.reshape(oshape) + + # Helper function that delivers the hook to program the thresholds via AXI-Lite + def config_hook(config): + if config is None: + return None + + def write_thresh_config(sim): + # axi_name = "s_axilite_0_" # works + axi_name = getCustomOp( + model.get_nodes_by_op_type("Thresholding_Binary_Search")[0] + ).get_verilog_top_module_intf_names()["axilite"][0] + axi_name += "_0_" + + # Write config registers to the Threshold memory. + # The dictionary defines (addr, value) tuples. + for config_entry in config.values(): + addr = config_entry[0] + val = config_entry[1] + axilite_write(sim, addr, val, basename=axi_name) + + reset_rtlsim(sim) + + return write_thresh_config + + input_dict = {"inp": x} + rtlsim_exec(model, input_dict, pre_hook=config_hook(config)) + y_produced = input_dict["outp"] + assert (y_produced == y_expected).all() diff --git a/tests/util/test_basic.py b/tests/util/test_basic.py new file mode 100755 index 0000000000..97a8c50261 --- /dev/null +++ b/tests/util/test_basic.py @@ -0,0 +1,60 @@ +# Copyright (C) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import pytest + +import finn.util.basic as basic + + +@pytest.mark.util +def test_next_power_of_2(): + test_vector = [ + {"input": -2, "expected_result": 0}, + {"input": -1, "expected_result": 0}, + {"input": 0, "expected_result": 0}, + {"input": 1, "expected_result": 2}, + {"input": 2, "expected_result": 2}, + {"input": 3, "expected_result": 4}, + {"input": 4, "expected_result": 4}, + {"input": 7, "expected_result": 8}, + {"input": 8, "expected_result": 8}, + {"input": 11, "expected_result": 16}, + {"input": 15, "expected_result": 16}, + {"input": 16, "expected_result": 16}, + {"input": 18, "expected_result": 32}, + {"input": 27, "expected_result": 32}, + {"input": 31, "expected_result": 32}, + {"input": 32, "expected_result": 32}, + {"input": 42, "expected_result": 64}, + {"input": 65, "expected_result": 128}, + ] + + for test_dict in test_vector: + output = basic.find_next_power_of_2(test_dict["input"]) + assert output >= test_dict["input"] + assert output == test_dict["expected_result"] From ffcca3c005f83ef768024bc1da18578fb2139c83 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Mon, 15 Jan 2024 16:21:31 +0000 Subject: [PATCH 378/665] [BTS-RTLLIB] Fix threshold weight file path --- finn-rtllib/thresholding/hdl/thresholding.sv | 3 +-- finn-rtllib/thresholding/sim/thresh_gen.sv | 4 ++-- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/finn-rtllib/thresholding/hdl/thresholding.sv b/finn-rtllib/thresholding/hdl/thresholding.sv index 75fbb61a4d..dc612f387f 100644 --- a/finn-rtllib/thresholding/hdl/thresholding.sv +++ b/finn-rtllib/thresholding/hdl/thresholding.sv @@ -209,8 +209,7 @@ module thresholding #( (* RAM_STYLE = RAM_STYLE *) val_t Threshs[DEPTH]; if(THRESHOLDS_PATH != "") begin - localparam FILE = $sformatf("%s/threshs_%0d_%0d.dat", THRESHOLDS_PATH, pe, stage); - initial $readmemh(FILE, Threshs); + initial $readmemh($sformatf("%sthreshs_%0d_%0d.dat", THRESHOLDS_PATH, pe, stage), Threshs); end if(USE_CONFIG) begin : genThreshMem diff --git a/finn-rtllib/thresholding/sim/thresh_gen.sv b/finn-rtllib/thresholding/sim/thresh_gen.sv index a8a18be691..713723aafa 100644 --- a/finn-rtllib/thresholding/sim/thresh_gen.sv +++ b/finn-rtllib/thresholding/sim/thresh_gen.sv @@ -12,7 +12,7 @@ module thresh_gen; '{ 'h40, 'h41, 'h42, 'h43, 'h44, 'h45, 'h46, 'h47, 'h48, 'h49, 'h4a, 'h4b, 'h4c, 'h4d, 'h4e }, '{ 'h50, 'h51, 'h52, 'h53, 'h54, 'h55, 'h56, 'h57, 'h58, 'h59, 'h5a, 'h5b, 'h5c, 'h5d, 'h5e } }; - localparam THRESHOLDS_PATH = "."; + localparam THRESHOLDS_PATH = "./"; localparam int unsigned PE = 2; localparam int unsigned CF = C/PE; @@ -21,7 +21,7 @@ module thresh_gen; localparam int unsigned SN = N-1-stage; for(genvar pe = 0; pe < PE; pe++) begin initial begin - automatic string file = $sformatf("%s/threshs_%0d_%0d.dat", THRESHOLDS_PATH, pe, stage); + automatic string file = $sformatf("%sthreshs_%0d_%0d.dat", THRESHOLDS_PATH, pe, stage); automatic thresh_t threshs[CF * 2**stage]; for(int unsigned c = 0; c < CF; c++) begin From ce0ebbceaad67604011a634677152c9bb6d3620c Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Mon, 15 Jan 2024 16:25:52 +0000 Subject: [PATCH 379/665] [BTS-RTLLIB] Use templates for module wrapper name --- finn-rtllib/thresholding/hdl/thresholding_template_wrapper.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/finn-rtllib/thresholding/hdl/thresholding_template_wrapper.v b/finn-rtllib/thresholding/hdl/thresholding_template_wrapper.v index 3f0b012ef1..79e7ad1bb7 100644 --- a/finn-rtllib/thresholding/hdl/thresholding_template_wrapper.v +++ b/finn-rtllib/thresholding/hdl/thresholding_template_wrapper.v @@ -31,7 +31,7 @@ * @brief Verilog wrapper for IP packaging. */ -module thresholding_template_wrapper #( +module $MODULE_NAME_AXI_WRAPPER$ #( parameter N = $N$, // output precision parameter K = $M$, // input/threshold precision parameter C = $C$, // Channels @@ -117,4 +117,4 @@ module thresholding_template_wrapper #( .m_axis_tready(out_V_tready), .m_axis_tvalid(out_V_tvalid), .m_axis_tdata(out_V_tdata) ); -endmodule // thresholding_template_wrapper +endmodule // $MODULE_NAME_AXI_WRAPPER$ From 5384739c6a34134f88d199d32cb63643fd005bdc Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Mon, 15 Jan 2024 16:26:53 +0000 Subject: [PATCH 380/665] [BTS-RTLLIB] Upper case signal names --- .../hdl/thresholding_template_wrapper.v | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/finn-rtllib/thresholding/hdl/thresholding_template_wrapper.v b/finn-rtllib/thresholding/hdl/thresholding_template_wrapper.v index 79e7ad1bb7..ef76a23cbc 100644 --- a/finn-rtllib/thresholding/hdl/thresholding_template_wrapper.v +++ b/finn-rtllib/thresholding/hdl/thresholding_template_wrapper.v @@ -84,14 +84,14 @@ module $MODULE_NAME_AXI_WRAPPER$ #( output [ 1:0] s_axilite_RRESP, //- AXI Stream - Input -------------- - output in0_V_tready, - input in0_V_tvalid, - input [((PE*K+7)/8)*8-1:0] in0_V_tdata, + output in0_V_TREADY, + input in0_V_TVALID, + input [((PE*K+7)/8)*8-1:0] in0_V_TDATA, //- AXI Stream - Output ------------- - input out_V_tready, - output out_V_tvalid, - output [((PE*O_BITS+7)/8)*8-1:0] out_V_tdata + input out_V_TREADY, + output out_V_TVALID, + output [((PE*O_BITS+7)/8)*8-1:0] out_V_TDATA ); thresholding_axi #( @@ -113,8 +113,8 @@ module $MODULE_NAME_AXI_WRAPPER$ #( .s_axilite_ARVALID(s_axilite_ARVALID), .s_axilite_ARREADY(s_axilite_ARREADY), .s_axilite_ARADDR(s_axilite_ARADDR), .s_axilite_RVALID(s_axilite_RVALID), .s_axilite_RREADY(s_axilite_RREADY), .s_axilite_RDATA(s_axilite_RDATA), .s_axilite_RRESP(s_axilite_RRESP), - .s_axis_tready(in0_V_tready), .s_axis_tvalid(in0_V_tvalid), .s_axis_tdata(in0_V_tdata), - .m_axis_tready(out_V_tready), .m_axis_tvalid(out_V_tvalid), .m_axis_tdata(out_V_tdata) + .s_axis_tready(in0_V_TREADY), .s_axis_tvalid(in0_V_TVALID), .s_axis_tdata(in0_V_TDATA), + .m_axis_tready(out_V_TREADY), .m_axis_tvalid(out_V_TVALID), .m_axis_tdata(out_V_TDATA) ); endmodule // $MODULE_NAME_AXI_WRAPPER$ From cc9c09c9ac401ef2e5093e46ec8a1be167b5181a Mon Sep 17 00:00:00 2001 From: johnnoel Date: Tue, 16 Jan 2024 09:48:30 +0000 Subject: [PATCH 381/665] Fix typo --- docker/jenkins/Jenkinsfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index d3aa216c21..a3a40725bd 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -341,7 +341,7 @@ void findCopyZip(String board, String findDir, String copyDir) { sh "cp -r ${buildDir}/${board} ${copyDir}/" dir(copyDir) { sh "zip -r ${board}.zip ${board}/" - sh "cp ${board}.zip ${env.FINN_HOST_BUILD_DIR}/${copyDir}/" + sh "cp ${board}.zip ${env.ARTIFACT_DIR}/${copyDir}/" } } From 7a0d5b7c3e32900049fb6df2ffa265648ef806ee Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 16 Jan 2024 17:43:09 +0000 Subject: [PATCH 382/665] [RTLBackend] Move top module node attribute into backend --- src/finn/custom_op/fpgadataflow/rtl/fmpadding_rtl.py | 4 +--- .../fpgadataflow/rtl/streamingdatawidthconverter_rtl.py | 5 +---- src/finn/custom_op/fpgadataflow/rtlbackend.py | 7 +++++-- 3 files changed, 7 insertions(+), 9 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/rtl/fmpadding_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/fmpadding_rtl.py index 3c8a1ad777..b8a1505018 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/fmpadding_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/fmpadding_rtl.py @@ -1,4 +1,4 @@ -# Copyright (C) 2022, Advanced Micro Devices, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -56,8 +56,6 @@ def get_nodeattr_types(self): # Enable reprogrammable implementation to change FM dimensions, # stride, or dilation during runtime "dynamic_mode": ("i", False, 0, {0, 1}), - # attribute to save top module name - not user configurable - "gen_top_module": ("s", False, ""), } my_attrs.update(FMPadding.get_nodeattr_types(self)) my_attrs.update(RTLBackend.get_nodeattr_types(self)) diff --git a/src/finn/custom_op/fpgadataflow/rtl/streamingdatawidthconverter_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/streamingdatawidthconverter_rtl.py index 2d17897afe..6fcfaa1db0 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/streamingdatawidthconverter_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/streamingdatawidthconverter_rtl.py @@ -48,10 +48,7 @@ class StreamingDataWidthConverter_rtl(StreamingDataWidthConverter, RTLBackend): module.""" def get_nodeattr_types(self): - my_attrs = { - # attribute to save top module name - not user configurable - "gen_top_module": ("s", False, ""), - } + my_attrs = {} my_attrs.update(StreamingDataWidthConverter.get_nodeattr_types(self)) my_attrs.update(RTLBackend.get_nodeattr_types(self)) return my_attrs diff --git a/src/finn/custom_op/fpgadataflow/rtlbackend.py b/src/finn/custom_op/fpgadataflow/rtlbackend.py index 4c1977852c..96deb49161 100644 --- a/src/finn/custom_op/fpgadataflow/rtlbackend.py +++ b/src/finn/custom_op/fpgadataflow/rtlbackend.py @@ -1,4 +1,4 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2023, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -36,7 +36,10 @@ class RTLBackend(ABC): when writing a new RTL custom op node.""" def get_nodeattr_types(self): - return {} + return { + # attribute to save top module name - not user configurable + "gen_top_module": ("s", False, ""), + } @abstractmethod def generate_hdl(self): From 4e44fa875fb67898ebd070ef5ff385e1afb83b9b Mon Sep 17 00:00:00 2001 From: johnnoel Date: Tue, 16 Jan 2024 19:42:27 +0000 Subject: [PATCH 383/665] Make sure artifact directory exists --- docker/jenkins/Jenkinsfile | 1 + 1 file changed, 1 insertion(+) diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index a3a40725bd..bf4505cc3f 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -341,6 +341,7 @@ void findCopyZip(String board, String findDir, String copyDir) { sh "cp -r ${buildDir}/${board} ${copyDir}/" dir(copyDir) { sh "zip -r ${board}.zip ${board}/" + sh "mkdir -p ${env.ARTIFACT_DIR}/${copyDir}/" sh "cp ${board}.zip ${env.ARTIFACT_DIR}/${copyDir}/" } } From ac525dcf35333f93a6bb66d99e3941fc8d35c911 Mon Sep 17 00:00:00 2001 From: Yaman Umuroglu Date: Wed, 25 Oct 2023 10:26:35 +0100 Subject: [PATCH 384/665] [Infra] extra optional envvars to pass to docker build and skip board file dl --- fetch-repos.sh | 26 ++++++++++++++++---------- run-docker.sh | 4 +++- 2 files changed, 19 insertions(+), 11 deletions(-) diff --git a/fetch-repos.sh b/fetch-repos.sh index 397f29637d..1275ccf31c 100755 --- a/fetch-repos.sh +++ b/fetch-repos.sh @@ -127,17 +127,23 @@ fetch_repo $XIL_BDF_URL $XIL_BDF_COMMIT $XIL_BDF_DIR fetch_repo $RFSOC4x2_BDF_URL $RFSOC4x2_BDF_COMMIT $RFSOC4x2_BDF_DIR fetch_repo $KV260_BDF_URL $KV260_BDF_COMMIT $KV260_SOM_BDF_DIR -# download extra Pynq board files and extract if needed -if [ ! -d "$SCRIPTPATH/deps/board_files" ]; then - fetch_board_files +# Can skip downloading of board files entirely if desired +if [ "$FINN_SKIP_BOARD_FILES" = "1" ]; then + echo "Skipping download and verification of board files" else - cd $SCRIPTPATH - BOARD_FILES_MD5=$(find deps/board_files/ -type f -exec md5sum {} \; | sort -k 2 | md5sum | cut -d' ' -f 1) - if [ "$BOARD_FILES_MD5" = "$EXP_BOARD_FILES_MD5" ]; then - echo "Verified board files folder content md5: $BOARD_FILES_MD5" - else - echo "Board files folder content mismatch, removing and re-downloading" - rm -rf deps/board_files/ + # download extra board files and extract if needed + if [ ! -d "$SCRIPTPATH/deps/board_files" ]; then fetch_board_files + else + cd $SCRIPTPATH + BOARD_FILES_MD5=$(find deps/board_files/ -type f -exec md5sum {} \; | sort -k 2 | md5sum | cut -d' ' -f 1) + if [ "$BOARD_FILES_MD5" = "$EXP_BOARD_FILES_MD5" ]; then + echo "Verified board files folder content md5: $BOARD_FILES_MD5" + else + echo "Board files folder md5: expected $BOARD_FILES_MD5 found $EXP_BOARD_FILES_MD5" + echo "Board files folder content mismatch, removing and re-downloading" + rm -rf deps/board_files/ + fetch_board_files + fi fi fi diff --git a/run-docker.sh b/run-docker.sh index 58d7d97084..cf7281eb6b 100755 --- a/run-docker.sh +++ b/run-docker.sh @@ -93,7 +93,9 @@ SCRIPTPATH=$(dirname "$SCRIPT") : ${FINN_DOCKER_RUN_AS_ROOT="0"} : ${FINN_DOCKER_GPU="$(docker info | grep nvidia | wc -m)"} : ${FINN_DOCKER_EXTRA=""} +: ${FINN_DOCKER_BUILD_EXTRA=""} : ${FINN_SKIP_DEP_REPOS="0"} +: ${FINN_SKIP_BOARD_FILES="0"} : ${OHMYXILINX="${SCRIPTPATH}/deps/oh-my-xilinx"} : ${NVIDIA_VISIBLE_DEVICES=""} : ${DOCKER_BUILDKIT="1"} @@ -181,7 +183,7 @@ if [ "$FINN_DOCKER_PREBUILT" = "0" ]; then # Need to ensure this is done within the finn/ root folder: OLD_PWD=$(pwd) cd $SCRIPTPATH - docker build -f docker/Dockerfile.finn --build-arg XRT_DEB_VERSION=$XRT_DEB_VERSION --tag=$FINN_DOCKER_TAG . + docker build -f docker/Dockerfile.finn --build-arg XRT_DEB_VERSION=$XRT_DEB_VERSION --tag=$FINN_DOCKER_TAG $FINN_DOCKER_BUILD_EXTRA . cd $OLD_PWD fi # Launch container with current directory mounted From 418c2b07a757d64d0094d5dcecad2760224993d4 Mon Sep 17 00:00:00 2001 From: Yaman Umuroglu Date: Wed, 13 Dec 2023 22:29:47 +0000 Subject: [PATCH 385/665] [FIFO] only remove 0-depth FIFOs --- src/finn/transformation/fpgadataflow/set_fifo_depths.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/set_fifo_depths.py b/src/finn/transformation/fpgadataflow/set_fifo_depths.py index da6099ab9a..d481fb027c 100644 --- a/src/finn/transformation/fpgadataflow/set_fifo_depths.py +++ b/src/finn/transformation/fpgadataflow/set_fifo_depths.py @@ -84,12 +84,13 @@ def optimize_depth(depth): class RemoveShallowFIFOs(Transformation): - """Remove small FIFOs as the streaming components have depth-2 FIFOs on the - input/outputs by default.""" + """Remove zero-depth FIFOs The threshold used to be 2 instead of 0, but + with increasing number of FINN RTL components 2-depth FIFOs are still + important for decoupling..""" # TODO add unit test - def __init__(self, shallow_threshold=2): + def __init__(self, shallow_threshold=0): self.shallow_threshold = shallow_threshold def apply(self, model): From 8f4e151433d1ddbb4b53ad7b768c474ce92417ba Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Wed, 17 Jan 2024 11:49:50 +0000 Subject: [PATCH 386/665] [BTS] Add memory estimation helper functions Signed-off-by: aziz bahri --- .../thresholding_binary_search.py | 75 ++++++++++++++++--- 1 file changed, 63 insertions(+), 12 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/thresholding_binary_search.py b/src/finn/custom_op/fpgadataflow/thresholding_binary_search.py index d02b778823..7d53d81de8 100755 --- a/src/finn/custom_op/fpgadataflow/thresholding_binary_search.py +++ b/src/finn/custom_op/fpgadataflow/thresholding_binary_search.py @@ -85,10 +85,60 @@ def get_nodeattr_types(self): "gen_top_module": ("s", False, ""), # bias to be applied to outputs of the node "activation_bias": ("i", False, 0), + # whether weights (thresholds) will be + # writable through an AXI-lite interface during runtime + # 1 for enabled, 0 for disabled. + "runtime_writeable_weights": ("i", False, 0, {0, 1}), + # memory depth triggers for threshold storage + "depth_trigger_uram": ("i", False, 0), + "depth_trigger_bram": ("i", False, 0), + # enable uniform thres optimization + # doesn't actually do anything yet, only + # for resource estimations + "uniform_thres": ("i", False, 0, {0, 1}), + # enable deep pipelining for easier timing closure + # setting to 0 may save some FFs but otherwise leave on + "deep_pipeline": ("i", False, 1, {0, 1}), } my_attrs.update(super().get_nodeattr_types()) return my_attrs + def get_pe_mem_geometries(self): + pe = self.get_nodeattr("PE") + wdt = self.get_weight_datatype() + wdt_bits = wdt.bitwidth() + odt = self.get_output_datatype() + odt_bits = odt.bitwidth() + t_channels = self.get_nodeattr("NumChannels") + cf = t_channels / pe + is_uniform = self.get_nodeattr("uniform_thres") + if is_uniform: + ret = [(odt_bits - x, cf * (2**x)) for x in range(1, odt_bits)] + else: + ret = [(wdt_bits, (cf) * 2**x) for x in range(odt_bits)] + return ret + + def get_memory_estimate(self): + res_dict = {} + depth_trigger_bram = self.get_nodeattr("depth_trigger_bram") + depth_trigger_uram = self.get_nodeattr("depth_trigger_uram") + pe = self.get_nodeattr("PE") + ret = self.get_pe_mem_geometries() + for mem_cfg in ret: + (width, depth) = mem_cfg + primitives = mem_primitives_versal + if depth_trigger_bram != 0 or depth_trigger_uram != 0: + if depth >= depth_trigger_bram and depth < depth_trigger_uram: + primitives = {k: v for (k, v) in mem_primitives_versal.items() if "BRAM" in k} + elif depth >= depth_trigger_uram: + primitives = {k: v for (k, v) in mem_primitives_versal.items() if "URAM" in k} + alts = get_memutil_alternatives(mem_cfg, primitives) + primary_alt = alts[0] + res_type = primary_alt[0].split("_")[0] + res_count, eff, waste = primary_alt[1] + res_dict[res_type] = res_dict.get(res_type, 0) + pe * res_count + return res_dict + def calc_tmem(self): """Calculates and returns TMEM.""" num_channels = self.get_nodeattr("NumChannels") @@ -122,10 +172,16 @@ def verify_node(self): return [] def bram_estimation(self): - return 0 + res_dict = self.get_memory_estimate() + return res_dict.get("BRAM", 0) + + def uram_estimation(self): + res_dict = self.get_memory_estimate() + return res_dict.get("URAM", 0) def lut_estimation(self): - return 0 + res_dict = self.get_memory_estimate() + return res_dict.get("LUTRAM", 0) def get_input_datatype(self, ind=0): return DataType[self.get_nodeattr("inputDataType")] @@ -202,7 +258,8 @@ def get_number_output_values(self): return 0 def get_exp_cycles(self): - return 0 + # Channels/PE * batch size * fmdim * fmdim + return np.prod(self.get_folded_output_shape()[:-1]) def get_hls_compatible_threshold_tensor(self, orig_thres_matrix): """Convert the original numpy weight matrix orig_weight_matrix into @@ -221,23 +278,17 @@ def get_hls_compatible_threshold_tensor(self, orig_thres_matrix): ), """Threshold matrix dimension is not as expected (2).""" n_thres_steps = orig_thres_matrix.shape[1] - assert n_thres_steps == self.get_nodeattr( - "numSteps" - ), "Mismatch in threshold steps" + assert n_thres_steps == self.get_nodeattr("numSteps"), "Mismatch in threshold steps" if not self.get_input_datatype().signed(): # ensure all thresholds are nonnegative assert (orig_thres_matrix >= 0).all() # ensure all thresholds are integer - assert np.equal( - np.mod(orig_thres_matrix, 1), 0 - ).all(), "Need int threshold tensor" + assert np.equal(np.mod(orig_thres_matrix, 1), 0).all(), "Need int threshold tensor" ret = orig_thres_matrix # ensure channels = mh , duplicating if necessary if ret.shape[0] == 1: ret = np.tile(ret, (mh, 1)) - assert ( - ret.shape[0] == mh - ), "Channels of threshold matrix are not as expected (mh)" + assert ret.shape[0] == mh, "Channels of threshold matrix are not as expected (mh)" # distribute rows between PEs ret = interleave_matrix_outer_dim_from_partitions(ret, pe) assert ( From 471e3d6bede1739fce14597118ea4460f5acad9f Mon Sep 17 00:00:00 2001 From: johnnoel Date: Wed, 17 Jan 2024 14:21:41 +0000 Subject: [PATCH 387/665] [CI] Add functions to clean up Jenkinsfile_HW --- docker/jenkins/Jenkinsfile_HW | 303 ++++++++-------------------------- 1 file changed, 68 insertions(+), 235 deletions(-) diff --git a/docker/jenkins/Jenkinsfile_HW b/docker/jenkins/Jenkinsfile_HW index 71a0bede87..dcf0e7e151 100644 --- a/docker/jenkins/Jenkinsfile_HW +++ b/docker/jenkins/Jenkinsfile_HW @@ -42,36 +42,12 @@ pipeline { } steps { catchError(stageResult: 'FAILURE') { - script { - // Clean any files from a previous run - cleanPreviousBuildFiles("${env.BOARD}*") - - // Get the test files - unstash name: "bnn_build_sanity_${env.BOARD}_zip" - sh "unzip -o ${env.BOARD}.zip" - - dir(env.BOARD) { - // Get the scripts necessary for running hw tests - unstash name: 'bnn_test_files' - - // Create test script - createTestScript(env.BOARD, env.BOARD, "sanity_bnn_test_hw_${env.BOARD}") - - // Use an env variable to help collect test results later in pipeline - env.SANITY_BNN_TEST_U250 = "SUCCESS" - - // Execute the script - sh './run-tests.sh' - } - } + runTest("bnn_build_sanity", "${env.BOARD}", "${env.BOARD}") } } post { always { - dir(env.BOARD) { - // Collect the results file on the worker node by stashing - stash name: "xml_sanity_bnn_test_${env.BOARD}", includes: "sanity_bnn_test_hw_${env.BOARD}.xml,sanity_bnn_test_hw_${env.BOARD}.html" - } + stashResults("bnn_build_sanity", "${env.BOARD}") } } } @@ -90,39 +66,12 @@ pipeline { } steps { catchError(stageResult: 'FAILURE') { - script { - // Clean any files from a previous run - cleanPreviousBoardBuildFiles("${env.BOARD}*") - - // Get the test files - unstash name: "bnn_build_sanity_${env.BOARD}_zip" - sh "unzip -o ${env.BOARD}.zip" - - dir(env.BOARD) { - // Get the scripts necessary for running hw tests - unstash name: 'bnn_test_files' - - // Create test script - // The marker here omits the '-Z1' as '-' is a special character - // that will not work with Pytest - createTestScript(env.BOARD, 'Pynq', "sanity_bnn_test_hw_${env.BOARD}") - - // Use an env variable to help collect test results later in pipeline - env.SANITY_BNN_TEST_PYNQZ1 = "SUCCESS" - - // Execute the script as the root user - needed for zynq platforms - sh 'echo $USER_CREDENTIALS_PSW | sudo -S ./run-tests.sh' - } - } + runTest("bnn_build_sanity", "${env.BOARD}", "Pynq") } } post { always { - // Get test result file and delete test files on the board - dir(env.BOARD) { - // Collect the results file on the worker node by stashing - stash name: "xml_sanity_bnn_test_PynqZ1", includes: "sanity_bnn_test_hw_${env.BOARD}.xml,sanity_bnn_test_hw_${env.BOARD}.html" - } + stashResults("bnn_build_sanity", "${env.BOARD}") } } } @@ -141,37 +90,12 @@ pipeline { } steps { catchError(stageResult: 'FAILURE') { - script { - // Clean any files from a previous run - cleanPreviousBoardBuildFiles("${env.BOARD}*") - - // Get the test files - unstash name: "bnn_build_sanity_${env.BOARD}_zip" - sh "unzip -o ${env.BOARD}.zip" - - dir(env.BOARD) { - // Get the scripts necessary for running hw tests - unstash name: 'bnn_test_files' - - // Create test script - createTestScript(env.BOARD, env.BOARD, "sanity_bnn_test_hw_${env.BOARD}") - - // Use an env variable to help collect test results later in pipeline - env.SANITY_BNN_TEST_ZCU104 = "SUCCESS" - - // Execute the script as the root user - needed for zynq platforms - sh 'echo $USER_CREDENTIALS_PSW | sudo -S ./run-tests.sh' - } - } + runTest("bnn_build_sanity", "${env.BOARD}", "${env.BOARD}") } } post { always { - // Get test result file and delete test files on the board - dir(env.BOARD) { - // Collect the results file on the worker node by stashing - stash name: "xml_sanity_bnn_test_${env.BOARD}", includes: "sanity_bnn_test_hw_${env.BOARD}.xml,sanity_bnn_test_hw_${env.BOARD}.html" - } + stashResults("bnn_build_sanity", "${env.BOARD}") } } } @@ -190,37 +114,12 @@ pipeline { } steps { catchError(stageResult: 'FAILURE') { - script { - // Clean any files from a previous run - cleanPreviousBoardBuildFiles("${env.BOARD}*") - - // Get the test files - unstash name: "bnn_build_sanity_${env.BOARD}_zip" - sh "unzip -o ${env.BOARD}.zip" - - dir(env.BOARD) { - // Get the scripts necessary for running hw tests - unstash name: 'bnn_test_files' - - // Create test script - createTestScript(env.BOARD, env.BOARD, "sanity_bnn_test_hw_${env.BOARD}") - - // Use an env variable to help collect test results later in pipeline - env.SANITY_BNN_TEST_KV260_SOM = "SUCCESS" - - // Execute the script as the root user - needed for zynq platforms - sh 'echo $USER_CREDENTIALS_PSW | sudo -S ./run-tests.sh' - } - } + runTest("bnn_build_sanity", "${env.BOARD}", "${env.BOARD}") } } - post { + post { always { - // Get test result file and delete test files on the board - dir(env.BOARD) { - // Collect the results file on the worker node by stashing - stash name: "xml_sanity_bnn_test_${env.BOARD}", includes: "sanity_bnn_test_hw_${env.BOARD}.xml,sanity_bnn_test_hw_${env.BOARD}.html" - } + stashResults("bnn_build_sanity", "${env.BOARD}") } } } @@ -242,36 +141,12 @@ pipeline { } steps { catchError(stageResult: 'FAILURE') { - script { - // Clean any files from a previous run - cleanPreviousBuildFiles("${env.BOARD}*") - - // Get the test files - unstash name: "bnn_build_full_${env.BOARD}_zip" - sh "unzip -o ${env.BOARD}.zip" - - dir(env.BOARD) { - // Get the scripts necessary for running hw tests - unstash name: 'bnn_test_files' - - // Create test script - createTestScript(env.BOARD, env.BOARD, "bnn_test_hw_${env.BOARD}") - - // Use an env variable to help collect test results later in pipeline - env.BNN_TEST_U250 = "SUCCESS" - - // Execute the script - sh './run-tests.sh' - } - } + runTest("bnn_build_full", "${env.BOARD}", "${env.BOARD}") } } post { always { - dir(env.BOARD) { - // Collect the results file on the worker node by stashing - stash name: "xml_bnn_test_${env.BOARD}", includes: "bnn_test_hw_${env.BOARD}.xml,bnn_test_hw_${env.BOARD}.html" - } + stashResults("bnn_build_full", "${env.BOARD}") } } } @@ -290,39 +165,12 @@ pipeline { } steps { catchError(stageResult: 'FAILURE') { - script { - // Clean any files from a previous run - cleanPreviousBoardBuildFiles("${env.BOARD}*") - - // Get the test files - unstash name: "bnn_build_full_${env.BOARD}_zip" - sh "unzip -o ${env.BOARD}.zip" - - dir(env.BOARD) { - // Get the scripts necessary for running hw tests - unstash name: 'bnn_test_files' - - // Create test script - // The marker here omits the '-Z1' as '-' is a special character - // that will not work with Pytest - createTestScript(env.BOARD, 'Pynq', "bnn_test_hw_${env.BOARD}") - - // Use an env variable to help collect test results later in pipeline - env.BNN_TEST_PYNQZ1 = "SUCCESS" - - // Execute the script as the root user - needed for zynq platforms - sh 'echo $USER_CREDENTIALS_PSW | sudo -S ./run-tests.sh' - } - } + runTest("bnn_build_full", "${env.BOARD}", "Pynq") } } post { always { - // Get test result file and delete test files on the board - dir(env.BOARD) { - // Collect the results file on the worker node by stashing - stash name: "xml_bnn_test_PynqZ1", includes: "bnn_test_hw_${env.BOARD}.xml,bnn_test_hw_${env.BOARD}.html" - } + stashResults("bnn_build_full", "${env.BOARD}") } } } @@ -341,37 +189,12 @@ pipeline { } steps { catchError(stageResult: 'FAILURE') { - script { - // Clean any files from a previous run - cleanPreviousBoardBuildFiles("${env.BOARD}*") - - // Get the test files - unstash name: "bnn_build_full_${env.BOARD}_zip" - sh "unzip -o ${env.BOARD}.zip" - - dir(env.BOARD) { - // Get the scripts necessary for running hw tests - unstash name: 'bnn_test_files' - - // Create test script - createTestScript(env.BOARD, env.BOARD, "bnn_test_hw_${env.BOARD}") - - // Use an env variable to help collect test results later in pipeline - env.BNN_TEST_ZCU104 = "SUCCESS" - - // Execute the script as the root user - needed for zynq platforms - sh 'echo $USER_CREDENTIALS_PSW | sudo -S ./run-tests.sh' - } - } + runTest("bnn_build_full", "${env.BOARD}", "${env.BOARD}") } } post { always { - // Get test result file and delete test files on the board - dir(env.BOARD) { - // Collect the results file on the worker node by stashing - stash name: "xml_bnn_test_${env.BOARD}", includes: "bnn_test_hw_${env.BOARD}.xml,bnn_test_hw_${env.BOARD}.html" - } + stashResults("bnn_build_full", "${env.BOARD}") } } } @@ -390,37 +213,12 @@ pipeline { } steps { catchError(stageResult: 'FAILURE') { - script { - // Clean any files from a previous run - cleanPreviousBoardBuildFiles("${env.BOARD}*") - - // Get the test files - unstash name: "bnn_build_full_${env.BOARD}_zip" - sh "unzip -o ${env.BOARD}.zip" - - dir(env.BOARD) { - // Get the scripts necessary for running hw tests - unstash name: 'bnn_test_files' - - // Create test script - createTestScript(env.BOARD, env.BOARD, "bnn_test_hw_${env.BOARD}") - - // Use an env variable to help collect test results later in pipeline - env.BNN_TEST_KV260_SOM = "SUCCESS" - - // Execute the script as the root user - needed for zynq platforms - sh 'echo $USER_CREDENTIALS_PSW | sudo -S ./run-tests.sh' - } - } + runTest("bnn_build_full", "${env.BOARD}", "${env.BOARD}") } } post { always { - // Get test result file and delete test files on the board - dir(env.BOARD) { - // Collect the results file on the worker node by stashing - stash name: "xml_bnn_test_${env.BOARD}", includes: "bnn_test_hw_${env.BOARD}.xml,bnn_test_hw_${env.BOARD}.html" - } + stashResults("bnn_build_full", "${env.BOARD}") } } } @@ -436,14 +234,14 @@ pipeline { cleanPreviousBuildFiles('reports') dir('reports') { // Only unstash for stages that ran - unstashSuccessfulStage(env.SANITY_BNN_TEST_U250, "xml_sanity_bnn_test_U250") - unstashSuccessfulStage(env.SANITY_BNN_TEST_PYNQZ1, "xml_sanity_bnn_test_PynqZ1") - unstashSuccessfulStage(env.SANITY_BNN_TEST_ZCU104, "xml_sanity_bnn_test_ZCU104") - unstashSuccessfulStage(env.SANITY_BNN_TEST_KV260_SOM, "xml_sanity_bnn_test_KV260_SOM") - unstashSuccessfulStage(env.BNN_TEST_U250, "xml_bnn_test_U250") - unstashSuccessfulStage(env.BNN_TEST_PYNQZ1, "xml_bnn_test_PynqZ1") - unstashSuccessfulStage(env.BNN_TEST_ZCU104, "xml_bnn_test_ZCU104") - unstashSuccessfulStage(env.BNN_TEST_KV260_SOM, "xml_bnn_test_KV260_SOM") + unstashSuccessfulStage(env.ALVEO_HOST_ONLINE, "xml_bnn_build_sanity_U250") + unstashSuccessfulStage(env.PYNQ_ONLINE, "xml_bnn_build_sanity_Pynq-Z1") + unstashSuccessfulStage(env.ZCU104_ONLINE, "xml_bnn_build_sanity_ZCU104") + unstashSuccessfulStage(env.KV260_ONLINE, "xml_bnn_build_sanity_KV260_SOM") + unstashSuccessfulStage(env.ALVEO_HOST_ONLINE, "xml_bnn_build_full_U250") + unstashSuccessfulStage(env.PYNQ_ONLINE, "xml_bnn_build_full_Pynq-Z1") + unstashSuccessfulStage(env.ZCU104_ONLINE, "xml_bnn_build_full_ZCU104") + unstashSuccessfulStage(env.KV260_ONLINE, "xml_bnn_build_full_KV260_SOM") } // Combine individual HTML files to one single report @@ -465,15 +263,11 @@ void cleanPreviousBuildFiles(String buildDir) { // Delete any build files from a previous build // Previous build folders affect findCopyZip() and can cause the stage to fail if (!buildDir.empty) { + if (env.USER_CREDENTIALS) { + sh "echo $USER_CREDENTIALS_PSW | sudo -S rm -rf ${buildDir}*" + } else { sh "rm -rf ${buildDir}" - } -} - -void cleanPreviousBoardBuildFiles(String boardDir) { - // Delete any board build files - // Specifically used on Pynq boards which require sudo to delete - if (!boardDir.empty) { - sh "echo $USER_CREDENTIALS_PSW | sudo -S rm -rf ${boardDir}*" + } } } @@ -536,3 +330,42 @@ void stashBuildArtifacts(String testDir) { } } } + +String runTest(String testType, String board, String marker) { + // Clean any files from a previous run + cleanPreviousBuildFiles("${board}*") + + // Get the test files + unstash name: "${testType}_${board}_zip" + sh "unzip -o ${board}.zip" + + dir("$board") { + // Get the scripts necessary for running hw tests + unstash name: 'bnn_test_files' + + // Create test script + createTestScript(board, marker, "${testType}_hw_${board}") + + if (env.USER_CREDENTIALS) { + // Execute the script as the root user - needed for zynq platforms + sh 'echo ${USER_CREDENTIALS_PSW} | sudo -S ./run-tests.sh' + } else { + // Execute the script + sh './run-tests.sh' + } + } + + return "SUCCESS" +} + +void stashResults (String testType, String board) { + // Get test result file and delete test files on the board + dir("${board}") { + // Collect the results file on the worker node by stashing + try { + stash name: "xml_${testType}_${board}", includes: "${testType}_hw_${board}.xml,${testType}_hw_${board}.html" + } catch (err) { + echo "No results to stash" + } + } +} \ No newline at end of file From 8c116be41f985340e71b6ef427502f51aff65c22 Mon Sep 17 00:00:00 2001 From: johnnoel Date: Wed, 17 Jan 2024 14:48:49 +0000 Subject: [PATCH 388/665] [CI] Download test files into test specific directories on hardware --- docker/jenkins/Jenkinsfile_HW | 37 +++++++++++++++++++---------------- 1 file changed, 20 insertions(+), 17 deletions(-) diff --git a/docker/jenkins/Jenkinsfile_HW b/docker/jenkins/Jenkinsfile_HW index dcf0e7e151..3436ec79e8 100644 --- a/docker/jenkins/Jenkinsfile_HW +++ b/docker/jenkins/Jenkinsfile_HW @@ -332,26 +332,29 @@ void stashBuildArtifacts(String testDir) { } String runTest(String testType, String board, String marker) { - // Clean any files from a previous run - cleanPreviousBuildFiles("${board}*") + sh "mkdir -p ${testType}" + dir("$testType") { + // Clean any files from a previous run + cleanPreviousBuildFiles("${board}*") - // Get the test files - unstash name: "${testType}_${board}_zip" - sh "unzip -o ${board}.zip" + // Get the test files + unstash name: "${testType}_${board}_zip" + sh "unzip -o ${board}.zip" - dir("$board") { - // Get the scripts necessary for running hw tests - unstash name: 'bnn_test_files' + dir("$board") { + // Get the scripts necessary for running hw tests + unstash name: 'bnn_test_files' - // Create test script - createTestScript(board, marker, "${testType}_hw_${board}") + // Create test script + createTestScript(board, marker, "${testType}_hw_${board}") - if (env.USER_CREDENTIALS) { - // Execute the script as the root user - needed for zynq platforms - sh 'echo ${USER_CREDENTIALS_PSW} | sudo -S ./run-tests.sh' - } else { - // Execute the script - sh './run-tests.sh' + if (env.USER_CREDENTIALS) { + // Execute the script as the root user - needed for zynq platforms + sh 'echo ${USER_CREDENTIALS_PSW} | sudo -S ./run-tests.sh' + } else { + // Execute the script + sh './run-tests.sh' + } } } @@ -360,7 +363,7 @@ String runTest(String testType, String board, String marker) { void stashResults (String testType, String board) { // Get test result file and delete test files on the board - dir("${board}") { + dir("${testType}/${board}") { // Collect the results file on the worker node by stashing try { stash name: "xml_${testType}_${board}", includes: "${testType}_hw_${board}.xml,${testType}_hw_${board}.html" From 7156f3f20c31dbf523f80c8c67e35bd8422b1bdc Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 17 Jan 2024 20:07:27 +0000 Subject: [PATCH 389/665] [CustomOp] Initial draft of convinputgen in new class hierarchy --- src/finn/custom_op/fpgadataflow/__init__.py | 10 +- .../fpgadataflow/convolutioninputgenerator.py | 424 +++------------ .../custom_op/fpgadataflow/hls/__init__.py | 4 + .../convolutioninputgenerator_hls.py} | 491 ++++++++---------- .../custom_op/fpgadataflow/rtl/__init__.py | 4 + .../convolutioninputgenerator_rtl.py | 210 +------- .../fpgadataflow/convert_to_hw_layers.py | 31 +- .../fpgadataflow/specialize_layers.py | 36 ++ .../test_fpgadataflow_convinputgenerator.py | 262 +++++++--- .../test_fpgadataflow_convinputgenerator1d.py | 268 ---------- ...est_fpgadataflow_convinputgenerator_rtl.py | 245 --------- 11 files changed, 593 insertions(+), 1392 deletions(-) rename src/finn/custom_op/fpgadataflow/{convolutioninputgenerator1d.py => hls/convolutioninputgenerator_hls.py} (63%) rename src/finn/custom_op/fpgadataflow/{ => rtl}/convolutioninputgenerator_rtl.py (85%) delete mode 100644 tests/fpgadataflow/test_fpgadataflow_convinputgenerator1d.py delete mode 100755 tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py diff --git a/src/finn/custom_op/fpgadataflow/__init__.py b/src/finn/custom_op/fpgadataflow/__init__.py index 157dfa5c53..8254083ef7 100644 --- a/src/finn/custom_op/fpgadataflow/__init__.py +++ b/src/finn/custom_op/fpgadataflow/__init__.py @@ -34,12 +34,6 @@ from finn.custom_op.fpgadataflow.convolutioninputgenerator import ( ConvolutionInputGenerator, ) -from finn.custom_op.fpgadataflow.convolutioninputgenerator1d import ( - ConvolutionInputGenerator1D, -) -from finn.custom_op.fpgadataflow.convolutioninputgenerator_rtl import ( - ConvolutionInputGenerator_rtl, -) from finn.custom_op.fpgadataflow.downsampler import DownSampler from finn.custom_op.fpgadataflow.duplicatestreams import DuplicateStreams from finn.custom_op.fpgadataflow.fmpadding import FMPadding @@ -69,9 +63,6 @@ # make sure new HLSCustomOp subclasses are imported here so that they get # registered and plug in correctly into the infrastructure custom_op["MatrixVectorActivation"] = MatrixVectorActivation -custom_op["ConvolutionInputGenerator"] = ConvolutionInputGenerator -custom_op["ConvolutionInputGenerator1D"] = ConvolutionInputGenerator1D -custom_op["ConvolutionInputGenerator_rtl"] = ConvolutionInputGenerator_rtl custom_op["TLastMarker"] = TLastMarker custom_op["StreamingFIFO"] = StreamingFIFO custom_op["Pool_Batch"] = Pool_Batch @@ -86,6 +77,7 @@ custom_op["FMPadding"] = FMPadding custom_op["AddStreams"] = AddStreams custom_op["ChannelwiseOp"] = ChannelwiseOp +custom_op["ConvolutionInputGenerator"] = ConvolutionInputGenerator custom_op["DownSampler"] = DownSampler custom_op["DuplicateStreams"] = DuplicateStreams custom_op["GlobalAccPool"] = GlobalAccPool diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py index 33c542d79d..3be0a117a8 100644 --- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py +++ b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py @@ -1,4 +1,4 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2023, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -26,33 +26,24 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import math import numpy as np -import os +from onnx import TensorProto, helper from qonnx.core.datatype import DataType +from qonnx.core.modelwrapper import ModelWrapper from qonnx.custom_op.general.im2col import compute_conv_output_dim +from qonnx.custom_op.registry import getCustomOp +from qonnx.util.basic import qonnx_make_model -from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp -from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy +from finn.custom_op.fpgadataflow.hwcustomop import HWCustomOp # ONNX i/o tensor shape assumptions for ConvolutionInputGenerator: # input 0 is the input tensor, shape NHWC = (1, IFMDim, IFMDim, IFMChannels) # output 0 is the output tensor, shape NHWC: # = (1, OFMDim, OFMDim, (ConvKernelDim^2)*IFMChannels) -# note: the actual data layout produced by the hlslib kernels is different -# for depthwise and non-depthwise ops. -# * non-depthwise SWG: (1, OFMDim, OFMDim, K, K, IFMChannels/SIMD, SIMD) -# * depthwise SWG: (1, OFMDim, OFMDim, IFMChannels/SIMD, K, K, SIMD) -# see test_fpgadataflow_slidingwindow.py for an example of how to transform -# between the two layouts - -class ConvolutionInputGenerator(HLSCustomOp): - """Class that corresponds to one of the finn-hlslib ConvolutionInputGenerator - (sliding window) function variants. Depending on the combination of - attributes (e.g. depthwise or not, whether k % stride is 0) a different - variant will be picked for the actual HLS implementation.""" +class ConvolutionInputGenerator(HWCustomOp): + """Abstraction layer for HW implementation of ConvolutionInputGenerator""" def __init__(self, onnx_node, **kwargs): super().__init__(onnx_node, **kwargs) @@ -82,23 +73,13 @@ def get_nodeattr_types(self): "distributed", {"auto", "block", "distributed", "ultra"}, ), + "parallel_window": ("i", False, 0, {0, 1}), + # 1D (True) or 2D (False) spatial data + "is1D": ("i", False, 0), } my_attrs.update(super().get_nodeattr_types()) return my_attrs - def get_nodeattr(self, name): - # overriding get_nodeattr to check for square kernel/img.. requirement - # since this can't be done with the attribute restriction in nodeattr_types - # TODO non-square can be enabled in theory but needs testing - ret = super().get_nodeattr(name) - props_to_check = ["ConvKernelDim", "IFMDim", "OFMDim", "Stride", "Dilation"] - if name in props_to_check: - is_square = ret[0] == ret[1] - assert is_square, "Only square %s supported" % name - if name == "Dilation": - assert ret[0] == ret[1] == 1, "Only dilation=1 supported" - return ret - def get_normal_input_shape(self, ind=0): ifm_dim_h, ifm_dim_w = self.get_nodeattr("IFMDim") ifm_ch = self.get_nodeattr("IFMChannels") @@ -137,8 +118,12 @@ def get_folded_output_shape(self, ind=0): ofm_dim_h = compute_conv_output_dim(ifm_dim_h, k_h, stride_h, pad, dilation_h) ofm_dim_w = compute_conv_output_dim(ifm_dim_w, k_w, stride_w, pad, dilation_w) assert ifm_ch % simd == 0, "SIMD must divide IFMChannels" - wf = int((k_h * k_w * ifm_ch) // simd) - folded_oshape = (1, ofm_dim_h, ofm_dim_w, wf, simd) + if self.use_parallel_window_output(): + wf = int((ifm_ch) // simd) + folded_oshape = (1, ofm_dim_h, ofm_dim_w, wf, k_h * k_w * simd) + else: + wf = int((k_h * k_w * ifm_ch) // simd) + folded_oshape = (1, ofm_dim_h, ofm_dim_w, wf, simd) return folded_oshape def make_shape_compatible_op(self, model): @@ -177,330 +162,93 @@ def get_instream_width(self, ind=0): return in_width def get_outstream_width(self, ind=0): - """Returns stream width, input and output stream width are equal for - the sliding window function, so the function to determine the input - stream width can be reused.""" - return self.get_instream_width() + if self.use_parallel_window_output(): + # feed all window pixels in parallel + k_h, k_w = self.get_nodeattr("ConvKernelDim") + return self.get_instream_width() * k_h * k_w + else: + # if parallel variant not in use: same width for output and input stream + return self.get_instream_width() def get_number_output_values(self): folded_oshape = self.get_folded_output_shape() num_output_elems = np.prod(folded_oshape[:-1]) return num_output_elems - def get_exp_cycles(self): - simd = self.get_nodeattr("SIMD") + def get_1d_conv_attrs_normalized(self): + # support both (1, D) and (D, 1) cases transparently: + # For the kernel, presenting the input data of size D as + # [H, W] = [Y, X] = [1, D] or [D, 1] + # effectively gives the same result. + # For consistency and ease of programming, this function + # returns the attributes of the layer as follows: + # [H, W] = [Y, X] = [1, D] or [D, 1] are always mapped to [1, D]. + # The dummy ('1') dimension is the Y-dimension. ifm_ch = self.get_nodeattr("IFMChannels") - k_h, k_w = self.get_nodeattr("ConvKernelDim") - ifm_dim_h, ifm_dim_w = self.get_nodeattr("IFMDim") - ofm_dim_h, ofm_dim_w = self.get_nodeattr("OFMDim") - stride_h, stride_w = self.get_nodeattr("Stride") - dilation_h, dilation_w = self.get_nodeattr("Dilation") - - # since mmv != 1 is not supported yet, we set mmv for now to 1 - mmv = 1 - # see https://github.com/Xilinx/finn-hlslib/blob/master/slidingwindow.h - cycles_write_block = (ofm_dim_w * k_w * k_h * (ifm_ch / simd)) / mmv - cycles_read_block = stride_w * ifm_dim_w * (ifm_ch / simd) - max_cycles = max(cycles_write_block, cycles_read_block) - exp_cycles = ifm_dim_w * k_h * dilation_h * (ifm_ch / simd) + ofm_dim_h * max_cycles + k = self.get_nodeattr("ConvKernelDim") + ifm_dim = self.get_nodeattr("IFMDim") + ofm_dim = self.get_nodeattr("OFMDim") + stride = self.get_nodeattr("Stride") + dilation = self.get_nodeattr("Dilation") + + # see defines() for an explanation + if ifm_dim[1] == 1: + ifm_dim = ifm_dim[::-1] + ofm_dim = ofm_dim[::-1] + k = k[::-1] + stride = stride[::-1] + dilation = dilation[::-1] + + return (ifm_ch, ifm_dim, ofm_dim, k, stride, dilation) - return int(exp_cycles) + def get_exp_cycles(self): + return 0 def bram_estimation(self): - # NOTE: only tested with a square convolution - simd = self.get_nodeattr("SIMD") - ifm_ch = self.get_nodeattr("IFMChannels") - ifm_dim = self.get_nodeattr("IFMDim")[0] - k = self.get_nodeattr("ConvKernelDim")[0] - stride = self.get_nodeattr("Stride")[0] - ram_style = self.get_nodeattr("ram_style") - if ram_style == "block" or ram_style == "auto": - ram_depth = ifm_dim * ifm_ch / simd - if ram_depth <= 512: - ram_width = 36 - elif ram_depth <= 1024: - ram_width = 18 - elif ram_depth <= 2048: - ram_width = 9 - elif ram_depth <= 4096: - ram_width = 4 - elif ram_depth <= 8192: - ram_width = 2 - else: - ram_width = 1 - return int( - (k + stride) - * ( - math.ceil(simd * self.get_input_datatype().bitwidth() / ram_width) - * math.ceil(ifm_dim * ifm_ch / simd / ram_depth) - ) - ) - else: - return 0 + return 0 def lut_estimation(self): - # NOTE: only tested with a square convolution - simd = self.get_nodeattr("SIMD") - ifm_ch = self.get_nodeattr("IFMChannels") - ifm_dim = self.get_nodeattr("IFMDim")[0] - k = self.get_nodeattr("ConvKernelDim")[0] - stride = self.get_nodeattr("Stride")[0] - ram_style = self.get_nodeattr("ram_style") - if ram_style == "distributed": - ram_luts = int( - (k + stride) - * ( - simd - * self.get_input_datatype().bitwidth() - * math.ceil(ifm_dim * ifm_ch / simd / 64) - ) - ) - else: - ram_luts = 0 - return 300 + ram_luts + return 0 def uram_estimation(self): - # NOTE: only tested with a square convolution - simd = self.get_nodeattr("SIMD") - ifm_ch = self.get_nodeattr("IFMChannels") - ifm_dim = self.get_nodeattr("IFMDim")[0] - k = self.get_nodeattr("ConvKernelDim")[0] - stride = self.get_nodeattr("Stride")[0] - ram_style = self.get_nodeattr("ram_style") - if ram_style == "ultra": - return int( - (k + stride) - * ( - math.ceil(simd * self.get_input_datatype().bitwidth() / 64) - * math.ceil(ifm_dim * ifm_ch / simd / 4096) - ) - ) - else: - return 0 + return 0 def execute_node(self, context, graph): - mode = self.get_nodeattr("exec_mode") + # using Im2Col node to calculate output node = self.onnx_node - exp_ishape = self.get_normal_input_shape() - exp_oshape = self.get_normal_output_shape() - folded_ishape = self.get_folded_input_shape() - - # TODO ensure codegen dir exists - if mode == "cppsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - elif mode == "rtlsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) - - inp = context[node.input[0]] - assert str(inp.dtype) == "float32", "Input datatype is not float32" - assert ( - inp.shape == exp_ishape - ), """Input shape doesn't - match expected shape (1, ifm_dim_h, ifm_dim_w, ifm_ch).""" - if self.get_input_datatype() == DataType["BIPOLAR"]: - # store bipolar activations as binary - inp = (inp + 1) / 2 - export_idt = DataType["BINARY"] - else: - export_idt = self.get_input_datatype() - # reshape input into folded form - inp = inp.reshape(folded_ishape) - # make copy before saving array - reshaped_input = inp.copy() - np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input) - - if mode == "cppsim": - # execute the precompiled model - super().exec_precompiled_singlenode_model() - # load output npy file - super().npy_to_dynamic_output(context) - assert ( - context[node.output[0]].shape == exp_oshape - ), "cppsim \ - did not produce expected output shape" - elif mode == "rtlsim": - sim = self.get_rtlsim() - nbits = self.get_instream_width() - rtlsim_inp = npy_to_rtlsim_input( - "{}/input_0.npy".format(code_gen_dir), export_idt, nbits - ) - super().reset_rtlsim(sim) - super().toggle_clk(sim) - rtlsim_output = self.rtlsim(sim, rtlsim_inp) - odt = export_idt - target_bits = odt.bitwidth() - packed_bits = self.get_outstream_width() - out_npy_path = "{}/output.npy".format(code_gen_dir) - out_shape = self.get_folded_output_shape() - rtlsim_output_to_npy( - rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits - ) - # load and reshape output - output = np.load(out_npy_path) - output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) - context[node.output[0]] = output - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) - # binary -> bipolar if needed - if self.get_output_datatype() == DataType["BIPOLAR"]: - out = context[node.output[0]] - out = 2 * out - 1 - context[node.output[0]] = out - assert ( - context[node.output[0]].shape == exp_oshape - ), """Output - shape doesn't match expected shape (1, ofm_dim_h, ofm_dim_w, k_h*k_w*ifm_ch).""" - - def global_includes(self): - self.code_gen_dict["$GLOBALS$"] = ['#include "slidingwindow.h"'] - - def defines(self, var): - numReps = 1 - ifm_dim = self.get_nodeattr("IFMDim")[0] + ifm_dim = self.get_nodeattr("IFMDim") + k = self.get_nodeattr("ConvKernelDim") + s = self.get_nodeattr("Stride") + d = self.get_nodeattr("Dilation") ifm_ch = self.get_nodeattr("IFMChannels") - ofm_dim = self.get_nodeattr("OFMDim")[0] - k = self.get_nodeattr("ConvKernelDim")[0] - stride = self.get_nodeattr("Stride")[0] - simd = self.get_nodeattr("SIMD") - ifm_precision = self.get_input_datatype().bitwidth() - - self.code_gen_dict["$DEFINES$"] = [ - """#define ConvKernelDim1 {}\n #define IFMChannels1 {}\n - #define Input_precision1 {}\n #define IFMDim1 {}\n - #define OFMDim1 {}\n #define SIMD1 {}\n - #define Stride1 {}\n #define numReps {}""".format( - k, ifm_ch, ifm_precision, ifm_dim, ofm_dim, simd, stride, numReps - ) - ] - - def read_npy_data(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_input_datatype() - if dtype == DataType["BIPOLAR"]: - # use binary for bipolar storage - dtype = DataType["BINARY"] - elem_bits = dtype.bitwidth() - packed_bits = self.get_instream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_in = "%s/input_0.npy" % code_gen_dir - self.code_gen_dict["$READNPYDATA$"] = [] - self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - npy_in, - self.hls_sname(), - ) - ) - - def strm_decl(self): - self.code_gen_dict["$STREAMDECLARATIONS$"] = [] - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0_{} ("in0_{}");'.format( - self.get_instream_width(), self.hls_sname(), self.hls_sname() - ) + inp_values = context[node.input[0]] + oshape = context[node.output[0]].shape + ishape = inp_values.shape + inp = helper.make_tensor_value_info(node.input[0], TensorProto.FLOAT, ishape) + outp = helper.make_tensor_value_info(node.output[0], TensorProto.FLOAT, oshape) + im2col_node = helper.make_node( + "Im2Col", + [node.input[0]], + [node.output[0]], + domain="qonnx.custom_op.general", + stride=[s[0], s[1]], + kernel_size=[k[0], k[1]], + dilations=[d[0], d[1]], + input_shape="(1,{},{},{})".format(ifm_dim[0], ifm_dim[1], ifm_ch), ) - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out_{} ("out_{}");'.format( - self.get_outstream_width(), self.hls_sname(), self.hls_sname() - ) + graph_im2col = helper.make_graph( + nodes=[im2col_node], + name="single-im2col-exec", + inputs=[inp], + outputs=[outp], ) - def docompute(self): - node = self.onnx_node - ram_style = self.get_nodeattr("ram_style") - map_to_hls_ram_style = { - "auto": "ap_resource_dflt()", - "block": "ap_resource_bram()", - "distributed": "ap_resource_lutram()", - "ultra": "ap_resource_uram()", - } - hls_ram_style = map_to_hls_ram_style[ram_style] - hls_call = node.op_type - - # check which ConvolutionInputGenerator is needed - k = self.get_nodeattr("ConvKernelDim")[0] - stride = self.get_nodeattr("Stride")[0] - - if k % stride != 0: - hls_call += "_kernel_stride" - - if self.get_nodeattr("depthwise") == 1: - self.code_gen_dict["$DOCOMPUTE$"] = [ - """{}_dws (in0_{}, out_{}, numReps, {});""".format( - hls_call, self.hls_sname(), self.hls_sname(), hls_ram_style - ) - ] - else: - self.code_gen_dict["$DOCOMPUTE$"] = [ - """{} (in0_{}, out_{}, numReps, {});""".format( - hls_call, self.hls_sname(), self.hls_sname(), hls_ram_style - ) - ] - - def dataoutstrm(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_output_datatype() - if dtype == DataType["BIPOLAR"]: - # use binary for bipolar storage - dtype = DataType["BINARY"] - elem_bits = dtype.bitwidth() - packed_bits = self.get_outstream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_out = "%s/output.npy" % code_gen_dir - oshape = self.get_folded_output_shape() - oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") - - self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - self.hls_sname(), - oshape_cpp_str, - npy_out, - ) - ] - - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - - def blackboxfunction(self): - self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - """void {}(hls::stream> &in0_{}, - hls::stream> &out_{})""".format( - self.onnx_node.name, self.hls_sname(), self.hls_sname() - ) - ] - - def pragmas(self): - self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() - ] - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() - ) - self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") + opset_version = self.onnx_opset_version + opset_imports = [helper.make_opsetid("", opset_version)] + onnx_kwargs = {"opset_imports": opset_imports} + model_im2col = ModelWrapper(qonnx_make_model(graph_im2col, **onnx_kwargs)) + model_im2col.set_tensor_datatype(node.input[0], self.get_input_datatype()) + # use execution function from Im2Col node + # this automatically updates the execution context + inst = getCustomOp(im2col_node) + inst.execute_node(context, model_im2col.graph) diff --git a/src/finn/custom_op/fpgadataflow/hls/__init__.py b/src/finn/custom_op/fpgadataflow/hls/__init__.py index 8b1ca6e719..bcf36dad67 100644 --- a/src/finn/custom_op/fpgadataflow/hls/__init__.py +++ b/src/finn/custom_op/fpgadataflow/hls/__init__.py @@ -28,6 +28,9 @@ from finn.custom_op.fpgadataflow.hls.addstreams_hls import AddStreams_hls from finn.custom_op.fpgadataflow.hls.channelwise_op_hls import ChannelwiseOp_hls +from finn.custom_op.fpgadataflow.hls.convolutioninputgenerator_hls import ( + ConvolutionInputGenerator_hls, +) from finn.custom_op.fpgadataflow.hls.downsampler_hls import DownSampler_hls from finn.custom_op.fpgadataflow.hls.duplicatestreams_hls import DuplicateStreams_hls from finn.custom_op.fpgadataflow.hls.fmpadding_hls import FMPadding_hls @@ -47,6 +50,7 @@ # registered and plug in correctly into the infrastructure custom_op["AddStreams_hls"] = AddStreams_hls custom_op["ChannelwiseOp_hls"] = ChannelwiseOp_hls +custom_op["ConvolutionInputGenerator_hls"] = ConvolutionInputGenerator_hls custom_op["DownSampler_hls"] = DownSampler_hls custom_op["DuplicateStreams_hls"] = DuplicateStreams_hls custom_op["FMPadding_hls"] = FMPadding_hls diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator1d.py b/src/finn/custom_op/fpgadataflow/hls/convolutioninputgenerator_hls.py similarity index 63% rename from src/finn/custom_op/fpgadataflow/convolutioninputgenerator1d.py rename to src/finn/custom_op/fpgadataflow/hls/convolutioninputgenerator_hls.py index 046e8e096d..7223996e8b 100644 --- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator1d.py +++ b/src/finn/custom_op/fpgadataflow/hls/convolutioninputgenerator_hls.py @@ -1,4 +1,5 @@ # Copyright (c) 2020, Xilinx +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -31,15 +32,13 @@ import os import warnings from qonnx.core.datatype import DataType -from qonnx.custom_op.general.im2col import compute_conv_output_dim -from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp +from finn.custom_op.fpgadataflow.convolutioninputgenerator import ( + ConvolutionInputGenerator, +) +from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy -# This operation should only be used for 1D convolutions. Either the -# IFMDim_H or IFMDim_W should be '1', which represents the so-called -# dummy-dimension - # ONNX i/o tensor shape assumptions for ConvolutionInputGenerator1D: # input 0 is the input tensor, shape NHWC = (1, IFMDim_H, IFMDim_W, IFMChannels) # output 0 is the output tensor, shape NHWC: @@ -53,7 +52,7 @@ # between the two layouts -class ConvolutionInputGenerator1D(HLSCustomOp): +class ConvolutionInputGenerator_hls(ConvolutionInputGenerator, HLSBackend): """Class that corresponds to one of the 1D finn-hlslib ConvolutionInputGenerator (sliding window) function variants. Depending on the combination of attributes (e.g. depthwise or not, whether dilation is 0) a different @@ -63,175 +62,49 @@ def __init__(self, onnx_node, **kwargs): super().__init__(onnx_node, **kwargs) def get_nodeattr_types(self): - my_attrs = { - "ConvKernelDim": ("ints", True, []), # [H, W] = [Y, X] - "IFMChannels": ("i", True, 0), - "IFMDim": ("ints", True, []), # [H, W] = [Y, X] - "OFMDim": ("ints", True, []), # [H, W] = [Y, X] - "SIMD": ("i", True, 0), - "Stride": ("ints", True, []), # [H, W] = [Y, X] - "Dilation": ("ints", True, []), # [H, W] = [Y, X] - # FINN DataTypes for inputs, weights, outputs - "inputDataType": ("s", True, ""), - "outputDataType": ("s", True, ""), - "depthwise": ("i", False, 0, {0, 1}), - # FPGA resource type for ConvolutionInputGenerator input buffer - # auto -- let Vivado HLS decide - # block -- use BRAM - # distributed -- use LUTRAM - # ultra -- use URAM - "ram_style": ( - "s", - False, - "distributed", - {"auto", "block", "distributed", "ultra"}, - ), - "parallel_window": ("i", False, 0, {0, 1}), - } - my_attrs.update(super().get_nodeattr_types()) + my_attrs = {} + my_attrs.update(ConvolutionInputGenerator.get_nodeattr_types(self)) + my_attrs.update(HLSBackend.get_nodeattr_types(self)) return my_attrs - def get_normal_input_shape(self, ind=0): - ifm_dim_h, ifm_dim_w = self.get_nodeattr("IFMDim") - ifm_ch = self.get_nodeattr("IFMChannels") - ishape = (1, ifm_dim_h, ifm_dim_w, ifm_ch) - return ishape - - def get_folded_input_shape(self, ind=0): - ifm_dim_h, ifm_dim_w = self.get_nodeattr("IFMDim") - ifm_ch = self.get_nodeattr("IFMChannels") - simd = self.get_nodeattr("SIMD") - assert ifm_ch % simd == 0, "SIMD must divide IFMChannels" - wf = int(ifm_ch / simd) - folded_ishape = (1, ifm_dim_h, ifm_dim_w, wf, simd) - return folded_ishape - - def get_normal_output_shape(self, ind=0): - k_h, k_w = self.get_nodeattr("ConvKernelDim") - ifm_dim_h, ifm_dim_w = self.get_nodeattr("IFMDim") - ifm_ch = self.get_nodeattr("IFMChannels") - stride_h, stride_w = self.get_nodeattr("Stride") - dilation_h, dilation_w = self.get_nodeattr("Dilation") - pad = 0 - ofm_dim_h = compute_conv_output_dim(ifm_dim_h, k_h, stride_h, pad, dilation_h) - ofm_dim_w = compute_conv_output_dim(ifm_dim_w, k_w, stride_w, pad, dilation_w) - oshape = (1, ofm_dim_h, ofm_dim_w, k_h * k_w * ifm_ch) - return oshape - - def get_folded_output_shape(self, ind=0): - k_h, k_w = self.get_nodeattr("ConvKernelDim") - ifm_dim_h, ifm_dim_w = self.get_nodeattr("IFMDim") - ifm_ch = self.get_nodeattr("IFMChannels") - stride_h, stride_w = self.get_nodeattr("Stride") - dilation_h, dilation_w = self.get_nodeattr("Dilation") - simd = self.get_nodeattr("SIMD") - pad = 0 - ofm_dim_h = compute_conv_output_dim(ifm_dim_h, k_h, stride_h, pad, dilation_h) - ofm_dim_w = compute_conv_output_dim(ifm_dim_w, k_w, stride_w, pad, dilation_w) - assert ifm_ch % simd == 0, "SIMD must divide IFMChannels" - if self.use_parallel_window_output(): - wf = int((ifm_ch) // simd) - folded_oshape = (1, ofm_dim_h, ofm_dim_w, wf, k_h * k_w * simd) - else: - wf = int((k_h * k_w * ifm_ch) // simd) - folded_oshape = (1, ofm_dim_h, ofm_dim_w, wf, simd) - return folded_oshape - - def make_shape_compatible_op(self, model): - exp_ishape = self.get_normal_input_shape() - oshape = self.get_normal_output_shape() - ishape = tuple(model.get_tensor_shape(self.onnx_node.input[0])) - assert ishape == exp_ishape, "Unexpect input shape for ConvInpGen." - return super().make_const_shape_op(oshape) - - def infer_node_datatype(self, model): - node = self.onnx_node - # data type stays the same - dtype = model.get_tensor_datatype(node.input[0]) - model.set_tensor_datatype(node.output[0], dtype) - - def verify_node(self): - pass - - def get_input_datatype(self, ind=0): - """Returns FINN DataType of input.""" - return DataType[self.get_nodeattr("inputDataType")] - - def get_output_datatype(self, ind=0): - """Returns FINN DataType of output.""" - return DataType[self.get_nodeattr("outputDataType")] - - def get_instream_width(self, ind=0): - ibits = self.get_input_datatype().bitwidth() - simd = self.get_nodeattr("SIMD") - ifm_ch = self.get_nodeattr("IFMChannels") - assert ifm_ch % simd == 0, "SIMD must divide IFMChannels" - in_width = simd * ibits - return in_width - - def get_outstream_width(self, ind=0): - if self.use_parallel_window_output(): - # feed all window pixels in parallel - k_h, k_w = self.get_nodeattr("ConvKernelDim") - return self.get_instream_width() * k_h * k_w - else: - # if parallel variant not in use: same width for output and input stream - return self.get_instream_width() - - def get_number_output_values(self): - folded_oshape = self.get_folded_output_shape() - num_output_elems = np.prod(folded_oshape[:-1]) - return num_output_elems - def get_swu_variant(self): - # checks which variant of the 1D ConvolutionInputGenerator (SWU) can be used - # We have 5 variants: ConvolutionInputGenerator_1D_parallel, + # checks which variant of the ConvolutionInputGenerator (SWU) can be used + # For the 2D case, we have 4 variants: + # ConvolutioninputGenerator, ConvolutioninputGenerator_dws, + # ConvolutioninputGenerator_kernel_stride, ConvolutioninputGenerator_kernel_stride_dws + # For the 1D case, we have 5 variants: ConvolutionInputGenerator_1D_parallel, # ConvolutionInputGenerator_1D_dws_naive, ConvolutionInputGenerator_1D, # ConvolutioninputGenerator_1D_dws, ConvolutionInputGenerator_1D_dws_stride is_dws = self.get_nodeattr("depthwise") - is_strided = np.prod(self.get_nodeattr("Stride")) > 1 - is_stride_2 = np.prod(self.get_nodeattr("Stride")) == 2 - is_dilated = np.prod(self.get_nodeattr("Dilation")) > 1 - if self.use_parallel_window_output(): - return "ConvolutionInputGenerator_1D_parallel" - if not is_dws: - return "ConvolutionInputGenerator_1D" - if is_dws: - if (is_strided and not is_stride_2) or (is_dilated): - return "ConvolutionInputGenerator_1D_dws_naive" - elif is_stride_2: - return "ConvolutionInputGenerator_1D_dws_stride" - else: - return "ConvolutionInputGenerator_1D_dws" - - def get_1d_conv_attrs_normalized(self): - # support both (1, D) and (D, 1) cases transparently: - # For the kernel, presenting the input data of size D as - # [H, W] = [Y, X] = [1, D] or [D, 1] - # effectively gives the same result. - # For consistency and ease of programming, this function - # returns the attributes of the layer as follows: - # [H, W] = [Y, X] = [1, D] or [D, 1] are always mapped to [1, D]. - # The dummy ('1') dimension is the Y-dimension. - ifm_ch = self.get_nodeattr("IFMChannels") - k = self.get_nodeattr("ConvKernelDim") - ifm_dim = self.get_nodeattr("IFMDim") - ofm_dim = self.get_nodeattr("OFMDim") - stride = self.get_nodeattr("Stride") - dilation = self.get_nodeattr("Dilation") - - # see defines() for an explanation - if ifm_dim[1] == 1: - ifm_dim = ifm_dim[::-1] - ofm_dim = ofm_dim[::-1] - k = k[::-1] - stride = stride[::-1] - dilation = dilation[::-1] - - return (ifm_ch, ifm_dim, ofm_dim, k, stride, dilation) + if self.get_nodeattr("is1D"): + is_strided = np.prod(self.get_nodeattr("Stride")) > 1 + is_stride_2 = np.prod(self.get_nodeattr("Stride")) == 2 + is_dilated = np.prod(self.get_nodeattr("Dilation")) > 1 + if self.use_parallel_window_output(): + return "ConvolutionInputGenerator_1D_parallel" + if not is_dws: + return "ConvolutionInputGenerator_1D" + if is_dws: + if (is_strided and not is_stride_2) or (is_dilated): + return "ConvolutionInputGenerator_1D_dws_naive" + elif is_stride_2: + return "ConvolutionInputGenerator_1D_dws_stride" + else: + return "ConvolutionInputGenerator_1D_dws" + else: + k = self.get_nodeattr("ConvKernelDim")[0] + stride = self.get_nodeattr("Stride")[0] + hls_call = "ConvolutionInputGenerator" + if k % stride != 0: + hls_call += "_kernel_stride" + if is_dws: + hls_call += "_dws" + return hls_call def use_parallel_window_output(self): - # Check if simple "ConvolutionInputGenerator_1D_parallel" variant can be used to + if not self.get_nodeattr("is1D"): + return False + # If 1D, check if simple "ConvolutionInputGenerator_1D_parallel" variant can be used to # feed window in parallel to the following layer, enabling full SIMD unfolding. stride = self.get_nodeattr("Stride") dilation = self.get_nodeattr("Dilation") @@ -261,61 +134,88 @@ def use_parallel_window_output(self): def get_exp_cycles(self): simd = self.get_nodeattr("SIMD") - ( - ifm_ch, - [ifm_dim_h, ifm_dim_w], - [ofm_dim_h, ofm_dim_w], - [k_h, k_w], - [stride_h, stride_w], - [dilation_h, dilation_w], - ) = self.get_1d_conv_attrs_normalized() - - # since mmv != 1 is not supported yet, we set mmv for now to 1 - # mmv = 1 - # see https://github.com/Xilinx/finn-hlslib/blob/master/slidingwindow.h - swu_variant = self.get_swu_variant() - if swu_variant == "ConvolutionInputGenerator_1D_parallel": - exp_cycles = k_w + ofm_dim_w - elif swu_variant == "ConvolutionInputGenerator_1D": - exp_cycles = 1 + ofm_dim_w * k_w * ifm_ch / simd - elif swu_variant in [ - "ConvolutionInputGenerator_1D_dws", - "ConvolutionInputGenerator_1D_dws_stride", - ]: - exp_cycles = ( - 1 + ofm_dim_w * k_w * ifm_ch / simd + (ifm_ch / simd) * (k_w - 1) - (k_w - 1) - ) - elif swu_variant == "ConvolutionInputGenerator_1D_dws_naive": - cycles_read_block = ifm_dim_w * ifm_ch / simd - cycles_write_block = ofm_dim_w * k_w * ifm_ch / simd - exp_cycles = cycles_read_block + cycles_write_block + # 2D case + if not self.get_nodeattr("is1D"): + ifm_ch = self.get_nodeattr("IFMChannels") + k_h, k_w = self.get_nodeattr("ConvKernelDim") + ifm_dim_h, ifm_dim_w = self.get_nodeattr("IFMDim") + ofm_dim_h, ofm_dim_w = self.get_nodeattr("OFMDim") + stride_h, stride_w = self.get_nodeattr("Stride") + dilation_h, dilation_w = self.get_nodeattr("Dilation") + + # since mmv != 1 is not supported yet, we set mmv for now to 1 + mmv = 1 + # see https://github.com/Xilinx/finn-hlslib/blob/master/slidingwindow.h + cycles_write_block = (ofm_dim_w * k_w * k_h * (ifm_ch / simd)) / mmv + cycles_read_block = stride_w * ifm_dim_w * (ifm_ch / simd) + max_cycles = max(cycles_write_block, cycles_read_block) + exp_cycles = ifm_dim_w * k_h * dilation_h * (ifm_ch / simd) + ofm_dim_h * max_cycles + # 1D case + else: + ( + ifm_ch, + [ifm_dim_h, ifm_dim_w], + [ofm_dim_h, ofm_dim_w], + [k_h, k_w], + [stride_h, stride_w], + [dilation_h, dilation_w], + ) = self.get_1d_conv_attrs_normalized() + + swu_variant = self.get_swu_variant() + if swu_variant == "ConvolutionInputGenerator_1D_parallel": + exp_cycles = k_w + ofm_dim_w + elif swu_variant == "ConvolutionInputGenerator_1D": + exp_cycles = 1 + ofm_dim_w * k_w * ifm_ch / simd + elif swu_variant in [ + "ConvolutionInputGenerator_1D_dws", + "ConvolutionInputGenerator_1D_dws_stride", + ]: + exp_cycles = ( + 1 + ofm_dim_w * k_w * ifm_ch / simd + (ifm_ch / simd) * (k_w - 1) - (k_w - 1) + ) + elif swu_variant == "ConvolutionInputGenerator_1D_dws_naive": + cycles_read_block = ifm_dim_w * ifm_ch / simd + cycles_write_block = ofm_dim_w * k_w * ifm_ch / simd + exp_cycles = cycles_read_block + cycles_write_block return int(exp_cycles) def bram_estimation(self): simd = self.get_nodeattr("SIMD") - ( - ifm_ch, - [ifm_dim_h, ifm_dim_w], - [ofm_dim_h, ofm_dim_w], - [k_h, k_w], - [stride_h, stride_w], - [dilation_h, dilation_w], - ) = self.get_1d_conv_attrs_normalized() + is1D = self.get_nodeattr("is1D") + if not is1D: + ifm_ch = self.get_nodeattr("IFMChannels") + ifm_dim = self.get_nodeattr("IFMDim")[0] + k = self.get_nodeattr("ConvKernelDim")[0] + stride = self.get_nodeattr("Stride")[0] + else: + ( + ifm_ch, + [ifm_dim_h, ifm_dim_w], + [ofm_dim_h, ofm_dim_w], + [k_h, k_w], + [stride_h, stride_w], + [dilation_h, dilation_w], + ) = self.get_1d_conv_attrs_normalized() ram_style = self.get_nodeattr("ram_style") swu_variant = self.get_swu_variant() if swu_variant == "ConvolutionInputGenerator_1D_parallel": return 0 if ram_style == "block" or ram_style == "auto": - if swu_variant == "ConvolutionInputGenerator_1D": - ram_depth = (k_w - 1) * ifm_ch / simd - elif swu_variant == "ConvolutionInputGenerator_1D_dws_naive": - ram_depth = ifm_dim_w * ifm_ch / simd - elif swu_variant in [ - "ConvolutionInputGenerator_1D_dws", - "ConvolutionInputGenerator_1D_dws_stride", - ]: - ram_depth = k_w * ifm_ch / simd + if not is1D: + ram_depth = ifm_dim * ifm_ch / simd + else: + if swu_variant == "ConvolutionInputGenerator_1D": + ram_depth = (k_w - 1) * ifm_ch / simd + elif swu_variant == "ConvolutionInputGenerator_1D_dws_naive": + ram_depth = ifm_dim_w * ifm_ch / simd + elif swu_variant in [ + "ConvolutionInputGenerator_1D_dws", + "ConvolutionInputGenerator_1D_dws_stride", + ]: + ram_depth = k_w * ifm_ch / simd + # after calculate the ram_depth depending on the variant + # determine ram_width if ram_depth <= 512: ram_width = 36 elif ram_depth <= 1024: @@ -328,27 +228,48 @@ def bram_estimation(self): ram_width = 2 else: ram_width = 1 + width_mul = math.ceil(simd * self.get_input_datatype().bitwidth() / ram_width) - depth_mul = math.ceil(ram_depth / 18432) - return width_mul * depth_mul + if not is1D: + depth_mul = math.ceil(ifm_dim * ifm_ch / simd / ram_depth) + return int((k + stride) * width_mul * depth_mul) + else: + depth_mul = math.ceil(ram_depth / 18432) + return int(width_mul * depth_mul) else: return 0 def lut_estimation(self): simd = self.get_nodeattr("SIMD") - ( - ifm_ch, - [ifm_dim_h, ifm_dim_w], - [ofm_dim_h, ofm_dim_w], - [k_h, k_w], - [stride_h, stride_w], - [dilation_h, dilation_w], - ) = self.get_1d_conv_attrs_normalized() + is1D = self.get_noadeattr("is1D") + if not is1D: + ifm_ch = self.get_nodeattr("IFMChannels") + ifm_dim = self.get_nodeattr("IFMDim")[0] + k = self.get_nodeattr("ConvKernelDim")[0] + stride = self.get_nodeattr("Stride")[0] + else: + ( + ifm_ch, + [ifm_dim_h, ifm_dim_w], + [ofm_dim_h, ofm_dim_w], + [k_h, k_w], + [stride_h, stride_w], + [dilation_h, dilation_w], + ) = self.get_1d_conv_attrs_normalized() ram_style = self.get_nodeattr("ram_style") swu_variant = self.get_swu_variant() if swu_variant == "ConvolutionInputGenerator_1D_parallel": ram_luts = math.ceil(simd * self.get_input_datatype().bitwidth() * (k_w + 1) / 64) - elif ram_style == "distributed": + if ram_style == "distributed": + if not is1D: + ram_luts = int( + (k + stride) + * ( + simd + * self.get_input_datatype().bitwidth() + * math.ceil(ifm_dim * ifm_ch / simd / 64) + ) + ) if swu_variant == "ConvolutionInputGenerator_1D": ram_luts = math.ceil(self.get_input_datatype().bitwidth() * (k_w - 1) * ifm_ch / 64) elif swu_variant == "ConvolutionInputGenerator_1D_dws_naive": @@ -364,34 +285,51 @@ def lut_estimation(self): def uram_estimation(self): simd = self.get_nodeattr("SIMD") - ( - ifm_ch, - [ifm_dim_h, ifm_dim_w], - [ofm_dim_h, ofm_dim_w], - [k_h, k_w], - [stride_h, stride_w], - [dilation_h, dilation_w], - ) = self.get_1d_conv_attrs_normalized() + is1D = self.get_nodeattr("is1D") + if not is1D: + ifm_ch = self.get_nodeattr("IFMChannels") + ifm_dim = self.get_nodeattr("IFMDim")[0] + k = self.get_nodeattr("ConvKernelDim")[0] + stride = self.get_nodeattr("Stride")[0] + else: + ( + ifm_ch, + [ifm_dim_h, ifm_dim_w], + [ofm_dim_h, ofm_dim_w], + [k_h, k_w], + [stride_h, stride_w], + [dilation_h, dilation_w], + ) = self.get_1d_conv_attrs_normalized() + ram_style = self.get_nodeattr("ram_style") swu_variant = self.get_swu_variant() if swu_variant == "ConvolutionInputGenerator_1D_parallel": return 0 - elif ram_style == "ultra": - if swu_variant == "ConvolutionInputGenerator_1D": - width_mul = math.ceil(simd * self.get_input_datatype().bitwidth() / 72) - depth_mul = math.ceil((k_w - 1) * ifm_ch / simd / 4096) - return width_mul * depth_mul - elif swu_variant == "ConvolutionInputGenerator_1D_dws_naive": - width_mul = math.ceil(simd * self.get_input_datatype().bitwidth() / 72) - depth_mul = math.ceil(ifm_dim_w * ifm_ch / simd / 4096) - return width_mul * depth_mul - elif swu_variant in [ - "ConvolutionInputGenerator_1D_dws", - "ConvolutionInputGenerator_1D_dws_stride", - ]: - width_mul = math.ceil(simd * self.get_input_datatype().bitwidth() / 72) - depth_mul = math.ceil(k_w * ifm_ch / simd / 4096) - return width_mul * depth_mul + if ram_style == "ultra": + if not is1D: + return int( + (k + stride) + * ( + math.ceil(simd * self.get_input_datatype().bitwidth() / 64) + * math.ceil(ifm_dim * ifm_ch / simd / 4096) + ) + ) + else: + if swu_variant == "ConvolutionInputGenerator_1D": + width_mul = math.ceil(simd * self.get_input_datatype().bitwidth() / 72) + depth_mul = math.ceil((k_w - 1) * ifm_ch / simd / 4096) + return width_mul * depth_mul + elif swu_variant == "ConvolutionInputGenerator_1D_dws_naive": + width_mul = math.ceil(simd * self.get_input_datatype().bitwidth() / 72) + depth_mul = math.ceil(ifm_dim_w * ifm_ch / simd / 4096) + return width_mul * depth_mul + elif swu_variant in [ + "ConvolutionInputGenerator_1D_dws", + "ConvolutionInputGenerator_1D_dws_stride", + ]: + width_mul = math.ceil(simd * self.get_input_datatype().bitwidth() / 72) + depth_mul = math.ceil(k_w * ifm_ch / simd / 4096) + return width_mul * depth_mul else: return 0 @@ -485,18 +423,28 @@ def global_includes(self): def defines(self, var): numReps = 1 - ( - ifm_ch, - [ifm_dim_h, ifm_dim_w], - [ofm_dim_h, ofm_dim_w], - [k_h, k_w], - [stride_h, stride_w], - [dilation_h, dilation_w], - ) = self.get_1d_conv_attrs_normalized() + is1D = self.get_nodeattr("is1D") simd = self.get_nodeattr("SIMD") ifm_precision = self.get_input_datatype().bitwidth() + if not is1D: + ifm_dim = self.get_nodeattr("IFMDim")[0] + ifm_ch = self.get_nodeattr("IFMChannels") + ofm_dim = self.get_nodeattr("OFMDim")[0] + k = self.get_nodeattr("ConvKernelDim")[0] + stride = self.get_nodeattr("Stride")[0] + else: + ( + ifm_ch, + [ifm_dim_h, ifm_dim_w], + [ofm_dim_h, ofm_dim_w], + [k_h, k_w], + [stride_h, stride_w], + [dilation_h, dilation_w], + ) = self.get_1d_conv_attrs_normalized() + swu_variant = self.get_swu_variant() + # check all different 1D scenarios if swu_variant in [ "ConvolutionInputGenerator_1D_parallel", "ConvolutionInputGenerator_1D", @@ -523,7 +471,7 @@ def defines(self, var): numReps, ) ] - if swu_variant == "ConvolutionInputGenerator_1D_dws": + elif swu_variant == "ConvolutionInputGenerator_1D_dws": self.code_gen_dict["$DEFINES$"] = [ """ #define ConvKernelDim1_x {}\n @@ -543,7 +491,7 @@ def defines(self, var): numReps, ) ] - if swu_variant == "ConvolutionInputGenerator_1D_dws_naive": + elif swu_variant == "ConvolutionInputGenerator_1D_dws_naive": self.code_gen_dict["$DEFINES$"] = [ """ #define ConvKernelDim1_x {}\n @@ -567,6 +515,16 @@ def defines(self, var): numReps, ) ] + # default to 2D cases + else: + self.code_gen_dict["$DEFINES$"] = [ + """#define ConvKernelDim1 {}\n #define IFMChannels1 {}\n + #define Input_precision1 {}\n #define IFMDim1 {}\n + #define OFMDim1 {}\n #define SIMD1 {}\n + #define Stride1 {}\n #define numReps {}""".format( + k, ifm_ch, ifm_precision, ifm_dim, ofm_dim, simd, stride, numReps + ) + ] def read_npy_data(self): code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") @@ -617,7 +575,7 @@ def docompute(self): hls_ram_style = map_to_hls_ram_style[ram_style] swu_variant = self.get_swu_variant() - # check which ConvolutionInputGenerator is needed + # check which 1D ConvolutionInputGenerator is needed if swu_variant == "ConvolutionInputGenerator_1D_parallel": self.code_gen_dict["$DOCOMPUTE$"] = [ """{} @@ -634,7 +592,7 @@ def docompute(self): swu_variant, self.hls_sname(), self.hls_sname(), hls_ram_style ) ] - if swu_variant == "ConvolutionInputGenerator_1D_dws": + elif swu_variant == "ConvolutionInputGenerator_1D_dws": self.code_gen_dict["$DOCOMPUTE$"] = [ """{} @@ -642,7 +600,7 @@ def docompute(self): swu_variant, self.hls_sname(), self.hls_sname(), hls_ram_style ) ] - if swu_variant == "ConvolutionInputGenerator_1D_dws_stride": + elif swu_variant == "ConvolutionInputGenerator_1D_dws_stride": self.code_gen_dict["$DOCOMPUTE$"] = [ """{} @@ -650,7 +608,7 @@ def docompute(self): swu_variant, self.hls_sname(), self.hls_sname(), hls_ram_style ) ] - if swu_variant == "ConvolutionInputGenerator_1D_dws_naive": + elif swu_variant == "ConvolutionInputGenerator_1D_dws_naive": self.code_gen_dict["$DOCOMPUTE$"] = [ """{} @@ -658,6 +616,13 @@ def docompute(self): swu_variant, self.hls_sname(), self.hls_sname(), hls_ram_style ) ] + else: + self.code_gen_dict["$DOCOMPUTE$"] = [ + """{} (in0_{}, out_{}, numReps, {});""".format( + swu_variant, self.hls_sname(), self.hls_sname(), hls_ram_style + ) + ] def dataoutstrm(self): code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") diff --git a/src/finn/custom_op/fpgadataflow/rtl/__init__.py b/src/finn/custom_op/fpgadataflow/rtl/__init__.py index 81110d8b9f..ac75371381 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/__init__.py +++ b/src/finn/custom_op/fpgadataflow/rtl/__init__.py @@ -26,6 +26,9 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +from finn.custom_op.fpgadataflow.rtl.convolutioninputgenerator_rtl import ( + ConvolutionInputGenerator_rtl, +) from finn.custom_op.fpgadataflow.rtl.fmpadding_rtl import FMPadding_rtl from finn.custom_op.fpgadataflow.rtl.streamingdatawidthconverter_rtl import ( StreamingDataWidthConverter_rtl, @@ -35,5 +38,6 @@ # make sure new HLSCustomOp subclasses are imported here so that they get # registered and plug in correctly into the infrastructure +custom_op["ConvolutionInputGenerator_rtl"] = ConvolutionInputGenerator_rtl custom_op["FMPadding_rtl"] = FMPadding_rtl custom_op["StreamingDataWidthConverter_rtl"] = StreamingDataWidthConverter_rtl diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/convolutioninputgenerator_rtl.py similarity index 85% rename from src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py rename to src/finn/custom_op/fpgadataflow/rtl/convolutioninputgenerator_rtl.py index 734f75a973..ba3921745f 100755 --- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/convolutioninputgenerator_rtl.py @@ -1,4 +1,4 @@ -# Copyright (C) 2022, Advanced Micro Devices, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -34,7 +34,10 @@ from qonnx.custom_op.general import im2col from qonnx.custom_op.general.im2col import compute_conv_output_dim -from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp +from finn.custom_op.fpgadataflow.convolutioninputgenerator import ( + ConvolutionInputGenerator, +) +from finn.custom_op.fpgadataflow.rtlbackend import RTLBackend from finn.util.basic import get_rtlsim_trace_depth, make_build_dir from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy @@ -56,169 +59,34 @@ # NOTE: "Parallel" implementation style not yet implemented in this version! -class ConvolutionInputGenerator_rtl(HLSCustomOp): - """Class that does not correspond to one of the finn-hlslib ConvolutionInputGenerator - (sliding window) function variants. Generates an RTL ConvolutionInputGenerator - implementation based on (System-)Verilog templates, defined in finn-rtllib/swg.""" +class ConvolutionInputGenerator_rtl(ConvolutionInputGenerator, RTLBackend): + """Class that corresponds to finn-rtllib swg module. + Generates an RTL ConvolutionInputGenerator implementation + based on (System-)Verilog templates, defined in finn-rtllib/swg.""" def __init__(self, onnx_node, **kwargs): super().__init__(onnx_node, **kwargs) def get_nodeattr_types(self): my_attrs = { - "ConvKernelDim": ("ints", True, []), # [H, W] = [Y, X] - "IFMChannels": ("i", True, 0), - "IFMDim": ("ints", True, []), # [H, W] = [Y, X] - "OFMDim": ("ints", True, []), # [H, W] = [Y, X] - "SIMD": ("i", True, 0), # additional parallelization parameter - not yet implemented "M": ("i", False, 1), - # Enable parallel window output (requires full SIMD unfolding) - "parallel_window": ("i", False, 0, {0, 1}), - "Stride": ("ints", True, []), # [H, W] = [Y, X] - "Dilation": ("ints", True, []), # [H, W] = [Y, X] - # FINN DataTypes for inputs, weights, outputs - "inputDataType": ("s", True, ""), - "outputDataType": ("s", True, ""), - "depthwise": ("i", False, 0, {0, 1}), # Enable reprogrammable implementation to change FM dimensions, # stride, or dilation during runtime (requires parallel_window = 0) "dynamic_mode": ("i", False, 0, {0, 1}), - # FPGA resource type for ConvolutionInputGenerator input buffer - # auto -- let Vivado decide - # block -- use BRAM - # distributed -- use LUTRAM - # ultra -- use URAM - "ram_style": ( - "s", - False, - "auto", - {"auto", "block", "distributed", "ultra"}, - ), - # attribute to save top module name - not user configurable - "gen_top_module": ("s", False, ""), } - my_attrs.update(super().get_nodeattr_types()) + my_attrs.update(ConvolutionInputGenerator.get_nodeattr_types(self)) + my_attrs.update(RTLBackend.get_nodeattr_types(self)) return my_attrs - def get_normal_input_shape(self, ind=0): - ifm_dim_h, ifm_dim_w = self.get_nodeattr("IFMDim") - ifm_ch = self.get_nodeattr("IFMChannels") - ishape = (1, ifm_dim_h, ifm_dim_w, ifm_ch) - return ishape - - def get_folded_input_shape(self, ind=0): - ifm_dim_h, ifm_dim_w = self.get_nodeattr("IFMDim") - ifm_ch = self.get_nodeattr("IFMChannels") - simd = self.get_nodeattr("SIMD") - assert ifm_ch % simd == 0, "SIMD must divide IFMChannels" - wf = int(ifm_ch / simd) - folded_ishape = (1, ifm_dim_h, ifm_dim_w, wf, simd) - return folded_ishape - - def get_normal_output_shape(self, ind=0): - k_h, k_w = self.get_nodeattr("ConvKernelDim") - ifm_dim_h, ifm_dim_w = self.get_nodeattr("IFMDim") - ifm_ch = self.get_nodeattr("IFMChannels") - stride_h, stride_w = self.get_nodeattr("Stride") - dilation_h, dilation_w = self.get_nodeattr("Dilation") - pad = 0 - ofm_dim_h = compute_conv_output_dim(ifm_dim_h, k_h, stride_h, pad, dilation_h) - ofm_dim_w = compute_conv_output_dim(ifm_dim_w, k_w, stride_w, pad, dilation_w) - oshape = (1, ofm_dim_h, ofm_dim_w, k_h * k_w * ifm_ch) - return oshape - - def get_folded_output_shape(self, ind=0): - k_h, k_w = self.get_nodeattr("ConvKernelDim") - ifm_dim_h, ifm_dim_w = self.get_nodeattr("IFMDim") - ifm_ch = self.get_nodeattr("IFMChannels") - stride_h, stride_w = self.get_nodeattr("Stride") - dilation_h, dilation_w = self.get_nodeattr("Dilation") - simd = self.get_nodeattr("SIMD") - pad = 0 - ofm_dim_h = compute_conv_output_dim(ifm_dim_h, k_h, stride_h, pad, dilation_h) - ofm_dim_w = compute_conv_output_dim(ifm_dim_w, k_w, stride_w, pad, dilation_w) - assert ifm_ch % simd == 0, "SIMD must divide IFMChannels" - if self.get_nodeattr("parallel_window"): - wf = int((ifm_ch) // simd) - folded_oshape = (1, ofm_dim_h, ofm_dim_w, wf, k_h * k_w * simd) - else: - wf = int((k_h * k_w * ifm_ch) // simd) - folded_oshape = (1, ofm_dim_h, ofm_dim_w, wf, simd) - return folded_oshape - - def make_shape_compatible_op(self, model): - exp_ishape = self.get_normal_input_shape() - oshape = self.get_normal_output_shape() - ishape = tuple(model.get_tensor_shape(self.onnx_node.input[0])) - assert ishape == exp_ishape, "Unexpect input shape for ConvInpGen." - return super().make_const_shape_op(oshape) - - def infer_node_datatype(self, model): - node = self.onnx_node - # data type stays the same - dtype = model.get_tensor_datatype(node.input[0]) - model.set_tensor_datatype(node.output[0], dtype) - - def verify_node(self): - pass - - def get_input_datatype(self, ind=0): - """Returns FINN DataType of input.""" - return DataType[self.get_nodeattr("inputDataType")] - - def get_output_datatype(self, ind=0): - """Returns FINN DataType of output.""" - return DataType[self.get_nodeattr("outputDataType")] - - def get_instream_width(self, ind=0): - ibits = self.get_input_datatype().bitwidth() - simd = self.get_nodeattr("SIMD") - ifm_ch = self.get_nodeattr("IFMChannels") - assert ifm_ch % simd == 0, "SIMD must divide IFMChannels" - in_width = simd * ibits - return in_width - - def get_outstream_width(self, ind=0): - if self.get_nodeattr("parallel_window"): - # feed all window pixels in parallel - k_h, k_w = self.get_nodeattr("ConvKernelDim") - return self.get_instream_width() * k_h * k_w - else: - # if parallel variant not in use: same width for output and input stream - return self.get_instream_width() - def get_number_input_values(self): """Function to get the number of expected input values.""" folded_ishape = self.get_folded_input_shape() num_input_elems = np.prod(folded_ishape[:-1]) return num_input_elems - def get_number_output_values(self): - folded_oshape = self.get_folded_output_shape() - num_output_elems = np.prod(folded_oshape[:-1]) - return num_output_elems - - def get_1d_conv_attrs_normalized(self): - """Returns normalized spatial attributes, where H=1 for the 1D case.""" - # normalize FM dimensions so that: - # [H, W] = [Y, X] = [1, D] or [D, 1] are always mapped to [1, D]. - # The dummy ('1') dimension is the Y-dimension. - ifm_ch = self.get_nodeattr("IFMChannels") - k = self.get_nodeattr("ConvKernelDim") - ifm_dim = self.get_nodeattr("IFMDim") - ofm_dim = self.get_nodeattr("OFMDim") - stride = self.get_nodeattr("Stride") - dilation = self.get_nodeattr("Dilation") - - if ifm_dim[1] == 1: - ifm_dim = ifm_dim[::-1] - ofm_dim = ofm_dim[::-1] - k = k[::-1] - stride = stride[::-1] - dilation = dilation[::-1] - - return (ifm_ch, ifm_dim, ofm_dim, k, stride, dilation) + def use_parallel_window_output(self): + return self.get_nodeattr("parallel_window") def get_buffer_depth(self): """Returns total depth of the internal buffer, depending on @@ -1170,55 +1038,3 @@ def get_dynamic_config(self, ifm_dim=None, stride=None, dilation=None): "cfg_last_write": (15 * 4, int(code_gen_dict["$LAST_WRITE_ELEM$"][0])), } return config - - def code_generation_ipgen(self, model, fpgapart, clk): - """Generates (System-)Verilog code for IP generation (instead of HLS code).""" - self.generate_hdl() - - def ipgen_singlenode_code(self): - """Not implemented (RTL component).""" - pass - - def code_generation_cppsim(self, model): - """Not implemented (RTL component).""" - pass - - def compile_singlenode_code(self): - """Not implemented (RTL component).""" - pass - - def global_includes(self): - """Not implemented (RTL component).""" - pass - - def defines(self, var): - """Not implemented (RTL component).""" - pass - - def read_npy_data(self): - """Not implemented (RTL component).""" - pass - - def strm_decl(self): - """Not implemented (RTL component).""" - pass - - def docompute(self): - """Not implemented (RTL component).""" - pass - - def dataoutstrm(self): - """Not implemented (RTL component).""" - pass - - def save_as_npy(self): - """Not implemented (RTL component).""" - pass - - def blackboxfunction(self): - """Not implemented (RTL component).""" - pass - - def pragmas(self): - """Not implemented (RTL component).""" - pass diff --git a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py index a65c925f97..28b7dba9cb 100644 --- a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py +++ b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py @@ -58,6 +58,7 @@ def apply(self, model): i2c_input = n.input[0] i2c_output = n.output[0] i2c_in_shape = model.get_tensor_shape(i2c_input) + i2c_out_shape = model.get_tensor_shape(i2c_output) dt = model.get_tensor_datatype(i2c_input) if not dt.is_integer(): warnings.warn("%s : Input is not int. Can't infer ConvInpGen." % n.name) @@ -69,11 +70,13 @@ def apply(self, model): pad_h = pad_attr[0] + pad_attr[2] pad_w = pad_attr[1] + pad_attr[3] dilation_h, dilation_w = i2c_inst.get_nodeattr("dilations") - # temporary checks until non-square conv support is finalized pad_val = i2c_inst.get_nodeattr("pad_value") + depthwise = i2c_inst.get_nodeattr("depthwise") ifm_ch = i2c_in_shape[-1] ifm_dim_h = i2c_in_shape[1] ifm_dim_w = i2c_in_shape[2] + ofm_dim_h = i2c_out_shape[1] + ofm_dim_w = i2c_out_shape[2] # default params for ConvolutionInputGenerator ConvInpGen_node_idx = node_ind @@ -122,9 +125,9 @@ def apply(self, model): is_square_image = ConvInpGen_idim_h == ConvInpGen_idim_w is_equal_stride = stride_h == stride_w - # Ensure that only supported HLS nodes are inserted + is_1D = (ifm_dim_h == 1) or (ifm_dim_w == 1) if (stride_h > 1 or stride_w > 1) and is_kernel_pointwise: - downsample_1D = (ifm_dim_h == 1) or (ifm_dim_w == 1) + downsample_1D = is_1D is1D_unitx = ifm_dim_w == 1 downsample_2D = (not downsample_1D) and is_square_image and is_equal_stride if not (downsample_1D or downsample_2D): @@ -148,9 +151,27 @@ def apply(self, model): is1D=downsample_1D, is1D_unitx=is1D_unitx, ) - graph.node.insert(ConvInpGen_node_idx, ConvInpGen_node) else: - continue + ConvInpGen_node = helper.make_node( + "ConvolutionInputGenerator", + [ConvInpGen_input], + [i2c_output], + domain="finn.custom_op.fpgadataflow", + backend="fpgadataflow", + ConvKernelDim=[k_h, k_w], + IFMChannels=ifm_ch, + IFMDim=[ConvInpGen_idim_h, ConvInpGen_idim_w], + OFMDim=[ofm_dim_h, ofm_dim_w], + SIMD=ifm_ch, + Stride=[stride_h, stride_w], + Dilation=[dilation_h, dilation_w], + inputDataType=dt.name, + outputDataType=dt.name, + depthwise=depthwise, + is1D=is_1D, + name="ConvolutionInputGenerator_" + n.name, + ) + graph.node.insert(ConvInpGen_node_idx, ConvInpGen_node) # remove old nodes graph.node.remove(n) graph_modified = True diff --git a/src/finn/transformation/fpgadataflow/specialize_layers.py b/src/finn/transformation/fpgadataflow/specialize_layers.py index eff40f83f3..6c1def628f 100644 --- a/src/finn/transformation/fpgadataflow/specialize_layers.py +++ b/src/finn/transformation/fpgadataflow/specialize_layers.py @@ -79,6 +79,18 @@ def _determine_impl_style(node): # check if user setting can be fulfilled # otherwise change impl_style if impl_style == "hls": + if optype == "ConvolutionInputGenerator": + if not _swg_hls_possible(node): + warn_str = ( + """Settings are not supported in HLS. Node %s will automatically be + set to RTL variant.""" + % node.name + ) + warnings.warn(warn_str) + return "rtl" + else: + return "hls" + if hls_variant: return "hls" elif rtl_variant: @@ -149,6 +161,30 @@ def _dwc_determine_impl_style(node): return "hls" +def _swg_hls_possible(node): + # the 2D HLS implementation for SWG + # can only be used for square inputs + # and no dilation + swg = getCustomOp(node) + # extract all attributes to check + k = swg.get_nodeattr("ConvKernelDim") + ifm_dim = swg.get_nodeattr("IFMDim") + ofm_dim = swg.get_nodeattr("OFMDim") + s = swg.get_nodeattr("Stride") + d = swg.get_nodeattr("Dilation") + # check if square and dilation=1 + if ( + k[0] == k[1] + and ifm_dim[0] == ifm_dim[1] + and ofm_dim[0] == ofm_dim[1] + and s[0] == s[1] + and d[0] == d[1] == 1 + ): + return True + else: + return False + + class SpecializeLayers(Transformation): """Specialize all layers to either HLS or RTL variants""" diff --git a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py index d94b5d6399..07de85d0b5 100644 --- a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py +++ b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (c) 2020-2022, Xilinx +# Copyright (C) 2023-2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -32,11 +33,13 @@ from onnx import TensorProto, helper from qonnx.core.datatype import DataType from qonnx.core.modelwrapper import ModelWrapper +from qonnx.custom_op.general.im2col import compute_conv_output_dim from qonnx.custom_op.registry import getCustomOp from qonnx.transformation.general import GiveUniqueNodeNames from qonnx.util.basic import gen_finn_dt_tensor, qonnx_make_model import finn.core.onnx_exec as oxe +import finn.transformation.fpgadataflow.convert_to_hw_layers as to_hw from finn.analysis.fpgadataflow.exp_cycles_per_layer import exp_cycles_per_layer from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP @@ -44,26 +47,34 @@ from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers -def make_single_im2col_modelwrapper(k, ifm_ch, ifm_dim, ofm_dim, simd, stride, dilation, idt): +def make_single_im2col_modelwrapper(k, ifm_ch, ifm_dim, ofm_dim, stride, dilation, idt, dw): + k_h, k_w = k + ifm_dim_h, ifm_dim_w = ifm_dim + stride_h, stride_w = stride + dilation_h, dilation_w = dilation + ofm_dim_h, ofm_dim_w = ofm_dim + odt = idt - inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, [1, ifm_dim, ifm_dim, ifm_ch]) + inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, [1, ifm_dim_h, ifm_dim_w, ifm_ch]) outp = helper.make_tensor_value_info( - "outp", TensorProto.FLOAT, [1, ofm_dim, ofm_dim, k * k * ifm_ch] + "outp", TensorProto.FLOAT, [1, ofm_dim_h, ofm_dim_w, k_h * k_w * ifm_ch] ) im2col_node = helper.make_node( "Im2Col", ["inp"], ["outp"], - domain="qonnx.custom_op.general", - stride=[stride, stride], - kernel_size=[k, k], - input_shape=str((1, ifm_dim, ifm_dim, ifm_ch)), + domain="finn.custom_op.general", + stride=[stride_h, stride_w], + kernel_size=[k_h, k_w], + input_shape=str((1, ifm_dim_h, ifm_dim_w, ifm_ch)), + dilations=[dilation_h, dilation_w], pad_amount=[0, 0, 0, 0], pad_value=0, - dilations=[dilation, dilation], + depthwise=dw, ) graph = helper.make_graph( nodes=[im2col_node], name="im2col_graph", inputs=[inp], outputs=[outp] @@ -78,86 +89,209 @@ def make_single_im2col_modelwrapper(k, ifm_ch, ifm_dim, ofm_dim, simd, stride, d return model -def make_single_slidingwindow_modelwrapper( - k, ifm_ch, ifm_dim, ofm_dim, simd, stride, dilation, idt, dw=0 +def prepare_inputs(input_tensor): + return {"inp": input_tensor} + + +# input datatype +@pytest.mark.parametrize("idt", [DataType["BIPOLAR"], DataType["INT2"]]) +# kernel size +@pytest.mark.parametrize("k", [[2, 2], [3, 3]]) +# input dimension +@pytest.mark.parametrize("ifm_dim", [[6, 6], [8, 8]]) +# input channels +@pytest.mark.parametrize("ifm_ch", [2, 4]) +# Stride +@pytest.mark.parametrize("stride", [[1, 1], [2, 2]]) +# Dilation +@pytest.mark.parametrize("dilation", [[1, 1], [2, 2]]) +# execution mode +@pytest.mark.parametrize("exec_mode", ["cppsim", "rtlsim"]) +# input channel parallelism ("SIMD") +@pytest.mark.parametrize("simd", [1, 2]) +# depthwise +@pytest.mark.parametrize("dw", [0, 1]) +# parallel_window enable (MMV_out = M*K) +@pytest.mark.parametrize("parallel_window", [0, 1]) +# in/out MMV ("M") +@pytest.mark.parametrize("m", [1]) +# Flip dimensions +@pytest.mark.parametrize("flip", [False]) +# implementation style +@pytest.mark.parametrize("impl_style", ["rtl", "hls"]) +@pytest.mark.fpgadataflow +@pytest.mark.slow +@pytest.mark.vivado +def test_fpgadataflow_slidingwindow( + idt, + k, + ifm_dim, + ifm_ch, + stride, + dilation, + exec_mode, + simd, + dw, + parallel_window, + m, + flip, + impl_style, ): - odt = idt - inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, [1, ifm_dim, ifm_dim, ifm_ch]) - outp = helper.make_tensor_value_info( - "outp", TensorProto.FLOAT, [1, ofm_dim, ofm_dim, k * k * ifm_ch] - ) + if flip: + if ( + ifm_dim[0] == ifm_dim[1] + and k[0] == k[1] + and stride[0] == stride[1] + and dilation[0] == dilation[1] + ): + pytest.skip("Dimension flip would have no effect") + k = k[::-1] + ifm_dim = ifm_dim[::-1] + stride = stride[::-1] + dilation = dilation[::-1] - SlidingWindow_node = helper.make_node( - "ConvolutionInputGenerator", - ["inp"], - ["outp"], - domain="finn.custom_op.fpgadataflow", - backend="fpgadataflow", - ConvKernelDim=[k, k], - IFMChannels=ifm_ch, - IFMDim=[ifm_dim, ifm_dim], - OFMDim=[ofm_dim, ofm_dim], - SIMD=simd, - Stride=[stride, stride], - Dilation=[dilation, dilation], - inputDataType=idt.name, - outputDataType=odt.name, - depthwise=dw, - ) - graph = helper.make_graph( - nodes=[SlidingWindow_node], - name="slidingwindow_graph", - inputs=[inp], - outputs=[outp], - ) + k_h, k_w = k + ifm_dim_h, ifm_dim_w = ifm_dim + stride_h, stride_w = stride + dilation_h, dilation_w = dilation - model = qonnx_make_model(graph, producer_name="slidingwindow-model") - model = ModelWrapper(model) + kernel_width = (k_w - 1) * dilation_w + 1 # incl. dilation + kernel_height = (k_h - 1) * dilation_h + 1 # incl. dilation - model.set_tensor_datatype("inp", idt) - model.set_tensor_datatype("outp", odt) + if simd > ifm_ch: + pytest.skip("SIMD cannot be larger than number of input channels") + if ifm_ch % simd != 0: + pytest.skip("SIMD must divide number of input channels") + if kernel_height > ifm_dim_h or stride_h > ifm_dim_h: + pytest.skip("Illegal convolution configuration: kernel or stride > FM dimension") + if kernel_width > ifm_dim_w or stride_w > ifm_dim_w: + pytest.skip("Illegal convolution configuration: kernel or stride > FM dimension") + if (k_h == 1 and dilation_h != 1) or (k_w == 1 and dilation_w != 1): + pytest.skip("Illegal convolution configuration: dilation for unitary kernel dim") + if ((stride_h > k_h) or (stride_w > k_w)) and not (parallel_window or (k_h == 1 and k_w == 1)): + pytest.skip("Not all combinations for stride > k edge case supported in default mode") + if parallel_window and simd != ifm_ch and not (dw or (k_h == 1 and k_w == 1)): + pytest.skip("Parallel window requires SIMD=C for non-depthwise case") - return model + ofm_dim_h = compute_conv_output_dim(ifm_dim_h, k_h, stride_h, 0, dilation_h) + ofm_dim_w = compute_conv_output_dim(ifm_dim_w, k_w, stride_w, 0, dilation_w) + ofm_dim = [ofm_dim_h, ofm_dim_w] + x = gen_finn_dt_tensor(idt, (1, ifm_dim_h, ifm_dim_w, ifm_ch)) + # prepare input data + input_dict = prepare_inputs(x) + model = make_single_im2col_modelwrapper(k, ifm_ch, ifm_dim, ofm_dim, stride, dilation, idt, dw) + y_expected = oxe.execute_onnx(model, input_dict)["outp"] -def prepare_inputs(input_tensor): - return {"inp": input_tensor} + model = model.transform(to_hw.InferConvInpGen()) + y_produced = oxe.execute_onnx(model, input_dict)["outp"] + assert (y_produced == y_expected).all() + # set impl_style + inst = getCustomOp(model.get_nodes_by_op_type("ConvolutionInputGenerator")[0]) + inst.set_nodeattr("preferred_impl_style", impl_style) + model = model.transform(SpecializeLayers()) + # set simd + inst = getCustomOp(model.graph.node[0]) + inst.set_nodeattr("SIMD", simd) + if model.graph.node[0].op_type == "ConvolutionInputGenerator_rtl": + inst.set_nodeattr("parallel_window", parallel_window) + inst.set_nodeattr("M", m) + + if exec_mode == "cppsim": + if model.graph.node[0].op_type == "ConvolutionInputGenerator_rtl": + pytest.skip("cppsim not supported for RTL DWC") + else: + model = model.transform(SetExecMode("cppsim")) + model = model.transform(PrepareCppSim()) + model = model.transform(CompileCppSim()) + elif exec_mode == "rtlsim": + model = model.transform(SetExecMode("rtlsim")) + model = model.transform(GiveUniqueNodeNames()) + model = model.transform(PrepareIP("xc7z020clg400-1", 5)) + model = model.transform(HLSSynthIP()) + model = model.transform(PrepareRTLSim()) + else: + raise Exception("Unknown exec_mode in test_fpgadataflow_slidingwindow") + + # execute model + y_produced = oxe.execute_onnx(model, input_dict)["outp"] + + if dw == 0: + assert (y_produced == y_expected).all() + else: + y_expected = y_expected.reshape(1, ofm_dim_h, ofm_dim_w, k_h * k_w, ifm_ch // simd, simd) + y_expected = y_expected.transpose(0, 1, 2, 4, 3, 5) + y_expected = y_expected.reshape(1, ofm_dim_h, ofm_dim_w, ifm_ch * k_h * k_w) + assert (y_produced == y_expected).all() + + if exec_mode == "rtlsim" and impl_style == "hls": + nodes = model.get_nodes_by_op_type("ConvolutionInputGenerator_hls") + if nodes: + node = nodes[0] + inst = getCustomOp(node) + cycles_rtlsim = inst.get_nodeattr("cycles_rtlsim") + exp_cycles_dict = model.analysis(exp_cycles_per_layer) + exp_cycles = exp_cycles_dict[node.name] + assert np.isclose(exp_cycles, cycles_rtlsim, atol=10) + assert exp_cycles != 0 + else: + assert model.graph.node[0].op_type == "ConvolutionInputGenerator_rtl" # input datatype -@pytest.mark.parametrize("idt", [DataType["BIPOLAR"], DataType["INT2"]]) +@pytest.mark.parametrize("idt", [DataType["INT8"]]) # kernel size -@pytest.mark.parametrize("k", [2, 3]) +@pytest.mark.parametrize("k", [[4, 1]]) # input dimension -@pytest.mark.parametrize("ifm_dim", [6, 8]) +@pytest.mark.parametrize("ifm_dim", [[10, 1]]) # input channels -@pytest.mark.parametrize("ifm_ch", [2, 4]) +@pytest.mark.parametrize("ifm_ch", [1, 4]) # Stride -@pytest.mark.parametrize("stride", [1, 2]) +@pytest.mark.parametrize("stride", [[1, 1], [2, 1]]) # Dilation -# Currently only dilation value of 1 is supported -@pytest.mark.parametrize("dilation", [1]) +@pytest.mark.parametrize("dilation", [[1, 1], [2, 1]]) # execution mode @pytest.mark.parametrize("exec_mode", ["cppsim", "rtlsim"]) # input channel parallelism ("SIMD") -@pytest.mark.parametrize("simd", [1, 2]) +@pytest.mark.parametrize("simd", [1, 4]) # depthwise @pytest.mark.parametrize("dw", [0, 1]) +# TODO add parallel_window and M option +# implementation style +@pytest.mark.parametrize("impl_style", ["rtl", "hls"]) @pytest.mark.fpgadataflow @pytest.mark.slow @pytest.mark.vivado -def test_fpgadataflow_slidingwindow(idt, k, ifm_dim, ifm_ch, stride, dilation, exec_mode, simd, dw): +def test_fpgadataflow_slidingwindow1d( + idt, k, ifm_dim, ifm_ch, stride, dilation, exec_mode, simd, dw, impl_style +): ofm_dim = int(((ifm_dim - k) / stride) + 1) x = gen_finn_dt_tensor(idt, (1, ifm_dim, ifm_dim, ifm_ch)) - model = make_single_slidingwindow_modelwrapper( + input_dict = prepare_inputs(x) + model = make_single_im2col_modelwrapper( k, ifm_ch, ifm_dim, ofm_dim, simd, stride, dilation, idt, dw ) + y_expected = oxe.execute_onnx(model, input_dict)["outp"] + + model = model.transform(to_hw.InferConvInpGen()) + model.save("model_before.onnx") + # set impl_style + inst = getCustomOp(model.get_nodes_by_op_type("ConvolutionInputGenerator")[0]) + inst.set_nodeattr("preferred_impl_style", impl_style) + model = model.transform(SpecializeLayers()) + # set simd + inst = getCustomOp(model.graph.node[0]) + inst.set_nodeattr("SIMD", simd) + model.save("model_after.onnx") if exec_mode == "cppsim": - model = model.transform(SetExecMode("cppsim")) - model = model.transform(PrepareCppSim()) - model = model.transform(CompileCppSim()) + if impl_style == "rtl": + pytest.skip("cppsim not supported for RTL DWC") + else: + model = model.transform(SetExecMode("cppsim")) + model = model.transform(PrepareCppSim()) + model = model.transform(CompileCppSim()) elif exec_mode == "rtlsim": model = model.transform(SetExecMode("rtlsim")) model = model.transform(GiveUniqueNodeNames()) @@ -167,14 +301,8 @@ def test_fpgadataflow_slidingwindow(idt, k, ifm_dim, ifm_ch, stride, dilation, e else: raise Exception("Unknown exec_mode in test_fpgadataflow_slidingwindow") - # prepare input data - input_dict = prepare_inputs(x) # execute model y_produced = oxe.execute_onnx(model, input_dict)["outp"] - golden = make_single_im2col_modelwrapper( - k, ifm_ch, ifm_dim, ofm_dim, simd, stride, dilation, idt - ) - y_expected = oxe.execute_onnx(golden, input_dict)["outp"] if dw == 0: assert (y_produced == y_expected).all() @@ -184,8 +312,8 @@ def test_fpgadataflow_slidingwindow(idt, k, ifm_dim, ifm_ch, stride, dilation, e y_expected = y_expected.reshape(1, ofm_dim, ofm_dim, ifm_ch * k * k) assert (y_produced == y_expected).all() - if exec_mode == "rtlsim": - node = model.get_nodes_by_op_type("ConvolutionInputGenerator")[0] + if exec_mode == "rtlsim" and impl_style == "hls": + node = model.get_nodes_by_op_type("ConvolutionInputGenerator_hls")[0] inst = getCustomOp(node) cycles_rtlsim = inst.get_nodeattr("cycles_rtlsim") exp_cycles_dict = model.analysis(exp_cycles_per_layer) diff --git a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator1d.py b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator1d.py deleted file mode 100644 index aa89dde5e7..0000000000 --- a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator1d.py +++ /dev/null @@ -1,268 +0,0 @@ -# Copyright (c) 2020, Xilinx -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# * Redistributions of source code must retain the above copyright notice, this -# list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# * Neither the name of FINN nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -import pytest - -import numpy as np -from onnx import TensorProto, helper -from qonnx.core.datatype import DataType -from qonnx.core.modelwrapper import ModelWrapper -from qonnx.custom_op.general.im2col import compute_conv_output_dim -from qonnx.custom_op.registry import getCustomOp -from qonnx.transformation.general import GiveUniqueNodeNames -from qonnx.util.basic import gen_finn_dt_tensor, qonnx_make_model - -import finn.core.onnx_exec as oxe -from finn.analysis.fpgadataflow.exp_cycles_per_layer import exp_cycles_per_layer -from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim -from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP -from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim -from finn.transformation.fpgadataflow.prepare_ip import PrepareIP -from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim -from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode - -fpga_part = "xczu3eg-sbva484-1-e" - - -def make_single_im2col_modelwrapper(k, ifm_ch, ifm_dim, ofm_dim, simd, stride, dilation, idt): - k_h, k_w = k - ifm_dim_h, ifm_dim_w = ifm_dim - stride_h, stride_w = stride - dilation_h, dilation_w = dilation - ofm_dim_h, ofm_dim_w = ofm_dim - - odt = idt - inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, [1, ifm_dim_h, ifm_dim_w, ifm_ch]) - outp = helper.make_tensor_value_info( - "outp", TensorProto.FLOAT, [1, ofm_dim_h, ofm_dim_w, k_h * k_w * ifm_ch] - ) - - im2col_node = helper.make_node( - "Im2Col", - ["inp"], - ["outp"], - domain="qonnx.custom_op.general", - stride=[stride_h, stride_w], - kernel_size=[k_h, k_w], - input_shape=str((1, ifm_dim_h, ifm_dim_w, ifm_ch)), - dilations=[dilation_h, dilation_w], - pad_amount=[0, 0, 0, 0], - pad_value=0, - ) - graph = helper.make_graph( - nodes=[im2col_node], name="im2col_graph", inputs=[inp], outputs=[outp] - ) - - model = qonnx_make_model(graph, producer_name="im2col-model") - model = ModelWrapper(model) - - model.set_tensor_datatype("inp", idt) - model.set_tensor_datatype("outp", odt) - - return model - - -def make_single_slidingwindow_modelwrapper( - k, ifm_ch, ifm_dim, ofm_dim, simd, stride, dilation, idt, parallel_window, dw=0 -): - k_h, k_w = k - ifm_dim_h, ifm_dim_w = ifm_dim - stride_h, stride_w = stride - dilation_h, dilation_w = dilation - ofm_dim_h, ofm_dim_w = ofm_dim - - odt = idt - inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, [1, ifm_dim_h, ifm_dim_w, ifm_ch]) - outp = helper.make_tensor_value_info( - "outp", TensorProto.FLOAT, [1, ofm_dim_h, ofm_dim_w, k_h * k_w * ifm_ch] - ) - - SlidingWindow_node = helper.make_node( - "ConvolutionInputGenerator1D", - ["inp"], - ["outp"], - domain="finn.custom_op.fpgadataflow", - backend="fpgadataflow", - ConvKernelDim=[k_h, k_w], - IFMChannels=ifm_ch, - IFMDim=[ifm_dim_h, ifm_dim_w], - OFMDim=[ofm_dim_h, ofm_dim_w], - SIMD=simd, - Stride=[stride_h, stride_w], - Dilation=[dilation_h, dilation_w], - inputDataType=idt.name, - outputDataType=odt.name, - depthwise=dw, - parallel_window=parallel_window, - ) - graph = helper.make_graph( - nodes=[SlidingWindow_node], - name="slidingwindow_graph", - inputs=[inp], - outputs=[outp], - ) - - model = qonnx_make_model(graph, producer_name="slidingwindow-model") - model = ModelWrapper(model) - - model.set_tensor_datatype("inp", idt) - model.set_tensor_datatype("outp", odt) - - return model - - -def prepare_inputs(input_tensor): - return {"inp": input_tensor} - - -# input datatype -# @pytest.mark.parametrize("idt", [DataType["BIPOLAR"], DataType["INT8"]]) -@pytest.mark.parametrize("idt", [DataType["INT8"]]) -# kernel size -@pytest.mark.parametrize("k", [[4, 1]]) -# input dimension -@pytest.mark.parametrize("ifm_dim", [[10, 1]]) -# input channels -@pytest.mark.parametrize("ifm_ch", [1, 4]) -# Stride -@pytest.mark.parametrize("stride", [[1, 1], [2, 1]]) -# Dilation -@pytest.mark.parametrize("dilation", [[1, 1], [2, 1]]) -# execution mode -@pytest.mark.parametrize("exec_mode", ["cppsim", "rtlsim"]) -# input channel parallelism ("SIMD") -@pytest.mark.parametrize("simd", [1, 4]) -# depthwise -@pytest.mark.parametrize("dw", [0, 1]) -# Flip dimensions -@pytest.mark.parametrize("flip", [False, True]) -# Use parallel window output variant -@pytest.mark.parametrize("parallel_window", [False, True]) -@pytest.mark.fpgadataflow -@pytest.mark.slow -@pytest.mark.vivado -def test_fpgadataflow_slidingwindow_1d( - idt, - k, - ifm_dim, - ifm_ch, - stride, - dilation, - exec_mode, - simd, - dw, - flip, - parallel_window, -): - if flip: - k = k[::-1] - ifm_dim = ifm_dim[::-1] - stride = stride[::-1] - dilation = dilation[::-1] - - k_h, k_w = k - ifm_dim_h, ifm_dim_w = ifm_dim - stride_h, stride_w = stride - dilation_h, dilation_w = dilation - - if (dilation_h > 1 or dilation_w > 1) and (stride_h > 1 or stride_w > 1): - pytest.skip( - """Dilation value greater than 1 and stride greater than 1 - currently not supported for 1D convolutions""" - ) - if (dilation_h > 1 or dilation_w > 1) and dw == 0: - pytest.skip( - """Dilation value greater than 1 currently not supported - for non-dws 1D convolutions""" - ) - if simd > ifm_ch: - pytest.skip("SIMD cannot be larger than number of input channels") - - ofm_dim_h = compute_conv_output_dim(ifm_dim_h, k_h, stride_h, 0, dilation_h) - ofm_dim_w = compute_conv_output_dim(ifm_dim_w, k_w, stride_w, 0, dilation_w) - ofm_dim = [ofm_dim_h, ofm_dim_w] - - x = gen_finn_dt_tensor(idt, (1, ifm_dim_h, ifm_dim_w, ifm_ch)) - model = make_single_slidingwindow_modelwrapper( - k=k, - ifm_ch=ifm_ch, - ifm_dim=ifm_dim, - ofm_dim=ofm_dim, - simd=simd, - stride=stride, - dilation=dilation, - idt=idt, - parallel_window=parallel_window, - dw=dw, - ) - - if exec_mode == "cppsim": - model = model.transform(SetExecMode("cppsim")) - model = model.transform(PrepareCppSim()) - model = model.transform(CompileCppSim()) - elif exec_mode == "rtlsim": - model = model.transform(SetExecMode("rtlsim")) - model = model.transform(GiveUniqueNodeNames()) - model = model.transform(PrepareIP(fpga_part, 5)) - model = model.transform(HLSSynthIP()) - model = model.transform(PrepareRTLSim()) - else: - raise Exception("Unknown exec_mode in test_fpgadataflow_slidingwindow") - - # prepare input data - input_dict = prepare_inputs(x) - # execute model - y_produced = oxe.execute_onnx(model, input_dict)["outp"] - golden = make_single_im2col_modelwrapper( - k=k, - ifm_ch=ifm_ch, - ifm_dim=ifm_dim, - ofm_dim=ofm_dim, - simd=simd, - stride=stride, - dilation=dilation, - idt=idt, - ) - y_expected = oxe.execute_onnx(golden, input_dict)["outp"] - - if dw == 0: - assert (y_produced == y_expected).all() - else: - y_expected = y_expected.reshape(1, ofm_dim_h, ofm_dim_w, k_h * k_w, ifm_ch // simd, simd) - y_expected = y_expected.transpose(0, 1, 2, 4, 3, 5) - y_expected = y_expected.reshape(1, ofm_dim_h, ofm_dim_w, ifm_ch * k_h * k_w) - assert (y_produced == y_expected).all() - - if exec_mode == "rtlsim": - node = model.get_nodes_by_op_type("ConvolutionInputGenerator1D")[0] - inst = getCustomOp(node) - cycles_rtlsim = inst.get_nodeattr("cycles_rtlsim") - exp_cycles_dict = model.analysis(exp_cycles_per_layer) - exp_cycles = exp_cycles_dict[node.name] - assert np.isclose(exp_cycles, cycles_rtlsim, atol=10) - assert exp_cycles != 0 diff --git a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py deleted file mode 100755 index 62b7abe536..0000000000 --- a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py +++ /dev/null @@ -1,245 +0,0 @@ -# Copyright (C) 2022, Advanced Micro Devices, Inc. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# * Redistributions of source code must retain the above copyright notice, this -# list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# * Neither the name of FINN nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -import pytest - -from onnx import TensorProto, helper -from qonnx.core.datatype import DataType -from qonnx.core.modelwrapper import ModelWrapper -from qonnx.custom_op.general.im2col import compute_conv_output_dim -from qonnx.transformation.general import GiveUniqueNodeNames -from qonnx.util.basic import gen_finn_dt_tensor, qonnx_make_model - -import finn.core.onnx_exec as oxe -from finn.transformation.fpgadataflow.prepare_ip import PrepareIP -from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim -from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode - - -def make_single_im2col_modelwrapper(k, ifm_ch, ifm_dim, ofm_dim, stride, dilation, idt): - k_h, k_w = k - ifm_dim_h, ifm_dim_w = ifm_dim - stride_h, stride_w = stride - dilation_h, dilation_w = dilation - ofm_dim_h, ofm_dim_w = ofm_dim - - odt = idt - inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, [1, ifm_dim_h, ifm_dim_w, ifm_ch]) - outp = helper.make_tensor_value_info( - "outp", TensorProto.FLOAT, [1, ofm_dim_h, ofm_dim_w, k_h * k_w * ifm_ch] - ) - - im2col_node = helper.make_node( - "Im2Col", - ["inp"], - ["outp"], - domain="finn.custom_op.general", - stride=[stride_h, stride_w], - kernel_size=[k_h, k_w], - input_shape=str((1, ifm_dim_h, ifm_dim_w, ifm_ch)), - dilations=[dilation_h, dilation_w], - pad_amount=[0, 0, 0, 0], - pad_value=0, - ) - graph = helper.make_graph( - nodes=[im2col_node], name="im2col_graph", inputs=[inp], outputs=[outp] - ) - - model = qonnx_make_model(graph, producer_name="im2col-model") - model = ModelWrapper(model) - - model.set_tensor_datatype("inp", idt) - model.set_tensor_datatype("outp", odt) - - return model - - -def make_single_slidingwindow_modelwrapper( - k, ifm_ch, ifm_dim, ofm_dim, simd, m, parallel_window, stride, dilation, idt, dw=0 -): - k_h, k_w = k - ifm_dim_h, ifm_dim_w = ifm_dim - stride_h, stride_w = stride - dilation_h, dilation_w = dilation - ofm_dim_h, ofm_dim_w = ofm_dim - - odt = idt - inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, [1, ifm_dim_h, ifm_dim_w, ifm_ch]) - outp = helper.make_tensor_value_info( - "outp", TensorProto.FLOAT, [1, ofm_dim_h, ofm_dim_w, k_h * k_w * ifm_ch] - ) - - SlidingWindow_node = helper.make_node( - "ConvolutionInputGenerator_rtl", - ["inp"], - ["outp"], - domain="finn.custom_op.fpgadataflow", - backend="fpgadataflow", - ConvKernelDim=[k_h, k_w], - IFMChannels=ifm_ch, - IFMDim=[ifm_dim_h, ifm_dim_w], - OFMDim=[ofm_dim_h, ofm_dim_w], - SIMD=simd, - M=m, - parallel_window=parallel_window, - Stride=[stride_h, stride_w], - Dilation=[dilation_h, dilation_w], - inputDataType=idt.name, - outputDataType=odt.name, - depthwise=dw, - ) - graph = helper.make_graph( - nodes=[SlidingWindow_node], - name="slidingwindow_graph", - inputs=[inp], - outputs=[outp], - ) - - model = qonnx_make_model(graph, producer_name="slidingwindow-model") - model = ModelWrapper(model) - - model.set_tensor_datatype("inp", idt) - model.set_tensor_datatype("outp", odt) - - return model - - -def prepare_inputs(input_tensor): - return {"inp": input_tensor} - - -# input datatype -@pytest.mark.parametrize("idt", [DataType["UINT4"]]) -# kernel size -@pytest.mark.parametrize("k", [[3, 3], [1, 5]]) -# input dimension -@pytest.mark.parametrize("ifm_dim", [[13, 13], [1, 21]]) -# input channels -@pytest.mark.parametrize("ifm_ch", [6]) -# Stride -@pytest.mark.parametrize("stride", [[1, 1], [2, 2]]) -# Dilation -@pytest.mark.parametrize("dilation", [[1, 1], [2, 2]]) -# depthwise -@pytest.mark.parametrize("dw", [0, 1]) -# input channel parallelism ("SIMD") -@pytest.mark.parametrize("simd", [1, 3, 6]) -# parallel_window enable (MMV_out = M*K) -@pytest.mark.parametrize("parallel_window", [0, 1]) -# in/out MMV ("M") -@pytest.mark.parametrize("m", [1]) -# Flip dimensions -@pytest.mark.parametrize("flip", [False]) -@pytest.mark.slow -@pytest.mark.vivado -@pytest.mark.fpgadataflow -def test_fpgadataflow_slidingwindow_rtl( - idt, k, ifm_dim, ifm_ch, stride, dilation, dw, simd, m, parallel_window, flip -): - if flip: - if ( - ifm_dim[0] == ifm_dim[1] - and k[0] == k[1] - and stride[0] == stride[1] - and dilation[0] == dilation[1] - ): - pytest.skip("Dimension flip would have no effect") - k = k[::-1] - ifm_dim = ifm_dim[::-1] - stride = stride[::-1] - dilation = dilation[::-1] - - k_h, k_w = k - ifm_dim_h, ifm_dim_w = ifm_dim - stride_h, stride_w = stride - dilation_h, dilation_w = dilation - - kernel_width = (k_w - 1) * dilation_w + 1 # incl. dilation - kernel_height = (k_h - 1) * dilation_h + 1 # incl. dilation - - if simd > ifm_ch: - pytest.skip("SIMD cannot be larger than number of input channels") - if ifm_ch % simd != 0: - pytest.skip("SIMD must divide number of input channels") - if kernel_height > ifm_dim_h or stride_h > ifm_dim_h: - pytest.skip("Illegal convolution configuration: kernel or stride > FM dimension") - if kernel_width > ifm_dim_w or stride_w > ifm_dim_w: - pytest.skip("Illegal convolution configuration: kernel or stride > FM dimension") - if (k_h == 1 and dilation_h != 1) or (k_w == 1 and dilation_w != 1): - pytest.skip("Illegal convolution configuration: dilation for unitary kernel dim") - if ((stride_h > k_h) or (stride_w > k_w)) and not (parallel_window or (k_h == 1 and k_w == 1)): - pytest.skip("Not all combinations for stride > k edge case supported in default mode") - if parallel_window and simd != ifm_ch and not (dw or (k_h == 1 and k_w == 1)): - pytest.skip("Parallel window requires SIMD=C for non-depthwise case") - - ofm_dim_h = compute_conv_output_dim(ifm_dim_h, k_h, stride_h, 0, dilation_h) - ofm_dim_w = compute_conv_output_dim(ifm_dim_w, k_w, stride_w, 0, dilation_w) - ofm_dim = [ofm_dim_h, ofm_dim_w] - - x = gen_finn_dt_tensor(idt, (1, ifm_dim_h, ifm_dim_w, ifm_ch)) - model = make_single_slidingwindow_modelwrapper( - k=k, - ifm_ch=ifm_ch, - ifm_dim=ifm_dim, - ofm_dim=ofm_dim, - simd=simd, - m=m, - parallel_window=parallel_window, - stride=stride, - dilation=dilation, - idt=idt, - dw=dw, - ) - - model = model.transform(SetExecMode("rtlsim")) - model = model.transform(GiveUniqueNodeNames()) - model = model.transform(PrepareIP("xc7z020clg400-1", 5)) - model = model.transform(PrepareRTLSim()) - - # prepare input data - input_dict = prepare_inputs(x) - # execute model - y_produced = oxe.execute_onnx(model, input_dict)["outp"] - golden = make_single_im2col_modelwrapper( - k=k, - ifm_ch=ifm_ch, - ifm_dim=ifm_dim, - ofm_dim=ofm_dim, - stride=stride, - dilation=dilation, - idt=idt, - ) - y_expected = oxe.execute_onnx(golden, input_dict)["outp"] - - if dw == 0: - assert (y_produced == y_expected).all() - else: - y_expected = y_expected.reshape(1, ofm_dim_h, ofm_dim_w, k_h * k_w, ifm_ch // simd, simd) - y_expected = y_expected.transpose(0, 1, 2, 4, 3, 5) - y_expected = y_expected.reshape(1, ofm_dim_h, ofm_dim_w, ifm_ch * k_h * k_w) - assert (y_produced == y_expected).all() From f2f56d6466fab50f0bc3e92d9c0dae4faae8cda4 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Thu, 18 Jan 2024 09:42:29 +0000 Subject: [PATCH 390/665] [BTS] WIP: custom changes --- .../thresholding_binary_search.py | 232 ++++++++++++++---- 1 file changed, 184 insertions(+), 48 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/thresholding_binary_search.py b/src/finn/custom_op/fpgadataflow/thresholding_binary_search.py index 7d53d81de8..cde0d8dc79 100755 --- a/src/finn/custom_op/fpgadataflow/thresholding_binary_search.py +++ b/src/finn/custom_op/fpgadataflow/thresholding_binary_search.py @@ -26,14 +26,27 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +import math import numpy as np import os +import shutil import warnings +from pyverilator.util.axi_utils import rtlsim_multi_io from qonnx.core.datatype import DataType -from qonnx.util.basic import interleave_matrix_outer_dim_from_partitions +from qonnx.util.basic import ( + interleave_matrix_outer_dim_from_partitions, + roundup_to_integer_multiple, +) from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp -from finn.util.basic import find_next_power_of_2, get_rtlsim_trace_depth, make_build_dir +from finn.util.basic import ( + find_next_power_of_2, + get_memutil_alternatives, + get_rtlsim_trace_depth, + make_build_dir, + mem_primitives_versal, + pyverilate_get_liveness_threshold_cycles, +) from finn.util.data_packing import ( npy_to_rtlsim_input, pack_innermost_dim_as_hex_string, @@ -255,7 +268,7 @@ def get_normal_output_shape(self, ind=0): return self.get_normal_input_shape() def get_number_output_values(self): - return 0 + return np.prod(self.get_folded_output_shape()[:-1]) def get_exp_cycles(self): # Channels/PE * batch size * fmdim * fmdim @@ -305,11 +318,70 @@ def get_hls_compatible_threshold_tensor(self, orig_thres_matrix): rows between PEs is not as expected (n_thres_steps)""" return ret.reshape(1, pe, tmem, n_thres_steps) - def prepare_codegen_rtl_values(self): + def get_all_meminit_filenames(self, abspath=False): + "Return a list of all .dat memory initializer files used for this node" + dat_files = [] + t_path = self.get_nodeattr("code_gen_dir_ipgen") if abspath else "." + pe = self.get_nodeattr("PE") + output_data_type = self.get_nodeattr("outputDataType") # output precision + o_bitwidth = DataType[output_data_type].bitwidth() + for stage in range(o_bitwidth): + for pe_value in range(pe): + thresh_file = t_path + "/%s_threshs_%s_%s.dat" % ( + self.onnx_node.name, + pe_value, + stage, + ) + dat_files.append(thresh_file) + return dat_files + + def prepare_codegen_rtl_values(self, model): """All dictionary values produced in this function are to replace their key value(s) in the RTL template files""" code_gen_dict = {} + # TODO check for sortedness and size here? + # RTL component currently always expects 2^N-1 thresholds, but + # sometimes we have fewer due to e.g. narrow range quantization + thresholds = model.get_initializer(self.onnx_node.input[1]) + # add dummy dimension as final dimension (that's what gets packed with next call) + thresholds = np.expand_dims(thresholds, axis=-1) + wdt = self.get_weight_datatype() + bw_hexdigit = roundup_to_integer_multiple(wdt.bitwidth(), 4) + t_packed = pack_innermost_dim_as_hex_string( + thresholds, + wdt, + bw_hexdigit, + prefix="", + ) + + t_path = self.get_nodeattr("code_gen_dir_ipgen") + pe = self.get_nodeattr("PE") + output_data_type = self.get_nodeattr("outputDataType") # output precision + o_bitwidth = DataType[output_data_type].bitwidth() + num_channels = self.get_nodeattr("NumChannels") # number of channels + + channel_fold = int(num_channels / pe) + + for stage in range(o_bitwidth): + sn = o_bitwidth - stage - 1 + for pe_value in range(pe): + thresh_file = t_path + "/%s_threshs_%s_%s.dat" % ( + self.onnx_node.name, + pe_value, + stage, + ) + threshs = np.zeros([channel_fold * (2**stage)], dtype="object") + for ch in range(channel_fold): + for i in range(2**stage): + threshs[(ch << stage) + i] = t_packed[ch * pe + pe_value][ + (i << (o_bitwidth - stage)) + 2**sn - 1 + ] + with open(thresh_file, "w") as f: + for val in threshs: + f.write(val + "\n") + code_gen_dict["$THRESHOLDS_PATH$"] = ['"./%s_"' % self.onnx_node.name] + # Identify the module name code_gen_dict["$MODULE_NAME_AXI_WRAPPER$"] = [ self.get_verilog_top_module_name() + "_axi_wrapper" @@ -318,19 +390,13 @@ def prepare_codegen_rtl_values(self): code_gen_dict["$TOP_MODULE$"] = code_gen_dict["$MODULE_NAME_AXI_WRAPPER$"] # Identify the module variables - output_data_type = self.get_nodeattr("outputDataType") # output precision - input_data_type = self.get_nodeattr( - "inputDataType" - ) # input/threshold precision - num_channels = self.get_nodeattr("NumChannels") # number of channels + input_data_type = self.get_nodeattr("inputDataType") # input/threshold precision bias = self.get_nodeattr("activation_bias") # activation bias value - pe = self.get_nodeattr("PE") + i_bitwidth = DataType[input_data_type].bitwidth() - code_gen_dict["$N$"] = [ - str(DataType[output_data_type].bitwidth()) - ] # output precision - convert bitwidth to string + code_gen_dict["$N$"] = [str(o_bitwidth)] # output precision - convert bitwidth to string code_gen_dict["$M$"] = [ - str(DataType[input_data_type].bitwidth()) + str(i_bitwidth) ] # input/threshold precision - convert bitwidth to string code_gen_dict["$C$"] = [str(num_channels)] # number of channels code_gen_dict["$BIAS$"] = [str(bias)] # activation bias value @@ -343,11 +409,34 @@ def prepare_codegen_rtl_values(self): else: code_gen_dict["$SIGNED$"] = [str(0)] + if bias >= 0: + o_bits = math.ceil(math.log2(2**o_bitwidth + bias)) + else: + o_bits = 1 + math.ceil( + math.log2(-bias if -bias >= 2 ** (o_bitwidth - 1) else 2**o_bitwidth + bias) + ) + + code_gen_dict["$O_BITS$"] = [str(int(o_bits))] + + rt_weights = self.get_nodeattr("runtime_writeable_weights") + code_gen_dict["$USE_AXILITE$"] = [str(rt_weights)] + + depth_trigger_uram = self.get_nodeattr("depth_trigger_uram") + depth_trigger_bram = self.get_nodeattr("depth_trigger_bram") + deep_pipeline = self.get_nodeattr("deep_pipeline") + code_gen_dict["$DEPTH_TRIGGER_URAM$"] = [str(depth_trigger_uram)] + code_gen_dict["$DEPTH_TRIGGER_BRAM$"] = [str(depth_trigger_bram)] + code_gen_dict["$DEEP_PIPELINE$"] = [str(deep_pipeline)] return code_gen_dict def get_rtl_file_list(self): """Thresholding binary search RTL file list""" - return ["thresholding.sv", "thresholding_axi.sv", "thresholding_axi_wrapper.v"] + return [ + "axilite_if.v", + "thresholding.sv", + "thresholding_axi.sv", + "thresholding_template_wrapper.v", + ] def get_rtl_file_paths(self): """Get full path of all RTL files""" @@ -372,14 +461,18 @@ def fill_in_rtl_template_data(self, replace_dict, template_data): def dump_rtl_data(self, dest_dir, filename, data): """Dump filled-in-template RTL files for future synthesis step""" + # when generating template files, handle a special case: + # if the filename contains the word "template", replace that + # with the node name to distinguish between instances + filename = filename.replace("template", self.onnx_node.name) with open(os.path.join(dest_dir, filename), "w") as f: f.write(data) return - def generate_hdl(self): + def generate_hdl(self, model): """Prepare HDL files from templates for synthesis""" # Generate a dictionary of values to put in RTL template - code_gen_dict = self.prepare_codegen_rtl_values() + code_gen_dict = self.prepare_codegen_rtl_values(model) # Retrieve the destination directory for the final RTL files code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") @@ -399,7 +492,7 @@ def generate_hdl(self): return def code_generation_ipgen(self, model, fpgapart, clk): - self.generate_hdl() + self.generate_hdl(model) # set ipgen_path and ip_path so that HLS-Synth transformation # and stich_ip transformation do not complain @@ -419,15 +512,20 @@ def prepare_rtlsim(self): code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") verilog_paths = [code_gen_dir] - verilog_files = self.get_rtl_file_list() + verilog_files = [x.replace("template", self.onnx_node.name) for x in self.get_rtl_file_list()] + dat_files = self.get_all_meminit_filenames(abspath=True) + single_src_dir = make_build_dir("pyverilator_" + self.onnx_node.name + "_") + for dat_file in dat_files: + shutil.copy(dat_file, single_src_dir) # build the Verilator emulation library sim = PyVerilator.build( verilog_files, - build_dir=make_build_dir("pyverilator_" + self.onnx_node.name + "_"), + build_dir=single_src_dir, verilog_path=verilog_paths, trace_depth=get_rtlsim_trace_depth(), top_module_name=self.get_nodeattr("gen_top_module"), + auto_eval=False, ) # save generated lib filename in attribute @@ -450,8 +548,7 @@ def execute_node(self, context, graph): in_ind = 0 for inputs in node.input: # it is assumed that the first input of the node is the data input - # the second input are the weights - # the third input are the thresholds + # the second input are the thresholds if in_ind == 0: assert ( str(context[inputs].dtype) == "float32" @@ -480,25 +577,16 @@ def execute_node(self, context, graph): # Create a PyVerilator wrapper of the RTLSim .so sim = self.get_rtlsim() nbits = self.get_instream_width() - inp = npy_to_rtlsim_input( - "{}/input_0.npy".format(code_gen_dir), export_idt, nbits - ) - - super().reset_rtlsim(sim) - super().toggle_clk(sim) - - wnbits = self.get_weightstream_width() - export_wdt = self.get_weight_datatype() - wei = npy_to_rtlsim_input( - "{}/thresholds.npy".format(code_gen_dir), export_wdt, wnbits - ) - num_w_reps = np.prod(self.get_nodeattr("numInputVectors")) + inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) + io_names = self.get_verilog_top_module_intf_names() + istream_name = io_names["s_axis"][0][0] + ostream_name = io_names["m_axis"][0][0] io_dict = { - "inputs": {"in0": inp, "weights": wei * num_w_reps}, - "outputs": {"s_axis": []}, + "inputs": {istream_name: inp}, + "outputs": {ostream_name: []}, } self.rtlsim_multi_io(sim, io_dict) - output = io_dict["outputs"]["out"] + output = io_dict["outputs"][ostream_name] # Manage output data odt = self.get_output_datatype() @@ -507,9 +595,7 @@ def execute_node(self, context, graph): out_npy_path = "{}/output.npy".format(code_gen_dir) out_shape = self.get_folded_output_shape() - rtlsim_output_to_npy( - output, out_npy_path, odt, out_shape, packed_bits, target_bits - ) + rtlsim_output_to_npy(output, out_npy_path, odt, out_shape, packed_bits, target_bits) # load and reshape output output = np.load(out_npy_path) @@ -518,16 +604,55 @@ def execute_node(self, context, graph): context[node.output[0]] = output return + def hls_sname(self): + """Get the naming convention used by Vitis HLS for stream signals + Example: the TDATA for a stream called "out" would be out_V_TDATA. + """ + # no additional prefix/suffix in interface names since this is an RTL component + return "" + + def rtlsim_multi_io(self, sim, io_dict): + "Run rtlsim for this node, supports multiple i/o streams." + + rtlsim_so = self.get_nodeattr("rtlsim_so") + so_dir = os.path.dirname(os.path.realpath(rtlsim_so)) + olcwd = os.getcwd() + os.chdir(so_dir) + + # signal name prefix + # TODO if the interface names on this component get standardized, + # it won't need its own rtlsim_multi_io variant anymore and can just + # use the base class one + sname = "_" + + trace_file = self.get_nodeattr("rtlsim_trace") + if trace_file == "default": + trace_file = self.onnx_node.name + ".vcd" + num_out_values = self.get_number_output_values() + total_cycle_count = rtlsim_multi_io( + sim, + io_dict, + num_out_values, + trace_file=trace_file, + sname=sname, + do_reset=True, + liveness_threshold=pyverilate_get_liveness_threshold_cycles(), + ) + self.set_nodeattr("cycles_rtlsim", total_cycle_count) + os.chdir(olcwd) + def code_generation_ipi(self): """Constructs and returns the TCL commands for node instantiation as an RTL block.""" - cmd = [] - rtl_file_list = self.get_rtl_file_list() + rtl_file_list = [x.replace("template", self.onnx_node.name) for x in self.get_rtl_file_list()] code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + source_target = "./ip/verilog/rtl_ops/%s" % self.onnx_node.name + cmd = ["file mkdir %s" % source_target] for rtl_file in rtl_file_list: cmd.append( - "add_files -norecurse %s" % (os.path.join(code_gen_dir, rtl_file)) + "add_files -copy_to %s -norecurse %s" + % (source_target, os.path.join(code_gen_dir, rtl_file)) ) # Create an RTL block, not an IP core (-type ip) @@ -548,8 +673,17 @@ def get_verilog_top_module_intf_names(self): axilite always assumed to be 32 bits and is not tuple (name only). Each block must have at most one aximm and one axilite.""" - intf_names = super().get_verilog_top_module_intf_names() - intf_names["axilite"] = ["s_axilite"] + intf_names = {} + intf_names["clk"] = ["ap_clk"] + intf_names["rst"] = ["ap_rst_n"] + intf_names["s_axis"] = [("in0_V", self.get_instream_width_padded())] + intf_names["m_axis"] = [("out_V", self.get_outstream_width_padded())] + intf_names["aximm"] = [] + intf_names["axilite"] = [] + intf_names["ap_none"] = [] + if self.get_nodeattr("runtime_writeable_weights") == 1: + intf_names["axilite"] = ["s_axilite"] + return intf_names def get_dynamic_config(self, model, address_stride=1): @@ -566,6 +700,8 @@ def get_dynamic_config(self, model, address_stride=1): config = {} channel_cntr = 0 + wdt = self.get_weight_datatype() + bw_hexdigit = roundup_to_integer_multiple(wdt.bitwidth(), 4) for channel in thresholds: channel_start_addr = channel_cntr * weight_addr_boundary * address_stride weight_cntr = 0 @@ -580,8 +716,8 @@ def get_dynamic_config(self, model, address_stride=1): str( pack_innermost_dim_as_hex_string( [weight], - self.get_weight_datatype(), - self.get_weight_datatype().bitwidth(), + wdt, + bw_hexdigit, ) ), 0, From 72ac0e5493aa499a094573dc9a8e5518cbfb9f4d Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Thu, 18 Jan 2024 09:45:43 +0000 Subject: [PATCH 391/665] [BTS] threshold supports other memory modes --- .../transformation/fpgadataflow/convert_to_hls_layers.py | 7 ------- 1 file changed, 7 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py b/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py index a50cbbaed1..c43f058fac 100644 --- a/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py +++ b/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py @@ -1081,13 +1081,6 @@ def apply(self, model): is_rtl_variant_compatible = True # Perform checks for RTL variant if chosen - if self.use_rtl_variant: - assert self.mem_mode == "decoupled", ( - """%s : RTL Thresholding only supports 'decoupled' memory - mode.""" - % node.name - ) - if self.use_rtl_variant and is_rtl_variant_compatible: new_node = helper.make_node( "Thresholding_Binary_Search", From a3d6b340d33faa6f30a3239f1a95513e5364cfe8 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Thu, 18 Jan 2024 09:47:51 +0000 Subject: [PATCH 392/665] [BTS] WIP: memory estimation helpers --- src/finn/util/basic.py | 51 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/src/finn/util/basic.py b/src/finn/util/basic.py index 5252422dcf..0a6c0b39c9 100644 --- a/src/finn/util/basic.py +++ b/src/finn/util/basic.py @@ -30,6 +30,7 @@ import subprocess import sys import tempfile +from qonnx.util.basic import roundup_to_integer_multiple # test boards test_board_map = ["Pynq-Z1", "KV260_SOM", "ZCU104", "U250"] @@ -76,6 +77,11 @@ alveo_default_platform["U280"] = "xilinx_u280_gen3x16_xdma_1_202211_1" alveo_default_platform["U55C"] = "xilinx_u55c_gen3x16_xdma_3_202210_1" +# Create a joint part map, encompassing other boards too +part_map = {**pynq_part_map, **alveo_part_map} +part_map["VEK280"] = "xcve2802-vsvh1760-2MP-e-S" +part_map["VCK190"] = "xcvc1902-vsva2197-2MP-e-S" + def get_rtlsim_trace_depth(): """Return the trace depth for rtlsim via PyVerilator. Controllable @@ -247,3 +253,48 @@ def find_next_power_of_2(n): # unset rightmost bit n = n & n - 1 return n << 1 + + +mem_primitives_versal = { + "URAM_72x4096": (72, 4096), + "URAM_36x8192": (36, 8192), + "URAM_18x16384": (18, 16384), + "URAM_9x32768": (9, 32768), + "BRAM18_36x512": (36, 512), + "BRAM18_18x1024": (18, 1024), + "BRAM18_9x2048": (9, 2048), + "LUTRAM": (1, 64), +} + + +def get_memutil_alternatives( + req_mem_spec, mem_primitives=mem_primitives_versal, sort_min_waste=True +): + ret = [ + (primitive_name, memutil(req_mem_spec, primitive_spec)) + for (primitive_name, primitive_spec) in mem_primitives.items() + ] + if sort_min_waste: + ret = sorted(ret, key=lambda x: x[1][2]) + return ret + + +def memutil(req_mem_spec, primitive_spec): + """Computes how many instances of a memory primitive are necessary to + implemented a desired memory size, where req_mem_spec is the desired + size and the primitive_spec is the primitve size. The sizes are expressed + as tuples of (mem_width, mem_depth). Returns (primitive_count, efficiency, waste) + where efficiency in range [0,1] indicates how much of the total capacity is + utilized, and waste indicates how many bits of storage are wasted.""" + + req_width, req_depth = req_mem_spec + prim_width, prim_depth = primitive_spec + + match_width = roundup_to_integer_multiple(req_width, prim_width) + match_depth = roundup_to_integer_multiple(req_depth, prim_depth) + count_width = match_width // prim_width + count_depth = match_depth // prim_depth + count = count_depth * count_width + eff = (req_width * req_depth) / (count * prim_width * prim_depth) + waste = (count * prim_width * prim_depth) - (req_width * req_depth) + return (count, eff, waste) From 2365592f699e9481091571126e60fbb15db122d2 Mon Sep 17 00:00:00 2001 From: Yaman Umuroglu Date: Sat, 16 Dec 2023 01:43:30 +0100 Subject: [PATCH 393/665] [FIFO] disable poorly justified SWG exception for FIFO sizing --- src/finn/transformation/fpgadataflow/set_fifo_depths.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/finn/transformation/fpgadataflow/set_fifo_depths.py b/src/finn/transformation/fpgadataflow/set_fifo_depths.py index d481fb027c..72b5e495a4 100644 --- a/src/finn/transformation/fpgadataflow/set_fifo_depths.py +++ b/src/finn/transformation/fpgadataflow/set_fifo_depths.py @@ -241,7 +241,7 @@ def __init__( clk_ns=10.0, max_qsrl_depth=256, max_depth=None, - swg_exception=True, + swg_exception=False, vivado_ram_style="auto", force_python_sim=False, ): From 234e568a268e8d670e3c255b7586068a9b32f28a Mon Sep 17 00:00:00 2001 From: auphelia Date: Thu, 18 Jan 2024 16:06:20 +0000 Subject: [PATCH 394/665] [Tests] Combine 1D and 2D tests for swg --- .../test_fpgadataflow_convinputgenerator.py | 102 ++---------------- 1 file changed, 11 insertions(+), 91 deletions(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py index 07de85d0b5..1a9a934df1 100644 --- a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py +++ b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py @@ -94,21 +94,21 @@ def prepare_inputs(input_tensor): # input datatype -@pytest.mark.parametrize("idt", [DataType["BIPOLAR"], DataType["INT2"]]) +@pytest.mark.parametrize("idt", [DataType["BIPOLAR"], DataType["UINT4"]]) # kernel size -@pytest.mark.parametrize("k", [[2, 2], [3, 3]]) +@pytest.mark.parametrize("k", [[2, 2], [3, 3], [1, 5]]) # input dimension -@pytest.mark.parametrize("ifm_dim", [[6, 6], [8, 8]]) +@pytest.mark.parametrize("ifm_dim", [[8, 8], [1, 21]]) # input channels @pytest.mark.parametrize("ifm_ch", [2, 4]) # Stride -@pytest.mark.parametrize("stride", [[1, 1], [2, 2]]) +@pytest.mark.parametrize("stride", [[1, 1], [2, 2], [2, 1]]) # Dilation -@pytest.mark.parametrize("dilation", [[1, 1], [2, 2]]) +@pytest.mark.parametrize("dilation", [[1, 1], [2, 2], [2, 1]]) # execution mode @pytest.mark.parametrize("exec_mode", ["cppsim", "rtlsim"]) # input channel parallelism ("SIMD") -@pytest.mark.parametrize("simd", [1, 2]) +@pytest.mark.parametrize("simd", [1, 2, 4]) # depthwise @pytest.mark.parametrize("dw", [0, 1]) # parallel_window enable (MMV_out = M*K) @@ -193,9 +193,13 @@ def test_fpgadataflow_slidingwindow( # set simd inst = getCustomOp(model.graph.node[0]) inst.set_nodeattr("SIMD", simd) - if model.graph.node[0].op_type == "ConvolutionInputGenerator_rtl": + optype = model.graph.node[0].op_type + if optype == "ConvolutionInputGenerator_rtl": inst.set_nodeattr("parallel_window", parallel_window) inst.set_nodeattr("M", m) + if optype == "ConvolutionInputGenerator_hls": + if inst.get_nodeattr("is1D"): + inst.set_nodeattr("parallel_window", parallel_window) if exec_mode == "cppsim": if model.graph.node[0].op_type == "ConvolutionInputGenerator_rtl": @@ -236,87 +240,3 @@ def test_fpgadataflow_slidingwindow( assert exp_cycles != 0 else: assert model.graph.node[0].op_type == "ConvolutionInputGenerator_rtl" - - -# input datatype -@pytest.mark.parametrize("idt", [DataType["INT8"]]) -# kernel size -@pytest.mark.parametrize("k", [[4, 1]]) -# input dimension -@pytest.mark.parametrize("ifm_dim", [[10, 1]]) -# input channels -@pytest.mark.parametrize("ifm_ch", [1, 4]) -# Stride -@pytest.mark.parametrize("stride", [[1, 1], [2, 1]]) -# Dilation -@pytest.mark.parametrize("dilation", [[1, 1], [2, 1]]) -# execution mode -@pytest.mark.parametrize("exec_mode", ["cppsim", "rtlsim"]) -# input channel parallelism ("SIMD") -@pytest.mark.parametrize("simd", [1, 4]) -# depthwise -@pytest.mark.parametrize("dw", [0, 1]) -# TODO add parallel_window and M option -# implementation style -@pytest.mark.parametrize("impl_style", ["rtl", "hls"]) -@pytest.mark.fpgadataflow -@pytest.mark.slow -@pytest.mark.vivado -def test_fpgadataflow_slidingwindow1d( - idt, k, ifm_dim, ifm_ch, stride, dilation, exec_mode, simd, dw, impl_style -): - ofm_dim = int(((ifm_dim - k) / stride) + 1) - - x = gen_finn_dt_tensor(idt, (1, ifm_dim, ifm_dim, ifm_ch)) - input_dict = prepare_inputs(x) - model = make_single_im2col_modelwrapper( - k, ifm_ch, ifm_dim, ofm_dim, simd, stride, dilation, idt, dw - ) - y_expected = oxe.execute_onnx(model, input_dict)["outp"] - - model = model.transform(to_hw.InferConvInpGen()) - model.save("model_before.onnx") - # set impl_style - inst = getCustomOp(model.get_nodes_by_op_type("ConvolutionInputGenerator")[0]) - inst.set_nodeattr("preferred_impl_style", impl_style) - model = model.transform(SpecializeLayers()) - # set simd - inst = getCustomOp(model.graph.node[0]) - inst.set_nodeattr("SIMD", simd) - model.save("model_after.onnx") - - if exec_mode == "cppsim": - if impl_style == "rtl": - pytest.skip("cppsim not supported for RTL DWC") - else: - model = model.transform(SetExecMode("cppsim")) - model = model.transform(PrepareCppSim()) - model = model.transform(CompileCppSim()) - elif exec_mode == "rtlsim": - model = model.transform(SetExecMode("rtlsim")) - model = model.transform(GiveUniqueNodeNames()) - model = model.transform(PrepareIP("xc7z020clg400-1", 5)) - model = model.transform(HLSSynthIP()) - model = model.transform(PrepareRTLSim()) - else: - raise Exception("Unknown exec_mode in test_fpgadataflow_slidingwindow") - - # execute model - y_produced = oxe.execute_onnx(model, input_dict)["outp"] - - if dw == 0: - assert (y_produced == y_expected).all() - else: - y_expected = y_expected.reshape(1, ofm_dim, ofm_dim, k * k, ifm_ch // simd, simd) - y_expected = y_expected.transpose(0, 1, 2, 4, 3, 5) - y_expected = y_expected.reshape(1, ofm_dim, ofm_dim, ifm_ch * k * k) - assert (y_produced == y_expected).all() - - if exec_mode == "rtlsim" and impl_style == "hls": - node = model.get_nodes_by_op_type("ConvolutionInputGenerator_hls")[0] - inst = getCustomOp(node) - cycles_rtlsim = inst.get_nodeattr("cycles_rtlsim") - exp_cycles_dict = model.analysis(exp_cycles_per_layer) - exp_cycles = exp_cycles_dict[node.name] - assert np.isclose(exp_cycles, cycles_rtlsim, atol=10) - assert exp_cycles != 0 From 5ae57acfd214b0e96f8b5242b08c33065db0bee4 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Thu, 18 Jan 2024 18:32:06 +0000 Subject: [PATCH 395/665] [BTS-Integration] HLS module Placeholder --- src/finn/custom_op/fpgadataflow/__init__.py | 6 +- .../custom_op/fpgadataflow/hls/__init__.py | 2 + .../hls/thresholdingbinarysearch_hls.py | 856 ++++++++++++++++++ .../fpgadataflow/thresholdingbinarysearch.py | 115 +++ ...fpgadataflow_thresholding_binary_search.py | 53 +- 5 files changed, 1028 insertions(+), 4 deletions(-) create mode 100644 src/finn/custom_op/fpgadataflow/hls/thresholdingbinarysearch_hls.py create mode 100644 src/finn/custom_op/fpgadataflow/thresholdingbinarysearch.py diff --git a/src/finn/custom_op/fpgadataflow/__init__.py b/src/finn/custom_op/fpgadataflow/__init__.py index 6fffbcc23d..827a8ea8da 100644 --- a/src/finn/custom_op/fpgadataflow/__init__.py +++ b/src/finn/custom_op/fpgadataflow/__init__.py @@ -54,8 +54,8 @@ from finn.custom_op.fpgadataflow.streamingfifo import StreamingFIFO from finn.custom_op.fpgadataflow.streamingmaxpool import StreamingMaxPool from finn.custom_op.fpgadataflow.thresholding_batch import Thresholding_Batch -from finn.custom_op.fpgadataflow.thresholding_binary_search import ( - Thresholding_Binary_Search, +from finn.custom_op.fpgadataflow.thresholdingbinarysearch import ( + ThresholdingBinarySearch, ) from finn.custom_op.fpgadataflow.tlastmarker import TLastMarker from finn.custom_op.fpgadataflow.upsampler import UpsampleNearestNeighbour @@ -71,7 +71,7 @@ custom_op["Pool_Batch"] = Pool_Batch custom_op["FMPadding_Pixel"] = FMPadding_Pixel custom_op["Thresholding_Batch"] = Thresholding_Batch -custom_op["Thresholding_Binary_Search"] = Thresholding_Binary_Search +custom_op["ThresholdingBinarySearch"] = ThresholdingBinarySearch custom_op["VectorVectorActivation"] = VectorVectorActivation custom_op["IODMA"] = IODMA custom_op["StreamingDataflowPartition"] = StreamingDataflowPartition diff --git a/src/finn/custom_op/fpgadataflow/hls/__init__.py b/src/finn/custom_op/fpgadataflow/hls/__init__.py index bcf36dad67..36b603102d 100644 --- a/src/finn/custom_op/fpgadataflow/hls/__init__.py +++ b/src/finn/custom_op/fpgadataflow/hls/__init__.py @@ -43,6 +43,7 @@ from finn.custom_op.fpgadataflow.hls.streamingeltwise_hls import StreamingEltwise_hls from finn.custom_op.fpgadataflow.hls.streamingmaxpool_hls import StreamingMaxPool_hls from finn.custom_op.fpgadataflow.hls.upsampler_hls import UpsampleNearestNeighbour_hls +from finn.custom_op.fpgadataflow.hls.thresholdingbinarysearch_hls import ThresholdingBinarySearch_hls custom_op = dict() @@ -60,4 +61,5 @@ custom_op["StreamingEltwise_hls"] = StreamingEltwise_hls custom_op["StreamingDataWidthConverter_hls"] = StreamingDataWidthConverter_hls custom_op["StreamingMaxPool_hls"] = StreamingMaxPool_hls +custom_op["ThresholdingBinarySearch_hls"] = ThresholdingBinarySearch_hls custom_op["UpsampleNearestNeighbour_hls"] = UpsampleNearestNeighbour_hls diff --git a/src/finn/custom_op/fpgadataflow/hls/thresholdingbinarysearch_hls.py b/src/finn/custom_op/fpgadataflow/hls/thresholdingbinarysearch_hls.py new file mode 100644 index 0000000000..a782b21800 --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/hls/thresholdingbinarysearch_hls.py @@ -0,0 +1,856 @@ +# Copyright (c) 2024, Xilinx +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import numpy as np +import os +import textwrap +import warnings +from math import ceil, log2 +from finn.custom_op.fpgadataflow.thresholdingbinarysearch import ThresholdingBinarySearch +from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend +from qonnx.core.datatype import DataType +from qonnx.util.basic import ( + interleave_matrix_outer_dim_from_partitions, + roundup_to_integer_multiple, +) + +from finn.util.data_packing import ( + npy_to_rtlsim_input, + numpy_to_hls_code, + pack_innermost_dim_as_hex_string, + rtlsim_output_to_npy, +) + +# ONNX i/o tensor shape assumptions for Thresholding: +# input 0 is the input tensor, shape (..., NumChannels) +# input 1 is the threshold tensor, shape (NumChannels, n_thres) +# output 0 is the output tensor, shape (..., NumChannels) - same as input +# the ... here can be any shape (representing groups of vectors) + + +class ThresholdingBinarySearch_hls(ThresholdingBinarySearch,HLSBackend): + """Class that corresponds to finn-hls Thresholding_Batch function.""" + + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) + + def get_nodeattr_types(self): + my_attrs = {} + my_attrs.update(ThresholdingBinarySearch.get_nodeattr_types(self)) + my_attrs.update(HLSBackend.get_nodeattr_types(self)) + return my_attrs + + def calc_tmem(self): + """Calculates and returns TMEM.""" + mh = self.get_nodeattr("NumChannels") + pe = self.get_nodeattr("PE") + return mh // pe + + def infer_node_datatype(self, model): + pass + + def verify_node(self): + info_messages = [] + # verify that "backend" is set to "fpgadataflow" + backend_value = self.get_nodeattr("backend") + if backend_value == "fpgadataflow": + info_messages.append("Attribute backend is set correctly") + else: + info_messages.append('Attribute backend should be set to "fpgadataflow"') + + # verify that all necessary attributes exist + # TODO collect automatically from get_nodeattr_types + try: + self.get_nodeattr("code_gen_dir_cppsim") + self.get_nodeattr("executable_path") + self.get_nodeattr("NumChannels") + self.get_nodeattr("PE") + self.get_nodeattr("inputDataType") + self.get_nodeattr("outputDataType") + info_messages.append("All necessary attributes exist") + except Exception: + info_messages.append("""The required Threshold_Batch attributes do not exist.""") + + return info_messages + + def bram_estimation(self): + """Calculates BRAM cost if resource set to BRAM""" + style = self.get_nodeattr("ram_style") + P = self.get_nodeattr("PE") + idt = self.get_input_datatype() + A = idt.bitwidth() + tmem = self.calc_tmem() + + if style == "block" and tmem > 1: + return int(ceil(A * P / 16)) * int(ceil(tmem / 1024)) + else: + return 0 + + def lut_estimation(self): + """Calculates LUT cost, taking memory resource type into account""" + # TODO add in/out FIFO contributions + style = self.get_nodeattr("ram_style") + P = self.get_nodeattr("PE") + idt = self.get_input_datatype() + A = idt.bitwidth() + tmem = self.calc_tmem() + # cost of comparators + comparator_cost = A * P + # cost of LUTRAM + if style == "distributed" and tmem > 1: + lutram_cost = P * A * int(ceil(tmem / 64)) + else: + lutram_cost = 0 + # total cost + return comparator_cost + lutram_cost + + def get_input_datatype(self, ind=0): + """Returns FINN DataType of input.""" + return DataType[self.get_nodeattr("inputDataType")] + + def get_output_datatype(self, ind=0): + """Returns FINN DataType of output.""" + return DataType[self.get_nodeattr("outputDataType")] + + def get_weight_datatype(self): + """Returns FINN DataType of thresholds, here called weights.""" + return DataType[self.get_nodeattr("weightDataType")] + + def minimize_accumulator_width(self, model): + "Minimize threshold width ('accumulator width' here due to convention)" + thresholds = model.get_initializer(self.onnx_node.input[1]) + threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds) + min_threshold = thresholds.min() + max_threshold = thresholds.max() + min_input = self.get_input_datatype().min() + max_input = self.get_input_datatype().max() + # get range required by threshold values + tdt_min = min(min_input, min_threshold) + tdt_max = max(max_input, max_threshold) + if tdt_min < 0: + if abs(tdt_min) > tdt_max: + tdt = DataType.get_smallest_possible(tdt_min) + else: + tdt = DataType.get_smallest_possible(-tdt_max - 1) + else: + tdt = DataType.get_smallest_possible(tdt_max) + assert np.vectorize(tdt.allowed)( + threshold_tensor + ).all(), "Thresholds can't be expressed with type %s" % str(tdt) + self.set_nodeattr("weightDataType", tdt.name) + # Update QONNX DataType of tensor for consistency + model.set_tensor_datatype(self.onnx_node.input[1], tdt) + return DataType[self.get_nodeattr("weightDataType")] + + def get_instream_width(self, ind=0): + i_bits = self.get_input_datatype().bitwidth() + return i_bits * self.get_nodeattr("PE") + + def get_outstream_width(self, ind=0): + o_bits = self.get_output_datatype().bitwidth() + return o_bits * self.get_nodeattr("PE") + + def get_weightstream_width(self): + """Returns weight stream width. Used only in decoupled mode.""" + if self.get_nodeattr("mem_mode") == "decoupled": + pe = self.get_nodeattr("PE") + wp = self.get_weight_datatype().bitwidth() + n_thres_steps = self.get_nodeattr("numSteps") + w_width = pe * wp * n_thres_steps + return w_width + else: + return 0 + + def get_weightstream_width_padded(self): + """Returns weight stream width padded to a multiple of 8. This is required + by the AXI Stream spec. Used in decoupled mode.""" + weight_width = self.get_weightstream_width() + return roundup_to_integer_multiple(weight_width, 8) + + def get_ap_int_max_w(self): + temp_value = super().get_ap_int_max_w() + weightstream = self.get_weightstream_width() + return max([weightstream, temp_value]) + + def get_folded_input_shape(self, ind=0): + ich = self.get_nodeattr("NumChannels") + pe = self.get_nodeattr("PE") + fold = ich // pe + vecs = list(self.get_nodeattr("numInputVectors")) + folded_input_shape = tuple(vecs + [fold, pe]) + return folded_input_shape + + def get_folded_output_shape(self, ind=0): + # same shape as input + return self.get_folded_input_shape() + + def get_normal_input_shape(self, ind=0): + ich = self.get_nodeattr("NumChannels") + vecs = list(self.get_nodeattr("numInputVectors")) + normal_input_shape = tuple(vecs + [ich]) + return normal_input_shape + + def get_normal_output_shape(self, ind=0): + # same shape as input + return self.get_normal_input_shape() + + def get_number_output_values(self): + nf = np.prod(self.get_folded_output_shape()[:-1]) + return nf + + def get_exp_cycles(self): + # Channels/PE * batch size * fmdim * fmdim + return np.prod(self.get_folded_output_shape()[:-1]) + + def get_template_param_values(self): + """Returns the template parameter values according to input, output and weight + data types.""" + ret = dict() + inp_hls_str = self.get_input_datatype().get_hls_datatype_str() + out_hls_str = self.get_output_datatype().get_hls_datatype_str() + # fill in TSrcI + ret["TSrcI"] = "Slice<%s>" % inp_hls_str + # fill in TDstI + ret["TDstI"] = "Slice<%s>" % out_hls_str + + return ret + + def get_hls_compatible_threshold_tensor(self, orig_thres_matrix): + """Convert the original numpy weight matrix orig_weight_matrix into + a form suitable for passing to the hlslib call: + * ensure MH % PE == 0 + * for unsigned inputs, ensure thresholds are positive + * interleave rows between PEs + * reshape into (PE, TMEM, n_thres_steps) and return + """ + mh = self.get_nodeattr("NumChannels") + pe = self.get_nodeattr("PE") + tmem = mh // pe + assert mh % pe == 0, "Requirement NumChannels divisable by PE is violated." + assert ( + orig_thres_matrix.ndim == 2 + ), """Threshold matrix dimension is + not as expected (2).""" + n_thres_steps = orig_thres_matrix.shape[1] + assert n_thres_steps == self.get_nodeattr("numSteps"), "Mismatch in threshold steps" + if not self.get_input_datatype().signed(): + # ensure all thresholds are nonnegative + assert (orig_thres_matrix >= 0).all() + # ensure all thresholds are integer + assert np.equal(np.mod(orig_thres_matrix, 1), 0).all(), "Need int threshold tensor" + ret = orig_thres_matrix + # ensure channels = mh , duplicating if necessary + if ret.shape[0] == 1: + ret = np.tile(ret, (mh, 1)) + assert ret.shape[0] == mh, "Channels of threshold matrix are not as expected (mh)" + # distribute rows between PEs + ret = interleave_matrix_outer_dim_from_partitions(ret, pe) + assert ( + ret.shape[0] == pe + ), """First dimension after distribution of the + rows between PEs is not as expected (pe)""" + assert ( + ret.shape[1] == tmem + ), """Second dimension after distribution of the + rows between PEs is not as expected (tmem)""" + assert ( + ret.shape[2] == n_thres_steps + ), """Third dimension after distribution of the + rows between PEs is not as expected (n_thres_steps)""" + return ret.reshape(1, pe, tmem, n_thres_steps) + + def make_weight_file(self, weights, weight_file_mode, weight_file_name): + """Produce a file containing given weights (thresholds) in appropriate + format for this layer. This file can be used for either synthesis or + run-time reconfig of weights. + + Arguments: + + * weights : numpy array with weights to be put into the file + * weight_file_mode : one of {hls_header, decoupled_verilog_dat, + decoupled_runtime} + * weight_file_name : filename for the weight file to be generated + + """ + threshold_tensor = self.get_hls_compatible_threshold_tensor(weights) + tdt = self.get_weight_datatype() + assert np.vectorize(tdt.allowed)( + threshold_tensor + ).all(), "Thresholds can't be expressed with type %s" % str(tdt) + if weight_file_mode == "hls_header": + # save thresholds in thresh.h + thresholds_hls_code = numpy_to_hls_code( + threshold_tensor, tdt, "thresholds", False, True + ) + # write thresholds into thresh.h + f_thresh = open(weight_file_name, "w") + tdt_hls = tdt.get_hls_datatype_str() + # use binary to export bipolar activations + export_odt = self.get_output_datatype() + if self.get_output_datatype() == DataType["BIPOLAR"]: + export_odt = DataType["BINARY"] + odt_hls = export_odt.get_hls_datatype_str() + f_thresh.write( + "static ThresholdsActivation<{},{},{},{},{},{},{}> threshs \ + = ".format( + self.calc_tmem(), + self.get_nodeattr("PE"), + threshold_tensor.shape[-1], + tdt_hls, + odt_hls, + self.get_nodeattr("ActVal"), + "comp::less_equal<%s, %s>" % (tdt_hls, tdt_hls), + ) + ) + f_thresh.write(thresholds_hls_code) + f_thresh.close() + elif "decoupled" in weight_file_mode: + # streaming thresholds need to be organized differently + # (1, pe, tmem, n_thres_steps) -> (1, tmem, pe, n_thres_steps) + decoupled_thres = np.transpose(threshold_tensor, (0, 2, 1, 3)) + # TODO add flips/reversals as needed here + # (1, tmem, pe, n_thres_steps) -(1, tmem, pe * n_thres_steps) + pe = self.get_nodeattr("PE") + n_thres_steps = self.get_nodeattr("numSteps") + decoupled_thres_pe_flipped = np.flip(decoupled_thres, axis=-2) + decoupled_thres = decoupled_thres.reshape(1, -1, pe * n_thres_steps) + decoupled_thres = decoupled_thres.copy() + decoupled_thres_pe_flipped = decoupled_thres_pe_flipped.reshape( + 1, -1, pe * n_thres_steps + ) + decoupled_thres_pe_flipped = decoupled_thres_pe_flipped.copy() + + if weight_file_mode == "decoupled_npy": + # save weight stream into npy for cppsim + np.save(weight_file_name, decoupled_thres) + elif weight_file_mode == "decoupled_verilog_dat": + # convert weight values into hexstring + weight_width = self.get_weightstream_width() + # pad to nearest 4 bits to get hex strings + weight_width_padded = roundup_to_integer_multiple(weight_width, 4) + weight_tensor_pe_flipped = pack_innermost_dim_as_hex_string( + decoupled_thres_pe_flipped, tdt, weight_width_padded, prefix="" + ) + weight_stream = weight_tensor_pe_flipped.flatten() + weight_stream = weight_stream.copy() + with open(weight_file_name, "w") as f: + for val in weight_stream: + f.write(val + "\n") + elif weight_file_mode == "decoupled_runtime": + # memstream axi-lite interface will map each mem line to + # one or multiple 32-bit words + weight_width = self.get_weightstream_width() + words_per_memwidth = 2 ** ceil(log2(weight_width / 32)) + if words_per_memwidth < 1: + words_per_memwidth = 1 + weight_width_padded = words_per_memwidth * 32 + # first, pack and ensure padding to 32 bits + weight_tensor_pe_flipped = pack_innermost_dim_as_hex_string( + decoupled_thres_pe_flipped, tdt, weight_width_padded, prefix="" + ) + weight_stream = weight_tensor_pe_flipped.flatten() + weight_stream = weight_stream.copy() + with open(weight_file_name, "w") as f: + for val in weight_stream: + # split into groups of 8 hex digits (= 32 bits) + words_32b = textwrap.wrap(val, 8) + words_32b.reverse() + for word_32b in words_32b: + f.write(word_32b + "\n") + else: + raise Exception("Decoupled weight export not yet implemented") + else: + raise Exception("Unknown weight_file_mode") + + def generate_params(self, model, path): + code_gen_dir = path + thresholds = model.get_initializer(self.onnx_node.input[1]) + mem_mode = self.get_nodeattr("mem_mode") + if mem_mode == "const": + # save thresholds in thresh.h + weight_filename = "{}/thresh.h".format(code_gen_dir) + self.make_weight_file(thresholds, "hls_header", weight_filename) + elif mem_mode == "decoupled": + # save decoupled weights for cppsim + weight_filename_sim = "{}/thresholds.npy".format(code_gen_dir) + self.make_weight_file(thresholds, "decoupled_npy", weight_filename_sim) + # also save weights as Verilog .dat file + # This file will be ignored when synthesizing UltraScale memory. + weight_filename_rtl = "{}/memblock.dat".format(code_gen_dir) + self.make_weight_file(thresholds, "decoupled_verilog_dat", weight_filename_rtl) + else: + raise Exception("Unrecognized mem_mode") + + def execute_node(self, context, graph): + mode = self.get_nodeattr("exec_mode") + node = self.onnx_node + + # TODO ensure codegen dir exists + if mode == "cppsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + elif mode == "rtlsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + + # create a npy file fore each input of the node (in_ind is input index) + in_ind = 0 + for inputs in node.input: + # it is assumed that the first input of the node is the data input + # the second input are the weights + # the third input are the thresholds + if in_ind == 0: + assert ( + str(context[inputs].dtype) == "float32" + ), """Input datatype is + not float32 as expected.""" + expected_inp_shape = self.get_folded_input_shape() + reshaped_input = context[inputs].reshape(expected_inp_shape) + if self.get_input_datatype() == DataType["BIPOLAR"]: + # store bipolar activations as binary + reshaped_input = (reshaped_input + 1) / 2 + export_idt = DataType["BINARY"] + else: + export_idt = self.get_input_datatype() + # make copy before saving the array + reshaped_input = reshaped_input.copy() + np.save( + os.path.join(code_gen_dir, "input_{}.npy".format(in_ind)), + reshaped_input, + ) + elif in_ind > 2: + raise Exception("Unexpected input found for Thresholding_Batch") + in_ind += 1 + + if mode == "cppsim": + # execute the precompiled model + super().exec_precompiled_singlenode_model() + # load output npy file + super().npy_to_dynamic_output(context) + # reinterpret binary output as bipolar where needed + if self.get_output_datatype() == DataType["BIPOLAR"]: + out = context[node.output[0]] + out = 2 * out - 1 + context[node.output[0]] = out + oshape = self.get_normal_output_shape() + assert context[node.output[0]].shape == oshape, """Output shape is not as expected""" + + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + + def global_includes(self): + self.code_gen_dict["$GLOBALS$"] = ['#include "activations.hpp"'] + if self.get_nodeattr("mem_mode") == "const": + self.code_gen_dict["$GLOBALS$"] += ['#include "thresh.h"'] + + # TODO check and add whatever missing + def defines(self, var): + numReps = 1 + numInputVectors = list(self.get_nodeattr("numInputVectors")) + total_spatial_size = int(np.prod(numInputVectors)) + + self.code_gen_dict["$DEFINES$"] = [ + """#define NumChannels1 {}\n #define PE1 {}\n #define numReps {}\n + #define ImgDim1 {}""".format( + self.get_nodeattr("NumChannels"), + self.get_nodeattr("PE"), + numReps, + total_spatial_size, + ) + ] + if self.get_nodeattr("mem_mode") == "decoupled": + self.code_gen_dict["$DEFINES$"].append( + "#define ActVal1 %d" % self.get_nodeattr("ActVal") + ) + self.code_gen_dict["$DEFINES$"].append( + "#define ThresType1 %s" % self.get_weight_datatype().get_hls_datatype_str() + ) + self.code_gen_dict["$DEFINES$"].append( + "#define NumSteps1 %d" % self.get_nodeattr("numSteps") + ) + + def read_npy_data(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_input_datatype() + elem_bits = dtype.bitwidth() + packed_bits = self.get_instream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "float" + npy_in = "%s/input_0.npy" % code_gen_dir + self.code_gen_dict["$READNPYDATA$"] = [] + # note: the innermost dim is reversed for the input + self.code_gen_dict["$READNPYDATA$"].append( + 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s, false);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) + ) + mem_mode = self.get_nodeattr("mem_mode") + if mem_mode == "decoupled": + tdt = self.get_weight_datatype() + elem_bits = tdt.bitwidth() + packed_bits = self.get_weightstream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = tdt.get_hls_datatype_str() + npy_type = "float" + npy_in = "%s/thresholds.npy" % code_gen_dir + + self.code_gen_dict["$READNPYDATA$"].append( + 'npy2apintstream<%s, %s, %d, %s>("%s", weights_%s, false, ImgDim1);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) + ) + + def strm_decl(self): + self.code_gen_dict["$STREAMDECLARATIONS$"] = [] + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> in0_{} ("in0_{}");'.format( + self.get_instream_width(), self.hls_sname(), self.hls_sname() + ) + ) + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> out_{} ("out_{}");'.format( + self.get_outstream_width(), self.hls_sname(), self.hls_sname() + ) + ) + mem_mode = self.get_nodeattr("mem_mode") + if mem_mode == "decoupled": + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> weights_{} ("weights_{}");'.format( + self.get_weightstream_width(), self.hls_sname(), self.hls_sname() + ) + ) + + def docompute(self): + tmpl_args = self.get_template_param_values() + node = self.onnx_node + mem_mode = self.get_nodeattr("mem_mode") + if mem_mode == "const": + self.code_gen_dict["$DOCOMPUTE$"] = [ + """{} + (in0_{}, out_{}, threshs, numReps);""".format( + node.op_type, + tmpl_args["TSrcI"], + tmpl_args["TDstI"], + self.hls_sname(), + self.hls_sname(), + ) + ] + elif mem_mode == "decoupled": + # note that numReps is set to 1 in the invocation below, since + # - for cppsim the repetition comes from the threshold stream reader+input + # - for synth the unit runs continuously anyway (ap_ctrl_none) + self.code_gen_dict["$DOCOMPUTE$"] = [ + """{} + (in0_{}, out_{}, weights_{}, numReps);""".format( + "Thresholding_Stream_Batch", + tmpl_args["TSrcI"], + tmpl_args["TDstI"], + self.hls_sname(), + self.hls_sname(), + self.hls_sname(), + ) + ] + else: + raise Exception("Unrecognized mem_mode") + + def dataoutstrm(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_output_datatype() + if dtype == DataType["BIPOLAR"]: + # use binary for bipolar storage + dtype = DataType["BINARY"] + elem_bits = dtype.bitwidth() + packed_bits = self.get_outstream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "float" + npy_out = "%s/output.npy" % code_gen_dir + shape = self.get_folded_output_shape() + shape_cpp_str = str(shape).replace("(", "{").replace(")", "}") + + # note: the innermost dim is not reversed for the output + self.code_gen_dict["$DATAOUTSTREAM$"] = [ + 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s", false);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + self.hls_sname(), + shape_cpp_str, + npy_out, + ) + ] + + def save_as_npy(self): + self.code_gen_dict["$SAVEASCNPY$"] = [] + + def blackboxfunction(self): + if self.get_nodeattr("mem_mode") == "const": + self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ + """void {}(hls::stream> &in0_{}, + hls::stream> &out_{} + )""".format( + self.onnx_node.name, + self.get_instream_width(), + self.hls_sname(), + self.get_outstream_width(), + self.hls_sname(), + ) + ] + elif self.get_nodeattr("mem_mode") == "decoupled": + self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ + """void {}(hls::stream> &in0_{}, + hls::stream> &weights_{}, + hls::stream> &out_{} + )""".format( + self.onnx_node.name, + self.get_instream_width(), + self.hls_sname(), + self.get_weightstream_width(), + self.hls_sname(), + self.get_outstream_width(), + self.hls_sname(), + ) + ] + else: + raise Exception("Unrecognized mem_mode") + + def pragmas(self): + self.code_gen_dict["$PRAGMAS$"] = [ + "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() + ] + self.code_gen_dict["$PRAGMAS$"].append( + "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() + ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") + + if self.get_nodeattr("mem_mode") == "const": + # the threshold tensor is acc_type [PE][TMEM][N_THRES] + # partition for parallel access along PE and N_THRES + # dimensions (dims 1 and 3) + self.code_gen_dict["$PRAGMAS$"].append( + ("#pragma HLS ARRAY_PARTITION variable=threshs.m_thresholds " "complete dim=1") + ) + self.code_gen_dict["$PRAGMAS$"].append( + ("#pragma HLS ARRAY_PARTITION variable=threshs.m_thresholds " "complete dim=3") + ) + # set resource type + ram_style = self.get_nodeattr("ram_style") + pe = self.get_nodeattr("PE") + ich = self.get_nodeattr("NumChannels") + # if PE less than NumChannels, assign cores according to ram_style; + # otherwise if PE == NumChannels, Vivado HLS will unroll to FFs + if pe < ich: + if ram_style == "distributed": + self.code_gen_dict["$PRAGMAS$"].append( + ("#pragma HLS RESOURCE variable=threshs.m_thresholds " "core=ROM_2P_LUTRAM") + ) + elif ram_style == "block": + self.code_gen_dict["$PRAGMAS$"].append( + ("#pragma HLS RESOURCE variable=threshs.m_thresholds " "core=ROM_2P_BRAM") + ) + else: + raise Exception( + """Invalid value for attribute ram_style! Is currently set to: {} + has to be set to one of ("block", "distributed")""".format( + ram_style + ) + ) + elif self.get_nodeattr("mem_mode") == "decoupled": + self.code_gen_dict["$PRAGMAS$"].append( + "#pragma HLS INTERFACE axis port=weights_" + self.hls_sname() + ) + + def code_generation_ipi(self): + cmd = [] + # add streamer if needed + mem_mode = self.get_nodeattr("mem_mode") + if mem_mode == "decoupled": + node_name = self.onnx_node.name + runtime_writable = self.get_nodeattr("runtime_writeable_weights") == 1 + sname = self.hls_sname() + # create a hierarchy for this layer, with the same port names + clk_name = self.get_verilog_top_module_intf_names()["clk"][0] + rst_name = self.get_verilog_top_module_intf_names()["rst"][0] + dout_name = self.get_verilog_top_module_intf_names()["m_axis"][0][0] + din_name = self.get_verilog_top_module_intf_names()["s_axis"][0][0] + cmd.append("create_bd_cell -type hier %s" % node_name) + cmd.append("create_bd_pin -dir I -type clk /%s/%s" % (node_name, clk_name)) + cmd.append("create_bd_pin -dir I -type rst /%s/%s" % (node_name, rst_name)) + cmd.append( + "create_bd_intf_pin -mode Master " + "-vlnv xilinx.com:interface:axis_rtl:1.0 /%s/%s" % (node_name, dout_name) + ) + cmd.append( + "create_bd_intf_pin -mode Slave " + "-vlnv xilinx.com:interface:axis_rtl:1.0 /%s/%s" % (node_name, din_name) + ) + # instantiate the hls ip + cmd.append( + "create_bd_cell -type ip -vlnv %s /%s/%s" + % (self.get_nodeattr("ip_vlnv"), node_name, node_name) + ) + # instantiate a streamer and connect it to the HLS IP + strm_vlnv = "amd.com:finn:memstream:1.0" + strm_inst = node_name + "_wstrm" + cmd.append( + "create_bd_cell -type ip -vlnv %s /%s/%s" % (strm_vlnv, node_name, strm_inst) + ) + cmd.append( + "set_property -dict [list " + "CONFIG.DEPTH {%d} " + "CONFIG.WIDTH {%d} " + "CONFIG.INIT_FILE {%s} " + "CONFIG.RAM_STYLE {%s} " + "] [get_bd_cells /%s/%s]" + % ( + self.calc_tmem(), + self.get_weightstream_width_padded(), + self.get_nodeattr("code_gen_dir_ipgen") + "/memblock.dat", + self.get_nodeattr("ram_style"), + node_name, + strm_inst, + ) + ) + cmd.append( + "connect_bd_intf_net [get_bd_intf_pins %s/%s/m_axis_0] " + "[get_bd_intf_pins %s/%s/weights_%s]" + % (node_name, strm_inst, node_name, node_name, sname) + ) + cmd.append( + "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/ap_rst_n]" + % (node_name, rst_name, node_name, strm_inst) + ) + cmd.append( + "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/ap_clk]" + % (node_name, clk_name, node_name, strm_inst) + ) + cmd.append( + "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/%s]" + % (node_name, rst_name, node_name, node_name, rst_name) + ) + cmd.append( + "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/%s]" + % (node_name, clk_name, node_name, node_name, clk_name) + ) + cmd.append( + "connect_bd_intf_net [get_bd_intf_pins %s/%s] " + "[get_bd_intf_pins %s/%s/%s]" + % (node_name, din_name, node_name, node_name, din_name) + ) + cmd.append( + "connect_bd_intf_net [get_bd_intf_pins %s/%s] " + "[get_bd_intf_pins %s/%s/%s]" + % (node_name, dout_name, node_name, node_name, dout_name) + ) + if runtime_writable: + # expose axi lite interface for writeable weights + axilite_name = self.get_verilog_top_module_intf_names()["axilite"][0] + cmd.append( + "create_bd_intf_pin -mode Slave " + "-vlnv xilinx.com:interface:aximm_rtl:1.0 /%s/%s" % (node_name, axilite_name) + ) + cmd.append( + "connect_bd_intf_net [get_bd_intf_pins %s/%s] " + "[get_bd_intf_pins %s/%s/%s]" + % (node_name, axilite_name, node_name, strm_inst, axilite_name) + ) + # TODO calculate and pass in segment size here + cmd.append("assign_bd_address") + cmd.append("save_bd_design") + elif mem_mode == "const": + # base class impl sufficient for const mode + return super().code_generation_ipi() + else: + raise Exception("Unrecognized mem_mode for Thresholding_Batch") + return cmd + + def get_verilog_top_module_intf_names(self): + intf_names = super().get_verilog_top_module_intf_names() + mem_mode = self.get_nodeattr("mem_mode") + if mem_mode == "decoupled": + # only expose axilite interface if attribute is set + runtime_writable = self.get_nodeattr("runtime_writeable_weights") == 1 + if runtime_writable: + intf_names["axilite"] = ["s_axilite"] + return intf_names + + def get_op_and_param_counts(self): + ret_dict = {} + weight_bits = self.get_weight_datatype().bitwidth() + out_features = self.get_nodeattr("NumChannels") + num_steps = self.get_nodeattr("numSteps") + # thresholds are called weights in this layer + thres_param_type = "param_threshold_%db" % (weight_bits) + thres_count = out_features * num_steps + ret_dict[thres_param_type] = thres_count + return ret_dict + + def ipgen_extra_directives(self): + "Return a list of extra tcl directives for HLS synthesis." + + return ["config_compile -pipeline_style frp"] + + def derive_characteristic_fxns(self, period): + n_inps = np.prod(self.get_folded_input_shape()[:-1]) + io_dict = { + "inputs": { + "in0": [0 for i in range(n_inps)], + }, + "outputs": {"out": []}, + } + mem_mode = self.get_nodeattr("mem_mode") + if mem_mode in ["decoupled", "external"]: + n_weight_inps = self.calc_tmem() + num_w_reps = np.prod(self.get_nodeattr("numInputVectors")) + io_dict["inputs"]["weights"] = [0 for i in range(num_w_reps * n_weight_inps)] + super().derive_characteristic_fxns(period, override_rtlsim_dict=io_dict) diff --git a/src/finn/custom_op/fpgadataflow/thresholdingbinarysearch.py b/src/finn/custom_op/fpgadataflow/thresholdingbinarysearch.py new file mode 100644 index 0000000000..3d919d3c6e --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/thresholdingbinarysearch.py @@ -0,0 +1,115 @@ +# Copyright (C) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import numpy as np +import warnings +from qonnx.core.datatype import DataType + +from finn.custom_op.fpgadataflow.hwcustomop import HWCustomOp + + +class ThresholdingBinarySearch(HWCustomOp): + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) + + def get_nodeattr_types(self): + my_attrs = { + # parallelization; channels thresholded per cycle + "PE": ("i", True, 0), + # number of channels (each may have different thresholds) + "NumChannels": ("i", True, 0), + # number of steps in thresholding function. Used only in decoupled mode + "numSteps": ("i", True, 1), + # FINN DataTypes for inputs, outputs + "inputDataType": ("s", True, ""), + "weightDataType": ("s", True, ""), + "outputDataType": ("s", True, ""), + # number of input vectors, examples: + # [1] is a single vector (like a FC layer with batch=1) + # [4] is four vectors (like a FC layer with batch=4) + # [1, 4, 4] is four * four vectors (like a conv layer with batch=1) + "numInputVectors": ("ints", False, [1]), + # name of the top module in verilog template. Used by PyVerilator + # and IPI generation + "gen_top_module": ("s", False, ""), + # bias to be applied to outputs of the node + "activation_bias": ("i", False, 0), + # whether weights (thresholds) will be + # writable through an AXI-lite interface during runtime + # 1 for enabled, 0 for disabled. + "runtime_writeable_weights": ("i", False, 0, {0, 1}), + # memory depth triggers for threshold storage + "depth_trigger_uram": ("i", False, 0), + "depth_trigger_bram": ("i", False, 0), + # enable uniform thres optimization + # doesn't actually do anything yet, only + # for resource estimations + "uniform_thres": ("i", False, 0, {0, 1}), + # enable deep pipelining for easier timing closure + # setting to 0 may save some FFs but otherwise leave on + "deep_pipeline": ("i", False, 1, {0, 1}), + } + my_attrs.update(super().get_nodeattr_types()) + return my_attrs + + def get_padded_odim(): + pass + + def get_exp_cycles(): + pass + + def get_normal_input_shape(): + pass + + def get_normal_output_shape(): + pass + def get_folded_input_shape(): + pass + def get_folded_output_shape(): + pass + def make_shape_compatible_op(self, model): + oshape = self.get_normal_output_shape() + return super().make_const_shape_op(oshape) + + def infer_node_datatype(): + pass + def verify_node(): + pass + def get_input_datatype(): + pass + def get_output_datatype(): + pass + def get_instream_width(): + pass + def get_outstream_width(): + pass + def get_number_output_values(): + pass + + def execute_node(self, context, graph): + pass diff --git a/tests/fpgadataflow/test_fpgadataflow_thresholding_binary_search.py b/tests/fpgadataflow/test_fpgadataflow_thresholding_binary_search.py index 24b60f5ea5..8e6bf5cbe3 100755 --- a/tests/fpgadataflow/test_fpgadataflow_thresholding_binary_search.py +++ b/tests/fpgadataflow/test_fpgadataflow_thresholding_binary_search.py @@ -45,6 +45,7 @@ from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers test_fpga_part = "xczu3eg-sbva484-1-e" target_clk_ns = 5 @@ -86,6 +87,7 @@ def convert_np_array_to_standard_data_layout(data): def make_single_thresholding_binary_search_modelwrapper( + impl_style, thresholds, pe, input_data_type, @@ -106,7 +108,7 @@ def make_single_thresholding_binary_search_modelwrapper( node_inp_list = ["inp", "thresh"] Thresholding_node = helper.make_node( - "Thresholding_Binary_Search", + "ThresholdingBinarySearch", node_inp_list, ["outp"], domain="finn.custom_op.fpgadataflow", @@ -119,6 +121,7 @@ def make_single_thresholding_binary_search_modelwrapper( outputDataType=output_data_type.name, activation_bias=activation_bias, numInputVectors=num_input_vecs, + preferred_impl_style=impl_style, ) graph = helper.make_graph( nodes=[Thresholding_node], @@ -285,3 +288,51 @@ def write_thresh_config(sim): rtlsim_exec(model, input_dict, pre_hook=config_hook(config)) y_produced = input_dict["outp"] assert (y_produced == y_expected).all() + + +# Test brief: Test basic transforms are working +@pytest.mark.parametrize("impl_style", ["rtl", "hls"]) +@pytest.mark.fpgadataflow +@pytest.mark.vivado +def test_fpgadataflow_thresholding_binary_search_transform(impl_style): + input_data_type = DataType["INT16"] + act = DataType["INT4"] + fold = -1 + num_input_channels = 16 + + # Handle inputs to the test + pe = generate_pe_value(fold, num_input_channels) + num_steps = act.get_num_possible_values() - 1 + + # Generate random, non-decreasing thresholds + thresholds = generate_random_threshold_values( + input_data_type, num_input_channels, num_steps + ) + thresholds = sort_thresholds_increasing(thresholds) + + # Other non-input parameters + num_input_vecs = [1, 2, 2] + output_data_type = act + if output_data_type == DataType["BIPOLAR"]: + activation_bias = 0 + else: + activation_bias = output_data_type.min() + + # Generate model from input parameters to the test + model = make_single_thresholding_binary_search_modelwrapper( + impl_style, + thresholds, + pe, + input_data_type, + output_data_type, + activation_bias, + num_input_vecs, + ) + + model = model.transform(SpecializeLayers()) + # model = model.transform(SetExecMode("rtlsim")) + # model = model.transform(GiveUniqueNodeNames()) + # model = model.transform(PrepareIP(test_fpga_part, target_clk_ns)) + # model = model.transform(HLSSynthIP()) + # model = model.transform(PrepareRTLSim()) + return \ No newline at end of file From f575b06e97261deb5e21b4b5a76fbaa296f6d622 Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 19 Jan 2024 15:36:58 +0000 Subject: [PATCH 396/665] [CustomOp] Initial draft of Pooling layer in new class hierarchy --- src/finn/custom_op/fpgadataflow/__init__.py | 4 +- .../custom_op/fpgadataflow/hls/__init__.py | 4 +- .../{pool_batch.py => hls/pool_hls.py} | 150 +------------ src/finn/custom_op/fpgadataflow/pool.py | 198 ++++++++++++++++++ .../fpgadataflow/convert_to_hw_layers.py | 188 ++++++++++++++++- .../fpgadataflow/specialize_layers.py | 33 +-- ...ch.py => test_convert_to_hw_pool_batch.py} | 32 +-- 7 files changed, 433 insertions(+), 176 deletions(-) rename src/finn/custom_op/fpgadataflow/{pool_batch.py => hls/pool_hls.py} (66%) create mode 100644 src/finn/custom_op/fpgadataflow/pool.py rename tests/fpgadataflow/{test_convert_to_hls_pool_batch.py => test_convert_to_hw_pool_batch.py} (88%) diff --git a/src/finn/custom_op/fpgadataflow/__init__.py b/src/finn/custom_op/fpgadataflow/__init__.py index 8254083ef7..cc496ddf2c 100644 --- a/src/finn/custom_op/fpgadataflow/__init__.py +++ b/src/finn/custom_op/fpgadataflow/__init__.py @@ -43,7 +43,7 @@ from finn.custom_op.fpgadataflow.labelselect import LabelSelect from finn.custom_op.fpgadataflow.lookup import Lookup from finn.custom_op.fpgadataflow.matrixvectoractivation import MatrixVectorActivation -from finn.custom_op.fpgadataflow.pool_batch import Pool_Batch +from finn.custom_op.fpgadataflow.pool import Pool from finn.custom_op.fpgadataflow.streamingdataflowpartition import ( StreamingDataflowPartition, ) @@ -65,7 +65,6 @@ custom_op["MatrixVectorActivation"] = MatrixVectorActivation custom_op["TLastMarker"] = TLastMarker custom_op["StreamingFIFO"] = StreamingFIFO -custom_op["Pool_Batch"] = Pool_Batch custom_op["FMPadding_Pixel"] = FMPadding_Pixel custom_op["Thresholding_Batch"] = Thresholding_Batch custom_op["VectorVectorActivation"] = VectorVectorActivation @@ -83,6 +82,7 @@ custom_op["GlobalAccPool"] = GlobalAccPool custom_op["LabelSelect"] = LabelSelect custom_op["Lookup"] = Lookup +custom_op["Pool"] = Pool custom_op["StreamingDataWidthConverter"] = StreamingDataWidthConverter custom_op["StreamingEltwise"] = StreamingEltwise custom_op["StreamingMaxPool"] = StreamingMaxPool diff --git a/src/finn/custom_op/fpgadataflow/hls/__init__.py b/src/finn/custom_op/fpgadataflow/hls/__init__.py index bcf36dad67..7ae7ffa34d 100644 --- a/src/finn/custom_op/fpgadataflow/hls/__init__.py +++ b/src/finn/custom_op/fpgadataflow/hls/__init__.py @@ -1,4 +1,4 @@ -# Copyright (C) 2023, Advanced Micro Devices, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -37,6 +37,7 @@ from finn.custom_op.fpgadataflow.hls.globalaccpool_hls import GlobalAccPool_hls from finn.custom_op.fpgadataflow.hls.labelselect_hls import LabelSelect_hls from finn.custom_op.fpgadataflow.hls.lookup_hls import Lookup_hls +from finn.custom_op.fpgadataflow.hls.pool_hls import Pool_hls from finn.custom_op.fpgadataflow.hls.streamingdatawidthconverter_hls import ( StreamingDataWidthConverter_hls, ) @@ -57,6 +58,7 @@ custom_op["GlobalAccPool_hls"] = GlobalAccPool_hls custom_op["LabelSelect_hls"] = LabelSelect_hls custom_op["Lookup_hls"] = Lookup_hls +custom_op["Pool_hls"] = Pool_hls custom_op["StreamingEltwise_hls"] = StreamingEltwise_hls custom_op["StreamingDataWidthConverter_hls"] = StreamingDataWidthConverter_hls custom_op["StreamingMaxPool_hls"] = StreamingMaxPool_hls diff --git a/src/finn/custom_op/fpgadataflow/pool_batch.py b/src/finn/custom_op/fpgadataflow/hls/pool_hls.py similarity index 66% rename from src/finn/custom_op/fpgadataflow/pool_batch.py rename to src/finn/custom_op/fpgadataflow/hls/pool_hls.py index 8c7bc83141..2baaad01a7 100644 --- a/src/finn/custom_op/fpgadataflow/pool_batch.py +++ b/src/finn/custom_op/fpgadataflow/hls/pool_hls.py @@ -1,4 +1,4 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2023, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -30,11 +30,12 @@ import os from qonnx.core.datatype import DataType -from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp +from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend +from finn.custom_op.fpgadataflow.pool import Pool from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy -class Pool_Batch(HLSCustomOp): +class Pool_hls(Pool, HLSBackend): """Class that corresponds to finn-hlslib Pool_batch function. Requires ConvolutionInputGenerator(depthwise == 1) to format its input @@ -54,148 +55,11 @@ class Pool_Batch(HLSCustomOp): """ def get_nodeattr_types(self): - my_attrs = { - "Channels": ("i", True, 0), - "PE": ("i", True, 1), - "KernelSize": ("ints", True, []), - # Function: - # - MaxPool - # - QuantAvgPool - # TODO add support for AvgPool and AccPool - "Function": ("s", True, "", {"MaxPool", "QuantAvgPool"}), - "OutImgDims": ("ints", True, []), - # FINN DataTypes for inputs/outputs - "InputDataType": ("s", True, ""), - "OutputDataType": ("s", True, ""), - "AccumBits": ("i", False, 0), - "Size": ("i", False, 1), - "BatchSize": ("i", False, 1), - } - - my_attrs.update(super().get_nodeattr_types()) + my_attrs = {} + my_attrs.update(Pool.get_nodeattr_types(self)) + my_attrs.update(HLSBackend.get_nodeattr_types(self)) return my_attrs - def get_input_datatype(self, ind=0): - """Returns FINN DataType of input.""" - return DataType[self.get_nodeattr("InputDataType")] - - def get_output_datatype(self, ind=0): - """Returns FINN DataType of output.""" - fxn = self.get_nodeattr("Function") - odt = DataType[self.get_nodeattr("OutputDataType")] - - if fxn == "MaxPool": - # Same as input - idt = DataType[self.get_nodeattr("InputDataType")] - assert odt == idt, "In datatype must be equal to out datatype for Maxpool" - elif fxn == "QuantAvgPool": - idt = DataType[self.get_nodeattr("InputDataType")] - assert ( - idt.signed() == odt.signed() - ), """QuantAvgPool: Can't mix signed - and unsigned datatypes""" - else: - raise Exception("Pool_Batch doesn't currently support " + fxn) - - return odt - - def get_normal_input_shape(self, ind=0): - ifm_ch = self.get_nodeattr("Channels") - odims = self.get_nodeattr("OutImgDims") - batch_size = self.get_nodeattr("BatchSize") - k = self.get_nodeattr("KernelSize") - k_prod = int(np.prod(k)) - ishape = (batch_size, *odims, k_prod * ifm_ch) - return ishape - - def get_folded_input_shape(self, ind=0): - normal_ishape = list(self.get_normal_input_shape()) - ifm_ch = self.get_nodeattr("Channels") - pe = self.get_nodeattr("PE") - assert ifm_ch % pe == 0, "PE must divide input channels" - fold = int(normal_ishape[-1] / pe) - folded_ishape = normal_ishape[:-1] + [fold, pe] - return tuple(folded_ishape) - - def get_normal_output_shape(self, ind=0): - ofm_ch = self.get_nodeattr("Channels") - odims = self.get_nodeattr("OutImgDims") - batch_size = self.get_nodeattr("BatchSize") - oshape = (batch_size, *odims, ofm_ch) - return oshape - - def get_folded_output_shape(self, ind=0): - normal_oshape = list(self.get_normal_output_shape()) - ifm_ch = self.get_nodeattr("Channels") - pe = self.get_nodeattr("PE") - assert ifm_ch % pe == 0, "PE must divide input channels" - fold = int(ifm_ch / pe) - folded_oshape = normal_oshape[:-1] + [fold, pe] - return tuple(folded_oshape) - - def get_number_output_values(self): - folded_oshape = self.get_folded_output_shape() - return np.prod(folded_oshape[1:-1]) - - def get_exp_cycles(self): - # (Channels * kernel * kernel) / PE * odim * odim * batch_size - ifm_ch = self.get_nodeattr("Channels") - pe = self.get_nodeattr("PE") - k = self.get_nodeattr("KernelSize") - k_prod = int(np.prod(k)) - odims = self.get_nodeattr("OutImgDims") - batch_size = self.get_nodeattr("BatchSize") - exp_cycles = ((ifm_ch * k_prod) / pe) * np.prod(odims) * batch_size - return int(exp_cycles) - - def get_instream_width(self, ind=0): - dt_bits = self.get_input_datatype().bitwidth() - pe = self.get_nodeattr("PE") - in_width = int(dt_bits * pe) - return in_width - - def get_outstream_width(self, ind=0): - dt_bits = self.get_output_datatype().bitwidth() - pe = self.get_nodeattr("PE") - out_width = int(dt_bits * pe) - return out_width - - def make_shape_compatible_op(self, model): - exp_ishape = self.get_normal_input_shape() - oshape = self.get_normal_output_shape() - ishape = tuple(model.get_tensor_shape(self.onnx_node.input[0])) - assert ishape == exp_ishape, "Unexpected input shape for Pool_Batch." - return super().make_const_shape_op(oshape) - - def infer_node_datatype(self, model): - node = self.onnx_node - # data type stays the same - dtype = self.get_output_datatype() - model.set_tensor_datatype(node.output[0], dtype) - - def verify_node(self): - info_messages = [] - # verify that "backend" is set to "fpgadataflow" - backend_value = self.get_nodeattr("backend") - if backend_value == "fpgadataflow": - info_messages.append("Attribute backend is set correctly") - else: - info_messages.append('Attribute backend should be set to "fpgadataflow"') - - # verify the number of inputs - if len(self.onnx_node.input) == 1: - info_messages.append("The number of inputs is correct") - else: - info_messages.append("""Pool_Batch needs 1 data input""") - - # check supported function - fnx = self.get_nodeattr("Function") - if fnx in ["MaxPool", "QuantAvgPool"]: - info_messages.append("Attribute Function contains a supported pool function") - else: - info_messages.append("Attribute Function contains an unsupported pool function") - return info_messages - def global_includes(self): self.code_gen_dict["$GLOBALS$"] = ['#include "activations.hpp"'] self.code_gen_dict["$GLOBALS$"] += ['#include "maxpool.h"'] diff --git a/src/finn/custom_op/fpgadataflow/pool.py b/src/finn/custom_op/fpgadataflow/pool.py new file mode 100644 index 0000000000..6a3962e7dd --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/pool.py @@ -0,0 +1,198 @@ +# Copyright (C) 2024, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import numpy as np +from qonnx.core.datatype import DataType + +from finn.custom_op.fpgadataflow.hwcustomop import HWCustomOp + + +class Pool(HWCustomOp): + """Abstraction layer for HW implementation of Pool. + Requires ConvolutionInputGenerator(depthwise == 1) to format its input + + Input shape (BatchSize,OutImgDim,OutImgDim,TotalKernelSize*Channels) + Output shape (BatchSize,OutImgDim,OutImgDim,Channels) + + Notes: + + * The input shape was chosen to be compatible with im2col (only true when there + is not folding). + * The actual data layout produced by the hlslib kernels is different + for depthwise ops. + + * depthwise SWG: (1, OFMDim, OFMDim, IFMChannels/PE, K, K, PE) + + Channels can be folded using PE (SIMD from the input perspective) + """ + + def get_nodeattr_types(self): + my_attrs = { + "Channels": ("i", True, 0), + "PE": ("i", True, 1), + "KernelSize": ("ints", True, []), + # Function: + # - MaxPool + # - QuantAvgPool + # TODO add support for AvgPool and AccPool + "Function": ("s", True, "", {"MaxPool", "QuantAvgPool"}), + "OutImgDims": ("ints", True, []), + # FINN DataTypes for inputs/outputs + "InputDataType": ("s", True, ""), + "OutputDataType": ("s", True, ""), + "AccumBits": ("i", False, 0), + "Size": ("i", False, 1), + "BatchSize": ("i", False, 1), + } + + my_attrs.update(super().get_nodeattr_types()) + return my_attrs + + def get_input_datatype(self, ind=0): + """Returns FINN DataType of input.""" + return DataType[self.get_nodeattr("InputDataType")] + + def get_output_datatype(self, ind=0): + """Returns FINN DataType of output.""" + fxn = self.get_nodeattr("Function") + odt = DataType[self.get_nodeattr("OutputDataType")] + + if fxn == "MaxPool": + # Same as input + idt = DataType[self.get_nodeattr("InputDataType")] + assert odt == idt, "In datatype must be equal to out datatype for Maxpool" + elif fxn == "QuantAvgPool": + idt = DataType[self.get_nodeattr("InputDataType")] + assert ( + idt.signed() == odt.signed() + ), """QuantAvgPool: Can't mix signed + and unsigned datatypes""" + else: + raise Exception("Pool_Batch doesn't currently support " + fxn) + + return odt + + def get_normal_input_shape(self, ind=0): + ifm_ch = self.get_nodeattr("Channels") + odims = self.get_nodeattr("OutImgDims") + batch_size = self.get_nodeattr("BatchSize") + k = self.get_nodeattr("KernelSize") + k_prod = int(np.prod(k)) + ishape = (batch_size, *odims, k_prod * ifm_ch) + return ishape + + def get_folded_input_shape(self, ind=0): + normal_ishape = list(self.get_normal_input_shape()) + ifm_ch = self.get_nodeattr("Channels") + pe = self.get_nodeattr("PE") + assert ifm_ch % pe == 0, "PE must divide input channels" + fold = int(normal_ishape[-1] / pe) + folded_ishape = normal_ishape[:-1] + [fold, pe] + return tuple(folded_ishape) + + def get_normal_output_shape(self, ind=0): + ofm_ch = self.get_nodeattr("Channels") + odims = self.get_nodeattr("OutImgDims") + batch_size = self.get_nodeattr("BatchSize") + oshape = (batch_size, *odims, ofm_ch) + return oshape + + def get_folded_output_shape(self, ind=0): + normal_oshape = list(self.get_normal_output_shape()) + ifm_ch = self.get_nodeattr("Channels") + pe = self.get_nodeattr("PE") + assert ifm_ch % pe == 0, "PE must divide input channels" + fold = int(ifm_ch / pe) + folded_oshape = normal_oshape[:-1] + [fold, pe] + return tuple(folded_oshape) + + def get_number_output_values(self): + folded_oshape = self.get_folded_output_shape() + return np.prod(folded_oshape[1:-1]) + + def get_exp_cycles(self): + # (Channels * kernel * kernel) / PE * odim * odim * batch_size + ifm_ch = self.get_nodeattr("Channels") + pe = self.get_nodeattr("PE") + k = self.get_nodeattr("KernelSize") + k_prod = int(np.prod(k)) + odims = self.get_nodeattr("OutImgDims") + batch_size = self.get_nodeattr("BatchSize") + exp_cycles = ((ifm_ch * k_prod) / pe) * np.prod(odims) * batch_size + return int(exp_cycles) + + def get_instream_width(self, ind=0): + dt_bits = self.get_input_datatype().bitwidth() + pe = self.get_nodeattr("PE") + in_width = int(dt_bits * pe) + return in_width + + def get_outstream_width(self, ind=0): + dt_bits = self.get_output_datatype().bitwidth() + pe = self.get_nodeattr("PE") + out_width = int(dt_bits * pe) + return out_width + + def make_shape_compatible_op(self, model): + exp_ishape = self.get_normal_input_shape() + oshape = self.get_normal_output_shape() + ishape = tuple(model.get_tensor_shape(self.onnx_node.input[0])) + assert ishape == exp_ishape, "Unexpected input shape for Pool_Batch." + return super().make_const_shape_op(oshape) + + def infer_node_datatype(self, model): + node = self.onnx_node + # data type stays the same + dtype = self.get_output_datatype() + model.set_tensor_datatype(node.output[0], dtype) + + def verify_node(self): + info_messages = [] + # verify that "backend" is set to "fpgadataflow" + backend_value = self.get_nodeattr("backend") + if backend_value == "fpgadataflow": + info_messages.append("Attribute backend is set correctly") + else: + info_messages.append('Attribute backend should be set to "fpgadataflow"') + + # verify the number of inputs + if len(self.onnx_node.input) == 1: + info_messages.append("The number of inputs is correct") + else: + info_messages.append("""Pool_Batch needs 1 data input""") + + # check supported function + fnx = self.get_nodeattr("Function") + if fnx in ["MaxPool", "QuantAvgPool"]: + info_messages.append("Attribute Function contains a supported pool function") + else: + info_messages.append("Attribute Function contains an unsupported pool function") + return info_messages + + def execute_node(self, context, graph): + pass diff --git a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py index 28b7dba9cb..0d3350a06d 100644 --- a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py +++ b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py @@ -311,7 +311,7 @@ def apply(self, model): pass_1d = is_1d and (not is_bipolar) pass_2d = (not is_1d) and is_divisable if pass_1d or pass_2d: - # create equivalent StreamingMaxPool_Batch node + # create equivalent StreamingMaxPool node new_node = helper.make_node( "StreamingMaxPool", [mp_input], @@ -804,6 +804,192 @@ def apply(self, model): return (model, graph_modified) +class InferPool(Transformation): + """If kernel_shape > strides, replace Pool layer with with of Im2col + + pool(with kernel_shape == strides), plus Transpose layers to keep the original + data layout.""" + + def apply(self, model): + graph = model.graph + node_ind = 0 + graph_modified = False + for node in graph.node: + node_ind += 1 + if node.op_type in ["MaxPool", "QuantAvgPool2d", "MaxPoolNHWC"]: + node_input = node.input[0] + ishape = model.get_tensor_shape(node_input) + node_output = node.output[0] + idt = model.get_tensor_datatype(node_input) + oshape = model.get_tensor_shape(node_output) + # only support 4D input tensors (1D convs need extra dummy dim) + if len(ishape) != 4: + continue + + # extract pool parameters + if node.op_type == "MaxPool": + kh, kw = list(get_by_name(node.attribute, "kernel_shape").ints) + sh, sw = list(get_by_name(node.attribute, "strides").ints) + dlayout = "NCHW" + elif node.op_type == "QuantAvgPool2d": + inst = getCustomOp(node) + # QuantAvgPool2d has a single scalar attribute + # for kernel size and stride (implicit square) + kh = kw = inst.get_nodeattr("kernel") + sh = sw = inst.get_nodeattr("stride") + dlayout = inst.get_nodeattr("data_layout") + elif node.op_type == "MaxPoolNHWC": + inst = getCustomOp(node) + kh, kw = inst.get_nodeattr("kernel_shape") + sh, sw = inst.get_nodeattr("strides") + dlayout = "NHWC" + try: + pad = list(get_by_name(node.attribute, "pads").ints) + except AttributeError: + pad = [0, 0, 0, 0] + + if not idt.is_integer(): + continue + + if (kh < sh) or (kw < sw): + # TODO check/implement swg support + continue + + odt = model.get_tensor_datatype(node_output) + + if dlayout == "NCHW": + _, ifm_ch, ifm_h, ifm_w = ishape + _, ofm_ch, ofm_h, ofm_w = oshape + elif dlayout == "NHWC": + _, ifm_h, ifm_w, ifm_ch = ishape + _, ofm_h, ofm_w, ofm_ch = oshape + else: + raise Exception("Unknown dlayout: " + str(dlayout)) + + # if data layout NCHW, we need transpose nodes surrounding + # the hls layer + if dlayout == "NCHW": + # create new intermediate values + inp_trans_out = helper.make_tensor_value_info( + model.make_new_valueinfo_name(), + TensorProto.FLOAT, + (1, ifm_h, ifm_w, ifm_ch), # NHWC + ) + graph.value_info.append(inp_trans_out) + inp_trans_out = inp_trans_out.name + model.set_tensor_datatype(inp_trans_out, idt) + + pool_output = helper.make_tensor_value_info( + model.make_new_valueinfo_name(), + TensorProto.FLOAT, + (1, ofm_h, ofm_w, ofm_ch), + ) + graph.value_info.append(pool_output) + pool_output = pool_output.name + + im2col_out = helper.make_tensor_value_info( + model.make_new_valueinfo_name(), + TensorProto.FLOAT, + (1, ofm_h, ofm_w, ifm_ch * kh * kw), + ) + graph.value_info.append(im2col_out) + im2col_out = im2col_out.name + model.set_tensor_datatype(im2col_out, idt) + + # create new nodes + if dlayout == "NCHW": + # NCHW -> NHWC + inp_trans_node = helper.make_node( + "Transpose", [node_input], [inp_trans_out], perm=[0, 2, 3, 1] + ) + im2col_in = inp_trans_out + else: + im2col_in = node_input + pool_output = node_output + + accum_bits = 0 + pool_size_param = 0 # will be overridden if neededs + pad_value = 0 + if node.op_type in ["MaxPool", "MaxPoolNHWC"]: + pool_fxn = "MaxPool" + odt = idt + pad_value = idt.min() + elif node.op_type == "QuantAvgPool2d": + assert odt.is_integer(), """Output data type for QuantAvgPool2d + needs to be integer""" + assert all(x == 0 for x in pad), "Padding is not supported for QuantAvgPool2d" + inst = getCustomOp(node) + pool_fxn = "QuantAvgPool" + pool_size_param = inst.get_shifts() + accum_bits = inst.get_accum_size() + + else: + raise Exception( + "pad_value and pool_fxn not configured for {}".format(node.op_type) + ) + + # format input tensor + im2col_node = helper.make_node( + "Im2Col", + [im2col_in], + [im2col_out], + domain="qonnx.custom_op.general", + stride=[sh, sw], + kernel_size=[kh, kw], + pad_amount=pad, + pad_value=pad_value, + depthwise=1, + input_shape="(1,{},{},{})".format(ifm_h, ifm_w, ifm_ch), + name="Im2Col_" + node.name, + ) + + # Warning PE has to be equal to ifm_ch until Im2Col is replaced by + # ConvolutionInputGenerator with depthwise=1. + # For other settings the output will be incorrect due to incorrect input + # data layout + pool_node = helper.make_node( + "Pool", + [im2col_out], + [pool_output], + domain="finn.custom_op.fpgadataflow", + backend="fpgadataflow", + InputDataType=idt.name, + OutputDataType=odt.name, + Channels=ifm_ch, + PE=ifm_ch, + KernelSize=[kh, kw], + Function=pool_fxn, + OutImgDims=[ofm_h, ofm_w], + AccumBits=accum_bits, + Size=pool_size_param, + BatchSize=1, + name="Pool_" + node.name, + ) + + if dlayout == "NCHW": + # NHWC -> NCHW + out_trans_node = helper.make_node( + "Transpose", [pool_output], [node_output], perm=[0, 3, 1, 2] + ) + + # insert nodes where the conv is to preserve topological ordering + if dlayout == "NCHW": + graph.node.insert(node_ind, inp_trans_node) + graph.node.insert(node_ind + 1, im2col_node) + graph.node.insert(node_ind + 2, pool_node) + graph.node.insert(node_ind + 3, out_trans_node) + else: + graph.node.insert(node_ind, im2col_node) + graph.node.insert(node_ind + 1, pool_node) + # remove old node + graph.node.remove(node) + graph_modified = True + + if graph_modified: + model = model.transform(InferShapes()) + model = model.transform(InferDataTypes()) + return (model, graph_modified) + + class InferLookupLayer(Transformation): """Convert Gather nodes with constant op0 into Lookup HW layers.""" diff --git a/src/finn/transformation/fpgadataflow/specialize_layers.py b/src/finn/transformation/fpgadataflow/specialize_layers.py index 6c1def628f..31da3756d3 100644 --- a/src/finn/transformation/fpgadataflow/specialize_layers.py +++ b/src/finn/transformation/fpgadataflow/specialize_layers.py @@ -166,23 +166,26 @@ def _swg_hls_possible(node): # can only be used for square inputs # and no dilation swg = getCustomOp(node) - # extract all attributes to check - k = swg.get_nodeattr("ConvKernelDim") - ifm_dim = swg.get_nodeattr("IFMDim") - ofm_dim = swg.get_nodeattr("OFMDim") - s = swg.get_nodeattr("Stride") - d = swg.get_nodeattr("Dilation") - # check if square and dilation=1 - if ( - k[0] == k[1] - and ifm_dim[0] == ifm_dim[1] - and ofm_dim[0] == ofm_dim[1] - and s[0] == s[1] - and d[0] == d[1] == 1 - ): + if swg.get_nodeattr("is1D"): return True else: - return False + # extract all attributes to check + k = swg.get_nodeattr("ConvKernelDim") + ifm_dim = swg.get_nodeattr("IFMDim") + ofm_dim = swg.get_nodeattr("OFMDim") + s = swg.get_nodeattr("Stride") + d = swg.get_nodeattr("Dilation") + # check if square and dilation=1 + if ( + k[0] == k[1] + and ifm_dim[0] == ifm_dim[1] + and ofm_dim[0] == ofm_dim[1] + and s[0] == s[1] + and d[0] == d[1] == 1 + ): + return True + else: + return False class SpecializeLayers(Transformation): diff --git a/tests/fpgadataflow/test_convert_to_hls_pool_batch.py b/tests/fpgadataflow/test_convert_to_hw_pool_batch.py similarity index 88% rename from tests/fpgadataflow/test_convert_to_hls_pool_batch.py rename to tests/fpgadataflow/test_convert_to_hw_pool_batch.py index 417b4fbae2..442f0a913f 100644 --- a/tests/fpgadataflow/test_convert_to_hls_pool_batch.py +++ b/tests/fpgadataflow/test_convert_to_hw_pool_batch.py @@ -1,4 +1,4 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -38,7 +38,7 @@ from qonnx.util.basic import gen_finn_dt_tensor, qonnx_make_model import finn.core.onnx_exec as oxe -import finn.transformation.fpgadataflow.convert_to_hls_layers as to_hls +import finn.transformation.fpgadataflow.convert_to_hw_layers as to_hw from finn.analysis.fpgadataflow.exp_cycles_per_layer import exp_cycles_per_layer from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP @@ -46,6 +46,7 @@ from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers def make_single_maxpool_modelwrapper(k, stride, pad, ifm_ch, ifm_dim, ofm_dim, idt, use_1d=False): @@ -133,7 +134,7 @@ def prepare_inputs(input_tensor): @pytest.mark.fpgadataflow @pytest.mark.slow @pytest.mark.vivado -def test_convert_to_hls_pool_batch(idt, odt, pool_config, ifm_ch, pe, op_type, exec_mode): +def test_convert_to_hw_pool(idt, odt, pool_config, ifm_ch, pe, op_type, exec_mode): k, stride, pad, ifm_dim = pool_config if ifm_ch % pe != 0: @@ -156,10 +157,6 @@ def test_convert_to_hls_pool_batch(idt, odt, pool_config, ifm_ch, pe, op_type, e # prepare input data input_dict = prepare_inputs(x) if op_type == "MaxPool": - # if idt.signed(): - # pytest.skip("""No support for signed input (see accu initialization - # in Pool_batch HLSLIB function). Skipping""") - if idt != odt: pytest.skip("Skipping Maxpool with idt != odt") @@ -178,16 +175,23 @@ def test_convert_to_hls_pool_batch(idt, odt, pool_config, ifm_ch, pe, op_type, e y_expected = oxe.execute_onnx(model, input_dict)["outp"] - new_model = model.transform(to_hls.InferPool_Batch()) + new_model = model.transform(to_hw.InferPool()) new_model = new_model.transform(GiveUniqueNodeNames()) + new_model = new_model.transform(to_hw.InferConvInpGen()) + # to test cppsim, set preferred_impl_style for swg to hls + inst = getCustomOp(new_model.get_nodes_by_op_type("ConvolutionInputGenerator")[0]) + inst.set_nodeattr("preferred_impl_style", "hls") + if pad != 0: + inst = getCustomOp(new_model.get_nodes_by_op_type("FMPadding")[0]) + inst.set_nodeattr("preferred_impl_style", "hls") + new_model = new_model.transform(SpecializeLayers()) - new_model = new_model.transform(to_hls.InferConvInpGen()) # Folding for n in new_model.graph.node: if n.op_type.startswith("ConvolutionInputGenerator"): inst = getCustomOp(n) inst.set_nodeattr("SIMD", pe) - elif n.op_type == "Pool_Batch": + elif n.op_type.startswith("Pool"): inst = getCustomOp(n) inst.set_nodeattr("PE", pe) @@ -196,14 +200,14 @@ def test_convert_to_hls_pool_batch(idt, odt, pool_config, ifm_ch, pe, op_type, e assert len(new_model.graph.node) == 4 assert new_model.graph.node[0].op_type == "Transpose" assert new_model.graph.node[1].op_type.startswith("ConvolutionInputGenerator") - assert new_model.graph.node[2].op_type == "Pool_Batch" + assert new_model.graph.node[2].op_type.startswith("Pool") assert new_model.graph.node[3].op_type == "Transpose" else: assert len(new_model.graph.node) == 5 assert new_model.graph.node[0].op_type == "Transpose" - assert new_model.graph.node[1].op_type == "FMPadding_Batch" + assert new_model.graph.node[1].op_type.startswith("FMPadding") assert new_model.graph.node[2].op_type.startswith("ConvolutionInputGenerator") - assert new_model.graph.node[3].op_type == "Pool_Batch" + assert new_model.graph.node[3].op_type.startswith("Pool") assert new_model.graph.node[4].op_type == "Transpose" else: # not currently converted to HLS, node stays as-is @@ -230,7 +234,7 @@ def test_convert_to_hls_pool_batch(idt, odt, pool_config, ifm_ch, pe, op_type, e assert (y_produced == y_expected).all() if exec_mode == "rtlsim": - node = new_model.get_nodes_by_op_type("Pool_Batch")[0] + node = new_model.get_nodes_by_op_type("Pool_hls")[0] inst = getCustomOp(node) cycles_rtlsim = inst.get_nodeattr("cycles_rtlsim") exp_cycles_dict = new_model.analysis(exp_cycles_per_layer) From 6519986b2ce7ae574f55d97b4597d6617fab1d03 Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 19 Jan 2024 16:19:51 +0000 Subject: [PATCH 397/665] [CustomOp] Initial draft of Concat layer in new class hierarchy --- src/finn/custom_op/fpgadataflow/__init__.py | 2 +- src/finn/custom_op/fpgadataflow/concat.py | 257 +-------------- .../custom_op/fpgadataflow/hls/__init__.py | 2 + .../custom_op/fpgadataflow/hls/concat_hls.py | 295 ++++++++++++++++++ .../fpgadataflow/convert_to_hw_layers.py | 62 +++- .../fpgadataflow/test_fpgadataflow_concat.py | 16 +- 6 files changed, 381 insertions(+), 253 deletions(-) create mode 100644 src/finn/custom_op/fpgadataflow/hls/concat_hls.py diff --git a/src/finn/custom_op/fpgadataflow/__init__.py b/src/finn/custom_op/fpgadataflow/__init__.py index cc496ddf2c..476489a26e 100644 --- a/src/finn/custom_op/fpgadataflow/__init__.py +++ b/src/finn/custom_op/fpgadataflow/__init__.py @@ -70,7 +70,6 @@ custom_op["VectorVectorActivation"] = VectorVectorActivation custom_op["IODMA"] = IODMA custom_op["StreamingDataflowPartition"] = StreamingDataflowPartition -custom_op["StreamingConcat"] = StreamingConcat custom_op["CheckSum"] = CheckSum custom_op["FMPadding"] = FMPadding @@ -83,6 +82,7 @@ custom_op["LabelSelect"] = LabelSelect custom_op["Lookup"] = Lookup custom_op["Pool"] = Pool +custom_op["StreamingConcat"] = StreamingConcat custom_op["StreamingDataWidthConverter"] = StreamingDataWidthConverter custom_op["StreamingEltwise"] = StreamingEltwise custom_op["StreamingMaxPool"] = StreamingMaxPool diff --git a/src/finn/custom_op/fpgadataflow/concat.py b/src/finn/custom_op/fpgadataflow/concat.py index 8c24dadbeb..210b6b7fdd 100644 --- a/src/finn/custom_op/fpgadataflow/concat.py +++ b/src/finn/custom_op/fpgadataflow/concat.py @@ -1,4 +1,5 @@ # Copyright (c) 2021, Xilinx +# Copyright (C) 2023, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -27,16 +28,14 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import numpy as np -import os from qonnx.core.datatype import DataType from qonnx.util.basic import roundup_to_integer_multiple -from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp -from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy +from finn.custom_op.fpgadataflow.hwcustomop import HWCustomOp -class StreamingConcat(HLSCustomOp): - """Streaming concatenation node with dynamically generated HLS. +class StreamingConcat(HWCustomOp): + """Abstraction layer for HW implementation of Concat. Only supports concatenating along the last axis.""" def __init__(self, onnx_node, **kwargs): @@ -127,251 +126,13 @@ def get_number_output_values(self): def get_exp_cycles(self): return np.prod(self.get_folded_output_shape()[:-1]) - def generate_params(self, model, path): - elems_per_stream = self.get_nodeattr("ElemsPerStream") - inp_streams = [] - commands = [] - idt = self.get_input_datatype() - total_elems = self.get_total_elems() - total_bw = idt.bitwidth() * total_elems - for i, elems in enumerate(elems_per_stream): - bw = idt.bitwidth() * elems - inp_stream = "hls::stream > &in%d" % (bw, i) - inp_streams.append(inp_stream) - cmd = "in%d.read()" % i - commands.append(cmd) - out_stream = "hls::stream > &out" % (total_bw) - inp_streams.append(out_stream) - - impl_hls_code = [] - impl_hls_code.append("void StreamingConcat(") - impl_hls_code.append(",".join(inp_streams)) - impl_hls_code.append(", unsigned int numReps) {") - impl_hls_code.append("for(unsigned int i = 0; i < numReps; i++) {") - impl_hls_code.append("#pragma HLS PIPELINE II=1") - impl_hls_code.append("ap_uint<%d> out_elem;" % total_bw) - # FIXME: the order of streams for concatenation works out differently - # for cppsim vs rtlsim, addressed via reversing the order of commands - # for now - impl_hls_code.append("#ifdef __SYNTHESIS__") - impl_hls_code.append("out_elem = (" + ",".join(commands[::-1]) + ");") - impl_hls_code.append("#else") - impl_hls_code.append("out_elem = (" + ",".join(commands) + ");") - impl_hls_code.append("#endif") - impl_hls_code.append("out.write(out_elem);") - impl_hls_code.append("}") - impl_hls_code.append("}") - impl_hls_code = "\n".join(impl_hls_code) - - impl_filename = "{}/concat_impl.hpp".format(path) - f_impl = open(impl_filename, "w") - f_impl.write(impl_hls_code) - f_impl.close() - def execute_node(self, context, graph): - mode = self.get_nodeattr("exec_mode") node = self.onnx_node - n_inps = len(self.onnx_node.input) - ishapes = [self.get_normal_input_shape(x) for x in range(n_inps)] - folded_ishapes = [self.get_folded_input_shape(x) for x in range(n_inps)] - exp_oshape = self.get_normal_output_shape() - folded_oshape = self.get_folded_output_shape() - export_idt = self.get_input_datatype() - - if mode == "cppsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - elif mode == "rtlsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) - - for i in range(n_inps): - inp = context[node.input[i]] - assert str(inp.dtype) == "float32", "Input datatype is not float32" - assert inp.shape == ishapes[i], "Input shape mismatch for " + node.input[i] - # reshape input into folded form - inp = inp.reshape(folded_ishapes[i]) - # make copy before saving array - reshaped_input = inp.copy() - np.save(os.path.join(code_gen_dir, "input_%d.npy" % i), reshaped_input) - - if mode == "cppsim": - # execute the precompiled model - super().exec_precompiled_singlenode_model() - # load output npy file - super().npy_to_dynamic_output(context) - assert ( - context[node.output[0]].shape == folded_oshape - ), "cppsim did not produce expected folded output shape" - context[node.output[0]] = context[node.output[0]].reshape(*exp_oshape) - elif mode == "rtlsim": - sim = self.get_rtlsim() - io_dict = {"inputs": {}, "outputs": {"out": []}} - for i in range(n_inps): - nbits = self.get_instream_width(i) - rtlsim_inp = npy_to_rtlsim_input( - "%s/input_%d.npy" % (code_gen_dir, i), - export_idt, - nbits, - reverse_inner=True, - ) - io_dict["inputs"]["in%d" % i] = rtlsim_inp - super().reset_rtlsim(sim) - super().toggle_clk(sim) - - self.rtlsim_multi_io(sim, io_dict) - rtlsim_output = io_dict["outputs"]["out"] - odt = self.get_output_datatype() - target_bits = odt.bitwidth() - packed_bits = self.get_outstream_width() - out_npy_path = "{}/output.npy".format(code_gen_dir) - out_shape = self.get_folded_output_shape() - rtlsim_output_to_npy( - rtlsim_output, - out_npy_path, - odt, - out_shape, - packed_bits, - target_bits, - reverse_inner=True, - ) - # load and reshape output - output = np.load(out_npy_path) - output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) - context[node.output[0]] = output - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) - - assert ( - context[node.output[0]].shape == exp_oshape - ), """Output shape doesn't match expected shape.""" - - def global_includes(self): - self.code_gen_dict["$GLOBALS$"] = ['#include "concat_impl.hpp"'] - - def defines(self, var): - num_reps = self.get_nodeattr("numInputVectors") - num_reps = np.prod(num_reps) - self.code_gen_dict["$DEFINES$"] = ["#define NumReps %d" % num_reps] - - def read_npy_data(self): - n_inputs = self.get_n_inputs() - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - npy_type = "float" - self.code_gen_dict["$READNPYDATA$"] = [] - idt = self.get_input_datatype() - idt_bw = idt.bitwidth() - elem_hls_type = idt.get_hls_datatype_str() - elem_bits = idt_bw - for i in range(n_inputs): - packed_bits = self.get_instream_width(i) - packed_hls_type = "ap_uint<%d>" % packed_bits - npy_in = "%s/input_%d.npy" % (code_gen_dir, i) - self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in%d_%s);' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - npy_in, - i, - self.hls_sname(), - ) - ) - - def strm_decl(self): - self.code_gen_dict["$STREAMDECLARATIONS$"] = [] - n_inputs = self.get_n_inputs() - for i in range(n_inputs): - packed_bits = self.get_instream_width(i) - packed_hls_type = "ap_uint<%d>" % packed_bits - stream_name = "in%d_%s" % (i, self.hls_sname()) - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream<%s> %s ("%s");' % (packed_hls_type, stream_name, stream_name) - ) - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out_{} ("out_{}");'.format( - self.get_outstream_width(), self.hls_sname(), self.hls_sname() - ) - ) - - def docompute(self): - self.code_gen_dict["$DOCOMPUTE$"] = [] - n_inputs = self.get_n_inputs() - in_streams = [] - for i in range(n_inputs): - in_streams.append("in%d_%s" % (i, self.hls_sname())) - in_stream_names = ",".join(in_streams) - comp_call = "StreamingConcat(%s, out_%s, NumReps);" % ( - in_stream_names, - self.hls_sname(), - ) - self.code_gen_dict["$DOCOMPUTE$"] = [comp_call] - - def dataoutstrm(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_output_datatype() - elem_bits = dtype.bitwidth() - packed_bits = self.get_outstream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_out = "%s/output.npy" % code_gen_dir - oshape = self.get_folded_output_shape() - oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") - - self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - self.hls_sname(), - oshape_cpp_str, - npy_out, - ) - ] - - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - - def blackboxfunction(self): - n_inputs = self.get_n_inputs() - in_streams = [] - for i in range(n_inputs): - iwidth = self.get_instream_width(i) - in_streams.append("hls::stream> &in%d_%s" % (iwidth, i, self.hls_sname())) - in_streams = ",".join(in_streams) - total_width = self.get_input_datatype().bitwidth() * self.get_total_elems() - out_stream = "hls::stream> &out_%s" % ( - total_width, - self.hls_sname(), - ) - blackbox_hls = "void %s(%s, %s)" % (self.onnx_node.name, in_streams, out_stream) - self.code_gen_dict["$BLACKBOXFUNCTION$"] = [blackbox_hls] - - def pragmas(self): - n_inputs = self.get_n_inputs() - pragmas = [] - for i in range(n_inputs): - pragmas.append("#pragma HLS INTERFACE axis port=in%d_%s" % (i, self.hls_sname())) - self.code_gen_dict["$PRAGMAS$"] = pragmas - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() - ) - self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") + inp_values = [] + for inp in node.input: + inp_values.append(context[inp]) + result = np.concatenate(inp_values, axis=-1) + context[node.output[0]] = result def get_instream_width_padded(self, ind=0): in_width = self.get_instream_width(ind) diff --git a/src/finn/custom_op/fpgadataflow/hls/__init__.py b/src/finn/custom_op/fpgadataflow/hls/__init__.py index 7ae7ffa34d..b4aae1ef3a 100644 --- a/src/finn/custom_op/fpgadataflow/hls/__init__.py +++ b/src/finn/custom_op/fpgadataflow/hls/__init__.py @@ -28,6 +28,7 @@ from finn.custom_op.fpgadataflow.hls.addstreams_hls import AddStreams_hls from finn.custom_op.fpgadataflow.hls.channelwise_op_hls import ChannelwiseOp_hls +from finn.custom_op.fpgadataflow.hls.concat_hls import StreamingConcat_hls from finn.custom_op.fpgadataflow.hls.convolutioninputgenerator_hls import ( ConvolutionInputGenerator_hls, ) @@ -59,6 +60,7 @@ custom_op["LabelSelect_hls"] = LabelSelect_hls custom_op["Lookup_hls"] = Lookup_hls custom_op["Pool_hls"] = Pool_hls +custom_op["StreamingConcat_hls"] = StreamingConcat_hls custom_op["StreamingEltwise_hls"] = StreamingEltwise_hls custom_op["StreamingDataWidthConverter_hls"] = StreamingDataWidthConverter_hls custom_op["StreamingMaxPool_hls"] = StreamingMaxPool_hls diff --git a/src/finn/custom_op/fpgadataflow/hls/concat_hls.py b/src/finn/custom_op/fpgadataflow/hls/concat_hls.py new file mode 100644 index 0000000000..f608b343f6 --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/hls/concat_hls.py @@ -0,0 +1,295 @@ +# Copyright (c) 2021, Xilinx +# Copyright (C) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import numpy as np +import os + +from finn.custom_op.fpgadataflow.concat import StreamingConcat +from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend +from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy + + +class StreamingConcat_hls(StreamingConcat, HLSBackend): + """Streaming concatenation node with dynamically generated HLS. + Only supports concatenating along the last axis.""" + + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) + + def get_nodeattr_types(self): + my_attrs = {} + my_attrs.update(StreamingConcat.get_nodeattr_types(self)) + my_attrs.update(HLSBackend.get_nodeattr_types(self)) + return my_attrs + + def generate_params(self, model, path): + elems_per_stream = self.get_nodeattr("ElemsPerStream") + inp_streams = [] + commands = [] + idt = self.get_input_datatype() + total_elems = self.get_total_elems() + total_bw = idt.bitwidth() * total_elems + for i, elems in enumerate(elems_per_stream): + bw = idt.bitwidth() * elems + inp_stream = "hls::stream > &in%d" % (bw, i) + inp_streams.append(inp_stream) + cmd = "in%d.read()" % i + commands.append(cmd) + out_stream = "hls::stream > &out" % (total_bw) + inp_streams.append(out_stream) + + impl_hls_code = [] + impl_hls_code.append("void StreamingConcat(") + impl_hls_code.append(",".join(inp_streams)) + impl_hls_code.append(", unsigned int numReps) {") + impl_hls_code.append("for(unsigned int i = 0; i < numReps; i++) {") + impl_hls_code.append("#pragma HLS PIPELINE II=1") + impl_hls_code.append("ap_uint<%d> out_elem;" % total_bw) + # FIXME: the order of streams for concatenation works out differently + # for cppsim vs rtlsim, addressed via reversing the order of commands + # for now + impl_hls_code.append("#ifdef __SYNTHESIS__") + impl_hls_code.append("out_elem = (" + ",".join(commands[::-1]) + ");") + impl_hls_code.append("#else") + impl_hls_code.append("out_elem = (" + ",".join(commands) + ");") + impl_hls_code.append("#endif") + impl_hls_code.append("out.write(out_elem);") + impl_hls_code.append("}") + impl_hls_code.append("}") + impl_hls_code = "\n".join(impl_hls_code) + + impl_filename = "{}/concat_impl.hpp".format(path) + f_impl = open(impl_filename, "w") + f_impl.write(impl_hls_code) + f_impl.close() + + def execute_node(self, context, graph): + mode = self.get_nodeattr("exec_mode") + node = self.onnx_node + n_inps = len(self.onnx_node.input) + ishapes = [self.get_normal_input_shape(x) for x in range(n_inps)] + folded_ishapes = [self.get_folded_input_shape(x) for x in range(n_inps)] + exp_oshape = self.get_normal_output_shape() + folded_oshape = self.get_folded_output_shape() + export_idt = self.get_input_datatype() + + if mode == "cppsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + elif mode == "rtlsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + + for i in range(n_inps): + inp = context[node.input[i]] + assert str(inp.dtype) == "float32", "Input datatype is not float32" + assert inp.shape == ishapes[i], "Input shape mismatch for " + node.input[i] + # reshape input into folded form + inp = inp.reshape(folded_ishapes[i]) + # make copy before saving array + reshaped_input = inp.copy() + np.save(os.path.join(code_gen_dir, "input_%d.npy" % i), reshaped_input) + + if mode == "cppsim": + # execute the precompiled model + super().exec_precompiled_singlenode_model() + # load output npy file + super().npy_to_dynamic_output(context) + assert ( + context[node.output[0]].shape == folded_oshape + ), "cppsim did not produce expected folded output shape" + context[node.output[0]] = context[node.output[0]].reshape(*exp_oshape) + elif mode == "rtlsim": + sim = self.get_rtlsim() + io_dict = {"inputs": {}, "outputs": {"out": []}} + for i in range(n_inps): + nbits = self.get_instream_width(i) + rtlsim_inp = npy_to_rtlsim_input( + "%s/input_%d.npy" % (code_gen_dir, i), + export_idt, + nbits, + reverse_inner=True, + ) + io_dict["inputs"]["in%d" % i] = rtlsim_inp + super().reset_rtlsim(sim) + super().toggle_clk(sim) + + self.rtlsim_multi_io(sim, io_dict) + rtlsim_output = io_dict["outputs"]["out"] + odt = self.get_output_datatype() + target_bits = odt.bitwidth() + packed_bits = self.get_outstream_width() + out_npy_path = "{}/output.npy".format(code_gen_dir) + out_shape = self.get_folded_output_shape() + rtlsim_output_to_npy( + rtlsim_output, + out_npy_path, + odt, + out_shape, + packed_bits, + target_bits, + reverse_inner=True, + ) + # load and reshape output + output = np.load(out_npy_path) + output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) + context[node.output[0]] = output + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + + assert ( + context[node.output[0]].shape == exp_oshape + ), """Output shape doesn't match expected shape.""" + + def global_includes(self): + self.code_gen_dict["$GLOBALS$"] = ['#include "concat_impl.hpp"'] + + def defines(self, var): + num_reps = self.get_nodeattr("numInputVectors") + num_reps = np.prod(num_reps) + self.code_gen_dict["$DEFINES$"] = ["#define NumReps %d" % num_reps] + + def read_npy_data(self): + n_inputs = self.get_n_inputs() + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + npy_type = "float" + self.code_gen_dict["$READNPYDATA$"] = [] + idt = self.get_input_datatype() + idt_bw = idt.bitwidth() + elem_hls_type = idt.get_hls_datatype_str() + elem_bits = idt_bw + for i in range(n_inputs): + packed_bits = self.get_instream_width(i) + packed_hls_type = "ap_uint<%d>" % packed_bits + npy_in = "%s/input_%d.npy" % (code_gen_dir, i) + self.code_gen_dict["$READNPYDATA$"].append( + 'npy2apintstream<%s, %s, %d, %s>("%s", in%d_%s);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + i, + self.hls_sname(), + ) + ) + + def strm_decl(self): + self.code_gen_dict["$STREAMDECLARATIONS$"] = [] + n_inputs = self.get_n_inputs() + for i in range(n_inputs): + packed_bits = self.get_instream_width(i) + packed_hls_type = "ap_uint<%d>" % packed_bits + stream_name = "in%d_%s" % (i, self.hls_sname()) + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream<%s> %s ("%s");' % (packed_hls_type, stream_name, stream_name) + ) + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> out_{} ("out_{}");'.format( + self.get_outstream_width(), self.hls_sname(), self.hls_sname() + ) + ) + + def docompute(self): + self.code_gen_dict["$DOCOMPUTE$"] = [] + n_inputs = self.get_n_inputs() + in_streams = [] + for i in range(n_inputs): + in_streams.append("in%d_%s" % (i, self.hls_sname())) + in_stream_names = ",".join(in_streams) + comp_call = "StreamingConcat(%s, out_%s, NumReps);" % ( + in_stream_names, + self.hls_sname(), + ) + self.code_gen_dict["$DOCOMPUTE$"] = [comp_call] + + def dataoutstrm(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_output_datatype() + elem_bits = dtype.bitwidth() + packed_bits = self.get_outstream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "float" + npy_out = "%s/output.npy" % code_gen_dir + oshape = self.get_folded_output_shape() + oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") + + self.code_gen_dict["$DATAOUTSTREAM$"] = [ + 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + self.hls_sname(), + oshape_cpp_str, + npy_out, + ) + ] + + def save_as_npy(self): + self.code_gen_dict["$SAVEASCNPY$"] = [] + + def blackboxfunction(self): + n_inputs = self.get_n_inputs() + in_streams = [] + for i in range(n_inputs): + iwidth = self.get_instream_width(i) + in_streams.append("hls::stream> &in%d_%s" % (iwidth, i, self.hls_sname())) + in_streams = ",".join(in_streams) + total_width = self.get_input_datatype().bitwidth() * self.get_total_elems() + out_stream = "hls::stream> &out_%s" % ( + total_width, + self.hls_sname(), + ) + blackbox_hls = "void %s(%s, %s)" % (self.onnx_node.name, in_streams, out_stream) + self.code_gen_dict["$BLACKBOXFUNCTION$"] = [blackbox_hls] + + def pragmas(self): + n_inputs = self.get_n_inputs() + pragmas = [] + for i in range(n_inputs): + pragmas.append("#pragma HLS INTERFACE axis port=in%d_%s" % (i, self.hls_sname())) + self.code_gen_dict["$PRAGMAS$"] = pragmas + self.code_gen_dict["$PRAGMAS$"].append( + "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() + ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") diff --git a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py index 0d3350a06d..2b8433e59c 100644 --- a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py +++ b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py @@ -866,7 +866,7 @@ def apply(self, model): raise Exception("Unknown dlayout: " + str(dlayout)) # if data layout NCHW, we need transpose nodes surrounding - # the hls layer + # the hw layer if dlayout == "NCHW": # create new intermediate values inp_trans_out = helper.make_tensor_value_info( @@ -1043,6 +1043,66 @@ def apply(self, model): return (model, graph_modified) +class InferConcatLayer(Transformation): + """Convert suitable Concat nodes (operating on last/-1 axis) + into StreamingConcat HW layers.""" + + def apply(self, model): + graph = model.graph + node_ind = 0 + graph_modified = False + for node in graph.node: + node_ind += 1 + if node.op_type == "Concat": + ishape = model.get_tensor_shape(node.input[0]) + axis = get_by_name(node.attribute, "axis") + if (axis is None) or (ishape is None): + continue + axis = axis.i + last_axis = len(ishape) - 1 + # skip conversion if not using last axis + if (axis != -1) and (axis != last_axis): + continue + # check datatype coherence + dt0 = model.get_tensor_datatype(node.input[0]) + if dt0 is None: + continue + dt_coherent = all([model.get_tensor_datatype(x) == dt0 for x in node.input]) + if not dt_coherent: + continue + # skip conversion if any inputs are static + all_static = all([model.get_initializer(x) is None for x in node.input]) + if not all_static: + continue + # skip conversion if inputs are not integers + if not dt0.is_integer(): + continue + # ready for conversion + elems_per_stream = [model.get_tensor_shape(x)[-1] for x in node.input] + inp_vec = list(model.get_tensor_shape(node.input[0])[:-1]) + new_node = helper.make_node( + "StreamingConcat", + node.input, + node.output, + domain="finn.custom_op.fpgadataflow", + backend="fpgadataflow", + name="Concat_" + node.name, + ElemsPerStream=elems_per_stream, + inputDataType=dt0.name, + numInputVectors=inp_vec, + inFIFODepths=[2] * len(node.input), + ) + graph.node.insert(node_ind, new_node) + # remove old node + graph.node.remove(node) + graph_modified = True + + if graph_modified: + model = model.transform(InferShapes()) + model = model.transform(InferDataTypes()) + return (model, graph_modified) + + class InferStreamingEltwise(Transformation): """Convert eltwise Sub or Sub -> Abs to StreamingEltwise layer with SubEltwise or AbsDiffEltwise op.""" diff --git a/tests/fpgadataflow/test_fpgadataflow_concat.py b/tests/fpgadataflow/test_fpgadataflow_concat.py index 2b2069a72b..b4d8a04a95 100644 --- a/tests/fpgadataflow/test_fpgadataflow_concat.py +++ b/tests/fpgadataflow/test_fpgadataflow_concat.py @@ -1,4 +1,5 @@ # Copyright (c) 2021, Xilinx +# Copyright (C) 2023, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -40,7 +41,7 @@ from finn.core.onnx_exec import execute_onnx from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim -from finn.transformation.fpgadataflow.convert_to_hls_layers import InferConcatLayer +from finn.transformation.fpgadataflow.convert_to_hw_layers import InferConcatLayer from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP from finn.transformation.fpgadataflow.insert_fifo import InsertFIFO @@ -48,6 +49,7 @@ from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers def make_concat_model(i_shapes, idt): @@ -90,10 +92,15 @@ def test_fpgadataflow_concat(exec_mode, idt): inp_dict[model.graph.input[i].name] = i_data[i] ret = execute_onnx(model, inp_dict) assert (ret[oname] == exp_out).all() - # call transformation to convert to HLS and verify conversion + # call transformation to convert to HW and verify conversion model = model.transform(InferConcatLayer()) assert model.graph.node[0].op_type == "StreamingConcat" assert model.graph.node[0].domain == "finn.custom_op.fpgadataflow" + ret = execute_onnx(model, inp_dict) + assert (ret[oname] == exp_out).all() + model = model.transform(SpecializeLayers()) + assert model.graph.node[0].op_type == "StreamingConcat_hls" + assert model.graph.node[0].domain == "finn.custom_op.fpgadataflow.hls" if exec_mode == "cppsim": model = model.transform(GiveUniqueNodeNames()) model = model.transform(PrepareCppSim()) @@ -130,10 +137,13 @@ def test_fpgadataflow_concat_stitchedip(): inp_dict[model.graph.input[i].name] = i_data[i] ret = execute_onnx(model, inp_dict) assert (ret[oname] == exp_out).all() - # call transformation to convert to HLS and verify conversion + # call transformation to convert to HW and verify conversion model = model.transform(InferConcatLayer()) assert model.graph.node[0].op_type == "StreamingConcat" assert model.graph.node[0].domain == "finn.custom_op.fpgadataflow" + model = model.transform(SpecializeLayers()) + assert model.graph.node[0].op_type == "StreamingConcat_hls" + assert model.graph.node[0].domain == "finn.custom_op.fpgadataflow.hls" model = model.transform(InsertFIFO(create_shallow_fifos=True)) model = model.transform(GiveUniqueNodeNames()) model = model.transform(PrepareIP(fpga_part, clk_ns)) From 1861a2086b36a341e0b0f9e366f01e8df753379f Mon Sep 17 00:00:00 2001 From: johnnoel Date: Tue, 23 Jan 2024 12:09:06 +0000 Subject: [PATCH 398/665] [CI] Add cleanup for ownership issues observed on zynq boards --- docker/jenkins/Jenkinsfile_HW | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/docker/jenkins/Jenkinsfile_HW b/docker/jenkins/Jenkinsfile_HW index 3436ec79e8..bd4180d83c 100644 --- a/docker/jenkins/Jenkinsfile_HW +++ b/docker/jenkins/Jenkinsfile_HW @@ -48,6 +48,7 @@ pipeline { post { always { stashResults("bnn_build_sanity", "${env.BOARD}") + cleanUpWorkspaceOwnership() } } } @@ -72,6 +73,7 @@ pipeline { post { always { stashResults("bnn_build_sanity", "${env.BOARD}") + cleanUpWorkspaceOwnership() } } } @@ -96,6 +98,7 @@ pipeline { post { always { stashResults("bnn_build_sanity", "${env.BOARD}") + cleanUpWorkspaceOwnership() } } } @@ -120,6 +123,7 @@ pipeline { post { always { stashResults("bnn_build_sanity", "${env.BOARD}") + cleanUpWorkspaceOwnership() } } } @@ -147,6 +151,7 @@ pipeline { post { always { stashResults("bnn_build_full", "${env.BOARD}") + cleanUpWorkspaceOwnership() } } } @@ -171,6 +176,7 @@ pipeline { post { always { stashResults("bnn_build_full", "${env.BOARD}") + cleanUpWorkspaceOwnership() } } } @@ -195,6 +201,7 @@ pipeline { post { always { stashResults("bnn_build_full", "${env.BOARD}") + cleanUpWorkspaceOwnership() } } } @@ -219,6 +226,7 @@ pipeline { post { always { stashResults("bnn_build_full", "${env.BOARD}") + cleanUpWorkspaceOwnership() } } } @@ -371,4 +379,10 @@ void stashResults (String testType, String board) { echo "No results to stash" } } -} \ No newline at end of file +} + +void cleanUpWorkspaceOwnership () { + if (env.USER_CREDENTIALS) { + sh 'echo ${USER_CREDENTIALS_PSW} | sudo -S chown -R $(id -u):$(id -g) ${WORKSPACE}' + } +} From 4fc99b48d502523ac1e6c339f88647643eca27a2 Mon Sep 17 00:00:00 2001 From: johnnoel Date: Tue, 23 Jan 2024 14:56:55 +0000 Subject: [PATCH 399/665] [CI] Reboot Zynq nodes before HW testing --- docker/jenkins/Jenkinsfile_HW | 101 ++++++++++++++++++++++++++++++++-- 1 file changed, 97 insertions(+), 4 deletions(-) diff --git a/docker/jenkins/Jenkinsfile_HW b/docker/jenkins/Jenkinsfile_HW index bd4180d83c..cdc4cbce27 100644 --- a/docker/jenkins/Jenkinsfile_HW +++ b/docker/jenkins/Jenkinsfile_HW @@ -1,7 +1,96 @@ pipeline { agent none stages { - stage('Sanity & BNN end2end - Setup Hardware Tests') { + stage('Get node status') { + options { skipDefaultCheckout() } + agent { + label 'finn-build' + } + steps { + script { + // Check which boards are online before running HW tests + env.ALVEO_HOST_ONLINE = isNodeOnline('finn-u250') + env.PYNQ_ONLINE = isNodeOnline('finn-pynq') + env.ZCU104_ONLINE = isNodeOnline('finn-zcu104') + env.KV260_ONLINE = isNodeOnline('finn-kv260') + } + } + } + stage('Reboot Zynq platforms') { + parallel { + stage('Pynq-Z1') { + options { skipDefaultCheckout() } + when { + // beforeAgent set to 'true' to prevent an offline agent hanging the stage + beforeAgent true + expression { return (env.PYNQ_ONLINE == 'true') } + } + agent { + label 'finn-pynq' + } + environment { + BOARD = 'Pynq-Z1' + USER_CREDENTIALS = credentials('pynq-z1-credentials') + } + steps { + catchError(stageResult: 'FAILURE') { + restartZynqPlatform() + } + } + } + stage('ZCU104') { + options { skipDefaultCheckout() } + when { + // beforeAgent set to 'true' to prevent an offline agent hanging the stage + beforeAgent true + expression { return (env.ZCU104_ONLINE == 'true') } + } + agent { + label 'finn-zcu104' + } + environment { + BOARD = 'ZCU104' + USER_CREDENTIALS = credentials('pynq-z1-credentials') + } + steps { + catchError(stageResult: 'FAILURE') { + restartZynqPlatform() + } + } + } + stage('Kria KV260_SOM') { + options { skipDefaultCheckout() } + when { + // beforeAgent set to 'true' to prevent an offline agent hanging the stage + beforeAgent true + expression { return (env.KV260_ONLINE == 'true') } + } + agent { + label 'finn-kv260' + } + environment { + BOARD = 'KV260_SOM' + USER_CREDENTIALS = credentials('user-ubuntu-credentials') + } + steps { + catchError(stageResult: 'FAILURE') { + restartZynqPlatform() + } + } + } + } + } + stage('Wait for Nodes to reboot') { + options { skipDefaultCheckout() } + agent { + label 'finn-build' + } + steps { + sleep(time: 3, unit: 'MINUTES') + } + } + stage('Collect build information for HW testing') { + options { skipDefaultCheckout() } agent { label 'finn-build' } @@ -339,7 +428,7 @@ void stashBuildArtifacts(String testDir) { } } -String runTest(String testType, String board, String marker) { +void runTest(String testType, String board, String marker) { sh "mkdir -p ${testType}" dir("$testType") { // Clean any files from a previous run @@ -365,8 +454,6 @@ String runTest(String testType, String board, String marker) { } } } - - return "SUCCESS" } void stashResults (String testType, String board) { @@ -386,3 +473,9 @@ void cleanUpWorkspaceOwnership () { sh 'echo ${USER_CREDENTIALS_PSW} | sudo -S chown -R $(id -u):$(id -g) ${WORKSPACE}' } } + +void restartZynqPlatform () { + if (env.USER_CREDENTIALS) { + sh 'echo ${USER_CREDENTIALS_PSW} | sudo -S shutdown -r +1' + } +} From 0e66e63e935d26950be337483120c8d6542bb99a Mon Sep 17 00:00:00 2001 From: johnnoel Date: Tue, 23 Jan 2024 15:04:00 +0000 Subject: [PATCH 400/665] [CI] Run all Fstages in parallel to improve runtime --- docker/jenkins/Jenkinsfile | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/docker/jenkins/Jenkinsfile b/docker/jenkins/Jenkinsfile index bf4505cc3f..6d51fffd64 100644 --- a/docker/jenkins/Jenkinsfile +++ b/docker/jenkins/Jenkinsfile @@ -6,7 +6,7 @@ pipeline { booleanParam(name: 'end2end', defaultValue: false, description: 'Run end2end tests') } stages { - stage('Sanity Tests') { + stage('Run Tests') { parallel { stage('Sanity - Build Hardware') { when { @@ -76,7 +76,7 @@ pipeline { } } } - stage('Sanity - fpgadataflow Tests') { + stage('fpgadataflow Tests') { when { expression { params['fpgadataflow'] } } @@ -107,10 +107,6 @@ pipeline { } } } - } - } - stage('End2end - Build Hardware') { - parallel { stage('End2end') { when { expression { params['end2end'] } From dca978ff07a4647b5b403c022996a3265f3dd887 Mon Sep 17 00:00:00 2001 From: johnnoel Date: Tue, 23 Jan 2024 15:20:28 +0000 Subject: [PATCH 401/665] [CI] Define reboot wait time using env variable --- docker/jenkins/Jenkinsfile_HW | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docker/jenkins/Jenkinsfile_HW b/docker/jenkins/Jenkinsfile_HW index cdc4cbce27..bd438d888e 100644 --- a/docker/jenkins/Jenkinsfile_HW +++ b/docker/jenkins/Jenkinsfile_HW @@ -86,7 +86,7 @@ pipeline { label 'finn-build' } steps { - sleep(time: 3, unit: 'MINUTES') + sleep(time: "${env.REBOOT_SLEEP}", unit: 'MINUTES') } } stage('Collect build information for HW testing') { From 89bfc756b9029561664e6df34029482d89deca67 Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 23 Jan 2024 16:27:07 +0000 Subject: [PATCH 402/665] [CustomOp] Add execution fct to pool hw layer --- src/finn/custom_op/fpgadataflow/pool.py | 28 ++++++++++++++++++- .../test_convert_to_hw_pool_batch.py | 2 ++ 2 files changed, 29 insertions(+), 1 deletion(-) diff --git a/src/finn/custom_op/fpgadataflow/pool.py b/src/finn/custom_op/fpgadataflow/pool.py index 6a3962e7dd..35aee023b9 100644 --- a/src/finn/custom_op/fpgadataflow/pool.py +++ b/src/finn/custom_op/fpgadataflow/pool.py @@ -195,4 +195,30 @@ def verify_node(self): return info_messages def execute_node(self, context, graph): - pass + # simulate behavior with Python functionality + node = self.onnx_node + fnx = self.get_nodeattr("Function") + k = self.get_nodeattr("KernelSize") + ch = self.get_nodeattr("Channels") + k2 = k[0] * k[1] + + inp_values = context[node.input[0]] + ishape = inp_values.shape + # reshape array to apply max or avg function only on kernel + tmp_shape = tuple(list(ishape)[:-1] + [k2, ch]) + tmp_values = inp_values.reshape(tmp_shape) + if fnx == "MaxPool": + result = np.max(tmp_values, axis=3) + elif fnx == "QuantAvgPool": + # determine bits to shift + ibits = self.get_input_datatype().bitwidth() + obits = self.get_output_datatype().bitwidth() + max_value = 2**ibits - 1 + max_value = max_value * k2 + max_bit_width = int(max_value).bit_length() + shift_bits = max_bit_width - obits + shift_bits = shift_bits if shift_bits >= 0 else 0 + result = np.sum(tmp_values, axis=3) + result = np.right_shift(result.astype(int), shift_bits) + oshape = context[node.output[0]].shape + context[node.output[0]] = np.asarray(result, dtype=np.float32).reshape(oshape) diff --git a/tests/fpgadataflow/test_convert_to_hw_pool_batch.py b/tests/fpgadataflow/test_convert_to_hw_pool_batch.py index 442f0a913f..d532cf345e 100644 --- a/tests/fpgadataflow/test_convert_to_hw_pool_batch.py +++ b/tests/fpgadataflow/test_convert_to_hw_pool_batch.py @@ -184,6 +184,8 @@ def test_convert_to_hw_pool(idt, odt, pool_config, ifm_ch, pe, op_type, exec_mod if pad != 0: inst = getCustomOp(new_model.get_nodes_by_op_type("FMPadding")[0]) inst.set_nodeattr("preferred_impl_style", "hls") + y_produced = oxe.execute_onnx(new_model, input_dict)["outp"] + assert (y_produced == y_expected).all() new_model = new_model.transform(SpecializeLayers()) # Folding From d4c8befda5dc38b2191405df20be6bfe093c46f3 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 24 Jan 2024 11:51:25 +0000 Subject: [PATCH 403/665] [CustomOp] Initial draft of pixel padding layer in new class hierarchy --- .../custom_op/fpgadataflow/fmpadding_pixel.py | 204 ++-------------- .../custom_op/fpgadataflow/hls/__init__.py | 2 + .../fpgadataflow/hls/fmpadding_pixel_hls.py | 228 ++++++++++++++++++ .../fpgadataflow/test_fpgadataflow_deconv.py | 26 +- 4 files changed, 270 insertions(+), 190 deletions(-) create mode 100644 src/finn/custom_op/fpgadataflow/hls/fmpadding_pixel_hls.py diff --git a/src/finn/custom_op/fpgadataflow/fmpadding_pixel.py b/src/finn/custom_op/fpgadataflow/fmpadding_pixel.py index bc686bc6d2..b1f9900070 100644 --- a/src/finn/custom_op/fpgadataflow/fmpadding_pixel.py +++ b/src/finn/custom_op/fpgadataflow/fmpadding_pixel.py @@ -1,4 +1,4 @@ -# Copyright (c) 2023, Advanced Micro Devices, Inc. +# Copyright (c) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -28,15 +28,13 @@ import numpy as np -import os import warnings from qonnx.core.datatype import DataType -from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp -from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy +from finn.custom_op.fpgadataflow.hwcustomop import HWCustomOp -class FMPadding_Pixel(HLSCustomOp): +class FMPadding_Pixel(HWCustomOp): def __init__(self, onnx_node, **kwargs): super().__init__(onnx_node, **kwargs) @@ -153,183 +151,25 @@ def get_number_output_values(self): folded_oshape = self.get_folded_output_shape() return np.prod(folded_oshape[:-1]) - def global_includes(self): - self.code_gen_dict["$GLOBALS$"] = ['#include "streamtools.h"'] - - def defines(self, var): - odim_h, odim_w = self.get_padded_odim() - stride_h, stride_w = self.get_nodeattr("Stride") - self.code_gen_dict["$DEFINES$"] = [ - """ - #define OutputDim_x {}\n - #define OutputDim_y {}\n - #define Stride_x {}\n - #define Stride_y {}\n - #define NumChannels {}\n - #define SIMD {}\n - """.format( - odim_w, - odim_h, - stride_w, - stride_h, - self.get_nodeattr("NumChannels"), - self.get_nodeattr("SIMD"), - ) - ] - - def read_npy_data(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_input_datatype() - if dtype == DataType["BIPOLAR"]: - # use binary for bipolar storage - dtype = DataType["BINARY"] - elem_bits = dtype.bitwidth() - packed_bits = self.get_instream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_in = "%s/input_0.npy" % code_gen_dir - self.code_gen_dict["$READNPYDATA$"] = [] - self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0);' - % (packed_hls_type, elem_hls_type, elem_bits, npy_type, npy_in) - ) - - def strm_decl(self): - self.code_gen_dict["$STREAMDECLARATIONS$"] = [] - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0 ("in0");'.format(self.get_instream_width()) - ) - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out ("out");'.format(self.get_outstream_width()) - ) - - def docompute(self): - in_t = self.get_input_datatype().get_hls_datatype_str() - odim_h, odim_w = self.get_padded_odim() - stride_h, stride_w = self.get_nodeattr("Stride") - hls_call = "FMPadding_Pixel_Nonsquare" - self.code_gen_dict["$DOCOMPUTE$"] = [ - """{} (in0, out);""".format( - hls_call, in_t - ) - ] - - def dataoutstrm(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_output_datatype() - if dtype == DataType["BIPOLAR"]: - # use binary for bipolar storage - dtype = DataType["BINARY"] - elem_bits = dtype.bitwidth() - packed_bits = self.get_outstream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_out = "%s/output.npy" % code_gen_dir - oshape = self.get_folded_output_shape() - oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") - - self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out, %s, "%s");' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - oshape_cpp_str, - npy_out, - ) - ] - - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - - def blackboxfunction(self): - packed_bits = self.get_instream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - "void %s(hls::stream<%s > &in0, hls::stream<%s > &out)" - % (self.onnx_node.name, packed_hls_type, packed_hls_type) - ] - - def pragmas(self): - self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0 name=in0_" + self.hls_sname() - ] - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out name=out_" + self.hls_sname() - ) - self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") - def execute_node(self, context, graph): - mode = self.get_nodeattr("exec_mode") + # simulate behavior with Python functionality node = self.onnx_node - exp_ishape = self.get_normal_input_shape() - exp_oshape = self.get_normal_output_shape() - folded_ishape = self.get_folded_input_shape() - - if mode == "cppsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - elif mode == "rtlsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) + s_h, s_w = self.get_nodeattr("Stride") + inp_values = context[node.input[0]] + ishape = inp_values.shape + result = np.zeros( + ( + ishape[0], + ishape[1] + (ishape[1] - 1) * (s_h - 1), + ishape[2] + (ishape[2] - 1) * (s_w - 1), + ishape[3], ) - - inp = context[node.input[0]] - assert str(inp.dtype) == "float32", "Input datatype is not float32" - assert ( - inp.shape == exp_ishape - ), """Input shape doesn't - match expected shape (1, ImgDim_h, ImgDim_w, NumChannels).""" - export_idt = self.get_input_datatype() - - reshaped_input = inp.reshape(folded_ishape) - np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input) - - if mode == "cppsim": - # execute the precompiled model - super().exec_precompiled_singlenode_model() - # load output npy file - super().npy_to_dynamic_output(context) - assert ( - context[node.output[0]].shape == exp_oshape - ), "cppsim did not produce expected output shape" - elif mode == "rtlsim": - sim = self.get_rtlsim() - nbits = self.get_instream_width() - rtlsim_inp = npy_to_rtlsim_input( - "{}/input_0.npy".format(code_gen_dir), export_idt, nbits - ) - super().reset_rtlsim(sim) - super().toggle_clk(sim) - rtlsim_output = self.rtlsim(sim, rtlsim_inp) - odt = export_idt - target_bits = odt.bitwidth() - packed_bits = self.get_outstream_width() - out_npy_path = "{}/output.npy".format(code_gen_dir) - out_shape = self.get_folded_output_shape() - rtlsim_output_to_npy( - rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits - ) - # load and reshape output - output = np.load(out_npy_path) - output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) - context[node.output[0]] = output - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) - assert ( - context[node.output[0]].shape == exp_oshape - ), """Output shape doesn't match expected shape - (1, OutputDim_H, OutputDim_W, NumChannels).""" + ) + for b in range(ishape[0]): + for h in range(ishape[1]): + for w in range(ishape[2]): + oh = h * s_h + ow = w * s_w + result[b, oh, ow, :] = inp_values[b, h, w, :] + oshape = context[node.output[0]].shape + context[node.output[0]] = np.asarray(result, dtype=np.float32).reshape(oshape) diff --git a/src/finn/custom_op/fpgadataflow/hls/__init__.py b/src/finn/custom_op/fpgadataflow/hls/__init__.py index b4aae1ef3a..38cfd73e97 100644 --- a/src/finn/custom_op/fpgadataflow/hls/__init__.py +++ b/src/finn/custom_op/fpgadataflow/hls/__init__.py @@ -35,6 +35,7 @@ from finn.custom_op.fpgadataflow.hls.downsampler_hls import DownSampler_hls from finn.custom_op.fpgadataflow.hls.duplicatestreams_hls import DuplicateStreams_hls from finn.custom_op.fpgadataflow.hls.fmpadding_hls import FMPadding_hls +from finn.custom_op.fpgadataflow.hls.fmpadding_pixel_hls import FMPadding_Pixel_hls from finn.custom_op.fpgadataflow.hls.globalaccpool_hls import GlobalAccPool_hls from finn.custom_op.fpgadataflow.hls.labelselect_hls import LabelSelect_hls from finn.custom_op.fpgadataflow.hls.lookup_hls import Lookup_hls @@ -56,6 +57,7 @@ custom_op["DownSampler_hls"] = DownSampler_hls custom_op["DuplicateStreams_hls"] = DuplicateStreams_hls custom_op["FMPadding_hls"] = FMPadding_hls +custom_op["FMPadding_Pixel_hls"] = FMPadding_Pixel_hls custom_op["GlobalAccPool_hls"] = GlobalAccPool_hls custom_op["LabelSelect_hls"] = LabelSelect_hls custom_op["Lookup_hls"] = Lookup_hls diff --git a/src/finn/custom_op/fpgadataflow/hls/fmpadding_pixel_hls.py b/src/finn/custom_op/fpgadataflow/hls/fmpadding_pixel_hls.py new file mode 100644 index 0000000000..e1393dc96e --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/hls/fmpadding_pixel_hls.py @@ -0,0 +1,228 @@ +# Copyright (c) 2024, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of Xilinx nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + +import numpy as np +import os +from qonnx.core.datatype import DataType + +from finn.custom_op.fpgadataflow.fmpadding_pixel import FMPadding_Pixel +from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend +from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy + + +class FMPadding_Pixel_hls(FMPadding_Pixel, HLSBackend): + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) + + def get_nodeattr_types(self): + my_attrs = {} + my_attrs.update(FMPadding_Pixel.get_nodeattr_types(self)) + my_attrs.update(HLSBackend.get_nodeattr_types(self)) + return my_attrs + + def global_includes(self): + self.code_gen_dict["$GLOBALS$"] = ['#include "streamtools.h"'] + + def defines(self, var): + odim_h, odim_w = self.get_padded_odim() + stride_h, stride_w = self.get_nodeattr("Stride") + self.code_gen_dict["$DEFINES$"] = [ + """ + #define OutputDim_x {}\n + #define OutputDim_y {}\n + #define Stride_x {}\n + #define Stride_y {}\n + #define NumChannels {}\n + #define SIMD {}\n + """.format( + odim_w, + odim_h, + stride_w, + stride_h, + self.get_nodeattr("NumChannels"), + self.get_nodeattr("SIMD"), + ) + ] + + def read_npy_data(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_input_datatype() + if dtype == DataType["BIPOLAR"]: + # use binary for bipolar storage + dtype = DataType["BINARY"] + elem_bits = dtype.bitwidth() + packed_bits = self.get_instream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "float" + npy_in = "%s/input_0.npy" % code_gen_dir + self.code_gen_dict["$READNPYDATA$"] = [] + self.code_gen_dict["$READNPYDATA$"].append( + 'npy2apintstream<%s, %s, %d, %s>("%s", in0);' + % (packed_hls_type, elem_hls_type, elem_bits, npy_type, npy_in) + ) + + def strm_decl(self): + self.code_gen_dict["$STREAMDECLARATIONS$"] = [] + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> in0 ("in0");'.format(self.get_instream_width()) + ) + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> out ("out");'.format(self.get_outstream_width()) + ) + + def docompute(self): + in_t = self.get_input_datatype().get_hls_datatype_str() + odim_h, odim_w = self.get_padded_odim() + stride_h, stride_w = self.get_nodeattr("Stride") + hls_call = "FMPadding_Pixel_Nonsquare" + self.code_gen_dict["$DOCOMPUTE$"] = [ + """{} (in0, out);""".format( + hls_call, in_t + ) + ] + + def dataoutstrm(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_output_datatype() + if dtype == DataType["BIPOLAR"]: + # use binary for bipolar storage + dtype = DataType["BINARY"] + elem_bits = dtype.bitwidth() + packed_bits = self.get_outstream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "float" + npy_out = "%s/output.npy" % code_gen_dir + oshape = self.get_folded_output_shape() + oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") + + self.code_gen_dict["$DATAOUTSTREAM$"] = [ + 'apintstream2npy<%s, %s, %d, %s>(out, %s, "%s");' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + oshape_cpp_str, + npy_out, + ) + ] + + def save_as_npy(self): + self.code_gen_dict["$SAVEASCNPY$"] = [] + + def blackboxfunction(self): + packed_bits = self.get_instream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ + "void %s(hls::stream<%s > &in0, hls::stream<%s > &out)" + % (self.onnx_node.name, packed_hls_type, packed_hls_type) + ] + + def pragmas(self): + self.code_gen_dict["$PRAGMAS$"] = [ + "#pragma HLS INTERFACE axis port=in0 name=in0_" + self.hls_sname() + ] + self.code_gen_dict["$PRAGMAS$"].append( + "#pragma HLS INTERFACE axis port=out name=out_" + self.hls_sname() + ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") + + def execute_node(self, context, graph): + mode = self.get_nodeattr("exec_mode") + node = self.onnx_node + exp_ishape = self.get_normal_input_shape() + exp_oshape = self.get_normal_output_shape() + folded_ishape = self.get_folded_input_shape() + + if mode == "cppsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + elif mode == "rtlsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + + inp = context[node.input[0]] + assert str(inp.dtype) == "float32", "Input datatype is not float32" + assert ( + inp.shape == exp_ishape + ), """Input shape doesn't + match expected shape (1, ImgDim_h, ImgDim_w, NumChannels).""" + export_idt = self.get_input_datatype() + + reshaped_input = inp.reshape(folded_ishape) + np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input) + + if mode == "cppsim": + # execute the precompiled model + super().exec_precompiled_singlenode_model() + # load output npy file + super().npy_to_dynamic_output(context) + assert ( + context[node.output[0]].shape == exp_oshape + ), "cppsim did not produce expected output shape" + elif mode == "rtlsim": + sim = self.get_rtlsim() + nbits = self.get_instream_width() + rtlsim_inp = npy_to_rtlsim_input( + "{}/input_0.npy".format(code_gen_dir), export_idt, nbits + ) + super().reset_rtlsim(sim) + super().toggle_clk(sim) + rtlsim_output = self.rtlsim(sim, rtlsim_inp) + odt = export_idt + target_bits = odt.bitwidth() + packed_bits = self.get_outstream_width() + out_npy_path = "{}/output.npy".format(code_gen_dir) + out_shape = self.get_folded_output_shape() + rtlsim_output_to_npy( + rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits + ) + # load and reshape output + output = np.load(out_npy_path) + output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) + context[node.output[0]] = output + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + assert ( + context[node.output[0]].shape == exp_oshape + ), """Output shape doesn't match expected shape + (1, OutputDim_H, OutputDim_W, NumChannels).""" diff --git a/tests/fpgadataflow/test_fpgadataflow_deconv.py b/tests/fpgadataflow/test_fpgadataflow_deconv.py index 6c25be0f85..9c333e6808 100644 --- a/tests/fpgadataflow/test_fpgadataflow_deconv.py +++ b/tests/fpgadataflow/test_fpgadataflow_deconv.py @@ -1,4 +1,4 @@ -# Copyright (c) 2023, Advanced Micro Devices, Inc. +# Copyright (c) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -41,10 +41,7 @@ import finn.core.onnx_exec as oxe from finn.analysis.fpgadataflow.exp_cycles_per_layer import exp_cycles_per_layer from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim -from finn.transformation.fpgadataflow.convert_to_hls_layers import ( - InferConvInpGen, - InferQuantizedMatrixVectorActivation, -) +from finn.transformation.fpgadataflow.convert_to_hw_layers import InferConvInpGen from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP from finn.transformation.fpgadataflow.infer_pixel_padding_deconv import ( InferPixelPaddingDeconv, @@ -53,6 +50,7 @@ from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers from finn.util.basic import pynq_part_map test_pynq_board = os.getenv("PYNQ_BOARD", default="Pynq-Z1") @@ -162,9 +160,12 @@ def test_fpgadataflow_deconv(idim, stride, ifm_ch, ofm_ch, simd, pe, k, padding, input_tensor = gen_finn_dt_tensor(idt, [1, ifm_ch, idim_h, idim_w]) input_dict = {"inp": input_tensor} + y_expected = oxe.execute_onnx(ref_model, input_dict)["outp"] + model = ref_model.transform(InferPixelPaddingDeconv()) model = model.transform(InferConvInpGen(use_rtl_variant=convinpgen_rtl)) - model = model.transform(InferQuantizedMatrixVectorActivation()) + # TODO: uncomment when MV(A)U is in new class hierarchy + # model = model.transform(InferQuantizedMatrixVectorActivation()) model = model.transform(InferShapes()) model = model.transform(GiveUniqueNodeNames()) @@ -172,13 +173,21 @@ def test_fpgadataflow_deconv(idim, stride, ifm_ch, ofm_ch, simd, pe, k, padding, if n.op_type == "ConvolutionInputGenerator" and not convinpgen_rtl: convinputgen_node = getCustomOp(n) convinputgen_node.set_nodeattr("SIMD", simd) + # to test cppsim, set preferred_impl_style for swg to hls + convinputgen_node.set_nodeattr("preferred_impl_style", "hls") + elif n.op_type == "FMPadding": + pad_node = getCustomOp(n) + pad_node.set_nodeattr("preferred_impl_style", "hls") elif n.op_type == "MatrixVectorActivation": mvau_node = getCustomOp(n) mvau_node.set_nodeattr("PE", pe) mvau_node.set_nodeattr("SIMD", simd) + y_produced = oxe.execute_onnx(model, input_dict)["outp"] + assert (y_produced == y_expected).all() + + model = model.transform(SpecializeLayers()) expected_oshape = (1, ofm_ch, odim_h, odim_w) - y_expected = oxe.execute_onnx(ref_model, input_dict)["outp"] # cppsim if exec_mode == "cppsim": @@ -188,6 +197,7 @@ def test_fpgadataflow_deconv(idim, stride, ifm_ch, ofm_ch, simd, pe, k, padding, # rtlsim else: + model = model.transform(GiveUniqueNodeNames()) model = model.transform(PrepareIP(test_fpga_part, target_clk_ns)) model = model.transform(HLSSynthIP()) model = model.transform(PrepareRTLSim()) @@ -198,7 +208,7 @@ def test_fpgadataflow_deconv(idim, stride, ifm_ch, ofm_ch, simd, pe, k, padding, assert (y_produced == y_expected).all() if exec_mode == "rtlsim": - node = model.get_nodes_by_op_type("FMPadding_Pixel")[0] + node = model.get_nodes_by_op_type("FMPadding_Pixel_hls")[0] inst = getCustomOp(node) cycles_rtlsim = inst.get_nodeattr("cycles_rtlsim") exp_cycles_dict = model.analysis(exp_cycles_per_layer) From 7ccc72a9a48d3dff0ea6f2c6d56693fbc3020187 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 24 Jan 2024 15:01:29 +0000 Subject: [PATCH 404/665] [CustomOp] Initial draft of checksum layer in new class hierarchy --- src/finn/custom_op/fpgadataflow/__init__.py | 6 ++---- src/finn/custom_op/fpgadataflow/hls/__init__.py | 2 ++ .../fpgadataflow/{checksum.py => hls/checksum_hls.py} | 9 ++++++--- src/finn/transformation/fpgadataflow/insert_hook.py | 11 ++++++----- tests/fpgadataflow/test_fpgadataflow_checksum.py | 11 ++++++----- 5 files changed, 22 insertions(+), 17 deletions(-) rename src/finn/custom_op/fpgadataflow/{checksum.py => hls/checksum_hls.py} (97%) diff --git a/src/finn/custom_op/fpgadataflow/__init__.py b/src/finn/custom_op/fpgadataflow/__init__.py index 476489a26e..1dd8a6051f 100644 --- a/src/finn/custom_op/fpgadataflow/__init__.py +++ b/src/finn/custom_op/fpgadataflow/__init__.py @@ -29,7 +29,6 @@ from finn.custom_op.fpgadataflow.addstreams import AddStreams from finn.custom_op.fpgadataflow.channelwise_op import ChannelwiseOp -from finn.custom_op.fpgadataflow.checksum import CheckSum from finn.custom_op.fpgadataflow.concat import StreamingConcat from finn.custom_op.fpgadataflow.convolutioninputgenerator import ( ConvolutionInputGenerator, @@ -65,19 +64,18 @@ custom_op["MatrixVectorActivation"] = MatrixVectorActivation custom_op["TLastMarker"] = TLastMarker custom_op["StreamingFIFO"] = StreamingFIFO -custom_op["FMPadding_Pixel"] = FMPadding_Pixel custom_op["Thresholding_Batch"] = Thresholding_Batch custom_op["VectorVectorActivation"] = VectorVectorActivation custom_op["IODMA"] = IODMA custom_op["StreamingDataflowPartition"] = StreamingDataflowPartition -custom_op["CheckSum"] = CheckSum -custom_op["FMPadding"] = FMPadding custom_op["AddStreams"] = AddStreams custom_op["ChannelwiseOp"] = ChannelwiseOp custom_op["ConvolutionInputGenerator"] = ConvolutionInputGenerator custom_op["DownSampler"] = DownSampler custom_op["DuplicateStreams"] = DuplicateStreams +custom_op["FMPadding"] = FMPadding +custom_op["FMPadding_Pixel"] = FMPadding_Pixel custom_op["GlobalAccPool"] = GlobalAccPool custom_op["LabelSelect"] = LabelSelect custom_op["Lookup"] = Lookup diff --git a/src/finn/custom_op/fpgadataflow/hls/__init__.py b/src/finn/custom_op/fpgadataflow/hls/__init__.py index 38cfd73e97..ad778de01b 100644 --- a/src/finn/custom_op/fpgadataflow/hls/__init__.py +++ b/src/finn/custom_op/fpgadataflow/hls/__init__.py @@ -28,6 +28,7 @@ from finn.custom_op.fpgadataflow.hls.addstreams_hls import AddStreams_hls from finn.custom_op.fpgadataflow.hls.channelwise_op_hls import ChannelwiseOp_hls +from finn.custom_op.fpgadataflow.hls.checksum_hls import CheckSum_hls from finn.custom_op.fpgadataflow.hls.concat_hls import StreamingConcat_hls from finn.custom_op.fpgadataflow.hls.convolutioninputgenerator_hls import ( ConvolutionInputGenerator_hls, @@ -53,6 +54,7 @@ # registered and plug in correctly into the infrastructure custom_op["AddStreams_hls"] = AddStreams_hls custom_op["ChannelwiseOp_hls"] = ChannelwiseOp_hls +custom_op["CheckSum_hls"] = CheckSum_hls custom_op["ConvolutionInputGenerator_hls"] = ConvolutionInputGenerator_hls custom_op["DownSampler_hls"] = DownSampler_hls custom_op["DuplicateStreams_hls"] = DuplicateStreams_hls diff --git a/src/finn/custom_op/fpgadataflow/checksum.py b/src/finn/custom_op/fpgadataflow/hls/checksum_hls.py similarity index 97% rename from src/finn/custom_op/fpgadataflow/checksum.py rename to src/finn/custom_op/fpgadataflow/hls/checksum_hls.py index 6121c5d97a..23818621b9 100644 --- a/src/finn/custom_op/fpgadataflow/checksum.py +++ b/src/finn/custom_op/fpgadataflow/hls/checksum_hls.py @@ -1,4 +1,5 @@ # Copyright (c) 2022, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -31,11 +32,12 @@ import warnings from qonnx.core.datatype import DataType -from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp +from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend +from finn.custom_op.fpgadataflow.hwcustomop import HWCustomOp from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy -class CheckSum(HLSCustomOp): +class CheckSum_hls(HWCustomOp, HLSBackend): """Class that corresponds to custom_hls checksum function.""" def __init__(self, onnx_node, **kwargs): @@ -52,7 +54,8 @@ def get_nodeattr_types(self): # folded shape of input/output "folded_shape": ("ints", True, []), } - my_attrs.update(super().get_nodeattr_types()) + my_attrs.update(HWCustomOp.get_nodeattr_types(self)) + my_attrs.update(HLSBackend.get_nodeattr_types(self)) return my_attrs def make_shape_compatible_op(self, model): diff --git a/src/finn/transformation/fpgadataflow/insert_hook.py b/src/finn/transformation/fpgadataflow/insert_hook.py index 14989efa75..23b60d6812 100644 --- a/src/finn/transformation/fpgadataflow/insert_hook.py +++ b/src/finn/transformation/fpgadataflow/insert_hook.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (c) 2022, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -37,7 +38,7 @@ def _is_hook_node(node): - if node.op_type in ["CheckSum"]: + if node.op_type in ["CheckSum_hls"]: return True else: return False @@ -81,7 +82,7 @@ def apply(self, model): if n0_hook in list_supported_hooks: if n0_hook == "checksum": if len(consumers) == 1: - if consumers[0].op_type == "CheckSum": + if consumers[0].op_type == "CheckSum_hls": continue n0_normal_oshape = n0.get_normal_output_shape() n0_folded_oshape = n0.get_folded_output_shape() @@ -99,10 +100,10 @@ def apply(self, model): [1], ) chk_node = oh.make_node( - "CheckSum", + "CheckSum_hls", [output_name], outputs=[chk_otensor.name, chk_result.name], - domain="finn.custom_op.fpgadataflow", + domain="finn.custom_op.fpgadataflow.hls", backend="fpgadataflow", words_per_frame=words_per_frame, items_per_word=items_per_word, diff --git a/tests/fpgadataflow/test_fpgadataflow_checksum.py b/tests/fpgadataflow/test_fpgadataflow_checksum.py index 403bb328ae..5cdd99f1e4 100644 --- a/tests/fpgadataflow/test_fpgadataflow_checksum.py +++ b/tests/fpgadataflow/test_fpgadataflow_checksum.py @@ -1,4 +1,5 @@ # Copyright (c) 2022, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -151,7 +152,7 @@ def test_fpgadataflow_checksum(): model = model.transform(InferShapes()) assert ( - len(model.get_nodes_by_op_type("CheckSum")) == 2 + len(model.get_nodes_by_op_type("CheckSum_hls")) == 2 ), """Insertion of checksum layers was unsuccessful""" @@ -166,8 +167,8 @@ def test_fpgadataflow_checksum(): model = model.transform(CompileCppSim()) inp = {"global_in": x} y_cppsim = oxe.execute_onnx(model, inp, return_full_exec_context=True) - checksum0_cppsim = y_cppsim["CheckSum_0_out1"] - checksum1_cppsim = y_cppsim["CheckSum_1_out1"] + checksum0_cppsim = y_cppsim["CheckSum_hls_0_out1"] + checksum1_cppsim = y_cppsim["CheckSum_hls_1_out1"] # in this test case scenario the checksums are equal assert checksum0_cppsim == checksum1_cppsim, "CheckSums are not equal" @@ -187,7 +188,7 @@ def test_fpgadataflow_checksum(): def read_checksum_and_drain(sim): chk_addr = 16 drain_addr = 32 - for i in range(len(model.get_nodes_by_op_type("CheckSum"))): + for i in range(len(model.get_nodes_by_op_type("CheckSum_hls"))): axi_name = "s_axi_checksum_{}_".format(i) checksums.append(axilite_read(sim, chk_addr, basename=axi_name)) drain.append(axilite_read(sim, drain_addr, basename=axi_name)) @@ -196,7 +197,7 @@ def read_checksum_and_drain(sim): def write_drain(sim): addr = 32 - for i in range(len(model.get_nodes_by_op_type("CheckSum"))): + for i in range(len(model.get_nodes_by_op_type("CheckSum_hls"))): axi_name = "s_axi_checksum_{}_".format(i) axilite_write(sim, addr, drain_value, basename=axi_name) From 42951dc11504d73d16acdac0b38acc1c0407d00a Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 24 Jan 2024 15:31:35 +0000 Subject: [PATCH 405/665] [CustomOp] Initial draft of iodma in new class hierarchy --- src/finn/custom_op/fpgadataflow/__init__.py | 2 -- src/finn/custom_op/fpgadataflow/hls/__init__.py | 2 ++ .../fpgadataflow/{iodma.py => hls/iodma_hls.py} | 11 +++++++---- .../transformation/fpgadataflow/insert_iodma.py | 16 ++++++++-------- 4 files changed, 17 insertions(+), 14 deletions(-) rename src/finn/custom_op/fpgadataflow/{iodma.py => hls/iodma_hls.py} (98%) diff --git a/src/finn/custom_op/fpgadataflow/__init__.py b/src/finn/custom_op/fpgadataflow/__init__.py index 1dd8a6051f..ec26b9d5c1 100644 --- a/src/finn/custom_op/fpgadataflow/__init__.py +++ b/src/finn/custom_op/fpgadataflow/__init__.py @@ -38,7 +38,6 @@ from finn.custom_op.fpgadataflow.fmpadding import FMPadding from finn.custom_op.fpgadataflow.fmpadding_pixel import FMPadding_Pixel from finn.custom_op.fpgadataflow.globalaccpool import GlobalAccPool -from finn.custom_op.fpgadataflow.iodma import IODMA from finn.custom_op.fpgadataflow.labelselect import LabelSelect from finn.custom_op.fpgadataflow.lookup import Lookup from finn.custom_op.fpgadataflow.matrixvectoractivation import MatrixVectorActivation @@ -66,7 +65,6 @@ custom_op["StreamingFIFO"] = StreamingFIFO custom_op["Thresholding_Batch"] = Thresholding_Batch custom_op["VectorVectorActivation"] = VectorVectorActivation -custom_op["IODMA"] = IODMA custom_op["StreamingDataflowPartition"] = StreamingDataflowPartition custom_op["AddStreams"] = AddStreams diff --git a/src/finn/custom_op/fpgadataflow/hls/__init__.py b/src/finn/custom_op/fpgadataflow/hls/__init__.py index ad778de01b..5be16c407a 100644 --- a/src/finn/custom_op/fpgadataflow/hls/__init__.py +++ b/src/finn/custom_op/fpgadataflow/hls/__init__.py @@ -38,6 +38,7 @@ from finn.custom_op.fpgadataflow.hls.fmpadding_hls import FMPadding_hls from finn.custom_op.fpgadataflow.hls.fmpadding_pixel_hls import FMPadding_Pixel_hls from finn.custom_op.fpgadataflow.hls.globalaccpool_hls import GlobalAccPool_hls +from finn.custom_op.fpgadataflow.hls.iodma_hls import IODMA_hls from finn.custom_op.fpgadataflow.hls.labelselect_hls import LabelSelect_hls from finn.custom_op.fpgadataflow.hls.lookup_hls import Lookup_hls from finn.custom_op.fpgadataflow.hls.pool_hls import Pool_hls @@ -61,6 +62,7 @@ custom_op["FMPadding_hls"] = FMPadding_hls custom_op["FMPadding_Pixel_hls"] = FMPadding_Pixel_hls custom_op["GlobalAccPool_hls"] = GlobalAccPool_hls +custom_op["IODMA_hls"] = IODMA_hls custom_op["LabelSelect_hls"] = LabelSelect_hls custom_op["Lookup_hls"] = Lookup_hls custom_op["Pool_hls"] = Pool_hls diff --git a/src/finn/custom_op/fpgadataflow/iodma.py b/src/finn/custom_op/fpgadataflow/hls/iodma_hls.py similarity index 98% rename from src/finn/custom_op/fpgadataflow/iodma.py rename to src/finn/custom_op/fpgadataflow/hls/iodma_hls.py index bb3de268a0..917ee3798c 100644 --- a/src/finn/custom_op/fpgadataflow/iodma.py +++ b/src/finn/custom_op/fpgadataflow/hls/iodma_hls.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (c) 2020-2022, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -31,7 +32,8 @@ import warnings from qonnx.core.datatype import DataType -from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp +from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend +from finn.custom_op.fpgadataflow.hwcustomop import HWCustomOp # the IODMA inerfaces a memory-mapped AXI interface and an AXI stream # direction "in": pulls data from AXI-MM to AXI stream @@ -72,7 +74,7 @@ # -the folded shape is not defined -class IODMA(HLSCustomOp): +class IODMA(HWCustomOp, HLSBackend): """Class that corresponds to finn-hlslib DMA function(s).""" def __init__(self, onnx_node, **kwargs): @@ -97,7 +99,8 @@ def get_nodeattr_types(self): # name of axi-mm interface "intfName": ("s", False, ""), } - my_attrs.update(super().get_nodeattr_types()) + my_attrs.update(HWCustomOp.get_nodeattr_types(self)) + my_attrs.update(HLSBackend.get_nodeattr_types(self)) return my_attrs def get_normal_input_shape(self, ind=0): diff --git a/src/finn/transformation/fpgadataflow/insert_iodma.py b/src/finn/transformation/fpgadataflow/insert_iodma.py index 90700d5726..93e3226b2a 100644 --- a/src/finn/transformation/fpgadataflow/insert_iodma.py +++ b/src/finn/transformation/fpgadataflow/insert_iodma.py @@ -106,7 +106,7 @@ def apply(self, model): graph_in_names = [x.name for x in model.graph.input] for graph_in_name in graph_in_names: first_node = model.find_consumer(graph_in_name) - if first_node.op_type == "IODMA": + if first_node.op_type == "IODMA_hls": # IODMA already inserted for this input continue else: @@ -134,7 +134,7 @@ def apply(self, model): # padding problems for i/o DMA first_node.input[0] = first_node_in.name dma_node = oh.make_node( - "IODMA", + "IODMA_hls", [graph_in_name], [first_node_in.name], numInputVectors=in_folded_shape[:-1], @@ -143,7 +143,7 @@ def apply(self, model): intfWidth=intfwidth, streamWidth=padded_instream_width, direction="in", - domain="finn.custom_op.fpgadataflow", + domain="finn.custom_op.fpgadataflow.hls", backend="fpgadataflow", ) model.graph.node.insert(0, dma_node) @@ -153,7 +153,7 @@ def apply(self, model): graph_out_names = [x.name for x in model.graph.output] for graph_out_name in graph_out_names: final_node = model.find_producer(graph_out_name) - if final_node.op_type == "IODMA": + if final_node.op_type == "IODMA_hls": continue else: out_shape = model.get_tensor_shape(graph_out_name) @@ -180,7 +180,7 @@ def apply(self, model): # FIXME: currently always using 8-bit dtypes to work around the # padding problems for i/o DMA dma_node = oh.make_node( - "IODMA", + "IODMA_hls", [final_node_out.name], [graph_out_name], numInputVectors=out_folded_shape[:-1], @@ -189,7 +189,7 @@ def apply(self, model): intfWidth=intfwidth, streamWidth=padded_outstream_width, direction="out", - domain="finn.custom_op.fpgadataflow", + domain="finn.custom_op.fpgadataflow.hls", backend="fpgadataflow", ) model.graph.node.append(dma_node) @@ -230,7 +230,7 @@ def apply(self, model): model.set_tensor_datatype(fc_node_in.name, w_dtype) model.set_initializer(fc_node_in.name, W) dma_node = oh.make_node( - "IODMA", + "IODMA_hls", [fc_w_name], [fc_node_in.name], numInputVectors=[iodma_mem.shape[0]], @@ -240,7 +240,7 @@ def apply(self, model): streamWidth=streamWidth, direction="in", burstMode="wrap", - domain="finn.custom_op.fpgadataflow", + domain="finn.custom_op.fpgadataflow.hls", backend="fpgadataflow", ) fc_node.input[1] = fc_node_in.name From 5a4673269abb822c408d039752c60cf799ce9196 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 24 Jan 2024 15:47:33 +0000 Subject: [PATCH 406/665] [CustomOp] Initial draft of tlastmarker in new class hierarchy --- src/finn/custom_op/fpgadataflow/__init__.py | 2 -- src/finn/custom_op/fpgadataflow/hls/__init__.py | 2 ++ .../{tlastmarker.py => hls/tlastmarker_hls.py} | 11 +++++++---- src/finn/transformation/fpgadataflow/floorplan.py | 2 +- .../transformation/fpgadataflow/insert_fifo.py | 2 +- .../fpgadataflow/insert_tlastmarker.py | 14 +++++++------- tests/fpgadataflow/test_fpgadataflow_ipstitch.py | 2 +- 7 files changed, 19 insertions(+), 16 deletions(-) rename src/finn/custom_op/fpgadataflow/{tlastmarker.py => hls/tlastmarker_hls.py} (96%) diff --git a/src/finn/custom_op/fpgadataflow/__init__.py b/src/finn/custom_op/fpgadataflow/__init__.py index ec26b9d5c1..7ae76f4894 100644 --- a/src/finn/custom_op/fpgadataflow/__init__.py +++ b/src/finn/custom_op/fpgadataflow/__init__.py @@ -52,7 +52,6 @@ from finn.custom_op.fpgadataflow.streamingfifo import StreamingFIFO from finn.custom_op.fpgadataflow.streamingmaxpool import StreamingMaxPool from finn.custom_op.fpgadataflow.thresholding_batch import Thresholding_Batch -from finn.custom_op.fpgadataflow.tlastmarker import TLastMarker from finn.custom_op.fpgadataflow.upsampler import UpsampleNearestNeighbour from finn.custom_op.fpgadataflow.vectorvectoractivation import VectorVectorActivation @@ -61,7 +60,6 @@ # make sure new HLSCustomOp subclasses are imported here so that they get # registered and plug in correctly into the infrastructure custom_op["MatrixVectorActivation"] = MatrixVectorActivation -custom_op["TLastMarker"] = TLastMarker custom_op["StreamingFIFO"] = StreamingFIFO custom_op["Thresholding_Batch"] = Thresholding_Batch custom_op["VectorVectorActivation"] = VectorVectorActivation diff --git a/src/finn/custom_op/fpgadataflow/hls/__init__.py b/src/finn/custom_op/fpgadataflow/hls/__init__.py index 5be16c407a..3e31c9785e 100644 --- a/src/finn/custom_op/fpgadataflow/hls/__init__.py +++ b/src/finn/custom_op/fpgadataflow/hls/__init__.py @@ -47,6 +47,7 @@ ) from finn.custom_op.fpgadataflow.hls.streamingeltwise_hls import StreamingEltwise_hls from finn.custom_op.fpgadataflow.hls.streamingmaxpool_hls import StreamingMaxPool_hls +from finn.custom_op.fpgadataflow.hls.tlastmarker_hls import TLastMarker_hls from finn.custom_op.fpgadataflow.hls.upsampler_hls import UpsampleNearestNeighbour_hls custom_op = dict() @@ -70,4 +71,5 @@ custom_op["StreamingEltwise_hls"] = StreamingEltwise_hls custom_op["StreamingDataWidthConverter_hls"] = StreamingDataWidthConverter_hls custom_op["StreamingMaxPool_hls"] = StreamingMaxPool_hls +custom_op["TLastMarker_hls"] = TLastMarker_hls custom_op["UpsampleNearestNeighbour_hls"] = UpsampleNearestNeighbour_hls diff --git a/src/finn/custom_op/fpgadataflow/tlastmarker.py b/src/finn/custom_op/fpgadataflow/hls/tlastmarker_hls.py similarity index 96% rename from src/finn/custom_op/fpgadataflow/tlastmarker.py rename to src/finn/custom_op/fpgadataflow/hls/tlastmarker_hls.py index 9309841b2e..c2ed06f832 100644 --- a/src/finn/custom_op/fpgadataflow/tlastmarker.py +++ b/src/finn/custom_op/fpgadataflow/hls/tlastmarker_hls.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (c) 2020-2022, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -26,10 +27,11 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp +from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend +from finn.custom_op.fpgadataflow.hwcustomop import HWCustomOp -class TLastMarker(HLSCustomOp): +class TLastMarker_hls(HWCustomOp, HLSBackend): """Node that adds/removes AXI stream TLAST signals where needed. Its behavior is transparent in node-by-node execution, only visible in IP-stitched rtlsim or actual hardware. @@ -56,7 +58,8 @@ def get_nodeattr_types(self): # Vitis docs recommend using qdma_axis for external, ap_axiu for internal "Protocol": ("s", False, "external", {"external", "internal"}), } - my_attrs.update(super().get_nodeattr_types()) + my_attrs.update(HWCustomOp.get_nodeattr_types(self)) + my_attrs.update(HLSBackend.get_nodeattr_types(self)) return my_attrs def execute_node(self, context, graph): diff --git a/src/finn/transformation/fpgadataflow/floorplan.py b/src/finn/transformation/fpgadataflow/floorplan.py index fce2c2264c..b6de086506 100644 --- a/src/finn/transformation/fpgadataflow/floorplan.py +++ b/src/finn/transformation/fpgadataflow/floorplan.py @@ -123,7 +123,7 @@ def apply(self, model): non_dma_nodes = list(filter(lambda x: x not in dma_nodes, df_nodes)) dyn_tlastmarker_nodes = list( filter( - lambda x: x.op_type == "TLastMarker" + lambda x: x.op_type == "TLastMarker_hls" and getCustomOp(x).get_nodeattr("DynIters") == "true", non_dma_nodes, ) diff --git a/src/finn/transformation/fpgadataflow/insert_fifo.py b/src/finn/transformation/fpgadataflow/insert_fifo.py index f57c9e41b7..8debf6f501 100644 --- a/src/finn/transformation/fpgadataflow/insert_fifo.py +++ b/src/finn/transformation/fpgadataflow/insert_fifo.py @@ -236,7 +236,7 @@ def apply(self, model): final_node = model.find_producer(graph_out_name) if final_node.op_type != "StreamingFIFO" and final_node.op_type != "IODMA": assert ( - final_node.op_type != "TLastMarker" + final_node.op_type != "TLastMarker_hls" ), """Insert tlast marker should be done after inserting the FIFOs""" n0 = getCustomOp(final_node) diff --git a/src/finn/transformation/fpgadataflow/insert_tlastmarker.py b/src/finn/transformation/fpgadataflow/insert_tlastmarker.py index 94f0b0eae1..00e5457b52 100644 --- a/src/finn/transformation/fpgadataflow/insert_tlastmarker.py +++ b/src/finn/transformation/fpgadataflow/insert_tlastmarker.py @@ -35,7 +35,7 @@ class InsertTLastMarker(Transformation): - """Ensure that the graph is started/terminated with a TLastMarker node, inserting + """Ensure that the graph is started/terminated with a TLastMarker_hls node, inserting one if necessary. Use constructor args to determine type of TLastMarker to be inserted. More information available on the TLastMarker documentation. @@ -52,7 +52,7 @@ def apply(self, model): graph_out_name = model.graph.output[0].name final_node = model.find_producer(graph_out_name) graph_modified = False - if final_node.op_type != "TLastMarker" and not ( + if final_node.op_type != "TLastMarker_hls" and not ( final_node.op_type == "IODMA" and get_by_name(final_node.attribute, "direction").s.decode("UTF-8") == "out" ): @@ -71,7 +71,7 @@ def apply(self, model): # reroute final node output to final_node_out_name final_node.output[0] = final_node_out.name tlast_node = oh.make_node( - "TLastMarker", + "TLastMarker_hls", [final_node_out.name], [graph_out_name], NumIters=num_iters, @@ -80,7 +80,7 @@ def apply(self, model): DynIters=(1 if self.dyniters else 0), Direction="out", Protocol=("external" if self.external else "internal"), - domain="finn.custom_op.fpgadataflow", + domain="finn.custom_op.fpgadataflow.hls", backend="fpgadataflow", ) model.graph.node.append(tlast_node) @@ -109,7 +109,7 @@ def apply(self, model): ): continue # 2. node is either a TLastMarker or an input IODMA - if first_node.op_type != "TLastMarker" and not ( + if first_node.op_type != "TLastMarker_hls" and not ( first_node.op_type == "IODMA" and get_by_name(first_node.attribute, "direction").s.decode("UTF-8") == "in" ): @@ -141,7 +141,7 @@ def apply(self, model): # reroute final node output to first_node_in_name first_node.input[inp_idx] = first_node_in.name tlast_node = oh.make_node( - "TLastMarker", + "TLastMarker_hls", [graph_in_name], [first_node_in.name], NumIters=num_iters, @@ -150,7 +150,7 @@ def apply(self, model): DynIters=(1 if self.dyniters else 0), Direction="in", Protocol=("external" if self.external else "internal"), - domain="finn.custom_op.fpgadataflow", + domain="finn.custom_op.fpgadataflow.hls", backend="fpgadataflow", ) model.graph.node.insert(insert_idx, tlast_node) diff --git a/tests/fpgadataflow/test_fpgadataflow_ipstitch.py b/tests/fpgadataflow/test_fpgadataflow_ipstitch.py index 2d85cc98f4..aedb151af9 100644 --- a/tests/fpgadataflow/test_fpgadataflow_ipstitch.py +++ b/tests/fpgadataflow/test_fpgadataflow_ipstitch.py @@ -209,7 +209,7 @@ def test_fpgadataflow_ipstitch_gen_model(mem_mode): model = model.transform(PrepareIP(test_fpga_part, 5)) model = model.transform(HLSSynthIP()) assert model.graph.node[0].op_type == "MatrixVectorActivation" - assert model.graph.node[-1].op_type == "TLastMarker" + assert model.graph.node[-1].op_type == "TLastMarker_hls" model.save(ip_stitch_model_dir + "/test_fpgadataflow_ipstitch_gen_model_%s.onnx" % mem_mode) From 161d43feb0f9c414505920e751365f79a17c7381 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 24 Jan 2024 15:52:18 +0000 Subject: [PATCH 407/665] [CustomOp] Rename IODMA to IODMA_hls --- src/finn/custom_op/fpgadataflow/hls/iodma_hls.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/finn/custom_op/fpgadataflow/hls/iodma_hls.py b/src/finn/custom_op/fpgadataflow/hls/iodma_hls.py index 917ee3798c..a0701b8989 100644 --- a/src/finn/custom_op/fpgadataflow/hls/iodma_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/iodma_hls.py @@ -74,7 +74,7 @@ # -the folded shape is not defined -class IODMA(HWCustomOp, HLSBackend): +class IODMA_hls(HWCustomOp, HLSBackend): """Class that corresponds to finn-hlslib DMA function(s).""" def __init__(self, onnx_node, **kwargs): From 02c04533fba5421ca68874de9c5cce07b61314d4 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 24 Jan 2024 16:49:00 +0000 Subject: [PATCH 408/665] [Transform] Rename IODMA optype in transformations --- .../fpgadataflow/create_dataflow_partition.py | 2 +- .../transformation/fpgadataflow/create_stitched_ip.py | 2 +- .../transformation/fpgadataflow/externalize_params.py | 2 +- src/finn/transformation/fpgadataflow/floorplan.py | 2 +- src/finn/transformation/fpgadataflow/insert_dwc.py | 2 +- src/finn/transformation/fpgadataflow/insert_fifo.py | 4 ++-- .../transformation/fpgadataflow/insert_tlastmarker.py | 4 ++-- src/finn/transformation/fpgadataflow/make_pynq_driver.py | 8 +++++--- 8 files changed, 14 insertions(+), 12 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/create_dataflow_partition.py b/src/finn/transformation/fpgadataflow/create_dataflow_partition.py index 07d6961be3..f34c6b90af 100644 --- a/src/finn/transformation/fpgadataflow/create_dataflow_partition.py +++ b/src/finn/transformation/fpgadataflow/create_dataflow_partition.py @@ -52,7 +52,7 @@ def __init__(self, partition_model_dir=None): def apply(self, model): def filter_fc_extw(x): - if x.op_type == "IODMA": + if x.op_type == "IODMA_hls": burst_mode = get_by_name(x.attribute, "burstMode") if burst_mode is not None: burst_mode = burst_mode.s.decode("UTF-8") diff --git a/src/finn/transformation/fpgadataflow/create_stitched_ip.py b/src/finn/transformation/fpgadataflow/create_stitched_ip.py index 9a653fe404..1a182c7f4f 100644 --- a/src/finn/transformation/fpgadataflow/create_stitched_ip.py +++ b/src/finn/transformation/fpgadataflow/create_stitched_ip.py @@ -284,7 +284,7 @@ def apply(self, model): ip_dirs.append("$::env(FINN_ROOT)/finn-rtllib/memstream") if self.signature: ip_dirs.append("$::env(FINN_ROOT)/finn-rtllib/axi_info") - if model.graph.node[0].op_type not in ["StreamingFIFO", "IODMA"]: + if model.graph.node[0].op_type not in ["StreamingFIFO", "IODMA_hls"]: warnings.warn( """First node is not StreamingFIFO or IODMA. You may experience incorrect stitched-IP rtlsim or hardware diff --git a/src/finn/transformation/fpgadataflow/externalize_params.py b/src/finn/transformation/fpgadataflow/externalize_params.py index 633db0c553..5e21d8cb2a 100644 --- a/src/finn/transformation/fpgadataflow/externalize_params.py +++ b/src/finn/transformation/fpgadataflow/externalize_params.py @@ -42,7 +42,7 @@ def apply(self, model): graph_modified = False def filter_fc_extw(x): - if x.op_type == "IODMA": + if x.op_type == "IODMA_hls": burst_mode = get_by_name(x.attribute, "burstMode") if burst_mode is not None: burst_mode = burst_mode.s.decode("UTF-8") diff --git a/src/finn/transformation/fpgadataflow/floorplan.py b/src/finn/transformation/fpgadataflow/floorplan.py index b6de086506..ceb2bdb5c9 100644 --- a/src/finn/transformation/fpgadataflow/floorplan.py +++ b/src/finn/transformation/fpgadataflow/floorplan.py @@ -119,7 +119,7 @@ def apply(self, model): df_nodes = list( filter(lambda x: get_by_name(x.attribute, "backend") is not None, all_nodes) ) - dma_nodes = list(filter(lambda x: x.op_type == "IODMA", df_nodes)) + dma_nodes = list(filter(lambda x: x.op_type == "IODMA_hls", df_nodes)) non_dma_nodes = list(filter(lambda x: x not in dma_nodes, df_nodes)) dyn_tlastmarker_nodes = list( filter( diff --git a/src/finn/transformation/fpgadataflow/insert_dwc.py b/src/finn/transformation/fpgadataflow/insert_dwc.py index ee4311a5a1..81cee8dae4 100644 --- a/src/finn/transformation/fpgadataflow/insert_dwc.py +++ b/src/finn/transformation/fpgadataflow/insert_dwc.py @@ -47,7 +47,7 @@ def _suitable_node(node): if _is_dwc_node(node): # no DWC for DWCs return False - elif node.op_type == "IODMA": + elif node.op_type == "IODMA_hls": # IODMA data shapes/widths need special handling return False else: diff --git a/src/finn/transformation/fpgadataflow/insert_fifo.py b/src/finn/transformation/fpgadataflow/insert_fifo.py index 8debf6f501..de555d4101 100644 --- a/src/finn/transformation/fpgadataflow/insert_fifo.py +++ b/src/finn/transformation/fpgadataflow/insert_fifo.py @@ -182,7 +182,7 @@ def apply(self, model): for graph_in_name in graph_in_names: first_node = model.find_consumer(graph_in_name) # insert FIFO as first node, except when first node is DMA - if first_node.op_type != "StreamingFIFO" and first_node.op_type != "IODMA": + if first_node.op_type != "StreamingFIFO" and first_node.op_type != "IODMA_hls": inp_ind = list(first_node.input).index(graph_in_name) n_input = first_node.input[inp_ind] n0 = getCustomOp(first_node) @@ -234,7 +234,7 @@ def apply(self, model): graph_out_names = [x.name for x in model.graph.output] for graph_out_name in graph_out_names: final_node = model.find_producer(graph_out_name) - if final_node.op_type != "StreamingFIFO" and final_node.op_type != "IODMA": + if final_node.op_type != "StreamingFIFO" and final_node.op_type != "IODMA_hls": assert ( final_node.op_type != "TLastMarker_hls" ), """Insert tlast marker should be done diff --git a/src/finn/transformation/fpgadataflow/insert_tlastmarker.py b/src/finn/transformation/fpgadataflow/insert_tlastmarker.py index 00e5457b52..157df46d71 100644 --- a/src/finn/transformation/fpgadataflow/insert_tlastmarker.py +++ b/src/finn/transformation/fpgadataflow/insert_tlastmarker.py @@ -53,7 +53,7 @@ def apply(self, model): final_node = model.find_producer(graph_out_name) graph_modified = False if final_node.op_type != "TLastMarker_hls" and not ( - final_node.op_type == "IODMA" + final_node.op_type == "IODMA_hls" and get_by_name(final_node.attribute, "direction").s.decode("UTF-8") == "out" ): custom_op = getCustomOp(final_node) @@ -110,7 +110,7 @@ def apply(self, model): continue # 2. node is either a TLastMarker or an input IODMA if first_node.op_type != "TLastMarker_hls" and not ( - first_node.op_type == "IODMA" + first_node.op_type == "IODMA_hls" and get_by_name(first_node.attribute, "direction").s.decode("UTF-8") == "in" ): custom_op = getCustomOp(first_node) diff --git a/src/finn/transformation/fpgadataflow/make_pynq_driver.py b/src/finn/transformation/fpgadataflow/make_pynq_driver.py index 6d1fa290b4..d5c2d8f2b5 100644 --- a/src/finn/transformation/fpgadataflow/make_pynq_driver.py +++ b/src/finn/transformation/fpgadataflow/make_pynq_driver.py @@ -146,7 +146,7 @@ def apply(self, model): Ensure CreateDataflowPartition called before driver creation.""" first_df_model = ModelWrapper(getCustomOp(i_consumer).get_nodeattr("model")) assert ( - first_df_model.graph.node[0].op_type == "IODMA" + first_df_model.graph.node[0].op_type == "IODMA_hls" ), "First partition must hold input IODMA" successors = model.find_direct_successors(i_consumer) successor_input_num = list(successors[0].input).index(i_consumer.output[0]) @@ -187,7 +187,9 @@ def apply(self, model): ), """ Ensure CreateDataflowPartition called before driver creation.""" df_model = ModelWrapper(getCustomOp(o_producer).get_nodeattr("model")) - assert df_model.graph.node[-1].op_type == "IODMA", "Partition must hold output IODMA" + assert ( + df_model.graph.node[-1].op_type == "IODMA_hls" + ), "Partition must hold output IODMA" predecessors = model.find_direct_predecessors(o_producer) predecessor_output_num = list(predecessors[0].output).index(o_producer.input[0]) predecessor_sdp = getCustomOp(predecessors[0]) @@ -231,7 +233,7 @@ def apply(self, model): sdp_inst = getCustomOp(node) idma_name = sdp_inst.get_nodeattr("instance_name") df_model = ModelWrapper(sdp_inst.get_nodeattr("model")) - assert df_model.graph.node[0].op_type == "IODMA" + assert df_model.graph.node[0].op_type == "IODMA_hls" iodma_node = getCustomOp(df_model.graph.node[0]) if iodma_node.get_nodeattr("burstMode") == "wrap": # input weights dma? init_tensor = df_model.get_initializer(iodma_node.onnx_node.input[0]) From d7104881e83a4b56502264925f32f0b3fbffc801 Mon Sep 17 00:00:00 2001 From: auphelia Date: Thu, 25 Jan 2024 15:49:44 +0000 Subject: [PATCH 409/665] [CustomOp] Initial draft of FIFO in new class hierarchy --- finn-rtllib/fifo/hdl/Q_srl.v | 308 ++++++++++++++++++ finn-rtllib/fifo/hdl/fifo_template.v | 72 ++++ .../custom_op/fpgadataflow/rtl/__init__.py | 2 + .../fpgadataflow/rtl/streamingfifo_rtl.py | 283 ++++++++++++++++ .../custom_op/fpgadataflow/streamingfifo.py | 263 +-------------- src/finn/custom_op/fpgadataflow/templates.py | 46 --- tests/fpgadataflow/test_fpgadataflow_fifo.py | 4 +- 7 files changed, 672 insertions(+), 306 deletions(-) create mode 100644 finn-rtllib/fifo/hdl/Q_srl.v create mode 100644 finn-rtllib/fifo/hdl/fifo_template.v create mode 100644 src/finn/custom_op/fpgadataflow/rtl/streamingfifo_rtl.py diff --git a/finn-rtllib/fifo/hdl/Q_srl.v b/finn-rtllib/fifo/hdl/Q_srl.v new file mode 100644 index 0000000000..11cef604e0 --- /dev/null +++ b/finn-rtllib/fifo/hdl/Q_srl.v @@ -0,0 +1,308 @@ +// original source: +// https://github.com/nachiket/tdfc/blob/master/verilog/queues/Q_srl_oreg3_prefull_SIMPLE.v + + +// Copyright (c) 1999 The Regents of the University of California +// Copyright (c) 2010 The Regents of the University of Pennsylvania +// Copyright (c) 2011 Department of Electrical and Electronic Engineering, Imperial College London +// Copyright (c) 2020 Xilinx +// +// Permission to use, copy, modify, and distribute this software and +// its documentation for any purpose, without fee, and without a +// written agreement is hereby granted, provided that the above copyright +// notice and this paragraph and the following two paragraphs appear in +// all copies. +// +// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR +// DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING +// LOST PROFITS, ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, +// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF +// SUCH DAMAGE. +// +// THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY +// AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS ON +// AN "AS IS" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO +// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. +// + +// Q_srl_oreg3_prefull_SIMPLE.v +// +// - In-page queue with parameterizable depth, bit width +// - Stream I/O is triple (data, valid, back-pressure), +// with EOS concatenated into the data +// - Flow control for input & output is combinationally decoupled +// - 2 <= depth <= 256 +// * (depth >= 2) is required to decouple I/O flow control, +// where empty => no produce, full => no consume, +// and depth 1 would ping-pong between the two at half rate +// * (depth <= 256) can be modified +// by changing ''synthesis loop_limit X'' below +// and changing ''addrwidth'' or its log computation +// - 1 <= width +// - Queue storage is in SRL16E, up to depth 16 per LUT per bit-slice, +// plus output register (for fast output) +// - Queue addressing is done by ''addr'' up-down counter +// - Queue fullness is checked by comparator (addr==depth) +// - Queue fullness is pre-computed for next cycle +// - Queue input back-pressure is pre-computed for next cycle +// - Queue output valid (state!=state__empty) is pre-computed for next cycle +// (necessary since SRL data output reg requires non-boolean state) +// - FSM has 3 states (empty, one, more) +// - When empty, continue to emit most recently emitted value (for debugging) +// +// - Queue slots used = / (state==state_empty) ? 0 +// | (state==state_one) ? 1 +// \ (state==state_more) ? addr+2 +// - Queue slots used <= depth +// - Queue slots remaining = depth - used +// = / (state==state_empty) ? depth +// | (state==state_one) ? depth-1 +// \ (state==state_more) ? depth-2-addr +// +// - Synplify 7.1 / 8.0 +// - Eylon Caspi, 9/11/03, 8/18/04, 3/29/05 + + +`ifdef Q_srl +`else +`define Q_srl + + +module Q_srl (clock, reset, i_d, i_v, i_r, o_d, o_v, o_r, count, maxcount); + + parameter depth = 16; // - greatest #items in queue (2 <= depth <= 256) + parameter width = 16; // - width of data (i_d, o_d) + + parameter addrwidth = $clog2(depth); + + input clock; + input reset; + + input [width-1:0] i_d; // - input stream data (concat data + eos) + input i_v; // - input stream valid + output i_r; // - input stream ready + wire i_b; // - input stream back-pressure + + output [width-1:0] o_d; // - output stream data (concat data + eos) + output o_v; // - output stream valid + input o_r; // - output stream ready + wire o_b; // - output stream back-pressure + + output [addrwidth:0] count; // - output number of elems in queue + output [addrwidth:0] maxcount; // - maximum observed count since reset + + reg [addrwidth:0] maxcount_reg; // - maximum count seen until now + reg [addrwidth-1:0] addr, addr_, a_; // - SRL16 address + // for data output + reg shift_en_; // - SRL16 shift enable + reg [width-1:0] srl [depth-2:0]; // - SRL16 memory + reg shift_en_o_; // - SRLO shift enable + reg [width-1:0] srlo_, srlo // - SRLO output reg + /* synthesis syn_allow_retiming=0 */ ; + + parameter state_empty = 2'd0; // - state empty : o_v=0 o_d=UNDEFINED + parameter state_one = 2'd1; // - state one : o_v=1 o_d=srlo + parameter state_more = 2'd2; // - state more : o_v=1 o_d=srlo + // #items in srl = addr+2 + + reg [1:0] state, state_; // - state register + + wire addr_full_; // - true iff addr==depth-2 on NEXT cycle + reg addr_full; // - true iff addr==depth-2 + wire addr_zero_; // - true iff addr==0 + wire o_v_reg_; // - true iff state_empty on NEXT cycle + reg o_v_reg // - true iff state_empty + /* synthesis syn_allow_retiming=0 */ ; + wire i_b_reg_; // - true iff !full on NEXT cycle + reg i_b_reg // - true iff !full + /* synthesis syn_allow_retiming=0 */ ; + + assign addr_full_ = (state_==state_more) && (addr_==depth-2); + // - queue full + assign addr_zero_ = (addr==0); // - queue contains 2 (or 1,0) + assign o_v_reg_ = (state_!=state_empty); // - output valid if non-empty + assign i_b_reg_ = addr_full_; // - input bp if full + assign o_d = srlo; // - output data from queue + assign o_v = o_v_reg; // - output valid if non-empty + assign i_b = i_b_reg; // - input bp if full + assign maxcount = maxcount_reg; + + assign i_r = !i_b; + assign o_b = !o_r; + + assign count = (state==state_more ? addr+2 : (state==state_one ? 1 : 0)); + + // - ''always'' block with both FFs and SRL16 does not work, + // since FFs need reset but SRL16 does not + + always @(posedge clock) begin // - seq always: FFs + if (reset) begin + state <= state_empty; + addr <= 0; + addr_full <= 0; + o_v_reg <= 0; + + i_b_reg <= 0; + maxcount_reg <= 0; + + end + else begin + state <= state_; + addr <= addr_; + addr_full <= addr_full_; + o_v_reg <= o_v_reg_; + i_b_reg <= i_b_reg_; + maxcount_reg <= (count > maxcount_reg ? count : maxcount_reg); + end + end // always @ (posedge clock) + + always @(posedge clock) begin // - seq always: srlo + // - infer enabled output reg at end of shift chain + // - input first element from i_d, all subsequent elements from SRL16 + if (reset) begin + srlo <= 0; + end + else begin + if (shift_en_o_) begin + srlo <= srlo_; + end + end + end // always @ (posedge clock) + + always @(posedge clock) begin // - seq always: srl + // - infer enabled SRL16E from shifting srl array + // - no reset capability; srl[] contents undefined on reset + if (shift_en_) begin + // synthesis loop_limit 256 + for (a_=depth-2; a_>0; a_=a_-1) begin + srl[a_] = srl[a_-1]; + end + srl[0] <= i_d; + end + end // always @ (posedge clock or negedge reset) + + always @* begin // - combi always + srlo_ <= 'bx; + shift_en_o_ <= 1'bx; + shift_en_ <= 1'bx; + addr_ <= 'bx; + state_ <= 2'bx; + case (state) + + state_empty: begin // - (empty, will not produce) + if (i_v) begin // - empty & i_v => consume + srlo_ <= i_d; + shift_en_o_ <= 1; + shift_en_ <= 1'bx; + addr_ <= 0; + state_ <= state_one; + end + else begin // - empty & !i_v => idle + srlo_ <= 'bx; + shift_en_o_ <= 0; + shift_en_ <= 1'bx; + addr_ <= 0; + state_ <= state_empty; + end + end + + state_one: begin // - (contains one) + if (i_v && o_b) begin // - one & i_v & o_b => consume + srlo_ <= 'bx; + shift_en_o_ <= 0; + shift_en_ <= 1; + addr_ <= 0; + state_ <= state_more; + end + else if (i_v && !o_b) begin // - one & i_v & !o_b => cons+prod + srlo_ <= i_d; + shift_en_o_ <= 1; + shift_en_ <= 1; + addr_ <= 0; + state_ <= state_one; + end + else if (!i_v && o_b) begin // - one & !i_v & o_b => idle + srlo_ <= 'bx; + shift_en_o_ <= 0; + shift_en_ <= 1'bx; + addr_ <= 0; + state_ <= state_one; + end + else if (!i_v && !o_b) begin // - one & !i_v & !o_b => produce + srlo_ <= 'bx; + shift_en_o_ <= 0; + shift_en_ <= 1'bx; + addr_ <= 0; + state_ <= state_empty; + end + end // case: state_one + + state_more: begin // - (contains more than one) + if (addr_full || (depth==2)) begin + // - (full, will not consume) + // - (full here if depth==2) + if (o_b) begin // - full & o_b => idle + srlo_ <= 'bx; + shift_en_o_ <= 0; + shift_en_ <= 0; + addr_ <= addr; + state_ <= state_more; + end + else begin // - full & !o_b => produce + srlo_ <= srl[addr]; + shift_en_o_ <= 1; + shift_en_ <= 0; +// addr_ <= addr-1; +// state_ <= state_more; + addr_ <= addr_zero_ ? 0 : addr-1; + state_ <= addr_zero_ ? state_one : state_more; + end + end + else begin // - (mid: neither empty nor full) + if (i_v && o_b) begin // - mid & i_v & o_b => consume + srlo_ <= 'bx; + shift_en_o_ <= 0; + shift_en_ <= 1; + addr_ <= addr+1; + state_ <= state_more; + end + else if (i_v && !o_b) begin // - mid & i_v & !o_b => cons+prod + srlo_ <= srl[addr]; + shift_en_o_ <= 1; + shift_en_ <= 1; + addr_ <= addr; + state_ <= state_more; + end + else if (!i_v && o_b) begin // - mid & !i_v & o_b => idle + srlo_ <= 'bx; + shift_en_o_ <= 0; + shift_en_ <= 0; + addr_ <= addr; + state_ <= state_more; + end + else if (!i_v && !o_b) begin // - mid & !i_v & !o_b => produce + srlo_ <= srl[addr]; + shift_en_o_ <= 1; + shift_en_ <= 0; + addr_ <= addr_zero_ ? 0 : addr-1; + state_ <= addr_zero_ ? state_one : state_more; + end + end // else: !if(addr_full) + end // case: state_more + + default: begin + srlo_ <= 'bx; + shift_en_o_ <= 1'bx; + shift_en_ <= 1'bx; + addr_ <= 'bx; + state_ <= 2'bx; + end // case: default + + endcase // case(state) + end // always @ * + +endmodule // Q_srl + + +`endif // `ifdef Q_srl diff --git a/finn-rtllib/fifo/hdl/fifo_template.v b/finn-rtllib/fifo/hdl/fifo_template.v new file mode 100644 index 0000000000..4c614c83dd --- /dev/null +++ b/finn-rtllib/fifo/hdl/fifo_template.v @@ -0,0 +1,72 @@ +/****************************************************************************** + * Copyright (C) 2024, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *****************************************************************************/ + +module $TOP_MODULE_NAME$( +//- Global Control ------------------ +(* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out_V:s_axilite" *) +input ap_clk, +(* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out_V:s_axilite" *) +input ap_rst_n, + + +output $COUNT_RANGE$ count, +output $COUNT_RANGE$ maxcount, + +//- AXI Stream - Input -------------- +output in0_V_TREADY, +input in0_V_TVALID, +input $IN_RANGE$ in0_V_TDATA, + +//- AXI Stream - Output -------------- +input out_V_TREADY, +output out_V_TVALID, +output $OUT_RANGE$ out_V_TDATA +); + +Q_srl #( +.depth($DEPTH$), +.width($WIDTH$) +) +$TOP_MODULE_NAME$_impl +( + .clock(ap_clk), + .reset(!ap_rst_n), + .count(count), + .maxcount(maxcount), + .i_d(in0_V_TDATA), + .i_v(in0_V_TVALID), + .i_r(in0_V_TREADY), + .o_d(out_V_TDATA), + .o_v(out_V_TVALID), + .o_r(out_V_TREADY) +); + +endmodule diff --git a/src/finn/custom_op/fpgadataflow/rtl/__init__.py b/src/finn/custom_op/fpgadataflow/rtl/__init__.py index ac75371381..914c033584 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/__init__.py +++ b/src/finn/custom_op/fpgadataflow/rtl/__init__.py @@ -33,6 +33,7 @@ from finn.custom_op.fpgadataflow.rtl.streamingdatawidthconverter_rtl import ( StreamingDataWidthConverter_rtl, ) +from finn.custom_op.fpgadataflow.rtl.streamingfifo_rtl import StreamingFIFO_rtl custom_op = dict() @@ -41,3 +42,4 @@ custom_op["ConvolutionInputGenerator_rtl"] = ConvolutionInputGenerator_rtl custom_op["FMPadding_rtl"] = FMPadding_rtl custom_op["StreamingDataWidthConverter_rtl"] = StreamingDataWidthConverter_rtl +custom_op["StreamingFIFO_rtl"] = StreamingFIFO_rtl diff --git a/src/finn/custom_op/fpgadataflow/rtl/streamingfifo_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/streamingfifo_rtl.py new file mode 100644 index 0000000000..a9d9e689eb --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/rtl/streamingfifo_rtl.py @@ -0,0 +1,283 @@ +# Copyright (C) 2024, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +import numpy as np +import os +import shutil +import warnings +from qonnx.core.datatype import DataType + +from finn.custom_op.fpgadataflow.rtlbackend import RTLBackend +from finn.custom_op.fpgadataflow.streamingfifo import StreamingFIFO +from finn.util.basic import get_rtlsim_trace_depth, make_build_dir +from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy + +try: + from pyverilator import PyVerilator +except ModuleNotFoundError: + PyVerilator = None + + +class StreamingFIFO_rtl(StreamingFIFO, RTLBackend): + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) + + def get_nodeattr_types(self): + my_attrs = { + # Toggle between rtl or IPI implementation + # rtl - use the rtl generated IP during stitching + # vivado - use the AXI Infrastructure FIFO + "impl_style": ("s", False, "rtl", {"rtl", "vivado"}), + } + my_attrs.update(StreamingFIFO.get_nodeattr_types(self)) + my_attrs.update(RTLBackend.get_nodeattr_types(self)) + + return my_attrs + + def get_adjusted_depth(self): + impl = self.get_nodeattr("impl_style") + depth = self.get_nodeattr("depth") + if impl == "vivado": + old_depth = depth + # round up depth to nearest power-of-2 + # Vivado FIFO impl may fail otherwise + depth = (1 << (depth - 1).bit_length()) if impl == "vivado" else depth + if old_depth != depth: + warnings.warn( + "%s: rounding-up FIFO depth from %d to %d for impl_style=vivado" + % (self.onnx_node.name, old_depth, depth) + ) + + return depth + + def get_verilog_top_module_intf_names(self): + ret = super().get_verilog_top_module_intf_names() + is_rtl = self.get_nodeattr("impl_style") == "rtl" + is_depth_monitor = self.get_nodeattr("depth_monitor") == 1 + if is_rtl and is_depth_monitor: + ret["ap_none"] = ["maxcount"] + return ret + + def generate_hdl(self): + rtlsrc = os.environ["FINN_ROOT"] + "/finn-rtllib/fifo/hdl" + template_path = rtlsrc + "/fifo_template.v" + + # save top module name so we can refer to it after this node has been renamed + # (e.g. by GiveUniqueNodeNames(prefix) during MakeZynqProject) + topname = self.get_verilog_top_module_name() + self.set_nodeattr("gen_top_module", topname) + + code_gen_dict = {} + code_gen_dict["$TOP_MODULE_NAME$"] = topname + # make instream width a multiple of 8 for axi interface + in_width = self.get_instream_width_padded() + count_width = int(self.get_nodeattr("depth") - 1).bit_length() + code_gen_dict["$COUNT_RANGE$"] = "[{}:0]".format(count_width - 1) + code_gen_dict["$IN_RANGE$"] = "[{}:0]".format(in_width - 1) + code_gen_dict["$OUT_RANGE$"] = "[{}:0]".format(in_width - 1) + code_gen_dict["$WIDTH$"] = str(in_width) + code_gen_dict["$DEPTH$"] = str(self.get_nodeattr("depth")) + # apply code generation to templates + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + with open(template_path, "r") as f: + template = f.read() + for key_name in code_gen_dict: + key = "%s" % key_name + template = template.replace(key, str(code_gen_dict[key_name])) + with open( + os.path.join(code_gen_dir, self.get_verilog_top_module_name() + ".v"), + "w", + ) as f: + f.write(template) + + shutil.copy(rtlsrc + "/Q_srl.v", code_gen_dir) + # set ipgen_path and ip_path so that HLS-Synth transformation + # and stich_ip transformation do not complain + self.set_nodeattr("ipgen_path", code_gen_dir) + self.set_nodeattr("ip_path", code_gen_dir) + + def execute_node(self, context, graph): + mode = self.get_nodeattr("exec_mode") + node = self.onnx_node + inp = context[node.input[0]] + exp_shape = self.get_normal_input_shape() + + if mode == "cppsim": + output = inp + output = np.asarray([output], dtype=np.float32).reshape(*exp_shape) + context[node.output[0]] = output + elif mode == "rtlsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + # create a npy file for the input of the node + assert ( + str(inp.dtype) == "float32" + ), """Input datatype is + not float32 as expected.""" + expected_inp_shape = self.get_folded_input_shape() + reshaped_input = inp.reshape(expected_inp_shape) + if DataType[self.get_nodeattr("dataType")] == DataType["BIPOLAR"]: + # store bipolar activations as binary + reshaped_input = (reshaped_input + 1) / 2 + export_idt = DataType["BINARY"] + else: + export_idt = DataType[self.get_nodeattr("dataType")] + # make copy before saving the array + reshaped_input = reshaped_input.copy() + np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input) + sim = self.get_rtlsim() + nbits = self.get_instream_width() + inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) + super().reset_rtlsim(sim) + super().toggle_clk(sim) + output = self.rtlsim(sim, inp) + odt = DataType[self.get_nodeattr("dataType")] + target_bits = odt.bitwidth() + packed_bits = self.get_outstream_width() + out_npy_path = "{}/output.npy".format(code_gen_dir) + out_shape = self.get_folded_output_shape() + rtlsim_output_to_npy(output, out_npy_path, odt, out_shape, packed_bits, target_bits) + # load and reshape output + output = np.load(out_npy_path) + oshape = self.get_normal_output_shape() + output = np.asarray([output], dtype=np.float32).reshape(*oshape) + context[node.output[0]] = output + + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + + def code_generation_ipi(self): + impl_style = self.get_nodeattr("impl_style") + if impl_style == "rtl": + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + + sourcefiles = [ + "Q_srl.v", + self.get_nodeattr("gen_top_module") + ".v", + ] + + sourcefiles = [os.path.join(code_gen_dir, f) for f in sourcefiles] + + cmd = [] + for f in sourcefiles: + cmd += ["add_files -norecurse %s" % (f)] + cmd += [ + "create_bd_cell -type module -reference %s %s" + % (self.get_nodeattr("gen_top_module"), self.onnx_node.name) + ] + return cmd + elif impl_style == "vivado": + cmd = [] + node_name = self.onnx_node.name + depth = self.get_adjusted_depth() + ram_style = self.get_nodeattr("ram_style") + # create a hierarchy for this layer, with the same port names + clk_name = self.get_verilog_top_module_intf_names()["clk"][0] + rst_name = self.get_verilog_top_module_intf_names()["rst"][0] + dout_name = self.get_verilog_top_module_intf_names()["m_axis"][0][0] + din_name = self.get_verilog_top_module_intf_names()["s_axis"][0][0] + cmd.append("create_bd_cell -type hier %s" % node_name) + cmd.append("create_bd_pin -dir I -type clk /%s/%s" % (node_name, clk_name)) + cmd.append("create_bd_pin -dir I -type rst /%s/%s" % (node_name, rst_name)) + cmd.append( + "create_bd_intf_pin -mode Master " + "-vlnv xilinx.com:interface:axis_rtl:1.0 /%s/%s" % (node_name, dout_name) + ) + cmd.append( + "create_bd_intf_pin -mode Slave " + "-vlnv xilinx.com:interface:axis_rtl:1.0 /%s/%s" % (node_name, din_name) + ) + # instantiate and configure DWC + cmd.append( + "create_bd_cell -type ip " + "-vlnv xilinx.com:ip:axis_data_fifo:2.0 /%s/fifo" % node_name + ) + cmd.append( + "set_property -dict [list CONFIG.FIFO_DEPTH {%d}] " + "[get_bd_cells /%s/fifo]" % (depth, node_name) + ) + cmd.append( + "set_property -dict [list CONFIG.FIFO_MEMORY_TYPE {%s}] " + "[get_bd_cells /%s/fifo]" % (ram_style, node_name) + ) + cmd.append( + "set_property -dict [list CONFIG.TDATA_NUM_BYTES {%d}] " + "[get_bd_cells /%s/fifo]" % (np.ceil(self.get_outstream_width() / 8), node_name) + ) + cmd.append( + "connect_bd_intf_net [get_bd_intf_pins %s/fifo/M_AXIS] " + "[get_bd_intf_pins %s/%s]" % (node_name, node_name, dout_name) + ) + cmd.append( + "connect_bd_intf_net [get_bd_intf_pins %s/fifo/S_AXIS] " + "[get_bd_intf_pins %s/%s]" % (node_name, node_name, din_name) + ) + cmd.append( + "connect_bd_net [get_bd_pins %s/%s] " + "[get_bd_pins %s/fifo/s_axis_aresetn]" % (node_name, rst_name, node_name) + ) + cmd.append( + "connect_bd_net [get_bd_pins %s/%s] " + "[get_bd_pins %s/fifo/s_axis_aclk]" % (node_name, clk_name, node_name) + ) + return cmd + else: + raise Exception( + "FIFO implementation style %s not supported, please use rtl or vivado" % impl_style + ) + + def prepare_rtlsim(self): + assert self.get_nodeattr("impl_style") != "vivado", ( + "StreamingFIFO impl_style " + "cannot be vivado for rtlsim. Only impl_style=rtl supported." + ) + # Modified to use generated (System-)Verilog instead of HLS output products + + if PyVerilator is None: + raise ImportError("Installation of PyVerilator is required.") + + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + verilog_paths = [code_gen_dir] + verilog_files = [ + "Q_srl.v", + self.get_nodeattr("gen_top_module") + ".v", + ] + # build the Verilator emu library + sim = PyVerilator.build( + verilog_files, + build_dir=make_build_dir("pyverilator_" + self.onnx_node.name + "_"), + verilog_path=verilog_paths, + trace_depth=get_rtlsim_trace_depth(), + top_module_name=self.get_verilog_top_module_name(), + ) + # save generated lib filename in attribute + self.set_nodeattr("rtlsim_so", sim.lib._name) + return sim diff --git a/src/finn/custom_op/fpgadataflow/streamingfifo.py b/src/finn/custom_op/fpgadataflow/streamingfifo.py index 1249bc1251..950574ba0a 100644 --- a/src/finn/custom_op/fpgadataflow/streamingfifo.py +++ b/src/finn/custom_op/fpgadataflow/streamingfifo.py @@ -1,4 +1,4 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -27,23 +27,15 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import math import numpy as np -import os -import subprocess import warnings from qonnx.core.datatype import DataType -from shutil import copy -from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp -from finn.util.basic import get_finn_root -from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy +from finn.custom_op.fpgadataflow.hwcustomop import HWCustomOp -from . import templates - -class StreamingFIFO(HLSCustomOp): +class StreamingFIFO(HWCustomOp): def __init__(self, onnx_node, **kwargs): super().__init__(onnx_node, **kwargs) - self.strm_fifo_wrapper = templates.strm_fifo_wrapper def get_nodeattr_types(self): my_attrs = super().get_nodeattr_types() @@ -55,10 +47,6 @@ def get_nodeattr_types(self): "folded_shape": ("ints", True, []), # FINN DataTypes for inputs/outputs "dataType": ("s", True, ""), - # Toggle between hls or IPI implementation - # rtl - use the hls generated IP during stitching - # vivado - use the AXI Infrastructure FIFO - "impl_style": ("s", False, "rtl", {"rtl", "vivado"}), # FPGA resource type for FIFOs when impl_style is vivado # auto -- let Vivado decide # block -- use BRAM @@ -80,22 +68,6 @@ def get_nodeattr_types(self): return my_attrs - def get_adjusted_depth(self): - impl = self.get_nodeattr("impl_style") - depth = self.get_nodeattr("depth") - if impl == "vivado": - old_depth = depth - # round up depth to nearest power-of-2 - # Vivado FIFO impl may fail otherwise - depth = (1 << (depth - 1).bit_length()) if impl == "vivado" else depth - if old_depth != depth: - warnings.warn( - "%s: rounding-up FIFO depth from %d to %d for impl_style=vivado" - % (self.onnx_node.name, old_depth, depth) - ) - - return depth - def make_shape_compatible_op(self, model): exp_ishape = self.get_normal_input_shape() oshape = self.get_normal_output_shape() @@ -128,85 +100,6 @@ def get_verilog_top_module_intf_names(self): ret["ap_none"] = ["maxcount"] return ret - def get_verilog_top_module_name(self): - "Return the Verilog top module name for this node." - - node = self.onnx_node - prefixed_top_name = "%s" % (node.name) - return prefixed_top_name - - def code_generation_ipgen(self, model, fpgapart, clk): - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - verilog_dir = "{}/project_{}/sol1/impl/verilog".format(code_gen_dir, self.onnx_node.name) - os.makedirs(verilog_dir) - # copy Q_srl.v from finn-rtllib to verilog directory - memstream_dir = get_finn_root() + "/finn-rtllib/memstream/hdl/" - Q_file = os.path.join(memstream_dir, "Q_srl.v") - copy(Q_file, verilog_dir) - - # empty code gen dictionary for new entries - self.code_gen_dict.clear() - self.code_gen_dict["$TOPNAME$"] = ["{}".format(self.onnx_node.name)] - self.code_gen_dict["$LAYER_NAME$"] = [ - "{}_{}".format(self.onnx_node.name, self.onnx_node.name) - ] - # make instream width a multiple of 8 for axi interface - in_width = self.get_instream_width_padded() - count_width = int(self.get_nodeattr("depth") - 1).bit_length() - self.code_gen_dict["$COUNT_RANGE$"] = ["[{}:0]".format(count_width - 1)] - self.code_gen_dict["$IN_RANGE$"] = ["[{}:0]".format(in_width - 1)] - self.code_gen_dict["$OUT_RANGE$"] = ["[{}:0]".format(in_width - 1)] - self.code_gen_dict["$WIDTH$"] = [str(in_width)] - self.code_gen_dict["$DEPTH$"] = [str(self.get_nodeattr("depth"))] - self.code_gen_dict["$HLS_SNAME$"] = [self.hls_sname()] - - template = self.strm_fifo_wrapper - - for key in self.code_gen_dict: - # transform list into long string separated by '\n' - code_gen_line = "\n".join(self.code_gen_dict[key]) - template = template.replace(key, code_gen_line) - f = open(os.path.join(verilog_dir, "{}.v".format(self.onnx_node.name)), "w") - f.write(template) - f.close() - self.code_gen_dict.clear() - - def ipgen_singlenode_code(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - verilog_dir = "{}/project_{}/sol1/impl/verilog".format(code_gen_dir, self.onnx_node.name) - # prepare the IP packaging tcl template - template = templates.ip_package_tcl - self.code_gen_dict.clear() - self.code_gen_dict["$TOPNAME$"] = ["{}".format(self.onnx_node.name)] - # note: setting the root dir as absolute can cause path problems - # the ipgen script will be invoked from the sources dir so root_dir=. is OK - self.code_gen_dict["$VERILOG_DIR$"] = ["."] - self.code_gen_dict["$HLS_SNAME$"] = [self.hls_sname()] - for key in self.code_gen_dict: - # transform list into long string separated by '\n' - code_gen_line = "\n".join(self.code_gen_dict[key]) - template = template.replace(key, code_gen_line) - f = open(os.path.join(verilog_dir, "package_ip.tcl"), "w") - f.write(template) - f.close() - # create a shell script and call Vivado to invoke the IP pkg script - make_project_sh = verilog_dir + "/make_ip.sh" - working_dir = os.environ["PWD"] - with open(make_project_sh, "w") as f: - f.write("#!/bin/bash \n") - f.write("cd {}\n".format(verilog_dir)) - f.write("vivado -mode batch -source package_ip.tcl\n") - f.write("cd {}\n".format(working_dir)) - bash_command = ["bash", make_project_sh] - process_compile = subprocess.Popen(bash_command, stdout=subprocess.PIPE) - process_compile.communicate() - # set ipgen_path and ip_path to point to the new packaged IP - self.set_nodeattr("ipgen_path", verilog_dir) - self.set_nodeattr("ip_path", verilog_dir) - vlnv = "xilinx.com:hls:%s:1.0" % (self.onnx_node.name) - self.set_nodeattr("ip_vlnv", vlnv) - self.code_gen_dict.clear() - def get_normal_input_shape(self, ind=0): depth = self.get_adjusted_depth() assert depth >= 2, """Depth is too low""" @@ -262,154 +155,13 @@ def get_output_datatype(self, ind=0): return DataType[self.get_nodeattr("dataType")] def execute_node(self, context, graph): - mode = self.get_nodeattr("exec_mode") node = self.onnx_node - inp = context[node.input[0]] - exp_shape = self.get_normal_input_shape() - - if mode == "cppsim": - output = inp - output = np.asarray([output], dtype=np.float32).reshape(*exp_shape) - context[node.output[0]] = output - elif mode == "rtlsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - # create a npy file for the input of the node - assert ( - str(inp.dtype) == "float32" - ), """Input datatype is - not float32 as expected.""" - expected_inp_shape = self.get_folded_input_shape() - reshaped_input = inp.reshape(expected_inp_shape) - if DataType[self.get_nodeattr("dataType")] == DataType["BIPOLAR"]: - # store bipolar activations as binary - reshaped_input = (reshaped_input + 1) / 2 - export_idt = DataType["BINARY"] - else: - export_idt = DataType[self.get_nodeattr("dataType")] - # make copy before saving the array - reshaped_input = reshaped_input.copy() - np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input) - sim = self.get_rtlsim() - nbits = self.get_instream_width() - inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) - super().reset_rtlsim(sim) - super().toggle_clk(sim) - output = self.rtlsim(sim, inp) - odt = DataType[self.get_nodeattr("dataType")] - target_bits = odt.bitwidth() - packed_bits = self.get_outstream_width() - out_npy_path = "{}/output.npy".format(code_gen_dir) - out_shape = self.get_folded_output_shape() - rtlsim_output_to_npy(output, out_npy_path, odt, out_shape, packed_bits, target_bits) - # load and reshape output - output = np.load(out_npy_path) - oshape = self.get_normal_output_shape() - output = np.asarray([output], dtype=np.float32).reshape(*oshape) - context[node.output[0]] = output - - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) + context[node.output[0]] = context[node.input[0]] def get_number_output_values(self): folded_oshape = self.get_folded_output_shape() return np.prod(folded_oshape[:-1]) - def global_includes(self): - pass - - def defines(self, var): - pass - - def read_npy_data(self): - pass - - def strm_decl(self): - pass - - def docompute(self): - pass - - def dataoutstrm(self): - pass - - def save_as_npy(self): - pass - - def blackboxfunction(self): - pass - - def pragmas(self): - pass - - def code_generation_ipi(self): - impl_style = self.get_nodeattr("impl_style") - if impl_style == "rtl": - return super().code_generation_ipi() - elif impl_style == "vivado": - cmd = [] - node_name = self.onnx_node.name - depth = self.get_adjusted_depth() - ram_style = self.get_nodeattr("ram_style") - # create a hierarchy for this layer, with the same port names - clk_name = self.get_verilog_top_module_intf_names()["clk"][0] - rst_name = self.get_verilog_top_module_intf_names()["rst"][0] - dout_name = self.get_verilog_top_module_intf_names()["m_axis"][0][0] - din_name = self.get_verilog_top_module_intf_names()["s_axis"][0][0] - cmd.append("create_bd_cell -type hier %s" % node_name) - cmd.append("create_bd_pin -dir I -type clk /%s/%s" % (node_name, clk_name)) - cmd.append("create_bd_pin -dir I -type rst /%s/%s" % (node_name, rst_name)) - cmd.append( - "create_bd_intf_pin -mode Master " - "-vlnv xilinx.com:interface:axis_rtl:1.0 /%s/%s" % (node_name, dout_name) - ) - cmd.append( - "create_bd_intf_pin -mode Slave " - "-vlnv xilinx.com:interface:axis_rtl:1.0 /%s/%s" % (node_name, din_name) - ) - # instantiate and configure DWC - cmd.append( - "create_bd_cell -type ip " - "-vlnv xilinx.com:ip:axis_data_fifo:2.0 /%s/fifo" % node_name - ) - cmd.append( - "set_property -dict [list CONFIG.FIFO_DEPTH {%d}] " - "[get_bd_cells /%s/fifo]" % (depth, node_name) - ) - cmd.append( - "set_property -dict [list CONFIG.FIFO_MEMORY_TYPE {%s}] " - "[get_bd_cells /%s/fifo]" % (ram_style, node_name) - ) - cmd.append( - "set_property -dict [list CONFIG.TDATA_NUM_BYTES {%d}] " - "[get_bd_cells /%s/fifo]" % (np.ceil(self.get_outstream_width() / 8), node_name) - ) - cmd.append( - "connect_bd_intf_net [get_bd_intf_pins %s/fifo/M_AXIS] " - "[get_bd_intf_pins %s/%s]" % (node_name, node_name, dout_name) - ) - cmd.append( - "connect_bd_intf_net [get_bd_intf_pins %s/fifo/S_AXIS] " - "[get_bd_intf_pins %s/%s]" % (node_name, node_name, din_name) - ) - cmd.append( - "connect_bd_net [get_bd_pins %s/%s] " - "[get_bd_pins %s/fifo/s_axis_aresetn]" % (node_name, rst_name, node_name) - ) - cmd.append( - "connect_bd_net [get_bd_pins %s/%s] " - "[get_bd_pins %s/fifo/s_axis_aclk]" % (node_name, clk_name, node_name) - ) - return cmd - else: - raise Exception( - "FIFO implementation style %s not supported, please use rtl or vivado" % impl_style - ) - def bram_estimation(self): """Calculates resource estimation for BRAM""" impl = self.get_nodeattr("impl_style") @@ -473,10 +225,3 @@ def lut_estimation(self): ram_luts = 0 return int(address_luts + ram_luts) - - def prepare_rtlsim(self): - assert self.get_nodeattr("impl_style") != "vivado", ( - "StreamingFIFO impl_style " - "cannot be vivado for rtlsim. Only impl_style=rtl supported." - ) - super().prepare_rtlsim() diff --git a/src/finn/custom_op/fpgadataflow/templates.py b/src/finn/custom_op/fpgadataflow/templates.py index 4e03e6daf9..3d89a0ab23 100644 --- a/src/finn/custom_op/fpgadataflow/templates.py +++ b/src/finn/custom_op/fpgadataflow/templates.py @@ -212,49 +212,3 @@ ipx::save_core [ipx::current_core] ipx::archive_core $Top.zip [ipx::current_core] """ - -strm_fifo_wrapper = """ -module $TOPNAME$( -ap_clk, -ap_rst_n, -count, -maxcount, -in0_$HLS_SNAME$_TDATA, -in0_$HLS_SNAME$_TVALID, -in0_$HLS_SNAME$_TREADY, -out_$HLS_SNAME$_TDATA, -out_$HLS_SNAME$_TVALID, -out_$HLS_SNAME$_TREADY -); - -input ap_clk; -input ap_rst_n; -output $COUNT_RANGE$ count; -output $COUNT_RANGE$ maxcount; -input $IN_RANGE$ in0_$HLS_SNAME$_TDATA; -input in0_$HLS_SNAME$_TVALID; -output in0_$HLS_SNAME$_TREADY; -output $OUT_RANGE$ out_$HLS_SNAME$_TDATA; -output out_$HLS_SNAME$_TVALID; -input out_$HLS_SNAME$_TREADY; - -Q_srl #( -.depth($DEPTH$), -.width($WIDTH$) -) -$LAYER_NAME$ -( - .clock(ap_clk), - .reset(!ap_rst_n), - .count(count), - .maxcount(maxcount), - .i_d(in0_$HLS_SNAME$_TDATA), - .i_v(in0_$HLS_SNAME$_TVALID), - .i_r(in0_$HLS_SNAME$_TREADY), - .o_d(out_$HLS_SNAME$_TDATA), - .o_v(out_$HLS_SNAME$_TVALID), - .o_r(out_$HLS_SNAME$_TREADY) -); - -endmodule -""" diff --git a/tests/fpgadataflow/test_fpgadataflow_fifo.py b/tests/fpgadataflow/test_fpgadataflow_fifo.py index 27417a78e1..ecbf867b69 100644 --- a/tests/fpgadataflow/test_fpgadataflow_fifo.py +++ b/tests/fpgadataflow/test_fpgadataflow_fifo.py @@ -40,6 +40,7 @@ from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers build_dir = os.environ["FINN_BUILD_DIR"] test_fpga_part = "xc7z020clg400-1" @@ -83,7 +84,7 @@ def prepare_inputs(input_tensor, dt): # outWidth @pytest.mark.parametrize("depth", [16]) # finn_dtype -@pytest.mark.parametrize("finn_dtype", [DataType["BIPOLAR"]]) # , DataType["INT2"]]) +@pytest.mark.parametrize("finn_dtype", [DataType["BIPOLAR"], DataType["INT2"]]) @pytest.mark.fpgadataflow @pytest.mark.slow @pytest.mark.vivado @@ -93,6 +94,7 @@ def test_fpgadataflow_fifo_rtlsim(Shape, folded_shape, depth, finn_dtype): input_dict = prepare_inputs(x, finn_dtype) model = make_single_fifo_modelwrapper(Shape, depth, folded_shape, finn_dtype) + model = model.transform(SpecializeLayers()) model = model.transform(SetExecMode("rtlsim")) model = model.transform(GiveUniqueNodeNames()) From dddef235f3cfe93623faab864d1a97f304706424 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Fri, 26 Jan 2024 14:26:09 +0000 Subject: [PATCH 410/665] [BTS] Infer bts Signed-off-by: aziz bahri --- .../hls/thresholdingbinarysearch_hls.py | 2 +- .../fpgadataflow/thresholding_batch.py | 4 +- .../fpgadataflow/convert_to_hw_layers.py | 118 +++++++ ...fpgadataflow_thresholding_binary_search.py | 287 ++++++++++-------- 4 files changed, 278 insertions(+), 133 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/hls/thresholdingbinarysearch_hls.py b/src/finn/custom_op/fpgadataflow/hls/thresholdingbinarysearch_hls.py index a782b21800..97ffc59f7a 100644 --- a/src/finn/custom_op/fpgadataflow/hls/thresholdingbinarysearch_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/thresholdingbinarysearch_hls.py @@ -58,7 +58,7 @@ class ThresholdingBinarySearch_hls(ThresholdingBinarySearch,HLSBackend): def __init__(self, onnx_node, **kwargs): super().__init__(onnx_node, **kwargs) - + def get_nodeattr_types(self): my_attrs = {} my_attrs.update(ThresholdingBinarySearch.get_nodeattr_types(self)) diff --git a/src/finn/custom_op/fpgadataflow/thresholding_batch.py b/src/finn/custom_op/fpgadataflow/thresholding_batch.py index 72ee2f7af6..37c51300a3 100644 --- a/src/finn/custom_op/fpgadataflow/thresholding_batch.py +++ b/src/finn/custom_op/fpgadataflow/thresholding_batch.py @@ -1,4 +1,4 @@ -# Copyright (c) 2020, Xilinx +# Copyright (c) 2024, Xilinx # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -31,6 +31,8 @@ import textwrap import warnings from math import ceil, log2 +from finn.custom_op.fpgadataflow.fmpadding import FMPadding +from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend from qonnx.core.datatype import DataType from qonnx.util.basic import ( interleave_matrix_outer_dim_from_partitions, diff --git a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py index 2b8433e59c..aacedcc6f2 100644 --- a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py +++ b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py @@ -180,7 +180,125 @@ def apply(self, model): model = model.transform(InferDataTypes()) return (model, graph_modified) +class InferThresholdingLayer(Transformation): + """Convert any MultiThreshold into a standalone thresholding HLS layer.""" + def __init__(self, mem_mode="const", use_rtl_variant=False): + super().__init__() + self.mem_mode = mem_mode + self.use_rtl_variant = use_rtl_variant + + def apply(self, model): + graph = model.graph + node_ind = 0 + graph_modified = False + for node in graph.node: + node_ind += 1 + if node.op_type == "MultiThreshold": + thl_input = node.input[0] + thl_threshold = node.input[1] + thl_output = node.output[0] + thl_in_shape = model.get_tensor_shape(thl_input) + thl_thres_shape = model.get_tensor_shape(thl_threshold) + idt = model.get_tensor_datatype(thl_input) + + # skip conversion for layers with float input + if not idt.is_integer(): + continue + + # check layout of inputs/outputs, and convert if needed + # check layout and convert if necessary + thl_in_layout = model.get_tensor_layout(thl_input) + if thl_in_layout == DataLayout.NCHW: + thl_input = nchw_to_nhwc(thl_input, model, node_ind) + node_ind += 1 + thl_in_shape = model.get_tensor_shape(thl_input) + + # keep track of where we need to insert the HLS Op + # it has to be ahead of the output transform + insert_point = node_ind + thl_output_layout = model.get_tensor_layout(thl_output) + if thl_output_layout == DataLayout.NCHW: + thl_output = nchw_to_nhwc(thl_output, model, node_ind, reverse=True) + node_ind += 1 + + # now safe to assume number of channels is in last dimension + ifc = int(thl_in_shape[-1]) + # create node with no parallelization first + pe = 1 + + odt = model.get_tensor_datatype(thl_output) + scale = getCustomOp(node).get_nodeattr("out_scale") + assert scale == 1.0, ( + node.name + ": MultiThreshold out_scale must be 1 for HLS conversion." + ) + actval = getCustomOp(node).get_nodeattr("out_bias") + assert int(actval) == actval, ( + node.name + ": MultiThreshold out_bias must be integer for HLS conversion." + ) + actval = int(actval) + assert (not odt.signed()) or (actval < 0), ( + node.name + ": Signed output requires actval < 0" + ) + + # Ensure that RTL variant is not inserted for unsupported configuration + is_rtl_variant_compatible = True + + # Perform checks for RTL variant if chosen + if self.use_rtl_variant and is_rtl_variant_compatible: + new_node = helper.make_node( + "Thresholding_Binary_Search", + [thl_input, thl_threshold], + [thl_output], + domain="finn.custom_op.fpgadataflow", + backend="fpgadataflow", + NumChannels=ifc, + PE=pe, + numSteps=thl_thres_shape[1], + inputDataType=idt.name, + weightDataType=idt.name, + outputDataType=odt.name, + numInputVectors=list(thl_in_shape[:-1]), + activation_bias=actval, + mem_mode=self.mem_mode, + name="Thresholding_Binary_Search_" + node.name, + ) + else: + if self.use_rtl_variant: + warnings.warn( + """%s : RTL Thresholding requested for unsupported + configuration. Falling back to HLS implementation.""" + % node.name + ) + + # create and insert new Thresholding_Batch node + new_node = helper.make_node( + "Thresholding_Batch", + [thl_input, thl_threshold], + [thl_output], + domain="finn.custom_op.fpgadataflow", + backend="fpgadataflow", + NumChannels=ifc, + PE=pe, + numSteps=thl_thres_shape[1], + inputDataType=idt.name, + weightDataType=idt.name, + outputDataType=odt.name, + numInputVectors=list(thl_in_shape[:-1]), + ActVal=actval, + mem_mode=self.mem_mode, + name="Thresholding_Batch_" + node.name, + ) + + graph.node.insert(insert_point, new_node) + # remove old node + graph.node.remove(node) + graph_modified = True + + if graph_modified: + model = model.transform(InferShapes()) + model = model.transform(InferDataTypes()) + return (model, graph_modified) class InferUpsample(Transformation): """Convert Upsample and Resize nodes to layers to UpsampleNearestNeighbour nodes.""" diff --git a/tests/fpgadataflow/test_fpgadataflow_thresholding_binary_search.py b/tests/fpgadataflow/test_fpgadataflow_thresholding_binary_search.py index 8e6bf5cbe3..c247e9cdfc 100755 --- a/tests/fpgadataflow/test_fpgadataflow_thresholding_binary_search.py +++ b/tests/fpgadataflow/test_fpgadataflow_thresholding_binary_search.py @@ -37,15 +37,19 @@ from qonnx.custom_op.registry import getCustomOp from qonnx.transformation.general import GiveUniqueNodeNames from qonnx.util.basic import gen_finn_dt_tensor - +from qonnx.transformation.infer_shapes import InferShapes +from finn.transformation.fpgadataflow.convert_to_hw_layers import InferThresholdingLayer from finn.core.rtlsim_exec import rtlsim_exec from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP +from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP +from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim from finn.transformation.fpgadataflow.insert_fifo import InsertFIFO from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers +import finn.core.onnx_exec as oxe test_fpga_part = "xczu3eg-sbva484-1-e" target_clk_ns = 5 @@ -141,50 +145,50 @@ def make_single_thresholding_binary_search_modelwrapper( return model -# Test brief: Test that PrepareRTLSim() runs successfully. This function is not -# tested in test_fpgadataflow_thresholding_binary_search() -@pytest.mark.fpgadataflow -@pytest.mark.vivado -def test_fpgadataflow_thresholding_binary_search_prepare_rtlsim(): - input_data_type = DataType["INT16"] - act = DataType["INT4"] - fold = -1 - num_input_channels = 16 - - # Handle inputs to the test - pe = generate_pe_value(fold, num_input_channels) - num_steps = act.get_num_possible_values() - 1 - - # Generate random, non-decreasing thresholds - thresholds = generate_random_threshold_values( - input_data_type, num_input_channels, num_steps - ) - thresholds = sort_thresholds_increasing(thresholds) - - # Other non-input parameters - num_input_vecs = [1, 2, 2] - output_data_type = act - if output_data_type == DataType["BIPOLAR"]: - activation_bias = 0 - else: - activation_bias = output_data_type.min() - - # Generate model from input parameters to the test - model = make_single_thresholding_binary_search_modelwrapper( - thresholds, - pe, - input_data_type, - output_data_type, - activation_bias, - num_input_vecs, - ) - - model = model.transform(SetExecMode("rtlsim")) - model = model.transform(GiveUniqueNodeNames()) - model = model.transform(PrepareIP(test_fpga_part, target_clk_ns)) - model = model.transform(HLSSynthIP()) - model = model.transform(PrepareRTLSim()) - return +# # Test brief: Test that PrepareRTLSim() runs successfully. This function is not +# # tested in test_fpgadataflow_thresholding_binary_search() +# @pytest.mark.fpgadataflow +# @pytest.mark.vivado +# def test_fpgadataflow_thresholding_binary_search_prepare_rtlsim(): +# input_data_type = DataType["INT16"] +# act = DataType["INT4"] +# fold = -1 +# num_input_channels = 16 + +# # Handle inputs to the test +# pe = generate_pe_value(fold, num_input_channels) +# num_steps = act.get_num_possible_values() - 1 + +# # Generate random, non-decreasing thresholds +# thresholds = generate_random_threshold_values( +# input_data_type, num_input_channels, num_steps +# ) +# thresholds = sort_thresholds_increasing(thresholds) + +# # Other non-input parameters +# num_input_vecs = [1, 2, 2] +# output_data_type = act +# if output_data_type == DataType["BIPOLAR"]: +# activation_bias = 0 +# else: +# activation_bias = output_data_type.min() + +# # Generate model from input parameters to the test +# model = make_single_thresholding_binary_search_modelwrapper( +# thresholds, +# pe, +# input_data_type, +# output_data_type, +# activation_bias, +# num_input_vecs, +# ) + +# model = model.transform(SetExecMode("rtlsim")) +# model = model.transform(GiveUniqueNodeNames()) +# model = model.transform(PrepareIP(test_fpga_part, target_clk_ns)) +# model = model.transform(HLSSynthIP()) +# model = model.transform(PrepareRTLSim()) +# return # Test brief: Create a Thresholding binary search layer using various parameters @@ -194,11 +198,13 @@ def test_fpgadataflow_thresholding_binary_search_prepare_rtlsim(): @pytest.mark.parametrize("input_data_type", [DataType["INT16"], DataType["UINT16"]]) @pytest.mark.parametrize("fold", [-1, 1, 2, 4, 6]) @pytest.mark.parametrize("num_input_channels", [16]) +@pytest.mark.parametrize("impl_style", ["rtl", "hls"]) +@pytest.mark.parametrize("mode", ["cppsim", "rtlsim"]) @pytest.mark.fpgadataflow @pytest.mark.vivado @pytest.mark.slow def test_fpgadataflow_thresholding_binary_search( - activation, input_data_type, fold, num_input_channels + activation, input_data_type, fold, num_input_channels, impl_style, mode ): # Handle inputs to the test pe = generate_pe_value(fold, num_input_channels) @@ -236,88 +242,6 @@ def test_fpgadataflow_thresholding_binary_search( # signed offset y += activation.min() - # Generate model from input parameters to the test - model = make_single_thresholding_binary_search_modelwrapper( - thresholds, - pe, - input_data_type, - output_data_type, - activation_bias, - num_input_vecs, - ) - - model = model.transform(InsertFIFO(True)) - model = model.transform(GiveUniqueNodeNames()) - model = model.transform(PrepareIP(test_fpga_part, target_clk_ns)) - model = model.transform(HLSSynthIP()) - model = model.transform(CreateStitchedIP(test_fpga_part, target_clk_ns)) - - # Retrieve the axilite programming sequence for weights - for decoupled mode only - tbs_node = model.get_nodes_by_op_type("Thresholding_Binary_Search")[0] - tbs_inst = getCustomOp(tbs_node) - config = tbs_inst.get_dynamic_config(model, 4) - - # Reshape generated data (not from model) - oshape = model.get_tensor_shape("outp") - y_expected = y.reshape(oshape) - - # Helper function that delivers the hook to program the thresholds via AXI-Lite - def config_hook(config): - if config is None: - return None - - def write_thresh_config(sim): - # axi_name = "s_axilite_0_" # works - axi_name = getCustomOp( - model.get_nodes_by_op_type("Thresholding_Binary_Search")[0] - ).get_verilog_top_module_intf_names()["axilite"][0] - axi_name += "_0_" - - # Write config registers to the Threshold memory. - # The dictionary defines (addr, value) tuples. - for config_entry in config.values(): - addr = config_entry[0] - val = config_entry[1] - axilite_write(sim, addr, val, basename=axi_name) - - reset_rtlsim(sim) - - return write_thresh_config - - input_dict = {"inp": x} - rtlsim_exec(model, input_dict, pre_hook=config_hook(config)) - y_produced = input_dict["outp"] - assert (y_produced == y_expected).all() - - -# Test brief: Test basic transforms are working -@pytest.mark.parametrize("impl_style", ["rtl", "hls"]) -@pytest.mark.fpgadataflow -@pytest.mark.vivado -def test_fpgadataflow_thresholding_binary_search_transform(impl_style): - input_data_type = DataType["INT16"] - act = DataType["INT4"] - fold = -1 - num_input_channels = 16 - - # Handle inputs to the test - pe = generate_pe_value(fold, num_input_channels) - num_steps = act.get_num_possible_values() - 1 - - # Generate random, non-decreasing thresholds - thresholds = generate_random_threshold_values( - input_data_type, num_input_channels, num_steps - ) - thresholds = sort_thresholds_increasing(thresholds) - - # Other non-input parameters - num_input_vecs = [1, 2, 2] - output_data_type = act - if output_data_type == DataType["BIPOLAR"]: - activation_bias = 0 - else: - activation_bias = output_data_type.min() - # Generate model from input parameters to the test model = make_single_thresholding_binary_search_modelwrapper( impl_style, @@ -329,10 +253,111 @@ def test_fpgadataflow_thresholding_binary_search_transform(impl_style): num_input_vecs, ) + model = model.transform(InferThresholdingLayer()) model = model.transform(SpecializeLayers()) - # model = model.transform(SetExecMode("rtlsim")) + model = model.transform(InferShapes()) + # model = model.transform(SetExecMode(mode)) + # model = model.transform(GiveUniqueNodeNames()) + # if mode == "cppsim": + # model = model.transform(PrepareCppSim()) + # model = model.transform(CompileCppSim()) + # elif mode == "rtlsim": + # model = model.transform(PrepareIP(test_fpga_part, target_clk_ns)) + # model = model.transform(HLSSynthIP()) + # model = model.transform(PrepareRTLSim()) + # input_dict = {"inp": x} + # y_produced = oxe.execute_onnx(model, input_dict)["outp"] + + # model = model.transform(InsertFIFO(True)) # model = model.transform(GiveUniqueNodeNames()) # model = model.transform(PrepareIP(test_fpga_part, target_clk_ns)) # model = model.transform(HLSSynthIP()) - # model = model.transform(PrepareRTLSim()) - return \ No newline at end of file + # model = model.transform(CreateStitchedIP(test_fpga_part, target_clk_ns)) + + # # Retrieve the axilite programming sequence for weights - for decoupled mode only + # tbs_node = model.get_nodes_by_op_type("Thresholding_Binary_Search")[0] + # tbs_inst = getCustomOp(tbs_node) + # config = tbs_inst.get_dynamic_config(model, 4) + + # # Reshape generated data (not from model) + # oshape = model.get_tensor_shape("outp") + # y_expected = y.reshape(oshape) + + # # Helper function that delivers the hook to program the thresholds via AXI-Lite + # def config_hook(config): + # if config is None: + # return None + + # def write_thresh_config(sim): + # # axi_name = "s_axilite_0_" # works + # axi_name = getCustomOp( + # model.get_nodes_by_op_type("Thresholding_Binary_Search")[0] + # ).get_verilog_top_module_intf_names()["axilite"][0] + # axi_name += "_0_" + + # # Write config registers to the Threshold memory. + # # The dictionary defines (addr, value) tuples. + # for config_entry in config.values(): + # addr = config_entry[0] + # val = config_entry[1] + # axilite_write(sim, addr, val, basename=axi_name) + + # reset_rtlsim(sim) + + # return write_thresh_config + + # input_dict = {"inp": x} + # rtlsim_exec(model, input_dict, pre_hook=config_hook(config)) + # y_produced = input_dict["outp"] + # assert (y_produced == y_expected).all() + + +# # Test brief: Test basic transforms are working +# @pytest.mark.parametrize("impl_style", ["rtl", "hls"]) +# @pytest.mark.fpgadataflow +# @pytest.mark.vivado +# def test_fpgadataflow_thresholding_binary_search_transform(impl_style): +# input_data_type = DataType["INT16"] +# act = DataType["INT4"] +# fold = -1 +# num_input_channels = 16 + +# # Handle inputs to the test +# pe = generate_pe_value(fold, num_input_channels) +# num_steps = act.get_num_possible_values() - 1 + +# # Generate random, non-decreasing thresholds +# thresholds = generate_random_threshold_values( +# input_data_type, num_input_channels, num_steps +# ) +# thresholds = sort_thresholds_increasing(thresholds) + +# # Other non-input parameters +# num_input_vecs = [1, 2, 2] +# output_data_type = act +# if output_data_type == DataType["BIPOLAR"]: +# activation_bias = 0 +# else: +# activation_bias = output_data_type.min() + +# # Generate model from input parameters to the test +# model = make_single_thresholding_binary_search_modelwrapper( +# impl_style, +# thresholds, +# pe, +# input_data_type, +# output_data_type, +# activation_bias, +# num_input_vecs, +# ) + +# model = model.transform(SpecializeLayers()) + +# # if "hls" in getCustomOp(model.graph.node[0]).__class__.__name__ and impl_style != "hls": + +# # model = model.transform(SetExecMode("rtlsim")) +# # model = model.transform(GiveUniqueNodeNames()) +# # model = model.transform(PrepareIP(test_fpga_part, target_clk_ns)) +# # model = model.transform(HLSSynthIP()) +# # model = model.transform(PrepareRTLSim()) +# return \ No newline at end of file From b34b6265e58e2b84a376514d78b18489dacc1e0e Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Fri, 26 Jan 2024 14:38:49 +0000 Subject: [PATCH 411/665] [BTS] Rename BTS to Thresholding Signed-off-by: aziz bahri --- src/finn/custom_op/fpgadataflow/__init__.py | 6 +++--- src/finn/custom_op/fpgadataflow/hls/__init__.py | 4 ++-- ...{thresholdingbinarysearch_hls.py => thresholding_hls.py} | 6 +++--- .../{thresholdingbinarysearch.py => thresholding.py} | 2 +- .../test_fpgadataflow_thresholding_binary_search.py | 2 +- 5 files changed, 10 insertions(+), 10 deletions(-) rename src/finn/custom_op/fpgadataflow/hls/{thresholdingbinarysearch_hls.py => thresholding_hls.py} (99%) rename src/finn/custom_op/fpgadataflow/{thresholdingbinarysearch.py => thresholding.py} (99%) diff --git a/src/finn/custom_op/fpgadataflow/__init__.py b/src/finn/custom_op/fpgadataflow/__init__.py index 5260f678ef..93c1a4bd1d 100644 --- a/src/finn/custom_op/fpgadataflow/__init__.py +++ b/src/finn/custom_op/fpgadataflow/__init__.py @@ -52,8 +52,8 @@ from finn.custom_op.fpgadataflow.streamingfifo import StreamingFIFO from finn.custom_op.fpgadataflow.streamingmaxpool import StreamingMaxPool from finn.custom_op.fpgadataflow.thresholding_batch import Thresholding_Batch -from finn.custom_op.fpgadataflow.thresholdingbinarysearch import ( - ThresholdingBinarySearch, +from finn.custom_op.fpgadataflow.thresholding import ( + Thresholding, ) from finn.custom_op.fpgadataflow.tlastmarker import TLastMarker from finn.custom_op.fpgadataflow.upsampler import UpsampleNearestNeighbour @@ -66,7 +66,7 @@ custom_op["MatrixVectorActivation"] = MatrixVectorActivation custom_op["StreamingFIFO"] = StreamingFIFO custom_op["Thresholding_Batch"] = Thresholding_Batch -custom_op["ThresholdingBinarySearch"] = ThresholdingBinarySearch +custom_op["Thresholding"] = Thresholding custom_op["VectorVectorActivation"] = VectorVectorActivation custom_op["StreamingDataflowPartition"] = StreamingDataflowPartition diff --git a/src/finn/custom_op/fpgadataflow/hls/__init__.py b/src/finn/custom_op/fpgadataflow/hls/__init__.py index 74d2b982af..87611517f1 100644 --- a/src/finn/custom_op/fpgadataflow/hls/__init__.py +++ b/src/finn/custom_op/fpgadataflow/hls/__init__.py @@ -49,7 +49,7 @@ from finn.custom_op.fpgadataflow.hls.streamingmaxpool_hls import StreamingMaxPool_hls from finn.custom_op.fpgadataflow.hls.tlastmarker_hls import TLastMarker_hls from finn.custom_op.fpgadataflow.hls.upsampler_hls import UpsampleNearestNeighbour_hls -from finn.custom_op.fpgadataflow.hls.thresholdingbinarysearch_hls import ThresholdingBinarySearch_hls +from finn.custom_op.fpgadataflow.hls.thresholding_hls import Thresholding_hls custom_op = dict() @@ -72,5 +72,5 @@ custom_op["StreamingEltwise_hls"] = StreamingEltwise_hls custom_op["StreamingDataWidthConverter_hls"] = StreamingDataWidthConverter_hls custom_op["StreamingMaxPool_hls"] = StreamingMaxPool_hls -custom_op["ThresholdingBinarySearch_hls"] = ThresholdingBinarySearch_hls +custom_op["Thresholding_hls"] = Thresholding_hls custom_op["UpsampleNearestNeighbour_hls"] = UpsampleNearestNeighbour_hls diff --git a/src/finn/custom_op/fpgadataflow/hls/thresholdingbinarysearch_hls.py b/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py similarity index 99% rename from src/finn/custom_op/fpgadataflow/hls/thresholdingbinarysearch_hls.py rename to src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py index 97ffc59f7a..bb8ca582ea 100644 --- a/src/finn/custom_op/fpgadataflow/hls/thresholdingbinarysearch_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py @@ -31,7 +31,7 @@ import textwrap import warnings from math import ceil, log2 -from finn.custom_op.fpgadataflow.thresholdingbinarysearch import ThresholdingBinarySearch +from finn.custom_op.fpgadataflow.thresholding import Thresholding from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend from qonnx.core.datatype import DataType from qonnx.util.basic import ( @@ -53,7 +53,7 @@ # the ... here can be any shape (representing groups of vectors) -class ThresholdingBinarySearch_hls(ThresholdingBinarySearch,HLSBackend): +class Thresholding_hls(Thresholding,HLSBackend): """Class that corresponds to finn-hls Thresholding_Batch function.""" def __init__(self, onnx_node, **kwargs): @@ -61,7 +61,7 @@ def __init__(self, onnx_node, **kwargs): def get_nodeattr_types(self): my_attrs = {} - my_attrs.update(ThresholdingBinarySearch.get_nodeattr_types(self)) + my_attrs.update(Thresholding.get_nodeattr_types(self)) my_attrs.update(HLSBackend.get_nodeattr_types(self)) return my_attrs diff --git a/src/finn/custom_op/fpgadataflow/thresholdingbinarysearch.py b/src/finn/custom_op/fpgadataflow/thresholding.py similarity index 99% rename from src/finn/custom_op/fpgadataflow/thresholdingbinarysearch.py rename to src/finn/custom_op/fpgadataflow/thresholding.py index 3d919d3c6e..d6d0d8d01c 100644 --- a/src/finn/custom_op/fpgadataflow/thresholdingbinarysearch.py +++ b/src/finn/custom_op/fpgadataflow/thresholding.py @@ -33,7 +33,7 @@ from finn.custom_op.fpgadataflow.hwcustomop import HWCustomOp -class ThresholdingBinarySearch(HWCustomOp): +class Thresholding(HWCustomOp): def __init__(self, onnx_node, **kwargs): super().__init__(onnx_node, **kwargs) diff --git a/tests/fpgadataflow/test_fpgadataflow_thresholding_binary_search.py b/tests/fpgadataflow/test_fpgadataflow_thresholding_binary_search.py index c247e9cdfc..ea331a4565 100755 --- a/tests/fpgadataflow/test_fpgadataflow_thresholding_binary_search.py +++ b/tests/fpgadataflow/test_fpgadataflow_thresholding_binary_search.py @@ -112,7 +112,7 @@ def make_single_thresholding_binary_search_modelwrapper( node_inp_list = ["inp", "thresh"] Thresholding_node = helper.make_node( - "ThresholdingBinarySearch", + "Thresholding", node_inp_list, ["outp"], domain="finn.custom_op.fpgadataflow", From 207fa941511f4a705044939ff758caef892f5bbe Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Fri, 26 Jan 2024 15:21:17 +0000 Subject: [PATCH 412/665] [TBS] Add HLS variant --- .../fpgadataflow/hls/thresholding_hls.py | 97 +++++++++++++++++-- 1 file changed, 91 insertions(+), 6 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py b/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py index bb8ca582ea..0ad198feb5 100644 --- a/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py @@ -39,6 +39,7 @@ roundup_to_integer_multiple, ) +from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp from finn.util.data_packing import ( npy_to_rtlsim_input, numpy_to_hls_code, @@ -58,11 +59,45 @@ class Thresholding_hls(Thresholding,HLSBackend): def __init__(self, onnx_node, **kwargs): super().__init__(onnx_node, **kwargs) - + self.variant = "hls" + def get_nodeattr_types(self): - my_attrs = {} - my_attrs.update(Thresholding.get_nodeattr_types(self)) - my_attrs.update(HLSBackend.get_nodeattr_types(self)) + my_attrs = { + # parallelization; channels thresholded per cycle + "PE": ("i", True, 0), + # number of channels (each may have different thresholds) + "NumChannels": ("i", True, 0), + # number of steps in thresholding function + "numSteps": ("i", True, 1), + # string defining memory type + "ram_style": ("s", False, "distributed", {"distributed", "block"}), + # FINN DataTypes for inputs, outputs + "inputDataType": ("s", True, ""), + "weightDataType": ("s", True, ""), + "outputDataType": ("s", True, ""), + # number of input vectors, examples: + # [1] is a single vector (like a FC layer with batch=1) + # [4] is four vectors (like a FC layer with batch=4) + # [1, 4, 4] is four * four vectors (like a conv layer with batch=1) + "numInputVectors": ("ints", False, [1]), + # initialization value for the thresholding accumulator + "ActVal": ("i", False, 0), + # memory mode for the thresholds + # const -- embedded thresholds, default + # decoupled -- streaming thresholds with streamer packaged inside IP + "mem_mode": ("s", False, "const", {"const", "decoupled"}), + # (mem_mode = decoupled only) whether weights (thresholds) will be + # writable through an AXI-lite interface during runtime + # 1 for enabled, 0 for disabled. + # see finn-rtllib/memstream/doc/README for more about the memory + # address map used for writable weights + # IMPORTANT: After using AXI lite to either read or write the weights, + # always "flush" the accelerator by first passing a dummy input + # vector through the accelerator. This will get rid of any old + # weight data from the weight FIFOs. + "runtime_writeable_weights": ("i", False, 0, {0, 1}), + } + my_attrs.update(super().get_nodeattr_types()) return my_attrs def calc_tmem(self): @@ -71,8 +106,24 @@ def calc_tmem(self): pe = self.get_nodeattr("PE") return mh // pe + def make_shape_compatible_op(self, model): + oshape = self.get_normal_output_shape() + return super().make_const_shape_op(oshape) + def infer_node_datatype(self, model): - pass + node = self.onnx_node + idt = model.get_tensor_datatype(node.input[0]) + if idt != self.get_input_datatype(): + warn_str = "inputDataType changing for %s: %s -> %s " % ( + node.name, + str(self.get_input_datatype().name), + str(idt.name), + ) + warnings.warn(warn_str) + self.set_nodeattr("inputDataType", idt.name) + # set output datatype from property + odt = self.get_output_datatype() + model.set_tensor_datatype(node.output[0], odt) def verify_node(self): info_messages = [] @@ -464,7 +515,41 @@ def execute_node(self, context, graph): context[node.output[0]] = out oshape = self.get_normal_output_shape() assert context[node.output[0]].shape == oshape, """Output shape is not as expected""" - + elif mode == "rtlsim": + sim = self.get_rtlsim() + nbits = self.get_instream_width() + inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) + super().reset_rtlsim(sim) + super().toggle_clk(sim) + if self.get_nodeattr("mem_mode") == "decoupled": + wnbits = self.get_weightstream_width() + export_wdt = self.get_weight_datatype() + wei = npy_to_rtlsim_input( + "{}/thresholds.npy".format(code_gen_dir), export_wdt, wnbits + ) + num_w_reps = np.prod(self.get_nodeattr("numInputVectors")) + io_dict = { + "inputs": {"in0": inp, "weights": wei * num_w_reps}, + "outputs": {"out": []}, + } + self.rtlsim_multi_io(sim, io_dict) + output = io_dict["outputs"]["out"] + elif self.get_nodeattr("mem_mode") == "const": + output = self.rtlsim(sim, inp) + else: + raise Exception("Unrecognized mem_mode") + odt = self.get_output_datatype() + target_bits = odt.bitwidth() + packed_bits = self.get_outstream_width() + out_npy_path = "{}/output.npy".format(code_gen_dir) + out_shape = self.get_folded_output_shape() + rtlsim_output_to_npy(output, out_npy_path, odt, out_shape, packed_bits, target_bits) + + # load and reshape output + output = np.load(out_npy_path) + oshape = self.get_normal_output_shape() + output = np.asarray([output], dtype=np.float32).reshape(*oshape) + context[node.output[0]] = output else: raise Exception( """Invalid value for attribute exec_mode! Is currently set to: {} From 09d5d3094b1b056fd6593d8680f8616eae47a9df Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Fri, 26 Jan 2024 15:26:35 +0000 Subject: [PATCH 413/665] [TBS] resolve merge conflict --- src/finn/custom_op/fpgadataflow/__init__.py | 1 - 1 file changed, 1 deletion(-) diff --git a/src/finn/custom_op/fpgadataflow/__init__.py b/src/finn/custom_op/fpgadataflow/__init__.py index 93c1a4bd1d..bd9c0366e7 100644 --- a/src/finn/custom_op/fpgadataflow/__init__.py +++ b/src/finn/custom_op/fpgadataflow/__init__.py @@ -55,7 +55,6 @@ from finn.custom_op.fpgadataflow.thresholding import ( Thresholding, ) -from finn.custom_op.fpgadataflow.tlastmarker import TLastMarker from finn.custom_op.fpgadataflow.upsampler import UpsampleNearestNeighbour from finn.custom_op.fpgadataflow.vectorvectoractivation import VectorVectorActivation From 7abb066a5d32f4bdcb9a58a207845e960c4e4ad5 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Fri, 26 Jan 2024 16:15:53 +0000 Subject: [PATCH 414/665] [TBS] Minimise Thresholding class methods: --- .../custom_op/fpgadataflow/thresholding.py | 26 +------------------ 1 file changed, 1 insertion(+), 25 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/thresholding.py b/src/finn/custom_op/fpgadataflow/thresholding.py index d6d0d8d01c..004bf1aec0 100644 --- a/src/finn/custom_op/fpgadataflow/thresholding.py +++ b/src/finn/custom_op/fpgadataflow/thresholding.py @@ -77,39 +77,15 @@ def get_nodeattr_types(self): my_attrs.update(super().get_nodeattr_types()) return my_attrs - def get_padded_odim(): - pass - - def get_exp_cycles(): - pass - - def get_normal_input_shape(): - pass - - def get_normal_output_shape(): - pass - def get_folded_input_shape(): - pass - def get_folded_output_shape(): - pass def make_shape_compatible_op(self, model): oshape = self.get_normal_output_shape() return super().make_const_shape_op(oshape) - def infer_node_datatype(): - pass def verify_node(): pass - def get_input_datatype(): - pass - def get_output_datatype(): - pass - def get_instream_width(): - pass - def get_outstream_width(): + def infer_node_datatype(): pass def get_number_output_values(): pass - def execute_node(self, context, graph): pass From f29d7439eda3448000aa74e5dc76c307b96253ae Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Fri, 26 Jan 2024 16:17:00 +0000 Subject: [PATCH 415/665] [TBS] InfeThreshold will only instantiate Thresholding class --- .../fpgadataflow/convert_to_hw_layers.py | 71 +++++-------------- 1 file changed, 18 insertions(+), 53 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py index aacedcc6f2..88a9a64cd6 100644 --- a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py +++ b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py @@ -183,10 +183,9 @@ def apply(self, model): class InferThresholdingLayer(Transformation): """Convert any MultiThreshold into a standalone thresholding HLS layer.""" - def __init__(self, mem_mode="const", use_rtl_variant=False): + def __init__(self, mem_mode="const"): super().__init__() self.mem_mode = mem_mode - self.use_rtl_variant = use_rtl_variant def apply(self, model): graph = model.graph @@ -241,63 +240,29 @@ def apply(self, model): node.name + ": Signed output requires actval < 0" ) - # Ensure that RTL variant is not inserted for unsupported configuration - is_rtl_variant_compatible = True - - # Perform checks for RTL variant if chosen - if self.use_rtl_variant and is_rtl_variant_compatible: - new_node = helper.make_node( - "Thresholding_Binary_Search", - [thl_input, thl_threshold], - [thl_output], - domain="finn.custom_op.fpgadataflow", - backend="fpgadataflow", - NumChannels=ifc, - PE=pe, - numSteps=thl_thres_shape[1], - inputDataType=idt.name, - weightDataType=idt.name, - outputDataType=odt.name, - numInputVectors=list(thl_in_shape[:-1]), - activation_bias=actval, - mem_mode=self.mem_mode, - name="Thresholding_Binary_Search_" + node.name, - ) - else: - if self.use_rtl_variant: - warnings.warn( - """%s : RTL Thresholding requested for unsupported - configuration. Falling back to HLS implementation.""" - % node.name - ) - - # create and insert new Thresholding_Batch node - new_node = helper.make_node( - "Thresholding_Batch", - [thl_input, thl_threshold], - [thl_output], - domain="finn.custom_op.fpgadataflow", - backend="fpgadataflow", - NumChannels=ifc, - PE=pe, - numSteps=thl_thres_shape[1], - inputDataType=idt.name, - weightDataType=idt.name, - outputDataType=odt.name, - numInputVectors=list(thl_in_shape[:-1]), - ActVal=actval, - mem_mode=self.mem_mode, - name="Thresholding_Batch_" + node.name, - ) + new_node = helper.make_node( + "Thresholding", + [thl_input, thl_threshold], + [thl_output], + domain="finn.custom_op.fpgadataflow", + backend="fpgadataflow", + NumChannels=ifc, + PE=pe, + numSteps=thl_thres_shape[1], + inputDataType=idt.name, + weightDataType=idt.name, + outputDataType=odt.name, + numInputVectors=list(thl_in_shape[:-1]), + ActVal=actval, + mem_mode=self.mem_mode, + name="Thresholding_Batch_" + node.name, + ) graph.node.insert(insert_point, new_node) # remove old node graph.node.remove(node) graph_modified = True - if graph_modified: - model = model.transform(InferShapes()) - model = model.transform(InferDataTypes()) return (model, graph_modified) class InferUpsample(Transformation): """Convert Upsample and Resize nodes to layers to UpsampleNearestNeighbour nodes.""" From 34005e38a00f3302e7b0d7b784fa52be2abc2679 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Fri, 26 Jan 2024 16:18:15 +0000 Subject: [PATCH 416/665] [TBS] Testcase to convert Thresholding layer --- .../test_convert_to_hls_thresholding.py | 109 ++---------------- 1 file changed, 11 insertions(+), 98 deletions(-) diff --git a/tests/fpgadataflow/test_convert_to_hls_thresholding.py b/tests/fpgadataflow/test_convert_to_hls_thresholding.py index 9c233bdd06..e96581dc89 100755 --- a/tests/fpgadataflow/test_convert_to_hls_thresholding.py +++ b/tests/fpgadataflow/test_convert_to_hls_thresholding.py @@ -49,6 +49,8 @@ from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP from finn.transformation.fpgadataflow.insert_fifo import InsertFIFO from finn.transformation.fpgadataflow.prepare_ip import PrepareIP +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers +from finn.transformation.fpgadataflow.convert_to_hw_layers import InferThresholdingLayer test_fpga_part = "xczu3eg-sbva484-1-e" target_clk_ns = 5 @@ -75,20 +77,6 @@ def generate_pe_value(fold, num_input_channels): return pe -# n = batch, c = channel, h = height, w = width of feature map -# Standard = NCHW; FINN = NHWC -# Convert from NCHW to NHWC -def convert_np_array_to_finn_data_layout(data): - return np.transpose(data, (0, 2, 3, 1)) - - -# n = batch, c = channel, h = height, w = width of feature map -# Standard = NCHW; FINN = NHWC -# Convert from NHWC to NCHW -def convert_np_array_to_standard_data_layout(data): - return np.transpose(data, (0, 3, 1, 2)) - - def make_single_multithresholding_modelwrapper( thresholds, pe, @@ -144,9 +132,11 @@ def make_single_multithresholding_modelwrapper( @pytest.mark.parametrize("input_data_type", [DataType["INT16"], DataType["UINT16"]]) @pytest.mark.parametrize("fold", [-1, 1, 2, 4, 6]) @pytest.mark.parametrize("num_input_channels", [16]) +@pytest.mark.parametrize("impl_style", ["rtl", "hls"]) @pytest.mark.fpgadataflow @pytest.mark.vivado -def test_convert_to_hls_tbs_rtl_variant( +def test_convert_multithreshold_to_hardware( + impl_style, activation, input_data_type, fold, @@ -173,10 +163,6 @@ def test_convert_to_hls_tbs_rtl_variant( else: activation_bias = output_data_type.min() - # generate random input data - tensor_shape = tuple(num_input_vecs + [num_input_channels]) - x = gen_finn_dt_tensor(input_data_type, tensor_shape) - # Generate random thresholds and sort in ascending order thresholds = generate_random_threshold_values( input_data_type, num_input_channels, num_steps @@ -185,73 +171,8 @@ def test_convert_to_hls_tbs_rtl_variant( # provide non-decreasing/ascending thresholds thresholds = sort_thresholds_increasing(thresholds) - x_nhwc = convert_np_array_to_standard_data_layout(x) - y = multithreshold(x_nhwc, thresholds) - - # convert back to NHWC for comparison to hw outputs - y = convert_np_array_to_finn_data_layout(y) - if activation == DataType["BIPOLAR"]: - # binary to bipolar - y = 2 * y - 1 - else: - # signed offset - y += activation.min() - - # Generate model from input parameters to the test - model = make_single_thresholding_binary_search_modelwrapper( - thresholds, - pe, - input_data_type, - output_data_type, - activation_bias, - num_input_vecs, - ) - - model = model.transform(InsertFIFO(True)) - model = model.transform(GiveUniqueNodeNames()) - model = model.transform(PrepareIP(test_fpga_part, target_clk_ns)) - model = model.transform(HLSSynthIP()) - model = model.transform(CreateStitchedIP(test_fpga_part, target_clk_ns)) - - # Retrieve the axilite programming sequence for weights - for decoupled mode only - tbs_node = model.get_nodes_by_op_type("Thresholding_Binary_Search")[0] - tbs_inst = getCustomOp(tbs_node) - config = tbs_inst.get_dynamic_config(model, 4) - - # Reshape generated data (not from model) - oshape = model.get_tensor_shape("outp") - y_expected = y.reshape(oshape) - - # Helper function that delivers the hook to program the thresholds via AXI-Lite - def config_hook(config): - if config is None: - return None - - def write_thresh_config(sim): - # axi_name = "s_axilite_0_" # works - axi_name = getCustomOp( - model.get_nodes_by_op_type("Thresholding_Binary_Search")[0] - ).get_verilog_top_module_intf_names()["axilite"][0] - axi_name += "_0_" - - # Write config registers to the Threshold memory. - # The dictionary defines (addr, value) tuples. - for config_entry in config.values(): - addr = config_entry[0] - val = config_entry[1] - axilite_write(sim, addr, val, basename=axi_name) - - reset_rtlsim(sim) - - return write_thresh_config - - input_dict = {"inp": x} - rtlsim_exec(model, input_dict, pre_hook=config_hook(config)) - y_produced = input_dict["outp"] - assert (y_produced == y_expected).all() - # Make a Multithreshold graph and convert to thresholding binary search node - new_model = make_single_multithresholding_modelwrapper( + model = make_single_multithresholding_modelwrapper( thresholds, pe, input_data_type, @@ -260,17 +181,9 @@ def write_thresh_config(sim): num_input_vecs, ) - # Recreate the model using the ConvertToHLS transform - new_model = new_model.transform( - to_hls.InferThresholdingLayer(mem_mode="decoupled", use_rtl_variant=True) - ) - new_model = new_model.transform(InsertFIFO(True)) - new_model = new_model.transform(GiveUniqueNodeNames()) - new_model = new_model.transform(PrepareIP(test_fpga_part, target_clk_ns)) - new_model = new_model.transform(HLSSynthIP()) - new_model = new_model.transform(CreateStitchedIP(test_fpga_part, target_clk_ns)) + model = model.transform(InferThresholdingLayer()) + model = model.transform(SpecializeLayers()) + model = model.transform(InferShapes()) - input_dict = {"inp": x} - rtlsim_exec(new_model, input_dict, pre_hook=config_hook(config)) - y_produced_new = input_dict["outp"] - assert (y_produced_new == y_expected).all() + node_variant = getCustomOp(model.graph.node[0]).variant + assert (impl_style == node_variant) \ No newline at end of file From e2c60f0b6b10eee530764f590014048ef605e8ad Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Fri, 26 Jan 2024 16:19:30 +0000 Subject: [PATCH 417/665] [TBS] Rename to_hw test --- ..._to_hls_thresholding.py => test_convert_to_hw_thresholding.py} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename tests/fpgadataflow/{test_convert_to_hls_thresholding.py => test_convert_to_hw_thresholding.py} (100%) diff --git a/tests/fpgadataflow/test_convert_to_hls_thresholding.py b/tests/fpgadataflow/test_convert_to_hw_thresholding.py similarity index 100% rename from tests/fpgadataflow/test_convert_to_hls_thresholding.py rename to tests/fpgadataflow/test_convert_to_hw_thresholding.py From d680a707c48111a3c5a77bbb3acc38f0745db96b Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Fri, 26 Jan 2024 16:20:37 +0000 Subject: [PATCH 418/665] [TBS] Remove functional testing for now --- ...fpgadataflow_thresholding_binary_search.py | 363 ------------------ 1 file changed, 363 deletions(-) delete mode 100755 tests/fpgadataflow/test_fpgadataflow_thresholding_binary_search.py diff --git a/tests/fpgadataflow/test_fpgadataflow_thresholding_binary_search.py b/tests/fpgadataflow/test_fpgadataflow_thresholding_binary_search.py deleted file mode 100755 index ea331a4565..0000000000 --- a/tests/fpgadataflow/test_fpgadataflow_thresholding_binary_search.py +++ /dev/null @@ -1,363 +0,0 @@ -# Copyright (C) 2022, Advanced Micro Devices, Inc. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# * Redistributions of source code must retain the above copyright notice, this -# list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# * Neither the name of FINN nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -import pytest - -import numpy as np -from onnx import TensorProto, helper -from pyverilator.util.axi_utils import axilite_write, reset_rtlsim -from qonnx.core.datatype import DataType -from qonnx.core.modelwrapper import ModelWrapper -from qonnx.custom_op.general.multithreshold import multithreshold -from qonnx.custom_op.registry import getCustomOp -from qonnx.transformation.general import GiveUniqueNodeNames -from qonnx.util.basic import gen_finn_dt_tensor -from qonnx.transformation.infer_shapes import InferShapes -from finn.transformation.fpgadataflow.convert_to_hw_layers import InferThresholdingLayer -from finn.core.rtlsim_exec import rtlsim_exec -from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP -from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim -from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP -from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim -from finn.transformation.fpgadataflow.insert_fifo import InsertFIFO -from finn.transformation.fpgadataflow.prepare_ip import PrepareIP -from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim -from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode -from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers -import finn.core.onnx_exec as oxe - -test_fpga_part = "xczu3eg-sbva484-1-e" -target_clk_ns = 5 - - -# Helper functions -def sort_thresholds_increasing(thresholds): - return np.sort(thresholds, axis=1) - - -def generate_random_threshold_values(input_data_type, num_input_channels, num_steps): - return np.random.randint( - input_data_type.min(), - input_data_type.max() + 1, - (num_input_channels, num_steps), - ).astype(np.float32) - - -def generate_pe_value(fold, num_input_channels): - if fold == -1: - fold = num_input_channels - pe = num_input_channels // fold - assert num_input_channels % pe == 0 - return pe - - -# n = batch, c = channel, h = height, w = width of feature map -# Standard = NCHW; FINN = NHWC -# Convert from NCHW to NHWC -def convert_np_array_to_finn_data_layout(data): - return np.transpose(data, (0, 2, 3, 1)) - - -# n = batch, c = channel, h = height, w = width of feature map -# Standard = NCHW; FINN = NHWC -# Convert from NHWC to NCHW -def convert_np_array_to_standard_data_layout(data): - return np.transpose(data, (0, 3, 1, 2)) - - -def make_single_thresholding_binary_search_modelwrapper( - impl_style, - thresholds, - pe, - input_data_type, - output_data_type, - activation_bias, - num_input_vecs, -): - - NumChannels = thresholds.shape[0] - - inp = helper.make_tensor_value_info( - "inp", TensorProto.FLOAT, num_input_vecs + [NumChannels] - ) - outp = helper.make_tensor_value_info( - "outp", TensorProto.FLOAT, num_input_vecs + [NumChannels] - ) - - node_inp_list = ["inp", "thresh"] - - Thresholding_node = helper.make_node( - "Thresholding", - node_inp_list, - ["outp"], - domain="finn.custom_op.fpgadataflow", - backend="fpgadataflow", - NumChannels=NumChannels, - PE=pe, - numSteps=thresholds.shape[1], - inputDataType=input_data_type.name, - weightDataType=input_data_type.name, - outputDataType=output_data_type.name, - activation_bias=activation_bias, - numInputVectors=num_input_vecs, - preferred_impl_style=impl_style, - ) - graph = helper.make_graph( - nodes=[Thresholding_node], - name="thresholding_graph", - inputs=[inp], - outputs=[outp], - ) - - model = helper.make_model(graph, producer_name="thresholding-model") - model = ModelWrapper(model) - - model.set_tensor_datatype("inp", input_data_type) - model.set_tensor_datatype("outp", output_data_type) - - model.set_tensor_datatype("thresh", input_data_type) - model.set_initializer("thresh", thresholds) - return model - - -# # Test brief: Test that PrepareRTLSim() runs successfully. This function is not -# # tested in test_fpgadataflow_thresholding_binary_search() -# @pytest.mark.fpgadataflow -# @pytest.mark.vivado -# def test_fpgadataflow_thresholding_binary_search_prepare_rtlsim(): -# input_data_type = DataType["INT16"] -# act = DataType["INT4"] -# fold = -1 -# num_input_channels = 16 - -# # Handle inputs to the test -# pe = generate_pe_value(fold, num_input_channels) -# num_steps = act.get_num_possible_values() - 1 - -# # Generate random, non-decreasing thresholds -# thresholds = generate_random_threshold_values( -# input_data_type, num_input_channels, num_steps -# ) -# thresholds = sort_thresholds_increasing(thresholds) - -# # Other non-input parameters -# num_input_vecs = [1, 2, 2] -# output_data_type = act -# if output_data_type == DataType["BIPOLAR"]: -# activation_bias = 0 -# else: -# activation_bias = output_data_type.min() - -# # Generate model from input parameters to the test -# model = make_single_thresholding_binary_search_modelwrapper( -# thresholds, -# pe, -# input_data_type, -# output_data_type, -# activation_bias, -# num_input_vecs, -# ) - -# model = model.transform(SetExecMode("rtlsim")) -# model = model.transform(GiveUniqueNodeNames()) -# model = model.transform(PrepareIP(test_fpga_part, target_clk_ns)) -# model = model.transform(HLSSynthIP()) -# model = model.transform(PrepareRTLSim()) -# return - - -# Test brief: Create a Thresholding binary search layer using various parameters -# and test against a SW generated & simulated dataset -# N.B. Fold values where C % PE != 0 fail -@pytest.mark.parametrize("activation", [DataType["INT4"], DataType["BIPOLAR"]]) -@pytest.mark.parametrize("input_data_type", [DataType["INT16"], DataType["UINT16"]]) -@pytest.mark.parametrize("fold", [-1, 1, 2, 4, 6]) -@pytest.mark.parametrize("num_input_channels", [16]) -@pytest.mark.parametrize("impl_style", ["rtl", "hls"]) -@pytest.mark.parametrize("mode", ["cppsim", "rtlsim"]) -@pytest.mark.fpgadataflow -@pytest.mark.vivado -@pytest.mark.slow -def test_fpgadataflow_thresholding_binary_search( - activation, input_data_type, fold, num_input_channels, impl_style, mode -): - # Handle inputs to the test - pe = generate_pe_value(fold, num_input_channels) - num_steps = activation.get_num_possible_values() - 1 - - # Other non-input parameters - num_input_vecs = [1, 2, 2] - output_data_type = activation - if output_data_type == DataType["BIPOLAR"]: - activation_bias = 0 - else: - activation_bias = output_data_type.min() - - # generate random input data - tensor_shape = tuple(num_input_vecs + [num_input_channels]) - x = gen_finn_dt_tensor(input_data_type, tensor_shape) - - # Generate random thresholds and sort in ascending order - thresholds = generate_random_threshold_values( - input_data_type, num_input_channels, num_steps - ) - - # provide non-decreasing/ascending thresholds - thresholds = sort_thresholds_increasing(thresholds) - - x_nhwc = convert_np_array_to_standard_data_layout(x) - y = multithreshold(x_nhwc, thresholds) - - # convert back to NHWC for comparison to hw outputs - y = convert_np_array_to_finn_data_layout(y) - if activation == DataType["BIPOLAR"]: - # binary to bipolar - y = 2 * y - 1 - else: - # signed offset - y += activation.min() - - # Generate model from input parameters to the test - model = make_single_thresholding_binary_search_modelwrapper( - impl_style, - thresholds, - pe, - input_data_type, - output_data_type, - activation_bias, - num_input_vecs, - ) - - model = model.transform(InferThresholdingLayer()) - model = model.transform(SpecializeLayers()) - model = model.transform(InferShapes()) - # model = model.transform(SetExecMode(mode)) - # model = model.transform(GiveUniqueNodeNames()) - # if mode == "cppsim": - # model = model.transform(PrepareCppSim()) - # model = model.transform(CompileCppSim()) - # elif mode == "rtlsim": - # model = model.transform(PrepareIP(test_fpga_part, target_clk_ns)) - # model = model.transform(HLSSynthIP()) - # model = model.transform(PrepareRTLSim()) - # input_dict = {"inp": x} - # y_produced = oxe.execute_onnx(model, input_dict)["outp"] - - # model = model.transform(InsertFIFO(True)) - # model = model.transform(GiveUniqueNodeNames()) - # model = model.transform(PrepareIP(test_fpga_part, target_clk_ns)) - # model = model.transform(HLSSynthIP()) - # model = model.transform(CreateStitchedIP(test_fpga_part, target_clk_ns)) - - # # Retrieve the axilite programming sequence for weights - for decoupled mode only - # tbs_node = model.get_nodes_by_op_type("Thresholding_Binary_Search")[0] - # tbs_inst = getCustomOp(tbs_node) - # config = tbs_inst.get_dynamic_config(model, 4) - - # # Reshape generated data (not from model) - # oshape = model.get_tensor_shape("outp") - # y_expected = y.reshape(oshape) - - # # Helper function that delivers the hook to program the thresholds via AXI-Lite - # def config_hook(config): - # if config is None: - # return None - - # def write_thresh_config(sim): - # # axi_name = "s_axilite_0_" # works - # axi_name = getCustomOp( - # model.get_nodes_by_op_type("Thresholding_Binary_Search")[0] - # ).get_verilog_top_module_intf_names()["axilite"][0] - # axi_name += "_0_" - - # # Write config registers to the Threshold memory. - # # The dictionary defines (addr, value) tuples. - # for config_entry in config.values(): - # addr = config_entry[0] - # val = config_entry[1] - # axilite_write(sim, addr, val, basename=axi_name) - - # reset_rtlsim(sim) - - # return write_thresh_config - - # input_dict = {"inp": x} - # rtlsim_exec(model, input_dict, pre_hook=config_hook(config)) - # y_produced = input_dict["outp"] - # assert (y_produced == y_expected).all() - - -# # Test brief: Test basic transforms are working -# @pytest.mark.parametrize("impl_style", ["rtl", "hls"]) -# @pytest.mark.fpgadataflow -# @pytest.mark.vivado -# def test_fpgadataflow_thresholding_binary_search_transform(impl_style): -# input_data_type = DataType["INT16"] -# act = DataType["INT4"] -# fold = -1 -# num_input_channels = 16 - -# # Handle inputs to the test -# pe = generate_pe_value(fold, num_input_channels) -# num_steps = act.get_num_possible_values() - 1 - -# # Generate random, non-decreasing thresholds -# thresholds = generate_random_threshold_values( -# input_data_type, num_input_channels, num_steps -# ) -# thresholds = sort_thresholds_increasing(thresholds) - -# # Other non-input parameters -# num_input_vecs = [1, 2, 2] -# output_data_type = act -# if output_data_type == DataType["BIPOLAR"]: -# activation_bias = 0 -# else: -# activation_bias = output_data_type.min() - -# # Generate model from input parameters to the test -# model = make_single_thresholding_binary_search_modelwrapper( -# impl_style, -# thresholds, -# pe, -# input_data_type, -# output_data_type, -# activation_bias, -# num_input_vecs, -# ) - -# model = model.transform(SpecializeLayers()) - -# # if "hls" in getCustomOp(model.graph.node[0]).__class__.__name__ and impl_style != "hls": - -# # model = model.transform(SetExecMode("rtlsim")) -# # model = model.transform(GiveUniqueNodeNames()) -# # model = model.transform(PrepareIP(test_fpga_part, target_clk_ns)) -# # model = model.transform(HLSSynthIP()) -# # model = model.transform(PrepareRTLSim()) -# return \ No newline at end of file From 9bc48a6cc269c8aaaba6dc1605e85f922f992607 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Fri, 26 Jan 2024 16:23:05 +0000 Subject: [PATCH 419/665] [TBS] remove unused thresholding scripts --- .../fpgadataflow/thresholding_batch.py | 940 ------------------ .../thresholding_binary_search.py | 766 -------------- 2 files changed, 1706 deletions(-) delete mode 100644 src/finn/custom_op/fpgadataflow/thresholding_batch.py delete mode 100755 src/finn/custom_op/fpgadataflow/thresholding_binary_search.py diff --git a/src/finn/custom_op/fpgadataflow/thresholding_batch.py b/src/finn/custom_op/fpgadataflow/thresholding_batch.py deleted file mode 100644 index 37c51300a3..0000000000 --- a/src/finn/custom_op/fpgadataflow/thresholding_batch.py +++ /dev/null @@ -1,940 +0,0 @@ -# Copyright (c) 2024, Xilinx -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# * Redistributions of source code must retain the above copyright notice, this -# list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# * Neither the name of FINN nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -import numpy as np -import os -import textwrap -import warnings -from math import ceil, log2 -from finn.custom_op.fpgadataflow.fmpadding import FMPadding -from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend -from qonnx.core.datatype import DataType -from qonnx.util.basic import ( - interleave_matrix_outer_dim_from_partitions, - roundup_to_integer_multiple, -) - -from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp -from finn.util.data_packing import ( - npy_to_rtlsim_input, - numpy_to_hls_code, - pack_innermost_dim_as_hex_string, - rtlsim_output_to_npy, -) - -# ONNX i/o tensor shape assumptions for Thresholding: -# input 0 is the input tensor, shape (..., NumChannels) -# input 1 is the threshold tensor, shape (NumChannels, n_thres) -# output 0 is the output tensor, shape (..., NumChannels) - same as input -# the ... here can be any shape (representing groups of vectors) - - -class Thresholding_Batch(HLSCustomOp): - """Class that corresponds to finn-hls Thresholding_Batch function.""" - - def __init__(self, onnx_node, **kwargs): - super().__init__(onnx_node, **kwargs) - - def get_nodeattr_types(self): - my_attrs = { - # parallelization; channels thresholded per cycle - "PE": ("i", True, 0), - # number of channels (each may have different thresholds) - "NumChannels": ("i", True, 0), - # number of steps in thresholding function - "numSteps": ("i", True, 1), - # string defining memory type - "ram_style": ("s", False, "distributed", {"distributed", "block"}), - # FINN DataTypes for inputs, outputs - "inputDataType": ("s", True, ""), - "weightDataType": ("s", True, ""), - "outputDataType": ("s", True, ""), - # number of input vectors, examples: - # [1] is a single vector (like a FC layer with batch=1) - # [4] is four vectors (like a FC layer with batch=4) - # [1, 4, 4] is four * four vectors (like a conv layer with batch=1) - "numInputVectors": ("ints", False, [1]), - # initialization value for the thresholding accumulator - "ActVal": ("i", False, 0), - # memory mode for the thresholds - # const -- embedded thresholds, default - # decoupled -- streaming thresholds with streamer packaged inside IP - "mem_mode": ("s", False, "const", {"const", "decoupled"}), - # (mem_mode = decoupled only) whether weights (thresholds) will be - # writable through an AXI-lite interface during runtime - # 1 for enabled, 0 for disabled. - # see finn-rtllib/memstream/doc/README for more about the memory - # address map used for writable weights - # IMPORTANT: After using AXI lite to either read or write the weights, - # always "flush" the accelerator by first passing a dummy input - # vector through the accelerator. This will get rid of any old - # weight data from the weight FIFOs. - "runtime_writeable_weights": ("i", False, 0, {0, 1}), - } - my_attrs.update(super().get_nodeattr_types()) - return my_attrs - - def calc_tmem(self): - """Calculates and returns TMEM.""" - mh = self.get_nodeattr("NumChannels") - pe = self.get_nodeattr("PE") - return mh // pe - - def make_shape_compatible_op(self, model): - oshape = self.get_normal_output_shape() - return super().make_const_shape_op(oshape) - - def infer_node_datatype(self, model): - node = self.onnx_node - idt = model.get_tensor_datatype(node.input[0]) - if idt != self.get_input_datatype(): - warn_str = "inputDataType changing for %s: %s -> %s " % ( - node.name, - str(self.get_input_datatype().name), - str(idt.name), - ) - warnings.warn(warn_str) - self.set_nodeattr("inputDataType", idt.name) - # set output datatype from property - odt = self.get_output_datatype() - model.set_tensor_datatype(node.output[0], odt) - - def verify_node(self): - info_messages = [] - # verify that "backend" is set to "fpgadataflow" - backend_value = self.get_nodeattr("backend") - if backend_value == "fpgadataflow": - info_messages.append("Attribute backend is set correctly") - else: - info_messages.append('Attribute backend should be set to "fpgadataflow"') - - # verify that all necessary attributes exist - # TODO collect automatically from get_nodeattr_types - try: - self.get_nodeattr("code_gen_dir_cppsim") - self.get_nodeattr("executable_path") - self.get_nodeattr("NumChannels") - self.get_nodeattr("PE") - self.get_nodeattr("inputDataType") - self.get_nodeattr("outputDataType") - info_messages.append("All necessary attributes exist") - except Exception: - info_messages.append("""The required Threshold_Batch attributes do not exist.""") - - return info_messages - - def bram_estimation(self): - """Calculates BRAM cost if resource set to BRAM""" - style = self.get_nodeattr("ram_style") - P = self.get_nodeattr("PE") - idt = self.get_input_datatype() - A = idt.bitwidth() - tmem = self.calc_tmem() - - if style == "block" and tmem > 1: - return int(ceil(A * P / 16)) * int(ceil(tmem / 1024)) - else: - return 0 - - def lut_estimation(self): - """Calculates LUT cost, taking memory resource type into account""" - # TODO add in/out FIFO contributions - style = self.get_nodeattr("ram_style") - P = self.get_nodeattr("PE") - idt = self.get_input_datatype() - A = idt.bitwidth() - tmem = self.calc_tmem() - # cost of comparators - comparator_cost = A * P - # cost of LUTRAM - if style == "distributed" and tmem > 1: - lutram_cost = P * A * int(ceil(tmem / 64)) - else: - lutram_cost = 0 - # total cost - return comparator_cost + lutram_cost - - def get_input_datatype(self, ind=0): - """Returns FINN DataType of input.""" - return DataType[self.get_nodeattr("inputDataType")] - - def get_output_datatype(self, ind=0): - """Returns FINN DataType of output.""" - return DataType[self.get_nodeattr("outputDataType")] - - def get_weight_datatype(self): - """Returns FINN DataType of thresholds, here called weights.""" - return DataType[self.get_nodeattr("weightDataType")] - - def minimize_accumulator_width(self, model): - "Minimize threshold width ('accumulator width' here due to convention)" - thresholds = model.get_initializer(self.onnx_node.input[1]) - threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds) - min_threshold = thresholds.min() - max_threshold = thresholds.max() - min_input = self.get_input_datatype().min() - max_input = self.get_input_datatype().max() - # get range required by threshold values - tdt_min = min(min_input, min_threshold) - tdt_max = max(max_input, max_threshold) - if tdt_min < 0: - if abs(tdt_min) > tdt_max: - tdt = DataType.get_smallest_possible(tdt_min) - else: - tdt = DataType.get_smallest_possible(-tdt_max - 1) - else: - tdt = DataType.get_smallest_possible(tdt_max) - assert np.vectorize(tdt.allowed)( - threshold_tensor - ).all(), "Thresholds can't be expressed with type %s" % str(tdt) - self.set_nodeattr("weightDataType", tdt.name) - # Update QONNX DataType of tensor for consistency - model.set_tensor_datatype(self.onnx_node.input[1], tdt) - return DataType[self.get_nodeattr("weightDataType")] - - def get_instream_width(self, ind=0): - i_bits = self.get_input_datatype().bitwidth() - return i_bits * self.get_nodeattr("PE") - - def get_outstream_width(self, ind=0): - o_bits = self.get_output_datatype().bitwidth() - return o_bits * self.get_nodeattr("PE") - - def get_weightstream_width(self): - """Returns weight stream width. Used only in decoupled mode.""" - if self.get_nodeattr("mem_mode") == "decoupled": - pe = self.get_nodeattr("PE") - wp = self.get_weight_datatype().bitwidth() - n_thres_steps = self.get_nodeattr("numSteps") - w_width = pe * wp * n_thres_steps - return w_width - else: - return 0 - - def get_weightstream_width_padded(self): - """Returns weight stream width padded to a multiple of 8. This is required - by the AXI Stream spec. Used in decoupled mode.""" - weight_width = self.get_weightstream_width() - return roundup_to_integer_multiple(weight_width, 8) - - def get_ap_int_max_w(self): - temp_value = super().get_ap_int_max_w() - weightstream = self.get_weightstream_width() - return max([weightstream, temp_value]) - - def get_folded_input_shape(self, ind=0): - ich = self.get_nodeattr("NumChannels") - pe = self.get_nodeattr("PE") - fold = ich // pe - vecs = list(self.get_nodeattr("numInputVectors")) - folded_input_shape = tuple(vecs + [fold, pe]) - return folded_input_shape - - def get_folded_output_shape(self, ind=0): - # same shape as input - return self.get_folded_input_shape() - - def get_normal_input_shape(self, ind=0): - ich = self.get_nodeattr("NumChannels") - vecs = list(self.get_nodeattr("numInputVectors")) - normal_input_shape = tuple(vecs + [ich]) - return normal_input_shape - - def get_normal_output_shape(self, ind=0): - # same shape as input - return self.get_normal_input_shape() - - def get_number_output_values(self): - nf = np.prod(self.get_folded_output_shape()[:-1]) - return nf - - def get_exp_cycles(self): - # Channels/PE * batch size * fmdim * fmdim - return np.prod(self.get_folded_output_shape()[:-1]) - - def get_template_param_values(self): - """Returns the template parameter values according to input, output and weight - data types.""" - ret = dict() - inp_hls_str = self.get_input_datatype().get_hls_datatype_str() - out_hls_str = self.get_output_datatype().get_hls_datatype_str() - # fill in TSrcI - ret["TSrcI"] = "Slice<%s>" % inp_hls_str - # fill in TDstI - ret["TDstI"] = "Slice<%s>" % out_hls_str - - return ret - - def get_hls_compatible_threshold_tensor(self, orig_thres_matrix): - """Convert the original numpy weight matrix orig_weight_matrix into - a form suitable for passing to the hlslib call: - * ensure MH % PE == 0 - * for unsigned inputs, ensure thresholds are positive - * interleave rows between PEs - * reshape into (PE, TMEM, n_thres_steps) and return - """ - mh = self.get_nodeattr("NumChannels") - pe = self.get_nodeattr("PE") - tmem = mh // pe - assert mh % pe == 0, "Requirement NumChannels divisable by PE is violated." - assert ( - orig_thres_matrix.ndim == 2 - ), """Threshold matrix dimension is - not as expected (2).""" - n_thres_steps = orig_thres_matrix.shape[1] - assert n_thres_steps == self.get_nodeattr("numSteps"), "Mismatch in threshold steps" - if not self.get_input_datatype().signed(): - # ensure all thresholds are nonnegative - assert (orig_thres_matrix >= 0).all() - # ensure all thresholds are integer - assert np.equal(np.mod(orig_thres_matrix, 1), 0).all(), "Need int threshold tensor" - ret = orig_thres_matrix - # ensure channels = mh , duplicating if necessary - if ret.shape[0] == 1: - ret = np.tile(ret, (mh, 1)) - assert ret.shape[0] == mh, "Channels of threshold matrix are not as expected (mh)" - # distribute rows between PEs - ret = interleave_matrix_outer_dim_from_partitions(ret, pe) - assert ( - ret.shape[0] == pe - ), """First dimension after distribution of the - rows between PEs is not as expected (pe)""" - assert ( - ret.shape[1] == tmem - ), """Second dimension after distribution of the - rows between PEs is not as expected (tmem)""" - assert ( - ret.shape[2] == n_thres_steps - ), """Third dimension after distribution of the - rows between PEs is not as expected (n_thres_steps)""" - return ret.reshape(1, pe, tmem, n_thres_steps) - - def make_weight_file(self, weights, weight_file_mode, weight_file_name): - """Produce a file containing given weights (thresholds) in appropriate - format for this layer. This file can be used for either synthesis or - run-time reconfig of weights. - - Arguments: - - * weights : numpy array with weights to be put into the file - * weight_file_mode : one of {hls_header, decoupled_verilog_dat, - decoupled_runtime} - * weight_file_name : filename for the weight file to be generated - - """ - threshold_tensor = self.get_hls_compatible_threshold_tensor(weights) - tdt = self.get_weight_datatype() - assert np.vectorize(tdt.allowed)( - threshold_tensor - ).all(), "Thresholds can't be expressed with type %s" % str(tdt) - if weight_file_mode == "hls_header": - # save thresholds in thresh.h - thresholds_hls_code = numpy_to_hls_code( - threshold_tensor, tdt, "thresholds", False, True - ) - # write thresholds into thresh.h - f_thresh = open(weight_file_name, "w") - tdt_hls = tdt.get_hls_datatype_str() - # use binary to export bipolar activations - export_odt = self.get_output_datatype() - if self.get_output_datatype() == DataType["BIPOLAR"]: - export_odt = DataType["BINARY"] - odt_hls = export_odt.get_hls_datatype_str() - f_thresh.write( - "static ThresholdsActivation<{},{},{},{},{},{},{}> threshs \ - = ".format( - self.calc_tmem(), - self.get_nodeattr("PE"), - threshold_tensor.shape[-1], - tdt_hls, - odt_hls, - self.get_nodeattr("ActVal"), - "comp::less_equal<%s, %s>" % (tdt_hls, tdt_hls), - ) - ) - f_thresh.write(thresholds_hls_code) - f_thresh.close() - elif "decoupled" in weight_file_mode: - # streaming thresholds need to be organized differently - # (1, pe, tmem, n_thres_steps) -> (1, tmem, pe, n_thres_steps) - decoupled_thres = np.transpose(threshold_tensor, (0, 2, 1, 3)) - # TODO add flips/reversals as needed here - # (1, tmem, pe, n_thres_steps) -(1, tmem, pe * n_thres_steps) - pe = self.get_nodeattr("PE") - n_thres_steps = self.get_nodeattr("numSteps") - decoupled_thres_pe_flipped = np.flip(decoupled_thres, axis=-2) - decoupled_thres = decoupled_thres.reshape(1, -1, pe * n_thres_steps) - decoupled_thres = decoupled_thres.copy() - decoupled_thres_pe_flipped = decoupled_thres_pe_flipped.reshape( - 1, -1, pe * n_thres_steps - ) - decoupled_thres_pe_flipped = decoupled_thres_pe_flipped.copy() - - if weight_file_mode == "decoupled_npy": - # save weight stream into npy for cppsim - np.save(weight_file_name, decoupled_thres) - elif weight_file_mode == "decoupled_verilog_dat": - # convert weight values into hexstring - weight_width = self.get_weightstream_width() - # pad to nearest 4 bits to get hex strings - weight_width_padded = roundup_to_integer_multiple(weight_width, 4) - weight_tensor_pe_flipped = pack_innermost_dim_as_hex_string( - decoupled_thres_pe_flipped, tdt, weight_width_padded, prefix="" - ) - weight_stream = weight_tensor_pe_flipped.flatten() - weight_stream = weight_stream.copy() - with open(weight_file_name, "w") as f: - for val in weight_stream: - f.write(val + "\n") - elif weight_file_mode == "decoupled_runtime": - # memstream axi-lite interface will map each mem line to - # one or multiple 32-bit words - weight_width = self.get_weightstream_width() - words_per_memwidth = 2 ** ceil(log2(weight_width / 32)) - if words_per_memwidth < 1: - words_per_memwidth = 1 - weight_width_padded = words_per_memwidth * 32 - # first, pack and ensure padding to 32 bits - weight_tensor_pe_flipped = pack_innermost_dim_as_hex_string( - decoupled_thres_pe_flipped, tdt, weight_width_padded, prefix="" - ) - weight_stream = weight_tensor_pe_flipped.flatten() - weight_stream = weight_stream.copy() - with open(weight_file_name, "w") as f: - for val in weight_stream: - # split into groups of 8 hex digits (= 32 bits) - words_32b = textwrap.wrap(val, 8) - words_32b.reverse() - for word_32b in words_32b: - f.write(word_32b + "\n") - else: - raise Exception("Decoupled weight export not yet implemented") - else: - raise Exception("Unknown weight_file_mode") - - def generate_params(self, model, path): - code_gen_dir = path - thresholds = model.get_initializer(self.onnx_node.input[1]) - mem_mode = self.get_nodeattr("mem_mode") - if mem_mode == "const": - # save thresholds in thresh.h - weight_filename = "{}/thresh.h".format(code_gen_dir) - self.make_weight_file(thresholds, "hls_header", weight_filename) - elif mem_mode == "decoupled": - # save decoupled weights for cppsim - weight_filename_sim = "{}/thresholds.npy".format(code_gen_dir) - self.make_weight_file(thresholds, "decoupled_npy", weight_filename_sim) - # also save weights as Verilog .dat file - # This file will be ignored when synthesizing UltraScale memory. - weight_filename_rtl = "{}/memblock.dat".format(code_gen_dir) - self.make_weight_file(thresholds, "decoupled_verilog_dat", weight_filename_rtl) - else: - raise Exception("Unrecognized mem_mode") - - def execute_node(self, context, graph): - mode = self.get_nodeattr("exec_mode") - node = self.onnx_node - - # TODO ensure codegen dir exists - if mode == "cppsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - elif mode == "rtlsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) - - # create a npy file fore each input of the node (in_ind is input index) - in_ind = 0 - for inputs in node.input: - # it is assumed that the first input of the node is the data input - # the second input are the weights - # the third input are the thresholds - if in_ind == 0: - assert ( - str(context[inputs].dtype) == "float32" - ), """Input datatype is - not float32 as expected.""" - expected_inp_shape = self.get_folded_input_shape() - reshaped_input = context[inputs].reshape(expected_inp_shape) - if self.get_input_datatype() == DataType["BIPOLAR"]: - # store bipolar activations as binary - reshaped_input = (reshaped_input + 1) / 2 - export_idt = DataType["BINARY"] - else: - export_idt = self.get_input_datatype() - # make copy before saving the array - reshaped_input = reshaped_input.copy() - np.save( - os.path.join(code_gen_dir, "input_{}.npy".format(in_ind)), - reshaped_input, - ) - elif in_ind > 2: - raise Exception("Unexpected input found for Thresholding_Batch") - in_ind += 1 - - if mode == "cppsim": - # execute the precompiled model - super().exec_precompiled_singlenode_model() - # load output npy file - super().npy_to_dynamic_output(context) - # reinterpret binary output as bipolar where needed - if self.get_output_datatype() == DataType["BIPOLAR"]: - out = context[node.output[0]] - out = 2 * out - 1 - context[node.output[0]] = out - oshape = self.get_normal_output_shape() - assert context[node.output[0]].shape == oshape, """Output shape is not as expected""" - elif mode == "rtlsim": - sim = self.get_rtlsim() - nbits = self.get_instream_width() - inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) - super().reset_rtlsim(sim) - super().toggle_clk(sim) - if self.get_nodeattr("mem_mode") == "decoupled": - wnbits = self.get_weightstream_width() - export_wdt = self.get_weight_datatype() - wei = npy_to_rtlsim_input( - "{}/thresholds.npy".format(code_gen_dir), export_wdt, wnbits - ) - num_w_reps = np.prod(self.get_nodeattr("numInputVectors")) - io_dict = { - "inputs": {"in0": inp, "weights": wei * num_w_reps}, - "outputs": {"out": []}, - } - self.rtlsim_multi_io(sim, io_dict) - output = io_dict["outputs"]["out"] - elif self.get_nodeattr("mem_mode") == "const": - output = self.rtlsim(sim, inp) - else: - raise Exception("Unrecognized mem_mode") - odt = self.get_output_datatype() - target_bits = odt.bitwidth() - packed_bits = self.get_outstream_width() - out_npy_path = "{}/output.npy".format(code_gen_dir) - out_shape = self.get_folded_output_shape() - rtlsim_output_to_npy(output, out_npy_path, odt, out_shape, packed_bits, target_bits) - - # load and reshape output - output = np.load(out_npy_path) - oshape = self.get_normal_output_shape() - output = np.asarray([output], dtype=np.float32).reshape(*oshape) - context[node.output[0]] = output - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) - - def global_includes(self): - self.code_gen_dict["$GLOBALS$"] = ['#include "activations.hpp"'] - if self.get_nodeattr("mem_mode") == "const": - self.code_gen_dict["$GLOBALS$"] += ['#include "thresh.h"'] - - # TODO check and add whatever missing - def defines(self, var): - numReps = 1 - numInputVectors = list(self.get_nodeattr("numInputVectors")) - total_spatial_size = int(np.prod(numInputVectors)) - - self.code_gen_dict["$DEFINES$"] = [ - """#define NumChannels1 {}\n #define PE1 {}\n #define numReps {}\n - #define ImgDim1 {}""".format( - self.get_nodeattr("NumChannels"), - self.get_nodeattr("PE"), - numReps, - total_spatial_size, - ) - ] - if self.get_nodeattr("mem_mode") == "decoupled": - self.code_gen_dict["$DEFINES$"].append( - "#define ActVal1 %d" % self.get_nodeattr("ActVal") - ) - self.code_gen_dict["$DEFINES$"].append( - "#define ThresType1 %s" % self.get_weight_datatype().get_hls_datatype_str() - ) - self.code_gen_dict["$DEFINES$"].append( - "#define NumSteps1 %d" % self.get_nodeattr("numSteps") - ) - - def read_npy_data(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_input_datatype() - elem_bits = dtype.bitwidth() - packed_bits = self.get_instream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_in = "%s/input_0.npy" % code_gen_dir - self.code_gen_dict["$READNPYDATA$"] = [] - # note: the innermost dim is reversed for the input - self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s, false);' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - npy_in, - self.hls_sname(), - ) - ) - mem_mode = self.get_nodeattr("mem_mode") - if mem_mode == "decoupled": - tdt = self.get_weight_datatype() - elem_bits = tdt.bitwidth() - packed_bits = self.get_weightstream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = tdt.get_hls_datatype_str() - npy_type = "float" - npy_in = "%s/thresholds.npy" % code_gen_dir - - self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", weights_%s, false, ImgDim1);' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - npy_in, - self.hls_sname(), - ) - ) - - def strm_decl(self): - self.code_gen_dict["$STREAMDECLARATIONS$"] = [] - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0_{} ("in0_{}");'.format( - self.get_instream_width(), self.hls_sname(), self.hls_sname() - ) - ) - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out_{} ("out_{}");'.format( - self.get_outstream_width(), self.hls_sname(), self.hls_sname() - ) - ) - mem_mode = self.get_nodeattr("mem_mode") - if mem_mode == "decoupled": - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> weights_{} ("weights_{}");'.format( - self.get_weightstream_width(), self.hls_sname(), self.hls_sname() - ) - ) - - def docompute(self): - tmpl_args = self.get_template_param_values() - node = self.onnx_node - mem_mode = self.get_nodeattr("mem_mode") - if mem_mode == "const": - self.code_gen_dict["$DOCOMPUTE$"] = [ - """{} - (in0_{}, out_{}, threshs, numReps);""".format( - node.op_type, - tmpl_args["TSrcI"], - tmpl_args["TDstI"], - self.hls_sname(), - self.hls_sname(), - ) - ] - elif mem_mode == "decoupled": - # note that numReps is set to 1 in the invocation below, since - # - for cppsim the repetition comes from the threshold stream reader+input - # - for synth the unit runs continuously anyway (ap_ctrl_none) - self.code_gen_dict["$DOCOMPUTE$"] = [ - """{} - (in0_{}, out_{}, weights_{}, numReps);""".format( - "Thresholding_Stream_Batch", - tmpl_args["TSrcI"], - tmpl_args["TDstI"], - self.hls_sname(), - self.hls_sname(), - self.hls_sname(), - ) - ] - else: - raise Exception("Unrecognized mem_mode") - - def dataoutstrm(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_output_datatype() - if dtype == DataType["BIPOLAR"]: - # use binary for bipolar storage - dtype = DataType["BINARY"] - elem_bits = dtype.bitwidth() - packed_bits = self.get_outstream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_out = "%s/output.npy" % code_gen_dir - shape = self.get_folded_output_shape() - shape_cpp_str = str(shape).replace("(", "{").replace(")", "}") - - # note: the innermost dim is not reversed for the output - self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s", false);' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - self.hls_sname(), - shape_cpp_str, - npy_out, - ) - ] - - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - - def blackboxfunction(self): - if self.get_nodeattr("mem_mode") == "const": - self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - """void {}(hls::stream> &in0_{}, - hls::stream> &out_{} - )""".format( - self.onnx_node.name, - self.get_instream_width(), - self.hls_sname(), - self.get_outstream_width(), - self.hls_sname(), - ) - ] - elif self.get_nodeattr("mem_mode") == "decoupled": - self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - """void {}(hls::stream> &in0_{}, - hls::stream> &weights_{}, - hls::stream> &out_{} - )""".format( - self.onnx_node.name, - self.get_instream_width(), - self.hls_sname(), - self.get_weightstream_width(), - self.hls_sname(), - self.get_outstream_width(), - self.hls_sname(), - ) - ] - else: - raise Exception("Unrecognized mem_mode") - - def pragmas(self): - self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() - ] - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() - ) - self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") - - if self.get_nodeattr("mem_mode") == "const": - # the threshold tensor is acc_type [PE][TMEM][N_THRES] - # partition for parallel access along PE and N_THRES - # dimensions (dims 1 and 3) - self.code_gen_dict["$PRAGMAS$"].append( - ("#pragma HLS ARRAY_PARTITION variable=threshs.m_thresholds " "complete dim=1") - ) - self.code_gen_dict["$PRAGMAS$"].append( - ("#pragma HLS ARRAY_PARTITION variable=threshs.m_thresholds " "complete dim=3") - ) - # set resource type - ram_style = self.get_nodeattr("ram_style") - pe = self.get_nodeattr("PE") - ich = self.get_nodeattr("NumChannels") - # if PE less than NumChannels, assign cores according to ram_style; - # otherwise if PE == NumChannels, Vivado HLS will unroll to FFs - if pe < ich: - if ram_style == "distributed": - self.code_gen_dict["$PRAGMAS$"].append( - ("#pragma HLS RESOURCE variable=threshs.m_thresholds " "core=ROM_2P_LUTRAM") - ) - elif ram_style == "block": - self.code_gen_dict["$PRAGMAS$"].append( - ("#pragma HLS RESOURCE variable=threshs.m_thresholds " "core=ROM_2P_BRAM") - ) - else: - raise Exception( - """Invalid value for attribute ram_style! Is currently set to: {} - has to be set to one of ("block", "distributed")""".format( - ram_style - ) - ) - elif self.get_nodeattr("mem_mode") == "decoupled": - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=weights_" + self.hls_sname() - ) - - def code_generation_ipi(self): - cmd = [] - # add streamer if needed - mem_mode = self.get_nodeattr("mem_mode") - if mem_mode == "decoupled": - node_name = self.onnx_node.name - runtime_writable = self.get_nodeattr("runtime_writeable_weights") == 1 - sname = self.hls_sname() - # create a hierarchy for this layer, with the same port names - clk_name = self.get_verilog_top_module_intf_names()["clk"][0] - rst_name = self.get_verilog_top_module_intf_names()["rst"][0] - dout_name = self.get_verilog_top_module_intf_names()["m_axis"][0][0] - din_name = self.get_verilog_top_module_intf_names()["s_axis"][0][0] - cmd.append("create_bd_cell -type hier %s" % node_name) - cmd.append("create_bd_pin -dir I -type clk /%s/%s" % (node_name, clk_name)) - cmd.append("create_bd_pin -dir I -type rst /%s/%s" % (node_name, rst_name)) - cmd.append( - "create_bd_intf_pin -mode Master " - "-vlnv xilinx.com:interface:axis_rtl:1.0 /%s/%s" % (node_name, dout_name) - ) - cmd.append( - "create_bd_intf_pin -mode Slave " - "-vlnv xilinx.com:interface:axis_rtl:1.0 /%s/%s" % (node_name, din_name) - ) - # instantiate the hls ip - cmd.append( - "create_bd_cell -type ip -vlnv %s /%s/%s" - % (self.get_nodeattr("ip_vlnv"), node_name, node_name) - ) - # instantiate a streamer and connect it to the HLS IP - strm_vlnv = "amd.com:finn:memstream:1.0" - strm_inst = node_name + "_wstrm" - cmd.append( - "create_bd_cell -type ip -vlnv %s /%s/%s" % (strm_vlnv, node_name, strm_inst) - ) - cmd.append( - "set_property -dict [list " - "CONFIG.DEPTH {%d} " - "CONFIG.WIDTH {%d} " - "CONFIG.INIT_FILE {%s} " - "CONFIG.RAM_STYLE {%s} " - "] [get_bd_cells /%s/%s]" - % ( - self.calc_tmem(), - self.get_weightstream_width_padded(), - self.get_nodeattr("code_gen_dir_ipgen") + "/memblock.dat", - self.get_nodeattr("ram_style"), - node_name, - strm_inst, - ) - ) - cmd.append( - "connect_bd_intf_net [get_bd_intf_pins %s/%s/m_axis_0] " - "[get_bd_intf_pins %s/%s/weights_%s]" - % (node_name, strm_inst, node_name, node_name, sname) - ) - cmd.append( - "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/ap_rst_n]" - % (node_name, rst_name, node_name, strm_inst) - ) - cmd.append( - "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/ap_clk]" - % (node_name, clk_name, node_name, strm_inst) - ) - cmd.append( - "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/%s]" - % (node_name, rst_name, node_name, node_name, rst_name) - ) - cmd.append( - "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s/%s]" - % (node_name, clk_name, node_name, node_name, clk_name) - ) - cmd.append( - "connect_bd_intf_net [get_bd_intf_pins %s/%s] " - "[get_bd_intf_pins %s/%s/%s]" - % (node_name, din_name, node_name, node_name, din_name) - ) - cmd.append( - "connect_bd_intf_net [get_bd_intf_pins %s/%s] " - "[get_bd_intf_pins %s/%s/%s]" - % (node_name, dout_name, node_name, node_name, dout_name) - ) - if runtime_writable: - # expose axi lite interface for writeable weights - axilite_name = self.get_verilog_top_module_intf_names()["axilite"][0] - cmd.append( - "create_bd_intf_pin -mode Slave " - "-vlnv xilinx.com:interface:aximm_rtl:1.0 /%s/%s" % (node_name, axilite_name) - ) - cmd.append( - "connect_bd_intf_net [get_bd_intf_pins %s/%s] " - "[get_bd_intf_pins %s/%s/%s]" - % (node_name, axilite_name, node_name, strm_inst, axilite_name) - ) - # TODO calculate and pass in segment size here - cmd.append("assign_bd_address") - cmd.append("save_bd_design") - elif mem_mode == "const": - # base class impl sufficient for const mode - return super().code_generation_ipi() - else: - raise Exception("Unrecognized mem_mode for Thresholding_Batch") - return cmd - - def get_verilog_top_module_intf_names(self): - intf_names = super().get_verilog_top_module_intf_names() - mem_mode = self.get_nodeattr("mem_mode") - if mem_mode == "decoupled": - # only expose axilite interface if attribute is set - runtime_writable = self.get_nodeattr("runtime_writeable_weights") == 1 - if runtime_writable: - intf_names["axilite"] = ["s_axilite"] - return intf_names - - def get_op_and_param_counts(self): - ret_dict = {} - weight_bits = self.get_weight_datatype().bitwidth() - out_features = self.get_nodeattr("NumChannels") - num_steps = self.get_nodeattr("numSteps") - # thresholds are called weights in this layer - thres_param_type = "param_threshold_%db" % (weight_bits) - thres_count = out_features * num_steps - ret_dict[thres_param_type] = thres_count - return ret_dict - - def ipgen_extra_directives(self): - "Return a list of extra tcl directives for HLS synthesis." - - return ["config_compile -pipeline_style frp"] - - def derive_characteristic_fxns(self, period): - n_inps = np.prod(self.get_folded_input_shape()[:-1]) - io_dict = { - "inputs": { - "in0": [0 for i in range(n_inps)], - }, - "outputs": {"out": []}, - } - mem_mode = self.get_nodeattr("mem_mode") - if mem_mode in ["decoupled", "external"]: - n_weight_inps = self.calc_tmem() - num_w_reps = np.prod(self.get_nodeattr("numInputVectors")) - io_dict["inputs"]["weights"] = [0 for i in range(num_w_reps * n_weight_inps)] - super().derive_characteristic_fxns(period, override_rtlsim_dict=io_dict) diff --git a/src/finn/custom_op/fpgadataflow/thresholding_binary_search.py b/src/finn/custom_op/fpgadataflow/thresholding_binary_search.py deleted file mode 100755 index cde0d8dc79..0000000000 --- a/src/finn/custom_op/fpgadataflow/thresholding_binary_search.py +++ /dev/null @@ -1,766 +0,0 @@ -# Copyright (C) 2022, Advanced Micro Devices, Inc. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# * Redistributions of source code must retain the above copyright notice, this -# list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# * Neither the name of FINN nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -import math -import numpy as np -import os -import shutil -import warnings -from pyverilator.util.axi_utils import rtlsim_multi_io -from qonnx.core.datatype import DataType -from qonnx.util.basic import ( - interleave_matrix_outer_dim_from_partitions, - roundup_to_integer_multiple, -) - -from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp -from finn.util.basic import ( - find_next_power_of_2, - get_memutil_alternatives, - get_rtlsim_trace_depth, - make_build_dir, - mem_primitives_versal, - pyverilate_get_liveness_threshold_cycles, -) -from finn.util.data_packing import ( - npy_to_rtlsim_input, - pack_innermost_dim_as_hex_string, - rtlsim_output_to_npy, -) - -try: - from pyverilator import PyVerilator -except ModuleNotFoundError: - PyVerilator = None - -"""@package thresholding_binary_search -- ONNX i/o tensor shape assumptions for Thresholding: -- input 0 is the input tensor, shape (..., NumChannels) -- input 1 is the threshold tensor, shape (NumChannels, n_thres) -- output 0 is the output tensor, shape (..., NumChannels) - same as input -- the '...' here can be any shape (representing groups of vectors) - -This module creates an RTL IP, HLS is not supported. See 'thresholding_batch' -for a HLS equivalent. -""" - - -class Thresholding_Binary_Search(HLSCustomOp): - """Class that corresponds to finn-rtllib 'thresholding' function.""" - - def __init__(self, onnx_node, **kwargs): - super().__init__(onnx_node, **kwargs) - - def get_nodeattr_types(self): - my_attrs = { - # parallelization; channels thresholded per cycle - "PE": ("i", True, 0), - # number of channels (each may have different thresholds) - "NumChannels": ("i", True, 0), - # number of steps in thresholding function. Used only in decoupled mode - "numSteps": ("i", True, 1), - # FINN DataTypes for inputs, outputs - "inputDataType": ("s", True, ""), - "weightDataType": ("s", True, ""), - "outputDataType": ("s", True, ""), - # number of input vectors, examples: - # [1] is a single vector (like a FC layer with batch=1) - # [4] is four vectors (like a FC layer with batch=4) - # [1, 4, 4] is four * four vectors (like a conv layer with batch=1) - "numInputVectors": ("ints", False, [1]), - # name of the top module in verilog template. Used by PyVerilator - # and IPI generation - "gen_top_module": ("s", False, ""), - # bias to be applied to outputs of the node - "activation_bias": ("i", False, 0), - # whether weights (thresholds) will be - # writable through an AXI-lite interface during runtime - # 1 for enabled, 0 for disabled. - "runtime_writeable_weights": ("i", False, 0, {0, 1}), - # memory depth triggers for threshold storage - "depth_trigger_uram": ("i", False, 0), - "depth_trigger_bram": ("i", False, 0), - # enable uniform thres optimization - # doesn't actually do anything yet, only - # for resource estimations - "uniform_thres": ("i", False, 0, {0, 1}), - # enable deep pipelining for easier timing closure - # setting to 0 may save some FFs but otherwise leave on - "deep_pipeline": ("i", False, 1, {0, 1}), - } - my_attrs.update(super().get_nodeattr_types()) - return my_attrs - - def get_pe_mem_geometries(self): - pe = self.get_nodeattr("PE") - wdt = self.get_weight_datatype() - wdt_bits = wdt.bitwidth() - odt = self.get_output_datatype() - odt_bits = odt.bitwidth() - t_channels = self.get_nodeattr("NumChannels") - cf = t_channels / pe - is_uniform = self.get_nodeattr("uniform_thres") - if is_uniform: - ret = [(odt_bits - x, cf * (2**x)) for x in range(1, odt_bits)] - else: - ret = [(wdt_bits, (cf) * 2**x) for x in range(odt_bits)] - return ret - - def get_memory_estimate(self): - res_dict = {} - depth_trigger_bram = self.get_nodeattr("depth_trigger_bram") - depth_trigger_uram = self.get_nodeattr("depth_trigger_uram") - pe = self.get_nodeattr("PE") - ret = self.get_pe_mem_geometries() - for mem_cfg in ret: - (width, depth) = mem_cfg - primitives = mem_primitives_versal - if depth_trigger_bram != 0 or depth_trigger_uram != 0: - if depth >= depth_trigger_bram and depth < depth_trigger_uram: - primitives = {k: v for (k, v) in mem_primitives_versal.items() if "BRAM" in k} - elif depth >= depth_trigger_uram: - primitives = {k: v for (k, v) in mem_primitives_versal.items() if "URAM" in k} - alts = get_memutil_alternatives(mem_cfg, primitives) - primary_alt = alts[0] - res_type = primary_alt[0].split("_")[0] - res_count, eff, waste = primary_alt[1] - res_dict[res_type] = res_dict.get(res_type, 0) + pe * res_count - return res_dict - - def calc_tmem(self): - """Calculates and returns TMEM.""" - num_channels = self.get_nodeattr("NumChannels") - pe = self.get_nodeattr("PE") - return num_channels // pe - - def make_shape_compatible_op(self, model): - oshape = self.get_normal_output_shape() - return super().make_const_shape_op(oshape) - - def infer_node_datatype(self, model): - """Used for FINN DataType inference: set the output tensors' datatypes - accordingly for this node""" - node = self.onnx_node - idt = model.get_tensor_datatype(node.input[0]) - if idt != self.get_input_datatype(): - warn_str = "inputDataType changing for %s: %s -> %s " % ( - node.name, - str(self.get_input_datatype().name), - str(idt.name), - ) - warnings.warn(warn_str) - self.set_nodeattr("inputDataType", idt.name) - # set output datatype from property - odt = self.get_output_datatype() - model.set_tensor_datatype(node.output[0], odt) - - def verify_node(self): - """Required by the FINN nalysis module. Checks if custom ops in graph - are correctly built, with all attributes and inputs.""" - return [] - - def bram_estimation(self): - res_dict = self.get_memory_estimate() - return res_dict.get("BRAM", 0) - - def uram_estimation(self): - res_dict = self.get_memory_estimate() - return res_dict.get("URAM", 0) - - def lut_estimation(self): - res_dict = self.get_memory_estimate() - return res_dict.get("LUTRAM", 0) - - def get_input_datatype(self, ind=0): - return DataType[self.get_nodeattr("inputDataType")] - - def get_output_datatype(self, ind=0): - return DataType[self.get_nodeattr("outputDataType")] - - def get_weight_datatype(self): - """The term 'weights' and 'thresholds' are used interchangably in this class.""" - return DataType[self.get_nodeattr("weightDataType")] - - def minimize_accumulator_width(self, model): - "Minimize threshold width ('accumulator width' here due to convention)" - thresholds = model.get_initializer(self.onnx_node.input[1]) - threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds) - min_threshold = thresholds.min() - max_threshold = thresholds.max() - min_input = self.get_input_datatype().min() - max_input = self.get_input_datatype().max() - # get range required by threshold values - tdt_min = min(min_input, min_threshold) - tdt_max = max(max_input, max_threshold) - if tdt_min < 0: - if abs(tdt_min) > tdt_max: - tdt = DataType.get_smallest_possible(tdt_min) - else: - tdt = DataType.get_smallest_possible(-tdt_max - 1) - else: - tdt = DataType.get_smallest_possible(tdt_max) - assert np.vectorize(tdt.allowed)( - threshold_tensor - ).all(), "Thresholds can't be expressed with type %s" % str(tdt) - self.set_nodeattr("weightDataType", tdt.name) - return DataType[self.get_nodeattr("weightDataType")] - - def get_instream_width(self, ind=0): - i_bits = self.get_input_datatype().bitwidth() - return i_bits * self.get_nodeattr("PE") - - def get_outstream_width(self, ind=0): - o_bits = self.get_output_datatype().bitwidth() - return o_bits * self.get_nodeattr("PE") - - def get_weightstream_width(self): - """Returns weight stream width""" - pe = self.get_nodeattr("PE") - wp = self.get_weight_datatype().bitwidth() - n_thres_steps = self.get_nodeattr("numSteps") - w_width = pe * wp * n_thres_steps - return w_width - - def get_folded_input_shape(self, ind=0): - fold = self.calc_tmem() - pe = self.get_nodeattr("PE") - vecs = list(self.get_nodeattr("numInputVectors")) - folded_input_shape = tuple(vecs + [fold, pe]) - return folded_input_shape - - def get_folded_output_shape(self, ind=0): - # same shape as input - return self.get_folded_input_shape() - - def get_normal_input_shape(self, ind=0): - num_channels = self.get_nodeattr("NumChannels") - vecs = list(self.get_nodeattr("numInputVectors")) - normal_input_shape = tuple(vecs + [num_channels]) - return normal_input_shape - - def get_normal_output_shape(self, ind=0): - # same shape as input - return self.get_normal_input_shape() - - def get_number_output_values(self): - return np.prod(self.get_folded_output_shape()[:-1]) - - def get_exp_cycles(self): - # Channels/PE * batch size * fmdim * fmdim - return np.prod(self.get_folded_output_shape()[:-1]) - - def get_hls_compatible_threshold_tensor(self, orig_thres_matrix): - """Convert the original numpy weight matrix orig_weight_matrix into - a form suitable for passing to the hlslib call: - * ensure MH % PE == 0 - * for unsigned inputs, ensure thresholds are positive - * interleave rows between PEs - * reshape into (PE, TMEM, n_thres_steps) and return - """ - mh = self.get_nodeattr("NumChannels") - pe = self.get_nodeattr("PE") - tmem = mh // pe - assert mh % pe == 0, "Requirement NumChannels divisable by PE is violated." - assert ( - orig_thres_matrix.ndim == 2 - ), """Threshold matrix dimension is - not as expected (2).""" - n_thres_steps = orig_thres_matrix.shape[1] - assert n_thres_steps == self.get_nodeattr("numSteps"), "Mismatch in threshold steps" - if not self.get_input_datatype().signed(): - # ensure all thresholds are nonnegative - assert (orig_thres_matrix >= 0).all() - # ensure all thresholds are integer - assert np.equal(np.mod(orig_thres_matrix, 1), 0).all(), "Need int threshold tensor" - ret = orig_thres_matrix - # ensure channels = mh , duplicating if necessary - if ret.shape[0] == 1: - ret = np.tile(ret, (mh, 1)) - assert ret.shape[0] == mh, "Channels of threshold matrix are not as expected (mh)" - # distribute rows between PEs - ret = interleave_matrix_outer_dim_from_partitions(ret, pe) - assert ( - ret.shape[0] == pe - ), """First dimension after distribution of the - rows between PEs is not as expected (pe)""" - assert ( - ret.shape[1] == tmem - ), """Second dimension after distribution of the - rows between PEs is not as expected (tmem)""" - assert ( - ret.shape[2] == n_thres_steps - ), """Third dimension after distribution of the - rows between PEs is not as expected (n_thres_steps)""" - return ret.reshape(1, pe, tmem, n_thres_steps) - - def get_all_meminit_filenames(self, abspath=False): - "Return a list of all .dat memory initializer files used for this node" - dat_files = [] - t_path = self.get_nodeattr("code_gen_dir_ipgen") if abspath else "." - pe = self.get_nodeattr("PE") - output_data_type = self.get_nodeattr("outputDataType") # output precision - o_bitwidth = DataType[output_data_type].bitwidth() - for stage in range(o_bitwidth): - for pe_value in range(pe): - thresh_file = t_path + "/%s_threshs_%s_%s.dat" % ( - self.onnx_node.name, - pe_value, - stage, - ) - dat_files.append(thresh_file) - return dat_files - - def prepare_codegen_rtl_values(self, model): - """All dictionary values produced in this function are to replace - their key value(s) in the RTL template files""" - code_gen_dict = {} - - # TODO check for sortedness and size here? - # RTL component currently always expects 2^N-1 thresholds, but - # sometimes we have fewer due to e.g. narrow range quantization - thresholds = model.get_initializer(self.onnx_node.input[1]) - # add dummy dimension as final dimension (that's what gets packed with next call) - thresholds = np.expand_dims(thresholds, axis=-1) - wdt = self.get_weight_datatype() - bw_hexdigit = roundup_to_integer_multiple(wdt.bitwidth(), 4) - t_packed = pack_innermost_dim_as_hex_string( - thresholds, - wdt, - bw_hexdigit, - prefix="", - ) - - t_path = self.get_nodeattr("code_gen_dir_ipgen") - pe = self.get_nodeattr("PE") - output_data_type = self.get_nodeattr("outputDataType") # output precision - o_bitwidth = DataType[output_data_type].bitwidth() - num_channels = self.get_nodeattr("NumChannels") # number of channels - - channel_fold = int(num_channels / pe) - - for stage in range(o_bitwidth): - sn = o_bitwidth - stage - 1 - for pe_value in range(pe): - thresh_file = t_path + "/%s_threshs_%s_%s.dat" % ( - self.onnx_node.name, - pe_value, - stage, - ) - threshs = np.zeros([channel_fold * (2**stage)], dtype="object") - for ch in range(channel_fold): - for i in range(2**stage): - threshs[(ch << stage) + i] = t_packed[ch * pe + pe_value][ - (i << (o_bitwidth - stage)) + 2**sn - 1 - ] - with open(thresh_file, "w") as f: - for val in threshs: - f.write(val + "\n") - code_gen_dict["$THRESHOLDS_PATH$"] = ['"./%s_"' % self.onnx_node.name] - - # Identify the module name - code_gen_dict["$MODULE_NAME_AXI_WRAPPER$"] = [ - self.get_verilog_top_module_name() + "_axi_wrapper" - ] - # Set the top module name - AXI wrapper - code_gen_dict["$TOP_MODULE$"] = code_gen_dict["$MODULE_NAME_AXI_WRAPPER$"] - - # Identify the module variables - input_data_type = self.get_nodeattr("inputDataType") # input/threshold precision - bias = self.get_nodeattr("activation_bias") # activation bias value - i_bitwidth = DataType[input_data_type].bitwidth() - - code_gen_dict["$N$"] = [str(o_bitwidth)] # output precision - convert bitwidth to string - code_gen_dict["$M$"] = [ - str(i_bitwidth) - ] # input/threshold precision - convert bitwidth to string - code_gen_dict["$C$"] = [str(num_channels)] # number of channels - code_gen_dict["$BIAS$"] = [str(bias)] # activation bias value - code_gen_dict["$PE$"] = [str(pe)] # requires C = M*PE - - # Is the input datatype signed or unsigned? - # The thresholding core needs to know this when comparing weights to inputs - if self.get_input_datatype().signed(): - code_gen_dict["$SIGNED$"] = [str(1)] - else: - code_gen_dict["$SIGNED$"] = [str(0)] - - if bias >= 0: - o_bits = math.ceil(math.log2(2**o_bitwidth + bias)) - else: - o_bits = 1 + math.ceil( - math.log2(-bias if -bias >= 2 ** (o_bitwidth - 1) else 2**o_bitwidth + bias) - ) - - code_gen_dict["$O_BITS$"] = [str(int(o_bits))] - - rt_weights = self.get_nodeattr("runtime_writeable_weights") - code_gen_dict["$USE_AXILITE$"] = [str(rt_weights)] - - depth_trigger_uram = self.get_nodeattr("depth_trigger_uram") - depth_trigger_bram = self.get_nodeattr("depth_trigger_bram") - deep_pipeline = self.get_nodeattr("deep_pipeline") - code_gen_dict["$DEPTH_TRIGGER_URAM$"] = [str(depth_trigger_uram)] - code_gen_dict["$DEPTH_TRIGGER_BRAM$"] = [str(depth_trigger_bram)] - code_gen_dict["$DEEP_PIPELINE$"] = [str(deep_pipeline)] - return code_gen_dict - - def get_rtl_file_list(self): - """Thresholding binary search RTL file list""" - return [ - "axilite_if.v", - "thresholding.sv", - "thresholding_axi.sv", - "thresholding_template_wrapper.v", - ] - - def get_rtl_file_paths(self): - """Get full path of all RTL files""" - rtl_root_dir = os.environ["FINN_ROOT"] + "/finn-rtllib/thresholding/hdl/" - rtl_file_list = self.get_rtl_file_list() - rtl_file_paths = [rtl_root_dir + file for file in rtl_file_list] - return rtl_file_paths - - def get_rtl_template_data(self, path): - """Return RTL file contents as a template""" - with open(path, "r") as f: - template = f.read() - return template - - def fill_in_rtl_template_data(self, replace_dict, template_data): - """Use attribute values to finn in RTL template placeholders""" - template_data_cp = template_data - for key in replace_dict: - replacement_line = "\n".join(replace_dict[key]) - template_data_cp = template_data_cp.replace(key, replacement_line) - return template_data_cp - - def dump_rtl_data(self, dest_dir, filename, data): - """Dump filled-in-template RTL files for future synthesis step""" - # when generating template files, handle a special case: - # if the filename contains the word "template", replace that - # with the node name to distinguish between instances - filename = filename.replace("template", self.onnx_node.name) - with open(os.path.join(dest_dir, filename), "w") as f: - f.write(data) - return - - def generate_hdl(self, model): - """Prepare HDL files from templates for synthesis""" - # Generate a dictionary of values to put in RTL template - code_gen_dict = self.prepare_codegen_rtl_values(model) - - # Retrieve the destination directory for the final RTL files - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - - for rtl_file_path in self.get_rtl_file_paths(): - # read in original RTL template file - template_data = self.get_rtl_template_data(rtl_file_path) - # apply code generation to templates - data = self.fill_in_rtl_template_data(code_gen_dict, template_data) - # dump filled-in template to destination directory for compilation - file_only_path = rtl_file_path.split("/")[-1] - self.dump_rtl_data(code_gen_dir, file_only_path, data) - - # Before we return - set the 'gen_top_module' attribute for use later - # by PyVerilator and IPI generation - self.set_nodeattr("gen_top_module", code_gen_dict["$TOP_MODULE$"][0]) - return - - def code_generation_ipgen(self, model, fpgapart, clk): - self.generate_hdl(model) - - # set ipgen_path and ip_path so that HLS-Synth transformation - # and stich_ip transformation do not complain - # i.e. during the HLSSynthIP() transformation - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - self.set_nodeattr("ipgen_path", code_gen_dir) - self.set_nodeattr("ip_path", code_gen_dir) - return - - def prepare_rtlsim(self): - """Creates a Verilator emulation library for the RTL code generated - for this node, sets the rtlsim_so attribute to its path and returns - a PyVerilator wrapper around it.""" - - if PyVerilator is None: - raise ImportError("Installation of PyVerilator is required.") - - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - verilog_paths = [code_gen_dir] - verilog_files = [x.replace("template", self.onnx_node.name) for x in self.get_rtl_file_list()] - dat_files = self.get_all_meminit_filenames(abspath=True) - single_src_dir = make_build_dir("pyverilator_" + self.onnx_node.name + "_") - for dat_file in dat_files: - shutil.copy(dat_file, single_src_dir) - - # build the Verilator emulation library - sim = PyVerilator.build( - verilog_files, - build_dir=single_src_dir, - verilog_path=verilog_paths, - trace_depth=get_rtlsim_trace_depth(), - top_module_name=self.get_nodeattr("gen_top_module"), - auto_eval=False, - ) - - # save generated lib filename in attribute - self.set_nodeattr("rtlsim_so", sim.lib._name) - return sim - - def execute_node(self, context, graph): - # Perform input checks - if self.get_nodeattr("exec_mode") != "rtlsim": - raise Exception( - "Invalid exec_mode value: {}; exec_mode must be set to '{}'".format( - self.get_nodeattr("exec_mode"), "rtlsim" - ) - ) - - node = self.onnx_node - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - - # create a npy file fore each input of the node (in_ind is input index) - in_ind = 0 - for inputs in node.input: - # it is assumed that the first input of the node is the data input - # the second input are the thresholds - if in_ind == 0: - assert ( - str(context[inputs].dtype) == "float32" - ), """Input datatype is - not float32 as expected.""" - expected_inp_shape = self.get_folded_input_shape() - reshaped_input = context[inputs].reshape(expected_inp_shape) - - if self.get_input_datatype() == DataType["BIPOLAR"]: - # store bipolar activations as binary - reshaped_input = (reshaped_input + 1) / 2 - export_idt = DataType["BINARY"] - else: - export_idt = self.get_input_datatype() - - # make copy before saving the array - reshaped_input = reshaped_input.copy() - np.save( - os.path.join(code_gen_dir, "input_{}.npy".format(in_ind)), - reshaped_input, - ) - elif in_ind > 2: - raise Exception("Unexpected input found for Thresholding_Binary_Search") - in_ind += 1 - - # Create a PyVerilator wrapper of the RTLSim .so - sim = self.get_rtlsim() - nbits = self.get_instream_width() - inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) - io_names = self.get_verilog_top_module_intf_names() - istream_name = io_names["s_axis"][0][0] - ostream_name = io_names["m_axis"][0][0] - io_dict = { - "inputs": {istream_name: inp}, - "outputs": {ostream_name: []}, - } - self.rtlsim_multi_io(sim, io_dict) - output = io_dict["outputs"][ostream_name] - - # Manage output data - odt = self.get_output_datatype() - target_bits = odt.bitwidth() - packed_bits = self.get_outstream_width() - out_npy_path = "{}/output.npy".format(code_gen_dir) - out_shape = self.get_folded_output_shape() - - rtlsim_output_to_npy(output, out_npy_path, odt, out_shape, packed_bits, target_bits) - - # load and reshape output - output = np.load(out_npy_path) - oshape = self.get_normal_output_shape() - output = np.asarray([output], dtype=np.float32).reshape(*oshape) - context[node.output[0]] = output - return - - def hls_sname(self): - """Get the naming convention used by Vitis HLS for stream signals - Example: the TDATA for a stream called "out" would be out_V_TDATA. - """ - # no additional prefix/suffix in interface names since this is an RTL component - return "" - - def rtlsim_multi_io(self, sim, io_dict): - "Run rtlsim for this node, supports multiple i/o streams." - - rtlsim_so = self.get_nodeattr("rtlsim_so") - so_dir = os.path.dirname(os.path.realpath(rtlsim_so)) - olcwd = os.getcwd() - os.chdir(so_dir) - - # signal name prefix - # TODO if the interface names on this component get standardized, - # it won't need its own rtlsim_multi_io variant anymore and can just - # use the base class one - sname = "_" - - trace_file = self.get_nodeattr("rtlsim_trace") - if trace_file == "default": - trace_file = self.onnx_node.name + ".vcd" - num_out_values = self.get_number_output_values() - total_cycle_count = rtlsim_multi_io( - sim, - io_dict, - num_out_values, - trace_file=trace_file, - sname=sname, - do_reset=True, - liveness_threshold=pyverilate_get_liveness_threshold_cycles(), - ) - self.set_nodeattr("cycles_rtlsim", total_cycle_count) - os.chdir(olcwd) - - def code_generation_ipi(self): - """Constructs and returns the TCL commands for node instantiation as an RTL - block.""" - rtl_file_list = [x.replace("template", self.onnx_node.name) for x in self.get_rtl_file_list()] - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - source_target = "./ip/verilog/rtl_ops/%s" % self.onnx_node.name - cmd = ["file mkdir %s" % source_target] - - for rtl_file in rtl_file_list: - cmd.append( - "add_files -copy_to %s -norecurse %s" - % (source_target, os.path.join(code_gen_dir, rtl_file)) - ) - - # Create an RTL block, not an IP core (-type ip) - cmd.append( - "create_bd_cell -type module -reference %s %s" - % (self.get_nodeattr("gen_top_module"), self.onnx_node.name) - ) - - return cmd - - def get_verilog_top_module_intf_names(self): - """Return a dict of names of input and output interfaces. - The keys reflect the protocols each interface implements: - 'clk', 'rst', 'm_axis', 's_axis', 'aximm', 'axilite'. - Values are lists of tuples (axis, aximm) or names (axilite): - 'axis' tuples correspond to the list of node inputs in order, - each tuple is (interface_name, interface_width_bits). - axilite always assumed to be 32 bits and is not tuple (name only). - Each block must have at most one aximm and one axilite.""" - - intf_names = {} - intf_names["clk"] = ["ap_clk"] - intf_names["rst"] = ["ap_rst_n"] - intf_names["s_axis"] = [("in0_V", self.get_instream_width_padded())] - intf_names["m_axis"] = [("out_V", self.get_outstream_width_padded())] - intf_names["aximm"] = [] - intf_names["axilite"] = [] - intf_names["ap_none"] = [] - if self.get_nodeattr("runtime_writeable_weights") == 1: - intf_names["axilite"] = ["s_axilite"] - - return intf_names - - def get_dynamic_config(self, model, address_stride=1): - """Returns a configuration dictionary containing axilite write commands - in order to program the thresholds into the RTL core during runtime. - The default address stride for the weights is 1 byte.""" - - thresholds = model.get_initializer(self.onnx_node.input[1]) - num_channels, num_weights_per_channel = thresholds.shape - - weight_addr_boundary = find_next_power_of_2(num_weights_per_channel) - # Make sure that the next power of 2 (output) is greater than the input - assert weight_addr_boundary >= num_weights_per_channel - - config = {} - channel_cntr = 0 - wdt = self.get_weight_datatype() - bw_hexdigit = roundup_to_integer_multiple(wdt.bitwidth(), 4) - for channel in thresholds: - channel_start_addr = channel_cntr * weight_addr_boundary * address_stride - weight_cntr = 0 - addr = 0 - for weight in channel: - key_name = "{}_{}{}_{}{}".format( - "axilite", "ch", str(channel_cntr), "w", str(weight_cntr) - ) - config[key_name] = ( - channel_start_addr + addr, - int( - str( - pack_innermost_dim_as_hex_string( - [weight], - wdt, - bw_hexdigit, - ) - ), - 0, - ), - ) - - weight_cntr += 1 - addr += address_stride - - channel_cntr += 1 - - return config - - def ipgen_singlenode_code(self): - """Normally: Builds the bash script for IP generation.""" - """This is needed for the HLSSynthIP() transformation. - This is an IP, not a HLS node, so therefore provide an empty hook - to prevent any HLS synthesis.""" - pass - - def global_includes(self): - pass - - def defines(self, var): - pass - - def read_npy_data(self): - pass - - def strm_decl(self): - pass - - def docompute(self): - pass - - def dataoutstrm(self): - pass - - def save_as_npy(self): - pass - - def blackboxfunction(self): - pass - - def pragmas(self): - pass From ac1478dac5774ec5d4e599213e37b19ca0ab8967 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Fri, 26 Jan 2024 16:39:46 +0000 Subject: [PATCH 420/665] [TBS] Clean up branch for HLS variant only --- finn-rtllib/thresholding/component.xml | 1002 ----------------- .../gui/thresholding_axi_v1_0.gtcl | 4 - finn-rtllib/thresholding/hdl/axilite_if.v | 210 ---- finn-rtllib/thresholding/hdl/thresholding.sv | 357 ------ .../thresholding/hdl/thresholding_axi.sv | 164 --- .../hdl/thresholding_template_wrapper.v | 120 -- finn-rtllib/thresholding/sim/thresh_gen.sv | 45 - finn-rtllib/thresholding/sim/thresholding.tcl | 17 - .../thresholding/sim/thresholding_axi_tb.sv | 314 ------ .../thresholding/sim/thresholding_tb.sv | 274 ----- .../xgui/thresholding_axi_v1_0.tcl | 187 --- src/finn/util/basic.py | 70 -- tests/util/test_basic.py | 60 - 13 files changed, 2824 deletions(-) delete mode 100644 finn-rtllib/thresholding/component.xml delete mode 100644 finn-rtllib/thresholding/gui/thresholding_axi_v1_0.gtcl delete mode 100644 finn-rtllib/thresholding/hdl/axilite_if.v delete mode 100644 finn-rtllib/thresholding/hdl/thresholding.sv delete mode 100644 finn-rtllib/thresholding/hdl/thresholding_axi.sv delete mode 100644 finn-rtllib/thresholding/hdl/thresholding_template_wrapper.v delete mode 100644 finn-rtllib/thresholding/sim/thresh_gen.sv delete mode 100644 finn-rtllib/thresholding/sim/thresholding.tcl delete mode 100644 finn-rtllib/thresholding/sim/thresholding_axi_tb.sv delete mode 100644 finn-rtllib/thresholding/sim/thresholding_tb.sv delete mode 100644 finn-rtllib/thresholding/xgui/thresholding_axi_v1_0.tcl delete mode 100755 tests/util/test_basic.py diff --git a/finn-rtllib/thresholding/component.xml b/finn-rtllib/thresholding/component.xml deleted file mode 100644 index e28a3a2c2d..0000000000 --- a/finn-rtllib/thresholding/component.xml +++ /dev/null @@ -1,1002 +0,0 @@ - - - amd.com - finn - thresholding_axi - 1.0 - - - ap_clk - - - - - - - CLK - - - ap_clk - - - - - - ASSOCIATED_RESET - ap_rst_n - - - ASSOCIATED_BUSIF - s_axilite:s_axis:m_axis - - - FREQ_TOLERANCE_HZ - -1 - - - - - m_axis - - - - - - - TDATA - - - m_axis_tdata - - - - - TVALID - - - m_axis_tvalid - - - - - TREADY - - - m_axis_tready - - - - - - s_axis - - - - - - - TDATA - - - s_axis_tdata - - - - - TVALID - - - s_axis_tvalid - - - - - TREADY - - - s_axis_tready - - - - - - s_axilite - - - - - - - - - AWADDR - - - s_axilite_AWADDR - - - - - AWVALID - - - s_axilite_AWVALID - - - - - AWREADY - - - s_axilite_AWREADY - - - - - WDATA - - - s_axilite_WDATA - - - - - WSTRB - - - s_axilite_WSTRB - - - - - WVALID - - - s_axilite_WVALID - - - - - WREADY - - - s_axilite_WREADY - - - - - BRESP - - - s_axilite_BRESP - - - - - BVALID - - - s_axilite_BVALID - - - - - BREADY - - - s_axilite_BREADY - - - - - ARADDR - - - s_axilite_ARADDR - - - - - ARVALID - - - s_axilite_ARVALID - - - - - ARREADY - - - s_axilite_ARREADY - - - - - RDATA - - - s_axilite_RDATA - - - - - RRESP - - - s_axilite_RRESP - - - - - RVALID - - - s_axilite_RVALID - - - - - RREADY - - - s_axilite_RREADY - - - - - - ap_rst_n - - - - - - - RST - - - ap_rst_n - - - - - - POLARITY - ACTIVE_LOW - - - - - - - s_axilite - s_axilite - - reg0 - reg0 - 0x0 - 4096 - 32 - register - - - - - - - xilinx_anylanguagesynthesis - Synthesis - :vivado.xilinx.com:synthesis - Verilog - thresholding_axi_wrapper - - xilinx_anylanguagesynthesis_view_fileset - - - - viewChecksum - fd0bd85b - - - - - xilinx_anylanguagebehavioralsimulation - Simulation - :vivado.xilinx.com:simulation - Verilog - thresholding_axi_wrapper - - xilinx_anylanguagebehavioralsimulation_view_fileset - - - - viewChecksum - fd0bd85b - - - - - xilinx_xpgui - UI Layout - :vivado.xilinx.com:xgui.ui - - xilinx_xpgui_view_fileset - - - - viewChecksum - fc6b9b63 - - - - - xilinx_utilityxitfiles - Utility XIT/TTCL - :vivado.xilinx.com:xit.util - - xilinx_utilityxitfiles_view_fileset - - - - viewChecksum - 8b0215cd - - - - - - - ap_clk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - ap_rst_n - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axilite_AWVALID - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axilite_AWREADY - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axilite_AWADDR - - in - - 5 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axilite_WVALID - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axilite_WREADY - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axilite_WDATA - - in - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axilite_WSTRB - - in - - 3 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 1 - - - - - s_axilite_BVALID - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axilite_BREADY - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axilite_BRESP - - out - - 1 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axilite_ARVALID - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axilite_ARREADY - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axilite_ARADDR - - in - - 5 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axilite_RVALID - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axilite_RREADY - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axilite_RDATA - - out - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axilite_RRESP - - out - - 1 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axis_tready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axis_tvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axis_tdata - - in - - 15 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - m_axis_tready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 1 - - - - - m_axis_tvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m_axis_tdata - - out - - 7 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - - N - N - 4 - - - K - K - 16 - - - C - C - 1 - - - PE - Pe - 1 - - - SIGNED - Signed - true - - - FPARG - Fparg - false - - - BIAS - Bias - 0 - - - CF - Cf - 1 - - - ADDR_BITS - Addr Bits - 6 - - - O_BITS - O Bits - 4 - - - - - - choice_list_9d8b0d81 - ACTIVE_HIGH - ACTIVE_LOW - - - - - xilinx_anylanguagesynthesis_view_fileset - - hdl/thresholding.sv - systemVerilogSource - - - hdl/thresholding_axi.sv - systemVerilogSource - - - hdl/thresholding_axi_wrapper.v - verilogSource - CHECKSUM_7b8c102d - - - hdl/axilite_if.v - verilogSource - CHECKSUM_69d1ba26 - xil_defaultlib - - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - hdl/thresholding.sv - systemVerilogSource - - - hdl/thresholding_axi.sv - systemVerilogSource - - - hdl/thresholding_axi_wrapper.v - verilogSource - - - hdl/axilite_if.v - verilogSource - USED_IN_ipstatic - xil_defaultlib - - - - xilinx_xpgui_view_fileset - - xgui/thresholding_axi_v1_0.tcl - tclSource - CHECKSUM_fc6b9b63 - XGUI_VERSION_2 - - - - xilinx_utilityxitfiles_view_fileset - - gui/thresholding_axi_v1_0.gtcl - GTCL - - - - MultiThreshold - - - N - Output Precision - 4 - - - K - Input Precision - 16 - - - C - Channels - 1 - - - PE - Pe - 1 - - - SIGNED - Signed Inputs - true - - - FPARG - Floating-Point Inputs - false - - - BIAS - Bias - 0 - - - CF - Channel Fold - 1 - - - - false - - - - - - ADDR_BITS - Address Bits - 6 - - - - false - - - - - - O_BITS - Output Value Width - 4 - - - - false - - - - - - Component_Name - thresholding_axi_wrapper_v1_0 - - - - - - virtex7 - qvirtex7 - versal - kintex7 - kintex7l - qkintex7 - qkintex7l - akintex7 - artix7 - artix7l - aartix7 - qartix7 - zynq - qzynq - azynq - spartan7 - aspartan7 - virtexu - zynquplus - virtexuplus - virtexuplusHBM - virtexuplus58g - kintexuplus - artixuplus - kintexu - - - /UserIP - - thresholding_axi - level_1 - package_project - 2 - - user.org:user:thresholding_axi_wrapper:1.0 - - 2023-06-27T05:47:20Z - - - - - - 2022.2 - - - - - - - - - - - - - - diff --git a/finn-rtllib/thresholding/gui/thresholding_axi_v1_0.gtcl b/finn-rtllib/thresholding/gui/thresholding_axi_v1_0.gtcl deleted file mode 100644 index 90d73ede7e..0000000000 --- a/finn-rtllib/thresholding/gui/thresholding_axi_v1_0.gtcl +++ /dev/null @@ -1,4 +0,0 @@ -# This file is automatically written. Do not modify. -proc gen_USERPARAMETER_CF_VALUE {C PE } {expr $C/$PE} -proc gen_USERPARAMETER_ADDR_BITS_VALUE {C PE N } {expr int(ceil(log($C/$PE)/log(2))+ceil(log($PE)/log(2))+$N+2)} -proc gen_USERPARAMETER_O_BITS_VALUE {BIAS N } {expr int(ceil($BIAS >= 0? log(pow(2,$N)+$BIAS)/log(2) : 1+log(-$BIAS >= pow(2,$N-1)? -$BIAS : pow(2,$N)+$BIAS)/log(2)))} diff --git a/finn-rtllib/thresholding/hdl/axilite_if.v b/finn-rtllib/thresholding/hdl/axilite_if.v deleted file mode 100644 index bdd4de288e..0000000000 --- a/finn-rtllib/thresholding/hdl/axilite_if.v +++ /dev/null @@ -1,210 +0,0 @@ -/* - Copyright (c) 2020, Xilinx - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - * Neither the name of FINN nor the names of its - contributors may be used to endorse or promote products derived from - this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -module axi4lite_if -#( - parameter ADDR_WIDTH = 32, - parameter DATA_WIDTH = 32,//AXI4 spec requires this to be strictly 32 or 64 - parameter IP_DATA_WIDTH = 64//can be any power-of-2 multiple of DATA_WIDTH -) -( -//system signals -input aclk, -input aresetn,//active low, asynchronous assertion and synchronous deassertion - -//Write channels -//write address -output reg awready, -input awvalid, -input [ADDR_WIDTH-1:0] awaddr, -input [2:0] awprot, -//write data -output reg wready, -input wvalid, -input [DATA_WIDTH-1:0] wdata, -input [(DATA_WIDTH/8)-1:0] wstrb, -//burst response -input bready, -output reg bvalid, -output reg [1:0] bresp,//NOTE: 00 = OKAY, 10 = SLVERR (write error) - -//Read channels -//read address -output reg arready, -input arvalid, -input [ADDR_WIDTH-1:0] araddr, -input [2:0] arprot, -//read data -input rready, -output reg rvalid, -output reg [1:0] rresp,//NOTE: 00 = OKAY, 10 = SLVERR (read error) -output reg [DATA_WIDTH-1:0] rdata, - -//IP-side interface -output reg ip_en, -output reg ip_wen, -output reg [ADDR_WIDTH-1:0] ip_addr, -output [IP_DATA_WIDTH-1:0] ip_wdata, -input ip_rack, -input [IP_DATA_WIDTH-1:0] ip_rdata -); - -localparam RESP_OKAY = 2'b00; -localparam RESP_SLVERR = 2'b10; -//get ceil(log2(ceil(IP_DATA_WIDTH/DATA_WIDTH))) -localparam NFOLDS_LOG = $clog2((IP_DATA_WIDTH + DATA_WIDTH - 1) / DATA_WIDTH); - -reg internal_ren; -reg internal_wen; -reg internal_wack; -reg [ADDR_WIDTH-1:0] internal_raddr; -reg [ADDR_WIDTH-1:0] internal_waddr; -reg [DATA_WIDTH-1:0] internal_wdata; -wire [DATA_WIDTH-1:0] internal_rdata; -reg internal_error = 0; - -//check DATA_WIDTH -initial begin - if(DATA_WIDTH != 32 & DATA_WIDTH != 64) begin - $display("AXI4Lite DATA_WIDTH must be 32 or 64"); - $finish; - end -end - -//transaction state machine -localparam STATE_IDLE = 0, - STATE_READ = 1, - STATE_WRITE = 2; - -reg [1:0] state; - -always @(posedge aclk or negedge aresetn) - if(~aresetn) - state <= STATE_IDLE; - else case(state) - STATE_IDLE: - if(awvalid & wvalid) - state <= STATE_WRITE; - else if(arvalid) - state <= STATE_READ; - STATE_READ: - if(rvalid & rready) - state <= STATE_IDLE; - STATE_WRITE: - if(bvalid & bready) - state <= STATE_IDLE; - default: state <= STATE_IDLE; - endcase - -//write-related internal signals -always @(*) begin - internal_waddr = awaddr >> $clog2(DATA_WIDTH/8); - internal_wdata = wdata; - internal_wen = (state == STATE_IDLE) & awvalid & wvalid; -end - -always @(posedge aclk) begin - awready <= internal_wen; - wready <= internal_wen; -end - -//read-related internal signals -always @(*) begin - internal_raddr = araddr >> $clog2(DATA_WIDTH/8); - internal_ren = (state == STATE_IDLE) & ~internal_wen & arvalid; -end - -always @(posedge aclk) - arready <= internal_ren; - -wire write_to_last_fold; - -always @(posedge aclk) begin - ip_wen <= write_to_last_fold; - ip_en <= internal_ren | write_to_last_fold; - if(internal_ren | write_to_last_fold) - ip_addr <= internal_ren ? (internal_raddr >> NFOLDS_LOG) : (internal_waddr >> NFOLDS_LOG); - internal_wack <= internal_wen; -end - -genvar i; -reg [(1<> (internal_rfold*DATA_WIDTH); - always @(posedge aclk) - if(internal_ren) - internal_rfold <= internal_raddr[NFOLDS_LOG-1:0]; - for(i=0; i<(1< - * - * @description - * Produces the N-bit count of those among 2^N-1 thresholds that are not - * larger than the corresponding input: - * y = Σ(T_i <= x) - * The result is computed by binary search. The runtime-configurable - * thresholds must be written in ascending order: - * i < j => T_i < T_j - * The design supports channel folding allowing each input to be processed - * with respect to a selectable set of thresholds. The corresponding - * threshold configuration relies on a channel address prefix. Inputs are - * accompanied by a channel selector. - * - * Parameter Layout as seen on AXI-Lite (row by row): - * | Base \ Offs | 0 1 2 ... 2^N-2 2^N-1 - * ---------+--------------------------------+------------------------------------ - * Chnl #0 | 0 | T_0 T_1 T_2 ... T_{2^N-2} 'x - * Chnl #1 | 2^N | T_0 T_1 T_2 ... T_{2^N-2} 'x - * Chnl #c | ((c/PE)*$clog2(PE) + c%PE)*2^N | T_0 T_1 T_2 ... T_{2^N-2} 'x - * - *****************************************************************************/ -module thresholding #( - int unsigned N, // output precision - int unsigned K, // input/threshold precision - int unsigned C, // number of channels - int unsigned PE, // parallel processing elements - - bit SIGNED = 1, // signed inputs - bit FPARG = 0, // floating-point inputs: [sign] | exponent | mantissa - int BIAS = 0, // offsetting the output [0, 2^N-1] -> [BIAS, 2^N-1 + BIAS] - - // Initial Thresholds - parameter THRESHOLDS_PATH = "", - bit USE_CONFIG = 1, - - // Force Use of On-Chip Memory Blocks - int unsigned DEPTH_TRIGGER_URAM = 0, // if non-zero, local mems of this depth or more go into URAM (prio) - int unsigned DEPTH_TRIGGER_BRAM = 0, // if non-zero, local mems of this depth or more go into BRAM - bit DEEP_PIPELINE = 0, - - localparam int unsigned CF = C/PE, // Channel fold - localparam int unsigned O_BITS = BIAS >= 0? - /* unsigned */ $clog2(2**N+BIAS) : - /* signed */ 1+$clog2(-BIAS >= 2**(N-1)? -BIAS : 2**N+BIAS) -)( - // Global Control - input logic clk, - input logic rst, - - // Threshold Configuration - input logic cfg_en, - input logic cfg_we, - input logic [$clog2(CF)+$clog2(PE)+N-1:0] cfg_a, - input logic [K-1:0] cfg_d, - output logic cfg_rack, - output logic [K-1:0] cfg_q, - - // Input Stream - output logic irdy, - input logic ivld, - input logic [PE-1:0][K-1:0] idat, - - // Output Stream - input logic ordy, - output logic ovld, - output logic [PE-1:0][O_BITS-1:0] odat -); - - // Parameter Constraints Checking - initial begin - if(CF*PE != C) begin - $error("Parallelism PE=%0d is not a multiple of channel count C=%0d.", PE, C); - $finish; - end - end - - // Operations within Pipeline - typedef enum logic [1:0] { - NOP = 2'b00, // No operation - TH = 2'b01, // Thresholding - WR = 2'b11, // Write (initialization) - RB = 2'b10, // Readback (validation) - CFG = 2'b1x // Config op (pointer-preserving) - } op_e; - - // Pipeline Link Type - typedef logic [$clog2(CF)+N-1:0] ptr_t; - typedef logic [K -1:0] val_t; - typedef struct packed { - op_e op; - ptr_t ptr; // WR/RB: address; TH: result - val_t val; // WR/RB: threshold value; TH: input value - } pipe_t; - - //----------------------------------------------------------------------- - // Pipeline Feed - // - configuration always takes precedence - // - number of pending thresholding ops capped to N+3 - // across pipeline and output FIFO: pipe:N + A:1 + B:1 + 1 - localparam int unsigned MAX_PENDING = (DEEP_PIPELINE+1)*N + 3; - pipe_t pipe[PE][N+1]; - if(1) begin : blkFeed - - // Thresholding Input Guard ensuring Output FIFO is never overrun - logic signed [$clog2(MAX_PENDING):0] GuardSem = MAX_PENDING-1; // MAX_PENDING-1, ..., 0, -1 - uwire th_full = GuardSem[$left(GuardSem)]; - always_ff @(posedge clk) begin - if(rst) GuardSem <= MAX_PENDING-1; - else begin - automatic logic dec = !(USE_CONFIG && cfg_en) && !th_full && ivld; - automatic logic inc = ovld && ordy; - GuardSem <= GuardSem + (inc == dec? 0 : inc? 1 : -1); - end - end - - // PE Configuration Address Decoding - uwire cfg_sel[PE]; - if(PE == 1) assign cfg_sel[0] = 1; - else begin - for(genvar pe = 0; pe < PE; pe++) begin - assign cfg_sel[pe] = USE_CONFIG && cfg_en && (cfg_a[N+:$clog2(PE)] == pe); - end - end - - uwire ptr_t iptr; - assign iptr[0+:N] = cfg_a[0+:N]; - if(CF > 1) begin - // Channel Fold Rotation - logic [$clog2(CF)-1:0] CnlCnt = 0; - logic CnlLst = 0; - always_ff @(posedge clk) begin - if(rst) begin - CnlCnt <= 0; - CnlLst <= 0; - end - else if(!(USE_CONFIG && cfg_en) && !th_full && ivld) begin - CnlCnt <= CnlCnt + (CnlLst? 1-CF : 1); - CnlLst <= CnlCnt == CF-2; - end - end - - assign iptr[N+:$clog2(CF)] = USE_CONFIG && cfg_en? cfg_a[N+$clog2(PE)+:$clog2(CF)] : CnlCnt; - end - - for(genvar pe = 0; pe < PE; pe++) begin - assign pipe[pe][0] = '{ - op: USE_CONFIG && cfg_en? - (!cfg_sel[pe]? NOP : cfg_we? WR : RB) : - (ivld && !th_full? TH : NOP), - ptr: iptr, - val: !(USE_CONFIG && cfg_en)? idat[pe] : cfg_we? cfg_d : 0 - }; - end - - assign irdy = !(USE_CONFIG && cfg_en) && !th_full; - end : blkFeed - - //----------------------------------------------------------------------- - // Free-Running Thresholding Pipeline - for(genvar stage = 0; stage < N; stage++) begin : genStages - - localparam int unsigned SN = N-1-stage; - for(genvar pe = 0; pe < PE; pe++) begin : genPE - uwire pipe_t p = pipe[pe][stage]; - uwire cs = (p.ptr[SN:0] == 2**SN-1); - - // Threshold Memory - val_t Thresh; // Read-out register - if(1) begin : blkThresh - localparam int unsigned DEPTH = CF * 2**stage; - localparam RAM_STYLE = - DEPTH_TRIGGER_URAM && (DEPTH >= DEPTH_TRIGGER_URAM)? "ultra" : - DEPTH_TRIGGER_BRAM && (DEPTH >= DEPTH_TRIGGER_BRAM)? "block" : - // If BRAM trigger defined, force distributed memory below if Vivado may be tempted to use BRAM nonetheless. - DEPTH_TRIGGER_BRAM && (DEPTH >= 64)? "distributed" : "auto"; - - (* RAM_STYLE = RAM_STYLE *) - val_t Threshs[DEPTH]; - if(THRESHOLDS_PATH != "") begin - initial $readmemh($sformatf("%sthreshs_%0d_%0d.dat", THRESHOLDS_PATH, pe, stage), Threshs); - end - - if(USE_CONFIG) begin : genThreshMem - uwire we = (p.op ==? WR) && cs; - if((CF == 1) && (stage == 0)) begin - always @(posedge clk) begin - if(we) Threshs[0] <= p.val; - end - end - else begin - uwire [$clog2(CF)+stage-1:0] addr = p.ptr[$clog2(CF)+N-1:SN+1]; - always @(posedge clk) begin - if(we) Threshs[addr] <= p.val; - end - end - end : genThreshMem - - if((CF == 1) && (stage == 0)) begin - assign Thresh = Threshs[0]; - end - else begin - uwire [$clog2(CF)+stage-1:0] addr = p.ptr[$clog2(CF)+N-1:SN+1]; - always_ff @(posedge clk) begin - Thresh <= Threshs[addr]; - end - end - - end : blkThresh - - // Pipeline State - pipe_t P = '{ op: NOP, default: 'x }; - logic Reval = 0; - always_ff @(posedge clk) begin - if(rst) begin - P <= '{ op: NOP, default: 'x }; - Reval <= 0; - end - else begin - P <= p; - Reval <= (p.op ==? RB) && cs; - end - end - - logic cmp; - if(!SIGNED) assign cmp = $unsigned(Thresh) <= $unsigned(P.val); - else if(!FPARG) assign cmp = $signed(Thresh) <= $signed(P.val); - else begin : blkSignedFloat - uwire mag_eq = Thresh[K-2:0] == P.val[K-2:0]; - uwire mag_le = Thresh[K-2:0] <= P.val[K-2:0]; - always_comb begin - unique case({Thresh[K-1], P.val[K-1]}) - 2'b00: cmp = mag_le; - 2'b01: cmp = 0; - 2'b10: cmp = 1; - 2'b11: cmp = !mag_le || mag_eq; - default: cmp = 'x; - endcase - end - end : blkSignedFloat - - // Pipeline State Update - pipe_t pp; - always_comb begin - pp = P; - if(P.op !=? CFG) pp.ptr[SN] = cmp; - if(Reval) pp.val = Thresh; - end - - // Pipeline State Forward (potentially additional register) - pipe_t pf; - if(!DEEP_PIPELINE) assign pf = pp; - else begin - pipe_t Pf = '{ op: NOP, default: 'x }; - always_ff @(posedge clk) begin - if(rst) Pf <= '{ op: NOP, default: 'x }; - else Pf <= pp; - end - assign pf = Pf; - end - - assign pipe[pe][stage+1] = pf; - - end : genPE - end : genStages - - //----------------------------------------------------------------------- - // Configuration Readback - always_comb begin - cfg_rack = 0; - cfg_q = 0; - foreach(pipe[pe]) begin - automatic pipe_t p = pipe[pe][N]; - cfg_rack |= p.op ==? RB; - cfg_q |= p.val; - end - end - - //----------------------------------------------------------------------- - // Stream Output through FIFO - // - Depth of N + Output Reg to allow pipe to drain entirely under backpressure - // - Typically mapped to an SRL shift register - if(1) begin : blkStreamOutput - localparam int unsigned A_DEPTH = MAX_PENDING - 1; - logic [PE-1 : 0][N-1 : 0] ADat[A_DEPTH]; - logic signed [$clog2(A_DEPTH):0] APtr = '1; // -1, 0, 1, ..., A_DEPTH-1 - uwire avld = !APtr[$left(APtr)]; - - logic [PE-1:0][N-1:0] BDat = 'x; - logic BVld = 0; - - uwire aload = pipe[0][N].op ==? TH; - uwire bload = !BVld || ordy; - - always_ff @(posedge clk) begin - if(aload) begin - assert(APtr < $signed(A_DEPTH-1)) else begin - $error("Overrun after failing stream guard."); - $stop; - end - foreach(pipe[pe]) ADat[0][pe] <= pipe[pe][N].ptr; - for(int unsigned i = 1; i < A_DEPTH; i++) ADat[i] <= ADat[i-1]; - end - end - always_ff @(posedge clk) begin - if(rst) APtr <= '1; - else APtr <= APtr + (aload == (avld && bload)? 0 : aload? 1 : -1); - end - always_ff @(posedge clk) begin - if(rst) begin - BDat <= 'x; - BVld <= 0; - end - else if(bload) begin - BDat <= ADat[APtr]; - BVld <= avld; - end - end - - assign ovld = BVld; - for(genvar pe = 0; pe < PE; pe++) begin - assign odat[pe] = BDat[pe] + BIAS; - end - end : blkStreamOutput - -endmodule : thresholding diff --git a/finn-rtllib/thresholding/hdl/thresholding_axi.sv b/finn-rtllib/thresholding/hdl/thresholding_axi.sv deleted file mode 100644 index 1f235b9486..0000000000 --- a/finn-rtllib/thresholding/hdl/thresholding_axi.sv +++ /dev/null @@ -1,164 +0,0 @@ -/****************************************************************************** - * Copyright (C) 2022, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF - * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * @brief All-AXI interface adapter for thresholding module. - * @author Thomas B. Preußer - * - * @description - * This AXI adapter fits the core thresholding functionality: - * - with AXI stream data interfaces with flow control - * - with implicit round-robin channel rotation as used by FINN, and - * - performs aligned byte address to parameter word address translation. - *****************************************************************************/ - -module thresholding_axi #( - int unsigned N, // output precision - int unsigned K, // input/threshold precision - int unsigned C = 1, // Channels - int unsigned PE = 1, // Processing Parallelism, requires C = k*PE - - bit SIGNED = 1, // signed inputs - bit FPARG = 0, // floating-point inputs: [sign] | exponent | mantissa - int BIAS = 0, // offsetting the output [0, 2^N-1] -> [BIAS, 2^N-1 + BIAS] - - // Initial Thresholds - parameter THRESHOLDS_PATH = "", - - bit USE_AXILITE, // Implement AXI-Lite for threshold read/write - - // Force Use of On-Chip Memory Blocks - int unsigned DEPTH_TRIGGER_URAM = 0, // if non-zero, local mems of this depth or more go into URAM (prio) - int unsigned DEPTH_TRIGGER_BRAM = 0, // if non-zero, local mems of this depth or more go into BRAM - bit DEEP_PIPELINE = 0, - - localparam int unsigned CF = C/PE, // Channel Fold - localparam int unsigned ADDR_BITS = $clog2(CF) + $clog2(PE) + N + 2, - localparam int unsigned O_BITS = BIAS >= 0? - /* unsigned */ $clog2(2**N+BIAS) : - /* signed */ 1+$clog2(-BIAS >= 2**(N-1)? -BIAS : 2**N+BIAS) -)( - //- Global Control ------------------ - input logic ap_clk, - input logic ap_rst_n, - - //- AXI Lite ------------------------ - // Writing - input logic s_axilite_AWVALID, - output logic s_axilite_AWREADY, - input logic [ADDR_BITS-1:0] s_axilite_AWADDR, // lowest 2 bits (byte selectors) are ignored - - input logic s_axilite_WVALID, - output logic s_axilite_WREADY, - input logic [31:0] s_axilite_WDATA, - input logic [ 3:0] s_axilite_WSTRB, - - output logic s_axilite_BVALID, - input logic s_axilite_BREADY, - output logic [1:0] s_axilite_BRESP, - - // Reading - input logic s_axilite_ARVALID, - output logic s_axilite_ARREADY, - input logic [ADDR_BITS-1:0] s_axilite_ARADDR, - - output logic s_axilite_RVALID, - input logic s_axilite_RREADY, - output logic [31:0] s_axilite_RDATA, - output logic [ 1:0] s_axilite_RRESP, - - //- AXI Stream - Input -------------- - output logic s_axis_tready, - input logic s_axis_tvalid, - input logic [((PE*K+7)/8)*8-1:0] s_axis_tdata, - - //- AXI Stream - Output ------------- - input logic m_axis_tready, - output logic m_axis_tvalid, - output logic [((PE*O_BITS+7)/8)*8-1:0] m_axis_tdata -); - - //----------------------------------------------------------------------- - // AXI-lite Configuration Interface - uwire cfg_en; - uwire cfg_we; - uwire [ADDR_BITS-3:0] cfg_a; - uwire [K -1:0] cfg_d; - uwire cfg_rack; - uwire [K -1:0] cfg_q; - - if(USE_AXILITE) begin - uwire [ADDR_BITS-1:0] cfg_a0; - axi4lite_if #(.ADDR_WIDTH(ADDR_BITS), .DATA_WIDTH(32), .IP_DATA_WIDTH(K)) axi ( - .aclk(ap_clk), .aresetn(ap_rst_n), - - .awready(s_axilite_AWREADY), .awvalid(s_axilite_AWVALID), .awaddr(s_axilite_AWADDR), .awprot('x), - .wready(s_axilite_WREADY), .wvalid(s_axilite_WVALID), .wdata(s_axilite_WDATA), .wstrb(s_axilite_WSTRB), - .bready(s_axilite_BREADY), .bvalid(s_axilite_BVALID), .bresp(s_axilite_BRESP), - - .arready(s_axilite_ARREADY), .arvalid(s_axilite_ARVALID), .araddr(s_axilite_ARADDR), .arprot('x), - .rready(s_axilite_RREADY), .rvalid(s_axilite_RVALID), .rresp(s_axilite_RRESP), .rdata(s_axilite_RDATA), - - .ip_en(cfg_en), .ip_wen(cfg_we), .ip_addr(cfg_a0), .ip_wdata(cfg_d), - .ip_rack(cfg_rack), .ip_rdata(cfg_q) - ); - assign cfg_a = cfg_a0[ADDR_BITS-3:0]; - always_ff @(posedge ap_clk) begin - assert(!ap_rst_n || !cfg_en || (cfg_a0[ADDR_BITS-2+:2] === 3'h0)) else begin - $error("%m: Spurious high address bits."); - $stop; - end - end - end - else begin - assign cfg_en = 0; - assign cfg_we = 'x; - assign cfg_a = 'x; - assign cfg_d = 'x; - end - - //----------------------------------------------------------------------- - // Kernel Implementation - thresholding #( - .N(N), .K(K), .C(C), .PE(PE), - .SIGNED(SIGNED), .FPARG(FPARG), .BIAS(BIAS), - .THRESHOLDS_PATH(THRESHOLDS_PATH), .USE_CONFIG(USE_AXILITE), - .DEPTH_TRIGGER_URAM(DEPTH_TRIGGER_URAM), .DEPTH_TRIGGER_BRAM(DEPTH_TRIGGER_BRAM), - .DEEP_PIPELINE(DEEP_PIPELINE) - ) impl ( - .clk(ap_clk), .rst(!ap_rst_n), - - .cfg_en, .cfg_we, .cfg_a, .cfg_d, - .cfg_rack, .cfg_q, - - .irdy(s_axis_tready), .ivld(s_axis_tvalid), .idat(s_axis_tdata), - .ordy(m_axis_tready), .ovld(m_axis_tvalid), .odat(m_axis_tdata) - ); - -endmodule : thresholding_axi diff --git a/finn-rtllib/thresholding/hdl/thresholding_template_wrapper.v b/finn-rtllib/thresholding/hdl/thresholding_template_wrapper.v deleted file mode 100644 index ef76a23cbc..0000000000 --- a/finn-rtllib/thresholding/hdl/thresholding_template_wrapper.v +++ /dev/null @@ -1,120 +0,0 @@ -/** - * Copyright (c) 2023, Xilinx - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * * Neither the name of FINN nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * @author Thomas B. Preußer - * @brief Verilog wrapper for IP packaging. - */ - -module $MODULE_NAME_AXI_WRAPPER$ #( - parameter N = $N$, // output precision - parameter K = $M$, // input/threshold precision - parameter C = $C$, // Channels - parameter PE = $PE$, // Processing Parallelism, requires C = k*PE - - parameter SIGNED = $SIGNED$, // signed inputs - parameter FPARG = 0, // floating-point inputs: [sign] | exponent | mantissa - parameter BIAS = $BIAS$, // offsetting the output [0, 2^N-1] -> [BIAS, 2^N-1 + BIAS] - - parameter THRESHOLDS_PATH = $THRESHOLDS_PATH$, // Directory with initial threshold data - parameter USE_AXILITE = $USE_AXILITE$, // Implement AXI-Lite for threshold read/write - - // Force Use of On-Chip Memory Blocks - parameter DEPTH_TRIGGER_URAM = $DEPTH_TRIGGER_URAM$, // if non-zero, local mems of this depth or more go into URAM (prio) - parameter DEPTH_TRIGGER_BRAM = $DEPTH_TRIGGER_BRAM$, // if non-zero, local mems of this depth or more go into BRAM - parameter DEEP_PIPELINE = $DEEP_PIPELINE$, // [bit] extra pipeline stages for easier timing closure - - parameter O_BITS = $O_BITS$ -)( - // Global Control - (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF s_axilite:in0_V:out_V, ASSOCIATED_RESET ap_rst_n" *) - (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *) - input ap_clk, - (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) - input ap_rst_n, - - //- AXI Lite ------------------------ - // Writing - input s_axilite_AWVALID, - output s_axilite_AWREADY, - input [$clog2(C/PE) + $clog2(PE) + N + 1:0] s_axilite_AWADDR, // lowest 2 bits (byte selectors) are ignored - - input s_axilite_WVALID, - output s_axilite_WREADY, - input [31:0] s_axilite_WDATA, - input [ 3:0] s_axilite_WSTRB, - - output s_axilite_BVALID, - input s_axilite_BREADY, - output [1:0] s_axilite_BRESP, - - // Reading - input s_axilite_ARVALID, - output s_axilite_ARREADY, - input [$clog2(C/PE) + $clog2(PE) + N + 1:0] s_axilite_ARADDR, - - output s_axilite_RVALID, - input s_axilite_RREADY, - output [31:0] s_axilite_RDATA, - output [ 1:0] s_axilite_RRESP, - - //- AXI Stream - Input -------------- - output in0_V_TREADY, - input in0_V_TVALID, - input [((PE*K+7)/8)*8-1:0] in0_V_TDATA, - - //- AXI Stream - Output ------------- - input out_V_TREADY, - output out_V_TVALID, - output [((PE*O_BITS+7)/8)*8-1:0] out_V_TDATA -); - - thresholding_axi #( - .N(N), .K(K), .C(C), .PE(PE), - .SIGNED(SIGNED), - .FPARG(FPARG), - .BIAS(BIAS), - .THRESHOLDS_PATH(THRESHOLDS_PATH), - .USE_AXILITE(USE_AXILITE), - .DEPTH_TRIGGER_URAM(DEPTH_TRIGGER_URAM), - .DEPTH_TRIGGER_BRAM(DEPTH_TRIGGER_BRAM), - .DEEP_PIPELINE(DEEP_PIPELINE) - ) core ( - .ap_clk(ap_clk), .ap_rst_n(ap_rst_n), - - .s_axilite_AWVALID(s_axilite_AWVALID), .s_axilite_AWREADY(s_axilite_AWREADY), .s_axilite_AWADDR(s_axilite_AWADDR), - .s_axilite_WVALID(s_axilite_WVALID), .s_axilite_WREADY(s_axilite_WREADY), .s_axilite_WDATA(s_axilite_WDATA), .s_axilite_WSTRB(s_axilite_WSTRB), - .s_axilite_BVALID(s_axilite_BVALID), .s_axilite_BREADY(s_axilite_BREADY), .s_axilite_BRESP(s_axilite_BRESP), - - .s_axilite_ARVALID(s_axilite_ARVALID), .s_axilite_ARREADY(s_axilite_ARREADY), .s_axilite_ARADDR(s_axilite_ARADDR), - .s_axilite_RVALID(s_axilite_RVALID), .s_axilite_RREADY(s_axilite_RREADY), .s_axilite_RDATA(s_axilite_RDATA), .s_axilite_RRESP(s_axilite_RRESP), - .s_axis_tready(in0_V_TREADY), .s_axis_tvalid(in0_V_TVALID), .s_axis_tdata(in0_V_TDATA), - .m_axis_tready(out_V_TREADY), .m_axis_tvalid(out_V_TVALID), .m_axis_tdata(out_V_TDATA) - ); - -endmodule // $MODULE_NAME_AXI_WRAPPER$ diff --git a/finn-rtllib/thresholding/sim/thresh_gen.sv b/finn-rtllib/thresholding/sim/thresh_gen.sv deleted file mode 100644 index 713723aafa..0000000000 --- a/finn-rtllib/thresholding/sim/thresh_gen.sv +++ /dev/null @@ -1,45 +0,0 @@ -module thresh_gen; - localparam int unsigned K = 9; - localparam int unsigned N = 4; - localparam int unsigned C = 6; - - typedef logic [K-1:0] thresh_t; - localparam thresh_t THRESHOLDS[C][2**N-1] = '{ - '{ 'h00, 'h01, 'h02, 'h03, 'h04, 'h05, 'h06, 'h07, 'h08, 'h09, 'h0a, 'h0b, 'h0c, 'h0d, 'h0e }, - '{ 'h10, 'h11, 'h12, 'h13, 'h14, 'h15, 'h16, 'h17, 'h18, 'h19, 'h1a, 'h1b, 'h1c, 'h1d, 'h1e }, - '{ 'h20, 'h21, 'h22, 'h23, 'h24, 'h25, 'h26, 'h27, 'h28, 'h29, 'h2a, 'h2b, 'h2c, 'h2d, 'h2e }, - '{ 'h30, 'h31, 'h32, 'h33, 'h34, 'h35, 'h36, 'h37, 'h38, 'h39, 'h3a, 'h3b, 'h3c, 'h3d, 'h3e }, - '{ 'h40, 'h41, 'h42, 'h43, 'h44, 'h45, 'h46, 'h47, 'h48, 'h49, 'h4a, 'h4b, 'h4c, 'h4d, 'h4e }, - '{ 'h50, 'h51, 'h52, 'h53, 'h54, 'h55, 'h56, 'h57, 'h58, 'h59, 'h5a, 'h5b, 'h5c, 'h5d, 'h5e } - }; - localparam THRESHOLDS_PATH = "./"; - - localparam int unsigned PE = 2; - localparam int unsigned CF = C/PE; - - for(genvar stage = 0; stage < N; stage++) begin - localparam int unsigned SN = N-1-stage; - for(genvar pe = 0; pe < PE; pe++) begin - initial begin - automatic string file = $sformatf("%sthreshs_%0d_%0d.dat", THRESHOLDS_PATH, pe, stage); - - automatic thresh_t threshs[CF * 2**stage]; - for(int unsigned c = 0; c < CF; c++) begin - for(int unsigned i = 0; i < 2**stage; i++) begin - threshs[(c << stage) + i] = THRESHOLDS[c*PE + pe][(i<<(N-stage)) + 2**SN-1]; - end - end - - $writememh(file, threshs); - end - end - end - - // Quit after running all initializers - initial begin - #1ns; - $display("Generation done."); - $finish; - end - -endmodule : thresh_gen diff --git a/finn-rtllib/thresholding/sim/thresholding.tcl b/finn-rtllib/thresholding/sim/thresholding.tcl deleted file mode 100644 index 82dc59deb1..0000000000 --- a/finn-rtllib/thresholding/sim/thresholding.tcl +++ /dev/null @@ -1,17 +0,0 @@ -create_project -force thresholding thresholding.vivado -part xcvc1902-vsva2197-2MP-e-S -set_property board_part xilinx.com:vck190:part0:2.2 [current_project] - -read_verilog hdl/axilite_if.v -read_verilog -sv { hdl/thresholding.sv hdl/thresholding_axi.sv } - -set simset [current_fileset -simset] -set_property -name xsim.simulate.log_all_signals -value true -objects $simset -set_property -name xsim.simulate.runtime -value all -objects $simset -add_files -fileset $simset { sim/thresholding_tb.sv sim/thresholding_axi_tb.sv } - -foreach top { thresholding_tb thresholding_axi_tb } { - set_property top $top $simset - - launch_simulation - close_sim -} diff --git a/finn-rtllib/thresholding/sim/thresholding_axi_tb.sv b/finn-rtllib/thresholding/sim/thresholding_axi_tb.sv deleted file mode 100644 index 918f539d15..0000000000 --- a/finn-rtllib/thresholding/sim/thresholding_axi_tb.sv +++ /dev/null @@ -1,314 +0,0 @@ -/****************************************************************************** - * Copyright (C) 2022, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF - * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * @brief Testbench for thresholding_axi. - * @author Monica Chiosa - * - */ - -module thresholding_axi_tb #( - int unsigned N = 4, // output precision - int unsigned C = 6, // number of channels - int unsigned PE = 2, - real M0 = 7.3, // slope of the uniform thresholding line - real B0 = 3.1, // offset of the uniform thresholding line - bit THROTTLED = 1, - - localparam int unsigned CF = C/PE, // Channel Fold - localparam int unsigned ADDR_BITS = $clog2(CF) + $clog2(PE) + N + 2 -); - - //----------------------------------------------------------------------- - // Design Geometry - - // For each channel = [0,channel): - // M_channel = M0 + CX*channel - // B_channel = B0 + CX*channel - // Input/threshold precision computed according with the maximum posible value - localparam real CX = 1.375; - localparam int unsigned K = $clog2((2**N-1)*(M0+C*CX) + (B0+C*CX)); // unused sign + magnitude - localparam int unsigned C_BITS = C < 2? 1 : $clog2(C); - - localparam int unsigned MST_STRM_WROUNDS = 503; - - typedef int unsigned threshs_t[C][2**N-1]; - function threshs_t init_thresholds(); - automatic threshs_t res; - for(int unsigned c = 0; c < C; c++) begin - automatic real m = M0 + c*CX; - automatic real b = B0 + c*CX; - foreach(res[c][i]) begin - res[c][i] = int'($ceil(m*i + b)); - end - end - return res; - endfunction : init_thresholds - localparam threshs_t THRESHS = init_thresholds(); - - //----------------------------------------------------------------------- - // Clock and Reset Control - logic clk = 0; - always #5ns clk = !clk; - logic rst = 1; - initial begin - #10ns; - @(posedge clk); - rst <= 0; - end - - //----------------------------------------------------------------------- - // DUT - logic s_axilite_AWVALID; - uwire s_axilite_AWREADY; - logic [ADDR_BITS-1:0] s_axilite_AWADDR; // lowest 2 bits (byte selectors) are ignored - logic s_axilite_WVALID; - uwire s_axilite_WREADY; - logic [ 31:0] s_axilite_WDATA; - uwire s_axilite_BVALID; - logic s_axilite_BREADY; - uwire [ 1:0] s_axilite_BRESP; - logic s_axilite_ARVALID; - uwire s_axilite_ARREADY; - logic [ADDR_BITS-1:0] s_axilite_ARADDR; - uwire s_axilite_RVALID; - uwire s_axilite_RREADY = 1; - uwire [ 31:0] s_axilite_RDATA; - uwire [ 1:0] s_axilite_RRESP; - - uwire irdy; - logic ivld; - logic [PE-1:0][K-1:0] idat; - - logic ordy = 0; - uwire ovld; - uwire [PE-1:0][N-1:0] odat; - - thresholding_axi #(.N(N), .K(K), .C(C), .PE(PE), .SIGNED(0), .USE_AXILITE(1)) dut ( - .ap_clk(clk), .ap_rst_n(!rst), - - // Configuration - .s_axilite_AWVALID, .s_axilite_AWREADY, .s_axilite_AWADDR, - .s_axilite_WVALID, .s_axilite_WREADY, .s_axilite_WDATA, .s_axilite_WSTRB('1), - .s_axilite_BVALID, .s_axilite_BREADY, .s_axilite_BRESP, - .s_axilite_ARVALID, .s_axilite_ARREADY, .s_axilite_ARADDR, - .s_axilite_RVALID, .s_axilite_RREADY, .s_axilite_RDATA, .s_axilite_RRESP, - - // Stream Processing - .s_axis_tready(irdy), .s_axis_tvalid(ivld), .s_axis_tdata(idat), - .m_axis_tready(ordy), .m_axis_tvalid(ovld), .m_axis_tdata(odat) - ); - - //----------------------------------------------------------------------- - // Input Stimuli - typedef logic [PE-1:0][K-1:0] input_t; - typedef logic [$clog2(CF)+$clog2(PE)+N-1:0] addr_t; - input_t QW[$]; // Input Feed Tracing - addr_t QC[$]; - - int unsigned error_cnt = 0; - bit done = 0; - initial begin - // Report testbench details - $display("Testbench - tresholding K=%0d -> N=%0d", K, N); - for(int unsigned c = 0; c < C; c++) begin - $write("Channel #%0d: Thresholds = {", c); - for(int unsigned i = 0; i < 2**N-1; i++) $write(" %0d", THRESHS[c][i]); - $display(" }"); - end - - // Config - s_axilite_AWVALID = 0; - s_axilite_AWADDR = 'x; - s_axilite_WVALID = 0; - s_axilite_WDATA = 'x; - s_axilite_BREADY = 0; - s_axilite_ARVALID = 0; - s_axilite_ARADDR = 'x; - - // Stream Input - ivld = 0; - idat = 'x; - - @(posedge clk iff !rst); - - // Threshold Configuration - for(int unsigned c = 0; c < C; c+=PE) begin - automatic addr_t addr = 0; - if(CF > 1) addr[N+$clog2(PE)+:$clog2(CF)] = c/PE; - for(int unsigned pe = 0; pe < PE; pe++) begin - if(PE > 1) addr[N+:$clog2(PE)] = pe; - for(int unsigned t = 0; t < 2**N-1; t++) begin - addr[0+:N] = t; - fork - begin - s_axilite_AWVALID <= 1; - s_axilite_AWADDR <= { addr, 2'b00 }; - @(posedge clk iff s_axilite_AWREADY); - s_axilite_AWVALID <= 0; - s_axilite_AWADDR <= 'x; - end - begin - s_axilite_WVALID <= 1; - s_axilite_WDATA <= THRESHS[c+pe][t]; - @(posedge clk iff s_axilite_WREADY); - s_axilite_WVALID <= 0; - s_axilite_WDATA <= 'x; - end - begin - s_axilite_BREADY <= 1; - @(posedge clk iff s_axilite_BVALID); - assert(s_axilite_BRESP == '0) else begin - $error("Error on parameter write."); - $stop; - end - s_axilite_BREADY <= 0; - end - join - end - end - end - - fork - // Intermittent configuration readback - while(!done) begin - if(($urandom()%37) != 0) begin - s_axilite_ARVALID <= 0; - s_axilite_ARADDR <= 'x; - @(posedge clk); - end - else begin - automatic addr_t addr = $urandom()%(N-1); - if(PE > 1) addr[N+:$clog2(PE)] = $urandom()%PE; - if(CF > 1) addr[N+$clog2(PE)+:$clog2(CF)] = $urandom()%CF; - - s_axilite_ARVALID <= 1; - s_axilite_ARADDR <= { addr, 2'b00 }; - @(posedge clk iff s_axilite_ARREADY); - - QC.push_back(addr); - end - end - - // AXI4Stream MST Writes input values - repeat(MST_STRM_WROUNDS) begin - automatic input_t dat; - - while(THROTTLED && ($urandom()%7 == 0)) @(posedge clk); - - std::randomize(dat); - ivld <= 1; - idat <= dat; - @(posedge clk iff irdy); - ivld <= 0; - idat <= 'x; - QW.push_back(dat); - end - join_any - done <= 1; - repeat(N+6) @(posedge clk); - - assert(QW.size() == 0) else begin - $error("Missing %0d outputs.", QW.size()); - $stop; - end - assert(QC.size() == 0) else begin - $error("Missing %0d readback replies.", QC.size()); - $stop; - end - - $display("Test completed: %0d errors in %0d tests.", error_cnt, MST_STRM_WROUNDS); - $display("========================================="); - $finish; - end - - // Output Checker ------------------------------------------------------- - - // Configuration Readback - always_ff @(posedge clk iff s_axilite_RVALID) begin - assert(s_axilite_RRESP == '0) else begin - $error("Read back error."); - $stop; - end - assert(QC.size()) begin - automatic addr_t addr = QC.pop_front(); - automatic int unsigned cnl = - (CF == 1? 0 : addr[N+$clog2(PE)+:$clog2(CF)] * PE) + - (PE == 1? 0 : addr[N+:$clog2(PE)]); - automatic logic [K-1:0] exp = THRESHS[cnl][addr[0+:N]]; - assert(s_axilite_RDATA == exp) else begin - $error("Readback mismatch on #%0d.%0d: %0d instead of %0d", cnl, addr[0+:N], s_axilite_RDATA, exp); - $stop; - end - end - else begin - $error("Spurious readback output."); - $stop; - end - end - - // Stream Output - int unsigned OCnl = 0; - always @(posedge clk) begin - if(rst) begin - OCnl <= 0; - ordy <= 1'b0; - end - else begin - if(!ordy || ovld) ordy <= ($urandom()%5 != 0) || !THROTTLED; - - if(ordy && ovld) begin - assert(QW.size()) begin - automatic input_t x = QW.pop_front(); - - for(int unsigned pe = 0; pe < PE; pe++) begin - automatic int unsigned cnl = OCnl + pe; - - $display("Mapped CNL=%0d DAT=%3d -> #%2d", cnl, x[pe], odat[pe]); - assert( - ((odat[pe] == 0) || (THRESHS[cnl][odat[pe]-1] <= x[pe])) && - ((odat[pe] == 2**N-1) || (x[pe] < THRESHS[cnl][odat[pe]])) - ) else begin - $error("Output error on presumed input CNL=%0d DAT=0x%0x -> #%0d", cnl, x[pe], odat[pe]); - error_cnt++; - $stop; - end - end - end - else begin - $error("Spurious output."); - $stop; - end - - OCnl <= (OCnl + PE)%C; - end - end - end - -endmodule: thresholding_axi_tb diff --git a/finn-rtllib/thresholding/sim/thresholding_tb.sv b/finn-rtllib/thresholding/sim/thresholding_tb.sv deleted file mode 100644 index e42145f10e..0000000000 --- a/finn-rtllib/thresholding/sim/thresholding_tb.sv +++ /dev/null @@ -1,274 +0,0 @@ -/****************************************************************************** - * Copyright (C) 2022, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF - * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * @brief Testbench for thresholding_axi. - * @author Monica Chiosa - * - */ - -module thresholding_tb #( - int unsigned K = 10, // input precision - int unsigned N = 4, // output precision - int unsigned C = 6, // number of channels - int unsigned PE = 2, - - localparam int unsigned CF = C/PE // Channel Fold -); - localparam bit DEEP_PIPELINE = 1; - - localparam int unsigned MST_STRM_WROUNDS = 507; - localparam bit THROTTLED = 1; - - //----------------------------------------------------------------------- - // Clock and Reset Control - logic clk = 0; - always #5ns clk = !clk; - logic rst = 1; - initial begin - #10ns; - @(posedge clk); - rst <= 0; - end - - //----------------------------------------------------------------------- - // Parallel Instances differing in Data Type - typedef logic [K -1:0] val_t; - typedef val_t threshs_t[C][2**N-1]; - typedef val_t [PE-1:0] input_t; - typedef logic [$clog2(CF)+$clog2(PE)+N-1:0] addr_t; - logic [0:2] term = '0; - always_comb begin - if(&term) $finish; - end - for(genvar i = 0; i < 3; i++) begin : genTypes - localparam bit SIGNED = i>0; - localparam bit FPARG = i>1; - - //- DUT ------------------------- - logic cfg_en; - logic cfg_we; - logic [$clog2(C)+N-1:0] cfg_a; - logic [K-1:0] cfg_d; - uwire cfg_rack; - uwire [K-1:0] cfg_q; - - uwire irdy; - logic ivld; - logic [PE-1:0][K-1:0] idat; - - logic ordy = 0; - uwire ovld; - uwire [PE-1:0][N-1:0] odat; - - thresholding #(.N(N), .K(K), .C(C), .PE(PE), .SIGNED(SIGNED), .FPARG(FPARG), .USE_CONFIG(1), .DEEP_PIPELINE(DEEP_PIPELINE)) dut ( - .clk, .rst, - - // Configuration - .cfg_en, .cfg_we, .cfg_a, .cfg_d, - .cfg_rack, .cfg_q, - - // Stream Processing - .irdy, .ivld, .idat, - .ordy, .ovld, .odat - ); - - //- Stimulus Driver ------------- - threshs_t THRESHS; - function val_t sigord(input val_t x); - automatic val_t res = x; - if(SIGNED) begin - if(FPARG && x[K-1]) res[K-2:0] = ~x[K-2:0]; - res[K-1] = !x[K-1]; - end - return res; - endfunction : sigord - - input_t QW[$]; // Input tracing - addr_t QC[$]; // Readback tracking - int unsigned error_cnt = 0; - bit done = 0; - initial begin - - // Generate thresholds - std::randomize(THRESHS); - foreach(THRESHS[c]) begin - val_t row[2**N-1] = THRESHS[c]; - row.sort with (sigord(item)); - THRESHS[c] = row; - end - - // Report test case details - $display("[%0d] Thresholding %s%s%0d -> uint%0d", i, SIGNED? "s" : "u", FPARG? "fp" : "int", K, N); - for(int unsigned c = 0; c < C; c++) begin - $write("[%0d] Channel #%0d: Thresholds = {", i, c); - for(int unsigned i = 0; i < 2**N-1; i++) $write(" %0X", THRESHS[c][i]); - $display(" }"); - end - - // Config - cfg_en = 0; - cfg_we = 'x; - cfg_a = 'x; - cfg_d = 'x; - - // Stream Input - ivld = 0; - idat = 'x; - - @(posedge clk iff !rst); - - // Threshold Configuratin - cfg_en <= 1; - cfg_we <= 1; - for(int unsigned c = 0; c < C; c+=PE) begin - if(CF > 1) cfg_a[N+$clog2(PE)+:$clog2(CF)] <= c/PE; - for(int unsigned pe = 0; pe < PE; pe++) begin - if(PE > 1) cfg_a[N+:$clog2(PE)] = pe; - for(int unsigned t = 0; t < 2**N-1; t++) begin - cfg_a[0+:N] <= t; - cfg_d <= THRESHS[c+pe][t]; - @(posedge clk); - end - end - end - cfg_d <= 'x; - - fork - // Intermittent configuration readback - while(!done) begin - cfg_en <= 0; - cfg_we <= 'x; - cfg_a <= 'x; - @(posedge clk); - if(($urandom()%41) == 0) begin - automatic addr_t addr = $urandom()%(N-1); - if(PE > 1) addr[N+:$clog2(PE)] = $urandom()%PE; - if(CF > 1) addr[N+$clog2(PE)+:$clog2(CF)] = $urandom()%CF; - - cfg_en <= 1; - cfg_we <= 0; - cfg_a <= addr; - @(posedge clk); - QC.push_back(addr); - end - end - - // AXI4Stream MST Writes input values - repeat(MST_STRM_WROUNDS) begin - automatic input_t dat; - - while(THROTTLED && ($urandom()%7 == 0)) @(posedge clk); - - std::randomize(dat); - ivld <= 1; - idat <= dat; - @(posedge clk iff irdy); - ivld <= 0; - idat <= 'x; - QW.push_back(dat); - end - join_any - done <= 1; - repeat((DEEP_PIPELINE+1)*N+6) @(posedge clk); - - assert(QW.size() == 0) else begin - $error("[%0d] Missing %0d outputs.", i, QW.size()); - $stop; - end - assert(QC.size() == 0) else begin - $error("[%0d] Missing %0d readback replies.", i, QC.size()); - $stop; - end - - $display("[%0d] Test completed: %0d errors in %0d tests.", i, error_cnt, MST_STRM_WROUNDS); - $display("============================================="); - term[i] <= 1; - end - - //- Readback Checker -------------- - always_ff @(posedge clk iff cfg_rack) begin - assert(QC.size()) begin - automatic addr_t addr = QC.pop_front(); - automatic int unsigned cnl = - (CF == 1? 0 : addr[N+$clog2(PE)+:$clog2(CF)] * PE) + - (PE == 1? 0 : addr[N+:$clog2(PE)]); - automatic logic [K-1:0] exp = THRESHS[cnl][addr[0+:N]]; - assert(cfg_q == exp) else begin - $error("[%0d] Readback mismatch on #%0d.%0d: %0d instead of %0d", i, cnl, addr[0+:N], cfg_q, exp); - $stop; - end - end - else begin - $error("[%0d] Spurious readback output.", i); - $stop; - end - end - - // Output Checker - int unsigned OCnl = 0; - always @(posedge clk) begin - if(rst) begin - OCnl <= 0; - ordy <= 1'b0; - end - else begin - if(!ordy || ovld) ordy <= ($urandom()%5 != 0) || !THROTTLED; - - if(ordy && ovld) begin - assert(QW.size()) begin - automatic input_t x = QW.pop_front(); - - for(int unsigned pe = 0; pe < PE; pe++) begin - automatic int unsigned cnl = OCnl + pe; - - $display("[%0d] Mapped CNL=%0d DAT=%3x -> #%2d", i, cnl, x[pe], odat[pe]); - assert( - ((odat[pe] == 0) || (sigord(THRESHS[cnl][odat[pe]-1]) <= sigord(x[pe]))) && - ((odat[pe] == 2**N-1) || (sigord(x[pe]) < sigord(THRESHS[cnl][odat[pe]]))) - ) else begin - $error("[%0d] Output error on presumed input CNL=%0d DAT=0x%0x -> #%0d", i, cnl, x[pe], odat[pe]); - error_cnt++; - $stop; - end - end - end - else begin - $error("[%0d] Spurious output.", i); - $stop; - end - - OCnl <= (OCnl + PE)%C; - end - end - end - - end : genTypes - -endmodule: thresholding_tb diff --git a/finn-rtllib/thresholding/xgui/thresholding_axi_v1_0.tcl b/finn-rtllib/thresholding/xgui/thresholding_axi_v1_0.tcl deleted file mode 100644 index 338304fa40..0000000000 --- a/finn-rtllib/thresholding/xgui/thresholding_axi_v1_0.tcl +++ /dev/null @@ -1,187 +0,0 @@ - -# Loading additional proc with user specified bodies to compute parameter values. -source [file join [file dirname [file dirname [info script]]] gui/thresholding_axi_v1_0.gtcl] - -# Definitional proc to organize widgets for parameters. -proc init_gui { IPINST } { - ipgui::add_param $IPINST -name "Component_Name" - #Adding Page - set Page_0 [ipgui::add_page $IPINST -name "Page 0"] - ipgui::add_param $IPINST -name "ADDR_BITS" -parent ${Page_0} - ipgui::add_param $IPINST -name "BIAS" -parent ${Page_0} - ipgui::add_param $IPINST -name "C" -parent ${Page_0} - ipgui::add_param $IPINST -name "CF" -parent ${Page_0} - ipgui::add_param $IPINST -name "FPARG" -parent ${Page_0} - ipgui::add_param $IPINST -name "K" -parent ${Page_0} - ipgui::add_param $IPINST -name "N" -parent ${Page_0} - ipgui::add_param $IPINST -name "O_BITS" -parent ${Page_0} - set PE [ipgui::add_param $IPINST -name "PE" -parent ${Page_0}] - set_property tooltip {PE Count} ${PE} - ipgui::add_param $IPINST -name "SIGNED" -parent ${Page_0} - - -} - -proc update_PARAM_VALUE.ADDR_BITS { PARAM_VALUE.ADDR_BITS PARAM_VALUE.C PARAM_VALUE.PE PARAM_VALUE.N } { - # Procedure called to update ADDR_BITS when any of the dependent parameters in the arguments change - - set ADDR_BITS ${PARAM_VALUE.ADDR_BITS} - set C ${PARAM_VALUE.C} - set PE ${PARAM_VALUE.PE} - set N ${PARAM_VALUE.N} - set values(C) [get_property value $C] - set values(PE) [get_property value $PE] - set values(N) [get_property value $N] - set_property value [gen_USERPARAMETER_ADDR_BITS_VALUE $values(C) $values(PE) $values(N)] $ADDR_BITS -} - -proc validate_PARAM_VALUE.ADDR_BITS { PARAM_VALUE.ADDR_BITS } { - # Procedure called to validate ADDR_BITS - return true -} - -proc update_PARAM_VALUE.CF { PARAM_VALUE.CF PARAM_VALUE.C PARAM_VALUE.PE } { - # Procedure called to update CF when any of the dependent parameters in the arguments change - - set CF ${PARAM_VALUE.CF} - set C ${PARAM_VALUE.C} - set PE ${PARAM_VALUE.PE} - set values(C) [get_property value $C] - set values(PE) [get_property value $PE] - set_property value [gen_USERPARAMETER_CF_VALUE $values(C) $values(PE)] $CF -} - -proc validate_PARAM_VALUE.CF { PARAM_VALUE.CF } { - # Procedure called to validate CF - return true -} - -proc update_PARAM_VALUE.O_BITS { PARAM_VALUE.O_BITS PARAM_VALUE.BIAS PARAM_VALUE.N } { - # Procedure called to update O_BITS when any of the dependent parameters in the arguments change - - set O_BITS ${PARAM_VALUE.O_BITS} - set BIAS ${PARAM_VALUE.BIAS} - set N ${PARAM_VALUE.N} - set values(BIAS) [get_property value $BIAS] - set values(N) [get_property value $N] - set_property value [gen_USERPARAMETER_O_BITS_VALUE $values(BIAS) $values(N)] $O_BITS -} - -proc validate_PARAM_VALUE.O_BITS { PARAM_VALUE.O_BITS } { - # Procedure called to validate O_BITS - return true -} - -proc update_PARAM_VALUE.BIAS { PARAM_VALUE.BIAS } { - # Procedure called to update BIAS when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.BIAS { PARAM_VALUE.BIAS } { - # Procedure called to validate BIAS - return true -} - -proc update_PARAM_VALUE.C { PARAM_VALUE.C } { - # Procedure called to update C when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.C { PARAM_VALUE.C } { - # Procedure called to validate C - return true -} - -proc update_PARAM_VALUE.FPARG { PARAM_VALUE.FPARG } { - # Procedure called to update FPARG when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.FPARG { PARAM_VALUE.FPARG } { - # Procedure called to validate FPARG - return true -} - -proc update_PARAM_VALUE.K { PARAM_VALUE.K } { - # Procedure called to update K when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.K { PARAM_VALUE.K } { - # Procedure called to validate K - return true -} - -proc update_PARAM_VALUE.N { PARAM_VALUE.N } { - # Procedure called to update N when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.N { PARAM_VALUE.N } { - # Procedure called to validate N - return true -} - -proc update_PARAM_VALUE.PE { PARAM_VALUE.PE } { - # Procedure called to update PE when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.PE { PARAM_VALUE.PE } { - # Procedure called to validate PE - return true -} - -proc update_PARAM_VALUE.SIGNED { PARAM_VALUE.SIGNED } { - # Procedure called to update SIGNED when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.SIGNED { PARAM_VALUE.SIGNED } { - # Procedure called to validate SIGNED - return true -} - - -proc update_MODELPARAM_VALUE.N { MODELPARAM_VALUE.N PARAM_VALUE.N } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.N}] ${MODELPARAM_VALUE.N} -} - -proc update_MODELPARAM_VALUE.K { MODELPARAM_VALUE.K PARAM_VALUE.K } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.K}] ${MODELPARAM_VALUE.K} -} - -proc update_MODELPARAM_VALUE.C { MODELPARAM_VALUE.C PARAM_VALUE.C } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.C}] ${MODELPARAM_VALUE.C} -} - -proc update_MODELPARAM_VALUE.PE { MODELPARAM_VALUE.PE PARAM_VALUE.PE } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.PE}] ${MODELPARAM_VALUE.PE} -} - -proc update_MODELPARAM_VALUE.SIGNED { MODELPARAM_VALUE.SIGNED PARAM_VALUE.SIGNED } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.SIGNED}] ${MODELPARAM_VALUE.SIGNED} -} - -proc update_MODELPARAM_VALUE.FPARG { MODELPARAM_VALUE.FPARG PARAM_VALUE.FPARG } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.FPARG}] ${MODELPARAM_VALUE.FPARG} -} - -proc update_MODELPARAM_VALUE.BIAS { MODELPARAM_VALUE.BIAS PARAM_VALUE.BIAS } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.BIAS}] ${MODELPARAM_VALUE.BIAS} -} - -proc update_MODELPARAM_VALUE.CF { MODELPARAM_VALUE.CF PARAM_VALUE.CF } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.CF}] ${MODELPARAM_VALUE.CF} -} - -proc update_MODELPARAM_VALUE.ADDR_BITS { MODELPARAM_VALUE.ADDR_BITS PARAM_VALUE.ADDR_BITS } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.ADDR_BITS}] ${MODELPARAM_VALUE.ADDR_BITS} -} - -proc update_MODELPARAM_VALUE.O_BITS { MODELPARAM_VALUE.O_BITS PARAM_VALUE.O_BITS } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.O_BITS}] ${MODELPARAM_VALUE.O_BITS} -} diff --git a/src/finn/util/basic.py b/src/finn/util/basic.py index 0a6c0b39c9..1796738c58 100644 --- a/src/finn/util/basic.py +++ b/src/finn/util/basic.py @@ -30,7 +30,6 @@ import subprocess import sys import tempfile -from qonnx.util.basic import roundup_to_integer_multiple # test boards test_board_map = ["Pynq-Z1", "KV260_SOM", "ZCU104", "U250"] @@ -77,11 +76,6 @@ alveo_default_platform["U280"] = "xilinx_u280_gen3x16_xdma_1_202211_1" alveo_default_platform["U55C"] = "xilinx_u55c_gen3x16_xdma_3_202210_1" -# Create a joint part map, encompassing other boards too -part_map = {**pynq_part_map, **alveo_part_map} -part_map["VEK280"] = "xcve2802-vsvh1760-2MP-e-S" -part_map["VCK190"] = "xcvc1902-vsva2197-2MP-e-S" - def get_rtlsim_trace_depth(): """Return the trace depth for rtlsim via PyVerilator. Controllable @@ -234,67 +228,3 @@ def is_exe(fpath): return exe_file return None - - -def find_next_power_of_2(n): - """For any integer 'n', find the next greatest power of 2""" - # Negative values will loop infinitely below - return 0 - if n <= 0: - return 0 - # If '1' is requested, output will be '0' in the loop below, avoid this now. - elif n == 1: - return 2 # i.e. 2**1 - - # decrement 'n' (to handle cases when `n` itself is a power of 2) - n = n - 1 - - # loop until only one bit is left - while n & n - 1: - # unset rightmost bit - n = n & n - 1 - return n << 1 - - -mem_primitives_versal = { - "URAM_72x4096": (72, 4096), - "URAM_36x8192": (36, 8192), - "URAM_18x16384": (18, 16384), - "URAM_9x32768": (9, 32768), - "BRAM18_36x512": (36, 512), - "BRAM18_18x1024": (18, 1024), - "BRAM18_9x2048": (9, 2048), - "LUTRAM": (1, 64), -} - - -def get_memutil_alternatives( - req_mem_spec, mem_primitives=mem_primitives_versal, sort_min_waste=True -): - ret = [ - (primitive_name, memutil(req_mem_spec, primitive_spec)) - for (primitive_name, primitive_spec) in mem_primitives.items() - ] - if sort_min_waste: - ret = sorted(ret, key=lambda x: x[1][2]) - return ret - - -def memutil(req_mem_spec, primitive_spec): - """Computes how many instances of a memory primitive are necessary to - implemented a desired memory size, where req_mem_spec is the desired - size and the primitive_spec is the primitve size. The sizes are expressed - as tuples of (mem_width, mem_depth). Returns (primitive_count, efficiency, waste) - where efficiency in range [0,1] indicates how much of the total capacity is - utilized, and waste indicates how many bits of storage are wasted.""" - - req_width, req_depth = req_mem_spec - prim_width, prim_depth = primitive_spec - - match_width = roundup_to_integer_multiple(req_width, prim_width) - match_depth = roundup_to_integer_multiple(req_depth, prim_depth) - count_width = match_width // prim_width - count_depth = match_depth // prim_depth - count = count_depth * count_width - eff = (req_width * req_depth) / (count * prim_width * prim_depth) - waste = (count * prim_width * prim_depth) - (req_width * req_depth) - return (count, eff, waste) diff --git a/tests/util/test_basic.py b/tests/util/test_basic.py deleted file mode 100755 index 97a8c50261..0000000000 --- a/tests/util/test_basic.py +++ /dev/null @@ -1,60 +0,0 @@ -# Copyright (C) 2023, Advanced Micro Devices, Inc. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# * Redistributions of source code must retain the above copyright notice, this -# list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# * Neither the name of FINN nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -import pytest - -import finn.util.basic as basic - - -@pytest.mark.util -def test_next_power_of_2(): - test_vector = [ - {"input": -2, "expected_result": 0}, - {"input": -1, "expected_result": 0}, - {"input": 0, "expected_result": 0}, - {"input": 1, "expected_result": 2}, - {"input": 2, "expected_result": 2}, - {"input": 3, "expected_result": 4}, - {"input": 4, "expected_result": 4}, - {"input": 7, "expected_result": 8}, - {"input": 8, "expected_result": 8}, - {"input": 11, "expected_result": 16}, - {"input": 15, "expected_result": 16}, - {"input": 16, "expected_result": 16}, - {"input": 18, "expected_result": 32}, - {"input": 27, "expected_result": 32}, - {"input": 31, "expected_result": 32}, - {"input": 32, "expected_result": 32}, - {"input": 42, "expected_result": 64}, - {"input": 65, "expected_result": 128}, - ] - - for test_dict in test_vector: - output = basic.find_next_power_of_2(test_dict["input"]) - assert output >= test_dict["input"] - assert output == test_dict["expected_result"] From 01cff8080b95ea777f7ce384e95118cdbf5a901f Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Fri, 26 Jan 2024 16:42:06 +0000 Subject: [PATCH 421/665] [TBS] clean up for HLS variant only --- .../fpgadataflow/convert_to_hls_layers.py | 74 ++++++------------- 1 file changed, 21 insertions(+), 53 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py b/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py index c43f058fac..ef02453498 100644 --- a/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py +++ b/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py @@ -1019,10 +1019,9 @@ def apply(self, model): class InferThresholdingLayer(Transformation): """Convert any MultiThreshold into a standalone thresholding HLS layer.""" - def __init__(self, mem_mode="const", use_rtl_variant=False): + def __init__(self, mem_mode="const"): super().__init__() self.mem_mode = mem_mode - self.use_rtl_variant = use_rtl_variant def apply(self, model): graph = model.graph @@ -1074,58 +1073,27 @@ def apply(self, model): ) actval = int(actval) assert (not odt.signed()) or (actval < 0), ( - node.name + ": Signed output requires actval < 0" + node.name + ": Signed output requres actval < 0" + ) + # create and insert new Thresholding_Batch node + new_node = helper.make_node( + "Thresholding_Batch", + [thl_input, thl_threshold], + [thl_output], + domain="finn.custom_op.fpgadataflow", + backend="fpgadataflow", + NumChannels=ifc, + PE=pe, + numSteps=thl_thres_shape[1], + inputDataType=idt.name, + # weightDataType can be tightened by MinimizeAccumulatorWidth + weightDataType=idt.name, + outputDataType=odt.name, + numInputVectors=list(thl_in_shape[:-1]), + ActVal=actval, + mem_mode=self.mem_mode, + name="Thresholding_Batch_" + node.name, ) - - # Ensure that RTL variant is not inserted for unsupported configuration - is_rtl_variant_compatible = True - - # Perform checks for RTL variant if chosen - if self.use_rtl_variant and is_rtl_variant_compatible: - new_node = helper.make_node( - "Thresholding_Binary_Search", - [thl_input, thl_threshold], - [thl_output], - domain="finn.custom_op.fpgadataflow", - backend="fpgadataflow", - NumChannels=ifc, - PE=pe, - numSteps=thl_thres_shape[1], - inputDataType=idt.name, - weightDataType=idt.name, - outputDataType=odt.name, - numInputVectors=list(thl_in_shape[:-1]), - activation_bias=actval, - mem_mode=self.mem_mode, - name="Thresholding_Binary_Search_" + node.name, - ) - else: - if self.use_rtl_variant: - warnings.warn( - """%s : RTL Thresholding requested for unsupported - configuration. Falling back to HLS implementation.""" - % node.name - ) - - # create and insert new Thresholding_Batch node - new_node = helper.make_node( - "Thresholding_Batch", - [thl_input, thl_threshold], - [thl_output], - domain="finn.custom_op.fpgadataflow", - backend="fpgadataflow", - NumChannels=ifc, - PE=pe, - numSteps=thl_thres_shape[1], - inputDataType=idt.name, - weightDataType=idt.name, - outputDataType=odt.name, - numInputVectors=list(thl_in_shape[:-1]), - ActVal=actval, - mem_mode=self.mem_mode, - name="Thresholding_Batch_" + node.name, - ) - graph.node.insert(insert_point, new_node) # remove old node graph.node.remove(node) From b7425284067ff9e3c99553ca05b65b0a22fc5166 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Fri, 26 Jan 2024 16:47:00 +0000 Subject: [PATCH 422/665] [TBS] Remove import of thresholding_batch Signed-off-by: aziz bahri --- src/finn/custom_op/fpgadataflow/__init__.py | 2 -- tests/fpgadataflow/test_convert_to_hw_thresholding.py | 4 ---- 2 files changed, 6 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/__init__.py b/src/finn/custom_op/fpgadataflow/__init__.py index bd9c0366e7..7697e8765d 100644 --- a/src/finn/custom_op/fpgadataflow/__init__.py +++ b/src/finn/custom_op/fpgadataflow/__init__.py @@ -51,7 +51,6 @@ from finn.custom_op.fpgadataflow.streamingeltwise import StreamingEltwise from finn.custom_op.fpgadataflow.streamingfifo import StreamingFIFO from finn.custom_op.fpgadataflow.streamingmaxpool import StreamingMaxPool -from finn.custom_op.fpgadataflow.thresholding_batch import Thresholding_Batch from finn.custom_op.fpgadataflow.thresholding import ( Thresholding, ) @@ -64,7 +63,6 @@ # registered and plug in correctly into the infrastructure custom_op["MatrixVectorActivation"] = MatrixVectorActivation custom_op["StreamingFIFO"] = StreamingFIFO -custom_op["Thresholding_Batch"] = Thresholding_Batch custom_op["Thresholding"] = Thresholding custom_op["VectorVectorActivation"] = VectorVectorActivation custom_op["StreamingDataflowPartition"] = StreamingDataflowPartition diff --git a/tests/fpgadataflow/test_convert_to_hw_thresholding.py b/tests/fpgadataflow/test_convert_to_hw_thresholding.py index e96581dc89..c7495dd1e4 100755 --- a/tests/fpgadataflow/test_convert_to_hw_thresholding.py +++ b/tests/fpgadataflow/test_convert_to_hw_thresholding.py @@ -39,10 +39,6 @@ from qonnx.transformation.infer_datatypes import InferDataTypes from qonnx.transformation.infer_shapes import InferShapes from qonnx.util.basic import gen_finn_dt_tensor -from test_fpgadataflow_thresholding_binary_search import ( - make_single_thresholding_binary_search_modelwrapper, -) - import finn.transformation.fpgadataflow.convert_to_hls_layers as to_hls from finn.core.rtlsim_exec import rtlsim_exec from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP From b626ae40e0e97d15cc3f453f49d35e6cd97c8bd5 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Fri, 26 Jan 2024 16:49:01 +0000 Subject: [PATCH 423/665] [TBS] Remove batch from layer name Signed-off-by: aziz bahri --- src/finn/transformation/fpgadataflow/convert_to_hw_layers.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py index 88a9a64cd6..58ff3e7c0c 100644 --- a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py +++ b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py @@ -255,7 +255,7 @@ def apply(self, model): numInputVectors=list(thl_in_shape[:-1]), ActVal=actval, mem_mode=self.mem_mode, - name="Thresholding_Batch_" + node.name, + name="Thresholding_" + node.name, ) graph.node.insert(insert_point, new_node) From e5a9ad424196fd762e9a389f7fd7850a5e1a523a Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 29 Jan 2024 11:30:01 +0000 Subject: [PATCH 424/665] [CustomOp] Re-add tlastmarker hls in registry --- src/finn/custom_op/fpgadataflow/hls/__init__.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/finn/custom_op/fpgadataflow/hls/__init__.py b/src/finn/custom_op/fpgadataflow/hls/__init__.py index 87611517f1..188f45273c 100644 --- a/src/finn/custom_op/fpgadataflow/hls/__init__.py +++ b/src/finn/custom_op/fpgadataflow/hls/__init__.py @@ -47,9 +47,9 @@ ) from finn.custom_op.fpgadataflow.hls.streamingeltwise_hls import StreamingEltwise_hls from finn.custom_op.fpgadataflow.hls.streamingmaxpool_hls import StreamingMaxPool_hls +from finn.custom_op.fpgadataflow.hls.thresholding_hls import Thresholding_hls from finn.custom_op.fpgadataflow.hls.tlastmarker_hls import TLastMarker_hls from finn.custom_op.fpgadataflow.hls.upsampler_hls import UpsampleNearestNeighbour_hls -from finn.custom_op.fpgadataflow.hls.thresholding_hls import Thresholding_hls custom_op = dict() @@ -73,4 +73,5 @@ custom_op["StreamingDataWidthConverter_hls"] = StreamingDataWidthConverter_hls custom_op["StreamingMaxPool_hls"] = StreamingMaxPool_hls custom_op["Thresholding_hls"] = Thresholding_hls +custom_op["TLastMarker_hls"] = TLastMarker_hls custom_op["UpsampleNearestNeighbour_hls"] = UpsampleNearestNeighbour_hls From cbda16ece4acd7f5fb5aead14a621c2a98dfb47c Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 29 Jan 2024 12:58:15 +0000 Subject: [PATCH 425/665] [CustomOp] Update thresholding new class hierarchy --- .../fpgadataflow/hls/thresholding_hls.py | 152 +----------------- .../custom_op/fpgadataflow/thresholding.py | 140 +++++++++++++--- .../fpgadataflow/specialize_layers.py | 1 + .../test_convert_to_hw_thresholding.py | 37 ++--- .../test_fpgadataflow_thresholding.py | 11 +- 5 files changed, 140 insertions(+), 201 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py b/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py index 0ad198feb5..91a8693761 100644 --- a/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py @@ -1,4 +1,4 @@ -# Copyright (c) 2024, Xilinx +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -29,17 +29,15 @@ import numpy as np import os import textwrap -import warnings from math import ceil, log2 -from finn.custom_op.fpgadataflow.thresholding import Thresholding -from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend from qonnx.core.datatype import DataType from qonnx.util.basic import ( interleave_matrix_outer_dim_from_partitions, roundup_to_integer_multiple, ) -from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp +from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend +from finn.custom_op.fpgadataflow.thresholding import Thresholding from finn.util.data_packing import ( npy_to_rtlsim_input, numpy_to_hls_code, @@ -54,32 +52,16 @@ # the ... here can be any shape (representing groups of vectors) -class Thresholding_hls(Thresholding,HLSBackend): +class Thresholding_hls(Thresholding, HLSBackend): """Class that corresponds to finn-hls Thresholding_Batch function.""" def __init__(self, onnx_node, **kwargs): super().__init__(onnx_node, **kwargs) - self.variant = "hls" def get_nodeattr_types(self): my_attrs = { - # parallelization; channels thresholded per cycle - "PE": ("i", True, 0), - # number of channels (each may have different thresholds) - "NumChannels": ("i", True, 0), - # number of steps in thresholding function - "numSteps": ("i", True, 1), # string defining memory type "ram_style": ("s", False, "distributed", {"distributed", "block"}), - # FINN DataTypes for inputs, outputs - "inputDataType": ("s", True, ""), - "weightDataType": ("s", True, ""), - "outputDataType": ("s", True, ""), - # number of input vectors, examples: - # [1] is a single vector (like a FC layer with batch=1) - # [4] is four vectors (like a FC layer with batch=4) - # [1, 4, 4] is four * four vectors (like a conv layer with batch=1) - "numInputVectors": ("ints", False, [1]), # initialization value for the thresholding accumulator "ActVal": ("i", False, 0), # memory mode for the thresholds @@ -97,7 +79,8 @@ def get_nodeattr_types(self): # weight data from the weight FIFOs. "runtime_writeable_weights": ("i", False, 0, {0, 1}), } - my_attrs.update(super().get_nodeattr_types()) + my_attrs.update(Thresholding.get_nodeattr_types(self)) + my_attrs.update(HLSBackend.get_nodeattr_types(self)) return my_attrs def calc_tmem(self): @@ -106,49 +89,6 @@ def calc_tmem(self): pe = self.get_nodeattr("PE") return mh // pe - def make_shape_compatible_op(self, model): - oshape = self.get_normal_output_shape() - return super().make_const_shape_op(oshape) - - def infer_node_datatype(self, model): - node = self.onnx_node - idt = model.get_tensor_datatype(node.input[0]) - if idt != self.get_input_datatype(): - warn_str = "inputDataType changing for %s: %s -> %s " % ( - node.name, - str(self.get_input_datatype().name), - str(idt.name), - ) - warnings.warn(warn_str) - self.set_nodeattr("inputDataType", idt.name) - # set output datatype from property - odt = self.get_output_datatype() - model.set_tensor_datatype(node.output[0], odt) - - def verify_node(self): - info_messages = [] - # verify that "backend" is set to "fpgadataflow" - backend_value = self.get_nodeattr("backend") - if backend_value == "fpgadataflow": - info_messages.append("Attribute backend is set correctly") - else: - info_messages.append('Attribute backend should be set to "fpgadataflow"') - - # verify that all necessary attributes exist - # TODO collect automatically from get_nodeattr_types - try: - self.get_nodeattr("code_gen_dir_cppsim") - self.get_nodeattr("executable_path") - self.get_nodeattr("NumChannels") - self.get_nodeattr("PE") - self.get_nodeattr("inputDataType") - self.get_nodeattr("outputDataType") - info_messages.append("All necessary attributes exist") - except Exception: - info_messages.append("""The required Threshold_Batch attributes do not exist.""") - - return info_messages - def bram_estimation(self): """Calculates BRAM cost if resource set to BRAM""" style = self.get_nodeattr("ram_style") @@ -180,52 +120,6 @@ def lut_estimation(self): # total cost return comparator_cost + lutram_cost - def get_input_datatype(self, ind=0): - """Returns FINN DataType of input.""" - return DataType[self.get_nodeattr("inputDataType")] - - def get_output_datatype(self, ind=0): - """Returns FINN DataType of output.""" - return DataType[self.get_nodeattr("outputDataType")] - - def get_weight_datatype(self): - """Returns FINN DataType of thresholds, here called weights.""" - return DataType[self.get_nodeattr("weightDataType")] - - def minimize_accumulator_width(self, model): - "Minimize threshold width ('accumulator width' here due to convention)" - thresholds = model.get_initializer(self.onnx_node.input[1]) - threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds) - min_threshold = thresholds.min() - max_threshold = thresholds.max() - min_input = self.get_input_datatype().min() - max_input = self.get_input_datatype().max() - # get range required by threshold values - tdt_min = min(min_input, min_threshold) - tdt_max = max(max_input, max_threshold) - if tdt_min < 0: - if abs(tdt_min) > tdt_max: - tdt = DataType.get_smallest_possible(tdt_min) - else: - tdt = DataType.get_smallest_possible(-tdt_max - 1) - else: - tdt = DataType.get_smallest_possible(tdt_max) - assert np.vectorize(tdt.allowed)( - threshold_tensor - ).all(), "Thresholds can't be expressed with type %s" % str(tdt) - self.set_nodeattr("weightDataType", tdt.name) - # Update QONNX DataType of tensor for consistency - model.set_tensor_datatype(self.onnx_node.input[1], tdt) - return DataType[self.get_nodeattr("weightDataType")] - - def get_instream_width(self, ind=0): - i_bits = self.get_input_datatype().bitwidth() - return i_bits * self.get_nodeattr("PE") - - def get_outstream_width(self, ind=0): - o_bits = self.get_output_datatype().bitwidth() - return o_bits * self.get_nodeattr("PE") - def get_weightstream_width(self): """Returns weight stream width. Used only in decoupled mode.""" if self.get_nodeattr("mem_mode") == "decoupled": @@ -248,36 +142,6 @@ def get_ap_int_max_w(self): weightstream = self.get_weightstream_width() return max([weightstream, temp_value]) - def get_folded_input_shape(self, ind=0): - ich = self.get_nodeattr("NumChannels") - pe = self.get_nodeattr("PE") - fold = ich // pe - vecs = list(self.get_nodeattr("numInputVectors")) - folded_input_shape = tuple(vecs + [fold, pe]) - return folded_input_shape - - def get_folded_output_shape(self, ind=0): - # same shape as input - return self.get_folded_input_shape() - - def get_normal_input_shape(self, ind=0): - ich = self.get_nodeattr("NumChannels") - vecs = list(self.get_nodeattr("numInputVectors")) - normal_input_shape = tuple(vecs + [ich]) - return normal_input_shape - - def get_normal_output_shape(self, ind=0): - # same shape as input - return self.get_normal_input_shape() - - def get_number_output_values(self): - nf = np.prod(self.get_folded_output_shape()[:-1]) - return nf - - def get_exp_cycles(self): - # Channels/PE * batch size * fmdim * fmdim - return np.prod(self.get_folded_output_shape()[:-1]) - def get_template_param_values(self): """Returns the template parameter values according to input, output and weight data types.""" @@ -655,13 +519,11 @@ def strm_decl(self): def docompute(self): tmpl_args = self.get_template_param_values() - node = self.onnx_node mem_mode = self.get_nodeattr("mem_mode") if mem_mode == "const": self.code_gen_dict["$DOCOMPUTE$"] = [ - """{} + """Thresholding_Batch (in0_{}, out_{}, threshs, numReps);""".format( - node.op_type, tmpl_args["TSrcI"], tmpl_args["TDstI"], self.hls_sname(), diff --git a/src/finn/custom_op/fpgadataflow/thresholding.py b/src/finn/custom_op/fpgadataflow/thresholding.py index 004bf1aec0..0297d0143b 100644 --- a/src/finn/custom_op/fpgadataflow/thresholding.py +++ b/src/finn/custom_op/fpgadataflow/thresholding.py @@ -54,25 +54,6 @@ def get_nodeattr_types(self): # [4] is four vectors (like a FC layer with batch=4) # [1, 4, 4] is four * four vectors (like a conv layer with batch=1) "numInputVectors": ("ints", False, [1]), - # name of the top module in verilog template. Used by PyVerilator - # and IPI generation - "gen_top_module": ("s", False, ""), - # bias to be applied to outputs of the node - "activation_bias": ("i", False, 0), - # whether weights (thresholds) will be - # writable through an AXI-lite interface during runtime - # 1 for enabled, 0 for disabled. - "runtime_writeable_weights": ("i", False, 0, {0, 1}), - # memory depth triggers for threshold storage - "depth_trigger_uram": ("i", False, 0), - "depth_trigger_bram": ("i", False, 0), - # enable uniform thres optimization - # doesn't actually do anything yet, only - # for resource estimations - "uniform_thres": ("i", False, 0, {0, 1}), - # enable deep pipelining for easier timing closure - # setting to 0 may save some FFs but otherwise leave on - "deep_pipeline": ("i", False, 1, {0, 1}), } my_attrs.update(super().get_nodeattr_types()) return my_attrs @@ -81,11 +62,120 @@ def make_shape_compatible_op(self, model): oshape = self.get_normal_output_shape() return super().make_const_shape_op(oshape) - def verify_node(): - pass - def infer_node_datatype(): - pass - def get_number_output_values(): - pass + def infer_node_datatype(self, model): + node = self.onnx_node + idt = model.get_tensor_datatype(node.input[0]) + if idt != self.get_input_datatype(): + warn_str = "inputDataType changing for %s: %s -> %s " % ( + node.name, + str(self.get_input_datatype().name), + str(idt.name), + ) + warnings.warn(warn_str) + self.set_nodeattr("inputDataType", idt.name) + # set output datatype from property + odt = self.get_output_datatype() + model.set_tensor_datatype(node.output[0], odt) + + def verify_node(self): + info_messages = [] + # verify that "backend" is set to "fpgadataflow" + backend_value = self.get_nodeattr("backend") + if backend_value == "fpgadataflow": + info_messages.append("Attribute backend is set correctly") + else: + info_messages.append('Attribute backend should be set to "fpgadataflow"') + + # verify that all necessary attributes exist + # TODO collect automatically from get_nodeattr_types + try: + self.get_nodeattr("code_gen_dir_cppsim") + self.get_nodeattr("executable_path") + self.get_nodeattr("NumChannels") + self.get_nodeattr("PE") + self.get_nodeattr("inputDataType") + self.get_nodeattr("outputDataType") + info_messages.append("All necessary attributes exist") + except Exception: + info_messages.append("""The required Threshold_Batch attributes do not exist.""") + + return info_messages + + def get_input_datatype(self, ind=0): + """Returns FINN DataType of input.""" + return DataType[self.get_nodeattr("inputDataType")] + + def get_output_datatype(self, ind=0): + """Returns FINN DataType of output.""" + return DataType[self.get_nodeattr("outputDataType")] + + def get_weight_datatype(self): + """Returns FINN DataType of thresholds, here called weights.""" + return DataType[self.get_nodeattr("weightDataType")] + + def minimize_accumulator_width(self, model): + "Minimize threshold width ('accumulator width' here due to convention)" + thresholds = model.get_initializer(self.onnx_node.input[1]) + threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds) + min_threshold = thresholds.min() + max_threshold = thresholds.max() + min_input = self.get_input_datatype().min() + max_input = self.get_input_datatype().max() + # get range required by threshold values + tdt_min = min(min_input, min_threshold) + tdt_max = max(max_input, max_threshold) + if tdt_min < 0: + if abs(tdt_min) > tdt_max: + tdt = DataType.get_smallest_possible(tdt_min) + else: + tdt = DataType.get_smallest_possible(-tdt_max - 1) + else: + tdt = DataType.get_smallest_possible(tdt_max) + assert np.vectorize(tdt.allowed)( + threshold_tensor + ).all(), "Thresholds can't be expressed with type %s" % str(tdt) + self.set_nodeattr("weightDataType", tdt.name) + # Update QONNX DataType of tensor for consistency + model.set_tensor_datatype(self.onnx_node.input[1], tdt) + return DataType[self.get_nodeattr("weightDataType")] + + def get_instream_width(self, ind=0): + i_bits = self.get_input_datatype().bitwidth() + return i_bits * self.get_nodeattr("PE") + + def get_outstream_width(self, ind=0): + o_bits = self.get_output_datatype().bitwidth() + return o_bits * self.get_nodeattr("PE") + + def get_folded_input_shape(self, ind=0): + ich = self.get_nodeattr("NumChannels") + pe = self.get_nodeattr("PE") + fold = ich // pe + vecs = list(self.get_nodeattr("numInputVectors")) + folded_input_shape = tuple(vecs + [fold, pe]) + return folded_input_shape + + def get_folded_output_shape(self, ind=0): + # same shape as input + return self.get_folded_input_shape() + + def get_normal_input_shape(self, ind=0): + ich = self.get_nodeattr("NumChannels") + vecs = list(self.get_nodeattr("numInputVectors")) + normal_input_shape = tuple(vecs + [ich]) + return normal_input_shape + + def get_normal_output_shape(self, ind=0): + # same shape as input + return self.get_normal_input_shape() + + def get_number_output_values(self): + nf = np.prod(self.get_folded_output_shape()[:-1]) + return nf + + def get_exp_cycles(self): + # Channels/PE * batch size * fmdim * fmdim + return np.prod(self.get_folded_output_shape()[:-1]) + def execute_node(self, context, graph): pass diff --git a/src/finn/transformation/fpgadataflow/specialize_layers.py b/src/finn/transformation/fpgadataflow/specialize_layers.py index 31da3756d3..7fda50c965 100644 --- a/src/finn/transformation/fpgadataflow/specialize_layers.py +++ b/src/finn/transformation/fpgadataflow/specialize_layers.py @@ -39,6 +39,7 @@ restricted_layers = [] restricted_layers.append("MatrixVectorActivation") restricted_layers.append("VectorVectorActivation") +restricted_layers.append("Thresholding") def _determine_impl_style(node): diff --git a/tests/fpgadataflow/test_convert_to_hw_thresholding.py b/tests/fpgadataflow/test_convert_to_hw_thresholding.py index c7495dd1e4..dffc5c4642 100755 --- a/tests/fpgadataflow/test_convert_to_hw_thresholding.py +++ b/tests/fpgadataflow/test_convert_to_hw_thresholding.py @@ -1,4 +1,4 @@ -# Copyright (C) 2023, Advanced Micro Devices, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -30,23 +30,14 @@ import numpy as np from onnx import TensorProto, helper -from pyverilator.util.axi_utils import axilite_write, reset_rtlsim from qonnx.core.datatype import DataType from qonnx.core.modelwrapper import ModelWrapper -from qonnx.custom_op.general.multithreshold import multithreshold -from qonnx.custom_op.registry import getCustomOp from qonnx.transformation.general import GiveUniqueNodeNames from qonnx.transformation.infer_datatypes import InferDataTypes from qonnx.transformation.infer_shapes import InferShapes -from qonnx.util.basic import gen_finn_dt_tensor -import finn.transformation.fpgadataflow.convert_to_hls_layers as to_hls -from finn.core.rtlsim_exec import rtlsim_exec -from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP -from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP -from finn.transformation.fpgadataflow.insert_fifo import InsertFIFO -from finn.transformation.fpgadataflow.prepare_ip import PrepareIP -from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers + from finn.transformation.fpgadataflow.convert_to_hw_layers import InferThresholdingLayer +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers test_fpga_part = "xczu3eg-sbva484-1-e" target_clk_ns = 5 @@ -83,12 +74,8 @@ def make_single_multithresholding_modelwrapper( ): NumChannels = thresholds.shape[0] - inp = helper.make_tensor_value_info( - "inp", TensorProto.FLOAT, num_input_vecs + [NumChannels] - ) - outp = helper.make_tensor_value_info( - "outp", TensorProto.FLOAT, num_input_vecs + [NumChannels] - ) + inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, num_input_vecs + [NumChannels]) + outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, num_input_vecs + [NumChannels]) node_inp_list = ["inp", "thresh"] @@ -128,7 +115,7 @@ def make_single_multithresholding_modelwrapper( @pytest.mark.parametrize("input_data_type", [DataType["INT16"], DataType["UINT16"]]) @pytest.mark.parametrize("fold", [-1, 1, 2, 4, 6]) @pytest.mark.parametrize("num_input_channels", [16]) -@pytest.mark.parametrize("impl_style", ["rtl", "hls"]) +@pytest.mark.parametrize("impl_style", ["hls"]) # TODO: add rtl later @pytest.mark.fpgadataflow @pytest.mark.vivado def test_convert_multithreshold_to_hardware( @@ -147,8 +134,7 @@ def test_convert_multithreshold_to_hardware( # This implies that it expects a negative activation, BIPOLAR does not provide that if activation == DataType["BIPOLAR"]: pytest.skip( - "Only negative activations are supported for " - "RTL Thresholding Binary Search node" + "Only negative activations are supported for " "RTL Thresholding Binary Search node" ) # Other non-input parameters @@ -160,9 +146,7 @@ def test_convert_multithreshold_to_hardware( activation_bias = output_data_type.min() # Generate random thresholds and sort in ascending order - thresholds = generate_random_threshold_values( - input_data_type, num_input_channels, num_steps - ) + thresholds = generate_random_threshold_values(input_data_type, num_input_channels, num_steps) # provide non-decreasing/ascending thresholds thresholds = sort_thresholds_increasing(thresholds) @@ -180,6 +164,5 @@ def test_convert_multithreshold_to_hardware( model = model.transform(InferThresholdingLayer()) model = model.transform(SpecializeLayers()) model = model.transform(InferShapes()) - - node_variant = getCustomOp(model.graph.node[0]).variant - assert (impl_style == node_variant) \ No newline at end of file + # TODO functional verification + assert model.graph.node[0].op_type == "Thresholding_" + str(impl_style) diff --git a/tests/fpgadataflow/test_fpgadataflow_thresholding.py b/tests/fpgadataflow/test_fpgadataflow_thresholding.py index 2b7bc28a10..ca2651a31c 100644 --- a/tests/fpgadataflow/test_fpgadataflow_thresholding.py +++ b/tests/fpgadataflow/test_fpgadataflow_thresholding.py @@ -1,4 +1,4 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -51,6 +51,7 @@ from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers test_fpga_part = "xczu3eg-sbva484-1-e" target_clk_ns = 5 @@ -65,7 +66,7 @@ def make_single_thresholding_modelwrapper(T, pe, idt, odt, actval, mem_mode, n_i node_inp_list = ["inp", "thresh"] Thresholding_node = helper.make_node( - "Thresholding_Batch", + "Thresholding", node_inp_list, ["outp"], domain="finn.custom_op.fpgadataflow", @@ -135,6 +136,7 @@ def test_fpgadataflow_thresholding(idt, act, nf, ich, exec_mode, mem_mode): actval = odt.min() model = make_single_thresholding_modelwrapper(T, pe, idt, odt, actval, mem_mode, n_inp_vecs) + model = model.transform(SpecializeLayers()) if exec_mode == "cppsim": model = model.transform(PrepareCppSim()) @@ -174,9 +176,9 @@ def test_fpgadataflow_thresholding(idt, act, nf, ich, exec_mode, mem_mode): if exec_mode == "rtlsim": hls_synt_res_est = model.analysis(hls_synth_res_estimation) - assert "Thresholding_Batch_0" in hls_synt_res_est + assert "Thresholding_hls_0" in hls_synt_res_est - node = model.get_nodes_by_op_type("Thresholding_Batch")[0] + node = model.get_nodes_by_op_type("Thresholding_hls")[0] inst = getCustomOp(node) cycles_rtlsim = inst.get_nodeattr("cycles_rtlsim") exp_cycles_dict = model.analysis(exp_cycles_per_layer) @@ -212,6 +214,7 @@ def test_runtime_thresholds_single_layer(): actval = odt.min() model = make_single_thresholding_modelwrapper(T, pe, idt, odt, actval, mem_mode, n_inp_vecs) + model = model.transform(SpecializeLayers()) op_inst = getCustomOp(model.graph.node[0]) op_inst.set_nodeattr("runtime_writeable_weights", 1) op_inst.make_weight_file(T, "decoupled_runtime", "old_weights.dat") From 8ab3857258d51c5f57ad36329f793d1858e17cb0 Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 29 Jan 2024 13:30:02 +0000 Subject: [PATCH 426/665] [Tests] Fix runtime thresholding test --- tests/fpgadataflow/test_fpgadataflow_thresholding.py | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/fpgadataflow/test_fpgadataflow_thresholding.py b/tests/fpgadataflow/test_fpgadataflow_thresholding.py index ca2651a31c..696ac63c75 100644 --- a/tests/fpgadataflow/test_fpgadataflow_thresholding.py +++ b/tests/fpgadataflow/test_fpgadataflow_thresholding.py @@ -225,6 +225,7 @@ def test_runtime_thresholds_single_layer(): old_weight_stream = list(old_weight_stream) # need to create stitched IP for runtime weight testing model = model.transform(InsertFIFO(True)) + model = model.transform(SpecializeLayers()) model = model.transform(GiveUniqueNodeNames()) model = model.transform(PrepareIP(test_fpga_part, target_clk_ns)) model = model.transform(HLSSynthIP()) From b1452d2cb2fe769e7f49b0ee0a146e8d6222f1c2 Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 29 Jan 2024 17:45:56 +0000 Subject: [PATCH 427/665] [CustomOp] Add execution fct for thresh hw layer --- .../custom_op/fpgadataflow/thresholding.py | 20 ++++++++- .../test_fpgadataflow_thresholding.py | 44 ++++++++++++------- 2 files changed, 45 insertions(+), 19 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/thresholding.py b/src/finn/custom_op/fpgadataflow/thresholding.py index 0297d0143b..6b91735119 100644 --- a/src/finn/custom_op/fpgadataflow/thresholding.py +++ b/src/finn/custom_op/fpgadataflow/thresholding.py @@ -1,4 +1,4 @@ -# Copyright (C) 2023, Advanced Micro Devices, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -29,11 +29,14 @@ import numpy as np import warnings from qonnx.core.datatype import DataType +from qonnx.custom_op.general.multithreshold import multithreshold from finn.custom_op.fpgadataflow.hwcustomop import HWCustomOp class Thresholding(HWCustomOp): + """Abstraction layer for HW implementation of Thresholding.""" + def __init__(self, onnx_node, **kwargs): super().__init__(onnx_node, **kwargs) @@ -178,4 +181,17 @@ def get_exp_cycles(self): return np.prod(self.get_folded_output_shape()[:-1]) def execute_node(self, context, graph): - pass + node = self.onnx_node + inp_values = context[node.input[0]] + th_val = context[node.input[1]] + + y = multithreshold(np.transpose(inp_values, (0, 3, 1, 2)), th_val) + y = y.transpose(0, 2, 3, 1) + act = DataType[self.get_nodeattr("outputDataType")] + if act == DataType["BIPOLAR"]: + # binary to bipolar + y = 2 * y - 1 + else: + # signed offset + y += act.min() + context[node.output[0]] = y diff --git a/tests/fpgadataflow/test_fpgadataflow_thresholding.py b/tests/fpgadataflow/test_fpgadataflow_thresholding.py index 696ac63c75..43eca7b7c3 100644 --- a/tests/fpgadataflow/test_fpgadataflow_thresholding.py +++ b/tests/fpgadataflow/test_fpgadataflow_thresholding.py @@ -136,6 +136,32 @@ def test_fpgadataflow_thresholding(idt, act, nf, ich, exec_mode, mem_mode): actval = odt.min() model = make_single_thresholding_modelwrapper(T, pe, idt, odt, actval, mem_mode, n_inp_vecs) + + # calculate reference output + # multithreshold util fxn wants NCHW input, not NHWC + y = multithreshold(np.transpose(x, (0, 3, 1, 2)), T) + # convert back to NHWC for comparison to hw outputs + y = np.transpose(y, (0, 2, 3, 1)) + if act == DataType["BIPOLAR"]: + # binary to bipolar + y = 2 * y - 1 + else: + # signed offset + y += act.min() + + oshape = model.get_tensor_shape("outp") + y_expected = y.reshape(oshape) + + # package input data as dictionary + input_dict = {"inp": x} + + # execute model + y_produced = oxe.execute_onnx(model, input_dict)["outp"] + + y_produced = y_produced.reshape(y_expected.shape) + + assert (y_produced == y_expected).all() + model = model.transform(SpecializeLayers()) if exec_mode == "cppsim": @@ -151,28 +177,12 @@ def test_fpgadataflow_thresholding(idt, act, nf, ich, exec_mode, mem_mode): else: raise Exception("Unknown exec_mode") - # package input data as dictionary - input_dict = {"inp": x} - - # multithreshold util fxn wants NCHW input, not NHWC - y = multithreshold(np.transpose(x, (0, 3, 1, 2)), T) - # convert back to NHWC for comparison to hw outputs - y = np.transpose(y, (0, 2, 3, 1)) - if act == DataType["BIPOLAR"]: - # binary to bipolar - y = 2 * y - 1 - else: - # signed offset - y += act.min() - - oshape = model.get_tensor_shape("outp") - y_expected = y.reshape(oshape) # execute model y_produced = oxe.execute_onnx(model, input_dict)["outp"] y_produced = y_produced.reshape(y_expected.shape) - assert (y_produced == y_expected).all(), "cppsim failed" + assert (y_produced == y_expected).all() if exec_mode == "rtlsim": hls_synt_res_est = model.analysis(hls_synth_res_estimation) From 53094b250756e0f97708595cffc1a417facc9374 Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 30 Jan 2024 09:16:31 +0000 Subject: [PATCH 428/665] [CustomOp] Move node attribute in thresholding --- src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py | 2 -- src/finn/custom_op/fpgadataflow/thresholding.py | 2 ++ .../transformation/fpgadataflow/convert_to_hw_layers.py | 7 ++++--- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py b/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py index 91a8693761..5dcff9aa2b 100644 --- a/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py @@ -62,8 +62,6 @@ def get_nodeattr_types(self): my_attrs = { # string defining memory type "ram_style": ("s", False, "distributed", {"distributed", "block"}), - # initialization value for the thresholding accumulator - "ActVal": ("i", False, 0), # memory mode for the thresholds # const -- embedded thresholds, default # decoupled -- streaming thresholds with streamer packaged inside IP diff --git a/src/finn/custom_op/fpgadataflow/thresholding.py b/src/finn/custom_op/fpgadataflow/thresholding.py index 6b91735119..1ce059358e 100644 --- a/src/finn/custom_op/fpgadataflow/thresholding.py +++ b/src/finn/custom_op/fpgadataflow/thresholding.py @@ -57,6 +57,8 @@ def get_nodeattr_types(self): # [4] is four vectors (like a FC layer with batch=4) # [1, 4, 4] is four * four vectors (like a conv layer with batch=1) "numInputVectors": ("ints", False, [1]), + # initialization value for the thresholding accumulator + "ActVal": ("i", False, 0), } my_attrs.update(super().get_nodeattr_types()) return my_attrs diff --git a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py index 58ff3e7c0c..d1d61f0ed5 100644 --- a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py +++ b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py @@ -180,12 +180,12 @@ def apply(self, model): model = model.transform(InferDataTypes()) return (model, graph_modified) + class InferThresholdingLayer(Transformation): """Convert any MultiThreshold into a standalone thresholding HLS layer.""" - def __init__(self, mem_mode="const"): + def __init__(self): super().__init__() - self.mem_mode = mem_mode def apply(self, model): graph = model.graph @@ -254,7 +254,6 @@ def apply(self, model): outputDataType=odt.name, numInputVectors=list(thl_in_shape[:-1]), ActVal=actval, - mem_mode=self.mem_mode, name="Thresholding_" + node.name, ) @@ -264,6 +263,8 @@ def apply(self, model): graph_modified = True return (model, graph_modified) + + class InferUpsample(Transformation): """Convert Upsample and Resize nodes to layers to UpsampleNearestNeighbour nodes.""" From 07b4d7fbd916a91f4e43f91e95d1ba98ebe23270 Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 30 Jan 2024 09:22:27 +0000 Subject: [PATCH 429/665] [CustomOp] Fix linting in registry --- src/finn/custom_op/fpgadataflow/__init__.py | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/__init__.py b/src/finn/custom_op/fpgadataflow/__init__.py index 7697e8765d..d4c9904fe1 100644 --- a/src/finn/custom_op/fpgadataflow/__init__.py +++ b/src/finn/custom_op/fpgadataflow/__init__.py @@ -51,9 +51,7 @@ from finn.custom_op.fpgadataflow.streamingeltwise import StreamingEltwise from finn.custom_op.fpgadataflow.streamingfifo import StreamingFIFO from finn.custom_op.fpgadataflow.streamingmaxpool import StreamingMaxPool -from finn.custom_op.fpgadataflow.thresholding import ( - Thresholding, -) +from finn.custom_op.fpgadataflow.thresholding import Thresholding from finn.custom_op.fpgadataflow.upsampler import UpsampleNearestNeighbour from finn.custom_op.fpgadataflow.vectorvectoractivation import VectorVectorActivation From c600189ab13e0bb5cfb0d024322eb70f90636e53 Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 30 Jan 2024 11:00:23 +0000 Subject: [PATCH 430/665] [rtllib] Clean up fifo and fmpadding wrapper --- finn-rtllib/fifo/hdl/fifo_template.v | 8 ++++---- finn-rtllib/fmpadding/hdl/fmpadding_template.v | 11 ++++++----- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/finn-rtllib/fifo/hdl/fifo_template.v b/finn-rtllib/fifo/hdl/fifo_template.v index 4c614c83dd..3f14ae991f 100644 --- a/finn-rtllib/fifo/hdl/fifo_template.v +++ b/finn-rtllib/fifo/hdl/fifo_template.v @@ -31,12 +31,12 @@ module $TOP_MODULE_NAME$( //- Global Control ------------------ -(* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out_V:s_axilite" *) +(* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out_V, ASSOCIATED_RESET = ap_rst_n" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *) input ap_clk, -(* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out_V:s_axilite" *) +(* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) input ap_rst_n, - output $COUNT_RANGE$ count, output $COUNT_RANGE$ maxcount, @@ -55,7 +55,7 @@ Q_srl #( .depth($DEPTH$), .width($WIDTH$) ) -$TOP_MODULE_NAME$_impl +impl ( .clock(ap_clk), .reset(!ap_rst_n), diff --git a/finn-rtllib/fmpadding/hdl/fmpadding_template.v b/finn-rtllib/fmpadding/hdl/fmpadding_template.v index 0b0f40f86a..2347d9b394 100644 --- a/finn-rtllib/fmpadding/hdl/fmpadding_template.v +++ b/finn-rtllib/fmpadding/hdl/fmpadding_template.v @@ -31,10 +31,11 @@ module $TOP_MODULE_NAME$( //- Global Control ------------------ -(* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out_V:s_axilite" *) -input ap_clk, -(* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out_V:s_axilite" *) -input ap_rst_n, +(* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out_V:s_axilite, ASSOCIATED_RESET = ap_rst_n" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *) +input ap_clk, +(* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) +input ap_rst_n, //- AXI Lite ------------------------ // Writing @@ -86,7 +87,7 @@ fmpadding_axi #( .INIT_YOFF($INIT_YOFF$), .INIT_YEND($INIT_YEND$) ) -$TOP_MODULE_NAME$_impl +impl ( .ap_clk(ap_clk), .ap_rst_n(ap_rst_n), From 88af9b7f74b3fb04c3b56af6d116672469e86f7f Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 30 Jan 2024 16:40:33 +0000 Subject: [PATCH 431/665] [CustomOps] First clean up over hls code generation functions --- .../fpgadataflow/hls/addstreams_hls.py | 3 - .../fpgadataflow/hls/channelwise_op_hls.py | 3 - .../fpgadataflow/hls/checksum_hls.py | 3 - .../custom_op/fpgadataflow/hls/concat_hls.py | 3 - .../hls/convolutioninputgenerator_hls.py | 37 ------------- .../fpgadataflow/hls/downsampler_hls.py | 37 ------------- .../fpgadataflow/hls/duplicatestreams_hls.py | 25 --------- .../fpgadataflow/hls/fmpadding_hls.py | 37 ------------- .../fpgadataflow/hls/fmpadding_pixel_hls.py | 55 ++++++------------- .../fpgadataflow/hls/globalaccpool_hls.py | 34 ------------ .../custom_op/fpgadataflow/hls/iodma_hls.py | 6 -- .../fpgadataflow/hls/labelselect_hls.py | 12 ---- .../custom_op/fpgadataflow/hls/lookup_hls.py | 3 - .../custom_op/fpgadataflow/hls/pool_hls.py | 12 ---- .../hls/streamingdatawidthconverter_hls.py | 28 ---------- .../fpgadataflow/hls/streamingeltwise_hls.py | 3 - .../fpgadataflow/hls/streamingmaxpool_hls.py | 37 ------------- .../fpgadataflow/hls/thresholding_hls.py | 3 - .../fpgadataflow/hls/tlastmarker_hls.py | 3 - .../fpgadataflow/hls/upsampler_hls.py | 37 ------------- src/finn/custom_op/fpgadataflow/hlsbackend.py | 46 ++++++++++++---- .../custom_op/fpgadataflow/streamingfifo.py | 24 +------- .../fpgadataflow/insert_fifo.py | 8 ++- .../fpgadataflow/set_fifo_depths.py | 2 + .../test_fpgadataflow_checksum.py | 2 + .../fpgadataflow/test_fpgadataflow_concat.py | 1 + 26 files changed, 68 insertions(+), 396 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/hls/addstreams_hls.py b/src/finn/custom_op/fpgadataflow/hls/addstreams_hls.py index 1a40970b77..4f7b58d8e1 100644 --- a/src/finn/custom_op/fpgadataflow/hls/addstreams_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/addstreams_hls.py @@ -251,9 +251,6 @@ def dataoutstrm(self): ) ] - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - def blackboxfunction(self): self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ """void {}(hls::stream> &in0_{}, hls::stream> &in1_{}, diff --git a/src/finn/custom_op/fpgadataflow/hls/channelwise_op_hls.py b/src/finn/custom_op/fpgadataflow/hls/channelwise_op_hls.py index e7c263c084..a698acfe49 100644 --- a/src/finn/custom_op/fpgadataflow/hls/channelwise_op_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/channelwise_op_hls.py @@ -408,9 +408,6 @@ def dataoutstrm(self): ) ] - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - def blackboxfunction(self): self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ """void {}(hls::stream> &in0_{}, diff --git a/src/finn/custom_op/fpgadataflow/hls/checksum_hls.py b/src/finn/custom_op/fpgadataflow/hls/checksum_hls.py index 23818621b9..8a72ca3c6c 100644 --- a/src/finn/custom_op/fpgadataflow/hls/checksum_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/checksum_hls.py @@ -305,9 +305,6 @@ def dataoutstrm(self): 'cnpy::npy_save("%s/output_checksum.npy",&checksum[0],{1},"w");' % code_gen_dir, ] - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - def blackboxfunction(self): self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ """using T = ap_uint;\n void {}(hls::stream &in0_{}, diff --git a/src/finn/custom_op/fpgadataflow/hls/concat_hls.py b/src/finn/custom_op/fpgadataflow/hls/concat_hls.py index f608b343f6..94e0c3626c 100644 --- a/src/finn/custom_op/fpgadataflow/hls/concat_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/concat_hls.py @@ -265,9 +265,6 @@ def dataoutstrm(self): ) ] - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - def blackboxfunction(self): n_inputs = self.get_n_inputs() in_streams = [] diff --git a/src/finn/custom_op/fpgadataflow/hls/convolutioninputgenerator_hls.py b/src/finn/custom_op/fpgadataflow/hls/convolutioninputgenerator_hls.py index 7223996e8b..5e0dbfd396 100644 --- a/src/finn/custom_op/fpgadataflow/hls/convolutioninputgenerator_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/convolutioninputgenerator_hls.py @@ -526,31 +526,6 @@ def defines(self, var): ) ] - def read_npy_data(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_input_datatype() - if dtype == DataType["BIPOLAR"]: - # use binary for bipolar storage - dtype = DataType["BINARY"] - elem_bits = dtype.bitwidth() - packed_bits = self.get_instream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_in = "%s/input_0.npy" % code_gen_dir - self.code_gen_dict["$READNPYDATA$"] = [] - self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - npy_in, - self.hls_sname(), - ) - ) - def strm_decl(self): self.code_gen_dict["$STREAMDECLARATIONS$"] = [] self.code_gen_dict["$STREAMDECLARATIONS$"].append( @@ -660,9 +635,6 @@ def dataoutstrm(self): ) ] - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - def blackboxfunction(self): if self.use_parallel_window_output(): self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ @@ -679,12 +651,3 @@ def blackboxfunction(self): self.onnx_node.name, self.hls_sname(), self.hls_sname() ) ] - - def pragmas(self): - self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() - ] - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() - ) - self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") diff --git a/src/finn/custom_op/fpgadataflow/hls/downsampler_hls.py b/src/finn/custom_op/fpgadataflow/hls/downsampler_hls.py index d5bd0877a4..ff9a83d091 100644 --- a/src/finn/custom_op/fpgadataflow/hls/downsampler_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/downsampler_hls.py @@ -72,31 +72,6 @@ def defines(self, var): batch_size = self.get_nodeattr("numInputVectors") self.code_gen_dict["$DEFINES$"] += ["#define numReps {}".format(batch_size)] - def read_npy_data(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_input_datatype() - if dtype == DataType["BIPOLAR"]: - # use binary for bipolar storage - dtype = DataType["BINARY"] - elem_bits = dtype.bitwidth() - packed_bits = self.get_instream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_in = "%s/input_0.npy" % code_gen_dir - self.code_gen_dict["$READNPYDATA$"] = [] - self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - npy_in, - self.hls_sname(), - ) - ) - def strm_decl(self): self.code_gen_dict["$STREAMDECLARATIONS$"] = [] self.code_gen_dict["$STREAMDECLARATIONS$"].append( @@ -146,9 +121,6 @@ def dataoutstrm(self): ) ] - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - def blackboxfunction(self): packed_bits = self.get_instream_width() packed_hls_type = "ap_uint<%d>" % packed_bits @@ -163,15 +135,6 @@ def blackboxfunction(self): ) ] - def pragmas(self): - self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() - ] - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() - ) - self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") - def execute_node(self, context, graph): mode = self.get_nodeattr("exec_mode") node = self.onnx_node diff --git a/src/finn/custom_op/fpgadataflow/hls/duplicatestreams_hls.py b/src/finn/custom_op/fpgadataflow/hls/duplicatestreams_hls.py index de0fadb26c..e19149435e 100644 --- a/src/finn/custom_op/fpgadataflow/hls/duplicatestreams_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/duplicatestreams_hls.py @@ -196,28 +196,6 @@ def global_includes(self): def defines(self, var): self.code_gen_dict["$DEFINES$"] = [] - def read_npy_data(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_input_datatype() - elem_bits = dtype.bitwidth() - packed_bits = self.get_instream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_in = "%s/input_0.npy" % code_gen_dir - self.code_gen_dict["$READNPYDATA$"] = [] - self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - npy_in, - self.hls_sname(), - ) - ) - def strm_decl(self): n_outputs = self.get_num_output_streams() self.code_gen_dict["$STREAMDECLARATIONS$"] = [] @@ -275,9 +253,6 @@ def dataoutstrm(self): self.code_gen_dict["$DATAOUTSTREAM$"] = outstrm_code - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - def blackboxfunction(self): n_outputs = self.get_num_output_streams() inp_streams = [] diff --git a/src/finn/custom_op/fpgadataflow/hls/fmpadding_hls.py b/src/finn/custom_op/fpgadataflow/hls/fmpadding_hls.py index 3b0b870e23..d21b672b73 100644 --- a/src/finn/custom_op/fpgadataflow/hls/fmpadding_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/fmpadding_hls.py @@ -100,31 +100,6 @@ def defines(self, var): ) ] - def read_npy_data(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_input_datatype() - if dtype == DataType["BIPOLAR"]: - # use binary for bipolar storage - dtype = DataType["BINARY"] - elem_bits = dtype.bitwidth() - packed_bits = self.get_instream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_in = "%s/input_0.npy" % code_gen_dir - self.code_gen_dict["$READNPYDATA$"] = [] - self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - npy_in, - self.hls_sname(), - ) - ) - def strm_decl(self): self.code_gen_dict["$STREAMDECLARATIONS$"] = [] self.code_gen_dict["$STREAMDECLARATIONS$"].append( @@ -193,9 +168,6 @@ def dataoutstrm(self): ) ] - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - def blackboxfunction(self): packed_bits = self.get_instream_width() packed_hls_type = "ap_uint<%d>" % packed_bits @@ -210,15 +182,6 @@ def blackboxfunction(self): ) ] - def pragmas(self): - self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() - ] - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() - ) - self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") - def execute_node(self, context, graph): mode = self.get_nodeattr("exec_mode") node = self.onnx_node diff --git a/src/finn/custom_op/fpgadataflow/hls/fmpadding_pixel_hls.py b/src/finn/custom_op/fpgadataflow/hls/fmpadding_pixel_hls.py index e1393dc96e..62942c4f28 100644 --- a/src/finn/custom_op/fpgadataflow/hls/fmpadding_pixel_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/fmpadding_pixel_hls.py @@ -70,31 +70,17 @@ def defines(self, var): ) ] - def read_npy_data(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_input_datatype() - if dtype == DataType["BIPOLAR"]: - # use binary for bipolar storage - dtype = DataType["BINARY"] - elem_bits = dtype.bitwidth() - packed_bits = self.get_instream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_in = "%s/input_0.npy" % code_gen_dir - self.code_gen_dict["$READNPYDATA$"] = [] - self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0);' - % (packed_hls_type, elem_hls_type, elem_bits, npy_type, npy_in) - ) - def strm_decl(self): self.code_gen_dict["$STREAMDECLARATIONS$"] = [] self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0 ("in0");'.format(self.get_instream_width()) + 'hls::stream> in0_{} ("in0_{}");'.format( + self.get_instream_width(), self.hls_sname(), self.hls_sname() + ) ) self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out ("out");'.format(self.get_outstream_width()) + 'hls::stream> out_{} ("out_{}");'.format( + self.get_outstream_width(), self.hls_sname(), self.hls_sname() + ) ) def docompute(self): @@ -104,8 +90,8 @@ def docompute(self): hls_call = "FMPadding_Pixel_Nonsquare" self.code_gen_dict["$DOCOMPUTE$"] = [ """{} (in0, out);""".format( - hls_call, in_t + SIMD, {}> (in0_{}, out_{});""".format( + hls_call, in_t, self.hls_sname(), self.hls_sname() ) ] @@ -125,36 +111,31 @@ def dataoutstrm(self): oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out, %s, "%s");' + 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' % ( packed_hls_type, elem_hls_type, elem_bits, npy_type, + self.hls_sname(), oshape_cpp_str, npy_out, ) ] - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - def blackboxfunction(self): packed_bits = self.get_instream_width() packed_hls_type = "ap_uint<%d>" % packed_bits self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - "void %s(hls::stream<%s > &in0, hls::stream<%s > &out)" - % (self.onnx_node.name, packed_hls_type, packed_hls_type) - ] - - def pragmas(self): - self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0 name=in0_" + self.hls_sname() + "void %s(hls::stream<%s > &in0_%s, hls::stream<%s > &out_%s)" + % ( + self.onnx_node.name, + packed_hls_type, + self.hls_sname(), + packed_hls_type, + self.hls_sname(), + ) ] - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out name=out_" + self.hls_sname() - ) - self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") def execute_node(self, context, graph): mode = self.get_nodeattr("exec_mode") diff --git a/src/finn/custom_op/fpgadataflow/hls/globalaccpool_hls.py b/src/finn/custom_op/fpgadataflow/hls/globalaccpool_hls.py index 93398b1dc9..8df18e8b8a 100644 --- a/src/finn/custom_op/fpgadataflow/hls/globalaccpool_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/globalaccpool_hls.py @@ -150,28 +150,6 @@ def global_includes(self): def defines(self, var): self.code_gen_dict["$DEFINES$"] = [] - def read_npy_data(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_input_datatype() - elem_bits = dtype.bitwidth() - packed_bits = self.get_instream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_in = "%s/input_0.npy" % code_gen_dir - self.code_gen_dict["$READNPYDATA$"] = [] - self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - npy_in, - self.hls_sname(), - ) - ) - def strm_decl(self): self.code_gen_dict["$STREAMDECLARATIONS$"] = [] self.code_gen_dict["$STREAMDECLARATIONS$"].append( @@ -223,9 +201,6 @@ def dataoutstrm(self): ) ] - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - def blackboxfunction(self): self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ """void {}(hls::stream> &in0_{}, @@ -237,12 +212,3 @@ def blackboxfunction(self): self.hls_sname(), ) ] - - def pragmas(self): - self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() - ] - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() - ) - self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") diff --git a/src/finn/custom_op/fpgadataflow/hls/iodma_hls.py b/src/finn/custom_op/fpgadataflow/hls/iodma_hls.py index a0701b8989..bdc313f592 100644 --- a/src/finn/custom_op/fpgadataflow/hls/iodma_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/iodma_hls.py @@ -413,12 +413,6 @@ def execute_node(self, context, graph): def dataoutstrm(self): pass - def read_npy_data(self): - pass - - def save_as_npy(self): - pass - def strm_decl(self): pass diff --git a/src/finn/custom_op/fpgadataflow/hls/labelselect_hls.py b/src/finn/custom_op/fpgadataflow/hls/labelselect_hls.py index 701d061987..cce45eb742 100644 --- a/src/finn/custom_op/fpgadataflow/hls/labelselect_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/labelselect_hls.py @@ -236,9 +236,6 @@ def dataoutstrm(self): ) ] - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - def blackboxfunction(self): self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ """void {}(hls::stream> &in0_{}, @@ -251,12 +248,3 @@ def blackboxfunction(self): self.hls_sname(), ) ] - - def pragmas(self): - self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() - ] - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() - ) - self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") diff --git a/src/finn/custom_op/fpgadataflow/hls/lookup_hls.py b/src/finn/custom_op/fpgadataflow/hls/lookup_hls.py index 885d3039a4..e51db9a811 100644 --- a/src/finn/custom_op/fpgadataflow/hls/lookup_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/lookup_hls.py @@ -141,9 +141,6 @@ def dataoutstrm(self): ) ] - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - def strm_decl(self): self.code_gen_dict["$STREAMDECLARATIONS$"] = [] self.code_gen_dict["$STREAMDECLARATIONS$"].append( diff --git a/src/finn/custom_op/fpgadataflow/hls/pool_hls.py b/src/finn/custom_op/fpgadataflow/hls/pool_hls.py index 2baaad01a7..05bb8fbd74 100644 --- a/src/finn/custom_op/fpgadataflow/hls/pool_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/pool_hls.py @@ -183,9 +183,6 @@ def dataoutstrm(self): ) ] - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - def blackboxfunction(self): packed_ibits = self.get_instream_width() packed_in_hls_type = "ap_uint<%d>" % packed_ibits @@ -203,15 +200,6 @@ def blackboxfunction(self): ) ] - def pragmas(self): - self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() - ] - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() - ) - self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") - def execute_node(self, context, graph): mode = self.get_nodeattr("exec_mode") node = self.onnx_node diff --git a/src/finn/custom_op/fpgadataflow/hls/streamingdatawidthconverter_hls.py b/src/finn/custom_op/fpgadataflow/hls/streamingdatawidthconverter_hls.py index be096e63c7..7b656a0120 100644 --- a/src/finn/custom_op/fpgadataflow/hls/streamingdatawidthconverter_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/streamingdatawidthconverter_hls.py @@ -71,31 +71,6 @@ def defines(self, var): self.code_gen_dict["$DEFINES$"].append("#define LCMWidth %d" % lcmWidth) self.code_gen_dict["$DEFINES$"].append("#define NumLCMToOut %d" % (numLCMToOut)) - def read_npy_data(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_input_datatype() - if dtype == DataType["BIPOLAR"]: - # use binary for bipolar storage - dtype = DataType["BINARY"] - elem_bits = dtype.bitwidth() - packed_bits = self.get_instream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_in = "%s/input_0.npy" % code_gen_dir - self.code_gen_dict["$READNPYDATA$"] = [] - self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - npy_in, - self.hls_sname(), - ) - ) - def strm_decl(self): self.code_gen_dict["$STREAMDECLARATIONS$"] = [] self.code_gen_dict["$STREAMDECLARATIONS$"].append( @@ -162,9 +137,6 @@ def dataoutstrm(self): ) ] - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - def blackboxfunction(self): in_packed_bits = self.get_instream_width() in_packed_hls_type = "ap_uint<%d>" % in_packed_bits diff --git a/src/finn/custom_op/fpgadataflow/hls/streamingeltwise_hls.py b/src/finn/custom_op/fpgadataflow/hls/streamingeltwise_hls.py index 2aec40f988..8528986d89 100644 --- a/src/finn/custom_op/fpgadataflow/hls/streamingeltwise_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/streamingeltwise_hls.py @@ -306,9 +306,6 @@ def dataoutstrm(self): ) ] - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - def blackboxfunction(self): self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ """void {}(hls::stream> &in0_{}, hls::stream> &in1_{}, diff --git a/src/finn/custom_op/fpgadataflow/hls/streamingmaxpool_hls.py b/src/finn/custom_op/fpgadataflow/hls/streamingmaxpool_hls.py index eb3284a343..b742e1f73b 100755 --- a/src/finn/custom_op/fpgadataflow/hls/streamingmaxpool_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/streamingmaxpool_hls.py @@ -95,31 +95,6 @@ def defines(self, var): ) ] - def read_npy_data(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_input_datatype() - if dtype == DataType["BIPOLAR"]: - # use binary for bipolar storage - dtype = DataType["BINARY"] - elem_bits = dtype.bitwidth() - packed_bits = self.get_instream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_in = "%s/input_0.npy" % code_gen_dir - self.code_gen_dict["$READNPYDATA$"] = [] - self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - npy_in, - self.hls_sname(), - ) - ) - def strm_decl(self): self.code_gen_dict["$STREAMDECLARATIONS$"] = [] self.code_gen_dict["$STREAMDECLARATIONS$"].append( @@ -190,9 +165,6 @@ def dataoutstrm(self): ) ] - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - def blackboxfunction(self): packed_bits = self.get_instream_width() packed_hls_type = "ap_uint<%d>" % packed_bits @@ -207,15 +179,6 @@ def blackboxfunction(self): ) ] - def pragmas(self): - self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() - ] - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() - ) - self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") - def execute_node(self, context, graph): mode = self.get_nodeattr("exec_mode") node = self.onnx_node diff --git a/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py b/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py index 5dcff9aa2b..fb90365eef 100644 --- a/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py @@ -575,9 +575,6 @@ def dataoutstrm(self): ) ] - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - def blackboxfunction(self): if self.get_nodeattr("mem_mode") == "const": self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ diff --git a/src/finn/custom_op/fpgadataflow/hls/tlastmarker_hls.py b/src/finn/custom_op/fpgadataflow/hls/tlastmarker_hls.py index c2ed06f832..2e908016e7 100644 --- a/src/finn/custom_op/fpgadataflow/hls/tlastmarker_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/tlastmarker_hls.py @@ -188,9 +188,6 @@ def docompute(self): def dataoutstrm(self): self.code_gen_dict["$DATAOUTSTREAM$"] = [] - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - def blackboxfunction(self): dyn_iters = self.get_nodeattr("DynIters") diff --git a/src/finn/custom_op/fpgadataflow/hls/upsampler_hls.py b/src/finn/custom_op/fpgadataflow/hls/upsampler_hls.py index 89a474a5d3..e52081edf2 100644 --- a/src/finn/custom_op/fpgadataflow/hls/upsampler_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/upsampler_hls.py @@ -74,31 +74,6 @@ def defines(self, var): batch_size = self.get_nodeattr("numInputVectors") self.code_gen_dict["$DEFINES$"] += ["#define numReps {}".format(batch_size)] - def read_npy_data(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_input_datatype() - if dtype == DataType["BIPOLAR"]: - # use binary for bipolar storage - dtype = DataType["BINARY"] - elem_bits = dtype.bitwidth() - packed_bits = self.get_instream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_in = "%s/input_0.npy" % code_gen_dir - self.code_gen_dict["$READNPYDATA$"] = [] - self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - npy_in, - self.hls_sname(), - ) - ) - def strm_decl(self): self.code_gen_dict["$STREAMDECLARATIONS$"] = [] self.code_gen_dict["$STREAMDECLARATIONS$"].append( @@ -157,9 +132,6 @@ def dataoutstrm(self): ) ] - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - def blackboxfunction(self): packed_bits = self.get_instream_width() packed_hls_type = "ap_uint<%d>" % packed_bits @@ -174,15 +146,6 @@ def blackboxfunction(self): ) ] - def pragmas(self): - self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() - ] - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() - ) - self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") - def execute_node(self, context, graph): mode = self.get_nodeattr("exec_mode") node = self.onnx_node diff --git a/src/finn/custom_op/fpgadataflow/hlsbackend.py b/src/finn/custom_op/fpgadataflow/hlsbackend.py index 403b992a05..f5fd8a1094 100644 --- a/src/finn/custom_op/fpgadataflow/hlsbackend.py +++ b/src/finn/custom_op/fpgadataflow/hlsbackend.py @@ -363,11 +363,32 @@ def defines(self, var): added.""" pass - @abstractmethod def read_npy_data(self): """Function to generate the commands for reading data from .npy file in c++, - is member function of HLSBackend class but has to be filled by every node.""" - pass + might need to be overwritten depending on custom op.""" + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_input_datatype() + if dtype == DataType["BIPOLAR"]: + # use binary for bipolar storage + dtype = DataType["BINARY"] + elem_bits = dtype.bitwidth() + packed_bits = self.get_instream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "float" + npy_in = "%s/input_0.npy" % code_gen_dir + self.code_gen_dict["$READNPYDATA$"] = [] + self.code_gen_dict["$READNPYDATA$"].append( + 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) + ) @abstractmethod def strm_decl(self): @@ -390,11 +411,9 @@ def dataoutstrm(self): by every node.""" pass - @abstractmethod def save_as_npy(self): - """Function to generate the commands for saving data in .npy file in c++, - is member function of HLSBackend class but has to be filled by every node.""" - pass + """Function to generate the commands for saving data in .npy file in c++""" + self.code_gen_dict["$SAVEASCNPY$"] = [] @abstractmethod def blackboxfunction(self): @@ -403,11 +422,16 @@ def blackboxfunction(self): by every node.""" pass - @abstractmethod def pragmas(self): - """Function to generate the pragma commands in c++, is member function of - HLSBackend class but has to be filled by every node.""" - pass + """Function to generate the pragma commands in c++, + might need to be overwritten depending on custom op.""" + self.code_gen_dict["$PRAGMAS$"] = [ + "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() + ] + self.code_gen_dict["$PRAGMAS$"].append( + "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() + ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") def get_ap_int_max_w(self): """Return the maximum width of any ap_int used in this module. Used to set the diff --git a/src/finn/custom_op/fpgadataflow/streamingfifo.py b/src/finn/custom_op/fpgadataflow/streamingfifo.py index 950574ba0a..b55af929ed 100644 --- a/src/finn/custom_op/fpgadataflow/streamingfifo.py +++ b/src/finn/custom_op/fpgadataflow/streamingfifo.py @@ -45,6 +45,8 @@ def get_nodeattr_types(self): "depth": ("i", True, 0), # folded shape of input/output "folded_shape": ("ints", True, []), + # normal shape of input/output + "normal_shape": ("ints", True, []), # FINN DataTypes for inputs/outputs "dataType": ("s", True, ""), # FPGA resource type for FIFOs when impl_style is vivado @@ -105,27 +107,7 @@ def get_normal_input_shape(self, ind=0): assert depth >= 2, """Depth is too low""" if depth > 256 and self.get_nodeattr("impl_style") == "rtl": warnings.warn("Depth is high, set between 2 and 256 for efficient SRL implementation") - # derive normal shape from folded shape - # StreamingFIFOs are inserted in between fpgadataflow nodes - # the folded shape could be for example (1, nf, pe) - # with nf (neuron folding): mh // pe - # the normal input shape is in this case (1, mh) - # so to achieve this the two inner dimensions are multiplied - # and together with all previous dimensions - # this gives the normal input shape - - folded_shape = self.get_nodeattr("folded_shape") - # extract inner dimension - inner_dim = folded_shape[-1] - # multiply with the next inner dimension - folding_factor = folded_shape[-2] * inner_dim - normal_ishape = [] - # create the normal_ishape - for i in range(len(folded_shape) - 2): - normal_ishape.append(folded_shape[i]) - normal_ishape.append(folding_factor) - - return normal_ishape + return self.get_nodeattr("normal_shape") def get_normal_output_shape(self, ind=0): return self.get_normal_input_shape() diff --git a/src/finn/transformation/fpgadataflow/insert_fifo.py b/src/finn/transformation/fpgadataflow/insert_fifo.py index de555d4101..4efadf0f27 100644 --- a/src/finn/transformation/fpgadataflow/insert_fifo.py +++ b/src/finn/transformation/fpgadataflow/insert_fifo.py @@ -127,6 +127,7 @@ def apply(self, model): folded output shape of the first node is not the same as the folded output shape of the second node. A streaming fifo can't be implemented in between these nodes.""" + n_shape = n0.get_normal_output_shape() # check if outFIFOdepths attribute of first node # and inFIFOdepths attribute of consumer node is equal @@ -162,6 +163,7 @@ def apply(self, model): backend="fpgadataflow", depth=fifo_depth, folded_shape=fld_shape, + normal_shape=n_shape, dataType=str(dtype.name), impl_style=impl_style, ram_style=self.vivado_ram_style, @@ -188,6 +190,7 @@ def apply(self, model): n0 = getCustomOp(first_node) # determine fifo node attributes fld_shape = n0.get_folded_input_shape(inp_ind) + n_shape = n0.get_normal_input_shape(inp_ind) dtype = n0.get_input_datatype(inp_ind) fifo_depth = n0.get_nodeattr("inFIFODepths")[inp_ind] @@ -196,7 +199,7 @@ def apply(self, model): fifo_output_tensor = oh.make_tensor_value_info( model.make_new_valueinfo_name(), TensorProto.FLOAT, - n0.get_normal_input_shape(), + n0.get_normal_input_shape(inp_ind), ) graph.value_info.append(fifo_output_tensor) model.set_tensor_datatype(fifo_output_tensor.name, dtype) @@ -213,6 +216,7 @@ def apply(self, model): backend="fpgadataflow", depth=fifo_depth, folded_shape=fld_shape, + normal_shape=n_shape, dataType=str(dtype.name), impl_style=impl_style, ram_style=self.vivado_ram_style, @@ -243,6 +247,7 @@ def apply(self, model): out_ind = list(final_node.output).index(graph_out_name) # determine fifo node attributes fld_shape = n0.get_folded_output_shape(out_ind) + n_shape = n0.get_normal_output_shape(out_ind) dtype = n0.get_output_datatype(out_ind) fifo_depth = n0.get_nodeattr("outFIFODepths")[out_ind] @@ -268,6 +273,7 @@ def apply(self, model): backend="fpgadataflow", depth=fifo_depth, folded_shape=fld_shape, + normal_shape=n_shape, dataType=str(dtype.name), impl_style=impl_style, ram_style=self.vivado_ram_style, diff --git a/src/finn/transformation/fpgadataflow/set_fifo_depths.py b/src/finn/transformation/fpgadataflow/set_fifo_depths.py index 72b5e495a4..11ffc965b6 100644 --- a/src/finn/transformation/fpgadataflow/set_fifo_depths.py +++ b/src/finn/transformation/fpgadataflow/set_fifo_depths.py @@ -568,6 +568,7 @@ def apply(self, model): cfgs = get_fifo_split_configs(depth, self.max_qsrl_depth, self.max_vivado_depth) if len(cfgs) > 1: fld_shape = n_inst.get_folded_output_shape() + n_shape = n_inst.get_normal_output_shape() dtype = n_inst.get_nodeattr("dataType") ram_style = n_inst.get_nodeattr("ram_style") shape = model.get_tensor_shape(node.input[0]) @@ -593,6 +594,7 @@ def apply(self, model): backend="fpgadataflow", depth=fifo_depth, folded_shape=fld_shape, + normal_shape=n_shape, dataType=dtype, impl_style=impl_style, ram_style=ram_style, diff --git a/tests/fpgadataflow/test_fpgadataflow_checksum.py b/tests/fpgadataflow/test_fpgadataflow_checksum.py index 5cdd99f1e4..71d4d60c06 100644 --- a/tests/fpgadataflow/test_fpgadataflow_checksum.py +++ b/tests/fpgadataflow/test_fpgadataflow_checksum.py @@ -49,6 +49,7 @@ from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers test_fpga_part = "xczu3eg-sbva484-1-e" target_clk_ns = 5 @@ -175,6 +176,7 @@ def test_fpgadataflow_checksum(): # rtlsim model = model.transform(InsertFIFO(True)) + model = model.transform(SpecializeLayers()) model = model.transform(GiveUniqueNodeNames()) model = model.transform(PrepareIP(test_fpga_part, target_clk_ns)) model = model.transform(HLSSynthIP()) diff --git a/tests/fpgadataflow/test_fpgadataflow_concat.py b/tests/fpgadataflow/test_fpgadataflow_concat.py index b4d8a04a95..b52b14fca3 100644 --- a/tests/fpgadataflow/test_fpgadataflow_concat.py +++ b/tests/fpgadataflow/test_fpgadataflow_concat.py @@ -145,6 +145,7 @@ def test_fpgadataflow_concat_stitchedip(): assert model.graph.node[0].op_type == "StreamingConcat_hls" assert model.graph.node[0].domain == "finn.custom_op.fpgadataflow.hls" model = model.transform(InsertFIFO(create_shallow_fifos=True)) + model = model.transform(SpecializeLayers()) model = model.transform(GiveUniqueNodeNames()) model = model.transform(PrepareIP(fpga_part, clk_ns)) model = model.transform(HLSSynthIP()) From 8416358ffd78c15e745cfa9d57180b8dccf58099 Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 30 Jan 2024 17:17:55 +0000 Subject: [PATCH 432/665] [CustomOp] Move stream declaration for hls code into hlsbackend --- .../fpgadataflow/hls/channelwise_op_hls.py | 13 ------------- .../hls/convolutioninputgenerator_hls.py | 13 ------------- .../custom_op/fpgadataflow/hls/downsampler_hls.py | 13 ------------- .../custom_op/fpgadataflow/hls/fmpadding_hls.py | 13 ------------- .../fpgadataflow/hls/fmpadding_pixel_hls.py | 13 ------------- .../custom_op/fpgadataflow/hls/globalaccpool_hls.py | 13 ------------- src/finn/custom_op/fpgadataflow/hls/iodma_hls.py | 3 --- .../custom_op/fpgadataflow/hls/labelselect_hls.py | 13 ------------- src/finn/custom_op/fpgadataflow/hls/lookup_hls.py | 13 ------------- src/finn/custom_op/fpgadataflow/hls/pool_hls.py | 13 ------------- .../fpgadataflow/hls/streamingmaxpool_hls.py | 13 ------------- .../custom_op/fpgadataflow/hls/upsampler_hls.py | 13 ------------- src/finn/custom_op/fpgadataflow/hlsbackend.py | 13 +++++++++++-- 13 files changed, 11 insertions(+), 148 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/hls/channelwise_op_hls.py b/src/finn/custom_op/fpgadataflow/hls/channelwise_op_hls.py index a698acfe49..14efa113dd 100644 --- a/src/finn/custom_op/fpgadataflow/hls/channelwise_op_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/channelwise_op_hls.py @@ -344,19 +344,6 @@ def read_npy_data(self): ) ) - def strm_decl(self): - self.code_gen_dict["$STREAMDECLARATIONS$"] = [] - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0_{} ("in0_{}");'.format( - self.get_instream_width(), self.hls_sname(), self.hls_sname() - ) - ) - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out_{} ("out_{}");'.format( - self.get_outstream_width(), self.hls_sname(), self.hls_sname() - ) - ) - def docompute(self): tmpl_args = self.get_template_param_values() # TODO: why put some template parameters into defines and not others? diff --git a/src/finn/custom_op/fpgadataflow/hls/convolutioninputgenerator_hls.py b/src/finn/custom_op/fpgadataflow/hls/convolutioninputgenerator_hls.py index 5e0dbfd396..585f152550 100644 --- a/src/finn/custom_op/fpgadataflow/hls/convolutioninputgenerator_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/convolutioninputgenerator_hls.py @@ -526,19 +526,6 @@ def defines(self, var): ) ] - def strm_decl(self): - self.code_gen_dict["$STREAMDECLARATIONS$"] = [] - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0_{} ("in0_{}");'.format( - self.get_instream_width(), self.hls_sname(), self.hls_sname() - ) - ) - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out_{} ("out_{}");'.format( - self.get_outstream_width(), self.hls_sname(), self.hls_sname() - ) - ) - def docompute(self): ram_style = self.get_nodeattr("ram_style") map_to_hls_ram_style = { diff --git a/src/finn/custom_op/fpgadataflow/hls/downsampler_hls.py b/src/finn/custom_op/fpgadataflow/hls/downsampler_hls.py index ff9a83d091..71db77ef6c 100644 --- a/src/finn/custom_op/fpgadataflow/hls/downsampler_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/downsampler_hls.py @@ -72,19 +72,6 @@ def defines(self, var): batch_size = self.get_nodeattr("numInputVectors") self.code_gen_dict["$DEFINES$"] += ["#define numReps {}".format(batch_size)] - def strm_decl(self): - self.code_gen_dict["$STREAMDECLARATIONS$"] = [] - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0_{} ("in0_{}");'.format( - self.get_instream_width(), self.hls_sname(), self.hls_sname() - ) - ) - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out_{} ("out_{}");'.format( - self.get_outstream_width(), self.hls_sname(), self.hls_sname() - ) - ) - def docompute(self): dim_var = "1D" if (self.get_nodeattr("is1D") == 1) else "2D" sname = self.hls_sname() diff --git a/src/finn/custom_op/fpgadataflow/hls/fmpadding_hls.py b/src/finn/custom_op/fpgadataflow/hls/fmpadding_hls.py index d21b672b73..b7ad5b1120 100644 --- a/src/finn/custom_op/fpgadataflow/hls/fmpadding_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/fmpadding_hls.py @@ -100,19 +100,6 @@ def defines(self, var): ) ] - def strm_decl(self): - self.code_gen_dict["$STREAMDECLARATIONS$"] = [] - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0_{} ("in0_{}");'.format( - self.get_instream_width(), self.hls_sname(), self.hls_sname() - ) - ) - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out_{} ("out_{}");'.format( - self.get_outstream_width(), self.hls_sname(), self.hls_sname() - ) - ) - def docompute(self): in_t = self.get_input_datatype().get_hls_datatype_str() idim_h, idim_w = self.get_nodeattr("ImgDim") diff --git a/src/finn/custom_op/fpgadataflow/hls/fmpadding_pixel_hls.py b/src/finn/custom_op/fpgadataflow/hls/fmpadding_pixel_hls.py index 62942c4f28..8ce9f79a6e 100644 --- a/src/finn/custom_op/fpgadataflow/hls/fmpadding_pixel_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/fmpadding_pixel_hls.py @@ -70,19 +70,6 @@ def defines(self, var): ) ] - def strm_decl(self): - self.code_gen_dict["$STREAMDECLARATIONS$"] = [] - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0_{} ("in0_{}");'.format( - self.get_instream_width(), self.hls_sname(), self.hls_sname() - ) - ) - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out_{} ("out_{}");'.format( - self.get_outstream_width(), self.hls_sname(), self.hls_sname() - ) - ) - def docompute(self): in_t = self.get_input_datatype().get_hls_datatype_str() odim_h, odim_w = self.get_padded_odim() diff --git a/src/finn/custom_op/fpgadataflow/hls/globalaccpool_hls.py b/src/finn/custom_op/fpgadataflow/hls/globalaccpool_hls.py index 8df18e8b8a..657528be7c 100644 --- a/src/finn/custom_op/fpgadataflow/hls/globalaccpool_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/globalaccpool_hls.py @@ -150,19 +150,6 @@ def global_includes(self): def defines(self, var): self.code_gen_dict["$DEFINES$"] = [] - def strm_decl(self): - self.code_gen_dict["$STREAMDECLARATIONS$"] = [] - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0_{} ("in0_{}");'.format( - self.get_instream_width(), self.hls_sname(), self.hls_sname() - ) - ) - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out_{} ("out_{}");'.format( - self.get_outstream_width(), self.hls_sname(), self.hls_sname() - ) - ) - def docompute(self): self.code_gen_dict["$DOCOMPUTE$"] = [ """AccPool_Batch<{}, {}, {}, {}, {}> (in0_{}, out_{}, 1);""".format( diff --git a/src/finn/custom_op/fpgadataflow/hls/iodma_hls.py b/src/finn/custom_op/fpgadataflow/hls/iodma_hls.py index bdc313f592..9644ab2098 100644 --- a/src/finn/custom_op/fpgadataflow/hls/iodma_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/iodma_hls.py @@ -413,9 +413,6 @@ def execute_node(self, context, graph): def dataoutstrm(self): pass - def strm_decl(self): - pass - def get_verilog_top_module_intf_names(self): intf_names = super().get_verilog_top_module_intf_names() if self.get_nodeattr("direction") == "out": diff --git a/src/finn/custom_op/fpgadataflow/hls/labelselect_hls.py b/src/finn/custom_op/fpgadataflow/hls/labelselect_hls.py index cce45eb742..634d9de55a 100644 --- a/src/finn/custom_op/fpgadataflow/hls/labelselect_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/labelselect_hls.py @@ -185,19 +185,6 @@ def read_npy_data(self): ) ) - def strm_decl(self): - self.code_gen_dict["$STREAMDECLARATIONS$"] = [] - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0_{} ("in0_{}");'.format( - self.get_instream_width(), self.hls_sname(), self.hls_sname() - ) - ) - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out_{} ("out_{}");'.format( - self.get_outstream_width(), self.hls_sname(), self.hls_sname() - ) - ) - def docompute(self): self.code_gen_dict["$DOCOMPUTE$"] = [ """LabelSelect_Batch<{}, {}, {}, {}, {} > (in0_{}, out_{}, 1);""".format( diff --git a/src/finn/custom_op/fpgadataflow/hls/lookup_hls.py b/src/finn/custom_op/fpgadataflow/hls/lookup_hls.py index e51db9a811..feeca8719b 100644 --- a/src/finn/custom_op/fpgadataflow/hls/lookup_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/lookup_hls.py @@ -141,19 +141,6 @@ def dataoutstrm(self): ) ] - def strm_decl(self): - self.code_gen_dict["$STREAMDECLARATIONS$"] = [] - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0_{} ("in0_{}");'.format( - self.get_instream_width(), self.hls_sname(), self.hls_sname() - ) - ) - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out_{} ("out_{}");'.format( - self.get_outstream_width(), self.hls_sname(), self.hls_sname() - ) - ) - def docompute(self): mem_mode = self.get_nodeattr("mem_mode") if mem_mode == "const": diff --git a/src/finn/custom_op/fpgadataflow/hls/pool_hls.py b/src/finn/custom_op/fpgadataflow/hls/pool_hls.py index 05bb8fbd74..64c6ec33f8 100644 --- a/src/finn/custom_op/fpgadataflow/hls/pool_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/pool_hls.py @@ -110,19 +110,6 @@ def read_npy_data(self): ) ) - def strm_decl(self): - self.code_gen_dict["$STREAMDECLARATIONS$"] = [] - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0_{} ("in0_{}");'.format( - self.get_instream_width(), self.hls_sname(), self.hls_sname() - ) - ) - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out_{} ("out_{}");'.format( - self.get_outstream_width(), self.hls_sname(), self.hls_sname() - ) - ) - def docompute(self): idt = self.get_input_datatype() i_hls_dt = idt.get_hls_datatype_str() diff --git a/src/finn/custom_op/fpgadataflow/hls/streamingmaxpool_hls.py b/src/finn/custom_op/fpgadataflow/hls/streamingmaxpool_hls.py index b742e1f73b..61c9ef3a3e 100755 --- a/src/finn/custom_op/fpgadataflow/hls/streamingmaxpool_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/streamingmaxpool_hls.py @@ -95,19 +95,6 @@ def defines(self, var): ) ] - def strm_decl(self): - self.code_gen_dict["$STREAMDECLARATIONS$"] = [] - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0_{} ("in0_{}");'.format( - self.get_instream_width(), self.hls_sname(), self.hls_sname() - ) - ) - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out_{} ("out_{}");'.format( - self.get_outstream_width(), self.hls_sname(), self.hls_sname() - ) - ) - def docompute(self): dtype = self.get_input_datatype() if dtype.bitwidth() == 1: diff --git a/src/finn/custom_op/fpgadataflow/hls/upsampler_hls.py b/src/finn/custom_op/fpgadataflow/hls/upsampler_hls.py index e52081edf2..f57d3f7237 100644 --- a/src/finn/custom_op/fpgadataflow/hls/upsampler_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/upsampler_hls.py @@ -74,19 +74,6 @@ def defines(self, var): batch_size = self.get_nodeattr("numInputVectors") self.code_gen_dict["$DEFINES$"] += ["#define numReps {}".format(batch_size)] - def strm_decl(self): - self.code_gen_dict["$STREAMDECLARATIONS$"] = [] - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0_{} ("in0_{}");'.format( - self.get_instream_width(), self.hls_sname(), self.hls_sname() - ) - ) - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out_{} ("out_{}");'.format( - self.get_outstream_width(), self.hls_sname(), self.hls_sname() - ) - ) - def docompute(self): is_2d = self.get_nodeattr("DimMode") == 0 batch = self.get_nodeattr("numInputVectors") diff --git a/src/finn/custom_op/fpgadataflow/hlsbackend.py b/src/finn/custom_op/fpgadataflow/hlsbackend.py index f5fd8a1094..0324b66f47 100644 --- a/src/finn/custom_op/fpgadataflow/hlsbackend.py +++ b/src/finn/custom_op/fpgadataflow/hlsbackend.py @@ -390,12 +390,21 @@ def read_npy_data(self): ) ) - @abstractmethod def strm_decl(self): """Function to generate the commands for the stream declaration in c++, is member function of HLSBackend class but has to be filled by every node.""" - pass + self.code_gen_dict["$STREAMDECLARATIONS$"] = [] + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> in0_{} ("in0_{}");'.format( + self.get_instream_width(), self.hls_sname(), self.hls_sname() + ) + ) + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> out_{} ("out_{}");'.format( + self.get_outstream_width(), self.hls_sname(), self.hls_sname() + ) + ) @abstractmethod def docompute(self): From 3a0da243b022ab021174e61b04834211b998e09d Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 30 Jan 2024 17:44:43 +0000 Subject: [PATCH 433/665] [CustomOp] Move dataout cpp function to hlsbackend --- .../fpgadataflow/hls/addstreams_hls.py | 25 ------------- .../custom_op/fpgadataflow/hls/concat_hls.py | 25 ------------- .../fpgadataflow/hls/downsampler_hls.py | 29 --------------- .../fpgadataflow/hls/fmpadding_hls.py | 29 --------------- .../fpgadataflow/hls/fmpadding_pixel_hls.py | 29 --------------- .../fpgadataflow/hls/globalaccpool_hls.py | 25 ------------- .../custom_op/fpgadataflow/hls/iodma_hls.py | 3 -- .../fpgadataflow/hls/labelselect_hls.py | 25 ------------- .../hls/streamingdatawidthconverter_hls.py | 28 --------------- .../fpgadataflow/hls/streamingeltwise_hls.py | 25 ------------- .../fpgadataflow/hls/streamingmaxpool_hls.py | 28 --------------- .../fpgadataflow/hls/upsampler_hls.py | 29 --------------- src/finn/custom_op/fpgadataflow/hlsbackend.py | 36 +++++++++++++++---- 13 files changed, 30 insertions(+), 306 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/hls/addstreams_hls.py b/src/finn/custom_op/fpgadataflow/hls/addstreams_hls.py index 4f7b58d8e1..a3f0e043f8 100644 --- a/src/finn/custom_op/fpgadataflow/hls/addstreams_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/addstreams_hls.py @@ -226,31 +226,6 @@ def docompute(self): ) ] - def dataoutstrm(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_output_datatype() - elem_bits = dtype.bitwidth() - packed_bits = self.get_outstream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_out = "%s/output.npy" % code_gen_dir - oshape = self.get_folded_output_shape() - oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") - - self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - self.hls_sname(), - oshape_cpp_str, - npy_out, - ) - ] - def blackboxfunction(self): self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ """void {}(hls::stream> &in0_{}, hls::stream> &in1_{}, diff --git a/src/finn/custom_op/fpgadataflow/hls/concat_hls.py b/src/finn/custom_op/fpgadataflow/hls/concat_hls.py index 94e0c3626c..008fa9cee8 100644 --- a/src/finn/custom_op/fpgadataflow/hls/concat_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/concat_hls.py @@ -240,31 +240,6 @@ def docompute(self): ) self.code_gen_dict["$DOCOMPUTE$"] = [comp_call] - def dataoutstrm(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_output_datatype() - elem_bits = dtype.bitwidth() - packed_bits = self.get_outstream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_out = "%s/output.npy" % code_gen_dir - oshape = self.get_folded_output_shape() - oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") - - self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - self.hls_sname(), - oshape_cpp_str, - npy_out, - ) - ] - def blackboxfunction(self): n_inputs = self.get_n_inputs() in_streams = [] diff --git a/src/finn/custom_op/fpgadataflow/hls/downsampler_hls.py b/src/finn/custom_op/fpgadataflow/hls/downsampler_hls.py index 71db77ef6c..56f472b9c0 100644 --- a/src/finn/custom_op/fpgadataflow/hls/downsampler_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/downsampler_hls.py @@ -28,7 +28,6 @@ import numpy as np import os -from qonnx.core.datatype import DataType from finn.custom_op.fpgadataflow.downsampler import DownSampler from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend @@ -80,34 +79,6 @@ def docompute(self): IFMDim, SIMD,Stride> (in0_{sname}, out_{sname}, numReps);""" ] - def dataoutstrm(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_output_datatype() - if dtype == DataType["BIPOLAR"]: - # use binary for bipolar storage - dtype = DataType["BINARY"] - elem_bits = dtype.bitwidth() - packed_bits = self.get_outstream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_out = "%s/output.npy" % code_gen_dir - oshape = self.get_folded_output_shape() - oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") - - self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - self.hls_sname(), - oshape_cpp_str, - npy_out, - ) - ] - def blackboxfunction(self): packed_bits = self.get_instream_width() packed_hls_type = "ap_uint<%d>" % packed_bits diff --git a/src/finn/custom_op/fpgadataflow/hls/fmpadding_hls.py b/src/finn/custom_op/fpgadataflow/hls/fmpadding_hls.py index b7ad5b1120..d57699af05 100644 --- a/src/finn/custom_op/fpgadataflow/hls/fmpadding_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/fmpadding_hls.py @@ -28,7 +28,6 @@ import numpy as np import os -from qonnx.core.datatype import DataType from finn.custom_op.fpgadataflow.fmpadding import FMPadding from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend @@ -127,34 +126,6 @@ def docompute(self): ) ] - def dataoutstrm(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_output_datatype() - if dtype == DataType["BIPOLAR"]: - # use binary for bipolar storage - dtype = DataType["BINARY"] - elem_bits = dtype.bitwidth() - packed_bits = self.get_outstream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_out = "%s/output.npy" % code_gen_dir - oshape = self.get_folded_output_shape() - oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") - - self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - self.hls_sname(), - oshape_cpp_str, - npy_out, - ) - ] - def blackboxfunction(self): packed_bits = self.get_instream_width() packed_hls_type = "ap_uint<%d>" % packed_bits diff --git a/src/finn/custom_op/fpgadataflow/hls/fmpadding_pixel_hls.py b/src/finn/custom_op/fpgadataflow/hls/fmpadding_pixel_hls.py index 8ce9f79a6e..b7ba301fbc 100644 --- a/src/finn/custom_op/fpgadataflow/hls/fmpadding_pixel_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/fmpadding_pixel_hls.py @@ -29,7 +29,6 @@ import numpy as np import os -from qonnx.core.datatype import DataType from finn.custom_op.fpgadataflow.fmpadding_pixel import FMPadding_Pixel from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend @@ -82,34 +81,6 @@ def docompute(self): ) ] - def dataoutstrm(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_output_datatype() - if dtype == DataType["BIPOLAR"]: - # use binary for bipolar storage - dtype = DataType["BINARY"] - elem_bits = dtype.bitwidth() - packed_bits = self.get_outstream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_out = "%s/output.npy" % code_gen_dir - oshape = self.get_folded_output_shape() - oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") - - self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - self.hls_sname(), - oshape_cpp_str, - npy_out, - ) - ] - def blackboxfunction(self): packed_bits = self.get_instream_width() packed_hls_type = "ap_uint<%d>" % packed_bits diff --git a/src/finn/custom_op/fpgadataflow/hls/globalaccpool_hls.py b/src/finn/custom_op/fpgadataflow/hls/globalaccpool_hls.py index 657528be7c..9b2a7b25b0 100644 --- a/src/finn/custom_op/fpgadataflow/hls/globalaccpool_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/globalaccpool_hls.py @@ -163,31 +163,6 @@ def docompute(self): ) ] - def dataoutstrm(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_output_datatype() - elem_bits = dtype.bitwidth() - packed_bits = self.get_outstream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_out = "%s/output.npy" % code_gen_dir - oshape = self.get_folded_output_shape() - oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") - - self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - self.hls_sname(), - oshape_cpp_str, - npy_out, - ) - ] - def blackboxfunction(self): self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ """void {}(hls::stream> &in0_{}, diff --git a/src/finn/custom_op/fpgadataflow/hls/iodma_hls.py b/src/finn/custom_op/fpgadataflow/hls/iodma_hls.py index 9644ab2098..8d9903f0f5 100644 --- a/src/finn/custom_op/fpgadataflow/hls/iodma_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/iodma_hls.py @@ -410,9 +410,6 @@ def pragmas(self): def execute_node(self, context, graph): pass - def dataoutstrm(self): - pass - def get_verilog_top_module_intf_names(self): intf_names = super().get_verilog_top_module_intf_names() if self.get_nodeattr("direction") == "out": diff --git a/src/finn/custom_op/fpgadataflow/hls/labelselect_hls.py b/src/finn/custom_op/fpgadataflow/hls/labelselect_hls.py index 634d9de55a..1e2c0d034a 100644 --- a/src/finn/custom_op/fpgadataflow/hls/labelselect_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/labelselect_hls.py @@ -198,31 +198,6 @@ def docompute(self): ) ] - def dataoutstrm(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_output_datatype() - elem_bits = dtype.bitwidth() - packed_bits = self.get_outstream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_out = "%s/output.npy" % code_gen_dir - oshape = self.get_folded_output_shape() - oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") - - self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - self.hls_sname(), - oshape_cpp_str, - npy_out, - ) - ] - def blackboxfunction(self): self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ """void {}(hls::stream> &in0_{}, diff --git a/src/finn/custom_op/fpgadataflow/hls/streamingdatawidthconverter_hls.py b/src/finn/custom_op/fpgadataflow/hls/streamingdatawidthconverter_hls.py index 7b656a0120..d1f58d3e87 100644 --- a/src/finn/custom_op/fpgadataflow/hls/streamingdatawidthconverter_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/streamingdatawidthconverter_hls.py @@ -109,34 +109,6 @@ def docompute(self): % (op, self.hls_sname(), self.hls_sname()) ] - def dataoutstrm(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_output_datatype() - if dtype == DataType["BIPOLAR"]: - # use binary for bipolar storage - dtype = DataType["BINARY"] - elem_bits = dtype.bitwidth() - packed_bits = self.get_outstream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_out = "%s/output.npy" % code_gen_dir - oshape = self.get_folded_output_shape() - oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") - - self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - self.hls_sname(), - oshape_cpp_str, - npy_out, - ) - ] - def blackboxfunction(self): in_packed_bits = self.get_instream_width() in_packed_hls_type = "ap_uint<%d>" % in_packed_bits diff --git a/src/finn/custom_op/fpgadataflow/hls/streamingeltwise_hls.py b/src/finn/custom_op/fpgadataflow/hls/streamingeltwise_hls.py index 8528986d89..0d618d832a 100644 --- a/src/finn/custom_op/fpgadataflow/hls/streamingeltwise_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/streamingeltwise_hls.py @@ -281,31 +281,6 @@ def docompute(self): ) ] - def dataoutstrm(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_output_datatype() - elem_bits = dtype.bitwidth() - packed_bits = self.get_outstream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_out = "%s/output.npy" % code_gen_dir - oshape = self.get_folded_output_shape() - oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") - - self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - self.hls_sname(), - oshape_cpp_str, - npy_out, - ) - ] - def blackboxfunction(self): self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ """void {}(hls::stream> &in0_{}, hls::stream> &in1_{}, diff --git a/src/finn/custom_op/fpgadataflow/hls/streamingmaxpool_hls.py b/src/finn/custom_op/fpgadataflow/hls/streamingmaxpool_hls.py index 61c9ef3a3e..69db7b4606 100755 --- a/src/finn/custom_op/fpgadataflow/hls/streamingmaxpool_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/streamingmaxpool_hls.py @@ -124,34 +124,6 @@ def docompute(self): % (op, dtype_hls, minval_str, self.hls_sname(), self.hls_sname()) ] - def dataoutstrm(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_output_datatype() - if dtype == DataType["BIPOLAR"]: - # use binary for bipolar storage - dtype = DataType["BINARY"] - elem_bits = dtype.bitwidth() - packed_bits = self.get_outstream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_out = "%s/output.npy" % code_gen_dir - oshape = self.get_folded_output_shape() - oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") - - self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - self.hls_sname(), - oshape_cpp_str, - npy_out, - ) - ] - def blackboxfunction(self): packed_bits = self.get_instream_width() packed_hls_type = "ap_uint<%d>" % packed_bits diff --git a/src/finn/custom_op/fpgadataflow/hls/upsampler_hls.py b/src/finn/custom_op/fpgadataflow/hls/upsampler_hls.py index f57d3f7237..05d26eddb2 100644 --- a/src/finn/custom_op/fpgadataflow/hls/upsampler_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/upsampler_hls.py @@ -27,7 +27,6 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import numpy as np -from qonnx.core.datatype import DataType from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend from finn.custom_op.fpgadataflow.upsampler import UpsampleNearestNeighbour @@ -91,34 +90,6 @@ def docompute(self): % (self.hls_sname(), self.hls_sname()) ] - def dataoutstrm(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_output_datatype() - if dtype == DataType["BIPOLAR"]: - # use binary for bipolar storage - dtype = DataType["BINARY"] - elem_bits = dtype.bitwidth() - packed_bits = self.get_outstream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_out = "%s/output.npy" % code_gen_dir - oshape = self.get_folded_output_shape() - oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") - - self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - self.hls_sname(), - oshape_cpp_str, - npy_out, - ) - ] - def blackboxfunction(self): packed_bits = self.get_instream_width() packed_hls_type = "ap_uint<%d>" % packed_bits diff --git a/src/finn/custom_op/fpgadataflow/hlsbackend.py b/src/finn/custom_op/fpgadataflow/hlsbackend.py index 0324b66f47..846894d85c 100644 --- a/src/finn/custom_op/fpgadataflow/hlsbackend.py +++ b/src/finn/custom_op/fpgadataflow/hlsbackend.py @@ -392,8 +392,8 @@ def read_npy_data(self): def strm_decl(self): """Function to generate the commands for the stream declaration in c++, - is member function of HLSBackend class but has to be filled - by every node.""" + is member function of HLSBackend class but might need to be filled + by node.""" self.code_gen_dict["$STREAMDECLARATIONS$"] = [] self.code_gen_dict["$STREAMDECLARATIONS$"].append( 'hls::stream> in0_{} ("in0_{}");'.format( @@ -413,12 +413,36 @@ def docompute(self): by every node.""" pass - @abstractmethod def dataoutstrm(self): """Function to generate the commands for reading out data from c++ and convert - into npy format, is member function of HLSBackend class but has to be filled - by every node.""" - pass + into npy format, is member function of HLSBackend class might need to be filled + by node.""" + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_output_datatype() + if dtype == DataType["BIPOLAR"]: + # use binary for bipolar storage + dtype = DataType["BINARY"] + elem_bits = dtype.bitwidth() + packed_bits = self.get_outstream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "float" + npy_out = "%s/output.npy" % code_gen_dir + oshape = self.get_folded_output_shape() + oshape_cpp_str = str(oshape).replace("(", "{").replace(")", "}") + + self.code_gen_dict["$DATAOUTSTREAM$"] = [ + 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s");' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + self.hls_sname(), + oshape_cpp_str, + npy_out, + ) + ] def save_as_npy(self): """Function to generate the commands for saving data in .npy file in c++""" From bf5de4d00d6a1a8cfa9055f33a37d3a86f62f0e7 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Tue, 30 Jan 2024 19:13:59 +0000 Subject: [PATCH 434/665] Revert "[TBS] Clean up branch for HLS variant only" This reverts commit ac1478dac5774ec5d4e599213e37b19ca0ab8967. --- finn-rtllib/thresholding/component.xml | 1002 +++++++++++++++++ .../gui/thresholding_axi_v1_0.gtcl | 4 + finn-rtllib/thresholding/hdl/axilite_if.v | 210 ++++ finn-rtllib/thresholding/hdl/thresholding.sv | 357 ++++++ .../thresholding/hdl/thresholding_axi.sv | 164 +++ .../hdl/thresholding_template_wrapper.v | 120 ++ finn-rtllib/thresholding/sim/thresh_gen.sv | 45 + finn-rtllib/thresholding/sim/thresholding.tcl | 17 + .../thresholding/sim/thresholding_axi_tb.sv | 314 ++++++ .../thresholding/sim/thresholding_tb.sv | 274 +++++ .../xgui/thresholding_axi_v1_0.tcl | 187 +++ src/finn/util/basic.py | 70 ++ tests/util/test_basic.py | 60 + 13 files changed, 2824 insertions(+) create mode 100644 finn-rtllib/thresholding/component.xml create mode 100644 finn-rtllib/thresholding/gui/thresholding_axi_v1_0.gtcl create mode 100644 finn-rtllib/thresholding/hdl/axilite_if.v create mode 100644 finn-rtllib/thresholding/hdl/thresholding.sv create mode 100644 finn-rtllib/thresholding/hdl/thresholding_axi.sv create mode 100644 finn-rtllib/thresholding/hdl/thresholding_template_wrapper.v create mode 100644 finn-rtllib/thresholding/sim/thresh_gen.sv create mode 100644 finn-rtllib/thresholding/sim/thresholding.tcl create mode 100644 finn-rtllib/thresholding/sim/thresholding_axi_tb.sv create mode 100644 finn-rtllib/thresholding/sim/thresholding_tb.sv create mode 100644 finn-rtllib/thresholding/xgui/thresholding_axi_v1_0.tcl create mode 100755 tests/util/test_basic.py diff --git a/finn-rtllib/thresholding/component.xml b/finn-rtllib/thresholding/component.xml new file mode 100644 index 0000000000..e28a3a2c2d --- /dev/null +++ b/finn-rtllib/thresholding/component.xml @@ -0,0 +1,1002 @@ + + + amd.com + finn + thresholding_axi + 1.0 + + + ap_clk + + + + + + + CLK + + + ap_clk + + + + + + ASSOCIATED_RESET + ap_rst_n + + + ASSOCIATED_BUSIF + s_axilite:s_axis:m_axis + + + FREQ_TOLERANCE_HZ + -1 + + + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + s_axilite + + + + + + + + + AWADDR + + + s_axilite_AWADDR + + + + + AWVALID + + + s_axilite_AWVALID + + + + + AWREADY + + + s_axilite_AWREADY + + + + + WDATA + + + s_axilite_WDATA + + + + + WSTRB + + + s_axilite_WSTRB + + + + + WVALID + + + s_axilite_WVALID + + + + + WREADY + + + s_axilite_WREADY + + + + + BRESP + + + s_axilite_BRESP + + + + + BVALID + + + s_axilite_BVALID + + + + + BREADY + + + s_axilite_BREADY + + + + + ARADDR + + + s_axilite_ARADDR + + + + + ARVALID + + + s_axilite_ARVALID + + + + + ARREADY + + + s_axilite_ARREADY + + + + + RDATA + + + s_axilite_RDATA + + + + + RRESP + + + s_axilite_RRESP + + + + + RVALID + + + s_axilite_RVALID + + + + + RREADY + + + s_axilite_RREADY + + + + + + ap_rst_n + + + + + + + RST + + + ap_rst_n + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axilite + s_axilite + + reg0 + reg0 + 0x0 + 4096 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + thresholding_axi_wrapper + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + fd0bd85b + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + thresholding_axi_wrapper + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + fd0bd85b + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + fc6b9b63 + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 8b0215cd + + + + + + + ap_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + ap_rst_n + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axilite_AWVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axilite_AWREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axilite_AWADDR + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axilite_WVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axilite_WREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axilite_WDATA + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axilite_WSTRB + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axilite_BVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axilite_BREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axilite_BRESP + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axilite_ARVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axilite_ARREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axilite_ARADDR + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axilite_RVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axilite_RREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axilite_RDATA + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axilite_RRESP + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tdata + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axis_tready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + m_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tdata + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + N + N + 4 + + + K + K + 16 + + + C + C + 1 + + + PE + Pe + 1 + + + SIGNED + Signed + true + + + FPARG + Fparg + false + + + BIAS + Bias + 0 + + + CF + Cf + 1 + + + ADDR_BITS + Addr Bits + 6 + + + O_BITS + O Bits + 4 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + hdl/thresholding.sv + systemVerilogSource + + + hdl/thresholding_axi.sv + systemVerilogSource + + + hdl/thresholding_axi_wrapper.v + verilogSource + CHECKSUM_7b8c102d + + + hdl/axilite_if.v + verilogSource + CHECKSUM_69d1ba26 + xil_defaultlib + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + hdl/thresholding.sv + systemVerilogSource + + + hdl/thresholding_axi.sv + systemVerilogSource + + + hdl/thresholding_axi_wrapper.v + verilogSource + + + hdl/axilite_if.v + verilogSource + USED_IN_ipstatic + xil_defaultlib + + + + xilinx_xpgui_view_fileset + + xgui/thresholding_axi_v1_0.tcl + tclSource + CHECKSUM_fc6b9b63 + XGUI_VERSION_2 + + + + xilinx_utilityxitfiles_view_fileset + + gui/thresholding_axi_v1_0.gtcl + GTCL + + + + MultiThreshold + + + N + Output Precision + 4 + + + K + Input Precision + 16 + + + C + Channels + 1 + + + PE + Pe + 1 + + + SIGNED + Signed Inputs + true + + + FPARG + Floating-Point Inputs + false + + + BIAS + Bias + 0 + + + CF + Channel Fold + 1 + + + + false + + + + + + ADDR_BITS + Address Bits + 6 + + + + false + + + + + + O_BITS + Output Value Width + 4 + + + + false + + + + + + Component_Name + thresholding_axi_wrapper_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /UserIP + + thresholding_axi + level_1 + package_project + 2 + + user.org:user:thresholding_axi_wrapper:1.0 + + 2023-06-27T05:47:20Z + + + + + + 2022.2 + + + + + + + + + + + + + + diff --git a/finn-rtllib/thresholding/gui/thresholding_axi_v1_0.gtcl b/finn-rtllib/thresholding/gui/thresholding_axi_v1_0.gtcl new file mode 100644 index 0000000000..90d73ede7e --- /dev/null +++ b/finn-rtllib/thresholding/gui/thresholding_axi_v1_0.gtcl @@ -0,0 +1,4 @@ +# This file is automatically written. Do not modify. +proc gen_USERPARAMETER_CF_VALUE {C PE } {expr $C/$PE} +proc gen_USERPARAMETER_ADDR_BITS_VALUE {C PE N } {expr int(ceil(log($C/$PE)/log(2))+ceil(log($PE)/log(2))+$N+2)} +proc gen_USERPARAMETER_O_BITS_VALUE {BIAS N } {expr int(ceil($BIAS >= 0? log(pow(2,$N)+$BIAS)/log(2) : 1+log(-$BIAS >= pow(2,$N-1)? -$BIAS : pow(2,$N)+$BIAS)/log(2)))} diff --git a/finn-rtllib/thresholding/hdl/axilite_if.v b/finn-rtllib/thresholding/hdl/axilite_if.v new file mode 100644 index 0000000000..bdd4de288e --- /dev/null +++ b/finn-rtllib/thresholding/hdl/axilite_if.v @@ -0,0 +1,210 @@ +/* + Copyright (c) 2020, Xilinx + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + * Neither the name of FINN nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +module axi4lite_if +#( + parameter ADDR_WIDTH = 32, + parameter DATA_WIDTH = 32,//AXI4 spec requires this to be strictly 32 or 64 + parameter IP_DATA_WIDTH = 64//can be any power-of-2 multiple of DATA_WIDTH +) +( +//system signals +input aclk, +input aresetn,//active low, asynchronous assertion and synchronous deassertion + +//Write channels +//write address +output reg awready, +input awvalid, +input [ADDR_WIDTH-1:0] awaddr, +input [2:0] awprot, +//write data +output reg wready, +input wvalid, +input [DATA_WIDTH-1:0] wdata, +input [(DATA_WIDTH/8)-1:0] wstrb, +//burst response +input bready, +output reg bvalid, +output reg [1:0] bresp,//NOTE: 00 = OKAY, 10 = SLVERR (write error) + +//Read channels +//read address +output reg arready, +input arvalid, +input [ADDR_WIDTH-1:0] araddr, +input [2:0] arprot, +//read data +input rready, +output reg rvalid, +output reg [1:0] rresp,//NOTE: 00 = OKAY, 10 = SLVERR (read error) +output reg [DATA_WIDTH-1:0] rdata, + +//IP-side interface +output reg ip_en, +output reg ip_wen, +output reg [ADDR_WIDTH-1:0] ip_addr, +output [IP_DATA_WIDTH-1:0] ip_wdata, +input ip_rack, +input [IP_DATA_WIDTH-1:0] ip_rdata +); + +localparam RESP_OKAY = 2'b00; +localparam RESP_SLVERR = 2'b10; +//get ceil(log2(ceil(IP_DATA_WIDTH/DATA_WIDTH))) +localparam NFOLDS_LOG = $clog2((IP_DATA_WIDTH + DATA_WIDTH - 1) / DATA_WIDTH); + +reg internal_ren; +reg internal_wen; +reg internal_wack; +reg [ADDR_WIDTH-1:0] internal_raddr; +reg [ADDR_WIDTH-1:0] internal_waddr; +reg [DATA_WIDTH-1:0] internal_wdata; +wire [DATA_WIDTH-1:0] internal_rdata; +reg internal_error = 0; + +//check DATA_WIDTH +initial begin + if(DATA_WIDTH != 32 & DATA_WIDTH != 64) begin + $display("AXI4Lite DATA_WIDTH must be 32 or 64"); + $finish; + end +end + +//transaction state machine +localparam STATE_IDLE = 0, + STATE_READ = 1, + STATE_WRITE = 2; + +reg [1:0] state; + +always @(posedge aclk or negedge aresetn) + if(~aresetn) + state <= STATE_IDLE; + else case(state) + STATE_IDLE: + if(awvalid & wvalid) + state <= STATE_WRITE; + else if(arvalid) + state <= STATE_READ; + STATE_READ: + if(rvalid & rready) + state <= STATE_IDLE; + STATE_WRITE: + if(bvalid & bready) + state <= STATE_IDLE; + default: state <= STATE_IDLE; + endcase + +//write-related internal signals +always @(*) begin + internal_waddr = awaddr >> $clog2(DATA_WIDTH/8); + internal_wdata = wdata; + internal_wen = (state == STATE_IDLE) & awvalid & wvalid; +end + +always @(posedge aclk) begin + awready <= internal_wen; + wready <= internal_wen; +end + +//read-related internal signals +always @(*) begin + internal_raddr = araddr >> $clog2(DATA_WIDTH/8); + internal_ren = (state == STATE_IDLE) & ~internal_wen & arvalid; +end + +always @(posedge aclk) + arready <= internal_ren; + +wire write_to_last_fold; + +always @(posedge aclk) begin + ip_wen <= write_to_last_fold; + ip_en <= internal_ren | write_to_last_fold; + if(internal_ren | write_to_last_fold) + ip_addr <= internal_ren ? (internal_raddr >> NFOLDS_LOG) : (internal_waddr >> NFOLDS_LOG); + internal_wack <= internal_wen; +end + +genvar i; +reg [(1<> (internal_rfold*DATA_WIDTH); + always @(posedge aclk) + if(internal_ren) + internal_rfold <= internal_raddr[NFOLDS_LOG-1:0]; + for(i=0; i<(1< + * + * @description + * Produces the N-bit count of those among 2^N-1 thresholds that are not + * larger than the corresponding input: + * y = Σ(T_i <= x) + * The result is computed by binary search. The runtime-configurable + * thresholds must be written in ascending order: + * i < j => T_i < T_j + * The design supports channel folding allowing each input to be processed + * with respect to a selectable set of thresholds. The corresponding + * threshold configuration relies on a channel address prefix. Inputs are + * accompanied by a channel selector. + * + * Parameter Layout as seen on AXI-Lite (row by row): + * | Base \ Offs | 0 1 2 ... 2^N-2 2^N-1 + * ---------+--------------------------------+------------------------------------ + * Chnl #0 | 0 | T_0 T_1 T_2 ... T_{2^N-2} 'x + * Chnl #1 | 2^N | T_0 T_1 T_2 ... T_{2^N-2} 'x + * Chnl #c | ((c/PE)*$clog2(PE) + c%PE)*2^N | T_0 T_1 T_2 ... T_{2^N-2} 'x + * + *****************************************************************************/ +module thresholding #( + int unsigned N, // output precision + int unsigned K, // input/threshold precision + int unsigned C, // number of channels + int unsigned PE, // parallel processing elements + + bit SIGNED = 1, // signed inputs + bit FPARG = 0, // floating-point inputs: [sign] | exponent | mantissa + int BIAS = 0, // offsetting the output [0, 2^N-1] -> [BIAS, 2^N-1 + BIAS] + + // Initial Thresholds + parameter THRESHOLDS_PATH = "", + bit USE_CONFIG = 1, + + // Force Use of On-Chip Memory Blocks + int unsigned DEPTH_TRIGGER_URAM = 0, // if non-zero, local mems of this depth or more go into URAM (prio) + int unsigned DEPTH_TRIGGER_BRAM = 0, // if non-zero, local mems of this depth or more go into BRAM + bit DEEP_PIPELINE = 0, + + localparam int unsigned CF = C/PE, // Channel fold + localparam int unsigned O_BITS = BIAS >= 0? + /* unsigned */ $clog2(2**N+BIAS) : + /* signed */ 1+$clog2(-BIAS >= 2**(N-1)? -BIAS : 2**N+BIAS) +)( + // Global Control + input logic clk, + input logic rst, + + // Threshold Configuration + input logic cfg_en, + input logic cfg_we, + input logic [$clog2(CF)+$clog2(PE)+N-1:0] cfg_a, + input logic [K-1:0] cfg_d, + output logic cfg_rack, + output logic [K-1:0] cfg_q, + + // Input Stream + output logic irdy, + input logic ivld, + input logic [PE-1:0][K-1:0] idat, + + // Output Stream + input logic ordy, + output logic ovld, + output logic [PE-1:0][O_BITS-1:0] odat +); + + // Parameter Constraints Checking + initial begin + if(CF*PE != C) begin + $error("Parallelism PE=%0d is not a multiple of channel count C=%0d.", PE, C); + $finish; + end + end + + // Operations within Pipeline + typedef enum logic [1:0] { + NOP = 2'b00, // No operation + TH = 2'b01, // Thresholding + WR = 2'b11, // Write (initialization) + RB = 2'b10, // Readback (validation) + CFG = 2'b1x // Config op (pointer-preserving) + } op_e; + + // Pipeline Link Type + typedef logic [$clog2(CF)+N-1:0] ptr_t; + typedef logic [K -1:0] val_t; + typedef struct packed { + op_e op; + ptr_t ptr; // WR/RB: address; TH: result + val_t val; // WR/RB: threshold value; TH: input value + } pipe_t; + + //----------------------------------------------------------------------- + // Pipeline Feed + // - configuration always takes precedence + // - number of pending thresholding ops capped to N+3 + // across pipeline and output FIFO: pipe:N + A:1 + B:1 + 1 + localparam int unsigned MAX_PENDING = (DEEP_PIPELINE+1)*N + 3; + pipe_t pipe[PE][N+1]; + if(1) begin : blkFeed + + // Thresholding Input Guard ensuring Output FIFO is never overrun + logic signed [$clog2(MAX_PENDING):0] GuardSem = MAX_PENDING-1; // MAX_PENDING-1, ..., 0, -1 + uwire th_full = GuardSem[$left(GuardSem)]; + always_ff @(posedge clk) begin + if(rst) GuardSem <= MAX_PENDING-1; + else begin + automatic logic dec = !(USE_CONFIG && cfg_en) && !th_full && ivld; + automatic logic inc = ovld && ordy; + GuardSem <= GuardSem + (inc == dec? 0 : inc? 1 : -1); + end + end + + // PE Configuration Address Decoding + uwire cfg_sel[PE]; + if(PE == 1) assign cfg_sel[0] = 1; + else begin + for(genvar pe = 0; pe < PE; pe++) begin + assign cfg_sel[pe] = USE_CONFIG && cfg_en && (cfg_a[N+:$clog2(PE)] == pe); + end + end + + uwire ptr_t iptr; + assign iptr[0+:N] = cfg_a[0+:N]; + if(CF > 1) begin + // Channel Fold Rotation + logic [$clog2(CF)-1:0] CnlCnt = 0; + logic CnlLst = 0; + always_ff @(posedge clk) begin + if(rst) begin + CnlCnt <= 0; + CnlLst <= 0; + end + else if(!(USE_CONFIG && cfg_en) && !th_full && ivld) begin + CnlCnt <= CnlCnt + (CnlLst? 1-CF : 1); + CnlLst <= CnlCnt == CF-2; + end + end + + assign iptr[N+:$clog2(CF)] = USE_CONFIG && cfg_en? cfg_a[N+$clog2(PE)+:$clog2(CF)] : CnlCnt; + end + + for(genvar pe = 0; pe < PE; pe++) begin + assign pipe[pe][0] = '{ + op: USE_CONFIG && cfg_en? + (!cfg_sel[pe]? NOP : cfg_we? WR : RB) : + (ivld && !th_full? TH : NOP), + ptr: iptr, + val: !(USE_CONFIG && cfg_en)? idat[pe] : cfg_we? cfg_d : 0 + }; + end + + assign irdy = !(USE_CONFIG && cfg_en) && !th_full; + end : blkFeed + + //----------------------------------------------------------------------- + // Free-Running Thresholding Pipeline + for(genvar stage = 0; stage < N; stage++) begin : genStages + + localparam int unsigned SN = N-1-stage; + for(genvar pe = 0; pe < PE; pe++) begin : genPE + uwire pipe_t p = pipe[pe][stage]; + uwire cs = (p.ptr[SN:0] == 2**SN-1); + + // Threshold Memory + val_t Thresh; // Read-out register + if(1) begin : blkThresh + localparam int unsigned DEPTH = CF * 2**stage; + localparam RAM_STYLE = + DEPTH_TRIGGER_URAM && (DEPTH >= DEPTH_TRIGGER_URAM)? "ultra" : + DEPTH_TRIGGER_BRAM && (DEPTH >= DEPTH_TRIGGER_BRAM)? "block" : + // If BRAM trigger defined, force distributed memory below if Vivado may be tempted to use BRAM nonetheless. + DEPTH_TRIGGER_BRAM && (DEPTH >= 64)? "distributed" : "auto"; + + (* RAM_STYLE = RAM_STYLE *) + val_t Threshs[DEPTH]; + if(THRESHOLDS_PATH != "") begin + initial $readmemh($sformatf("%sthreshs_%0d_%0d.dat", THRESHOLDS_PATH, pe, stage), Threshs); + end + + if(USE_CONFIG) begin : genThreshMem + uwire we = (p.op ==? WR) && cs; + if((CF == 1) && (stage == 0)) begin + always @(posedge clk) begin + if(we) Threshs[0] <= p.val; + end + end + else begin + uwire [$clog2(CF)+stage-1:0] addr = p.ptr[$clog2(CF)+N-1:SN+1]; + always @(posedge clk) begin + if(we) Threshs[addr] <= p.val; + end + end + end : genThreshMem + + if((CF == 1) && (stage == 0)) begin + assign Thresh = Threshs[0]; + end + else begin + uwire [$clog2(CF)+stage-1:0] addr = p.ptr[$clog2(CF)+N-1:SN+1]; + always_ff @(posedge clk) begin + Thresh <= Threshs[addr]; + end + end + + end : blkThresh + + // Pipeline State + pipe_t P = '{ op: NOP, default: 'x }; + logic Reval = 0; + always_ff @(posedge clk) begin + if(rst) begin + P <= '{ op: NOP, default: 'x }; + Reval <= 0; + end + else begin + P <= p; + Reval <= (p.op ==? RB) && cs; + end + end + + logic cmp; + if(!SIGNED) assign cmp = $unsigned(Thresh) <= $unsigned(P.val); + else if(!FPARG) assign cmp = $signed(Thresh) <= $signed(P.val); + else begin : blkSignedFloat + uwire mag_eq = Thresh[K-2:0] == P.val[K-2:0]; + uwire mag_le = Thresh[K-2:0] <= P.val[K-2:0]; + always_comb begin + unique case({Thresh[K-1], P.val[K-1]}) + 2'b00: cmp = mag_le; + 2'b01: cmp = 0; + 2'b10: cmp = 1; + 2'b11: cmp = !mag_le || mag_eq; + default: cmp = 'x; + endcase + end + end : blkSignedFloat + + // Pipeline State Update + pipe_t pp; + always_comb begin + pp = P; + if(P.op !=? CFG) pp.ptr[SN] = cmp; + if(Reval) pp.val = Thresh; + end + + // Pipeline State Forward (potentially additional register) + pipe_t pf; + if(!DEEP_PIPELINE) assign pf = pp; + else begin + pipe_t Pf = '{ op: NOP, default: 'x }; + always_ff @(posedge clk) begin + if(rst) Pf <= '{ op: NOP, default: 'x }; + else Pf <= pp; + end + assign pf = Pf; + end + + assign pipe[pe][stage+1] = pf; + + end : genPE + end : genStages + + //----------------------------------------------------------------------- + // Configuration Readback + always_comb begin + cfg_rack = 0; + cfg_q = 0; + foreach(pipe[pe]) begin + automatic pipe_t p = pipe[pe][N]; + cfg_rack |= p.op ==? RB; + cfg_q |= p.val; + end + end + + //----------------------------------------------------------------------- + // Stream Output through FIFO + // - Depth of N + Output Reg to allow pipe to drain entirely under backpressure + // - Typically mapped to an SRL shift register + if(1) begin : blkStreamOutput + localparam int unsigned A_DEPTH = MAX_PENDING - 1; + logic [PE-1 : 0][N-1 : 0] ADat[A_DEPTH]; + logic signed [$clog2(A_DEPTH):0] APtr = '1; // -1, 0, 1, ..., A_DEPTH-1 + uwire avld = !APtr[$left(APtr)]; + + logic [PE-1:0][N-1:0] BDat = 'x; + logic BVld = 0; + + uwire aload = pipe[0][N].op ==? TH; + uwire bload = !BVld || ordy; + + always_ff @(posedge clk) begin + if(aload) begin + assert(APtr < $signed(A_DEPTH-1)) else begin + $error("Overrun after failing stream guard."); + $stop; + end + foreach(pipe[pe]) ADat[0][pe] <= pipe[pe][N].ptr; + for(int unsigned i = 1; i < A_DEPTH; i++) ADat[i] <= ADat[i-1]; + end + end + always_ff @(posedge clk) begin + if(rst) APtr <= '1; + else APtr <= APtr + (aload == (avld && bload)? 0 : aload? 1 : -1); + end + always_ff @(posedge clk) begin + if(rst) begin + BDat <= 'x; + BVld <= 0; + end + else if(bload) begin + BDat <= ADat[APtr]; + BVld <= avld; + end + end + + assign ovld = BVld; + for(genvar pe = 0; pe < PE; pe++) begin + assign odat[pe] = BDat[pe] + BIAS; + end + end : blkStreamOutput + +endmodule : thresholding diff --git a/finn-rtllib/thresholding/hdl/thresholding_axi.sv b/finn-rtllib/thresholding/hdl/thresholding_axi.sv new file mode 100644 index 0000000000..1f235b9486 --- /dev/null +++ b/finn-rtllib/thresholding/hdl/thresholding_axi.sv @@ -0,0 +1,164 @@ +/****************************************************************************** + * Copyright (C) 2022, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * @brief All-AXI interface adapter for thresholding module. + * @author Thomas B. Preußer + * + * @description + * This AXI adapter fits the core thresholding functionality: + * - with AXI stream data interfaces with flow control + * - with implicit round-robin channel rotation as used by FINN, and + * - performs aligned byte address to parameter word address translation. + *****************************************************************************/ + +module thresholding_axi #( + int unsigned N, // output precision + int unsigned K, // input/threshold precision + int unsigned C = 1, // Channels + int unsigned PE = 1, // Processing Parallelism, requires C = k*PE + + bit SIGNED = 1, // signed inputs + bit FPARG = 0, // floating-point inputs: [sign] | exponent | mantissa + int BIAS = 0, // offsetting the output [0, 2^N-1] -> [BIAS, 2^N-1 + BIAS] + + // Initial Thresholds + parameter THRESHOLDS_PATH = "", + + bit USE_AXILITE, // Implement AXI-Lite for threshold read/write + + // Force Use of On-Chip Memory Blocks + int unsigned DEPTH_TRIGGER_URAM = 0, // if non-zero, local mems of this depth or more go into URAM (prio) + int unsigned DEPTH_TRIGGER_BRAM = 0, // if non-zero, local mems of this depth or more go into BRAM + bit DEEP_PIPELINE = 0, + + localparam int unsigned CF = C/PE, // Channel Fold + localparam int unsigned ADDR_BITS = $clog2(CF) + $clog2(PE) + N + 2, + localparam int unsigned O_BITS = BIAS >= 0? + /* unsigned */ $clog2(2**N+BIAS) : + /* signed */ 1+$clog2(-BIAS >= 2**(N-1)? -BIAS : 2**N+BIAS) +)( + //- Global Control ------------------ + input logic ap_clk, + input logic ap_rst_n, + + //- AXI Lite ------------------------ + // Writing + input logic s_axilite_AWVALID, + output logic s_axilite_AWREADY, + input logic [ADDR_BITS-1:0] s_axilite_AWADDR, // lowest 2 bits (byte selectors) are ignored + + input logic s_axilite_WVALID, + output logic s_axilite_WREADY, + input logic [31:0] s_axilite_WDATA, + input logic [ 3:0] s_axilite_WSTRB, + + output logic s_axilite_BVALID, + input logic s_axilite_BREADY, + output logic [1:0] s_axilite_BRESP, + + // Reading + input logic s_axilite_ARVALID, + output logic s_axilite_ARREADY, + input logic [ADDR_BITS-1:0] s_axilite_ARADDR, + + output logic s_axilite_RVALID, + input logic s_axilite_RREADY, + output logic [31:0] s_axilite_RDATA, + output logic [ 1:0] s_axilite_RRESP, + + //- AXI Stream - Input -------------- + output logic s_axis_tready, + input logic s_axis_tvalid, + input logic [((PE*K+7)/8)*8-1:0] s_axis_tdata, + + //- AXI Stream - Output ------------- + input logic m_axis_tready, + output logic m_axis_tvalid, + output logic [((PE*O_BITS+7)/8)*8-1:0] m_axis_tdata +); + + //----------------------------------------------------------------------- + // AXI-lite Configuration Interface + uwire cfg_en; + uwire cfg_we; + uwire [ADDR_BITS-3:0] cfg_a; + uwire [K -1:0] cfg_d; + uwire cfg_rack; + uwire [K -1:0] cfg_q; + + if(USE_AXILITE) begin + uwire [ADDR_BITS-1:0] cfg_a0; + axi4lite_if #(.ADDR_WIDTH(ADDR_BITS), .DATA_WIDTH(32), .IP_DATA_WIDTH(K)) axi ( + .aclk(ap_clk), .aresetn(ap_rst_n), + + .awready(s_axilite_AWREADY), .awvalid(s_axilite_AWVALID), .awaddr(s_axilite_AWADDR), .awprot('x), + .wready(s_axilite_WREADY), .wvalid(s_axilite_WVALID), .wdata(s_axilite_WDATA), .wstrb(s_axilite_WSTRB), + .bready(s_axilite_BREADY), .bvalid(s_axilite_BVALID), .bresp(s_axilite_BRESP), + + .arready(s_axilite_ARREADY), .arvalid(s_axilite_ARVALID), .araddr(s_axilite_ARADDR), .arprot('x), + .rready(s_axilite_RREADY), .rvalid(s_axilite_RVALID), .rresp(s_axilite_RRESP), .rdata(s_axilite_RDATA), + + .ip_en(cfg_en), .ip_wen(cfg_we), .ip_addr(cfg_a0), .ip_wdata(cfg_d), + .ip_rack(cfg_rack), .ip_rdata(cfg_q) + ); + assign cfg_a = cfg_a0[ADDR_BITS-3:0]; + always_ff @(posedge ap_clk) begin + assert(!ap_rst_n || !cfg_en || (cfg_a0[ADDR_BITS-2+:2] === 3'h0)) else begin + $error("%m: Spurious high address bits."); + $stop; + end + end + end + else begin + assign cfg_en = 0; + assign cfg_we = 'x; + assign cfg_a = 'x; + assign cfg_d = 'x; + end + + //----------------------------------------------------------------------- + // Kernel Implementation + thresholding #( + .N(N), .K(K), .C(C), .PE(PE), + .SIGNED(SIGNED), .FPARG(FPARG), .BIAS(BIAS), + .THRESHOLDS_PATH(THRESHOLDS_PATH), .USE_CONFIG(USE_AXILITE), + .DEPTH_TRIGGER_URAM(DEPTH_TRIGGER_URAM), .DEPTH_TRIGGER_BRAM(DEPTH_TRIGGER_BRAM), + .DEEP_PIPELINE(DEEP_PIPELINE) + ) impl ( + .clk(ap_clk), .rst(!ap_rst_n), + + .cfg_en, .cfg_we, .cfg_a, .cfg_d, + .cfg_rack, .cfg_q, + + .irdy(s_axis_tready), .ivld(s_axis_tvalid), .idat(s_axis_tdata), + .ordy(m_axis_tready), .ovld(m_axis_tvalid), .odat(m_axis_tdata) + ); + +endmodule : thresholding_axi diff --git a/finn-rtllib/thresholding/hdl/thresholding_template_wrapper.v b/finn-rtllib/thresholding/hdl/thresholding_template_wrapper.v new file mode 100644 index 0000000000..ef76a23cbc --- /dev/null +++ b/finn-rtllib/thresholding/hdl/thresholding_template_wrapper.v @@ -0,0 +1,120 @@ +/** + * Copyright (c) 2023, Xilinx + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of FINN nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * @author Thomas B. Preußer + * @brief Verilog wrapper for IP packaging. + */ + +module $MODULE_NAME_AXI_WRAPPER$ #( + parameter N = $N$, // output precision + parameter K = $M$, // input/threshold precision + parameter C = $C$, // Channels + parameter PE = $PE$, // Processing Parallelism, requires C = k*PE + + parameter SIGNED = $SIGNED$, // signed inputs + parameter FPARG = 0, // floating-point inputs: [sign] | exponent | mantissa + parameter BIAS = $BIAS$, // offsetting the output [0, 2^N-1] -> [BIAS, 2^N-1 + BIAS] + + parameter THRESHOLDS_PATH = $THRESHOLDS_PATH$, // Directory with initial threshold data + parameter USE_AXILITE = $USE_AXILITE$, // Implement AXI-Lite for threshold read/write + + // Force Use of On-Chip Memory Blocks + parameter DEPTH_TRIGGER_URAM = $DEPTH_TRIGGER_URAM$, // if non-zero, local mems of this depth or more go into URAM (prio) + parameter DEPTH_TRIGGER_BRAM = $DEPTH_TRIGGER_BRAM$, // if non-zero, local mems of this depth or more go into BRAM + parameter DEEP_PIPELINE = $DEEP_PIPELINE$, // [bit] extra pipeline stages for easier timing closure + + parameter O_BITS = $O_BITS$ +)( + // Global Control + (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF s_axilite:in0_V:out_V, ASSOCIATED_RESET ap_rst_n" *) + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *) + input ap_clk, + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) + input ap_rst_n, + + //- AXI Lite ------------------------ + // Writing + input s_axilite_AWVALID, + output s_axilite_AWREADY, + input [$clog2(C/PE) + $clog2(PE) + N + 1:0] s_axilite_AWADDR, // lowest 2 bits (byte selectors) are ignored + + input s_axilite_WVALID, + output s_axilite_WREADY, + input [31:0] s_axilite_WDATA, + input [ 3:0] s_axilite_WSTRB, + + output s_axilite_BVALID, + input s_axilite_BREADY, + output [1:0] s_axilite_BRESP, + + // Reading + input s_axilite_ARVALID, + output s_axilite_ARREADY, + input [$clog2(C/PE) + $clog2(PE) + N + 1:0] s_axilite_ARADDR, + + output s_axilite_RVALID, + input s_axilite_RREADY, + output [31:0] s_axilite_RDATA, + output [ 1:0] s_axilite_RRESP, + + //- AXI Stream - Input -------------- + output in0_V_TREADY, + input in0_V_TVALID, + input [((PE*K+7)/8)*8-1:0] in0_V_TDATA, + + //- AXI Stream - Output ------------- + input out_V_TREADY, + output out_V_TVALID, + output [((PE*O_BITS+7)/8)*8-1:0] out_V_TDATA +); + + thresholding_axi #( + .N(N), .K(K), .C(C), .PE(PE), + .SIGNED(SIGNED), + .FPARG(FPARG), + .BIAS(BIAS), + .THRESHOLDS_PATH(THRESHOLDS_PATH), + .USE_AXILITE(USE_AXILITE), + .DEPTH_TRIGGER_URAM(DEPTH_TRIGGER_URAM), + .DEPTH_TRIGGER_BRAM(DEPTH_TRIGGER_BRAM), + .DEEP_PIPELINE(DEEP_PIPELINE) + ) core ( + .ap_clk(ap_clk), .ap_rst_n(ap_rst_n), + + .s_axilite_AWVALID(s_axilite_AWVALID), .s_axilite_AWREADY(s_axilite_AWREADY), .s_axilite_AWADDR(s_axilite_AWADDR), + .s_axilite_WVALID(s_axilite_WVALID), .s_axilite_WREADY(s_axilite_WREADY), .s_axilite_WDATA(s_axilite_WDATA), .s_axilite_WSTRB(s_axilite_WSTRB), + .s_axilite_BVALID(s_axilite_BVALID), .s_axilite_BREADY(s_axilite_BREADY), .s_axilite_BRESP(s_axilite_BRESP), + + .s_axilite_ARVALID(s_axilite_ARVALID), .s_axilite_ARREADY(s_axilite_ARREADY), .s_axilite_ARADDR(s_axilite_ARADDR), + .s_axilite_RVALID(s_axilite_RVALID), .s_axilite_RREADY(s_axilite_RREADY), .s_axilite_RDATA(s_axilite_RDATA), .s_axilite_RRESP(s_axilite_RRESP), + .s_axis_tready(in0_V_TREADY), .s_axis_tvalid(in0_V_TVALID), .s_axis_tdata(in0_V_TDATA), + .m_axis_tready(out_V_TREADY), .m_axis_tvalid(out_V_TVALID), .m_axis_tdata(out_V_TDATA) + ); + +endmodule // $MODULE_NAME_AXI_WRAPPER$ diff --git a/finn-rtllib/thresholding/sim/thresh_gen.sv b/finn-rtllib/thresholding/sim/thresh_gen.sv new file mode 100644 index 0000000000..713723aafa --- /dev/null +++ b/finn-rtllib/thresholding/sim/thresh_gen.sv @@ -0,0 +1,45 @@ +module thresh_gen; + localparam int unsigned K = 9; + localparam int unsigned N = 4; + localparam int unsigned C = 6; + + typedef logic [K-1:0] thresh_t; + localparam thresh_t THRESHOLDS[C][2**N-1] = '{ + '{ 'h00, 'h01, 'h02, 'h03, 'h04, 'h05, 'h06, 'h07, 'h08, 'h09, 'h0a, 'h0b, 'h0c, 'h0d, 'h0e }, + '{ 'h10, 'h11, 'h12, 'h13, 'h14, 'h15, 'h16, 'h17, 'h18, 'h19, 'h1a, 'h1b, 'h1c, 'h1d, 'h1e }, + '{ 'h20, 'h21, 'h22, 'h23, 'h24, 'h25, 'h26, 'h27, 'h28, 'h29, 'h2a, 'h2b, 'h2c, 'h2d, 'h2e }, + '{ 'h30, 'h31, 'h32, 'h33, 'h34, 'h35, 'h36, 'h37, 'h38, 'h39, 'h3a, 'h3b, 'h3c, 'h3d, 'h3e }, + '{ 'h40, 'h41, 'h42, 'h43, 'h44, 'h45, 'h46, 'h47, 'h48, 'h49, 'h4a, 'h4b, 'h4c, 'h4d, 'h4e }, + '{ 'h50, 'h51, 'h52, 'h53, 'h54, 'h55, 'h56, 'h57, 'h58, 'h59, 'h5a, 'h5b, 'h5c, 'h5d, 'h5e } + }; + localparam THRESHOLDS_PATH = "./"; + + localparam int unsigned PE = 2; + localparam int unsigned CF = C/PE; + + for(genvar stage = 0; stage < N; stage++) begin + localparam int unsigned SN = N-1-stage; + for(genvar pe = 0; pe < PE; pe++) begin + initial begin + automatic string file = $sformatf("%sthreshs_%0d_%0d.dat", THRESHOLDS_PATH, pe, stage); + + automatic thresh_t threshs[CF * 2**stage]; + for(int unsigned c = 0; c < CF; c++) begin + for(int unsigned i = 0; i < 2**stage; i++) begin + threshs[(c << stage) + i] = THRESHOLDS[c*PE + pe][(i<<(N-stage)) + 2**SN-1]; + end + end + + $writememh(file, threshs); + end + end + end + + // Quit after running all initializers + initial begin + #1ns; + $display("Generation done."); + $finish; + end + +endmodule : thresh_gen diff --git a/finn-rtllib/thresholding/sim/thresholding.tcl b/finn-rtllib/thresholding/sim/thresholding.tcl new file mode 100644 index 0000000000..82dc59deb1 --- /dev/null +++ b/finn-rtllib/thresholding/sim/thresholding.tcl @@ -0,0 +1,17 @@ +create_project -force thresholding thresholding.vivado -part xcvc1902-vsva2197-2MP-e-S +set_property board_part xilinx.com:vck190:part0:2.2 [current_project] + +read_verilog hdl/axilite_if.v +read_verilog -sv { hdl/thresholding.sv hdl/thresholding_axi.sv } + +set simset [current_fileset -simset] +set_property -name xsim.simulate.log_all_signals -value true -objects $simset +set_property -name xsim.simulate.runtime -value all -objects $simset +add_files -fileset $simset { sim/thresholding_tb.sv sim/thresholding_axi_tb.sv } + +foreach top { thresholding_tb thresholding_axi_tb } { + set_property top $top $simset + + launch_simulation + close_sim +} diff --git a/finn-rtllib/thresholding/sim/thresholding_axi_tb.sv b/finn-rtllib/thresholding/sim/thresholding_axi_tb.sv new file mode 100644 index 0000000000..918f539d15 --- /dev/null +++ b/finn-rtllib/thresholding/sim/thresholding_axi_tb.sv @@ -0,0 +1,314 @@ +/****************************************************************************** + * Copyright (C) 2022, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * @brief Testbench for thresholding_axi. + * @author Monica Chiosa + * + */ + +module thresholding_axi_tb #( + int unsigned N = 4, // output precision + int unsigned C = 6, // number of channels + int unsigned PE = 2, + real M0 = 7.3, // slope of the uniform thresholding line + real B0 = 3.1, // offset of the uniform thresholding line + bit THROTTLED = 1, + + localparam int unsigned CF = C/PE, // Channel Fold + localparam int unsigned ADDR_BITS = $clog2(CF) + $clog2(PE) + N + 2 +); + + //----------------------------------------------------------------------- + // Design Geometry + + // For each channel = [0,channel): + // M_channel = M0 + CX*channel + // B_channel = B0 + CX*channel + // Input/threshold precision computed according with the maximum posible value + localparam real CX = 1.375; + localparam int unsigned K = $clog2((2**N-1)*(M0+C*CX) + (B0+C*CX)); // unused sign + magnitude + localparam int unsigned C_BITS = C < 2? 1 : $clog2(C); + + localparam int unsigned MST_STRM_WROUNDS = 503; + + typedef int unsigned threshs_t[C][2**N-1]; + function threshs_t init_thresholds(); + automatic threshs_t res; + for(int unsigned c = 0; c < C; c++) begin + automatic real m = M0 + c*CX; + automatic real b = B0 + c*CX; + foreach(res[c][i]) begin + res[c][i] = int'($ceil(m*i + b)); + end + end + return res; + endfunction : init_thresholds + localparam threshs_t THRESHS = init_thresholds(); + + //----------------------------------------------------------------------- + // Clock and Reset Control + logic clk = 0; + always #5ns clk = !clk; + logic rst = 1; + initial begin + #10ns; + @(posedge clk); + rst <= 0; + end + + //----------------------------------------------------------------------- + // DUT + logic s_axilite_AWVALID; + uwire s_axilite_AWREADY; + logic [ADDR_BITS-1:0] s_axilite_AWADDR; // lowest 2 bits (byte selectors) are ignored + logic s_axilite_WVALID; + uwire s_axilite_WREADY; + logic [ 31:0] s_axilite_WDATA; + uwire s_axilite_BVALID; + logic s_axilite_BREADY; + uwire [ 1:0] s_axilite_BRESP; + logic s_axilite_ARVALID; + uwire s_axilite_ARREADY; + logic [ADDR_BITS-1:0] s_axilite_ARADDR; + uwire s_axilite_RVALID; + uwire s_axilite_RREADY = 1; + uwire [ 31:0] s_axilite_RDATA; + uwire [ 1:0] s_axilite_RRESP; + + uwire irdy; + logic ivld; + logic [PE-1:0][K-1:0] idat; + + logic ordy = 0; + uwire ovld; + uwire [PE-1:0][N-1:0] odat; + + thresholding_axi #(.N(N), .K(K), .C(C), .PE(PE), .SIGNED(0), .USE_AXILITE(1)) dut ( + .ap_clk(clk), .ap_rst_n(!rst), + + // Configuration + .s_axilite_AWVALID, .s_axilite_AWREADY, .s_axilite_AWADDR, + .s_axilite_WVALID, .s_axilite_WREADY, .s_axilite_WDATA, .s_axilite_WSTRB('1), + .s_axilite_BVALID, .s_axilite_BREADY, .s_axilite_BRESP, + .s_axilite_ARVALID, .s_axilite_ARREADY, .s_axilite_ARADDR, + .s_axilite_RVALID, .s_axilite_RREADY, .s_axilite_RDATA, .s_axilite_RRESP, + + // Stream Processing + .s_axis_tready(irdy), .s_axis_tvalid(ivld), .s_axis_tdata(idat), + .m_axis_tready(ordy), .m_axis_tvalid(ovld), .m_axis_tdata(odat) + ); + + //----------------------------------------------------------------------- + // Input Stimuli + typedef logic [PE-1:0][K-1:0] input_t; + typedef logic [$clog2(CF)+$clog2(PE)+N-1:0] addr_t; + input_t QW[$]; // Input Feed Tracing + addr_t QC[$]; + + int unsigned error_cnt = 0; + bit done = 0; + initial begin + // Report testbench details + $display("Testbench - tresholding K=%0d -> N=%0d", K, N); + for(int unsigned c = 0; c < C; c++) begin + $write("Channel #%0d: Thresholds = {", c); + for(int unsigned i = 0; i < 2**N-1; i++) $write(" %0d", THRESHS[c][i]); + $display(" }"); + end + + // Config + s_axilite_AWVALID = 0; + s_axilite_AWADDR = 'x; + s_axilite_WVALID = 0; + s_axilite_WDATA = 'x; + s_axilite_BREADY = 0; + s_axilite_ARVALID = 0; + s_axilite_ARADDR = 'x; + + // Stream Input + ivld = 0; + idat = 'x; + + @(posedge clk iff !rst); + + // Threshold Configuration + for(int unsigned c = 0; c < C; c+=PE) begin + automatic addr_t addr = 0; + if(CF > 1) addr[N+$clog2(PE)+:$clog2(CF)] = c/PE; + for(int unsigned pe = 0; pe < PE; pe++) begin + if(PE > 1) addr[N+:$clog2(PE)] = pe; + for(int unsigned t = 0; t < 2**N-1; t++) begin + addr[0+:N] = t; + fork + begin + s_axilite_AWVALID <= 1; + s_axilite_AWADDR <= { addr, 2'b00 }; + @(posedge clk iff s_axilite_AWREADY); + s_axilite_AWVALID <= 0; + s_axilite_AWADDR <= 'x; + end + begin + s_axilite_WVALID <= 1; + s_axilite_WDATA <= THRESHS[c+pe][t]; + @(posedge clk iff s_axilite_WREADY); + s_axilite_WVALID <= 0; + s_axilite_WDATA <= 'x; + end + begin + s_axilite_BREADY <= 1; + @(posedge clk iff s_axilite_BVALID); + assert(s_axilite_BRESP == '0) else begin + $error("Error on parameter write."); + $stop; + end + s_axilite_BREADY <= 0; + end + join + end + end + end + + fork + // Intermittent configuration readback + while(!done) begin + if(($urandom()%37) != 0) begin + s_axilite_ARVALID <= 0; + s_axilite_ARADDR <= 'x; + @(posedge clk); + end + else begin + automatic addr_t addr = $urandom()%(N-1); + if(PE > 1) addr[N+:$clog2(PE)] = $urandom()%PE; + if(CF > 1) addr[N+$clog2(PE)+:$clog2(CF)] = $urandom()%CF; + + s_axilite_ARVALID <= 1; + s_axilite_ARADDR <= { addr, 2'b00 }; + @(posedge clk iff s_axilite_ARREADY); + + QC.push_back(addr); + end + end + + // AXI4Stream MST Writes input values + repeat(MST_STRM_WROUNDS) begin + automatic input_t dat; + + while(THROTTLED && ($urandom()%7 == 0)) @(posedge clk); + + std::randomize(dat); + ivld <= 1; + idat <= dat; + @(posedge clk iff irdy); + ivld <= 0; + idat <= 'x; + QW.push_back(dat); + end + join_any + done <= 1; + repeat(N+6) @(posedge clk); + + assert(QW.size() == 0) else begin + $error("Missing %0d outputs.", QW.size()); + $stop; + end + assert(QC.size() == 0) else begin + $error("Missing %0d readback replies.", QC.size()); + $stop; + end + + $display("Test completed: %0d errors in %0d tests.", error_cnt, MST_STRM_WROUNDS); + $display("========================================="); + $finish; + end + + // Output Checker ------------------------------------------------------- + + // Configuration Readback + always_ff @(posedge clk iff s_axilite_RVALID) begin + assert(s_axilite_RRESP == '0) else begin + $error("Read back error."); + $stop; + end + assert(QC.size()) begin + automatic addr_t addr = QC.pop_front(); + automatic int unsigned cnl = + (CF == 1? 0 : addr[N+$clog2(PE)+:$clog2(CF)] * PE) + + (PE == 1? 0 : addr[N+:$clog2(PE)]); + automatic logic [K-1:0] exp = THRESHS[cnl][addr[0+:N]]; + assert(s_axilite_RDATA == exp) else begin + $error("Readback mismatch on #%0d.%0d: %0d instead of %0d", cnl, addr[0+:N], s_axilite_RDATA, exp); + $stop; + end + end + else begin + $error("Spurious readback output."); + $stop; + end + end + + // Stream Output + int unsigned OCnl = 0; + always @(posedge clk) begin + if(rst) begin + OCnl <= 0; + ordy <= 1'b0; + end + else begin + if(!ordy || ovld) ordy <= ($urandom()%5 != 0) || !THROTTLED; + + if(ordy && ovld) begin + assert(QW.size()) begin + automatic input_t x = QW.pop_front(); + + for(int unsigned pe = 0; pe < PE; pe++) begin + automatic int unsigned cnl = OCnl + pe; + + $display("Mapped CNL=%0d DAT=%3d -> #%2d", cnl, x[pe], odat[pe]); + assert( + ((odat[pe] == 0) || (THRESHS[cnl][odat[pe]-1] <= x[pe])) && + ((odat[pe] == 2**N-1) || (x[pe] < THRESHS[cnl][odat[pe]])) + ) else begin + $error("Output error on presumed input CNL=%0d DAT=0x%0x -> #%0d", cnl, x[pe], odat[pe]); + error_cnt++; + $stop; + end + end + end + else begin + $error("Spurious output."); + $stop; + end + + OCnl <= (OCnl + PE)%C; + end + end + end + +endmodule: thresholding_axi_tb diff --git a/finn-rtllib/thresholding/sim/thresholding_tb.sv b/finn-rtllib/thresholding/sim/thresholding_tb.sv new file mode 100644 index 0000000000..e42145f10e --- /dev/null +++ b/finn-rtllib/thresholding/sim/thresholding_tb.sv @@ -0,0 +1,274 @@ +/****************************************************************************** + * Copyright (C) 2022, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * @brief Testbench for thresholding_axi. + * @author Monica Chiosa + * + */ + +module thresholding_tb #( + int unsigned K = 10, // input precision + int unsigned N = 4, // output precision + int unsigned C = 6, // number of channels + int unsigned PE = 2, + + localparam int unsigned CF = C/PE // Channel Fold +); + localparam bit DEEP_PIPELINE = 1; + + localparam int unsigned MST_STRM_WROUNDS = 507; + localparam bit THROTTLED = 1; + + //----------------------------------------------------------------------- + // Clock and Reset Control + logic clk = 0; + always #5ns clk = !clk; + logic rst = 1; + initial begin + #10ns; + @(posedge clk); + rst <= 0; + end + + //----------------------------------------------------------------------- + // Parallel Instances differing in Data Type + typedef logic [K -1:0] val_t; + typedef val_t threshs_t[C][2**N-1]; + typedef val_t [PE-1:0] input_t; + typedef logic [$clog2(CF)+$clog2(PE)+N-1:0] addr_t; + logic [0:2] term = '0; + always_comb begin + if(&term) $finish; + end + for(genvar i = 0; i < 3; i++) begin : genTypes + localparam bit SIGNED = i>0; + localparam bit FPARG = i>1; + + //- DUT ------------------------- + logic cfg_en; + logic cfg_we; + logic [$clog2(C)+N-1:0] cfg_a; + logic [K-1:0] cfg_d; + uwire cfg_rack; + uwire [K-1:0] cfg_q; + + uwire irdy; + logic ivld; + logic [PE-1:0][K-1:0] idat; + + logic ordy = 0; + uwire ovld; + uwire [PE-1:0][N-1:0] odat; + + thresholding #(.N(N), .K(K), .C(C), .PE(PE), .SIGNED(SIGNED), .FPARG(FPARG), .USE_CONFIG(1), .DEEP_PIPELINE(DEEP_PIPELINE)) dut ( + .clk, .rst, + + // Configuration + .cfg_en, .cfg_we, .cfg_a, .cfg_d, + .cfg_rack, .cfg_q, + + // Stream Processing + .irdy, .ivld, .idat, + .ordy, .ovld, .odat + ); + + //- Stimulus Driver ------------- + threshs_t THRESHS; + function val_t sigord(input val_t x); + automatic val_t res = x; + if(SIGNED) begin + if(FPARG && x[K-1]) res[K-2:0] = ~x[K-2:0]; + res[K-1] = !x[K-1]; + end + return res; + endfunction : sigord + + input_t QW[$]; // Input tracing + addr_t QC[$]; // Readback tracking + int unsigned error_cnt = 0; + bit done = 0; + initial begin + + // Generate thresholds + std::randomize(THRESHS); + foreach(THRESHS[c]) begin + val_t row[2**N-1] = THRESHS[c]; + row.sort with (sigord(item)); + THRESHS[c] = row; + end + + // Report test case details + $display("[%0d] Thresholding %s%s%0d -> uint%0d", i, SIGNED? "s" : "u", FPARG? "fp" : "int", K, N); + for(int unsigned c = 0; c < C; c++) begin + $write("[%0d] Channel #%0d: Thresholds = {", i, c); + for(int unsigned i = 0; i < 2**N-1; i++) $write(" %0X", THRESHS[c][i]); + $display(" }"); + end + + // Config + cfg_en = 0; + cfg_we = 'x; + cfg_a = 'x; + cfg_d = 'x; + + // Stream Input + ivld = 0; + idat = 'x; + + @(posedge clk iff !rst); + + // Threshold Configuratin + cfg_en <= 1; + cfg_we <= 1; + for(int unsigned c = 0; c < C; c+=PE) begin + if(CF > 1) cfg_a[N+$clog2(PE)+:$clog2(CF)] <= c/PE; + for(int unsigned pe = 0; pe < PE; pe++) begin + if(PE > 1) cfg_a[N+:$clog2(PE)] = pe; + for(int unsigned t = 0; t < 2**N-1; t++) begin + cfg_a[0+:N] <= t; + cfg_d <= THRESHS[c+pe][t]; + @(posedge clk); + end + end + end + cfg_d <= 'x; + + fork + // Intermittent configuration readback + while(!done) begin + cfg_en <= 0; + cfg_we <= 'x; + cfg_a <= 'x; + @(posedge clk); + if(($urandom()%41) == 0) begin + automatic addr_t addr = $urandom()%(N-1); + if(PE > 1) addr[N+:$clog2(PE)] = $urandom()%PE; + if(CF > 1) addr[N+$clog2(PE)+:$clog2(CF)] = $urandom()%CF; + + cfg_en <= 1; + cfg_we <= 0; + cfg_a <= addr; + @(posedge clk); + QC.push_back(addr); + end + end + + // AXI4Stream MST Writes input values + repeat(MST_STRM_WROUNDS) begin + automatic input_t dat; + + while(THROTTLED && ($urandom()%7 == 0)) @(posedge clk); + + std::randomize(dat); + ivld <= 1; + idat <= dat; + @(posedge clk iff irdy); + ivld <= 0; + idat <= 'x; + QW.push_back(dat); + end + join_any + done <= 1; + repeat((DEEP_PIPELINE+1)*N+6) @(posedge clk); + + assert(QW.size() == 0) else begin + $error("[%0d] Missing %0d outputs.", i, QW.size()); + $stop; + end + assert(QC.size() == 0) else begin + $error("[%0d] Missing %0d readback replies.", i, QC.size()); + $stop; + end + + $display("[%0d] Test completed: %0d errors in %0d tests.", i, error_cnt, MST_STRM_WROUNDS); + $display("============================================="); + term[i] <= 1; + end + + //- Readback Checker -------------- + always_ff @(posedge clk iff cfg_rack) begin + assert(QC.size()) begin + automatic addr_t addr = QC.pop_front(); + automatic int unsigned cnl = + (CF == 1? 0 : addr[N+$clog2(PE)+:$clog2(CF)] * PE) + + (PE == 1? 0 : addr[N+:$clog2(PE)]); + automatic logic [K-1:0] exp = THRESHS[cnl][addr[0+:N]]; + assert(cfg_q == exp) else begin + $error("[%0d] Readback mismatch on #%0d.%0d: %0d instead of %0d", i, cnl, addr[0+:N], cfg_q, exp); + $stop; + end + end + else begin + $error("[%0d] Spurious readback output.", i); + $stop; + end + end + + // Output Checker + int unsigned OCnl = 0; + always @(posedge clk) begin + if(rst) begin + OCnl <= 0; + ordy <= 1'b0; + end + else begin + if(!ordy || ovld) ordy <= ($urandom()%5 != 0) || !THROTTLED; + + if(ordy && ovld) begin + assert(QW.size()) begin + automatic input_t x = QW.pop_front(); + + for(int unsigned pe = 0; pe < PE; pe++) begin + automatic int unsigned cnl = OCnl + pe; + + $display("[%0d] Mapped CNL=%0d DAT=%3x -> #%2d", i, cnl, x[pe], odat[pe]); + assert( + ((odat[pe] == 0) || (sigord(THRESHS[cnl][odat[pe]-1]) <= sigord(x[pe]))) && + ((odat[pe] == 2**N-1) || (sigord(x[pe]) < sigord(THRESHS[cnl][odat[pe]]))) + ) else begin + $error("[%0d] Output error on presumed input CNL=%0d DAT=0x%0x -> #%0d", i, cnl, x[pe], odat[pe]); + error_cnt++; + $stop; + end + end + end + else begin + $error("[%0d] Spurious output.", i); + $stop; + end + + OCnl <= (OCnl + PE)%C; + end + end + end + + end : genTypes + +endmodule: thresholding_tb diff --git a/finn-rtllib/thresholding/xgui/thresholding_axi_v1_0.tcl b/finn-rtllib/thresholding/xgui/thresholding_axi_v1_0.tcl new file mode 100644 index 0000000000..338304fa40 --- /dev/null +++ b/finn-rtllib/thresholding/xgui/thresholding_axi_v1_0.tcl @@ -0,0 +1,187 @@ + +# Loading additional proc with user specified bodies to compute parameter values. +source [file join [file dirname [file dirname [info script]]] gui/thresholding_axi_v1_0.gtcl] + +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "ADDR_BITS" -parent ${Page_0} + ipgui::add_param $IPINST -name "BIAS" -parent ${Page_0} + ipgui::add_param $IPINST -name "C" -parent ${Page_0} + ipgui::add_param $IPINST -name "CF" -parent ${Page_0} + ipgui::add_param $IPINST -name "FPARG" -parent ${Page_0} + ipgui::add_param $IPINST -name "K" -parent ${Page_0} + ipgui::add_param $IPINST -name "N" -parent ${Page_0} + ipgui::add_param $IPINST -name "O_BITS" -parent ${Page_0} + set PE [ipgui::add_param $IPINST -name "PE" -parent ${Page_0}] + set_property tooltip {PE Count} ${PE} + ipgui::add_param $IPINST -name "SIGNED" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.ADDR_BITS { PARAM_VALUE.ADDR_BITS PARAM_VALUE.C PARAM_VALUE.PE PARAM_VALUE.N } { + # Procedure called to update ADDR_BITS when any of the dependent parameters in the arguments change + + set ADDR_BITS ${PARAM_VALUE.ADDR_BITS} + set C ${PARAM_VALUE.C} + set PE ${PARAM_VALUE.PE} + set N ${PARAM_VALUE.N} + set values(C) [get_property value $C] + set values(PE) [get_property value $PE] + set values(N) [get_property value $N] + set_property value [gen_USERPARAMETER_ADDR_BITS_VALUE $values(C) $values(PE) $values(N)] $ADDR_BITS +} + +proc validate_PARAM_VALUE.ADDR_BITS { PARAM_VALUE.ADDR_BITS } { + # Procedure called to validate ADDR_BITS + return true +} + +proc update_PARAM_VALUE.CF { PARAM_VALUE.CF PARAM_VALUE.C PARAM_VALUE.PE } { + # Procedure called to update CF when any of the dependent parameters in the arguments change + + set CF ${PARAM_VALUE.CF} + set C ${PARAM_VALUE.C} + set PE ${PARAM_VALUE.PE} + set values(C) [get_property value $C] + set values(PE) [get_property value $PE] + set_property value [gen_USERPARAMETER_CF_VALUE $values(C) $values(PE)] $CF +} + +proc validate_PARAM_VALUE.CF { PARAM_VALUE.CF } { + # Procedure called to validate CF + return true +} + +proc update_PARAM_VALUE.O_BITS { PARAM_VALUE.O_BITS PARAM_VALUE.BIAS PARAM_VALUE.N } { + # Procedure called to update O_BITS when any of the dependent parameters in the arguments change + + set O_BITS ${PARAM_VALUE.O_BITS} + set BIAS ${PARAM_VALUE.BIAS} + set N ${PARAM_VALUE.N} + set values(BIAS) [get_property value $BIAS] + set values(N) [get_property value $N] + set_property value [gen_USERPARAMETER_O_BITS_VALUE $values(BIAS) $values(N)] $O_BITS +} + +proc validate_PARAM_VALUE.O_BITS { PARAM_VALUE.O_BITS } { + # Procedure called to validate O_BITS + return true +} + +proc update_PARAM_VALUE.BIAS { PARAM_VALUE.BIAS } { + # Procedure called to update BIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.BIAS { PARAM_VALUE.BIAS } { + # Procedure called to validate BIAS + return true +} + +proc update_PARAM_VALUE.C { PARAM_VALUE.C } { + # Procedure called to update C when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C { PARAM_VALUE.C } { + # Procedure called to validate C + return true +} + +proc update_PARAM_VALUE.FPARG { PARAM_VALUE.FPARG } { + # Procedure called to update FPARG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPARG { PARAM_VALUE.FPARG } { + # Procedure called to validate FPARG + return true +} + +proc update_PARAM_VALUE.K { PARAM_VALUE.K } { + # Procedure called to update K when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.K { PARAM_VALUE.K } { + # Procedure called to validate K + return true +} + +proc update_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to update N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to validate N + return true +} + +proc update_PARAM_VALUE.PE { PARAM_VALUE.PE } { + # Procedure called to update PE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PE { PARAM_VALUE.PE } { + # Procedure called to validate PE + return true +} + +proc update_PARAM_VALUE.SIGNED { PARAM_VALUE.SIGNED } { + # Procedure called to update SIGNED when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SIGNED { PARAM_VALUE.SIGNED } { + # Procedure called to validate SIGNED + return true +} + + +proc update_MODELPARAM_VALUE.N { MODELPARAM_VALUE.N PARAM_VALUE.N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.N}] ${MODELPARAM_VALUE.N} +} + +proc update_MODELPARAM_VALUE.K { MODELPARAM_VALUE.K PARAM_VALUE.K } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.K}] ${MODELPARAM_VALUE.K} +} + +proc update_MODELPARAM_VALUE.C { MODELPARAM_VALUE.C PARAM_VALUE.C } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C}] ${MODELPARAM_VALUE.C} +} + +proc update_MODELPARAM_VALUE.PE { MODELPARAM_VALUE.PE PARAM_VALUE.PE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PE}] ${MODELPARAM_VALUE.PE} +} + +proc update_MODELPARAM_VALUE.SIGNED { MODELPARAM_VALUE.SIGNED PARAM_VALUE.SIGNED } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SIGNED}] ${MODELPARAM_VALUE.SIGNED} +} + +proc update_MODELPARAM_VALUE.FPARG { MODELPARAM_VALUE.FPARG PARAM_VALUE.FPARG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPARG}] ${MODELPARAM_VALUE.FPARG} +} + +proc update_MODELPARAM_VALUE.BIAS { MODELPARAM_VALUE.BIAS PARAM_VALUE.BIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.BIAS}] ${MODELPARAM_VALUE.BIAS} +} + +proc update_MODELPARAM_VALUE.CF { MODELPARAM_VALUE.CF PARAM_VALUE.CF } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CF}] ${MODELPARAM_VALUE.CF} +} + +proc update_MODELPARAM_VALUE.ADDR_BITS { MODELPARAM_VALUE.ADDR_BITS PARAM_VALUE.ADDR_BITS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ADDR_BITS}] ${MODELPARAM_VALUE.ADDR_BITS} +} + +proc update_MODELPARAM_VALUE.O_BITS { MODELPARAM_VALUE.O_BITS PARAM_VALUE.O_BITS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.O_BITS}] ${MODELPARAM_VALUE.O_BITS} +} diff --git a/src/finn/util/basic.py b/src/finn/util/basic.py index 1796738c58..0a6c0b39c9 100644 --- a/src/finn/util/basic.py +++ b/src/finn/util/basic.py @@ -30,6 +30,7 @@ import subprocess import sys import tempfile +from qonnx.util.basic import roundup_to_integer_multiple # test boards test_board_map = ["Pynq-Z1", "KV260_SOM", "ZCU104", "U250"] @@ -76,6 +77,11 @@ alveo_default_platform["U280"] = "xilinx_u280_gen3x16_xdma_1_202211_1" alveo_default_platform["U55C"] = "xilinx_u55c_gen3x16_xdma_3_202210_1" +# Create a joint part map, encompassing other boards too +part_map = {**pynq_part_map, **alveo_part_map} +part_map["VEK280"] = "xcve2802-vsvh1760-2MP-e-S" +part_map["VCK190"] = "xcvc1902-vsva2197-2MP-e-S" + def get_rtlsim_trace_depth(): """Return the trace depth for rtlsim via PyVerilator. Controllable @@ -228,3 +234,67 @@ def is_exe(fpath): return exe_file return None + + +def find_next_power_of_2(n): + """For any integer 'n', find the next greatest power of 2""" + # Negative values will loop infinitely below - return 0 + if n <= 0: + return 0 + # If '1' is requested, output will be '0' in the loop below, avoid this now. + elif n == 1: + return 2 # i.e. 2**1 + + # decrement 'n' (to handle cases when `n` itself is a power of 2) + n = n - 1 + + # loop until only one bit is left + while n & n - 1: + # unset rightmost bit + n = n & n - 1 + return n << 1 + + +mem_primitives_versal = { + "URAM_72x4096": (72, 4096), + "URAM_36x8192": (36, 8192), + "URAM_18x16384": (18, 16384), + "URAM_9x32768": (9, 32768), + "BRAM18_36x512": (36, 512), + "BRAM18_18x1024": (18, 1024), + "BRAM18_9x2048": (9, 2048), + "LUTRAM": (1, 64), +} + + +def get_memutil_alternatives( + req_mem_spec, mem_primitives=mem_primitives_versal, sort_min_waste=True +): + ret = [ + (primitive_name, memutil(req_mem_spec, primitive_spec)) + for (primitive_name, primitive_spec) in mem_primitives.items() + ] + if sort_min_waste: + ret = sorted(ret, key=lambda x: x[1][2]) + return ret + + +def memutil(req_mem_spec, primitive_spec): + """Computes how many instances of a memory primitive are necessary to + implemented a desired memory size, where req_mem_spec is the desired + size and the primitive_spec is the primitve size. The sizes are expressed + as tuples of (mem_width, mem_depth). Returns (primitive_count, efficiency, waste) + where efficiency in range [0,1] indicates how much of the total capacity is + utilized, and waste indicates how many bits of storage are wasted.""" + + req_width, req_depth = req_mem_spec + prim_width, prim_depth = primitive_spec + + match_width = roundup_to_integer_multiple(req_width, prim_width) + match_depth = roundup_to_integer_multiple(req_depth, prim_depth) + count_width = match_width // prim_width + count_depth = match_depth // prim_depth + count = count_depth * count_width + eff = (req_width * req_depth) / (count * prim_width * prim_depth) + waste = (count * prim_width * prim_depth) - (req_width * req_depth) + return (count, eff, waste) diff --git a/tests/util/test_basic.py b/tests/util/test_basic.py new file mode 100755 index 0000000000..97a8c50261 --- /dev/null +++ b/tests/util/test_basic.py @@ -0,0 +1,60 @@ +# Copyright (C) 2023, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import pytest + +import finn.util.basic as basic + + +@pytest.mark.util +def test_next_power_of_2(): + test_vector = [ + {"input": -2, "expected_result": 0}, + {"input": -1, "expected_result": 0}, + {"input": 0, "expected_result": 0}, + {"input": 1, "expected_result": 2}, + {"input": 2, "expected_result": 2}, + {"input": 3, "expected_result": 4}, + {"input": 4, "expected_result": 4}, + {"input": 7, "expected_result": 8}, + {"input": 8, "expected_result": 8}, + {"input": 11, "expected_result": 16}, + {"input": 15, "expected_result": 16}, + {"input": 16, "expected_result": 16}, + {"input": 18, "expected_result": 32}, + {"input": 27, "expected_result": 32}, + {"input": 31, "expected_result": 32}, + {"input": 32, "expected_result": 32}, + {"input": 42, "expected_result": 64}, + {"input": 65, "expected_result": 128}, + ] + + for test_dict in test_vector: + output = basic.find_next_power_of_2(test_dict["input"]) + assert output >= test_dict["input"] + assert output == test_dict["expected_result"] From 36603f69609e969fede24cba87d7d35f7bf78aaa Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Tue, 30 Jan 2024 21:05:04 +0000 Subject: [PATCH 435/665] [tests] add rtl impl style to threshold test Signed-off-by: aziz bahri --- .../test_fpgadataflow_thresholding.py | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_thresholding.py b/tests/fpgadataflow/test_fpgadataflow_thresholding.py index 43eca7b7c3..e88511f5cf 100644 --- a/tests/fpgadataflow/test_fpgadataflow_thresholding.py +++ b/tests/fpgadataflow/test_fpgadataflow_thresholding.py @@ -57,7 +57,7 @@ target_clk_ns = 5 -def make_single_thresholding_modelwrapper(T, pe, idt, odt, actval, mem_mode, n_inp_vecs): +def make_single_thresholding_modelwrapper(impl_style, T, pe, idt, odt, actval, mem_mode, n_inp_vecs): NumChannels = T.shape[0] inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, n_inp_vecs + [NumChannels]) @@ -80,6 +80,7 @@ def make_single_thresholding_modelwrapper(T, pe, idt, odt, actval, mem_mode, n_i ActVal=actval, mem_mode=mem_mode, numInputVectors=n_inp_vecs, + preferred_impl_style=impl_style ) graph = helper.make_graph( nodes=[Thresholding_node], @@ -111,10 +112,11 @@ def make_single_thresholding_modelwrapper(T, pe, idt, odt, actval, mem_mode, n_i @pytest.mark.parametrize("exec_mode", ["cppsim", "rtlsim"]) # memory mode @pytest.mark.parametrize("mem_mode", ["const", "decoupled"]) +@pytest.mark.parametrize("impl_style", ["rtl", "hls"]) @pytest.mark.fpgadataflow @pytest.mark.vivado @pytest.mark.slow -def test_fpgadataflow_thresholding(idt, act, nf, ich, exec_mode, mem_mode): +def test_fpgadataflow_thresholding(impl_style,idt, act, nf, ich, exec_mode, mem_mode): if nf == -1: nf = ich pe = ich // nf @@ -135,7 +137,7 @@ def test_fpgadataflow_thresholding(idt, act, nf, ich, exec_mode, mem_mode): else: actval = odt.min() - model = make_single_thresholding_modelwrapper(T, pe, idt, odt, actval, mem_mode, n_inp_vecs) + model = make_single_thresholding_modelwrapper(impl_style,T, pe, idt, odt, actval, mem_mode, n_inp_vecs) # calculate reference output # multithreshold util fxn wants NCHW input, not NHWC @@ -196,10 +198,10 @@ def test_fpgadataflow_thresholding(idt, act, nf, ich, exec_mode, mem_mode): assert np.isclose(exp_cycles, cycles_rtlsim, atol=10) assert exp_cycles != 0 - +@pytest.mark.parametrize("impl_style", ["rtl", "hls"]) @pytest.mark.fpgadataflow @pytest.mark.vivado -def test_runtime_thresholds_single_layer(): +def test_runtime_thresholds_single_layer(impl_style): n_inp_vecs = [1, 2, 2] mem_mode = "decoupled" act = DataType["INT4"] @@ -223,8 +225,10 @@ def test_runtime_thresholds_single_layer(): else: actval = odt.min() - model = make_single_thresholding_modelwrapper(T, pe, idt, odt, actval, mem_mode, n_inp_vecs) + model = make_single_thresholding_modelwrapper(impl_style, T, pe, idt, odt, actval, mem_mode, n_inp_vecs) model = model.transform(SpecializeLayers()) + assert model.graph.node[0].op_type == "Thresholding_" + str(impl_style) + op_inst = getCustomOp(model.graph.node[0]) op_inst.set_nodeattr("runtime_writeable_weights", 1) op_inst.make_weight_file(T, "decoupled_runtime", "old_weights.dat") From 8843c0e204c31ac82ee753bfee66526cf0277d94 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Tue, 30 Jan 2024 21:51:17 +0000 Subject: [PATCH 436/665] [CustomOp] Add Thresholding RTL Class --- .../custom_op/fpgadataflow/rtl/__init__.py | 2 + .../fpgadataflow/rtl/thresholding_rtl.py | 776 ++++++++++++++++++ .../fpgadataflow/specialize_layers.py | 1 - 3 files changed, 778 insertions(+), 1 deletion(-) create mode 100644 src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py diff --git a/src/finn/custom_op/fpgadataflow/rtl/__init__.py b/src/finn/custom_op/fpgadataflow/rtl/__init__.py index 914c033584..ae1f4e6acf 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/__init__.py +++ b/src/finn/custom_op/fpgadataflow/rtl/__init__.py @@ -34,6 +34,7 @@ StreamingDataWidthConverter_rtl, ) from finn.custom_op.fpgadataflow.rtl.streamingfifo_rtl import StreamingFIFO_rtl +from finn.custom_op.fpgadataflow.rtl.thresholding_rtl import Thresholding_rtl custom_op = dict() @@ -43,3 +44,4 @@ custom_op["FMPadding_rtl"] = FMPadding_rtl custom_op["StreamingDataWidthConverter_rtl"] = StreamingDataWidthConverter_rtl custom_op["StreamingFIFO_rtl"] = StreamingFIFO_rtl +custom_op["Thresholding_rtl"] = Thresholding_rtl diff --git a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py new file mode 100644 index 0000000000..63abdd1545 --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py @@ -0,0 +1,776 @@ +# Copyright (C) 2022, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import math +import numpy as np +import os +import shutil +import warnings +from pyverilator.util.axi_utils import rtlsim_multi_io +from qonnx.core.datatype import DataType +from qonnx.util.basic import ( + interleave_matrix_outer_dim_from_partitions, + roundup_to_integer_multiple, +) + +from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp +from finn.util.basic import ( + find_next_power_of_2, + get_memutil_alternatives, + get_rtlsim_trace_depth, + make_build_dir, + mem_primitives_versal, + pyverilate_get_liveness_threshold_cycles, +) +from finn.util.data_packing import ( + npy_to_rtlsim_input, + pack_innermost_dim_as_hex_string, + rtlsim_output_to_npy, +) + +try: + from pyverilator import PyVerilator +except ModuleNotFoundError: + PyVerilator = None + +"""@package Thresholding_rtl +- ONNX i/o tensor shape assumptions for Thresholding: +- input 0 is the input tensor, shape (..., NumChannels) +- input 1 is the threshold tensor, shape (NumChannels, n_thres) +- output 0 is the output tensor, shape (..., NumChannels) - same as input +- the '...' here can be any shape (representing groups of vectors) + +This module creates an RTL IP, HLS is not supported. See 'thresholding_batch' +for a HLS equivalent. +""" + + +class Thresholding_rtl(HLSCustomOp): + """Class that corresponds to finn-rtllib 'thresholding' function.""" + + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) + + def get_nodeattr_types(self): + my_attrs = { + # parallelization; channels thresholded per cycle + "PE": ("i", True, 0), + # number of channels (each may have different thresholds) + "NumChannels": ("i", True, 0), + # number of steps in thresholding function. Used only in decoupled mode + "numSteps": ("i", True, 1), + # FINN DataTypes for inputs, outputs + "inputDataType": ("s", True, ""), + "weightDataType": ("s", True, ""), + "outputDataType": ("s", True, ""), + # number of input vectors, examples: + # [1] is a single vector (like a FC layer with batch=1) + # [4] is four vectors (like a FC layer with batch=4) + # [1, 4, 4] is four * four vectors (like a conv layer with batch=1) + "numInputVectors": ("ints", False, [1]), + # name of the top module in verilog template. Used by PyVerilator + # and IPI generation + "gen_top_module": ("s", False, ""), + # bias to be applied to outputs of the node + "activation_bias": ("i", False, 0), + # whether weights (thresholds) will be + # writable through an AXI-lite interface during runtime + # 1 for enabled, 0 for disabled. + "runtime_writeable_weights": ("i", False, 0, {0, 1}), + # memory depth triggers for threshold storage + "depth_trigger_uram": ("i", False, 0), + "depth_trigger_bram": ("i", False, 0), + # enable uniform thres optimization + # doesn't actually do anything yet, only + # for resource estimations + "uniform_thres": ("i", False, 0, {0, 1}), + # enable deep pipelining for easier timing closure + # setting to 0 may save some FFs but otherwise leave on + "deep_pipeline": ("i", False, 1, {0, 1}), + } + my_attrs.update(super().get_nodeattr_types()) + return my_attrs + + def get_pe_mem_geometries(self): + pe = self.get_nodeattr("PE") + wdt = self.get_weight_datatype() + wdt_bits = wdt.bitwidth() + odt = self.get_output_datatype() + odt_bits = odt.bitwidth() + t_channels = self.get_nodeattr("NumChannels") + cf = t_channels / pe + is_uniform = self.get_nodeattr("uniform_thres") + if is_uniform: + ret = [(odt_bits - x, cf * (2**x)) for x in range(1, odt_bits)] + else: + ret = [(wdt_bits, (cf) * 2**x) for x in range(odt_bits)] + return ret + + def get_memory_estimate(self): + res_dict = {} + depth_trigger_bram = self.get_nodeattr("depth_trigger_bram") + depth_trigger_uram = self.get_nodeattr("depth_trigger_uram") + pe = self.get_nodeattr("PE") + ret = self.get_pe_mem_geometries() + for mem_cfg in ret: + (width, depth) = mem_cfg + primitives = mem_primitives_versal + if depth_trigger_bram != 0 or depth_trigger_uram != 0: + if depth >= depth_trigger_bram and depth < depth_trigger_uram: + primitives = {k: v for (k, v) in mem_primitives_versal.items() if "BRAM" in k} + elif depth >= depth_trigger_uram: + primitives = {k: v for (k, v) in mem_primitives_versal.items() if "URAM" in k} + alts = get_memutil_alternatives(mem_cfg, primitives) + primary_alt = alts[0] + res_type = primary_alt[0].split("_")[0] + res_count, eff, waste = primary_alt[1] + res_dict[res_type] = res_dict.get(res_type, 0) + pe * res_count + return res_dict + + def calc_tmem(self): + """Calculates and returns TMEM.""" + num_channels = self.get_nodeattr("NumChannels") + pe = self.get_nodeattr("PE") + return num_channels // pe + + def make_shape_compatible_op(self, model): + oshape = self.get_normal_output_shape() + return super().make_const_shape_op(oshape) + + def infer_node_datatype(self, model): + """Used for FINN DataType inference: set the output tensors' datatypes + accordingly for this node""" + node = self.onnx_node + idt = model.get_tensor_datatype(node.input[0]) + if idt != self.get_input_datatype(): + warn_str = "inputDataType changing for %s: %s -> %s " % ( + node.name, + str(self.get_input_datatype().name), + str(idt.name), + ) + warnings.warn(warn_str) + self.set_nodeattr("inputDataType", idt.name) + # set output datatype from property + odt = self.get_output_datatype() + model.set_tensor_datatype(node.output[0], odt) + + def verify_node(self): + """Required by the FINN nalysis module. Checks if custom ops in graph + are correctly built, with all attributes and inputs.""" + return [] + + def bram_estimation(self): + res_dict = self.get_memory_estimate() + return res_dict.get("BRAM", 0) + + def uram_estimation(self): + res_dict = self.get_memory_estimate() + return res_dict.get("URAM", 0) + + def lut_estimation(self): + res_dict = self.get_memory_estimate() + return res_dict.get("LUTRAM", 0) + + def get_input_datatype(self, ind=0): + return DataType[self.get_nodeattr("inputDataType")] + + def get_output_datatype(self, ind=0): + return DataType[self.get_nodeattr("outputDataType")] + + def get_weight_datatype(self): + """The term 'weights' and 'thresholds' are used interchangably in this class.""" + return DataType[self.get_nodeattr("weightDataType")] + + def minimize_accumulator_width(self, model): + "Minimize threshold width ('accumulator width' here due to convention)" + thresholds = model.get_initializer(self.onnx_node.input[1]) + threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds) + min_threshold = thresholds.min() + max_threshold = thresholds.max() + min_input = self.get_input_datatype().min() + max_input = self.get_input_datatype().max() + # get range required by threshold values + tdt_min = min(min_input, min_threshold) + tdt_max = max(max_input, max_threshold) + if tdt_min < 0: + if abs(tdt_min) > tdt_max: + tdt = DataType.get_smallest_possible(tdt_min) + else: + tdt = DataType.get_smallest_possible(-tdt_max - 1) + else: + tdt = DataType.get_smallest_possible(tdt_max) + assert np.vectorize(tdt.allowed)( + threshold_tensor + ).all(), "Thresholds can't be expressed with type %s" % str(tdt) + self.set_nodeattr("weightDataType", tdt.name) + return DataType[self.get_nodeattr("weightDataType")] + + def get_instream_width(self, ind=0): + i_bits = self.get_input_datatype().bitwidth() + return i_bits * self.get_nodeattr("PE") + + def get_outstream_width(self, ind=0): + o_bits = self.get_output_datatype().bitwidth() + return o_bits * self.get_nodeattr("PE") + + def get_weightstream_width(self): + """Returns weight stream width""" + pe = self.get_nodeattr("PE") + wp = self.get_weight_datatype().bitwidth() + n_thres_steps = self.get_nodeattr("numSteps") + w_width = pe * wp * n_thres_steps + return w_width + + def get_folded_input_shape(self, ind=0): + fold = self.calc_tmem() + pe = self.get_nodeattr("PE") + vecs = list(self.get_nodeattr("numInputVectors")) + folded_input_shape = tuple(vecs + [fold, pe]) + return folded_input_shape + + def get_folded_output_shape(self, ind=0): + # same shape as input + return self.get_folded_input_shape() + + def get_normal_input_shape(self, ind=0): + num_channels = self.get_nodeattr("NumChannels") + vecs = list(self.get_nodeattr("numInputVectors")) + normal_input_shape = tuple(vecs + [num_channels]) + return normal_input_shape + + def get_normal_output_shape(self, ind=0): + # same shape as input + return self.get_normal_input_shape() + + def get_number_output_values(self): + return np.prod(self.get_folded_output_shape()[:-1]) + + def get_exp_cycles(self): + # Channels/PE * batch size * fmdim * fmdim + return np.prod(self.get_folded_output_shape()[:-1]) + + def get_hls_compatible_threshold_tensor(self, orig_thres_matrix): + """Convert the original numpy weight matrix orig_weight_matrix into + a form suitable for passing to the hlslib call: + * ensure MH % PE == 0 + * for unsigned inputs, ensure thresholds are positive + * interleave rows between PEs + * reshape into (PE, TMEM, n_thres_steps) and return + """ + mh = self.get_nodeattr("NumChannels") + pe = self.get_nodeattr("PE") + tmem = mh // pe + assert mh % pe == 0, "Requirement NumChannels divisable by PE is violated." + assert ( + orig_thres_matrix.ndim == 2 + ), """Threshold matrix dimension is + not as expected (2).""" + n_thres_steps = orig_thres_matrix.shape[1] + assert n_thres_steps == self.get_nodeattr("numSteps"), "Mismatch in threshold steps" + if not self.get_input_datatype().signed(): + # ensure all thresholds are nonnegative + assert (orig_thres_matrix >= 0).all() + # ensure all thresholds are integer + assert np.equal(np.mod(orig_thres_matrix, 1), 0).all(), "Need int threshold tensor" + ret = orig_thres_matrix + # ensure channels = mh , duplicating if necessary + if ret.shape[0] == 1: + ret = np.tile(ret, (mh, 1)) + assert ret.shape[0] == mh, "Channels of threshold matrix are not as expected (mh)" + # distribute rows between PEs + ret = interleave_matrix_outer_dim_from_partitions(ret, pe) + assert ( + ret.shape[0] == pe + ), """First dimension after distribution of the + rows between PEs is not as expected (pe)""" + assert ( + ret.shape[1] == tmem + ), """Second dimension after distribution of the + rows between PEs is not as expected (tmem)""" + assert ( + ret.shape[2] == n_thres_steps + ), """Third dimension after distribution of the + rows between PEs is not as expected (n_thres_steps)""" + return ret.reshape(1, pe, tmem, n_thres_steps) + + def get_all_meminit_filenames(self, abspath=False): + "Return a list of all .dat memory initializer files used for this node" + dat_files = [] + t_path = self.get_nodeattr("code_gen_dir_ipgen") if abspath else "." + pe = self.get_nodeattr("PE") + output_data_type = self.get_nodeattr("outputDataType") # output precision + o_bitwidth = DataType[output_data_type].bitwidth() + for stage in range(o_bitwidth): + for pe_value in range(pe): + thresh_file = t_path + "/%s_threshs_%s_%s.dat" % ( + self.onnx_node.name, + pe_value, + stage, + ) + dat_files.append(thresh_file) + return dat_files + + def prepare_codegen_rtl_values(self, model): + """All dictionary values produced in this function are to replace + their key value(s) in the RTL template files""" + code_gen_dict = {} + + # TODO check for sortedness and size here? + # RTL component currently always expects 2^N-1 thresholds, but + # sometimes we have fewer due to e.g. narrow range quantization + thresholds = model.get_initializer(self.onnx_node.input[1]) + # add dummy dimension as final dimension (that's what gets packed with next call) + thresholds = np.expand_dims(thresholds, axis=-1) + wdt = self.get_weight_datatype() + bw_hexdigit = roundup_to_integer_multiple(wdt.bitwidth(), 4) + t_packed = pack_innermost_dim_as_hex_string( + thresholds, + wdt, + bw_hexdigit, + prefix="", + ) + + t_path = self.get_nodeattr("code_gen_dir_ipgen") + pe = self.get_nodeattr("PE") + output_data_type = self.get_nodeattr("outputDataType") # output precision + o_bitwidth = DataType[output_data_type].bitwidth() + num_channels = self.get_nodeattr("NumChannels") # number of channels + + channel_fold = int(num_channels / pe) + + for stage in range(o_bitwidth): + sn = o_bitwidth - stage - 1 + for pe_value in range(pe): + thresh_file = t_path + "/%s_threshs_%s_%s.dat" % ( + self.onnx_node.name, + pe_value, + stage, + ) + threshs = np.zeros([channel_fold * (2**stage)], dtype="object") + for ch in range(channel_fold): + for i in range(2**stage): + threshs[(ch << stage) + i] = t_packed[ch * pe + pe_value][ + (i << (o_bitwidth - stage)) + 2**sn - 1 + ] + with open(thresh_file, "w") as f: + for val in threshs: + f.write(val + "\n") + code_gen_dict["$THRESHOLDS_PATH$"] = ['"./%s_"' % self.onnx_node.name] + + # Identify the module name + code_gen_dict["$MODULE_NAME_AXI_WRAPPER$"] = [ + self.get_verilog_top_module_name() + "_axi_wrapper" + ] + # Set the top module name - AXI wrapper + code_gen_dict["$TOP_MODULE$"] = code_gen_dict["$MODULE_NAME_AXI_WRAPPER$"] + + # Identify the module variables + input_data_type = self.get_nodeattr("inputDataType") # input/threshold precision + bias = self.get_nodeattr("activation_bias") # activation bias value + i_bitwidth = DataType[input_data_type].bitwidth() + + code_gen_dict["$N$"] = [str(o_bitwidth)] # output precision - convert bitwidth to string + code_gen_dict["$M$"] = [ + str(i_bitwidth) + ] # input/threshold precision - convert bitwidth to string + code_gen_dict["$C$"] = [str(num_channels)] # number of channels + code_gen_dict["$BIAS$"] = [str(bias)] # activation bias value + code_gen_dict["$PE$"] = [str(pe)] # requires C = M*PE + + # Is the input datatype signed or unsigned? + # The thresholding core needs to know this when comparing weights to inputs + if self.get_input_datatype().signed(): + code_gen_dict["$SIGNED$"] = [str(1)] + else: + code_gen_dict["$SIGNED$"] = [str(0)] + + if bias >= 0: + o_bits = math.ceil(math.log2(2**o_bitwidth + bias)) + else: + o_bits = 1 + math.ceil( + math.log2(-bias if -bias >= 2 ** (o_bitwidth - 1) else 2**o_bitwidth + bias) + ) + + code_gen_dict["$O_BITS$"] = [str(int(o_bits))] + + rt_weights = self.get_nodeattr("runtime_writeable_weights") + code_gen_dict["$USE_AXILITE$"] = [str(rt_weights)] + + depth_trigger_uram = self.get_nodeattr("depth_trigger_uram") + depth_trigger_bram = self.get_nodeattr("depth_trigger_bram") + deep_pipeline = self.get_nodeattr("deep_pipeline") + code_gen_dict["$DEPTH_TRIGGER_URAM$"] = [str(depth_trigger_uram)] + code_gen_dict["$DEPTH_TRIGGER_BRAM$"] = [str(depth_trigger_bram)] + code_gen_dict["$DEEP_PIPELINE$"] = [str(deep_pipeline)] + return code_gen_dict + + def get_rtl_file_list(self): + """Thresholding binary search RTL file list""" + return [ + "axilite_if.v", + "thresholding.sv", + "thresholding_axi.sv", + "thresholding_template_wrapper.v", + ] + + def get_rtl_file_paths(self): + """Get full path of all RTL files""" + rtl_root_dir = os.environ["FINN_ROOT"] + "/finn-rtllib/thresholding/hdl/" + rtl_file_list = self.get_rtl_file_list() + rtl_file_paths = [rtl_root_dir + file for file in rtl_file_list] + return rtl_file_paths + + def get_rtl_template_data(self, path): + """Return RTL file contents as a template""" + with open(path, "r") as f: + template = f.read() + return template + + def fill_in_rtl_template_data(self, replace_dict, template_data): + """Use attribute values to finn in RTL template placeholders""" + template_data_cp = template_data + for key in replace_dict: + replacement_line = "\n".join(replace_dict[key]) + template_data_cp = template_data_cp.replace(key, replacement_line) + return template_data_cp + + def dump_rtl_data(self, dest_dir, filename, data): + """Dump filled-in-template RTL files for future synthesis step""" + # when generating template files, handle a special case: + # if the filename contains the word "template", replace that + # with the node name to distinguish between instances + filename = filename.replace("template", self.onnx_node.name) + with open(os.path.join(dest_dir, filename), "w") as f: + f.write(data) + return + + def generate_hdl(self, model): + """Prepare HDL files from templates for synthesis""" + # Generate a dictionary of values to put in RTL template + code_gen_dict = self.prepare_codegen_rtl_values(model) + + # Retrieve the destination directory for the final RTL files + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + + for rtl_file_path in self.get_rtl_file_paths(): + # read in original RTL template file + template_data = self.get_rtl_template_data(rtl_file_path) + # apply code generation to templates + data = self.fill_in_rtl_template_data(code_gen_dict, template_data) + # dump filled-in template to destination directory for compilation + file_only_path = rtl_file_path.split("/")[-1] + self.dump_rtl_data(code_gen_dir, file_only_path, data) + + # Before we return - set the 'gen_top_module' attribute for use later + # by PyVerilator and IPI generation + self.set_nodeattr("gen_top_module", code_gen_dict["$TOP_MODULE$"][0]) + return + + def code_generation_ipgen(self, model, fpgapart, clk): + self.generate_hdl(model) + + # set ipgen_path and ip_path so that HLS-Synth transformation + # and stich_ip transformation do not complain + # i.e. during the HLSSynthIP() transformation + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + self.set_nodeattr("ipgen_path", code_gen_dir) + self.set_nodeattr("ip_path", code_gen_dir) + return + + def prepare_rtlsim(self): + """Creates a Verilator emulation library for the RTL code generated + for this node, sets the rtlsim_so attribute to its path and returns + a PyVerilator wrapper around it.""" + + if PyVerilator is None: + raise ImportError("Installation of PyVerilator is required.") + + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + verilog_paths = [code_gen_dir] + verilog_files = [x.replace("template", self.onnx_node.name) for x in self.get_rtl_file_list()] + dat_files = self.get_all_meminit_filenames(abspath=True) + single_src_dir = make_build_dir("pyverilator_" + self.onnx_node.name + "_") + for dat_file in dat_files: + shutil.copy(dat_file, single_src_dir) + + # build the Verilator emulation library + sim = PyVerilator.build( + verilog_files, + build_dir=single_src_dir, + verilog_path=verilog_paths, + trace_depth=get_rtlsim_trace_depth(), + top_module_name=self.get_nodeattr("gen_top_module"), + auto_eval=False, + ) + + # save generated lib filename in attribute + self.set_nodeattr("rtlsim_so", sim.lib._name) + return sim + + def execute_node(self, context, graph): + # Perform input checks + if self.get_nodeattr("exec_mode") != "rtlsim": + raise Exception( + "Invalid exec_mode value: {}; exec_mode must be set to '{}'".format( + self.get_nodeattr("exec_mode"), "rtlsim" + ) + ) + mode = self.get_nodeattr("exec_mode") + if mode == "cppsim": + raise Exception("cppsim not possible for RTL Thresholding, please set exec_mode to rtlsim") + elif mode == "rtlsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + node = self.onnx_node + + # create a npy file fore each input of the node (in_ind is input index) + in_ind = 0 + for inputs in node.input: + # it is assumed that the first input of the node is the data input + # the second input are the thresholds + if in_ind == 0: + assert ( + str(context[inputs].dtype) == "float32" + ), """Input datatype is + not float32 as expected.""" + expected_inp_shape = self.get_folded_input_shape() + reshaped_input = context[inputs].reshape(expected_inp_shape) + + if self.get_input_datatype() == DataType["BIPOLAR"]: + # store bipolar activations as binary + reshaped_input = (reshaped_input + 1) / 2 + export_idt = DataType["BINARY"] + else: + export_idt = self.get_input_datatype() + + # make copy before saving the array + reshaped_input = reshaped_input.copy() + np.save( + os.path.join(code_gen_dir, "input_{}.npy".format(in_ind)), + reshaped_input, + ) + elif in_ind > 2: + raise Exception("Unexpected input found for Thresholding_rtl") + in_ind += 1 + + # Create a PyVerilator wrapper of the RTLSim .so + sim = self.get_rtlsim() + nbits = self.get_instream_width() + inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) + io_names = self.get_verilog_top_module_intf_names() + istream_name = io_names["s_axis"][0][0] + ostream_name = io_names["m_axis"][0][0] + io_dict = { + "inputs": {istream_name: inp}, + "outputs": {ostream_name: []}, + } + self.rtlsim_multi_io(sim, io_dict) + output = io_dict["outputs"][ostream_name] + + # Manage output data + odt = self.get_output_datatype() + target_bits = odt.bitwidth() + packed_bits = self.get_outstream_width() + out_npy_path = "{}/output.npy".format(code_gen_dir) + out_shape = self.get_folded_output_shape() + + rtlsim_output_to_npy(output, out_npy_path, odt, out_shape, packed_bits, target_bits) + + # load and reshape output + output = np.load(out_npy_path) + oshape = self.get_normal_output_shape() + output = np.asarray([output], dtype=np.float32).reshape(*oshape) + context[node.output[0]] = output + return + + def hls_sname(self): + """Get the naming convention used by Vitis HLS for stream signals + Example: the TDATA for a stream called "out" would be out_V_TDATA. + """ + # no additional prefix/suffix in interface names since this is an RTL component + return "" + + def rtlsim_multi_io(self, sim, io_dict): + "Run rtlsim for this node, supports multiple i/o streams." + + rtlsim_so = self.get_nodeattr("rtlsim_so") + so_dir = os.path.dirname(os.path.realpath(rtlsim_so)) + olcwd = os.getcwd() + os.chdir(so_dir) + + # signal name prefix + # TODO if the interface names on this component get standardized, + # it won't need its own rtlsim_multi_io variant anymore and can just + # use the base class one + sname = "_" + + trace_file = self.get_nodeattr("rtlsim_trace") + if trace_file == "default": + trace_file = self.onnx_node.name + ".vcd" + num_out_values = self.get_number_output_values() + total_cycle_count = rtlsim_multi_io( + sim, + io_dict, + num_out_values, + trace_file=trace_file, + sname=sname, + do_reset=True, + liveness_threshold=pyverilate_get_liveness_threshold_cycles(), + ) + self.set_nodeattr("cycles_rtlsim", total_cycle_count) + os.chdir(olcwd) + + def code_generation_ipi(self): + """Constructs and returns the TCL commands for node instantiation as an RTL + block.""" + rtl_file_list = [x.replace("template", self.onnx_node.name) for x in self.get_rtl_file_list()] + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + source_target = "./ip/verilog/rtl_ops/%s" % self.onnx_node.name + cmd = ["file mkdir %s" % source_target] + + for rtl_file in rtl_file_list: + cmd.append( + "add_files -copy_to %s -norecurse %s" + % (source_target, os.path.join(code_gen_dir, rtl_file)) + ) + + # Create an RTL block, not an IP core (-type ip) + cmd.append( + "create_bd_cell -type module -reference %s %s" + % (self.get_nodeattr("gen_top_module"), self.onnx_node.name) + ) + + return cmd + + def get_verilog_top_module_intf_names(self): + """Return a dict of names of input and output interfaces. + The keys reflect the protocols each interface implements: + 'clk', 'rst', 'm_axis', 's_axis', 'aximm', 'axilite'. + Values are lists of tuples (axis, aximm) or names (axilite): + 'axis' tuples correspond to the list of node inputs in order, + each tuple is (interface_name, interface_width_bits). + axilite always assumed to be 32 bits and is not tuple (name only). + Each block must have at most one aximm and one axilite.""" + + intf_names = {} + intf_names["clk"] = ["ap_clk"] + intf_names["rst"] = ["ap_rst_n"] + intf_names["s_axis"] = [("in0_V", self.get_instream_width_padded())] + intf_names["m_axis"] = [("out_V", self.get_outstream_width_padded())] + intf_names["aximm"] = [] + intf_names["axilite"] = [] + intf_names["ap_none"] = [] + if self.get_nodeattr("runtime_writeable_weights") == 1: + intf_names["axilite"] = ["s_axilite"] + + return intf_names + + def get_dynamic_config(self, model, address_stride=1): + """Returns a configuration dictionary containing axilite write commands + in order to program the thresholds into the RTL core during runtime. + The default address stride for the weights is 1 byte.""" + + thresholds = model.get_initializer(self.onnx_node.input[1]) + num_channels, num_weights_per_channel = thresholds.shape + + weight_addr_boundary = find_next_power_of_2(num_weights_per_channel) + # Make sure that the next power of 2 (output) is greater than the input + assert weight_addr_boundary >= num_weights_per_channel + + config = {} + channel_cntr = 0 + wdt = self.get_weight_datatype() + bw_hexdigit = roundup_to_integer_multiple(wdt.bitwidth(), 4) + for channel in thresholds: + channel_start_addr = channel_cntr * weight_addr_boundary * address_stride + weight_cntr = 0 + addr = 0 + for weight in channel: + key_name = "{}_{}{}_{}{}".format( + "axilite", "ch", str(channel_cntr), "w", str(weight_cntr) + ) + config[key_name] = ( + channel_start_addr + addr, + int( + str( + pack_innermost_dim_as_hex_string( + [weight], + wdt, + bw_hexdigit, + ) + ), + 0, + ), + ) + + weight_cntr += 1 + addr += address_stride + + channel_cntr += 1 + + return config + + def ipgen_singlenode_code(self): + """Normally: Builds the bash script for IP generation.""" + """This is needed for the HLSSynthIP() transformation. + This is an IP, not a HLS node, so therefore provide an empty hook + to prevent any HLS synthesis.""" + pass + + def global_includes(self): + pass + + def defines(self, var): + pass + + def read_npy_data(self): + pass + + def strm_decl(self): + pass + + def docompute(self): + pass + + def dataoutstrm(self): + pass + + def save_as_npy(self): + pass + + def blackboxfunction(self): + pass + + def pragmas(self): + pass diff --git a/src/finn/transformation/fpgadataflow/specialize_layers.py b/src/finn/transformation/fpgadataflow/specialize_layers.py index 7fda50c965..31da3756d3 100644 --- a/src/finn/transformation/fpgadataflow/specialize_layers.py +++ b/src/finn/transformation/fpgadataflow/specialize_layers.py @@ -39,7 +39,6 @@ restricted_layers = [] restricted_layers.append("MatrixVectorActivation") restricted_layers.append("VectorVectorActivation") -restricted_layers.append("Thresholding") def _determine_impl_style(node): From 23c3f82a87a405d996ad6e3b096ca9352314adf1 Mon Sep 17 00:00:00 2001 From: johnnoel Date: Wed, 31 Jan 2024 10:36:52 +0000 Subject: [PATCH 437/665] [Tests] Temporarily re-enable SWG exception for bnn_w2_a2_cnv_Pynq-Z1 test --- tests/end2end/test_end2end_bnn_pynq.py | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index b296dad827..9fb41ec78e 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -653,7 +653,13 @@ def test_set_fifo_depths(self, topology, wbits, abits, board): prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, "ipgen_" + board) model = load_test_checkpoint_or_skip(prev_chkpt_name) test_fpga_part = get_build_env(board, target_clk_ns)["part"] - model = model.transform(InsertAndSetFIFODepths(test_fpga_part, target_clk_ns)) + if topology == "cnv" and wbits == 2 and abits == 2 and board == "Pynq-Z1": + # Enabling swg_exception for this single test case. Disabling the exception results in a design + # that exceeds the resources of the Pynq-Z1 board. In future this should be revisited and handled + # correctly as the swg_exception is poorly justified. + model = model.transform(InsertAndSetFIFODepths(test_fpga_part, target_clk_ns, swg_exception=True)) + else: + model = model.transform(InsertAndSetFIFODepths(test_fpga_part, target_clk_ns)) fifo_layers = model.get_nodes_by_op_type("StreamingFIFO") assert len(fifo_layers) > 0 model.save(get_checkpoint_name(topology, wbits, abits, "fifodepth_" + board)) From 7b272bde95a4be015a1f8b0023e96d30d3f3d17c Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 31 Jan 2024 10:48:19 +0000 Subject: [PATCH 438/665] [CustomOp] Clean up tests and move dynamic mode in swg hw abstraction layer --- .../fpgadataflow/convolutioninputgenerator.py | 3 +++ .../fpgadataflow/rtl/convolutioninputgenerator_rtl.py | 3 --- .../transformation/fpgadataflow/specialize_layers.py | 9 ++++++++- ...test_fpgadataflow_convinputgenerator_rtl_dynamic.py | 10 +++++++--- tests/fpgadataflow/test_fpgadataflow_dwc.py | 1 + 5 files changed, 19 insertions(+), 7 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py index 3be0a117a8..96f49069c7 100644 --- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py +++ b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py @@ -76,6 +76,9 @@ def get_nodeattr_types(self): "parallel_window": ("i", False, 0, {0, 1}), # 1D (True) or 2D (False) spatial data "is1D": ("i", False, 0), + # Enable reprogrammable implementation to change FM dimensions, + # stride, or dilation during runtime (requires parallel_window = 0) + "dynamic_mode": ("i", False, 0, {0, 1}), } my_attrs.update(super().get_nodeattr_types()) return my_attrs diff --git a/src/finn/custom_op/fpgadataflow/rtl/convolutioninputgenerator_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/convolutioninputgenerator_rtl.py index ba3921745f..6f4bafd73a 100755 --- a/src/finn/custom_op/fpgadataflow/rtl/convolutioninputgenerator_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/convolutioninputgenerator_rtl.py @@ -71,9 +71,6 @@ def get_nodeattr_types(self): my_attrs = { # additional parallelization parameter - not yet implemented "M": ("i", False, 1), - # Enable reprogrammable implementation to change FM dimensions, - # stride, or dilation during runtime (requires parallel_window = 0) - "dynamic_mode": ("i", False, 0, {0, 1}), } my_attrs.update(ConvolutionInputGenerator.get_nodeattr_types(self)) my_attrs.update(RTLBackend.get_nodeattr_types(self)) diff --git a/src/finn/transformation/fpgadataflow/specialize_layers.py b/src/finn/transformation/fpgadataflow/specialize_layers.py index 7fda50c965..d06f7d524e 100644 --- a/src/finn/transformation/fpgadataflow/specialize_layers.py +++ b/src/finn/transformation/fpgadataflow/specialize_layers.py @@ -163,10 +163,17 @@ def _dwc_determine_impl_style(node): def _swg_hls_possible(node): + # there are some constraints to + # the HLS variant of the SWG + # first constraint to check is + # if user has set dynamic_mode to 1 + # this is only supported in rtl variant + swg = getCustomOp(node) + if swg.get_nodeattr("dynamic_mode"): + return False # the 2D HLS implementation for SWG # can only be used for square inputs # and no dilation - swg = getCustomOp(node) if swg.get_nodeattr("is1D"): return True else: diff --git a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py index f5a06316e2..368bdbb2ad 100644 --- a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py +++ b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py @@ -49,6 +49,7 @@ import finn.core.onnx_exec as oxe import finn.transformation.fpgadataflow.convert_to_hls_layers as to_hls +import finn.transformation.fpgadataflow.convert_to_hw_layers as to_hw import finn.transformation.streamline.absorb as absorb from finn.core.onnx_exec import execute_onnx from finn.core.rtlsim_exec import rtlsim_exec @@ -60,6 +61,7 @@ from finn.transformation.fpgadataflow.insert_dwc import InsertDWC from finn.transformation.fpgadataflow.insert_fifo import InsertFIFO from finn.transformation.fpgadataflow.prepare_ip import PrepareIP +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers from finn.util.basic import pyverilate_get_liveness_threshold_cycles @@ -404,7 +406,7 @@ def make_single_slidingwindow_modelwrapper( ) SlidingWindow_node = helper.make_node( - "ConvolutionInputGenerator_rtl", + "ConvolutionInputGenerator", ["inp"], ["outp"], domain="finn.custom_op.fpgadataflow", @@ -518,9 +520,11 @@ def test_fpgadataflow_slidingwindow_rtl_dynamic( dw=dw, ) + model = model.transform(SpecializeLayers()) # Simulate using stitched-ip-rtlsim so we can use existing infrastructure # that supports hook functions to re-program configuration before rtlsim model = model.transform(InsertFIFO(True)) # required for proper simulation + model = model.transform(SpecializeLayers()) model = model.transform(GiveUniqueNodeNames()) model = model.transform(PrepareIP("xc7z020clg400-1", 5)) model = model.transform(HLSSynthIP()) @@ -547,7 +551,7 @@ def test_fpgadataflow_slidingwindow_rtl_dynamic( configs = [("s_axilite_0_", config)] # Also update FIFO nodes and corresponding tensors - fifo_node = model.get_nodes_by_op_type("StreamingFIFO")[0] + fifo_node = model.get_nodes_by_op_type("StreamingFIFO_rtl")[0] fifo_inst = getCustomOp(fifo_node) shape = fifo_inst.get_nodeattr("folded_shape") shape[1] = ifm_dim_h @@ -555,7 +559,7 @@ def test_fpgadataflow_slidingwindow_rtl_dynamic( fifo_inst.set_nodeattr("folded_shape", shape) update_tensor_dim(model, fifo_node.input[0], ifm_dim) - fifo_node = model.get_nodes_by_op_type("StreamingFIFO")[1] + fifo_node = model.get_nodes_by_op_type("StreamingFIFO_rtl")[1] fifo_inst = getCustomOp(fifo_node) shape = fifo_inst.get_nodeattr("folded_shape") shape[1] = ofm_dim_h diff --git a/tests/fpgadataflow/test_fpgadataflow_dwc.py b/tests/fpgadataflow/test_fpgadataflow_dwc.py index 706b3d2065..d46815ebac 100644 --- a/tests/fpgadataflow/test_fpgadataflow_dwc.py +++ b/tests/fpgadataflow/test_fpgadataflow_dwc.py @@ -164,6 +164,7 @@ def test_fpgadataflow_dwc_stitched_rtlsim(config): model = make_single_dwc_modelwrapper(shape, inWidth, outWidth, finn_dtype) model = model.transform(SpecializeLayers()) model = model.transform(InsertFIFO(create_shallow_fifos=True)) + model = model.transform(SpecializeLayers()) model = model.transform(GiveUniqueNodeNames()) model = model.transform(PrepareIP(test_fpga_part, target_clk_ns)) model = model.transform(HLSSynthIP()) From 2cafe59154b24b73f21445f98bccf65c0ca7f522 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 31 Jan 2024 10:54:49 +0000 Subject: [PATCH 439/665] [Tests] Fix linting for swg dynamic test --- .../test_fpgadataflow_convinputgenerator_rtl_dynamic.py | 1 - 1 file changed, 1 deletion(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py index 368bdbb2ad..ee37ab86ef 100644 --- a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py +++ b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py @@ -49,7 +49,6 @@ import finn.core.onnx_exec as oxe import finn.transformation.fpgadataflow.convert_to_hls_layers as to_hls -import finn.transformation.fpgadataflow.convert_to_hw_layers as to_hw import finn.transformation.streamline.absorb as absorb from finn.core.onnx_exec import execute_onnx from finn.core.rtlsim_exec import rtlsim_exec From 562d153b96c96ac28968d01a9f09b2be9471ea17 Mon Sep 17 00:00:00 2001 From: johnnoel Date: Wed, 31 Jan 2024 13:37:50 +0000 Subject: [PATCH 440/665] [Tests] Fix fpgadataflow split large fifos test --- tests/fpgadataflow/test_split_large_fifos.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/fpgadataflow/test_split_large_fifos.py b/tests/fpgadataflow/test_split_large_fifos.py index 3061696a68..653e1e7896 100644 --- a/tests/fpgadataflow/test_split_large_fifos.py +++ b/tests/fpgadataflow/test_split_large_fifos.py @@ -54,7 +54,7 @@ def fetch_test_model(topology, wbits=2, abits=2): def get_folding_cfg(depth=65536): cfg = dict() cfg["Defaults"] = dict() - for i in range(3): + for i in range(4): key = "StreamingFIFO_" + str(i) cfg[key] = {"depth": depth, "ram_style": "auto", "impl_style": "vivado"} return cfg From a884e11ff52023e68a0f798c47bf777bacb873df Mon Sep 17 00:00:00 2001 From: johnnoel Date: Wed, 31 Jan 2024 13:48:05 +0000 Subject: [PATCH 441/665] Fix linting --- tests/end2end/test_end2end_bnn_pynq.py | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index 9fb41ec78e..db065fec42 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -654,10 +654,12 @@ def test_set_fifo_depths(self, topology, wbits, abits, board): model = load_test_checkpoint_or_skip(prev_chkpt_name) test_fpga_part = get_build_env(board, target_clk_ns)["part"] if topology == "cnv" and wbits == 2 and abits == 2 and board == "Pynq-Z1": - # Enabling swg_exception for this single test case. Disabling the exception results in a design - # that exceeds the resources of the Pynq-Z1 board. In future this should be revisited and handled - # correctly as the swg_exception is poorly justified. - model = model.transform(InsertAndSetFIFODepths(test_fpga_part, target_clk_ns, swg_exception=True)) + # Enabling swg_exception for this single test case. Disabling the exception results in + # a design that exceeds the resources of the Pynq-Z1 board. In future this should be + # revisited and handled correctly as the swg_exception is poorly justified. + model = model.transform( + InsertAndSetFIFODepths(test_fpga_part, target_clk_ns, swg_exception=True) + ) else: model = model.transform(InsertAndSetFIFODepths(test_fpga_part, target_clk_ns)) fifo_layers = model.get_nodes_by_op_type("StreamingFIFO") From a0e56399447c3770001dbe0a1fdc9004b317b3de Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Wed, 31 Jan 2024 14:09:17 +0000 Subject: [PATCH 442/665] [CustomOp] rtl threshold must inherit abstraction and rtlbackend --- src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py index 63abdd1545..30671423d0 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py @@ -38,7 +38,8 @@ roundup_to_integer_multiple, ) -from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp +from finn.custom_op.fpgadataflow.rtlbackend import RTLBackend +from finn.custom_op.fpgadataflow.thresholding import Thresholding from finn.util.basic import ( find_next_power_of_2, get_memutil_alternatives, @@ -68,8 +69,7 @@ This module creates an RTL IP, HLS is not supported. See 'thresholding_batch' for a HLS equivalent. """ - - +class Thresholding_rtl(Thresholding, RTLBackend): class Thresholding_rtl(HLSCustomOp): """Class that corresponds to finn-rtllib 'thresholding' function.""" From 33ed7408abcd206522c814cc27343c26e2b23785 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Wed, 31 Jan 2024 14:13:03 +0000 Subject: [PATCH 443/665] [CustomOp] Remove duplicate inherited functions and attributes from thresholing --- .../fpgadataflow/rtl/thresholding_rtl.py | 75 +------------------ 1 file changed, 4 insertions(+), 71 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py index 30671423d0..1119461c39 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py @@ -69,8 +69,8 @@ This module creates an RTL IP, HLS is not supported. See 'thresholding_batch' for a HLS equivalent. """ + class Thresholding_rtl(Thresholding, RTLBackend): -class Thresholding_rtl(HLSCustomOp): """Class that corresponds to finn-rtllib 'thresholding' function.""" def __init__(self, onnx_node, **kwargs): @@ -78,26 +78,6 @@ def __init__(self, onnx_node, **kwargs): def get_nodeattr_types(self): my_attrs = { - # parallelization; channels thresholded per cycle - "PE": ("i", True, 0), - # number of channels (each may have different thresholds) - "NumChannels": ("i", True, 0), - # number of steps in thresholding function. Used only in decoupled mode - "numSteps": ("i", True, 1), - # FINN DataTypes for inputs, outputs - "inputDataType": ("s", True, ""), - "weightDataType": ("s", True, ""), - "outputDataType": ("s", True, ""), - # number of input vectors, examples: - # [1] is a single vector (like a FC layer with batch=1) - # [4] is four vectors (like a FC layer with batch=4) - # [1, 4, 4] is four * four vectors (like a conv layer with batch=1) - "numInputVectors": ("ints", False, [1]), - # name of the top module in verilog template. Used by PyVerilator - # and IPI generation - "gen_top_module": ("s", False, ""), - # bias to be applied to outputs of the node - "activation_bias": ("i", False, 0), # whether weights (thresholds) will be # writable through an AXI-lite interface during runtime # 1 for enabled, 0 for disabled. @@ -113,7 +93,8 @@ def get_nodeattr_types(self): # setting to 0 may save some FFs but otherwise leave on "deep_pipeline": ("i", False, 1, {0, 1}), } - my_attrs.update(super().get_nodeattr_types()) + my_attrs.update(Thresholding.get_nodeattr_types(self)) + my_attrs.update(RTLBackend.get_nodeattr_types(self)) return my_attrs def get_pe_mem_geometries(self): @@ -158,10 +139,6 @@ def calc_tmem(self): pe = self.get_nodeattr("PE") return num_channels // pe - def make_shape_compatible_op(self, model): - oshape = self.get_normal_output_shape() - return super().make_const_shape_op(oshape) - def infer_node_datatype(self, model): """Used for FINN DataType inference: set the output tensors' datatypes accordingly for this node""" @@ -391,7 +368,7 @@ def prepare_codegen_rtl_values(self, model): # Identify the module variables input_data_type = self.get_nodeattr("inputDataType") # input/threshold precision - bias = self.get_nodeattr("activation_bias") # activation bias value + bias = self.get_nodeattr("ActVal") # activation bias value i_bitwidth = DataType[input_data_type].bitwidth() code_gen_dict["$N$"] = [str(o_bitwidth)] # output precision - convert bitwidth to string @@ -489,15 +466,10 @@ def generate_hdl(self, model): # Before we return - set the 'gen_top_module' attribute for use later # by PyVerilator and IPI generation self.set_nodeattr("gen_top_module", code_gen_dict["$TOP_MODULE$"][0]) - return - - def code_generation_ipgen(self, model, fpgapart, clk): - self.generate_hdl(model) # set ipgen_path and ip_path so that HLS-Synth transformation # and stich_ip transformation do not complain # i.e. during the HLSSynthIP() transformation - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") self.set_nodeattr("ipgen_path", code_gen_dir) self.set_nodeattr("ip_path", code_gen_dir) return @@ -614,13 +586,6 @@ def execute_node(self, context, graph): context[node.output[0]] = output return - def hls_sname(self): - """Get the naming convention used by Vitis HLS for stream signals - Example: the TDATA for a stream called "out" would be out_V_TDATA. - """ - # no additional prefix/suffix in interface names since this is an RTL component - return "" - def rtlsim_multi_io(self, sim, io_dict): "Run rtlsim for this node, supports multiple i/o streams." @@ -741,36 +706,4 @@ def get_dynamic_config(self, model, address_stride=1): return config - def ipgen_singlenode_code(self): - """Normally: Builds the bash script for IP generation.""" - """This is needed for the HLSSynthIP() transformation. - This is an IP, not a HLS node, so therefore provide an empty hook - to prevent any HLS synthesis.""" - pass - - def global_includes(self): - pass - - def defines(self, var): - pass - - def read_npy_data(self): - pass - - def strm_decl(self): - pass - - def docompute(self): - pass - - def dataoutstrm(self): - pass - - def save_as_npy(self): - pass - - def blackboxfunction(self): - pass - def pragmas(self): - pass From 5f05460237666e4ba747280af0137b1dbf47c858 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Thu, 1 Feb 2024 11:14:44 +0000 Subject: [PATCH 444/665] [Test] add helper functions Signed-off-by: aziz bahri --- .../test_fpgadataflow_thresholding.py | 56 +++++++++++++++---- 1 file changed, 46 insertions(+), 10 deletions(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_thresholding.py b/tests/fpgadataflow/test_fpgadataflow_thresholding.py index e88511f5cf..69d9a2f427 100644 --- a/tests/fpgadataflow/test_fpgadataflow_thresholding.py +++ b/tests/fpgadataflow/test_fpgadataflow_thresholding.py @@ -56,6 +56,26 @@ test_fpga_part = "xczu3eg-sbva484-1-e" target_clk_ns = 5 +def generate_random_threshold_values(input_data_type, num_input_channels, num_steps): + return np.random.randint( + input_data_type.min(), + input_data_type.max() + 1, + (num_input_channels, num_steps), + ).astype(np.float32) + +def sort_thresholds_increasing(thresholds): + return np.sort(thresholds, axis=1) + +# n = batch, c = channel, h = height, w = width of feature map +# Standard = NCHW; FINN = NHWC +# Convert from NHWC(FINN) to NCHW(Standard) +def layout_FINN2NCHW(data): + return np.transpose(data, (0, 3, 1, 2)) + +# Convert from NCHW(Standard) to NHWC(FINN) +def layout_NCHW2FINN(data): + return np.transpose(data, (0, 2, 3, 1)) + def make_single_thresholding_modelwrapper(impl_style, T, pe, idt, odt, actval, mem_mode, n_inp_vecs): NumChannels = T.shape[0] @@ -123,27 +143,43 @@ def test_fpgadataflow_thresholding(impl_style,idt, act, nf, ich, exec_mode, mem_ n_inp_vecs = [1, 2, 2] assert ich % pe == 0 - # generate input data + # generate input data, data layout is NHWC for FINN x = gen_finn_dt_tensor(idt, tuple(n_inp_vecs + [ich])) odt = act n_steps = act.get_num_possible_values() - 1 - T = np.random.randint(idt.min(), idt.max() + 1, (ich, n_steps)).astype(np.float32) - # provide non-decreasing thresholds - T = np.sort(T, axis=1) + + # Generate random, non-decreasing thresholds + thresholds = generate_random_threshold_values( + idt, ich, n_steps + ) + + thresholds = sort_thresholds_increasing(thresholds) if odt == DataType["BIPOLAR"]: actval = 0 else: actval = odt.min() - model = make_single_thresholding_modelwrapper(impl_style,T, pe, idt, odt, actval, mem_mode, n_inp_vecs) - - # calculate reference output + # Build DUT + model = make_single_thresholding_modelwrapper( + impl_style, + thresholds, + pe, + idt, + odt, + actval, + mem_mode, + n_inp_vecs + ) + + # Expected Reference output # multithreshold util fxn wants NCHW input, not NHWC - y = multithreshold(np.transpose(x, (0, 3, 1, 2)), T) + x_nchw = layout_FINN2NCHW(x) + y = multithreshold(x_nchw, thresholds) + # convert back to NHWC for comparison to hw outputs - y = np.transpose(y, (0, 2, 3, 1)) + y = layout_NCHW2FINN(y) if act == DataType["BIPOLAR"]: # binary to bipolar y = 2 * y - 1 @@ -157,7 +193,7 @@ def test_fpgadataflow_thresholding(impl_style,idt, act, nf, ich, exec_mode, mem_ # package input data as dictionary input_dict = {"inp": x} - # execute model + # execute DUT y_produced = oxe.execute_onnx(model, input_dict)["outp"] y_produced = y_produced.reshape(y_expected.shape) From ff3d60c88525f947f091c1657933a2be33f54588 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Thu, 1 Feb 2024 11:17:59 +0000 Subject: [PATCH 445/665] [Test] RTL test skip cppsim exec mode Signed-off-by: aziz bahri --- tests/fpgadataflow/test_fpgadataflow_thresholding.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/fpgadataflow/test_fpgadataflow_thresholding.py b/tests/fpgadataflow/test_fpgadataflow_thresholding.py index 69d9a2f427..d75c9ef992 100644 --- a/tests/fpgadataflow/test_fpgadataflow_thresholding.py +++ b/tests/fpgadataflow/test_fpgadataflow_thresholding.py @@ -137,6 +137,8 @@ def make_single_thresholding_modelwrapper(impl_style, T, pe, idt, odt, actval, m @pytest.mark.vivado @pytest.mark.slow def test_fpgadataflow_thresholding(impl_style,idt, act, nf, ich, exec_mode, mem_mode): + if impl_style == "rtl" and exec_mode == "cppsim": + pytest.skip("rtl implstyle has no cppsim, skipping") if nf == -1: nf = ich pe = ich // nf From c54d32ce2fb619cfd231579dd2b8f0ddcf711983 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Thu, 1 Feb 2024 14:04:21 +0000 Subject: [PATCH 446/665] [Pyverilator] update to new rtlsim_multi_io implementation --- fetch-repos.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fetch-repos.sh b/fetch-repos.sh index 1275ccf31c..ba7cd28a00 100755 --- a/fetch-repos.sh +++ b/fetch-repos.sh @@ -30,7 +30,7 @@ QONNX_COMMIT="47e4357faf66b5b0d1bf77bf908bb47752421e5b" FINN_EXP_COMMIT="de99347e936d51715f5356a1b6c64e37b91c23c2" BREVITAS_COMMIT="84f42259ec869eb151af4cb8a8b23ad925f493db" -PYVERILATOR_COMMIT="766e457465f5c0dd315490d7b9cc5d74f9a76f4f" +PYVERILATOR_COMMIT="fc2dd96ac07c5a23897af8f0b0339135e12fa0ba" CNPY_COMMIT="4e8810b1a8637695171ed346ce68f6984e585ef4" HLSLIB_COMMIT="16e5847a5e3ef76cffe84c8fad2f010d593457d3" OMX_COMMIT="0b59762f9e4c4f7e5aa535ee9bc29f292434ca7a" From 21103343e05dedb2eebe20940d087feea627cfb5 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Thu, 1 Feb 2024 14:12:21 +0000 Subject: [PATCH 447/665] [CustomOp] overload thresholding rtl code_generation_ipgen function --- src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py index 1119461c39..a539ab6f84 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py @@ -446,6 +446,9 @@ def dump_rtl_data(self, dest_dir, filename, data): f.write(data) return + def code_generation_ipgen(self, model, fpgapart, clk): + self.generate_hdl(model) + def generate_hdl(self, model): """Prepare HDL files from templates for synthesis""" # Generate a dictionary of values to put in RTL template From be5ae0277dbab87fa9d8dde2840976b9d5908428 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Thu, 1 Feb 2024 14:15:10 +0000 Subject: [PATCH 448/665] [tests] relax rtlsim cycle count match Signed-off-by: aziz bahri --- tests/fpgadataflow/test_fpgadataflow_thresholding.py | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_thresholding.py b/tests/fpgadataflow/test_fpgadataflow_thresholding.py index d75c9ef992..3daf44a055 100644 --- a/tests/fpgadataflow/test_fpgadataflow_thresholding.py +++ b/tests/fpgadataflow/test_fpgadataflow_thresholding.py @@ -203,6 +203,8 @@ def test_fpgadataflow_thresholding(impl_style,idt, act, nf, ich, exec_mode, mem_ assert (y_produced == y_expected).all() model = model.transform(SpecializeLayers()) + # Make sure that SpecializeLayers did not default to HLS implementation unexpectedly + assert model.graph.node[0].op_type == "Thresholding_" + str(impl_style) if exec_mode == "cppsim": model = model.transform(PrepareCppSim()) @@ -226,14 +228,13 @@ def test_fpgadataflow_thresholding(impl_style,idt, act, nf, ich, exec_mode, mem_ if exec_mode == "rtlsim": hls_synt_res_est = model.analysis(hls_synth_res_estimation) - assert "Thresholding_hls_0" in hls_synt_res_est - - node = model.get_nodes_by_op_type("Thresholding_hls")[0] + assert model.graph.node[0].name in hls_synt_res_est + node = model.get_nodes_by_op_type(model.graph.node[0].op_type)[0] inst = getCustomOp(node) cycles_rtlsim = inst.get_nodeattr("cycles_rtlsim") exp_cycles_dict = model.analysis(exp_cycles_per_layer) exp_cycles = exp_cycles_dict[node.name] - assert np.isclose(exp_cycles, cycles_rtlsim, atol=10) + assert np.isclose(exp_cycles, cycles_rtlsim, atol=15) assert exp_cycles != 0 @pytest.mark.parametrize("impl_style", ["rtl", "hls"]) @@ -265,6 +266,8 @@ def test_runtime_thresholds_single_layer(impl_style): model = make_single_thresholding_modelwrapper(impl_style, T, pe, idt, odt, actval, mem_mode, n_inp_vecs) model = model.transform(SpecializeLayers()) + + # Make sure that specialize layer did not default to HLS implementation assert model.graph.node[0].op_type == "Thresholding_" + str(impl_style) op_inst = getCustomOp(model.graph.node[0]) From f0dcec3b5375c11647d7c0177fb491f895c1f1d3 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Thu, 11 Jan 2024 15:07:05 +0000 Subject: [PATCH 449/665] [hlsbackend]: update limit HLS axi streams (8k-1) --- src/finn/custom_op/fpgadataflow/hlsbackend.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/finn/custom_op/fpgadataflow/hlsbackend.py b/src/finn/custom_op/fpgadataflow/hlsbackend.py index 846894d85c..d8210fd684 100644 --- a/src/finn/custom_op/fpgadataflow/hlsbackend.py +++ b/src/finn/custom_op/fpgadataflow/hlsbackend.py @@ -472,5 +472,5 @@ def get_ap_int_max_w(self): instream = self.get_instream_width() outstream = self.get_outstream_width() ret = max([instream, outstream]) - assert ret <= 32768, "AP_INT_MAX_W=%d is larger than allowed maximum of 32768" % ret + assert ret <= 8191, "AP_INT_MAX_W=%d is larger than allowed maximum of 8191" % ret return ret From 5176eb79b90e1da206ec8aad93af3af8272043db Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 26 Jan 2024 11:11:05 +0000 Subject: [PATCH 450/665] [mvau hls]: refactored MVAU_hls custom_op --- .../hls/matrixvectoractivation_hls.py | 522 ++++++++++++++++++ 1 file changed, 522 insertions(+) create mode 100644 src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py diff --git a/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py b/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py new file mode 100644 index 0000000000..2ad9fefc07 --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py @@ -0,0 +1,522 @@ +# Copyright (c) 2020, Xilinx +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import math +import numpy as np +import os +import textwrap +import warnings +from qonnx.core.datatype import DataType +from qonnx.util.basic import ( + calculate_matvec_accumulator_range, + interleave_matrix_outer_dim_from_partitions, + roundup_to_integer_multiple, +) + +from finn.custom_op.fpgadataflow.matrixvectoractivation import MatrixVectorActivation +from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend +from finn.util.data_packing import ( + npy_to_rtlsim_input, + numpy_to_hls_code, + pack_innermost_dim_as_hex_string, + rtlsim_output_to_npy, +) + +# ONNX i/o tensor shape assumptions for MatrixVectorActivation: +# input 0 is the input tensor, shape (.., i_size) = (..., MW) +# input 1 is the weight tensor, shape (i_size, o_size) = (MW, MH) +# (optional) input 2 is the thresholds tensor, shape (o_size, n_thres) +# output 0 is the output tensor, shape (.., o_size) = (..., MH) +# the ... here can be any shape (representing groups of vectors) + + +class MatrixVectorActivation_hls(MatrixVectorActivation, HLSBackend): + """Corresponds to finn-hlslib MatrixVectorActivation_Batch function.""" + + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) + + def get_nodeattr_types(self): + my_attrs = {} + my_attrs.update(MatrixVectorActivation.get_nodeattr_types(self)) + my_attrs.update(HLSBackend.get_nodeattr_types(self)) + return my_attrs + + def get_template_param_values(self): + """Returns the template parameter values according to input, output and weight + data types.""" + ret = dict() + inp_hls_str = self.get_input_datatype().get_hls_datatype_str() + out_hls_str = self.get_output_datatype().get_hls_datatype_str() + inp_is_binary = self.get_input_datatype() == DataType["BINARY"] + # out_is_binary = self.get_output_datatype() == DataType["BINARY"] + wt_is_binary = self.get_weight_datatype() == DataType["BINARY"] + bin_xnor_mode = self.get_nodeattr("binaryXnorMode") == 1 + if (inp_is_binary or wt_is_binary) and (not bin_xnor_mode): + raise Exception("True binary (non-bipolar) inputs not yet supported") + inp_is_bipolar = self.get_input_datatype() == DataType["BIPOLAR"] + # out_is_bipolar = self.get_output_datatype() == DataType["BIPOLAR"] + wt_is_bipolar = self.get_weight_datatype() == DataType["BIPOLAR"] + # reinterpret inp/wt as bipolar if bin_xnor_mode is iset + inp_is_bipolar = inp_is_bipolar or (inp_is_binary and bin_xnor_mode) + wt_is_bipolar = wt_is_bipolar or (wt_is_binary and bin_xnor_mode) + # fill in TSrcI and TWeightI + # TODO check these with Giulio + # TODO handle non-bipolar binary inputs + if inp_is_bipolar and wt_is_bipolar: + ret["TSrcI"] = "Recast" + ret["TWeightI"] = "Identity" + elif (not inp_is_bipolar) and wt_is_bipolar: + ret["TSrcI"] = "Slice<%s>" % inp_hls_str + ret["TWeightI"] = "Recast" + elif inp_is_bipolar and (not wt_is_bipolar): + ret["TSrcI"] = "Recast" + ret["TWeightI"] = "Identity" + elif (not inp_is_bipolar) and (not wt_is_bipolar): + ret["TSrcI"] = "Slice<%s>" % inp_hls_str + ret["TWeightI"] = "Identity" + + # fill in TDstI + ret["TDstI"] = "Slice<%s>" % out_hls_str + + return ret + + def get_verilog_top_module_intf_names(self): + intf_names = super().get_verilog_top_module_intf_names() + mem_mode = self.get_nodeattr("mem_mode") + sname = self.hls_sname() + if mem_mode == "external": + intf_names["s_axis"].append(("weights_" + sname, self.get_weightstream_width_padded())) + if mem_mode == "decoupled": + # only expose axilite interface if attribute is set + runtime_writable = self.get_nodeattr("runtime_writeable_weights") == 1 + if runtime_writable: + intf_names["axilite"] = ["s_axilite"] + return intf_names + + def global_includes(self): + self.code_gen_dict["$GLOBALS$"] = ['#include "weights.hpp"'] + self.code_gen_dict["$GLOBALS$"] += ['#include "activations.hpp"'] + + mem_mode = self.get_nodeattr("mem_mode") + if mem_mode not in ["const", "decoupled", "external"]: + raise Exception( + """Please set mem_mode to "const", "decoupled", or "external", + currently no other parameter value is supported!""" + ) + self.code_gen_dict["$GLOBALS$"] += ['#include "mvau.hpp"'] + if self.calc_tmem() != 0: + # TODO find a better way of checking for no pregenerated thresholds + self.code_gen_dict["$GLOBALS$"] += ['#include "thresh.h"'] + + def defines(self, var): + # Only ipgen mode: Make sure that SIMD parameter satisfies minimum requirements. + if var == "ipgen": + SIMD = self.get_nodeattr("SIMD") + MW = self.get_nodeattr("MW") + condition = SIMD >= (MW / 1024) + msg = ( + f"HLS synthesis of MatrixVectorActivation requires: " + f"SIMD >= MW / 1024. This is not fulfilled with: SIMD={SIMD} " + f"and MW={MW} for node: {self.onnx_node.name}." + ) + assert condition, msg + mem_mode = self.get_nodeattr("mem_mode") + numInputVectors = list(self.get_nodeattr("numInputVectors")) + numReps = np.prod(numInputVectors) + self.code_gen_dict["$DEFINES$"] = [ + """#define MW1 {}\n #define MH1 {}\n + #define SIMD1 {}\n #define PE1 {}\n #define WMEM1 {}\n + #define TMEM1 {}\n #define numReps {}""".format( + self.get_nodeattr("MW"), + self.get_nodeattr("MH"), + self.get_nodeattr("SIMD"), + self.get_nodeattr("PE"), + self.calc_wmem(), + self.calc_tmem(), + numReps, + ) + ] + if mem_mode == "decoupled" or mem_mode == "external": + wdt = self.get_weight_datatype() + self.code_gen_dict["$DEFINES$"].append("#define WP1 {}\n".format(wdt.bitwidth())) + + def read_npy_data(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_input_datatype() + if dtype == DataType["BIPOLAR"]: + # use binary for bipolar storage + dtype = DataType["BINARY"] + elem_bits = dtype.bitwidth() + packed_bits = self.get_instream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "float" + npy_in = "%s/input_0.npy" % code_gen_dir + self.code_gen_dict["$READNPYDATA$"] = [] + # note: the innermost dim is reversed for the input + self.code_gen_dict["$READNPYDATA$"].append( + 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s, false);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) + ) + + mem_mode = self.get_nodeattr("mem_mode") + if mem_mode == "decoupled" or mem_mode == "external": + wdt = self.get_weight_datatype() + elem_bits = wdt.bitwidth() + packed_bits = self.get_weightstream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = wdt.get_hls_datatype_str() + npy_type = "float" + npy_in = "%s/weights.npy" % code_gen_dir + + self.code_gen_dict["$READNPYDATA$"].append( + 'npy2apintstream<%s, %s, %d, %s>("%s", weights_%s, false, numReps);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) + ) + + def strm_decl(self): + mem_mode = self.get_nodeattr("mem_mode") + self.code_gen_dict["$STREAMDECLARATIONS$"] = [] + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> in0_{} ("in0_{}");'.format( + self.get_instream_width(), self.hls_sname(), self.hls_sname() + ) + ) + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> out_{} ("out_{}");'.format( + self.get_outstream_width(), self.hls_sname(), self.hls_sname() + ) + ) + + if mem_mode == "decoupled" or mem_mode == "external": + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> weights_{} ("weights_{}");'.format( + self.get_weightstream_width(), self.hls_sname(), self.hls_sname() + ) + ) + + def docompute(self): + mem_mode = self.get_nodeattr("mem_mode") + map_to_hls_mult_style = { + "auto": "ap_resource_dflt()", + "lut": "ap_resource_lut()", + "dsp": "ap_resource_dsp()", + } + tmpl_args = self.get_template_param_values() + if self.calc_tmem() == 0: + odtype_hls_str = self.get_output_datatype().get_hls_datatype_str() + threshs = "PassThroughActivation<%s>()" % odtype_hls_str + else: + threshs = "threshs" + if mem_mode == "const": + self.code_gen_dict["$DOCOMPUTE$"] = [ + """Matrix_Vector_Activate_Batch + (in0_{}, out_{}, weights, {}, numReps, {});""".format( + tmpl_args["TSrcI"], + tmpl_args["TDstI"], + tmpl_args["TWeightI"], + self.hls_sname(), + self.hls_sname(), + threshs, + map_to_hls_mult_style[self.get_nodeattr("resType")], + ) + ] + elif mem_mode == "decoupled" or mem_mode == "external": + wdt = self.get_weight_datatype() + if wdt == DataType["BIPOLAR"]: + export_wdt = DataType["BINARY"] + else: + export_wdt = wdt + wdtype_hls_str = export_wdt.get_hls_datatype_str() + self.code_gen_dict["$DOCOMPUTE$"] = [ + """Matrix_Vector_Activate_Stream_Batch + (in0_{}, out_{}, weights_{}, {}, numReps, {});""".format( + tmpl_args["TSrcI"], + tmpl_args["TDstI"], + tmpl_args["TWeightI"], + wdtype_hls_str, + self.hls_sname(), + self.hls_sname(), + self.hls_sname(), + threshs, + map_to_hls_mult_style[self.get_nodeattr("resType")], + ) + ] + + else: + raise Exception( + """Please set mem_mode to "const", "decoupled", or "external", + currently no other parameter value is supported!""" + ) + + def dataoutstrm(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_output_datatype() + if dtype == DataType["BIPOLAR"]: + # use binary for bipolar storage + dtype = DataType["BINARY"] + elem_bits = dtype.bitwidth() + packed_bits = self.get_outstream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "float" + npy_out = "%s/output.npy" % code_gen_dir + shape = self.get_folded_output_shape() + shape_cpp_str = str(shape).replace("(", "{").replace(")", "}") + + # note: the innermost dim is not reversed for the output + self.code_gen_dict["$DATAOUTSTREAM$"] = [ + 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s", false);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + self.hls_sname(), + shape_cpp_str, + npy_out, + ) + ] + + def save_as_npy(self): + self.code_gen_dict["$SAVEASCNPY$"] = [] + + def blackboxfunction(self): + mem_mode = self.get_nodeattr("mem_mode") + if mem_mode == "const": + self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ + """void {}(hls::stream> &in0_{}, + hls::stream> &out_{} + )""".format( + self.onnx_node.name, + self.get_instream_width(), + self.hls_sname(), + self.get_outstream_width(), + self.hls_sname(), + ) + ] + elif mem_mode == "decoupled" or mem_mode == "external": + self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ + """void {}( + hls::stream> &in0_{}, + hls::stream> &weights_{}, + hls::stream> &out_{} + )""".format( + self.onnx_node.name, + self.get_instream_width(), + self.hls_sname(), + self.get_weightstream_width(), + self.hls_sname(), + self.get_outstream_width(), + self.hls_sname(), + ) + ] + + else: + raise Exception( + """Please set mem_mode to "const" or "decoupled", currently no other + parameter value is supported!""" + ) + + def pragmas(self): + mem_mode = self.get_nodeattr("mem_mode") + ram_style_thresholds = self.get_nodeattr("ram_style_thresholds") + self.code_gen_dict["$PRAGMAS$"] = [ + "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() + ] + self.code_gen_dict["$PRAGMAS$"].append( + "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() + ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") + + if mem_mode == "const": + self.code_gen_dict["$PRAGMAS$"].append('#include "params.h"') + # the weight tensor is ap_uint [PE][WMEM] + # partition for parallel access along the PE dimension (dim 1) + self.code_gen_dict["$PRAGMAS$"].append( + ("#pragma HLS ARRAY_PARTITION variable=weights.m_weights " "complete dim=1") + ) + elif mem_mode == "decoupled" or mem_mode == "external": + self.code_gen_dict["$PRAGMAS$"].append( + "#pragma HLS INTERFACE axis port=weights_" + self.hls_sname() + ) + + else: + raise Exception( + """Please set mem_mode to "const", "decoupled", or external, + currently no other parameter value is supported!""" + ) + + # the threshold tensor is acc_type [PE][TMEM][N_THRES] + # partition for parallel access along PE and N_THRES + # dimensions (dims 1 and 3) + if self.calc_tmem() != 0: + # TODO find a better way of checking for no pregenerated thresholds + self.code_gen_dict["$PRAGMAS$"].append( + ("#pragma HLS ARRAY_PARTITION variable=threshs.m_thresholds " "complete dim=1") + ) + self.code_gen_dict["$PRAGMAS$"].append( + ("#pragma HLS ARRAY_PARTITION variable=threshs.m_thresholds " "complete dim=3") + ) + # add resource pragma for thresholds if set + if ram_style_thresholds == "distributed": + self.code_gen_dict["$PRAGMAS$"].append( + ("#pragma HLS RESOURCE variable=threshs.m_thresholds " "core=ROM_2P_LUTRAM") + ) + elif ram_style_thresholds == "block": + self.code_gen_dict["$PRAGMAS$"].append( + ("#pragma HLS RESOURCE variable=threshs.m_thresholds " "core=ROM_2P_BRAM") + ) + elif ram_style_thresholds == "auto": + # no pragma needed + pass + else: + raise Exception("Unrecognized ram_style_thresholds value:" + ram_style_thresholds) + + def get_ap_int_max_w(self): + # base class impl (max of inp/out stream widths) + max_of_io = super().get_ap_int_max_w() + # decoupled mode weight stream + weightstream = self.get_weightstream_width() + # single PE weight entry + weight_bits = self.get_weight_datatype().bitwidth() + simd = self.get_nodeattr("SIMD") + single_pe_w = simd * weight_bits + return max([weightstream, max_of_io, single_pe_w]) + + def execute_node(self, context, graph): + mode = self.get_nodeattr("exec_mode") + mem_mode = self.get_nodeattr("mem_mode") + node = self.onnx_node + + if mode == "cppsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + elif mode == "rtlsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + + # create a npy file fore each input of the node (in_ind is input index) + in_ind = 0 + for inputs in node.input: + # it is assumed that the first input of the node is the data input + # the second input are the weights + if in_ind == 0: + assert ( + str(context[inputs].dtype) == "float32" + ), """Input datatype is + not float32 as expected.""" + expected_inp_shape = self.get_folded_input_shape() + reshaped_input = context[inputs].reshape(expected_inp_shape) + export_idt = self.get_input_datatype() + # make copy before saving the array + reshaped_input = reshaped_input.copy() + np.save( + os.path.join(code_gen_dir, "input_{}.npy".format(in_ind)), + reshaped_input, + ) + elif in_ind > 2: + raise Exception("Unexpected input found for MatrixVectorActivation") + in_ind += 1 + + if mode == "cppsim": + # execute the precompiled model + super().exec_precompiled_singlenode_model() + # load output npy file + super().npy_to_dynamic_output(context) + # reinterpret binary output as bipolar where needed + if self.get_output_datatype() == DataType["BIPOLAR"]: + out = context[node.output[0]] + out = 2 * out - 1 + context[node.output[0]] = out + assert ( + context[node.output[0]].shape == self.get_normal_output_shape() + ), "cppsim did not produce expected output shape" + elif mode == "rtlsim": + sim = self.get_rtlsim() + nbits = self.get_instream_width() + inp = npy_to_rtlsim_input( + "{}/input_0.npy".format(code_gen_dir), export_idt, nbits + ) + self.reset_rtlsim(sim) + self.toggle_clk(sim) + if mem_mode in ["external", "decoupled"]: + wnbits = self.get_weightstream_width() + export_wdt = self.get_weight_datatype() + wei = npy_to_rtlsim_input( + "{}/weights.npy".format(code_gen_dir), export_wdt, wnbits + ) + num_w_reps = np.prod(self.get_nodeattr("numInputVectors")) + io_dict = { + "inputs": {"in0": inp, "weights": wei * num_w_reps}, + "outputs": {"out": []}, + } + self.rtlsim_multi_io(sim, io_dict) + output = io_dict["outputs"]["out"] + else: + output = self.rtlsim(sim, inp) + odt = self.get_output_datatype() + target_bits = odt.bitwidth() + packed_bits = self.get_outstream_width() + out_npy_path = "{}/output.npy".format(code_gen_dir) + out_shape = self.get_folded_output_shape() + rtlsim_output_to_npy( + output, out_npy_path, odt, out_shape, packed_bits, target_bits + ) + # load and reshape output + output = np.load(out_npy_path) + oshape = self.get_normal_output_shape() + output = np.asarray([output], dtype=np.float32).reshape(*oshape) + context[node.output[0]] = output + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to "rtlsim" """.format( + mode + ) + ) \ No newline at end of file From b7480bb7a98681343a55af93627b97285e5e1e11 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 26 Jan 2024 11:45:12 +0000 Subject: [PATCH 451/665] [refactor]: call to base_op_type method instead of custom_op type --- src/finn/analysis/fpgadataflow/res_estimation.py | 2 +- src/finn/transformation/fpgadataflow/create_stitched_ip.py | 3 ++- src/finn/transformation/fpgadataflow/floorplan.py | 2 +- src/finn/transformation/fpgadataflow/insert_dwc.py | 2 +- src/finn/transformation/fpgadataflow/insert_iodma.py | 2 +- src/finn/transformation/fpgadataflow/insert_tlastmarker.py | 4 ++-- src/finn/transformation/fpgadataflow/make_pynq_driver.py | 2 +- src/finn/transformation/fpgadataflow/make_zynq_proj.py | 2 +- src/finn/transformation/fpgadataflow/set_fifo_depths.py | 6 +++--- src/finn/transformation/fpgadataflow/set_folding.py | 2 +- 10 files changed, 14 insertions(+), 13 deletions(-) diff --git a/src/finn/analysis/fpgadataflow/res_estimation.py b/src/finn/analysis/fpgadataflow/res_estimation.py index be4cf417bc..a7f220daa9 100644 --- a/src/finn/analysis/fpgadataflow/res_estimation.py +++ b/src/finn/analysis/fpgadataflow/res_estimation.py @@ -60,8 +60,8 @@ def res_estimation_complete(model): res_dict = {} for node in model.graph.node: if is_fpgadataflow_node(node) is True: - op_type = node.op_type inst = registry.getCustomOp(node) + op_type = inst.base_op_type() if op_type == "MatrixVectorActivation" or op_type == "VectorVectorActivation": orig_restype = inst.get_nodeattr("resType") res_dict[node.name] = [] diff --git a/src/finn/transformation/fpgadataflow/create_stitched_ip.py b/src/finn/transformation/fpgadataflow/create_stitched_ip.py index 1a182c7f4f..81c5848d57 100644 --- a/src/finn/transformation/fpgadataflow/create_stitched_ip.py +++ b/src/finn/transformation/fpgadataflow/create_stitched_ip.py @@ -48,12 +48,13 @@ def is_external_input(model, node, i): # True only if input is unconnected and has no initializer # Only esception is second input of FC layers when mem_mode is external node_inst = getCustomOp(node) + op_type = node_inst.base_op_type() producer = model.find_producer(node.input[i]) if producer is None: if model.get_initializer(node.input[i]) is None: return True else: - if node.op_type == "MatrixVectorActivation": + if op_type == "MatrixVectorActivation": if node_inst.get_nodeattr("mem_mode") == "external": return True return False diff --git a/src/finn/transformation/fpgadataflow/floorplan.py b/src/finn/transformation/fpgadataflow/floorplan.py index ceb2bdb5c9..56e644f2b8 100644 --- a/src/finn/transformation/fpgadataflow/floorplan.py +++ b/src/finn/transformation/fpgadataflow/floorplan.py @@ -150,7 +150,7 @@ def apply(self, model): continue elif not ( - node.op_type == "MatrixVectorActivation" + node_inst.base_op_type() == "MatrixVectorActivation" and node_inst.get_nodeattr("mem_mode") is not None and node_inst.get_nodeattr("mem_mode") == "external" ): diff --git a/src/finn/transformation/fpgadataflow/insert_dwc.py b/src/finn/transformation/fpgadataflow/insert_dwc.py index 81cee8dae4..d0029cb630 100644 --- a/src/finn/transformation/fpgadataflow/insert_dwc.py +++ b/src/finn/transformation/fpgadataflow/insert_dwc.py @@ -88,7 +88,7 @@ def apply(self, model): # - if FC and external mem, it could be connected to input 1 # - if concat, could be connected to any input if ( - consumer.op_type == "MatrixVectorActivation" + n1.base_op_type() == "MatrixVectorActivation" and n1.get_nodeattr("mem_mode") == "external" ) or (consumer.op_type == "StreamingConcat"): # get input idx diff --git a/src/finn/transformation/fpgadataflow/insert_iodma.py b/src/finn/transformation/fpgadataflow/insert_iodma.py index 93e3226b2a..fd546459fa 100644 --- a/src/finn/transformation/fpgadataflow/insert_iodma.py +++ b/src/finn/transformation/fpgadataflow/insert_iodma.py @@ -199,7 +199,7 @@ def apply(self, model): # attached IODMA fc_extw_nodes = list( filter( - lambda x: x.op_type in ["MatrixVectorActivation", "VectorVectorActivation"] + lambda x: getCustomOp(x).base_op_type() in ["MatrixVectorActivation", "VectorVectorActivation"] and getCustomOp(x).get_nodeattr("mem_mode") == "external" and model.find_producer(x.input[1]) is None, all_nodes, diff --git a/src/finn/transformation/fpgadataflow/insert_tlastmarker.py b/src/finn/transformation/fpgadataflow/insert_tlastmarker.py index 157df46d71..ab5142e4d8 100644 --- a/src/finn/transformation/fpgadataflow/insert_tlastmarker.py +++ b/src/finn/transformation/fpgadataflow/insert_tlastmarker.py @@ -103,7 +103,7 @@ def apply(self, model): # the input is in the list of graph inputs because it has an # initializer (TODO: fix this with a clean-up transform) if ( - first_node.op_type == "MatrixVectorActivation" + getCustomOp(first_node).base_op_type() == "MatrixVectorActivation" and get_by_name(first_node.attribute, "mem_mode").s.decode("UTF-8") != "external" ): @@ -117,7 +117,7 @@ def apply(self, model): num_iters = np.prod(custom_op.get_folded_input_shape()[1:-1]) inp_idx = list(first_node.input).index(graph_in_name) if inp_idx > 0: - if first_node.op_type == "MatrixVectorActivation" and inp_idx == 1: + if getCustomOp(first_node).base_op_type() == "MatrixVectorActivation" and inp_idx == 1: stream_width = int(custom_op.get_weightstream_width()) elif first_node.op_type == "AddStreams_Batch" and inp_idx == 1: stream_width = int(custom_op.get_instream_width()) diff --git a/src/finn/transformation/fpgadataflow/make_pynq_driver.py b/src/finn/transformation/fpgadataflow/make_pynq_driver.py index d5c2d8f2b5..e66236bf39 100644 --- a/src/finn/transformation/fpgadataflow/make_pynq_driver.py +++ b/src/finn/transformation/fpgadataflow/make_pynq_driver.py @@ -282,7 +282,7 @@ def apply(self, model): dataflow_model = ModelWrapper(dataflow_model_filename) rt_layer_ind = 0 for node in dataflow_model.graph.node: - if node.op_type in ["MatrixVectorActivation", "Thresholding_Batch"]: + if getCustomOp(node).base_op_type() == "MatrixVectorActivation" or node.op_type == "Thresholding_Batch": node_inst = getCustomOp(node) is_rt_weights = node_inst.get_nodeattr("runtime_writeable_weights") if is_rt_weights == 1: diff --git a/src/finn/transformation/fpgadataflow/make_zynq_proj.py b/src/finn/transformation/fpgadataflow/make_zynq_proj.py index 989eb62a88..193e6e8b42 100644 --- a/src/finn/transformation/fpgadataflow/make_zynq_proj.py +++ b/src/finn/transformation/fpgadataflow/make_zynq_proj.py @@ -62,7 +62,7 @@ def collect_ip_dirs(model, ipstitch_path): ), """The directory that should contain the generated ip blocks doesn't exist.""" ip_dirs += [ip_dir_value] - if node.op_type in ["MatrixVectorActivation", "Thresholding_Batch"]: + if getCustomOp(node).base_op_type() == "MatrixVectorActivation" or node.op_type == "Thresholding_Batch": if node_inst.get_nodeattr("mem_mode") == "decoupled": need_memstreamer = True ip_dirs += [ipstitch_path + "/ip"] diff --git a/src/finn/transformation/fpgadataflow/set_fifo_depths.py b/src/finn/transformation/fpgadataflow/set_fifo_depths.py index 11ffc965b6..84a8084832 100644 --- a/src/finn/transformation/fpgadataflow/set_fifo_depths.py +++ b/src/finn/transformation/fpgadataflow/set_fifo_depths.py @@ -174,7 +174,7 @@ def apply(self, model): continue if fifo_cons is None: continue - if fifo_cons.op_type != "MatrixVectorActivation": + if getCustomOp(fifo_cons).base_op_type() != "MatrixVectorActivation": continue op_inst = getCustomOp(node) depth = op_inst.get_nodeattr("depth") @@ -281,7 +281,7 @@ def apply(self, model): node.set_nodeattr("inFIFODepths", ifd) node.set_nodeattr("outFIFODepths", ofd) - if node.onnx_node.op_type in extw_optypes: + if getCustomOp(node).base_op_type() in extw_optypes: mmode = node.get_nodeattr("mem_mode") if mmode == "external": modified_fc_nodes.append(node.onnx_node.name) @@ -422,7 +422,7 @@ def apply(self, model): # (removed setting of node FIFO size attributes to 0 here) # for every extw node we changed from external to decoupled, # change back and reset implementation - if node.op_type in extw_optypes: + if getCustomOp(node).base_op_type() in extw_optypes: if node.name in modified_fc_nodes: node_inst = getCustomOp(node) node_inst.set_nodeattr("mem_mode", "external") diff --git a/src/finn/transformation/fpgadataflow/set_folding.py b/src/finn/transformation/fpgadataflow/set_folding.py index 4045a28e16..7b65023abc 100644 --- a/src/finn/transformation/fpgadataflow/set_folding.py +++ b/src/finn/transformation/fpgadataflow/set_folding.py @@ -125,7 +125,7 @@ def apply(self, model): continue op_type = node.op_type node_inst = getCustomOp(node) - if op_type == "MatrixVectorActivation": + if node_inst.base_op_type() == "MatrixVectorActivation": max_simd = node_inst.get_nodeattr("MW") max_pe = node_inst.get_nodeattr("MH") node_inst.set_nodeattr("PE", 1) From 4f707d8308e6b6e1cb90d0f068d6536017cc9d40 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 26 Jan 2024 11:46:01 +0000 Subject: [PATCH 452/665] [hls custom-op]: add mvau_hls --- src/finn/custom_op/fpgadataflow/hls/__init__.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/finn/custom_op/fpgadataflow/hls/__init__.py b/src/finn/custom_op/fpgadataflow/hls/__init__.py index 188f45273c..1f1448b9fc 100644 --- a/src/finn/custom_op/fpgadataflow/hls/__init__.py +++ b/src/finn/custom_op/fpgadataflow/hls/__init__.py @@ -50,6 +50,7 @@ from finn.custom_op.fpgadataflow.hls.thresholding_hls import Thresholding_hls from finn.custom_op.fpgadataflow.hls.tlastmarker_hls import TLastMarker_hls from finn.custom_op.fpgadataflow.hls.upsampler_hls import UpsampleNearestNeighbour_hls +from finn.custom_op.fpgadataflow.hls.matrixvectoractivation_hls import MatrixVectorActivation_hls custom_op = dict() @@ -75,3 +76,4 @@ custom_op["Thresholding_hls"] = Thresholding_hls custom_op["TLastMarker_hls"] = TLastMarker_hls custom_op["UpsampleNearestNeighbour_hls"] = UpsampleNearestNeighbour_hls +custom_op["MatrixVectorActivation_hls"] = MatrixVectorActivation_hls \ No newline at end of file From 7c6065c12f16ac250aee2c9717a6a54d95d52cea Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 26 Jan 2024 11:46:17 +0000 Subject: [PATCH 453/665] [hw custom-op]: refactor MVAU --- .../fpgadataflow/matrixvectoractivation.py | 820 ++++++------------ 1 file changed, 274 insertions(+), 546 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index 6699340cac..7cf6c2b2cd 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -31,20 +31,32 @@ import os import textwrap import warnings +from onnx import TensorProto, helper from qonnx.core.datatype import DataType +import qonnx.custom_op.general.xnorpopcount as xp +from qonnx.custom_op.general.multithreshold import multithreshold +from qonnx.core.modelwrapper import ModelWrapper +from qonnx.custom_op.registry import getCustomOp from qonnx.util.basic import ( calculate_matvec_accumulator_range, interleave_matrix_outer_dim_from_partitions, roundup_to_integer_multiple, + qonnx_make_model ) -from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp +from finn.custom_op.fpgadataflow.hwcustomop import HWCustomOp from finn.util.data_packing import ( npy_to_rtlsim_input, numpy_to_hls_code, pack_innermost_dim_as_hex_string, rtlsim_output_to_npy, ) +import qonnx.core.data_layout as DataLayout +import finn.core.onnx_exec as oxe +from qonnx.transformation.infer_shapes import InferShapes +import onnx.numpy_helper as np_helper +from qonnx.transformation.general import GiveUniqueNodeNames + # ONNX i/o tensor shape assumptions for MatrixVectorActivation: # input 0 is the input tensor, shape (.., i_size) = (..., MW) @@ -54,9 +66,8 @@ # the ... here can be any shape (representing groups of vectors) -class MatrixVectorActivation(HLSCustomOp): - """Class that corresponds to finn-hls Matrix_Vector_Activate(_Stream)_Batch - function.""" +class MatrixVectorActivation(HWCustomOp): + """Abstraction layer for HW implementation of MatrixVectorActivation layers.""" def __init__(self, onnx_node, **kwargs): super().__init__(onnx_node, **kwargs) @@ -122,10 +133,14 @@ def get_nodeattr_types(self): # vector through the accelerator. This will get rid of any old # weight data from the weight FIFOs. "runtime_writeable_weights": ("i", False, 0, {0, 1}), - } + "preferred_impl_style" : ("s", False, "hls", {"hls", "rtl"}), + } my_attrs.update(super().get_nodeattr_types()) return my_attrs + def base_op_type(self): + return "MatrixVectorActivation" + def calc_wmem(self): """Calculates and returns WMEM.""" mw = self.get_nodeattr("MW") @@ -165,6 +180,61 @@ def infer_node_datatype(self, model): odt = self.get_output_datatype() model.set_tensor_datatype(node.output[0], odt) + def get_input_datatype(self, ind=0): + """Returns FINN DataType of input.""" + # when performing FIFO insertion on an FC layer with ext weights, the ind + # parameter can be > 0 (referring to the weights) so handle that here + if ind == 0: + return DataType[self.get_nodeattr("inputDataType")] + elif ind == 1: + return DataType[self.get_nodeattr("weightDataType")] + else: + raise Exception("Undefined input ind for this layer type") + + def get_weight_datatype(self): + """Returns FINN DataType of weights.""" + return DataType[self.get_nodeattr("weightDataType")] + + def get_output_datatype(self, ind=0): + """Returns FINN DataType of output.""" + return DataType[self.get_nodeattr("outputDataType")] + + def get_instream_width(self, ind=0): + i_bits = self.get_input_datatype().bitwidth() + assert ( + i_bits <= 9 + ), "RTL-based MVAU only supports activations with bit-width up to 9-bits" + in_width = i_bits * self.get_nodeattr("SIMD") + return in_width + + def get_weightstream_width(self): + """Returns weight stream width. Used only in decoupled mode.""" + if ( + self.get_nodeattr("mem_mode") == "decoupled" + or self.get_nodeattr("mem_mode") == "external" + ): + pe = self.get_nodeattr("PE") + simd = self.get_nodeattr("SIMD") + wp = self.get_weight_datatype().bitwidth() + assert ( + wp <= 8 + ), "RTL-based MVAU only supports weights with bit-width up to 8-bits" + w_width = pe * simd * wp + return w_width + else: + return 0 + + def get_outstream_width(self, ind=0): + o_bits = self.get_output_datatype().bitwidth() + out_width = o_bits * self.get_nodeattr("PE") + return out_width + + def get_weightstream_width_padded(self): + """Returns weight stream width padded to a multiple of 8. This is required + by the AXI Stream spec. Used in decoupled mode.""" + weight_width = self.get_weightstream_width() + return roundup_to_integer_multiple(weight_width, 8) + def verify_node(self): info_messages = [] # verify that "backend" is set to "fpgadataflow" @@ -385,6 +455,25 @@ def dsp_estimation(self): else: mult_dsp = 0 return int(mult_dsp) +# # TODO: fix DSP estimations --> depends on fpga_part +# def dsp_estimation(self): +# # multiplication +# # mvu_8sx9 (DSP58): ceil(SIMD/3) +# # mvu_4sx4u (DSP48/DSP58): ceil(PE/4) +# # mvu_8sx8u (DSP48): ceil(PE/2) +# # mvu_lut: 0 +# P = self.get_nodeattr("PE") +# res_type = self.get_nodeattr("resType") +# Q = self.get_nodeattr("SIMD") +# wdt = self.get_weight_datatype() +# W = wdt.bitwidth() +# idt = self.get_input_datatype() +# A = idt.bitwidth() +# if res_type == "dsp": +# mult_dsp = P * Q * np.ceil((W + A) / 48) # TODO: more accurate modelling +# else: +# mult_dsp = 0 +# return int(mult_dsp) def get_exp_cycles(self): pe = self.get_nodeattr("PE") @@ -397,6 +486,27 @@ def get_exp_cycles(self): exp_cycles = (mh / pe) * (mw / simd) * np.prod(num_inp_vec) / mmv return int(exp_cycles) +# # TODO: fix exp_cycles estimations --> depends on fpga_part and clk +# def get_exp_cycles(self): +# # mvu_8sx9 (DSP58): +# # 2 (replay_buffer) + ceil(chainlen/seglen) + 2 (MREG, PREG) + 2 (output reg slice) +# # + MW/SIMD * MH/PE +# # mvu_4sx4u (DSP48/DSP58) / mvu_8sx8u (DSP48): +# # 3 (IN_REG, MREG, PREG) + 2 (replay_buffer) + 2 (output reg slice) + 1 (adder tree SIMD) + 1 (output lane) +# # + MW/SIMD * MH/PE +# # mvu_lut: +# # 2 (replay_buffer) + 1 OR 2 (no MREG OR MREG) + 2 (output reg slice) +# # + MW/SIMD * MH/PE +# pe = self.get_nodeattr("PE") +# simd = self.get_nodeattr("SIMD") +# num_inp_vec = self.get_nodeattr("numInputVectors") +# mh = self.get_nodeattr("MH") +# mw = self.get_nodeattr("MW") +# # since mmv != 1 is not supported yet, we set mmv for now to 1 +# mmv = 1 +# exp_cycles = (mh / pe) * (mw / simd) * np.prod(num_inp_vec) / mmv +# return int(exp_cycles) + def get_input_datatype(self, ind=0): """Returns FINN DataType of input.""" # when performing FIFO insertion on an FC layer with ext weights, the ind @@ -450,17 +560,6 @@ def get_weightstream_width_padded(self): weight_width = self.get_weightstream_width() return roundup_to_integer_multiple(weight_width, 8) - def get_ap_int_max_w(self): - # base class impl (max of inp/out stream widths) - max_of_io = super().get_ap_int_max_w() - # decoupled mode weight stream - weightstream = self.get_weightstream_width() - # single PE weight entry - weight_bits = self.get_weight_datatype().bitwidth() - simd = self.get_nodeattr("SIMD") - single_pe_w = simd * weight_bits - return max([weightstream, max_of_io, single_pe_w]) - def get_folded_input_shape(self, ind=0): mw = self.get_nodeattr("MW") mh = self.get_nodeattr("MH") @@ -505,82 +604,6 @@ def get_number_output_values(self): nf = np.prod(self.get_folded_output_shape()[:-1]) return nf - def get_template_param_values(self): - """Returns the template parameter values according to input, output and weight - data types.""" - ret = dict() - inp_hls_str = self.get_input_datatype().get_hls_datatype_str() - out_hls_str = self.get_output_datatype().get_hls_datatype_str() - inp_is_binary = self.get_input_datatype() == DataType["BINARY"] - # out_is_binary = self.get_output_datatype() == DataType["BINARY"] - wt_is_binary = self.get_weight_datatype() == DataType["BINARY"] - bin_xnor_mode = self.get_nodeattr("binaryXnorMode") == 1 - if (inp_is_binary or wt_is_binary) and (not bin_xnor_mode): - raise Exception("True binary (non-bipolar) inputs not yet supported") - inp_is_bipolar = self.get_input_datatype() == DataType["BIPOLAR"] - # out_is_bipolar = self.get_output_datatype() == DataType["BIPOLAR"] - wt_is_bipolar = self.get_weight_datatype() == DataType["BIPOLAR"] - # reinterpret inp/wt as bipolar if bin_xnor_mode is iset - inp_is_bipolar = inp_is_bipolar or (inp_is_binary and bin_xnor_mode) - wt_is_bipolar = wt_is_bipolar or (wt_is_binary and bin_xnor_mode) - # fill in TSrcI and TWeightI - # TODO check these with Giulio - # TODO handle non-bipolar binary inputs - if inp_is_bipolar and wt_is_bipolar: - ret["TSrcI"] = "Recast" - ret["TWeightI"] = "Identity" - elif (not inp_is_bipolar) and wt_is_bipolar: - ret["TSrcI"] = "Slice<%s>" % inp_hls_str - ret["TWeightI"] = "Recast" - elif inp_is_bipolar and (not wt_is_bipolar): - ret["TSrcI"] = "Recast" - ret["TWeightI"] = "Identity" - elif (not inp_is_bipolar) and (not wt_is_bipolar): - ret["TSrcI"] = "Slice<%s>" % inp_hls_str - ret["TWeightI"] = "Identity" - - # fill in TDstI - ret["TDstI"] = "Slice<%s>" % out_hls_str - - return ret - - def get_hls_compatible_weight_tensor(self, orig_weight_matrix): - """Convert the original numpy weight matrix orig_weight_matrix into - a form suitable for passing to the hlslib call: - * ensure MH % PE == 0 and MW % SIMD == 0 - * for bipolar {-1,+1} weights, convert to binary {0, 1} - * interleave rows between PEs - * reshape into (1, PE, WMEM, SIMD) and return - """ - mw = self.get_nodeattr("MW") - mh = self.get_nodeattr("MH") - pe = self.get_nodeattr("PE") - simd = self.get_nodeattr("SIMD") - wmem = self.calc_wmem() - assert orig_weight_matrix.shape == ( - mw, - mh, - ), """Weights matrix doesn't - have expected shape (mw, mh)""" - assert mw % simd == 0, "Requirement MH divisable by SIMD is violated." - assert mh % pe == 0, "Requirement MH divisable by PE is violated." - # start by transposing the original weight matrix, since ONNX and - # finn-hlslib use different assumptions - # ONNX uses (in_features, out_features) and matmul(x, W) - # finn-hlslib uses (out_features, in_features) and matmul(W, x) - ret = orig_weight_matrix.T - if self.get_weight_datatype() == DataType["BIPOLAR"]: - # convert bipolar to binary - ret = (ret + 1) / 2 - # interleave rows between PEs and reshape - # distribute rows between PEs - ret = interleave_matrix_outer_dim_from_partitions(ret, pe) - # create SIMD as innermost dimension and add a dummy outer dim - ret = ret.reshape(1, pe, wmem, simd) - # reverse the SIMD dimension - ret = np.flip(ret, axis=-1) - return ret - def minimize_accumulator_width(self, model): """Minimize the accumulator bit width according to the weight values, input data types, and size of dot product""" @@ -728,6 +751,43 @@ def get_hls_compatible_threshold_tensor(self, orig_thres_matrix): rows between PEs is not as expected (n_thres_steps)""" return ret.reshape(1, pe, tmem, n_thres_steps) + def get_hls_compatible_weight_tensor(self, orig_weight_matrix): + """Convert the original numpy weight matrix orig_weight_matrix into + a form suitable for passing to the hlslib call: + * ensure MH % PE == 0 and MW % SIMD == 0 + * for bipolar {-1,+1} weights, convert to binary {0, 1} + * interleave rows between PEs + * reshape into (1, PE, WMEM, SIMD) and return + """ + mw = self.get_nodeattr("MW") + mh = self.get_nodeattr("MH") + pe = self.get_nodeattr("PE") + simd = self.get_nodeattr("SIMD") + wmem = self.calc_wmem() + assert orig_weight_matrix.shape == ( + mw, + mh, + ), """Weights matrix doesn't + have expected shape (mw, mh)""" + assert mw % simd == 0, "Requirement MH divisable by SIMD is violated." + assert mh % pe == 0, "Requirement MH divisable by PE is violated." + # start by transposing the original weight matrix, since ONNX and + # finn-hlslib use different assumptions + # ONNX uses (in_features, out_features) and matmul(x, W) + # finn-hlslib uses (out_features, in_features) and matmul(W, x) + ret = orig_weight_matrix.T + if self.get_weight_datatype() == DataType["BIPOLAR"]: + # convert bipolar to binary + ret = (ret + 1) / 2 + # interleave rows between PEs and reshape + # distribute rows between PEs + ret = interleave_matrix_outer_dim_from_partitions(ret, pe) + # create SIMD as innermost dimension and add a dummy outer dim + ret = ret.reshape(1, pe, wmem, simd) + # reverse the SIMD dimension + ret = np.flip(ret, axis=-1) + return ret + def make_weight_file(self, weights, weight_file_mode, weight_file_name): """Produce a file containing given weights in appropriate format for this layer. This file can be used for either synthesis or run-time reconfig @@ -905,402 +965,68 @@ def generate_params(self, model, path): f_thresh.write(thresholds_hls_code) f_thresh.close() - def execute_node(self, context, graph): - mode = self.get_nodeattr("exec_mode") - mem_mode = self.get_nodeattr("mem_mode") - node = self.onnx_node - - # TODO ensure codegen dir exists - if mode == "cppsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - elif mode == "rtlsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) - - # create a npy file fore each input of the node (in_ind is input index) - in_ind = 0 - for inputs in node.input: - # it is assumed that the first input of the node is the data input - # the second input are the weights - # the third input are the thresholds - if in_ind == 0: - assert ( - str(context[inputs].dtype) == "float32" - ), """Input datatype is - not float32 as expected.""" - expected_inp_shape = self.get_folded_input_shape() - reshaped_input = context[inputs].reshape(expected_inp_shape) - if self.get_input_datatype() == DataType["BIPOLAR"]: - # store bipolar activations as binary - reshaped_input = (reshaped_input + 1) / 2 - export_idt = DataType["BINARY"] - else: - export_idt = self.get_input_datatype() - # make copy before saving the array - reshaped_input = reshaped_input.copy() - np.save( - os.path.join(code_gen_dir, "input_{}.npy".format(in_ind)), - reshaped_input, - ) - elif in_ind > 2: - raise Exception("Unexpected input found for MatrixVectorActivation") - in_ind += 1 - - if mode == "cppsim": - # execute the precompiled model - super().exec_precompiled_singlenode_model() - # load output npy file - super().npy_to_dynamic_output(context) - # reinterpret binary output as bipolar where needed - if self.get_output_datatype() == DataType["BIPOLAR"]: - out = context[node.output[0]] - out = 2 * out - 1 - context[node.output[0]] = out - assert ( - context[node.output[0]].shape == self.get_normal_output_shape() - ), "cppsim did not produce expected output shape" - elif mode == "rtlsim": - sim = self.get_rtlsim() - nbits = self.get_instream_width() - inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) - super().reset_rtlsim(sim) - super().toggle_clk(sim) - if mem_mode == "external" or mem_mode == "decoupled": - wnbits = self.get_weightstream_width() - export_wdt = self.get_weight_datatype() - # we have converted bipolar weights to binary for export, - # so use it as such for weight generation - if self.get_weight_datatype() == DataType["BIPOLAR"]: - export_wdt = DataType["BINARY"] - wei = npy_to_rtlsim_input("{}/weights.npy".format(code_gen_dir), export_wdt, wnbits) - num_w_reps = np.prod(self.get_nodeattr("numInputVectors")) - io_dict = { - "inputs": {"in0": inp, "weights": wei * num_w_reps}, - "outputs": {"out": []}, - } - self.rtlsim_multi_io(sim, io_dict) - output = io_dict["outputs"]["out"] - else: - output = self.rtlsim(sim, inp) - odt = self.get_output_datatype() - target_bits = odt.bitwidth() - packed_bits = self.get_outstream_width() - out_npy_path = "{}/output.npy".format(code_gen_dir) - out_shape = self.get_folded_output_shape() - rtlsim_output_to_npy(output, out_npy_path, odt, out_shape, packed_bits, target_bits) - - # load and reshape output - output = np.load(out_npy_path) - oshape = self.get_normal_output_shape() - output = np.asarray([output], dtype=np.float32).reshape(*oshape) - context[node.output[0]] = output - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) - - def global_includes(self): - self.code_gen_dict["$GLOBALS$"] = ['#include "weights.hpp"'] - self.code_gen_dict["$GLOBALS$"] += ['#include "activations.hpp"'] - - mem_mode = self.get_nodeattr("mem_mode") - if mem_mode not in ["const", "decoupled", "external"]: - raise Exception( - """Please set mem_mode to "const", "decoupled", or "external", - currently no other parameter value is supported!""" - ) - self.code_gen_dict["$GLOBALS$"] += ['#include "mvau.hpp"'] - if self.calc_tmem() != 0: - # TODO find a better way of checking for no pregenerated thresholds - self.code_gen_dict["$GLOBALS$"] += ['#include "thresh.h"'] - - def defines(self, var): - # Only ipgen mode: Make sure that SIMD parameter satisfies minimum requirements. - if var == "ipgen": - SIMD = self.get_nodeattr("SIMD") - MW = self.get_nodeattr("MW") - condition = SIMD >= (MW / 1024) - msg = ( - f"HLS synthesis of MatrixVectorActivation requires: " - f"SIMD >= MW / 1024. This is not fulfilled with: SIMD={SIMD} " - f"and MW={MW} for node: {self.onnx_node.name}." - ) - assert condition, msg - mem_mode = self.get_nodeattr("mem_mode") - numInputVectors = list(self.get_nodeattr("numInputVectors")) - numReps = np.prod(numInputVectors) - self.code_gen_dict["$DEFINES$"] = [ - """#define MW1 {}\n #define MH1 {}\n - #define SIMD1 {}\n #define PE1 {}\n #define WMEM1 {}\n - #define TMEM1 {}\n #define numReps {}""".format( - self.get_nodeattr("MW"), - self.get_nodeattr("MH"), - self.get_nodeattr("SIMD"), - self.get_nodeattr("PE"), - self.calc_wmem(), - self.calc_tmem(), - numReps, - ) - ] - if mem_mode == "decoupled" or mem_mode == "external": - wdt = self.get_weight_datatype() - self.code_gen_dict["$DEFINES$"].append("#define WP1 {}\n".format(wdt.bitwidth())) - - def read_npy_data(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_input_datatype() - if dtype == DataType["BIPOLAR"]: - # use binary for bipolar storage - dtype = DataType["BINARY"] - elem_bits = dtype.bitwidth() - packed_bits = self.get_instream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_in = "%s/input_0.npy" % code_gen_dir - self.code_gen_dict["$READNPYDATA$"] = [] - # note: the innermost dim is reversed for the input - self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s, false);' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - npy_in, - self.hls_sname(), - ) - ) - - mem_mode = self.get_nodeattr("mem_mode") - if mem_mode == "decoupled" or mem_mode == "external": - wdt = self.get_weight_datatype() - elem_bits = wdt.bitwidth() - packed_bits = self.get_weightstream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = wdt.get_hls_datatype_str() - npy_type = "float" - npy_in = "%s/weights.npy" % code_gen_dir - - self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", weights_%s, false, numReps);' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - npy_in, - self.hls_sname(), - ) - ) - - def strm_decl(self): - mem_mode = self.get_nodeattr("mem_mode") - self.code_gen_dict["$STREAMDECLARATIONS$"] = [] - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0_{} ("in0_{}");'.format( - self.get_instream_width(), self.hls_sname(), self.hls_sname() - ) - ) - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out_{} ("out_{}");'.format( - self.get_outstream_width(), self.hls_sname(), self.hls_sname() - ) - ) - - if mem_mode == "decoupled" or mem_mode == "external": - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> weights_{} ("weights_{}");'.format( - self.get_weightstream_width(), self.hls_sname(), self.hls_sname() - ) - ) + def get_op_and_param_counts(self): + in_features = self.get_nodeattr("MW") + out_features = self.get_nodeattr("MH") + weight_bits = self.get_weight_datatype().bitwidth() + inp_bits = self.get_input_datatype().bitwidth() + num_inp_vec = self.get_nodeattr("numInputVectors") + num_repetitions = int(np.prod(num_inp_vec)) + mac_count = in_features * out_features * num_repetitions + # cannonicalize op type: highest bitwidth operand first s.t. + # e.g. mac_8bx4b and mac_4bx8b don't appear as two different op types + bw1 = min(inp_bits, weight_bits) + bw2 = max(inp_bits, weight_bits) + mac_op_type = "op_mac_%dbx%db" % (bw1, bw2) + weight_param_type = "param_weight_%db" % (weight_bits) + weight_count = in_features * out_features + ret_dict = {mac_op_type: mac_count, weight_param_type: weight_count} + if self.get_nodeattr("noActivation") == 0: + tdt = DataType[self.get_nodeattr("accDataType")] + thres_bits = tdt.bitwidth() + thres_param_type = "param_threshold_%db" % (thres_bits) + thres_count = out_features + ret_dict[thres_param_type] = thres_count + return ret_dict - def docompute(self): - mem_mode = self.get_nodeattr("mem_mode") - map_to_hls_mult_style = { - "auto": "ap_resource_dflt()", - "lut": "ap_resource_lut()", - "dsp": "ap_resource_dsp()", + def derive_characteristic_fxns(self, period): + n_inps = np.prod(self.get_folded_input_shape()[:-1]) + io_dict = { + "inputs": { + "in0": [0 for i in range(n_inps)], + }, + "outputs": {"out": []}, } - tmpl_args = self.get_template_param_values() - if self.calc_tmem() == 0: - odtype_hls_str = self.get_output_datatype().get_hls_datatype_str() - threshs = "PassThroughActivation<%s>()" % odtype_hls_str - else: - threshs = "threshs" - if mem_mode == "const": - self.code_gen_dict["$DOCOMPUTE$"] = [ - """Matrix_Vector_Activate_Batch - (in0_{}, out_{}, weights, {}, numReps, {});""".format( - tmpl_args["TSrcI"], - tmpl_args["TDstI"], - tmpl_args["TWeightI"], - self.hls_sname(), - self.hls_sname(), - threshs, - map_to_hls_mult_style[self.get_nodeattr("resType")], - ) - ] - elif mem_mode == "decoupled" or mem_mode == "external": - wdt = self.get_weight_datatype() - if wdt == DataType["BIPOLAR"]: - export_wdt = DataType["BINARY"] - else: - export_wdt = wdt - wdtype_hls_str = export_wdt.get_hls_datatype_str() - self.code_gen_dict["$DOCOMPUTE$"] = [ - """Matrix_Vector_Activate_Stream_Batch - (in0_{}, out_{}, weights_{}, {}, numReps, {});""".format( - tmpl_args["TSrcI"], - tmpl_args["TDstI"], - tmpl_args["TWeightI"], - wdtype_hls_str, - self.hls_sname(), - self.hls_sname(), - self.hls_sname(), - threshs, - map_to_hls_mult_style[self.get_nodeattr("resType")], - ) - ] - - else: - raise Exception( - """Please set mem_mode to "const", "decoupled", or "external", - currently no other parameter value is supported!""" - ) - - def dataoutstrm(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_output_datatype() - if dtype == DataType["BIPOLAR"]: - # use binary for bipolar storage - dtype = DataType["BINARY"] - elem_bits = dtype.bitwidth() - packed_bits = self.get_outstream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_out = "%s/output.npy" % code_gen_dir - shape = self.get_folded_output_shape() - shape_cpp_str = str(shape).replace("(", "{").replace(")", "}") - - # note: the innermost dim is not reversed for the output - self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s", false);' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - self.hls_sname(), - shape_cpp_str, - npy_out, - ) - ] - - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - - def blackboxfunction(self): - mem_mode = self.get_nodeattr("mem_mode") - if mem_mode == "const": - self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - """void {}(hls::stream> &in0_{}, - hls::stream> &out_{} - )""".format( - self.onnx_node.name, - self.get_instream_width(), - self.hls_sname(), - self.get_outstream_width(), - self.hls_sname(), - ) - ] - elif mem_mode == "decoupled" or mem_mode == "external": - self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - """void {}( - hls::stream> &in0_{}, - hls::stream> &weights_{}, - hls::stream> &out_{} - )""".format( - self.onnx_node.name, - self.get_instream_width(), - self.hls_sname(), - self.get_weightstream_width(), - self.hls_sname(), - self.get_outstream_width(), - self.hls_sname(), - ) - ] - - else: - raise Exception( - """Please set mem_mode to "const" or "decoupled", currently no other - parameter value is supported!""" - ) - - def pragmas(self): mem_mode = self.get_nodeattr("mem_mode") - ram_style_thresholds = self.get_nodeattr("ram_style_thresholds") - self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() - ] - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() - ) - self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") - - if mem_mode == "const": - self.code_gen_dict["$PRAGMAS$"].append('#include "params.h"') - # the weight tensor is ap_uint [PE][WMEM] - # partition for parallel access along the PE dimension (dim 1) - self.code_gen_dict["$PRAGMAS$"].append( - ("#pragma HLS ARRAY_PARTITION variable=weights.m_weights " "complete dim=1") - ) - elif mem_mode == "decoupled" or mem_mode == "external": - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=weights_" + self.hls_sname() - ) + if mem_mode in ["decoupled", "external"]: + n_weight_inps = self.calc_wmem() + num_w_reps = np.prod(self.get_nodeattr("numInputVectors")) + io_dict["inputs"]["weights"] = [0 for i in range(num_w_reps * n_weight_inps)] + super().derive_characteristic_fxns(period, override_rtlsim_dict=io_dict) + def execute_node(self, context, graph): + node = self.onnx_node + in_act = context[node.input[0]] + mvau_w_init = [x for x in graph.initializer if x.name == node.input[1]][0] + mvau_w = np_helper.to_array(mvau_w_init) + # Matrix multiplication + if self.get_nodeattr("binaryXnorMode"): + # Note: activation/weights are expected to be binary (by design coming from the transformation inferring this operation mode) + result = xp.xnorpopcountmatmul(in_act, mvau_w) + elif (self.get_nodeattr("inputDataType") == "BIPOLAR" and self.get_nodeattr("weightDataType") == "BIPOLAR"): + result = xp.xnorpopcountmatmul((in_act+1)/2, (mvau_w+1)/2) else: - raise Exception( - """Please set mem_mode to "const", "decoupled", or external, - currently no other parameter value is supported!""" - ) - - # the threshold tensor is acc_type [PE][TMEM][N_THRES] - # partition for parallel access along PE and N_THRES - # dimensions (dims 1 and 3) - if self.calc_tmem() != 0: - # TODO find a better way of checking for no pregenerated thresholds - self.code_gen_dict["$PRAGMAS$"].append( - ("#pragma HLS ARRAY_PARTITION variable=threshs.m_thresholds " "complete dim=1") - ) - self.code_gen_dict["$PRAGMAS$"].append( - ("#pragma HLS ARRAY_PARTITION variable=threshs.m_thresholds " "complete dim=3") - ) - # add resource pragma for thresholds if set - if ram_style_thresholds == "distributed": - self.code_gen_dict["$PRAGMAS$"].append( - ("#pragma HLS RESOURCE variable=threshs.m_thresholds " "core=ROM_2P_LUTRAM") - ) - elif ram_style_thresholds == "block": - self.code_gen_dict["$PRAGMAS$"].append( - ("#pragma HLS RESOURCE variable=threshs.m_thresholds " "core=ROM_2P_BRAM") - ) - elif ram_style_thresholds == "auto": - # no pragma needed - pass - else: - raise Exception("Unrecognized ram_style_thresholds value:" + ram_style_thresholds) + result = np.matmul(in_act, mvau_w) + # Thresholding if noActivation==0 + if self.get_nodeattr("noActivation") == 0: + mvau_thr_init = [x for x in graph.initializer if x.name == node.input[2]][0] + mvau_thr = np_helper.to_array(mvau_thr_init) + odt_is_bipolar = self.get_nodeattr("outputDataType") == DataType["BIPOLAR"] + out_scale = 2 if odt_is_bipolar else 1 + out_bias = -1 if odt_is_bipolar else self.get_nodeattr("ActVal") + result = multithreshold(result, mvau_thr, out_scale, out_bias) + + context[node.output[0]] = result def code_generation_ipi(self): cmd = [] @@ -1324,22 +1050,51 @@ def code_generation_ipi(self): cmd.append("create_bd_pin -dir I -type rst /%s/%s" % (node_name, rst_name)) cmd.append( "create_bd_intf_pin -mode Master " - "-vlnv xilinx.com:interface:axis_rtl:1.0 /%s/%s" % (node_name, dout_name) + "-vlnv xilinx.com:interface:axis_rtl:1.0 /%s/%s" + % (node_name, dout_name) ) cmd.append( "create_bd_intf_pin -mode Slave " "-vlnv xilinx.com:interface:axis_rtl:1.0 /%s/%s" % (node_name, din_name) ) - # instantiate the hls ip - cmd.append( - "create_bd_cell -type ip -vlnv %s /%s/%s" - % (self.get_nodeattr("ip_vlnv"), node_name, node_name) - ) + is_rtl_op = self.__class__.__name__ == "MatrixVectorActivation_rtl" + if is_rtl_op: + # instantiate the RTL block + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + rtllib_dir = os.path.join(os.environ["FINN_ROOT"], "finn-rtllib/mvu/") + sourcefiles = [ + os.path.join( + code_gen_dir, self.get_nodeattr("gen_top_module") + "_wrapper.v" + ), + rtllib_dir + "mvu_vvu_axi.sv", + rtllib_dir + "replay_buffer.sv", + rtllib_dir + "mvu_4sx4u.sv", + rtllib_dir + "mvu_vvu_8sx9_dsp58.sv", + rtllib_dir + "mvu_8sx8u_dsp48.sv", + ] + for f in sourcefiles: + cmd.append("add_files -norecurse %s" % (f)) + cmd.append( + "create_bd_cell -type hier -reference %s /%s/%s" + % ( + self.get_nodeattr("gen_top_module"), + self.onnx_node.name, + self.onnx_node.name, + ) + ) + else: + # instantiate the hls ip + cmd.append( + "create_bd_cell -type ip -vlnv %s /%s/%s" + % (self.get_nodeattr("ip_vlnv"), node_name, node_name) + ) + # instantiate a streamer and connect it to the HLS IP strm_vlnv = "amd.com:finn:memstream:1.0" strm_inst = node_name + "_wstrm" cmd.append( - "create_bd_cell -type ip -vlnv %s /%s/%s" % (strm_vlnv, node_name, strm_inst) + "create_bd_cell -type ip -vlnv %s /%s/%s" + % (strm_vlnv, node_name, strm_inst) ) cmd.append( "set_property -dict [list " @@ -1393,7 +1148,8 @@ def code_generation_ipi(self): axilite_name = self.get_verilog_top_module_intf_names()["axilite"][0] cmd.append( "create_bd_intf_pin -mode Slave " - "-vlnv xilinx.com:interface:aximm_rtl:1.0 /%s/%s" % (node_name, axilite_name) + "-vlnv xilinx.com:interface:aximm_rtl:1.0 /%s/%s" + % (node_name, axilite_name) ) cmd.append( "connect_bd_intf_net [get_bd_intf_pins %s/%s] " @@ -1404,60 +1160,32 @@ def code_generation_ipi(self): cmd.append("assign_bd_address") cmd.append("save_bd_design") elif mem_mode == "const" or mem_mode == "external": - # base class impl sufficient for const/external modes - return super().code_generation_ipi() + if is_rtl_op and mem_mode == "external": + # instantiate the RTL block + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + rtllib_dir = os.path.join(os.environ["FINN_ROOT"], "finn-rtllib/mvu/") + sourcefiles = [ + os.path.join( + code_gen_dir, self.get_nodeattr("gen_top_module") + "_wrapper.v" + ), + rtllib_dir + "mvu_vvu_axi.sv", + rtllib_dir + "replay_buffer.sv", + rtllib_dir + "mvu_4sx4u.sv", + rtllib_dir + "mvu_vvu_8sx9_dsp58.sv", + rtllib_dir + "mvu_8sx8u_dsp48.sv", + ] + for f in sourcefiles: + cmd.append("add_files -norecurse %s" % (f)) + cmd.append( + "create_bd_cell -type module -reference %s %s" + % ( + self.get_nodeattr("gen_top_module"), + self.onnx_node.name, + ) + ) + else: + # base class impl sufficient for const/external modes + return super().code_generation_ipi() else: raise Exception("Unrecognized mem_mode for MatrixVectorActivation") - return cmd - - def get_verilog_top_module_intf_names(self): - intf_names = super().get_verilog_top_module_intf_names() - mem_mode = self.get_nodeattr("mem_mode") - sname = self.hls_sname() - if mem_mode == "external": - intf_names["s_axis"].append(("weights_" + sname, self.get_weightstream_width_padded())) - if mem_mode == "decoupled": - # only expose axilite interface if attribute is set - runtime_writable = self.get_nodeattr("runtime_writeable_weights") == 1 - if runtime_writable: - intf_names["axilite"] = ["s_axilite"] - return intf_names - - def get_op_and_param_counts(self): - in_features = self.get_nodeattr("MW") - out_features = self.get_nodeattr("MH") - weight_bits = self.get_weight_datatype().bitwidth() - inp_bits = self.get_input_datatype().bitwidth() - num_inp_vec = self.get_nodeattr("numInputVectors") - num_repetitions = int(np.prod(num_inp_vec)) - mac_count = in_features * out_features * num_repetitions - # cannonicalize op type: highest bitwidth operand first s.t. - # e.g. mac_8bx4b and mac_4bx8b don't appear as two different op types - bw1 = min(inp_bits, weight_bits) - bw2 = max(inp_bits, weight_bits) - mac_op_type = "op_mac_%dbx%db" % (bw1, bw2) - weight_param_type = "param_weight_%db" % (weight_bits) - weight_count = in_features * out_features - ret_dict = {mac_op_type: mac_count, weight_param_type: weight_count} - if self.get_nodeattr("noActivation") == 0: - tdt = DataType[self.get_nodeattr("accDataType")] - thres_bits = tdt.bitwidth() - thres_param_type = "param_threshold_%db" % (thres_bits) - thres_count = out_features - ret_dict[thres_param_type] = thres_count - return ret_dict - - def derive_characteristic_fxns(self, period): - n_inps = np.prod(self.get_folded_input_shape()[:-1]) - io_dict = { - "inputs": { - "in0": [0 for i in range(n_inps)], - }, - "outputs": {"out": []}, - } - mem_mode = self.get_nodeattr("mem_mode") - if mem_mode in ["decoupled", "external"]: - n_weight_inps = self.calc_wmem() - num_w_reps = np.prod(self.get_nodeattr("numInputVectors")) - io_dict["inputs"]["weights"] = [0 for i in range(num_w_reps * n_weight_inps)] - super().derive_characteristic_fxns(period, override_rtlsim_dict=io_dict) + return cmd \ No newline at end of file From 0cb2d594c1a67abff4167c3dfa8f1c34b1f612f6 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 26 Jan 2024 11:46:51 +0000 Subject: [PATCH 454/665] [VVAU hw custom-op]: add base_op_type method --- src/finn/custom_op/fpgadataflow/vectorvectoractivation.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index bd5bb75f1d..891730ece3 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -104,6 +104,9 @@ def get_nodeattr_types(self): my_attrs.update(super().get_nodeattr_types()) return my_attrs + def base_op_type(self): + return "VectorVectorActivation" + def minimize_accumulator_width(self, model): """Minimize the accumulator bit width according to the weight values, input data types, and size of dot product""" From 627639ab09b708861db05a97bda2d544ed314d65 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 26 Jan 2024 11:47:27 +0000 Subject: [PATCH 455/665] [transform]: add transformation to infer MVAU hw custom-op --- .../fpgadataflow/convert_to_hw_layers.py | 136 ++++++++++++++++++ 1 file changed, 136 insertions(+) diff --git a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py index d1d61f0ed5..eb6dd337f5 100644 --- a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py +++ b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py @@ -1280,3 +1280,139 @@ def apply(self, model): graph_modified = True return (model, graph_modified) + +class InferQuantizedMatrixVectorActivation(Transformation): + """Convert MatMul layers with quantized inputs and weights to + MatrixVectorActivation layers.""" + + def __init__(self, mem_mode="const"): + super().__init__() + self.mem_mode = mem_mode + + def apply(self, model): + graph = model.graph + node_ind = 0 + graph_modified = False + for n in graph.node: + node_ind += 1 + if n.op_type == "MatMul" and model.get_tensor_sparsity(n.input[1]) is None: + mm_input = n.input[0] + mm_weight = n.input[1] + mm_output = n.output[0] + mm_in_shape = model.get_tensor_shape(mm_input) + mm_out_shape = model.get_tensor_shape(mm_output) + idt = model.get_tensor_datatype(mm_input) + wdt = model.get_tensor_datatype(mm_weight) + if idt.is_integer() and wdt.is_integer(): + mm_output = n.output[0] + W = model.get_initializer(mm_weight) + # extract weight shape, note that ONNX and finn-hlslib + # make different assumptions about dim order here + # ONNX assumes W has (in, out) shape + # finn-hlslib assumes W has (out, in) shape + mh = int(W.shape[1]) + mw = int(W.shape[0]) + # create node with no parallelization first + pe = 1 + simd = 1 + wmem = mw * mh // (pe * simd) + assert mw * mh == wmem * pe * simd, ( + n.name + + """: Requirement (MW * MH) divisible by + (WMEM * PE * SIMD) is violated.""" + ) + # see if we have any following thresholds + consumer = model.find_consumer(mm_output) + if consumer is not None and consumer.op_type == "MultiThreshold": + # TODO ensure integer thresholds? + # create MVTU (i.e. including activation) + mt_output = consumer.output[0] + mt_out_shape = model.get_tensor_shape(mt_output) + mt_thres = consumer.input[1] + T = model.get_initializer(mt_thres) + assert T.shape[0] == 1 or T.shape[0] == mh, ( + consumer.name + + """: First dimension of + thresholds neither 1 nor MH.""" + ) + odt = model.get_tensor_datatype(mt_output) + scale = getCustomOp(consumer).get_nodeattr("out_scale") + actval = getCustomOp(consumer).get_nodeattr("out_bias") + assert int(actval) == actval, ( + consumer.name + ": out_bias must be integer for HLS conversion." + ) + actval = int(actval) + odt_is_bipolar = odt == DataType["BIPOLAR"] + bipolar_ok = odt_is_bipolar and (scale == 2.0) and (actval == -1) + assert scale == 1.0 or bipolar_ok, ( + consumer.name + ": out_scale=1 or bipolar output needed for conversion." + ) + assert (not odt.signed()) or (actval < 0), ( + consumer.name + ": Signed output requres actval < 0" + ) + model.set_tensor_shape(mm_input, mm_in_shape) + model.set_tensor_shape(mt_output, mt_out_shape) + if bipolar_ok: + # remove bias for bipolar, since + # binary->bipolar is achieved by reinterpretation + actval = 0 + # create and insert new MatrixVectorActivation node + new_node = helper.make_node( + "MatrixVectorActivation", + [mm_input, mm_weight, mt_thres], + [mt_output], + domain="finn.custom_op.fpgadataflow", + backend="fpgadataflow", + MW=mw, + MH=mh, + SIMD=simd, + PE=pe, + inputDataType=idt.name, + weightDataType=wdt.name, + outputDataType=odt.name, + ActVal=actval, + binaryXnorMode=0, + noActivation=0, + numInputVectors=list(mm_in_shape[:-1]), + mem_mode=self.mem_mode, + name="MatrixVectorActivation_" + n.name, + ) + graph.node.insert(node_ind, new_node) + # remove old nodes + graph.node.remove(n) + graph.node.remove(consumer) + graph_modified = True + else: + # no activation, matmul only + odt = model.get_tensor_datatype(mm_output) + model.set_tensor_shape(mm_input, mm_in_shape) + model.set_tensor_shape(mm_output, mm_out_shape) + # create and insert new MatrixVectorActivation node + new_node = helper.make_node( + "MatrixVectorActivation", + [mm_input, mm_weight], + [mm_output], + domain="finn.custom_op.fpgadataflow", + backend="fpgadataflow", + MW=mw, + MH=mh, + SIMD=simd, + PE=pe, + inputDataType=idt.name, + weightDataType=wdt.name, + outputDataType=odt.name, + ActVal=0, + binaryXnorMode=0, + noActivation=1, + numInputVectors=list(mm_in_shape[:-1]), + mem_mode=self.mem_mode, + name="MatrixVectorActivation_" + n.name, + ) + graph.node.insert(node_ind, new_node) + # remove old node + graph.node.remove(n) + graph_modified = True + if graph_modified: + model = model.transform(InferShapes()) + model = model.transform(InferDataTypes()) + return (model, graph_modified) \ No newline at end of file From cd3d431331a0a9afa41ad3cbe3f721529e8bd1f2 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 26 Jan 2024 12:46:06 +0000 Subject: [PATCH 456/665] [test mvau]: modified to support new custom-ops --- tests/fpgadataflow/test_fpgadataflow_mvau.py | 120 +++++++++++++++++-- 1 file changed, 113 insertions(+), 7 deletions(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_mvau.py b/tests/fpgadataflow/test_fpgadataflow_mvau.py index b80ef76a19..bd283855e3 100644 --- a/tests/fpgadataflow/test_fpgadataflow_mvau.py +++ b/tests/fpgadataflow/test_fpgadataflow_mvau.py @@ -52,6 +52,9 @@ from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from qonnx.transformation.general import ApplyConfig, GiveUniqueNodeNames, GiveReadableTensorNames +from qonnx.transformation.infer_shapes import InferShapes +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers def make_single_fclayer_modelwrapper(W, pe, simd, wdt, idt, odt, T=None, tdt=None): @@ -135,6 +138,87 @@ def prepare_inputs(input_tensor, idt, wdt): return {"inp": input_tensor} +# activation: None or DataType +@pytest.mark.parametrize("act", [None, DataType["BIPOLAR"], DataType["INT4"]]) +# weight datatype +@pytest.mark.parametrize("wdt", [DataType["BIPOLAR"], DataType["INT4"]]) +# input datatype +@pytest.mark.parametrize("idt", [DataType["BIPOLAR"], DataType["INT4"]]) +# neuron folding, -1 is maximum possible +@pytest.mark.parametrize("nf", [-1, 2, 1]) +# synapse folding, -1 is maximum possible +@pytest.mark.parametrize("sf", [-1, 2, 1]) +# HLS matrix width (input features) +@pytest.mark.parametrize("mw", [16]) +# HLS matrix height (output features) +@pytest.mark.parametrize("mh", [16]) +@pytest.mark.fpgadataflow +@pytest.mark.slow +@pytest.mark.vivado +def test_fpgadataflow_fclayer_hwop(idt, wdt, act, nf, sf, mw, mh): + if nf == -1: + nf = mh + if sf == -1: + sf = mw + pe = mh // nf + simd = mw // sf + assert mh % pe == 0 + assert mw % sf == 0 + # generate weights + W = gen_finn_dt_tensor(wdt, (mw, mh)) + # generate input data + x = gen_finn_dt_tensor(idt, (1, mw)) + if act is None: + # no activation, produce accumulators + T = None + tdt = None + if wdt == DataType["BIPOLAR"] and idt == DataType["BIPOLAR"]: + odt = DataType["UINT32"] + else: + odt = DataType["INT32"] + else: + odt = act + (min, max) = calculate_signed_dot_prod_range(idt, wdt, mw) + n_steps = act.get_num_possible_values() - 1 + T = np.random.randint(min, max - 1, (mh, n_steps)).astype(np.float32) + # provide non-decreasing thresholds + T = np.sort(T, axis=1) + # generate thresholds for activation + if wdt == DataType["BIPOLAR"] and idt == DataType["BIPOLAR"]: + tdt = DataType["UINT32"] + # bias thresholds to be positive + T = np.ceil((T + mw) / 2) + assert (T >= 0).all() + else: + tdt = DataType["INT32"] + model = make_single_fclayer_modelwrapper(W, pe, simd, wdt, idt, odt, T, tdt) + # prepare input data + input_dict = prepare_inputs(x, idt, wdt) + if wdt == DataType["BIPOLAR"] and idt == DataType["BIPOLAR"]: + # convert inputs to binary and use xnorpopcountmatmul + y = xp.xnorpopcountmatmul((x + 1) / 2, (W + 1) / 2) + else: + y = np.matmul(x, W) + if T is not None: + # y = multithreshold(y, T) + if act == DataType["BIPOLAR"]: + # binary to bipolar + # y = 2 * y - 1 + y = multithreshold(y, T, 2, -1) + else: + # signed offset + # y += act.min() + y = multithreshold(y, T, 1, act.min()) + oshape = model.get_tensor_shape("outp") + y_expected = y.reshape(oshape) + # execute model + y_produced = oxe.execute_onnx(model, input_dict)["outp"] + + y_produced = y_produced.reshape(y_expected.shape) + + assert (y_produced == y_expected).all(), "cppsim hw-op failed" + + # mem_mode: const or decoupled @pytest.mark.parametrize("mem_mode", ["const", "decoupled", "external"]) # activation: None or DataType @@ -154,7 +238,9 @@ def prepare_inputs(input_tensor, idt, wdt): @pytest.mark.fpgadataflow @pytest.mark.slow @pytest.mark.vivado -def test_fpgadataflow_fclayer_cppsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): +def test_fpgadataflow_fclayer_hlsop_cppsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): + if idt == DataType["BIPOLAR"] and wdt != DataType["BIPOLAR"] or idt != DataType["BIPOLAR"] and wdt == DataType["BIPOLAR"]: + pytest.skip("Bipolar activations/weights only supported in MVU if both operands are bipolar") if nf == -1: nf = mh if sf == -1: @@ -195,6 +281,8 @@ def test_fpgadataflow_fclayer_cppsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): # lookup op_type in registry of CustomOps inst = getCustomOp(node) inst.set_nodeattr("mem_mode", mem_mode) + inst.set_nodeattr("preferred_impl_style", "hls") + model = model.transform(SpecializeLayers()) model = model.transform(SetExecMode("cppsim")) model = model.transform(PrepareCppSim()) model = model.transform(CompileCppSim()) @@ -220,7 +308,7 @@ def test_fpgadataflow_fclayer_cppsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): y_produced = y_produced.reshape(y_expected.shape) - assert (y_produced == y_expected).all(), "cppsim failed" + assert (y_produced == y_expected).all(), "cppsim hls-op failed" # mem_mode: const or decoupled @@ -239,10 +327,14 @@ def test_fpgadataflow_fclayer_cppsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): @pytest.mark.parametrize("mw", [16]) # HLS matrix height (output features) @pytest.mark.parametrize("mh", [16]) +# Backend +@pytest.mark.parametrize("backend", ["rtl", "hls"]) @pytest.mark.fpgadataflow @pytest.mark.slow @pytest.mark.vivado -def test_fpgadataflow_fclayer_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): +def test_fpgadataflow_fclayer_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh, backend): + if backend == "rtl" and act is not None: + pytest.skip("RTL MVU doesn't support embedded thresholding functionality.") if nf == -1: nf = mh if sf == -1: @@ -283,6 +375,7 @@ def test_fpgadataflow_fclayer_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): # lookup op_type in registry of CustomOps inst = getCustomOp(node) inst.set_nodeattr("mem_mode", mem_mode) + inst.set_nodeattr("preferred_impl_style", backend) # prepare input data input_dict = prepare_inputs(x, idt, wdt) @@ -303,6 +396,7 @@ def test_fpgadataflow_fclayer_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): y_expected = y.reshape(oshape) # TODO split up into several dependent tests -- need to check how this # works for parametrized tests... + model = model.transform(SpecializeLayers()) model = model.transform(SetExecMode("rtlsim")) model = model.transform(GiveUniqueNodeNames()) model = model.transform(PrepareIP("xc7z020clg400-1", 5)) @@ -312,7 +406,10 @@ def test_fpgadataflow_fclayer_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): assert (y_produced.reshape(y_expected.shape) == y_expected).all(), "rtlsim failed" hls_synt_res_est = model.analysis(hls_synth_res_estimation) - assert "MatrixVectorActivation_0" in hls_synt_res_est + if backend == "hls": + assert "MatrixVectorActivation_hls_0" in hls_synt_res_est + else: + assert "MatrixVectorActivation_rtl_0" in hls_synt_res_est node = model.get_nodes_by_op_type("MatrixVectorActivation")[0] inst = getCustomOp(node) @@ -339,10 +436,12 @@ def test_fpgadataflow_fclayer_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): @pytest.mark.parametrize("mw", [128]) # HLS matrix height (output features) @pytest.mark.parametrize("mh", [128]) +# Backend +@pytest.mark.parametrize("backend", ["rtl", "hls"]) @pytest.mark.fpgadataflow @pytest.mark.vivado def test_fpgadataflow_fclayer_large_depth_decoupled_mode_rtlsim( - mem_mode, idt, wdt, act, nf, sf, mw, mh + mem_mode, idt, wdt, act, nf, sf, mw, mh, backend ): if nf == -1: nf = mh @@ -404,6 +503,7 @@ def test_fpgadataflow_fclayer_large_depth_decoupled_mode_rtlsim( y_expected = y.reshape(oshape) # TODO split up into several dependent tests -- need to check how this # works for parametrized tests... + model = model.transform(SpecializeLayers()) model = model.transform(SetExecMode("rtlsim")) model = model.transform(GiveUniqueNodeNames()) model = model.transform(PrepareIP("xc7z020clg400-1", 5)) @@ -413,7 +513,10 @@ def test_fpgadataflow_fclayer_large_depth_decoupled_mode_rtlsim( assert (y_produced.reshape(y_expected.shape) == y_expected).all(), "rtlsim failed" hls_synt_res_est = model.analysis(hls_synth_res_estimation) - assert "MatrixVectorActivation_0" in hls_synt_res_est + if backend == "hls": + assert "MatrixVectorActivation_hls_0" in hls_synt_res_est + else: + assert "MatrixVectorActivation_rtl_0" in hls_synt_res_est node = model.get_nodes_by_op_type("MatrixVectorActivation")[0] inst = getCustomOp(node) @@ -440,9 +543,11 @@ def test_fpgadataflow_fclayer_large_depth_decoupled_mode_rtlsim( @pytest.mark.parametrize("mw", [32]) # HLS matrix height (output features) @pytest.mark.parametrize("mh", [32]) +# Backend +@pytest.mark.parametrize("backend", ["rtl", "hls"]) @pytest.mark.fpgadataflow @pytest.mark.vivado -def test_fclayer_fifocharacterize_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): +def test_fclayer_fifocharacterize_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh, backend): if nf == -1: nf = mh if sf == -1: @@ -469,6 +574,7 @@ def test_fclayer_fifocharacterize_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh inst.set_nodeattr("mem_mode", mem_mode) total_fold = nf * sf exp_total_cycles = total_fold + 10 + model = model.transform(SpecializeLayers()) model = model.transform(SetExecMode("rtlsim")) model = model.transform(GiveUniqueNodeNames()) model = model.transform(PrepareIP("xc7z020clg400-1", 5)) From 0348a7c54b29432751e2098670c939b95522be35 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Thu, 1 Feb 2024 14:34:15 +0000 Subject: [PATCH 457/665] [vvau hls]: add custom op to dict --- src/finn/custom_op/fpgadataflow/hls/__init__.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/finn/custom_op/fpgadataflow/hls/__init__.py b/src/finn/custom_op/fpgadataflow/hls/__init__.py index 1f1448b9fc..ebb5ce98da 100644 --- a/src/finn/custom_op/fpgadataflow/hls/__init__.py +++ b/src/finn/custom_op/fpgadataflow/hls/__init__.py @@ -51,6 +51,7 @@ from finn.custom_op.fpgadataflow.hls.tlastmarker_hls import TLastMarker_hls from finn.custom_op.fpgadataflow.hls.upsampler_hls import UpsampleNearestNeighbour_hls from finn.custom_op.fpgadataflow.hls.matrixvectoractivation_hls import MatrixVectorActivation_hls +from finn.custom_op.fpgadataflow.hls.vectorvectoractivation_hls import VectorVectorActivation_hls custom_op = dict() @@ -76,4 +77,5 @@ custom_op["Thresholding_hls"] = Thresholding_hls custom_op["TLastMarker_hls"] = TLastMarker_hls custom_op["UpsampleNearestNeighbour_hls"] = UpsampleNearestNeighbour_hls -custom_op["MatrixVectorActivation_hls"] = MatrixVectorActivation_hls \ No newline at end of file +custom_op["MatrixVectorActivation_hls"] = MatrixVectorActivation_hls +custom_op["VectorVectorActivation_hls"] = VectorVectorActivation_hls \ No newline at end of file From b2c10d899ceeb2dc29c50e823d343a5f8c52a53e Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Thu, 1 Feb 2024 14:35:56 +0000 Subject: [PATCH 458/665] [vvu hw-op]: refactored hw custom-op VVAU --- .../fpgadataflow/vectorvectoractivation.py | 1196 ++++++----------- 1 file changed, 423 insertions(+), 773 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index 891730ece3..2168474298 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -38,17 +38,21 @@ roundup_to_integer_multiple, ) -from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp +from finn.custom_op.fpgadataflow.hwcustomop import HWCustomOp from finn.util.data_packing import ( npy_to_rtlsim_input, numpy_to_hls_code, pack_innermost_dim_as_hex_string, rtlsim_output_to_npy, ) +import onnx.numpy_helper as np_helper +import qonnx.custom_op.general.xnorpopcount as xp +from qonnx.custom_op.general.multithreshold import multithreshold -class VectorVectorActivation(HLSCustomOp): - """Class that corresponds to finn-hlslib Vector_Vector_Activate_Batch function""" + +class VectorVectorActivation(HWCustomOp): + """Abstraction layer for HW implementation of VectorVectorActivation layers.""" def __init__(self, onnx_node, **kwargs): super().__init__(onnx_node, **kwargs) @@ -100,6 +104,10 @@ def get_nodeattr_types(self): # use xnor-popcount for binary weights/inputs, thus treating them # as bipolar "binaryXnorMode": ("i", False, 0, {0, 1}), + # Backend implementation for layer + # hls -- Vivado HLS + # rtl -- (System)Verilog + "preferred_impl_style": ("s", False, "hls", {"hls", "rtl"}), } my_attrs.update(super().get_nodeattr_types()) return my_attrs @@ -107,124 +115,55 @@ def get_nodeattr_types(self): def base_op_type(self): return "VectorVectorActivation" - def minimize_accumulator_width(self, model): - """Minimize the accumulator bit width according to the weight values, - input data types, and size of dot product""" - weights = model.get_initializer(self.onnx_node.input[1]) - k_h, k_w = self.get_nodeattr("Kernel") - fm = self.get_nodeattr("Channels") - # put weights into the shape expected by calculate_matvec_accumulator_range - weights = weights.reshape(fm, k_h * k_w).transpose() - # since in the calculation the values of the weight matrix are used, - # for the bipolar case they need to be converted to bipolar - if self.get_nodeattr("binaryXnorMode"): - weights = 2 * weights - 1 - if len(self.onnx_node.input) > 2: - thresholds = model.get_initializer(self.onnx_node.input[2]) - else: - thresholds = None - idt = self.get_input_datatype() - - (acc_min, acc_max) = calculate_matvec_accumulator_range(weights, idt) - # if runtime-writeable weights, then the values of the weights can - # change and we need to use the worst-case values from the datatypes - if self.get_nodeattr("runtime_writeable_weights"): - wdt = self.get_weight_datatype() - lower_worst = wdt.min() * np.ones_like(weights) - lower_range = calculate_matvec_accumulator_range(lower_worst, idt) - upper_worst = wdt.max() * np.ones_like(weights) - upper_range = calculate_matvec_accumulator_range(upper_worst, idt) - acc_min = min(min(lower_range), min(upper_range)) - acc_max = max(max(upper_range), max(upper_range)) - - # if the thresholds can be used to determine range, then adjust the range - # according to the known values of the thresholds - if thresholds is not None: - threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds) - # set threshold datatype (and accumulator datatype implicitly) - min_threshold = thresholds.min() - max_threshold = thresholds.max() - # clip threshold values - if max_threshold > acc_max or min_threshold < acc_min: - warnings.warn("Clipping some thresholds in %s" % self.onnx_node.name) - thresholds = np.clip(thresholds, acc_min, acc_max) - model.set_initializer(self.onnx_node.input[2], thresholds) - threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds) - min_threshold = thresholds.min() - max_threshold = thresholds.max() - acc_min = min(min_threshold, acc_min) - acc_max = max(max_threshold, acc_max) + def _infer_sparse_weight_tensor(self, W_conv, k_h, k_w, channels): + W_sparse = np.zeros((channels, channels, k_h, k_w), dtype=np.float32) + for ch in range(channels): + W_sparse[ch][ch] = W_conv[ch][0] + W_conv = W_sparse.astype(np.float32) + W_matmul = W_conv.transpose(0, 2, 3, 1) + W_matmul = W_matmul.reshape(channels, channels * k_h * k_w) + W_matmul = W_matmul.T + return W_matmul - # if the acc_range is always greater than 0, then acc_max <= 2^P - 1 - if acc_min >= 0: - acc_bit_width = np.log2(acc_max + 1) - acc_bit_width = math.ceil(acc_bit_width) - adt = DataType[f"UINT{acc_bit_width}"] - # if the acc_range is signed, then acc_min >= -2^{P-1} and acc_max <= - # 2^{P - 1} - 1, which means 2^{P - 1} >= max(-acc_min, 1 + acc_max) + def execute_node(self, context, graph): + node = self.onnx_node + in_act = context[node.input[0]] + (_, dim_h, dim_w, _) = in_act.shape + (k_h, k_w) = self.get_nodeattr("Kernel") + channels = self.get_nodeattr("Channels") + # Reshape input activations in right format + in_act = in_act.reshape(1, dim_h, dim_w, channels, k_h*k_w) + in_act = in_act.transpose(0, 1, 2, 4, 3) + in_act = in_act.reshape(1, dim_h, dim_w, channels*k_h*k_w) + # Reshape + vvau_w_init = [x for x in graph.initializer if x.name == node.input[1]][0] + vvau_w = np_helper.to_array(vvau_w_init) + vvau_w_onnx = self._infer_sparse_weight_tensor(vvau_w, k_h, k_w, channels) + + if self.get_nodeattr("inputDataType") == "BIPOLAR" and self.get_nodeattr("weightDataType") == "BIPOLAR": + result = np.matmul(in_act, vvau_w_onnx) + result = (result + k_h*k_w) / 2 else: - _acc_max = max(-acc_min, 1 + acc_max) - acc_bit_width = np.log2(_acc_max) + 1 - acc_bit_width = math.ceil(acc_bit_width) - adt = DataType[f"INT{acc_bit_width}"] - - # if activation, assert that the thresholds can be expressed with adt - if thresholds is not None: - assert np.vectorize(adt.allowed)( - threshold_tensor - ).all(), "Thresholds in %s can't be expressed with type %s" % ( - self.onnx_node.name, - str(adt), - ) - - # if no activation, output and accumulator datatypes are the same - if self.get_nodeattr("noActivation"): - # if this is the last node in the graph, then ensure the datatype is - # divisibly by 8 bits - if model.find_direct_successors(self.onnx_node) is None: - bw = roundup_to_integer_multiple(adt.bitwidth(), 8) - new_adt_name = adt.name.replace(str(adt.bitwidth()), str(bw)) - adt = DataType[new_adt_name] - # for no-activation nodes, output dt = acc dt - self.set_nodeattr("outputDataType", adt.name) - self.set_nodeattr("accDataType", adt.name) - - return DataType[self.get_nodeattr("accDataType")] - - def minimize_weight_bit_width(self, model): - """Minimize the bit width based on the values of the weights""" - if not self.get_nodeattr("runtime_writeable_weights"): - weights = model.get_initializer(self.onnx_node.input[1]) - w_min = weights.min() - w_max = weights.max() - if w_min < 0: - if abs(w_min) > w_max: - wdt = DataType.get_smallest_possible(w_min) - else: - wdt = DataType.get_smallest_possible(-w_max - 1) - else: - wdt = DataType.get_smallest_possible(w_max) - self.set_nodeattr("weightDataType", wdt.name) - return DataType[self.get_nodeattr("weightDataType")] - - def calc_wmem(self): - """Calculates and returns WMEM.""" - ch = self.get_nodeattr("Channels") - k_h, k_w = self.get_nodeattr("Kernel") - pe = self.get_nodeattr("PE") - simd = self.get_nodeattr("SIMD") - wmem = (k_h * k_w * ch // pe) // simd - return wmem + result = np.matmul(in_act, vvau_w_onnx) # result is in [N, H, W, C] format - def calc_tmem(self): - """Calculates and returns TMEM.""" - if self.get_nodeattr("noActivation") == 1: - return 0 - else: - ch = self.get_nodeattr("Channels") - pe = self.get_nodeattr("PE") - return ch // pe + if self.get_nodeattr("noActivation") == 0: + vvau_thr_init = [x for x in graph.initializer if x.name == node.input[2]][0] + vvau_thr = np_helper.to_array(vvau_thr_init) + odt_is_bipolar = self.get_nodeattr("outputDataType") == DataType["BIPOLAR"] + out_scale = 2 if odt_is_bipolar else 1 + out_bias = -1 if odt_is_bipolar else self.get_nodeattr("ActVal") + # NHWC to NCHW for multithreshold node + result = result.transpose((0,3,1,2)) + result = multithreshold(result, vvau_thr, out_scale, out_bias) + # NCHW to NHWC + result = result.transpose((0,2,3,1)) + + # for i in range(self.get_nodeattr("Channels")): + context[node.output[0]] = result + def verify_node(self): + pass + def make_shape_compatible_op(self, model): oshape = self.get_normal_output_shape() return super().make_const_shape_op(oshape) @@ -244,9 +183,6 @@ def infer_node_datatype(self, model): odt = self.get_output_datatype() model.set_tensor_datatype(node.output[0], odt) - def verify_node(self): - pass - def get_input_datatype(self, ind=0): """Returns FINN DataType of input.""" return DataType[self.get_nodeattr("inputDataType")] @@ -269,12 +205,32 @@ def get_instream_width(self, ind=0): pe = self.get_nodeattr("PE") in_width = i_bits * simd * pe return in_width + + def get_weightstream_width(self): + """Returns weight stream width. Used only in decoupled mode.""" + if ( + self.get_nodeattr("mem_mode") == "decoupled" + or self.get_nodeattr("mem_mode") == "external" + ): + simd = self.get_nodeattr("SIMD") + pe = self.get_nodeattr("PE") + wp = self.get_weight_datatype().bitwidth() + w_width = simd * pe * wp + return w_width + else: + return 0 def get_outstream_width(self, ind=0): o_bits = self.get_output_datatype().bitwidth() out_width = o_bits * self.get_nodeattr("PE") return out_width + def get_weightstream_width_padded(self): + """Returns weight stream width padded to a multiple of 8. This is required + by the AXI Stream spec. Used in decoupled mode.""" + weight_width = self.get_weightstream_width() + return roundup_to_integer_multiple(weight_width, 8) + def get_folded_input_shape(self, ind=0): k_h, k_w = self.get_nodeattr("Kernel") dim_h, dim_w = self.get_nodeattr("Dim") @@ -323,88 +279,302 @@ def get_number_output_values(self): nf = np.prod(self.get_folded_output_shape()[:-1]) return nf - def get_exp_cycles(self): - pe = self.get_nodeattr("PE") - simd = self.get_nodeattr("SIMD") + def calc_wmem(self): + """Calculates and returns WMEM.""" ch = self.get_nodeattr("Channels") - dim_h, dim_w = self.get_nodeattr("Dim") k_h, k_w = self.get_nodeattr("Kernel") - # currently FINN supports for vvau a batch size of 1 - batch_size = 1 - # since mmv != 1 is not supported yet, we set mmv for now to 1 - mmv = 1 - exp_cycles = ((ch * k_h * k_w) / pe / simd) * batch_size * (dim_h * dim_w) / mmv - return int(exp_cycles) + pe = self.get_nodeattr("PE") + simd = self.get_nodeattr("SIMD") + wmem = (k_h * k_w * ch // pe) // simd + return wmem - def get_template_param_values(self): - """Returns the template parameter values according to input, output and weight - data types.""" - ret = dict() - inp_hls_str = self.get_input_datatype().get_hls_datatype_str() - out_hls_str = self.get_output_datatype().get_hls_datatype_str() - inp_is_binary = self.get_input_datatype() == DataType["BINARY"] - # out_is_binary = self.get_output_datatype() == DataType["BINARY"] - wt_is_binary = self.get_weight_datatype() == DataType["BINARY"] - bin_xnor_mode = self.get_nodeattr("binaryXnorMode") == 1 - if (inp_is_binary or wt_is_binary) and (not bin_xnor_mode): - raise Exception("True binary (non-bipolar) inputs not yet supported") - inp_is_bipolar = self.get_input_datatype() == DataType["BIPOLAR"] - # out_is_bipolar = self.get_output_datatype() == DataType["BIPOLAR"] - wt_is_bipolar = self.get_weight_datatype() == DataType["BIPOLAR"] - # reinterpret inp/wt as bipolar if bin_xnor_mode is iset - inp_is_bipolar = inp_is_bipolar or (inp_is_binary and bin_xnor_mode) - wt_is_bipolar = wt_is_bipolar or (wt_is_binary and bin_xnor_mode) - # fill in TSrcI and TWeightI - # TODO check these with Giulio - # TODO handle non-bipolar binary inputs - if inp_is_bipolar and wt_is_bipolar: - ret["TSrcI"] = "Recast" - ret["TWeightI"] = "Identity" - elif (not inp_is_bipolar) and wt_is_bipolar: - ret["TSrcI"] = "Slice<%s>" % inp_hls_str - ret["TWeightI"] = "Recast" - elif inp_is_bipolar and (not wt_is_bipolar): - ret["TSrcI"] = "Recast" - ret["TWeightI"] = "Identity" - elif (not inp_is_bipolar) and (not wt_is_bipolar): - ret["TSrcI"] = "Slice<%s>" % inp_hls_str - ret["TWeightI"] = "Identity" + def calc_tmem(self): + """Calculates and returns TMEM.""" + if self.get_nodeattr("noActivation") == 1: + return 0 + else: + ch = self.get_nodeattr("Channels") + pe = self.get_nodeattr("PE") + return ch // pe - # fill in TDstI - ret["TDstI"] = "Slice<%s>" % out_hls_str + def uram_estimation(self): + P = self.get_nodeattr("PE") + Q = self.get_nodeattr("SIMD") + wdt = self.get_weight_datatype() + W = wdt.bitwidth() + omega = self.calc_wmem() + mem_width = Q * W * P + mmode = self.get_nodeattr("mem_mode") + mstyle = self.get_nodeattr("ram_style") + if ( + (mmode == "decoupled" and mstyle != "ultra") + or (mmode == "const") + or (mmode == "external") + ): + return 0 + width_multiplier = math.ceil(mem_width / 72) + depth_multiplier = math.ceil(omega / 4096) + return width_multiplier * depth_multiplier - return ret + def bram_estimation(self): + """Calculates resource estimation for BRAM""" + # TODO add in/out FIFO contributions + P = self.get_nodeattr("PE") + Q = self.get_nodeattr("SIMD") + wdt = self.get_weight_datatype() + W = wdt.bitwidth() + omega = self.calc_wmem() + mem_width = Q * W * P + # assuming SDP mode RAMB18s (see UG573 Table 1-10) + # since this is HLS memory, not using the full width of a BRAM + # assuming memories up to 128 deep get implemented in LUTs + mmode = self.get_nodeattr("mem_mode") + mstyle = self.get_nodeattr("ram_style") + if ( + (mmode == "decoupled" and mstyle in ["distributed", "ultra"]) + or (mstyle == "auto" and self.calc_wmem() <= 128) + or (mmode == "const" and self.calc_wmem() <= 128) + or (mmode == "external") + ): + return 0 - def get_hls_compatible_weight_tensor(self, orig_weight_matrix): - pe = self.get_nodeattr("PE") - simd = self.get_nodeattr("SIMD") - ch = self.get_nodeattr("Channels") - k_h, k_w = self.get_nodeattr("Kernel") - wmem = self.calc_wmem() - assert orig_weight_matrix.shape == ( - ch, - 1, - k_h, - k_w, - ), """Weights matrix doesn't - have expected shape (channels, 1, kernel_size, kernel_size)""" - ret = orig_weight_matrix - if self.get_weight_datatype() == DataType["BIPOLAR"]: - # convert bipolar to binary - ret = (ret + 1) / 2 - ret = ret.reshape(ch, k_h * k_w) - # distribute rows between PEs - ret = interleave_matrix_outer_dim_from_partitions(ret, pe) - ret = ret.reshape(1, pe, wmem, simd) - return ret + if mem_width == 1: + return math.ceil(omega / 16384) + elif mem_width == 2: + return math.ceil(omega / 8192) + elif mem_width <= 4: + return (math.ceil(omega / 4096)) * (math.ceil(mem_width / 4)) + elif mem_width <= 9: + return (math.ceil(omega / 2048)) * (math.ceil(mem_width / 8)) + elif mem_width <= 18 or omega > 512: + return (math.ceil(omega / 1024)) * (math.ceil(mem_width / 16)) + else: + return (math.ceil(omega / 512)) * (math.ceil(mem_width / 32)) - def get_hls_compatible_threshold_tensor(self, orig_thres_matrix): - """Convert the original numpy weight matrix orig_weight_matrix into - a form suitable for passing to the hlslib call: - * ensure MH % PE == 0 - * for bipolar weights&inputs, ensure thresholds are positive - * interleave rows between PEs - * reshape into (PE, TMEM, n_thres_steps) and return + def bram_efficiency_estimation(self): + P = self.get_nodeattr("PE") + wdt = self.get_weight_datatype() + W = wdt.bitwidth() + omega = self.calc_wmem() + bram16_est = self.bram_estimation() + if bram16_est == 0: + return 1 + wbits = W * P * omega + bram16_est_capacity = bram16_est * 36 * 512 + return wbits / bram16_est_capacity + + def uram_efficiency_estimation(self): + """Function for URAM efficiency estimation: actual parameter storage + needed divided by the allocated URAM storage (from estimation)""" + wdt = self.get_weight_datatype() + W = wdt.bitwidth() + D_in = int(np.prod(self.get_nodeattr("Kernel"))) + D_out = self.get_nodeattr("Channels") + uram_est = self.uram_estimation() + if uram_est == 0: + return 1 + wbits = W * D_in * D_out + uram_est_capacity = uram_est * 72 * 4096 + return wbits / uram_est_capacity + + def lut_estimation(self): + """Calculates resource estimations for LUTs based on: + - FINN-R: An End-to-End Deep-Learning Framework for Fast + Exploration of Quantized Neural Networks + - M. Blott, T. B. Preusser, N. J. Fraser, G. Gambardella, K. O'Brien, + Y. Umuroglu, M. Leeser and K. Vissers + - 12. Sep 2018 + """ + # TODO add in/out FIFO contributions + P = self.get_nodeattr("PE") + Q = self.get_nodeattr("SIMD") + wdt = self.get_weight_datatype() + W = wdt.bitwidth() + # determine tdt with input and weight data types + idt = self.get_input_datatype() + A = idt.bitwidth() + # parameters from experiments in paper mentioned above + c0 = 300 + c1 = 1.1 + c2 = 0 + mmode = self.get_nodeattr("mem_mode") + mstyle = self.get_nodeattr("ram_style") + if (mmode == "decoupled" and mstyle == "distributed") or ( + mmode == "const" and self.calc_wmem() <= 128 + ): + c2 = (P * Q * W) * math.ceil(self.calc_wmem() / 64) + + # multiplication + res_type = self.get_nodeattr("resType") + if res_type == "dsp": + mult_luts = 0 + else: + mult_luts = Q * (2 * math.ceil((W + A) / 6) - 1) * (W + A) + # adder tree + addertree_luts = (W + A) * (2 * Q - 1) + # accumulator + acc_datatype = self.get_accumulator_datatype() + acc_bits = acc_datatype.bitwidth() + k_h, k_w = self.get_nodeattr("Kernel") + # if accDataType is not set, then it will default to INT32, which would + # be a large overestimate in most (if not all) cases. In this scenario, + # we would use the minimum accumulator as determined by the data types + # bound, derived in https://arxiv.org/abs/2301.13376 + alpha = math.log(k_h * k_w, 2) + W + A - 1 - int(idt.signed()) + acc_bits = min( + acc_datatype.bitwidth(), + np.ceil(alpha + math.log(1 + pow(2, -alpha), 2) + 1), + ) + acc_luts = acc_bits + # thresholds and threshold comparators + thr_luts = 0 + comp_luts = 0 + noact = self.get_nodeattr("noActivation") + # TODO - add 'ram_style_threshold' node attribute + if noact == 0: + odt = self.get_output_datatype() + B = odt.bitwidth() + thr_luts = (2**B - 1) * acc_bits * self.calc_tmem() / 64 + comp_luts = (2**B - 1) * acc_bits + + return int( + c0 + c1 * (P * (mult_luts + addertree_luts + acc_luts + thr_luts + comp_luts)) + c2 + ) + + def dsp_estimation(self): + # multiplication + P = self.get_nodeattr("PE") + res_type = self.get_nodeattr("resType") + wdt = self.get_weight_datatype() + W = wdt.bitwidth() + idt = self.get_input_datatype() + A = idt.bitwidth() + if res_type == "dsp": + mult_dsp = P * np.ceil((W + A) / 48) # TODO: more accurate modelling + else: + mult_dsp = 0 + return int(mult_dsp) + + def get_exp_cycles(self): + pe = self.get_nodeattr("PE") + simd = self.get_nodeattr("SIMD") + ch = self.get_nodeattr("Channels") + dim_h, dim_w = self.get_nodeattr("Dim") + k_h, k_w = self.get_nodeattr("Kernel") + # currently FINN supports for vvau a batch size of 1 + batch_size = 1 + # since mmv != 1 is not supported yet, we set mmv for now to 1 + mmv = 1 + exp_cycles = ((ch * k_h * k_w) / pe / simd) * batch_size * (dim_h * dim_w) / mmv + return int(exp_cycles) + + def minimize_accumulator_width(self, model): + """Minimize the accumulator bit width according to the weight values, + input data types, and size of dot product""" + weights = model.get_initializer(self.onnx_node.input[1]) + k_h, k_w = self.get_nodeattr("Kernel") + fm = self.get_nodeattr("Channels") + # put weights into the shape expected by calculate_matvec_accumulator_range + weights = weights.reshape(fm, k_h * k_w).transpose() + # since in the calculation the values of the weight matrix are used, + # for the bipolar case they need to be converted to bipolar + if self.get_nodeattr("binaryXnorMode"): + weights = 2 * weights - 1 + if len(self.onnx_node.input) > 2: + thresholds = model.get_initializer(self.onnx_node.input[2]) + else: + thresholds = None + idt = self.get_input_datatype() + + (acc_min, acc_max) = calculate_matvec_accumulator_range(weights, idt) + # if runtime-writeable weights, then the values of the weights can + # change and we need to use the worst-case values from the datatypes + if self.get_nodeattr("runtime_writeable_weights"): + wdt = self.get_weight_datatype() + lower_worst = wdt.min() * np.ones_like(weights) + lower_range = calculate_matvec_accumulator_range(lower_worst, idt) + upper_worst = wdt.max() * np.ones_like(weights) + upper_range = calculate_matvec_accumulator_range(upper_worst, idt) + acc_min = min(min(lower_range), min(upper_range)) + acc_max = max(max(upper_range), max(upper_range)) + + # if the thresholds can be used to determine range, then adjust the range + # according to the known values of the thresholds + if thresholds is not None: + threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds) + # set threshold datatype (and accumulator datatype implicitly) + min_threshold = thresholds.min() + max_threshold = thresholds.max() + # clip threshold values + if max_threshold > acc_max or min_threshold < acc_min: + warnings.warn("Clipping some thresholds in %s" % self.onnx_node.name) + thresholds = np.clip(thresholds, acc_min, acc_max) + model.set_initializer(self.onnx_node.input[2], thresholds) + threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds) + min_threshold = thresholds.min() + max_threshold = thresholds.max() + acc_min = min(min_threshold, acc_min) + acc_max = max(max_threshold, acc_max) + + # if the acc_range is always greater than 0, then acc_max <= 2^P - 1 + if acc_min >= 0: + acc_bit_width = np.log2(acc_max + 1) + acc_bit_width = math.ceil(acc_bit_width) + adt = DataType[f"UINT{acc_bit_width}"] + # if the acc_range is signed, then acc_min >= -2^{P-1} and acc_max <= + # 2^{P - 1} - 1, which means 2^{P - 1} >= max(-acc_min, 1 + acc_max) + else: + _acc_max = max(-acc_min, 1 + acc_max) + acc_bit_width = np.log2(_acc_max) + 1 + acc_bit_width = math.ceil(acc_bit_width) + adt = DataType[f"INT{acc_bit_width}"] + + # if activation, assert that the thresholds can be expressed with adt + if thresholds is not None: + assert np.vectorize(adt.allowed)( + threshold_tensor + ).all(), "Thresholds in %s can't be expressed with type %s" % ( + self.onnx_node.name, + str(adt), + ) + + # if no activation, output and accumulator datatypes are the same + if self.get_nodeattr("noActivation"): + # if this is the last node in the graph, then ensure the datatype is + # divisibly by 8 bits + if model.find_direct_successors(self.onnx_node) is None: + bw = roundup_to_integer_multiple(adt.bitwidth(), 8) + new_adt_name = adt.name.replace(str(adt.bitwidth()), str(bw)) + adt = DataType[new_adt_name] + # for no-activation nodes, output dt = acc dt + self.set_nodeattr("outputDataType", adt.name) + self.set_nodeattr("accDataType", adt.name) + + return DataType[self.get_nodeattr("accDataType")] + + def minimize_weight_bit_width(self, model): + """Minimize the bit width based on the values of the weights""" + if not self.get_nodeattr("runtime_writeable_weights"): + weights = model.get_initializer(self.onnx_node.input[1]) + w_min = weights.min() + w_max = weights.max() + if w_min < 0: + if abs(w_min) > w_max: + wdt = DataType.get_smallest_possible(w_min) + else: + wdt = DataType.get_smallest_possible(-w_max - 1) + else: + wdt = DataType.get_smallest_possible(w_max) + self.set_nodeattr("weightDataType", wdt.name) + return DataType[self.get_nodeattr("weightDataType")] + + def get_hls_compatible_threshold_tensor(self, orig_thres_matrix): + """Convert the original numpy weight matrix orig_weight_matrix into + a form suitable for passing to the hlslib call: + * ensure MH % PE == 0 + * for bipolar weights&inputs, ensure thresholds are positive + * interleave rows between PEs + * reshape into (PE, TMEM, n_thres_steps) and return """ ch = self.get_nodeattr("Channels") pe = self.get_nodeattr("PE") @@ -449,6 +619,29 @@ def get_hls_compatible_threshold_tensor(self, orig_thres_matrix): rows between PEs is not as expected (n_thres_steps)""" return ret.reshape(1, pe, tmem, n_thres_steps) + def get_hls_compatible_weight_tensor(self, orig_weight_matrix): + pe = self.get_nodeattr("PE") + simd = self.get_nodeattr("SIMD") + ch = self.get_nodeattr("Channels") + k_h, k_w = self.get_nodeattr("Kernel") + wmem = self.calc_wmem() + assert orig_weight_matrix.shape == ( + ch, + 1, + k_h, + k_w, + ), """Weights matrix doesn't + have expected shape (channels, 1, kernel_size, kernel_size)""" + ret = orig_weight_matrix + if self.get_weight_datatype() == DataType["BIPOLAR"]: + # convert bipolar to binary + ret = (ret + 1) / 2 + ret = ret.reshape(ch, k_h * k_w) + # distribute rows between PEs + ret = interleave_matrix_outer_dim_from_partitions(ret, pe) + ret = ret.reshape(1, pe, wmem, simd) + return ret + def make_weight_file(self, weights, weight_file_mode, weight_file_name): """Produce a file containing given weights in appropriate format for this layer. This file can be used for either synthesis or run-time reconfig @@ -626,384 +819,44 @@ def generate_params(self, model, path): f_thresh.write(thresholds_hls_code) f_thresh.close() - def execute_node(self, context, graph): - mode = self.get_nodeattr("exec_mode") - mem_mode = self.get_nodeattr("mem_mode") - node = self.onnx_node - - # TODO ensure codegen dir exists - if mode == "cppsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - elif mode == "rtlsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) - - # create a npy file fore each input of the node (in_ind is input index) - in_ind = 0 - for inputs in node.input: - # it is assumed that the first input of the node is the data input - # the second input are the weights - # the third input are the thresholds - if in_ind == 0: - assert ( - str(context[inputs].dtype) == "float32" - ), """Input datatype is - not float32 as expected.""" - expected_inp_shape = self.get_folded_input_shape() - reshaped_input = context[inputs].reshape(expected_inp_shape) - if self.get_input_datatype() == DataType["BIPOLAR"]: - # store bipolar activations as binary - reshaped_input = (reshaped_input + 1) / 2 - export_idt = DataType["BINARY"] - else: - export_idt = self.get_input_datatype() - # make copy before saving the array - reshaped_input = reshaped_input.copy() - np.save( - os.path.join(code_gen_dir, "input_{}.npy".format(in_ind)), - reshaped_input, - ) - elif in_ind > 2: - raise Exception("Unexpected input found for VectorVectorActivation") - in_ind += 1 - - if mode == "cppsim": - # execute the precompiled model - super().exec_precompiled_singlenode_model() - # load output npy file - super().npy_to_dynamic_output(context) - # reinterpret binary output as bipolar where needed - if self.get_output_datatype() == DataType["BIPOLAR"]: - out = context[node.output[0]] - out = 2 * out - 1 - context[node.output[0]] = out - assert ( - context[node.output[0]].shape == self.get_normal_output_shape() - ), "cppsim did not produce expected output shape" - elif mode == "rtlsim": - sim = self.get_rtlsim() - nbits = self.get_instream_width() - inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) - super().reset_rtlsim(sim) - super().toggle_clk(sim) - - if mem_mode == "external" or mem_mode == "decoupled": - wnbits = self.get_weightstream_width() - export_wdt = self.get_weight_datatype() - # we have converted bipolar weights to binary for export, - # so use it as such for weight generation - if self.get_weight_datatype() == DataType["BIPOLAR"]: - export_wdt = DataType["BINARY"] - wei = npy_to_rtlsim_input("{}/weights.npy".format(code_gen_dir), export_wdt, wnbits) - dim_h, dim_w = self.get_nodeattr("Dim") - num_w_reps = dim_h * dim_w - - io_dict = { - "inputs": {"in0": inp, "weights": wei * num_w_reps}, - "outputs": {"out": []}, - } - self.rtlsim_multi_io(sim, io_dict) - output = io_dict["outputs"]["out"] - else: - output = self.rtlsim(sim, inp) - odt = self.get_output_datatype() - target_bits = odt.bitwidth() - packed_bits = self.get_outstream_width() - out_npy_path = "{}/output.npy".format(code_gen_dir) - out_shape = self.get_folded_output_shape() - rtlsim_output_to_npy(output, out_npy_path, odt, out_shape, packed_bits, target_bits) - - # load and reshape output - output = np.load(out_npy_path) - oshape = self.get_normal_output_shape() - output = np.asarray([output], dtype=np.float32).reshape(*oshape) - context[node.output[0]] = output - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) - - def global_includes(self): - self.code_gen_dict["$GLOBALS$"] = ['#include "weights.hpp"'] - self.code_gen_dict["$GLOBALS$"] += ['#include "activations.hpp"'] - mem_mode = self.get_nodeattr("mem_mode") - if mem_mode not in ["const", "decoupled", "external"]: - raise Exception( - """Please set mem_mode to "const", "decoupled", or "external", - currently no other parameter value is supported!""" - ) - if self.calc_tmem() != 0: - self.code_gen_dict["$GLOBALS$"] += ['#include "thresh.h"'] - - def defines(self, var): - dim_h, dim_w = self.get_nodeattr("Dim") - numReps = 1 * dim_h * dim_w + def get_op_and_param_counts(self): k_h, k_w = self.get_nodeattr("Kernel") - innerProdDim = k_h * k_w - mem_mode = self.get_nodeattr("mem_mode") - - self.code_gen_dict["$DEFINES$"] = [ - """#define Channels1 {}\n #define InnerProdDim {}\n - #define SIMD1 {}\n #define PE1 {}\n #define numReps {}""".format( - self.get_nodeattr("Channels"), - innerProdDim, - self.get_nodeattr("SIMD"), - self.get_nodeattr("PE"), - numReps, - ) - ] - if mem_mode == "decoupled" or mem_mode == "external": - wdt = self.get_weight_datatype() - self.code_gen_dict["$DEFINES$"].append("#define WP1 {}\n".format(wdt.bitwidth())) - - def read_npy_data(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_input_datatype() - if dtype == DataType["BIPOLAR"]: - # use binary for bipolar storage - dtype = DataType["BINARY"] - elem_bits = dtype.bitwidth() - packed_bits = self.get_instream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_in = "%s/input_0.npy" % code_gen_dir - self.code_gen_dict["$READNPYDATA$"] = [] - # note: the innermost dim is reversed for the input - self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s, false);' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - npy_in, - self.hls_sname(), - ) - ) - - mem_mode = self.get_nodeattr("mem_mode") - if mem_mode == "decoupled" or mem_mode == "external": - wdt = self.get_weight_datatype() - elem_bits = wdt.bitwidth() - packed_bits = self.get_weightstream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = wdt.get_hls_datatype_str() - npy_type = "float" - npy_in = "%s/weights.npy" % code_gen_dir - - self.code_gen_dict["$READNPYDATA$"].append( - 'npy2apintstream<%s, %s, %d, %s>("%s", weights_%s, false, numReps);' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - npy_in, - self.hls_sname(), - ) - ) - - def strm_decl(self): - mem_mode = self.get_nodeattr("mem_mode") - self.code_gen_dict["$STREAMDECLARATIONS$"] = [] - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> in0_{} ("in0_{}");'.format( - self.get_instream_width(), self.hls_sname(), self.hls_sname() - ) - ) - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> out_{} ("out_{}");'.format( - self.get_outstream_width(), self.hls_sname(), self.hls_sname() - ) - ) - if mem_mode == "decoupled" or mem_mode == "external": - self.code_gen_dict["$STREAMDECLARATIONS$"].append( - 'hls::stream> weights_{} ("weights_{}");'.format( - self.get_weightstream_width(), self.hls_sname(), self.hls_sname() - ) - ) + fm = self.get_nodeattr("Channels") + dim_h, dim_w = self.get_nodeattr("Dim") + weight_bits = self.get_weight_datatype().bitwidth() + inp_bits = self.get_input_datatype().bitwidth() + num_repetitions = int(dim_h * dim_w) + mac_count = k_h * k_w * fm * num_repetitions + # cannonicalize op type: highest bitwidth operand first s.t. + # e.g. mac_8bx4b and mac_4bx8b don't appear as two different op types + bw1 = min(inp_bits, weight_bits) + bw2 = max(inp_bits, weight_bits) + mac_op_type = "op_mac_%dbx%db" % (bw1, bw2) + weight_param_type = "param_weight_%db" % (weight_bits) + weight_count = k_h * k_w * fm + ret_dict = {mac_op_type: mac_count, weight_param_type: weight_count} + if self.get_nodeattr("noActivation") == 0: + tdt = DataType[self.get_nodeattr("accDataType")] + thres_bits = tdt.bitwidth() + thres_param_type = "param_threshold_%db" % (thres_bits) + thres_count = fm + ret_dict[thres_param_type] = thres_count + return ret_dict - def docompute(self): - mem_mode = self.get_nodeattr("mem_mode") - map_to_hls_mult_style = { - "auto": "ap_resource_dflt()", - "lut": "ap_resource_lut()", - "dsp": "ap_resource_dsp()", + def derive_characteristic_fxns(self, period): + n_inps = np.prod(self.get_folded_input_shape()[:-1]) + io_dict = { + "inputs": { + "in0": [0 for i in range(n_inps)], + }, + "outputs": {"out": []}, } - tmpl_args = self.get_template_param_values() - if self.calc_tmem() == 0: - odtype_hls_str = self.get_output_datatype().get_hls_datatype_str() - threshs = "PassThroughActivation<%s>()" % odtype_hls_str - else: - threshs = "threshs" - - if mem_mode == "const": - self.code_gen_dict["$DOCOMPUTE$"] = [ - """Vector_Vector_Activate_Batch - (in0_{}, out_{}, weights, {}, numReps, {});""".format( - tmpl_args["TSrcI"], - tmpl_args["TDstI"], - tmpl_args["TWeightI"], - self.hls_sname(), - self.hls_sname(), - threshs, - map_to_hls_mult_style[self.get_nodeattr("resType")], - ) - ] - elif mem_mode == "decoupled" or mem_mode == "external": - wdt = self.get_weight_datatype() - if wdt == DataType["BIPOLAR"]: - export_wdt = DataType["BINARY"] - else: - export_wdt = wdt - wdtype_hls_str = export_wdt.get_hls_datatype_str() - self.code_gen_dict["$DOCOMPUTE$"] = [ - """{} - (in0_{}, out_{}, weights_{}, {}, numReps, {});""".format( - "Vector_Vector_Activate_Stream_Batch", - tmpl_args["TSrcI"], - tmpl_args["TDstI"], - tmpl_args["TWeightI"], - wdtype_hls_str, - self.hls_sname(), - self.hls_sname(), - self.hls_sname(), - threshs, - map_to_hls_mult_style[self.get_nodeattr("resType")], - ) - ] - else: - raise Exception( - """Please set mem_mode to "const", "decoupled", or "external", - currently no other parameter value is supported!""" - ) - - def dataoutstrm(self): - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - dtype = self.get_output_datatype() - if dtype == DataType["BIPOLAR"]: - # use binary for bipolar storage - dtype = DataType["BINARY"] - elem_bits = dtype.bitwidth() - packed_bits = self.get_outstream_width() - packed_hls_type = "ap_uint<%d>" % packed_bits - elem_hls_type = dtype.get_hls_datatype_str() - npy_type = "float" - npy_out = "%s/output.npy" % code_gen_dir - shape = self.get_folded_output_shape() - shape_cpp_str = str(shape).replace("(", "{").replace(")", "}") - - # note: the innermost dim is not reversed for the output - self.code_gen_dict["$DATAOUTSTREAM$"] = [ - 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s", false);' - % ( - packed_hls_type, - elem_hls_type, - elem_bits, - npy_type, - self.hls_sname(), - shape_cpp_str, - npy_out, - ) - ] - - def save_as_npy(self): - self.code_gen_dict["$SAVEASCNPY$"] = [] - - def blackboxfunction(self): - mem_mode = self.get_nodeattr("mem_mode") - if mem_mode == "const": - self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - """void {}(hls::stream> &in0_{}, - hls::stream> &out_{} - )""".format( - self.onnx_node.name, - self.get_instream_width(), - self.hls_sname(), - self.get_outstream_width(), - self.hls_sname(), - ) - ] - elif mem_mode == "decoupled" or mem_mode == "external": - self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ - """void {}( - hls::stream> &in0_{}, - hls::stream> &weights_{}, - hls::stream> &out_{} - )""".format( - self.onnx_node.name, - self.get_instream_width(), - self.hls_sname(), - self.get_weightstream_width(), - self.hls_sname(), - self.get_outstream_width(), - self.hls_sname(), - ) - ] - else: - raise Exception( - """Please set mem_mode to "const" or "decoupled", currently no other - parameter value is supported!""" - ) - - def pragmas(self): - mem_mode = self.get_nodeattr("mem_mode") - self.code_gen_dict["$PRAGMAS$"] = [ - "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() - ] - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() - ) - self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") - - if mem_mode == "const": - self.code_gen_dict["$PRAGMAS$"].append('#include "params.h"') - # the weight tensor is ap_uint [PE][WMEM] - # partition for parallel access along the PE dimension (dim 1) - self.code_gen_dict["$PRAGMAS$"].append( - ("#pragma HLS ARRAY_PARTITION variable=weights.m_weights " "complete dim=1") - ) - elif mem_mode == "decoupled" or mem_mode == "external": - self.code_gen_dict["$PRAGMAS$"].append( - "#pragma HLS INTERFACE axis port=weights_" + self.hls_sname() - ) - else: - raise Exception( - """Please set mem_mode to "const", "decoupled", or external, - currently no other parameter value is supported!""" - ) - - if self.calc_tmem() != 0: - # TODO find a better way of checking for no pregenerated thresholds - self.code_gen_dict["$PRAGMAS$"].append( - ("#pragma HLS ARRAY_PARTITION variable=threshs.m_thresholds " "complete dim=1") - ) - self.code_gen_dict["$PRAGMAS$"].append( - ("#pragma HLS ARRAY_PARTITION variable=threshs.m_thresholds " "complete dim=3") - ) - - def get_verilog_top_module_intf_names(self): - intf_names = super().get_verilog_top_module_intf_names() mem_mode = self.get_nodeattr("mem_mode") - sname = self.hls_sname() - if mem_mode == "external": - intf_names["s_axis"].append(("weights_" + sname, self.get_weightstream_width_padded())) - if mem_mode == "decoupled": - # only expose axilite interface if attribute is set - runtime_writable = self.get_nodeattr("runtime_writeable_weights") == 1 - if runtime_writable: - intf_names["axilite"] = ["s_axilite"] - return intf_names + if mem_mode in ["decoupled", "external"]: + n_weight_inps = self.calc_wmem() + num_w_reps = np.prod(self.get_nodeattr("numInputVectors")) + io_dict["inputs"]["weights"] = [0 for i in range(num_w_reps * n_weight_inps)] + super().derive_characteristic_fxns(period, override_rtlsim_dict=io_dict) def code_generation_ipi(self): cmd = [] @@ -1111,207 +964,4 @@ def code_generation_ipi(self): return super().code_generation_ipi() else: raise Exception("Unrecognized mem_mode for VectorVectorActivation") - return cmd - - def uram_estimation(self): - P = self.get_nodeattr("PE") - Q = self.get_nodeattr("SIMD") - wdt = self.get_weight_datatype() - W = wdt.bitwidth() - omega = self.calc_wmem() - mem_width = Q * W * P - mmode = self.get_nodeattr("mem_mode") - mstyle = self.get_nodeattr("ram_style") - if ( - (mmode == "decoupled" and mstyle != "ultra") - or (mmode == "const") - or (mmode == "external") - ): - return 0 - width_multiplier = math.ceil(mem_width / 72) - depth_multiplier = math.ceil(omega / 4096) - return width_multiplier * depth_multiplier - - def bram_estimation(self): - """Calculates resource estimation for BRAM""" - # TODO add in/out FIFO contributions - P = self.get_nodeattr("PE") - Q = self.get_nodeattr("SIMD") - wdt = self.get_weight_datatype() - W = wdt.bitwidth() - omega = self.calc_wmem() - mem_width = Q * W * P - # assuming SDP mode RAMB18s (see UG573 Table 1-10) - # since this is HLS memory, not using the full width of a BRAM - # assuming memories up to 128 deep get implemented in LUTs - mmode = self.get_nodeattr("mem_mode") - mstyle = self.get_nodeattr("ram_style") - if ( - (mmode == "decoupled" and mstyle in ["distributed", "ultra"]) - or (mstyle == "auto" and self.calc_wmem() <= 128) - or (mmode == "const" and self.calc_wmem() <= 128) - or (mmode == "external") - ): - return 0 - - if mem_width == 1: - return math.ceil(omega / 16384) - elif mem_width == 2: - return math.ceil(omega / 8192) - elif mem_width <= 4: - return (math.ceil(omega / 4096)) * (math.ceil(mem_width / 4)) - elif mem_width <= 9: - return (math.ceil(omega / 2048)) * (math.ceil(mem_width / 8)) - elif mem_width <= 18 or omega > 512: - return (math.ceil(omega / 1024)) * (math.ceil(mem_width / 16)) - else: - return (math.ceil(omega / 512)) * (math.ceil(mem_width / 32)) - - def bram_efficiency_estimation(self): - P = self.get_nodeattr("PE") - wdt = self.get_weight_datatype() - W = wdt.bitwidth() - omega = self.calc_wmem() - bram16_est = self.bram_estimation() - if bram16_est == 0: - return 1 - wbits = W * P * omega - bram16_est_capacity = bram16_est * 36 * 512 - return wbits / bram16_est_capacity - - def lut_estimation(self): - """Calculates resource estimations for LUTs based on: - - FINN-R: An End-to-End Deep-Learning Framework for Fast - Exploration of Quantized Neural Networks - - M. Blott, T. B. Preusser, N. J. Fraser, G. Gambardella, K. O'Brien, - Y. Umuroglu, M. Leeser and K. Vissers - - 12. Sep 2018 - """ - # TODO add in/out FIFO contributions - P = self.get_nodeattr("PE") - Q = self.get_nodeattr("SIMD") - wdt = self.get_weight_datatype() - W = wdt.bitwidth() - # determine tdt with input and weight data types - idt = self.get_input_datatype() - A = idt.bitwidth() - # parameters from experiments in paper mentioned above - c0 = 300 - c1 = 1.1 - c2 = 0 - mmode = self.get_nodeattr("mem_mode") - mstyle = self.get_nodeattr("ram_style") - if (mmode == "decoupled" and mstyle == "distributed") or ( - mmode == "const" and self.calc_wmem() <= 128 - ): - c2 = (P * Q * W) * math.ceil(self.calc_wmem() / 64) - - # multiplication - res_type = self.get_nodeattr("resType") - if res_type == "dsp": - mult_luts = 0 - else: - mult_luts = Q * (2 * math.ceil((W + A) / 6) - 1) * (W + A) - # adder tree - addertree_luts = (W + A) * (2 * Q - 1) - # accumulator - acc_datatype = self.get_accumulator_datatype() - acc_bits = acc_datatype.bitwidth() - k_h, k_w = self.get_nodeattr("Kernel") - # if accDataType is not set, then it will default to INT32, which would - # be a large overestimate in most (if not all) cases. In this scenario, - # we would use the minimum accumulator as determined by the data types - # bound, derived in https://arxiv.org/abs/2301.13376 - alpha = math.log(k_h * k_w, 2) + W + A - 1 - int(idt.signed()) - acc_bits = min( - acc_datatype.bitwidth(), - np.ceil(alpha + math.log(1 + pow(2, -alpha), 2) + 1), - ) - acc_luts = acc_bits - # thresholds and threshold comparators - thr_luts = 0 - comp_luts = 0 - noact = self.get_nodeattr("noActivation") - # TODO - add 'ram_style_threshold' node attribute - if noact == 0: - odt = self.get_output_datatype() - B = odt.bitwidth() - thr_luts = (2**B - 1) * acc_bits * self.calc_tmem() / 64 - comp_luts = (2**B - 1) * acc_bits - - return int( - c0 + c1 * (P * (mult_luts + addertree_luts + acc_luts + thr_luts + comp_luts)) + c2 - ) - - def dsp_estimation(self): - # multiplication - P = self.get_nodeattr("PE") - res_type = self.get_nodeattr("resType") - wdt = self.get_weight_datatype() - W = wdt.bitwidth() - idt = self.get_input_datatype() - A = idt.bitwidth() - if res_type == "dsp": - mult_dsp = P * np.ceil((W + A) / 48) # TODO: more accurate modelling - else: - mult_dsp = 0 - return int(mult_dsp) - - def get_weightstream_width(self): - """Returns weight stream width. Used only in decoupled mode.""" - if ( - self.get_nodeattr("mem_mode") == "decoupled" - or self.get_nodeattr("mem_mode") == "external" - ): - simd = self.get_nodeattr("SIMD") - pe = self.get_nodeattr("PE") - wp = self.get_weight_datatype().bitwidth() - w_width = simd * pe * wp - return w_width - else: - return 0 - - def get_weightstream_width_padded(self): - """Returns weight stream width padded to a multiple of 8. This is required - by the AXI Stream spec. Used in decoupled mode.""" - weight_width = self.get_weightstream_width() - return roundup_to_integer_multiple(weight_width, 8) - - def get_op_and_param_counts(self): - k_h, k_w = self.get_nodeattr("Kernel") - fm = self.get_nodeattr("Channels") - dim_h, dim_w = self.get_nodeattr("Dim") - weight_bits = self.get_weight_datatype().bitwidth() - inp_bits = self.get_input_datatype().bitwidth() - num_repetitions = int(dim_h * dim_w) - mac_count = k_h * k_w * fm * num_repetitions - # cannonicalize op type: highest bitwidth operand first s.t. - # e.g. mac_8bx4b and mac_4bx8b don't appear as two different op types - bw1 = min(inp_bits, weight_bits) - bw2 = max(inp_bits, weight_bits) - mac_op_type = "op_mac_%dbx%db" % (bw1, bw2) - weight_param_type = "param_weight_%db" % (weight_bits) - weight_count = k_h * k_w * fm - ret_dict = {mac_op_type: mac_count, weight_param_type: weight_count} - if self.get_nodeattr("noActivation") == 0: - tdt = DataType[self.get_nodeattr("accDataType")] - thres_bits = tdt.bitwidth() - thres_param_type = "param_threshold_%db" % (thres_bits) - thres_count = fm - ret_dict[thres_param_type] = thres_count - return ret_dict - - def derive_characteristic_fxns(self, period): - n_inps = np.prod(self.get_folded_input_shape()[:-1]) - io_dict = { - "inputs": { - "in0": [0 for i in range(n_inps)], - }, - "outputs": {"out": []}, - } - mem_mode = self.get_nodeattr("mem_mode") - if mem_mode in ["decoupled", "external"]: - n_weight_inps = self.calc_wmem() - num_w_reps = np.prod(self.get_nodeattr("numInputVectors")) - io_dict["inputs"]["weights"] = [0 for i in range(num_w_reps * n_weight_inps)] - super().derive_characteristic_fxns(period, override_rtlsim_dict=io_dict) + return cmd \ No newline at end of file From f7d0ad9355f3014af5d92a0750d8bec4b8b5c8fb Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Thu, 1 Feb 2024 14:36:31 +0000 Subject: [PATCH 459/665] [vvau hls-op]: refactored HLS custom-op VVAU --- .../hls/vectorvectoractivation_hls.py | 372 ++++++++++++++++++ 1 file changed, 372 insertions(+) create mode 100644 src/finn/custom_op/fpgadataflow/hls/vectorvectoractivation_hls.py diff --git a/src/finn/custom_op/fpgadataflow/hls/vectorvectoractivation_hls.py b/src/finn/custom_op/fpgadataflow/hls/vectorvectoractivation_hls.py new file mode 100644 index 0000000000..51de49f1c7 --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/hls/vectorvectoractivation_hls.py @@ -0,0 +1,372 @@ +# Copyright (c) 2020, Xilinx +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import math +import numpy as np +import os +import textwrap +import warnings +from qonnx.core.datatype import DataType +from qonnx.util.basic import ( + calculate_matvec_accumulator_range, + interleave_matrix_outer_dim_from_partitions, + roundup_to_integer_multiple, +) + +from finn.util.data_packing import ( + npy_to_rtlsim_input, + numpy_to_hls_code, + pack_innermost_dim_as_hex_string, + rtlsim_output_to_npy, +) +from finn.custom_op.fpgadataflow.vectorvectoractivation import VectorVectorActivation +from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend + +class VectorVectorActivation_hls(VectorVectorActivation, HLSBackend): + """Corresponds to finn-hlslib Vector_Vector_Activate_Batch function""" + + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) + + def get_nodeattr_types(self): + my_attrs = {} + my_attrs.update(VectorVectorActivation.get_nodeattr_types(self)) + my_attrs.update(HLSBackend.get_nodeattr_types(self)) + return my_attrs + + def get_template_param_values(self): + """Returns the template parameter values according to input, output and weight + data types.""" + ret = dict() + inp_hls_str = self.get_input_datatype().get_hls_datatype_str() + out_hls_str = self.get_output_datatype().get_hls_datatype_str() + inp_is_binary = self.get_input_datatype() == DataType["BINARY"] + # out_is_binary = self.get_output_datatype() == DataType["BINARY"] + wt_is_binary = self.get_weight_datatype() == DataType["BINARY"] + bin_xnor_mode = self.get_nodeattr("binaryXnorMode") == 1 + if (inp_is_binary or wt_is_binary) and (not bin_xnor_mode): + raise Exception("True binary (non-bipolar) inputs not yet supported") + inp_is_bipolar = self.get_input_datatype() == DataType["BIPOLAR"] + # out_is_bipolar = self.get_output_datatype() == DataType["BIPOLAR"] + wt_is_bipolar = self.get_weight_datatype() == DataType["BIPOLAR"] + # reinterpret inp/wt as bipolar if bin_xnor_mode is iset + inp_is_bipolar = inp_is_bipolar or (inp_is_binary and bin_xnor_mode) + wt_is_bipolar = wt_is_bipolar or (wt_is_binary and bin_xnor_mode) + # fill in TSrcI and TWeightI + # TODO check these with Giulio + # TODO handle non-bipolar binary inputs + if inp_is_bipolar and wt_is_bipolar: + ret["TSrcI"] = "Recast" + ret["TWeightI"] = "Identity" + elif (not inp_is_bipolar) and wt_is_bipolar: + ret["TSrcI"] = "Slice<%s>" % inp_hls_str + ret["TWeightI"] = "Recast" + elif inp_is_bipolar and (not wt_is_bipolar): + ret["TSrcI"] = "Recast" + ret["TWeightI"] = "Identity" + elif (not inp_is_bipolar) and (not wt_is_bipolar): + ret["TSrcI"] = "Slice<%s>" % inp_hls_str + ret["TWeightI"] = "Identity" + + # fill in TDstI + ret["TDstI"] = "Slice<%s>" % out_hls_str + + return ret + + def global_includes(self): + self.code_gen_dict["$GLOBALS$"] = ['#include "weights.hpp"'] + self.code_gen_dict["$GLOBALS$"] += ['#include "activations.hpp"'] + mem_mode = self.get_nodeattr("mem_mode") + if mem_mode not in ["const", "decoupled", "external"]: + raise Exception( + """Please set mem_mode to "const", "decoupled", or "external", + currently no other parameter value is supported!""" + ) + if self.calc_tmem() != 0: + self.code_gen_dict["$GLOBALS$"] += ['#include "thresh.h"'] + + def defines(self, var): + dim_h, dim_w = self.get_nodeattr("Dim") + numReps = 1 * dim_h * dim_w + k_h, k_w = self.get_nodeattr("Kernel") + innerProdDim = k_h * k_w + mem_mode = self.get_nodeattr("mem_mode") + + self.code_gen_dict["$DEFINES$"] = [ + """#define Channels1 {}\n #define InnerProdDim {}\n + #define SIMD1 {}\n #define PE1 {}\n #define numReps {}""".format( + self.get_nodeattr("Channels"), + innerProdDim, + self.get_nodeattr("SIMD"), + self.get_nodeattr("PE"), + numReps, + ) + ] + if mem_mode == "decoupled" or mem_mode == "external": + wdt = self.get_weight_datatype() + self.code_gen_dict["$DEFINES$"].append("#define WP1 {}\n".format(wdt.bitwidth())) + + def read_npy_data(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_input_datatype() + if dtype == DataType["BIPOLAR"]: + # use binary for bipolar storage + dtype = DataType["BINARY"] + elem_bits = dtype.bitwidth() + packed_bits = self.get_instream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "float" + npy_in = "%s/input_0.npy" % code_gen_dir + self.code_gen_dict["$READNPYDATA$"] = [] + # note: the innermost dim is reversed for the input + self.code_gen_dict["$READNPYDATA$"].append( + 'npy2apintstream<%s, %s, %d, %s>("%s", in0_%s, false);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) + ) + + mem_mode = self.get_nodeattr("mem_mode") + if mem_mode == "decoupled" or mem_mode == "external": + wdt = self.get_weight_datatype() + elem_bits = wdt.bitwidth() + packed_bits = self.get_weightstream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = wdt.get_hls_datatype_str() + npy_type = "float" + npy_in = "%s/weights.npy" % code_gen_dir + + self.code_gen_dict["$READNPYDATA$"].append( + 'npy2apintstream<%s, %s, %d, %s>("%s", weights_%s, false, numReps);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + npy_in, + self.hls_sname(), + ) + ) + + def strm_decl(self): + mem_mode = self.get_nodeattr("mem_mode") + self.code_gen_dict["$STREAMDECLARATIONS$"] = [] + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> in0_{} ("in0_{}");'.format( + self.get_instream_width(), self.hls_sname(), self.hls_sname() + ) + ) + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> out_{} ("out_{}");'.format( + self.get_outstream_width(), self.hls_sname(), self.hls_sname() + ) + ) + if mem_mode == "decoupled" or mem_mode == "external": + self.code_gen_dict["$STREAMDECLARATIONS$"].append( + 'hls::stream> weights_{} ("weights_{}");'.format( + self.get_weightstream_width(), self.hls_sname(), self.hls_sname() + ) + ) + + def docompute(self): + mem_mode = self.get_nodeattr("mem_mode") + map_to_hls_mult_style = { + "auto": "ap_resource_dflt()", + "lut": "ap_resource_lut()", + "dsp": "ap_resource_dsp()", + } + tmpl_args = self.get_template_param_values() + if self.calc_tmem() == 0: + odtype_hls_str = self.get_output_datatype().get_hls_datatype_str() + threshs = "PassThroughActivation<%s>()" % odtype_hls_str + else: + threshs = "threshs" + + if mem_mode == "const": + self.code_gen_dict["$DOCOMPUTE$"] = [ + """Vector_Vector_Activate_Batch + (in0_{}, out_{}, weights, {}, numReps, {});""".format( + tmpl_args["TSrcI"], + tmpl_args["TDstI"], + tmpl_args["TWeightI"], + self.hls_sname(), + self.hls_sname(), + threshs, + map_to_hls_mult_style[self.get_nodeattr("resType")], + ) + ] + elif mem_mode == "decoupled" or mem_mode == "external": + wdt = self.get_weight_datatype() + if wdt == DataType["BIPOLAR"]: + export_wdt = DataType["BINARY"] + else: + export_wdt = wdt + wdtype_hls_str = export_wdt.get_hls_datatype_str() + self.code_gen_dict["$DOCOMPUTE$"] = [ + """{} + (in0_{}, out_{}, weights_{}, {}, numReps, {});""".format( + "Vector_Vector_Activate_Stream_Batch", + tmpl_args["TSrcI"], + tmpl_args["TDstI"], + tmpl_args["TWeightI"], + wdtype_hls_str, + self.hls_sname(), + self.hls_sname(), + self.hls_sname(), + threshs, + map_to_hls_mult_style[self.get_nodeattr("resType")], + ) + ] + else: + raise Exception( + """Please set mem_mode to "const", "decoupled", or "external", + currently no other parameter value is supported!""" + ) + + def dataoutstrm(self): + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + dtype = self.get_output_datatype() + if dtype == DataType["BIPOLAR"]: + # use binary for bipolar storage + dtype = DataType["BINARY"] + elem_bits = dtype.bitwidth() + packed_bits = self.get_outstream_width() + packed_hls_type = "ap_uint<%d>" % packed_bits + elem_hls_type = dtype.get_hls_datatype_str() + npy_type = "float" + npy_out = "%s/output.npy" % code_gen_dir + shape = self.get_folded_output_shape() + shape_cpp_str = str(shape).replace("(", "{").replace(")", "}") + + # note: the innermost dim is not reversed for the output + self.code_gen_dict["$DATAOUTSTREAM$"] = [ + 'apintstream2npy<%s, %s, %d, %s>(out_%s, %s, "%s", false);' + % ( + packed_hls_type, + elem_hls_type, + elem_bits, + npy_type, + self.hls_sname(), + shape_cpp_str, + npy_out, + ) + ] + + def save_as_npy(self): + self.code_gen_dict["$SAVEASCNPY$"] = [] + + def blackboxfunction(self): + mem_mode = self.get_nodeattr("mem_mode") + if mem_mode == "const": + self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ + """void {}(hls::stream> &in0_{}, + hls::stream> &out_{} + )""".format( + self.onnx_node.name, + self.get_instream_width(), + self.hls_sname(), + self.get_outstream_width(), + self.hls_sname(), + ) + ] + elif mem_mode == "decoupled" or mem_mode == "external": + self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ + """void {}( + hls::stream> &in0_{}, + hls::stream> &weights_{}, + hls::stream> &out_{} + )""".format( + self.onnx_node.name, + self.get_instream_width(), + self.hls_sname(), + self.get_weightstream_width(), + self.hls_sname(), + self.get_outstream_width(), + self.hls_sname(), + ) + ] + else: + raise Exception( + """Please set mem_mode to "const" or "decoupled", currently no other + parameter value is supported!""" + ) + + def pragmas(self): + mem_mode = self.get_nodeattr("mem_mode") + self.code_gen_dict["$PRAGMAS$"] = [ + "#pragma HLS INTERFACE axis port=in0_" + self.hls_sname() + ] + self.code_gen_dict["$PRAGMAS$"].append( + "#pragma HLS INTERFACE axis port=out_" + self.hls_sname() + ) + self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") + + if mem_mode == "const": + self.code_gen_dict["$PRAGMAS$"].append('#include "params.h"') + # the weight tensor is ap_uint [PE][WMEM] + # partition for parallel access along the PE dimension (dim 1) + self.code_gen_dict["$PRAGMAS$"].append( + ("#pragma HLS ARRAY_PARTITION variable=weights.m_weights " "complete dim=1") + ) + elif mem_mode == "decoupled" or mem_mode == "external": + self.code_gen_dict["$PRAGMAS$"].append( + "#pragma HLS INTERFACE axis port=weights_" + self.hls_sname() + ) + else: + raise Exception( + """Please set mem_mode to "const", "decoupled", or external, + currently no other parameter value is supported!""" + ) + + if self.calc_tmem() != 0: + # TODO find a better way of checking for no pregenerated thresholds + self.code_gen_dict["$PRAGMAS$"].append( + ("#pragma HLS ARRAY_PARTITION variable=threshs.m_thresholds " "complete dim=1") + ) + self.code_gen_dict["$PRAGMAS$"].append( + ("#pragma HLS ARRAY_PARTITION variable=threshs.m_thresholds " "complete dim=3") + ) + + def get_verilog_top_module_intf_names(self): + intf_names = super().get_verilog_top_module_intf_names() + mem_mode = self.get_nodeattr("mem_mode") + sname = self.hls_sname() + if mem_mode == "external": + intf_names["s_axis"].append(("weights_" + sname, self.get_weightstream_width_padded())) + if mem_mode == "decoupled": + # only expose axilite interface if attribute is set + runtime_writable = self.get_nodeattr("runtime_writeable_weights") == 1 + if runtime_writable: + intf_names["axilite"] = ["s_axilite"] + return intf_names \ No newline at end of file From f9b8fbcdf614bf060a2ce7a6faf45502b9cef9ba Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Thu, 1 Feb 2024 14:37:12 +0000 Subject: [PATCH 460/665] [convert-to-hw]: added transformations to infer binary-MVAU and VVAU --- .../fpgadataflow/convert_to_hw_layers.py | 279 ++++++++++++++++++ 1 file changed, 279 insertions(+) diff --git a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py index eb6dd337f5..26cd0b74ad 100644 --- a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py +++ b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py @@ -1281,6 +1281,139 @@ def apply(self, model): return (model, graph_modified) +class InferBinaryMatrixVectorActivation(Transformation): + """Convert XnorPopcountMatMul layers to + MatrixVectorActivation layers. Any immediately following MultiThreshold + layers will also be absorbed into the MVTU.""" + + def __init__(self, mem_mode="const"): + super().__init__() + self.mem_mode = mem_mode + + def apply(self, model): + graph = model.graph + node_ind = 0 + graph_modified = False + for n in graph.node: + node_ind += 1 + if n.op_type == "XnorPopcountMatMul": + mm_input = n.input[0] + mm_weight = n.input[1] + mm_output = n.output[0] + mm_in_shape = model.get_tensor_shape(mm_input) + mm_out_shape = model.get_tensor_shape(mm_output) + assert model.get_tensor_datatype(mm_input) == DataType["BINARY"], ( + n.name + + """: First + input for xnorpopcount is not Wset to FINN DataType BINARY.""" + ) + assert model.get_tensor_datatype(mm_weight) == DataType["BINARY"], ( + n.name + + """: Second + input (weights) for xnorpopcount is not set to FINN DataType BINARY.""" + ) + idt = DataType["BINARY"] + wdt = DataType["BINARY"] + mm_output = n.output[0] + W = model.get_initializer(mm_weight) + # extract weight shape, note that ONNX and finn-hlslib + # make different assumptions about dim order here + # ONNX assumes W has (in, out) shape + # finn-hlslib assumes W has (out, in) shape + mh = int(W.shape[1]) + mw = int(W.shape[0]) + # create node with no parallelization first + pe = 1 + simd = 1 + wmem = mw * mh // (pe * simd) + assert mw * mh == wmem * pe * simd, ( + n.name + + """: Requirement (MW * MH) divisiable by + (WMEM * PE * SIMD) is violated.""" + ) + # see if we have any following thresholds + consumer = model.find_consumer(mm_output) + if consumer is not None and consumer.op_type == "MultiThreshold": + # TODO ensure integer thresholds? + # create MVTU (i.e. including activation) + mt_output = consumer.output[0] + mt_out_shape = model.get_tensor_shape(mt_output) + mt_thres = consumer.input[1] + T = model.get_initializer(mt_thres) + assert T.shape[0] == 1 or T.shape[0] == mh, ( + consumer.name + + """: First dimension of + thresholds neither 1 nor MH.""" + ) + odt = model.get_tensor_datatype(mt_output) + if odt.bitwidth() == 1: + # covers both bipolar and binary + actval = 0 + else: + actval = odt.min() + model.set_tensor_shape(mm_input, mm_in_shape) + model.set_tensor_shape(mt_output, mt_out_shape) + # create and insert new MatrixVectorActivation node + new_node = helper.make_node( + "MatrixVectorActivation", + [mm_input, mm_weight, mt_thres], + [mt_output], + domain="finn.custom_op.fpgadataflow", + backend="fpgadataflow", + MW=mw, + MH=mh, + SIMD=simd, + PE=pe, + inputDataType=idt.name, + weightDataType=wdt.name, + outputDataType=odt.name, + ActVal=actval, + binaryXnorMode=1, + noActivation=0, + numInputVectors=list(mm_in_shape[:-1]), + mem_mode=self.mem_mode, + name=n.name, + ) + graph.node.insert(node_ind, new_node) + # remove old nodes + graph.node.remove(n) + graph.node.remove(consumer) + graph_modified = True + else: + # no activation, matmul only + odt = model.get_tensor_datatype(mm_output) + model.set_tensor_shape(mm_input, mm_in_shape) + model.set_tensor_shape(mm_output, mm_out_shape) + # create and insert new MatrixVectorActivation node + new_node = helper.make_node( + "MatrixVectorActivation", + [mm_input, mm_weight], + [mm_output], + domain="finn.custom_op.fpgadataflow", + backend="fpgadataflow", + MW=mw, + MH=mh, + SIMD=simd, + PE=pe, + inputDataType=idt.name, + weightDataType=wdt.name, + outputDataType=odt.name, + ActVal=0, + binaryXnorMode=1, + noActivation=1, + numInputVectors=list(mm_in_shape[:-1]), + mem_mode=self.mem_mode, + name=n.name, + ) + graph.node.insert(node_ind, new_node) + # remove old node + graph.node.remove(n) + graph_modified = True + if graph_modified: + model = model.transform(InferShapes()) + model = model.transform(InferDataTypes()) + return (model, graph_modified) + class InferQuantizedMatrixVectorActivation(Transformation): """Convert MatMul layers with quantized inputs and weights to MatrixVectorActivation layers.""" @@ -1415,4 +1548,150 @@ def apply(self, model): if graph_modified: model = model.transform(InferShapes()) model = model.transform(InferDataTypes()) + return (model, graph_modified) + +class InferVectorVectorActivation(Transformation): + """Convert MatMul layers with quantized inputs and weights to + VectorVectorActivation layers, if the sparsity annotation + of the weight matrix indicates that the MatMul layer belongs to + a depthwise convolution. Any immediately following MultiThreshold + layers will also be absorbed into the VVAU.""" + + def __init__(self, mem_mode="const"): + super().__init__() + self.mem_mode = mem_mode + + def apply(self, model): + graph = model.graph + node_ind = 0 + graph_modified = False + for n in graph.node: + node_ind += 1 + if n.op_type == "MatMul" and model.get_tensor_sparsity(n.input[1]) is not None: + sparsity = model.get_tensor_sparsity(n.input[1]) + try: + k_h, k_w = sparsity["dw"]["kernel_shape"] + except KeyError: + raise Exception( + n.name + + """: sparsity annotation doesn't indicate that MatMul + belongs to a depthwise convolution.""" + ) + + mm_input = n.input[0] + mm_weight = n.input[1] + mm_output = n.output[0] + mm_in_shape = model.get_tensor_shape(mm_input) + mm_out_shape = model.get_tensor_shape(mm_output) + idt = model.get_tensor_datatype(mm_input) + wdt = model.get_tensor_datatype(mm_weight) + if idt.is_integer() and wdt.is_integer(): + mm_output = n.output[0] + W = model.get_initializer(mm_weight) + # infer dense weight tensor from sparse weight matrix + # kernel size (k_h, k_w) which was extracted above and the value of + # the channels is used. + # the weight matrix has a shape of (k_h * k_w * Channels, Channels) + # we need to reverse the creation of the sparse weight matrix + # to achieve a weight tensor of shape (Channels, 1, k_h, k_w) + channels = int(W.shape[1]) + # transpose to achieve a shape of (k_h * k_w * Channels, Channels) + W = W.T + # reshape to (Channels, k_h, k_w, Channels) to transpose afterwards + # to (Channels, Channels, k_h, k_w) + W = W.reshape(channels, k_h, k_w, channels) + W = W.transpose(0, 3, 1, 2) + # now we can extract the values using a for loop over the channels + # and fill a zero numpy array in the correct shape + w_tensor = np.zeros((channels, 1, k_h, k_w), dtype=np.float32) + for ch in range(channels): + w_tensor[ch][0] = W[ch][ch] + model.set_initializer(mm_weight, w_tensor) + model.set_tensor_shape(mm_weight, (channels, 1, k_h, k_w)) + # create node with pe=channels as default + pe = channels + # see if we have any following thresholds + consumer = model.find_consumer(mm_output) + if consumer is not None and consumer.op_type == "MultiThreshold": + # create VVAU (i.e. including activation) + mt_output = consumer.output[0] + mt_out_shape = model.get_tensor_shape(mt_output) + mt_thres = consumer.input[1] + T = model.get_initializer(mt_thres) + assert T.shape[0] == 1 or T.shape[0] == channels, ( + consumer.name + + """: First dimension of + thresholds neither 1 nor Channels.""" + ) + odt = model.get_tensor_datatype(mt_output) + scale = getCustomOp(consumer).get_nodeattr("out_scale") + assert scale == 1.0, ( + consumer.name + ": out_scale must be equal to 1.0 for HLS conversion." + ) + actval = getCustomOp(consumer).get_nodeattr("out_bias") + assert int(actval) == actval, ( + consumer.name + ": out_bias must be integer for HLS conversion." + ) + actval = int(actval) + assert (not odt.signed()) or (actval < 0), ( + consumer.name + ": Signed output requres actval < 0" + ) + model.set_tensor_shape(mm_input, mm_in_shape) + model.set_tensor_shape(mt_output, mt_out_shape) + # create and insert new VectorVectorActivation node + new_node = helper.make_node( + "VectorVectorActivation", + [mm_input, mm_weight, mt_thres], + [mt_output], + domain="finn.custom_op.fpgadataflow", + backend="fpgadataflow", + resType="lut", + PE=pe, + Dim=[mm_in_shape[1], mm_in_shape[2]], + Channels=channels, + Kernel=[k_h, k_w], + inputDataType=idt.name, + weightDataType=wdt.name, + outputDataType=odt.name, + ActVal=actval, + noActivation=0, + name="VectorVectorActivation_" + n.name, + mem_mode=self.mem_mode, + ) + graph.node.insert(node_ind, new_node) + # remove old nodes + graph.node.remove(n) + graph.node.remove(consumer) + graph_modified = True + else: + # no activation, matmul only + odt = model.get_tensor_datatype(mm_output) + model.set_tensor_shape(mm_input, mm_in_shape) + model.set_tensor_shape(mm_output, mm_out_shape) + # create and insert new VVAU node + new_node = helper.make_node( + "VectorVectorActivation", + [mm_input, mm_weight], + [mm_output], + domain="finn.custom_op.fpgadataflow", + backend="fpgadataflow", + resType="lut", + PE=pe, + Dim=[mm_in_shape[1], mm_in_shape[2]], + Channels=channels, + Kernel=[k_h, k_w], + inputDataType=idt.name, + weightDataType=wdt.name, + outputDataType=odt.name, + ActVal=0, + noActivation=1, + name="VectorVectorActivation_" + n.name, + ) + graph.node.insert(node_ind, new_node) + # remove old node + graph.node.remove(n) + graph_modified = True + if graph_modified: + model = model.transform(InferShapes()) + model = model.transform(InferDataTypes()) return (model, graph_modified) \ No newline at end of file From 8be157c07df653392210eafe9f8fdc9e2a08215e Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Thu, 1 Feb 2024 15:42:14 +0000 Subject: [PATCH 461/665] [mvau/vvau hw-op]: remove duplicate node attribute --- src/finn/custom_op/fpgadataflow/matrixvectoractivation.py | 1 - src/finn/custom_op/fpgadataflow/vectorvectoractivation.py | 4 ---- 2 files changed, 5 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index 7cf6c2b2cd..e5455e1850 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -133,7 +133,6 @@ def get_nodeattr_types(self): # vector through the accelerator. This will get rid of any old # weight data from the weight FIFOs. "runtime_writeable_weights": ("i", False, 0, {0, 1}), - "preferred_impl_style" : ("s", False, "hls", {"hls", "rtl"}), } my_attrs.update(super().get_nodeattr_types()) return my_attrs diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index 2168474298..af659dd936 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -104,10 +104,6 @@ def get_nodeattr_types(self): # use xnor-popcount for binary weights/inputs, thus treating them # as bipolar "binaryXnorMode": ("i", False, 0, {0, 1}), - # Backend implementation for layer - # hls -- Vivado HLS - # rtl -- (System)Verilog - "preferred_impl_style": ("s", False, "hls", {"hls", "rtl"}), } my_attrs.update(super().get_nodeattr_types()) return my_attrs From 445cfa6b4c45b89b35504e2975e34f159e73c5fd Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 2 Feb 2024 11:21:10 +0000 Subject: [PATCH 462/665] [hw vvau]: rename specific method to more generic name --- src/finn/custom_op/fpgadataflow/vectorvectoractivation.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index af659dd936..e6a9e1e199 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -615,7 +615,7 @@ def get_hls_compatible_threshold_tensor(self, orig_thres_matrix): rows between PEs is not as expected (n_thres_steps)""" return ret.reshape(1, pe, tmem, n_thres_steps) - def get_hls_compatible_weight_tensor(self, orig_weight_matrix): + def get_hw_compatible_weight_tensor(self, orig_weight_matrix): pe = self.get_nodeattr("PE") simd = self.get_nodeattr("SIMD") ch = self.get_nodeattr("Channels") @@ -652,7 +652,7 @@ def make_weight_file(self, weights, weight_file_mode, weight_file_name): """ # convert weights into hlslib-compatible format - weight_tensor = self.get_hls_compatible_weight_tensor(weights) + weight_tensor = self.get_hw_compatible_weight_tensor(weights) export_wdt = self.get_weight_datatype() # we have converted bipolar weights to binary for export, # so use it as such for weight generation From e33104e662de62430411668122a3de36538ac7e2 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 2 Feb 2024 12:28:21 +0000 Subject: [PATCH 463/665] [hw vvau]: minor bugfix to node execution --- .../fpgadataflow/vectorvectoractivation.py | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index e6a9e1e199..65431a18dd 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -127,17 +127,20 @@ def execute_node(self, context, graph): (_, dim_h, dim_w, _) = in_act.shape (k_h, k_w) = self.get_nodeattr("Kernel") channels = self.get_nodeattr("Channels") - # Reshape input activations in right format - in_act = in_act.reshape(1, dim_h, dim_w, channels, k_h*k_w) - in_act = in_act.transpose(0, 1, 2, 4, 3) + pe = self.get_nodeattr("PE") + # Reorder the input activations. Note that PE gets interleaved by the SWG, + # so we have to untangle and for simplicity of computation assume pe=1. + # Note that PE has no effect on the QONNX node + in_act = in_act.reshape(1, dim_h, dim_w, channels // pe, k_h*k_w, pe) + in_act = in_act.transpose(0, 1, 2, 4, 3, 5) in_act = in_act.reshape(1, dim_h, dim_w, channels*k_h*k_w) - # Reshape + # Reshape weights in appropriate format vvau_w_init = [x for x in graph.initializer if x.name == node.input[1]][0] vvau_w = np_helper.to_array(vvau_w_init) vvau_w_onnx = self._infer_sparse_weight_tensor(vvau_w, k_h, k_w, channels) if self.get_nodeattr("inputDataType") == "BIPOLAR" and self.get_nodeattr("weightDataType") == "BIPOLAR": - result = np.matmul(in_act, vvau_w_onnx) + result = np.matmul(in_act, vvau_w_onnx) # result is in [N, H, W, C] format result = (result + k_h*k_w) / 2 else: result = np.matmul(in_act, vvau_w_onnx) # result is in [N, H, W, C] format @@ -145,7 +148,7 @@ def execute_node(self, context, graph): if self.get_nodeattr("noActivation") == 0: vvau_thr_init = [x for x in graph.initializer if x.name == node.input[2]][0] vvau_thr = np_helper.to_array(vvau_thr_init) - odt_is_bipolar = self.get_nodeattr("outputDataType") == DataType["BIPOLAR"] + odt_is_bipolar = self.get_nodeattr("outputDataType") == "BIPOLAR" out_scale = 2 if odt_is_bipolar else 1 out_bias = -1 if odt_is_bipolar else self.get_nodeattr("ActVal") # NHWC to NCHW for multithreshold node @@ -154,7 +157,6 @@ def execute_node(self, context, graph): # NCHW to NHWC result = result.transpose((0,2,3,1)) - # for i in range(self.get_nodeattr("Channels")): context[node.output[0]] = result def verify_node(self): From 6884030b68519327fbf447b6914bae99c1576a6e Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 2 Feb 2024 12:28:59 +0000 Subject: [PATCH 464/665] [test]: extend vvau test to simulate HW custom-op as well --- tests/fpgadataflow/test_fpgadataflow_vvau.py | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_vvau.py b/tests/fpgadataflow/test_fpgadataflow_vvau.py index 4208169c0b..447ba5148f 100644 --- a/tests/fpgadataflow/test_fpgadataflow_vvau.py +++ b/tests/fpgadataflow/test_fpgadataflow_vvau.py @@ -47,6 +47,7 @@ from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers def _infer_sparse_weight_tensor(W_conv, k_h, k_w, channels): @@ -233,6 +234,10 @@ def test_fpgadataflow_vvau( W, pe, simd, k_h, k_w, channels, dim_h, dim_w, wdt, idt, odt, T, tdt, mem_mode ) + input_dict = prepare_inputs(x_vvau) + y_hwop = oxe.execute_onnx(model, input_dict)["outp"] + model = model.transform(SpecializeLayers()) + if exec_mode == "cppsim": model = model.transform(SetExecMode("cppsim")) model = model.transform(PrepareCppSim()) @@ -246,8 +251,6 @@ def test_fpgadataflow_vvau( else: raise Exception("Unknown exec_mode in test_fpgadataflow_vvau") - input_dict = prepare_inputs(x_vvau) - # Calculate output if wdt == DataType["BIPOLAR"] and idt == DataType["BIPOLAR"]: # Simulate XNOR-popcount matrix multiplication, see @@ -271,7 +274,8 @@ def test_fpgadataflow_vvau( y_produced = oxe.execute_onnx(model, input_dict, return_full_exec_context=False)["outp"] - assert (y_produced == y_expected).all(), "incorrect result" + assert (y_hwop == y_expected).all(), "VVAU HW-op mismatches with golden output!" + assert (y_produced == y_expected).all(), "VVAU specialized-op mismatches with golden output!" if exec_mode == "rtlsim": node = model.get_nodes_by_op_type("VectorVectorActivation")[0] From 8aaec4b400623d2d63e193a66030fda892ea7b2b Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 2 Feb 2024 12:33:21 +0000 Subject: [PATCH 465/665] [hw mvau]: minor bugfix to node execution and cleaned up code --- .../fpgadataflow/matrixvectoractivation.py | 437 ++++++------------ 1 file changed, 151 insertions(+), 286 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index e5455e1850..63d8e586a1 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -140,25 +140,89 @@ def get_nodeattr_types(self): def base_op_type(self): return "MatrixVectorActivation" - def calc_wmem(self): - """Calculates and returns WMEM.""" - mw = self.get_nodeattr("MW") - mh = self.get_nodeattr("MH") - pe = self.get_nodeattr("PE") - simd = self.get_nodeattr("SIMD") - assert mh % pe == 0, "Requirement MH divisable by PE is violated." - assert mw % simd == 0, "Requirement MW divisable by SIMD is violated." - wmem = mw * mh // (pe * simd) - return wmem + def execute_node(self, context, graph): + node = self.onnx_node + in_act = context[node.input[0]] + mvau_w_init = [x for x in graph.initializer if x.name == node.input[1]][0] + mvau_w = np_helper.to_array(mvau_w_init) + # Matrix multiplication + if self.get_nodeattr("binaryXnorMode"): + # Note: activation/weights are expected to be binary (by design coming from the transformation inferring this operation mode) + result = xp.xnorpopcountmatmul(in_act, mvau_w) + elif (self.get_nodeattr("inputDataType") == "BIPOLAR" and self.get_nodeattr("weightDataType") == "BIPOLAR"): + # Convert to binary and use xnorpopcountmatmul function + result = xp.xnorpopcountmatmul((in_act+1)/2, (mvau_w+1)/2) + else: + # Regular matrix multiplication + result = np.matmul(in_act, mvau_w) + if self.get_nodeattr("noActivation") == 0: + mvau_thr_init = [x for x in graph.initializer if x.name == node.input[2]][0] + mvau_thr = np_helper.to_array(mvau_thr_init) + odt_is_bipolar = self.get_nodeattr("outputDataType") == DataType["BIPOLAR"] + out_scale = 2 if odt_is_bipolar else 1 + out_bias = -1 if odt_is_bipolar else self.get_nodeattr("ActVal") + # NHWC to NCHW for multithreshold node + result = result.transpose((0,3,1,2)) + result = multithreshold(result, mvau_thr, out_scale, out_bias) + # NCHW to NHWC + result = result.transpose((0,2,3,1)) + + context[node.output[0]] = result - def calc_tmem(self): - """Calculates and returns TMEM.""" - if self.get_nodeattr("noActivation") == 1: - return 0 + def verify_node(self): + info_messages = [] + # verify that "backend" is set to "fpgadataflow" + backend_value = self.get_nodeattr("backend") + if backend_value == "fpgadataflow": + info_messages.append("Attribute backend is set correctly") else: - mh = self.get_nodeattr("MH") - pe = self.get_nodeattr("PE") - return mh // pe + info_messages.append('Attribute backend should be set to "fpgadataflow"') + + # verify that all necessary attributes exist + # TODO collect automatically from get_nodeattr_types + try: + self.get_nodeattr("code_gen_dir_cppsim") + self.get_nodeattr("executable_path") + self.get_nodeattr("resType") + self.get_nodeattr("MW") + self.get_nodeattr("MH") + self.get_nodeattr("SIMD") + self.get_nodeattr("PE") + self.get_nodeattr("inputDataType") + self.get_nodeattr("weightDataType") + self.get_nodeattr("outputDataType") + info_messages.append("All necessary attributes exist") + except Exception: + info_messages.append("""The required MatrixVectorActivation attributes do not exist.""") + + # verify the number of inputs depending on noActivation value + # check noActivation value to determine the number of inputs + no_act = self.get_nodeattr("noActivation") + + if no_act == 1: + if len(self.onnx_node.input) == 2: + info_messages.append("The number of inputs is correct") + else: + info_messages.append( + """MatrixVectorActivation needs in no + activation mode 2 inputs (data input and weights)""" + ) + elif no_act == 0: + if len(self.onnx_node.input) == 3: + info_messages.append("The number of inputs is correct") + else: + info_messages.append( + """MatrixVectorActivation needs 3 inputs + (data input and weights and threshold values)""" + ) + else: + info_messages.append( + """noActivation attribute contains {} should + be 0 or 1""".format( + no_act + ) + ) + return info_messages def make_shape_compatible_op(self, model): oshape = self.get_normal_output_shape() @@ -194,9 +258,13 @@ def get_weight_datatype(self): """Returns FINN DataType of weights.""" return DataType[self.get_nodeattr("weightDataType")] + def get_accumulator_datatype(self): + """Returns FINN DataType of accumulator""" + return DataType[self.get_nodeattr("accDataType")] + def get_output_datatype(self, ind=0): """Returns FINN DataType of output.""" - return DataType[self.get_nodeattr("outputDataType")] + return DataType[self.get_nodeattr("outputDataType")] def get_instream_width(self, ind=0): i_bits = self.get_input_datatype().bitwidth() @@ -234,61 +302,69 @@ def get_weightstream_width_padded(self): weight_width = self.get_weightstream_width() return roundup_to_integer_multiple(weight_width, 8) - def verify_node(self): - info_messages = [] - # verify that "backend" is set to "fpgadataflow" - backend_value = self.get_nodeattr("backend") - if backend_value == "fpgadataflow": - info_messages.append("Attribute backend is set correctly") + def get_folded_input_shape(self, ind=0): + mw = self.get_nodeattr("MW") + mh = self.get_nodeattr("MH") + simd = self.get_nodeattr("SIMD") + pe = self.get_nodeattr("PE") + sf = mw // simd + nf = mh // pe + vecs = list(self.get_nodeattr("numInputVectors")) + + if ind == 0: + # calculate shape of input 0 + folded_input_shape = tuple(vecs + [sf, simd]) + elif ind == 1 and self.get_nodeattr("mem_mode") == "external": + # calculate shape of input 1 (weights) + folded_input_shape = tuple(vecs + [sf * nf, simd * pe]) else: - info_messages.append('Attribute backend should be set to "fpgadataflow"') + raise Exception("Undefined input shape for requested input") - # verify that all necessary attributes exist - # TODO collect automatically from get_nodeattr_types - try: - self.get_nodeattr("code_gen_dir_cppsim") - self.get_nodeattr("executable_path") - self.get_nodeattr("resType") - self.get_nodeattr("MW") - self.get_nodeattr("MH") - self.get_nodeattr("SIMD") - self.get_nodeattr("PE") - self.get_nodeattr("inputDataType") - self.get_nodeattr("weightDataType") - self.get_nodeattr("outputDataType") - info_messages.append("All necessary attributes exist") - except Exception: - info_messages.append("""The required MatrixVectorActivation attributes do not exist.""") + return folded_input_shape - # verify the number of inputs depending on noActivation value - # check noActivation value to determine the number of inputs - no_act = self.get_nodeattr("noActivation") + def get_folded_output_shape(self, ind=0): + mh = self.get_nodeattr("MH") + pe = self.get_nodeattr("PE") + nf = mh // pe + vecs = list(self.get_nodeattr("numInputVectors")) + folded_output_shape = tuple(vecs + [nf, pe]) + return folded_output_shape - if no_act == 1: - if len(self.onnx_node.input) == 2: - info_messages.append("The number of inputs is correct") - else: - info_messages.append( - """MatrixVectorActivation needs in no - activation mode 2 inputs (data input and weights)""" - ) - elif no_act == 0: - if len(self.onnx_node.input) == 3: - info_messages.append("The number of inputs is correct") - else: - info_messages.append( - """MatrixVectorActivation needs 3 inputs - (data input and weights and threshold values)""" - ) - else: - info_messages.append( - """noActivation attribute contains {} should - be 0 or 1""".format( - no_act - ) - ) + def get_normal_input_shape(self, ind=0): + mw = self.get_nodeattr("MW") + vecs = list(self.get_nodeattr("numInputVectors")) + normal_input_shape = tuple(vecs + [mw]) + return normal_input_shape - return info_messages + def get_normal_output_shape(self, ind=0): + mh = self.get_nodeattr("MH") + vecs = list(self.get_nodeattr("numInputVectors")) + normal_output_shape = tuple(vecs + [mh]) + return normal_output_shape + + def get_number_output_values(self): + nf = np.prod(self.get_folded_output_shape()[:-1]) + return nf + + def calc_wmem(self): + """Calculates and returns WMEM.""" + mw = self.get_nodeattr("MW") + mh = self.get_nodeattr("MH") + pe = self.get_nodeattr("PE") + simd = self.get_nodeattr("SIMD") + assert mh % pe == 0, "Requirement MH divisable by PE is violated." + assert mw % simd == 0, "Requirement MW divisable by SIMD is violated." + wmem = mw * mh // (pe * simd) + return wmem + + def calc_tmem(self): + """Calculates and returns TMEM.""" + if self.get_nodeattr("noActivation") == 1: + return 0 + else: + mh = self.get_nodeattr("MH") + pe = self.get_nodeattr("PE") + return mh // pe def uram_estimation(self): P = self.get_nodeattr("PE") @@ -454,25 +530,6 @@ def dsp_estimation(self): else: mult_dsp = 0 return int(mult_dsp) -# # TODO: fix DSP estimations --> depends on fpga_part -# def dsp_estimation(self): -# # multiplication -# # mvu_8sx9 (DSP58): ceil(SIMD/3) -# # mvu_4sx4u (DSP48/DSP58): ceil(PE/4) -# # mvu_8sx8u (DSP48): ceil(PE/2) -# # mvu_lut: 0 -# P = self.get_nodeattr("PE") -# res_type = self.get_nodeattr("resType") -# Q = self.get_nodeattr("SIMD") -# wdt = self.get_weight_datatype() -# W = wdt.bitwidth() -# idt = self.get_input_datatype() -# A = idt.bitwidth() -# if res_type == "dsp": -# mult_dsp = P * Q * np.ceil((W + A) / 48) # TODO: more accurate modelling -# else: -# mult_dsp = 0 -# return int(mult_dsp) def get_exp_cycles(self): pe = self.get_nodeattr("PE") @@ -485,124 +542,6 @@ def get_exp_cycles(self): exp_cycles = (mh / pe) * (mw / simd) * np.prod(num_inp_vec) / mmv return int(exp_cycles) -# # TODO: fix exp_cycles estimations --> depends on fpga_part and clk -# def get_exp_cycles(self): -# # mvu_8sx9 (DSP58): -# # 2 (replay_buffer) + ceil(chainlen/seglen) + 2 (MREG, PREG) + 2 (output reg slice) -# # + MW/SIMD * MH/PE -# # mvu_4sx4u (DSP48/DSP58) / mvu_8sx8u (DSP48): -# # 3 (IN_REG, MREG, PREG) + 2 (replay_buffer) + 2 (output reg slice) + 1 (adder tree SIMD) + 1 (output lane) -# # + MW/SIMD * MH/PE -# # mvu_lut: -# # 2 (replay_buffer) + 1 OR 2 (no MREG OR MREG) + 2 (output reg slice) -# # + MW/SIMD * MH/PE -# pe = self.get_nodeattr("PE") -# simd = self.get_nodeattr("SIMD") -# num_inp_vec = self.get_nodeattr("numInputVectors") -# mh = self.get_nodeattr("MH") -# mw = self.get_nodeattr("MW") -# # since mmv != 1 is not supported yet, we set mmv for now to 1 -# mmv = 1 -# exp_cycles = (mh / pe) * (mw / simd) * np.prod(num_inp_vec) / mmv -# return int(exp_cycles) - - def get_input_datatype(self, ind=0): - """Returns FINN DataType of input.""" - # when performing FIFO insertion on an FC layer with ext weights, the ind - # parameter can be > 0 (referring to the weights) so handle that here - if ind == 0: - return DataType[self.get_nodeattr("inputDataType")] - elif ind == 1: - return DataType[self.get_nodeattr("weightDataType")] - else: - raise Exception("Undefined input ind for this layer type") - - def get_accumulator_datatype(self): - """Returns FINN DataType of accumulator""" - return DataType[self.get_nodeattr("accDataType")] - - def get_weight_datatype(self): - """Returns FINN DataType of weights.""" - return DataType[self.get_nodeattr("weightDataType")] - - def get_output_datatype(self, ind=0): - """Returns FINN DataType of output.""" - return DataType[self.get_nodeattr("outputDataType")] - - def get_instream_width(self, ind=0): - i_bits = self.get_input_datatype().bitwidth() - in_width = i_bits * self.get_nodeattr("SIMD") - return in_width - - def get_outstream_width(self, ind=0): - o_bits = self.get_output_datatype().bitwidth() - out_width = o_bits * self.get_nodeattr("PE") - return out_width - - def get_weightstream_width(self): - """Returns weight stream width. Used only in decoupled mode.""" - if ( - self.get_nodeattr("mem_mode") == "decoupled" - or self.get_nodeattr("mem_mode") == "external" - ): - pe = self.get_nodeattr("PE") - simd = self.get_nodeattr("SIMD") - wp = self.get_weight_datatype().bitwidth() - w_width = pe * simd * wp - return w_width - else: - return 0 - - def get_weightstream_width_padded(self): - """Returns weight stream width padded to a multiple of 8. This is required - by the AXI Stream spec. Used in decoupled mode.""" - weight_width = self.get_weightstream_width() - return roundup_to_integer_multiple(weight_width, 8) - - def get_folded_input_shape(self, ind=0): - mw = self.get_nodeattr("MW") - mh = self.get_nodeattr("MH") - simd = self.get_nodeattr("SIMD") - pe = self.get_nodeattr("PE") - sf = mw // simd - nf = mh // pe - vecs = list(self.get_nodeattr("numInputVectors")) - - if ind == 0: - # calculate shape of input 0 - folded_input_shape = tuple(vecs + [sf, simd]) - elif ind == 1 and self.get_nodeattr("mem_mode") == "external": - # calculate shape of input 1 (weights) - folded_input_shape = tuple(vecs + [sf * nf, simd * pe]) - else: - raise Exception("Undefined input shape for requested input") - - return folded_input_shape - - def get_folded_output_shape(self, ind=0): - mh = self.get_nodeattr("MH") - pe = self.get_nodeattr("PE") - nf = mh // pe - vecs = list(self.get_nodeattr("numInputVectors")) - folded_output_shape = tuple(vecs + [nf, pe]) - return folded_output_shape - - def get_normal_input_shape(self, ind=0): - mw = self.get_nodeattr("MW") - vecs = list(self.get_nodeattr("numInputVectors")) - normal_input_shape = tuple(vecs + [mw]) - return normal_input_shape - - def get_normal_output_shape(self, ind=0): - mh = self.get_nodeattr("MH") - vecs = list(self.get_nodeattr("numInputVectors")) - normal_output_shape = tuple(vecs + [mh]) - return normal_output_shape - - def get_number_output_values(self): - nf = np.prod(self.get_folded_output_shape()[:-1]) - return nf - def minimize_accumulator_width(self, model): """Minimize the accumulator bit width according to the weight values, input data types, and size of dot product""" @@ -1003,30 +942,6 @@ def derive_characteristic_fxns(self, period): io_dict["inputs"]["weights"] = [0 for i in range(num_w_reps * n_weight_inps)] super().derive_characteristic_fxns(period, override_rtlsim_dict=io_dict) - def execute_node(self, context, graph): - node = self.onnx_node - in_act = context[node.input[0]] - mvau_w_init = [x for x in graph.initializer if x.name == node.input[1]][0] - mvau_w = np_helper.to_array(mvau_w_init) - # Matrix multiplication - if self.get_nodeattr("binaryXnorMode"): - # Note: activation/weights are expected to be binary (by design coming from the transformation inferring this operation mode) - result = xp.xnorpopcountmatmul(in_act, mvau_w) - elif (self.get_nodeattr("inputDataType") == "BIPOLAR" and self.get_nodeattr("weightDataType") == "BIPOLAR"): - result = xp.xnorpopcountmatmul((in_act+1)/2, (mvau_w+1)/2) - else: - result = np.matmul(in_act, mvau_w) - # Thresholding if noActivation==0 - if self.get_nodeattr("noActivation") == 0: - mvau_thr_init = [x for x in graph.initializer if x.name == node.input[2]][0] - mvau_thr = np_helper.to_array(mvau_thr_init) - odt_is_bipolar = self.get_nodeattr("outputDataType") == DataType["BIPOLAR"] - out_scale = 2 if odt_is_bipolar else 1 - out_bias = -1 if odt_is_bipolar else self.get_nodeattr("ActVal") - result = multithreshold(result, mvau_thr, out_scale, out_bias) - - context[node.output[0]] = result - def code_generation_ipi(self): cmd = [] # add streamer if needed @@ -1056,37 +971,11 @@ def code_generation_ipi(self): "create_bd_intf_pin -mode Slave " "-vlnv xilinx.com:interface:axis_rtl:1.0 /%s/%s" % (node_name, din_name) ) - is_rtl_op = self.__class__.__name__ == "MatrixVectorActivation_rtl" - if is_rtl_op: - # instantiate the RTL block - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - rtllib_dir = os.path.join(os.environ["FINN_ROOT"], "finn-rtllib/mvu/") - sourcefiles = [ - os.path.join( - code_gen_dir, self.get_nodeattr("gen_top_module") + "_wrapper.v" - ), - rtllib_dir + "mvu_vvu_axi.sv", - rtllib_dir + "replay_buffer.sv", - rtllib_dir + "mvu_4sx4u.sv", - rtllib_dir + "mvu_vvu_8sx9_dsp58.sv", - rtllib_dir + "mvu_8sx8u_dsp48.sv", - ] - for f in sourcefiles: - cmd.append("add_files -norecurse %s" % (f)) - cmd.append( - "create_bd_cell -type hier -reference %s /%s/%s" - % ( - self.get_nodeattr("gen_top_module"), - self.onnx_node.name, - self.onnx_node.name, - ) - ) - else: - # instantiate the hls ip - cmd.append( - "create_bd_cell -type ip -vlnv %s /%s/%s" - % (self.get_nodeattr("ip_vlnv"), node_name, node_name) - ) + # instantiate the hls ip + cmd.append( + "create_bd_cell -type ip -vlnv %s /%s/%s" + % (self.get_nodeattr("ip_vlnv"), node_name, node_name) + ) # instantiate a streamer and connect it to the HLS IP strm_vlnv = "amd.com:finn:memstream:1.0" @@ -1159,32 +1048,8 @@ def code_generation_ipi(self): cmd.append("assign_bd_address") cmd.append("save_bd_design") elif mem_mode == "const" or mem_mode == "external": - if is_rtl_op and mem_mode == "external": - # instantiate the RTL block - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - rtllib_dir = os.path.join(os.environ["FINN_ROOT"], "finn-rtllib/mvu/") - sourcefiles = [ - os.path.join( - code_gen_dir, self.get_nodeattr("gen_top_module") + "_wrapper.v" - ), - rtllib_dir + "mvu_vvu_axi.sv", - rtllib_dir + "replay_buffer.sv", - rtllib_dir + "mvu_4sx4u.sv", - rtllib_dir + "mvu_vvu_8sx9_dsp58.sv", - rtllib_dir + "mvu_8sx8u_dsp48.sv", - ] - for f in sourcefiles: - cmd.append("add_files -norecurse %s" % (f)) - cmd.append( - "create_bd_cell -type module -reference %s %s" - % ( - self.get_nodeattr("gen_top_module"), - self.onnx_node.name, - ) - ) - else: - # base class impl sufficient for const/external modes - return super().code_generation_ipi() + # base class impl sufficient for const/external modes + return super().code_generation_ipi() else: raise Exception("Unrecognized mem_mode for MatrixVectorActivation") return cmd \ No newline at end of file From 07f977eaebdfcb65ff18440d3b76ddad03a3aec2 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 2 Feb 2024 12:42:41 +0000 Subject: [PATCH 466/665] [test]: cleaned up mvau test --- tests/fpgadataflow/test_fpgadataflow_mvau.py | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_mvau.py b/tests/fpgadataflow/test_fpgadataflow_mvau.py index bd283855e3..e862900e2b 100644 --- a/tests/fpgadataflow/test_fpgadataflow_mvau.py +++ b/tests/fpgadataflow/test_fpgadataflow_mvau.py @@ -238,9 +238,7 @@ def test_fpgadataflow_fclayer_hwop(idt, wdt, act, nf, sf, mw, mh): @pytest.mark.fpgadataflow @pytest.mark.slow @pytest.mark.vivado -def test_fpgadataflow_fclayer_hlsop_cppsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): - if idt == DataType["BIPOLAR"] and wdt != DataType["BIPOLAR"] or idt != DataType["BIPOLAR"] and wdt == DataType["BIPOLAR"]: - pytest.skip("Bipolar activations/weights only supported in MVU if both operands are bipolar") +def test_fpgadataflow_fclayer_cppsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): if nf == -1: nf = mh if sf == -1: @@ -281,6 +279,7 @@ def test_fpgadataflow_fclayer_hlsop_cppsim(mem_mode, idt, wdt, act, nf, sf, mw, # lookup op_type in registry of CustomOps inst = getCustomOp(node) inst.set_nodeattr("mem_mode", mem_mode) + # Note: only HLS-based MVAU layers execute CPPsim inst.set_nodeattr("preferred_impl_style", "hls") model = model.transform(SpecializeLayers()) model = model.transform(SetExecMode("cppsim")) @@ -327,14 +326,10 @@ def test_fpgadataflow_fclayer_hlsop_cppsim(mem_mode, idt, wdt, act, nf, sf, mw, @pytest.mark.parametrize("mw", [16]) # HLS matrix height (output features) @pytest.mark.parametrize("mh", [16]) -# Backend -@pytest.mark.parametrize("backend", ["rtl", "hls"]) @pytest.mark.fpgadataflow @pytest.mark.slow @pytest.mark.vivado -def test_fpgadataflow_fclayer_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh, backend): - if backend == "rtl" and act is not None: - pytest.skip("RTL MVU doesn't support embedded thresholding functionality.") +def test_fpgadataflow_fclayer_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): if nf == -1: nf = mh if sf == -1: @@ -375,7 +370,6 @@ def test_fpgadataflow_fclayer_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh, ba # lookup op_type in registry of CustomOps inst = getCustomOp(node) inst.set_nodeattr("mem_mode", mem_mode) - inst.set_nodeattr("preferred_impl_style", backend) # prepare input data input_dict = prepare_inputs(x, idt, wdt) @@ -397,7 +391,8 @@ def test_fpgadataflow_fclayer_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh, ba # TODO split up into several dependent tests -- need to check how this # works for parametrized tests... model = model.transform(SpecializeLayers()) - model = model.transform(SetExecMode("rtlsim")) + # model = model.transform(SetExecMode("rtlsim")) + model.set_metadata_prop("exec_mode", "rtlsim") model = model.transform(GiveUniqueNodeNames()) model = model.transform(PrepareIP("xc7z020clg400-1", 5)) model = model.transform(HLSSynthIP()) @@ -406,8 +401,11 @@ def test_fpgadataflow_fclayer_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh, ba assert (y_produced.reshape(y_expected.shape) == y_expected).all(), "rtlsim failed" hls_synt_res_est = model.analysis(hls_synth_res_estimation) - if backend == "hls": assert "MatrixVectorActivation_hls_0" in hls_synt_res_est + assert "MatrixVectorActivation_hls_0" in hls_synt_res_est + else: + assert "MatrixVectorActivation_rtl_0" in hls_synt_res_est + assert "MatrixVectorActivation_hls_0" in hls_synt_res_est else: assert "MatrixVectorActivation_rtl_0" in hls_synt_res_est From 3466e882d14b7c2a2e0848268aac031c61b78436 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 2 Feb 2024 12:43:09 +0000 Subject: [PATCH 467/665] [hw mvau]: minor bugfix --- src/finn/custom_op/fpgadataflow/matrixvectoractivation.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index 63d8e586a1..8f8292e994 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -158,7 +158,7 @@ def execute_node(self, context, graph): if self.get_nodeattr("noActivation") == 0: mvau_thr_init = [x for x in graph.initializer if x.name == node.input[2]][0] mvau_thr = np_helper.to_array(mvau_thr_init) - odt_is_bipolar = self.get_nodeattr("outputDataType") == DataType["BIPOLAR"] + odt_is_bipolar = self.get_nodeattr("outputDataType") == "BIPOLAR" out_scale = 2 if odt_is_bipolar else 1 out_bias = -1 if odt_is_bipolar else self.get_nodeattr("ActVal") # NHWC to NCHW for multithreshold node From 496869fc8fbd34ff343aa417a1d27f4997744985 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 2 Feb 2024 14:13:39 +0000 Subject: [PATCH 468/665] updated copyright header --- .../custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py | 2 +- .../custom_op/fpgadataflow/hls/vectorvectoractivation_hls.py | 2 +- src/finn/custom_op/fpgadataflow/matrixvectoractivation.py | 2 +- src/finn/custom_op/fpgadataflow/vectorvectoractivation.py | 2 +- tests/fpgadataflow/test_fpgadataflow_mvau.py | 2 +- tests/fpgadataflow/test_fpgadataflow_vvau.py | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py b/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py index 2ad9fefc07..e27e77fe4f 100644 --- a/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py @@ -1,4 +1,4 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/src/finn/custom_op/fpgadataflow/hls/vectorvectoractivation_hls.py b/src/finn/custom_op/fpgadataflow/hls/vectorvectoractivation_hls.py index 51de49f1c7..615ff7c71e 100644 --- a/src/finn/custom_op/fpgadataflow/hls/vectorvectoractivation_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/vectorvectoractivation_hls.py @@ -1,4 +1,4 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index 8f8292e994..04594f4109 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -1,4 +1,4 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index 65431a18dd..e793321879 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -1,4 +1,4 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/tests/fpgadataflow/test_fpgadataflow_mvau.py b/tests/fpgadataflow/test_fpgadataflow_mvau.py index e862900e2b..38f77e3836 100644 --- a/tests/fpgadataflow/test_fpgadataflow_mvau.py +++ b/tests/fpgadataflow/test_fpgadataflow_mvau.py @@ -1,4 +1,4 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/tests/fpgadataflow/test_fpgadataflow_vvau.py b/tests/fpgadataflow/test_fpgadataflow_vvau.py index 447ba5148f..1cb64dda91 100644 --- a/tests/fpgadataflow/test_fpgadataflow_vvau.py +++ b/tests/fpgadataflow/test_fpgadataflow_vvau.py @@ -1,4 +1,4 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without From 2910acaf0c22d31d6de28388c400653561635ab6 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 2 Feb 2024 15:08:06 +0000 Subject: [PATCH 469/665] [hls vvau]: add execute_node function --- .../hls/vectorvectoractivation_hls.py | 106 ++++++++++++++++++ 1 file changed, 106 insertions(+) diff --git a/src/finn/custom_op/fpgadataflow/hls/vectorvectoractivation_hls.py b/src/finn/custom_op/fpgadataflow/hls/vectorvectoractivation_hls.py index 615ff7c71e..c824f9682c 100644 --- a/src/finn/custom_op/fpgadataflow/hls/vectorvectoractivation_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/vectorvectoractivation_hls.py @@ -59,6 +59,112 @@ def get_nodeattr_types(self): my_attrs.update(HLSBackend.get_nodeattr_types(self)) return my_attrs + def execute_node(self, context, graph): + mode = self.get_nodeattr("exec_mode") + mem_mode = self.get_nodeattr("mem_mode") + node = self.onnx_node + + # TODO ensure codegen dir exists + if mode == "cppsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") + elif mode == "rtlsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + + # create a npy file fore each input of the node (in_ind is input index) + in_ind = 0 + for inputs in node.input: + # it is assumed that the first input of the node is the data input + # the second input are the weights + # the third input are the thresholds + if in_ind == 0: + assert ( + str(context[inputs].dtype) == "float32" + ), """Input datatype is + not float32 as expected.""" + expected_inp_shape = self.get_folded_input_shape() + reshaped_input = context[inputs].reshape(expected_inp_shape) + if self.get_input_datatype() == DataType["BIPOLAR"]: + # store bipolar activations as binary + reshaped_input = (reshaped_input + 1) / 2 + export_idt = DataType["BINARY"] + else: + export_idt = self.get_input_datatype() + # make copy before saving the array + reshaped_input = reshaped_input.copy() + np.save( + os.path.join(code_gen_dir, "input_{}.npy".format(in_ind)), + reshaped_input, + ) + elif in_ind > 2: + raise Exception("Unexpected input found for VectorVectorActivation") + in_ind += 1 + + if mode == "cppsim": + # execute the precompiled model + super().exec_precompiled_singlenode_model() + # load output npy file + super().npy_to_dynamic_output(context) + # reinterpret binary output as bipolar where needed + if self.get_output_datatype() == DataType["BIPOLAR"]: + out = context[node.output[0]] + out = 2 * out - 1 + context[node.output[0]] = out + assert ( + context[node.output[0]].shape == self.get_normal_output_shape() + ), "cppsim did not produce expected output shape" + elif mode == "rtlsim": + sim = self.get_rtlsim() + nbits = self.get_instream_width() + inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) + super().reset_rtlsim(sim) + super().toggle_clk(sim) + + if mem_mode == "external" or mem_mode == "decoupled": + wnbits = self.get_weightstream_width() + export_wdt = self.get_weight_datatype() + # we have converted bipolar weights to binary for export, + # so use it as such for weight generation + if self.get_weight_datatype() == DataType["BIPOLAR"]: + export_wdt = DataType["BINARY"] + wei = npy_to_rtlsim_input("{}/weights.npy".format(code_gen_dir), export_wdt, wnbits) + dim_h, dim_w = self.get_nodeattr("Dim") + num_w_reps = dim_h * dim_w + + io_dict = { + "inputs": {"in0": inp, "weights": wei * num_w_reps}, + "outputs": {"out": []}, + } + self.rtlsim_multi_io(sim, io_dict) + output = io_dict["outputs"]["out"] + else: + output = self.rtlsim(sim, inp) + odt = self.get_output_datatype() + target_bits = odt.bitwidth() + packed_bits = self.get_outstream_width() + out_npy_path = "{}/output.npy".format(code_gen_dir) + out_shape = self.get_folded_output_shape() + rtlsim_output_to_npy(output, out_npy_path, odt, out_shape, packed_bits, target_bits) + + # load and reshape output + output = np.load(out_npy_path) + oshape = self.get_normal_output_shape() + output = np.asarray([output], dtype=np.float32).reshape(*oshape) + context[node.output[0]] = output + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + def get_template_param_values(self): """Returns the template parameter values according to input, output and weight data types.""" From b4fb60458bf0b5e52425623bd2ee0f64f51e4d06 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Fri, 2 Feb 2024 15:33:52 +0000 Subject: [PATCH 470/665] [CustomOp] re arrange threshold mem_mode related attributes to match class hiearchy --- .../fpgadataflow/hls/thresholding_hls.py | 19 +----------------- .../fpgadataflow/rtl/thresholding_rtl.py | 4 ---- .../custom_op/fpgadataflow/thresholding.py | 20 +++++++++++++++++++ 3 files changed, 21 insertions(+), 22 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py b/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py index fb90365eef..1cd5f4d3ed 100644 --- a/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py @@ -59,24 +59,7 @@ def __init__(self, onnx_node, **kwargs): super().__init__(onnx_node, **kwargs) def get_nodeattr_types(self): - my_attrs = { - # string defining memory type - "ram_style": ("s", False, "distributed", {"distributed", "block"}), - # memory mode for the thresholds - # const -- embedded thresholds, default - # decoupled -- streaming thresholds with streamer packaged inside IP - "mem_mode": ("s", False, "const", {"const", "decoupled"}), - # (mem_mode = decoupled only) whether weights (thresholds) will be - # writable through an AXI-lite interface during runtime - # 1 for enabled, 0 for disabled. - # see finn-rtllib/memstream/doc/README for more about the memory - # address map used for writable weights - # IMPORTANT: After using AXI lite to either read or write the weights, - # always "flush" the accelerator by first passing a dummy input - # vector through the accelerator. This will get rid of any old - # weight data from the weight FIFOs. - "runtime_writeable_weights": ("i", False, 0, {0, 1}), - } + my_attrs = {} my_attrs.update(Thresholding.get_nodeattr_types(self)) my_attrs.update(HLSBackend.get_nodeattr_types(self)) return my_attrs diff --git a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py index a539ab6f84..50e30efc4f 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py @@ -78,10 +78,6 @@ def __init__(self, onnx_node, **kwargs): def get_nodeattr_types(self): my_attrs = { - # whether weights (thresholds) will be - # writable through an AXI-lite interface during runtime - # 1 for enabled, 0 for disabled. - "runtime_writeable_weights": ("i", False, 0, {0, 1}), # memory depth triggers for threshold storage "depth_trigger_uram": ("i", False, 0), "depth_trigger_bram": ("i", False, 0), diff --git a/src/finn/custom_op/fpgadataflow/thresholding.py b/src/finn/custom_op/fpgadataflow/thresholding.py index 1ce059358e..8494cf97bb 100644 --- a/src/finn/custom_op/fpgadataflow/thresholding.py +++ b/src/finn/custom_op/fpgadataflow/thresholding.py @@ -42,6 +42,26 @@ def __init__(self, onnx_node, **kwargs): def get_nodeattr_types(self): my_attrs = { + # memory mode for the thresholds + # const -- embedded thresholds, default + # decoupled -- streaming thresholds with streamer packaged inside IP + "mem_mode": ("s", False, "const", {"const", "decoupled"}), + # whether weights (thresholds) will be + # writable through an AXI-lite interface during runtime + # 1 for enabled, 0 for disabled. + "runtime_writeable_weights": ("i", False, 0, {0, 1}), + # FPGA resource type for memories in decoupled mode + # auto -- let Vivado decide + # block -- use BRAM + # distributed -- use LUTRAM + # ultra -- use UltraRAM (URAM), must have runtime_writeable_weights=1 + # see also https://www.xilinx.com/support/answers/38070.html + "ram_style": ( + "s", + False, + "auto", + {"auto", "block", "distributed", "ultra"}, + ), # parallelization; channels thresholded per cycle "PE": ("i", True, 0), # number of channels (each may have different thresholds) From 9ec0a3dd0d1bf9048cc52829867c4fa382080e0a Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Fri, 2 Feb 2024 15:35:50 +0000 Subject: [PATCH 471/665] [rtllib] Remove threshold IP Package --- finn-rtllib/thresholding/component.xml | 1002 ----------------- .../gui/thresholding_axi_v1_0.gtcl | 4 - .../xgui/thresholding_axi_v1_0.tcl | 187 --- 3 files changed, 1193 deletions(-) delete mode 100644 finn-rtllib/thresholding/component.xml delete mode 100644 finn-rtllib/thresholding/gui/thresholding_axi_v1_0.gtcl delete mode 100644 finn-rtllib/thresholding/xgui/thresholding_axi_v1_0.tcl diff --git a/finn-rtllib/thresholding/component.xml b/finn-rtllib/thresholding/component.xml deleted file mode 100644 index e28a3a2c2d..0000000000 --- a/finn-rtllib/thresholding/component.xml +++ /dev/null @@ -1,1002 +0,0 @@ - - - amd.com - finn - thresholding_axi - 1.0 - - - ap_clk - - - - - - - CLK - - - ap_clk - - - - - - ASSOCIATED_RESET - ap_rst_n - - - ASSOCIATED_BUSIF - s_axilite:s_axis:m_axis - - - FREQ_TOLERANCE_HZ - -1 - - - - - m_axis - - - - - - - TDATA - - - m_axis_tdata - - - - - TVALID - - - m_axis_tvalid - - - - - TREADY - - - m_axis_tready - - - - - - s_axis - - - - - - - TDATA - - - s_axis_tdata - - - - - TVALID - - - s_axis_tvalid - - - - - TREADY - - - s_axis_tready - - - - - - s_axilite - - - - - - - - - AWADDR - - - s_axilite_AWADDR - - - - - AWVALID - - - s_axilite_AWVALID - - - - - AWREADY - - - s_axilite_AWREADY - - - - - WDATA - - - s_axilite_WDATA - - - - - WSTRB - - - s_axilite_WSTRB - - - - - WVALID - - - s_axilite_WVALID - - - - - WREADY - - - s_axilite_WREADY - - - - - BRESP - - - s_axilite_BRESP - - - - - BVALID - - - s_axilite_BVALID - - - - - BREADY - - - s_axilite_BREADY - - - - - ARADDR - - - s_axilite_ARADDR - - - - - ARVALID - - - s_axilite_ARVALID - - - - - ARREADY - - - s_axilite_ARREADY - - - - - RDATA - - - s_axilite_RDATA - - - - - RRESP - - - s_axilite_RRESP - - - - - RVALID - - - s_axilite_RVALID - - - - - RREADY - - - s_axilite_RREADY - - - - - - ap_rst_n - - - - - - - RST - - - ap_rst_n - - - - - - POLARITY - ACTIVE_LOW - - - - - - - s_axilite - s_axilite - - reg0 - reg0 - 0x0 - 4096 - 32 - register - - - - - - - xilinx_anylanguagesynthesis - Synthesis - :vivado.xilinx.com:synthesis - Verilog - thresholding_axi_wrapper - - xilinx_anylanguagesynthesis_view_fileset - - - - viewChecksum - fd0bd85b - - - - - xilinx_anylanguagebehavioralsimulation - Simulation - :vivado.xilinx.com:simulation - Verilog - thresholding_axi_wrapper - - xilinx_anylanguagebehavioralsimulation_view_fileset - - - - viewChecksum - fd0bd85b - - - - - xilinx_xpgui - UI Layout - :vivado.xilinx.com:xgui.ui - - xilinx_xpgui_view_fileset - - - - viewChecksum - fc6b9b63 - - - - - xilinx_utilityxitfiles - Utility XIT/TTCL - :vivado.xilinx.com:xit.util - - xilinx_utilityxitfiles_view_fileset - - - - viewChecksum - 8b0215cd - - - - - - - ap_clk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - ap_rst_n - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axilite_AWVALID - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axilite_AWREADY - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axilite_AWADDR - - in - - 5 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axilite_WVALID - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axilite_WREADY - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axilite_WDATA - - in - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axilite_WSTRB - - in - - 3 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 1 - - - - - s_axilite_BVALID - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axilite_BREADY - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axilite_BRESP - - out - - 1 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axilite_ARVALID - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axilite_ARREADY - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axilite_ARADDR - - in - - 5 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axilite_RVALID - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axilite_RREADY - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - s_axilite_RDATA - - out - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axilite_RRESP - - out - - 1 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axis_tready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axis_tvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - s_axis_tdata - - in - - 15 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - m_axis_tready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 1 - - - - - m_axis_tvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - m_axis_tdata - - out - - 7 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - - N - N - 4 - - - K - K - 16 - - - C - C - 1 - - - PE - Pe - 1 - - - SIGNED - Signed - true - - - FPARG - Fparg - false - - - BIAS - Bias - 0 - - - CF - Cf - 1 - - - ADDR_BITS - Addr Bits - 6 - - - O_BITS - O Bits - 4 - - - - - - choice_list_9d8b0d81 - ACTIVE_HIGH - ACTIVE_LOW - - - - - xilinx_anylanguagesynthesis_view_fileset - - hdl/thresholding.sv - systemVerilogSource - - - hdl/thresholding_axi.sv - systemVerilogSource - - - hdl/thresholding_axi_wrapper.v - verilogSource - CHECKSUM_7b8c102d - - - hdl/axilite_if.v - verilogSource - CHECKSUM_69d1ba26 - xil_defaultlib - - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - hdl/thresholding.sv - systemVerilogSource - - - hdl/thresholding_axi.sv - systemVerilogSource - - - hdl/thresholding_axi_wrapper.v - verilogSource - - - hdl/axilite_if.v - verilogSource - USED_IN_ipstatic - xil_defaultlib - - - - xilinx_xpgui_view_fileset - - xgui/thresholding_axi_v1_0.tcl - tclSource - CHECKSUM_fc6b9b63 - XGUI_VERSION_2 - - - - xilinx_utilityxitfiles_view_fileset - - gui/thresholding_axi_v1_0.gtcl - GTCL - - - - MultiThreshold - - - N - Output Precision - 4 - - - K - Input Precision - 16 - - - C - Channels - 1 - - - PE - Pe - 1 - - - SIGNED - Signed Inputs - true - - - FPARG - Floating-Point Inputs - false - - - BIAS - Bias - 0 - - - CF - Channel Fold - 1 - - - - false - - - - - - ADDR_BITS - Address Bits - 6 - - - - false - - - - - - O_BITS - Output Value Width - 4 - - - - false - - - - - - Component_Name - thresholding_axi_wrapper_v1_0 - - - - - - virtex7 - qvirtex7 - versal - kintex7 - kintex7l - qkintex7 - qkintex7l - akintex7 - artix7 - artix7l - aartix7 - qartix7 - zynq - qzynq - azynq - spartan7 - aspartan7 - virtexu - zynquplus - virtexuplus - virtexuplusHBM - virtexuplus58g - kintexuplus - artixuplus - kintexu - - - /UserIP - - thresholding_axi - level_1 - package_project - 2 - - user.org:user:thresholding_axi_wrapper:1.0 - - 2023-06-27T05:47:20Z - - - - - - 2022.2 - - - - - - - - - - - - - - diff --git a/finn-rtllib/thresholding/gui/thresholding_axi_v1_0.gtcl b/finn-rtllib/thresholding/gui/thresholding_axi_v1_0.gtcl deleted file mode 100644 index 90d73ede7e..0000000000 --- a/finn-rtllib/thresholding/gui/thresholding_axi_v1_0.gtcl +++ /dev/null @@ -1,4 +0,0 @@ -# This file is automatically written. Do not modify. -proc gen_USERPARAMETER_CF_VALUE {C PE } {expr $C/$PE} -proc gen_USERPARAMETER_ADDR_BITS_VALUE {C PE N } {expr int(ceil(log($C/$PE)/log(2))+ceil(log($PE)/log(2))+$N+2)} -proc gen_USERPARAMETER_O_BITS_VALUE {BIAS N } {expr int(ceil($BIAS >= 0? log(pow(2,$N)+$BIAS)/log(2) : 1+log(-$BIAS >= pow(2,$N-1)? -$BIAS : pow(2,$N)+$BIAS)/log(2)))} diff --git a/finn-rtllib/thresholding/xgui/thresholding_axi_v1_0.tcl b/finn-rtllib/thresholding/xgui/thresholding_axi_v1_0.tcl deleted file mode 100644 index 338304fa40..0000000000 --- a/finn-rtllib/thresholding/xgui/thresholding_axi_v1_0.tcl +++ /dev/null @@ -1,187 +0,0 @@ - -# Loading additional proc with user specified bodies to compute parameter values. -source [file join [file dirname [file dirname [info script]]] gui/thresholding_axi_v1_0.gtcl] - -# Definitional proc to organize widgets for parameters. -proc init_gui { IPINST } { - ipgui::add_param $IPINST -name "Component_Name" - #Adding Page - set Page_0 [ipgui::add_page $IPINST -name "Page 0"] - ipgui::add_param $IPINST -name "ADDR_BITS" -parent ${Page_0} - ipgui::add_param $IPINST -name "BIAS" -parent ${Page_0} - ipgui::add_param $IPINST -name "C" -parent ${Page_0} - ipgui::add_param $IPINST -name "CF" -parent ${Page_0} - ipgui::add_param $IPINST -name "FPARG" -parent ${Page_0} - ipgui::add_param $IPINST -name "K" -parent ${Page_0} - ipgui::add_param $IPINST -name "N" -parent ${Page_0} - ipgui::add_param $IPINST -name "O_BITS" -parent ${Page_0} - set PE [ipgui::add_param $IPINST -name "PE" -parent ${Page_0}] - set_property tooltip {PE Count} ${PE} - ipgui::add_param $IPINST -name "SIGNED" -parent ${Page_0} - - -} - -proc update_PARAM_VALUE.ADDR_BITS { PARAM_VALUE.ADDR_BITS PARAM_VALUE.C PARAM_VALUE.PE PARAM_VALUE.N } { - # Procedure called to update ADDR_BITS when any of the dependent parameters in the arguments change - - set ADDR_BITS ${PARAM_VALUE.ADDR_BITS} - set C ${PARAM_VALUE.C} - set PE ${PARAM_VALUE.PE} - set N ${PARAM_VALUE.N} - set values(C) [get_property value $C] - set values(PE) [get_property value $PE] - set values(N) [get_property value $N] - set_property value [gen_USERPARAMETER_ADDR_BITS_VALUE $values(C) $values(PE) $values(N)] $ADDR_BITS -} - -proc validate_PARAM_VALUE.ADDR_BITS { PARAM_VALUE.ADDR_BITS } { - # Procedure called to validate ADDR_BITS - return true -} - -proc update_PARAM_VALUE.CF { PARAM_VALUE.CF PARAM_VALUE.C PARAM_VALUE.PE } { - # Procedure called to update CF when any of the dependent parameters in the arguments change - - set CF ${PARAM_VALUE.CF} - set C ${PARAM_VALUE.C} - set PE ${PARAM_VALUE.PE} - set values(C) [get_property value $C] - set values(PE) [get_property value $PE] - set_property value [gen_USERPARAMETER_CF_VALUE $values(C) $values(PE)] $CF -} - -proc validate_PARAM_VALUE.CF { PARAM_VALUE.CF } { - # Procedure called to validate CF - return true -} - -proc update_PARAM_VALUE.O_BITS { PARAM_VALUE.O_BITS PARAM_VALUE.BIAS PARAM_VALUE.N } { - # Procedure called to update O_BITS when any of the dependent parameters in the arguments change - - set O_BITS ${PARAM_VALUE.O_BITS} - set BIAS ${PARAM_VALUE.BIAS} - set N ${PARAM_VALUE.N} - set values(BIAS) [get_property value $BIAS] - set values(N) [get_property value $N] - set_property value [gen_USERPARAMETER_O_BITS_VALUE $values(BIAS) $values(N)] $O_BITS -} - -proc validate_PARAM_VALUE.O_BITS { PARAM_VALUE.O_BITS } { - # Procedure called to validate O_BITS - return true -} - -proc update_PARAM_VALUE.BIAS { PARAM_VALUE.BIAS } { - # Procedure called to update BIAS when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.BIAS { PARAM_VALUE.BIAS } { - # Procedure called to validate BIAS - return true -} - -proc update_PARAM_VALUE.C { PARAM_VALUE.C } { - # Procedure called to update C when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.C { PARAM_VALUE.C } { - # Procedure called to validate C - return true -} - -proc update_PARAM_VALUE.FPARG { PARAM_VALUE.FPARG } { - # Procedure called to update FPARG when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.FPARG { PARAM_VALUE.FPARG } { - # Procedure called to validate FPARG - return true -} - -proc update_PARAM_VALUE.K { PARAM_VALUE.K } { - # Procedure called to update K when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.K { PARAM_VALUE.K } { - # Procedure called to validate K - return true -} - -proc update_PARAM_VALUE.N { PARAM_VALUE.N } { - # Procedure called to update N when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.N { PARAM_VALUE.N } { - # Procedure called to validate N - return true -} - -proc update_PARAM_VALUE.PE { PARAM_VALUE.PE } { - # Procedure called to update PE when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.PE { PARAM_VALUE.PE } { - # Procedure called to validate PE - return true -} - -proc update_PARAM_VALUE.SIGNED { PARAM_VALUE.SIGNED } { - # Procedure called to update SIGNED when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.SIGNED { PARAM_VALUE.SIGNED } { - # Procedure called to validate SIGNED - return true -} - - -proc update_MODELPARAM_VALUE.N { MODELPARAM_VALUE.N PARAM_VALUE.N } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.N}] ${MODELPARAM_VALUE.N} -} - -proc update_MODELPARAM_VALUE.K { MODELPARAM_VALUE.K PARAM_VALUE.K } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.K}] ${MODELPARAM_VALUE.K} -} - -proc update_MODELPARAM_VALUE.C { MODELPARAM_VALUE.C PARAM_VALUE.C } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.C}] ${MODELPARAM_VALUE.C} -} - -proc update_MODELPARAM_VALUE.PE { MODELPARAM_VALUE.PE PARAM_VALUE.PE } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.PE}] ${MODELPARAM_VALUE.PE} -} - -proc update_MODELPARAM_VALUE.SIGNED { MODELPARAM_VALUE.SIGNED PARAM_VALUE.SIGNED } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.SIGNED}] ${MODELPARAM_VALUE.SIGNED} -} - -proc update_MODELPARAM_VALUE.FPARG { MODELPARAM_VALUE.FPARG PARAM_VALUE.FPARG } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.FPARG}] ${MODELPARAM_VALUE.FPARG} -} - -proc update_MODELPARAM_VALUE.BIAS { MODELPARAM_VALUE.BIAS PARAM_VALUE.BIAS } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.BIAS}] ${MODELPARAM_VALUE.BIAS} -} - -proc update_MODELPARAM_VALUE.CF { MODELPARAM_VALUE.CF PARAM_VALUE.CF } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.CF}] ${MODELPARAM_VALUE.CF} -} - -proc update_MODELPARAM_VALUE.ADDR_BITS { MODELPARAM_VALUE.ADDR_BITS PARAM_VALUE.ADDR_BITS } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.ADDR_BITS}] ${MODELPARAM_VALUE.ADDR_BITS} -} - -proc update_MODELPARAM_VALUE.O_BITS { MODELPARAM_VALUE.O_BITS PARAM_VALUE.O_BITS } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.O_BITS}] ${MODELPARAM_VALUE.O_BITS} -} From 3fd52600a9e095c04084b300e46fdb8fb4aee553 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Fri, 2 Feb 2024 15:56:47 +0000 Subject: [PATCH 472/665] [CustomOp] do not allow ram_style for threshold RTL --- .../custom_op/fpgadataflow/hls/thresholding_hls.py | 5 ++++- src/finn/custom_op/fpgadataflow/thresholding.py | 12 ------------ 2 files changed, 4 insertions(+), 13 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py b/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py index 1cd5f4d3ed..16dee92e8a 100644 --- a/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py @@ -59,7 +59,10 @@ def __init__(self, onnx_node, **kwargs): super().__init__(onnx_node, **kwargs) def get_nodeattr_types(self): - my_attrs = {} + my_attrs = { + # string defining memory type + "ram_style": ("s", False, "distributed", {"distributed", "block"}), + } my_attrs.update(Thresholding.get_nodeattr_types(self)) my_attrs.update(HLSBackend.get_nodeattr_types(self)) return my_attrs diff --git a/src/finn/custom_op/fpgadataflow/thresholding.py b/src/finn/custom_op/fpgadataflow/thresholding.py index 8494cf97bb..945ec16cf0 100644 --- a/src/finn/custom_op/fpgadataflow/thresholding.py +++ b/src/finn/custom_op/fpgadataflow/thresholding.py @@ -50,18 +50,6 @@ def get_nodeattr_types(self): # writable through an AXI-lite interface during runtime # 1 for enabled, 0 for disabled. "runtime_writeable_weights": ("i", False, 0, {0, 1}), - # FPGA resource type for memories in decoupled mode - # auto -- let Vivado decide - # block -- use BRAM - # distributed -- use LUTRAM - # ultra -- use UltraRAM (URAM), must have runtime_writeable_weights=1 - # see also https://www.xilinx.com/support/answers/38070.html - "ram_style": ( - "s", - False, - "auto", - {"auto", "block", "distributed", "ultra"}, - ), # parallelization; channels thresholded per cycle "PE": ("i", True, 0), # number of channels (each may have different thresholds) From c8281c33d47bc084375dbf4d7b21cf69c261ee57 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Fri, 2 Feb 2024 15:58:37 +0000 Subject: [PATCH 473/665] Revert "[Pyverilator] update to new rtlsim_multi_io implementation" This reverts commit c54d32ce2fb619cfd231579dd2b8f0ddcf711983. --- fetch-repos.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fetch-repos.sh b/fetch-repos.sh index ba7cd28a00..1275ccf31c 100755 --- a/fetch-repos.sh +++ b/fetch-repos.sh @@ -30,7 +30,7 @@ QONNX_COMMIT="47e4357faf66b5b0d1bf77bf908bb47752421e5b" FINN_EXP_COMMIT="de99347e936d51715f5356a1b6c64e37b91c23c2" BREVITAS_COMMIT="84f42259ec869eb151af4cb8a8b23ad925f493db" -PYVERILATOR_COMMIT="fc2dd96ac07c5a23897af8f0b0339135e12fa0ba" +PYVERILATOR_COMMIT="766e457465f5c0dd315490d7b9cc5d74f9a76f4f" CNPY_COMMIT="4e8810b1a8637695171ed346ce68f6984e585ef4" HLSLIB_COMMIT="16e5847a5e3ef76cffe84c8fad2f010d593457d3" OMX_COMMIT="0b59762f9e4c4f7e5aa535ee9bc29f292434ca7a" From 3f3b7c5e6972a0ade4f8e3488152e2febe4d2325 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Fri, 2 Feb 2024 16:52:41 +0000 Subject: [PATCH 474/665] [CustomOp] Thresholding node must explicitly reset_rtlsim --- src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py index 50e30efc4f..48aeb0b9f8 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py @@ -31,7 +31,7 @@ import os import shutil import warnings -from pyverilator.util.axi_utils import rtlsim_multi_io +from pyverilator.util.axi_utils import rtlsim_multi_io, reset_rtlsim from qonnx.core.datatype import DataType from qonnx.util.basic import ( interleave_matrix_outer_dim_from_partitions, @@ -603,13 +603,13 @@ def rtlsim_multi_io(self, sim, io_dict): if trace_file == "default": trace_file = self.onnx_node.name + ".vcd" num_out_values = self.get_number_output_values() + reset_rtlsim(sim) total_cycle_count = rtlsim_multi_io( sim, io_dict, num_out_values, trace_file=trace_file, sname=sname, - do_reset=True, liveness_threshold=pyverilate_get_liveness_threshold_cycles(), ) self.set_nodeattr("cycles_rtlsim", total_cycle_count) From 84ec9eadb5a8c2a19db26453084fe355069b58b8 Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 2 Feb 2024 17:22:43 +0000 Subject: [PATCH 475/665] [CustomOp/Transform] Fix linting and cleanup --- .../analysis/fpgadataflow/res_estimation.py | 6 +- .../custom_op/fpgadataflow/hls/__init__.py | 10 ++- .../hls/matrixvectoractivation_hls.py | 33 ++------- .../hls/vectorvectoractivation_hls.py | 22 ++---- .../fpgadataflow/matrixvectoractivation.py | 70 +++++++------------ .../fpgadataflow/vectorvectoractivation.py | 41 +++++------ .../fpgadataflow/convert_to_hw_layers.py | 5 +- .../fpgadataflow/create_stitched_ip.py | 4 +- .../transformation/fpgadataflow/floorplan.py | 2 +- .../transformation/fpgadataflow/insert_dwc.py | 2 +- .../fpgadataflow/insert_iodma.py | 3 +- .../fpgadataflow/insert_tlastmarker.py | 4 +- .../fpgadataflow/make_pynq_driver.py | 4 +- .../fpgadataflow/make_zynq_proj.py | 4 +- .../fpgadataflow/set_fifo_depths.py | 8 +-- .../fpgadataflow/set_folding.py | 2 +- tests/fpgadataflow/test_fpgadataflow_mvau.py | 10 +-- 17 files changed, 90 insertions(+), 140 deletions(-) diff --git a/src/finn/analysis/fpgadataflow/res_estimation.py b/src/finn/analysis/fpgadataflow/res_estimation.py index a7f220daa9..d48c423b9d 100644 --- a/src/finn/analysis/fpgadataflow/res_estimation.py +++ b/src/finn/analysis/fpgadataflow/res_estimation.py @@ -61,8 +61,10 @@ def res_estimation_complete(model): for node in model.graph.node: if is_fpgadataflow_node(node) is True: inst = registry.getCustomOp(node) - op_type = inst.base_op_type() - if op_type == "MatrixVectorActivation" or op_type == "VectorVectorActivation": + op_type = node.op_type + if op_type.startswith("MatrixVectorActivation") or op_type.startswith( + "VectorVectorActivation" + ): orig_restype = inst.get_nodeattr("resType") res_dict[node.name] = [] inst.set_nodeattr("resType", "dsp") diff --git a/src/finn/custom_op/fpgadataflow/hls/__init__.py b/src/finn/custom_op/fpgadataflow/hls/__init__.py index ebb5ce98da..1e2c83ba39 100644 --- a/src/finn/custom_op/fpgadataflow/hls/__init__.py +++ b/src/finn/custom_op/fpgadataflow/hls/__init__.py @@ -41,6 +41,9 @@ from finn.custom_op.fpgadataflow.hls.iodma_hls import IODMA_hls from finn.custom_op.fpgadataflow.hls.labelselect_hls import LabelSelect_hls from finn.custom_op.fpgadataflow.hls.lookup_hls import Lookup_hls +from finn.custom_op.fpgadataflow.hls.matrixvectoractivation_hls import ( + MatrixVectorActivation_hls, +) from finn.custom_op.fpgadataflow.hls.pool_hls import Pool_hls from finn.custom_op.fpgadataflow.hls.streamingdatawidthconverter_hls import ( StreamingDataWidthConverter_hls, @@ -50,8 +53,9 @@ from finn.custom_op.fpgadataflow.hls.thresholding_hls import Thresholding_hls from finn.custom_op.fpgadataflow.hls.tlastmarker_hls import TLastMarker_hls from finn.custom_op.fpgadataflow.hls.upsampler_hls import UpsampleNearestNeighbour_hls -from finn.custom_op.fpgadataflow.hls.matrixvectoractivation_hls import MatrixVectorActivation_hls -from finn.custom_op.fpgadataflow.hls.vectorvectoractivation_hls import VectorVectorActivation_hls +from finn.custom_op.fpgadataflow.hls.vectorvectoractivation_hls import ( + VectorVectorActivation_hls, +) custom_op = dict() @@ -78,4 +82,4 @@ custom_op["TLastMarker_hls"] = TLastMarker_hls custom_op["UpsampleNearestNeighbour_hls"] = UpsampleNearestNeighbour_hls custom_op["MatrixVectorActivation_hls"] = MatrixVectorActivation_hls -custom_op["VectorVectorActivation_hls"] = VectorVectorActivation_hls \ No newline at end of file +custom_op["VectorVectorActivation_hls"] = VectorVectorActivation_hls diff --git a/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py b/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py index e27e77fe4f..5206ee3a06 100644 --- a/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py @@ -26,26 +26,13 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import math import numpy as np import os -import textwrap -import warnings from qonnx.core.datatype import DataType -from qonnx.util.basic import ( - calculate_matvec_accumulator_range, - interleave_matrix_outer_dim_from_partitions, - roundup_to_integer_multiple, -) -from finn.custom_op.fpgadataflow.matrixvectoractivation import MatrixVectorActivation from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend -from finn.util.data_packing import ( - npy_to_rtlsim_input, - numpy_to_hls_code, - pack_innermost_dim_as_hex_string, - rtlsim_output_to_npy, -) +from finn.custom_op.fpgadataflow.matrixvectoractivation import MatrixVectorActivation +from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy # ONNX i/o tensor shape assumptions for MatrixVectorActivation: # input 0 is the input tensor, shape (.., i_size) = (..., MW) @@ -60,7 +47,7 @@ class MatrixVectorActivation_hls(MatrixVectorActivation, HLSBackend): def __init__(self, onnx_node, **kwargs): super().__init__(onnx_node, **kwargs) - + def get_nodeattr_types(self): my_attrs = {} my_attrs.update(MatrixVectorActivation.get_nodeattr_types(self)) @@ -480,17 +467,13 @@ def execute_node(self, context, graph): elif mode == "rtlsim": sim = self.get_rtlsim() nbits = self.get_instream_width() - inp = npy_to_rtlsim_input( - "{}/input_0.npy".format(code_gen_dir), export_idt, nbits - ) + inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) self.reset_rtlsim(sim) self.toggle_clk(sim) if mem_mode in ["external", "decoupled"]: wnbits = self.get_weightstream_width() export_wdt = self.get_weight_datatype() - wei = npy_to_rtlsim_input( - "{}/weights.npy".format(code_gen_dir), export_wdt, wnbits - ) + wei = npy_to_rtlsim_input("{}/weights.npy".format(code_gen_dir), export_wdt, wnbits) num_w_reps = np.prod(self.get_nodeattr("numInputVectors")) io_dict = { "inputs": {"in0": inp, "weights": wei * num_w_reps}, @@ -505,9 +488,7 @@ def execute_node(self, context, graph): packed_bits = self.get_outstream_width() out_npy_path = "{}/output.npy".format(code_gen_dir) out_shape = self.get_folded_output_shape() - rtlsim_output_to_npy( - output, out_npy_path, odt, out_shape, packed_bits, target_bits - ) + rtlsim_output_to_npy(output, out_npy_path, odt, out_shape, packed_bits, target_bits) # load and reshape output output = np.load(out_npy_path) oshape = self.get_normal_output_shape() @@ -519,4 +500,4 @@ def execute_node(self, context, graph): has to be set to "rtlsim" """.format( mode ) - ) \ No newline at end of file + ) diff --git a/src/finn/custom_op/fpgadataflow/hls/vectorvectoractivation_hls.py b/src/finn/custom_op/fpgadataflow/hls/vectorvectoractivation_hls.py index c824f9682c..7e475ff67f 100644 --- a/src/finn/custom_op/fpgadataflow/hls/vectorvectoractivation_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/vectorvectoractivation_hls.py @@ -26,26 +26,14 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import math import numpy as np import os -import textwrap -import warnings from qonnx.core.datatype import DataType -from qonnx.util.basic import ( - calculate_matvec_accumulator_range, - interleave_matrix_outer_dim_from_partitions, - roundup_to_integer_multiple, -) - -from finn.util.data_packing import ( - npy_to_rtlsim_input, - numpy_to_hls_code, - pack_innermost_dim_as_hex_string, - rtlsim_output_to_npy, -) -from finn.custom_op.fpgadataflow.vectorvectoractivation import VectorVectorActivation + from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend +from finn.custom_op.fpgadataflow.vectorvectoractivation import VectorVectorActivation +from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy + class VectorVectorActivation_hls(VectorVectorActivation, HLSBackend): """Corresponds to finn-hlslib Vector_Vector_Activate_Batch function""" @@ -475,4 +463,4 @@ def get_verilog_top_module_intf_names(self): runtime_writable = self.get_nodeattr("runtime_writeable_weights") == 1 if runtime_writable: intf_names["axilite"] = ["s_axilite"] - return intf_names \ No newline at end of file + return intf_names diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index 04594f4109..463a4effa8 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -28,35 +28,20 @@ import math import numpy as np -import os +import onnx.numpy_helper as np_helper +import qonnx.custom_op.general.xnorpopcount as xp import textwrap import warnings -from onnx import TensorProto, helper from qonnx.core.datatype import DataType -import qonnx.custom_op.general.xnorpopcount as xp from qonnx.custom_op.general.multithreshold import multithreshold -from qonnx.core.modelwrapper import ModelWrapper -from qonnx.custom_op.registry import getCustomOp from qonnx.util.basic import ( calculate_matvec_accumulator_range, interleave_matrix_outer_dim_from_partitions, roundup_to_integer_multiple, - qonnx_make_model ) from finn.custom_op.fpgadataflow.hwcustomop import HWCustomOp -from finn.util.data_packing import ( - npy_to_rtlsim_input, - numpy_to_hls_code, - pack_innermost_dim_as_hex_string, - rtlsim_output_to_npy, -) -import qonnx.core.data_layout as DataLayout -import finn.core.onnx_exec as oxe -from qonnx.transformation.infer_shapes import InferShapes -import onnx.numpy_helper as np_helper -from qonnx.transformation.general import GiveUniqueNodeNames - +from finn.util.data_packing import numpy_to_hls_code, pack_innermost_dim_as_hex_string # ONNX i/o tensor shape assumptions for MatrixVectorActivation: # input 0 is the input tensor, shape (.., i_size) = (..., MW) @@ -133,7 +118,7 @@ def get_nodeattr_types(self): # vector through the accelerator. This will get rid of any old # weight data from the weight FIFOs. "runtime_writeable_weights": ("i", False, 0, {0, 1}), - } + } my_attrs.update(super().get_nodeattr_types()) return my_attrs @@ -147,11 +132,15 @@ def execute_node(self, context, graph): mvau_w = np_helper.to_array(mvau_w_init) # Matrix multiplication if self.get_nodeattr("binaryXnorMode"): - # Note: activation/weights are expected to be binary (by design coming from the transformation inferring this operation mode) + # Note: activation/weights are expected to be binary + # (by design coming from the transformation inferring this operation mode) result = xp.xnorpopcountmatmul(in_act, mvau_w) - elif (self.get_nodeattr("inputDataType") == "BIPOLAR" and self.get_nodeattr("weightDataType") == "BIPOLAR"): + elif ( + self.get_nodeattr("inputDataType") == "BIPOLAR" + and self.get_nodeattr("weightDataType") == "BIPOLAR" + ): # Convert to binary and use xnorpopcountmatmul function - result = xp.xnorpopcountmatmul((in_act+1)/2, (mvau_w+1)/2) + result = xp.xnorpopcountmatmul((in_act + 1) / 2, (mvau_w + 1) / 2) else: # Regular matrix multiplication result = np.matmul(in_act, mvau_w) @@ -162,11 +151,11 @@ def execute_node(self, context, graph): out_scale = 2 if odt_is_bipolar else 1 out_bias = -1 if odt_is_bipolar else self.get_nodeattr("ActVal") # NHWC to NCHW for multithreshold node - result = result.transpose((0,3,1,2)) + result = result.transpose((0, 3, 1, 2)) result = multithreshold(result, mvau_thr, out_scale, out_bias) # NCHW to NHWC - result = result.transpose((0,2,3,1)) - + result = result.transpose((0, 2, 3, 1)) + context[node.output[0]] = result def verify_node(self): @@ -260,20 +249,22 @@ def get_weight_datatype(self): def get_accumulator_datatype(self): """Returns FINN DataType of accumulator""" - return DataType[self.get_nodeattr("accDataType")] + return DataType[self.get_nodeattr("accDataType")] def get_output_datatype(self, ind=0): """Returns FINN DataType of output.""" - return DataType[self.get_nodeattr("outputDataType")] + return DataType[self.get_nodeattr("outputDataType")] def get_instream_width(self, ind=0): i_bits = self.get_input_datatype().bitwidth() - assert ( - i_bits <= 9 - ), "RTL-based MVAU only supports activations with bit-width up to 9-bits" in_width = i_bits * self.get_nodeattr("SIMD") return in_width + def get_outstream_width(self, ind=0): + o_bits = self.get_output_datatype().bitwidth() + out_width = o_bits * self.get_nodeattr("PE") + return out_width + def get_weightstream_width(self): """Returns weight stream width. Used only in decoupled mode.""" if ( @@ -283,19 +274,11 @@ def get_weightstream_width(self): pe = self.get_nodeattr("PE") simd = self.get_nodeattr("SIMD") wp = self.get_weight_datatype().bitwidth() - assert ( - wp <= 8 - ), "RTL-based MVAU only supports weights with bit-width up to 8-bits" w_width = pe * simd * wp return w_width else: return 0 - def get_outstream_width(self, ind=0): - o_bits = self.get_output_datatype().bitwidth() - out_width = o_bits * self.get_nodeattr("PE") - return out_width - def get_weightstream_width_padded(self): """Returns weight stream width padded to a multiple of 8. This is required by the AXI Stream spec. Used in decoupled mode.""" @@ -964,8 +947,7 @@ def code_generation_ipi(self): cmd.append("create_bd_pin -dir I -type rst /%s/%s" % (node_name, rst_name)) cmd.append( "create_bd_intf_pin -mode Master " - "-vlnv xilinx.com:interface:axis_rtl:1.0 /%s/%s" - % (node_name, dout_name) + "-vlnv xilinx.com:interface:axis_rtl:1.0 /%s/%s" % (node_name, dout_name) ) cmd.append( "create_bd_intf_pin -mode Slave " @@ -981,8 +963,7 @@ def code_generation_ipi(self): strm_vlnv = "amd.com:finn:memstream:1.0" strm_inst = node_name + "_wstrm" cmd.append( - "create_bd_cell -type ip -vlnv %s /%s/%s" - % (strm_vlnv, node_name, strm_inst) + "create_bd_cell -type ip -vlnv %s /%s/%s" % (strm_vlnv, node_name, strm_inst) ) cmd.append( "set_property -dict [list " @@ -1036,8 +1017,7 @@ def code_generation_ipi(self): axilite_name = self.get_verilog_top_module_intf_names()["axilite"][0] cmd.append( "create_bd_intf_pin -mode Slave " - "-vlnv xilinx.com:interface:aximm_rtl:1.0 /%s/%s" - % (node_name, axilite_name) + "-vlnv xilinx.com:interface:aximm_rtl:1.0 /%s/%s" % (node_name, axilite_name) ) cmd.append( "connect_bd_intf_net [get_bd_intf_pins %s/%s] " @@ -1052,4 +1032,4 @@ def code_generation_ipi(self): return super().code_generation_ipi() else: raise Exception("Unrecognized mem_mode for MatrixVectorActivation") - return cmd \ No newline at end of file + return cmd diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index e793321879..79265f8daa 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -28,10 +28,11 @@ import math import numpy as np -import os +import onnx.numpy_helper as np_helper import textwrap import warnings from qonnx.core.datatype import DataType +from qonnx.custom_op.general.multithreshold import multithreshold from qonnx.util.basic import ( calculate_matvec_accumulator_range, interleave_matrix_outer_dim_from_partitions, @@ -39,16 +40,7 @@ ) from finn.custom_op.fpgadataflow.hwcustomop import HWCustomOp -from finn.util.data_packing import ( - npy_to_rtlsim_input, - numpy_to_hls_code, - pack_innermost_dim_as_hex_string, - rtlsim_output_to_npy, -) -import onnx.numpy_helper as np_helper -import qonnx.custom_op.general.xnorpopcount as xp -from qonnx.custom_op.general.multithreshold import multithreshold - +from finn.util.data_packing import numpy_to_hls_code, pack_innermost_dim_as_hex_string class VectorVectorActivation(HWCustomOp): @@ -131,19 +123,22 @@ def execute_node(self, context, graph): # Reorder the input activations. Note that PE gets interleaved by the SWG, # so we have to untangle and for simplicity of computation assume pe=1. # Note that PE has no effect on the QONNX node - in_act = in_act.reshape(1, dim_h, dim_w, channels // pe, k_h*k_w, pe) + in_act = in_act.reshape(1, dim_h, dim_w, channels // pe, k_h * k_w, pe) in_act = in_act.transpose(0, 1, 2, 4, 3, 5) - in_act = in_act.reshape(1, dim_h, dim_w, channels*k_h*k_w) + in_act = in_act.reshape(1, dim_h, dim_w, channels * k_h * k_w) # Reshape weights in appropriate format vvau_w_init = [x for x in graph.initializer if x.name == node.input[1]][0] vvau_w = np_helper.to_array(vvau_w_init) vvau_w_onnx = self._infer_sparse_weight_tensor(vvau_w, k_h, k_w, channels) - if self.get_nodeattr("inputDataType") == "BIPOLAR" and self.get_nodeattr("weightDataType") == "BIPOLAR": - result = np.matmul(in_act, vvau_w_onnx) # result is in [N, H, W, C] format - result = (result + k_h*k_w) / 2 + if ( + self.get_nodeattr("inputDataType") == "BIPOLAR" + and self.get_nodeattr("weightDataType") == "BIPOLAR" + ): + result = np.matmul(in_act, vvau_w_onnx) # result is in [N, H, W, C] format + result = (result + k_h * k_w) / 2 else: - result = np.matmul(in_act, vvau_w_onnx) # result is in [N, H, W, C] format + result = np.matmul(in_act, vvau_w_onnx) # result is in [N, H, W, C] format if self.get_nodeattr("noActivation") == 0: vvau_thr_init = [x for x in graph.initializer if x.name == node.input[2]][0] @@ -152,16 +147,16 @@ def execute_node(self, context, graph): out_scale = 2 if odt_is_bipolar else 1 out_bias = -1 if odt_is_bipolar else self.get_nodeattr("ActVal") # NHWC to NCHW for multithreshold node - result = result.transpose((0,3,1,2)) + result = result.transpose((0, 3, 1, 2)) result = multithreshold(result, vvau_thr, out_scale, out_bias) # NCHW to NHWC - result = result.transpose((0,2,3,1)) - + result = result.transpose((0, 2, 3, 1)) + context[node.output[0]] = result def verify_node(self): pass - + def make_shape_compatible_op(self, model): oshape = self.get_normal_output_shape() return super().make_const_shape_op(oshape) @@ -203,7 +198,7 @@ def get_instream_width(self, ind=0): pe = self.get_nodeattr("PE") in_width = i_bits * simd * pe return in_width - + def get_weightstream_width(self): """Returns weight stream width. Used only in decoupled mode.""" if ( @@ -962,4 +957,4 @@ def code_generation_ipi(self): return super().code_generation_ipi() else: raise Exception("Unrecognized mem_mode for VectorVectorActivation") - return cmd \ No newline at end of file + return cmd diff --git a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py index 26cd0b74ad..ade76afdde 100644 --- a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py +++ b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py @@ -1281,6 +1281,7 @@ def apply(self, model): return (model, graph_modified) + class InferBinaryMatrixVectorActivation(Transformation): """Convert XnorPopcountMatMul layers to MatrixVectorActivation layers. Any immediately following MultiThreshold @@ -1414,6 +1415,7 @@ def apply(self, model): model = model.transform(InferDataTypes()) return (model, graph_modified) + class InferQuantizedMatrixVectorActivation(Transformation): """Convert MatMul layers with quantized inputs and weights to MatrixVectorActivation layers.""" @@ -1550,6 +1552,7 @@ def apply(self, model): model = model.transform(InferDataTypes()) return (model, graph_modified) + class InferVectorVectorActivation(Transformation): """Convert MatMul layers with quantized inputs and weights to VectorVectorActivation layers, if the sparsity annotation @@ -1694,4 +1697,4 @@ def apply(self, model): if graph_modified: model = model.transform(InferShapes()) model = model.transform(InferDataTypes()) - return (model, graph_modified) \ No newline at end of file + return (model, graph_modified) diff --git a/src/finn/transformation/fpgadataflow/create_stitched_ip.py b/src/finn/transformation/fpgadataflow/create_stitched_ip.py index 81c5848d57..1c316e1285 100644 --- a/src/finn/transformation/fpgadataflow/create_stitched_ip.py +++ b/src/finn/transformation/fpgadataflow/create_stitched_ip.py @@ -48,13 +48,13 @@ def is_external_input(model, node, i): # True only if input is unconnected and has no initializer # Only esception is second input of FC layers when mem_mode is external node_inst = getCustomOp(node) - op_type = node_inst.base_op_type() + op_type = node.op_type producer = model.find_producer(node.input[i]) if producer is None: if model.get_initializer(node.input[i]) is None: return True else: - if op_type == "MatrixVectorActivation": + if op_type.startswith("MatrixVectorActivation"): if node_inst.get_nodeattr("mem_mode") == "external": return True return False diff --git a/src/finn/transformation/fpgadataflow/floorplan.py b/src/finn/transformation/fpgadataflow/floorplan.py index 56e644f2b8..6149dffd59 100644 --- a/src/finn/transformation/fpgadataflow/floorplan.py +++ b/src/finn/transformation/fpgadataflow/floorplan.py @@ -150,7 +150,7 @@ def apply(self, model): continue elif not ( - node_inst.base_op_type() == "MatrixVectorActivation" + node.op_type.startswith("MatrixVectorActivation") and node_inst.get_nodeattr("mem_mode") is not None and node_inst.get_nodeattr("mem_mode") == "external" ): diff --git a/src/finn/transformation/fpgadataflow/insert_dwc.py b/src/finn/transformation/fpgadataflow/insert_dwc.py index d0029cb630..f6dd587c76 100644 --- a/src/finn/transformation/fpgadataflow/insert_dwc.py +++ b/src/finn/transformation/fpgadataflow/insert_dwc.py @@ -88,7 +88,7 @@ def apply(self, model): # - if FC and external mem, it could be connected to input 1 # - if concat, could be connected to any input if ( - n1.base_op_type() == "MatrixVectorActivation" + consumer.op_type.startswith("MatrixVectorActivation") and n1.get_nodeattr("mem_mode") == "external" ) or (consumer.op_type == "StreamingConcat"): # get input idx diff --git a/src/finn/transformation/fpgadataflow/insert_iodma.py b/src/finn/transformation/fpgadataflow/insert_iodma.py index fd546459fa..f3334d94f5 100644 --- a/src/finn/transformation/fpgadataflow/insert_iodma.py +++ b/src/finn/transformation/fpgadataflow/insert_iodma.py @@ -199,7 +199,8 @@ def apply(self, model): # attached IODMA fc_extw_nodes = list( filter( - lambda x: getCustomOp(x).base_op_type() in ["MatrixVectorActivation", "VectorVectorActivation"] + lambda x: x.op_type + in ["MatrixVectorActivation_hls", "VectorVectorActivation_hls"] and getCustomOp(x).get_nodeattr("mem_mode") == "external" and model.find_producer(x.input[1]) is None, all_nodes, diff --git a/src/finn/transformation/fpgadataflow/insert_tlastmarker.py b/src/finn/transformation/fpgadataflow/insert_tlastmarker.py index ab5142e4d8..fbb64428aa 100644 --- a/src/finn/transformation/fpgadataflow/insert_tlastmarker.py +++ b/src/finn/transformation/fpgadataflow/insert_tlastmarker.py @@ -103,7 +103,7 @@ def apply(self, model): # the input is in the list of graph inputs because it has an # initializer (TODO: fix this with a clean-up transform) if ( - getCustomOp(first_node).base_op_type() == "MatrixVectorActivation" + first_node.op_type.startswith("MatrixVectorActivation") and get_by_name(first_node.attribute, "mem_mode").s.decode("UTF-8") != "external" ): @@ -117,7 +117,7 @@ def apply(self, model): num_iters = np.prod(custom_op.get_folded_input_shape()[1:-1]) inp_idx = list(first_node.input).index(graph_in_name) if inp_idx > 0: - if getCustomOp(first_node).base_op_type() == "MatrixVectorActivation" and inp_idx == 1: + if first_node.op_type.startswith("MatrixVectorActivation") and inp_idx == 1: stream_width = int(custom_op.get_weightstream_width()) elif first_node.op_type == "AddStreams_Batch" and inp_idx == 1: stream_width = int(custom_op.get_instream_width()) diff --git a/src/finn/transformation/fpgadataflow/make_pynq_driver.py b/src/finn/transformation/fpgadataflow/make_pynq_driver.py index e66236bf39..9a5317e588 100644 --- a/src/finn/transformation/fpgadataflow/make_pynq_driver.py +++ b/src/finn/transformation/fpgadataflow/make_pynq_driver.py @@ -282,7 +282,9 @@ def apply(self, model): dataflow_model = ModelWrapper(dataflow_model_filename) rt_layer_ind = 0 for node in dataflow_model.graph.node: - if getCustomOp(node).base_op_type() == "MatrixVectorActivation" or node.op_type == "Thresholding_Batch": + if node.op_type.startswith("MatrixVectorActivation") or node.op_type.startswith( + "Thresholding" + ): node_inst = getCustomOp(node) is_rt_weights = node_inst.get_nodeattr("runtime_writeable_weights") if is_rt_weights == 1: diff --git a/src/finn/transformation/fpgadataflow/make_zynq_proj.py b/src/finn/transformation/fpgadataflow/make_zynq_proj.py index 193e6e8b42..2f58064f11 100644 --- a/src/finn/transformation/fpgadataflow/make_zynq_proj.py +++ b/src/finn/transformation/fpgadataflow/make_zynq_proj.py @@ -62,7 +62,9 @@ def collect_ip_dirs(model, ipstitch_path): ), """The directory that should contain the generated ip blocks doesn't exist.""" ip_dirs += [ip_dir_value] - if getCustomOp(node).base_op_type() == "MatrixVectorActivation" or node.op_type == "Thresholding_Batch": + if node.op_type.startswith("MatrixVectorActivation") or node.op_type.startswith( + "Thresholding" + ): if node_inst.get_nodeattr("mem_mode") == "decoupled": need_memstreamer = True ip_dirs += [ipstitch_path + "/ip"] diff --git a/src/finn/transformation/fpgadataflow/set_fifo_depths.py b/src/finn/transformation/fpgadataflow/set_fifo_depths.py index 84a8084832..f2aefc25dd 100644 --- a/src/finn/transformation/fpgadataflow/set_fifo_depths.py +++ b/src/finn/transformation/fpgadataflow/set_fifo_depths.py @@ -174,7 +174,7 @@ def apply(self, model): continue if fifo_cons is None: continue - if getCustomOp(fifo_cons).base_op_type() != "MatrixVectorActivation": + if not fifo_cons.op_type.startswith("MatrixVectorActivation"): continue op_inst = getCustomOp(node) depth = op_inst.get_nodeattr("depth") @@ -257,7 +257,7 @@ def __init__( def apply(self, model): # these optypes may potentially use external weights # we'll temporarily change them to use decoupled mode for FIFO sizing - extw_optypes = ["MatrixVectorActivation", "VectorVectorActivation"] + extw_optypes = ["MatrixVectorActivation_hls", "VectorVectorActivation_hls"] # change external to decoupled and warn user # this way we are sure we have exactly one input/output modified_fc_nodes = [] @@ -281,7 +281,7 @@ def apply(self, model): node.set_nodeattr("inFIFODepths", ifd) node.set_nodeattr("outFIFODepths", ofd) - if getCustomOp(node).base_op_type() in extw_optypes: + if node.op_type in extw_optypes: mmode = node.get_nodeattr("mem_mode") if mmode == "external": modified_fc_nodes.append(node.onnx_node.name) @@ -422,7 +422,7 @@ def apply(self, model): # (removed setting of node FIFO size attributes to 0 here) # for every extw node we changed from external to decoupled, # change back and reset implementation - if getCustomOp(node).base_op_type() in extw_optypes: + if node.op_type in extw_optypes: if node.name in modified_fc_nodes: node_inst = getCustomOp(node) node_inst.set_nodeattr("mem_mode", "external") diff --git a/src/finn/transformation/fpgadataflow/set_folding.py b/src/finn/transformation/fpgadataflow/set_folding.py index 7b65023abc..62457f164a 100644 --- a/src/finn/transformation/fpgadataflow/set_folding.py +++ b/src/finn/transformation/fpgadataflow/set_folding.py @@ -125,7 +125,7 @@ def apply(self, model): continue op_type = node.op_type node_inst = getCustomOp(node) - if node_inst.base_op_type() == "MatrixVectorActivation": + if op_type.startswith("MatrixVectorActivation"): max_simd = node_inst.get_nodeattr("MW") max_pe = node_inst.get_nodeattr("MH") node_inst.set_nodeattr("PE", 1) diff --git a/tests/fpgadataflow/test_fpgadataflow_mvau.py b/tests/fpgadataflow/test_fpgadataflow_mvau.py index 38f77e3836..7e632b4018 100644 --- a/tests/fpgadataflow/test_fpgadataflow_mvau.py +++ b/tests/fpgadataflow/test_fpgadataflow_mvau.py @@ -52,8 +52,6 @@ from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode -from qonnx.transformation.general import ApplyConfig, GiveUniqueNodeNames, GiveReadableTensorNames -from qonnx.transformation.infer_shapes import InferShapes from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers @@ -401,15 +399,9 @@ def test_fpgadataflow_fclayer_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): assert (y_produced.reshape(y_expected.shape) == y_expected).all(), "rtlsim failed" hls_synt_res_est = model.analysis(hls_synth_res_estimation) - assert "MatrixVectorActivation_hls_0" in hls_synt_res_est - assert "MatrixVectorActivation_hls_0" in hls_synt_res_est - else: - assert "MatrixVectorActivation_rtl_0" in hls_synt_res_est assert "MatrixVectorActivation_hls_0" in hls_synt_res_est - else: - assert "MatrixVectorActivation_rtl_0" in hls_synt_res_est - node = model.get_nodes_by_op_type("MatrixVectorActivation")[0] + node = model.get_nodes_by_op_type("MatrixVectorActivation_hls")[0] inst = getCustomOp(node) cycles_rtlsim = inst.get_nodeattr("cycles_rtlsim") exp_cycles_dict = model.analysis(exp_cycles_per_layer) From 6986a8bbac59eec16f73275beaaefd4e492d8862 Mon Sep 17 00:00:00 2001 From: johnnoel Date: Wed, 7 Feb 2024 10:49:55 +0000 Subject: [PATCH 476/665] [Tests] Disable lfc on Alveo and apply fix to driver_base --- src/finn/qnn-data/templates/driver/driver_base.py | 8 +++++--- tests/end2end/test_end2end_bnn_pynq.py | 6 ++++++ 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/src/finn/qnn-data/templates/driver/driver_base.py b/src/finn/qnn-data/templates/driver/driver_base.py index b73bba3121..aa54f84733 100644 --- a/src/finn/qnn-data/templates/driver/driver_base.py +++ b/src/finn/qnn-data/templates/driver/driver_base.py @@ -198,9 +198,11 @@ def load_runtime_weights(self, flush_accel=True, verify=True): # from a tinynumpy.ndarray to numpy.ndarray. To work around this, we first # convert the tinynumpy.ndarray to a list and then copy the list to a # numpy.ndarray. - new_w = np.copy( - list(layer_mmio.array[: layer_w.shape[0]]), dtype=layer_w.dtype - ) + # There is a known bug with larger sets of weights. Accesses to address + # spaces over 16KB do NOT work as intended. Be aware of this if seeing + # unexpected behaviour. + new_array = layer_mmio.array[: layer_w.shape[0]] + new_w = np.copy(np.array(([x for x in new_array]), dtype=layer_w.dtype)) else: new_w = np.copy(layer_mmio.array[: layer_w.shape[0]]) assert (layer_w == new_w).all() diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index db065fec42..46eb9a6744 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -450,6 +450,12 @@ def pytest_generate_tests(metafunc): @pytest.mark.bnn_u250 class TestEnd2End: def test_export(self, topology, wbits, abits, board): + build_data = get_build_env(board, target_clk_ns) + if topology == "lfc" and build_data["kind"] == "alveo": + # There is a known Pynq/XRT issue with larger sets of weights on Alveo. + # Accesses to address spaces over 16KB do NOT work as intended. + # Disabling Alveo lfc until resolved. + pytest.skip("Currently not testing lfc on Alveo due to pynq driver issues") if wbits > abits: pytest.skip("No wbits > abits end2end network configs for now") if topology == "lfc" and not (wbits == 1 and abits == 1): From 1ee77b7725e8242b470364fac401302e69fa9d13 Mon Sep 17 00:00:00 2001 From: johnnoel Date: Wed, 7 Feb 2024 14:01:47 +0000 Subject: [PATCH 477/665] [Tests] Only disable lfc test for alveo during HW testing --- docker/jenkins/test_bnn_hw_pytest.py | 5 +++++ tests/end2end/test_end2end_bnn_pynq.py | 6 ------ 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/docker/jenkins/test_bnn_hw_pytest.py b/docker/jenkins/test_bnn_hw_pytest.py index c8f4fbf74d..dc350d8504 100755 --- a/docker/jenkins/test_bnn_hw_pytest.py +++ b/docker/jenkins/test_bnn_hw_pytest.py @@ -87,6 +87,11 @@ def pytest_generate_tests(metafunc): if len(scenarios) > 0: for scenario in scenarios: + # There is a known Pynq/XRT issue with larger sets of weights on Alveo. + # Accesses to address spaces over 16KB do NOT work as intended. + # Disabling Alveo lfc HW test until resolved. + if scenario[0] == "U250_bnn_w1_a1_lfc_batchSize-1_platform-alveo": + continue idlist.append(scenario[0]) items = scenario[1].items() argnames = [x[0] for x in items] diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index 46eb9a6744..db065fec42 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -450,12 +450,6 @@ def pytest_generate_tests(metafunc): @pytest.mark.bnn_u250 class TestEnd2End: def test_export(self, topology, wbits, abits, board): - build_data = get_build_env(board, target_clk_ns) - if topology == "lfc" and build_data["kind"] == "alveo": - # There is a known Pynq/XRT issue with larger sets of weights on Alveo. - # Accesses to address spaces over 16KB do NOT work as intended. - # Disabling Alveo lfc until resolved. - pytest.skip("Currently not testing lfc on Alveo due to pynq driver issues") if wbits > abits: pytest.skip("No wbits > abits end2end network configs for now") if topology == "lfc" and not (wbits == 1 and abits == 1): From 05881df6baad3b0dc1bbc683c446830a7a5c6101 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 7 Feb 2024 15:30:22 +0000 Subject: [PATCH 478/665] [Util] Introduce new functions to check if node is hls or rtl --- .../custom_op/fpgadataflow/hlscustomop.py | 868 ------------------ .../fpgadataflow/compile_cppsim.py | 7 +- .../fpgadataflow/hlssynth_ip.py | 9 +- .../fpgadataflow/prepare_cppsim.py | 7 +- .../fpgadataflow/set_exec_mode.py | 18 +- src/finn/util/fpgadataflow.py | 28 + 6 files changed, 54 insertions(+), 883 deletions(-) delete mode 100644 src/finn/custom_op/fpgadataflow/hlscustomop.py diff --git a/src/finn/custom_op/fpgadataflow/hlscustomop.py b/src/finn/custom_op/fpgadataflow/hlscustomop.py deleted file mode 100644 index 4fed8ed4b5..0000000000 --- a/src/finn/custom_op/fpgadataflow/hlscustomop.py +++ /dev/null @@ -1,868 +0,0 @@ -# Copyright (c) 2020, Xilinx -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# * Redistributions of source code must retain the above copyright notice, this -# list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# * Neither the name of FINN nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -import numpy as np -import os -import subprocess -import warnings -from abc import abstractmethod -from pyverilator.util.axi_utils import _read_signal, reset_rtlsim, rtlsim_multi_io -from qonnx.core.datatype import DataType -from qonnx.custom_op.base import CustomOp -from qonnx.util.basic import roundup_to_integer_multiple - -from finn.util.basic import ( - CppBuilder, - get_rtlsim_trace_depth, - make_build_dir, - pyverilate_get_liveness_threshold_cycles, -) -from finn.util.hls import CallHLS -from finn.util.pyverilator import make_single_source_file - -from . import templates - -try: - from pyverilator import PyVerilator -except ModuleNotFoundError: - PyVerilator = None - - -class HLSCustomOp(CustomOp): - """HLSCustomOp class all custom ops that correspond to a finn-hlslib - function are based on. Contains different functions every fpgadataflow - custom node should have. Some as abstract methods, these have to be filled - when writing a new fpgadataflow custom op node.""" - - def __init__(self, onnx_node, **kwargs): - super().__init__(onnx_node, **kwargs) - - self.code_gen_dict = {} - - # getting templates from templates.py - - # template for single node execution - self.docompute_template = templates.docompute_template - - # templates for single node ip generation - # cpp file - self.ipgen_template = templates.ipgen_template - # tcl script - self.ipgentcl_template = templates.ipgentcl_template - - def get_nodeattr_types(self): - return { - "backend": ("s", True, "fpgadataflow"), - "code_gen_dir_cppsim": ("s", False, ""), - "code_gen_dir_ipgen": ("s", False, ""), - "executable_path": ("s", False, ""), - "ipgen_path": ("s", False, ""), - "ip_path": ("s", False, ""), - "ip_vlnv": ("s", False, ""), - "exec_mode": ("s", False, "", {"", "rtlsim", "cppsim"}), - "cycles_rtlsim": ("i", False, 0), - "cycles_estimate": ("i", False, 0), - "rtlsim_trace": ("s", False, ""), - "res_estimate": ("s", False, ""), - "res_hls": ("s", False, ""), - "res_synth": ("s", False, ""), - "rtlsim_so": ("s", False, ""), - # partitioning info - # ID of SLR to which the Op is attached in Vitis builds - # Set to -1 as 'don't care' - "slr": ("i", False, -1), - # Vitis memory port to which any AXI-MM interface - # of this Op should be attached in Vitis builds - # E.g.: "DDR[0]", "HBM[0]", "PLRAM[0]" - "mem_port": ("s", False, ""), - # Partition to which the Op belongs; all Ops with the - # same partition_id are stitched together - # Users should avoid setting this attribute manually - # and instead use the floorplan transform to set - # partition IDs from Vitis design rules and SLR IDs - "partition_id": ("i", False, 0), - # ID of FPGA device to which this Op is allocated, in - # a multi-FPGA setting - "device_id": ("i", False, 0), - # input and output FIFO depths for multi-I/O nodes - "inFIFODepths": ("ints", False, [2]), - "outFIFODepths": ("ints", False, [2]), - "output_hook": ("s", False, ""), - # accumulated characteristic function over two periods - "io_chrc_in": ("t", False, np.asarray([], dtype=np.int32)), - "io_chrc_out": ("t", False, np.asarray([], dtype=np.int32)), - # the period for which the characterization was run - "io_chrc_period": ("i", False, 0), - # amount of zero padding inserted during chrc. - "io_chrc_pads_in": ("ints", False, []), - "io_chrc_pads_out": ("ints", False, []), - } - - def get_verilog_top_module_name(self): - "Return the Verilog top module name for this node." - - node = self.onnx_node - prefixed_top_name = node.name - - return prefixed_top_name - - def get_verilog_top_module_intf_names(self): - """Return a dict of names of input and output interfaces. - The keys reflect the protocols each interface implements: - 'clk', 'rst', 'm_axis', 's_axis', 'aximm', 'axilite'. - Values are lists of tuples (axis, aximm) or names (axilite): - 'axis' tuples correspond to the list of node inputs in order, - each tuple is (interface_name, interface_width_bits). - axilite always assumed to be 32 bits and is not tuple (name only). - Each block must have at most one aximm and one axilite.""" - intf_names = {} - intf_names["clk"] = ["ap_clk"] - intf_names["rst"] = ["ap_rst_n"] - sname = self.hls_sname() - intf_names["s_axis"] = [("in0_" + sname, self.get_instream_width_padded())] - intf_names["m_axis"] = [("out_" + sname, self.get_outstream_width_padded())] - intf_names["aximm"] = [] - intf_names["axilite"] = [] - intf_names["ap_none"] = [] - return intf_names - - def get_verilog_top_filename(self): - "Return the Verilog top module filename for this node." - - verilog_file = "{}/project_{}/sol1/impl/verilog/{}.v".format( - self.get_nodeattr("code_gen_dir_ipgen"), - self.onnx_node.name, - self.get_verilog_top_module_name(), - ) - return verilog_file - - def get_all_verilog_paths(self): - "Return list of all folders containing Verilog code for this node." - - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - assert ( - code_gen_dir != "" - ), """Node attribute "code_gen_dir_ipgen" is - not set. Please run HLSSynthIP first.""" - verilog_path = "{}/project_{}/sol1/impl/verilog/".format(code_gen_dir, self.onnx_node.name) - # default impl only returns the HLS verilog codegen dir - return [verilog_path] - - def get_all_verilog_filenames(self, abspath=False): - "Return list of all Verilog files used for this node." - - verilog_files = [] - verilog_paths = self.get_all_verilog_paths() - for verilog_path in verilog_paths: - for f in os.listdir(verilog_path): - if f.endswith(".v"): - if abspath: - verilog_files += [verilog_path + "/" + f] - else: - verilog_files += [f] - return verilog_files - - def prepare_rtlsim(self): - """Creates a Verilator emulation library for the RTL code generated - for this node, sets the rtlsim_so attribute to its path and returns - a PyVerilator wrapper around it.""" - - if PyVerilator is None: - raise ImportError("Installation of PyVerilator is required.") - - verilog_files = self.get_all_verilog_filenames(abspath=True) - single_src_dir = make_build_dir("rtlsim_" + self.onnx_node.name + "_") - tmp_build_dir = make_build_dir("pyverilator_" + self.onnx_node.name + "_") - target_file = single_src_dir + "/" + self.get_verilog_top_module_name() + ".v" - make_single_source_file(verilog_files, target_file) - - # build the Verilator emu library - sim = PyVerilator.build( - self.get_verilog_top_module_name() + ".v", - build_dir=tmp_build_dir, - verilog_path=[single_src_dir], - trace_depth=get_rtlsim_trace_depth(), - top_module_name=self.get_verilog_top_module_name(), - ) - # save generated lib filename in attribute - self.set_nodeattr("rtlsim_so", sim.lib._name) - return sim - - def get_rtlsim(self): - """Return a PyVerilator wrapper for the Verilator emulation library - for this node.""" - - rtlsim_so = self.get_nodeattr("rtlsim_so") - assert os.path.isfile(rtlsim_so), "Cannot find rtlsim library." - # create PyVerilator wrapper - sim = PyVerilator(rtlsim_so) - return sim - - def node_res_estimation(self): - """Returns summarized resource estimation of BRAMs and LUTs - of the node as a dictionary.""" - ret = dict() - ret["BRAM_18K"] = self.bram_estimation() - ret["BRAM_efficiency"] = self.bram_efficiency_estimation() - ret["LUT"] = self.lut_estimation() - ret["URAM"] = self.uram_estimation() - ret["URAM_efficiency"] = self.uram_efficiency_estimation() - ret["DSP"] = self.dsp_estimation() - return ret - - def bram_efficiency_estimation(self): - """Function for BRAM efficiency estimation: actual parameter storage - needed divided by the allocated BRAM storage (from estimation)""" - return 1 - - def uram_efficiency_estimation(self): - """Function for URAM efficiency estimation: actual parameter storage - needed divided by the allocated URAM storage (from estimation)""" - return 1 - - def bram_estimation(self): - """Function for BRAM resource estimation, is member function of - HLSCustomOp class but has to be filled by every node""" - return 0 - - def uram_estimation(self): - """Function for UltraRAM resource estimation, is member function of - HLSCustomOp class but has to be filled by every node""" - return 0 - - def lut_estimation(self): - """Function for LUT resource estimation, is member function of - HLSCustomOp class but has to be filled by every node""" - return 0 - - def dsp_estimation(self): - """Function for DSP resource estimation, is member function of - HLSCustomOp class but has to be filled by every node""" - return 0 - - def get_exp_cycles(self): - """Function for estimation of expected cycles for set folding, - is member function of HLSCustomOp class but has to be filled - by every node""" - return 0 - - def get_op_and_param_counts(self): - """Return a dictionary with number of ops needed per inference for - this layer as well as parameter count (weights, thresholds, etc.). - Entries should be in the format: - {op_ : , param_: }.""" - return {} - - def code_generation_ipgen(self, model, fpgapart, clk): - """Generates c++ code and tcl script for ip generation.""" - node = self.onnx_node - - # generate top cpp file for ip generation - path = self.get_nodeattr("code_gen_dir_ipgen") - self.code_gen_dict["$AP_INT_MAX_W$"] = [str(self.get_ap_int_max_w())] - self.generate_params(model, path) - self.global_includes() - self.defines("ipgen") - self.blackboxfunction() - self.pragmas() - self.docompute() - - template = self.ipgen_template - - for key in self.code_gen_dict: - # transform list into long string separated by '\n' - code_gen_line = "\n".join(self.code_gen_dict[key]) - template = template.replace(key, code_gen_line) - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - f = open(os.path.join(code_gen_dir, "top_{}.cpp".format(node.name)), "w") - f.write(template) - f.close() - self.code_gen_dict.clear() - - # generate tcl script for ip generation - self.code_gen_dict["$PROJECTNAME$"] = ["project_{}".format(node.name)] - self.code_gen_dict["$HWSRCDIR$"] = [code_gen_dir] - self.code_gen_dict["$FPGAPART$"] = [fpgapart] - self.code_gen_dict["$TOPFXN$"] = [node.name] - self.code_gen_dict["$CLKPERIOD$"] = [str(clk)] - self.code_gen_dict["$DEFAULT_DIRECTIVES$"] = self.ipgen_default_directives() - self.code_gen_dict["$EXTRA_DIRECTIVES$"] = self.ipgen_extra_directives() - - template = self.ipgentcl_template - - for key in self.code_gen_dict: - # transform list into long string separated by '\n' - code_gen_line = "\n".join(self.code_gen_dict[key]) - template = template.replace(key, code_gen_line) - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - f = open(os.path.join(code_gen_dir, "hls_syn_{}.tcl".format(node.name)), "w") - f.write(template) - f.close() - self.code_gen_dict.clear() - - def ipgen_default_directives(self): - """Return list of default HLS synthesis directives""" - - default_directives = [ - "set_param hls.enable_hidden_option_error false", - "config_compile -disable_unroll_code_size_check -pipeline_style flp", - "config_interface -m_axi_addr64", - "config_rtl -module_auto_prefix", - "config_rtl -deadlock_detection none", - ] - return default_directives - - def ipgen_extra_directives(self): - "Return a list of extra tcl directives for HLS synthesis." - return [] - - def ipgen_singlenode_code(self): - """Builds the bash script for IP generation using the CallHLS utility.""" - node = self.onnx_node - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - builder = CallHLS() - builder.append_tcl(code_gen_dir + "/hls_syn_{}.tcl".format(node.name)) - builder.set_ipgen_path(code_gen_dir + "/project_{}".format(node.name)) - builder.build(code_gen_dir) - ipgen_path = builder.ipgen_path - assert os.path.isdir(ipgen_path), "IPGen failed: %s not found" % (ipgen_path) - self.set_nodeattr("ipgen_path", ipgen_path) - ip_path = ipgen_path + "/sol1/impl/ip" - assert os.path.isdir(ip_path), "IPGen failed: %s not found. Check log under %s" % ( - ip_path, - code_gen_dir, - ) - self.set_nodeattr("ip_path", ip_path) - vlnv = "xilinx.com:hls:%s:1.0" % node.name - self.set_nodeattr("ip_vlnv", vlnv) - - def code_generation_cppsim(self, model): - """Generates c++ code for simulation (cppsim).""" - node = self.onnx_node - path = self.get_nodeattr("code_gen_dir_cppsim") - self.code_gen_dict["$AP_INT_MAX_W$"] = [str(self.get_ap_int_max_w())] - self.generate_params(model, path) - self.global_includes() - self.defines("cppsim") - self.read_npy_data() - self.strm_decl() - self.pragmas() - self.docompute() - self.dataoutstrm() - self.save_as_npy() - - template = self.docompute_template - - for key in self.code_gen_dict: - # transform list into long string separated by '\n' - code_gen_line = "\n".join(self.code_gen_dict[key]) - template = template.replace(key, code_gen_line) - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - f = open(os.path.join(code_gen_dir, "execute_{}.cpp".format(node.op_type)), "w") - f.write(template) - f.close() - self.code_gen_dict.clear() - - def code_generation_ipi(self): - """Constructs and returns the TCL for node instantiation in Vivado IPI.""" - vlnv = self.get_nodeattr("ip_vlnv") - cmd = ["create_bd_cell -type ip -vlnv %s %s" % (vlnv, self.onnx_node.name)] - return cmd - - def compile_singlenode_code(self): - """Builds the bash script for compilation using the CppBuilder from - finn.util.basic and executes the script to produce the executable.""" - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - builder = CppBuilder() - # to enable additional debug features please uncommand the next line - # builder.append_includes("-DDEBUG") - builder.append_includes("-I$FINN_ROOT/src/finn/qnn-data/cpp") - builder.append_includes("-I$FINN_ROOT/deps/cnpy/") - builder.append_includes("-I$FINN_ROOT/deps/finn-hlslib") - builder.append_includes("-I$FINN_ROOT/custom_hls") - builder.append_includes("-I{}/include".format(os.environ["HLS_PATH"])) - builder.append_includes("--std=c++14") - builder.append_includes("-O3") - builder.append_sources(code_gen_dir + "/*.cpp") - builder.append_sources("$FINN_ROOT/deps/cnpy/cnpy.cpp") - builder.append_includes("-lz") - builder.set_executable_path(code_gen_dir + "/node_model") - builder.build(code_gen_dir) - self.set_nodeattr("executable_path", builder.executable_path) - - def dynamic_input_to_npy(self, context, count, target_dir=""): - """Saves input (given context) into .npy files. - - Count indicates the number of inputs that have to be saved.""" - node = self.onnx_node - if target_dir == "": - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - if code_gen_dir == "": - raise Exception( - """ - Found no codegen dir for this node, did you run the prepare_cppsim transformation? - """ - ) - target_dir = code_gen_dir - # create a npy file for each input of the node (in_ind is input index) - # assuming dynamic inputs start from 0 - for in_ind in range(count): - current_input_name = node.input[in_ind] - input_array = context[current_input_name] - if in_ind == 0: - expected_inp_shape = self.get_folded_input_shape() - idt = self.get_input_datatype() - else: - expected_inp_shape = self.get_folded_input_shape(in_ind) - idt = self.get_input_datatype(in_ind) - reshaped_input = input_array.reshape(expected_inp_shape) - if idt == DataType["BIPOLAR"]: - # store bipolar activations as binary - reshaped_input = (reshaped_input + 1) / 2 - # make copy before saving the array - reshaped_input = reshaped_input.copy() - np.save( - os.path.join(target_dir, "input_{}.npy".format(in_ind)), - reshaped_input, - ) - - def npy_to_dynamic_output(self, context): - """Reads the output from an output.npy file generated from cppsim and - places its content into the context dictionary.""" - node = self.onnx_node - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - output = np.load("{}/output.npy".format(code_gen_dir)) - exp_shape = self.get_normal_output_shape() - context[node.output[0]] = output.reshape(exp_shape) - - def npy_to_dynamic_outputs(self, context, npy_list): - """Reads the output from .npy files generated from cppsim and places - their content into the context dictionary. - npy_list is a list specifying which files to read, and its order must - match the order of node outputs.""" - node = self.onnx_node - code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") - for i in range(len(npy_list)): - output = np.load("{}/{}".format(code_gen_dir, npy_list[i])) - if i == 0: - exp_shape = self.get_normal_output_shape() - else: - exp_shape = self.get_normal_output_shape(i) - context[node.output[i]] = output.reshape(exp_shape) - - def exec_precompiled_singlenode_model(self): - """Executes precompiled executable.""" - executable_path = self.get_nodeattr("executable_path") - if executable_path == "": - raise Exception( - """ -Found no executable for this node, did you run the codegen and -compilation transformations? - """ - ) - process_execute = subprocess.Popen(executable_path, stdout=subprocess.PIPE) - process_execute.communicate() - - def reset_rtlsim(self, sim): - """Sets reset input in pyverilator to zero, toggles the clock and set it - back to one""" - sim.io.ap_rst_n = 0 - sim.io.ap_clk = 1 - sim.io.ap_clk = 0 - sim.io.ap_rst_n = 1 - - def toggle_clk(self, sim): - """Toggles the clock input in pyverilator once.""" - sim.io.ap_clk = 1 - sim.io.ap_clk = 0 - - def hls_sname(self): - """Get the naming convention used by Vitis HLS for stream signals - Example: the TDATA for a stream called "out" would be out_V_TDATA. - """ - return "V" - - def rtlsim(self, sim, inp, inp2=None): - """Runs the pyverilator simulation by passing the input values to the simulation, - toggle the clock and observing the execution time. Function contains also an - observation loop that can abort the simulation if no output value is produced - after 100 cycles.""" - - trace_file = self.get_nodeattr("rtlsim_trace") - if trace_file != "": - if trace_file == "default": - trace_file = self.onnx_node.name + ".vcd" - sim.start_vcd_trace(trace_file) - inputs = inp - outputs = [] - sname = self.hls_sname() - o_ready = "out_" + sname + "_TREADY" - o_valid = "out_" + sname + "_TVALID" - o_data = "out_" + sname + "_TDATA" - in0_ready = "in0_" + sname + "_TREADY" - in0_valid = "in0_" + sname + "_TVALID" - in0_data = "in0_" + sname + "_TDATA" - in1_ready = "in1_" + sname + "_TREADY" - in1_valid = "in1_" + sname + "_TVALID" - in1_data = "in1_" + sname + "_TDATA" - - sim.io[o_ready] = 1 - - # observe if output is completely calculated - # observation_count will contain the number of cycles the calculation ran - num_out_values = self.get_number_output_values() - output_observed = False - observation_count = 0 - - # avoid infinite looping of simulation by aborting when there is no change in - # output values after 100 cycles - no_change_count = 0 - old_outputs = outputs - liveness_threshold = pyverilate_get_liveness_threshold_cycles() - - while not (output_observed): - sim.io[in0_valid] = 1 if len(inputs) > 0 else 0 - sim.io[in0_data] = inputs[0] if len(inputs) > 0 else 0 - if sim.io[in0_ready] == 1 and sim.io[in0_valid] == 1: - inputs = inputs[1:] - - if inp2 is not None: - sim.io[in1_valid] = 1 if len(inp2) > 0 else 0 - sim.io[in1_data] = inp2[0] if len(inp2) > 0 else 0 - if sim.io[in1_ready] == 1 and sim.io[in1_valid] == 1: - inp2 = inp2[1:] - - if sim.io[o_valid] == 1 and sim.io[o_ready] == 1: - outputs = outputs + [sim.io[o_data]] - sim.io.ap_clk = 1 - sim.io.ap_clk = 0 - - observation_count = observation_count + 1 - no_change_count = no_change_count + 1 - - if len(outputs) == num_out_values: - self.set_nodeattr("cycles_rtlsim", observation_count) - output_observed = True - - if no_change_count == liveness_threshold: - if old_outputs == outputs: - if trace_file != "": - sim.flush_vcd_trace() - sim.stop_vcd_trace() - raise Exception( - "Error in simulation! Takes too long to produce output. " - "Consider setting the LIVENESS_THRESHOLD env.var. to a " - "larger value." - ) - else: - no_change_count = 0 - old_outputs = outputs - if trace_file != "": - sim.flush_vcd_trace() - sim.stop_vcd_trace() - return outputs - - def rtlsim_multi_io(self, sim, io_dict): - "Run rtlsim for this node, supports multiple i/o streams." - - # signal name - sname = "_" + self.hls_sname() + "_" - - trace_file = self.get_nodeattr("rtlsim_trace") - if trace_file == "default": - trace_file = self.onnx_node.name + ".vcd" - num_out_values = self.get_number_output_values() - total_cycle_count = rtlsim_multi_io( - sim, - io_dict, - num_out_values, - trace_file=trace_file, - sname=sname, - liveness_threshold=pyverilate_get_liveness_threshold_cycles(), - ) - self.set_nodeattr("cycles_rtlsim", total_cycle_count) - - def execute_node(self, context, graph): - """Executes single node using cppsim or rtlsim.""" - mode = self.get_nodeattr("exec_mode") - if mode == "cppsim": - # save input(s) - self.dynamic_input_to_npy(context, 1) - # execute the precompiled model - self.exec_precompiled_singlenode_model() - # load output npy file - self.npy_to_dynamic_output(context) - elif mode == "rtlsim": - pass - - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to one of the following value ("cppsim", "rtlsim")""".format( - mode - ) - ) - - def generate_params(self, model, path): - """Function to generate parameters (i.e. weights and thresholds), - is member function of HLSCustomOp class but has to be filled - by every node.""" - pass - - @abstractmethod - def get_number_output_values(self): - """Function to get the number of expected output values, - is member function of HLSCustomOp class but has to be filled - by every node.""" - pass - - @abstractmethod - def global_includes(self): - """Function to set the global includes for c++ code that has to be generated - for cppsim or rtlsim, is member function of HLSCustomOp class but has to - be filled by every node.""" - pass - - @abstractmethod - def defines(self, var): - """Function to set the define commands for c++ code that has to be generated - for cppsim or rtlsim, is member function of HLSCustomOp class but has to - be filled by every node. - - var: makes it possible to reuse the function for different c++ code generation. - I.e. if set to "ipgen" in MatrixVectorActivation additional PRAGMA defines are - added.""" - pass - - @abstractmethod - def read_npy_data(self): - """Function to generate the commands for reading data from .npy file in c++, - is member function of HLSCustomOp class but has to be filled by every node.""" - pass - - @abstractmethod - def strm_decl(self): - """Function to generate the commands for the stream declaration in c++, - is member function of HLSCustomOp class but has to be filled - by every node.""" - pass - - @abstractmethod - def docompute(self): - """Function to generate the commands for the computational part of the - c++ code, is member function of HLSCustomOp class but has to be filled - by every node.""" - pass - - @abstractmethod - def dataoutstrm(self): - """Function to generate the commands for reading out data from c++ and convert - into npy format, is member function of HLSCustomOp class but has to be filled - by every node.""" - pass - - @abstractmethod - def save_as_npy(self): - """Function to generate the commands for saving data in .npy file in c++, - is member function of HLSCustomOp class but has to be filled by every node.""" - pass - - @abstractmethod - def blackboxfunction(self): - """Function to generate a blackbock function in c++ from which an IP block - will be generated, is member function of HLSCustomOp class but has to be filled - by every node.""" - pass - - @abstractmethod - def pragmas(self): - """Function to generate the pragma commands in c++, is member function of - HLSCustomOp class but has to be filled by every node.""" - pass - - def get_input_datatype(self, ind=0): - """Returns FINN DataType of input stream ind.""" - raise Exception("get_input_datatype not implemented for this op") - - def get_output_datatype(self, ind=0): - """Returns FINN DataType of output stream ind.""" - raise Exception("get_output_datatype not implemented for this op") - - def get_normal_input_shape(self, ind=0): - """Returns normal input shape if implemented.""" - raise Exception("get_normal_input_shape not implemented for this op") - - def get_normal_output_shape(self, ind=0): - """Returns folded output shape if implemented.""" - raise Exception("get_normal_output_shape not implemented for this op") - - def get_folded_input_shape(self, ind=0): - """Returns folded input shape (according to synapse folding), if implemented.""" - raise Exception("get_folded_input_shape not implemented for this op") - - def get_folded_output_shape(self, ind=0): - """Returns folded output shape (according to neuron folding), if implemented.""" - raise Exception("get_folded_output_shape not implemented for this op") - - def get_instream_width(self, ind=0): - """Returns input stream width, if implemented.""" - raise Exception("get_instream_width not implemented for this op") - - def get_outstream_width(self, ind=0): - """Returns output stream width, if implemented.""" - raise Exception("get_outstream_width not implemented for this op") - - def get_instream_width_padded(self, ind=0): - """Returns input stream width padded to a multiple of 8. This is required - by the AXI Stream spec.""" - in_width = self.get_instream_width(ind=ind) - return roundup_to_integer_multiple(in_width, 8) - - def get_outstream_width_padded(self, ind=0): - """Returns output stream width padded to a multiple of 8. This is required - by the AXI Stream spec.""" - out_width = self.get_outstream_width(ind=ind) - return roundup_to_integer_multiple(out_width, 8) - - def get_ap_int_max_w(self): - """Return the maximum width of any ap_int used in this module. Used to set the - AP_INT_MAX_W definition for HLS.""" - instream = self.get_instream_width() - outstream = self.get_outstream_width() - ret = max([instream, outstream]) - assert ret <= 32768, "AP_INT_MAX_W=%d is larger than allowed maximum of 32768" % ret - return ret - - def derive_characteristic_fxns(self, period, override_rtlsim_dict=None): - """Return the unconstrained characteristic functions for this node.""" - # ensure rtlsim is ready - assert self.get_nodeattr("rtlsim_so") != "", "rtlsim not ready for " + self.onnx_node.name - if self.get_nodeattr("io_chrc_period") > 0: - warnings.warn("Skipping node %s: already has FIFO characteristic" % self.onnx_node.name) - return - exp_cycles = self.get_exp_cycles() - n_inps = np.prod(self.get_folded_input_shape()[:-1]) - n_outs = np.prod(self.get_folded_output_shape()[:-1]) - if exp_cycles == 0: - # try to come up with an optimistic estimate - exp_cycles = min(n_inps, n_outs) - assert ( - exp_cycles <= period - ), "Period %d too short to characterize %s : expects min %d cycles" % ( - period, - self.onnx_node.name, - exp_cycles, - ) - sim = self.get_rtlsim() - # signal name - sname = "_" + self.hls_sname() + "_" - if override_rtlsim_dict is not None: - io_dict = override_rtlsim_dict - else: - io_dict = { - "inputs": { - "in0": [0 for i in range(n_inps)], - }, - "outputs": {"out": []}, - } - - # extra dicts to keep track of cycle-by-cycle transaction behavior - # note that we restrict key names to filter out weight streams etc - txns_in = {key: [] for (key, value) in io_dict["inputs"].items() if "in" in key} - txns_out = {key: [] for (key, value) in io_dict["outputs"].items() if "out" in key} - - def monitor_txns(sim_obj): - for inp in txns_in: - in_ready = _read_signal(sim, inp + sname + "TREADY") == 1 - in_valid = _read_signal(sim, inp + sname + "TVALID") == 1 - if in_ready and in_valid: - txns_in[inp].append(1) - else: - txns_in[inp].append(0) - for outp in txns_out: - if ( - _read_signal(sim, outp + sname + "TREADY") == 1 - and _read_signal(sim, outp + sname + "TVALID") == 1 - ): - txns_out[outp].append(1) - else: - txns_out[outp].append(0) - - reset_rtlsim(sim) - total_cycle_count = rtlsim_multi_io( - sim, - io_dict, - n_outs, - sname=sname, - liveness_threshold=period, - hook_preclk=monitor_txns, - ) - assert ( - total_cycle_count <= period - ), """Total cycle count from rtl simulation is higher than - specified period, please set the period higher than {}""".format( - total_cycle_count - ) - self.set_nodeattr("io_chrc_period", period) - - def accumulate_char_fxn(chrc): - p = len(chrc) - ret = [] - for t in range(2 * p): - if t == 0: - ret.append(chrc[0]) - else: - ret.append(ret[-1] + chrc[t % p]) - return np.asarray(ret, dtype=np.int32) - - all_txns_in = np.empty((len(txns_in.keys()), 2 * period), dtype=np.int32) - all_txns_out = np.empty((len(txns_out.keys()), 2 * period), dtype=np.int32) - all_pad_in = [] - all_pad_out = [] - for in_idx, in_strm_nm in enumerate(txns_in.keys()): - txn_in = txns_in[in_strm_nm] - if len(txn_in) < period: - pad_in = period - len(txn_in) - txn_in += [0 for x in range(pad_in)] - txn_in = accumulate_char_fxn(txn_in) - all_txns_in[in_idx, :] = txn_in - all_pad_in.append(pad_in) - - for out_idx, out_strm_nm in enumerate(txns_out.keys()): - txn_out = txns_out[out_strm_nm] - if len(txn_out) < period: - pad_out = period - len(txn_out) - txn_out += [0 for x in range(pad_out)] - txn_out = accumulate_char_fxn(txn_out) - all_txns_out[out_idx, :] = txn_out - all_pad_out.append(pad_out) - - self.set_nodeattr("io_chrc_in", all_txns_in) - self.set_nodeattr("io_chrc_out", all_txns_out) - self.set_nodeattr("io_chrc_pads_in", all_pad_in) - self.set_nodeattr("io_chrc_pads_out", all_pad_out) diff --git a/src/finn/transformation/fpgadataflow/compile_cppsim.py b/src/finn/transformation/fpgadataflow/compile_cppsim.py index e93a8ec307..4814b24a92 100644 --- a/src/finn/transformation/fpgadataflow/compile_cppsim.py +++ b/src/finn/transformation/fpgadataflow/compile_cppsim.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2020, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -29,7 +30,7 @@ import qonnx.custom_op.registry as registry from qonnx.transformation.base import NodeLocalTransformation -from finn.util.fpgadataflow import is_fpgadataflow_node +from finn.util.fpgadataflow import is_fpgadataflow_node, is_hls_node class CompileCppSim(NodeLocalTransformation): @@ -50,7 +51,7 @@ def __init__(self, num_workers=None): def applyNodeLocal(self, node): op_type = node.op_type - if is_fpgadataflow_node(node) is True: + if is_fpgadataflow_node(node) and is_hls_node(node): try: # lookup op_type in registry of CustomOps inst = registry.getCustomOp(node) diff --git a/src/finn/transformation/fpgadataflow/hlssynth_ip.py b/src/finn/transformation/fpgadataflow/hlssynth_ip.py index 08069fa00f..daf64656b5 100644 --- a/src/finn/transformation/fpgadataflow/hlssynth_ip.py +++ b/src/finn/transformation/fpgadataflow/hlssynth_ip.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2020, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -31,7 +32,7 @@ import warnings from qonnx.transformation.base import NodeLocalTransformation -from finn.util.fpgadataflow import is_fpgadataflow_node +from finn.util.fpgadataflow import is_fpgadataflow_node, is_hls_node class HLSSynthIP(NodeLocalTransformation): @@ -42,7 +43,7 @@ class HLSSynthIP(NodeLocalTransformation): Any nodes that already have a ipgen_path attribute pointing to a valid path will be skipped. - This transformation calls Vivado HLS for synthesis, so it will run for + This transformation calls Vitis HLS for synthesis, so it will run for some time (minutes to hours depending on configuration). * num_workers (int or None) number of parallel workers, see documentation in @@ -54,7 +55,7 @@ def __init__(self, num_workers=None): def applyNodeLocal(self, node): op_type = node.op_type - if is_fpgadataflow_node(node) is True: + if is_fpgadataflow_node(node) and is_hls_node(node): try: # lookup op_type in registry of CustomOps inst = registry.getCustomOp(node) diff --git a/src/finn/transformation/fpgadataflow/prepare_cppsim.py b/src/finn/transformation/fpgadataflow/prepare_cppsim.py index 76c3f88310..0b744b5f4f 100644 --- a/src/finn/transformation/fpgadataflow/prepare_cppsim.py +++ b/src/finn/transformation/fpgadataflow/prepare_cppsim.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2020, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -34,7 +35,7 @@ from qonnx.util.basic import get_num_default_workers from finn.util.basic import make_build_dir -from finn.util.fpgadataflow import is_fpgadataflow_node +from finn.util.fpgadataflow import is_fpgadataflow_node, is_hls_node def _codegen_single_node(node, model): @@ -78,7 +79,7 @@ def __init__(self, num_workers=None): self._num_workers = mp.cpu_count() def prepareCppSim_node(self, node): - if is_fpgadataflow_node(node) is True: + if is_fpgadataflow_node(node) and is_hls_node(node): _codegen_single_node(node, self.model) return (node, False) diff --git a/src/finn/transformation/fpgadataflow/set_exec_mode.py b/src/finn/transformation/fpgadataflow/set_exec_mode.py index 8488b4ef83..7df4451a22 100644 --- a/src/finn/transformation/fpgadataflow/set_exec_mode.py +++ b/src/finn/transformation/fpgadataflow/set_exec_mode.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2020, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -29,12 +30,15 @@ import qonnx.custom_op.registry as registry from qonnx.transformation.base import Transformation -from finn.util.fpgadataflow import is_fpgadataflow_node +from finn.util.fpgadataflow import is_fpgadataflow_node, is_rtl_node class SetExecMode(Transformation): """Set attribute exec_mode in all fpgadataflow nodes to specify which - kind of execution should be used ("cppsim" or "rtlsim")""" + kind of execution should be used ("cppsim" or "rtlsim"). + Note that RTL components do not support cppsim. + If cppsim is selected, only HLS components will be set for cppsim, + RTL components default in this case to rtlsim execution mode.""" def __init__(self, mode): super().__init__() @@ -43,12 +47,16 @@ def __init__(self, mode): def apply(self, model): for node in model.graph.node: op_type = node.op_type - if is_fpgadataflow_node(node) is True: + if is_fpgadataflow_node(node): + if self.mode == "cppsim" and is_rtl_node(node): + mode = "rtlsim" + else: + mode = self.mode try: # lookup op_type in registry of CustomOps inst = registry.getCustomOp(node) # set sim_mode accordingly to argument mode - inst.set_nodeattr("exec_mode", self.mode) + inst.set_nodeattr("exec_mode", mode) # ensure that sim_mode is now set assert ( inst.get_nodeattr("exec_mode") != "" diff --git a/src/finn/util/fpgadataflow.py b/src/finn/util/fpgadataflow.py index 769ddb9465..aae438fac2 100644 --- a/src/finn/util/fpgadataflow.py +++ b/src/finn/util/fpgadataflow.py @@ -41,3 +41,31 @@ def is_fpgadataflow_node(node): is_node = True return is_node + + +def is_hls_node(node): + """Returns True if given node is hls node. Otherwise False.""" + is_node = False + if node is not None: + if node.domain == "finn.custom_op.fpgadataflow.hls": + n_backend = get_by_name(node.attribute, "backend") + if n_backend is not None: + backend_value = n_backend.s.decode("UTF-8") + if backend_value == "fpgadataflow": + is_node = True + + return is_node + + +def is_rtl_node(node): + """Returns True if given node is rtl node. Otherwise False.""" + is_node = False + if node is not None: + if node.domain == "finn.custom_op.fpgadataflow.rtl": + n_backend = get_by_name(node.attribute, "backend") + if n_backend is not None: + backend_value = n_backend.s.decode("UTF-8") + if backend_value == "fpgadataflow": + is_node = True + + return is_node From 94a2ff31d4e7e79c77536e97924b58e58f4c6329 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 7 Feb 2024 15:48:13 +0000 Subject: [PATCH 479/665] [Tests] First cleanup over tests to update to new flow --- tests/fpgadataflow/test_code_gen_trafo.py | 7 +- tests/fpgadataflow/test_compilation_trafo.py | 7 +- .../test_convert_to_hls_channelwise_layer.py | 134 ------------------ ...py => test_convert_to_hw_1d_conv_layer.py} | 28 ++-- ... test_convert_to_hw_conv_fc_transition.py} | 25 ++-- tests/fpgadataflow/test_fpgadataflow_vvau.py | 2 +- tests/fpgadataflow/test_runtime_weights.py | 8 +- 7 files changed, 51 insertions(+), 160 deletions(-) delete mode 100644 tests/fpgadataflow/test_convert_to_hls_channelwise_layer.py rename tests/fpgadataflow/{test_convert_to_hls_1d_conv_layer.py => test_convert_to_hw_1d_conv_layer.py} (88%) rename tests/fpgadataflow/{test_convert_to_hls_conv_fc_transition.py => test_convert_to_hw_conv_fc_transition.py} (90%) diff --git a/tests/fpgadataflow/test_code_gen_trafo.py b/tests/fpgadataflow/test_code_gen_trafo.py index f5edabbd4b..709333949e 100644 --- a/tests/fpgadataflow/test_code_gen_trafo.py +++ b/tests/fpgadataflow/test_code_gen_trafo.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2020, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -50,10 +51,10 @@ def test_code_gen_trafo(): outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, [1, mh]) node_inp_list = ["inp", "weights", "thresh"] FCLayer_node = helper.make_node( - "MatrixVectorActivation", + "MatrixVectorActivation_hls", node_inp_list, ["outp"], - domain="finn.custom_op.fpgadataflow", + domain="finn.custom_op.fpgadataflow.hls", backend="fpgadataflow", code_gen_dir="", executable_path="", diff --git a/tests/fpgadataflow/test_compilation_trafo.py b/tests/fpgadataflow/test_compilation_trafo.py index d04b68a56b..1b48df3d4a 100644 --- a/tests/fpgadataflow/test_compilation_trafo.py +++ b/tests/fpgadataflow/test_compilation_trafo.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2020, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -51,10 +52,10 @@ def test_compilation_trafo(): outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, [1, mh]) node_inp_list = ["inp", "weights", "thresh"] FCLayer_node = helper.make_node( - "MatrixVectorActivation", + "MatrixVectorActivation_hls", node_inp_list, ["outp"], - domain="finn.custom_op.fpgadataflow", + domain="finn.custom_op.fpgadataflow.hls", backend="fpgadataflow", code_gen_dir="", executable_path="", diff --git a/tests/fpgadataflow/test_convert_to_hls_channelwise_layer.py b/tests/fpgadataflow/test_convert_to_hls_channelwise_layer.py deleted file mode 100644 index bb2c1d74c2..0000000000 --- a/tests/fpgadataflow/test_convert_to_hls_channelwise_layer.py +++ /dev/null @@ -1,134 +0,0 @@ -# Copyright (c) 2020, Xilinx -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# * Redistributions of source code must retain the above copyright notice, this -# list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# * Neither the name of FINN nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -import pytest - -import numpy as np -from onnx import TensorProto, helper -from qonnx.core.datatype import DataType -from qonnx.core.modelwrapper import ModelWrapper -from qonnx.transformation.general import GiveUniqueNodeNames -from qonnx.transformation.infer_data_layouts import InferDataLayouts -from qonnx.transformation.infer_shapes import InferShapes -from qonnx.util.basic import gen_finn_dt_tensor, qonnx_make_model - -import finn.core.onnx_exec as oxe -import finn.transformation.fpgadataflow.convert_to_hls_layers as to_hls -from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim -from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP -from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim -from finn.transformation.fpgadataflow.prepare_ip import PrepareIP -from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim -from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode - - -def prepare_inputs(input_tensor): - return {"inp": input_tensor} - - -def make_single_maxpool_modelwrapper(onnx_op_name, ishape, idt, pdt, pshape): - inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, ishape) - outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, ishape) - p0 = helper.make_tensor_value_info("p0", TensorProto.FLOAT, pshape) - - model = qonnx_make_model( - helper.make_graph( - name="test", - inputs=[inp], - outputs=[outp], - value_info=[p0], - nodes=[helper.make_node(onnx_op_name, ["inp", "p0"], ["outp"])], - ) - ) - - model = ModelWrapper(model) - model.set_initializer("p0", gen_finn_dt_tensor(pdt, pshape)) - model.set_tensor_datatype("inp", idt) - model.transform(InferDataLayouts(), make_deepcopy=False) - model.transform(InferShapes(), make_deepcopy=False) - return model - - -# parameter datatype -@pytest.mark.parametrize("pdt", [DataType["BIPOLAR"], DataType["UINT4"], DataType["INT2"]]) -# input datatype -@pytest.mark.parametrize("idt", [DataType["INT32"], DataType["UINT4"], DataType["INT4"]]) -# function -@pytest.mark.parametrize("onnx_op_name", ["Add", "Mul"]) -# vector parameter or scalar parameter (broadcast) -@pytest.mark.parametrize("scalar_param", [True, False]) -# execution mode -@pytest.mark.parametrize("exec_mode", ["cppsim", "rtlsim"]) -@pytest.mark.fpgadataflow -@pytest.mark.vivado -@pytest.mark.slow -def test_convert_to_hls_channelwise_layer(pdt, idt, onnx_op_name, scalar_param, exec_mode): - ifm_ch = 16 - ifm_dim = 5 - ishape = (1, ifm_ch, ifm_dim, ifm_dim) - if scalar_param: - pshape = (1,) - else: - pshape = (1, ifm_ch, 1, 1) - - np.random.seed(0) - model = make_single_maxpool_modelwrapper(onnx_op_name, ishape, idt, pdt, pshape) - - # Since the aren't Data types with a bit width of a non power of 2, - # there are cases where the input won't use it full range. - if idt == DataType["INT32"]: - x = gen_finn_dt_tensor(DataType["INT16"], (1, ifm_ch, ifm_dim, ifm_dim)) - elif idt == DataType["UINT32"]: - x = gen_finn_dt_tensor(DataType["UINT16"], (1, ifm_ch, ifm_dim, ifm_dim)) - else: - x = gen_finn_dt_tensor(idt, (1, ifm_ch, ifm_dim, ifm_dim)) - - input_dict = prepare_inputs(x) - y_expected = oxe.execute_onnx(model, input_dict)["outp"] - - new_model = model.transform(to_hls.InferChannelwiseLinearLayer()) - new_model = new_model.transform(GiveUniqueNodeNames()) - - if exec_mode == "cppsim": - new_model = new_model.transform(PrepareCppSim()) - new_model = new_model.transform(CompileCppSim()) - new_model = new_model.transform(SetExecMode("cppsim")) - elif exec_mode == "rtlsim": - new_model = new_model.transform(SetExecMode("rtlsim")) - new_model = new_model.transform(GiveUniqueNodeNames()) - new_model = new_model.transform(PrepareIP("xc7z020clg400-1", 5)) - new_model = new_model.transform(HLSSynthIP()) - new_model = new_model.transform(PrepareRTLSim()) - else: - raise Exception("Unknown exec_mode") - - ctx_produced = oxe.execute_onnx(new_model, input_dict, return_full_exec_context=True) - y_produced = ctx_produced["outp"] - - assert (y_produced == y_expected).all() - assert new_model.graph.node[1].op_type == "ChannelwiseOp_Batch" diff --git a/tests/fpgadataflow/test_convert_to_hls_1d_conv_layer.py b/tests/fpgadataflow/test_convert_to_hw_1d_conv_layer.py similarity index 88% rename from tests/fpgadataflow/test_convert_to_hls_1d_conv_layer.py rename to tests/fpgadataflow/test_convert_to_hw_1d_conv_layer.py index 2af0957e12..32ec229334 100644 --- a/tests/fpgadataflow/test_convert_to_hls_1d_conv_layer.py +++ b/tests/fpgadataflow/test_convert_to_hw_1d_conv_layer.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2020, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -41,7 +42,7 @@ from qonnx.util.basic import gen_finn_dt_tensor, qonnx_make_model import finn.core.onnx_exec as oxe -import finn.transformation.fpgadataflow.convert_to_hls_layers as to_hls +import finn.transformation.fpgadataflow.convert_to_hw_layers as to_hw from finn.analysis.fpgadataflow.exp_cycles_per_layer import exp_cycles_per_layer from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP @@ -49,6 +50,8 @@ from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers +from finn.util.fpgadataflow import is_fpgadataflow_node # conv_config: @@ -86,7 +89,7 @@ def test_convert_to_hls_1d_conv_layer(conv_config, depthwise, use_rtl_swg, exec_ pad_w = pad[1] + pad[3] if use_rtl_swg and exec_mode == "cppsim": - pytest.skip("cppsim not supported for RTL SWG") + pytest.skip("Skip cppsim if SWG is in rtl") if depthwise is True: group = out_chn = in_chn @@ -135,12 +138,19 @@ def test_convert_to_hls_1d_conv_layer(conv_config, depthwise, use_rtl_swg, exec_ model = model.transform(InferDataTypes()) new_model = model.transform(LowerConvsToMatMul()) - new_model = new_model.transform(to_hls.InferConvInpGen(use_rtl_variant=use_rtl_swg)) + new_model = new_model.transform(to_hw.InferConvInpGen()) + if not use_rtl_swg: + for node in new_model.graph.node: + if is_fpgadataflow_node(node): + inst = getCustomOp(node) + inst.set_nodeattr("preferred_impl_style", "hls") if depthwise is True: - new_model = new_model.transform(to_hls.InferVectorVectorActivation()) + new_model = new_model.transform(to_hw.InferVectorVectorActivation()) + new_model = new_model.transform(SpecializeLayers()) else: - new_model = new_model.transform(to_hls.InferQuantizedMatrixVectorActivation()) - fc_node = new_model.get_nodes_by_op_type("MatrixVectorActivation")[0] + new_model = new_model.transform(to_hw.InferQuantizedMatrixVectorActivation()) + new_model = new_model.transform(SpecializeLayers()) + fc_node = new_model.get_nodes_by_op_type("MatrixVectorActivation_hls")[0] fc_inst = getCustomOp(fc_node) mw = fc_inst.get_nodeattr("MW") mh = fc_inst.get_nodeattr("MH") @@ -171,12 +181,12 @@ def test_convert_to_hls_1d_conv_layer(conv_config, depthwise, use_rtl_swg, exec_ assert oxe.compare_execution(model, new_model, inp_dict) if pad_h == 1 and pad_w == 1: - padding_node = new_model.get_nodes_by_op_type("FMPadding_Batch")[0] + padding_node = new_model.get_nodes_by_op_type("FMPadding_rtl")[0] padding_inst = getCustomOp(padding_node) assert padding_inst.get_nodeattr("SIMD") == in_chn if depthwise is True and exec_mode == "rtlsim": - node = new_model.get_nodes_by_op_type("VectorVectorActivation")[0] + node = new_model.get_nodes_by_op_type("VectorVectorActivation_hls")[0] inst = getCustomOp(node) cycles_rtlsim = inst.get_nodeattr("cycles_rtlsim") exp_cycles_dict = new_model.analysis(exp_cycles_per_layer) diff --git a/tests/fpgadataflow/test_convert_to_hls_conv_fc_transition.py b/tests/fpgadataflow/test_convert_to_hw_conv_fc_transition.py similarity index 90% rename from tests/fpgadataflow/test_convert_to_hls_conv_fc_transition.py rename to tests/fpgadataflow/test_convert_to_hw_conv_fc_transition.py index 94007bdd14..59d65c820d 100755 --- a/tests/fpgadataflow/test_convert_to_hls_conv_fc_transition.py +++ b/tests/fpgadataflow/test_convert_to_hw_conv_fc_transition.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2020, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -34,6 +35,7 @@ from qonnx.core.datatype import DataType from qonnx.core.modelwrapper import ModelWrapper from qonnx.custom_op.general.im2col import compute_conv_output_dim +from qonnx.custom_op.registry import getCustomOp from qonnx.transformation.general import GiveUniqueNodeNames, RemoveUnusedTensors from qonnx.transformation.infer_data_layouts import InferDataLayouts from qonnx.transformation.infer_datatypes import InferDataTypes @@ -42,14 +44,16 @@ from qonnx.util.basic import gen_finn_dt_tensor, qonnx_make_model import finn.core.onnx_exec as oxe -import finn.transformation.fpgadataflow.convert_to_hls_layers as to_hls +import finn.transformation.fpgadataflow.convert_to_hw_layers as to_hw import finn.transformation.streamline.absorb as absorb from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers from finn.transformation.move_reshape import RemoveCNVtoFCFlatten from finn.transformation.streamline import Streamline from finn.transformation.streamline.reorder import MoveScalarLinearPastInvariants +from finn.util.fpgadataflow import is_fpgadataflow_node def get_multithreshold_rand_params(channels, num_of_thres, seed=None): @@ -187,15 +191,20 @@ def test_convert_to_hls_conv_fc_transition(conv_config, depthwise, use_reshape): new_model = new_model.transform(InferDataLayouts()) new_model = new_model.transform(RemoveUnusedTensors()) - # convert_to_hls + # convert_to_hw if depthwise is True: - new_model = new_model.transform(to_hls.InferVectorVectorActivation()) - new_model = new_model.transform(to_hls.InferQuantizedMatrixVectorActivation()) - new_model = new_model.transform(to_hls.InferThresholdingLayer()) - new_model = new_model.transform(to_hls.InferConvInpGen()) - new_model = new_model.transform(to_hls.InferStreamingMaxPool()) + new_model = new_model.transform(to_hw.InferVectorVectorActivation()) + new_model = new_model.transform(to_hw.InferQuantizedMatrixVectorActivation()) + new_model = new_model.transform(to_hw.InferThresholdingLayer()) + new_model = new_model.transform(to_hw.InferConvInpGen()) + new_model = new_model.transform(to_hw.InferStreamingMaxPool()) new_model = new_model.transform(RemoveCNVtoFCFlatten()) new_model = new_model.transform(absorb.AbsorbConsecutiveTransposes()) + for node in new_model.graph.node: + if is_fpgadataflow_node(node): + inst = getCustomOp(node) + inst.set_nodeattr("preferred_impl_style", "hls") + new_model = new_model.transform(SpecializeLayers()) new_model = new_model.transform(GiveUniqueNodeNames()) new_model = new_model.transform(InferDataLayouts()) diff --git a/tests/fpgadataflow/test_fpgadataflow_vvau.py b/tests/fpgadataflow/test_fpgadataflow_vvau.py index 1cb64dda91..d4fef6952d 100644 --- a/tests/fpgadataflow/test_fpgadataflow_vvau.py +++ b/tests/fpgadataflow/test_fpgadataflow_vvau.py @@ -278,7 +278,7 @@ def test_fpgadataflow_vvau( assert (y_produced == y_expected).all(), "VVAU specialized-op mismatches with golden output!" if exec_mode == "rtlsim": - node = model.get_nodes_by_op_type("VectorVectorActivation")[0] + node = model.get_nodes_by_op_type("VectorVectorActivation_hls")[0] inst = getCustomOp(node) cycles_rtlsim = inst.get_nodeattr("cycles_rtlsim") exp_cycles_dict = model.analysis(exp_cycles_per_layer) diff --git a/tests/fpgadataflow/test_runtime_weights.py b/tests/fpgadataflow/test_runtime_weights.py index 9b2f418776..0f0d88dd35 100644 --- a/tests/fpgadataflow/test_runtime_weights.py +++ b/tests/fpgadataflow/test_runtime_weights.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2020, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -41,6 +42,7 @@ from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP from finn.transformation.fpgadataflow.insert_fifo import InsertFIFO from finn.transformation.fpgadataflow.prepare_ip import PrepareIP +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers from finn.util.create import hls_random_mlp_maker test_fpga_part = "xczu3eg-sbva484-1-e" @@ -68,7 +70,8 @@ def test_runtime_weights_single_layer(): } layer_spec_list = [layer_spec] model = hls_random_mlp_maker(layer_spec_list) - fcl = model.get_nodes_by_op_type("MatrixVectorActivation")[0] + model = model.transform(SpecializeLayers()) + fcl = model.get_nodes_by_op_type("MatrixVectorActivation_hls")[0] op_inst = getCustomOp(fcl) op_inst.set_nodeattr("mem_mode", "decoupled") op_inst.set_nodeattr("runtime_writeable_weights", 1) @@ -80,6 +83,7 @@ def test_runtime_weights_single_layer(): old_weight_stream = map(lambda x: int(x, 16), old_weight_stream.split("\n")) old_weight_stream = list(old_weight_stream) model = model.transform(InsertFIFO(True)) + model = model.transform(SpecializeLayers()) model = model.transform(GiveUniqueNodeNames()) model = model.transform(PrepareIP(test_fpga_part, target_clk_ns)) model = model.transform(HLSSynthIP()) From d24ef6358841355e00e0c2e2b9979acbf463cc85 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Thu, 8 Feb 2024 16:01:50 +0000 Subject: [PATCH 480/665] [CustomOp] Thresholding Generate Param --- .../fpgadataflow/rtl/thresholding_rtl.py | 103 ++++++++++++++++++ 1 file changed, 103 insertions(+) diff --git a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py index 48aeb0b9f8..714930b73d 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py @@ -31,6 +31,7 @@ import os import shutil import warnings +from math import ceil, log2 from pyverilator.util.axi_utils import rtlsim_multi_io, reset_rtlsim from qonnx.core.datatype import DataType from qonnx.util.basic import ( @@ -705,4 +706,106 @@ def get_dynamic_config(self, model, address_stride=1): return config + def generate_params(self, model, path): + code_gen_dir = path + thresholds = model.get_initializer(self.onnx_node.input[1]) + mem_mode = self.get_nodeattr("mem_mode") + if mem_mode == "const": + # save thresholds in thresh.h + weight_filename = "{}/thresh.h".format(code_gen_dir) + self.make_weight_file(thresholds, "hls_header", weight_filename) + elif mem_mode == "decoupled": + # save decoupled weights for cppsim + weight_filename_sim = "{}/thresholds.npy".format(code_gen_dir) + self.make_weight_file(thresholds, "decoupled_npy", weight_filename_sim) + # also save weights as Verilog .dat file + # This file will be ignored when synthesizing UltraScale memory. + weight_filename_rtl = "{}/memblock.dat".format(code_gen_dir) + self.make_weight_file(thresholds, "decoupled_verilog_dat", weight_filename_rtl) + else: + raise Exception( + """Please set mem_mode to "const", "decoupled", + currently no other parameter value is supported!""" + ) + def make_weight_file(self, weights, weight_file_mode, weight_file_name): + """Produce a file containing given weights (thresholds) in appropriate + format for this layer. This file can be used for either synthesis or + run-time reconfig of weights. + + Arguments: + + * weights : numpy array with weights to be put into the file + * weight_file_mode : one of { decoupled_verilog_dat, + decoupled_runtime} + * weight_file_name : filename for the weight file to be generated + + """ + threshold_tensor = self.get_hls_compatible_threshold_tensor(weights) + tdt = self.get_weight_datatype() + assert np.vectorize(tdt.allowed)( + threshold_tensor + ).all(), "Thresholds can't be expressed with type %s" % str(tdt) + if "decoupled" in weight_file_mode: + # streaming thresholds need to be organized differently + # (1, pe, tmem, n_thres_steps) -> (1, tmem, pe, n_thres_steps) + decoupled_thres = np.transpose(threshold_tensor, (0, 2, 1, 3)) + # TODO add flips/reversals as needed here + # (1, tmem, pe, n_thres_steps) -(1, tmem, pe * n_thres_steps) + pe = self.get_nodeattr("PE") + n_thres_steps = self.get_nodeattr("numSteps") + decoupled_thres_pe_flipped = np.flip(decoupled_thres, axis=-2) + decoupled_thres = decoupled_thres.reshape(1, -1, pe * n_thres_steps) + decoupled_thres = decoupled_thres.copy() + decoupled_thres_pe_flipped = decoupled_thres_pe_flipped.reshape( + 1, -1, pe * n_thres_steps + ) + decoupled_thres_pe_flipped = decoupled_thres_pe_flipped.copy() + width_padded = roundup_to_integer_multiple(pe * n_thres_steps, 4) + + # zero pad the columns + thres_padded = np.zeros((1, self.calc_tmem() ,width_padded)) + thres_padded[0, :self.calc_tmem(), :(pe * n_thres_steps) ] = decoupled_thres_pe_flipped + decoupled_thres_pe_flipped = thres_padded.copy() + weight_tensor_pe_flipped = [] + if weight_file_mode == "decoupled_npy": + # save weight stream into npy for cppsim + np.save(weight_file_name, decoupled_thres) + elif weight_file_mode == "decoupled_verilog_dat": + # convert weight values into hexstring + weight_width = self.get_weightstream_width() + # pad to nearest 4 bits to get hex strings + weight_width_padded = roundup_to_integer_multiple(weight_width, 4) + weight_tensor_pe_flipped = pack_innermost_dim_as_hex_string( + decoupled_thres_pe_flipped, tdt, weight_width_padded, prefix="" + ) + weight_stream = weight_tensor_pe_flipped.flatten() + weight_stream = weight_stream.copy() + with open(weight_file_name, "w") as f: + for val in weight_stream: + f.write(val + "\n") + elif weight_file_mode == "decoupled_runtime": + # memstream axi-lite interface will map each mem line to + # one or multiple 32-bit words + weight_width = self.get_weightstream_width() + words_per_memwidth = 2 ** ceil(log2(weight_width / 32)) + if words_per_memwidth < 1: + words_per_memwidth = 1 + weight_width_padded = words_per_memwidth * 32 # convert to bits + # first, pack and ensure padding to 32 bits + for channel in decoupled_thres_pe_flipped[0]: + for weight in channel: + wdt = self.get_weight_datatype() + bw_hexdigit = roundup_to_integer_multiple(wdt.bitwidth(), 32) + weight_tensor_pe_flipped.append(pack_innermost_dim_as_hex_string( + [weight], wdt, bw_hexdigit, prefix="" + ).item()) + weight_stream = weight_tensor_pe_flipped.copy() + + with open(weight_file_name, "w") as f: + for val in weight_stream: + f.write(val + "\n") + else: + raise Exception("Decoupled weight export not yet implemented") + else: + raise Exception("Unknown weight_file_mode") From c4b7b4b9356a6ab19574e4603f7e9fa17d706433 Mon Sep 17 00:00:00 2001 From: auphelia Date: Thu, 8 Feb 2024 17:09:54 +0000 Subject: [PATCH 481/665] [Tests/transforms] Cleanup tests and transforms for new flow --- .../fpgadataflow/hls_synth_res_estimation.py | 7 +- .../fpgadataflow/derive_characteristic.py | 5 +- .../fpgadataflow/make_zynq_proj.py | 6 +- .../fpgadataflow/set_fifo_depths.py | 7 +- .../fpgadataflow/vitis_build.py | 7 +- tests/end2end/test_end2end_bnn_pynq.py | 114 ++++++--- tests/end2end/test_end2end_mobilenet_v1.py | 64 +++-- .../test_convert_to_hls_layers_synthetic.py | 222 ------------------ .../test_convert_to_hw_1d_conv_layer.py | 2 +- .../test_convert_to_hw_conv_fc_transition.py | 2 +- ...er.py => test_convert_to_hw_conv_layer.py} | 34 ++- ...nv.py => test_convert_to_hw_layers_cnv.py} | 37 +-- ..._fc.py => test_convert_to_hw_layers_fc.py} | 38 +-- .../test_convert_to_hw_layers_synthetic.py | 8 +- .../test_convert_to_hw_thresholding.py | 2 +- .../test_depthwise_convolution.py | 27 ++- ...dataflow_convinputgenerator_rtl_dynamic.py | 16 +- 17 files changed, 251 insertions(+), 347 deletions(-) delete mode 100644 tests/fpgadataflow/test_convert_to_hls_layers_synthetic.py rename tests/fpgadataflow/{test_convert_to_hls_conv_layer.py => test_convert_to_hw_conv_layer.py} (86%) rename tests/fpgadataflow/{test_convert_to_hls_layers_cnv.py => test_convert_to_hw_layers_cnv.py} (84%) rename tests/fpgadataflow/{test_convert_to_hls_layers_fc.py => test_convert_to_hw_layers_fc.py} (88%) diff --git a/src/finn/analysis/fpgadataflow/hls_synth_res_estimation.py b/src/finn/analysis/fpgadataflow/hls_synth_res_estimation.py index 4d921438f6..cd6b322727 100644 --- a/src/finn/analysis/fpgadataflow/hls_synth_res_estimation.py +++ b/src/finn/analysis/fpgadataflow/hls_synth_res_estimation.py @@ -30,11 +30,12 @@ import warnings import xml.etree.ElementTree as ET -from finn.util.fpgadataflow import is_fpgadataflow_node +from finn.util.fpgadataflow import is_fpgadataflow_node, is_hls_node def hls_synth_res_estimation(model): - """Extracts the FPGA resource results from the Vivado HLS synthesis estimates. + """Extracts the FPGA resource results from the Vitis HLS synthesis estimates. + Note that this analysis pass only works on nodes that have an HLS backend. Ensure that all nodes have unique names (by calling the GiveUniqueNodeNames transformation) prior to calling this analysis pass to ensure all nodes are visible in the results. @@ -43,7 +44,7 @@ def hls_synth_res_estimation(model): res_dict = {} for node in model.graph.node: - if is_fpgadataflow_node(node) is True: + if is_fpgadataflow_node(node) and is_hls_node(node): # init values to zero res_dict[node.name] = dict() res_dict[node.name]["BRAM_18K"] = 0 diff --git a/src/finn/transformation/fpgadataflow/derive_characteristic.py b/src/finn/transformation/fpgadataflow/derive_characteristic.py index dc660f5fba..d5699e4dc6 100644 --- a/src/finn/transformation/fpgadataflow/derive_characteristic.py +++ b/src/finn/transformation/fpgadataflow/derive_characteristic.py @@ -1,4 +1,5 @@ -# Copyright (c) 2022, Xilinx +# Copyright (C) 2022, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -134,7 +135,7 @@ def applyNodeLocal(self, node): try: # lookup op_type in registry of CustomOps prod = registry.getCustomOp(node) - assert op_type != "StreamingFIFO", "Found existing FIFOs" + assert not (op_type.startswith("StreamingFIFO")), "Found existing FIFOs" period = prod.get_nodeattr("io_chrc_period") prod_chrc = prod.get_nodeattr("io_chrc_out")[0] assert len(prod_chrc) == 2 * period, "Found unexpected characterization attribute" diff --git a/src/finn/transformation/fpgadataflow/make_zynq_proj.py b/src/finn/transformation/fpgadataflow/make_zynq_proj.py index 2f58064f11..65095f1de7 100644 --- a/src/finn/transformation/fpgadataflow/make_zynq_proj.py +++ b/src/finn/transformation/fpgadataflow/make_zynq_proj.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2020, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -45,6 +46,7 @@ from finn.transformation.fpgadataflow.insert_fifo import InsertFIFO from finn.transformation.fpgadataflow.insert_iodma import InsertIODMA from finn.transformation.fpgadataflow.prepare_ip import PrepareIP +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers from finn.util.basic import make_build_dir, pynq_native_port_width, pynq_part_map from . import templates @@ -322,6 +324,7 @@ def apply(self, model): prep_transforms = [ InsertIODMA(self.axi_port_width), InsertDWC(), + SpecializeLayers(), Floorplan(), CreateDataflowPartition(partition_model_dir=self.partition_model_dir), ] @@ -337,6 +340,7 @@ def apply(self, model): dataflow_model_filename = sdp_node.get_nodeattr("model") kernel_model = ModelWrapper(dataflow_model_filename) kernel_model = kernel_model.transform(InsertFIFO()) + kernel_model = kernel_model.transform(SpecializeLayers()) kernel_model = kernel_model.transform(GiveUniqueNodeNames(prefix)) kernel_model.save(dataflow_model_filename) kernel_model = kernel_model.transform(PrepareIP(self.fpga_part, self.period_ns)) diff --git a/src/finn/transformation/fpgadataflow/set_fifo_depths.py b/src/finn/transformation/fpgadataflow/set_fifo_depths.py index f2aefc25dd..75c35df7d7 100644 --- a/src/finn/transformation/fpgadataflow/set_fifo_depths.py +++ b/src/finn/transformation/fpgadataflow/set_fifo_depths.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2020, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -47,6 +48,7 @@ from finn.transformation.fpgadataflow.insert_dwc import InsertDWC from finn.transformation.fpgadataflow.insert_fifo import InsertFIFO from finn.transformation.fpgadataflow.prepare_ip import PrepareIP +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers from finn.util.fpgadataflow import is_fpgadataflow_node from finn.util.pyverilator import pyverilate_stitched_ip, verilator_fifosim @@ -294,12 +296,13 @@ def apply(self, model): # insert stream infrastructure (DWC/FIFO) model = model.transform(InsertDWC()) model = model.transform(InsertFIFO(create_shallow_fifos=True)) + model = model.transform(SpecializeLayers()) model = model.transform(GiveUniqueNodeNames()) model = model.transform(GiveReadableTensorNames()) # gather FIFO names, check they are of expected depth fifos = {} - fifo_nodes = model.get_nodes_by_op_type("StreamingFIFO") + fifo_nodes = model.get_nodes_by_op_type("StreamingFIFO_rtl") for node in fifo_nodes: fifos[node.name] = 0 node = getCustomOp(node) diff --git a/src/finn/transformation/fpgadataflow/vitis_build.py b/src/finn/transformation/fpgadataflow/vitis_build.py index a102660001..da7624b8ff 100644 --- a/src/finn/transformation/fpgadataflow/vitis_build.py +++ b/src/finn/transformation/fpgadataflow/vitis_build.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (c) 2020, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -49,6 +50,7 @@ from finn.transformation.fpgadataflow.insert_fifo import InsertFIFO from finn.transformation.fpgadataflow.insert_iodma import InsertIODMA from finn.transformation.fpgadataflow.prepare_ip import PrepareIP +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers from finn.util.basic import make_build_dir from . import templates @@ -381,7 +383,7 @@ def __init__( def apply(self, model): _check_vitis_envvars() # prepare at global level, then break up into kernels - prep_transforms = [InsertIODMA(512), InsertDWC()] + prep_transforms = [InsertIODMA(512), InsertDWC(), SpecializeLayers()] for trn in prep_transforms: model = model.transform(trn) model = model.transform(GiveUniqueNodeNames()) @@ -403,6 +405,7 @@ def apply(self, model): dataflow_model_filename = sdp_node.get_nodeattr("model") kernel_model = ModelWrapper(dataflow_model_filename) kernel_model = kernel_model.transform(InsertFIFO()) + kernel_model = kernel_model.transform(SpecializeLayers()) kernel_model = kernel_model.transform(RemoveUnusedTensors()) kernel_model = kernel_model.transform(GiveUniqueNodeNames(prefix)) kernel_model.save(dataflow_model_filename) diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index b296dad827..53e5bb85eb 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (c) 2020, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -60,7 +61,7 @@ from qonnx.util.cleanup import cleanup as qonnx_cleanup from shutil import copy -import finn.transformation.fpgadataflow.convert_to_hls_layers as to_hls +import finn.transformation.fpgadataflow.convert_to_hw_layers as to_hw import finn.transformation.streamline.absorb as absorb from finn.analysis.fpgadataflow.dataflow_performance import dataflow_performance from finn.core.onnx_exec import execute_onnx @@ -85,6 +86,7 @@ from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode from finn.transformation.fpgadataflow.set_fifo_depths import InsertAndSetFIFODepths +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers from finn.transformation.move_reshape import RemoveCNVtoFCFlatten from finn.transformation.qonnx.convert_qonnx_to_finn import ConvertQONNXtoFINN from finn.transformation.streamline import Streamline @@ -93,6 +95,7 @@ MoveScalarLinearPastInvariants, ) from finn.util.basic import get_finn_root, make_build_dir, test_board_map +from finn.util.fpgadataflow import is_fpgadataflow_node from finn.util.pytorch import ToTensor from finn.util.test import ( execute_parent, @@ -119,7 +122,7 @@ def get_checkpoint_name(topology, wbits, abits, step): def fold_tfc(model): - fc_layers = model.get_nodes_by_op_type("MatrixVectorActivation") + fc_layers = model.get_nodes_by_op_type("MatrixVectorActivation_hls") # (PE, SIMD, ramstyle) for each layer config = [(16, 49, "block"), (8, 8, "auto"), (8, 8, "auto"), (10, 8, "distributed")] for fcl, (pe, simd, ramstyle) in zip(fc_layers, config): @@ -128,7 +131,7 @@ def fold_tfc(model): fcl_inst.set_nodeattr("SIMD", simd) fcl_inst.set_nodeattr("ram_style", ramstyle) # set parallelism for input quantizer to be same as first layer's SIMD - inp_qnt_node = model.get_nodes_by_op_type("Thresholding_Batch")[0] + inp_qnt_node = model.get_nodes_by_op_type("Thresholding_hls")[0] inp_qnt = getCustomOp(inp_qnt_node) inp_qnt.set_nodeattr("PE", 49) inp_qnt.set_nodeattr("mem_mode", "decoupled") @@ -137,7 +140,7 @@ def fold_tfc(model): def fold_lfc(model): - fc_layers = model.get_nodes_by_op_type("MatrixVectorActivation") + fc_layers = model.get_nodes_by_op_type("MatrixVectorActivation_hls") # (PE, SIMD, ramstyle) for each layer config = [ (32, 49, "block"), @@ -152,14 +155,14 @@ def fold_lfc(model): fcl_inst.set_nodeattr("ram_style", ramstyle) fcl_inst.set_nodeattr("runtime_writeable_weights", 1) # set parallelism for input quantizer to be same as first layer's SIMD - inp_qnt_node = model.get_nodes_by_op_type("Thresholding_Batch")[0] + inp_qnt_node = model.get_nodes_by_op_type("Thresholding_hls")[0] inp_qnt = getCustomOp(inp_qnt_node) inp_qnt.set_nodeattr("PE", 49) return model def fold_cnv_large(model): - fc_layers = model.get_nodes_by_op_type("MatrixVectorActivation") + fc_layers = model.get_nodes_by_op_type("MatrixVectorActivation_hls") # each tuple is (PE, SIMD) for a layer folding = [ (16, 3), @@ -177,7 +180,7 @@ def fold_cnv_large(model): fcl_inst.set_nodeattr("PE", pe) fcl_inst.set_nodeattr("SIMD", simd) - swg_layers = model.get_nodes_by_op_type("ConvolutionInputGenerator") + swg_layers = model.get_nodes_by_op_type("ConvolutionInputGenerator_hls") for i in range(len(swg_layers)): swg_inst = getCustomOp(swg_layers[i]) simd = folding[i][1] @@ -186,7 +189,7 @@ def fold_cnv_large(model): def fold_cnv_small(model): - fc_layers = model.get_nodes_by_op_type("MatrixVectorActivation") + fc_layers = model.get_nodes_by_op_type("MatrixVectorActivation_hls") # each tuple is (PE, SIMD) for a layer folding = [ (8, 3, "distributed"), @@ -205,7 +208,7 @@ def fold_cnv_small(model): fcl_inst.set_nodeattr("SIMD", simd) fcl_inst.set_nodeattr("ram_style", ramstyle) - swg_layers = model.get_nodes_by_op_type("ConvolutionInputGenerator") + swg_layers = model.get_nodes_by_op_type("ConvolutionInputGenerator_hls") for i in range(len(swg_layers)): swg_inst = getCustomOp(swg_layers[i]) simd = folding[i][1] @@ -529,56 +532,103 @@ def test_streamline(self, topology, wbits, abits, board): model = model.transform(RemoveUnusedTensors()) model.save(get_checkpoint_name(topology, wbits, abits, "streamline")) - def test_convert_to_hls_layers(self, topology, wbits, abits, board): + def test_convert_to_hw_layers(self, topology, wbits, abits, board): prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, "streamline") model = load_test_checkpoint_or_skip(prev_chkpt_name) if topology == "tfc" and wbits == 1 and abits == 1: # use standalone thresholds for tfc-w1a1 to also exercise that option - model = model.transform(to_hls.InferThresholdingLayer()) + model = model.transform(to_hw.InferThresholdingLayer()) # needed for bipolar MatMul layers - model = model.transform(to_hls.InferBinaryMatrixVectorActivation(mem_mode)) + model = model.transform(to_hw.InferBinaryMatrixVectorActivation(mem_mode)) # needed for non-bipolar MatMul layers - model = model.transform(to_hls.InferQuantizedMatrixVectorActivation(mem_mode)) + model = model.transform(to_hw.InferQuantizedMatrixVectorActivation(mem_mode)) # TopK to LabelSelect - model = model.transform(to_hls.InferLabelSelectLayer()) + model = model.transform(to_hw.InferLabelSelectLayer()) # input quantization (if any) to standalone thresholding - model = model.transform(to_hls.InferThresholdingLayer()) + model = model.transform(to_hw.InferThresholdingLayer()) # needed for convolutions if "fc" not in topology: - model = model.transform(to_hls.InferConvInpGen()) - model = model.transform(to_hls.InferStreamingMaxPool()) + model = model.transform(to_hw.InferConvInpGen()) + model = model.transform(to_hw.InferStreamingMaxPool()) model = model.transform(RemoveCNVtoFCFlatten()) # get rid of Tranpose -> Tranpose identity seq model = model.transform(absorb.AbsorbConsecutiveTransposes()) model = model.transform(GiveUniqueNodeNames()) model = model.transform(InferDataLayouts()) - model.save(get_checkpoint_name(topology, wbits, abits, "convert_to_hls_layers")) + model.save(get_checkpoint_name(topology, wbits, abits, "convert_to_hw_layers")) exp_layer_counts = { "tfc": [ ("Reshape", 1), - ("Thresholding_Batch", 1), + ("Thresholding", 1), ("MatrixVectorActivation", 4), - ("LabelSelect_Batch", 1), + ("LabelSelect", 1), ], "tfc-1-1": [ ("Reshape", 1), - ("Thresholding_Batch", 4), + ("Thresholding", 4), ("MatrixVectorActivation", 4), - ("LabelSelect_Batch", 1), + ("LabelSelect", 1), ], "lfc": [ ("Reshape", 1), - ("Thresholding_Batch", 1), + ("Thresholding", 1), ("MatrixVectorActivation", 4), - ("LabelSelect_Batch", 1), + ("LabelSelect", 1), ], "cnv": [ ("Transpose", 1), - ("Thresholding_Batch", 1), + ("Thresholding", 1), ("ConvolutionInputGenerator", 6), ("MatrixVectorActivation", 9), - ("StreamingMaxPool_Batch", 2), - ("LabelSelect_Batch", 1), + ("StreamingMaxPool", 2), + ("LabelSelect", 1), + ], + } + if topology == "tfc" and wbits == 1 and abits == 1: + exp_key = "tfc-1-1" + else: + exp_key = topology + exp_layer_counts = exp_layer_counts[exp_key] + for op_type, exp_count in exp_layer_counts: + assert len(model.get_nodes_by_op_type(op_type)) == exp_count + + def test_specialize_layers(self, topology, wbits, abits, board): + prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, "convert_to_hw_layers") + model = load_test_checkpoint_or_skip(prev_chkpt_name) + # set preferred impl style to hls for all layers + for node in model.graph.node: + if is_fpgadataflow_node(node): + inst = getCustomOp(node) + inst.set_nodeattr("preferred_impl_style", "hls") + model = model.transform(SpecializeLayers()) + model = model.transform(GiveUniqueNodeNames()) + model.save(get_checkpoint_name(topology, wbits, abits, "specialize_layers")) + exp_layer_counts = { + "tfc": [ + ("Reshape", 1), + ("Thresholding_hls", 1), + ("MatrixVectorActivation_hls", 4), + ("LabelSelect_hls", 1), + ], + "tfc-1-1": [ + ("Reshape", 1), + ("Thresholding_hls", 4), + ("MatrixVectorActivation_hls", 4), + ("LabelSelect_hls", 1), + ], + "lfc": [ + ("Reshape", 1), + ("Thresholding_hls", 1), + ("MatrixVectorActivation_hls", 4), + ("LabelSelect_hls", 1), + ], + "cnv": [ + ("Transpose", 1), + ("Thresholding_hls", 1), + ("ConvolutionInputGenerator_rtl", 6), + ("MatrixVectorActivation_hls", 9), + ("StreamingMaxPool_hls", 2), + ("LabelSelect_hls", 1), ], } if topology == "tfc" and wbits == 1 and abits == 1: @@ -590,7 +640,7 @@ def test_convert_to_hls_layers(self, topology, wbits, abits, board): assert len(model.get_nodes_by_op_type(op_type)) == exp_count def test_create_dataflow_partition(self, topology, wbits, abits, board): - prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, "convert_to_hls_layers") + prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, "specialize_layers") model = load_test_checkpoint_or_skip(prev_chkpt_name) parent_model = model.transform(CreateDataflowPartition()) parent_model_chkpt = get_checkpoint_name(topology, wbits, abits, "dataflow_parent") @@ -656,6 +706,9 @@ def test_set_fifo_depths(self, topology, wbits, abits, board): model = model.transform(InsertAndSetFIFODepths(test_fpga_part, target_clk_ns)) fifo_layers = model.get_nodes_by_op_type("StreamingFIFO") assert len(fifo_layers) > 0 + model = model.transform(SpecializeLayers()) + fifo_layers = model.get_nodes_by_op_type("StreamingFIFO_rtl") + assert len(fifo_layers) > 0 model.save(get_checkpoint_name(topology, wbits, abits, "fifodepth_" + board)) @pytest.mark.slow @@ -665,12 +718,13 @@ def test_ipstitch_rtlsim(self, topology, wbits, abits, board): model = load_test_checkpoint_or_skip(prev_chkpt_name) test_fpga_part = get_build_env(board, target_clk_ns)["part"] model = model.transform(InsertDWC()) + model = model.transform(SpecializeLayers()) model = model.transform(GiveUniqueNodeNames()) model = model.transform(AnnotateCycles()) perf = model.analysis(dataflow_performance) latency = perf["critical_path_cycles"] # rtlsim only supports impl_style=rtl for StreamingFIFO, ensure that - for fifo_layer in model.get_nodes_by_op_type("StreamingFIFO"): + for fifo_layer in model.get_nodes_by_op_type("StreamingFIFO_rtl"): getCustomOp(fifo_layer).set_nodeattr("impl_style", "rtl") model = model.transform(PrepareIP(test_fpga_part, target_clk_ns)) model = model.transform(HLSSynthIP()) diff --git a/tests/end2end/test_end2end_mobilenet_v1.py b/tests/end2end/test_end2end_mobilenet_v1.py index 512558eb09..ba52548290 100644 --- a/tests/end2end/test_end2end_mobilenet_v1.py +++ b/tests/end2end/test_end2end_mobilenet_v1.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (c) 2020, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -54,7 +55,7 @@ from qonnx.transformation.remove import RemoveIdentityOps from qonnx.util.cleanup import cleanup as qonnx_cleanup -import finn.transformation.fpgadataflow.convert_to_hls_layers as to_hls +import finn.transformation.fpgadataflow.convert_to_hw_layers as to_hw import finn.transformation.streamline.absorb as absorb import finn.transformation.streamline.reorder as reorder from finn.core.onnx_exec import execute_onnx @@ -62,13 +63,21 @@ from finn.transformation.fpgadataflow.create_dataflow_partition import ( CreateDataflowPartition, ) +from finn.transformation.fpgadataflow.minimize_accumulator_width import ( + MinimizeAccumulatorWidth, +) +from finn.transformation.fpgadataflow.minimize_weight_bit_width import ( + MinimizeWeightBitWidth, +) from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers from finn.transformation.qonnx.convert_qonnx_to_finn import ConvertQONNXtoFINN from finn.transformation.streamline import Streamline from finn.transformation.streamline.collapse_repeated import CollapseRepeatedMul from finn.transformation.streamline.round_thresholds import RoundAndClipThresholds from finn.util.basic import alveo_default_platform, alveo_part_map, get_finn_root +from finn.util.fpgadataflow import is_fpgadataflow_node from finn.util.pytorch import NormalizePreProc from finn.util.test import ( crop_center, @@ -212,29 +221,42 @@ def test_end2end_mobilenet_lowering(): @pytest.mark.end2end @pytest.mark.xfail -def test_end2end_mobilenet_convert_to_hls_layers(): +def test_end2end_mobilenet_convert_to_hw_layers(): model = load_test_checkpoint_or_skip(build_dir + "/end2end_mobilenet_lowered.onnx") - model = model.transform(to_hls.InferPool_Batch()) - model = model.transform(to_hls.InferConvInpGen()) - model = model.transform(to_hls.InferVectorVectorActivation()) - model = model.transform(to_hls.InferQuantizedMatrixVectorActivation(mem_mode)) - model = model.transform(to_hls.InferChannelwiseLinearLayer()) - model = model.transform(to_hls.InferLabelSelectLayer()) + model = model.transform(to_hw.InferPool()) + model = model.transform(to_hw.InferConvInpGen()) + model = model.transform(to_hw.InferVectorVectorActivation()) + model = model.transform(to_hw.InferQuantizedMatrixVectorActivation(mem_mode)) + model = model.transform(to_hw.InferChannelwiseLinearLayer()) + model = model.transform(to_hw.InferLabelSelectLayer()) model = model.transform(InferShapes()) model = model.transform(GiveUniqueNodeNames()) model = model.transform(GiveReadableTensorNames()) - model.save(build_dir + "/end2end_mobilenet_hls_layers.onnx") + model.save(build_dir + "/end2end_mobilenet_hw_layers.onnx") + + +@pytest.mark.end2end +def test_end2end_mobilenet_specialize_layers(): + model = load_test_checkpoint_or_skip(build_dir + "/end2end_mobilenet_hw_layers.onnx") + for node in model.graph.node: + if is_fpgadataflow_node(node): + inst = getCustomOp(node) + inst.set_nodeattr("preferred_impl_style", "hls") + model = model.transform(SpecializeLayers()) + model = model.transform(GiveUniqueNodeNames()) + model = model.transform(GiveReadableTensorNames()) + model.save(build_dir + "/end2end_mobilenet_specialize_layers.onnx") @pytest.mark.end2end def test_end2end_mobilenet_folding(): - model = load_test_checkpoint_or_skip(build_dir + "/end2end_mobilenet_hls_layers.onnx") + model = load_test_checkpoint_or_skip(build_dir + "/end2end_mobilenet_specialize_layers.onnx") # optional extra folding to use fewer resources # applied while setting the attributes on each node assert extra_fold in [1, 2, 4] # set up folding for the depthwise conv layers impl'd by VVAUs # each value is PE for a layer - fc_layers = model.get_nodes_by_op_type("MatrixVectorActivation") + fc_layers = model.get_nodes_by_op_type("MatrixVectorActivation_hls") # each tuple is (PE, SIMD, ram_style) for a layer folding = [ (32, 3, "block"), @@ -263,7 +285,7 @@ def test_end2end_mobilenet_folding(): getCustomOp(fc_layers[0]).set_nodeattr("resType", first_layer_res_type) # set up folding for the depthwise conv layers impl'd by VVAUs # each value is PE for a layer - vvau_layers = model.get_nodes_by_op_type("VectorVectorActivation") + vvau_layers = model.get_nodes_by_op_type("VectorVectorActivation_hls") folding = [32, 32, 64, 16, 32, 8, 16, 16, 16, 16, 16, 4, 8] for vvau, pe in zip(vvau_layers, folding): vvau_inst = getCustomOp(vvau) @@ -274,11 +296,11 @@ def test_end2end_mobilenet_folding(): convinputgen_inst.set_nodeattr("SIMD", pe // extra_fold) # set SIMD in preceeding FMPadding to same value padding = model.find_direct_predecessors(convinputgen)[0] - if padding.op_type == "FMPadding_Batch": + if padding.op_type == "FMPadding_hls": padding_inst = getCustomOp(padding) padding_inst.set_nodeattr("SIMD", pe // extra_fold) # adjust final pooling layer + its inpgen - pool_node = model.get_nodes_by_op_type("Pool_Batch")[0] + pool_node = model.get_nodes_by_op_type("Pool_hls")[0] pool_inst = getCustomOp(pool_node) pool_inst.set_nodeattr("PE", 4 // extra_fold) pool_inpgen = model.find_direct_predecessors(pool_node)[0] @@ -289,8 +311,16 @@ def test_end2end_mobilenet_folding(): @pytest.mark.end2end -def test_end2end_mobilenet_create_dataflow_partition(): +def test_end2end_mobilenet_minimize_bit_width(): model = load_test_checkpoint_or_skip(build_dir + "/end2end_mobilenet_folded.onnx") + model = model.transform(MinimizeAccumulatorWidth()) + model = model.transform(MinimizeWeightBitWidth()) + model = model.save(build_dir + "/end2end_mobilenet_minimize_bitwidth.onnx") + + +@pytest.mark.end2end +def test_end2end_mobilenet_create_dataflow_partition(): + model = load_test_checkpoint_or_skip(build_dir + "/end2end_mobilenet_minimize_bitwidth.onnx") parent_model = model.transform(CreateDataflowPartition()) parent_model.save(build_dir + "/end2end_mobilenet_dataflow_parent.onnx") sdp_node = parent_model.get_nodes_by_op_type("StreamingDataflowPartition")[0] @@ -306,7 +336,7 @@ def test_end2end_mobilenet_create_dataflow_partition(): @pytest.mark.end2end @pytest.mark.xfail def test_end2end_mobilenet_cppsim(): - model = load_test_checkpoint_or_skip(build_dir + "/end2end_mobilenet_folded.onnx") + model = load_test_checkpoint_or_skip(build_dir + "/end2end_mobilenet_minimize_bitwidth.onnx") x = np.load(build_dir + "/end2end_mobilenet_input.npy") inp_name = model.graph.input[0].name out_name = model.graph.output[0].name diff --git a/tests/fpgadataflow/test_convert_to_hls_layers_synthetic.py b/tests/fpgadataflow/test_convert_to_hls_layers_synthetic.py deleted file mode 100644 index f8e566156b..0000000000 --- a/tests/fpgadataflow/test_convert_to_hls_layers_synthetic.py +++ /dev/null @@ -1,222 +0,0 @@ -# Copyright (c) 2020, Xilinx -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# * Redistributions of source code must retain the above copyright notice, this -# list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# * Neither the name of FINN nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -import pytest - -import numpy as np -import os -from onnx import TensorProto, helper -from qonnx.core.datatype import DataType -from qonnx.core.modelwrapper import ModelWrapper -from qonnx.transformation.fold_constants import FoldConstants -from qonnx.transformation.general import ( - GiveReadableTensorNames, - GiveUniqueNodeNames, - SortGraph, -) -from qonnx.transformation.infer_data_layouts import InferDataLayouts -from qonnx.transformation.infer_datatypes import InferDataTypes -from qonnx.transformation.infer_shapes import InferShapes -from qonnx.transformation.insert_topk import InsertTopK -from qonnx.util.basic import gen_finn_dt_tensor, qonnx_make_model - -import finn.core.onnx_exec as oxe -import finn.transformation.fpgadataflow.convert_to_hls_layers as to_hls -from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim -from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim -from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode -from finn.transformation.streamline.absorb import ( - AbsorbConsecutiveTransposes, - AbsorbScalarMulAddIntoTopK, -) -from finn.transformation.streamline.collapse_repeated import ( - CollapseRepeatedAdd, - CollapseRepeatedMul, -) -from finn.transformation.streamline.reorder import ( - MoveAddPastMul, - MoveScalarLinearPastInvariants, -) -from finn.util.test import soft_verify_topk - -export_onnx_path = "test_output_synthetic.onnx" - -# construct a synthetic graph to test: -# topk insertion, topk conversion to hls, add conversion to hls -# graph should just be a sum - - -def make_model(ch, ifmdim): - shape = [1, ch, ifmdim, ifmdim] - inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, shape) - inp1_add0_ct = helper.make_tensor_value_info("inp1_add0_ct", TensorProto.FLOAT, [1]) - inp1_add = helper.make_tensor_value_info("inp1_add", TensorProto.FLOAT, shape) - inp1_add_ct = helper.make_tensor_value_info("inp1_add_ct", TensorProto.FLOAT, [1]) - inp2_add = helper.make_tensor_value_info("inp2_add", TensorProto.FLOAT, shape) - inp2_add_ct = helper.make_tensor_value_info("inp2_add_ct", TensorProto.FLOAT, [1]) - inp1_mul = helper.make_tensor_value_info("inp1_mul", TensorProto.FLOAT, shape) - inp1_mul_ct = helper.make_tensor_value_info("inp1_mul_ct", TensorProto.FLOAT, [1]) - inp2_mul = helper.make_tensor_value_info("inp2_mul", TensorProto.FLOAT, shape) - inp2_mul_ct = helper.make_tensor_value_info("inp2_mul_ct", TensorProto.FLOAT, [1]) - eltwise_add = helper.make_tensor_value_info("eltwise_add", TensorProto.FLOAT, shape) - pool = helper.make_tensor_value_info("pool", TensorProto.FLOAT, [1, ch, 1, 1]) - reshape_ct = helper.make_tensor_value_info("reshape_ct", TensorProto.INT64, [2]) - outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, [1, ch]) - - add0_node = helper.make_node("Add", [inp.name, inp1_add0_ct.name], ["out_add0"]) - add1_node = helper.make_node("Add", ["out_add0", inp1_add_ct.name], [inp1_add.name]) - add2_node = helper.make_node("Add", ["out_add0", inp2_add_ct.name], [inp2_add.name]) - mul1_node = helper.make_node("Mul", [inp1_add.name, inp1_mul_ct.name], [inp1_mul.name]) - mul2_node = helper.make_node("Mul", [inp2_add.name, inp2_mul_ct.name], [inp2_mul.name]) - eltwise_add_node = helper.make_node("Add", [inp1_mul.name, inp2_mul.name], [eltwise_add.name]) - globalavgpool_node = helper.make_node("GlobalAveragePool", [eltwise_add.name], [pool.name]) - reshape_node = helper.make_node("Reshape", [pool.name, reshape_ct.name], [outp.name]) - - graph = helper.make_graph( - nodes=[ - add0_node, - add1_node, - add2_node, - mul1_node, - mul2_node, - eltwise_add_node, - globalavgpool_node, - reshape_node, - ], - name="graph", - inputs=[inp], - outputs=[outp], - ) - - model = qonnx_make_model(graph, producer_name="add-model") - model = ModelWrapper(model) - - # set initializers for scalar add/mul nodes - model.set_initializer(add0_node.input[1], np.array([0.0], dtype=np.float32)) - model.set_initializer(add1_node.input[1], np.array([7.0], dtype=np.float32)) - model.set_initializer(add2_node.input[1], np.array([8.0], dtype=np.float32)) - model.set_initializer(mul1_node.input[1], np.array([2.0], dtype=np.float32)) - model.set_initializer(mul2_node.input[1], np.array([2.0], dtype=np.float32)) - model.set_initializer(reshape_node.input[1], np.array([1, -1], dtype=np.int64)) - - return model - - -# data types -@pytest.mark.parametrize("idt", [DataType["UINT2"]]) -# channels -@pytest.mark.parametrize("ch", [16]) -# ifmdim -@pytest.mark.parametrize("ifmdim", [5]) -@pytest.mark.fpgadataflow -@pytest.mark.vivado -@pytest.mark.slow -def test_convert_to_hls_layers_synthetic(ch, ifmdim, idt): - model = make_model(ch, ifmdim) - model.save(export_onnx_path) - model = ModelWrapper(export_onnx_path, fix_float64=True) - model = model.transform(InferShapes()) - model = model.transform(FoldConstants()) - model = model.transform(GiveUniqueNodeNames()) - model = model.transform(GiveReadableTensorNames()) - model = model.transform(InferDataLayouts()) - # model.save("golden.onnx") - # generate test vectors of correct shape - if ifmdim == -1: - input_tensor_shape = (1, ch) - else: - input_tensor_shape = (1, ch, ifmdim, ifmdim) - - x = gen_finn_dt_tensor(idt, input_tensor_shape) - - # generate expected value from streamlined net - input_dict = {model.graph.input[0].name: x} - - output_dict = oxe.execute_onnx(model, input_dict, True) - produced_sum = output_dict[model.graph.output[0].name] - chw_mul = model.get_initializer(model.graph.node[-1].input[1]) - chw_mul = 1 - expected_sum = chw_mul * np.sum(2 * (2 * x + 15.0), axis=(2, 3)) / (ifmdim * ifmdim) - assert (produced_sum.flatten() == expected_sum.flatten()).all() - - model = model.transform(InferDataLayouts()) - - # convert to hls - model.set_tensor_datatype(model.graph.input[0].name, idt) - # extra streamlining - model = model.transform(MoveScalarLinearPastInvariants()) - model = model.transform(MoveAddPastMul()) - model = model.transform(CollapseRepeatedMul()) - model = model.transform(CollapseRepeatedAdd()) - # insert top-k node, which should absorb linear ops before it - - model = model.transform(InferShapes()) - model = model.transform(InferDataLayouts()) - model = model.transform(InferDataTypes()) - - model = model.transform(to_hls.InferChannelwiseLinearLayer()) - model = model.transform(to_hls.InferAddStreamsLayer()) - model = model.transform(to_hls.InferGlobalAccPoolLayer()) - model = model.transform(MoveScalarLinearPastInvariants()) - model = model.transform(InsertTopK()) - model = model.transform(AbsorbScalarMulAddIntoTopK()) - model = model.transform(InferDataTypes()) - model = model.transform(to_hls.InferLabelSelectLayer()) - model = model.transform(AbsorbConsecutiveTransposes()) - model = model.transform(InferDataTypes()) - model = model.transform(to_hls.InferLabelSelectLayer()) - model = model.transform(to_hls.InferDuplicateStreamsLayer()) - - model = model.transform(SortGraph()) - - # model.save("golden_hls.onnx") - # check topology status - - finn_nodes = model.get_finn_nodes() - assert len(finn_nodes) == 9 - add_nodes = model.get_nodes_by_op_type("AddStreams_Batch") - assert len(add_nodes) == 1 - pool_nodes = model.get_nodes_by_op_type("GlobalAccPool_Batch") - assert len(pool_nodes) == 1 - label_nodes = model.get_nodes_by_op_type("LabelSelect_Batch") - assert len(label_nodes) == 1 - channelwise_nodes = model.get_nodes_by_op_type("ChannelwiseOp_Batch") - assert len(channelwise_nodes) == 5 - dup_nodes = model.get_nodes_by_op_type("DuplicateStreams_Batch") - assert len(dup_nodes) == 1 - - model = model.transform(PrepareCppSim()) - model = model.transform(CompileCppSim()) - model = model.transform(SetExecMode("cppsim")) - - output_dict = oxe.execute_onnx(model, input_dict, True) - produced_topk_hls = output_dict[model.graph.output[0].name] - topk_input = output_dict[model.graph.node[-1].input[0]] - assert soft_verify_topk(topk_input, produced_topk_hls, 5) - - os.remove(export_onnx_path) diff --git a/tests/fpgadataflow/test_convert_to_hw_1d_conv_layer.py b/tests/fpgadataflow/test_convert_to_hw_1d_conv_layer.py index 32ec229334..55f46e321b 100644 --- a/tests/fpgadataflow/test_convert_to_hw_1d_conv_layer.py +++ b/tests/fpgadataflow/test_convert_to_hw_1d_conv_layer.py @@ -74,7 +74,7 @@ @pytest.mark.fpgadataflow @pytest.mark.slow @pytest.mark.vivado -def test_convert_to_hls_1d_conv_layer(conv_config, depthwise, use_rtl_swg, exec_mode): +def test_convert_to_hw_1d_conv_layer(conv_config, depthwise, use_rtl_swg, exec_mode): pad, kernel_size, stride, dilation = conv_config np.random.seed(0) idt = DataType["UINT4"] diff --git a/tests/fpgadataflow/test_convert_to_hw_conv_fc_transition.py b/tests/fpgadataflow/test_convert_to_hw_conv_fc_transition.py index 59d65c820d..f7b3c55c2a 100755 --- a/tests/fpgadataflow/test_convert_to_hw_conv_fc_transition.py +++ b/tests/fpgadataflow/test_convert_to_hw_conv_fc_transition.py @@ -82,7 +82,7 @@ def get_multithreshold_rand_params(channels, num_of_thres, seed=None): @pytest.mark.fpgadataflow @pytest.mark.vivado @pytest.mark.slow -def test_convert_to_hls_conv_fc_transition(conv_config, depthwise, use_reshape): +def test_convert_to_hw_conv_fc_transition(conv_config, depthwise, use_reshape): np.random.seed(0) idt = DataType["UINT4"] odt = DataType["UINT4"] diff --git a/tests/fpgadataflow/test_convert_to_hls_conv_layer.py b/tests/fpgadataflow/test_convert_to_hw_conv_layer.py similarity index 86% rename from tests/fpgadataflow/test_convert_to_hls_conv_layer.py rename to tests/fpgadataflow/test_convert_to_hw_conv_layer.py index 95beffafac..8cade1bfa1 100644 --- a/tests/fpgadataflow/test_convert_to_hls_conv_layer.py +++ b/tests/fpgadataflow/test_convert_to_hw_conv_layer.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2020, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -41,7 +42,7 @@ from qonnx.util.basic import gen_finn_dt_tensor, qonnx_make_model import finn.core.onnx_exec as oxe -import finn.transformation.fpgadataflow.convert_to_hls_layers as to_hls +import finn.transformation.fpgadataflow.convert_to_hw_layers as to_hw from finn.analysis.fpgadataflow.exp_cycles_per_layer import exp_cycles_per_layer from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP @@ -49,6 +50,8 @@ from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers +from finn.util.fpgadataflow import is_fpgadataflow_node # conv_config kernel_size,stride, pad @@ -62,7 +65,7 @@ @pytest.mark.fpgadataflow @pytest.mark.slow @pytest.mark.vivado -def test_convert_to_hls_conv_layer(conv_config, depthwise, use_rtl_swg, exec_mode): +def test_convert_to_hw_conv_layer(conv_config, depthwise, use_rtl_swg, exec_mode): kernel_size, stride, pad = conv_config np.random.seed(0) idt = DataType["UINT4"] @@ -71,7 +74,7 @@ def test_convert_to_hls_conv_layer(conv_config, depthwise, use_rtl_swg, exec_mod in_chn = 16 if use_rtl_swg and exec_mode == "cppsim": - pytest.skip("cppsim not supported for RTL SWG") + pytest.skip("Skip cppsim if SWG in rtl") if depthwise is True: group = out_chn = in_chn @@ -120,12 +123,19 @@ def test_convert_to_hls_conv_layer(conv_config, depthwise, use_rtl_swg, exec_mod model = model.transform(InferDataTypes()) new_model = model.transform(LowerConvsToMatMul()) - new_model = new_model.transform(to_hls.InferConvInpGen(use_rtl_variant=use_rtl_swg)) + new_model = new_model.transform(to_hw.InferConvInpGen()) + if not use_rtl_swg: + for node in new_model.graph.node: + if is_fpgadataflow_node(node): + inst = getCustomOp(node) + inst.set_nodeattr("preferred_impl_style", "hls") if depthwise is True: - new_model = new_model.transform(to_hls.InferVectorVectorActivation()) + new_model = new_model.transform(to_hw.InferVectorVectorActivation()) + new_model = new_model.transform(SpecializeLayers()) else: - new_model = new_model.transform(to_hls.InferQuantizedMatrixVectorActivation()) - fc_node = new_model.get_nodes_by_op_type("MatrixVectorActivation")[0] + new_model = new_model.transform(to_hw.InferQuantizedMatrixVectorActivation()) + new_model = new_model.transform(SpecializeLayers()) + fc_node = new_model.get_nodes_by_op_type("MatrixVectorActivation_hls")[0] fc_inst = getCustomOp(fc_node) mw = fc_inst.get_nodeattr("MW") mh = fc_inst.get_nodeattr("MH") @@ -156,9 +166,9 @@ def test_convert_to_hls_conv_layer(conv_config, depthwise, use_rtl_swg, exec_mod assert oxe.compare_execution(model, new_model, inp_dict) if not use_rtl_swg and kernel_size == 1 and stride > 1 and pad == 0: - assert new_model.graph.node[1].op_type == "DownSampler" + assert new_model.graph.node[1].op_type == "DownSampler_hls" if exec_mode == "rtlsim": - node = new_model.get_nodes_by_op_type("DownSampler")[0] + node = new_model.get_nodes_by_op_type("DownSampler_hls")[0] inst = getCustomOp(node) cycles_rtlsim = inst.get_nodeattr("cycles_rtlsim") exp_cycles_dict = new_model.analysis(exp_cycles_per_layer) @@ -170,12 +180,12 @@ def test_convert_to_hls_conv_layer(conv_config, depthwise, use_rtl_swg, exec_mod if use_rtl_swg: padding_node = new_model.get_nodes_by_op_type("FMPadding_rtl")[0] else: - padding_node = new_model.get_nodes_by_op_type("FMPadding_Batch")[0] + padding_node = new_model.get_nodes_by_op_type("FMPadding_hls")[0] padding_inst = getCustomOp(padding_node) assert padding_inst.get_nodeattr("SIMD") == in_chn if depthwise is True and exec_mode == "rtlsim": - node = new_model.get_nodes_by_op_type("VectorVectorActivation")[0] + node = new_model.get_nodes_by_op_type("VectorVectorActivation_hls")[0] inst = getCustomOp(node) cycles_rtlsim = inst.get_nodeattr("cycles_rtlsim") exp_cycles_dict = new_model.analysis(exp_cycles_per_layer) diff --git a/tests/fpgadataflow/test_convert_to_hls_layers_cnv.py b/tests/fpgadataflow/test_convert_to_hw_layers_cnv.py similarity index 84% rename from tests/fpgadataflow/test_convert_to_hls_layers_cnv.py rename to tests/fpgadataflow/test_convert_to_hw_layers_cnv.py index c9cb4f0802..117a9a5850 100644 --- a/tests/fpgadataflow/test_convert_to_hls_layers_cnv.py +++ b/tests/fpgadataflow/test_convert_to_hw_layers_cnv.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2020, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -48,24 +49,25 @@ from qonnx.util.cleanup import cleanup as qonnx_cleanup import finn.core.onnx_exec as oxe -import finn.transformation.fpgadataflow.convert_to_hls_layers as to_hls +import finn.transformation.fpgadataflow.convert_to_hw_layers as to_hw import finn.transformation.streamline.absorb as absorb from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers from finn.transformation.qonnx.convert_qonnx_to_finn import ConvertQONNXtoFINN from finn.transformation.streamline import Streamline from finn.transformation.streamline.reorder import MakeMaxPoolNHWC from finn.util.test import get_test_model_trained -export_onnx_path_cnv = "test_convert_to_hls_layers_cnv.onnx" +export_onnx_path_cnv = "test_convert_to_hw_layers_cnv.onnx" @pytest.mark.fpgadataflow @pytest.mark.vivado # Standalone or fused thresholding-based activation @pytest.mark.parametrize("fused_activation", [True, False]) -def test_convert_to_hls_layers_cnv_w1a1(fused_activation): +def test_convert_to_hw_layers_cnv_w1a1(fused_activation): cnv = get_test_model_trained("CNV", 1, 1) export_qonnx(cnv, torch.randn(1, 3, 32, 32), export_onnx_path_cnv) qonnx_cleanup(export_onnx_path_cnv, out_file=export_onnx_path_cnv) @@ -95,14 +97,21 @@ def test_convert_to_hls_layers_cnv_w1a1(fused_activation): expected_ctx = oxe.execute_onnx(model, input_dict, True) expected = expected_ctx[model.graph.output[0].name] - # if we infer thresholding first, all MultiThresholds get converted to HLS + # if we infer thresholding first, all MultiThresholds get converted to HW # subsequently, the FC inference will generate passthrough MVAUs if not fused_activation: - model = model.transform(to_hls.InferThresholdingLayer()) - model = model.transform(to_hls.InferBinaryMatrixVectorActivation()) - model = model.transform(to_hls.InferQuantizedMatrixVectorActivation()) + model = model.transform(to_hw.InferThresholdingLayer()) + model = model.transform(to_hw.InferBinaryMatrixVectorActivation()) + model = model.transform(to_hw.InferQuantizedMatrixVectorActivation()) + model = model.transform(to_hw.InferConvInpGen()) + conv_nodes = model.get_nodes_by_op_type("ConvolutionInputGenerator") + for cnv in conv_nodes: + cnv_inst = getCustomOp(cnv) + cnv_inst.set_nodeattr("preferred_impl_style", "hls") + model = model.transform(to_hw.InferStreamingMaxPool()) + model = model.transform(SpecializeLayers()) for node in model.graph.node: - if node.op_type == "MatrixVectorActivation": + if node.op_type == "MatrixVectorActivation_hls": inst = getCustomOp(node) inst.set_nodeattr("mem_mode", "decoupled") mw = inst.get_nodeattr("MW") @@ -117,25 +126,23 @@ def test_convert_to_hls_layers_cnv_w1a1(fused_activation): else: simd = mw inst.set_nodeattr("SIMD", simd) - model = model.transform(to_hls.InferConvInpGen()) - model = model.transform(to_hls.InferStreamingMaxPool()) # check topology status finn_nodes = model.get_finn_nodes() if fused_activation: assert len(finn_nodes) == 18 else: assert len(finn_nodes) == 26 - thr_nodes = model.get_nodes_by_op_type("Thresholding_Batch") + thr_nodes = model.get_nodes_by_op_type("Thresholding_hls") assert len(thr_nodes) == 8 non_finn_nodes = model.get_non_finn_nodes() assert len(non_finn_nodes) == 5 exp_non_finn_nodes = ["Transpose", "Transpose", "Reshape", "Mul", "Add"] assert [x.op_type for x in non_finn_nodes] == exp_non_finn_nodes - fc_nodes = model.get_nodes_by_op_type("MatrixVectorActivation") + fc_nodes = model.get_nodes_by_op_type("MatrixVectorActivation_hls") assert len(fc_nodes) == 9 - swg_nodes = model.get_nodes_by_op_type("ConvolutionInputGenerator") + swg_nodes = model.get_nodes_by_op_type("ConvolutionInputGenerator_hls") assert len(swg_nodes) == 6 - mp_nodes = model.get_nodes_by_op_type("StreamingMaxPool_Batch") + mp_nodes = model.get_nodes_by_op_type("StreamingMaxPool_hls") assert len(mp_nodes) == 2 model = model.transform(PrepareCppSim()) model = model.transform(CompileCppSim()) diff --git a/tests/fpgadataflow/test_convert_to_hls_layers_fc.py b/tests/fpgadataflow/test_convert_to_hw_layers_fc.py similarity index 88% rename from tests/fpgadataflow/test_convert_to_hls_layers_fc.py rename to tests/fpgadataflow/test_convert_to_hw_layers_fc.py index 8a7b2509a4..13f6a4393e 100644 --- a/tests/fpgadataflow/test_convert_to_hls_layers_fc.py +++ b/tests/fpgadataflow/test_convert_to_hw_layers_fc.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2020, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -48,22 +49,23 @@ from qonnx.util.cleanup import cleanup as qonnx_cleanup import finn.core.onnx_exec as oxe -import finn.transformation.fpgadataflow.convert_to_hls_layers as to_hls +import finn.transformation.fpgadataflow.convert_to_hw_layers as to_hw import finn.transformation.streamline.absorb as absorb from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers from finn.transformation.qonnx.convert_qonnx_to_finn import ConvertQONNXtoFINN from finn.transformation.streamline import Streamline from finn.transformation.streamline.round_thresholds import RoundAndClipThresholds from finn.util.test import get_test_model_trained -export_onnx_path = "test_convert_to_hls_layers_fc.onnx" +export_onnx_path = "test_convert_to_hw_layers_fc.onnx" @pytest.mark.fpgadataflow @pytest.mark.vivado -def test_convert_to_hls_layers_tfc_w1a1(): +def test_convert_to_hw_layers_tfc_w1a1(): tfc = get_test_model_trained("TFC", 1, 1) export_qonnx(tfc, torch.randn(1, 1, 28, 28), export_onnx_path) qonnx_cleanup(export_onnx_path, out_file=export_onnx_path) @@ -79,24 +81,25 @@ def test_convert_to_hls_layers_tfc_w1a1(): model = model.transform(absorb.AbsorbAddIntoMultiThreshold()) model = model.transform(absorb.AbsorbMulIntoMultiThreshold()) model = model.transform(RoundAndClipThresholds()) - model = model.transform(to_hls.InferBinaryMatrixVectorActivation()) + model = model.transform(to_hw.InferBinaryMatrixVectorActivation()) + model = model.transform(SpecializeLayers()) fc0 = model.graph.node[2] - assert fc0.op_type == "MatrixVectorActivation" + assert fc0.op_type == "MatrixVectorActivation_hls" assert model.get_tensor_shape(fc0.input[0]) == [1, 784] assert model.get_tensor_shape(fc0.input[1]) == [784, 64] assert model.get_tensor_shape(fc0.input[2]) == [64, 1] fc1 = model.graph.node[3] - assert fc1.op_type == "MatrixVectorActivation" + assert fc1.op_type == "MatrixVectorActivation_hls" assert model.get_tensor_shape(fc1.input[0]) == [1, 64] assert model.get_tensor_shape(fc1.input[1]) == [64, 64] assert model.get_tensor_shape(fc1.input[2]) == [64, 1] fc2 = model.graph.node[4] - assert fc2.op_type == "MatrixVectorActivation" + assert fc2.op_type == "MatrixVectorActivation_hls" assert model.get_tensor_shape(fc2.input[0]) == [1, 64] assert model.get_tensor_shape(fc2.input[1]) == [64, 64] assert model.get_tensor_shape(fc2.input[2]) == [64, 1] fc3 = model.graph.node[5] - assert fc3.op_type == "MatrixVectorActivation" + assert fc3.op_type == "MatrixVectorActivation_hls" assert model.get_tensor_shape(fc3.input[0]) == [1, 64] assert model.get_tensor_shape(fc3.input[1]) == [64, 10] @@ -137,7 +140,7 @@ def test_convert_to_hls_layers_tfc_w1a1(): @pytest.mark.fpgadataflow @pytest.mark.vivado -def test_convert_to_hls_layers_tfc_w1a2(): +def test_convert_to_hw_layers_tfc_w1a2(): tfc = get_test_model_trained("TFC", 1, 2) export_qonnx(tfc, torch.randn(1, 1, 28, 28), export_onnx_path) qonnx_cleanup(export_onnx_path, out_file=export_onnx_path) @@ -150,29 +153,26 @@ def test_convert_to_hls_layers_tfc_w1a2(): model = model.transform(GiveUniqueParameterTensors()) model = model.transform(GiveReadableTensorNames()) model = model.transform(Streamline()) - from finn.transformation.fpgadataflow.convert_to_hls_layers import ( - InferQuantizedMatrixVectorActivation, - ) - - model = model.transform(InferQuantizedMatrixVectorActivation()) + model = model.transform(to_hw.InferQuantizedMatrixVectorActivation()) + model = model.transform(SpecializeLayers()) fc0 = model.graph.node[2] - assert fc0.op_type == "MatrixVectorActivation" + assert fc0.op_type == "MatrixVectorActivation_hls" assert model.get_tensor_shape(fc0.input[0]) == [1, 784] assert model.get_tensor_shape(fc0.input[1]) == [784, 64] assert model.get_tensor_shape(fc0.input[2]) == [64, 2] fc1 = model.graph.node[3] - assert fc1.op_type == "MatrixVectorActivation" + assert fc1.op_type == "MatrixVectorActivation_hls" assert model.get_tensor_shape(fc1.input[0]) == [1, 64] assert model.get_tensor_shape(fc1.input[1]) == [64, 64] assert model.get_tensor_shape(fc1.input[2]) == [64, 2] fc2 = model.graph.node[4] - assert fc2.op_type == "MatrixVectorActivation" + assert fc2.op_type == "MatrixVectorActivation_hls" assert model.get_tensor_shape(fc2.input[0]) == [1, 64] assert model.get_tensor_shape(fc2.input[1]) == [64, 64] assert model.get_tensor_shape(fc2.input[2]) == [64, 2] fc3 = model.graph.node[5] - assert fc3.op_type == "MatrixVectorActivation" + assert fc3.op_type == "MatrixVectorActivation_hls" assert model.get_tensor_shape(fc3.input[0]) == [1, 64] assert model.get_tensor_shape(fc3.input[1]) == [64, 10] fc0w = getCustomOp(fc0) diff --git a/tests/fpgadataflow/test_convert_to_hw_layers_synthetic.py b/tests/fpgadataflow/test_convert_to_hw_layers_synthetic.py index 02a53485ad..6c83f10617 100644 --- a/tests/fpgadataflow/test_convert_to_hw_layers_synthetic.py +++ b/tests/fpgadataflow/test_convert_to_hw_layers_synthetic.py @@ -1,4 +1,4 @@ -# Copyright (C) 2023, Advanced Micro Devices, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -68,7 +68,7 @@ export_onnx_path = "test_output_synthetic.onnx" # construct a synthetic graph to test: -# topk insertion, topk conversion to hls, add conversion to hls +# topk insertion, topk conversion to hw, add conversion to hw # graph should just be a sum @@ -137,7 +137,7 @@ def make_model(ch, ifmdim): @pytest.mark.fpgadataflow @pytest.mark.vivado @pytest.mark.slow -def test_convert_to_hls_layers_synthetic(ch, ifmdim, idt): +def test_convert_to_hw_layers_synthetic(ch, ifmdim, idt): model = make_model(ch, ifmdim) model.save(export_onnx_path) model = ModelWrapper(export_onnx_path, fix_float64=True) @@ -166,7 +166,7 @@ def test_convert_to_hls_layers_synthetic(ch, ifmdim, idt): model = model.transform(InferDataLayouts()) - # convert to hls + # convert to hw model.set_tensor_datatype(model.graph.input[0].name, idt) # extra streamlining model = model.transform(MoveScalarLinearPastInvariants()) diff --git a/tests/fpgadataflow/test_convert_to_hw_thresholding.py b/tests/fpgadataflow/test_convert_to_hw_thresholding.py index dffc5c4642..685c955f4e 100755 --- a/tests/fpgadataflow/test_convert_to_hw_thresholding.py +++ b/tests/fpgadataflow/test_convert_to_hw_thresholding.py @@ -129,7 +129,7 @@ def test_convert_multithreshold_to_hardware( pe = generate_pe_value(fold, num_input_channels) num_steps = activation.get_num_possible_values() - 1 - # See convert_to_hls_layers::InferThresholdingLayer: + # See convert_to_hw_layers::InferThresholdingLayer: # assert (not odt.signed()) or (actval < 0) # This implies that it expects a negative activation, BIPOLAR does not provide that if activation == DataType["BIPOLAR"]: diff --git a/tests/fpgadataflow/test_depthwise_convolution.py b/tests/fpgadataflow/test_depthwise_convolution.py index 2ffd696528..6ad8618981 100644 --- a/tests/fpgadataflow/test_depthwise_convolution.py +++ b/tests/fpgadataflow/test_depthwise_convolution.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2020, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -45,7 +46,7 @@ import finn.core.onnx_exec as oxe from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim -from finn.transformation.fpgadataflow.convert_to_hls_layers import ( +from finn.transformation.fpgadataflow.convert_to_hw_layers import ( InferConvInpGen, InferVectorVectorActivation, ) @@ -54,6 +55,8 @@ from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers +from finn.util.fpgadataflow import is_fpgadataflow_node def set_up_reference_model(act, idt, wdt, k, ifm_dim, ifm_ch, stride, padding): @@ -166,7 +169,7 @@ def set_up_reference_model(act, idt, wdt, k, ifm_dim, ifm_ch, stride, padding): @pytest.mark.fpgadataflow @pytest.mark.slow @pytest.mark.vivado -def test_depthwise_conv_hls_cppsim(act, pe, k, stride, padding): +def test_depthwise_conv_hw_cppsim(act, pe, k, stride, padding): idt = wdt = DataType["INT4"] ifm_dim = 6 ifm_ch = 4 @@ -179,14 +182,21 @@ def test_depthwise_conv_hls_cppsim(act, pe, k, stride, padding): new_model = model.transform(InferConvInpGen()) new_model = new_model.transform(InferVectorVectorActivation()) + # for cppsim set all layers to preferred impl style = "hls" + for node in new_model.graph.node: + if is_fpgadataflow_node(node): + inst = getCustomOp(node) + inst.set_nodeattr("preferred_impl_style", "hls") + + new_model = new_model.transform(SpecializeLayers()) # set SIMD in ConvInputGen node and PE in VVAU node for n in new_model.graph.node: - if n.op_type == "ConvolutionInputGenerator": + if n.op_type == "ConvolutionInputGenerator_hls": convinputgen_node = getCustomOp(n) convinputgen_node.set_nodeattr("SIMD", pe) - elif n.op_type == "VectorVectorActivation": + elif n.op_type == "VectorVectorActivation_hls": vvau_node = getCustomOp(n) vvau_node.set_nodeattr("PE", pe) new_model = new_model.transform(SetExecMode("cppsim")) @@ -209,7 +219,7 @@ def test_depthwise_conv_hls_cppsim(act, pe, k, stride, padding): @pytest.mark.fpgadataflow @pytest.mark.slow @pytest.mark.vivado -def test_depthwise_conv_hls_rtlsim(act, pe, k, stride, padding): +def test_depthwise_conv_hw_rtlsim(act, pe, k, stride, padding): idt = wdt = DataType["INT4"] ifm_dim = 6 ifm_ch = 4 @@ -223,13 +233,14 @@ def test_depthwise_conv_hls_rtlsim(act, pe, k, stride, padding): new_model = model.transform(InferConvInpGen()) new_model = new_model.transform(InferVectorVectorActivation()) + new_model = new_model.transform(SpecializeLayers()) # set SIMD in ConvInputGen node and PE in VVAU node for n in new_model.graph.node: - if n.op_type == "ConvolutionInputGenerator": + if n.op_type == "ConvolutionInputGenerator_rtl": convinputgen_node = getCustomOp(n) convinputgen_node.set_nodeattr("SIMD", pe) - elif n.op_type == "VectorVectorActivation": + elif n.op_type == "VectorVectorActivation_hls": vvau_node = getCustomOp(n) vvau_node.set_nodeattr("PE", pe) diff --git a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py index ee37ab86ef..a05dd53e28 100644 --- a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py +++ b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py @@ -1,4 +1,4 @@ -# Copyright (c) 2022, Advanced Micro Devices, Inc. +# Copyright (c) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -48,7 +48,7 @@ from qonnx.util.basic import gen_finn_dt_tensor, get_by_name, qonnx_make_model import finn.core.onnx_exec as oxe -import finn.transformation.fpgadataflow.convert_to_hls_layers as to_hls +import finn.transformation.fpgadataflow.convert_to_hw_layers as to_hw import finn.transformation.streamline.absorb as absorb from finn.core.onnx_exec import execute_onnx from finn.core.rtlsim_exec import rtlsim_exec @@ -249,10 +249,11 @@ def test_fpgadataflow_conv_dynamic(cfg): # convert to hardware and prepare simulation model = largest_model.transform(LowerConvsToMatMul()) - model = model.transform(to_hls.InferConvInpGen(use_rtl_variant=True)) - model = model.transform(to_hls.InferQuantizedMatrixVectorActivation(mem_mode="decoupled")) - model = model.transform(to_hls.InferVectorVectorActivation()) + model = model.transform(to_hw.InferConvInpGen()) + model = model.transform(to_hw.InferQuantizedMatrixVectorActivation()) + model = model.transform(to_hw.InferVectorVectorActivation()) model = model.transform(absorb.AbsorbConsecutiveTransposes()) + model = model.transform(SpecializeLayers()) parent_model = model.transform(CreateDataflowPartition()) sdp_inst = getCustomOp(parent_model.get_nodes_by_op_type("StreamingDataflowPartition")[0]) model = ModelWrapper(sdp_inst.get_nodeattr("model")) @@ -268,8 +269,8 @@ def test_fpgadataflow_conv_dynamic(cfg): getCustomOp(swg_node).set_nodeattr("dynamic_mode", 1) getCustomOp(swg_node).set_nodeattr("inFIFODepths", [16]) getCustomOp(swg_node).set_nodeattr("outFIFODepths", [16]) - comp_nodes = model.get_nodes_by_op_type("MatrixVectorActivation") - comp_nodes += model.get_nodes_by_op_type("VectorVectorActivation") + comp_nodes = model.get_nodes_by_op_type("MatrixVectorActivation_hls") + comp_nodes += model.get_nodes_by_op_type("VectorVectorActivation_hls") for comp_node in comp_nodes: if depthwise: getCustomOp(comp_node).set_nodeattr("PE", 4) @@ -278,6 +279,7 @@ def test_fpgadataflow_conv_dynamic(cfg): getCustomOp(comp_node).set_nodeattr("PE", 4) model = model.transform(InsertDWC()) model = model.transform(InsertFIFO(create_shallow_fifos=True)) + model = model.transform(SpecializeLayers()) model = model.transform(GiveUniqueNodeNames()) model = model.transform(GiveReadableTensorNames()) model = model.transform(PrepareIP("xc7z020clg400-1", 5)) From 0fe2e30cfb7c1e804756651c7b07705bca971b6d Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 9 Feb 2024 14:20:04 +0000 Subject: [PATCH 482/665] [Tests] Update infer data layout test --- tests/transformation/test_infer_data_layouts_cnv.py | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/tests/transformation/test_infer_data_layouts_cnv.py b/tests/transformation/test_infer_data_layouts_cnv.py index 2d7fc54f94..6b6674d661 100644 --- a/tests/transformation/test_infer_data_layouts_cnv.py +++ b/tests/transformation/test_infer_data_layouts_cnv.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (c) 2020, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -45,7 +46,7 @@ from qonnx.transformation.lower_convs_to_matmul import LowerConvsToMatMul from qonnx.util.cleanup import cleanup as qonnx_cleanup -import finn.transformation.fpgadataflow.convert_to_hls_layers as to_hls +import finn.transformation.fpgadataflow.convert_to_hw_layers as to_hw import finn.transformation.streamline.absorb as absorb from finn.transformation.qonnx.convert_qonnx_to_finn import ConvertQONNXtoFINN from finn.transformation.streamline import Streamline @@ -101,10 +102,10 @@ def test_infer_data_layouts_cnv(): model = model.transform(absorb.AbsorbTransposeIntoMultiThreshold()) model = model.transform(ConvertBipolarMatMulToXnorPopcount()) model = model.transform(Streamline()) - model = model.transform(to_hls.InferBinaryMatrixVectorActivation()) - model = model.transform(to_hls.InferQuantizedMatrixVectorActivation()) - model = model.transform(to_hls.InferConvInpGen()) - model = model.transform(to_hls.InferStreamingMaxPool()) + model = model.transform(to_hw.InferBinaryMatrixVectorActivation()) + model = model.transform(to_hw.InferQuantizedMatrixVectorActivation()) + model = model.transform(to_hw.InferConvInpGen()) + model = model.transform(to_hw.InferStreamingMaxPool()) model = model.transform(GiveUniqueNodeNames()) model = model.transform(GiveReadableTensorNames()) model = model.transform(InferDataLayouts()) From ab1395d162e5ffe1a0545f2a768fe32941cad410 Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 9 Feb 2024 14:48:19 +0000 Subject: [PATCH 483/665] [GHA] Delete singularity workflow --- .github/workflows/singularity-quicktest.yml | 47 --------------------- 1 file changed, 47 deletions(-) delete mode 100644 .github/workflows/singularity-quicktest.yml diff --git a/.github/workflows/singularity-quicktest.yml b/.github/workflows/singularity-quicktest.yml deleted file mode 100644 index 4fd8ec38ae..0000000000 --- a/.github/workflows/singularity-quicktest.yml +++ /dev/null @@ -1,47 +0,0 @@ -name: SingularityQuicktest - -on: - pull_request: - branches: [ dev ] - push: - branches: [ dev ] - -jobs: - build_quicktest_singularity: - name: Build and quicktest Singularity container - runs-on: ubuntu-22.04 - steps: - - name: Reclaim storage - run: | - docker image prune -a -f - sudo rm -rf /usr/share/dotnet - sudo rm -rf /usr/local/lib/android - - name: Checkout - uses: actions/checkout@v3 - - name: Set up Docker - uses: docker/setup-buildx-action@v2 - with: - driver: docker - - name: Set up Singularity - run: | - sudo add-apt-repository -y ppa:apptainer/ppa - sudo apt update - sudo apt install -y apptainer - alias singularity="apptainer" - - name: Build Docker image - uses: docker/build-push-action@v4 - with: - file: docker/Dockerfile.finn - context: . - load: true - no-cache: true - tags: finn_docker_export:latest - - name: Build Singularity image - run: | - mkdir $GITHUB_WORKSPACE/singularity_tmp - export APPTAINER_TMPDIR=$GITHUB_WORKSPACE/singularity_tmp - singularity build --disable-cache finn_singularity_image.sif docker-daemon://finn_docker_export:latest - - name: Run quicktest - run: | - export FINN_SINGULARITY=finn_singularity_image.sif - ./run-docker.sh quicktest From 40cfe01c70173e43a6222f229d925d5944fc6958 Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 9 Feb 2024 16:04:36 +0000 Subject: [PATCH 484/665] [Builder/Transform] Update builder and transformations according to new flow --- .../analysis/fpgadataflow/res_estimation.py | 2 +- src/finn/builder/build_dataflow_config.py | 35 +- src/finn/builder/build_dataflow_steps.py | 94 +- .../custom_op/fpgadataflow/streamingfifo.py | 2 +- src/finn/qnn-data/build_dataflow/build.py | 1 + .../specialize_layers_config.json | 30 + .../fpgadataflow/convert_to_hls_layers.py | 1782 ----------------- .../fpgadataflow/create_stitched_ip.py | 6 +- .../fpgadataflow/derive_characteristic.py | 6 +- .../transformation/fpgadataflow/floorplan.py | 2 +- .../transformation/fpgadataflow/insert_dwc.py | 2 +- .../fpgadataflow/insert_fifo.py | 12 +- .../fpgadataflow/insert_tlastmarker.py | 2 +- .../fpgadataflow/set_fifo_depths.py | 25 +- .../fpgadataflow/set_folding.py | 33 +- .../fpgadataflow/specialize_layers.py | 5 - src/finn/transformation/move_reshape.py | 2 +- src/finn/util/pyverilator.py | 2 +- tests/end2end/test_end2end_bnn_pynq.py | 3 - tests/util/test_build_dataflow.py | 1 + 20 files changed, 164 insertions(+), 1883 deletions(-) create mode 100644 src/finn/qnn-data/build_dataflow/specialize_layers_config.json delete mode 100644 src/finn/transformation/fpgadataflow/convert_to_hls_layers.py diff --git a/src/finn/analysis/fpgadataflow/res_estimation.py b/src/finn/analysis/fpgadataflow/res_estimation.py index d48c423b9d..000e1208d7 100644 --- a/src/finn/analysis/fpgadataflow/res_estimation.py +++ b/src/finn/analysis/fpgadataflow/res_estimation.py @@ -72,7 +72,7 @@ def res_estimation_complete(model): inst.set_nodeattr("resType", "lut") res_dict[node.name].append(inst.node_res_estimation()) inst.set_nodeattr("resType", orig_restype) - elif op_type == "ConvolutionInputGenerator": + elif op_type.startswith("ConvolutionInputGenerator"): orig_ramstyle = inst.get_nodeattr("ram_style") res_dict[node.name] = [] inst.set_nodeattr("ram_style", "block") diff --git a/src/finn/builder/build_dataflow_config.py b/src/finn/builder/build_dataflow_config.py index e4fed05731..1b22265a4d 100644 --- a/src/finn/builder/build_dataflow_config.py +++ b/src/finn/builder/build_dataflow_config.py @@ -1,4 +1,5 @@ # Copyright (c) 2020 Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -115,14 +116,15 @@ class VerificationStepType(str, Enum): "step_qonnx_to_finn", "step_tidy_up", "step_streamline", - "step_convert_to_hls", + "step_convert_to_hw", "step_create_dataflow_partition", + "step_specialize_layers", "step_target_fps_parallelization", "step_apply_folding_config", "step_minimize_bit_width", "step_generate_estimate_reports", - "step_hls_codegen", - "step_hls_ipgen", + "step_hw_codegen", + "step_hw_ipgen", "step_set_fifo_depths", "step_create_stitched_ip", "step_measure_rtlsim_performance", @@ -137,17 +139,18 @@ class VerificationStepType(str, Enum): "step_qonnx_to_finn", "step_tidy_up", "step_streamline", - "step_convert_to_hls", + "step_convert_to_hw", "step_create_dataflow_partition", + "step_specialize_layers", "step_target_fps_parallelization", "step_apply_folding_config", "step_minimize_bit_width", "step_generate_estimate_reports", ] -#: List of steps to run for a dataflow build including HLS code generation, but +#: List of steps to run for a dataflow build including HW code generation, but #: without any synthesis. -hls_codegen_dataflow_steps = estimate_only_dataflow_steps + ["step_hls_codegen"] +hw_codegen_dataflow_steps = estimate_only_dataflow_steps + ["step_hw_codegen"] @dataclass_json @@ -170,6 +173,14 @@ class DataflowBuildConfig: #: DataflowOutputType for available options. generate_outputs: List[DataflowOutputType] + #: (Optional) Path to configuration JSON file in which user can specify + #: a preferred implementation style (HLS or RTL) for each node. + #: The SpecializeLayers transformation picks up these settings and if possible + #: fulfills the desired implementation style for each layer by converting the + #: node into its HLS or RTL variant. + #: Will be applied with :py:mod:`qonnx.transformation.general.ApplyConfig` + specialize_layers_config_file: Optional[str] = None + #: (Optional) Path to configuration JSON file. May include parallelization, #: FIFO sizes, RAM and implementation style attributes and so on. #: If the parallelization attributes (PE, SIMD) are part of the config, @@ -230,7 +241,7 @@ class DataflowBuildConfig: mvau_wwidth_max: Optional[int] = 36 #: (Optional) Whether thresholding layers (which implement quantized - #: activations in FINN) will be implemented as stand-alone HLS layers, + #: activations in FINN) will be implemented as stand-alone HW layers, #: instead of being part of MatrixVectorActivation layer. This gives larger #: flexibility, and makes it possible to have runtime-writable thresholds. standalone_thresholds: Optional[bool] = False @@ -277,7 +288,7 @@ class DataflowBuildConfig: #: Only relevant when `auto_fifo_depths = True` large_fifo_mem_style: Optional[LargeFIFOMemStyle] = LargeFIFOMemStyle.AUTO - #: Target clock frequency (in nanoseconds) for Vivado HLS synthesis. + #: Target clock frequency (in nanoseconds) for Vitis HLS synthesis. #: e.g. `hls_clk_period_ns=5.0` will target a 200 MHz clock. #: If not specified it will default to synth_clk_period_ns hls_clk_period_ns: Optional[float] = None @@ -285,10 +296,6 @@ class DataflowBuildConfig: #: Which memory mode will be used for compute layers default_mem_mode: Optional[ComputeEngineMemMode] = ComputeEngineMemMode.DECOUPLED - #: Force inference of RTL ConvolutionInputGenerator over HLS implementation - #: If set to False, falls back to the default behavior of InferConvInpGen() - force_rtl_conv_inp_gen: Optional[bool] = False - #: Which Vitis platform will be used. #: Only relevant when `shell_flow_type = ShellFlowType.VITIS_ALVEO` #: e.g. "xilinx_u250_xdma_201830_2" @@ -347,8 +354,8 @@ class DataflowBuildConfig: #: Override the number of inputs for rtlsim performance measurement. rtlsim_batch_size: Optional[int] = 1 - #: If set to True, FIFOs and DWCs with impl_style=vivado will be kept during - #: rtlsim, otherwise they will be replaced by HLS implementations. + #: If set to True, FIFOs with impl_style=vivado will be kept during + #: rtlsim, otherwise they will be replaced by RTL implementations. rtlsim_use_vivado_comps: Optional[bool] = True def _resolve_hls_clk_period(self): diff --git a/src/finn/builder/build_dataflow_steps.py b/src/finn/builder/build_dataflow_steps.py index 54ba7e4ea1..d031e971f1 100644 --- a/src/finn/builder/build_dataflow_steps.py +++ b/src/finn/builder/build_dataflow_steps.py @@ -1,4 +1,5 @@ # Copyright (c) 2020 Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -52,7 +53,7 @@ from qonnx.util.config import extract_model_config_to_json from shutil import copy -import finn.transformation.fpgadataflow.convert_to_hls_layers as to_hls +import finn.transformation.fpgadataflow.convert_to_hw_layers as to_hw import finn.transformation.streamline.absorb as absorb from finn.analysis.fpgadataflow.dataflow_performance import dataflow_performance from finn.analysis.fpgadataflow.exp_cycles_per_layer import exp_cycles_per_layer @@ -108,6 +109,7 @@ SplitLargeFIFOs, ) from finn.transformation.fpgadataflow.set_folding import SetFolding +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers from finn.transformation.fpgadataflow.synth_ooc import SynthOutOfContext from finn.transformation.fpgadataflow.vitis_build import VitisBuild from finn.transformation.move_reshape import RemoveCNVtoFCFlatten @@ -216,23 +218,15 @@ def verify_step( def prepare_for_stitched_ip_rtlsim(verify_model, cfg): if not cfg.rtlsim_use_vivado_comps: need_restitch = False - # switch impl_style=vivado components to rtl/hls + # switch impl_style=vivado components to rtl # StreamingFIFO must have impl_style=rtl - for fifo_layer in verify_model.get_nodes_by_op_type("StreamingFIFO"): + for fifo_layer in verify_model.get_nodes_by_op_type("StreamingFIFO_rtl"): inst = getCustomOp(fifo_layer) if inst.get_nodeattr("impl_style") != "rtl": inst.set_nodeattr("impl_style", "rtl") inst.set_nodeattr("code_gen_dir_ipgen", "") inst.set_nodeattr("ipgen_path", "") need_restitch = True - # StreamingDataWidthConverter must have impl_style=hls - for dwc_layer in verify_model.get_nodes_by_op_type("StreamingDataWidthConverter_Batch"): - inst = getCustomOp(dwc_layer) - if inst.get_nodeattr("impl_style") != "hls": - inst.set_nodeattr("impl_style", "hls") - inst.set_nodeattr("code_gen_dir_ipgen", "") - inst.set_nodeattr("ipgen_path", "") - need_restitch = True # if we've made alterations to the model, need to do some re-prep if need_restitch: print("Need to regen/re-stitch some IP for STITCHED_IP_RTLSIM") @@ -336,43 +330,43 @@ def step_streamline(model: ModelWrapper, cfg: DataflowBuildConfig): return model -def step_convert_to_hls(model: ModelWrapper, cfg: DataflowBuildConfig): - """Convert eligible nodes to `HLSCustomOp` subclasses that represent HLS - layers. Which nodes and particular configurations can be converted to HLS - is limited, see the source code of the `convert_to_hls` module for more.""" +def step_convert_to_hw(model: ModelWrapper, cfg: DataflowBuildConfig): + """Convert eligible nodes to `HWCustomOp` subclasses that represent HW + layers. Which nodes and particular configurations can be converted to HW + is limited, see the source code of the `convert_to_hw` module for more. + In the end am empty json file is created which can be used to set user specific + preferred implementation styles for each node.""" mem_mode = cfg.default_mem_mode.value if cfg.standalone_thresholds: # doing this first causes all threshold layers to be standalone - model = model.transform(to_hls.InferThresholdingLayer()) + model = model.transform(to_hw.InferThresholdingLayer()) # needed for bipolar MatMul layers - model = model.transform(to_hls.InferBinaryMatrixVectorActivation(mem_mode)) + model = model.transform(to_hw.InferBinaryMatrixVectorActivation(mem_mode)) # needed for non-bipolar MatMul layers - model = model.transform(to_hls.InferQuantizedMatrixVectorActivation(mem_mode)) + model = model.transform(to_hw.InferQuantizedMatrixVectorActivation(mem_mode)) # TopK to LabelSelect - model = model.transform(to_hls.InferLabelSelectLayer()) + model = model.transform(to_hw.InferLabelSelectLayer()) # input quantization (if any) as standalone threshold - model = model.transform(to_hls.InferThresholdingLayer()) + model = model.transform(to_hw.InferThresholdingLayer()) # needed for convolutions -- TODO always exec? need_conv = len(model.get_nodes_by_op_type("Im2Col")) > 0 if need_conv: - if cfg.force_rtl_conv_inp_gen: - model = model.transform(to_hls.InferConvInpGen(use_rtl_variant=True)) - else: - model = model.transform(to_hls.InferConvInpGen()) - model = model.transform(to_hls.InferStreamingMaxPool()) + model = model.transform(to_hw.InferConvInpGen()) + model = model.transform(to_hw.InferStreamingMaxPool()) model = model.transform(RemoveCNVtoFCFlatten()) # get rid of Tranpose -> Tranpose identity seq model = model.transform(absorb.AbsorbConsecutiveTransposes()) model = model.transform(GiveUniqueNodeNames()) model = model.transform(InferDataLayouts()) + return model def step_create_dataflow_partition(model: ModelWrapper, cfg: DataflowBuildConfig): - """Separate consecutive groups of HLSCustomOp nodes into StreamingDataflowPartition + """Separate consecutive groups of HWCustomOp nodes into StreamingDataflowPartition nodes, which point to a separate ONNX file. Dataflow accelerator synthesis - can only be performed on those HLSCustomOp sub-graphs.""" + can only be performed on those HWCustomOp sub-graphs.""" parent_model = model.transform( CreateDataflowPartition( @@ -387,6 +381,31 @@ def step_create_dataflow_partition(model: ModelWrapper, cfg: DataflowBuildConfig if cfg.save_intermediate_models: parent_model.save(cfg.output_dir + "/intermediate_models/dataflow_parent.onnx") model = ModelWrapper(dataflow_model_filename) + + # create a configuration json file that can be used to set the specialize layer config + attrs = [ + "preferred_impl_style", + ] + extract_model_config_to_json( + model, cfg.output_dir + "/template_specialize_layers_config.json", attrs + ) + + return model + + +def step_specialize_layers(model: ModelWrapper, cfg: DataflowBuildConfig): + """Convert HW nodes to either an HLS or RTL variant of the node. HW nodes + get converted either based on pre-determined rules (details can be found + in `specialize_layers` source code) or the user provides a configuration file + which contains the desired setting. If the user preference cannot be fulfilled, + a warning will be printed and the implementation style will be set to a default.""" + + if cfg.specialize_layers_config_file is not None: + model = model.transform(GiveUniqueNodeNames()) + model = model.transform(ApplyConfig(cfg.specialize_layers_config_file)) + model = model.transform(SpecializeLayers()) + model = model.transform(InferShapes()) + model = model.transform(InferDataTypes()) return model @@ -482,16 +501,17 @@ def step_minimize_bit_width(model: ModelWrapper, cfg: DataflowBuildConfig): return model -def step_hls_codegen(model: ModelWrapper, cfg: DataflowBuildConfig): - "Generate Vivado HLS code to prepare HLSCustomOp nodes for IP generation." +def step_hw_codegen(model: ModelWrapper, cfg: DataflowBuildConfig): + """Generate Vitis HLS code to prepare HLSBackend nodes for IP generation. + And fills RTL templates for RTLBackend nodes.""" model = model.transform(PrepareIP(cfg._resolve_fpga_part(), cfg._resolve_hls_clk_period())) return model -def step_hls_ipgen(model: ModelWrapper, cfg: DataflowBuildConfig): - """Run Vivado HLS synthesis on generated code for HLSCustomOp nodes, - in order to generate IP blocks.""" +def step_hw_ipgen(model: ModelWrapper, cfg: DataflowBuildConfig): + """Run Vitis HLS synthesis on generated code for HLSBackend nodes, + in order to generate IP blocks. For RTL nodes this step does not do anything.""" model = model.transform(HLSSynthIP()) model = model.transform(ReplaceVerilogRelPaths()) @@ -519,6 +539,7 @@ def step_set_fifo_depths(model: ModelWrapper, cfg: DataflowBuildConfig): if cfg.auto_fifo_depths: if cfg.auto_fifo_strategy == "characterize": model = model.transform(InsertDWC()) + model = model.transform(SpecializeLayers()) model = model.transform(GiveUniqueNodeNames()) model = model.transform( PrepareIP(cfg._resolve_fpga_part(), cfg._resolve_hls_clk_period()) @@ -536,6 +557,7 @@ def step_set_fifo_depths(model: ModelWrapper, cfg: DataflowBuildConfig): create_shallow_fifos=True, ) ) + model = model.transform(SpecializeLayers()) model = model.transform(GiveUniqueNodeNames()) model = model.transform(GiveReadableTensorNames()) elif cfg.auto_fifo_strategy == "largefifo_rtlsim": @@ -566,6 +588,7 @@ def step_set_fifo_depths(model: ModelWrapper, cfg: DataflowBuildConfig): # need to make sure all FIFOs are created so that their depth can be # set by ApplyConfig, so create_shallow_fifos=True model = model.transform(InsertFIFO(create_shallow_fifos=True)) + model = model.transform(SpecializeLayers()) model = model.transform(GiveUniqueNodeNames()) model = model.transform(GiveReadableTensorNames()) if cfg.folding_config_file is not None: @@ -823,14 +846,15 @@ def step_deployment_package(model: ModelWrapper, cfg: DataflowBuildConfig): "step_qonnx_to_finn": step_qonnx_to_finn, "step_tidy_up": step_tidy_up, "step_streamline": step_streamline, - "step_convert_to_hls": step_convert_to_hls, + "step_convert_to_hw": step_convert_to_hw, + "step_specialize_layers": step_specialize_layers, "step_create_dataflow_partition": step_create_dataflow_partition, "step_target_fps_parallelization": step_target_fps_parallelization, "step_apply_folding_config": step_apply_folding_config, "step_minimize_bit_width": step_minimize_bit_width, "step_generate_estimate_reports": step_generate_estimate_reports, - "step_hls_codegen": step_hls_codegen, - "step_hls_ipgen": step_hls_ipgen, + "step_hw_codegen": step_hw_codegen, + "step_hw_ipgen": step_hw_ipgen, "step_set_fifo_depths": step_set_fifo_depths, "step_create_stitched_ip": step_create_stitched_ip, "step_measure_rtlsim_performance": step_measure_rtlsim_performance, diff --git a/src/finn/custom_op/fpgadataflow/streamingfifo.py b/src/finn/custom_op/fpgadataflow/streamingfifo.py index b55af929ed..1556575b00 100644 --- a/src/finn/custom_op/fpgadataflow/streamingfifo.py +++ b/src/finn/custom_op/fpgadataflow/streamingfifo.py @@ -104,7 +104,7 @@ def get_verilog_top_module_intf_names(self): def get_normal_input_shape(self, ind=0): depth = self.get_adjusted_depth() - assert depth >= 2, """Depth is too low""" + assert depth >= 1, """Depth is too low""" if depth > 256 and self.get_nodeattr("impl_style") == "rtl": warnings.warn("Depth is high, set between 2 and 256 for efficient SRL implementation") return self.get_nodeattr("normal_shape") diff --git a/src/finn/qnn-data/build_dataflow/build.py b/src/finn/qnn-data/build_dataflow/build.py index 0d9d55a086..13d58d2c91 100644 --- a/src/finn/qnn-data/build_dataflow/build.py +++ b/src/finn/qnn-data/build_dataflow/build.py @@ -43,6 +43,7 @@ mvau_wwidth_max=10000, # can specify detailed folding/FIFO/etc config with: # folding_config_file="folding_config.json", + specialize_layers_config_file="specialize_layers_config.json", synth_clk_period_ns=10.0, board=platform_name, shell_flow_type=build_cfg.ShellFlowType.VIVADO_ZYNQ, diff --git a/src/finn/qnn-data/build_dataflow/specialize_layers_config.json b/src/finn/qnn-data/build_dataflow/specialize_layers_config.json new file mode 100644 index 0000000000..4fc37896db --- /dev/null +++ b/src/finn/qnn-data/build_dataflow/specialize_layers_config.json @@ -0,0 +1,30 @@ +{ + "Defaults": {}, + "Thresholding_0": { + "preferred_impl_style": "hls" + }, + "MatrixVectorActivation_0": { + "preferred_impl_style": "hls" + }, + "Thresholding_1": { + "preferred_impl_style": "" + }, + "MatrixVectorActivation_1": { + "preferred_impl_style": "" + }, + "Thresholding_2": { + "preferred_impl_style": "" + }, + "MatrixVectorActivation_2": { + "preferred_impl_style": "" + }, + "Thresholding_3": { + "preferred_impl_style": "rtl" + }, + "MatrixVectorActivation_3": { + "preferred_impl_style": "" + }, + "LabelSelect_0": { + "preferred_impl_style": "hls" + } +} diff --git a/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py b/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py deleted file mode 100644 index ef02453498..0000000000 --- a/src/finn/transformation/fpgadataflow/convert_to_hls_layers.py +++ /dev/null @@ -1,1782 +0,0 @@ -# Copyright (c) 2020, Xilinx -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# * Redistributions of source code must retain the above copyright notice, this -# list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# * Neither the name of FINN nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - -import numpy as np -import qonnx.core.data_layout as DataLayout -import warnings -from onnx import TensorProto, helper -from qonnx.core.datatype import DataType -from qonnx.custom_op.registry import getCustomOp -from qonnx.transformation.base import Transformation -from qonnx.transformation.general import SortGraph -from qonnx.transformation.infer_datatypes import InferDataTypes -from qonnx.transformation.infer_shapes import InferShapes -from qonnx.util.basic import get_by_name -from qonnx.util.onnx import nchw_to_nhwc - - -class InferConvInpGen(Transformation): - """Convert Im2Col layers to ConvolutionInputGenerator layers.""" - - def __init__(self, use_rtl_variant=False): - super().__init__() - self.use_rtl_variant = use_rtl_variant - - def apply(self, model): - graph = model.graph - node_ind = 0 - graph_modified = False - for n in graph.node: - node_ind += 1 - if n.op_type == "Im2Col": - i2c_input = n.input[0] - i2c_output = n.output[0] - i2c_in_shape = model.get_tensor_shape(i2c_input) - i2c_out_shape = model.get_tensor_shape(i2c_output) - dt = model.get_tensor_datatype(i2c_input) - if not dt.is_integer(): - warnings.warn("%s : Input is not int. Can't infer ConvInpGen." % n.name) - continue - i2c_inst = getCustomOp(n) - stride_h, stride_w = i2c_inst.get_nodeattr("stride") - k_h, k_w = i2c_inst.get_nodeattr("kernel_size") - pad_attr = i2c_inst.get_nodeattr("pad_amount") - pad_h = pad_attr[0] + pad_attr[2] - pad_w = pad_attr[1] + pad_attr[3] - dilation_h, dilation_w = i2c_inst.get_nodeattr("dilations") - # temporary checks until non-square conv support is finalized - pad_val = i2c_inst.get_nodeattr("pad_value") - depthwise = i2c_inst.get_nodeattr("depthwise") - ifm_ch = i2c_in_shape[-1] - ifm_dim_h = i2c_in_shape[1] - ifm_dim_w = i2c_in_shape[2] - ofm_dim_h = i2c_out_shape[1] - ofm_dim_w = i2c_out_shape[2] - - # default params for ConvolutionInputGenerator - ConvInpGen_node_idx = node_ind - ConvInpGen_input = i2c_input - ConvInpGen_idim_h = ifm_dim_h - ConvInpGen_idim_w = ifm_dim_w - - if pad_h > 0 or pad_w > 0: - # if padding enabled, ensure pad_val supported by DataType - # assert dt.allowed(pad_val),"""FMPadding_Batch DataType - # must support pad_val""" - assert pad_val == 0, ( - "%s : FMPadding_Batch doesn't currently support pad_val!= 0" % n.name - ) - - odim_padding_h = ifm_dim_h + pad_h - odim_padding_w = ifm_dim_w + pad_w - - padding_out = helper.make_tensor_value_info( - model.make_new_valueinfo_name(), - TensorProto.FLOAT, - (1, odim_padding_h, odim_padding_w, ifm_ch), - ) - graph.value_info.append(padding_out) - padding_out = padding_out.name - model.set_tensor_datatype(padding_out, dt) - - ConvInpGen_node_idx += 1 - ConvInpGen_input = padding_out - ConvInpGen_idim_h = odim_padding_h - ConvInpGen_idim_w = odim_padding_w - - padding_optype = "FMPadding_rtl" if self.use_rtl_variant else "FMPadding_Batch" - - padding_node = helper.make_node( - padding_optype, - [i2c_input], - [padding_out], - domain="finn.custom_op.fpgadataflow", - backend="fpgadataflow", - ImgDim=[ifm_dim_h, ifm_dim_w], - Padding=pad_attr, - NumChannels=ifm_ch, - inputDataType=dt.name, - SIMD=ifm_ch, - name="FMPadding_Batch_" + n.name, - ) - graph.node.insert(node_ind, padding_node) - - is_kernel_pointwise = k_h == 1 and k_w == 1 - is_square_image = ConvInpGen_idim_h == ConvInpGen_idim_w - is_square_kernel = k_h == k_w - is_equal_stride = stride_h == stride_w - is_1d_convolution = (k_h == 1 and k_w > 1 and ifm_dim_h == 1) or ( - k_h > 1 and k_w == 1 and ifm_dim_w == 1 - ) - - if self.use_rtl_variant: - ConvInpGen_node = helper.make_node( - "ConvolutionInputGenerator_rtl", - [ConvInpGen_input], - [i2c_output], - domain="finn.custom_op.fpgadataflow", - backend="fpgadataflow", - ConvKernelDim=[k_h, k_w], - IFMChannels=ifm_ch, - IFMDim=[ConvInpGen_idim_h, ConvInpGen_idim_w], - OFMDim=[ofm_dim_h, ofm_dim_w], - SIMD=ifm_ch, - M=1, - parallel_window=0, - Stride=[stride_h, stride_w], - Dilation=[dilation_h, dilation_w], - inputDataType=dt.name, - outputDataType=dt.name, - depthwise=depthwise, - name="ConvolutionInputGenerator_rtl_" + n.name, - ) - graph.node.insert(ConvInpGen_node_idx, ConvInpGen_node) - else: - # Ensure that only supported HLS nodes are inserted - if (stride_h > 1 or stride_w > 1) and is_kernel_pointwise: - downsample_1D = (ifm_dim_h == 1) or (ifm_dim_w == 1) - is1D_unitx = ifm_dim_w == 1 - downsample_2D = (not downsample_1D) and is_square_image and is_equal_stride - if not (downsample_1D or downsample_2D): - warnings.warn(f"Couldn't infer Downsample from {n.name},check config.") - continue - ConvInpGen_idim = max(ConvInpGen_idim_h, ConvInpGen_idim_w) - stride = max(stride_h, stride_w) - # create DownSampler node - ConvInpGen_node = helper.make_node( - "DownSampler", - [ConvInpGen_input], - [i2c_output], - domain="finn.custom_op.fpgadataflow", - backend="fpgadataflow", - ImgDim=ConvInpGen_idim, - NumChannels=ifm_ch, - SIMD=ifm_ch, - Stride=stride, - inputDataType=dt.name, - name="DownSampler_" + n.name, - is1D=downsample_1D, - is1D_unitx=is1D_unitx, - ) - graph.node.insert(ConvInpGen_node_idx, ConvInpGen_node) - else: - # create equivalent ConvolutionInputGenerator node - if is_square_image and is_square_kernel: # square images and square kernels - assert is_equal_stride, ( - """%s: Non-equal strides along different axes is not supported - for (non-)square convolutions""" - % n.name - ) - assert dilation_h == 1 and dilation_w == 1, ( - """%s: Dilation value != 1 is not supported - for square convolutions""" - % n.name - ) - ConvInpGen_node = helper.make_node( - "ConvolutionInputGenerator", - [ConvInpGen_input], - [i2c_output], - domain="finn.custom_op.fpgadataflow", - backend="fpgadataflow", - ConvKernelDim=[k_h, k_w], - IFMChannels=ifm_ch, - IFMDim=[ConvInpGen_idim_h, ConvInpGen_idim_w], - OFMDim=[ofm_dim_h, ofm_dim_w], - SIMD=ifm_ch, - Stride=[stride_h, stride_w], - Dilation=[dilation_h, dilation_w], - inputDataType=dt.name, - outputDataType=dt.name, - depthwise=depthwise, - name="ConvolutionInputGenerator_" + n.name, - ) - else: # 1D images and/or kernels - assert is_1d_convolution, ( - """%s: ConvolutionInputGenerator1D works only - for 1D convs""" - % n.name - ) - if dilation_h > 1 or dilation_w > 1: - assert depthwise == 1, ( - """%s: Dilation value > 1 is only supported for - 1D depthwise separable convolutions""" - % n.name - ) - ConvInpGen_node = helper.make_node( - "ConvolutionInputGenerator1D", - [ConvInpGen_input], - [i2c_output], - domain="finn.custom_op.fpgadataflow", - backend="fpgadataflow", - ConvKernelDim=[k_h, k_w], - IFMChannels=ifm_ch, - IFMDim=[ConvInpGen_idim_h, ConvInpGen_idim_w], - OFMDim=[ofm_dim_h, ofm_dim_w], - SIMD=ifm_ch, - Stride=[stride_h, stride_w], - Dilation=[dilation_h, dilation_w], - inputDataType=dt.name, - outputDataType=dt.name, - depthwise=depthwise, - name="ConvolutionInputGenerator1D_" + n.name, - ) - graph.node.insert(ConvInpGen_node_idx, ConvInpGen_node) - # remove old nodes - graph.node.remove(n) - graph_modified = True - if graph_modified: - model = model.transform(InferShapes()) - model = model.transform(InferDataTypes()) - return (model, graph_modified) - - -class InferUpsample(Transformation): - """ - Convert Upsample and Resize nodes to layers to UpsampleNearestNeighbour_Batch nodes. - """ - - def apply(self, model): - graph = model.graph - node_ind = 0 - graph_modified = False - for n in graph.node: - node_ind += 1 - if n.op_type == "Upsample" or n.op_type == "Resize": - # Extract mode and scales and input shape - mode = get_by_name(n.attribute, "mode").s.decode("ascii") - if n.op_type == "Upsample": - scales = model.get_initializer(n.input[1]) - else: - scales = model.get_initializer(n.input[2]) - in_shape = model.get_tensor_shape(n.input[0]) - - dt = model.get_tensor_datatype(n.input[0]) - if not dt.is_integer(): - warnings.warn( - "%s: Input not int. Can't infer UpsampleNearestNeighbour." % n.name - ) - continue - - if model.get_tensor_layout(n.input[0]) != DataLayout.NHWC: - warnings.warn( - "%s: Input not NHWC. Can't infer UpsampleNearestNeighbour." % n.name - ) - continue - - # Check that the parameters are okay - assert mode == "nearest", ( - "%s: Upsampling is only supported for the mode nearest." % n.name - ) - assert len(in_shape) == 4, "Upsampling is only supported for 4D inputs." - assert scales.shape == (4,), ( - "%s: Upsampling is only supported for 4D scales." % n.name - ) - assert (scales >= 1).all(), ( - n.name + ": Upsampling is only supported for scales " - "which are larger or equal 1 in all dimensions." - ) - - # Assumes nhwc layout for scales and input - is_scale_square_2d = scales[1] == scales[2] - is_scale_1d = scales[1] > 1 and scales[2] == 1 - assert is_scale_square_2d or is_scale_1d, ( - "%s: Upsampling only supported for 1D H, or 2D square scaling" % n.name - ) - assert scales[0] == scales[3] == 1, ( - n.name + ": Upsampling is only supported for scales with " - "the first and last dimensions being 1 in NHWC." - ) - spatial_scale = scales[1] - assert spatial_scale == int(spatial_scale), ( - "%s: Upsampling is only supported for integer scales." % n.name - ) - is_shape_square_2d = in_shape[1] == in_shape[2] - is_shape_1d = in_shape[1] > 1 and in_shape[2] == 1 - - assert is_shape_square_2d or is_shape_1d, ( - "%s: Upsampling is only supported for 1D H or 2D square inputs." % n.name - ) - - # Extract information for HLS node - IFMDim = in_shape[1] - OFMDim = int(round(in_shape[1] * spatial_scale)) - NumChannels = in_shape[-1] - numInputVectors = in_shape[0] - inputDataType = dt.name - dim_mode = 0 if is_shape_square_2d else 1 - - # Insert the HLSCustomOp node - Upsample_HLS_node = helper.make_node( - "UpsampleNearestNeighbour_Batch", - [n.input[0]], - [n.output[0]], - domain="finn.custom_op.fpgadataflow", - backend="fpgadataflow", - OFMDim=OFMDim, - IFMDim=IFMDim, - NumChannels=NumChannels, - inputDataType=inputDataType, - numInputVectors=numInputVectors, - DimMode=dim_mode, - name="UpsampleNearestNeighbour_Batch_" + n.name, - ) - - # Remove the old node - graph.node.insert(node_ind, Upsample_HLS_node) - # remove old nodes - graph.node.remove(n) - graph_modified = True - return (model, graph_modified) - - -class InferStreamingMaxPool(Transformation): - """Convert MaxPoolNHWC layers to StreamingMaxPool layers.""" - - def apply(self, model): - graph = model.graph - node_ind = 0 - graph_modified = False - for node in graph.node: - node_ind += 1 - if node.op_type == "MaxPoolNHWC": - mp_input = node.input[0] - mp_output = node.output[0] - mp_in_shape = model.get_tensor_shape(mp_input) - # mp_out_shape = model.get_tensor_shape(mp_output) - dt = model.get_tensor_datatype(mp_input) - mp_inst = getCustomOp(node) - k_h, k_w = mp_inst.get_nodeattr("kernel_shape") - ifm_ch = mp_in_shape[-1] - ifm_dim_h = mp_in_shape[1] - ifm_dim_w = mp_in_shape[2] - pe = 1 - ceil_mode = mp_inst.get_nodeattr("ceil_mode") - is_1d = (ifm_dim_h == 1 and k_h == 1) or (ifm_dim_w == 1 and k_w == 1) - is_divisable = (ifm_dim_h % k_h == 0) or (ifm_dim_w % k_w == 0) - is_bipolar = dt == DataType["BIPOLAR"] - pass_1d = is_1d and (not is_bipolar) - pass_2d = (not is_1d) and is_divisable - if pass_1d or pass_2d: - # create equivalent StreamingMaxPool_Batch node - new_node = helper.make_node( - "StreamingMaxPool_Batch", - [mp_input], - [mp_output], - domain="finn.custom_op.fpgadataflow", - backend="fpgadataflow", - PoolDim=(k_h, k_w), - NumChannels=ifm_ch, - ImgDim=(ifm_dim_h, ifm_dim_w), - dataType=dt.name, - PE=pe, - CeilMode=ceil_mode, - name="StreamingMaxPool_Batch_" + node.name, - ) - graph.node.insert(node_ind, new_node) - # remove old nodes - graph.node.remove(node) - graph_modified = True - else: - warnings.warn(node.name + ": could not convert to HLS") - if graph_modified: - model = model.transform(InferShapes()) - model = model.transform(InferDataTypes()) - return (model, graph_modified) - - -class InferPool_Batch(Transformation): - """If kernel_shape > strides, replace Pool layer with with of Im2col - + pool(with kernel_shape == strides), plus Transpose layers to keep the original - data layout.""" - - def apply(self, model): - graph = model.graph - node_ind = 0 - graph_modified = False - for node in graph.node: - node_ind += 1 - if node.op_type in ["MaxPool", "QuantAvgPool2d", "MaxPoolNHWC"]: - node_input = node.input[0] - ishape = model.get_tensor_shape(node_input) - node_output = node.output[0] - idt = model.get_tensor_datatype(node_input) - oshape = model.get_tensor_shape(node_output) - # only support 4D input tensors (1D convs need extra dummy dim) - if len(ishape) != 4: - continue - - # extract pool parameters - if node.op_type == "MaxPool": - kh, kw = list(get_by_name(node.attribute, "kernel_shape").ints) - sh, sw = list(get_by_name(node.attribute, "strides").ints) - dlayout = "NCHW" - elif node.op_type == "QuantAvgPool2d": - inst = getCustomOp(node) - # QuantAvgPool2d has a single scalar attribute - # for kernel size and stride (implicit square) - kh = kw = inst.get_nodeattr("kernel") - sh = sw = inst.get_nodeattr("stride") - dlayout = inst.get_nodeattr("data_layout") - elif node.op_type == "MaxPoolNHWC": - inst = getCustomOp(node) - kh, kw = inst.get_nodeattr("kernel_shape") - sh, sw = inst.get_nodeattr("strides") - dlayout = "NHWC" - try: - pad = list(get_by_name(node.attribute, "pads").ints) - except AttributeError: - pad = [0, 0, 0, 0] - - if not idt.is_integer(): - continue - - if (kh < sh) or (kw < sw): - # TODO check/implement swg support - continue - - odt = model.get_tensor_datatype(node_output) - - if dlayout == "NCHW": - _, ifm_ch, ifm_h, ifm_w = ishape - _, ofm_ch, ofm_h, ofm_w = oshape - elif dlayout == "NHWC": - _, ifm_h, ifm_w, ifm_ch = ishape - _, ofm_h, ofm_w, ofm_ch = oshape - else: - raise Exception("Unknown dlayout: " + str(dlayout)) - - # if data layout NCHW, we need transpose nodes surrounding - # the hls layer - if dlayout == "NCHW": - # create new intermediate values - inp_trans_out = helper.make_tensor_value_info( - model.make_new_valueinfo_name(), - TensorProto.FLOAT, - (1, ifm_h, ifm_w, ifm_ch), # NHWC - ) - graph.value_info.append(inp_trans_out) - inp_trans_out = inp_trans_out.name - model.set_tensor_datatype(inp_trans_out, idt) - - pool_output = helper.make_tensor_value_info( - model.make_new_valueinfo_name(), - TensorProto.FLOAT, - (1, ofm_h, ofm_w, ofm_ch), - ) - graph.value_info.append(pool_output) - pool_output = pool_output.name - # model.set_tensor_datatype(pool_output, odt) - - im2col_out = helper.make_tensor_value_info( - model.make_new_valueinfo_name(), - TensorProto.FLOAT, - (1, ofm_h, ofm_w, ifm_ch * kh * kw), - ) - graph.value_info.append(im2col_out) - im2col_out = im2col_out.name - model.set_tensor_datatype(im2col_out, idt) - - # create new nodes - if dlayout == "NCHW": - # NCHW -> NHWC - inp_trans_node = helper.make_node( - "Transpose", [node_input], [inp_trans_out], perm=[0, 2, 3, 1] - ) - im2col_in = inp_trans_out - else: - im2col_in = node_input - pool_output = node_output - - accum_bits = 0 - pool_size_param = 0 # will be overridden if neededs - pad_value = 0 - if node.op_type in ["MaxPool", "MaxPoolNHWC"]: - pool_fxn = "MaxPool" - odt = idt - pad_value = idt.min() - elif node.op_type == "QuantAvgPool2d": - assert odt.is_integer(), """Output data type for QuantAvgPool2d - needs to be integer""" - assert all(x == 0 for x in pad), "Padding is not supported for QuantAvgPool2d" - inst = getCustomOp(node) - pool_fxn = "QuantAvgPool" - pool_size_param = inst.get_shifts() - accum_bits = inst.get_accum_size() - - else: - raise Exception( - "pad_value and pool_fxn not configured for {}".format(node.op_type) - ) - - # format input tensor - im2col_node = helper.make_node( - "Im2Col", - [im2col_in], - [im2col_out], - domain="qonnx.custom_op.general", - stride=[sh, sw], - kernel_size=[kh, kw], - pad_amount=pad, - pad_value=pad_value, - depthwise=1, - input_shape="(1,{},{},{})".format(ifm_h, ifm_w, ifm_ch), - name="Im2Col_" + node.name, - ) - - # Warning PE has to be equal to ifm_ch until Im2Col is replaced by - # ConvolutionInputGenerator with depthwise=1. - # For other settings the output will be incorrect due to incorrect input - # data layout - pool_node = helper.make_node( - "Pool_Batch", - [im2col_out], - [pool_output], - domain="finn.custom_op.fpgadataflow", - backend="fpgadataflow", - InputDataType=idt.name, - OutputDataType=odt.name, - Channels=ifm_ch, - PE=ifm_ch, - KernelSize=[kh, kw], - Function=pool_fxn, - OutImgDims=[ofm_h, ofm_w], - AccumBits=accum_bits, - Size=pool_size_param, - BatchSize=1, - name="Pool_Batch_" + node.name, - ) - - if dlayout == "NCHW": - # NHWC -> NCHW - out_trans_node = helper.make_node( - "Transpose", [pool_output], [node_output], perm=[0, 3, 1, 2] - ) - - # insert nodes where the conv is to preserve topological ordering - if dlayout == "NCHW": - graph.node.insert(node_ind, inp_trans_node) - graph.node.insert(node_ind + 1, im2col_node) - graph.node.insert(node_ind + 2, pool_node) - graph.node.insert(node_ind + 3, out_trans_node) - else: - graph.node.insert(node_ind, im2col_node) - graph.node.insert(node_ind + 1, pool_node) - # remove old node - graph.node.remove(node) - graph_modified = True - - if graph_modified: - model = model.transform(InferShapes()) - model = model.transform(InferDataTypes()) - return (model, graph_modified) - - -class InferBinaryMatrixVectorActivation(Transformation): - """Convert XnorPopcountMatMul layers to - MatrixVectorActivation layers. Any immediately following MultiThreshold - layers will also be absorbed into the MVTU.""" - - def __init__(self, mem_mode="const"): - super().__init__() - self.mem_mode = mem_mode - - def apply(self, model): - graph = model.graph - node_ind = 0 - graph_modified = False - for n in graph.node: - node_ind += 1 - if n.op_type == "XnorPopcountMatMul": - mm_input = n.input[0] - mm_weight = n.input[1] - mm_output = n.output[0] - mm_in_shape = model.get_tensor_shape(mm_input) - mm_out_shape = model.get_tensor_shape(mm_output) - assert model.get_tensor_datatype(mm_input) == DataType["BINARY"], ( - n.name - + """: First - input for xnorpopcount is not set to FINN DataType BINARY.""" - ) - assert model.get_tensor_datatype(mm_weight) == DataType["BINARY"], ( - n.name - + """: Second - input (weights) for xnorpopcount is not set to FINN DataType BINARY.""" - ) - idt = DataType["BINARY"] - wdt = DataType["BINARY"] - mm_output = n.output[0] - W = model.get_initializer(mm_weight) - # extract weight shape, note that ONNX and finn-hlslib - # make different assumptions about dim order here - # ONNX assumes W has (in, out) shape - # finn-hlslib assumes W has (out, in) shape - mh = int(W.shape[1]) - mw = int(W.shape[0]) - # create node with no parallelization first - pe = 1 - simd = 1 - wmem = mw * mh // (pe * simd) - assert mw * mh == wmem * pe * simd, ( - n.name - + """: Requirement (MW * MH) divisiable by - (WMEM * PE * SIMD) is violated.""" - ) - # see if we have any following thresholds - consumer = model.find_consumer(mm_output) - if consumer is not None and consumer.op_type == "MultiThreshold": - # TODO ensure integer thresholds? - # create MVTU (i.e. including activation) - mt_output = consumer.output[0] - mt_out_shape = model.get_tensor_shape(mt_output) - mt_thres = consumer.input[1] - T = model.get_initializer(mt_thres) - assert T.shape[0] == 1 or T.shape[0] == mh, ( - consumer.name - + """: First dimension of - thresholds neither 1 nor MH.""" - ) - odt = model.get_tensor_datatype(mt_output) - if odt.bitwidth() == 1: - # covers both bipolar and binary - actval = 0 - else: - actval = odt.min() - model.set_tensor_shape(mm_input, mm_in_shape) - model.set_tensor_shape(mt_output, mt_out_shape) - # create and insert new MatrixVectorActivation node - new_node = helper.make_node( - "MatrixVectorActivation", - [mm_input, mm_weight, mt_thres], - [mt_output], - domain="finn.custom_op.fpgadataflow", - backend="fpgadataflow", - MW=mw, - MH=mh, - SIMD=simd, - PE=pe, - inputDataType=idt.name, - weightDataType=wdt.name, - outputDataType=odt.name, - ActVal=actval, - binaryXnorMode=1, - noActivation=0, - numInputVectors=list(mm_in_shape[:-1]), - mem_mode=self.mem_mode, - name=n.name, - ) - graph.node.insert(node_ind, new_node) - # remove old nodes - graph.node.remove(n) - graph.node.remove(consumer) - graph_modified = True - else: - # no activation, matmul only - odt = model.get_tensor_datatype(mm_output) - model.set_tensor_shape(mm_input, mm_in_shape) - model.set_tensor_shape(mm_output, mm_out_shape) - # create and insert new MatrixVectorActivation node - new_node = helper.make_node( - "MatrixVectorActivation", - [mm_input, mm_weight], - [mm_output], - domain="finn.custom_op.fpgadataflow", - backend="fpgadataflow", - MW=mw, - MH=mh, - SIMD=simd, - PE=pe, - inputDataType=idt.name, - weightDataType=wdt.name, - outputDataType=odt.name, - ActVal=0, - binaryXnorMode=1, - noActivation=1, - numInputVectors=list(mm_in_shape[:-1]), - mem_mode=self.mem_mode, - name=n.name, - ) - graph.node.insert(node_ind, new_node) - # remove old node - graph.node.remove(n) - graph_modified = True - if graph_modified: - model = model.transform(InferShapes()) - model = model.transform(InferDataTypes()) - return (model, graph_modified) - - -class InferQuantizedMatrixVectorActivation(Transformation): - """Convert MatMul layers with quantized inputs and weights to - MatrixVectorActivation layers. Any immediately following MultiThreshold - layers will also be absorbed into the MVTU.""" - - def __init__(self, mem_mode="const"): - super().__init__() - self.mem_mode = mem_mode - - def apply(self, model): - graph = model.graph - node_ind = 0 - graph_modified = False - for n in graph.node: - node_ind += 1 - if n.op_type == "MatMul" and model.get_tensor_sparsity(n.input[1]) is None: - mm_input = n.input[0] - mm_weight = n.input[1] - mm_output = n.output[0] - mm_in_shape = model.get_tensor_shape(mm_input) - mm_out_shape = model.get_tensor_shape(mm_output) - idt = model.get_tensor_datatype(mm_input) - wdt = model.get_tensor_datatype(mm_weight) - if idt.is_integer() and wdt.is_integer(): - mm_output = n.output[0] - W = model.get_initializer(mm_weight) - # extract weight shape, note that ONNX and finn-hlslib - # make different assumptions about dim order here - # ONNX assumes W has (in, out) shape - # finn-hlslib assumes W has (out, in) shape - mh = int(W.shape[1]) - mw = int(W.shape[0]) - # create node with no parallelization first - pe = 1 - simd = 1 - wmem = mw * mh // (pe * simd) - assert mw * mh == wmem * pe * simd, ( - n.name - + """: Requirement (MW * MH) divisible by - (WMEM * PE * SIMD) is violated.""" - ) - # see if we have any following thresholds - consumer = model.find_consumer(mm_output) - if consumer is not None and consumer.op_type == "MultiThreshold": - # TODO ensure integer thresholds? - # create MVTU (i.e. including activation) - mt_output = consumer.output[0] - mt_out_shape = model.get_tensor_shape(mt_output) - mt_thres = consumer.input[1] - T = model.get_initializer(mt_thres) - assert T.shape[0] == 1 or T.shape[0] == mh, ( - consumer.name - + """: First dimension of - thresholds neither 1 nor MH.""" - ) - odt = model.get_tensor_datatype(mt_output) - scale = getCustomOp(consumer).get_nodeattr("out_scale") - actval = getCustomOp(consumer).get_nodeattr("out_bias") - assert int(actval) == actval, ( - consumer.name + ": out_bias must be integer for HLS conversion." - ) - actval = int(actval) - odt_is_bipolar = odt == DataType["BIPOLAR"] - bipolar_ok = odt_is_bipolar and (scale == 2.0) and (actval == -1) - assert scale == 1.0 or bipolar_ok, ( - consumer.name + ": out_scale=1 or bipolar output needed for conversion." - ) - assert (not odt.signed()) or (actval < 0), ( - consumer.name + ": Signed output requres actval < 0" - ) - model.set_tensor_shape(mm_input, mm_in_shape) - model.set_tensor_shape(mt_output, mt_out_shape) - if bipolar_ok: - # remove bias for bipolar, since - # binary->bipolar is achieved by reinterpretation - actval = 0 - # create and insert new MatrixVectorActivation node - new_node = helper.make_node( - "MatrixVectorActivation", - [mm_input, mm_weight, mt_thres], - [mt_output], - domain="finn.custom_op.fpgadataflow", - backend="fpgadataflow", - MW=mw, - MH=mh, - SIMD=simd, - PE=pe, - inputDataType=idt.name, - weightDataType=wdt.name, - outputDataType=odt.name, - ActVal=actval, - binaryXnorMode=0, - noActivation=0, - numInputVectors=list(mm_in_shape[:-1]), - mem_mode=self.mem_mode, - name="MatrixVectorActivation_" + n.name, - ) - graph.node.insert(node_ind, new_node) - # remove old nodes - graph.node.remove(n) - graph.node.remove(consumer) - graph_modified = True - else: - # no activation, matmul only - odt = model.get_tensor_datatype(mm_output) - model.set_tensor_shape(mm_input, mm_in_shape) - model.set_tensor_shape(mm_output, mm_out_shape) - # create and insert new MatrixVectorActivation node - new_node = helper.make_node( - "MatrixVectorActivation", - [mm_input, mm_weight], - [mm_output], - domain="finn.custom_op.fpgadataflow", - backend="fpgadataflow", - MW=mw, - MH=mh, - SIMD=simd, - PE=pe, - inputDataType=idt.name, - weightDataType=wdt.name, - outputDataType=odt.name, - ActVal=0, - binaryXnorMode=0, - noActivation=1, - numInputVectors=list(mm_in_shape[:-1]), - mem_mode=self.mem_mode, - name="MatrixVectorActivation_" + n.name, - ) - graph.node.insert(node_ind, new_node) - # remove old node - graph.node.remove(n) - graph_modified = True - if graph_modified: - model = model.transform(InferShapes()) - model = model.transform(InferDataTypes()) - return (model, graph_modified) - - -class InferVectorVectorActivation(Transformation): - """Convert MatMul layers with quantized inputs and weights to - VectorVectorActivation layers, if the sparsity annotation - of the weight matrix indicates that the MatMul layer belongs to - a depthwise convolution. Any immediately following MultiThreshold - layers will also be absorbed into the VVAU.""" - - def __init__(self, mem_mode="const"): - super().__init__() - self.mem_mode = mem_mode - - def apply(self, model): - graph = model.graph - node_ind = 0 - graph_modified = False - for n in graph.node: - node_ind += 1 - if n.op_type == "MatMul" and model.get_tensor_sparsity(n.input[1]) is not None: - sparsity = model.get_tensor_sparsity(n.input[1]) - try: - k_h, k_w = sparsity["dw"]["kernel_shape"] - except KeyError: - raise Exception( - n.name - + """: sparsity annotation doesn't indicate that MatMul - belongs to a depthwise convolution.""" - ) - - mm_input = n.input[0] - mm_weight = n.input[1] - mm_output = n.output[0] - mm_in_shape = model.get_tensor_shape(mm_input) - mm_out_shape = model.get_tensor_shape(mm_output) - idt = model.get_tensor_datatype(mm_input) - wdt = model.get_tensor_datatype(mm_weight) - if idt.is_integer() and wdt.is_integer(): - mm_output = n.output[0] - W = model.get_initializer(mm_weight) - # infer dense weight tensor from sparse weight matrix - # kernel size (k_h, k_w) which was extracted above and the value of - # the channels is used. - # the weight matrix has a shape of (k_h * k_w * Channels, Channels) - # we need to reverse the creation of the sparse weight matrix - # to achieve a weight tensor of shape (Channels, 1, k_h, k_w) - channels = int(W.shape[1]) - # transpose to achieve a shape of (k_h * k_w * Channels, Channels) - W = W.T - # reshape to (Channels, k_h, k_w, Channels) to transpose afterwards - # to (Channels, Channels, k_h, k_w) - W = W.reshape(channels, k_h, k_w, channels) - W = W.transpose(0, 3, 1, 2) - # now we can extract the values using a for loop over the channels - # and fill a zero numpy array in the correct shape - w_tensor = np.zeros((channels, 1, k_h, k_w), dtype=np.float32) - for ch in range(channels): - w_tensor[ch][0] = W[ch][ch] - model.set_initializer(mm_weight, w_tensor) - model.set_tensor_shape(mm_weight, (channels, 1, k_h, k_w)) - # create node with pe=channels as default - pe = channels - # see if we have any following thresholds - consumer = model.find_consumer(mm_output) - if consumer is not None and consumer.op_type == "MultiThreshold": - # create VVAU (i.e. including activation) - mt_output = consumer.output[0] - mt_out_shape = model.get_tensor_shape(mt_output) - mt_thres = consumer.input[1] - T = model.get_initializer(mt_thres) - assert T.shape[0] == 1 or T.shape[0] == channels, ( - consumer.name - + """: First dimension of - thresholds neither 1 nor Channels.""" - ) - odt = model.get_tensor_datatype(mt_output) - scale = getCustomOp(consumer).get_nodeattr("out_scale") - assert scale == 1.0, ( - consumer.name + ": out_scale must be equal to 1.0 for HLS conversion." - ) - actval = getCustomOp(consumer).get_nodeattr("out_bias") - assert int(actval) == actval, ( - consumer.name + ": out_bias must be integer for HLS conversion." - ) - actval = int(actval) - assert (not odt.signed()) or (actval < 0), ( - consumer.name + ": Signed output requres actval < 0" - ) - model.set_tensor_shape(mm_input, mm_in_shape) - model.set_tensor_shape(mt_output, mt_out_shape) - # create and insert new VectorVectorActivation node - new_node = helper.make_node( - "VectorVectorActivation", - [mm_input, mm_weight, mt_thres], - [mt_output], - domain="finn.custom_op.fpgadataflow", - backend="fpgadataflow", - resType="lut", - PE=pe, - Dim=[mm_in_shape[1], mm_in_shape[2]], - Channels=channels, - Kernel=[k_h, k_w], - inputDataType=idt.name, - weightDataType=wdt.name, - outputDataType=odt.name, - ActVal=actval, - noActivation=0, - name="VectorVectorActivation_" + n.name, - mem_mode=self.mem_mode, - ) - graph.node.insert(node_ind, new_node) - # remove old nodes - graph.node.remove(n) - graph.node.remove(consumer) - graph_modified = True - else: - # no activation, matmul only - odt = model.get_tensor_datatype(mm_output) - model.set_tensor_shape(mm_input, mm_in_shape) - model.set_tensor_shape(mm_output, mm_out_shape) - # create and insert new VVAU node - new_node = helper.make_node( - "VectorVectorActivation", - [mm_input, mm_weight], - [mm_output], - domain="finn.custom_op.fpgadataflow", - backend="fpgadataflow", - resType="lut", - PE=pe, - Dim=[mm_in_shape[1], mm_in_shape[2]], - Channels=channels, - Kernel=[k_h, k_w], - inputDataType=idt.name, - weightDataType=wdt.name, - outputDataType=odt.name, - ActVal=0, - noActivation=1, - name="VectorVectorActivation_" + n.name, - ) - graph.node.insert(node_ind, new_node) - # remove old node - graph.node.remove(n) - graph_modified = True - if graph_modified: - model = model.transform(InferShapes()) - model = model.transform(InferDataTypes()) - return (model, graph_modified) - - -class InferThresholdingLayer(Transformation): - """Convert any MultiThreshold into a standalone thresholding HLS layer.""" - - def __init__(self, mem_mode="const"): - super().__init__() - self.mem_mode = mem_mode - - def apply(self, model): - graph = model.graph - node_ind = 0 - graph_modified = False - for node in graph.node: - node_ind += 1 - if node.op_type == "MultiThreshold": - thl_input = node.input[0] - thl_threshold = node.input[1] - thl_output = node.output[0] - thl_in_shape = model.get_tensor_shape(thl_input) - thl_thres_shape = model.get_tensor_shape(thl_threshold) - idt = model.get_tensor_datatype(thl_input) - - # skip conversion for layers with float input - if not idt.is_integer(): - continue - - # check layout of inputs/outputs, and convert if needed - # check layout and convert if necessary - thl_in_layout = model.get_tensor_layout(thl_input) - if thl_in_layout == DataLayout.NCHW: - thl_input = nchw_to_nhwc(thl_input, model, node_ind) - node_ind += 1 - thl_in_shape = model.get_tensor_shape(thl_input) - - # keep track of where we need to insert the HLS Op - # it has to be ahead of the output transform - insert_point = node_ind - thl_output_layout = model.get_tensor_layout(thl_output) - if thl_output_layout == DataLayout.NCHW: - thl_output = nchw_to_nhwc(thl_output, model, node_ind, reverse=True) - node_ind += 1 - - # now safe to assume number of channels is in last dimension - ifc = int(thl_in_shape[-1]) - # create node with no parallelization first - pe = 1 - - odt = model.get_tensor_datatype(thl_output) - scale = getCustomOp(node).get_nodeattr("out_scale") - assert scale == 1.0, ( - node.name + ": MultiThreshold out_scale must be 1 for HLS conversion." - ) - actval = getCustomOp(node).get_nodeattr("out_bias") - assert int(actval) == actval, ( - node.name + ": MultiThreshold out_bias must be integer for HLS conversion." - ) - actval = int(actval) - assert (not odt.signed()) or (actval < 0), ( - node.name + ": Signed output requres actval < 0" - ) - # create and insert new Thresholding_Batch node - new_node = helper.make_node( - "Thresholding_Batch", - [thl_input, thl_threshold], - [thl_output], - domain="finn.custom_op.fpgadataflow", - backend="fpgadataflow", - NumChannels=ifc, - PE=pe, - numSteps=thl_thres_shape[1], - inputDataType=idt.name, - # weightDataType can be tightened by MinimizeAccumulatorWidth - weightDataType=idt.name, - outputDataType=odt.name, - numInputVectors=list(thl_in_shape[:-1]), - ActVal=actval, - mem_mode=self.mem_mode, - name="Thresholding_Batch_" + node.name, - ) - graph.node.insert(insert_point, new_node) - # remove old node - graph.node.remove(node) - graph_modified = True - - if graph_modified: - model = model.transform(InferShapes()) - model = model.transform(InferDataTypes()) - return (model, graph_modified) - - -class InferAddStreamsLayer(Transformation): - """Convert any Add into a AddStreams HLS layer.""" - - def apply(self, model): - graph = model.graph - node_ind = 0 - graph_modified = False - for node in graph.node: - node_ind += 1 - if node.op_type == "Add": - in0 = node.input[0] - in1 = node.input[1] - result = node.output[0] - in0_shape = model.get_tensor_shape(in0) - in1_shape = model.get_tensor_shape(in1) - in0_static = not (model.get_initializer(in0) is None) - in1_static = not (model.get_initializer(in1) is None) - - # skip if different shapes on inputs - if in0_shape != in1_shape: - continue - # skip if any of inputs have initializers - # (this node is meant for adding two dynamic streams) - if in0_static or in1_static: - continue - - idt0 = model.get_tensor_datatype(in0) - idt1 = model.get_tensor_datatype(in1) - - # skip if different data types on inputs - if idt0 != idt1: - continue - - idt = idt0 - - # skip conversion for layers with float input - if not idt.is_integer(): - continue - - # check layout and convert if necessary - in0_layout = model.get_tensor_layout(in0) - in1_layout = model.get_tensor_layout(in1) - result_layout = model.get_tensor_layout(result) - - if in0_layout == DataLayout.NCHW: - in0 = nchw_to_nhwc(in0, model, node_ind) - node_ind += 1 - in0_shape = model.get_tensor_shape(in0) - - if in1_layout == DataLayout.NCHW: - in1 = nchw_to_nhwc(in1, model, node_ind) - node_ind += 1 - in1_shape = model.get_tensor_shape(in1) - - # keep track of where we need to insert the HLS Op - # it has to be ahead of the output transform - insert_point = node_ind - - if result_layout == DataLayout.NCHW: - result = nchw_to_nhwc(result, model, node_ind, reverse=True) - node_ind += 1 - - # now safe to assume num_channels is size of last dimension - num_channels = int(in0_shape[-1]) - # create node with no parallelization first - pe = 1 - - # create and insert new AddStreams_Batch node - new_node = helper.make_node( - "AddStreams_Batch", - [in0, in1], - [result], - domain="finn.custom_op.fpgadataflow", - backend="fpgadataflow", - NumChannels=num_channels, - PE=pe, - inputDataType=idt.name, - numInputVectors=in0_shape[:-1], - name="AddStreams_Batch_" + node.name, - ) - graph.node.insert(insert_point, new_node) - # remove old node - graph.node.remove(node) - graph_modified = True - - if graph_modified: - model = model.transform(InferShapes()) - model = model.transform(InferDataTypes()) - return (model, graph_modified) - - -class InferDuplicateStreamsLayer(Transformation): - """Insert a DuplicateStreams HLS layer for any tensor with fanout == 2""" - - def apply(self, model): - graph = model.graph - node_ind = 0 - graph_modified = False - for node in graph.node: - node_ind += 1 - successors = model.find_consumers(node.output[0]) - if successors is not None and len(successors) >= 2: - output_tensor = node.output[0] - n_outputs = len(successors) - - dt = model.get_tensor_datatype(output_tensor) - - # skip conversion for layers with float input - if not dt.is_integer(): - continue - - # create clone tensors - out_shape = model.get_tensor_shape(output_tensor) - out_tensor_clones = [] - for i in range(n_outputs): - clone = helper.make_tensor_value_info( - model.make_new_valueinfo_name(), TensorProto.FLOAT, out_shape - ) - model.graph.value_info.append(clone) - out_tensor_clones += [clone.name] - - num_ch = int(out_shape[-1]) - vecs = out_shape[:-1] - - # create node with no parallelization first - pe = 1 - - dup_node = helper.make_node( - "DuplicateStreams_Batch", - [output_tensor], - out_tensor_clones, - domain="finn.custom_op.fpgadataflow", - backend="fpgadataflow", - NumChannels=num_ch, - PE=pe, - inputDataType=dt.name, - numInputVectors=vecs, - NumOutputStreams=n_outputs, - outFIFODepths=[2] * n_outputs, - name="DuplicateStreams_Batch_" + node.name, - ) - - graph.node.insert(node_ind, dup_node) - - # connect successors to out tensor clone - clone_idx = 0 - for successor in successors: - for i, succ_input in enumerate(successor.input): - if succ_input == output_tensor: - successor.input[i] = out_tensor_clones[clone_idx] - clone_idx += 1 - # if one node has multiple connections to the same output - # find_direct_successors will return one node per input - # so break the inner loop will result in correct behaviour - break - - graph_modified = True - - if graph_modified: - model = model.transform(SortGraph()) - model = model.transform(InferShapes()) - model = model.transform(InferDataTypes()) - return (model, graph_modified) - - -class InferChannelwiseLinearLayer(Transformation): - """Convert any channel-wise Add/Mul into a HLS layer.""" - - def get_smallest_possible(self, vals): - """Returns smallest (fewest bits) possible DataType that can represent - value. Prefers unsigned integers where possible.""" - vals = np.array(vals, dtype=np.float64) - for v in vals: - assert int(v) == v, "Error float value" - - for k in DataType.get_accumulator_dt_cands(): - dt = DataType[k] - - if dt in [DataType["BIPOLAR"], DataType["TERNARY"], DataType["FLOAT32"]]: - # not currently supported - continue - - if (dt.min() <= vals).all() and (vals <= dt.max()).all(): - return dt - - warnings.warn( - """InferChannelwiseLinearLayer: Output values may not be - representable with supported data types. - Setting maximum width data type available. - This will lead to errors if there are no constrains on the input - """ - ) - - if (0 <= vals).all(): - return DataType["UINT64"] - else: - return DataType["INT64"] - - def apply(self, model): - graph = model.graph - node_ind = 0 - graph_modified = False - for node in graph.node: - node_ind += 1 - if node.op_type == "Add" or node.op_type == "Mul": - # assuming input[0] is dynamic - ll_input = node.input[0] - ll_output = node.output[0] - ll_in_shape = model.get_tensor_shape(ll_input) - - # check if input 1 has an initializer - ll_const = node.input[1] - if ll_const is not None: - ll_cinit = model.get_initializer(ll_const) - if ll_cinit is None: - # input 1 is also dynamic - continue - else: - continue - - # get number of channels and channel index from input - ll_in_layout = model.get_tensor_layout(ll_input) - if ll_in_layout == DataLayout.NHWC or ll_in_layout == DataLayout.NC: - ch_index = -1 - ch = ll_in_shape[-1] - elif ll_in_layout == DataLayout.NCHW: - ch_index = 1 - ch = ll_in_shape[1] - else: - continue - - # check if the shape of initializer is compatible - ll_cinit_shape = list(ll_cinit.shape) - if np.prod(ll_cinit_shape) == 1: - warnings.warn("Broadcasting " + str(node.op_type) + "(" + node.name + ")") - ll_cinit = np.full((ch), ll_cinit.flatten()[0]) - elif np.prod(ll_cinit_shape) != ch or ll_cinit_shape[ch_index] != ch: - # parameter shape not compatible with Channelwise_batch - continue - - # check initializer contains integers as floats - if not (ll_cinit.astype(np.int32) == ll_cinit).all(): - continue - # all initializer conditions are met - - # check inputs - idt = model.get_tensor_datatype(ll_input) - if not idt.is_integer(): - # skip conversion for layers with float input - continue - - # check layout of inputs/outputs, and convert if needed - # check layout and convert if necessary - if ll_in_layout == DataLayout.NCHW: - ll_input = nchw_to_nhwc(ll_input, model, node_ind) - node_ind += 1 - ll_in_shape = model.get_tensor_shape(ll_input) - - # keep track of where we need to insert the HLS Op - # it has to be ahead of the output transform - insert_point = node_ind - ll_output_layout = model.get_tensor_layout(ll_output) - if ll_output_layout == DataLayout.NCHW: - ll_output = nchw_to_nhwc(ll_output, model, node_ind, reverse=True) - node_ind += 1 - - # get parameter data type - param_min = min(ll_cinit.flatten()) - param_max = max(ll_cinit.flatten()) - pdt = self.get_smallest_possible([param_min, param_max]) - - # set function and determine output data type - if node.op_type == "Add": - func = "add" - out_min = idt.min() + param_min - out_max = idt.max() + param_max - odt = self.get_smallest_possible([out_min, out_max]) - elif node.op_type == "Mul": - func = "mul" - possible_limits = [] - possible_limits += [idt.min() * param_min] - possible_limits += [idt.min() * param_max] - possible_limits += [idt.max() * param_min] - possible_limits += [idt.max() * param_max] - odt = self.get_smallest_possible(possible_limits) - - model.set_initializer(ll_const, ll_cinit.reshape(ch)) - model.set_tensor_datatype(ll_output, odt) - - # create node with no parallelization first - pe = 1 - assert ch % pe == 0, "Requirement IFC divisable by PE is violated." - # create and insert node - new_node = helper.make_node( - "ChannelwiseOp_Batch", - [ll_input, ll_const], - [ll_output], - domain="finn.custom_op.fpgadataflow", - backend="fpgadataflow", - Func=func, - NumChannels=ch, - PE=pe, - inputDataType=idt.name, - paramDataType=pdt.name, - outputDataType=odt.name, - numInputVectors=list(ll_in_shape[:-1]), - name="ChannelwiseOp_Batch_" + node.name, - ) - graph.node.insert(insert_point, new_node) - # remove old node - graph.node.remove(node) - graph_modified = True - - if graph_modified: - model = model.transform(InferShapes()) - model = model.transform(InferDataTypes()) - return (model, graph_modified) - - -class InferLabelSelectLayer(Transformation): - """Convert any TopK into a LabelSelect HLS layer.""" - - def apply(self, model): - graph = model.graph - node_ind = 0 - graph_modified = False - for node in graph.node: - node_ind += 1 - if node.op_type == "TopK": - fc_input = node.input[0] - k_input = node.input[1] - val_output = node.output[0] - idx_output = node.output[1] - fc_in_shape = model.get_tensor_shape(fc_input) - - idt = model.get_tensor_datatype(fc_input) - - # skip conversion for layers with float input - if not idt.is_integer(): - continue - - # skip conversion for if value output is connected (not supported) - if model.find_consumer(val_output) is not None: - continue - - num_labels = int(fc_in_shape[-1]) - num_inp_vecs = list(fc_in_shape[:-1]) - # create node with no parallelization first - pe = 1 - - k = model.get_initializer(k_input)[0] - - # create and insert new LabelSelect_Batch node - new_node = helper.make_node( - "LabelSelect_Batch", - [fc_input], - [idx_output], - domain="finn.custom_op.fpgadataflow", - backend="fpgadataflow", - Labels=num_labels, - PE=pe, - K=k, - inputDataType=idt.name, - numInputVectors=num_inp_vecs, - name="LabelSelect_Batch_" + node.name, - ) - graph.node.insert(node_ind, new_node) - # remove old node - graph.node.remove(node) - graph_modified = True - - if graph_modified: - model = model.transform(InferShapes()) - model = model.transform(InferDataTypes()) - return (model, graph_modified) - - -class InferGlobalAccPoolLayer(Transformation): - """Convert any GlobalAveragePool into a GlobalAccPool HLS layer and a scalar Mul.""" - - def apply(self, model): - graph = model.graph - node_ind = 0 - graph_modified = False - for node in graph.node: - node_ind += 1 - if node.op_type == "GlobalAveragePool": - in0 = node.input[0] - result = node.output[0] - in0_shape = model.get_tensor_shape(in0) - - idt = model.get_tensor_datatype(in0) - - # skip conversion for layers with float input - if not idt.is_integer(): - continue - - # check layout and convert if necessary - in0_layout = model.get_tensor_layout(in0) - result_layout = model.get_tensor_layout(result) - - if in0_layout == DataLayout.NCHW: - in0 = nchw_to_nhwc(in0, model, node_ind) - node_ind += 1 - in0_shape = model.get_tensor_shape(in0) - - # keep track of where we need to insert the HLS Op - # it has to be ahead of the output transform - insert_point = node_ind - - if result_layout == DataLayout.NCHW: - result = nchw_to_nhwc(result, model, node_ind, reverse=True) - node_ind += 1 - - num_ch = int(in0_shape[-1]) - vecs = in0_shape[:-1] - # create node with no parallelization first - pe = 1 - - # create an additional tensor of the same shape and layout as result - out_shape = model.get_tensor_shape(result) - pool_out = helper.make_tensor_value_info( - model.make_new_valueinfo_name(), TensorProto.FLOAT, out_shape - ) - model.graph.value_info.append(pool_out) - pool_out = pool_out.name - model.set_tensor_layout(pool_out, model.get_tensor_layout(result)) - - new_pool = helper.make_node( - "GlobalAccPool_Batch", - [in0], - [pool_out], - domain="finn.custom_op.fpgadataflow", - backend="fpgadataflow", - NumChannels=num_ch, - PE=pe, - inputDataType=idt.name, - numInputVectors=vecs, - name="GlobalAccPool_Batch_" + node.name, - ) - - mul_value = helper.make_tensor_value_info( - model.make_new_valueinfo_name(), TensorProto.FLOAT, [1] - ) - model.graph.value_info.append(mul_value) - model.set_initializer( - mul_value.name, np.array(1 / (vecs[1] * vecs[2]), dtype=np.float32) - ) - new_mul = helper.make_node( - "Mul", - [pool_out, mul_value.name], - [result], - ) - graph.node.insert(insert_point, new_pool) - graph.node.insert(insert_point + 1, new_mul) - node_ind += 1 - # remove old node - graph.node.remove(node) - graph_modified = True - - if graph_modified: - model = model.transform(InferShapes()) - model = model.transform(InferDataTypes()) - return (model, graph_modified) - - -class InferLookupLayer(Transformation): - """Convert Gather nodes with constant op0 into Lookup HLS layers.""" - - def apply(self, model): - graph = model.graph - node_ind = 0 - graph_modified = False - for node in graph.node: - node_ind += 1 - if node.op_type == "Gather": - emb_name = node.input[0] - embs = model.get_initializer(emb_name) - axis = get_by_name(node.attribute, "axis") - # skip conversion if input0 is not constant - if embs is None: - continue - # skip conversion if axis != 0 - if axis is not None and axis.i != 0: - continue - ind_name = node.input[1] - ind_dtype = model.get_tensor_datatype(ind_name) - emb_dtype = model.get_tensor_datatype(emb_name) - # skip conversion if inputs are not unsigned integers - if (not ind_dtype.is_integer()) or ind_dtype.signed(): - continue - num_embs, emb_dim = embs.shape - out_name = node.output[0] - ishape = model.get_tensor_shape(node.input[1]) - # create and insert new Lookup node - new_node = helper.make_node( - "Lookup", - [ind_name, emb_name], - [out_name], - domain="finn.custom_op.fpgadataflow", - backend="fpgadataflow", - name="Lookup_" + node.name, - NumEmbeddings=num_embs, - EmbeddingDim=emb_dim, - EmbeddingType=emb_dtype.name, - InputType=ind_dtype.name, - InputShape=list(ishape), - ) - graph.node.insert(node_ind, new_node) - # remove old node - graph.node.remove(node) - graph_modified = True - - if graph_modified: - model = model.transform(InferShapes()) - model = model.transform(InferDataTypes()) - return (model, graph_modified) - - -class InferConcatLayer(Transformation): - """Convert suitable Concat nodes (operating on last/-1 axis) - into StreamingConcat HLS layers.""" - - def apply(self, model): - graph = model.graph - node_ind = 0 - graph_modified = False - for node in graph.node: - node_ind += 1 - if node.op_type == "Concat": - ishape = model.get_tensor_shape(node.input[0]) - axis = get_by_name(node.attribute, "axis") - if (axis is None) or (ishape is None): - continue - axis = axis.i - last_axis = len(ishape) - 1 - # skip conversion if not using last axis - if (axis != -1) and (axis != last_axis): - continue - # check datatype coherence - dt0 = model.get_tensor_datatype(node.input[0]) - if dt0 is None: - continue - dt_coherent = all([model.get_tensor_datatype(x) == dt0 for x in node.input]) - if not dt_coherent: - continue - # skip conversion if any inputs are static - all_static = all([model.get_initializer(x) is None for x in node.input]) - if not all_static: - continue - # skip conversion if inputs are not integers - if not dt0.is_integer(): - continue - # ready for conversion - elems_per_stream = [model.get_tensor_shape(x)[-1] for x in node.input] - inp_vec = list(model.get_tensor_shape(node.input[0])[:-1]) - new_node = helper.make_node( - "StreamingConcat", - node.input, - node.output, - domain="finn.custom_op.fpgadataflow", - backend="fpgadataflow", - name="Concat_" + node.name, - ElemsPerStream=elems_per_stream, - inputDataType=dt0.name, - numInputVectors=inp_vec, - inFIFODepths=[2] * len(node.input), - ) - graph.node.insert(node_ind, new_node) - # remove old node - graph.node.remove(node) - graph_modified = True - - if graph_modified: - model = model.transform(InferShapes()) - model = model.transform(InferDataTypes()) - return (model, graph_modified) - - -class InferStreamingEltwise(Transformation): - """Convert eltwise Sub or Sub -> Abs to StreamingEltwise layer - with SubEltwise or AbsDiffEltwise op.""" - - def apply(self, model): - graph = model.graph - node_ind = 0 - graph_modified = False - for node in graph.node: - node_ind += 1 - if node.op_type == "Sub": - in0 = node.input[0] - in1 = node.input[1] - result = node.output[0] - in0_shape = model.get_tensor_shape(in0) - in1_shape = model.get_tensor_shape(in1) - in0_static = not (model.get_initializer(in0) is None) - in1_static = not (model.get_initializer(in1) is None) - - # skip if different shapes on inputs - if in0_shape != in1_shape: - continue - # skip if any of inputs have initializers - # (this node is meant for two dynamic streams) - if in0_static or in1_static: - continue - - idt0 = model.get_tensor_datatype(in0) - idt1 = model.get_tensor_datatype(in1) - - # skip conversion for layers with float input - if not (idt0.is_integer() and idt1.is_integer()): - continue - - eltwiseOp = "Sub" - nodes_to_remove = [node] - # look for a downstream Abs node - res_consumer = model.find_consumer(result) - if (res_consumer is not None) and (res_consumer.op_type == "Abs"): - eltwiseOp = "AbsDiff" - result = res_consumer.output[0] - nodes_to_remove.append(res_consumer) - - # check layout and convert if necessary - in0_layout = model.get_tensor_layout(in0) - in1_layout = model.get_tensor_layout(in1) - result_layout = model.get_tensor_layout(result) - - if in0_layout == DataLayout.NCHW: - in0 = nchw_to_nhwc(in0, model, node_ind) - node_ind += 1 - in0_shape = model.get_tensor_shape(in0) - - if in1_layout == DataLayout.NCHW: - in1 = nchw_to_nhwc(in1, model, node_ind) - node_ind += 1 - in1_shape = model.get_tensor_shape(in1) - - # keep track of where we need to insert the HLS Op - # it has to be ahead of the output transform - insert_point = node_ind - - if result_layout == DataLayout.NCHW: - result = nchw_to_nhwc(result, model, node_ind, reverse=True) - node_ind += 1 - - # now safe to assume num_channels is size of last dimension - num_channels = int(in0_shape[-1]) - # create node with no parallelization first - pe = 1 - - # create and insert new Eltwise node - new_node = helper.make_node( - "StreamingEltwise", - [in0, in1], - [result], - domain="finn.custom_op.fpgadataflow", - backend="fpgadataflow", - NumChannels=num_channels, - PE=pe, - inputDataType0=idt0.name, - inputDataType1=idt1.name, - eltwiseOp=eltwiseOp, - numInputVectors=in0_shape[:-1], - name="StreamingEltwise_" + node.name, - ) - graph.node.insert(insert_point, new_node) - # remove old nodes - for nd in nodes_to_remove: - graph.node.remove(nd) - graph_modified = True - - # if graph_modified: - # model = model.transform(InferShapes()) - # model = model.transform(InferDataTypes()) - return (model, graph_modified) diff --git a/src/finn/transformation/fpgadataflow/create_stitched_ip.py b/src/finn/transformation/fpgadataflow/create_stitched_ip.py index 1c316e1285..0ce0923934 100644 --- a/src/finn/transformation/fpgadataflow/create_stitched_ip.py +++ b/src/finn/transformation/fpgadataflow/create_stitched_ip.py @@ -285,14 +285,14 @@ def apply(self, model): ip_dirs.append("$::env(FINN_ROOT)/finn-rtllib/memstream") if self.signature: ip_dirs.append("$::env(FINN_ROOT)/finn-rtllib/axi_info") - if model.graph.node[0].op_type not in ["StreamingFIFO", "IODMA_hls"]: + if model.graph.node[0].op_type not in ["StreamingFIFO_rtl", "IODMA_hls"]: warnings.warn( """First node is not StreamingFIFO or IODMA. You may experience incorrect stitched-IP rtlsim or hardware behavior. It is strongly recommended to insert FIFOs prior to calling CreateStitchedIP.""" ) - if model.graph.node[0].op_type == "StreamingFIFO": + if model.graph.node[0].op_type == "StreamingFIFO_rtl": firstfifo = getCustomOp(model.graph.node[0]) if firstfifo.get_nodeattr("impl_style") == "vivado": warnings.warn( @@ -349,7 +349,7 @@ def apply(self, model): if self.signature: # extract number of checksum layer from graph - checksum_layers = model.get_nodes_by_op_type("checksum") + checksum_layers = model.get_nodes_by_op_type("CheckSum_hls") self.insert_signature(len(checksum_layers)) # create a temporary folder for the project diff --git a/src/finn/transformation/fpgadataflow/derive_characteristic.py b/src/finn/transformation/fpgadataflow/derive_characteristic.py index d5699e4dc6..dee9b62e67 100644 --- a/src/finn/transformation/fpgadataflow/derive_characteristic.py +++ b/src/finn/transformation/fpgadataflow/derive_characteristic.py @@ -75,7 +75,7 @@ def apply(self, model: ModelWrapper): return (model, run_again) # apply manual fix for DuplicateStreams and AddStreams for # simple residual reconvergent paths with bypass - addstrm_nodes = model.get_nodes_by_op_type("AddStreams_Batch") + addstrm_nodes = model.get_nodes_by_op_type("AddStreams_hls") for addstrm_node in addstrm_nodes: # we currently only support the case where one branch is # a bypass @@ -84,8 +84,8 @@ def apply(self, model: ModelWrapper): if (b0 is None) or (b1 is None): warnings.warn("Found unsupported AddStreams, skipping") return (model, run_again) - b0_is_bypass = b0.op_type == "DuplicateStreams_Batch" - b1_is_bypass = b1.op_type == "DuplicateStreams_Batch" + b0_is_bypass = b0.op_type == "DuplicateStreams_hls" + b1_is_bypass = b1.op_type == "DuplicateStreams_hls" if (not b0_is_bypass) and (not b1_is_bypass): warnings.warn("Found unsupported AddStreams, skipping") return (model, run_again) diff --git a/src/finn/transformation/fpgadataflow/floorplan.py b/src/finn/transformation/fpgadataflow/floorplan.py index 6149dffd59..5231fc288b 100644 --- a/src/finn/transformation/fpgadataflow/floorplan.py +++ b/src/finn/transformation/fpgadataflow/floorplan.py @@ -95,7 +95,7 @@ def apply(self, model): narrow_neighbour = model.find_producer(node.input[0]) node_slr = getCustomOp(narrow_neighbour).get_nodeattr("slr") node_inst.set_nodeattr("slr", node_slr) - if node.op_type == "StreamingFIFO": + if node.op_type.startswith("StreamingFIFO"): # if we have SLR assignment already. use that if node_slr != -1: continue diff --git a/src/finn/transformation/fpgadataflow/insert_dwc.py b/src/finn/transformation/fpgadataflow/insert_dwc.py index f6dd587c76..e3a52f68f0 100644 --- a/src/finn/transformation/fpgadataflow/insert_dwc.py +++ b/src/finn/transformation/fpgadataflow/insert_dwc.py @@ -90,7 +90,7 @@ def apply(self, model): if ( consumer.op_type.startswith("MatrixVectorActivation") and n1.get_nodeattr("mem_mode") == "external" - ) or (consumer.op_type == "StreamingConcat"): + ) or (consumer.op_type.startswith("StreamingConcat")): # get input idx in_idx = None for idx, n_input in enumerate(consumer.input): diff --git a/src/finn/transformation/fpgadataflow/insert_fifo.py b/src/finn/transformation/fpgadataflow/insert_fifo.py index 4efadf0f27..630310842c 100644 --- a/src/finn/transformation/fpgadataflow/insert_fifo.py +++ b/src/finn/transformation/fpgadataflow/insert_fifo.py @@ -37,7 +37,7 @@ def _is_fifo_node(node): - if node.op_type == "StreamingFIFO": + if node.op_type.startswith("StreamingFIFO"): return True else: return False @@ -184,7 +184,10 @@ def apply(self, model): for graph_in_name in graph_in_names: first_node = model.find_consumer(graph_in_name) # insert FIFO as first node, except when first node is DMA - if first_node.op_type != "StreamingFIFO" and first_node.op_type != "IODMA_hls": + if ( + not first_node.op_type.startswith("StreamingFIFO") + and first_node.op_type != "IODMA_hls" + ): inp_ind = list(first_node.input).index(graph_in_name) n_input = first_node.input[inp_ind] n0 = getCustomOp(first_node) @@ -238,7 +241,10 @@ def apply(self, model): graph_out_names = [x.name for x in model.graph.output] for graph_out_name in graph_out_names: final_node = model.find_producer(graph_out_name) - if final_node.op_type != "StreamingFIFO" and final_node.op_type != "IODMA_hls": + if ( + not final_node.op_type.startswith("StreamingFIFO") + and final_node.op_type != "IODMA_hls" + ): assert ( final_node.op_type != "TLastMarker_hls" ), """Insert tlast marker should be done diff --git a/src/finn/transformation/fpgadataflow/insert_tlastmarker.py b/src/finn/transformation/fpgadataflow/insert_tlastmarker.py index fbb64428aa..431ca8e0b5 100644 --- a/src/finn/transformation/fpgadataflow/insert_tlastmarker.py +++ b/src/finn/transformation/fpgadataflow/insert_tlastmarker.py @@ -119,7 +119,7 @@ def apply(self, model): if inp_idx > 0: if first_node.op_type.startswith("MatrixVectorActivation") and inp_idx == 1: stream_width = int(custom_op.get_weightstream_width()) - elif first_node.op_type == "AddStreams_Batch" and inp_idx == 1: + elif first_node.op_type.startswith("AddStreams") and inp_idx == 1: stream_width = int(custom_op.get_instream_width()) else: raise Exception("No method to determine stream width") diff --git a/src/finn/transformation/fpgadataflow/set_fifo_depths.py b/src/finn/transformation/fpgadataflow/set_fifo_depths.py index 75c35df7d7..5d3b42b0c0 100644 --- a/src/finn/transformation/fpgadataflow/set_fifo_depths.py +++ b/src/finn/transformation/fpgadataflow/set_fifo_depths.py @@ -103,7 +103,7 @@ def apply(self, model): else: is_first_node = True if ( - node.op_type == "StreamingFIFO" + node.op_type.startswith("StreamingFIFO") and getCustomOp(node).get_nodeattr("depth") <= self.shallow_threshold and (not is_first_node) ): @@ -167,12 +167,12 @@ def apply(self, model): for node in model.graph.node: # look for following pattern: # ConvolutionInputGenerator -> StreamingFIFO -> MatrixVectorActivation - if node.op_type == "StreamingFIFO": + if node.op_type.startswith("StreamingFIFO"): fifo_prod = model.find_producer(node.input[0]) fifo_cons = model.find_consumer(node.output[0]) if fifo_prod is None: continue - if fifo_prod.op_type != "ConvolutionInputGenerator": + if not fifo_prod.op_type.startswith("ConvolutionInputGenerator"): continue if fifo_cons is None: continue @@ -266,7 +266,8 @@ def apply(self, model): for node in model.graph.node: # verify assumptions assert is_fpgadataflow_node(node), "Found non-fpgadataflow node: " + str(node) - assert node.op_type != "StreamingFIFO", "Found existing StreamingFIFO node" + op_type = node.op_type + assert not op_type.startswith("StreamingFIFO"), "Found existing StreamingFIFO node" node = getCustomOp(node) ifd = node.get_nodeattr("inFIFODepths") ofd = node.get_nodeattr("outFIFODepths") @@ -283,7 +284,7 @@ def apply(self, model): node.set_nodeattr("inFIFODepths", ifd) node.set_nodeattr("outFIFODepths", ofd) - if node.op_type in extw_optypes: + if op_type in extw_optypes: mmode = node.get_nodeattr("mem_mode") if mmode == "external": modified_fc_nodes.append(node.onnx_node.name) @@ -376,7 +377,9 @@ def apply(self, model): else: # do rtlsim in C++ for FIFO sizing # determine # inputs for FIFO sizing according to topology type - swg_nodes = [x for x in model.graph.node if "ConvolutionInputGenerator" in x.op_type] + swg_nodes = [ + x for x in model.graph.node if x.op_type.startswith("ConvolutionInputGenerator") + ] if len(swg_nodes) == 0: # MLP, no layer overlap # assuming half the nodes are now FIFOs, use half the # of @@ -400,7 +403,7 @@ def apply(self, model): for node in model.graph.node: # set FIFO depth, reset FIFO implementation, # and set implementation/ram styles - if node.op_type == "StreamingFIFO": + if node.op_type.startswith("StreamingFIFO"): assert node.name in fifos, "FIFO node not found in size dictionary" # set depth of FIFO depth = optimize_depth(fifos[node.name]) @@ -444,7 +447,7 @@ def apply(self, model): # reflect final values in attributes for node in model.graph.node: - if node.op_type != "StreamingFIFO": + if not node.op_type.startswith("StreamingFIFO"): node_inst = getCustomOp(node) fifodepth_in = [] for node_inp in node.input: @@ -459,7 +462,7 @@ def apply(self, model): pass else: # there is a producer for this input - if prod.op_type == "StreamingFIFO": + if prod.op_type.startswith("StreamingFIFO"): prod_inst = getCustomOp(prod) fifodepth_in.append(prod_inst.get_nodeattr("depth")) else: @@ -478,7 +481,7 @@ def apply(self, model): pass else: # there is a consumer for this input - if cons.op_type == "StreamingFIFO": + if cons.op_type.startswith("StreamingFIFO"): cons_inst = getCustomOp(cons) fifodepth_out.append(cons_inst.get_nodeattr("depth")) else: @@ -565,7 +568,7 @@ def apply(self, model): graph_modified = False for node in graph.node: node_ind += 1 - if node.op_type == "StreamingFIFO": + if node.op_type.startswith("StreamingFIFO"): n_inst = getCustomOp(node) depth = n_inst.get_nodeattr("depth") cfgs = get_fifo_split_configs(depth, self.max_qsrl_depth, self.max_vivado_depth) diff --git a/src/finn/transformation/fpgadataflow/set_folding.py b/src/finn/transformation/fpgadataflow/set_folding.py index 62457f164a..83f4138668 100644 --- a/src/finn/transformation/fpgadataflow/set_folding.py +++ b/src/finn/transformation/fpgadataflow/set_folding.py @@ -99,33 +99,32 @@ def apply(self, model): graph = model.graph # these ops use PE parallelism, up to a max value of NumChannels pe_ops = [ - "AddStreams_Batch", - "ChannelwiseOp_Batch", - "DuplicateStreams_Batch", - "GlobalAccPool_Batch", - "Thresholding_Batch", + "AddStreams_hls", + "ChannelwiseOp_hls", + "DuplicateStreams_hls", + "GlobalAccPool_hls", + "Thresholding_hls", ] # these ops use SIMD parallelism, up to a max value of NumChannels # ConvolutionInputGenerator* has a special case when depthwise=1 # ConvolutionInputGenerator_rtl supports additional parallelism by # setting parallel_window=1 mode after maxing out SIMD simd_ops = [ - "DownSampler", - "FMPadding_Batch", - "FMPadding_Pixel", - "ConvolutionInputGenerator", - "ConvolutionInputGenerator1D", + "DownSampler_hls", + "FMPadding_hls", + "FMPadding_Pixel_hls", + "ConvolutionInputGenerator_hls", "ConvolutionInputGenerator_rtl", ] # these ops are preceded by depthwise SWG and have special behavior, # as explained in the SetFolding docstring - depthwise_op_exceptions = ["VectorVectorActivation", "Pool_Batch"] + depthwise_op_exceptions = ["VectorVectorActivation_hls", "Pool_hls"] for node in graph.node: if not is_fpgadataflow_node(node): continue op_type = node.op_type node_inst = getCustomOp(node) - if op_type.startswith("MatrixVectorActivation"): + if op_type == "MatrixVectorActivation_hls": max_simd = node_inst.get_nodeattr("MW") max_pe = node_inst.get_nodeattr("MH") node_inst.set_nodeattr("PE", 1) @@ -152,12 +151,12 @@ def apply(self, model): elif op_type in pe_ops: max_pe = node_inst.get_nodeattr("NumChannels") self.optimize_attribute_val(node_inst, max_pe, "PE") - elif op_type == "LabelSelect_Batch": + elif op_type == "LabelSelect_hls": max_pe = node_inst.get_nodeattr("Labels") self.optimize_attribute_val(node_inst, max_pe, "PE") elif op_type in depthwise_op_exceptions: # init/reset SIMD of VVAU - if op_type == "VectorVectorActivation": + if op_type == "VectorVectorActivation_hls": node_inst.set_nodeattr("SIMD", 1) max_pe = node_inst.get_nodeattr("Channels") self.optimize_attribute_val(node_inst, max_pe, "PE") @@ -165,7 +164,7 @@ def apply(self, model): pe = node_inst.get_nodeattr("PE") cyc = node_inst.get_exp_cycles() if ( - op_type == "VectorVectorActivation" + op_type == "VectorVectorActivation_hls" and pe == max_pe and cyc > self.target_cycles_per_frame ): @@ -187,9 +186,9 @@ def apply(self, model): else: swu_node_inst.set_nodeattr("parallel_window", 0) else: - if op_type == "VectorVectorActivation": + if op_type == "VectorVectorActivation_hls": ksize = np.prod(node_inst.get_nodeattr("Kernel")) - elif op_type == "Pool_Batch": + elif op_type == "Pool_hls": ksize = node_inst.get_nodeattr("KernelSize") else: raise Exception("Undefined edge case for %s" % op_type) diff --git a/src/finn/transformation/fpgadataflow/specialize_layers.py b/src/finn/transformation/fpgadataflow/specialize_layers.py index d06f7d524e..691d7aed34 100644 --- a/src/finn/transformation/fpgadataflow/specialize_layers.py +++ b/src/finn/transformation/fpgadataflow/specialize_layers.py @@ -30,8 +30,6 @@ from onnx import helper from qonnx.custom_op.registry import getCustomOp from qonnx.transformation.base import Transformation -from qonnx.transformation.infer_datatypes import InferDataTypes -from qonnx.transformation.infer_shapes import InferShapes from finn.custom_op.fpgadataflow.hls import custom_op as hls_variants from finn.custom_op.fpgadataflow.rtl import custom_op as rtl_variants @@ -225,7 +223,4 @@ def apply(self, model): # remove old nodes graph.node.remove(node) graph_modified = True - if graph_modified: - model = model.transform(InferShapes()) - model = model.transform(InferDataTypes()) return (model, graph_modified) diff --git a/src/finn/transformation/move_reshape.py b/src/finn/transformation/move_reshape.py index ed553e7cee..6b5fa5516f 100644 --- a/src/finn/transformation/move_reshape.py +++ b/src/finn/transformation/move_reshape.py @@ -50,7 +50,7 @@ def apply(self, model): producer = model.find_producer(transp_node.input[0]) if _is_fpgadataflow_node(producer) is True: consumer = model.find_consumer(n.output[0]) - if consumer.op_type == "MatrixVectorActivation": + if consumer.op_type.startswith("MatrixVectorActivation"): fc_inst = getCustomOp(consumer) mw = fc_inst.get_nodeattr("MW") mh = fc_inst.get_nodeattr("MH") diff --git a/src/finn/util/pyverilator.py b/src/finn/util/pyverilator.py index 318ba7045e..7486402be5 100644 --- a/src/finn/util/pyverilator.py +++ b/src/finn/util/pyverilator.py @@ -147,7 +147,7 @@ def verilator_fifosim(model, n_inputs, max_iters=100000000): fifo_log = [] fifo_log_templ = ' results_file << "maxcount%s" << "\\t" ' fifo_log_templ += "<< to_string(top->maxcount%s) << endl;" - fifo_nodes = model.get_nodes_by_op_type("StreamingFIFO") + fifo_nodes = model.get_nodes_by_op_type("StreamingFIFO_rtl") fifo_ind = 0 for fifo_node in fifo_nodes: fifo_node = getCustomOp(fifo_node) diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index 53e5bb85eb..1dab57a7d3 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -704,9 +704,6 @@ def test_set_fifo_depths(self, topology, wbits, abits, board): model = load_test_checkpoint_or_skip(prev_chkpt_name) test_fpga_part = get_build_env(board, target_clk_ns)["part"] model = model.transform(InsertAndSetFIFODepths(test_fpga_part, target_clk_ns)) - fifo_layers = model.get_nodes_by_op_type("StreamingFIFO") - assert len(fifo_layers) > 0 - model = model.transform(SpecializeLayers()) fifo_layers = model.get_nodes_by_op_type("StreamingFIFO_rtl") assert len(fifo_layers) > 0 model.save(get_checkpoint_name(topology, wbits, abits, "fifodepth_" + board)) diff --git a/tests/util/test_build_dataflow.py b/tests/util/test_build_dataflow.py index 3649d6709e..c8f80a8e1b 100644 --- a/tests/util/test_build_dataflow.py +++ b/tests/util/test_build_dataflow.py @@ -50,6 +50,7 @@ def test_end2end_build_dataflow_directory(): assert os.path.isfile(output_dir + "/time_per_step.json") assert os.path.isfile(output_dir + "/auto_folding_config.json") assert os.path.isfile(output_dir + "/final_hw_config.json") + assert os.path.isfile(output_dir + "/template_specialize_layers_config.json") assert os.path.isfile(output_dir + "/stitched_ip/ip/component.xml") assert os.path.isfile(output_dir + "/driver/driver.py") assert os.path.isfile(output_dir + "/report/estimate_layer_cycles.json") From 7c3ccd33eae027afbd521fcf49af218f14c5959c Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 9 Feb 2024 16:30:02 +0000 Subject: [PATCH 485/665] [Tests] Change cnv dictionary for bnn pynq test --- tests/end2end/test_end2end_bnn_pynq.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index 1dab57a7d3..d95cc1dc4c 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -625,7 +625,7 @@ def test_specialize_layers(self, topology, wbits, abits, board): "cnv": [ ("Transpose", 1), ("Thresholding_hls", 1), - ("ConvolutionInputGenerator_rtl", 6), + ("ConvolutionInputGenerator_hls", 6), ("MatrixVectorActivation_hls", 9), ("StreamingMaxPool_hls", 2), ("LabelSelect_hls", 1), From 64c0c7d4509c8e17c3b9da174280eac8a07d74ed Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 9 Feb 2024 16:52:38 +0000 Subject: [PATCH 486/665] [Tests] Update folding test --- tests/fpgadataflow/test_set_folding.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/fpgadataflow/test_set_folding.py b/tests/fpgadataflow/test_set_folding.py index ce9f4b12ed..4992bf59f8 100644 --- a/tests/fpgadataflow/test_set_folding.py +++ b/tests/fpgadataflow/test_set_folding.py @@ -64,10 +64,10 @@ def make_multi_fclayer_model(ch, wdt, adt, tdt, nnodes): simd = 1 FCLayer_nodes += [ helper.make_node( - "MatrixVectorActivation", + "MatrixVectorActivation_hls", [tensors[i].name, "weights_" + str(i), "thresh_" + str(i)], [tensors[i + 1].name], - domain="finn.custom_op.fpgadataflow", + domain="finn.custom_op.fpgadataflow.hls", backend="fpgadataflow", MW=ch, MH=ch, From ba56a2d9bd63eded63e32ed039ef3b5c35dc1394 Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 12 Feb 2024 12:13:48 +0000 Subject: [PATCH 487/665] [Tests] Update fifo and ipstitch test to new flow --- tests/fpgadataflow/test_fpgadataflow_fifo.py | 4 +++- .../fpgadataflow/test_fpgadataflow_ipstitch.py | 17 +++++++++-------- 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_fifo.py b/tests/fpgadataflow/test_fpgadataflow_fifo.py index ecbf867b69..1719da1454 100644 --- a/tests/fpgadataflow/test_fpgadataflow_fifo.py +++ b/tests/fpgadataflow/test_fpgadataflow_fifo.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (c) 2020, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -59,6 +60,7 @@ def make_single_fifo_modelwrapper(Shape, Depth, fld_shape, finn_dtype): backend="fpgadataflow", depth=Depth, folded_shape=fld_shape, + normal_shape=Shape, dataType=str(finn_dtype.name), ) diff --git a/tests/fpgadataflow/test_fpgadataflow_ipstitch.py b/tests/fpgadataflow/test_fpgadataflow_ipstitch.py index aedb151af9..846f2c1fe0 100644 --- a/tests/fpgadataflow/test_fpgadataflow_ipstitch.py +++ b/tests/fpgadataflow/test_fpgadataflow_ipstitch.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (c) 2020, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -78,10 +79,10 @@ def create_one_fc_model(mem_mode="const"): outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, [1, m]) fc0 = helper.make_node( - "MatrixVectorActivation", + "MatrixVectorActivation_hls", ["inp", "w0"], ["outp"], - domain="finn.custom_op.fpgadataflow", + domain="finn.custom_op.fpgadataflow.hls", backend="fpgadataflow", MW=m, MH=m, @@ -130,10 +131,10 @@ def create_two_fc_model(mem_mode="decoupled"): outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, [1, m]) fc0 = helper.make_node( - "MatrixVectorActivation", + "MatrixVectorActivation_hls", ["inp", "w0"], ["mid"], - domain="finn.custom_op.fpgadataflow", + domain="finn.custom_op.fpgadataflow.hls", backend="fpgadataflow", MW=m, MH=m, @@ -149,10 +150,10 @@ def create_two_fc_model(mem_mode="decoupled"): ) fc1 = helper.make_node( - "MatrixVectorActivation", + "MatrixVectorActivation_hls", ["mid", "w1"], ["outp"], - domain="finn.custom_op.fpgadataflow", + domain="finn.custom_op.fpgadataflow.hls", backend="fpgadataflow", MW=m, MH=m, @@ -208,7 +209,7 @@ def test_fpgadataflow_ipstitch_gen_model(mem_mode): model = model.transform(GiveUniqueNodeNames()) model = model.transform(PrepareIP(test_fpga_part, 5)) model = model.transform(HLSSynthIP()) - assert model.graph.node[0].op_type == "MatrixVectorActivation" + assert model.graph.node[0].op_type == "MatrixVectorActivation_hls" assert model.graph.node[-1].op_type == "TLastMarker_hls" model.save(ip_stitch_model_dir + "/test_fpgadataflow_ipstitch_gen_model_%s.onnx" % mem_mode) From 79ef071995cf4d3c20b2687a03e5d3e461cb11dd Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 13 Feb 2024 11:28:12 +0000 Subject: [PATCH 488/665] [CustomOp] Fix typo in HLS SWG LUT estimation --- .../custom_op/fpgadataflow/hls/convolutioninputgenerator_hls.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/finn/custom_op/fpgadataflow/hls/convolutioninputgenerator_hls.py b/src/finn/custom_op/fpgadataflow/hls/convolutioninputgenerator_hls.py index 585f152550..4a5c02ee06 100644 --- a/src/finn/custom_op/fpgadataflow/hls/convolutioninputgenerator_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/convolutioninputgenerator_hls.py @@ -241,7 +241,7 @@ def bram_estimation(self): def lut_estimation(self): simd = self.get_nodeattr("SIMD") - is1D = self.get_noadeattr("is1D") + is1D = self.get_nodeattr("is1D") if not is1D: ifm_ch = self.get_nodeattr("IFMChannels") ifm_dim = self.get_nodeattr("IFMDim")[0] From 5b10b9878caf9dbb226e2e110e3db58a9c54dd7c Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 13 Feb 2024 11:28:48 +0000 Subject: [PATCH 489/665] [Tests] Update cybsec mlp test to new flow --- tests/end2end/test_end2end_cybsec_mlp.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/tests/end2end/test_end2end_cybsec_mlp.py b/tests/end2end/test_end2end_cybsec_mlp.py index 1cd38eb83a..b58b9f472c 100644 --- a/tests/end2end/test_end2end_cybsec_mlp.py +++ b/tests/end2end/test_end2end_cybsec_mlp.py @@ -168,6 +168,7 @@ def test_end2end_cybsec_mlp_build(): # check the generated files assert os.path.isfile(output_dir + "/time_per_step.json") assert os.path.isfile(output_dir + "/final_hw_config.json") + assert os.path.isfile(output_dir + "/template_specialize_layers_config.json") assert os.path.isfile(output_dir + "/driver/driver.py") est_cycles_report = output_dir + "/report/estimate_layer_cycles.json" assert os.path.isfile(est_cycles_report) @@ -181,8 +182,8 @@ def test_end2end_cybsec_mlp_build(): # examine the report contents with open(est_cycles_report, "r") as f: est_cycles_dict = json.load(f) - assert est_cycles_dict["MatrixVectorActivation_0"] == 80 - assert est_cycles_dict["MatrixVectorActivation_1"] == 64 + assert est_cycles_dict["MatrixVectorActivation_hls_0"] == 80 + assert est_cycles_dict["MatrixVectorActivation_hls_1"] == 64 with open(est_res_report, "r") as f: est_res_dict = json.load(f) assert est_res_dict["total"]["LUT"] == 7899.0 From 100d2812be58299f4fd38a7c46bd5d4a92cf48f2 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Tue, 13 Feb 2024 15:45:26 +0000 Subject: [PATCH 490/665] [hw mvau]: remove dsp/lut estimation functions, modified how ip gets stitched in and bugfix to execution of 2D tensors --- .../fpgadataflow/matrixvectoractivation.py | 99 ++----------------- 1 file changed, 10 insertions(+), 89 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index 463a4effa8..baa70c580c 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -150,11 +150,13 @@ def execute_node(self, context, graph): odt_is_bipolar = self.get_nodeattr("outputDataType") == "BIPOLAR" out_scale = 2 if odt_is_bipolar else 1 out_bias = -1 if odt_is_bipolar else self.get_nodeattr("ActVal") - # NHWC to NCHW for multithreshold node - result = result.transpose((0, 3, 1, 2)) + if result.ndim == 4: + # NHWC to NCHW for multithreshold node + result = result.transpose((0, 3, 1, 2)) result = multithreshold(result, mvau_thr, out_scale, out_bias) - # NCHW to NHWC - result = result.transpose((0, 2, 3, 1)) + if result.ndim == 4: + # NCHW to NHWC + result = result.transpose((0, 2, 3, 1)) context[node.output[0]] = result @@ -436,84 +438,6 @@ def uram_efficiency_estimation(self): uram_est_capacity = uram_est * 72 * 4096 return wbits / uram_est_capacity - def lut_estimation(self): - """Calculates resource estimations for LUTs based on: - - FINN-R: An End-to-End Deep-Learning Framework for Fast - Exploration of Quantized Neural Networks - - M. Blott, T. B. Preusser, N. J. Fraser, G. Gambardella, K. O'Brien, - Y. Umuroglu, M. Leeser and K. Vissers - - 12. Sep 2018 - """ - # TODO add in/out FIFO contributions - P = self.get_nodeattr("PE") - Q = self.get_nodeattr("SIMD") - MW = self.get_nodeattr("MW") - wdt = self.get_weight_datatype() - W = wdt.bitwidth() - # determine tdt with input and weight data types - idt = self.get_input_datatype() - A = idt.bitwidth() - # parameters from experiments in paper mentioned above - c0 = 300 - c1 = 1.1 - c2 = 0 - mmode = self.get_nodeattr("mem_mode") - mstyle = self.get_nodeattr("ram_style") - if (mmode == "decoupled" and mstyle == "distributed") or ( - mmode == "const" and self.calc_wmem() <= 128 - ): - c2 = (P * Q * W) * math.ceil(self.calc_wmem() / 64) - - # multiplication - res_type = self.get_nodeattr("resType") - if res_type == "dsp": - mult_luts = 0 - else: - mult_luts = Q * (2 * math.ceil((W + A) / 6) - 1) * (W + A) - # adder tree - addertree_luts = (W + A) * (2 * Q - 1) - # accumulator - acc_datatype = self.get_accumulator_datatype() - # if accDataType is not set, then it will default to INT32, which would - # be a large overestimate in most (if not all) cases. In this scenario, - # we would use the minimum accumulator as determined by the data types - # bound, derived in https://arxiv.org/abs/2301.13376 - alpha = math.log(MW, 2) + W + A - 1 - int(idt.signed()) - acc_bits = min( - acc_datatype.bitwidth(), - np.ceil(alpha + math.log(1 + pow(2, -alpha), 2) + 1), - ) - acc_luts = acc_bits - # thresholds and threshold comparators - thr_luts = 0 - comp_luts = 0 - noact = self.get_nodeattr("noActivation") - tmem_style = self.get_nodeattr("ram_style_thresholds") - if (noact == 0) and (tmem_style == "distributed"): - odt = self.get_output_datatype() - B = odt.bitwidth() - thr_luts = (2**B - 1) * acc_bits * math.ceil(self.calc_tmem() / 64) - comp_luts = (2**B - 1) * acc_bits - - return int( - c0 + c1 * (P * (mult_luts + addertree_luts + acc_luts + thr_luts + comp_luts)) + c2 - ) - - def dsp_estimation(self): - # multiplication - P = self.get_nodeattr("PE") - res_type = self.get_nodeattr("resType") - Q = self.get_nodeattr("SIMD") - wdt = self.get_weight_datatype() - W = wdt.bitwidth() - idt = self.get_input_datatype() - A = idt.bitwidth() - if res_type == "dsp": - mult_dsp = P * Q * np.ceil((W + A) / 48) # TODO: more accurate modelling - else: - mult_dsp = 0 - return int(mult_dsp) - def get_exp_cycles(self): pe = self.get_nodeattr("PE") simd = self.get_nodeattr("SIMD") @@ -953,12 +877,9 @@ def code_generation_ipi(self): "create_bd_intf_pin -mode Slave " "-vlnv xilinx.com:interface:axis_rtl:1.0 /%s/%s" % (node_name, din_name) ) - # instantiate the hls ip - cmd.append( - "create_bd_cell -type ip -vlnv %s /%s/%s" - % (self.get_nodeattr("ip_vlnv"), node_name, node_name) - ) - + # Instantiate either the HLS or RTL IP depending on operator + self.instantiate_ip(cmd) + # instantiate a streamer and connect it to the HLS IP strm_vlnv = "amd.com:finn:memstream:1.0" strm_inst = node_name + "_wstrm" @@ -1029,7 +950,7 @@ def code_generation_ipi(self): cmd.append("save_bd_design") elif mem_mode == "const" or mem_mode == "external": # base class impl sufficient for const/external modes - return super().code_generation_ipi() + self.instantiate_ip(cmd) else: raise Exception("Unrecognized mem_mode for MatrixVectorActivation") return cmd From 3a36ef12f0a918f597e15db95fc20ea53b6700fb Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Tue, 13 Feb 2024 15:46:07 +0000 Subject: [PATCH 491/665] [hls mvau]: added lut/dsp estimation functions, instantiate_ip method and bugfix to node execution --- .../hls/matrixvectoractivation_hls.py | 113 +++++++++++++++++- 1 file changed, 108 insertions(+), 5 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py b/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py index 5206ee3a06..aa3631a240 100644 --- a/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py @@ -33,6 +33,7 @@ from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend from finn.custom_op.fpgadataflow.matrixvectoractivation import MatrixVectorActivation from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy +from pyverilator.util.axi_utils import toggle_clk, reset_rtlsim # ONNX i/o tensor shape assumptions for MatrixVectorActivation: # input 0 is the input tensor, shape (.., i_size) = (..., MW) @@ -54,6 +55,84 @@ def get_nodeattr_types(self): my_attrs.update(HLSBackend.get_nodeattr_types(self)) return my_attrs + def lut_estimation(self): + """Calculates resource estimations for LUTs based on: + - FINN-R: An End-to-End Deep-Learning Framework for Fast + Exploration of Quantized Neural Networks + - M. Blott, T. B. Preusser, N. J. Fraser, G. Gambardella, K. O'Brien, + Y. Umuroglu, M. Leeser and K. Vissers + - 12. Sep 2018 + """ + # TODO add in/out FIFO contributions + P = self.get_nodeattr("PE") + Q = self.get_nodeattr("SIMD") + MW = self.get_nodeattr("MW") + wdt = self.get_weight_datatype() + W = wdt.bitwidth() + # determine tdt with input and weight data types + idt = self.get_input_datatype() + A = idt.bitwidth() + # parameters from experiments in paper mentioned above + c0 = 300 + c1 = 1.1 + c2 = 0 + mmode = self.get_nodeattr("mem_mode") + mstyle = self.get_nodeattr("ram_style") + if (mmode == "decoupled" and mstyle == "distributed") or ( + mmode == "const" and self.calc_wmem() <= 128 + ): + c2 = (P * Q * W) * math.ceil(self.calc_wmem() / 64) + + # multiplication + res_type = self.get_nodeattr("resType") + if res_type == "dsp": + mult_luts = 0 + else: + mult_luts = Q * (2 * math.ceil((W + A) / 6) - 1) * (W + A) + # adder tree + addertree_luts = (W + A) * (2 * Q - 1) + # accumulator + acc_datatype = self.get_accumulator_datatype() + # if accDataType is not set, then it will default to INT32, which would + # be a large overestimate in most (if not all) cases. In this scenario, + # we would use the minimum accumulator as determined by the data types + # bound, derived in https://arxiv.org/abs/2301.13376 + alpha = math.log(MW, 2) + W + A - 1 - int(idt.signed()) + acc_bits = min( + acc_datatype.bitwidth(), + np.ceil(alpha + math.log(1 + pow(2, -alpha), 2) + 1), + ) + acc_luts = acc_bits + # thresholds and threshold comparators + thr_luts = 0 + comp_luts = 0 + noact = self.get_nodeattr("noActivation") + tmem_style = self.get_nodeattr("ram_style_thresholds") + if (noact == 0) and (tmem_style == "distributed"): + odt = self.get_output_datatype() + B = odt.bitwidth() + thr_luts = (2**B - 1) * acc_bits * math.ceil(self.calc_tmem() / 64) + comp_luts = (2**B - 1) * acc_bits + + return int( + c0 + c1 * (P * (mult_luts + addertree_luts + acc_luts + thr_luts + comp_luts)) + c2 + ) + + def dsp_estimation(self): + # multiplication + P = self.get_nodeattr("PE") + res_type = self.get_nodeattr("resType") + Q = self.get_nodeattr("SIMD") + wdt = self.get_weight_datatype() + W = wdt.bitwidth() + idt = self.get_input_datatype() + A = idt.bitwidth() + if res_type == "dsp": + mult_dsp = P * Q * np.ceil((W + A) / 48) # TODO: more accurate modelling + else: + mult_dsp = 0 + return int(mult_dsp) + def get_template_param_values(self): """Returns the template parameter values according to input, output and weight data types.""" @@ -416,6 +495,7 @@ def execute_node(self, context, graph): mem_mode = self.get_nodeattr("mem_mode") node = self.onnx_node + # TODO ensure codegen dir exists if mode == "cppsim": code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") elif mode == "rtlsim": @@ -433,6 +513,7 @@ def execute_node(self, context, graph): for inputs in node.input: # it is assumed that the first input of the node is the data input # the second input are the weights + # the third input are the thresholds if in_ind == 0: assert ( str(context[inputs].dtype) == "float32" @@ -440,7 +521,12 @@ def execute_node(self, context, graph): not float32 as expected.""" expected_inp_shape = self.get_folded_input_shape() reshaped_input = context[inputs].reshape(expected_inp_shape) - export_idt = self.get_input_datatype() + if self.get_input_datatype() == DataType["BIPOLAR"]: + # store bipolar activations as binary + reshaped_input = (reshaped_input + 1) / 2 + export_idt = DataType["BINARY"] + else: + export_idt = self.get_input_datatype() # make copy before saving the array reshaped_input = reshaped_input.copy() np.save( @@ -468,11 +554,15 @@ def execute_node(self, context, graph): sim = self.get_rtlsim() nbits = self.get_instream_width() inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) - self.reset_rtlsim(sim) - self.toggle_clk(sim) - if mem_mode in ["external", "decoupled"]: + reset_rtlsim(sim) + toggle_clk(sim) + if mem_mode == "external" or mem_mode == "decoupled": wnbits = self.get_weightstream_width() export_wdt = self.get_weight_datatype() + # we have converted bipolar weights to binary for export, + # so use it as such for weight generation + if self.get_weight_datatype() == DataType["BIPOLAR"]: + export_wdt = DataType["BINARY"] wei = npy_to_rtlsim_input("{}/weights.npy".format(code_gen_dir), export_wdt, wnbits) num_w_reps = np.prod(self.get_nodeattr("numInputVectors")) io_dict = { @@ -489,6 +579,7 @@ def execute_node(self, context, graph): out_npy_path = "{}/output.npy".format(code_gen_dir) out_shape = self.get_folded_output_shape() rtlsim_output_to_npy(output, out_npy_path, odt, out_shape, packed_bits, target_bits) + # load and reshape output output = np.load(out_npy_path) oshape = self.get_normal_output_shape() @@ -497,7 +588,19 @@ def execute_node(self, context, graph): else: raise Exception( """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to "rtlsim" """.format( + has to be set to one of the following value ("cppsim", "rtlsim")""".format( mode ) ) + + def instantiate_ip(self, cmd): + # instantiate the HLS IP + vlnv = self.get_nodeattr("ip_vlnv") + node_name = self.onnx_node.name + if self.get_nodeattr("mem_mode") == "decoupled": + cmd.append( + "create_bd_cell -type ip -vlnv %s /%s/%s" + % (vlnv, node_name, node_name) + ) + else: + cmd.append("create_bd_cell -type ip -vlnv %s %s" % (vlnv, self.onnx_node.name)) \ No newline at end of file From 4266e0872686b967f3b2ec0d0d68d4d852138cb5 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Tue, 13 Feb 2024 16:12:09 +0000 Subject: [PATCH 492/665] [test]: added GiveUniqueNodeNames transform and changed RTLsim test preparation --- tests/fpgadataflow/test_fpgadataflow_mvau.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_mvau.py b/tests/fpgadataflow/test_fpgadataflow_mvau.py index 7e632b4018..1853392724 100644 --- a/tests/fpgadataflow/test_fpgadataflow_mvau.py +++ b/tests/fpgadataflow/test_fpgadataflow_mvau.py @@ -273,6 +273,7 @@ def test_fpgadataflow_fclayer_cppsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): else: tdt = DataType["INT32"] model = make_single_fclayer_modelwrapper(W, pe, simd, wdt, idt, odt, T, tdt) + model = model.transform(GiveUniqueNodeNames()) for node in model.graph.node: # lookup op_type in registry of CustomOps inst = getCustomOp(node) @@ -280,6 +281,7 @@ def test_fpgadataflow_fclayer_cppsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): # Note: only HLS-based MVAU layers execute CPPsim inst.set_nodeattr("preferred_impl_style", "hls") model = model.transform(SpecializeLayers()) + model = model.transform(GiveUniqueNodeNames()) model = model.transform(SetExecMode("cppsim")) model = model.transform(PrepareCppSim()) model = model.transform(CompileCppSim()) @@ -389,8 +391,7 @@ def test_fpgadataflow_fclayer_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): # TODO split up into several dependent tests -- need to check how this # works for parametrized tests... model = model.transform(SpecializeLayers()) - # model = model.transform(SetExecMode("rtlsim")) - model.set_metadata_prop("exec_mode", "rtlsim") + model = model.transform(SetExecMode("rtlsim")) model = model.transform(GiveUniqueNodeNames()) model = model.transform(PrepareIP("xc7z020clg400-1", 5)) model = model.transform(HLSSynthIP()) From 5dfc440695c4530e2e0cf517e7a60a373cfd6019 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Tue, 13 Feb 2024 16:14:55 +0000 Subject: [PATCH 493/665] post linting --- .../fpgadataflow/hls/matrixvectoractivation_hls.py | 10 ++++------ .../custom_op/fpgadataflow/matrixvectoractivation.py | 2 +- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py b/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py index aa3631a240..f2119667bf 100644 --- a/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py @@ -26,14 +26,15 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +import math import numpy as np import os +from pyverilator.util.axi_utils import reset_rtlsim, toggle_clk from qonnx.core.datatype import DataType from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend from finn.custom_op.fpgadataflow.matrixvectoractivation import MatrixVectorActivation from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy -from pyverilator.util.axi_utils import toggle_clk, reset_rtlsim # ONNX i/o tensor shape assumptions for MatrixVectorActivation: # input 0 is the input tensor, shape (.., i_size) = (..., MW) @@ -598,9 +599,6 @@ def instantiate_ip(self, cmd): vlnv = self.get_nodeattr("ip_vlnv") node_name = self.onnx_node.name if self.get_nodeattr("mem_mode") == "decoupled": - cmd.append( - "create_bd_cell -type ip -vlnv %s /%s/%s" - % (vlnv, node_name, node_name) - ) + cmd.append("create_bd_cell -type ip -vlnv %s /%s/%s" % (vlnv, node_name, node_name)) else: - cmd.append("create_bd_cell -type ip -vlnv %s %s" % (vlnv, self.onnx_node.name)) \ No newline at end of file + cmd.append("create_bd_cell -type ip -vlnv %s %s" % (vlnv, self.onnx_node.name)) diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index baa70c580c..1b6be752dc 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -879,7 +879,7 @@ def code_generation_ipi(self): ) # Instantiate either the HLS or RTL IP depending on operator self.instantiate_ip(cmd) - + # instantiate a streamer and connect it to the HLS IP strm_vlnv = "amd.com:finn:memstream:1.0" strm_inst = node_name + "_wstrm" From a6a3d4cc7dfb99ca48c2f543fe019c11681a7f21 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Tue, 13 Feb 2024 17:03:41 +0000 Subject: [PATCH 494/665] [tests] Split threshold runtime tests to runtime read and write tests --- .../test_fpgadataflow_thresholding.py | 167 ++++++++++++++---- 1 file changed, 128 insertions(+), 39 deletions(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_thresholding.py b/tests/fpgadataflow/test_fpgadataflow_thresholding.py index 3daf44a055..f1be5f89a7 100644 --- a/tests/fpgadataflow/test_fpgadataflow_thresholding.py +++ b/tests/fpgadataflow/test_fpgadataflow_thresholding.py @@ -42,7 +42,7 @@ import finn.core.onnx_exec as oxe from finn.analysis.fpgadataflow.exp_cycles_per_layer import exp_cycles_per_layer from finn.analysis.fpgadataflow.hls_synth_res_estimation import hls_synth_res_estimation -from finn.core.rtlsim_exec import rtlsim_exec +from finn.core.rtlsim_exec import rtlsim_exec, reset_rtlsim from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP @@ -150,7 +150,7 @@ def test_fpgadataflow_thresholding(impl_style,idt, act, nf, ich, exec_mode, mem_ odt = act n_steps = act.get_num_possible_values() - 1 - + # Generate random, non-decreasing thresholds thresholds = generate_random_threshold_values( idt, ich, n_steps @@ -165,16 +165,16 @@ def test_fpgadataflow_thresholding(impl_style,idt, act, nf, ich, exec_mode, mem_ # Build DUT model = make_single_thresholding_modelwrapper( - impl_style, - thresholds, - pe, - idt, - odt, - actval, - mem_mode, + impl_style, + thresholds, + pe, + idt, + odt, + actval, + mem_mode, n_inp_vecs ) - + # Expected Reference output # multithreshold util fxn wants NCHW input, not NHWC x_nchw = layout_FINN2NCHW(x) @@ -238,24 +238,29 @@ def test_fpgadataflow_thresholding(impl_style,idt, act, nf, ich, exec_mode, mem_ assert exp_cycles != 0 @pytest.mark.parametrize("impl_style", ["rtl", "hls"]) +@pytest.mark.parametrize("cf", [2]) +@pytest.mark.parametrize("ch", [6]) @pytest.mark.fpgadataflow @pytest.mark.vivado -def test_runtime_thresholds_single_layer(impl_style): +def test_runtime_thresholds_read(impl_style,cf,ch): + """ Read back threshold weights during runtime + + 1. Create random initial weights T + 2. Execute model + 3. Read back weights via AXI + 4. Compare with initial weights T + """ n_inp_vecs = [1, 2, 2] mem_mode = "decoupled" act = DataType["INT4"] idt = DataType["INT16"] - nf = 8 - ich = 16 - pe = ich // nf - assert ich % pe == 0 - - # generate input data - in_tensor = gen_finn_dt_tensor(idt, tuple(n_inp_vecs + [ich])) + pe = ch // cf + assert ch % pe == 0 odt = act n_steps = act.get_num_possible_values() - 1 - T = np.random.randint(idt.min(), idt.max() + 1, (ich, n_steps)).astype(np.float32) + np.random.seed(2) + T = np.random.randint(idt.min(), idt.max() + 1, (ch, n_steps)).astype(np.float32) # provide non-decreasing thresholds T = np.sort(T, axis=1) @@ -290,10 +295,12 @@ def test_runtime_thresholds_single_layer(impl_style): # add two copies of the input tensor as the first one is just used to # "flush out" the pipeline (as mvau already starts receiving old weights while # we read/write new ones and reads seem to cause a disturbance too) + # generate input data + in_tensor = gen_finn_dt_tensor(idt, tuple(n_inp_vecs + [ch])) in_tensor = np.tile(in_tensor, (2, 1, 1, 1)) + exec_ctx = {"inp": in_tensor} extracted_weight_stream = [] - def read_weights(sim): addr = 0 for i in range(len(old_weight_stream)): @@ -301,51 +308,133 @@ def read_weights(sim): addr += 4 rtlsim_exec(model, exec_ctx, pre_hook=read_weights) + + # Validate the AXI Read weights assert extracted_weight_stream == old_weight_stream - # only use second batch element in output; first will be invalid due to - # old weights (see above) - y = exec_ctx["outp"][1] + + y = exec_ctx["outp"][0] # multithreshold util fxn wants NCHW input, not NHWC expected = multithreshold(np.transpose(in_tensor, (0, 3, 1, 2)), T) # convert back to NHWC for comparison to hw outputs expected = np.transpose(expected, (0, 2, 3, 1))[1] - # expected = multithreshold(in_tensor, T)[1] if act == DataType["BIPOLAR"]: - # binary to bipolar + # binary to bipolarW expected = 2 * expected - 1 else: # signed offset expected += act.min() + + # Validate the output is as expected assert (y == expected).all() - new_weights = np.random.randint(idt.min(), idt.max() + 1, (ich, n_steps)).astype(np.float32) +@pytest.mark.parametrize("impl_style", ["rtl", "hls"]) +@pytest.mark.parametrize("cf", [8]) +@pytest.mark.parametrize("ch", [16]) +@pytest.mark.fpgadataflow +@pytest.mark.vivado +def test_runtime_thresholds_write(impl_style,cf,ch): + """ Write threshold weights during runtime + + 1. Create random initial weights T_init + 2. Create model with initial weights + 3. Create new set of weights T_write + 4. Write T_write using AXI bus + 5. Read back using AXI bus to T_read + 6. Compare T_write and T_read + 7. Validate outputs with expected vectors + """ + n_inp_vecs = [1, 2, 2] + mem_mode = "decoupled" + act = DataType["INT4"] + idt = DataType["INT16"] + pe = ch // cf + assert ch % pe == 0 + + odt = act + n_steps = act.get_num_possible_values() - 1 + np.random.seed(2) + T_init = np.random.randint(idt.min(), idt.max() + 1, (ch, n_steps)).astype(np.float32) + # provide non-decreasing thresholds + T_init = np.sort(T_init, axis=1) + + if odt == DataType["BIPOLAR"]: + actval = 0 + else: + actval = odt.min() + + model = make_single_thresholding_modelwrapper(impl_style, T_init, pe, idt, odt, actval, mem_mode, n_inp_vecs) + model = model.transform(SpecializeLayers()) + + # Validate that specialize layer did not default to HLS implementation + assert model.graph.node[0].op_type == "Thresholding_" + str(impl_style) + + op_inst = getCustomOp(model.graph.node[0]) + op_inst.set_nodeattr("runtime_writeable_weights", 1) + + # Make new weights for runtime write + np.random.seed(4) + T_write = np.random.randint(idt.min(), idt.max() + 1, (ch, n_steps)).astype(np.float32) # provide non-decreasing thresholds - new_weights = np.sort(T, axis=1) - op_inst.make_weight_file(new_weights, "decoupled_runtime", "new_weights.dat") - with open("new_weights.dat", "r") as f: - new_weight_stream = f.read().strip() - os.remove("new_weights.dat") - new_weight_stream = map(lambda x: int(x, 16), new_weight_stream.split("\n")) - new_weight_stream = list(new_weight_stream) + T_write = np.sort(T_write, axis=1) + + op_inst.make_weight_file(T_write, "decoupled_runtime", "T_write.dat") + with open("T_write.dat", "r") as f: + T_write_stream = f.read().strip() + os.remove("T_write.dat") + + T_write_stream = map(lambda x: int(x, 16), T_write_stream.split("\n")) + T_write_stream = list(T_write_stream) + + # need to create stitched IP for runtime weight testing + model = model.transform(InsertFIFO(True)) + model = model.transform(SpecializeLayers()) + model = model.transform(GiveUniqueNodeNames()) + model = model.transform(PrepareIP(test_fpga_part, target_clk_ns)) + model = model.transform(HLSSynthIP()) + model = model.transform(CreateStitchedIP(test_fpga_part, target_clk_ns)) + model = model.transform(PrepareRTLSim()) + model.set_metadata_prop("exec_mode", "rtlsim") + # add two copies of the input tensor as the first one is just used to + # "flush out" the pipeline (as mvau already starts receiving old weights while + # we read/write new ones and reads seem to cause a disturbance too) + # generate input data + in_tensor = gen_finn_dt_tensor(idt, tuple(n_inp_vecs + [ch])) + in_tensor = np.tile(in_tensor, (2, 1, 1, 1)) + # trace_file = "trace_wr_01.vcd" + # model.set_metadata_prop("rtlsim_trace",trace_file) + exec_ctx_write = {"inp": in_tensor} def write_weights(sim): addr = 0 - for nw in new_weight_stream: + for nw in T_write_stream: axilite_write(sim, addr, nw, basename="s_axilite_0_") addr += 4 + T_read_stream = [] + def read_weights(sim): + addr = 0 + for i in range(len(T_write_stream)): + T_read_stream.append(axilite_read(sim, addr, basename="s_axilite_0_")) + addr += 4 + + rtlsim_exec(model, exec_ctx_write, pre_hook=write_weights, post_hook=read_weights) + + y = exec_ctx_write["outp"][1] + + assert T_read_stream == T_write_stream - rtlsim_exec(model, exec_ctx, pre_hook=write_weights) - y = exec_ctx["outp"][1] # multithreshold util fxn wants NCHW input, not NHWC - expected = multithreshold(np.transpose(in_tensor, (0, 3, 1, 2)), new_weights) + expected = multithreshold(np.transpose(in_tensor, (0, 3, 1, 2)), T_write) # convert back to NHWC for comparison to hw outputs expected = np.transpose(expected, (0, 2, 3, 1))[1] + if act == DataType["BIPOLAR"]: - # binary to bipolar + # binary to bipolarW expected = 2 * expected - 1 else: # signed offset expected += act.min() - assert (y == expected).all() + + # Validate the output is as expected + assert (y == expected).all() \ No newline at end of file From 9c96192eeac5fd709eb72e9c0f1df0e2c480ba6c Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Tue, 13 Feb 2024 17:04:26 +0000 Subject: [PATCH 495/665] [CustomOp] Zero pad row of threshold weight dat file --- .../fpgadataflow/rtl/thresholding_rtl.py | 77 ++++++------------- 1 file changed, 24 insertions(+), 53 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py index 714930b73d..54797e1b94 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py @@ -183,7 +183,7 @@ def get_weight_datatype(self): def minimize_accumulator_width(self, model): "Minimize threshold width ('accumulator width' here due to convention)" thresholds = model.get_initializer(self.onnx_node.input[1]) - threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds) + threshold_tensor = self.get_hw_compatible_threshold_tensor(thresholds) min_threshold = thresholds.min() max_threshold = thresholds.max() min_input = self.get_input_datatype().min() @@ -248,7 +248,7 @@ def get_exp_cycles(self): # Channels/PE * batch size * fmdim * fmdim return np.prod(self.get_folded_output_shape()[:-1]) - def get_hls_compatible_threshold_tensor(self, orig_thres_matrix): + def get_hw_compatible_threshold_tensor(self, orig_thres_matrix): """Convert the original numpy weight matrix orig_weight_matrix into a form suitable for passing to the hlslib call: * ensure MH % PE == 0 @@ -661,12 +661,13 @@ def get_verilog_top_module_intf_names(self): return intf_names - def get_dynamic_config(self, model, address_stride=1): + def get_dynamic_config(self, weights, address_stride=1): """Returns a configuration dictionary containing axilite write commands in order to program the thresholds into the RTL core during runtime. The default address stride for the weights is 1 byte.""" - thresholds = model.get_initializer(self.onnx_node.input[1]) + # thresholds = model.get_initializer(self.onnx_node.input[1]) + thresholds = weights num_channels, num_weights_per_channel = thresholds.shape weight_addr_boundary = find_next_power_of_2(num_weights_per_channel) @@ -740,7 +741,7 @@ def make_weight_file(self, weights, weight_file_mode, weight_file_name): * weight_file_name : filename for the weight file to be generated """ - threshold_tensor = self.get_hls_compatible_threshold_tensor(weights) + threshold_tensor = self.get_hw_compatible_threshold_tensor(weights) tdt = self.get_weight_datatype() assert np.vectorize(tdt.allowed)( threshold_tensor @@ -760,52 +761,22 @@ def make_weight_file(self, weights, weight_file_mode, weight_file_name): 1, -1, pe * n_thres_steps ) decoupled_thres_pe_flipped = decoupled_thres_pe_flipped.copy() - width_padded = roundup_to_integer_multiple(pe * n_thres_steps, 4) - - # zero pad the columns - thres_padded = np.zeros((1, self.calc_tmem() ,width_padded)) - thres_padded[0, :self.calc_tmem(), :(pe * n_thres_steps) ] = decoupled_thres_pe_flipped - decoupled_thres_pe_flipped = thres_padded.copy() - weight_tensor_pe_flipped = [] - if weight_file_mode == "decoupled_npy": - # save weight stream into npy for cppsim - np.save(weight_file_name, decoupled_thres) - elif weight_file_mode == "decoupled_verilog_dat": - # convert weight values into hexstring - weight_width = self.get_weightstream_width() - # pad to nearest 4 bits to get hex strings - weight_width_padded = roundup_to_integer_multiple(weight_width, 4) - weight_tensor_pe_flipped = pack_innermost_dim_as_hex_string( - decoupled_thres_pe_flipped, tdt, weight_width_padded, prefix="" - ) - weight_stream = weight_tensor_pe_flipped.flatten() - weight_stream = weight_stream.copy() - with open(weight_file_name, "w") as f: - for val in weight_stream: - f.write(val + "\n") - elif weight_file_mode == "decoupled_runtime": - # memstream axi-lite interface will map each mem line to - # one or multiple 32-bit words - weight_width = self.get_weightstream_width() - words_per_memwidth = 2 ** ceil(log2(weight_width / 32)) - if words_per_memwidth < 1: - words_per_memwidth = 1 - weight_width_padded = words_per_memwidth * 32 # convert to bits - # first, pack and ensure padding to 32 bits - for channel in decoupled_thres_pe_flipped[0]: - for weight in channel: - wdt = self.get_weight_datatype() - bw_hexdigit = roundup_to_integer_multiple(wdt.bitwidth(), 32) - weight_tensor_pe_flipped.append(pack_innermost_dim_as_hex_string( - [weight], wdt, bw_hexdigit, prefix="" - ).item()) - weight_stream = weight_tensor_pe_flipped.copy() - - with open(weight_file_name, "w") as f: - for val in weight_stream: - f.write(val + "\n") - else: - raise Exception("Decoupled weight export not yet implemented") - else: - raise Exception("Unknown weight_file_mode") + width_padded = roundup_to_integer_multiple(weights.shape[1], 4) + # # zero pad the row + weight_padded = np.zeros((weights.shape[0],width_padded)) + weight_padded[:weights.shape[0], :n_thres_steps ] = weights + weight_stream = [] + for channel in weight_padded: + for weight in channel: + wdt = self.get_weight_datatype() + bw_hexdigit = roundup_to_integer_multiple(wdt.bitwidth(), 32) + weight_stream.append(pack_innermost_dim_as_hex_string( + [weight], wdt, bw_hexdigit, prefix="" + ).item()) + + with open(weight_file_name, "w") as f: + for val in weight_stream: + f.write(val + "\n") + else: + raise Exception("Unknown weight_file_mode") \ No newline at end of file From 13c7ffb3bc9303c0aa87d227501589fcb3eebb3b Mon Sep 17 00:00:00 2001 From: Felix Jentzsch Date: Fri, 16 Feb 2024 09:48:33 +0100 Subject: [PATCH 496/665] Add stream padding to RTL SWG --- finn-rtllib/swg/swg_template_wrapper.v | 10 ++++++---- finn-rtllib/swg/swg_template_wrapper_dynamic.v | 10 ++++++---- .../fpgadataflow/convolutioninputgenerator_rtl.py | 7 +++++++ .../test_fpgadataflow_convinputgenerator_rtl.py | 2 +- 4 files changed, 20 insertions(+), 9 deletions(-) diff --git a/finn-rtllib/swg/swg_template_wrapper.v b/finn-rtllib/swg/swg_template_wrapper.v index 11fa0a88cb..22dc6bd8cd 100644 --- a/finn-rtllib/swg/swg_template_wrapper.v +++ b/finn-rtllib/swg/swg_template_wrapper.v @@ -35,10 +35,10 @@ module $TOP_MODULE_NAME$ ( input ap_clk, (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) input ap_rst_n, - input [BUF_IN_WIDTH-1:0] in0_V_TDATA, + input [IN_WIDTH_PADDED-1:0] in0_V_TDATA, input in0_V_TVALID, output in0_V_TREADY, - output [BUF_OUT_WIDTH-1:0] out_V_TDATA, + output [OUT_WIDTH_PADDED-1:0] out_V_TDATA, output out_V_TVALID, input out_V_TREADY ); @@ -48,6 +48,8 @@ parameter BIT_WIDTH = $BIT_WIDTH$; parameter SIMD = $SIMD$; parameter MMV_IN = $MMV_IN$; parameter MMV_OUT = $MMV_OUT$; +parameter IN_WIDTH_PADDED = $IN_WIDTH_PADDED$; +parameter OUT_WIDTH_PADDED = $OUT_WIDTH_PADDED$; // derived constants parameter BUF_IN_WIDTH = BIT_WIDTH * SIMD * MMV_IN; @@ -61,10 +63,10 @@ $TOP_MODULE_NAME$_impl #( ) impl ( .ap_clk(ap_clk), .ap_rst_n(ap_rst_n), - .in0_V_V_TDATA(in0_V_TDATA), + .in0_V_V_TDATA(in0_V_TDATA[BUF_IN_WIDTH-1:0]), .in0_V_V_TVALID(in0_V_TVALID), .in0_V_V_TREADY(in0_V_TREADY), - .out_V_V_TDATA(out_V_TDATA), + .out_V_V_TDATA(out_V_TDATA[BUF_OUT_WIDTH-1:0]), .out_V_V_TVALID(out_V_TVALID), .out_V_V_TREADY(out_V_TREADY) ); diff --git a/finn-rtllib/swg/swg_template_wrapper_dynamic.v b/finn-rtllib/swg/swg_template_wrapper_dynamic.v index 5c09e7c1b4..158f3132e3 100644 --- a/finn-rtllib/swg/swg_template_wrapper_dynamic.v +++ b/finn-rtllib/swg/swg_template_wrapper_dynamic.v @@ -35,6 +35,8 @@ module $TOP_MODULE_NAME$ #( parameter SIMD = $SIMD$, parameter MMV_IN = $MMV_IN$, parameter MMV_OUT = $MMV_OUT$, + parameter IN_WIDTH_PADDED = $IN_WIDTH_PADDED$, + parameter OUT_WIDTH_PADDED = $OUT_WIDTH_PADDED$, parameter CNTR_BITWIDTH = $CNTR_BITWIDTH$, parameter INCR_BITWIDTH = $INCR_BITWIDTH$, @@ -52,10 +54,10 @@ module $TOP_MODULE_NAME$ #( input ap_clk, (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) input ap_rst_n, - input [BUF_IN_WIDTH-1:0] in0_V_TDATA, + input [IN_WIDTH_PADDED-1:0] in0_V_TDATA, input in0_V_TVALID, output in0_V_TREADY, - output [BUF_OUT_WIDTH-1:0] out_V_TDATA, + output [OUT_WIDTH_PADDED-1:0] out_V_TDATA, output out_V_TVALID, input out_V_TREADY, @@ -153,10 +155,10 @@ $TOP_MODULE_NAME$_impl #( ) impl ( .ap_clk(ap_clk), .ap_rst_n(ap_rst_n), - .in0_V_V_TDATA(in0_V_TDATA), + .in0_V_V_TDATA(in0_V_TDATA[BUF_IN_WIDTH-1:0]), .in0_V_V_TVALID(in0_V_TVALID), .in0_V_V_TREADY(in0_V_TREADY), - .out_V_V_TDATA(out_V_TDATA), + .out_V_V_TDATA(out_V_TDATA[BUF_OUT_WIDTH-1:0]), .out_V_V_TVALID(out_V_TVALID), .out_V_V_TREADY(out_V_TREADY), diff --git a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py index 734f75a973..d3e5576354 100755 --- a/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py +++ b/src/finn/custom_op/fpgadataflow/convolutioninputgenerator_rtl.py @@ -33,6 +33,7 @@ from qonnx.core.datatype import DataType from qonnx.custom_op.general import im2col from qonnx.custom_op.general.im2col import compute_conv_output_dim +from qonnx.util.basic import roundup_to_integer_multiple from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp from finn.util.basic import get_rtlsim_trace_depth, make_build_dir @@ -991,6 +992,12 @@ def generate_hdl(self): # (e.g. by GiveUniqueNodeNames(prefix) during MakeZynqProject) self.set_nodeattr("gen_top_module", self.get_verilog_top_module_name()) code_gen_dict["$BIT_WIDTH$"] = [str(self.get_input_datatype().bitwidth())] + code_gen_dict["$IN_WIDTH_PADDED$"] = [ + str(roundup_to_integer_multiple(self.get_instream_width(), 8)) + ] + code_gen_dict["$OUT_WIDTH_PADDED$"] = [ + str(roundup_to_integer_multiple(self.get_outstream_width(), 8)) + ] ram_style = self.get_nodeattr("ram_style") code_gen_dict["$RAM_STYLE$"] = ['"{}"'.format(ram_style)] diff --git a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py index 62b7abe536..4b6f9f4913 100755 --- a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py +++ b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl.py @@ -134,7 +134,7 @@ def prepare_inputs(input_tensor): # input datatype -@pytest.mark.parametrize("idt", [DataType["UINT4"]]) +@pytest.mark.parametrize("idt", [DataType["INT2"], DataType["UINT4"]]) # kernel size @pytest.mark.parametrize("k", [[3, 3], [1, 5]]) # input dimension From 526e71fb61ff29758aef47d874b34f59c0451c3a Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 16 Feb 2024 15:19:05 +0000 Subject: [PATCH 497/665] [hls mvau]: minor style change --- .../custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py b/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py index f2119667bf..5b85323f32 100644 --- a/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py @@ -601,4 +601,4 @@ def instantiate_ip(self, cmd): if self.get_nodeattr("mem_mode") == "decoupled": cmd.append("create_bd_cell -type ip -vlnv %s /%s/%s" % (vlnv, node_name, node_name)) else: - cmd.append("create_bd_cell -type ip -vlnv %s %s" % (vlnv, self.onnx_node.name)) + cmd.append("create_bd_cell -type ip -vlnv %s %s" % (vlnv, node_name)) \ No newline at end of file From 1091ce9214a98daaf1f127f2cc86e54e075d0640 Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 16 Feb 2024 15:25:57 +0000 Subject: [PATCH 498/665] [Builder] Expose swg expection for FIFOs to build args --- src/finn/builder/build_dataflow_config.py | 4 ++++ src/finn/builder/build_dataflow_steps.py | 1 + 2 files changed, 5 insertions(+) diff --git a/src/finn/builder/build_dataflow_config.py b/src/finn/builder/build_dataflow_config.py index 1b22265a4d..4cbcfb21c3 100644 --- a/src/finn/builder/build_dataflow_config.py +++ b/src/finn/builder/build_dataflow_config.py @@ -296,6 +296,10 @@ class DataflowBuildConfig: #: Which memory mode will be used for compute layers default_mem_mode: Optional[ComputeEngineMemMode] = ComputeEngineMemMode.DECOUPLED + #: Call CapConvolutionFIFODepths in InsertAndSetFIFODepths transform + #: to make convolution FIFOs smaller where appropriate + default_swg_exception: Optional[bool] = False + #: Which Vitis platform will be used. #: Only relevant when `shell_flow_type = ShellFlowType.VITIS_ALVEO` #: e.g. "xilinx_u250_xdma_201830_2" diff --git a/src/finn/builder/build_dataflow_steps.py b/src/finn/builder/build_dataflow_steps.py index d031e971f1..a75bbe98a1 100644 --- a/src/finn/builder/build_dataflow_steps.py +++ b/src/finn/builder/build_dataflow_steps.py @@ -573,6 +573,7 @@ def step_set_fifo_depths(model: ModelWrapper, cfg: DataflowBuildConfig): InsertAndSetFIFODepths( cfg._resolve_fpga_part(), cfg._resolve_hls_clk_period(), + swg_exception=cfg.default_swg_exception, vivado_ram_style=cfg.large_fifo_mem_style, force_python_sim=force_python_sim, ) From 462a79c6ab308fef29885b9c5911aec8b3634d69 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 16 Feb 2024 15:28:57 +0000 Subject: [PATCH 499/665] linting --- .../custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py b/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py index 5b85323f32..f40e6d78e8 100644 --- a/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py @@ -601,4 +601,4 @@ def instantiate_ip(self, cmd): if self.get_nodeattr("mem_mode") == "decoupled": cmd.append("create_bd_cell -type ip -vlnv %s /%s/%s" % (vlnv, node_name, node_name)) else: - cmd.append("create_bd_cell -type ip -vlnv %s %s" % (vlnv, node_name)) \ No newline at end of file + cmd.append("create_bd_cell -type ip -vlnv %s %s" % (vlnv, node_name)) From f31f8449c21950daf9543333b09e66c472eac068 Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 16 Feb 2024 15:30:02 +0000 Subject: [PATCH 500/665] [IPStitching] Check if node has hls or rtl backend --- .../transformation/fpgadataflow/create_stitched_ip.py | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/create_stitched_ip.py b/src/finn/transformation/fpgadataflow/create_stitched_ip.py index 0ce0923934..a8ecdcf484 100644 --- a/src/finn/transformation/fpgadataflow/create_stitched_ip.py +++ b/src/finn/transformation/fpgadataflow/create_stitched_ip.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (c) 2020, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -40,7 +41,7 @@ ReplaceVerilogRelPaths, ) from finn.util.basic import make_build_dir -from finn.util.fpgadataflow import is_fpgadataflow_node +from finn.util.fpgadataflow import is_hls_node, is_rtl_node def is_external_input(model, node, i): @@ -302,7 +303,9 @@ def apply(self, model): ) for node in model.graph.node: # ensure that all nodes are fpgadataflow, and that IPs are generated - assert is_fpgadataflow_node(node), "All nodes must be FINN fpgadataflow nodes." + assert is_hls_node(node) or is_rtl_node( + node + ), "All nodes must be FINN fpgadataflow nodes." node_inst = getCustomOp(node) ip_dir_value = node_inst.get_nodeattr("ip_path") assert os.path.isdir(ip_dir_value), "IP generation directory doesn't exist." From 91679a1f7af6b8dc6ee630bd366730cced3bfa27 Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 16 Feb 2024 16:48:35 +0000 Subject: [PATCH 501/665] [MVAU] Shorten op type MatrixVectorActivation to MVAU --- .../analysis/fpgadataflow/res_estimation.py | 10 ++++---- src/finn/custom_op/fpgadataflow/__init__.py | 4 ++-- .../custom_op/fpgadataflow/hls/__init__.py | 6 ++--- .../hls/matrixvectoractivation_hls.py | 6 ++--- .../fpgadataflow/matrixvectoractivation.py | 5 +--- .../build_dataflow/folding_config.json | 12 +++++----- .../specialize_layers_config.json | 8 +++---- .../test_ext_weights/tfc-w1a1-extw.json | 12 +++++----- .../fpgadataflow/convert_to_hw_layers.py | 12 +++++----- .../fpgadataflow/create_stitched_ip.py | 2 +- .../transformation/fpgadataflow/floorplan.py | 2 +- .../transformation/fpgadataflow/insert_dwc.py | 2 +- .../fpgadataflow/insert_iodma.py | 3 +-- .../fpgadataflow/insert_tlastmarker.py | 4 ++-- .../fpgadataflow/make_pynq_driver.py | 4 +--- .../fpgadataflow/make_zynq_proj.py | 4 +--- .../fpgadataflow/set_fifo_depths.py | 10 ++++---- .../fpgadataflow/set_folding.py | 2 +- .../fpgadataflow/specialize_layers.py | 2 +- src/finn/transformation/move_reshape.py | 2 +- src/finn/util/create.py | 2 +- tests/end2end/test_end2end_bnn_pynq.py | 24 +++++++++---------- tests/end2end/test_end2end_cybsec_mlp.py | 4 ++-- tests/end2end/test_end2end_mobilenet_v1.py | 2 +- tests/fpgadataflow/test_code_gen_trafo.py | 2 +- tests/fpgadataflow/test_compilation_trafo.py | 2 +- .../test_convert_to_hw_1d_conv_layer.py | 2 +- .../test_convert_to_hw_conv_layer.py | 2 +- .../test_convert_to_hw_layers_cnv.py | 4 ++-- .../test_convert_to_hw_layers_fc.py | 16 ++++++------- .../test_fpgadataflow_checksum.py | 4 ++-- ...dataflow_convinputgenerator_rtl_dynamic.py | 2 +- .../fpgadataflow/test_fpgadataflow_deconv.py | 10 ++++---- .../test_fpgadataflow_ipstitch.py | 8 +++---- tests/fpgadataflow/test_fpgadataflow_mvau.py | 12 +++++----- .../test_fpgadataflow_res_estimate.py | 8 ++++--- tests/fpgadataflow/test_minimize_bit_width.py | 16 ++++++------- tests/fpgadataflow/test_set_folding.py | 2 +- tests/fpgadataflow/test_split_large_fifos.py | 6 ++--- 39 files changed, 116 insertions(+), 124 deletions(-) diff --git a/src/finn/analysis/fpgadataflow/res_estimation.py b/src/finn/analysis/fpgadataflow/res_estimation.py index 000e1208d7..c2d0cf7048 100644 --- a/src/finn/analysis/fpgadataflow/res_estimation.py +++ b/src/finn/analysis/fpgadataflow/res_estimation.py @@ -28,7 +28,7 @@ import qonnx.custom_op.registry as registry -from finn.util.fpgadataflow import is_fpgadataflow_node +from finn.util.fpgadataflow import is_hls_node, is_rtl_node def res_estimation(model): @@ -41,7 +41,7 @@ def res_estimation(model): res_dict = {} for node in model.graph.node: - if is_fpgadataflow_node(node) is True: + if is_hls_node(node) or is_rtl_node(node): inst = registry.getCustomOp(node) res_dict[node.name] = inst.node_res_estimation() @@ -59,12 +59,10 @@ def res_estimation_complete(model): res_dict = {} for node in model.graph.node: - if is_fpgadataflow_node(node) is True: + if is_hls_node(node) or is_rtl_node(node): inst = registry.getCustomOp(node) op_type = node.op_type - if op_type.startswith("MatrixVectorActivation") or op_type.startswith( - "VectorVectorActivation" - ): + if op_type.startswith("MVAU") or op_type.startswith("VectorVectorActivation"): orig_restype = inst.get_nodeattr("resType") res_dict[node.name] = [] inst.set_nodeattr("resType", "dsp") diff --git a/src/finn/custom_op/fpgadataflow/__init__.py b/src/finn/custom_op/fpgadataflow/__init__.py index d4c9904fe1..6154bdc924 100644 --- a/src/finn/custom_op/fpgadataflow/__init__.py +++ b/src/finn/custom_op/fpgadataflow/__init__.py @@ -40,7 +40,7 @@ from finn.custom_op.fpgadataflow.globalaccpool import GlobalAccPool from finn.custom_op.fpgadataflow.labelselect import LabelSelect from finn.custom_op.fpgadataflow.lookup import Lookup -from finn.custom_op.fpgadataflow.matrixvectoractivation import MatrixVectorActivation +from finn.custom_op.fpgadataflow.matrixvectoractivation import MVAU from finn.custom_op.fpgadataflow.pool import Pool from finn.custom_op.fpgadataflow.streamingdataflowpartition import ( StreamingDataflowPartition, @@ -59,7 +59,7 @@ # make sure new HLSCustomOp subclasses are imported here so that they get # registered and plug in correctly into the infrastructure -custom_op["MatrixVectorActivation"] = MatrixVectorActivation +custom_op["MVAU"] = MVAU custom_op["StreamingFIFO"] = StreamingFIFO custom_op["Thresholding"] = Thresholding custom_op["VectorVectorActivation"] = VectorVectorActivation diff --git a/src/finn/custom_op/fpgadataflow/hls/__init__.py b/src/finn/custom_op/fpgadataflow/hls/__init__.py index 1e2c83ba39..6e465fd0f2 100644 --- a/src/finn/custom_op/fpgadataflow/hls/__init__.py +++ b/src/finn/custom_op/fpgadataflow/hls/__init__.py @@ -41,9 +41,7 @@ from finn.custom_op.fpgadataflow.hls.iodma_hls import IODMA_hls from finn.custom_op.fpgadataflow.hls.labelselect_hls import LabelSelect_hls from finn.custom_op.fpgadataflow.hls.lookup_hls import Lookup_hls -from finn.custom_op.fpgadataflow.hls.matrixvectoractivation_hls import ( - MatrixVectorActivation_hls, -) +from finn.custom_op.fpgadataflow.hls.matrixvectoractivation_hls import MVAU_hls from finn.custom_op.fpgadataflow.hls.pool_hls import Pool_hls from finn.custom_op.fpgadataflow.hls.streamingdatawidthconverter_hls import ( StreamingDataWidthConverter_hls, @@ -81,5 +79,5 @@ custom_op["Thresholding_hls"] = Thresholding_hls custom_op["TLastMarker_hls"] = TLastMarker_hls custom_op["UpsampleNearestNeighbour_hls"] = UpsampleNearestNeighbour_hls -custom_op["MatrixVectorActivation_hls"] = MatrixVectorActivation_hls +custom_op["MVAU_hls"] = MVAU_hls custom_op["VectorVectorActivation_hls"] = VectorVectorActivation_hls diff --git a/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py b/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py index f40e6d78e8..c6ca66e15d 100644 --- a/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py @@ -33,7 +33,7 @@ from qonnx.core.datatype import DataType from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend -from finn.custom_op.fpgadataflow.matrixvectoractivation import MatrixVectorActivation +from finn.custom_op.fpgadataflow.matrixvectoractivation import MVAU from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy # ONNX i/o tensor shape assumptions for MatrixVectorActivation: @@ -44,7 +44,7 @@ # the ... here can be any shape (representing groups of vectors) -class MatrixVectorActivation_hls(MatrixVectorActivation, HLSBackend): +class MVAU_hls(MVAU, HLSBackend): """Corresponds to finn-hlslib MatrixVectorActivation_Batch function.""" def __init__(self, onnx_node, **kwargs): @@ -52,7 +52,7 @@ def __init__(self, onnx_node, **kwargs): def get_nodeattr_types(self): my_attrs = {} - my_attrs.update(MatrixVectorActivation.get_nodeattr_types(self)) + my_attrs.update(MVAU.get_nodeattr_types(self)) my_attrs.update(HLSBackend.get_nodeattr_types(self)) return my_attrs diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index 1b6be752dc..ac173e4af6 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -51,7 +51,7 @@ # the ... here can be any shape (representing groups of vectors) -class MatrixVectorActivation(HWCustomOp): +class MVAU(HWCustomOp): """Abstraction layer for HW implementation of MatrixVectorActivation layers.""" def __init__(self, onnx_node, **kwargs): @@ -122,9 +122,6 @@ def get_nodeattr_types(self): my_attrs.update(super().get_nodeattr_types()) return my_attrs - def base_op_type(self): - return "MatrixVectorActivation" - def execute_node(self, context, graph): node = self.onnx_node in_act = context[node.input[0]] diff --git a/src/finn/qnn-data/build_dataflow/folding_config.json b/src/finn/qnn-data/build_dataflow/folding_config.json index 95167f1a30..46f1d6236d 100644 --- a/src/finn/qnn-data/build_dataflow/folding_config.json +++ b/src/finn/qnn-data/build_dataflow/folding_config.json @@ -1,30 +1,30 @@ { "Defaults": {}, - "Thresholding_Batch_0": { + "Thresholding_hls_0": { "PE": 49, "ram_style": "distributed" }, - "MatrixVectorActivation_0": { + "MVAU_hls_0": { "PE": 16, "SIMD": 49, "ram_style": "block" }, - "MatrixVectorActivation_1": { + "MVAU_hls_1": { "PE": 8, "SIMD": 8, "ram_style": "auto" }, - "MatrixVectorActivation_2": { + "MVAU_hls_2": { "PE": 8, "SIMD": 8, "ram_style": "auto" }, - "MatrixVectorActivation_3": { + "MVA_hls_3": { "PE": 10, "SIMD": 8, "ram_style": "distributed" }, - "LabelSelect_Batch_0": { + "LabelSelect_hls_0": { "PE": 1 } } diff --git a/src/finn/qnn-data/build_dataflow/specialize_layers_config.json b/src/finn/qnn-data/build_dataflow/specialize_layers_config.json index 4fc37896db..c2a8bd4553 100644 --- a/src/finn/qnn-data/build_dataflow/specialize_layers_config.json +++ b/src/finn/qnn-data/build_dataflow/specialize_layers_config.json @@ -3,25 +3,25 @@ "Thresholding_0": { "preferred_impl_style": "hls" }, - "MatrixVectorActivation_0": { + "MVAU_0": { "preferred_impl_style": "hls" }, "Thresholding_1": { "preferred_impl_style": "" }, - "MatrixVectorActivation_1": { + "MVAU_1": { "preferred_impl_style": "" }, "Thresholding_2": { "preferred_impl_style": "" }, - "MatrixVectorActivation_2": { + "MVAU_2": { "preferred_impl_style": "" }, "Thresholding_3": { "preferred_impl_style": "rtl" }, - "MatrixVectorActivation_3": { + "MVAU_3": { "preferred_impl_style": "" }, "LabelSelect_0": { diff --git a/src/finn/qnn-data/test_ext_weights/tfc-w1a1-extw.json b/src/finn/qnn-data/test_ext_weights/tfc-w1a1-extw.json index 442ea72d9a..498d329ba3 100644 --- a/src/finn/qnn-data/test_ext_weights/tfc-w1a1-extw.json +++ b/src/finn/qnn-data/test_ext_weights/tfc-w1a1-extw.json @@ -1,30 +1,30 @@ { "Defaults": {}, - "Thresholding_Batch_0": { + "Thresholding_hls_0": { "PE": 49, "ram_style": "distributed" }, - "MatrixVectorActivation_0": { + "MVAU_hls_0": { "PE": 16, "SIMD": 49, "ram_style": "block" }, - "MatrixVectorActivation_1": { + "MVAU_hls_1": { "PE": 8, "SIMD": 8, "mem_mode": "external" }, - "MatrixVectorActivation_2": { + "MVAU_hls_2": { "PE": 8, "SIMD": 8, "mem_mode": "external" }, - "MatrixVectorActivation_3": { + "MVAU_hls_3": { "PE": 10, "SIMD": 8, "ram_style": "distributed" }, - "LabelSelect_Batch_0": { + "LabelSelect_hls_0": { "PE": 1 } } diff --git a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py index ade76afdde..014a5c82bd 100644 --- a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py +++ b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py @@ -1356,7 +1356,7 @@ def apply(self, model): model.set_tensor_shape(mt_output, mt_out_shape) # create and insert new MatrixVectorActivation node new_node = helper.make_node( - "MatrixVectorActivation", + "MVAU", [mm_input, mm_weight, mt_thres], [mt_output], domain="finn.custom_op.fpgadataflow", @@ -1387,7 +1387,7 @@ def apply(self, model): model.set_tensor_shape(mm_output, mm_out_shape) # create and insert new MatrixVectorActivation node new_node = helper.make_node( - "MatrixVectorActivation", + "MVAU", [mm_input, mm_weight], [mm_output], domain="finn.custom_op.fpgadataflow", @@ -1493,7 +1493,7 @@ def apply(self, model): actval = 0 # create and insert new MatrixVectorActivation node new_node = helper.make_node( - "MatrixVectorActivation", + "MVAU", [mm_input, mm_weight, mt_thres], [mt_output], domain="finn.custom_op.fpgadataflow", @@ -1510,7 +1510,7 @@ def apply(self, model): noActivation=0, numInputVectors=list(mm_in_shape[:-1]), mem_mode=self.mem_mode, - name="MatrixVectorActivation_" + n.name, + name="MVAU_" + n.name, ) graph.node.insert(node_ind, new_node) # remove old nodes @@ -1524,7 +1524,7 @@ def apply(self, model): model.set_tensor_shape(mm_output, mm_out_shape) # create and insert new MatrixVectorActivation node new_node = helper.make_node( - "MatrixVectorActivation", + "MVAU", [mm_input, mm_weight], [mm_output], domain="finn.custom_op.fpgadataflow", @@ -1541,7 +1541,7 @@ def apply(self, model): noActivation=1, numInputVectors=list(mm_in_shape[:-1]), mem_mode=self.mem_mode, - name="MatrixVectorActivation_" + n.name, + name="MVAU_" + n.name, ) graph.node.insert(node_ind, new_node) # remove old node diff --git a/src/finn/transformation/fpgadataflow/create_stitched_ip.py b/src/finn/transformation/fpgadataflow/create_stitched_ip.py index a8ecdcf484..4212e2b58a 100644 --- a/src/finn/transformation/fpgadataflow/create_stitched_ip.py +++ b/src/finn/transformation/fpgadataflow/create_stitched_ip.py @@ -55,7 +55,7 @@ def is_external_input(model, node, i): if model.get_initializer(node.input[i]) is None: return True else: - if op_type.startswith("MatrixVectorActivation"): + if op_type.startswith("MVAU"): if node_inst.get_nodeattr("mem_mode") == "external": return True return False diff --git a/src/finn/transformation/fpgadataflow/floorplan.py b/src/finn/transformation/fpgadataflow/floorplan.py index 5231fc288b..b24145afcb 100644 --- a/src/finn/transformation/fpgadataflow/floorplan.py +++ b/src/finn/transformation/fpgadataflow/floorplan.py @@ -150,7 +150,7 @@ def apply(self, model): continue elif not ( - node.op_type.startswith("MatrixVectorActivation") + node.op_type.startswith("MVAU") and node_inst.get_nodeattr("mem_mode") is not None and node_inst.get_nodeattr("mem_mode") == "external" ): diff --git a/src/finn/transformation/fpgadataflow/insert_dwc.py b/src/finn/transformation/fpgadataflow/insert_dwc.py index e3a52f68f0..100beefcc2 100644 --- a/src/finn/transformation/fpgadataflow/insert_dwc.py +++ b/src/finn/transformation/fpgadataflow/insert_dwc.py @@ -88,7 +88,7 @@ def apply(self, model): # - if FC and external mem, it could be connected to input 1 # - if concat, could be connected to any input if ( - consumer.op_type.startswith("MatrixVectorActivation") + consumer.op_type.startswith("MVAU") and n1.get_nodeattr("mem_mode") == "external" ) or (consumer.op_type.startswith("StreamingConcat")): # get input idx diff --git a/src/finn/transformation/fpgadataflow/insert_iodma.py b/src/finn/transformation/fpgadataflow/insert_iodma.py index f3334d94f5..96f23ca320 100644 --- a/src/finn/transformation/fpgadataflow/insert_iodma.py +++ b/src/finn/transformation/fpgadataflow/insert_iodma.py @@ -199,8 +199,7 @@ def apply(self, model): # attached IODMA fc_extw_nodes = list( filter( - lambda x: x.op_type - in ["MatrixVectorActivation_hls", "VectorVectorActivation_hls"] + lambda x: x.op_type in ["MVAU_hls", "VectorVectorActivation_hls"] and getCustomOp(x).get_nodeattr("mem_mode") == "external" and model.find_producer(x.input[1]) is None, all_nodes, diff --git a/src/finn/transformation/fpgadataflow/insert_tlastmarker.py b/src/finn/transformation/fpgadataflow/insert_tlastmarker.py index 431ca8e0b5..2131100dcf 100644 --- a/src/finn/transformation/fpgadataflow/insert_tlastmarker.py +++ b/src/finn/transformation/fpgadataflow/insert_tlastmarker.py @@ -103,7 +103,7 @@ def apply(self, model): # the input is in the list of graph inputs because it has an # initializer (TODO: fix this with a clean-up transform) if ( - first_node.op_type.startswith("MatrixVectorActivation") + first_node.op_type.startswith("MVAU") and get_by_name(first_node.attribute, "mem_mode").s.decode("UTF-8") != "external" ): @@ -117,7 +117,7 @@ def apply(self, model): num_iters = np.prod(custom_op.get_folded_input_shape()[1:-1]) inp_idx = list(first_node.input).index(graph_in_name) if inp_idx > 0: - if first_node.op_type.startswith("MatrixVectorActivation") and inp_idx == 1: + if first_node.op_type.startswith("MVAU") and inp_idx == 1: stream_width = int(custom_op.get_weightstream_width()) elif first_node.op_type.startswith("AddStreams") and inp_idx == 1: stream_width = int(custom_op.get_instream_width()) diff --git a/src/finn/transformation/fpgadataflow/make_pynq_driver.py b/src/finn/transformation/fpgadataflow/make_pynq_driver.py index 9a5317e588..ea9bd2aa26 100644 --- a/src/finn/transformation/fpgadataflow/make_pynq_driver.py +++ b/src/finn/transformation/fpgadataflow/make_pynq_driver.py @@ -282,9 +282,7 @@ def apply(self, model): dataflow_model = ModelWrapper(dataflow_model_filename) rt_layer_ind = 0 for node in dataflow_model.graph.node: - if node.op_type.startswith("MatrixVectorActivation") or node.op_type.startswith( - "Thresholding" - ): + if node.op_type.startswith("MVAU") or node.op_type.startswith("Thresholding"): node_inst = getCustomOp(node) is_rt_weights = node_inst.get_nodeattr("runtime_writeable_weights") if is_rt_weights == 1: diff --git a/src/finn/transformation/fpgadataflow/make_zynq_proj.py b/src/finn/transformation/fpgadataflow/make_zynq_proj.py index 65095f1de7..7e3754e41e 100644 --- a/src/finn/transformation/fpgadataflow/make_zynq_proj.py +++ b/src/finn/transformation/fpgadataflow/make_zynq_proj.py @@ -64,9 +64,7 @@ def collect_ip_dirs(model, ipstitch_path): ), """The directory that should contain the generated ip blocks doesn't exist.""" ip_dirs += [ip_dir_value] - if node.op_type.startswith("MatrixVectorActivation") or node.op_type.startswith( - "Thresholding" - ): + if node.op_type.startswith("MVAU") or node.op_type.startswith("Thresholding"): if node_inst.get_nodeattr("mem_mode") == "decoupled": need_memstreamer = True ip_dirs += [ipstitch_path + "/ip"] diff --git a/src/finn/transformation/fpgadataflow/set_fifo_depths.py b/src/finn/transformation/fpgadataflow/set_fifo_depths.py index 5d3b42b0c0..1e25670a71 100644 --- a/src/finn/transformation/fpgadataflow/set_fifo_depths.py +++ b/src/finn/transformation/fpgadataflow/set_fifo_depths.py @@ -176,7 +176,7 @@ def apply(self, model): continue if fifo_cons is None: continue - if not fifo_cons.op_type.startswith("MatrixVectorActivation"): + if not fifo_cons.op_type.startswith("MVAU"): continue op_inst = getCustomOp(node) depth = op_inst.get_nodeattr("depth") @@ -259,7 +259,7 @@ def __init__( def apply(self, model): # these optypes may potentially use external weights # we'll temporarily change them to use decoupled mode for FIFO sizing - extw_optypes = ["MatrixVectorActivation_hls", "VectorVectorActivation_hls"] + extw_optypes = ["MVAU_hls", "VectorVectorActivation_hls"] # change external to decoupled and warn user # this way we are sure we have exactly one input/output modified_fc_nodes = [] @@ -568,7 +568,7 @@ def apply(self, model): graph_modified = False for node in graph.node: node_ind += 1 - if node.op_type.startswith("StreamingFIFO"): + if node.op_type == ("StreamingFIFO_rtl"): n_inst = getCustomOp(node) depth = n_inst.get_nodeattr("depth") cfgs = get_fifo_split_configs(depth, self.max_qsrl_depth, self.max_vivado_depth) @@ -593,10 +593,10 @@ def apply(self, model): graph.value_info.append(out_tensor) model.set_tensor_datatype(out_tensor.name, DataType[dtype]) fifo_node = helper.make_node( - "StreamingFIFO", + "StreamingFIFO_rtl", [inp], [outp], - domain="finn.custom_op.fpgadataflow", + domain="finn.custom_op.fpgadataflow.rtl", backend="fpgadataflow", depth=fifo_depth, folded_shape=fld_shape, diff --git a/src/finn/transformation/fpgadataflow/set_folding.py b/src/finn/transformation/fpgadataflow/set_folding.py index 83f4138668..28358fdacc 100644 --- a/src/finn/transformation/fpgadataflow/set_folding.py +++ b/src/finn/transformation/fpgadataflow/set_folding.py @@ -124,7 +124,7 @@ def apply(self, model): continue op_type = node.op_type node_inst = getCustomOp(node) - if op_type == "MatrixVectorActivation_hls": + if op_type == "MVAU_hls": max_simd = node_inst.get_nodeattr("MW") max_pe = node_inst.get_nodeattr("MH") node_inst.set_nodeattr("PE", 1) diff --git a/src/finn/transformation/fpgadataflow/specialize_layers.py b/src/finn/transformation/fpgadataflow/specialize_layers.py index 691d7aed34..6c94f45d16 100644 --- a/src/finn/transformation/fpgadataflow/specialize_layers.py +++ b/src/finn/transformation/fpgadataflow/specialize_layers.py @@ -35,7 +35,7 @@ from finn.custom_op.fpgadataflow.rtl import custom_op as rtl_variants restricted_layers = [] -restricted_layers.append("MatrixVectorActivation") +restricted_layers.append("MVAU") restricted_layers.append("VectorVectorActivation") restricted_layers.append("Thresholding") diff --git a/src/finn/transformation/move_reshape.py b/src/finn/transformation/move_reshape.py index 6b5fa5516f..a13ecee80f 100644 --- a/src/finn/transformation/move_reshape.py +++ b/src/finn/transformation/move_reshape.py @@ -50,7 +50,7 @@ def apply(self, model): producer = model.find_producer(transp_node.input[0]) if _is_fpgadataflow_node(producer) is True: consumer = model.find_consumer(n.output[0]) - if consumer.op_type.startswith("MatrixVectorActivation"): + if consumer.op_type.startswith("MVAU"): fc_inst = getCustomOp(consumer) mw = fc_inst.get_nodeattr("MW") mh = fc_inst.get_nodeattr("MH") diff --git a/src/finn/util/create.py b/src/finn/util/create.py index af92d1cb8e..09ec4f334c 100644 --- a/src/finn/util/create.py +++ b/src/finn/util/create.py @@ -143,7 +143,7 @@ def hls_mlp_maker(layer_spec): actval = 0 no_act = 1 FCLayer_node = helper.make_node( - "MatrixVectorActivation", + "MVAU", node_inp_list, [current_out_name], domain="finn.custom_op.fpgadataflow", diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index b718e62fdf..bdede35244 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -122,7 +122,7 @@ def get_checkpoint_name(topology, wbits, abits, step): def fold_tfc(model): - fc_layers = model.get_nodes_by_op_type("MatrixVectorActivation_hls") + fc_layers = model.get_nodes_by_op_type("MVAU_hls") # (PE, SIMD, ramstyle) for each layer config = [(16, 49, "block"), (8, 8, "auto"), (8, 8, "auto"), (10, 8, "distributed")] for fcl, (pe, simd, ramstyle) in zip(fc_layers, config): @@ -140,7 +140,7 @@ def fold_tfc(model): def fold_lfc(model): - fc_layers = model.get_nodes_by_op_type("MatrixVectorActivation_hls") + fc_layers = model.get_nodes_by_op_type("MVAU_hls") # (PE, SIMD, ramstyle) for each layer config = [ (32, 49, "block"), @@ -162,7 +162,7 @@ def fold_lfc(model): def fold_cnv_large(model): - fc_layers = model.get_nodes_by_op_type("MatrixVectorActivation_hls") + fc_layers = model.get_nodes_by_op_type("MVAU_hls") # each tuple is (PE, SIMD) for a layer folding = [ (16, 3), @@ -189,7 +189,7 @@ def fold_cnv_large(model): def fold_cnv_small(model): - fc_layers = model.get_nodes_by_op_type("MatrixVectorActivation_hls") + fc_layers = model.get_nodes_by_op_type("MVAU_hls") # each tuple is (PE, SIMD) for a layer folding = [ (8, 3, "distributed"), @@ -560,26 +560,26 @@ def test_convert_to_hw_layers(self, topology, wbits, abits, board): "tfc": [ ("Reshape", 1), ("Thresholding", 1), - ("MatrixVectorActivation", 4), + ("MVAU", 4), ("LabelSelect", 1), ], "tfc-1-1": [ ("Reshape", 1), ("Thresholding", 4), - ("MatrixVectorActivation", 4), + ("MVAU", 4), ("LabelSelect", 1), ], "lfc": [ ("Reshape", 1), ("Thresholding", 1), - ("MatrixVectorActivation", 4), + ("MVAU", 4), ("LabelSelect", 1), ], "cnv": [ ("Transpose", 1), ("Thresholding", 1), ("ConvolutionInputGenerator", 6), - ("MatrixVectorActivation", 9), + ("MVAU", 9), ("StreamingMaxPool", 2), ("LabelSelect", 1), ], @@ -607,26 +607,26 @@ def test_specialize_layers(self, topology, wbits, abits, board): "tfc": [ ("Reshape", 1), ("Thresholding_hls", 1), - ("MatrixVectorActivation_hls", 4), + ("MVAU_hls", 4), ("LabelSelect_hls", 1), ], "tfc-1-1": [ ("Reshape", 1), ("Thresholding_hls", 4), - ("MatrixVectorActivation_hls", 4), + ("MVAU_hls", 4), ("LabelSelect_hls", 1), ], "lfc": [ ("Reshape", 1), ("Thresholding_hls", 1), - ("MatrixVectorActivation_hls", 4), + ("MVAU_hls", 4), ("LabelSelect_hls", 1), ], "cnv": [ ("Transpose", 1), ("Thresholding_hls", 1), ("ConvolutionInputGenerator_hls", 6), - ("MatrixVectorActivation_hls", 9), + ("MVAU_hls", 9), ("StreamingMaxPool_hls", 2), ("LabelSelect_hls", 1), ], diff --git a/tests/end2end/test_end2end_cybsec_mlp.py b/tests/end2end/test_end2end_cybsec_mlp.py index b58b9f472c..9ee07d57a3 100644 --- a/tests/end2end/test_end2end_cybsec_mlp.py +++ b/tests/end2end/test_end2end_cybsec_mlp.py @@ -182,8 +182,8 @@ def test_end2end_cybsec_mlp_build(): # examine the report contents with open(est_cycles_report, "r") as f: est_cycles_dict = json.load(f) - assert est_cycles_dict["MatrixVectorActivation_hls_0"] == 80 - assert est_cycles_dict["MatrixVectorActivation_hls_1"] == 64 + assert est_cycles_dict["MVAU_hls_0"] == 80 + assert est_cycles_dict["MVAU_hls_1"] == 64 with open(est_res_report, "r") as f: est_res_dict = json.load(f) assert est_res_dict["total"]["LUT"] == 7899.0 diff --git a/tests/end2end/test_end2end_mobilenet_v1.py b/tests/end2end/test_end2end_mobilenet_v1.py index ba52548290..1fceda8141 100644 --- a/tests/end2end/test_end2end_mobilenet_v1.py +++ b/tests/end2end/test_end2end_mobilenet_v1.py @@ -256,7 +256,7 @@ def test_end2end_mobilenet_folding(): assert extra_fold in [1, 2, 4] # set up folding for the depthwise conv layers impl'd by VVAUs # each value is PE for a layer - fc_layers = model.get_nodes_by_op_type("MatrixVectorActivation_hls") + fc_layers = model.get_nodes_by_op_type("MVAU_hls") # each tuple is (PE, SIMD, ram_style) for a layer folding = [ (32, 3, "block"), diff --git a/tests/fpgadataflow/test_code_gen_trafo.py b/tests/fpgadataflow/test_code_gen_trafo.py index 709333949e..deb9dd43b4 100644 --- a/tests/fpgadataflow/test_code_gen_trafo.py +++ b/tests/fpgadataflow/test_code_gen_trafo.py @@ -51,7 +51,7 @@ def test_code_gen_trafo(): outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, [1, mh]) node_inp_list = ["inp", "weights", "thresh"] FCLayer_node = helper.make_node( - "MatrixVectorActivation_hls", + "MVAU_hls", node_inp_list, ["outp"], domain="finn.custom_op.fpgadataflow.hls", diff --git a/tests/fpgadataflow/test_compilation_trafo.py b/tests/fpgadataflow/test_compilation_trafo.py index 1b48df3d4a..7022311d4c 100644 --- a/tests/fpgadataflow/test_compilation_trafo.py +++ b/tests/fpgadataflow/test_compilation_trafo.py @@ -52,7 +52,7 @@ def test_compilation_trafo(): outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, [1, mh]) node_inp_list = ["inp", "weights", "thresh"] FCLayer_node = helper.make_node( - "MatrixVectorActivation_hls", + "MVAU_hls", node_inp_list, ["outp"], domain="finn.custom_op.fpgadataflow.hls", diff --git a/tests/fpgadataflow/test_convert_to_hw_1d_conv_layer.py b/tests/fpgadataflow/test_convert_to_hw_1d_conv_layer.py index 55f46e321b..5e06cf9904 100644 --- a/tests/fpgadataflow/test_convert_to_hw_1d_conv_layer.py +++ b/tests/fpgadataflow/test_convert_to_hw_1d_conv_layer.py @@ -150,7 +150,7 @@ def test_convert_to_hw_1d_conv_layer(conv_config, depthwise, use_rtl_swg, exec_m else: new_model = new_model.transform(to_hw.InferQuantizedMatrixVectorActivation()) new_model = new_model.transform(SpecializeLayers()) - fc_node = new_model.get_nodes_by_op_type("MatrixVectorActivation_hls")[0] + fc_node = new_model.get_nodes_by_op_type("MVAU_hls")[0] fc_inst = getCustomOp(fc_node) mw = fc_inst.get_nodeattr("MW") mh = fc_inst.get_nodeattr("MH") diff --git a/tests/fpgadataflow/test_convert_to_hw_conv_layer.py b/tests/fpgadataflow/test_convert_to_hw_conv_layer.py index 8cade1bfa1..ddcf386377 100644 --- a/tests/fpgadataflow/test_convert_to_hw_conv_layer.py +++ b/tests/fpgadataflow/test_convert_to_hw_conv_layer.py @@ -135,7 +135,7 @@ def test_convert_to_hw_conv_layer(conv_config, depthwise, use_rtl_swg, exec_mode else: new_model = new_model.transform(to_hw.InferQuantizedMatrixVectorActivation()) new_model = new_model.transform(SpecializeLayers()) - fc_node = new_model.get_nodes_by_op_type("MatrixVectorActivation_hls")[0] + fc_node = new_model.get_nodes_by_op_type("MVAU_hls")[0] fc_inst = getCustomOp(fc_node) mw = fc_inst.get_nodeattr("MW") mh = fc_inst.get_nodeattr("MH") diff --git a/tests/fpgadataflow/test_convert_to_hw_layers_cnv.py b/tests/fpgadataflow/test_convert_to_hw_layers_cnv.py index 117a9a5850..64ccebf97a 100644 --- a/tests/fpgadataflow/test_convert_to_hw_layers_cnv.py +++ b/tests/fpgadataflow/test_convert_to_hw_layers_cnv.py @@ -111,7 +111,7 @@ def test_convert_to_hw_layers_cnv_w1a1(fused_activation): model = model.transform(to_hw.InferStreamingMaxPool()) model = model.transform(SpecializeLayers()) for node in model.graph.node: - if node.op_type == "MatrixVectorActivation_hls": + if node.op_type == "MVAU_hls": inst = getCustomOp(node) inst.set_nodeattr("mem_mode", "decoupled") mw = inst.get_nodeattr("MW") @@ -138,7 +138,7 @@ def test_convert_to_hw_layers_cnv_w1a1(fused_activation): assert len(non_finn_nodes) == 5 exp_non_finn_nodes = ["Transpose", "Transpose", "Reshape", "Mul", "Add"] assert [x.op_type for x in non_finn_nodes] == exp_non_finn_nodes - fc_nodes = model.get_nodes_by_op_type("MatrixVectorActivation_hls") + fc_nodes = model.get_nodes_by_op_type("MVAU_hls") assert len(fc_nodes) == 9 swg_nodes = model.get_nodes_by_op_type("ConvolutionInputGenerator_hls") assert len(swg_nodes) == 6 diff --git a/tests/fpgadataflow/test_convert_to_hw_layers_fc.py b/tests/fpgadataflow/test_convert_to_hw_layers_fc.py index 13f6a4393e..d00521f09f 100644 --- a/tests/fpgadataflow/test_convert_to_hw_layers_fc.py +++ b/tests/fpgadataflow/test_convert_to_hw_layers_fc.py @@ -84,22 +84,22 @@ def test_convert_to_hw_layers_tfc_w1a1(): model = model.transform(to_hw.InferBinaryMatrixVectorActivation()) model = model.transform(SpecializeLayers()) fc0 = model.graph.node[2] - assert fc0.op_type == "MatrixVectorActivation_hls" + assert fc0.op_type == "MVAU_hls" assert model.get_tensor_shape(fc0.input[0]) == [1, 784] assert model.get_tensor_shape(fc0.input[1]) == [784, 64] assert model.get_tensor_shape(fc0.input[2]) == [64, 1] fc1 = model.graph.node[3] - assert fc1.op_type == "MatrixVectorActivation_hls" + assert fc1.op_type == "MVAU_hls" assert model.get_tensor_shape(fc1.input[0]) == [1, 64] assert model.get_tensor_shape(fc1.input[1]) == [64, 64] assert model.get_tensor_shape(fc1.input[2]) == [64, 1] fc2 = model.graph.node[4] - assert fc2.op_type == "MatrixVectorActivation_hls" + assert fc2.op_type == "MVAU_hls" assert model.get_tensor_shape(fc2.input[0]) == [1, 64] assert model.get_tensor_shape(fc2.input[1]) == [64, 64] assert model.get_tensor_shape(fc2.input[2]) == [64, 1] fc3 = model.graph.node[5] - assert fc3.op_type == "MatrixVectorActivation_hls" + assert fc3.op_type == "MVAU_hls" assert model.get_tensor_shape(fc3.input[0]) == [1, 64] assert model.get_tensor_shape(fc3.input[1]) == [64, 10] @@ -157,22 +157,22 @@ def test_convert_to_hw_layers_tfc_w1a2(): model = model.transform(SpecializeLayers()) fc0 = model.graph.node[2] - assert fc0.op_type == "MatrixVectorActivation_hls" + assert fc0.op_type == "MVAU_hls" assert model.get_tensor_shape(fc0.input[0]) == [1, 784] assert model.get_tensor_shape(fc0.input[1]) == [784, 64] assert model.get_tensor_shape(fc0.input[2]) == [64, 2] fc1 = model.graph.node[3] - assert fc1.op_type == "MatrixVectorActivation_hls" + assert fc1.op_type == "MVAU_hls" assert model.get_tensor_shape(fc1.input[0]) == [1, 64] assert model.get_tensor_shape(fc1.input[1]) == [64, 64] assert model.get_tensor_shape(fc1.input[2]) == [64, 2] fc2 = model.graph.node[4] - assert fc2.op_type == "MatrixVectorActivation_hls" + assert fc2.op_type == "MVAU_hls" assert model.get_tensor_shape(fc2.input[0]) == [1, 64] assert model.get_tensor_shape(fc2.input[1]) == [64, 64] assert model.get_tensor_shape(fc2.input[2]) == [64, 2] fc3 = model.graph.node[5] - assert fc3.op_type == "MatrixVectorActivation_hls" + assert fc3.op_type == "MVAU_hls" assert model.get_tensor_shape(fc3.input[0]) == [1, 64] assert model.get_tensor_shape(fc3.input[1]) == [64, 10] fc0w = getCustomOp(fc0) diff --git a/tests/fpgadataflow/test_fpgadataflow_checksum.py b/tests/fpgadataflow/test_fpgadataflow_checksum.py index 71d4d60c06..c51030764c 100644 --- a/tests/fpgadataflow/test_fpgadataflow_checksum.py +++ b/tests/fpgadataflow/test_fpgadataflow_checksum.py @@ -72,7 +72,7 @@ def create_two_fc_model(): outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, [1, m]) fc0 = helper.make_node( - "MatrixVectorActivation", + "MVAU", ["inp", "w0"], ["mid"], domain="finn.custom_op.fpgadataflow", @@ -91,7 +91,7 @@ def create_two_fc_model(): ) fc1 = helper.make_node( - "MatrixVectorActivation", + "MVAU", ["mid", "w1"], ["outp"], domain="finn.custom_op.fpgadataflow", diff --git a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py index a05dd53e28..766a294977 100644 --- a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py +++ b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py @@ -269,7 +269,7 @@ def test_fpgadataflow_conv_dynamic(cfg): getCustomOp(swg_node).set_nodeattr("dynamic_mode", 1) getCustomOp(swg_node).set_nodeattr("inFIFODepths", [16]) getCustomOp(swg_node).set_nodeattr("outFIFODepths", [16]) - comp_nodes = model.get_nodes_by_op_type("MatrixVectorActivation_hls") + comp_nodes = model.get_nodes_by_op_type("MVAU_hls") comp_nodes += model.get_nodes_by_op_type("VectorVectorActivation_hls") for comp_node in comp_nodes: if depthwise: diff --git a/tests/fpgadataflow/test_fpgadataflow_deconv.py b/tests/fpgadataflow/test_fpgadataflow_deconv.py index 9c333e6808..ce8e1ce003 100644 --- a/tests/fpgadataflow/test_fpgadataflow_deconv.py +++ b/tests/fpgadataflow/test_fpgadataflow_deconv.py @@ -41,7 +41,10 @@ import finn.core.onnx_exec as oxe from finn.analysis.fpgadataflow.exp_cycles_per_layer import exp_cycles_per_layer from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim -from finn.transformation.fpgadataflow.convert_to_hw_layers import InferConvInpGen +from finn.transformation.fpgadataflow.convert_to_hw_layers import ( + InferConvInpGen, + InferQuantizedMatrixVectorActivation, +) from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP from finn.transformation.fpgadataflow.infer_pixel_padding_deconv import ( InferPixelPaddingDeconv, @@ -164,8 +167,7 @@ def test_fpgadataflow_deconv(idim, stride, ifm_ch, ofm_ch, simd, pe, k, padding, model = ref_model.transform(InferPixelPaddingDeconv()) model = model.transform(InferConvInpGen(use_rtl_variant=convinpgen_rtl)) - # TODO: uncomment when MV(A)U is in new class hierarchy - # model = model.transform(InferQuantizedMatrixVectorActivation()) + model = model.transform(InferQuantizedMatrixVectorActivation()) model = model.transform(InferShapes()) model = model.transform(GiveUniqueNodeNames()) @@ -178,7 +180,7 @@ def test_fpgadataflow_deconv(idim, stride, ifm_ch, ofm_ch, simd, pe, k, padding, elif n.op_type == "FMPadding": pad_node = getCustomOp(n) pad_node.set_nodeattr("preferred_impl_style", "hls") - elif n.op_type == "MatrixVectorActivation": + elif n.op_type == "MVAU": mvau_node = getCustomOp(n) mvau_node.set_nodeattr("PE", pe) mvau_node.set_nodeattr("SIMD", simd) diff --git a/tests/fpgadataflow/test_fpgadataflow_ipstitch.py b/tests/fpgadataflow/test_fpgadataflow_ipstitch.py index 846f2c1fe0..ab62b2d476 100644 --- a/tests/fpgadataflow/test_fpgadataflow_ipstitch.py +++ b/tests/fpgadataflow/test_fpgadataflow_ipstitch.py @@ -79,7 +79,7 @@ def create_one_fc_model(mem_mode="const"): outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, [1, m]) fc0 = helper.make_node( - "MatrixVectorActivation_hls", + "MVAU_hls", ["inp", "w0"], ["outp"], domain="finn.custom_op.fpgadataflow.hls", @@ -131,7 +131,7 @@ def create_two_fc_model(mem_mode="decoupled"): outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, [1, m]) fc0 = helper.make_node( - "MatrixVectorActivation_hls", + "MVAU_hls", ["inp", "w0"], ["mid"], domain="finn.custom_op.fpgadataflow.hls", @@ -150,7 +150,7 @@ def create_two_fc_model(mem_mode="decoupled"): ) fc1 = helper.make_node( - "MatrixVectorActivation_hls", + "MVAU_hls", ["mid", "w1"], ["outp"], domain="finn.custom_op.fpgadataflow.hls", @@ -209,7 +209,7 @@ def test_fpgadataflow_ipstitch_gen_model(mem_mode): model = model.transform(GiveUniqueNodeNames()) model = model.transform(PrepareIP(test_fpga_part, 5)) model = model.transform(HLSSynthIP()) - assert model.graph.node[0].op_type == "MatrixVectorActivation_hls" + assert model.graph.node[0].op_type == "MVAU_hls" assert model.graph.node[-1].op_type == "TLastMarker_hls" model.save(ip_stitch_model_dir + "/test_fpgadataflow_ipstitch_gen_model_%s.onnx" % mem_mode) diff --git a/tests/fpgadataflow/test_fpgadataflow_mvau.py b/tests/fpgadataflow/test_fpgadataflow_mvau.py index 1853392724..f202b094e8 100644 --- a/tests/fpgadataflow/test_fpgadataflow_mvau.py +++ b/tests/fpgadataflow/test_fpgadataflow_mvau.py @@ -91,7 +91,7 @@ def make_single_fclayer_modelwrapper(W, pe, simd, wdt, idt, odt, T=None, tdt=Non actval = 0 no_act = 1 FCLayer_node = helper.make_node( - "MatrixVectorActivation", + "MVAU", node_inp_list, ["outp"], domain="finn.custom_op.fpgadataflow", @@ -400,9 +400,9 @@ def test_fpgadataflow_fclayer_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): assert (y_produced.reshape(y_expected.shape) == y_expected).all(), "rtlsim failed" hls_synt_res_est = model.analysis(hls_synth_res_estimation) - assert "MatrixVectorActivation_hls_0" in hls_synt_res_est + assert "MVAU_hls_0" in hls_synt_res_est - node = model.get_nodes_by_op_type("MatrixVectorActivation_hls")[0] + node = model.get_nodes_by_op_type("MVAU_hls")[0] inst = getCustomOp(node) cycles_rtlsim = inst.get_nodeattr("cycles_rtlsim") exp_cycles_dict = model.analysis(exp_cycles_per_layer) @@ -505,11 +505,11 @@ def test_fpgadataflow_fclayer_large_depth_decoupled_mode_rtlsim( hls_synt_res_est = model.analysis(hls_synth_res_estimation) if backend == "hls": - assert "MatrixVectorActivation_hls_0" in hls_synt_res_est + assert "MVAU_hls_0" in hls_synt_res_est else: - assert "MatrixVectorActivation_rtl_0" in hls_synt_res_est + assert "MVAU_rtl_0" in hls_synt_res_est - node = model.get_nodes_by_op_type("MatrixVectorActivation")[0] + node = model.get_nodes_by_op_type("MVAU")[0] inst = getCustomOp(node) cycles_rtlsim = inst.get_nodeattr("cycles_rtlsim") exp_cycles_dict = model.analysis(exp_cycles_per_layer) diff --git a/tests/fpgadataflow/test_fpgadataflow_res_estimate.py b/tests/fpgadataflow/test_fpgadataflow_res_estimate.py index 2ff7dd8b32..1bc2d9d59e 100644 --- a/tests/fpgadataflow/test_fpgadataflow_res_estimate.py +++ b/tests/fpgadataflow/test_fpgadataflow_res_estimate.py @@ -38,6 +38,7 @@ res_estimation, res_estimation_complete, ) +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers def check_two_dict_for_equality(dict1, dict2): @@ -68,7 +69,7 @@ def test_res_estimate(): node_inp_list = ["inp", "weights", "thresh"] FCLayer_node = helper.make_node( - "MatrixVectorActivation", + "MVAU", node_inp_list, ["outp"], domain="finn.custom_op.fpgadataflow", @@ -95,10 +96,11 @@ def test_res_estimate(): model.set_tensor_datatype("outp", odt) model.set_tensor_datatype("weights", wdt) + model.transform(SpecializeLayers()) model = model.transform(GiveUniqueNodeNames()) prod_resource_estimation = model.analysis(res_estimation) expect_resource_estimation = { - "MatrixVectorActivation_0": { + "MVAU_hls_0": { "BRAM_18K": 0, "BRAM_efficiency": 1, "LUT": 317, @@ -115,7 +117,7 @@ def test_res_estimate(): prod_resource_estimation = model.analysis(res_estimation_complete) expect_resource_estimation = { - "MatrixVectorActivation_0": [ + "MVAU_hls_0": [ { "BRAM_18K": 0, "BRAM_efficiency": 1, diff --git a/tests/fpgadataflow/test_minimize_bit_width.py b/tests/fpgadataflow/test_minimize_bit_width.py index 0e704230e7..2b765610ab 100644 --- a/tests/fpgadataflow/test_minimize_bit_width.py +++ b/tests/fpgadataflow/test_minimize_bit_width.py @@ -36,7 +36,7 @@ from qonnx.util.basic import gen_finn_dt_tensor, roundup_to_integer_multiple from typing import Optional, Union -from finn.custom_op.fpgadataflow.matrixvectoractivation import MatrixVectorActivation +from finn.custom_op.fpgadataflow.matrixvectoractivation import MVAU from finn.custom_op.fpgadataflow.vectorvectoractivation import VectorVectorActivation from finn.transformation.fpgadataflow.minimize_accumulator_width import ( MinimizeAccumulatorWidth, @@ -68,7 +68,7 @@ def make_unit_test_model(wdt: DataType, idt: DataType, tdt: Optional[DataType] = noActivation=0 if tdt is not None else 1, ) layer2 = helper.make_node( - "MatrixVectorActivation", + "MVAU", ["hid", "params1", "thresh1"] if tdt is not None else ["hid", "params1"], ["outp"], domain="finn.custom_op.fpgadataflow", @@ -170,7 +170,7 @@ def test_minimize_weight_bit_width(wdt: DataType, rww: bool): # If runtime-writeable weights, specify as a node attribute for node in model.graph.node: inst = getCustomOp(node) - if isinstance(inst, (MatrixVectorActivation, VectorVectorActivation)): + if isinstance(inst, (MVAU, VectorVectorActivation)): inst.set_nodeattr("runtime_writeable_weights", int(rww)) # Apply the optimization @@ -179,14 +179,14 @@ def test_minimize_weight_bit_width(wdt: DataType, rww: bool): # Iterate through each node to make sure it functioned properly for node in model.graph.node: inst = getCustomOp(node) - if isinstance(inst, (MatrixVectorActivation, VectorVectorActivation)): + if isinstance(inst, (MVAU, VectorVectorActivation)): cur_wdt = DataType[inst.get_nodeattr("weightDataType")] exp_wdt = def_wdt if rww else wdt assert cur_wdt.bitwidth() == exp_wdt.bitwidth(), "Mismatched data types" def calculate_accumulator_bit_width( - inst: Union[MatrixVectorActivation, VectorVectorActivation], model: ModelWrapper + inst: Union[MVAU, VectorVectorActivation], model: ModelWrapper ) -> Union[DataType, IntType]: """Calculate the accumulator bit width using the closed-form expressions derived in `Quantized Neural Networks for Low-Precision Accumulation @@ -206,7 +206,7 @@ def phi(x: float) -> float: if inst.get_nodeattr("binaryXnorMode"): weights = 2 * weights - 1 # modify the weights based on if the node is a VVAU or MVAU - if isinstance(inst, MatrixVectorActivation): + if isinstance(inst, MVAU): K = inst.get_nodeattr("MW") # matrix_width = num_inputs elif isinstance(inst, VectorVectorActivation): k_h, k_w = inst.get_nodeattr("Kernel") @@ -275,7 +275,7 @@ def test_minimize_accumulator_width(wdt: DataType, idt: DataType, tdt: DataType, # If runtime-writeable weights, specify as a node attribute for node in model.graph.node: inst = getCustomOp(node) - if isinstance(inst, (MatrixVectorActivation, VectorVectorActivation)): + if isinstance(inst, (MVAU, VectorVectorActivation)): inst.set_nodeattr("runtime_writeable_weights", int(rww)) cur_adt = DataType[inst.get_nodeattr("accDataType")] assert cur_adt.bitwidth() == def_adt.bitwidth(), "Default data type is incorrect" @@ -286,7 +286,7 @@ def test_minimize_accumulator_width(wdt: DataType, idt: DataType, tdt: DataType, # Iterate through each node to make sure it functioned properly for node in model.graph.node: inst = getCustomOp(node) - if isinstance(inst, (MatrixVectorActivation, VectorVectorActivation)): + if isinstance(inst, (MVAU, VectorVectorActivation)): cur_adt = DataType[inst.get_nodeattr("accDataType")] cur_odt = DataType[inst.get_nodeattr("outputDataType")] # Calculating expected accumulator bit width using a closed-form expression diff --git a/tests/fpgadataflow/test_set_folding.py b/tests/fpgadataflow/test_set_folding.py index 4992bf59f8..19e459c222 100644 --- a/tests/fpgadataflow/test_set_folding.py +++ b/tests/fpgadataflow/test_set_folding.py @@ -64,7 +64,7 @@ def make_multi_fclayer_model(ch, wdt, adt, tdt, nnodes): simd = 1 FCLayer_nodes += [ helper.make_node( - "MatrixVectorActivation_hls", + "MVAU_hls", [tensors[i].name, "weights_" + str(i), "thresh_" + str(i)], [tensors[i + 1].name], domain="finn.custom_op.fpgadataflow.hls", diff --git a/tests/fpgadataflow/test_split_large_fifos.py b/tests/fpgadataflow/test_split_large_fifos.py index 653e1e7896..d4901c92ce 100644 --- a/tests/fpgadataflow/test_split_large_fifos.py +++ b/tests/fpgadataflow/test_split_large_fifos.py @@ -1,4 +1,4 @@ -# Copyright (C) 2022, Advanced Micro Devices, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -55,7 +55,7 @@ def get_folding_cfg(depth=65536): cfg = dict() cfg["Defaults"] = dict() for i in range(4): - key = "StreamingFIFO_" + str(i) + key = "StreamingFIFO_rtl_" + str(i) cfg[key] = {"depth": depth, "ram_style": "auto", "impl_style": "vivado"} return cfg @@ -98,7 +98,7 @@ def test_split_large_fifos(depth, force_python_rtlsim): ) model = ModelWrapper(tmp_output_dir + "/intermediate_models/step_set_fifo_depths.onnx") # exclude final FIFO node (output FIFO, not part of test) - fifo_nodes = model.get_nodes_by_op_type("StreamingFIFO")[:-1] + fifo_nodes = model.get_nodes_by_op_type("StreamingFIFO_rtl")[:-1] golden_cfg = get_fifo_split_configs(depth, 256, 32768) for i, fifo_node in enumerate(fifo_nodes): inst = getCustomOp(fifo_node) From b99035a3cea8d2470b1b6aa834953d7b39760c14 Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 19 Feb 2024 10:51:52 +0000 Subject: [PATCH 502/665] [MVAU/Tests] Change rtlsim function in MVAU execute node --- .../fpgadataflow/hls/matrixvectoractivation_hls.py | 5 ++--- tests/fpgadataflow/test_fpgadataflow_mvau.py | 10 +++++----- 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py b/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py index c6ca66e15d..e279d3953a 100644 --- a/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py @@ -29,7 +29,6 @@ import math import numpy as np import os -from pyverilator.util.axi_utils import reset_rtlsim, toggle_clk from qonnx.core.datatype import DataType from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend @@ -555,8 +554,8 @@ def execute_node(self, context, graph): sim = self.get_rtlsim() nbits = self.get_instream_width() inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) - reset_rtlsim(sim) - toggle_clk(sim) + self.reset_rtlsim(sim) + self.toggle_clk(sim) if mem_mode == "external" or mem_mode == "decoupled": wnbits = self.get_weightstream_width() export_wdt = self.get_weight_datatype() diff --git a/tests/fpgadataflow/test_fpgadataflow_mvau.py b/tests/fpgadataflow/test_fpgadataflow_mvau.py index f202b094e8..d10b560191 100644 --- a/tests/fpgadataflow/test_fpgadataflow_mvau.py +++ b/tests/fpgadataflow/test_fpgadataflow_mvau.py @@ -153,7 +153,7 @@ def prepare_inputs(input_tensor, idt, wdt): @pytest.mark.fpgadataflow @pytest.mark.slow @pytest.mark.vivado -def test_fpgadataflow_fclayer_hwop(idt, wdt, act, nf, sf, mw, mh): +def test_fpgadataflow_mvau_hwop(idt, wdt, act, nf, sf, mw, mh): if nf == -1: nf = mh if sf == -1: @@ -236,7 +236,7 @@ def test_fpgadataflow_fclayer_hwop(idt, wdt, act, nf, sf, mw, mh): @pytest.mark.fpgadataflow @pytest.mark.slow @pytest.mark.vivado -def test_fpgadataflow_fclayer_cppsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): +def test_fpgadataflow_mvau_cppsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): if nf == -1: nf = mh if sf == -1: @@ -329,7 +329,7 @@ def test_fpgadataflow_fclayer_cppsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): @pytest.mark.fpgadataflow @pytest.mark.slow @pytest.mark.vivado -def test_fpgadataflow_fclayer_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): +def test_fpgadataflow_mvau_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): if nf == -1: nf = mh if sf == -1: @@ -431,7 +431,7 @@ def test_fpgadataflow_fclayer_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): @pytest.mark.parametrize("backend", ["rtl", "hls"]) @pytest.mark.fpgadataflow @pytest.mark.vivado -def test_fpgadataflow_fclayer_large_depth_decoupled_mode_rtlsim( +def test_fpgadataflow_mvau_large_depth_decoupled_mode_rtlsim( mem_mode, idt, wdt, act, nf, sf, mw, mh, backend ): if nf == -1: @@ -538,7 +538,7 @@ def test_fpgadataflow_fclayer_large_depth_decoupled_mode_rtlsim( @pytest.mark.parametrize("backend", ["rtl", "hls"]) @pytest.mark.fpgadataflow @pytest.mark.vivado -def test_fclayer_fifocharacterize_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh, backend): +def test_mvau_fifocharacterize_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh, backend): if nf == -1: nf = mh if sf == -1: From e29485a0133d0ef271026a9e8505940575b36241 Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 19 Feb 2024 14:05:36 +0000 Subject: [PATCH 503/665] [Tests] Change tests to use new op type for MVAU --- tests/fpgadataflow/test_runtime_weights.py | 2 +- tests/transformation/test_infer_data_layouts_cnv.py | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/fpgadataflow/test_runtime_weights.py b/tests/fpgadataflow/test_runtime_weights.py index 0f0d88dd35..32534d4aa5 100644 --- a/tests/fpgadataflow/test_runtime_weights.py +++ b/tests/fpgadataflow/test_runtime_weights.py @@ -71,7 +71,7 @@ def test_runtime_weights_single_layer(): layer_spec_list = [layer_spec] model = hls_random_mlp_maker(layer_spec_list) model = model.transform(SpecializeLayers()) - fcl = model.get_nodes_by_op_type("MatrixVectorActivation_hls")[0] + fcl = model.get_nodes_by_op_type("MVAU_hls")[0] op_inst = getCustomOp(fcl) op_inst.set_nodeattr("mem_mode", "decoupled") op_inst.set_nodeattr("runtime_writeable_weights", 1) diff --git a/tests/transformation/test_infer_data_layouts_cnv.py b/tests/transformation/test_infer_data_layouts_cnv.py index 6b6674d661..fc9d98d24f 100644 --- a/tests/transformation/test_infer_data_layouts_cnv.py +++ b/tests/transformation/test_infer_data_layouts_cnv.py @@ -116,9 +116,9 @@ def test_infer_data_layouts_cnv(): # since the concept of channels changes with lowering... but it is # conceptually close to NHWC since the innermost dim gets multiplied assert model.get_tensor_layout("ConvolutionInputGenerator_0_out0") == DataLayout.NHWC - assert model.get_tensor_layout("MatrixVectorActivation_3_out0") == DataLayout.NHWC + assert model.get_tensor_layout("MVAU_3_out0") == DataLayout.NHWC assert model.get_tensor_layout("Reshape_0_out0") == DataLayout.NC - assert model.get_tensor_layout("MatrixVectorActivation_6_out0") == DataLayout.NC + assert model.get_tensor_layout("MVAU_6_out0") == DataLayout.NC assert model.get_tensor_layout("global_out") == DataLayout.NC os.remove(export_onnx_path_cnv) From 7429ee607c688e45589333b055cc68f6c0d898b3 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Tue, 20 Feb 2024 11:07:02 +0000 Subject: [PATCH 504/665] [CustomOp] Zero Pad threshold weights file between channel folds --- .../fpgadataflow/rtl/thresholding_rtl.py | 32 +++++++++++++------ 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py index 54797e1b94..26cba23620 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py @@ -753,6 +753,7 @@ def make_weight_file(self, weights, weight_file_mode, weight_file_name): # TODO add flips/reversals as needed here # (1, tmem, pe, n_thres_steps) -(1, tmem, pe * n_thres_steps) pe = self.get_nodeattr("PE") + ch = self.get_nodeattr("NumChannels") n_thres_steps = self.get_nodeattr("numSteps") decoupled_thres_pe_flipped = np.flip(decoupled_thres, axis=-2) decoupled_thres = decoupled_thres.reshape(1, -1, pe * n_thres_steps) @@ -762,21 +763,32 @@ def make_weight_file(self, weights, weight_file_mode, weight_file_name): ) decoupled_thres_pe_flipped = decoupled_thres_pe_flipped.copy() width_padded = roundup_to_integer_multiple(weights.shape[1], 4) - # # zero pad the row weight_padded = np.zeros((weights.shape[0],width_padded)) weight_padded[:weights.shape[0], :n_thres_steps ] = weights weight_stream = [] - for channel in weight_padded: - for weight in channel: - wdt = self.get_weight_datatype() - bw_hexdigit = roundup_to_integer_multiple(wdt.bitwidth(), 32) - weight_stream.append(pack_innermost_dim_as_hex_string( - [weight], wdt, bw_hexdigit, prefix="" - ).item()) - + wdt = self.get_weight_datatype() + bw_hexdigit = roundup_to_integer_multiple(wdt.bitwidth(), 32) + padding = np.zeros(width_padded, dtype=np.int32) + + chan_ind = 0 + cf = ch//pe + for fold in range(cf): + for c in range(2**pe.bit_length()): + if (c==0 or c%pe != 0) and c < pe: + for w in weight_padded[chan_ind]: + w_packed = pack_innermost_dim_as_hex_string( + [w], wdt, bw_hexdigit, prefix="" + ).item() + weight_stream.append(w_packed) + chan_ind +=1 + else: + for z in padding: + w_packed = pack_innermost_dim_as_hex_string( + [z], wdt, bw_hexdigit, prefix="" + ).item() + weight_stream.append(w_packed) with open(weight_file_name, "w") as f: for val in weight_stream: f.write(val + "\n") - else: raise Exception("Unknown weight_file_mode") \ No newline at end of file From b8b7bafa992c75e80e1bb333e3b3d8ee45c06312 Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 20 Feb 2024 11:45:48 +0000 Subject: [PATCH 505/665] [Tests] Fix MVAU test with large depth decoupled mode --- tests/fpgadataflow/test_fpgadataflow_mvau.py | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_mvau.py b/tests/fpgadataflow/test_fpgadataflow_mvau.py index d10b560191..216b0f2937 100644 --- a/tests/fpgadataflow/test_fpgadataflow_mvau.py +++ b/tests/fpgadataflow/test_fpgadataflow_mvau.py @@ -427,12 +427,10 @@ def test_fpgadataflow_mvau_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): @pytest.mark.parametrize("mw", [128]) # HLS matrix height (output features) @pytest.mark.parametrize("mh", [128]) -# Backend -@pytest.mark.parametrize("backend", ["rtl", "hls"]) @pytest.mark.fpgadataflow @pytest.mark.vivado def test_fpgadataflow_mvau_large_depth_decoupled_mode_rtlsim( - mem_mode, idt, wdt, act, nf, sf, mw, mh, backend + mem_mode, idt, wdt, act, nf, sf, mw, mh ): if nf == -1: nf = mh @@ -504,12 +502,9 @@ def test_fpgadataflow_mvau_large_depth_decoupled_mode_rtlsim( assert (y_produced.reshape(y_expected.shape) == y_expected).all(), "rtlsim failed" hls_synt_res_est = model.analysis(hls_synth_res_estimation) - if backend == "hls": - assert "MVAU_hls_0" in hls_synt_res_est - else: - assert "MVAU_rtl_0" in hls_synt_res_est + assert "MVAU_hls_0" in hls_synt_res_est - node = model.get_nodes_by_op_type("MVAU")[0] + node = model.get_nodes_by_op_type("MVAU_hls")[0] inst = getCustomOp(node) cycles_rtlsim = inst.get_nodeattr("cycles_rtlsim") exp_cycles_dict = model.analysis(exp_cycles_per_layer) @@ -534,11 +529,9 @@ def test_fpgadataflow_mvau_large_depth_decoupled_mode_rtlsim( @pytest.mark.parametrize("mw", [32]) # HLS matrix height (output features) @pytest.mark.parametrize("mh", [32]) -# Backend -@pytest.mark.parametrize("backend", ["rtl", "hls"]) @pytest.mark.fpgadataflow @pytest.mark.vivado -def test_mvau_fifocharacterize_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh, backend): +def test_mvau_fifocharacterize_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): if nf == -1: nf = mh if sf == -1: From 8220852b4d82cdd3e1e71bb1e7e223bbbcbdde19 Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 20 Feb 2024 13:27:24 +0000 Subject: [PATCH 506/665] [NB] First cleanup over notebooks --- notebooks/advanced/0_custom_analysis_pass.ipynb | 4 ++-- notebooks/advanced/1_custom_transformation_pass.ipynb | 8 ++++---- notebooks/advanced/2_custom_op.ipynb | 2 +- notebooks/basics/0_how_to_work_with_onnx.ipynb | 4 ++-- .../basics/1_brevitas_network_import_via_QONNX.ipynb | 6 +++--- 5 files changed, 12 insertions(+), 12 deletions(-) diff --git a/notebooks/advanced/0_custom_analysis_pass.ipynb b/notebooks/advanced/0_custom_analysis_pass.ipynb index f915b11fa0..5ed48ca6d8 100644 --- a/notebooks/advanced/0_custom_analysis_pass.ipynb +++ b/notebooks/advanced/0_custom_analysis_pass.ipynb @@ -153,9 +153,9 @@ "name": "python", "nbconvert_exporter": "python", "pygments_lexer": "ipython3", - "version": "3.8.5" + "version": "3.10.12" } }, "nbformat": 4, - "nbformat_minor": 2 + "nbformat_minor": 4 } diff --git a/notebooks/advanced/1_custom_transformation_pass.ipynb b/notebooks/advanced/1_custom_transformation_pass.ipynb index 7e4989c902..91dd925b25 100644 --- a/notebooks/advanced/1_custom_transformation_pass.ipynb +++ b/notebooks/advanced/1_custom_transformation_pass.ipynb @@ -212,7 +212,7 @@ "\n", "To control the degree of parallelization the argument `num_workers` can be specified. When the Docker container is started, the env variable `NUM_DEFAULT_WORKERS` is set to 4 by default, this can be increased or decreased depending on the system. You can also set the number of workers manually to a specific value when calling a transformation that allows parallelization. If the value is set to 0, all available CPU cores are used.\n", "\n", - "In the following we want to take a closer look at the implementation using the compile transformation as example." + "In the following we want to take a closer look at the implementation using the compile transformation that is used for cpp simulation as example." ] }, { @@ -230,7 +230,7 @@ "cell_type": "markdown", "metadata": {}, "source": [ - "The class is derived from the NodeLocalTransformation class and performs the compilation at every node that is fpgadataflow node." + "The class is derived from the NodeLocalTransformation class and performs the compilation at every node that is an hls node." ] } ], @@ -250,9 +250,9 @@ "name": "python", "nbconvert_exporter": "python", "pygments_lexer": "ipython3", - "version": "3.8.5" + "version": "3.10.12" } }, "nbformat": 4, - "nbformat_minor": 2 + "nbformat_minor": 4 } diff --git a/notebooks/advanced/2_custom_op.ipynb b/notebooks/advanced/2_custom_op.ipynb index 636da64dd5..bdd2976412 100644 --- a/notebooks/advanced/2_custom_op.ipynb +++ b/notebooks/advanced/2_custom_op.ipynb @@ -672,7 +672,7 @@ "name": "python", "nbconvert_exporter": "python", "pygments_lexer": "ipython3", - "version": "3.8.5" + "version": "3.10.12" } }, "nbformat": 4, diff --git a/notebooks/basics/0_how_to_work_with_onnx.ipynb b/notebooks/basics/0_how_to_work_with_onnx.ipynb index 35a83ea97b..f1b3dcf68b 100644 --- a/notebooks/basics/0_how_to_work_with_onnx.ipynb +++ b/notebooks/basics/0_how_to_work_with_onnx.ipynb @@ -613,9 +613,9 @@ "name": "python", "nbconvert_exporter": "python", "pygments_lexer": "ipython3", - "version": "3.8.5" + "version": "3.10.12" } }, "nbformat": 4, - "nbformat_minor": 2 + "nbformat_minor": 4 } diff --git a/notebooks/basics/1_brevitas_network_import_via_QONNX.ipynb b/notebooks/basics/1_brevitas_network_import_via_QONNX.ipynb index f15f716e7f..5c2f10310f 100644 --- a/notebooks/basics/1_brevitas_network_import_via_QONNX.ipynb +++ b/notebooks/basics/1_brevitas_network_import_via_QONNX.ipynb @@ -177,7 +177,7 @@ "source": [ "## 3. Import into FINN and converting QONNX to FINN-ONNX\n", "\n", - "Similarily to the 1a notebook we will first run a cleanup transformation on the exported QONNX model." + "We will first run a cleanup transformation on the exported QONNX model." ] }, { @@ -318,9 +318,9 @@ "name": "python", "nbconvert_exporter": "python", "pygments_lexer": "ipython3", - "version": "3.10.6" + "version": "3.10.12" } }, "nbformat": 4, - "nbformat_minor": 2 + "nbformat_minor": 4 } From c5ca1285e8b613f38930eb3b91d7039750f9c9d0 Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 20 Feb 2024 15:10:19 +0000 Subject: [PATCH 507/665] [NB] Update cybersec notebooks --- .../cybersecurity/1-train-mlp-with-brevitas.ipynb | 2 +- .../cybersecurity/2-import-into-finn-and-verify.ipynb | 2 +- .../cybersecurity/3-build-accelerator-with-finn.ipynb | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/notebooks/end2end_example/cybersecurity/1-train-mlp-with-brevitas.ipynb b/notebooks/end2end_example/cybersecurity/1-train-mlp-with-brevitas.ipynb index 7644173284..da037050bb 100644 --- a/notebooks/end2end_example/cybersecurity/1-train-mlp-with-brevitas.ipynb +++ b/notebooks/end2end_example/cybersecurity/1-train-mlp-with-brevitas.ipynb @@ -769,7 +769,7 @@ "name": "python", "nbconvert_exporter": "python", "pygments_lexer": "ipython3", - "version": "3.10.6" + "version": "3.10.12" } }, "nbformat": 4, diff --git a/notebooks/end2end_example/cybersecurity/2-import-into-finn-and-verify.ipynb b/notebooks/end2end_example/cybersecurity/2-import-into-finn-and-verify.ipynb index a5bc165573..33b64e11c0 100644 --- a/notebooks/end2end_example/cybersecurity/2-import-into-finn-and-verify.ipynb +++ b/notebooks/end2end_example/cybersecurity/2-import-into-finn-and-verify.ipynb @@ -399,7 +399,7 @@ "name": "python", "nbconvert_exporter": "python", "pygments_lexer": "ipython3", - "version": "3.10.6" + "version": "3.10.12" } }, "nbformat": 4, diff --git a/notebooks/end2end_example/cybersecurity/3-build-accelerator-with-finn.ipynb b/notebooks/end2end_example/cybersecurity/3-build-accelerator-with-finn.ipynb index 80f3cd3819..5e8bff3e04 100644 --- a/notebooks/end2end_example/cybersecurity/3-build-accelerator-with-finn.ipynb +++ b/notebooks/end2end_example/cybersecurity/3-build-accelerator-with-finn.ipynb @@ -659,7 +659,7 @@ "name": "python", "nbconvert_exporter": "python", "pygments_lexer": "ipython3", - "version": "3.8.5" + "version": "3.10.12" } }, "nbformat": 4, From 0928d31039107b57c69b6bf0144be0d2939077bc Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Tue, 20 Feb 2024 17:47:24 +0000 Subject: [PATCH 508/665] [test]: added extra tests to RTL-based MVAU --- tests/fpgadataflow/test_fpgadataflow_mvau.py | 139 ++++++++++++++++++- 1 file changed, 135 insertions(+), 4 deletions(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_mvau.py b/tests/fpgadataflow/test_fpgadataflow_mvau.py index d10b560191..85cca66835 100644 --- a/tests/fpgadataflow/test_fpgadataflow_mvau.py +++ b/tests/fpgadataflow/test_fpgadataflow_mvau.py @@ -26,6 +26,8 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +import os +import pickle import pytest import numpy as np @@ -35,7 +37,7 @@ from qonnx.core.modelwrapper import ModelWrapper from qonnx.custom_op.general.multithreshold import multithreshold from qonnx.custom_op.registry import getCustomOp -from qonnx.transformation.general import GiveUniqueNodeNames +from qonnx.transformation.general import GiveUniqueNodeNames, GiveReadableTensorNames, ApplyConfig from qonnx.util.basic import ( calculate_signed_dot_prod_range, gen_finn_dt_tensor, @@ -53,6 +55,9 @@ from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers +import finn.transformation.fpgadataflow.convert_to_hw_layers as to_hw +from finn.transformation.fpgadataflow.set_fifo_depths import InsertAndSetFIFODepths +from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP def make_single_fclayer_modelwrapper(W, pe, simd, wdt, idt, odt, T=None, tdt=None): @@ -128,12 +133,30 @@ def make_single_fclayer_modelwrapper(W, pe, simd, wdt, idt, odt, T=None, tdt=Non return model -def prepare_inputs(input_tensor, idt, wdt): +def make_single_matmul_modelwrapper(ifm, ofm, idt, wdt, W): + matmul_node = helper.make_node("MatMul", ["ifm", "weights"], ["ofm"]) + graph = helper.make_graph(nodes=[matmul_node], name="matmul_graph", inputs=[ifm], outputs=[ofm]) + + model = qonnx_make_model(graph, producer_name="fclayer-model") + model = ModelWrapper(model) + + model.set_tensor_datatype("ifm", idt) + model.set_tensor_datatype("weights", wdt) + model.set_tensor_datatype( + "ofm", DataType["INT32"] + ) # At this step, the MatMul layer does not optimize the bit-width of the output datatype + model.set_initializer("weights", W) + # model.set_tensor_layout("ifm", DataLayout.NHWC) + + return model + + +def prepare_inputs(input_tensor, idt, wdt, inp_name="inp"): if wdt == DataType["BIPOLAR"] and idt == DataType["BIPOLAR"]: # convert bipolar to binary - return {"inp": (input_tensor + 1) / 2} + return {inp_name: (input_tensor + 1) / 2} else: - return {"inp": input_tensor} + return {inp_name: input_tensor} # activation: None or DataType @@ -370,6 +393,7 @@ def test_fpgadataflow_mvau_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): # lookup op_type in registry of CustomOps inst = getCustomOp(node) inst.set_nodeattr("mem_mode", mem_mode) + inst.set_nodeattr("rtlsim_trace", "mvau_trace.vcd") # prepare input data input_dict = prepare_inputs(x, idt, wdt) @@ -396,6 +420,7 @@ def test_fpgadataflow_mvau_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): model = model.transform(PrepareIP("xc7z020clg400-1", 5)) model = model.transform(HLSSynthIP()) model = model.transform(PrepareRTLSim()) + model.save("mvau_rtl.onnx") y_produced = oxe.execute_onnx(model, input_dict)["outp"] assert (y_produced.reshape(y_expected.shape) == y_expected).all(), "rtlsim failed" @@ -583,3 +608,109 @@ def test_mvau_fifocharacterize_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh, b assert (chrc_in[0, :sf] == range(1, sf + 1)).all() # all outputs should be produced within the exp n of cycles assert chrc_out[0, exp_total_cycles] == nf + + +# @pytest.mark.parametrize("mh", [36]) +# @pytest.mark.parametrize("mw", [256]) +@pytest.mark.parametrize("mh", [1]) +@pytest.mark.parametrize("mw", [8]) +# @pytest.mark.parametrize("pe", [1, 4, 9, 36]) +# @pytest.mark.parametrize("simd", [1, 4, 16, 64, 256]) +# @pytest.mark.parametrize("pe", [1, 3, 9]) +# @pytest.mark.parametrize("simd", [1, 3, 6, 18, 36]) +@pytest.mark.parametrize("pe", [1]) +@pytest.mark.parametrize("simd", [4]) +# @pytest.mark.parametrize("idt", [DataType["UINT4"], DataType["UINT8"]]) +# @pytest.mark.parametrize("wdt", [DataType["INT4"], DataType["INT8"]]) +@pytest.mark.parametrize("idt", [DataType["UINT4"]]) +@pytest.mark.parametrize("wdt", [DataType["INT4"]]) +# @pytest.mark.parametrize("part", ["xcvc1902-vsva2197-2MP-e-S", "xcku3p-ffva676-1-e"]) +@pytest.mark.parametrize("part", ["xcvc1902-vsva2197-2MP-e-S"]) +# @pytest.mark.parametrize("clk_ns", [1.66, 4]) +@pytest.mark.parametrize("clk_ns", [4]) +@pytest.mark.fpgadataflow +@pytest.mark.slow +@pytest.mark.vivado +def test_fpgadataflow_rtl_mvau( + mh, mw, pe, simd, idt, wdt, part, clk_ns +): + if part == "xcku3p-ffva676-1-e" and clk_ns != 1.66: + pytest.skip("Skip test for varying clk for devices other than Versal, since this variable doesn't change anything for this test") + + build_dir = os.environ["FINN_BUILD_DIR"] + # Create test input vector (produced by SWG) + ofm_shape = (2, 2) + ofm_h, ofm_w = ofm_shape + ifm = helper.make_tensor_value_info("ifm", TensorProto.FLOAT, [1, ofm_h, ofm_w, mw]) + ofm = helper.make_tensor_value_info("ofm", TensorProto.FLOAT, (1, ofm_h, ofm_w, mh)) + W = gen_finn_dt_tensor(wdt, (mw, mh)) + model = make_single_matmul_modelwrapper(ifm, ofm, idt, wdt, W) + model = model.transform(GiveUniqueNodeNames()) + model = model.transform(GiveReadableTensorNames()) + + model.save(build_dir + "/matmul.onnx") + + # Create MatMul & obtain golden reference output + A = gen_finn_dt_tensor(model.get_tensor_datatype("global_in"), model.get_tensor_shape("global_in")) + input_dict = prepare_inputs(A, idt, wdt, inp_name="global_in") + + # Execute ONNX model + output_matmul = oxe.execute_onnx(model, input_dict)["global_out"] + + with open(build_dir + "/onnx_output.pkl", "wb") as f: + pickle.dump(output_matmul, f) + + # Create MVAU (HLS) + model = model.transform(to_hw.InferQuantizedMatrixVectorActivation(mem_mode="decoupled")) + model = model.transform(GiveUniqueNodeNames()) + + # Apply folding (i.e. specify to use DSPs) + folding_config = { + "Defaults": {}, + "MVAU_0": { + "PE": pe, + "SIMD": simd, + "mem_mode": "decoupled", + "ram_style": "auto", + "resType": "dsp", + "preferred_impl_style" : "rtl" + }, + } + model = model.transform(ApplyConfig(folding_config)) + model.save(build_dir + "/mvau_hls.onnx") + + # Apply convert-to-rtl step + model = model.transform(SpecializeLayers()) + model = model.transform(GiveUniqueNodeNames()) + model.save(build_dir + "/mvau_rtl.onnx") + + # Reset rtlsim_so and ip-related paths such that new Pyverilator SO and IP is generated + for n in model.graph.node: + getCustomOp(n).set_nodeattr("rtlsim_trace", build_dir + "/mvu_trace_rtl_nodebynode.vcd") + + model = model.transform(SetExecMode("rtlsim")) + model = model.transform(PrepareIP(part, clk_ns)) + model = model.transform(HLSSynthIP()) + model = model.transform(PrepareRTLSim()) + output_mvau_rtl = oxe.execute_onnx(model, input_dict)["global_out"] + + with open(build_dir + "/mvau_rtl_output.pkl", "wb") as f: + pickle.dump(output_mvau_rtl, f) + + model.save(build_dir + "/mvau_rtl_sim.onnx") + import pdb; pdb.set_trace() + assert (output_matmul == output_mvau_rtl).all(), "Output of ONNX model not matching output of node-by-node sim!" + + model = model.transform(InsertAndSetFIFODepths(part, clk_ns)) + model = model.transform(PrepareIP(part, clk_ns)) + model = model.transform(HLSSynthIP()) + model = model.transform(CreateStitchedIP(part, clk_ns)) + + os.environ["RTLSIM_TRACE_DEPTH"] = "3" + model.set_metadata_prop("rtlsim_so", "") + model.set_metadata_prop("exec_mode", "rtlsim") + model.set_metadata_prop("rtlsim_trace", build_dir + "/mvu_trace_rtl_stitch.vcd") + model.save(build_dir + "/stitched_ip.onnx") + output_mvau_rtl_stitch = oxe.execute_onnx(model, input_dict)["global_out"] + + assert (output_matmul == output_mvau_rtl_stitch).all(), "Output of ONNX model not matching output of stitched-IP RTL model!" \ No newline at end of file From ef8157c06c4d5d771c9aa9d4bd527ec09c898ad5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thomas=20B=2E=20Preu=C3=9Fer?= Date: Wed, 21 Feb 2024 14:36:56 +0000 Subject: [PATCH 509/665] Reply to readbacks from padded memory areas. --- finn-rtllib/thresholding/hdl/thresholding.sv | 26 +++++++++++++++---- .../thresholding/sim/thresholding_tb.sv | 2 +- 2 files changed, 22 insertions(+), 6 deletions(-) diff --git a/finn-rtllib/thresholding/hdl/thresholding.sv b/finn-rtllib/thresholding/hdl/thresholding.sv index dc612f387f..4c83c8e9db 100644 --- a/finn-rtllib/thresholding/hdl/thresholding.sv +++ b/finn-rtllib/thresholding/hdl/thresholding.sv @@ -146,16 +146,32 @@ module thresholding #( end // PE Configuration Address Decoding - uwire cfg_sel[PE]; - if(PE == 1) assign cfg_sel[0] = 1; + logic cfg_sel[PE]; + logic cfg_oob; + logic [N-1:0] cfg_ofs; + if(PE == 1) begin + assign cfg_sel[0] = 1; + assign cfg_oob = 0; + assign cfg_ofs = cfg_a[0+:N]; + end else begin - for(genvar pe = 0; pe < PE; pe++) begin - assign cfg_sel[pe] = USE_CONFIG && cfg_en && (cfg_a[N+:$clog2(PE)] == pe); + uwire [$clog2(PE)-1:0] cfg_pe = cfg_a[N+:$clog2(PE)]; + always_comb begin + foreach(cfg_sel[pe]) begin + cfg_sel[pe] = USE_CONFIG && cfg_en && (cfg_pe == pe); + end + cfg_oob = (cfg_pe >= PE); + cfg_ofs = cfg_a[0+:N]; + if(cfg_oob && !cfg_we) begin + // Map readbacks from padded rows (non-existent PEs) to padded highest threshold index of first PE + cfg_sel[0] = 1; + cfg_ofs = '1; + end end end uwire ptr_t iptr; - assign iptr[0+:N] = cfg_a[0+:N]; + assign iptr[0+:N] = cfg_ofs; if(CF > 1) begin // Channel Fold Rotation logic [$clog2(CF)-1:0] CnlCnt = 0; diff --git a/finn-rtllib/thresholding/sim/thresholding_tb.sv b/finn-rtllib/thresholding/sim/thresholding_tb.sv index e42145f10e..3f4ca61a85 100644 --- a/finn-rtllib/thresholding/sim/thresholding_tb.sv +++ b/finn-rtllib/thresholding/sim/thresholding_tb.sv @@ -196,7 +196,7 @@ module thresholding_tb #( end join_any done <= 1; - repeat((DEEP_PIPELINE+1)*N+6) @(posedge clk); + repeat((DEEP_PIPELINE+1)*N+8) @(posedge clk); assert(QW.size() == 0) else begin $error("[%0d] Missing %0d outputs.", i, QW.size()); From a395fc7d35e7410693edfb5253c91b83dfe054fb Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 21 Feb 2024 18:16:33 +0000 Subject: [PATCH 510/665] [Transform/Analysis] Cleanup usage of is_fpgadataflow_node --- .../fpgadataflow/dataflow_performance.py | 9 ++-- .../fpgadataflow/exp_cycles_per_layer.py | 7 +-- .../analysis/fpgadataflow/floorplan_params.py | 3 +- .../fpgadataflow/hls_synth_res_estimation.py | 4 +- .../analysis/fpgadataflow/post_synth_res.py | 7 +-- .../fpgadataflow/annotate_cycles.py | 7 +-- .../fpgadataflow/annotate_resources.py | 7 +-- .../transformation/fpgadataflow/cleanup.py | 5 +- .../fpgadataflow/compile_cppsim.py | 4 +- .../fpgadataflow/derive_characteristic.py | 6 +-- .../fpgadataflow/hlssynth_ip.py | 6 +-- .../transformation/fpgadataflow/insert_dwc.py | 2 +- .../fpgadataflow/insert_fifo.py | 7 +-- .../fpgadataflow/insert_hook.py | 6 +-- .../minimize_accumulator_width.py | 5 +- .../fpgadataflow/minimize_weight_bit_width.py | 4 +- .../fpgadataflow/prepare_cppsim.py | 4 +- .../transformation/fpgadataflow/prepare_ip.py | 18 +++++-- .../fpgadataflow/prepare_rtlsim.py | 7 +-- .../fpgadataflow/replace_verilog_relpaths.py | 7 +-- .../fpgadataflow/set_exec_mode.py | 51 ++++++++++--------- .../fpgadataflow/set_fifo_depths.py | 6 ++- .../fpgadataflow/set_folding.py | 7 +-- src/finn/transformation/move_reshape.py | 23 ++------- 24 files changed, 113 insertions(+), 99 deletions(-) diff --git a/src/finn/analysis/fpgadataflow/dataflow_performance.py b/src/finn/analysis/fpgadataflow/dataflow_performance.py index 824690f5f6..a4bf40760e 100644 --- a/src/finn/analysis/fpgadataflow/dataflow_performance.py +++ b/src/finn/analysis/fpgadataflow/dataflow_performance.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (c) 2020, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -28,7 +29,7 @@ from qonnx.custom_op.registry import getCustomOp -from finn.util.fpgadataflow import is_fpgadataflow_node +from finn.util.fpgadataflow import is_hls_node, is_rtl_node def dataflow_performance(model): @@ -38,7 +39,7 @@ def dataflow_performance(model): for each node along the critical path. Preconditions: - - model consists of fpgadataflow nodes + - model consists of HLS/RTL nodes - model has cycle estimates annotated (see AnnotateCycles transformation) - nodes have unique names (see GiveUniqueNodeNames) @@ -52,7 +53,7 @@ def dataflow_performance(model): max_node_name = "" for node in model.graph.node: - if is_fpgadataflow_node(node) is True: + if is_hls_node(node) or is_rtl_node(node): inst = getCustomOp(node) node_cycles = int(inst.get_nodeattr("cycles_estimate")) if node_cycles > max_cycles: diff --git a/src/finn/analysis/fpgadataflow/exp_cycles_per_layer.py b/src/finn/analysis/fpgadataflow/exp_cycles_per_layer.py index e1517ec636..50585720fe 100644 --- a/src/finn/analysis/fpgadataflow/exp_cycles_per_layer.py +++ b/src/finn/analysis/fpgadataflow/exp_cycles_per_layer.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (c) 2020, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -28,7 +29,7 @@ import qonnx.custom_op.registry as registry -from finn.util.fpgadataflow import is_fpgadataflow_node +from finn.util.fpgadataflow import is_hls_node, is_rtl_node def exp_cycles_per_layer(model): @@ -41,7 +42,7 @@ def exp_cycles_per_layer(model): cycle_dict = {} for node in model.graph.node: - if is_fpgadataflow_node(node) is True: + if is_hls_node(node) or is_rtl_node(node): inst = registry.getCustomOp(node) cycle_dict[node.name] = int(inst.get_exp_cycles()) diff --git a/src/finn/analysis/fpgadataflow/floorplan_params.py b/src/finn/analysis/fpgadataflow/floorplan_params.py index d57b660bce..be03966fb9 100644 --- a/src/finn/analysis/fpgadataflow/floorplan_params.py +++ b/src/finn/analysis/fpgadataflow/floorplan_params.py @@ -1,4 +1,5 @@ # Copyright (c) 2020, Xilinx +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -45,7 +46,7 @@ def floorplan_params(model): } } for node in model.graph.node: - if is_fpgadataflow_node(node) is True: + if is_fpgadataflow_node(node): node_inst = getCustomOp(node) node_slr = node_inst.get_nodeattr("slr") node_pid = node_inst.get_nodeattr("partition_id") diff --git a/src/finn/analysis/fpgadataflow/hls_synth_res_estimation.py b/src/finn/analysis/fpgadataflow/hls_synth_res_estimation.py index cd6b322727..330494315a 100644 --- a/src/finn/analysis/fpgadataflow/hls_synth_res_estimation.py +++ b/src/finn/analysis/fpgadataflow/hls_synth_res_estimation.py @@ -30,7 +30,7 @@ import warnings import xml.etree.ElementTree as ET -from finn.util.fpgadataflow import is_fpgadataflow_node, is_hls_node +from finn.util.fpgadataflow import is_hls_node def hls_synth_res_estimation(model): @@ -44,7 +44,7 @@ def hls_synth_res_estimation(model): res_dict = {} for node in model.graph.node: - if is_fpgadataflow_node(node) and is_hls_node(node): + if is_hls_node(node): # init values to zero res_dict[node.name] = dict() res_dict[node.name]["BRAM_18K"] = 0 diff --git a/src/finn/analysis/fpgadataflow/post_synth_res.py b/src/finn/analysis/fpgadataflow/post_synth_res.py index 3304b88d60..7b65b60fa7 100644 --- a/src/finn/analysis/fpgadataflow/post_synth_res.py +++ b/src/finn/analysis/fpgadataflow/post_synth_res.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (c) 2020, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -31,7 +32,7 @@ from qonnx.core.modelwrapper import ModelWrapper from qonnx.custom_op.registry import getCustomOp -from finn.transformation.move_reshape import _is_fpgadataflow_node +from finn.util.fpgadataflow import is_hls_node, is_rtl_node def post_synth_res(model, override_synth_report_filename=None): @@ -102,7 +103,7 @@ def get_instance_stats(inst_name): sdp_model = ModelWrapper(getCustomOp(node).get_nodeattr("model")) sdp_res_dict = post_synth_res(sdp_model, synth_report_filename) res_dict.update(sdp_res_dict) - elif _is_fpgadataflow_node(node): + elif is_hls_node(node) or is_rtl_node(node): node_dict = get_instance_stats(node.name) if node_dict is not None: res_dict[node.name] = node_dict diff --git a/src/finn/transformation/fpgadataflow/annotate_cycles.py b/src/finn/transformation/fpgadataflow/annotate_cycles.py index 7befad7aa7..6646434bdf 100644 --- a/src/finn/transformation/fpgadataflow/annotate_cycles.py +++ b/src/finn/transformation/fpgadataflow/annotate_cycles.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (c) 2020, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -31,7 +32,7 @@ from qonnx.custom_op.registry import getCustomOp from qonnx.transformation.base import Transformation -from finn.transformation.move_reshape import _is_fpgadataflow_node +from finn.util.fpgadataflow import is_hls_node, is_rtl_node class AnnotateCycles(Transformation): @@ -46,7 +47,7 @@ def apply(self, model): graph = model.graph # annotate node cycles for node in graph.node: - if _is_fpgadataflow_node(node): + if is_hls_node(node) or is_rtl_node(node): op_inst = registry.getCustomOp(node) cycles = op_inst.get_exp_cycles() op_inst.set_nodeattr("cycles_estimate", cycles) diff --git a/src/finn/transformation/fpgadataflow/annotate_resources.py b/src/finn/transformation/fpgadataflow/annotate_resources.py index bb5637f7d3..f07a5186d5 100644 --- a/src/finn/transformation/fpgadataflow/annotate_resources.py +++ b/src/finn/transformation/fpgadataflow/annotate_resources.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (c) 2020, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -34,7 +35,7 @@ from finn.analysis.fpgadataflow.hls_synth_res_estimation import hls_synth_res_estimation from finn.analysis.fpgadataflow.post_synth_res import post_synth_res from finn.analysis.fpgadataflow.res_estimation import res_estimation -from finn.transformation.move_reshape import _is_fpgadataflow_node +from finn.util.fpgadataflow import is_fpgadataflow_node class AnnotateResources(Transformation): @@ -68,7 +69,7 @@ def apply(self, model): children_dict = {} # annotate node resources for node in graph.node: - if _is_fpgadataflow_node(node) and node.name in self.res_dict.keys(): + if is_fpgadataflow_node(node) and node.name in self.res_dict.keys(): op_inst = registry.getCustomOp(node) op_inst.set_nodeattr("res_" + self.mode, str(self.res_dict[node.name])) children_dict[node.name] = self.res_dict[node.name] diff --git a/src/finn/transformation/fpgadataflow/cleanup.py b/src/finn/transformation/fpgadataflow/cleanup.py index 398580c48e..907b65eb9d 100644 --- a/src/finn/transformation/fpgadataflow/cleanup.py +++ b/src/finn/transformation/fpgadataflow/cleanup.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (c) 2020, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -53,7 +54,7 @@ def apply(self, model): model.set_metadata_prop("vivado_stitch_proj", "") for node in model.graph.node: op_type = node.op_type - if is_fpgadataflow_node(node) is True: + if is_fpgadataflow_node(node): try: # lookup op_type in registry of CustomOps inst = registry.getCustomOp(node) diff --git a/src/finn/transformation/fpgadataflow/compile_cppsim.py b/src/finn/transformation/fpgadataflow/compile_cppsim.py index 4814b24a92..6190560265 100644 --- a/src/finn/transformation/fpgadataflow/compile_cppsim.py +++ b/src/finn/transformation/fpgadataflow/compile_cppsim.py @@ -30,7 +30,7 @@ import qonnx.custom_op.registry as registry from qonnx.transformation.base import NodeLocalTransformation -from finn.util.fpgadataflow import is_fpgadataflow_node, is_hls_node +from finn.util.fpgadataflow import is_hls_node class CompileCppSim(NodeLocalTransformation): @@ -51,7 +51,7 @@ def __init__(self, num_workers=None): def applyNodeLocal(self, node): op_type = node.op_type - if is_fpgadataflow_node(node) and is_hls_node(node): + if is_hls_node(node): try: # lookup op_type in registry of CustomOps inst = registry.getCustomOp(node) diff --git a/src/finn/transformation/fpgadataflow/derive_characteristic.py b/src/finn/transformation/fpgadataflow/derive_characteristic.py index dee9b62e67..4d3ac7dc67 100644 --- a/src/finn/transformation/fpgadataflow/derive_characteristic.py +++ b/src/finn/transformation/fpgadataflow/derive_characteristic.py @@ -33,7 +33,7 @@ from qonnx.core.modelwrapper import ModelWrapper from qonnx.transformation.base import NodeLocalTransformation -from finn.util.fpgadataflow import is_fpgadataflow_node +from finn.util.fpgadataflow import is_hls_node, is_rtl_node class DeriveCharacteristic(NodeLocalTransformation): @@ -59,7 +59,7 @@ def __init__(self, period, num_workers=None, manual_bypass=False): def applyNodeLocal(self, node): op_type = node.op_type - if is_fpgadataflow_node(node) is True: + if is_hls_node(node) or is_rtl_node(node): try: # lookup op_type in registry of CustomOps inst = registry.getCustomOp(node) @@ -131,7 +131,7 @@ def __init__(self, num_workers=None, io_fifo_depth=32): def applyNodeLocal(self, node): op_type = node.op_type - if is_fpgadataflow_node(node) is True: + if is_hls_node(node) or is_rtl_node(node): try: # lookup op_type in registry of CustomOps prod = registry.getCustomOp(node) diff --git a/src/finn/transformation/fpgadataflow/hlssynth_ip.py b/src/finn/transformation/fpgadataflow/hlssynth_ip.py index daf64656b5..5b901d9284 100644 --- a/src/finn/transformation/fpgadataflow/hlssynth_ip.py +++ b/src/finn/transformation/fpgadataflow/hlssynth_ip.py @@ -32,11 +32,11 @@ import warnings from qonnx.transformation.base import NodeLocalTransformation -from finn.util.fpgadataflow import is_fpgadataflow_node, is_hls_node +from finn.util.fpgadataflow import is_hls_node class HLSSynthIP(NodeLocalTransformation): - """For each node: generate IP block from code in folder + """For each HLS node: generate IP block from code in folder that is referenced in node attribute "code_gen_dir_ipgen" and save path of generated project in node attribute "ipgen_path". All nodes in the graph must have the fpgadataflow backend attribute. @@ -55,7 +55,7 @@ def __init__(self, num_workers=None): def applyNodeLocal(self, node): op_type = node.op_type - if is_fpgadataflow_node(node) and is_hls_node(node): + if is_hls_node(node): try: # lookup op_type in registry of CustomOps inst = registry.getCustomOp(node) diff --git a/src/finn/transformation/fpgadataflow/insert_dwc.py b/src/finn/transformation/fpgadataflow/insert_dwc.py index 100beefcc2..96c114498c 100644 --- a/src/finn/transformation/fpgadataflow/insert_dwc.py +++ b/src/finn/transformation/fpgadataflow/insert_dwc.py @@ -43,7 +43,7 @@ def _is_dwc_node(node): def _suitable_node(node): if node is not None: - if is_fpgadataflow_node(node) is True: + if is_fpgadataflow_node(node): if _is_dwc_node(node): # no DWC for DWCs return False diff --git a/src/finn/transformation/fpgadataflow/insert_fifo.py b/src/finn/transformation/fpgadataflow/insert_fifo.py index 630310842c..9df193efcf 100644 --- a/src/finn/transformation/fpgadataflow/insert_fifo.py +++ b/src/finn/transformation/fpgadataflow/insert_fifo.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (c) 2020, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -45,8 +46,8 @@ def _is_fifo_node(node): def _suitable_node(node): if node is not None: - if is_fpgadataflow_node(node) is True: - if _is_fifo_node(node) is False: + if is_fpgadataflow_node(node): + if not _is_fifo_node(node): return True else: return False diff --git a/src/finn/transformation/fpgadataflow/insert_hook.py b/src/finn/transformation/fpgadataflow/insert_hook.py index 23b60d6812..843a32a73e 100644 --- a/src/finn/transformation/fpgadataflow/insert_hook.py +++ b/src/finn/transformation/fpgadataflow/insert_hook.py @@ -34,7 +34,7 @@ from qonnx.transformation.base import Transformation from qonnx.transformation.general import GiveReadableTensorNames, GiveUniqueNodeNames -from finn.util.fpgadataflow import is_fpgadataflow_node +from finn.util.fpgadataflow import is_hls_node, is_rtl_node def _is_hook_node(node): @@ -46,8 +46,8 @@ def _is_hook_node(node): def _suitable_node(node): if node is not None: - if is_fpgadataflow_node(node) is True: - if _is_hook_node(node) is False: + if is_hls_node(node) or is_rtl_node(node): + if not _is_hook_node(node): return True else: return False diff --git a/src/finn/transformation/fpgadataflow/minimize_accumulator_width.py b/src/finn/transformation/fpgadataflow/minimize_accumulator_width.py index 8d04d5b817..61159fde0c 100644 --- a/src/finn/transformation/fpgadataflow/minimize_accumulator_width.py +++ b/src/finn/transformation/fpgadataflow/minimize_accumulator_width.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2020, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -46,7 +47,7 @@ def apply(self, model): # Since InferDataTypes potentially changes node attributes in each loop iterations, # the for-loop cannot loop over a list of a snapshot of the graph's node protos node = model.graph.node[node_id] - if is_fpgadataflow_node(node) is True: + if is_fpgadataflow_node(node): inst = getCustomOp(node) if hasattr(inst, "minimize_accumulator_width"): inst.minimize_accumulator_width(model) diff --git a/src/finn/transformation/fpgadataflow/minimize_weight_bit_width.py b/src/finn/transformation/fpgadataflow/minimize_weight_bit_width.py index 32871cc44a..49770f7d0c 100644 --- a/src/finn/transformation/fpgadataflow/minimize_weight_bit_width.py +++ b/src/finn/transformation/fpgadataflow/minimize_weight_bit_width.py @@ -1,4 +1,4 @@ -# Copyright (C) 2023, Advanced Micro Devices, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -42,7 +42,7 @@ def __init__(self): def apply(self, model): for node in model.graph.node: - if is_fpgadataflow_node(node) is True: + if is_fpgadataflow_node(node): inst = getCustomOp(node) if hasattr(inst, "minimize_weight_bit_width"): inst.minimize_weight_bit_width(model) diff --git a/src/finn/transformation/fpgadataflow/prepare_cppsim.py b/src/finn/transformation/fpgadataflow/prepare_cppsim.py index 0b744b5f4f..d4cc6dcc99 100644 --- a/src/finn/transformation/fpgadataflow/prepare_cppsim.py +++ b/src/finn/transformation/fpgadataflow/prepare_cppsim.py @@ -35,7 +35,7 @@ from qonnx.util.basic import get_num_default_workers from finn.util.basic import make_build_dir -from finn.util.fpgadataflow import is_fpgadataflow_node, is_hls_node +from finn.util.fpgadataflow import is_hls_node def _codegen_single_node(node, model): @@ -79,7 +79,7 @@ def __init__(self, num_workers=None): self._num_workers = mp.cpu_count() def prepareCppSim_node(self, node): - if is_fpgadataflow_node(node) and is_hls_node(node): + if is_hls_node(node): _codegen_single_node(node, self.model) return (node, False) diff --git a/src/finn/transformation/fpgadataflow/prepare_ip.py b/src/finn/transformation/fpgadataflow/prepare_ip.py index 5461bbd77c..a74e0f7afc 100644 --- a/src/finn/transformation/fpgadataflow/prepare_ip.py +++ b/src/finn/transformation/fpgadataflow/prepare_ip.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2020, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -32,7 +33,7 @@ from qonnx.transformation.base import Transformation from finn.util.basic import make_build_dir -from finn.util.fpgadataflow import is_fpgadataflow_node +from finn.util.fpgadataflow import is_hls_node, is_rtl_node def _codegen_single_node(node, model, fpgapart, clk): @@ -72,8 +73,15 @@ class PrepareIP(Transformation): will be skipped. Outcome if succesful: Node attribute "code_gen_dir_ipgen" contains path to folder - that contains generated C++ code that can be used to generate a Vivado IP block. - The subsequent transformation is HLSSynthIP""" + that contains: + + * For HLS layers: generated C++ code that can be used to generate a Vivado IP block. + The necessary subsequent transformation is HLSSynthIP. + + * For RTL layers: filled template verilog files that can be used to instantiate as + module during IP stitching. + + """ def __init__(self, fpgapart, clk): super().__init__() @@ -82,6 +90,6 @@ def __init__(self, fpgapart, clk): def apply(self, model): for node in model.graph.node: - if is_fpgadataflow_node(node) is True: + if is_hls_node(node) or is_rtl_node(node): _codegen_single_node(node, model, self.fpgapart, self.clk) return (model, False) diff --git a/src/finn/transformation/fpgadataflow/prepare_rtlsim.py b/src/finn/transformation/fpgadataflow/prepare_rtlsim.py index 8ba7cfd965..b8f45deb1d 100644 --- a/src/finn/transformation/fpgadataflow/prepare_rtlsim.py +++ b/src/finn/transformation/fpgadataflow/prepare_rtlsim.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2020, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -32,7 +33,7 @@ from finn.transformation.fpgadataflow.replace_verilog_relpaths import ( ReplaceVerilogRelPaths, ) -from finn.util.fpgadataflow import is_fpgadataflow_node +from finn.util.fpgadataflow import is_hls_node, is_rtl_node try: from pyverilator import PyVerilator @@ -63,7 +64,7 @@ def apply(self, model): def applyNodeLocal(self, node): op_type = node.op_type - if is_fpgadataflow_node(node) is True: + if is_hls_node(node) or is_rtl_node(node): try: # lookup op_type in registry of CustomOps inst = registry.getCustomOp(node) diff --git a/src/finn/transformation/fpgadataflow/replace_verilog_relpaths.py b/src/finn/transformation/fpgadataflow/replace_verilog_relpaths.py index 4e7970caa0..de13166e73 100644 --- a/src/finn/transformation/fpgadataflow/replace_verilog_relpaths.py +++ b/src/finn/transformation/fpgadataflow/replace_verilog_relpaths.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2020, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -30,7 +31,7 @@ import qonnx.custom_op.registry as registry from qonnx.transformation.base import Transformation -from finn.util.fpgadataflow import is_fpgadataflow_node +from finn.util.fpgadataflow import is_hls_node, is_rtl_node class ReplaceVerilogRelPaths(Transformation): @@ -41,7 +42,7 @@ def __init__(self): def apply(self, model): for node in model.graph.node: - if is_fpgadataflow_node(node) is True: + if is_hls_node(node) or is_rtl_node(node): try: # lookup op_type in registry of CustomOps inst = registry.getCustomOp(node) diff --git a/src/finn/transformation/fpgadataflow/set_exec_mode.py b/src/finn/transformation/fpgadataflow/set_exec_mode.py index 7df4451a22..1b5a510d2f 100644 --- a/src/finn/transformation/fpgadataflow/set_exec_mode.py +++ b/src/finn/transformation/fpgadataflow/set_exec_mode.py @@ -30,39 +30,44 @@ import qonnx.custom_op.registry as registry from qonnx.transformation.base import Transformation -from finn.util.fpgadataflow import is_fpgadataflow_node, is_rtl_node +from finn.util.fpgadataflow import is_hls_node, is_rtl_node class SetExecMode(Transformation): """Set attribute exec_mode in all fpgadataflow nodes to specify which kind of execution should be used ("cppsim" or "rtlsim"). Note that RTL components do not support cppsim. - If cppsim is selected, only HLS components will be set for cppsim, - RTL components default in this case to rtlsim execution mode.""" + For now, only a model consisting of 100% of HLS layers can be executed + using cppsim.""" def __init__(self, mode): super().__init__() self.mode = mode def apply(self, model): - for node in model.graph.node: - op_type = node.op_type - if is_fpgadataflow_node(node): - if self.mode == "cppsim" and is_rtl_node(node): - mode = "rtlsim" - else: - mode = self.mode - try: - # lookup op_type in registry of CustomOps - inst = registry.getCustomOp(node) - # set sim_mode accordingly to argument mode - inst.set_nodeattr("exec_mode", mode) - # ensure that sim_mode is now set - assert ( - inst.get_nodeattr("exec_mode") != "" - ), """Transformation - was not successful. Node attribute "exec_mode" is not set""" - except KeyError: - # exception if op_type is not supported - raise Exception("Custom op_type %s is currently not supported." % op_type) + mode = self.mode + # if "cppsim" selected, check if model does not contain RTL layers + if mode == "cppsim" and any(is_rtl_node(node) for node in model.graph.node): + raise Exception( + """Model contains RTL layers, + cppsim can only be used on models consisting of HLS layers + and non fpgadataflow nodes.""" + ) + else: + for node in model.graph.node: + op_type = node.op_type + if is_hls_node(node) or is_rtl_node(node): + try: + # lookup op_type in registry of CustomOps + inst = registry.getCustomOp(node) + # set sim_mode accordingly to argument mode + inst.set_nodeattr("exec_mode", mode) + # ensure that sim_mode is now set + assert ( + inst.get_nodeattr("exec_mode") != "" + ), """Transformation + was not successful. Node attribute "exec_mode" is not set""" + except KeyError: + # exception if op_type is not supported + raise Exception("Custom op_type %s is currently not supported." % op_type) return (model, False) diff --git a/src/finn/transformation/fpgadataflow/set_fifo_depths.py b/src/finn/transformation/fpgadataflow/set_fifo_depths.py index 1e25670a71..d81f1fe247 100644 --- a/src/finn/transformation/fpgadataflow/set_fifo_depths.py +++ b/src/finn/transformation/fpgadataflow/set_fifo_depths.py @@ -49,7 +49,7 @@ from finn.transformation.fpgadataflow.insert_fifo import InsertFIFO from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers -from finn.util.fpgadataflow import is_fpgadataflow_node +from finn.util.fpgadataflow import is_hls_node, is_rtl_node from finn.util.pyverilator import pyverilate_stitched_ip, verilator_fifosim @@ -265,7 +265,9 @@ def apply(self, model): modified_fc_nodes = [] for node in model.graph.node: # verify assumptions - assert is_fpgadataflow_node(node), "Found non-fpgadataflow node: " + str(node) + assert is_hls_node(node) or is_rtl_node(node), "Found non-fpgadataflow node: " + str( + node + ) op_type = node.op_type assert not op_type.startswith("StreamingFIFO"), "Found existing StreamingFIFO node" node = getCustomOp(node) diff --git a/src/finn/transformation/fpgadataflow/set_folding.py b/src/finn/transformation/fpgadataflow/set_folding.py index 28358fdacc..bff64d3885 100644 --- a/src/finn/transformation/fpgadataflow/set_folding.py +++ b/src/finn/transformation/fpgadataflow/set_folding.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020, Xilinx +# Copyright (C) 2020, Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -34,7 +35,7 @@ from finn.analysis.fpgadataflow.dataflow_performance import dataflow_performance from finn.transformation.fpgadataflow.annotate_cycles import AnnotateCycles -from finn.util.fpgadataflow import is_fpgadataflow_node +from finn.util.fpgadataflow import is_hls_node, is_rtl_node def divisors(num): @@ -120,7 +121,7 @@ def apply(self, model): # as explained in the SetFolding docstring depthwise_op_exceptions = ["VectorVectorActivation_hls", "Pool_hls"] for node in graph.node: - if not is_fpgadataflow_node(node): + if not (is_hls_node(node) or is_rtl_node(node)): continue op_type = node.op_type node_inst = getCustomOp(node) diff --git a/src/finn/transformation/move_reshape.py b/src/finn/transformation/move_reshape.py index a13ecee80f..2e6639c5c6 100644 --- a/src/finn/transformation/move_reshape.py +++ b/src/finn/transformation/move_reshape.py @@ -1,22 +1,9 @@ import warnings from qonnx.custom_op.registry import getCustomOp from qonnx.transformation.base import Transformation -from qonnx.util.basic import get_by_name, is_finn_op +from qonnx.util.basic import get_by_name - -def _is_fpgadataflow_node(node): - if node is not None: - if is_finn_op(node.domain): - n_backend = get_by_name(node.attribute, "backend") - if n_backend is None: - return False - backend_value = n_backend.s.decode("UTF-8") - if backend_value == "fpgadataflow": - return True - else: - return False - else: - return False +from finn.util.fpgadataflow import is_fpgadataflow_node class RemoveCNVtoFCFlatten(Transformation): @@ -34,10 +21,10 @@ def apply(self, model): oshape = model.get_tensor_shape(n.output[0]) if len(oshape) == 2 and ishape[0] == oshape[0]: producer = model.find_producer(n.input[0]) - if _is_fpgadataflow_node(producer) is True: + if is_fpgadataflow_node(producer): # standalone flatten, remove consumer = model.find_consumer(n.output[0]) - if _is_fpgadataflow_node(consumer) is True: + if is_fpgadataflow_node(consumer): graph_modified = True consumer.input[0] = n.input[0] graph.node.remove(n) @@ -48,7 +35,7 @@ def apply(self, model): perms = list(get_by_name(transp_node.attribute, "perm").ints) if perms == [0, 3, 1, 2]: producer = model.find_producer(transp_node.input[0]) - if _is_fpgadataflow_node(producer) is True: + if is_fpgadataflow_node(producer): consumer = model.find_consumer(n.output[0]) if consumer.op_type.startswith("MVAU"): fc_inst = getCustomOp(consumer) From 34716ba5fd02704bcf1a6bb3e0b4ad93f3d508c0 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Thu, 22 Feb 2024 10:37:31 +0000 Subject: [PATCH 511/665] [tests] only check hls model analysis on hls modules --- tests/fpgadataflow/test_fpgadataflow_thresholding.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_thresholding.py b/tests/fpgadataflow/test_fpgadataflow_thresholding.py index f1be5f89a7..e1e91038ef 100644 --- a/tests/fpgadataflow/test_fpgadataflow_thresholding.py +++ b/tests/fpgadataflow/test_fpgadataflow_thresholding.py @@ -227,8 +227,9 @@ def test_fpgadataflow_thresholding(impl_style,idt, act, nf, ich, exec_mode, mem_ assert (y_produced == y_expected).all() if exec_mode == "rtlsim": - hls_synt_res_est = model.analysis(hls_synth_res_estimation) - assert model.graph.node[0].name in hls_synt_res_est + if impl_style == "hls": + hls_synt_res_est = model.analysis(hls_synth_res_estimation) + assert model.graph.node[0].name in hls_synt_res_est node = model.get_nodes_by_op_type(model.graph.node[0].op_type)[0] inst = getCustomOp(node) cycles_rtlsim = inst.get_nodeattr("cycles_rtlsim") From 2bf40ca4f1da4ad5cd7a068e0d739b7ba691bf64 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Thu, 22 Feb 2024 10:39:00 +0000 Subject: [PATCH 512/665] [tests] increase folding config for threshold tests --- .../test_fpgadataflow_thresholding.py | 22 +++++++++---------- 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_thresholding.py b/tests/fpgadataflow/test_fpgadataflow_thresholding.py index e1e91038ef..49061e4c9e 100644 --- a/tests/fpgadataflow/test_fpgadataflow_thresholding.py +++ b/tests/fpgadataflow/test_fpgadataflow_thresholding.py @@ -239,11 +239,10 @@ def test_fpgadataflow_thresholding(impl_style,idt, act, nf, ich, exec_mode, mem_ assert exp_cycles != 0 @pytest.mark.parametrize("impl_style", ["rtl", "hls"]) -@pytest.mark.parametrize("cf", [2]) -@pytest.mark.parametrize("ch", [6]) +@pytest.mark.parametrize("cfg", [(1,1), (6,2), (6,3), (8,2), (8,4)]) @pytest.mark.fpgadataflow @pytest.mark.vivado -def test_runtime_thresholds_read(impl_style,cf,ch): +def test_runtime_thresholds_read(impl_style,cfg): """ Read back threshold weights during runtime 1. Create random initial weights T @@ -251,13 +250,12 @@ def test_runtime_thresholds_read(impl_style,cf,ch): 3. Read back weights via AXI 4. Compare with initial weights T """ + ch = cfg[0] + pe = cfg[1] n_inp_vecs = [1, 2, 2] mem_mode = "decoupled" act = DataType["INT4"] idt = DataType["INT16"] - pe = ch // cf - assert ch % pe == 0 - odt = act n_steps = act.get_num_possible_values() - 1 np.random.seed(2) @@ -330,12 +328,11 @@ def read_weights(sim): # Validate the output is as expected assert (y == expected).all() -@pytest.mark.parametrize("impl_style", ["rtl", "hls"]) -@pytest.mark.parametrize("cf", [8]) -@pytest.mark.parametrize("ch", [16]) +@pytest.mark.parametrize("impl_style", ["hls", "rtl"]) +@pytest.mark.parametrize("cfg", [(1,1), (6,2), (6,3), (8,2), (8,4)]) @pytest.mark.fpgadataflow @pytest.mark.vivado -def test_runtime_thresholds_write(impl_style,cf,ch): +def test_runtime_thresholds_write(impl_style,cfg): """ Write threshold weights during runtime 1. Create random initial weights T_init @@ -346,12 +343,13 @@ def test_runtime_thresholds_write(impl_style,cf,ch): 6. Compare T_write and T_read 7. Validate outputs with expected vectors """ + ch = cfg[0] + pe = cfg[1] + n_inp_vecs = [1, 2, 2] mem_mode = "decoupled" act = DataType["INT4"] idt = DataType["INT16"] - pe = ch // cf - assert ch % pe == 0 odt = act n_steps = act.get_num_possible_values() - 1 From c09005b37529c78489fec057a9480297151ca873 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Thu, 22 Feb 2024 10:39:34 +0000 Subject: [PATCH 513/665] [tests] rename threshold weight files for distributed testing --- .../test_fpgadataflow_thresholding.py | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_thresholding.py b/tests/fpgadataflow/test_fpgadataflow_thresholding.py index 49061e4c9e..dfd14268e5 100644 --- a/tests/fpgadataflow/test_fpgadataflow_thresholding.py +++ b/tests/fpgadataflow/test_fpgadataflow_thresholding.py @@ -276,10 +276,12 @@ def test_runtime_thresholds_read(impl_style,cfg): op_inst = getCustomOp(model.graph.node[0]) op_inst.set_nodeattr("runtime_writeable_weights", 1) - op_inst.make_weight_file(T, "decoupled_runtime", "old_weights.dat") - with open("old_weights.dat", "r") as f: + + dat_fname = f"old_weights_{cfg}.dat" + op_inst.make_weight_file(T, "decoupled_runtime", dat_fname) + with open(dat_fname, "r") as f: old_weight_stream = f.read().strip() - os.remove("old_weights.dat") + os.remove(dat_fname) old_weight_stream = map(lambda x: int(x, 16), old_weight_stream.split("\n")) old_weight_stream = list(old_weight_stream) # need to create stitched IP for runtime weight testing @@ -378,10 +380,11 @@ def test_runtime_thresholds_write(impl_style,cfg): # provide non-decreasing thresholds T_write = np.sort(T_write, axis=1) - op_inst.make_weight_file(T_write, "decoupled_runtime", "T_write.dat") - with open("T_write.dat", "r") as f: + dat_fname = f"T_write_{cfg}.dat" # distinguish fname per paramter for distributed testing + op_inst.make_weight_file(T_write, "decoupled_runtime", dat_fname) + with open(dat_fname, "r") as f: T_write_stream = f.read().strip() - os.remove("T_write.dat") + os.remove(dat_fname) T_write_stream = map(lambda x: int(x, 16), T_write_stream.split("\n")) T_write_stream = list(T_write_stream) @@ -402,8 +405,6 @@ def test_runtime_thresholds_write(impl_style,cfg): in_tensor = gen_finn_dt_tensor(idt, tuple(n_inp_vecs + [ch])) in_tensor = np.tile(in_tensor, (2, 1, 1, 1)) - # trace_file = "trace_wr_01.vcd" - # model.set_metadata_prop("rtlsim_trace",trace_file) exec_ctx_write = {"inp": in_tensor} def write_weights(sim): addr = 0 From 0f03e37668f9ff0cc0024852f872b8918fee6d6b Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Thu, 22 Feb 2024 10:40:56 +0000 Subject: [PATCH 514/665] [CustomOp] threshold stage loop starts from 0 --- src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py index 26cba23620..04a1815a32 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py @@ -773,7 +773,7 @@ def make_weight_file(self, weights, weight_file_mode, weight_file_name): chan_ind = 0 cf = ch//pe for fold in range(cf): - for c in range(2**pe.bit_length()): + for c in range(2**(pe-1).bit_length()): if (c==0 or c%pe != 0) and c < pe: for w in weight_padded[chan_ind]: w_packed = pack_innermost_dim_as_hex_string( From c4e57da733bff97d63daa8692fc08a05f2d1ba59 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Thu, 22 Feb 2024 11:30:16 +0000 Subject: [PATCH 515/665] [tests] convert to hw test for thresholding layers --- tests/fpgadataflow/test_convert_to_hw_thresholding.py | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/tests/fpgadataflow/test_convert_to_hw_thresholding.py b/tests/fpgadataflow/test_convert_to_hw_thresholding.py index 685c955f4e..3f0487f9f7 100755 --- a/tests/fpgadataflow/test_convert_to_hw_thresholding.py +++ b/tests/fpgadataflow/test_convert_to_hw_thresholding.py @@ -35,6 +35,7 @@ from qonnx.transformation.general import GiveUniqueNodeNames from qonnx.transformation.infer_datatypes import InferDataTypes from qonnx.transformation.infer_shapes import InferShapes +from qonnx.custom_op.registry import getCustomOp from finn.transformation.fpgadataflow.convert_to_hw_layers import InferThresholdingLayer from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers @@ -115,7 +116,7 @@ def make_single_multithresholding_modelwrapper( @pytest.mark.parametrize("input_data_type", [DataType["INT16"], DataType["UINT16"]]) @pytest.mark.parametrize("fold", [-1, 1, 2, 4, 6]) @pytest.mark.parametrize("num_input_channels", [16]) -@pytest.mark.parametrize("impl_style", ["hls"]) # TODO: add rtl later +@pytest.mark.parametrize("impl_style", ["hls", "rtl"]) @pytest.mark.fpgadataflow @pytest.mark.vivado def test_convert_multithreshold_to_hardware( @@ -162,7 +163,10 @@ def test_convert_multithreshold_to_hardware( ) model = model.transform(InferThresholdingLayer()) + + node = model.get_nodes_by_op_type(model.graph.node[0].op_type)[0] + inst = getCustomOp(node) + inst.set_nodeattr("preferred_impl_style", impl_style) model = model.transform(SpecializeLayers()) model = model.transform(InferShapes()) - # TODO functional verification assert model.graph.node[0].op_type == "Thresholding_" + str(impl_style) From 666356a862e922f913264f351495ce2d5d6f8400 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Fri, 23 Feb 2024 11:40:41 +0000 Subject: [PATCH 516/665] [CustomOp] Update copyright headers for thresholding --- finn-rtllib/thresholding/hdl/axilite_if.v | 59 ++++++++++--------- finn-rtllib/thresholding/hdl/thresholding.sv | 2 +- .../thresholding/hdl/thresholding_axi.sv | 2 +- .../hdl/thresholding_template_wrapper.v | 39 ++++++------ finn-rtllib/thresholding/sim/thresh_gen.sv | 30 ++++++++++ finn-rtllib/thresholding/sim/thresholding.tcl | 17 ------ .../thresholding/sim/thresholding_axi_tb.sv | 2 +- .../thresholding/sim/thresholding_tb.sv | 2 +- .../fpgadataflow/rtl/thresholding_rtl.py | 12 +--- src/finn/util/basic.py | 4 +- 10 files changed, 87 insertions(+), 82 deletions(-) delete mode 100644 finn-rtllib/thresholding/sim/thresholding.tcl diff --git a/finn-rtllib/thresholding/hdl/axilite_if.v b/finn-rtllib/thresholding/hdl/axilite_if.v index bdd4de288e..2aeff770d2 100644 --- a/finn-rtllib/thresholding/hdl/axilite_if.v +++ b/finn-rtllib/thresholding/hdl/axilite_if.v @@ -1,32 +1,33 @@ -/* - Copyright (c) 2020, Xilinx - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - * Neither the name of FINN nor the names of its - contributors may be used to endorse or promote products derived from - this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ +/****************************************************************************** + * Copyright (C) 2024, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *****************************************************************************/ module axi4lite_if #( diff --git a/finn-rtllib/thresholding/hdl/thresholding.sv b/finn-rtllib/thresholding/hdl/thresholding.sv index 4c83c8e9db..2e4d419746 100644 --- a/finn-rtllib/thresholding/hdl/thresholding.sv +++ b/finn-rtllib/thresholding/hdl/thresholding.sv @@ -1,5 +1,5 @@ /****************************************************************************** - * Copyright (C) 2022, Advanced Micro Devices, Inc. + * Copyright (C) 2024, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/finn-rtllib/thresholding/hdl/thresholding_axi.sv b/finn-rtllib/thresholding/hdl/thresholding_axi.sv index 1f235b9486..5c7182b214 100644 --- a/finn-rtllib/thresholding/hdl/thresholding_axi.sv +++ b/finn-rtllib/thresholding/hdl/thresholding_axi.sv @@ -1,5 +1,5 @@ /****************************************************************************** - * Copyright (C) 2022, Advanced Micro Devices, Inc. + * Copyright (C) 2024, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/finn-rtllib/thresholding/hdl/thresholding_template_wrapper.v b/finn-rtllib/thresholding/hdl/thresholding_template_wrapper.v index ef76a23cbc..f35db156f6 100644 --- a/finn-rtllib/thresholding/hdl/thresholding_template_wrapper.v +++ b/finn-rtllib/thresholding/hdl/thresholding_template_wrapper.v @@ -1,31 +1,32 @@ -/** - * Copyright (c) 2023, Xilinx +/****************************************************************************** + * Copyright (C) 2024, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * - * * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. * - * * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * * Neither the name of FINN nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * @author Thomas B. Preußer * @brief Verilog wrapper for IP packaging. diff --git a/finn-rtllib/thresholding/sim/thresh_gen.sv b/finn-rtllib/thresholding/sim/thresh_gen.sv index 713723aafa..ae30503f8f 100644 --- a/finn-rtllib/thresholding/sim/thresh_gen.sv +++ b/finn-rtllib/thresholding/sim/thresh_gen.sv @@ -1,3 +1,33 @@ +/****************************************************************************** + * Copyright (C) 2024, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *****************************************************************************/ module thresh_gen; localparam int unsigned K = 9; localparam int unsigned N = 4; diff --git a/finn-rtllib/thresholding/sim/thresholding.tcl b/finn-rtllib/thresholding/sim/thresholding.tcl deleted file mode 100644 index 82dc59deb1..0000000000 --- a/finn-rtllib/thresholding/sim/thresholding.tcl +++ /dev/null @@ -1,17 +0,0 @@ -create_project -force thresholding thresholding.vivado -part xcvc1902-vsva2197-2MP-e-S -set_property board_part xilinx.com:vck190:part0:2.2 [current_project] - -read_verilog hdl/axilite_if.v -read_verilog -sv { hdl/thresholding.sv hdl/thresholding_axi.sv } - -set simset [current_fileset -simset] -set_property -name xsim.simulate.log_all_signals -value true -objects $simset -set_property -name xsim.simulate.runtime -value all -objects $simset -add_files -fileset $simset { sim/thresholding_tb.sv sim/thresholding_axi_tb.sv } - -foreach top { thresholding_tb thresholding_axi_tb } { - set_property top $top $simset - - launch_simulation - close_sim -} diff --git a/finn-rtllib/thresholding/sim/thresholding_axi_tb.sv b/finn-rtllib/thresholding/sim/thresholding_axi_tb.sv index 918f539d15..429fb7776f 100644 --- a/finn-rtllib/thresholding/sim/thresholding_axi_tb.sv +++ b/finn-rtllib/thresholding/sim/thresholding_axi_tb.sv @@ -1,5 +1,5 @@ /****************************************************************************** - * Copyright (C) 2022, Advanced Micro Devices, Inc. + * Copyright (C) 2024, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/finn-rtllib/thresholding/sim/thresholding_tb.sv b/finn-rtllib/thresholding/sim/thresholding_tb.sv index 3f4ca61a85..1564f28f0d 100644 --- a/finn-rtllib/thresholding/sim/thresholding_tb.sv +++ b/finn-rtllib/thresholding/sim/thresholding_tb.sv @@ -1,5 +1,5 @@ /****************************************************************************** - * Copyright (C) 2022, Advanced Micro Devices, Inc. + * Copyright (C) 2024, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py index 04a1815a32..02133dff39 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py @@ -1,4 +1,4 @@ -# Copyright (C) 2022, Advanced Micro Devices, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -60,16 +60,6 @@ except ModuleNotFoundError: PyVerilator = None -"""@package Thresholding_rtl -- ONNX i/o tensor shape assumptions for Thresholding: -- input 0 is the input tensor, shape (..., NumChannels) -- input 1 is the threshold tensor, shape (NumChannels, n_thres) -- output 0 is the output tensor, shape (..., NumChannels) - same as input -- the '...' here can be any shape (representing groups of vectors) - -This module creates an RTL IP, HLS is not supported. See 'thresholding_batch' -for a HLS equivalent. -""" class Thresholding_rtl(Thresholding, RTLBackend): """Class that corresponds to finn-rtllib 'thresholding' function.""" diff --git a/src/finn/util/basic.py b/src/finn/util/basic.py index 0a6c0b39c9..077e45200d 100644 --- a/src/finn/util/basic.py +++ b/src/finn/util/basic.py @@ -1,4 +1,4 @@ -# Copyright (c) 2020 Xilinx, Inc. +# Copyright (C) 2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -11,7 +11,7 @@ # this list of conditions and the following disclaimer in the documentation # and/or other materials provided with the distribution. # -# * Neither the name of Xilinx nor the names of its +# * Neither the name of FINN nor the names of its # contributors may be used to endorse or promote products derived from # this software without specific prior written permission. # From 89378115f6000439e7fd934fa0455d749420a94d Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Fri, 23 Feb 2024 11:49:15 +0000 Subject: [PATCH 517/665] [CustomOp] Move calc_tmem to abstraction layer Signed-off-by: aziz bahri --- src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py | 6 ------ src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py | 6 ------ src/finn/custom_op/fpgadataflow/thresholding.py | 6 ++++++ 3 files changed, 6 insertions(+), 12 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py b/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py index 16dee92e8a..07fe4296e3 100644 --- a/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py @@ -67,12 +67,6 @@ def get_nodeattr_types(self): my_attrs.update(HLSBackend.get_nodeattr_types(self)) return my_attrs - def calc_tmem(self): - """Calculates and returns TMEM.""" - mh = self.get_nodeattr("NumChannels") - pe = self.get_nodeattr("PE") - return mh // pe - def bram_estimation(self): """Calculates BRAM cost if resource set to BRAM""" style = self.get_nodeattr("ram_style") diff --git a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py index 02133dff39..cdca8cc373 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py @@ -120,12 +120,6 @@ def get_memory_estimate(self): res_dict[res_type] = res_dict.get(res_type, 0) + pe * res_count return res_dict - def calc_tmem(self): - """Calculates and returns TMEM.""" - num_channels = self.get_nodeattr("NumChannels") - pe = self.get_nodeattr("PE") - return num_channels // pe - def infer_node_datatype(self, model): """Used for FINN DataType inference: set the output tensors' datatypes accordingly for this node""" diff --git a/src/finn/custom_op/fpgadataflow/thresholding.py b/src/finn/custom_op/fpgadataflow/thresholding.py index 945ec16cf0..73c5ecf997 100644 --- a/src/finn/custom_op/fpgadataflow/thresholding.py +++ b/src/finn/custom_op/fpgadataflow/thresholding.py @@ -205,3 +205,9 @@ def execute_node(self, context, graph): # signed offset y += act.min() context[node.output[0]] = y + + def calc_tmem(self): + """Calculates and returns TMEM.""" + num_channels = self.get_nodeattr("NumChannels") + pe = self.get_nodeattr("PE") + return num_channels // pe \ No newline at end of file From ce14ea228920c75c3b7820d6e660495c790ef099 Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 23 Feb 2024 11:52:36 +0000 Subject: [PATCH 518/665] [RTL layers] Default to parent execute node function for cppsim --- src/finn/custom_op/fpgadataflow/hwcustomop.py | 16 +-- .../rtl/convolutioninputgenerator_rtl.py | 111 ++++++++++-------- .../fpgadataflow/rtl/fmpadding_rtl.py | 87 ++++++++------ .../rtl/streamingdatawidthconverter_rtl.py | 86 +++++++------- .../fpgadataflow/set_exec_mode.py | 47 +++----- .../test_fpgadataflow_convinputgenerator.py | 9 +- tests/fpgadataflow/test_fpgadataflow_dwc.py | 14 +-- .../test_fpgadataflow_fmpadding.py | 2 - 8 files changed, 189 insertions(+), 183 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/hwcustomop.py b/src/finn/custom_op/fpgadataflow/hwcustomop.py index bf89bcc0b4..854587afc4 100644 --- a/src/finn/custom_op/fpgadataflow/hwcustomop.py +++ b/src/finn/custom_op/fpgadataflow/hwcustomop.py @@ -170,27 +170,27 @@ def uram_efficiency_estimation(self): def bram_estimation(self): """Function for BRAM resource estimation, is member function of - HLSCustomOp class but has to be filled by every node""" + HWCustomOp class but has to be filled by every node""" return 0 def uram_estimation(self): """Function for UltraRAM resource estimation, is member function of - HLSCustomOp class but has to be filled by every node""" + HWCustomOp class but has to be filled by every node""" return 0 def lut_estimation(self): """Function for LUT resource estimation, is member function of - HLSCustomOp class but has to be filled by every node""" + HWCustomOp class but has to be filled by every node""" return 0 def dsp_estimation(self): """Function for DSP resource estimation, is member function of - HLSCustomOp class but has to be filled by every node""" + HWCustomOp class but has to be filled by every node""" return 0 def get_exp_cycles(self): """Function for estimation of expected cycles for set folding, - is member function of HLSCustomOp class but has to be filled + is member function of HWCustomOp class but has to be filled by every node""" return 0 @@ -316,14 +316,14 @@ def rtlsim_multi_io(self, sim, io_dict): def generate_params(self, model, path): """Function to generate parameters (i.e. weights and thresholds), - is member function of HLSCustomOp class but has to be filled - by every node.""" + is member function of HWCustomOp class but has to be filled + by every node that needs to generate parameters.""" pass @abstractmethod def get_number_output_values(self): """Function to get the number of expected output values, - is member function of HLSCustomOp class but has to be filled + is member function of HWCustomOp class but has to be filled by every node.""" pass diff --git a/src/finn/custom_op/fpgadataflow/rtl/convolutioninputgenerator_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/convolutioninputgenerator_rtl.py index 6f4bafd73a..aebbc6c646 100755 --- a/src/finn/custom_op/fpgadataflow/rtl/convolutioninputgenerator_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/convolutioninputgenerator_rtl.py @@ -30,6 +30,7 @@ import numpy as np import os import shutil +import warnings from qonnx.core.datatype import DataType from qonnx.custom_op.general import im2col from qonnx.custom_op.general.im2col import compute_conv_output_dim @@ -285,15 +286,68 @@ def uram_estimation(self): def execute_node(self, context, graph): mode = self.get_nodeattr("exec_mode") - node = self.onnx_node - exp_ishape = self.get_normal_input_shape() - exp_oshape = self.get_normal_output_shape() - folded_ishape = self.get_folded_input_shape() + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") if mode == "cppsim": - raise Exception("cppsim not possible for RTL SWG, please set exec_mode to rtlsim") + warnings.warn( + """RTL components cannot be executed with cppsim. + By default the execution of the HW abstraction parent will be used.""" + ) + ConvolutionInputGenerator.execute_node(self, context, graph) elif mode == "rtlsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + node = self.onnx_node + exp_ishape = self.get_normal_input_shape() + exp_oshape = self.get_normal_output_shape() + folded_ishape = self.get_folded_input_shape() + + inp = context[node.input[0]] + assert str(inp.dtype) == "float32", "Input datatype is not float32" + assert ( + inp.shape == exp_ishape + ), """Input shape doesn't match expected shape (1, ifm_dim, ifm_dim, ifm_ch).""" + if self.get_input_datatype() == DataType["BIPOLAR"]: + # store bipolar activations as binary + inp = (inp + 1) / 2 + export_idt = DataType["BINARY"] + else: + export_idt = self.get_input_datatype() + + # reshape input into folded form + inp = inp.reshape(folded_ishape) + # make copy before saving array + reshaped_input = inp.copy() + np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input) + + sim = self.get_rtlsim() + nbits = self.get_instream_width() + rtlsim_inp = npy_to_rtlsim_input( + "{}/input_0.npy".format(code_gen_dir), export_idt, nbits + ) + super().reset_rtlsim(sim) + super().toggle_clk(sim) + rtlsim_output = self.rtlsim(sim, rtlsim_inp) + odt = export_idt + target_bits = odt.bitwidth() + packed_bits = self.get_outstream_width() + out_npy_path = "{}/output.npy".format(code_gen_dir) + out_shape = self.get_folded_output_shape() + rtlsim_output_to_npy( + rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits + ) + # load and reshape output + output = np.load(out_npy_path) + output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) + context[node.output[0]] = output + + # binary -> bipolar if needed + if self.get_output_datatype() == DataType["BIPOLAR"]: + out = context[node.output[0]] + out = 2 * out - 1 + context[node.output[0]] = out + assert ( + context[node.output[0]].shape == exp_oshape + ), """Output + shape doesn't match expected shape (1, ofm_dim_h, ofm_dim_w, k_h*k_w*ifm_ch).""" else: raise Exception( """Invalid value for attribute exec_mode! Is currently set to: {} @@ -302,51 +356,6 @@ def execute_node(self, context, graph): ) ) - inp = context[node.input[0]] - assert str(inp.dtype) == "float32", "Input datatype is not float32" - assert ( - inp.shape == exp_ishape - ), """Input shape doesn't match expected shape (1, ifm_dim, ifm_dim, ifm_ch).""" - if self.get_input_datatype() == DataType["BIPOLAR"]: - # store bipolar activations as binary - inp = (inp + 1) / 2 - export_idt = DataType["BINARY"] - else: - export_idt = self.get_input_datatype() - - # reshape input into folded form - inp = inp.reshape(folded_ishape) - # make copy before saving array - reshaped_input = inp.copy() - np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input) - - sim = self.get_rtlsim() - nbits = self.get_instream_width() - rtlsim_inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) - super().reset_rtlsim(sim) - super().toggle_clk(sim) - rtlsim_output = self.rtlsim(sim, rtlsim_inp) - odt = export_idt - target_bits = odt.bitwidth() - packed_bits = self.get_outstream_width() - out_npy_path = "{}/output.npy".format(code_gen_dir) - out_shape = self.get_folded_output_shape() - rtlsim_output_to_npy(rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits) - # load and reshape output - output = np.load(out_npy_path) - output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) - context[node.output[0]] = output - - # binary -> bipolar if needed - if self.get_output_datatype() == DataType["BIPOLAR"]: - out = context[node.output[0]] - out = 2 * out - 1 - context[node.output[0]] = out - assert ( - context[node.output[0]].shape == exp_oshape - ), """Output - shape doesn't match expected shape (1, ofm_dim_h, ofm_dim_w, k_h*k_w*ifm_ch).""" - def prepare_codegen_default(self): """Fills code generation dict for the default implementation style by computing the incremental addressing scheme for the circular buffer.""" diff --git a/src/finn/custom_op/fpgadataflow/rtl/fmpadding_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/fmpadding_rtl.py index b8a1505018..713fd81da6 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/fmpadding_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/fmpadding_rtl.py @@ -30,6 +30,7 @@ import numpy as np import os import shutil +import warnings from qonnx.util.basic import roundup_to_integer_multiple from finn.custom_op.fpgadataflow.fmpadding import FMPadding @@ -70,15 +71,56 @@ def get_verilog_top_module_intf_names(self): def execute_node(self, context, graph): mode = self.get_nodeattr("exec_mode") - node = self.onnx_node - exp_ishape = self.get_normal_input_shape() - exp_oshape = self.get_normal_output_shape() - folded_ishape = self.get_folded_input_shape() + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") if mode == "cppsim": - raise Exception("cppsim not possible for FMPadding_rtl, please set exec_mode to rtlsim") + warnings.warn( + """RTL components cannot be executed with cppsim. + By default the execution of the HW abstraction parent will be used.""" + ) + FMPadding.execute_node(self, context, graph) elif mode == "rtlsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + node = self.onnx_node + exp_ishape = self.get_normal_input_shape() + exp_oshape = self.get_normal_output_shape() + folded_ishape = self.get_folded_input_shape() + inp = context[node.input[0]] + assert str(inp.dtype) == "float32", "Input datatype is not float32" + assert ( + inp.shape == exp_ishape + ), """Input shape doesn't + match expected shape (1, ImgDim_h, ImgDim_w, NumChannels).""" + export_idt = self.get_input_datatype() + + reshaped_input = inp.reshape(folded_ishape) + np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input) + + sim = self.get_rtlsim() + nbits = self.get_instream_width() + rtlsim_inp = npy_to_rtlsim_input( + "{}/input_0.npy".format(code_gen_dir), export_idt, nbits + ) + super().reset_rtlsim(sim) + super().toggle_clk(sim) + rtlsim_output = self.rtlsim(sim, rtlsim_inp) + odt = export_idt + target_bits = odt.bitwidth() + packed_bits = self.get_outstream_width() + out_npy_path = "{}/output.npy".format(code_gen_dir) + out_shape = self.get_folded_output_shape() + rtlsim_output_to_npy( + rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits + ) + # load and reshape output + output = np.load(out_npy_path) + output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) + context[node.output[0]] = output + + assert ( + context[node.output[0]].shape == exp_oshape + ), """Output shape doesn't match expected shape + (1, OutputDim_H, OutputDim_W, NumChannels).""" + else: raise Exception( """Invalid value for attribute exec_mode! Is currently set to: {} @@ -87,39 +129,6 @@ def execute_node(self, context, graph): ) ) - inp = context[node.input[0]] - assert str(inp.dtype) == "float32", "Input datatype is not float32" - assert ( - inp.shape == exp_ishape - ), """Input shape doesn't - match expected shape (1, ImgDim_h, ImgDim_w, NumChannels).""" - export_idt = self.get_input_datatype() - - reshaped_input = inp.reshape(folded_ishape) - np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input) - - sim = self.get_rtlsim() - nbits = self.get_instream_width() - rtlsim_inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) - super().reset_rtlsim(sim) - super().toggle_clk(sim) - rtlsim_output = self.rtlsim(sim, rtlsim_inp) - odt = export_idt - target_bits = odt.bitwidth() - packed_bits = self.get_outstream_width() - out_npy_path = "{}/output.npy".format(code_gen_dir) - out_shape = self.get_folded_output_shape() - rtlsim_output_to_npy(rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits) - # load and reshape output - output = np.load(out_npy_path) - output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) - context[node.output[0]] = output - - assert ( - context[node.output[0]].shape == exp_oshape - ), """Output shape doesn't match expected shape - (1, OutputDim_H, OutputDim_W, NumChannels).""" - def get_template_values(self, ifm_dims, pads, chans, simd, idt): dimY, dimX = ifm_dims padT, padL, padB, padR = pads diff --git a/src/finn/custom_op/fpgadataflow/rtl/streamingdatawidthconverter_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/streamingdatawidthconverter_rtl.py index 6fcfaa1db0..2b1ff019ac 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/streamingdatawidthconverter_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/streamingdatawidthconverter_rtl.py @@ -29,6 +29,7 @@ import numpy as np import os import shutil +import warnings from finn.custom_op.fpgadataflow.rtlbackend import RTLBackend from finn.custom_op.fpgadataflow.streamingdatawidthconverter import ( @@ -73,18 +74,55 @@ def check_divisible_iowidths(self): def execute_node(self, context, graph): mode = self.get_nodeattr("exec_mode") - node = self.onnx_node - exp_ishape = self.get_normal_input_shape() - exp_oshape = self.get_normal_output_shape() - folded_ishape = self.get_folded_input_shape() + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") if mode == "cppsim": - raise Exception( - """cppsim not possible for StreamingDataWidthConverter_rtl, - please set exec_mode to rtlsim""" + warnings.warn( + """RTL components cannot be executed with cppsim. + By default the execution of the HW abstraction parent will be used.""" ) + StreamingDataWidthConverter.execute_node(self, context, graph) elif mode == "rtlsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + node = self.onnx_node + exp_ishape = self.get_normal_input_shape() + exp_oshape = self.get_normal_output_shape() + folded_ishape = self.get_folded_input_shape() + + inp = context[node.input[0]] + assert str(inp.dtype) == "float32", "Input datatype is not float32" + assert inp.shape == tuple( + exp_ishape + ), """Input shape doesn't + match expected shape.""" + export_idt = self.get_input_datatype() + + reshaped_input = inp.reshape(folded_ishape) + np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input) + + sim = self.get_rtlsim() + nbits = self.get_instream_width() + rtlsim_inp = npy_to_rtlsim_input( + "{}/input_0.npy".format(code_gen_dir), export_idt, nbits + ) + super().reset_rtlsim(sim) + super().toggle_clk(sim) + rtlsim_output = self.rtlsim(sim, rtlsim_inp) + odt = export_idt + target_bits = odt.bitwidth() + packed_bits = self.get_outstream_width() + out_npy_path = "{}/output.npy".format(code_gen_dir) + out_shape = self.get_folded_output_shape() + rtlsim_output_to_npy( + rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits + ) + # load and reshape output + output = np.load(out_npy_path) + output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) + context[node.output[0]] = output + + assert context[node.output[0]].shape == tuple( + exp_oshape + ), """Output shape doesn't match expected shape.""" else: raise Exception( """Invalid value for attribute exec_mode! Is currently set to: {} @@ -93,38 +131,6 @@ def execute_node(self, context, graph): ) ) - inp = context[node.input[0]] - assert str(inp.dtype) == "float32", "Input datatype is not float32" - assert inp.shape == tuple( - exp_ishape - ), """Input shape doesn't - match expected shape.""" - export_idt = self.get_input_datatype() - - reshaped_input = inp.reshape(folded_ishape) - np.save(os.path.join(code_gen_dir, "input_0.npy"), reshaped_input) - - sim = self.get_rtlsim() - nbits = self.get_instream_width() - rtlsim_inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) - super().reset_rtlsim(sim) - super().toggle_clk(sim) - rtlsim_output = self.rtlsim(sim, rtlsim_inp) - odt = export_idt - target_bits = odt.bitwidth() - packed_bits = self.get_outstream_width() - out_npy_path = "{}/output.npy".format(code_gen_dir) - out_shape = self.get_folded_output_shape() - rtlsim_output_to_npy(rtlsim_output, out_npy_path, odt, out_shape, packed_bits, target_bits) - # load and reshape output - output = np.load(out_npy_path) - output = np.asarray([output], dtype=np.float32).reshape(*exp_oshape) - context[node.output[0]] = output - - assert context[node.output[0]].shape == tuple( - exp_oshape - ), """Output shape doesn't match expected shape.""" - def get_template_values(self): topname = self.get_verilog_top_module_name() ibits = self.get_instream_width() diff --git a/src/finn/transformation/fpgadataflow/set_exec_mode.py b/src/finn/transformation/fpgadataflow/set_exec_mode.py index 1b5a510d2f..405ddb0c42 100644 --- a/src/finn/transformation/fpgadataflow/set_exec_mode.py +++ b/src/finn/transformation/fpgadataflow/set_exec_mode.py @@ -36,38 +36,29 @@ class SetExecMode(Transformation): """Set attribute exec_mode in all fpgadataflow nodes to specify which kind of execution should be used ("cppsim" or "rtlsim"). - Note that RTL components do not support cppsim. - For now, only a model consisting of 100% of HLS layers can be executed - using cppsim.""" + Note that RTL components do not support cppsim. When cppsim is selected + for RTL components, by default the execution of the HW op parent is + executed.""" def __init__(self, mode): super().__init__() self.mode = mode def apply(self, model): - mode = self.mode - # if "cppsim" selected, check if model does not contain RTL layers - if mode == "cppsim" and any(is_rtl_node(node) for node in model.graph.node): - raise Exception( - """Model contains RTL layers, - cppsim can only be used on models consisting of HLS layers - and non fpgadataflow nodes.""" - ) - else: - for node in model.graph.node: - op_type = node.op_type - if is_hls_node(node) or is_rtl_node(node): - try: - # lookup op_type in registry of CustomOps - inst = registry.getCustomOp(node) - # set sim_mode accordingly to argument mode - inst.set_nodeattr("exec_mode", mode) - # ensure that sim_mode is now set - assert ( - inst.get_nodeattr("exec_mode") != "" - ), """Transformation - was not successful. Node attribute "exec_mode" is not set""" - except KeyError: - # exception if op_type is not supported - raise Exception("Custom op_type %s is currently not supported." % op_type) + for node in model.graph.node: + op_type = node.op_type + if is_hls_node(node) or is_rtl_node(node): + try: + # lookup op_type in registry of CustomOps + inst = registry.getCustomOp(node) + # set sim_mode accordingly to argument mode + inst.set_nodeattr("exec_mode", self.mode) + # ensure that sim_mode is now set + assert ( + inst.get_nodeattr("exec_mode") != "" + ), """Transformation + was not successful. Node attribute "exec_mode" is not set""" + except KeyError: + # exception if op_type is not supported + raise Exception("Custom op_type %s is currently not supported." % op_type) return (model, False) diff --git a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py index 1a9a934df1..1fe96d6bd7 100644 --- a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py +++ b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py @@ -202,12 +202,9 @@ def test_fpgadataflow_slidingwindow( inst.set_nodeattr("parallel_window", parallel_window) if exec_mode == "cppsim": - if model.graph.node[0].op_type == "ConvolutionInputGenerator_rtl": - pytest.skip("cppsim not supported for RTL DWC") - else: - model = model.transform(SetExecMode("cppsim")) - model = model.transform(PrepareCppSim()) - model = model.transform(CompileCppSim()) + model = model.transform(SetExecMode("cppsim")) + model = model.transform(PrepareCppSim()) + model = model.transform(CompileCppSim()) elif exec_mode == "rtlsim": model = model.transform(SetExecMode("rtlsim")) model = model.transform(GiveUniqueNodeNames()) diff --git a/tests/fpgadataflow/test_fpgadataflow_dwc.py b/tests/fpgadataflow/test_fpgadataflow_dwc.py index d46815ebac..7152d32a7b 100644 --- a/tests/fpgadataflow/test_fpgadataflow_dwc.py +++ b/tests/fpgadataflow/test_fpgadataflow_dwc.py @@ -96,7 +96,7 @@ def prepare_inputs(input_tensor, dt): @pytest.mark.fpgadataflow @pytest.mark.slow @pytest.mark.vivado -def test_fpgadataflow_dwc_rtlsim(config, exec_mode): +def test_fpgadataflow_dwc(config, exec_mode): shape, inWidth, outWidth, finn_dtype = config test_fpga_part = "xc7z020clg400-1" @@ -114,16 +114,12 @@ def test_fpgadataflow_dwc_rtlsim(config, exec_mode): assert y.shape == tuple(shape), """The output shape is incorrect.""" model = model.transform(SpecializeLayers()) + model = model.transform(GiveUniqueNodeNames()) if exec_mode == "cppsim": - if model.graph.node[0].op_type == "StreamingDataWidthConverter_rtl": - pytest.skip("cppsim not supported for RTL DWC") - else: - model = model.transform(GiveUniqueNodeNames()) - model = model.transform(PrepareCppSim()) - model = model.transform(CompileCppSim()) - model = model.transform(SetExecMode("cppsim")) + model = model.transform(PrepareCppSim()) + model = model.transform(CompileCppSim()) + model = model.transform(SetExecMode("cppsim")) elif exec_mode == "rtlsim": - model = model.transform(GiveUniqueNodeNames()) model = model.transform(PrepareIP(test_fpga_part, 5)) model = model.transform(HLSSynthIP()) model = model.transform(SetExecMode("rtlsim")) diff --git a/tests/fpgadataflow/test_fpgadataflow_fmpadding.py b/tests/fpgadataflow/test_fpgadataflow_fmpadding.py index 12c84e7221..45cc265ac7 100644 --- a/tests/fpgadataflow/test_fpgadataflow_fmpadding.py +++ b/tests/fpgadataflow/test_fpgadataflow_fmpadding.py @@ -113,8 +113,6 @@ def make_single_fmpadding_modelwrapper(impl_style, idim, padding, num_ch, simd, @pytest.mark.slow @pytest.mark.vivado def test_fpgadataflow_fmpadding(idim, pad, num_ch, simd, idt, mode, impl_style): - if impl_style == "rtl" and mode == "cppsim": - pytest.skip("rtl implstyle has no cppsim, skipping") if num_ch % simd != 0: pytest.skip(" num_ch % simd != 0, skipping") From 243883137ede3a8425a52897b559f2c3558793d6 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Fri, 23 Feb 2024 14:39:02 +0000 Subject: [PATCH 519/665] [CustomOps] threshold mem_mode for HLS variant only --- src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py | 4 ++++ src/finn/custom_op/fpgadataflow/thresholding.py | 4 ---- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py b/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py index 07fe4296e3..7afc42b6e7 100644 --- a/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py @@ -60,6 +60,10 @@ def __init__(self, onnx_node, **kwargs): def get_nodeattr_types(self): my_attrs = { + # memory mode for the thresholds + # const -- embedded thresholds, default + # decoupled -- streaming thresholds with streamer packaged inside IP + "mem_mode": ("s", False, "const", {"const", "decoupled"}), # string defining memory type "ram_style": ("s", False, "distributed", {"distributed", "block"}), } diff --git a/src/finn/custom_op/fpgadataflow/thresholding.py b/src/finn/custom_op/fpgadataflow/thresholding.py index 73c5ecf997..a2f4b7e624 100644 --- a/src/finn/custom_op/fpgadataflow/thresholding.py +++ b/src/finn/custom_op/fpgadataflow/thresholding.py @@ -42,10 +42,6 @@ def __init__(self, onnx_node, **kwargs): def get_nodeattr_types(self): my_attrs = { - # memory mode for the thresholds - # const -- embedded thresholds, default - # decoupled -- streaming thresholds with streamer packaged inside IP - "mem_mode": ("s", False, "const", {"const", "decoupled"}), # whether weights (thresholds) will be # writable through an AXI-lite interface during runtime # 1 for enabled, 0 for disabled. From e3e8c974d3adefc630019ad35931a23e318a0705 Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 23 Feb 2024 14:44:31 +0000 Subject: [PATCH 520/665] [Transform] Clean up SpecializeLayers transform --- .../transformation/fpgadataflow/specialize_layers.py | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/specialize_layers.py b/src/finn/transformation/fpgadataflow/specialize_layers.py index 6c94f45d16..a8e8fc72c1 100644 --- a/src/finn/transformation/fpgadataflow/specialize_layers.py +++ b/src/finn/transformation/fpgadataflow/specialize_layers.py @@ -34,20 +34,10 @@ from finn.custom_op.fpgadataflow.hls import custom_op as hls_variants from finn.custom_op.fpgadataflow.rtl import custom_op as rtl_variants -restricted_layers = [] -restricted_layers.append("MVAU") -restricted_layers.append("VectorVectorActivation") -restricted_layers.append("Thresholding") - def _determine_impl_style(node): optype = node.op_type - # if rtl variant has specific restrictions - # use always the hls variant for now - if optype in restricted_layers: - return "hls" - # check if there is an HLS or RTL variant or both hls_variant = optype + "_hls" in hls_variants.keys() rtl_variant = optype + "_rtl" in rtl_variants.keys() @@ -77,7 +67,7 @@ def _determine_impl_style(node): # check if user setting can be fulfilled # otherwise change impl_style - if impl_style == "hls": + elif impl_style == "hls": if optype == "ConvolutionInputGenerator": if not _swg_hls_possible(node): warn_str = ( From 55671acc2116ba8fb2e59de9352fc2ca91beab87 Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 23 Feb 2024 17:02:08 +0000 Subject: [PATCH 521/665] [Transform] Cleanup InsertDWC check if node is dwc node --- src/finn/transformation/fpgadataflow/insert_dwc.py | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/insert_dwc.py b/src/finn/transformation/fpgadataflow/insert_dwc.py index 96c114498c..33cc3e86d3 100644 --- a/src/finn/transformation/fpgadataflow/insert_dwc.py +++ b/src/finn/transformation/fpgadataflow/insert_dwc.py @@ -35,10 +35,7 @@ def _is_dwc_node(node): - if node.op_type.startswith("StreamingDataWidthConverter"): - return True - else: - return False + return node.op_type.startswith("StreamingDataWidthConverter") def _suitable_node(node): From b60dc425578266feb68c7c3ad7fd591189da0b88 Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 23 Feb 2024 17:30:37 +0000 Subject: [PATCH 522/665] [RTL layers] Remove warning for cppsim --- .../fpgadataflow/rtl/convolutioninputgenerator_rtl.py | 5 ----- src/finn/custom_op/fpgadataflow/rtl/fmpadding_rtl.py | 5 ----- .../fpgadataflow/rtl/streamingdatawidthconverter_rtl.py | 5 ----- 3 files changed, 15 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/rtl/convolutioninputgenerator_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/convolutioninputgenerator_rtl.py index aebbc6c646..08564ca6da 100755 --- a/src/finn/custom_op/fpgadataflow/rtl/convolutioninputgenerator_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/convolutioninputgenerator_rtl.py @@ -30,7 +30,6 @@ import numpy as np import os import shutil -import warnings from qonnx.core.datatype import DataType from qonnx.custom_op.general import im2col from qonnx.custom_op.general.im2col import compute_conv_output_dim @@ -289,10 +288,6 @@ def execute_node(self, context, graph): code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") if mode == "cppsim": - warnings.warn( - """RTL components cannot be executed with cppsim. - By default the execution of the HW abstraction parent will be used.""" - ) ConvolutionInputGenerator.execute_node(self, context, graph) elif mode == "rtlsim": node = self.onnx_node diff --git a/src/finn/custom_op/fpgadataflow/rtl/fmpadding_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/fmpadding_rtl.py index 713fd81da6..19765d64c4 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/fmpadding_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/fmpadding_rtl.py @@ -30,7 +30,6 @@ import numpy as np import os import shutil -import warnings from qonnx.util.basic import roundup_to_integer_multiple from finn.custom_op.fpgadataflow.fmpadding import FMPadding @@ -74,10 +73,6 @@ def execute_node(self, context, graph): code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") if mode == "cppsim": - warnings.warn( - """RTL components cannot be executed with cppsim. - By default the execution of the HW abstraction parent will be used.""" - ) FMPadding.execute_node(self, context, graph) elif mode == "rtlsim": node = self.onnx_node diff --git a/src/finn/custom_op/fpgadataflow/rtl/streamingdatawidthconverter_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/streamingdatawidthconverter_rtl.py index 2b1ff019ac..ef918b5db8 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/streamingdatawidthconverter_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/streamingdatawidthconverter_rtl.py @@ -29,7 +29,6 @@ import numpy as np import os import shutil -import warnings from finn.custom_op.fpgadataflow.rtlbackend import RTLBackend from finn.custom_op.fpgadataflow.streamingdatawidthconverter import ( @@ -77,10 +76,6 @@ def execute_node(self, context, graph): code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") if mode == "cppsim": - warnings.warn( - """RTL components cannot be executed with cppsim. - By default the execution of the HW abstraction parent will be used.""" - ) StreamingDataWidthConverter.execute_node(self, context, graph) elif mode == "rtlsim": node = self.onnx_node From e7c1e5fddb0c178e3c3a474d970061e1783ea3b3 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Wed, 28 Feb 2024 11:37:37 +0000 Subject: [PATCH 523/665] [CustomOp] restructure class methods from class hierachy --- .../fpgadataflow/hls/thresholding_hls.py | 6 +- .../fpgadataflow/rtl/thresholding_rtl.py | 140 +----------------- .../custom_op/fpgadataflow/thresholding.py | 59 +++++++- 3 files changed, 58 insertions(+), 147 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py b/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py index 7afc42b6e7..7b9809f495 100644 --- a/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py @@ -105,11 +105,7 @@ def lut_estimation(self): def get_weightstream_width(self): """Returns weight stream width. Used only in decoupled mode.""" if self.get_nodeattr("mem_mode") == "decoupled": - pe = self.get_nodeattr("PE") - wp = self.get_weight_datatype().bitwidth() - n_thres_steps = self.get_nodeattr("numSteps") - w_width = pe * wp * n_thres_steps - return w_width + return super().get_weightstream_width() else: return 0 diff --git a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py index cdca8cc373..007c322dea 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py @@ -154,128 +154,6 @@ def lut_estimation(self): res_dict = self.get_memory_estimate() return res_dict.get("LUTRAM", 0) - def get_input_datatype(self, ind=0): - return DataType[self.get_nodeattr("inputDataType")] - - def get_output_datatype(self, ind=0): - return DataType[self.get_nodeattr("outputDataType")] - - def get_weight_datatype(self): - """The term 'weights' and 'thresholds' are used interchangably in this class.""" - return DataType[self.get_nodeattr("weightDataType")] - - def minimize_accumulator_width(self, model): - "Minimize threshold width ('accumulator width' here due to convention)" - thresholds = model.get_initializer(self.onnx_node.input[1]) - threshold_tensor = self.get_hw_compatible_threshold_tensor(thresholds) - min_threshold = thresholds.min() - max_threshold = thresholds.max() - min_input = self.get_input_datatype().min() - max_input = self.get_input_datatype().max() - # get range required by threshold values - tdt_min = min(min_input, min_threshold) - tdt_max = max(max_input, max_threshold) - if tdt_min < 0: - if abs(tdt_min) > tdt_max: - tdt = DataType.get_smallest_possible(tdt_min) - else: - tdt = DataType.get_smallest_possible(-tdt_max - 1) - else: - tdt = DataType.get_smallest_possible(tdt_max) - assert np.vectorize(tdt.allowed)( - threshold_tensor - ).all(), "Thresholds can't be expressed with type %s" % str(tdt) - self.set_nodeattr("weightDataType", tdt.name) - return DataType[self.get_nodeattr("weightDataType")] - - def get_instream_width(self, ind=0): - i_bits = self.get_input_datatype().bitwidth() - return i_bits * self.get_nodeattr("PE") - - def get_outstream_width(self, ind=0): - o_bits = self.get_output_datatype().bitwidth() - return o_bits * self.get_nodeattr("PE") - - def get_weightstream_width(self): - """Returns weight stream width""" - pe = self.get_nodeattr("PE") - wp = self.get_weight_datatype().bitwidth() - n_thres_steps = self.get_nodeattr("numSteps") - w_width = pe * wp * n_thres_steps - return w_width - - def get_folded_input_shape(self, ind=0): - fold = self.calc_tmem() - pe = self.get_nodeattr("PE") - vecs = list(self.get_nodeattr("numInputVectors")) - folded_input_shape = tuple(vecs + [fold, pe]) - return folded_input_shape - - def get_folded_output_shape(self, ind=0): - # same shape as input - return self.get_folded_input_shape() - - def get_normal_input_shape(self, ind=0): - num_channels = self.get_nodeattr("NumChannels") - vecs = list(self.get_nodeattr("numInputVectors")) - normal_input_shape = tuple(vecs + [num_channels]) - return normal_input_shape - - def get_normal_output_shape(self, ind=0): - # same shape as input - return self.get_normal_input_shape() - - def get_number_output_values(self): - return np.prod(self.get_folded_output_shape()[:-1]) - - def get_exp_cycles(self): - # Channels/PE * batch size * fmdim * fmdim - return np.prod(self.get_folded_output_shape()[:-1]) - - def get_hw_compatible_threshold_tensor(self, orig_thres_matrix): - """Convert the original numpy weight matrix orig_weight_matrix into - a form suitable for passing to the hlslib call: - * ensure MH % PE == 0 - * for unsigned inputs, ensure thresholds are positive - * interleave rows between PEs - * reshape into (PE, TMEM, n_thres_steps) and return - """ - mh = self.get_nodeattr("NumChannels") - pe = self.get_nodeattr("PE") - tmem = mh // pe - assert mh % pe == 0, "Requirement NumChannels divisable by PE is violated." - assert ( - orig_thres_matrix.ndim == 2 - ), """Threshold matrix dimension is - not as expected (2).""" - n_thres_steps = orig_thres_matrix.shape[1] - assert n_thres_steps == self.get_nodeattr("numSteps"), "Mismatch in threshold steps" - if not self.get_input_datatype().signed(): - # ensure all thresholds are nonnegative - assert (orig_thres_matrix >= 0).all() - # ensure all thresholds are integer - assert np.equal(np.mod(orig_thres_matrix, 1), 0).all(), "Need int threshold tensor" - ret = orig_thres_matrix - # ensure channels = mh , duplicating if necessary - if ret.shape[0] == 1: - ret = np.tile(ret, (mh, 1)) - assert ret.shape[0] == mh, "Channels of threshold matrix are not as expected (mh)" - # distribute rows between PEs - ret = interleave_matrix_outer_dim_from_partitions(ret, pe) - assert ( - ret.shape[0] == pe - ), """First dimension after distribution of the - rows between PEs is not as expected (pe)""" - assert ( - ret.shape[1] == tmem - ), """Second dimension after distribution of the - rows between PEs is not as expected (tmem)""" - assert ( - ret.shape[2] == n_thres_steps - ), """Third dimension after distribution of the - rows between PEs is not as expected (n_thres_steps)""" - return ret.reshape(1, pe, tmem, n_thres_steps) - def get_all_meminit_filenames(self, abspath=False): "Return a list of all .dat memory initializer files used for this node" dat_files = [] @@ -623,23 +501,7 @@ def code_generation_ipi(self): return cmd def get_verilog_top_module_intf_names(self): - """Return a dict of names of input and output interfaces. - The keys reflect the protocols each interface implements: - 'clk', 'rst', 'm_axis', 's_axis', 'aximm', 'axilite'. - Values are lists of tuples (axis, aximm) or names (axilite): - 'axis' tuples correspond to the list of node inputs in order, - each tuple is (interface_name, interface_width_bits). - axilite always assumed to be 32 bits and is not tuple (name only). - Each block must have at most one aximm and one axilite.""" - - intf_names = {} - intf_names["clk"] = ["ap_clk"] - intf_names["rst"] = ["ap_rst_n"] - intf_names["s_axis"] = [("in0_V", self.get_instream_width_padded())] - intf_names["m_axis"] = [("out_V", self.get_outstream_width_padded())] - intf_names["aximm"] = [] - intf_names["axilite"] = [] - intf_names["ap_none"] = [] + intf_names = super().get_verilog_top_module_intf_names() if self.get_nodeattr("runtime_writeable_weights") == 1: intf_names["axilite"] = ["s_axilite"] diff --git a/src/finn/custom_op/fpgadataflow/thresholding.py b/src/finn/custom_op/fpgadataflow/thresholding.py index a2f4b7e624..d3ba724818 100644 --- a/src/finn/custom_op/fpgadataflow/thresholding.py +++ b/src/finn/custom_op/fpgadataflow/thresholding.py @@ -30,7 +30,7 @@ import warnings from qonnx.core.datatype import DataType from qonnx.custom_op.general.multithreshold import multithreshold - +from qonnx.util.basic import interleave_matrix_outer_dim_from_partitions from finn.custom_op.fpgadataflow.hwcustomop import HWCustomOp @@ -122,10 +122,18 @@ def get_weight_datatype(self): """Returns FINN DataType of thresholds, here called weights.""" return DataType[self.get_nodeattr("weightDataType")] + def get_weightstream_width(self): + """Returns weight stream width""" + pe = self.get_nodeattr("PE") + wp = self.get_weight_datatype().bitwidth() + n_thres_steps = self.get_nodeattr("numSteps") + w_width = pe * wp * n_thres_steps + return w_width + def minimize_accumulator_width(self, model): "Minimize threshold width ('accumulator width' here due to convention)" thresholds = model.get_initializer(self.onnx_node.input[1]) - threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds) + threshold_tensor = self.get_hw_compatible_threshold_tensor(thresholds) min_threshold = thresholds.min() max_threshold = thresholds.max() min_input = self.get_input_datatype().min() @@ -159,7 +167,7 @@ def get_outstream_width(self, ind=0): def get_folded_input_shape(self, ind=0): ich = self.get_nodeattr("NumChannels") pe = self.get_nodeattr("PE") - fold = ich // pe + fold = self.calc_tmem() vecs = list(self.get_nodeattr("numInputVectors")) folded_input_shape = tuple(vecs + [fold, pe]) return folded_input_shape @@ -186,6 +194,51 @@ def get_exp_cycles(self): # Channels/PE * batch size * fmdim * fmdim return np.prod(self.get_folded_output_shape()[:-1]) + + def get_hw_compatible_threshold_tensor(self, orig_thres_matrix): + """Convert the original numpy weight matrix orig_weight_matrix into + a form suitable for passing to the hlslib call: + * ensure MH % PE == 0 + * for unsigned inputs, ensure thresholds are positive + * interleave rows between PEs + * reshape into (PE, TMEM, n_thres_steps) and return + """ + mh = self.get_nodeattr("NumChannels") + pe = self.get_nodeattr("PE") + tmem = mh // pe + assert mh % pe == 0, "Requirement NumChannels divisable by PE is violated." + assert ( + orig_thres_matrix.ndim == 2 + ), """Threshold matrix dimension is + not as expected (2).""" + n_thres_steps = orig_thres_matrix.shape[1] + assert n_thres_steps == self.get_nodeattr("numSteps"), "Mismatch in threshold steps" + if not self.get_input_datatype().signed(): + # ensure all thresholds are nonnegative + assert (orig_thres_matrix >= 0).all() + # ensure all thresholds are integer + assert np.equal(np.mod(orig_thres_matrix, 1), 0).all(), "Need int threshold tensor" + ret = orig_thres_matrix + # ensure channels = mh , duplicating if necessary + if ret.shape[0] == 1: + ret = np.tile(ret, (mh, 1)) + assert ret.shape[0] == mh, "Channels of threshold matrix are not as expected (mh)" + # distribute rows between PEs + ret = interleave_matrix_outer_dim_from_partitions(ret, pe) + assert ( + ret.shape[0] == pe + ), """First dimension after distribution of the + rows between PEs is not as expected (pe)""" + assert ( + ret.shape[1] == tmem + ), """Second dimension after distribution of the + rows between PEs is not as expected (tmem)""" + assert ( + ret.shape[2] == n_thres_steps + ), """Third dimension after distribution of the + rows between PEs is not as expected (n_thres_steps)""" + return ret.reshape(1, pe, tmem, n_thres_steps) + def execute_node(self, context, graph): node = self.onnx_node inp_values = context[node.input[0]] From d16d493ad99a1758b04df37cb96d6cd7b7074308 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Fri, 1 Mar 2024 11:18:28 +0000 Subject: [PATCH 524/665] [CustomOp] Remove redudent methods from thresholding rtl --- .../fpgadataflow/rtl/thresholding_rtl.py | 53 ++++++++----------- 1 file changed, 22 insertions(+), 31 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py index 007c322dea..c112125925 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py @@ -429,7 +429,28 @@ def execute_node(self, context, graph): "inputs": {istream_name: inp}, "outputs": {ostream_name: []}, } - self.rtlsim_multi_io(sim, io_dict) + + trace_file = self.get_nodeattr("rtlsim_trace") + if trace_file == "default": + trace_file = self.onnx_node.name + ".vcd" + sname = "_" + + # Change into so directory to ensure threshold files can be found + rtlsim_so = self.get_nodeattr("rtlsim_so") + so_dir = os.path.dirname(os.path.realpath(rtlsim_so)) + olcwd = os.getcwd() + os.chdir(so_dir) + num_out_values = self.get_number_output_values() + reset_rtlsim(sim) + total_cycle_count = rtlsim_multi_io(sim, + io_dict, + num_out_values, + trace_file=trace_file, + sname=sname, + liveness_threshold=pyverilate_get_liveness_threshold_cycles() + ) + self.set_nodeattr("cycles_rtlsim", total_cycle_count) + os.chdir(olcwd) output = io_dict["outputs"][ostream_name] # Manage output data @@ -448,36 +469,6 @@ def execute_node(self, context, graph): context[node.output[0]] = output return - def rtlsim_multi_io(self, sim, io_dict): - "Run rtlsim for this node, supports multiple i/o streams." - - rtlsim_so = self.get_nodeattr("rtlsim_so") - so_dir = os.path.dirname(os.path.realpath(rtlsim_so)) - olcwd = os.getcwd() - os.chdir(so_dir) - - # signal name prefix - # TODO if the interface names on this component get standardized, - # it won't need its own rtlsim_multi_io variant anymore and can just - # use the base class one - sname = "_" - - trace_file = self.get_nodeattr("rtlsim_trace") - if trace_file == "default": - trace_file = self.onnx_node.name + ".vcd" - num_out_values = self.get_number_output_values() - reset_rtlsim(sim) - total_cycle_count = rtlsim_multi_io( - sim, - io_dict, - num_out_values, - trace_file=trace_file, - sname=sname, - liveness_threshold=pyverilate_get_liveness_threshold_cycles(), - ) - self.set_nodeattr("cycles_rtlsim", total_cycle_count) - os.chdir(olcwd) - def code_generation_ipi(self): """Constructs and returns the TCL commands for node instantiation as an RTL block.""" From d612c29dccb82ba070af729b287010bfcf8fc4f7 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Fri, 1 Mar 2024 12:01:23 +0000 Subject: [PATCH 525/665] [CustomOp] clean up threshold weight generation --- .../fpgadataflow/rtl/thresholding_rtl.py | 83 ++++++++----------- 1 file changed, 34 insertions(+), 49 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py index c112125925..26387a7192 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py @@ -565,7 +565,7 @@ def generate_params(self, model, path): """Please set mem_mode to "const", "decoupled", currently no other parameter value is supported!""" ) - def make_weight_file(self, weights, weight_file_mode, weight_file_name): + def make_weight_file(self, weights, weight_file_name): """Produce a file containing given weights (thresholds) in appropriate format for this layer. This file can be used for either synthesis or run-time reconfig of weights. @@ -573,8 +573,6 @@ def make_weight_file(self, weights, weight_file_mode, weight_file_name): Arguments: * weights : numpy array with weights to be put into the file - * weight_file_mode : one of { decoupled_verilog_dat, - decoupled_runtime} * weight_file_name : filename for the weight file to be generated """ @@ -583,49 +581,36 @@ def make_weight_file(self, weights, weight_file_mode, weight_file_name): assert np.vectorize(tdt.allowed)( threshold_tensor ).all(), "Thresholds can't be expressed with type %s" % str(tdt) - if "decoupled" in weight_file_mode: - # streaming thresholds need to be organized differently - # (1, pe, tmem, n_thres_steps) -> (1, tmem, pe, n_thres_steps) - decoupled_thres = np.transpose(threshold_tensor, (0, 2, 1, 3)) - # TODO add flips/reversals as needed here - # (1, tmem, pe, n_thres_steps) -(1, tmem, pe * n_thres_steps) - pe = self.get_nodeattr("PE") - ch = self.get_nodeattr("NumChannels") - n_thres_steps = self.get_nodeattr("numSteps") - decoupled_thres_pe_flipped = np.flip(decoupled_thres, axis=-2) - decoupled_thres = decoupled_thres.reshape(1, -1, pe * n_thres_steps) - decoupled_thres = decoupled_thres.copy() - decoupled_thres_pe_flipped = decoupled_thres_pe_flipped.reshape( - 1, -1, pe * n_thres_steps - ) - decoupled_thres_pe_flipped = decoupled_thres_pe_flipped.copy() - width_padded = roundup_to_integer_multiple(weights.shape[1], 4) - weight_padded = np.zeros((weights.shape[0],width_padded)) - weight_padded[:weights.shape[0], :n_thres_steps ] = weights - weight_stream = [] - wdt = self.get_weight_datatype() - bw_hexdigit = roundup_to_integer_multiple(wdt.bitwidth(), 32) - padding = np.zeros(width_padded, dtype=np.int32) - - chan_ind = 0 - cf = ch//pe - for fold in range(cf): - for c in range(2**(pe-1).bit_length()): - if (c==0 or c%pe != 0) and c < pe: - for w in weight_padded[chan_ind]: - w_packed = pack_innermost_dim_as_hex_string( - [w], wdt, bw_hexdigit, prefix="" - ).item() - weight_stream.append(w_packed) - chan_ind +=1 - else: - for z in padding: - w_packed = pack_innermost_dim_as_hex_string( - [z], wdt, bw_hexdigit, prefix="" - ).item() - weight_stream.append(w_packed) - with open(weight_file_name, "w") as f: - for val in weight_stream: - f.write(val + "\n") - else: - raise Exception("Unknown weight_file_mode") \ No newline at end of file + + pe = self.get_nodeattr("PE") + ch = self.get_nodeattr("NumChannels") + n_thres_steps = self.get_nodeattr("numSteps") + + width_padded = roundup_to_integer_multiple(weights.shape[1], 4) + weight_padded = np.zeros((weights.shape[0],width_padded)) + weight_padded[:weights.shape[0], :n_thres_steps ] = weights + weight_stream = [] + wdt = self.get_weight_datatype() + bw_hexdigit = roundup_to_integer_multiple(wdt.bitwidth(), 32) + padding = np.zeros(width_padded, dtype=np.int32) + + chan_ind = 0 + cf = ch//pe + for fold in range(cf): + for c in range(2**(pe-1).bit_length()): + if (c==0 or c%pe != 0) and c < pe: + for w in weight_padded[chan_ind]: + w_packed = pack_innermost_dim_as_hex_string( + [w], wdt, bw_hexdigit, prefix="" + ).item() + weight_stream.append(w_packed) + chan_ind +=1 + else: + for z in padding: + w_packed = pack_innermost_dim_as_hex_string( + [z], wdt, bw_hexdigit, prefix="" + ).item() + weight_stream.append(w_packed) + with open(weight_file_name, "w") as f: + for val in weight_stream: + f.write(val + "\n") From 503efe7b55e8269a42ca0ea780c377461daf60ff Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Fri, 1 Mar 2024 17:52:45 +0000 Subject: [PATCH 526/665] [CustomOps] make weight files during HDL file generation --- .../custom_op/fpgadataflow/rtl/thresholding_rtl.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py index 26387a7192..4adde1452d 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py @@ -31,13 +31,9 @@ import os import shutil import warnings -from math import ceil, log2 from pyverilator.util.axi_utils import rtlsim_multi_io, reset_rtlsim from qonnx.core.datatype import DataType -from qonnx.util.basic import ( - interleave_matrix_outer_dim_from_partitions, - roundup_to_integer_multiple, -) +from qonnx.util.basic import roundup_to_integer_multiple from finn.custom_op.fpgadataflow.rtlbackend import RTLBackend from finn.custom_op.fpgadataflow.thresholding import Thresholding @@ -316,6 +312,10 @@ def generate_hdl(self, model): # Retrieve the destination directory for the final RTL files code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + weights = model.get_initializer(self.onnx_node.input[1]) + weights_fname = f"{code_gen_dir}/memblock.dat" + self.make_weight_file(weights,"decoupled", weights_fname) + for rtl_file_path in self.get_rtl_file_paths(): # read in original RTL template file template_data = self.get_rtl_template_data(rtl_file_path) @@ -565,7 +565,7 @@ def generate_params(self, model, path): """Please set mem_mode to "const", "decoupled", currently no other parameter value is supported!""" ) - def make_weight_file(self, weights, weight_file_name): + def make_weight_file(self, weights, weight_file_mode, weight_file_name): """Produce a file containing given weights (thresholds) in appropriate format for this layer. This file can be used for either synthesis or run-time reconfig of weights. From 2c50994abe7f16a41141a6a578355e4e2fec85bc Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Fri, 1 Mar 2024 17:53:21 +0000 Subject: [PATCH 527/665] [tests] threshold test get the right impl_style --- tests/fpgadataflow/test_fpgadataflow_thresholding.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_thresholding.py b/tests/fpgadataflow/test_fpgadataflow_thresholding.py index dfd14268e5..62d7b04278 100644 --- a/tests/fpgadataflow/test_fpgadataflow_thresholding.py +++ b/tests/fpgadataflow/test_fpgadataflow_thresholding.py @@ -274,7 +274,8 @@ def test_runtime_thresholds_read(impl_style,cfg): # Make sure that specialize layer did not default to HLS implementation assert model.graph.node[0].op_type == "Thresholding_" + str(impl_style) - op_inst = getCustomOp(model.graph.node[0]) + node = model.get_nodes_by_op_type(f"Thresholding_{impl_style}")[0] + op_inst = getCustomOp(node) op_inst.set_nodeattr("runtime_writeable_weights", 1) dat_fname = f"old_weights_{cfg}.dat" From d48c7119d30d936b5f32027c43a3a46825f6dcf1 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Fri, 1 Mar 2024 18:32:50 +0000 Subject: [PATCH 528/665] [CustomOp] Add doc string for memutil function Signed-off-by: aziz bahri --- src/finn/util/basic.py | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/finn/util/basic.py b/src/finn/util/basic.py index 077e45200d..49220e9718 100644 --- a/src/finn/util/basic.py +++ b/src/finn/util/basic.py @@ -270,6 +270,15 @@ def find_next_power_of_2(n): def get_memutil_alternatives( req_mem_spec, mem_primitives=mem_primitives_versal, sort_min_waste=True ): + '''Computes how many instances of a memory primitive are necessary to + implement a desired memory size, where req_mem_spec is the desired + size and the primitive_spec is the primitve size. The sizes are expressed + as tuples of (mem_width, mem_depth). Returns a list of tuples of the form + (primitive_name, (primitive_count, efficiency, waste)) where efficiency in + range [0,1] indicates how much of the total capacity is utilized, and waste + indicates how many bits of storage are wasted. If sort_min_waste is True, + the list is sorted by increasing waste. + ''' ret = [ (primitive_name, memutil(req_mem_spec, primitive_spec)) for (primitive_name, primitive_spec) in mem_primitives.items() From ff3458bc4388eb8fe787f360c1e061ed91b03182 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Mon, 4 Mar 2024 10:43:11 +0000 Subject: [PATCH 529/665] [build dataflow]: add fpgapart as argument to SpecializeLayers transform --- src/finn/builder/build_dataflow_steps.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/finn/builder/build_dataflow_steps.py b/src/finn/builder/build_dataflow_steps.py index a75bbe98a1..72463a3865 100644 --- a/src/finn/builder/build_dataflow_steps.py +++ b/src/finn/builder/build_dataflow_steps.py @@ -403,7 +403,7 @@ def step_specialize_layers(model: ModelWrapper, cfg: DataflowBuildConfig): if cfg.specialize_layers_config_file is not None: model = model.transform(GiveUniqueNodeNames()) model = model.transform(ApplyConfig(cfg.specialize_layers_config_file)) - model = model.transform(SpecializeLayers()) + model = model.transform(SpecializeLayers(cfg._resolve_fpga_part())) model = model.transform(InferShapes()) model = model.transform(InferDataTypes()) return model From 4f4385fd1defdb6adaf2d92ef7bfa7e64f716fba Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Mon, 4 Mar 2024 10:47:39 +0000 Subject: [PATCH 530/665] [hls mvau]: remove duplicate method --- .../fpgadataflow/hls/matrixvectoractivation_hls.py | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py b/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py index e279d3953a..55a84b9dcb 100644 --- a/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py @@ -172,19 +172,6 @@ def get_template_param_values(self): return ret - def get_verilog_top_module_intf_names(self): - intf_names = super().get_verilog_top_module_intf_names() - mem_mode = self.get_nodeattr("mem_mode") - sname = self.hls_sname() - if mem_mode == "external": - intf_names["s_axis"].append(("weights_" + sname, self.get_weightstream_width_padded())) - if mem_mode == "decoupled": - # only expose axilite interface if attribute is set - runtime_writable = self.get_nodeattr("runtime_writeable_weights") == 1 - if runtime_writable: - intf_names["axilite"] = ["s_axilite"] - return intf_names - def global_includes(self): self.code_gen_dict["$GLOBALS$"] = ['#include "weights.hpp"'] self.code_gen_dict["$GLOBALS$"] += ['#include "activations.hpp"'] From 055c8fe9a31544cae534a8d398d571772dbf15af Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Mon, 4 Mar 2024 10:51:16 +0000 Subject: [PATCH 531/665] [hw mvau]: move get_verilog_top_module_intf_names to hw-op abstraction layer --- .../fpgadataflow/matrixvectoractivation.py | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index ac173e4af6..dc713c8b42 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -542,7 +542,7 @@ def minimize_weight_bit_width(self, model): self.set_nodeattr("weightDataType", wdt.name) return DataType[self.get_nodeattr("weightDataType")] - def get_hls_compatible_threshold_tensor(self, orig_thres_matrix): + def get_hw_compatible_threshold_tensor(self, orig_thres_matrix): """Convert the original numpy weight matrix orig_weight_matrix into a form suitable for passing to the hlslib call: * ensure MH % PE == 0 @@ -846,6 +846,19 @@ def derive_characteristic_fxns(self, period): io_dict["inputs"]["weights"] = [0 for i in range(num_w_reps * n_weight_inps)] super().derive_characteristic_fxns(period, override_rtlsim_dict=io_dict) + def get_verilog_top_module_intf_names(self): + intf_names = super().get_verilog_top_module_intf_names() + mem_mode = self.get_nodeattr("mem_mode") + sname = self.hls_sname() + if mem_mode == "external": + intf_names["s_axis"].append(("weights_" + sname, self.get_weightstream_width_padded())) + if mem_mode == "decoupled": + # only expose axilite interface if attribute is set + runtime_writable = self.get_nodeattr("runtime_writeable_weights") == 1 + if runtime_writable: + intf_names["axilite"] = ["s_axilite"] + return intf_names + def code_generation_ipi(self): cmd = [] # add streamer if needed From fd0f796b735ad082219993bee968e82298f1256a Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Mon, 4 Mar 2024 10:54:00 +0000 Subject: [PATCH 532/665] added MVAU_rtl custom-op --- src/finn/custom_op/fpgadataflow/rtl/__init__.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/finn/custom_op/fpgadataflow/rtl/__init__.py b/src/finn/custom_op/fpgadataflow/rtl/__init__.py index 914c033584..b7a798be98 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/__init__.py +++ b/src/finn/custom_op/fpgadataflow/rtl/__init__.py @@ -30,6 +30,7 @@ ConvolutionInputGenerator_rtl, ) from finn.custom_op.fpgadataflow.rtl.fmpadding_rtl import FMPadding_rtl +from finn.custom_op.fpgadataflow.rtl.matrixvectoractivation_rtl import MVAU_rtl from finn.custom_op.fpgadataflow.rtl.streamingdatawidthconverter_rtl import ( StreamingDataWidthConverter_rtl, ) @@ -43,3 +44,4 @@ custom_op["FMPadding_rtl"] = FMPadding_rtl custom_op["StreamingDataWidthConverter_rtl"] = StreamingDataWidthConverter_rtl custom_op["StreamingFIFO_rtl"] = StreamingFIFO_rtl +custom_op["MVAU_rtl"] = MVAU_rtl From 91a8c00cde59fb3bd995df7bb47e989823436abd Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Mon, 4 Mar 2024 10:56:29 +0000 Subject: [PATCH 533/665] [transform]: minor fix to extracting op_type from node, added fpgapart as argument to SpecializeLayers transform --- src/finn/transformation/fpgadataflow/set_fifo_depths.py | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/set_fifo_depths.py b/src/finn/transformation/fpgadataflow/set_fifo_depths.py index 1e25670a71..ca7499428f 100644 --- a/src/finn/transformation/fpgadataflow/set_fifo_depths.py +++ b/src/finn/transformation/fpgadataflow/set_fifo_depths.py @@ -266,8 +266,7 @@ def apply(self, model): for node in model.graph.node: # verify assumptions assert is_fpgadataflow_node(node), "Found non-fpgadataflow node: " + str(node) - op_type = node.op_type - assert not op_type.startswith("StreamingFIFO"), "Found existing StreamingFIFO node" + assert not node.op_type.startswith("StreamingFIFO"), "Found existing StreamingFIFO node" node = getCustomOp(node) ifd = node.get_nodeattr("inFIFODepths") ofd = node.get_nodeattr("outFIFODepths") @@ -283,8 +282,7 @@ def apply(self, model): ofd[o] = np.prod(node.get_folded_output_shape(o)[:-1]) node.set_nodeattr("inFIFODepths", ifd) node.set_nodeattr("outFIFODepths", ofd) - - if op_type in extw_optypes: + if node.onnx_node.op_type in extw_optypes: mmode = node.get_nodeattr("mem_mode") if mmode == "external": modified_fc_nodes.append(node.onnx_node.name) @@ -297,7 +295,7 @@ def apply(self, model): # insert stream infrastructure (DWC/FIFO) model = model.transform(InsertDWC()) model = model.transform(InsertFIFO(create_shallow_fifos=True)) - model = model.transform(SpecializeLayers()) + model = model.transform(SpecializeLayers(self.fpgapart)) model = model.transform(GiveUniqueNodeNames()) model = model.transform(GiveReadableTensorNames()) From d7f87146b8c01a4b3a2a85bc1ba6e9fc43165bb2 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Mon, 4 Mar 2024 10:58:38 +0000 Subject: [PATCH 534/665] [transform]: added fpgapart as attribute and functions to determine whether RTL MVU/VVU is supported --- .../fpgadataflow/specialize_layers.py | 74 +++++++++++++++++-- 1 file changed, 68 insertions(+), 6 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/specialize_layers.py b/src/finn/transformation/fpgadataflow/specialize_layers.py index 6c94f45d16..2bfb32caf6 100644 --- a/src/finn/transformation/fpgadataflow/specialize_layers.py +++ b/src/finn/transformation/fpgadataflow/specialize_layers.py @@ -26,21 +26,22 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +import numpy as np import warnings from onnx import helper +from qonnx.core.datatype import DataType from qonnx.custom_op.registry import getCustomOp from qonnx.transformation.base import Transformation from finn.custom_op.fpgadataflow.hls import custom_op as hls_variants from finn.custom_op.fpgadataflow.rtl import custom_op as rtl_variants +from finn.util.fpgadataflow import is_versal restricted_layers = [] -restricted_layers.append("MVAU") -restricted_layers.append("VectorVectorActivation") restricted_layers.append("Thresholding") -def _determine_impl_style(node): +def _determine_impl_style(node, fpgapart=""): optype = node.op_type # if rtl variant has specific restrictions @@ -62,10 +63,10 @@ def _determine_impl_style(node): if optype == "StreamingDataWidthConverter": return _dwc_determine_impl_style(node) if rtl_variant: - return "rtl" + impl_style = "rtl" # but if no rtl variant, set impl_style to hls elif hls_variant: - return "hls" + impl_style = "hls" # if there is neither an rtl nor hls variant # throw error else: @@ -121,6 +122,28 @@ def _determine_impl_style(node): else: # user setting can be fulfilled return "rtl" + elif optype == "MVAU": + if _mvu_rtl_possible(node): + if getCustomOp(node).get_nodeattr("noActivation") == 0: + # Split thresholding + pass + return "rtl" + else: + warn_str = """There is no RTL variant for %s. The node will automatically be + set to HLS variant.""" % ( + node.name, + ) + warnings.warn(warn_str) + elif optype == "VectorVectorActivation": + if _vvu_rtl_possible(node, fpgapart): + return "rtl" + else: + warn_str = """There is no RTL variant for %s. The node will automatically be + set to HLS variant.""" % ( + node.name, + ) + warnings.warn(warn_str) + if rtl_variant: return "rtl" elif hls_variant: @@ -194,9 +217,48 @@ def _swg_hls_possible(node): return False +def _mvu_rtl_possible(n): + # Checks whether RTL-based MVU is supported + act_width_in_range = ( + DataType[getCustomOp(n).get_nodeattr("inputDataType")].bitwidth() <= 8 + ) or ( + DataType[getCustomOp(n).get_nodeattr("inputDataType")].bitwidth() == 9 + and DataType[getCustomOp(n).get_nodeattr("inputDataType")].min() < 0 + ) + weight_width_in_range = DataType[getCustomOp(n).get_nodeattr("weightDataType")].bitwidth() <= 8 + folding_supported = ( + getCustomOp(n).get_nodeattr("MH") % getCustomOp(n).get_nodeattr("PE") == 0 + ) and (getCustomOp(n).get_nodeattr("MW") % getCustomOp(n).get_nodeattr("SIMD") == 0) + + return act_width_in_range and weight_width_in_range and folding_supported + + +def _vvu_rtl_possible(n, fpgapart): + # Checks whether RTL-based VVU is supported + act_width_in_range = ( + DataType[getCustomOp(n).get_nodeattr("inputDataType")].bitwidth() <= 8 + ) or ( + DataType[getCustomOp(n).get_nodeattr("inputDataType")].bitwidth() == 9 + and DataType[getCustomOp(n).get_nodeattr("inputDataType")].min() < 0 + ) + weight_width_in_range = DataType[getCustomOp(n).get_nodeattr("weightDataType")].bitwidth() <= 8 + folding_supported = ( + getCustomOp(n).get_nodeattr("Channels") % getCustomOp(n).get_nodeattr("PE") == 0 + ) and ( + np.prod(getCustomOp(n).get_nodeattr("Kernel")) % getCustomOp(n).get_nodeattr("SIMD") == 0 + ) + is_versal_family = is_versal(fpgapart) + + return act_width_in_range and weight_width_in_range and folding_supported and is_versal_family + + class SpecializeLayers(Transformation): """Specialize all layers to either HLS or RTL variants""" + def __init__(self, fpgapart): + super().__init__() + self.fpgapart = fpgapart + def apply(self, model): graph = model.graph node_ind = 0 @@ -206,7 +268,7 @@ def apply(self, model): if not node.domain == "finn.custom_op.fpgadataflow": continue node_ind += 1 - impl_style = _determine_impl_style(node) + impl_style = _determine_impl_style(node, self.fpgapart) optype = node.op_type + "_" + impl_style new_node = helper.make_node( From 11d0c5ccbee3a8534df7dba5f76083d59c09f4b1 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Mon, 4 Mar 2024 10:59:29 +0000 Subject: [PATCH 535/665] [util]: added function to check if device is part of Versal family --- src/finn/util/fpgadataflow.py | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/finn/util/fpgadataflow.py b/src/finn/util/fpgadataflow.py index aae438fac2..3d3d343cd4 100644 --- a/src/finn/util/fpgadataflow.py +++ b/src/finn/util/fpgadataflow.py @@ -69,3 +69,11 @@ def is_rtl_node(node): is_node = True return is_node + + +def is_versal(fpgapart): + """Returns whether board is part of the Versal family""" + return ( + fpgapart[0:4] in ["xcvc", "xcve", "xcvp", "xcvm", "xqvc", "xqvm"] + or fpgapart[0:5] == "xqrvc" + ) From ea6fb3529203b8c23e90d8159b3a27517dad955a Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Mon, 4 Mar 2024 11:01:19 +0000 Subject: [PATCH 536/665] [rtl mvu/vvu]: rtl compute core, flow control and axi wrapper for MVU/VVU layers --- finn-rtllib/mvu/mvu_4sx4u.sv | 494 ++++++++++++++++++++++++++ finn-rtllib/mvu/mvu_8sx8u_dsp48.sv | 492 +++++++++++++++++++++++++ finn-rtllib/mvu/mvu_vvu_8sx9_dsp58.sv | 430 ++++++++++++++++++++++ finn-rtllib/mvu/mvu_vvu_axi.sv | 375 +++++++++++++++++++ finn-rtllib/mvu/mvu_vvu_axi_wrapper.v | 97 +++++ finn-rtllib/mvu/replay_buffer.sv | 181 ++++++++++ 6 files changed, 2069 insertions(+) create mode 100644 finn-rtllib/mvu/mvu_4sx4u.sv create mode 100644 finn-rtllib/mvu/mvu_8sx8u_dsp48.sv create mode 100644 finn-rtllib/mvu/mvu_vvu_8sx9_dsp58.sv create mode 100644 finn-rtllib/mvu/mvu_vvu_axi.sv create mode 100644 finn-rtllib/mvu/mvu_vvu_axi_wrapper.v create mode 100644 finn-rtllib/mvu/replay_buffer.sv diff --git a/finn-rtllib/mvu/mvu_4sx4u.sv b/finn-rtllib/mvu/mvu_4sx4u.sv new file mode 100644 index 0000000000..aafe0e3429 --- /dev/null +++ b/finn-rtllib/mvu/mvu_4sx4u.sv @@ -0,0 +1,494 @@ +module mvu_4sx4u #( + int unsigned PE, + int unsigned SIMD, + int unsigned ACCU_WIDTH, + + int unsigned VERSION = 1, + bit SIGNED_ACTIVATIONS = 0, + bit FORCE_BEHAVIORAL = 0 +)( + // Global Control + input logic clk, + input logic rst, + input logic en, + + // Input + input logic last, + input logic zero, // ignore current inputs and force this partial product to zero + input logic signed [PE-1:0][SIMD-1:0][3:0] w, // signed weights + input logic [SIMD-1:0][3:0] a, // unsigned activations (override by SIGNED_ACTIVATIONS) + + // Ouput + output logic vld, + output logic signed [PE-1:0][ACCU_WIDTH-1:0] p +); + // for verilator always use behavioral code + localparam bit BEHAVIORAL = +`ifdef VERILATOR + 1 || +`endif + FORCE_BEHAVIORAL; + + typedef int unsigned leave_load_t[2*SIMD-1]; + function leave_load_t init_leave_loads(); + automatic leave_load_t res; + for(int i = 2*(SIMD-1); i >= int'(SIMD)-1; i--) res[i] = 1; + for(int i = SIMD-2; i >= 0; i--) res[i] = res[2*i+1] + res[2*i+2]; + return res; + endfunction : init_leave_loads + + // Pipeline for last indicator flag + logic [1:5] L = '0; + always_ff @(posedge clk) begin + if(rst) L <= '0; + else if(en) L <= { last, L[1:4] }; + end + assign vld = L[5]; + + // Stages #1 - #3: DSP Lanes + cross-lane canaries duplicated with SIMD parallelism + localparam int unsigned D[4:0] = '{ ACCU_WIDTH+22, 22, 15, 8, 0 }; // Lane offsets + + localparam int unsigned PIPE_COUNT = (PE+3)/4; + for(genvar c = 0; c < PIPE_COUNT; c++) begin : genPipes + + localparam int unsigned PE_BEG = 4*c; + localparam int unsigned PE_END = PE < 4*(c+1)? PE : 4*(c+1); + localparam int unsigned PE_REM = 4*(c+1) - PE_END; + + uwire [57:0] p3[SIMD]; + uwire signed [ 1:0] h3[SIMD][3]; + for(genvar s = 0; s < SIMD; s++) begin : genSIMD + + // Input Lane Assembly + uwire [17:0] bb = { {(14){SIGNED_ACTIVATIONS && a[s][3]}}, a[s] }; + logic [29:0] aa; + logic [26:0] dd; + logic [ 1:0] xx[3:1]; + if(1) begin : blkVectorize + uwire [3:0] ww[PE_END - PE_BEG]; + for(genvar pe = 0; pe < PE_END - PE_BEG; pe++) begin + assign ww[pe] = w[PE_BEG + pe][s]; + if(pe) begin + if(BEHAVIORAL) assign xx[pe + PE_REM] = zero? 0 : ww[pe] * a[s]; +`ifndef VERILATOR + else begin + LUT6_2 #(.INIT(64'h0000_6AC0_0000_8888)) lut_x ( + .O6(xx[pe + PE_REM][1]), + .O5(xx[pe + PE_REM][0]), + .I5(1'b1), + .I4(zero), + .I3(ww[pe][1]), + .I2(a[s][1]), + .I1(ww[pe][0]), + .I0(a[s][0]) + ); + end +`endif + end + end + always_comb begin + dd = '0; + aa = '0; + for(int unsigned pe = 0; pe < PE_END - PE_BEG; pe++) begin + dd[D[pe + PE_REM]+:3] = ww[pe]; + aa[D[pe + PE_REM]+ 3] = ww[pe][3]; + end + end + end : blkVectorize + + uwire [47:0] pp; + + // Note: Since the product B * AD is computed, + // rst can be only applied to AD and zero only to B + // with the same effect as zeroing both. + if(BEHAVIORAL) begin : genBehav + // Stage #1: Input Refine + logic signed [17:0] B1 = 0; + always_ff @(posedge clk) begin + if(zero) B1 <= 0; + else if(en) B1 <= bb; + end + + logic signed [26:0] AD1 = 0; + always_ff @(posedge clk) begin + if(rst) AD1 <= 0; + else if(en) AD1 <= dd - aa; + end + + // Stage #2: Multiply + logic signed [45:0] M2 = 0; + always_ff @(posedge clk) begin + if(rst) M2 <= 0; + else if(en) M2 <= +// synthesis translate off + (B1 === '0) || (AD1 === '0)? 0 : +// synthesis translate on + B1 * AD1; + end + + // Stage #3: Accumulate + logic signed [47:0] P3 = 0; + always_ff @(posedge clk) begin + if(rst) P3 <= 0; + else if(en) P3 <= M2 + (L[3]? 0 : P3); + end + + assign pp = P3; + end : genBehav +`ifndef VERILATOR + else begin : genDSP + localparam logic [6:0] OPMODE_INVERSION = 7'b010_01_01; + uwire [6:0] opmode = { { 1'b0, L[2], 1'b0 }, 4'b00_00 }; + case(VERSION) + 1: DSP48E1 #( + // Feature Control Attributes: Data Path Selection + .A_INPUT("DIRECT"), // Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + .B_INPUT("DIRECT"), // Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + .USE_DPORT("TRUE"), // Select D port usage (TRUE or FALSE) + .USE_MULT("MULTIPLY"), // Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE") + .USE_SIMD("ONE48"), // SIMD selection ("ONE48", "TWO24", "FOUR12") + + // Pattern Detector Attributes: Pattern Detection Configuration + .AUTORESET_PATDET("NO_RESET"), // "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH" + .MASK('1), // 48-bit mask value for pattern detect (1=ignore) + .PATTERN('0), // 48-bit pattern match for pattern detect + .SEL_MASK("MASK"), // "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2" + .SEL_PATTERN("PATTERN"), // Select pattern value ("PATTERN" or "C") + .USE_PATTERN_DETECT("NO_PATDET"), // Enable pattern detect ("PATDET" or "NO_PATDET") + + // Register Control Attributes: Pipeline Register Configuration + .ACASCREG(0), // Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2) + .ADREG(1), // Number of pipeline stages for pre-adder (0 or 1) + .ALUMODEREG(0), // Number of pipeline stages for ALUMODE (0 or 1) + .AREG(0), // Number of pipeline stages for A (0, 1 or 2) + .BCASCREG(1), // Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2) + .BREG(1), // Number of pipeline stages for B (0, 1 or 2) + .CARRYINREG(0), // Number of pipeline stages for CARRYIN (0 or 1) + .CARRYINSELREG(0), // Number of pipeline stages for CARRYINSEL (0 or 1) + .CREG(0), // Number of pipeline stages for C (0 or 1) + .DREG(0), // Number of pipeline stages for D (0 or 1) + .INMODEREG(0), // Number of pipeline stages for INMODE (0 or 1) + .MREG(1), // Number of multiplier pipeline stages (0 or 1) + .OPMODEREG(1), // Number of pipeline stages for OPMODE (0 or 1) + .PREG(1) // Number of pipeline stages for P (0 or 1) + ) dsp ( + // Cascade: 30-bit (each) output: Cascade Ports + .ACOUT(), // 30-bit output: A port cascade output + .BCOUT(), // 18-bit output: B port cascade output + .CARRYCASCOUT(), // 1-bit output: Cascade carry output + .MULTSIGNOUT(), // 1-bit output: Multiplier sign cascade output + .PCOUT(), // 48-bit output: Cascade output + + // Control: 1-bit (each) output: Control Inputs/Status Bits + .OVERFLOW(), // 1-bit output: Overflow in add/acc output + .PATTERNBDETECT(), // 1-bit output: Pattern bar detect output + .PATTERNDETECT(), // 1-bit output: Pattern detect output + .UNDERFLOW(), // 1-bit output: Underflow in add/acc output + + // Data: 4-bit (each) output: Data Ports + .CARRYOUT(), // 4-bit output: Carry output + .P(pp), // 48-bit output: Primary data output + + // Cascade: 30-bit (each) input: Cascade Ports + .ACIN('x), // 30-bit input: A cascade data input + .BCIN('x), // 18-bit input: B cascade input + .CARRYCASCIN('x), // 1-bit input: Cascade carry input + .MULTSIGNIN('x), // 1-bit input: Multiplier sign input + .PCIN('x), // 48-bit input: P cascade input + + // Control: 4-bit (each) input: Control Inputs/Status Bits + .CLK(clk), // 1-bit input: Clock input + .ALUMODE('0), // 4-bit input: ALU control input + .CARRYINSEL('0), // 3-bit input: Carry select input + .INMODE(5'b01100), // 5-bit input: INMODE control input + .OPMODE(opmode ^ OPMODE_INVERSION), // 7-bit input: Operation mode input + + // Data: 30-bit (each) input: Data Ports + .A(aa), // 30-bit input: A data input + .B(bb), // 18-bit input: B data input + .C('x), // 48-bit input: C data input + .CARRYIN('0), // 1-bit input: Carry input signal + .D(dd), // 25-bit input: D data input + + // Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs + .CEA1('0), // 1-bit input: Clock enable input for 1st stage AREG + .CEA2('0), // 1-bit input: Clock enable input for 2nd stage AREG + .CEAD(en), // 1-bit input: Clock enable input for ADREG + .CEALUMODE('0), // 1-bit input: Clock enable input for ALUMODERE + .CEB1('0), // 1-bit input: Clock enable input for 1st stage BREG + .CEB2(en), // 1-bit input: Clock enable input for 2nd stage BREG + .CEC('0), // 1-bit input: Clock enable input for CREG + .CECARRYIN('0), // 1-bit input: Clock enable input for CARRYINREG + .CECTRL(en), // 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG + .CED('0), // 1-bit input: Clock enable input for DREG + .CEINMODE('0), // 1-bit input: Clock enable input for INMODEREG + .CEM(en), // 1-bit input: Clock enable input for MREG + .CEP(en), // 1-bit input: Clock enable input for PREG + .RSTA('0), // 1-bit input: Reset input for AREG + .RSTB( // 1-bit input: Reset for BREG +// synthesis translate_off + rst || +// synthesis translate_on + zero + ), + .RSTC('0), // 1-bit input: Reset for CREG + .RSTD( // 1-bit input: Reset for DREG and ADREG +// synthesis translate_off + zero || +// synthesis translate_on + rst + ), + .RSTALLCARRYIN('0), // 1-bit input: Reset for CARRYINREG + .RSTALUMODE('0), // 1-bit input: Reset for ALUMODEREG + .RSTCTRL('0), // 1-bit input: Reset for OPMODEREG and CARRYINSELREG + .RSTINMODE('0), // 1-bit input: Reset for INMODE register + .RSTM(rst), // 1-bit input: Reset for MREG + .RSTP(rst) // 1-bit input: Reset for PREG + ); + 2: DSP48E2 #( + // Feature Control Attributes: Data Path Selection + .AMULTSEL("AD"), // Selects A input to multiplier (A, AD) + .A_INPUT("DIRECT"), // Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + .BMULTSEL("B"), // Selects B input to multiplier (AD, B) + .B_INPUT("DIRECT"), // Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + .PREADDINSEL("A"), // Selects input to pre-adder (A, B) + .RND('0), // Rounding Constant + .USE_MULT("MULTIPLY"), // Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + .USE_SIMD("ONE48"), // SIMD selection (FOUR12, ONE58, TWO24) + .USE_WIDEXOR("FALSE"), // Use the Wide XOR function (FALSE, TRUE) + .XORSIMD("XOR24_48_96"), // Mode of operation for the Wide XOR (XOR12_22, XOR24_34_58_116) + + // Pattern Detector Attributes: Pattern Detection Configuration + .AUTORESET_PATDET("NO_RESET"), // NO_RESET, RESET_MATCH, RESET_NOT_MATCH + .AUTORESET_PRIORITY("RESET"), // Priority of AUTORESET vs. CEP (CEP, RESET). + .MASK('1), // 58-bit mask value for pattern detect (1=ignore) + .PATTERN('0), // 58-bit pattern match for pattern detect + .SEL_MASK("MASK"), // C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + .SEL_PATTERN("PATTERN"), // Select pattern value (C, PATTERN) + .USE_PATTERN_DETECT("NO_PATDET"), // Enable pattern detect (NO_PATDET, PATDET) + + // Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + .IS_ALUMODE_INVERTED('0), // Optional inversion for ALUMODE + .IS_CARRYIN_INVERTED('0), // Optional inversion for CARRYIN + .IS_CLK_INVERTED('0), // Optional inversion for CLK + .IS_INMODE_INVERTED('0), // Optional inversion for INMODE + .IS_OPMODE_INVERTED({ 2'b00, OPMODE_INVERSION}), // Optional inversion for OPMODE + .IS_RSTALLCARRYIN_INVERTED('0), // Optional inversion for RSTALLCARRYIN + .IS_RSTALUMODE_INVERTED('0), // Optional inversion for RSTALUMODE + .IS_RSTA_INVERTED('0), // Optional inversion for RSTA + .IS_RSTB_INVERTED('0), // Optional inversion for RSTB + .IS_RSTCTRL_INVERTED('0), // Optional inversion for STCONJUGATE_A + .IS_RSTC_INVERTED('0), // Optional inversion for RSTC + .IS_RSTD_INVERTED('0), // Optional inversion for RSTD + .IS_RSTINMODE_INVERTED('0), // Optional inversion for RSTINMODE + .IS_RSTM_INVERTED('0), // Optional inversion for RSTM + .IS_RSTP_INVERTED('0), // Optional inversion for RSTP + + // Register Control Attributes: Pipeline Register Configuration + .ACASCREG(0), // Number of pipeline stages between A/ACIN and ACOUT (0-2) + .ADREG(1), // Pipeline stages for pre-adder (0-1) + .ALUMODEREG(0), // Pipeline stages for ALUMODE (0-1) + .AREG(0), // Pipeline stages for A (0-2) + .BCASCREG(1), // Number of pipeline stages between B/BCIN and BCOUT (0-2) + .BREG(1), // Pipeline stages for B (0-2) + .CARRYINREG(0), // Pipeline stages for CARRYIN (0-1) + .CARRYINSELREG(0), // Pipeline stages for CARRYINSEL (0-1) + .CREG(0), // Pipeline stages for C (0-1) + .DREG(0), // Pipeline stages for D (0-1) + .INMODEREG(0), // Pipeline stages for INMODE (0-1) + .MREG(1), // Multiplier pipeline stages (0-1) + .OPMODEREG(1), // Pipeline stages for OPMODE (0-1) + .PREG(1) // Number of pipeline stages for P (0-1) + ) dsp ( + // Cascade outputs: Cascade Ports + .ACOUT(), // 34-bit output: A port cascade + .BCOUT(), // 24-bit output: B cascade + .CARRYCASCOUT(), // 1-bit output: Cascade carry + .MULTSIGNOUT(), // 1-bit output: Multiplier sign cascade + .PCOUT(), // 58-bit output: Cascade output + + // Control outputs: Control Inputs/Status Bits + .OVERFLOW(), // 1-bit output: Overflow in add/acc + .PATTERNBDETECT(), // 1-bit output: Pattern bar detect + .PATTERNDETECT(), // 1-bit output: Pattern detect + .UNDERFLOW(), // 1-bit output: Underflow in add/acc + + // Data outputs: Data Ports + .CARRYOUT(), // 4-bit output: Carry + .P(pp), // 58-bit output: Primary data + .XOROUT(), // 8-bit output: XOR data + + // Cascade inputs: Cascade Ports + .ACIN('x), // 34-bit input: A cascade data + .BCIN('x), // 24-bit input: B cascade + .CARRYCASCIN('x), // 1-bit input: Cascade carry + .MULTSIGNIN('x), // 1-bit input: Multiplier sign cascade + .PCIN('x), // 58-bit input: P cascade + + // Control inputs: Control Inputs/Status Bits + .CLK(clk), // 1-bit input: Clock + .ALUMODE(4'h0), // 4-bit input: ALU control + .CARRYINSEL('0), // 3-bit input: Carry select + .INMODE(5'b01100), // 5-bit input: INMODE control + .OPMODE({ 2'b00, opmode }), // 9-bit input: Operation mode + + // Data inputs: Data Ports + .A(aa), // 34-bit input: A data + .B(bb), // 24-bit input: B data + .C('x), // 58-bit input: C data + .CARRYIN('0), // 1-bit input: Carry-in + .D(dd), // 27-bit input: D data + + // Reset/Clock Enable inputs: Reset/Clock Enable Inputs + .CEA1('0), // 1-bit input: Clock enable for 1st stage AREG + .CEA2('0), // 1-bit input: Clock enable for 2nd stage AREG + .CEAD(en), // 1-bit input: Clock enable for ADREG + .CEALUMODE('0), // 1-bit input: Clock enable for ALUMODE + .CEB1('0), // 1-bit input: Clock enable for 1st stage BREG + .CEB2(en), // 1-bit input: Clock enable for 2nd stage BREG + .CEC('0), // 1-bit input: Clock enable for CREG + .CECARRYIN('0), // 1-bit input: Clock enable for CARRYINREG + .CECTRL(en), // 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + .CED('0), // 1-bit input: Clock enable for DREG + .CEINMODE('0), // 1-bit input: Clock enable for INMODEREG + .CEM(en), // 1-bit input: Clock enable for MREG + .CEP(en), // 1-bit input: Clock enable for PREG + .RSTA('0), // 1-bit input: Reset for AREG + .RSTB( // 1-bit input: Reset for BREG +// synthesis translate_off + rst || +// synthesis translate_on + zero + ), + .RSTC('0), // 1-bit input: Reset for CREG + .RSTD( // 1-bit input: Reset for DREG and ADREG +// synthesis translate_off + zero || +// synthesis translate_on + rst + ), + .RSTALLCARRYIN('0), // 1-bit input: Reset for CARRYINREG + .RSTALUMODE('0), // 1-bit input: Reset for ALUMODEREG + .RSTCTRL('0), // 1-bit input: Reset for OPMODEREG and CARRYINSELREG + .RSTINMODE('0), // 1-bit input: Reset for INMODE register + .RSTM(rst), // 1-bit input: Reset for MREG + .RSTP(rst) // 1-bit input: Reset for PREG + ); + default: initial begin + $error("Unknown version DSP48E%0d.", VERSION); + $finish; + end + endcase + end : genDSP +`endif + + // External Canary Pipeline + logic [1:0] X1[3:1] = '{ default: 0 }; + logic [1:0] X2[3:1] = '{ default: 0 }; + logic [1:0] X3[3:1] = '{ default: 0 }; + always_ff @(posedge clk) begin + if(rst) begin + X1 <= '{ default: 0 }; + X2 <= '{ default: 0 }; + X3 <= '{ default: 0 }; + end + else if(en) begin + X1 <= xx; + X2 <= X1; + foreach(X3[i]) begin + X3[i] <= X2[i] + (L[3]? 2'h0 : pp[D[i]+:2]); + end + end + end + + // Derive actual cross-lane overflows + for(genvar i = 0; i < 3; i++) begin + assign h3[s][i] = pp[D[i+1]+:2] - X3[i+1]; + end + assign p3[s] = pp; + + end : genSIMD + + // Stage #4: Cross-SIMD Reduction + + // Count leaves reachable from each node + localparam leave_load_t LEAVE_LOAD = SIMD > 1 ? init_leave_loads() : '{ default: 1}; // SIMD=1 requires no adder tree, so zero-ing out, otherwise init_leave_loads ends up in infinite loop + + uwire signed [ACCU_WIDTH -1:0] up4; + uwire signed [ACCU_WIDTH -8:0] hi4[3]; + uwire [$clog2(SIMD)+7:0] lo4[3]; + for(genvar i = 0; i < 4; i++) begin + localparam int unsigned LO_WIDTH = D[i+1] - D[i]; + localparam int unsigned HI_WIDTH = ACCU_WIDTH - LO_WIDTH; + + // Conclusive high part accumulation + if(i >= PE_REM && i < 3) begin : genHi + // Adder Tree across all SIMD high contributions, each from [-1:1] + uwire signed [2*SIMD-2:0][$clog2(1+SIMD):0] tree; + for(genvar s = 0; s < SIMD; s++) assign tree[SIMD-1+s] = h3[s][i]; + for(genvar n = 0; n < SIMD-1; n++) begin + // Sum truncated to actual maximum bit width at this node + uwire signed [$clog2(1+LEAVE_LOAD[n]):0] s = $signed(tree[2*n+1]) + $signed(tree[2*n+2]); + assign tree[n] = s; + end + + // High Sideband Accumulation + logic signed [HI_WIDTH-1:0] Hi4 = 0; + always_ff @(posedge clk) begin + if(rst) Hi4 <= 0; + else if(en) Hi4 <= (L[4]? 0 : Hi4) + $signed(tree[0]); + end + assign hi4[i] = Hi4; + end : genHi + else if (i < 3) begin : genHiZero + assign hi4[i] = '0; + end : genHiZero + + // Conclusive low part accumulation + if(i >= PE_REM) begin : blkLo + // Adder Tree across all SIMD low contributions + localparam int unsigned ROOT_WIDTH = $clog2(1 + SIMD*(2**LO_WIDTH-1)); + uwire [2*SIMD-2:0][ROOT_WIDTH-1:0] tree; + for(genvar s = 0; s < SIMD; s++) assign tree[SIMD-1+s] = p3[s][D[i]+:LO_WIDTH]; + for(genvar n = 0; n < SIMD-1; n++) begin + // Sum truncated to actual maximum bit width at this node + localparam int unsigned NODE_WIDTH = $clog2(1 + LEAVE_LOAD[n]*(2**LO_WIDTH-1)); + uwire [NODE_WIDTH-1:0] s = $signed(tree[2*n+1]) + $signed(tree[2*n+2]); + assign tree[n] = s; + end + + logic [ROOT_WIDTH-1:0] Lo4 = 0; + always_ff @(posedge clk) begin + if(rst) Lo4 <= 0; + else if(en) Lo4 <= tree[0]; + end + + if(i == 3) assign up4 = Lo4; + else assign lo4[i] = Lo4; + end : blkLo + else begin : blkLoZero + assign lo4[i] = '0; + end : blkLoZero + + end + + // Stage #5: Resolve lane totals + logic signed [3:0][ACCU_WIDTH-1:0] Res5 = '{ default: 0 }; + always_ff @(posedge clk) begin + if(rst) Res5 <= '{ default: 0 }; + else if(en) begin + Res5[3] <= up4 - hi4[2]; + Res5[2] <= $signed({ hi4[2], {(D[3] - D[2]){1'b0}} }) + $signed({ 1'b0, lo4[2] }) - hi4[1]; + Res5[1] <= $signed({ hi4[1], {(D[2] - D[1]){1'b0}} }) + $signed({ 1'b0, lo4[1] }) - hi4[0]; + Res5[0] <= $signed({ hi4[0], {(D[1] - D[0]){1'b0}} }) + $signed({ 1'b0, lo4[0] }); + end + end + + // Output + for(genvar pe = PE_BEG; pe < PE_END; pe++) begin + assign p[pe] = Res5[pe - PE_BEG + PE_REM]; + end + + end : genPipes + +endmodule : mvu_4sx4u diff --git a/finn-rtllib/mvu/mvu_8sx8u_dsp48.sv b/finn-rtllib/mvu/mvu_8sx8u_dsp48.sv new file mode 100644 index 0000000000..1423153c97 --- /dev/null +++ b/finn-rtllib/mvu/mvu_8sx8u_dsp48.sv @@ -0,0 +1,492 @@ +module mvu_8sx8u_dsp48 #( + int unsigned PE, + int unsigned SIMD, + int unsigned ACCU_WIDTH, + int unsigned ACTIVATION_WIDTH, + int unsigned WEIGHT_WIDTH, + + int unsigned VERSION = 1, + bit SIGNED_ACTIVATIONS = 0, + bit FORCE_BEHAVIORAL = 0 +)( + // Global Control + input logic clk, + input logic rst, + input logic en, + + // Input + input logic last, + input logic zero, // ignore current inputs and force this partial product to zero + input logic signed [PE-1:0][SIMD-1:0][WEIGHT_WIDTH -1:0] w, // signed weights + input logic [SIMD-1:0][ACTIVATION_WIDTH-1:0] a, // unsigned activations (override by SIGNED_ACTIVATIONS) + + // Ouput + output logic vld, + output logic signed [PE-1:0][ACCU_WIDTH-1:0] p +); + // for verilator always use behavioral code + localparam bit BEHAVIORAL = +`ifdef VERILATOR + 1 || +`endif + FORCE_BEHAVIORAL; + + typedef int unsigned leave_load_t[2*SIMD-1]; + function leave_load_t init_leave_loads(); + automatic leave_load_t res; + for(int i = 2*(SIMD-1); i >= int'(SIMD)-1; i--) res[i] = 1; + for(int i = SIMD-2; i >= 0; i--) res[i] = res[2*i+1] + res[2*i+2]; + return res; + endfunction : init_leave_loads + + // Pipeline for last indicator flag + logic [1:5] L = '0; + always_ff @(posedge clk) begin + if(rst) L <= '0; + else if(en) L <= { last, L[1:4] }; + end + assign vld = L[5]; + + // Stages #1 - #3: DSP Lanes + cross-lane canaries duplicated with SIMD parallelism + localparam int unsigned SINGLE_PROD_WIDTH = ACTIVATION_WIDTH+WEIGHT_WIDTH; + localparam int unsigned D[2:0] = '{ ACCU_WIDTH+SINGLE_PROD_WIDTH, SINGLE_PROD_WIDTH, 0 }; // Lane offsets + + localparam int unsigned PIPE_COUNT = (PE+1)/2; + for(genvar c = 0; c < PIPE_COUNT; c++) begin : genPipes + + localparam int unsigned PE_BEG = 2*c; + localparam int unsigned PE_END = PE < 2*(c+1)? PE : 2*(c+1); + localparam int unsigned PE_REM = 2*(c+1) - PE_END; + + uwire [57:0] p3[SIMD]; + uwire signed [ 1:0] h3[SIMD]; + for(genvar s = 0; s < SIMD; s++) begin : genSIMD + + // Input Lane Assembly + uwire [17:0] bb = { {(18-ACTIVATION_WIDTH){SIGNED_ACTIVATIONS && a[s][ACTIVATION_WIDTH-1]}}, a[s] }; + logic [29:0] aa; + logic [26:0] dd; + logic [ 1:0] xx; + if(1) begin : blkVectorize + uwire [WEIGHT_WIDTH-1:0] ww[PE_END - PE_BEG]; + for(genvar pe = 0; pe < PE_END - PE_BEG; pe++) begin + assign ww[pe] = w[PE_BEG + pe][s]; + if(pe) begin + if(BEHAVIORAL) assign xx = zero? 0 : ww[pe] * a[s]; +`ifndef VERILATOR + else begin + LUT6_2 #(.INIT(64'h0000_6AC0_0000_8888)) lut_x ( + .O6(xx[1]), + .O5(xx[0]), + .I5(1'b1), + .I4(zero), + .I3(ww[pe][1]), + .I2(a[s][1]), + .I1(ww[pe][0]), + .I0(a[s][0]) + ); + end +`endif + end + end + always_comb begin + dd = '0; + aa = '0; + for(int unsigned pe = 0; pe < PE_END - PE_BEG; pe++) begin + dd[D[pe + PE_REM] +: WEIGHT_WIDTH-1] = ww[pe]; + aa[D[pe + PE_REM] + WEIGHT_WIDTH-1] = ww[pe][WEIGHT_WIDTH-1]; + end + end + end : blkVectorize + + uwire [47:0] pp; + + // Note: Since the product B * AD is computed, + // rst can be only applied to AD and zero only to B + // with the same effect as zeroing both. + if(BEHAVIORAL) begin : genBehav + // Stage #1: Input Refine + logic signed [17:0] B1 = 0; + always_ff @(posedge clk) begin + if(zero) B1 <= 0; + else if(en) B1 <= bb; + end + + logic signed [26:0] AD1 = 0; + always_ff @(posedge clk) begin + if(rst) AD1 <= 0; + else if(en) AD1 <= dd - aa; + end + + // Stage #2: Multiply + logic signed [45:0] M2 = 0; + always_ff @(posedge clk) begin + if(rst) M2 <= 0; + else if(en) M2 <= +// synthesis translate off + (B1 === '0) || (AD1 === '0)? 0 : +// synthesis translate on + B1 * AD1; + end + + // Stage #3: Accumulate + logic signed [47:0] P3 = 0; + always_ff @(posedge clk) begin + if(rst) P3 <= 0; + else if(en) P3 <= M2 + (L[3]? 0 : P3); + end + + assign pp = P3; + end : genBehav +`ifndef VERILATOR + else begin : genDSP + localparam logic [6:0] OPMODE_INVERSION = 7'b010_01_01; + uwire [6:0] opmode = { { 1'b0, L[2], 1'b0 }, 4'b00_00 }; + case(VERSION) + 1: DSP48E1 #( + // Feature Control Attributes: Data Path Selection + .A_INPUT("DIRECT"), // Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + .B_INPUT("DIRECT"), // Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + .USE_DPORT("TRUE"), // Select D port usage (TRUE or FALSE) + .USE_MULT("MULTIPLY"), // Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE") + .USE_SIMD("ONE48"), // SIMD selection ("ONE48", "TWO24", "FOUR12") + + // Pattern Detector Attributes: Pattern Detection Configuration + .AUTORESET_PATDET("NO_RESET"), // "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH" + .MASK('1), // 48-bit mask value for pattern detect (1=ignore) + .PATTERN('0), // 48-bit pattern match for pattern detect + .SEL_MASK("MASK"), // "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2" + .SEL_PATTERN("PATTERN"), // Select pattern value ("PATTERN" or "C") + .USE_PATTERN_DETECT("NO_PATDET"), // Enable pattern detect ("PATDET" or "NO_PATDET") + + // Register Control Attributes: Pipeline Register Configuration + .ACASCREG(0), // Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2) + .ADREG(1), // Number of pipeline stages for pre-adder (0 or 1) + .ALUMODEREG(0), // Number of pipeline stages for ALUMODE (0 or 1) + .AREG(0), // Number of pipeline stages for A (0, 1 or 2) + .BCASCREG(1), // Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2) + .BREG(1), // Number of pipeline stages for B (0, 1 or 2) + .CARRYINREG(0), // Number of pipeline stages for CARRYIN (0 or 1) + .CARRYINSELREG(0), // Number of pipeline stages for CARRYINSEL (0 or 1) + .CREG(0), // Number of pipeline stages for C (0 or 1) + .DREG(0), // Number of pipeline stages for D (0 or 1) + .INMODEREG(0), // Number of pipeline stages for INMODE (0 or 1) + .MREG(1), // Number of multiplier pipeline stages (0 or 1) + .OPMODEREG(1), // Number of pipeline stages for OPMODE (0 or 1) + .PREG(1) // Number of pipeline stages for P (0 or 1) + ) dsp ( + // Cascade: 30-bit (each) output: Cascade Ports + .ACOUT(), // 30-bit output: A port cascade output + .BCOUT(), // 18-bit output: B port cascade output + .CARRYCASCOUT(), // 1-bit output: Cascade carry output + .MULTSIGNOUT(), // 1-bit output: Multiplier sign cascade output + .PCOUT(), // 48-bit output: Cascade output + + // Control: 1-bit (each) output: Control Inputs/Status Bits + .OVERFLOW(), // 1-bit output: Overflow in add/acc output + .PATTERNBDETECT(), // 1-bit output: Pattern bar detect output + .PATTERNDETECT(), // 1-bit output: Pattern detect output + .UNDERFLOW(), // 1-bit output: Underflow in add/acc output + + // Data: 4-bit (each) output: Data Ports + .CARRYOUT(), // 4-bit output: Carry output + .P(pp), // 48-bit output: Primary data output + + // Cascade: 30-bit (each) input: Cascade Ports + .ACIN('x), // 30-bit input: A cascade data input + .BCIN('x), // 18-bit input: B cascade input + .CARRYCASCIN('x), // 1-bit input: Cascade carry input + .MULTSIGNIN('x), // 1-bit input: Multiplier sign input + .PCIN('x), // 48-bit input: P cascade input + + // Control: 4-bit (each) input: Control Inputs/Status Bits + .CLK(clk), // 1-bit input: Clock input + .ALUMODE('0), // 4-bit input: ALU control input + .CARRYINSEL('0), // 3-bit input: Carry select input + .INMODE(5'b01100), // 5-bit input: INMODE control input + .OPMODE(opmode ^ OPMODE_INVERSION), // 7-bit input: Operation mode input + + // Data: 30-bit (each) input: Data Ports + .A(aa), // 30-bit input: A data input + .B(bb), // 18-bit input: B data input + .C('x), // 48-bit input: C data input + .CARRYIN('0), // 1-bit input: Carry input signal + .D(dd), // 25-bit input: D data input + + // Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs + .CEA1('0), // 1-bit input: Clock enable input for 1st stage AREG + .CEA2('0), // 1-bit input: Clock enable input for 2nd stage AREG + .CEAD(en), // 1-bit input: Clock enable input for ADREG + .CEALUMODE('0), // 1-bit input: Clock enable input for ALUMODERE + .CEB1('0), // 1-bit input: Clock enable input for 1st stage BREG + .CEB2(en), // 1-bit input: Clock enable input for 2nd stage BREG + .CEC('0), // 1-bit input: Clock enable input for CREG + .CECARRYIN('0), // 1-bit input: Clock enable input for CARRYINREG + .CECTRL(en), // 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG + .CED('0), // 1-bit input: Clock enable input for DREG + .CEINMODE('0), // 1-bit input: Clock enable input for INMODEREG + .CEM(en), // 1-bit input: Clock enable input for MREG + .CEP(en), // 1-bit input: Clock enable input for PREG + .RSTA('0), // 1-bit input: Reset input for AREG + .RSTB( // 1-bit input: Reset for BREG +// synthesis translate_off + rst || +// synthesis translate_on + zero + ), + .RSTC('0), // 1-bit input: Reset for CREG + .RSTD( // 1-bit input: Reset for DREG and ADREG +// synthesis translate_off + zero || +// synthesis translate_on + rst + ), + .RSTALLCARRYIN('0), // 1-bit input: Reset for CARRYINREG + .RSTALUMODE('0), // 1-bit input: Reset for ALUMODEREG + .RSTCTRL('0), // 1-bit input: Reset for OPMODEREG and CARRYINSELREG + .RSTINMODE('0), // 1-bit input: Reset for INMODE register + .RSTM(rst), // 1-bit input: Reset for MREG + .RSTP(rst) // 1-bit input: Reset for PREG + ); + 2: DSP48E2 #( + // Feature Control Attributes: Data Path Selection + .AMULTSEL("AD"), // Selects A input to multiplier (A, AD) + .A_INPUT("DIRECT"), // Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + .BMULTSEL("B"), // Selects B input to multiplier (AD, B) + .B_INPUT("DIRECT"), // Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + .PREADDINSEL("A"), // Selects input to pre-adder (A, B) + .RND('0), // Rounding Constant + .USE_MULT("MULTIPLY"), // Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + .USE_SIMD("ONE48"), // SIMD selection (FOUR12, ONE58, TWO24) + .USE_WIDEXOR("FALSE"), // Use the Wide XOR function (FALSE, TRUE) + .XORSIMD("XOR24_48_96"), // Mode of operation for the Wide XOR (XOR12_22, XOR24_34_58_116) + + // Pattern Detector Attributes: Pattern Detection Configuration + .AUTORESET_PATDET("NO_RESET"), // NO_RESET, RESET_MATCH, RESET_NOT_MATCH + .AUTORESET_PRIORITY("RESET"), // Priority of AUTORESET vs. CEP (CEP, RESET). + .MASK('1), // 58-bit mask value for pattern detect (1=ignore) + .PATTERN('0), // 58-bit pattern match for pattern detect + .SEL_MASK("MASK"), // C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + .SEL_PATTERN("PATTERN"), // Select pattern value (C, PATTERN) + .USE_PATTERN_DETECT("NO_PATDET"), // Enable pattern detect (NO_PATDET, PATDET) + + // Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + .IS_ALUMODE_INVERTED('0), // Optional inversion for ALUMODE + .IS_CARRYIN_INVERTED('0), // Optional inversion for CARRYIN + .IS_CLK_INVERTED('0), // Optional inversion for CLK + .IS_INMODE_INVERTED('0), // Optional inversion for INMODE + .IS_OPMODE_INVERTED({ 2'b00, OPMODE_INVERSION}), // Optional inversion for OPMODE + .IS_RSTALLCARRYIN_INVERTED('0), // Optional inversion for RSTALLCARRYIN + .IS_RSTALUMODE_INVERTED('0), // Optional inversion for RSTALUMODE + .IS_RSTA_INVERTED('0), // Optional inversion for RSTA + .IS_RSTB_INVERTED('0), // Optional inversion for RSTB + .IS_RSTCTRL_INVERTED('0), // Optional inversion for STCONJUGATE_A + .IS_RSTC_INVERTED('0), // Optional inversion for RSTC + .IS_RSTD_INVERTED('0), // Optional inversion for RSTD + .IS_RSTINMODE_INVERTED('0), // Optional inversion for RSTINMODE + .IS_RSTM_INVERTED('0), // Optional inversion for RSTM + .IS_RSTP_INVERTED('0), // Optional inversion for RSTP + + // Register Control Attributes: Pipeline Register Configuration + .ACASCREG(0), // Number of pipeline stages between A/ACIN and ACOUT (0-2) + .ADREG(1), // Pipeline stages for pre-adder (0-1) + .ALUMODEREG(0), // Pipeline stages for ALUMODE (0-1) + .AREG(0), // Pipeline stages for A (0-2) + .BCASCREG(1), // Number of pipeline stages between B/BCIN and BCOUT (0-2) + .BREG(1), // Pipeline stages for B (0-2) + .CARRYINREG(0), // Pipeline stages for CARRYIN (0-1) + .CARRYINSELREG(0), // Pipeline stages for CARRYINSEL (0-1) + .CREG(0), // Pipeline stages for C (0-1) + .DREG(0), // Pipeline stages for D (0-1) + .INMODEREG(0), // Pipeline stages for INMODE (0-1) + .MREG(1), // Multiplier pipeline stages (0-1) + .OPMODEREG(1), // Pipeline stages for OPMODE (0-1) + .PREG(1) // Number of pipeline stages for P (0-1) + ) dsp ( + // Cascade outputs: Cascade Ports + .ACOUT(), // 34-bit output: A port cascade + .BCOUT(), // 24-bit output: B cascade + .CARRYCASCOUT(), // 1-bit output: Cascade carry + .MULTSIGNOUT(), // 1-bit output: Multiplier sign cascade + .PCOUT(), // 58-bit output: Cascade output + + // Control outputs: Control Inputs/Status Bits + .OVERFLOW(), // 1-bit output: Overflow in add/acc + .PATTERNBDETECT(), // 1-bit output: Pattern bar detect + .PATTERNDETECT(), // 1-bit output: Pattern detect + .UNDERFLOW(), // 1-bit output: Underflow in add/acc + + // Data outputs: Data Ports + .CARRYOUT(), // 4-bit output: Carry + .P(pp), // 58-bit output: Primary data + .XOROUT(), // 8-bit output: XOR data + + // Cascade inputs: Cascade Ports + .ACIN('x), // 34-bit input: A cascade data + .BCIN('x), // 24-bit input: B cascade + .CARRYCASCIN('x), // 1-bit input: Cascade carry + .MULTSIGNIN('x), // 1-bit input: Multiplier sign cascade + .PCIN('x), // 58-bit input: P cascade + + // Control inputs: Control Inputs/Status Bits + .CLK(clk), // 1-bit input: Clock + .ALUMODE(4'h0), // 4-bit input: ALU control + .CARRYINSEL('0), // 3-bit input: Carry select + .INMODE(5'b01100), // 5-bit input: INMODE control + .OPMODE({ 2'b00, opmode }), // 9-bit input: Operation mode + + // Data inputs: Data Ports + .A(aa), // 34-bit input: A data + .B(bb), // 24-bit input: B data + .C('x), // 58-bit input: C data + .CARRYIN('0), // 1-bit input: Carry-in + .D(dd), // 27-bit input: D data + + // Reset/Clock Enable inputs: Reset/Clock Enable Inputs + .CEA1('0), // 1-bit input: Clock enable for 1st stage AREG + .CEA2('0), // 1-bit input: Clock enable for 2nd stage AREG + .CEAD(en), // 1-bit input: Clock enable for ADREG + .CEALUMODE('0), // 1-bit input: Clock enable for ALUMODE + .CEB1('0), // 1-bit input: Clock enable for 1st stage BREG + .CEB2(en), // 1-bit input: Clock enable for 2nd stage BREG + .CEC('0), // 1-bit input: Clock enable for CREG + .CECARRYIN('0), // 1-bit input: Clock enable for CARRYINREG + .CECTRL(en), // 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + .CED('0), // 1-bit input: Clock enable for DREG + .CEINMODE('0), // 1-bit input: Clock enable for INMODEREG + .CEM(en), // 1-bit input: Clock enable for MREG + .CEP(en), // 1-bit input: Clock enable for PREG + .RSTA('0), // 1-bit input: Reset for AREG + .RSTB( // 1-bit input: Reset for BREG +// synthesis translate_off + rst || +// synthesis translate_on + zero + ), + .RSTC('0), // 1-bit input: Reset for CREG + .RSTD( // 1-bit input: Reset for DREG and ADREG +// synthesis translate_off + zero || +// synthesis translate_on + rst + ), + .RSTALLCARRYIN('0), // 1-bit input: Reset for CARRYINREG + .RSTALUMODE('0), // 1-bit input: Reset for ALUMODEREG + .RSTCTRL('0), // 1-bit input: Reset for OPMODEREG and CARRYINSELREG + .RSTINMODE('0), // 1-bit input: Reset for INMODE register + .RSTM(rst), // 1-bit input: Reset for MREG + .RSTP(rst) // 1-bit input: Reset for PREG + ); + default: initial begin + $error("Unknown version DSP48E%0d.", VERSION); + $finish; + end + endcase + end : genDSP +`endif + + // External Canary Pipeline + logic [1:0] X1 = '{ default: 0 }; + logic [1:0] X2 = '{ default: 0 }; + logic [1:0] X3 = '{ default: 0 }; + always_ff @(posedge clk) begin + if(rst) begin + X1 <= '{ default: 0 }; + X2 <= '{ default: 0 }; + X3 <= '{ default: 0 }; + end + else if(en) begin + X1 <= xx; + X2 <= X1; + X3 <= X2 + (L[3]? 2'h0 : pp[D[1]+:2]); + end + end + + // Derive actual cross-lane overflows + assign h3[s] = pp[D[1]+:2] - X3; + + assign p3[s] = pp; + + end : genSIMD + + // Stage #4: Cross-SIMD Reduction + + // Count leaves reachable from each node + localparam leave_load_t LEAVE_LOAD = SIMD > 1 ? init_leave_loads() : '{ default: 0}; // SIMD=1 requires no adder tree, so zero-ing out, otherwise init_leave_loads ends up in infinite loop + + uwire signed [ACCU_WIDTH -1:0] up4; + uwire signed [ACCU_WIDTH -SINGLE_PROD_WIDTH:0] hi4; + uwire [$clog2(SIMD)+SINGLE_PROD_WIDTH-1:0] lo4; + + // Conclusive high part accumulation + if(PE_REM == 0) begin : genHi + localparam int unsigned HI_WIDTH = ACCU_WIDTH - D[1]; + // Adder Tree across all SIMD high contributions, each from [-1:1] + uwire signed [2*SIMD-2:0][$clog2(1+SIMD):0] tree; + for(genvar s = 0; s < SIMD; s++) assign tree[SIMD-1+s] = h3[s]; + for(genvar n = 0; n < SIMD-1; n++) begin + // Sum truncated to actual maximum bit width at this node + uwire signed [$clog2(1+LEAVE_LOAD[n]):0] s = $signed(tree[2*n+1]) + $signed(tree[2*n+2]); + assign tree[n] = s; + end + + // High Sideband Accumulation + logic signed [HI_WIDTH-1:0] Hi4 = 0; + always_ff @(posedge clk) begin + if(rst) Hi4 <= 0; + else if(en) Hi4 <= (L[4]? 0 : Hi4) + $signed(tree[0]); + end + assign hi4 = Hi4; + end : genHi + else begin : genHiZero + assign hi4 = '0; + end : genHiZero + + for(genvar i = 0; i < 2; i++) begin + localparam int unsigned LO_WIDTH = D[i+1] - D[i]; + // Conclusive low part accumulation + if(i >= PE_REM) begin : blkLo + // Adder Tree across all SIMD low contributions + localparam int unsigned ROOT_WIDTH = $clog2(1 + SIMD*(2**LO_WIDTH-1)); + uwire [2*SIMD-2:0][ROOT_WIDTH-1:0] tree; + for(genvar s = 0; s < SIMD; s++) assign tree[SIMD-1+s] = p3[s][D[i]+:LO_WIDTH]; + for(genvar n = 0; n < SIMD-1; n++) begin + // Sum truncated to actual maximum bit width at this node + localparam int unsigned NODE_WIDTH = $clog2(1 + LEAVE_LOAD[n]*(2**LO_WIDTH-1)); + uwire [NODE_WIDTH-1:0] s = $signed(tree[2*n+1]) + $signed(tree[2*n+2]); + assign tree[n] = s; + end + + logic [ROOT_WIDTH-1:0] Lo4 = 0; + always_ff @(posedge clk) begin + if(rst) Lo4 <= 0; + else if(en) Lo4 <= tree[0]; + end + + if(i == 1) assign up4 = Lo4; + else assign lo4 = Lo4; + end : blkLo + else begin : blkLoZero + assign lo4 = '0; + end : blkLoZero + + end + + // Stage #5: Resolve lane totals + logic signed [1:0][ACCU_WIDTH-1:0] Res5 = '{ default: 0 }; + always_ff @(posedge clk) begin + if(rst) Res5 <= '{ default: 0 }; + else if(en) begin + Res5[1] <= up4 - hi4; + Res5[0] <= $signed({ hi4, {(D[1] - D[0]){1'b0}} }) + $signed({ 1'b0, lo4 }); + end + end + + // Output + for(genvar pe = PE_BEG; pe < PE_END; pe++) begin + assign p[pe] = Res5[pe - PE_BEG + PE_REM]; + end + + end : genPipes + +endmodule : mvu_8sx8u_dsp48 diff --git a/finn-rtllib/mvu/mvu_vvu_8sx9_dsp58.sv b/finn-rtllib/mvu/mvu_vvu_8sx9_dsp58.sv new file mode 100644 index 0000000000..53cf71fd5f --- /dev/null +++ b/finn-rtllib/mvu/mvu_vvu_8sx9_dsp58.sv @@ -0,0 +1,430 @@ +/****************************************************************************** + * Copyright (C) 2022, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * @brief Matrix Vector Unit (MVU) core compute kernel utilizing DSP58. + *****************************************************************************/ + +module mvu_vvu_8sx9_dsp58 #( + bit IS_MVU, + int unsigned PE, + int unsigned SIMD, + int unsigned ACTIVATION_WIDTH, + int unsigned WEIGHT_WIDTH, + int unsigned ACCU_WIDTH, + bit SIGNED_ACTIVATIONS = 0, + int unsigned SEGMENTLEN = 0, // Default to 0 (which implies a single segment) + bit FORCE_BEHAVIORAL = 0, + + localparam int unsigned ACTIVATION_ELEMENTS = (IS_MVU ? 1 : PE) * SIMD, + localparam int unsigned WEIGHT_ELEMENTS = PE*SIMD + ) + ( + // Global Control + input logic clk, + input logic rst, + input logic en, + + // Input + input logic last, + input logic zero, // ignore current inputs and force this partial product to zero + input logic [WEIGHT_ELEMENTS-1:0][WEIGHT_WIDTH-1:0] w, // weights + input logic [ACTIVATION_ELEMENTS-1:0][ACTIVATION_WIDTH-1:0] a, // activations + + // Ouput + output logic vld, + output logic [PE-1:0][ACCU_WIDTH-1:0] p + ); + // for verilator always use behavioral code + localparam bit BEHAVIORAL = +`ifdef VERILATOR + 1 || +`endif + FORCE_BEHAVIORAL; + +//-------------------- Declare global signals --------------------\\ + localparam int unsigned CHAINLEN = (SIMD+2)/3; + localparam int unsigned SEGLEN = SEGMENTLEN == 0 ? CHAINLEN : SEGMENTLEN; // Additional constant to default a SEGMENTLEN of '0' to the DSP-chain length + localparam int unsigned PE_ACTIVATION = IS_MVU ? 1 : PE; + uwire [26:0] a_in_i [PE_ACTIVATION * CHAINLEN]; + uwire [23:0] b_in_i [PE][CHAINLEN]; + uwire [PE-1:0][CHAINLEN-1:0][57:0] pcout; // Array with packed dimension > 256 (with a loop-carried dependency) cannot be handled out-of-the-box with PyVerilator + +//-------------------- Shift register for opmode select signal --------------------\\ + localparam int unsigned MAX_PIPELINE_STAGES = (CHAINLEN + SEGLEN-1)/SEGLEN; // >=1 (== number of pipeline registers + 1 (A/B inputs always have 1 register)) + logic L [0:1+MAX_PIPELINE_STAGES] = '{default: 0}; // After MAX_PIPELINE_STAGES (== number of pipeline stages for input data), we have 3 additional cycles latency (A/B reg, Mreg, Preg). Thus, we add +2 (since OPMODE is buffered by 1 cycle in the DSP fabric) + + always_ff @(posedge clk) begin + if(rst) L <= '{default: 0}; + else if(en) begin + L[1+MAX_PIPELINE_STAGES] <= last; + L[0:MAX_PIPELINE_STAGES] <= L[1:1+MAX_PIPELINE_STAGES]; + end + end + assign vld = L[0]; + +//-------------------- Shift register for ZERO flag --------------------\\ + logic Z [0:MAX_PIPELINE_STAGES-2] = '{default:0}; // We need MAX_PIPELINE_STAGES-1 pipeline stages (note: INMODE is buffered inside DSP fabric) + + if (MAX_PIPELINE_STAGES > 1) begin : genZreg + always_ff @(posedge clk) begin + if (rst) Z <= '{default: 0}; + else if(en) begin + Z[0] <= zero; + if (MAX_PIPELINE_STAGES > 2) Z[1:MAX_PIPELINE_STAGES-2] <= Z[0:MAX_PIPELINE_STAGES-3]; + end + end + end; + +//-------------------- Buffer for input activations --------------------\\ + localparam int unsigned PAD_BITS_ACT = 9 - ACTIVATION_WIDTH; + for (genvar k=0; k1 ? TOTAL_PREGS-1 : 0; + localparam int LANES_OCCUPIED = i == CHAINLEN-1 ? SIMD - 3*i : 3; + + if (EXTERNAL_PREGS > 0) begin : genExternalPregAct + logic [0:EXTERNAL_PREGS-1][LANES_OCCUPIED-1:0][ACTIVATION_WIDTH-1:0] A = '{ default : 0}; + always_ff @(posedge clk) begin + if (rst) A <= '{default: 0}; + else if(en) begin + A[EXTERNAL_PREGS-1] <= + // synthesis translate_off + zero ? '1 : + // synthesis translate_on + a[SIMD*k + 3*i +: LANES_OCCUPIED]; + if (EXTERNAL_PREGS > 1) A[0:EXTERNAL_PREGS-2] <= A[1:EXTERNAL_PREGS-1]; + end + end + for (genvar j=0; j1 ? TOTAL_PREGS-1 : 0; + localparam int LANES_OCCUPIED = j == CHAINLEN-1 ? SIMD - 3*j : 3; + + if (EXTERNAL_PREGS > 0) begin : genExternalPregWeight + logic [0:PE-1][0:EXTERNAL_PREGS-1][LANES_OCCUPIED-1:0][WEIGHT_WIDTH-1:0] B = '{ default : 0}; + always_ff @(posedge clk) begin + if (rst) B <= '{default: 0}; + else if (en) begin + B[i][EXTERNAL_PREGS-1] <= +// synthesis translate_off + zero ? '1 : +// synthesis translate_on + //w[i][3*j +: LANES_OCCUPIED]; + w[SIMD*i+3*j +: LANES_OCCUPIED]; + if (EXTERNAL_PREGS > 1) B[i][0:EXTERNAL_PREGS-2] <= B[i][1:EXTERNAL_PREGS-1]; + end + end + for (genvar k = 0 ; k < LANES_OCCUPIED ; k++) begin : genBin + assign b_in_i[i][j][8*k +: 8] = PAD_BITS_WEIGHT == 0 ? B[i][0][k] : { {PAD_BITS_WEIGHT{B[i][0][k][WEIGHT_WIDTH-1]}}, B[i][0][k] }; + end : genBin + for (genvar k=LANES_OCCUPIED; k<3; k++) begin : genBinZero + assign b_in_i[i][j][8*k +: 8] = 8'b0; + end : genBinZero + end : genExternalPregWeight + else begin : genInpDSPWeight + for (genvar k = 0; k < LANES_OCCUPIED; k++) begin : genBin + assign b_in_i[i][j][8*k +: 8] = +// synthesis translate_off + zero ? '1 : +// synthesis translate_on + //PAD_BITS_WEIGHT == 0 ? w[i][3*j+k] : { {PAD_BITS_WEIGHT{w[i][3*j+k][WEIGHT_WIDTH-1]}}, w[i][3*j+k] }; + PAD_BITS_WEIGHT == 0 ? w[SIMD*i+3*j+k] : { {PAD_BITS_WEIGHT{w[SIMD*i+3*j+k][WEIGHT_WIDTH-1]}}, w[SIMD*i+3*j+k] }; + end : genBin + for (genvar k=LANES_OCCUPIED; k<3; k++) begin : genBinZero + assign b_in_i[i][j][8*k +: 8] = 8'b0; + end : genBinZero + end : genInpDSPWeight + end : genWeightSIMD + end : genWeightPE + +//-------------------- Instantiate PE x CHAINLEN DSPs --------------------\\ + for (genvar i=0; i0 ? 2 : 1; // 1 : 0 + localparam bit PREG = (j+1)%SEGLEN==0 || j == CHAINLEN-1; + localparam bit FIRST = j == 0; + localparam bit LAST = j == CHAINLEN-1; + uwire [57:0] pp; + + if (LAST) begin : genPOUT + assign p[i] = pp[ACCU_WIDTH-1:0]; + end + + // Note: Since the product B * AD is computed, + // rst can be only applied to AD and zero only to B + // with the same effect as zeroing both. + if(BEHAVIORAL) begin : genBehav + // Stage #1: Input A/B + logic signed [33:0] Areg [INTERNAL_PREGS]; + always_ff @(posedge clk) begin + if (rst) Areg <= '{ default : 0}; + else if (en) begin + Areg[0] <= { 7'bx, a_in_i[(IS_MVU ? 0 : CHAINLEN*i) + j] }; + if (INTERNAL_PREGS == 2) Areg[1] <= Areg[0]; + end + end + logic signed [23:0] Breg [INTERNAL_PREGS]; + always_ff @(posedge clk) begin + if (rst) Breg <= '{ default : 0}; + else if (en) begin + Breg[0] <= b_in_i[i][j]; + if (INTERNAL_PREGS == 2) Breg[1] <= Breg[0]; + end + end + + // Stage #2: Multiply-Accumulate + logic signed [57:0] Mreg; + logic InmodeZero = 0; + always_ff @(posedge clk) begin + if (rst) InmodeZero <= 0; + else if (en) InmodeZero <= ( TOTAL_PREGS > 0 ? Z[TOTAL_PREGS-1] : zero ); + end + always_ff @(posedge clk) begin + if (rst) Mreg <= 0; + else if (en) begin + automatic logic signed [57:0] m = 0; + for (int k = 0; k < 3; k++) begin + m = m + (InmodeZero ? 0 : $signed(Areg[INTERNAL_PREGS-1][9*k +: 9]) * $signed(Breg[INTERNAL_PREGS-1][8*k +: 8])); + end + Mreg <= m; + end + end + + // Stage #3: Accumulate + logic signed [57:0] Preg; + logic Opmode = 0; + if (FIRST && !LAST) begin : genFirst + if (PREG) begin : genPregBehav + always_ff @(posedge clk) begin + if (rst) Preg <= 0; + else if (en) Preg <= Mreg; + end + end + else assign Preg = Mreg; + end + else if (FIRST && LAST) begin : genSingle + always_ff @(posedge clk) begin + if (rst) Opmode <= 0; + else if (en) Opmode <= L[1]; + end + always_ff @(posedge clk) begin + if (rst) Preg <= 0; + else if (en) Preg <= (Opmode ? 0 : Preg) + Mreg; + end + end + else if (!FIRST && LAST) begin : genLast + always_ff @(posedge clk) begin + if (rst) Opmode <= 0; + else if (en) Opmode <= L[1]; + end + always_ff @(posedge clk) begin + if (rst) Preg <= 0; + else if (en) Preg <= (Opmode ? 0 : Preg) + Mreg + pcout[i][j-1]; + end + end + else begin : genMid + if (PREG) begin : genPregBehav + always_ff @(posedge clk) begin + if (rst) Preg <= 0; + else if (en) Preg <= Mreg + pcout[i][j-1]; + end + end + else assign Preg = Mreg + pcout[i][j-1]; + end + assign pp = Preg; + assign pcout[i][j] = Preg; + end : genBehav +`ifndef VERILATOR + else begin: genDSP + DSP58 #( + // Feature Control Attributes: Data Path Selection + .AMULTSEL("A"), // Selects A input to multiplier (A, AD) + .A_INPUT("DIRECT"), // Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) + .BMULTSEL("B"), // Selects B input to multiplier (AD, B) + .B_INPUT("DIRECT"), // Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) + .DSP_MODE("INT8"), // Configures DSP to a particular mode of operation. Set to INT24 for + // legacy mode. + .PREADDINSEL("A"), // Selects input to pre-adder (A, B) + .RND(58'h000000000000000), // Rounding Constant + .USE_MULT("MULTIPLY"), // Select multiplier usage (DYNAMIC, MULTIPLY, NONE) + .USE_SIMD("ONE58"), // SIMD selection (FOUR12, ONE58, TWO24) + .USE_WIDEXOR("FALSE"), // Use the Wide XOR function (FALSE, TRUE) + .XORSIMD("XOR24_34_58_116"), // Mode of operation for the Wide XOR (XOR12_22, XOR24_34_58_116) + // Pattern Detector Attributes: Pattern Detection Configuration + .AUTORESET_PATDET("NO_RESET"), // NO_RESET, RESET_MATCH, RESET_NOT_MATCH + .AUTORESET_PRIORITY("RESET"), // Priority of AUTORESET vs. CEP (CEP, RESET). + .MASK(58'h0ffffffffffffff), // 58-bit mask value for pattern detect (1=ignore) + .PATTERN(58'h000000000000000), // 58-bit pattern match for pattern detect + .SEL_MASK("MASK"), // C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 + .SEL_PATTERN("PATTERN"), // Select pattern value (C, PATTERN) + .USE_PATTERN_DETECT("NO_PATDET"), // Enable pattern detect (NO_PATDET, PATDET) + // Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + .IS_ALUMODE_INVERTED(4'b0000), // Optional inversion for ALUMODE + .IS_CARRYIN_INVERTED(1'b0), // Optional inversion for CARRYIN + .IS_CLK_INVERTED(1'b0), // Optional inversion for CLK + .IS_INMODE_INVERTED(5'b00000), // Optional inversion for INMODE + .IS_NEGATE_INVERTED(3'b000), // Optional inversion for NEGATE + .IS_OPMODE_INVERTED({ LAST ? 2'b01 : 2'b00 , // W: LAST ? (L[1] ? 0 : P) : 0 + FIRST ? 3'b000 : 3'b001, // Z: FIRST ? 0 : PCIN + 2'b01, // Y : M + 2'b01 // X: M + }), // Optional inversion for OPMODE + .IS_RSTALLCARRYIN_INVERTED(1'b0), // Optional inversion for RSTALLCARRYIN + .IS_RSTALUMODE_INVERTED(1'b0), // Optional inversion for RSTALUMODE + .IS_RSTA_INVERTED(1'b0), // Optional inversion for RSTA + .IS_RSTB_INVERTED(1'b0), // Optional inversion for RSTB + .IS_RSTCTRL_INVERTED(1'b0), // Optional inversion for STCONJUGATE_A + .IS_RSTC_INVERTED(1'b0), // Optional inversion for RSTC + .IS_RSTD_INVERTED(1'b0), // Optional inversion for RSTD + .IS_RSTINMODE_INVERTED(1'b0), // Optional inversion for RSTINMODE + .IS_RSTM_INVERTED(1'b0), // Optional inversion for RSTM + .IS_RSTP_INVERTED(1'b0), // Optional inversion for RSTP + // Register Control Attributes: Pipeline Register Configuration + .ACASCREG(INTERNAL_PREGS), // Number of pipeline stages between A/ACIN and ACOUT (0-2) + .ADREG(0), // Pipeline stages for pre-adder (0-1) + .ALUMODEREG(0), // Pipeline stages for ALUMODE (0-1) + .AREG(INTERNAL_PREGS), // Pipeline stages for A (0-2) + .BCASCREG(INTERNAL_PREGS), // Number of pipeline stages between B/BCIN and BCOUT (0-2) + .BREG(INTERNAL_PREGS), // Pipeline stages for B (0-2) + .CARRYINREG(0), // Pipeline stages for CARRYIN (0-1) + .CARRYINSELREG(0), // Pipeline stages for CARRYINSEL (0-1) + .CREG(0), // Pipeline stages for C (0-1) + .DREG(0), // Pipeline stages for D (0-1) + .INMODEREG(1), // Pipeline stages for INMODE (0-1) + .MREG(1), // Multiplier pipeline stages (0-1) + .OPMODEREG(1), // Pipeline stages for OPMODE (0-1) + .PREG(PREG), // Number of pipeline stages for P (0-1) + .RESET_MODE("SYNC") // Selection of synchronous or asynchronous reset. (ASYNC, SYNC). + ) + DSP58_inst ( + // Cascade outputs: Cascade Ports + .ACOUT(), // 34-bit output: A port cascade + .BCOUT(), // 24-bit output: B cascade + .CARRYCASCOUT(), // 1-bit output: Cascade carry + .MULTSIGNOUT(), // 1-bit output: Multiplier sign cascade + .PCOUT(pcout[i][j]), // 58-bit output: Cascade output + // Control outputs: Control Inputs/Status Bits + .OVERFLOW(), // 1-bit output: Overflow in add/acc + .PATTERNBDETECT(), // 1-bit output: Pattern bar detect + .PATTERNDETECT(), // 1-bit output: Pattern detect + .UNDERFLOW(), // 1-bit output: Underflow in add/acc + // Data outputs: Data Ports + .CARRYOUT(), // 4-bit output: Carry + .P(pp), // 58-bit output: Primary data + .XOROUT(), // 8-bit output: XOR data + // Cascade inputs: Cascade Ports + .ACIN('x), // 34-bit input: A cascade data + .BCIN('x), // 24-bit input: B cascade + .CARRYCASCIN('x), // 1-bit input: Cascade carry + .MULTSIGNIN('x), // 1-bit input: Multiplier sign cascade + .PCIN(FIRST ? 'x : pcout[i][j-1]), // 58-bit input: P cascade + // Control inputs: Control Inputs/Status Bits + .ALUMODE(4'h0), // 4-bit input: ALU control + .CARRYINSEL('0), // 3-bit input: Carry select + .CLK(clk), // 1-bit input: Clock + .INMODE({ + INTERNAL_PREGS==2 ? 1'b0 : 1'b1, + 2'b00, + TOTAL_PREGS > 0 ? Z[TOTAL_PREGS-1] : zero, + INTERNAL_PREGS==2 ? 1'b0 : 1'b1 + }), // 5-bit input: INMODE control + .NEGATE('0), // 3-bit input: Negates the input of the multiplier + .OPMODE({ + LAST ? {1'b0, L[1]} : 2'b00, + 7'b000_0000 + }), // 9-bit input: Operation mode + // Data inputs: Data Ports + .A({ 7'bx, a_in_i[(IS_MVU ? 0 : CHAINLEN*i) + j] }), // 34-bit input: A data + .B(b_in_i[i][j]), // 24-bit input: B data + .C('x), // 58-bit input: C data + .CARRYIN('0), // 1-bit input: Carry-in + .D('x), // 27-bit input: D data + // Reset/Clock Enable inputs: Reset/Clock Enable Inputs + .ASYNC_RST('0), // 1-bit input: Asynchronous reset for all registers. + .CEA1(en), // 1-bit input: Clock enable for 1st stage AREG + .CEA2(INTERNAL_PREGS==2 ? en : '0), // 1-bit input: Clock enable for 2nd stage AREG + .CEAD('0), // 1-bit input: Clock enable for ADREG + .CEALUMODE('0), // 1-bit input: Clock enable for ALUMODE + .CEB1(en), // 1-bit input: Clock enable for 1st stage BREG + .CEB2(INTERNAL_PREGS==2 ? en : '0), // 1-bit input: Clock enable for 2nd stage BREG + .CEC('0), // 1-bit input: Clock enable for CREG + .CECARRYIN('0), // 1-bit input: Clock enable for CARRYINREG + .CECTRL(en), // 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG + .CED('0), // 1-bit input: Clock enable for DREG + .CEINMODE(en), // 1-bit input: Clock enable for INMODEREG + .CEM(en), // 1-bit input: Clock enable for MREG + .CEP(PREG && en), // 1-bit input: Clock enable for PREG + .RSTA(rst), // 1-bit input: Reset for AREG + .RSTALLCARRYIN('0), // 1-bit input: Reset for CARRYINREG + .RSTALUMODE('0), // 1-bit input: Reset for ALUMODEREG + .RSTB(rst), // 1-bit input: Reset for BREG + .RSTC('0), // 1-bit input: Reset for CREG + .RSTCTRL(rst), // 1-bit input: Reset for OPMODEREG and CARRYINSELREG + .RSTD('0), // 1-bit input: Reset for DREG and ADREG + .RSTINMODE(rst), // 1-bit input: Reset for INMODE register + .RSTM(rst), // 1-bit input: Reset for MREG + .RSTP(PREG && rst) // 1-bit input: Reset for PREG + ); + end : genDSP +`endif + end : genDSPChain + end : genDSPPE + +endmodule : mvu_vvu_8sx9_dsp58 diff --git a/finn-rtllib/mvu/mvu_vvu_axi.sv b/finn-rtllib/mvu/mvu_vvu_axi.sv new file mode 100644 index 0000000000..91e3b77216 --- /dev/null +++ b/finn-rtllib/mvu/mvu_vvu_axi.sv @@ -0,0 +1,375 @@ +/****************************************************************************** + * Copyright (C) 2022, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * @brief Matrix Vector Unit (MVU) & Vector Vector Unit (VVU) AXI-lite interface wrapper. + * @details + * The following compute cores are supported: + * - 4-bit MVU on DSP48 & DSP58 achieving 4 MACs/DSP, + * (4,8]-bit MVU on DSP48 achieving 2 MACs/DSP, + * [4,9]-bit MVU and VVU on DSP58 achieving 3 MACs/DSP, + * 'unconstrained' LUT-based MVU and VVU. + * Folding hints: + * - PE scaling should divide MH. + * - SIMD scaling should divide MW. + * - Otherwise, keep SIMD and PE somewhat balanced. SIMD scaling tends to + * impact critical paths more than PE scaling. PE scaling implies a + * bigger fanout on the input activations. + * - Full unfolding along MH (PE=MH) results in no replay buffer instantiated + *****************************************************************************/ + +module mvu_vvu_axi #( + bit IS_MVU, + parameter COMPUTE_CORE, + int unsigned MW, + int unsigned MH, + int unsigned PE, + int unsigned SIMD, + int unsigned SEGMENTLEN = 0, + + int unsigned ACTIVATION_WIDTH, + int unsigned WEIGHT_WIDTH, + int unsigned ACCU_WIDTH, + bit SIGNED_ACTIVATIONS = 0, + + bit PUMPED_COMPUTE = 0, // requires an even SIMD % 2 == 0 + bit FORCE_BEHAVIORAL = 0, + bit M_REG_LUT = 1, + + // Safely deducible parameters + localparam int unsigned WEIGHT_STREAM_WIDTH = PE * SIMD * WEIGHT_WIDTH, + localparam int unsigned WEIGHT_STREAM_WIDTH_BA = (WEIGHT_STREAM_WIDTH + 7)/8 * 8, + localparam int unsigned INPUT_STREAM_WIDTH = (IS_MVU ? 1 : PE) * SIMD * ACTIVATION_WIDTH, + localparam int unsigned INPUT_STREAM_WIDTH_BA = (INPUT_STREAM_WIDTH + 7)/8 * 8, + localparam int unsigned OUTPUT_STREAM_WIDTH = PE*ACCU_WIDTH, + localparam int unsigned OUTPUT_STREAM_WIDTH_BA = (OUTPUT_STREAM_WIDTH + 7)/8 * 8, + localparam bit SIMD_UNEVEN = SIMD % 2 +)( + // Global Control + input logic ap_clk, + input logic ap_clk2x, // synchronous, double-speed clock; only used for PUMPED_COMPUTE + input logic ap_rst_n, + + // Weight Stream + input logic [WEIGHT_STREAM_WIDTH_BA-1:0] s_axis_weights_tdata, + input logic s_axis_weights_tvalid, + output logic s_axis_weights_tready, + + // Input Stream + input logic [INPUT_STREAM_WIDTH_BA-1:0] s_axis_input_tdata, + input logic s_axis_input_tvalid, + output logic s_axis_input_tready, + + // Output Stream + output logic [OUTPUT_STREAM_WIDTH_BA-1:0] m_axis_output_tdata, + output logic m_axis_output_tvalid, + input logic m_axis_output_tready +); + +//-------------------- Parameter sanity checks --------------------\\ + initial begin + if (MW % SIMD != 0) begin + $error("Matrix width (%0d) is not a multiple of SIMD (%0d).", MW, SIMD); + $finish; + end + if (MH % PE != 0) begin + $error("Matrix height (%0d) is not a multiple of PE (%0d).", MH, PE); + $finish; + end + if (WEIGHT_WIDTH > 8) begin + $error("Weight width of %0d-bits exceeds maximum of 8-bits", WEIGHT_WIDTH); + $finish; + end + if (ACTIVATION_WIDTH > 8) begin + if (!(SIGNED_ACTIVATIONS == 1 && ACTIVATION_WIDTH == 9 && COMPUTE_CORE == "mvu_vvu_8sx9_dsp58")) begin + $error("Activation width of %0d-bits exceeds maximum of 9-bits for signed numbers on DSP48", ACTIVATION_WIDTH); + $finish; + end + end + if (COMPUTE_CORE == "mvu_vvu_8sx9_dsp58") begin + if (SEGMENTLEN == 0) begin + $warning("Segment length of %0d defaults to chain length of %0d", SEGMENTLEN, (SIMD+2)/3); + end + if (SEGMENTLEN > (SIMD+2)/3) begin + $error("Segment length of %0d exceeds chain length of %0d", SEGMENTLEN, (SIMD+2)/3); + $finish; + end + end + if (!IS_MVU) begin + if (COMPUTE_CORE != "mvu_vvu_8sx9_dsp58" && COMPUTE_CORE != "mvu_vvu_lut") begin + $error("VVU only supported on DSP58 or LUT-based implementation"); + $finish; + end + end + end + + uwire clk = ap_clk; + uwire clk2x = ap_clk2x; + uwire rst = !ap_rst_n; + + //- Replay to Accommodate Neuron Fold ----------------------------------- + typedef logic [(IS_MVU? 1:PE)*SIMD-1:0][ACTIVATION_WIDTH-1:0] mvu_flatin_t; + uwire mvu_flatin_t amvau; + uwire alast; + uwire afin; + uwire avld; + uwire ardy; + + localparam int unsigned SF = MW/SIMD; + localparam int unsigned NF = MH/PE; + replay_buffer #(.LEN(SF), .REP(IS_MVU ? NF : 1), .W($bits(mvu_flatin_t))) activation_replay ( + .clk, .rst, + .ivld(s_axis_input_tvalid), .irdy(s_axis_input_tready), .idat(mvu_flatin_t'(s_axis_input_tdata)), + .ovld(avld), .ordy(ardy), .odat(amvau), .olast(alast), .ofin(afin) + ); + + //- Unflatten inputs into structured matrices --------------------------- + localparam int unsigned ACT_PE = IS_MVU? 1 : PE; + typedef logic [PE -1:0][SIMD-1:0][WEIGHT_WIDTH -1:0] mvu_w_t; + typedef logic [ACT_PE-1:0][SIMD-1:0][ACTIVATION_WIDTH-1:0] mvu_a_t; + + uwire mvu_w_t mvu_w = s_axis_weights_tdata; + + //- Conditional Activations Layout Adjustment for VVU + uwire mvu_a_t amvau_i; + if (IS_MVU || (PE == 1)) begin : genMVUInput + assign amvau_i = amvau; + end : genMVUInput + else begin : genVVUInput + // The input stream will have the channels interleaved for VVU when PE>1 + // Hence, we need to 'untangle' the input stream, i.e. [..][SIMD*PE][..] --> [..][PE][SIMD][..] + // Note that for each 'SIMD' (S) and 'PE' (P) element, we have something like: + // (S_0, P_0), ..., (S_0, P_i), (S_1, P_0), ..., (S_1, P_i), ..., (S_i, P_i) which we need to 'untangle' to + // (S_0, P_0), ..., (S_i, P_0), (S_0, P_1), ..., (S_i, P_1), ..., (S_i, P_i) + for(genvar pe = 0; pe < ACT_PE; pe++) begin + for(genvar simd = 0; simd < SIMD; simd++) begin + assign amvau_i[pe][simd] = amvau[simd*ACT_PE+pe]; + end + end + end : genVVUInput + + //- Flow Control Bracket around Compute Core ---------------------------- + uwire en; + uwire istb = avld && s_axis_weights_tvalid; + assign ardy = en && s_axis_weights_tvalid; + assign s_axis_weights_tready = en && avld; + + //- Conditionally Pumped DSP Compute ------------------------------------ + typedef logic [PE-1:0][ACCU_WIDTH-1:0] dsp_p_t; + uwire ovld; + uwire dsp_p_t odat; + if(1) begin : blkDsp + localparam int unsigned EFFECTIVE_SIMD = SIMD_UNEVEN && PUMPED_COMPUTE ? SIMD+1 : SIMD; + localparam int unsigned DSP_SIMD = EFFECTIVE_SIMD/(PUMPED_COMPUTE+1); + typedef logic [PE -1:0][DSP_SIMD-1:0][WEIGHT_WIDTH -1:0] dsp_w_t; + typedef logic [ACT_PE-1:0][DSP_SIMD-1:0][ACTIVATION_WIDTH-1:0] dsp_a_t; + + uwire dsp_clk; + uwire dsp_en; + + uwire dsp_last; + uwire dsp_zero; + uwire dsp_w_t dsp_w; + uwire dsp_a_t dsp_a; + + uwire dsp_vld; + uwire dsp_p_t dsp_p; + + if(!PUMPED_COMPUTE) begin : genUnpumpedCompute + assign dsp_clk = clk; + assign dsp_en = en; + + assign dsp_last = alast && avld; + assign dsp_zero = !istb; + assign dsp_w = mvu_w; + assign dsp_a = amvau_i; + + assign ovld = dsp_vld; + assign odat = dsp_p; + end : genUnpumpedCompute + else begin : genPumpedCompute + assign dsp_clk = clk2x; + + // Identify second fast cycle just before active slow clock edge + logic Active = 0; + if(1) begin : blkActive + uwire clk_lut[2]; // Put some LUT delay on the input from the fast clock net + (* DONT_TOUCH = "TRUE", HLUTNM = "CLK_LUT" *) LUT1 #(.INIT(2'b10)) lut0(.O(clk_lut[0]), .I0(clk)); + (* DONT_TOUCH = "TRUE", HLUTNM = "CLK_LUT" *) LUT1 #(.INIT(2'b10)) lut1(.O(clk_lut[1]), .I0(clk_lut[0])); + always_ff @(posedge clk2x) Active <= clk_lut[1]; + end : blkActive + + // The input for a slow cycle is split across two fast cycles along the SIMD dimension. + // - Both fast cycles are controlled by the same enable state. + // - A zero cycle is duplicated across both fast cycles. + // - The last flag must be restricted to the second fast cycle. + + dsp_w_t W = 'x; + for(genvar pe = 0; pe < PE; pe++) begin : genPERegW + + uwire [2*DSP_SIMD-1:0][WEIGHT_WIDTH-1:0] w; + for(genvar i = 0; i < SIMD; i++) assign w[i] = mvu_w[pe][i]; + for(genvar i = SIMD; i < 2*DSP_SIMD; i++) assign w[i] = 0; + + always_ff @(posedge clk2x) begin + if(rst) W[pe] <= 'x; + else if(en) W[pe] <= w[(Active? DSP_SIMD : 0) +: DSP_SIMD]; + end + + end : genPERegW + + dsp_a_t A = 'x; + for(genvar pe = 0; pe < ACT_PE; pe++) begin : genPERegA + + uwire [2*DSP_SIMD-1:0][ACTIVATION_WIDTH-1:0] a; + for(genvar i = 0; i < SIMD; i++) assign a[i] = amvau_i[pe][i]; + for(genvar i = SIMD; i < 2*DSP_SIMD; i++) assign a[i] = 0; + + always_ff @(posedge clk2x) begin + if(rst) A[pe] <= 'x; + else if(en) A[pe] <= a[(Active? DSP_SIMD : 0) +: DSP_SIMD]; + end + + end : genPERegA + + logic Zero = 1; + logic Last = 0; + always_ff @(posedge clk2x) begin + if(rst) begin + Zero <= 1; + Last <= 0; + end + else if(en) begin + Zero <= !istb; + Last <= alast && avld && Active; + end + end + + assign dsp_en = en; + assign dsp_last = Last; + assign dsp_zero = Zero; + assign dsp_w = W; + assign dsp_a = A; + + // Since no two consecutive last cycles will ever be asserted on the input, + // valid outputs will also always be spaced by, at least, one other cycle. + // We can always hold a captured output for two cycles to allow the slow + // clock to pick it up. + logic Vld = 0; + dsp_p_t P = 'x; + always_ff @(posedge clk2x) begin + if(rst) begin + Vld <= 0; + P <= 'x; + end + else if(en) begin + if(dsp_vld) P <= dsp_p; + Vld <= dsp_vld || (Vld && !Active); + end + end + assign ovld = Vld; + assign odat = P; + + end : genPumpedCompute + + case(COMPUTE_CORE) + "mvu_vvu_8sx9_dsp58": + mvu_vvu_8sx9_dsp58 #(.IS_MVU(IS_MVU), .PE(PE), .SIMD(DSP_SIMD), .ACTIVATION_WIDTH(ACTIVATION_WIDTH), .WEIGHT_WIDTH(WEIGHT_WIDTH), + .ACCU_WIDTH(ACCU_WIDTH), .SIGNED_ACTIVATIONS(SIGNED_ACTIVATIONS), .SEGMENTLEN(SEGMENTLEN), + .FORCE_BEHAVIORAL(FORCE_BEHAVIORAL)) core ( + .clk(dsp_clk), .rst, .en(dsp_en), + .last(dsp_last), .zero(dsp_zero), .w(dsp_w), .a(dsp_a), + .vld(dsp_vld), .p(dsp_p) + ); + "mvu_4sx4u": + mvu_4sx4u #(.PE(PE), .SIMD(DSP_SIMD), .ACCU_WIDTH(ACCU_WIDTH), .SIGNED_ACTIVATIONS(SIGNED_ACTIVATIONS), .FORCE_BEHAVIORAL(FORCE_BEHAVIORAL)) core ( + .clk(dsp_clk), .rst, .en(dsp_en), + .last(dsp_last), .zero(dsp_zero), .w(dsp_w), .a(dsp_a), + .vld(dsp_vld), .p(dsp_p) + ); + "mvu_8sx8u_dsp48": + mvu_8sx8u_dsp48 #(.PE(PE), .SIMD(DSP_SIMD), .ACCU_WIDTH(ACCU_WIDTH), .ACTIVATION_WIDTH(ACTIVATION_WIDTH), .WEIGHT_WIDTH(WEIGHT_WIDTH), + .SIGNED_ACTIVATIONS(SIGNED_ACTIVATIONS), .FORCE_BEHAVIORAL(FORCE_BEHAVIORAL)) core ( + .clk(dsp_clk), .rst, .en(dsp_en), + .last(dsp_last), .zero(dsp_zero), .w(dsp_w), .a(dsp_a), + .vld(dsp_vld), .p(dsp_p) + ); + "mvu_vvu_lut": + mvu_vvu_lut #(.IS_MVU(IS_MVU), .PE(PE), .SIMD(DSP_SIMD), .ACCU_WIDTH(ACCU_WIDTH), .ACTIVATION_WIDTH(ACTIVATION_WIDTH), + .WEIGHT_WIDTH(WEIGHT_WIDTH), .SIGNED_ACTIVATIONS(SIGNED_ACTIVATIONS), .M_REG(M_REG_LUT)) core ( + .clk(dsp_clk), .rst, .en(dsp_en), + .last(dsp_last), .zero(dsp_zero), .w(dsp_w), .a(dsp_a), + .vld(dsp_vld), .p(dsp_p) + ); + default: initial begin + $error("Unrecognized COMPUTE_CORE '%s'", COMPUTE_CORE); + $finish; + end + endcase + + end : blkDsp + +//-------------------- Output register slice --------------------\\ + // Make `en`computation independent from external inputs. + // Drive all outputs from registers. + struct packed { + logic rdy; + logic [PE-1:0][ACCU_WIDTH-1:0] dat; + } A = '{ rdy: 1, default: 'x }; // side-step register used when encountering backpressure + struct packed { + logic vld; + logic [PE-1:0][ACCU_WIDTH-1:0] dat; + } B = '{ vld: 0, default: 'x }; // ultimate output register + + assign en = A.rdy; + uwire b_load = !B.vld || m_axis_output_tready; + + always_ff @(posedge clk) begin + if(rst) begin + A <= '{ rdy: 1, default: 'x }; + B <= '{ vld: 0, default: 'x }; + end + else begin + if(A.rdy) A.dat <= odat; + A.rdy <= (A.rdy && !ovld) || b_load; + + if(b_load) begin + B <= '{ + vld: ovld || !A.rdy, + dat: A.rdy? odat : A.dat + }; + end + end + end + assign m_axis_output_tvalid = B.vld; + // Why would we need a sign extension here potentially creating a higher signal load into the next FIFO? + // These extra bits should never be used. Why not 'x them out? + assign m_axis_output_tdata = { {(OUTPUT_STREAM_WIDTH_BA-OUTPUT_STREAM_WIDTH){B.dat[PE-1][ACCU_WIDTH-1]}}, B.dat}; + +endmodule : mvu_vvu_axi diff --git a/finn-rtllib/mvu/mvu_vvu_axi_wrapper.v b/finn-rtllib/mvu/mvu_vvu_axi_wrapper.v new file mode 100644 index 0000000000..ee067fa8b5 --- /dev/null +++ b/finn-rtllib/mvu/mvu_vvu_axi_wrapper.v @@ -0,0 +1,97 @@ +/****************************************************************************** + * Copyright (C) 2022, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * @brief Verilog AXI-lite wrapper for MVU & VVU. + *****************************************************************************/ + +module $MODULE_NAME_AXI_WRAPPER$ #( + parameter IS_MVU = $IS_MVU$, + parameter COMPUTE_CORE = "$COMPUTE_CORE$", + parameter PUMPED_COMPUTE = 0, + parameter MW = $MW$, + parameter MH = $MH$, + parameter PE = $PE$, + parameter SIMD = $SIMD$, + parameter ACTIVATION_WIDTH = $ACTIVATION_WIDTH$, + parameter WEIGHT_WIDTH = $WEIGHT_WIDTH$, + parameter ACCU_WIDTH = $ACCU_WIDTH$, + parameter SIGNED_ACTIVATIONS = $SIGNED_ACTIVATIONS$, + parameter SEGMENTLEN = $SEGMENTLEN$, + parameter FORCE_BEHAVIORAL = $FORCE_BEHAVIORAL$, + + // Safely deducible parameters + parameter WEIGHT_STREAM_WIDTH_BA = (PE*SIMD*WEIGHT_WIDTH+7)/8 * 8, + parameter INPUT_STREAM_WIDTH_BA = ((IS_MVU == 1 ? 1 : PE) * SIMD * ACTIVATION_WIDTH + 7) / 8 * 8, + parameter OUTPUT_STREAM_WIDTH_BA = (PE*ACCU_WIDTH + 7)/8 * 8 +)( + // Global Control + (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF weights_V:in0_V:out_V, ASSOCIATED_RESET ap_rst_n" *) + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *) + input ap_clk, + // (* X_INTERFACE_PARAMETER = "ASSOCIATED_RESET ap_rst_n" *) + // (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk2x CLK" *) + // input ap_clk2x, + (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *) + input ap_rst_n, + + // Weight Stream + input [WEIGHT_STREAM_WIDTH_BA-1:0] weights_V_TDATA, + input weights_V_TVALID, + output weights_V_TREADY, + // Input Stream + input [INPUT_STREAM_WIDTH_BA-1:0] in0_V_TDATA, + input in0_V_TVALID, + output in0_V_TREADY, + // Output Stream + output [OUTPUT_STREAM_WIDTH_BA-1:0] out_V_TDATA, + output out_V_TVALID, + input out_V_TREADY +); + +mvu_vvu_axi #( + .IS_MVU(IS_MVU), .COMPUTE_CORE(COMPUTE_CORE), .PUMPED_COMPUTE(PUMPED_COMPUTE), .MW(MW), .MH(MH), .PE(PE), .SIMD(SIMD), + .ACTIVATION_WIDTH(ACTIVATION_WIDTH), .WEIGHT_WIDTH(WEIGHT_WIDTH), .ACCU_WIDTH(ACCU_WIDTH), + .SIGNED_ACTIVATIONS(SIGNED_ACTIVATIONS), .SEGMENTLEN(SEGMENTLEN), .FORCE_BEHAVIORAL(FORCE_BEHAVIORAL) + ) inst ( + .ap_clk(ap_clk), + .ap_clk2x(1'b0), + .ap_rst_n(ap_rst_n), + .s_axis_weights_tdata(weights_V_TDATA), + .s_axis_weights_tvalid(weights_V_TVALID), + .s_axis_weights_tready(weights_V_TREADY), + .s_axis_input_tdata(in0_V_TDATA), + .s_axis_input_tvalid(in0_V_TVALID), + .s_axis_input_tready(in0_V_TREADY), + .m_axis_output_tdata(out_V_TDATA), + .m_axis_output_tvalid(out_V_TVALID), + .m_axis_output_tready(out_V_TREADY) +); + +endmodule // $MODULE_NAME_AXI_WRAPPER$ diff --git a/finn-rtllib/mvu/replay_buffer.sv b/finn-rtllib/mvu/replay_buffer.sv new file mode 100644 index 0000000000..3e2766f63d --- /dev/null +++ b/finn-rtllib/mvu/replay_buffer.sv @@ -0,0 +1,181 @@ +/****************************************************************************** + * Copyright (C) 2022-2023, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * @brief Replay buffer for counted sequences on an AXI-lite stream. + * @author Thomas B. Preußer + *****************************************************************************/ + +module replay_buffer #( + int unsigned LEN, // Sequence length + int unsigned REP, // Sequence replay count + int unsigned W // Data width +)( + input logic clk, + input logic rst, + + input logic [W-1:0] idat, + input logic ivld, + output logic irdy, + + output logic [W-1:0] odat, + output logic olast, + output logic ofin, + output logic ovld, + input logic ordy +); + + if(LEN == 0) initial begin + $error("%m: Illegal zero sequence LEN."); + $finish; + end + if(REP == 0) initial begin + $error("%m: Illegal zero REP count."); + $finish; + end + + // Track position in Sequence + uwire last_item; + uwire shift; + if(LEN == 1) assign last_item = 1; + else begin + typedef logic [$clog2(LEN)-1:0] count_t; + count_t Count = 0; + logic Last = 0; + always_ff @(posedge clk) begin + if(rst) begin + Count <= 0; + Last <= 0; + end + else if(shift) begin + Count <= Count + (Last? 2**$clog2(LEN)-LEN+1 : 1); + Last <= (((LEN-2) & ~Count) == 0) && ((LEN&1) || !Last); + end + end + assign last_item = Last; + end + + if(REP == 1) begin + assign shift = ivld && ordy; + + assign irdy = ordy; + assign odat = idat; + assign olast = last_item; + assign ofin = last_item; + assign ovld = ivld; + end + else begin + + // Track Repetitions + uwire last_rep; + if(1) begin : blkRep + typedef logic [$clog2(REP)-1:0] rep_t; + rep_t RepCnt = 0; + logic RepLst = 0; + always_ff @(posedge clk) begin + if(rst) begin + RepCnt <= 0; + RepLst <= 0; + end + else if(last_item && shift) begin + RepCnt <= RepCnt + (RepLst? 2**$clog2(REP)-REP+1 : 1); + RepLst <= (((REP-2) & ~RepCnt) == 0) && ((REP&1) || !RepLst); + end + end + assign last_rep = RepLst; + end : blkRep + + localparam int unsigned AWIDTH = LEN < 2? 1 : $clog2(LEN); + typedef logic [AWIDTH :0] ptr_t; // pointers with additional generational MSB + typedef logic [W -1:0] data_t; + + // Output Registers + data_t ODat; + logic OVld = 0; + logic OLst = 'x; + logic OFin = 'x; + assign odat = ODat; + assign olast = OLst; + assign ofin = OFin; + assign ovld = OVld; + + // Buffer Memory Management + data_t Mem[2**AWIDTH]; + ptr_t WP = 0; // Write Pointer + ptr_t RP = 0; // Read Pointer + ptr_t FP = 0; // Free Pointer + + // Operational Guards + // Occupancy: WP-FP + // WP-FP < 2**AWIDTH -> writing allowed + // - increments WP + // Availability: WP-RP + // WP-RP > 0 -> reading allowed + // - increments RP, last in sequence rewinds to FP for non-final repetition + // - increments FP in last repetition + assign irdy = !((WP-FP) >> AWIDTH); + + uwire wr = irdy && ivld; + uwire rd = !OVld || ordy; + always_ff @(posedge clk) begin + if(wr) Mem[WP[AWIDTH-1:0]] <= idat; + if(rd) ODat <= Mem[RP[AWIDTH-1:0]]; + end + + uwire vld = (RP != WP); + assign shift = rd && vld; + always_ff @(posedge clk) begin + if(rst) begin + WP <= 0; + RP <= 0; + FP <= 0; + + OVld <= 0; + OLst <= 'x; + OFin <= 'x; + end + else begin + if(wr) WP <= WP + 1; + if(rd) begin + if(vld) begin + automatic logic rewind = last_item && !last_rep; + RP <= RP + (rewind? 2**(AWIDTH+1)-LEN+1 : 1); + FP <= FP + last_rep; + end + + OVld <= vld; + OLst <= last_item; + OFin <= last_rep && last_item; + end + end + end + + end + +endmodule : replay_buffer From b295329694dc19eb97cb1fc76b8e57426cca4101 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Mon, 4 Mar 2024 11:02:43 +0000 Subject: [PATCH 537/665] [tb]: testbench for replay_buffer and mvu/vvu layers --- finn-rtllib/mvu/tb/mvu_axi_tb.sv | 239 +++++++++++++++++++++++++ finn-rtllib/mvu/tb/replay_buffer_tb.sv | 130 ++++++++++++++ finn-rtllib/mvu/tb/vvu_axi_tb.sv | 227 +++++++++++++++++++++++ 3 files changed, 596 insertions(+) create mode 100644 finn-rtllib/mvu/tb/mvu_axi_tb.sv create mode 100644 finn-rtllib/mvu/tb/replay_buffer_tb.sv create mode 100644 finn-rtllib/mvu/tb/vvu_axi_tb.sv diff --git a/finn-rtllib/mvu/tb/mvu_axi_tb.sv b/finn-rtllib/mvu/tb/mvu_axi_tb.sv new file mode 100644 index 0000000000..2f35a112ab --- /dev/null +++ b/finn-rtllib/mvu/tb/mvu_axi_tb.sv @@ -0,0 +1,239 @@ +/****************************************************************************** + * Copyright (C) 2022, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * @brief Testbench for MVU AXI-lite interface wrapper. + *****************************************************************************/ + +module mvu_axi_tb(); + +//-------------------- Simulation parameters --------------------\\ + // Matrix & parallelism config + localparam bit IS_MVU = 1; + localparam string COMPUTE_CORE = "mvu_4sx4u"; + localparam int unsigned MW = 120; + localparam int unsigned MH = 40; + localparam int unsigned SIMD = 20; + localparam int unsigned PE = 10; + localparam int unsigned SEGMENTLEN = 2.0; + localparam bit FORCE_BEHAVIORAL = 1; + localparam bit M_REG_LUT = 1; + // Bit-width config + localparam int unsigned ACTIVATION_WIDTH = 4; + localparam int unsigned WEIGHT_WIDTH = 4; + localparam int unsigned ACCU_WIDTH = ACTIVATION_WIDTH+WEIGHT_WIDTH+$clog2(MW); + localparam bit SIGNED_ACTIVATIONS = 0; + // Simulation constants + localparam int unsigned NF = MH/PE; + localparam int unsigned SF = MW/SIMD; + localparam int unsigned WEIGHT_WIDTH_BA = (PE*SIMD*WEIGHT_WIDTH+7)/8*8; + localparam int unsigned ACTIVATION_WIDTH_BA = (SIMD*ACTIVATION_WIDTH+7)/8*8; + localparam int unsigned WEIGHT_WIDTH_BA_DELTA = WEIGHT_WIDTH_BA - PE*SIMD*WEIGHT_WIDTH; + localparam int unsigned ACTIVATION_WIDTH_BA_DELTA = ACTIVATION_WIDTH_BA - SIMD*ACTIVATION_WIDTH; + localparam int unsigned OUTPUT_STREAM_WIDTH_BA = (PE*ACCU_WIDTH + 7)/8 * 8; + + // Generate clk and reset signal + logic clk = 0; + always #5ns clk = !clk; + + logic ap_rst_n = 0; + initial begin + repeat(16) @(posedge clk); + ap_rst_n <= 1; + end + + uwire ap_clk = clk; + + // Generate activations + typedef logic [SIMD-1:0][ACTIVATION_WIDTH-1:0] activation_t; + typedef activation_t activation_vector_t[SF]; + + function activation_vector_t init_ACTIVATIONS; + automatic activation_vector_t res; + std::randomize(res); + return res; + endfunction : init_ACTIVATIONS + + activation_vector_t ACTIVATIONS = init_ACTIVATIONS(); + + struct { + activation_t dat; + logic vld; + logic rdy; + } activations; + + initial begin + activations.vld = 0; + activations.dat = 'X; + @(posedge clk iff ap_rst_n); + + for (int i=0; i= 0; + @(posedge clk); + end while (!(activations.vld === 1 && activations.rdy === 1)); + end + + activations.vld <= 0; + activations.dat <= 'x; + end + + // Generate weights + typedef logic [PE-1:0][SIMD-1:0][WEIGHT_WIDTH-1:0] weight_t; + typedef weight_t weight_matrix_t[NF][SF]; + + function weight_matrix_t init_WEIGHTS; + automatic weight_matrix_t res; + std::randomize(res); + return res; + endfunction : init_WEIGHTS; + + weight_matrix_t WEIGHTS = init_WEIGHTS(); + + struct { + weight_t dat; + logic vld; + logic rdy; + } weights; + + initial begin + weights.vld = 0; + weights.dat = 'X; + @(posedge clk iff ap_rst_n); + + weights.vld <= 1; + for (int i=0; i 1 ? $signed(a[i/SIMD/PE][i % (SIMD*PE)]) : $signed(a[i/SIMD/PE][(i)%(SIMD*PE)]) ) * $signed(w[0][i/SIMD/PE][i/PE][i%SIMD]); + // else + // res[j/PE][j%PE] = IS_MVU ? $signed(res[j/PE][j%PE]) + $signed({1'b0, a[i/SIMD][i%SIMD]}) * $signed(w[j/PE][i/SIMD][j%PE][i%SIMD]) : + // $signed(res[j/PE][j%PE]) + ( PE > 1 ? $signed({1'b0, a[i/SIMD/PE][i % (SIMD*PE)]}) : $signed({1'b0, a[i/SIMD/PE][i%(SIMD*PE)]}) ) * $signed(w[0][i/SIMD][0][i%SIMD]); + // end + // end + // The input stream will have the channels interleaved for VVU when PE>1 + // Hence, we need to 'untangle' the input stream, i.e. [..][SIMD*PE][..] --> [..][PE][SIMD][..] + // Note that for each 'SIMD' (S) and 'PE' (P) element, we have something like: + // (S_0, P_0), ..., (S_0, P_i), (S_1, P_0), ..., (S_1, P_i), ..., (S_i, P_i) which we need to 'untangle' to + // (S_0, P_0), ..., (S_i, P_0), (S_0, P_1), ..., (S_i,, P_1), ..., (S_i, P_i) + for (int i = 0; i < NF; i++) begin + for (int j = 0; j < SF; j++) begin + for (int k = 0; k < PE; k++) begin + for (int l = 0; l < SIMD; l++) begin + if (SIGNED_ACTIVATIONS) + res[i][k] = $signed(res[i][k]) + $signed(a[j][l]) * $signed(w[i][j][k][l]); + else + res[i][k] = $signed(res[i][k]) + $signed({1'b0, a[j][l]}) * $signed(w[i][j][k][l]); + end + end + end + end + return res; + endfunction : check_output; + + output_vector_t GOLDEN_OUTPUT = check_output(ACTIVATIONS, WEIGHTS); + + int unsigned NF_CNT = 0; + initial begin + outputs.rdy = 0; + while (NF_CNT < NF) begin + // Loop until both rdy & vld are asserted + do begin + outputs.rdy <= $urandom()%7 >= 0; + @(posedge clk iff ap_rst_n); + end while (!(outputs.rdy === 1 && outputs.vld === 1)); + + // Compare produced outputs against golden outputs + foreach(outputs.dat[i]) begin + assert ($signed(outputs.dat[i]) == $signed(GOLDEN_OUTPUT[NF_CNT][i])) $display(">>> [t=%0t] Test succeeded (NF=%0d)! Computed / GOLDEN = %0d / %0d", $time, NF_CNT, $signed(outputs.dat[i]), $signed(GOLDEN_OUTPUT[NF_CNT][i])); + else begin + $error(">>> [t=%0t] TEST failed (NF=%0d)! Computed / GOLDEN = %0d / %0d", $time, NF_CNT, $signed(outputs.dat[i]), $signed(GOLDEN_OUTPUT[NF_CNT][i])); + $stop; + end + end + + NF_CNT += 1; + end + + $finish; + end + + // Instantiate DUT + mvu_vvu_axi #( + .IS_MVU(IS_MVU), + .COMPUTE_CORE(COMPUTE_CORE), + .MW(MW), + .MH(MH), + .PE(PE), + .SIMD(SIMD), + .ACTIVATION_WIDTH(ACTIVATION_WIDTH), + .WEIGHT_WIDTH(WEIGHT_WIDTH), + .ACCU_WIDTH(ACCU_WIDTH), + .SIGNED_ACTIVATIONS(SIGNED_ACTIVATIONS), + .SEGMENTLEN(SEGMENTLEN), + .FORCE_BEHAVIORAL(FORCE_BEHAVIORAL), + .M_REG_LUT(M_REG_LUT) + ) + dut ( + .ap_clk, .ap_rst_n, .s_axis_weights_tdata({ {WEIGHT_WIDTH_BA_DELTA{1'b0}}, weights.dat }), .s_axis_weights_tvalid(weights.vld), + .s_axis_weights_tready(weights.rdy), .s_axis_input_tdata({ {ACTIVATION_WIDTH_BA_DELTA{1'b0}}, activations.dat }), .s_axis_input_tvalid(activations.vld), + .s_axis_input_tready(activations.rdy), .m_axis_output_tdata(outputs.dat), .m_axis_output_tvalid(outputs.vld), + .m_axis_output_tready(outputs.rdy) + ); + +endmodule : mvu_axi_tb \ No newline at end of file diff --git a/finn-rtllib/mvu/tb/replay_buffer_tb.sv b/finn-rtllib/mvu/tb/replay_buffer_tb.sv new file mode 100644 index 0000000000..5581354e0e --- /dev/null +++ b/finn-rtllib/mvu/tb/replay_buffer_tb.sv @@ -0,0 +1,130 @@ +/****************************************************************************** + * Copyright (C) 2023, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * @brief Testbench for replay_buffer module. + * @author Thomas B. Preußer + *****************************************************************************/ + +module replay_buffer_tb; + + // Global Control + logic clk = 0; + always #5ns clk = !clk; + uwire rst = 0; + + // DUT Geometries + localparam int unsigned DIMS[3] = '{ 7, 8, 10 }; + localparam int unsigned W = 8; + typedef logic [W-1:0] data_t; + + bit [2**$size(DIMS)-1:0] done = 0; + always_comb begin + if(&done) begin + $display("Test completed."); + $finish; + end + end + + // Parallel DUT Instantiations + for(genvar r = 0; r < $size(DIMS); r++) begin + for(genvar l = 0; l < $size(DIMS); l++) begin + localparam int unsigned REP = DIMS[r]; + localparam int unsigned LEN = DIMS[l]; + + data_t idat; + logic ivld; + uwire irdy; + + uwire data_t odat; + uwire olast; + uwire ofin; + uwire ovld; + logic ordy; + + replay_buffer #(.LEN(LEN), .REP(REP), .W(W)) dut ( + .clk, .rst, + .idat, .ivld, .irdy, + .odat, .olast, .ofin, .ovld, .ordy + ); + + // Input Feed: 0, 1, ..., 10*LEN-1 + initial begin + idat = 'x; + ivld = 0; + @(posedge clk iff !rst); + + for(int unsigned i = 0; i < 10*LEN; i++) begin + idat <= i; + ivld <= 1; + @(posedge clk iff irdy); + idat <= 'x; + ivld <= 0; + while($urandom()%(REP-1) != 0) @(posedge clk); + end + end + + // Output Check + initial begin + automatic int unsigned base = 0; + + ordy = 0; + @(posedge clk iff !rst); + + for(int unsigned k = 0; k < 10; k++) begin + for(int unsigned j = 0; j < REP; j++) begin + for(int unsigned i = 0; i < LEN; i++) begin + ordy <= 1; + @(posedge clk iff ovld); + assert(odat == base+i) else begin + $error("#%0d.%0d: Data mismatch: %0d instead of %0d.", r, l, odat, base+i); + $stop; + end + assert(olast == (i == LEN-1)) else begin + $error("#%0d.%0d: Last mismatch.", r, l); + $stop; + end + assert(ofin == ((i == LEN-1) && (j == REP-1))) else begin + $error("#%0d.%0d: Fin mismatch.", r, l); + $stop; + end + + ordy <= 0; + while($urandom()%13 == 0) @(posedge clk); + end + end + base += LEN; + end + + done[$size(DIMS)*r + l] <= 1; + end + end + end + +endmodule : replay_buffer_tb diff --git a/finn-rtllib/mvu/tb/vvu_axi_tb.sv b/finn-rtllib/mvu/tb/vvu_axi_tb.sv new file mode 100644 index 0000000000..fbb45845e1 --- /dev/null +++ b/finn-rtllib/mvu/tb/vvu_axi_tb.sv @@ -0,0 +1,227 @@ +/****************************************************************************** + * Copyright (C) 2022, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * @brief Testbench for MVU AXI-lite interface wrapper. + *****************************************************************************/ + +module vvu_axi_tb(); + +//-------------------- Simulation parameters --------------------\\ + // Matrix & parallelism config + localparam bit IS_MVU = 0; + localparam string COMPUTE_CORE = "mvu_vvu_8sx9_dsp58"; + localparam int unsigned MW = 25; // Kernel*Kernel + localparam int unsigned MH = 4; // Channels + localparam int unsigned SIMD = 25; // MW%SIMD == 0 + localparam int unsigned PE = 2; // MH%PE == 0 + localparam int unsigned SEGMENTLEN = 3.0; + localparam bit FORCE_BEHAVIORAL = 1; + localparam bit M_REG_LUT = 1; + // Bit-width config + localparam int unsigned ACTIVATION_WIDTH = 4; + localparam int unsigned WEIGHT_WIDTH = 4; + localparam int unsigned ACCU_WIDTH = ACTIVATION_WIDTH+WEIGHT_WIDTH+$clog2(MW); + localparam bit SIGNED_ACTIVATIONS = 1; + // Simulation constants + localparam int unsigned NF = MH/PE; + localparam int unsigned SF = MW/SIMD; + localparam int unsigned WEIGHT_WIDTH_BA = (PE*SIMD*WEIGHT_WIDTH+7)/8*8; + localparam int unsigned ACTIVATION_WIDTH_BA = (PE*SIMD*ACTIVATION_WIDTH+7)/8*8; + localparam int unsigned WEIGHT_WIDTH_BA_DELTA = WEIGHT_WIDTH_BA - PE*SIMD*WEIGHT_WIDTH; + localparam int unsigned ACTIVATION_WIDTH_BA_DELTA = ACTIVATION_WIDTH_BA - PE*SIMD*ACTIVATION_WIDTH; + localparam int unsigned OUTPUT_STREAM_WIDTH_BA = (PE*ACCU_WIDTH + 7)/8 * 8; + + // Generate clk and reset signal + logic clk = 0; + always #5ns clk = !clk; + + logic ap_rst_n = 0; + initial begin + repeat(16) @(posedge clk); + ap_rst_n <= 1; + end + + uwire ap_clk = clk; + + // Generate activations + typedef logic [PE*SIMD-1:0][ACTIVATION_WIDTH-1:0] activation_t; + typedef activation_t activation_vector_t[NF*SF]; + + function activation_vector_t init_ACTIVATIONS; + automatic activation_vector_t res; + std::randomize(res); + return res; + endfunction : init_ACTIVATIONS + + activation_vector_t ACTIVATIONS = init_ACTIVATIONS(); + + struct { + activation_t dat; + logic vld; + logic rdy; + } activations; + + initial begin + activations.vld = 0; + activations.dat = 'X; + @(posedge clk iff ap_rst_n); + + for (int i=0; i= 0; + @(posedge clk); + end while (!(activations.vld === 1 && activations.rdy === 1)); + end + + activations.vld <= 0; + activations.dat <= 'x; + end + + // Generate weights + typedef logic [PE-1:0][SIMD-1:0][WEIGHT_WIDTH-1:0] weight_t; + typedef weight_t weight_matrix_t[NF][SF]; + + function weight_matrix_t init_WEIGHTS; + automatic weight_matrix_t res; + std::randomize(res); + return res; + endfunction : init_WEIGHTS; + + weight_matrix_t WEIGHTS = init_WEIGHTS(); + + struct { + weight_t dat; + logic vld; + logic rdy; + } weights; + + initial begin + weights.vld = 0; + weights.dat = 'X; + @(posedge clk iff ap_rst_n); + + weights.vld <= 1; + for (int i=0; i1 + // Hence, we need to 'untangle' the input stream, i.e. [..][SIMD*PE][..] --> [..][PE][SIMD][..] + // Note that for each 'SIMD' (S) and 'PE' (P) element, we have something like: + // (S_0, P_0), ..., (S_0, P_i), (S_1, P_0), ..., (S_1, P_i), ..., (S_i, P_i) which we need to 'untangle' to + // (S_0, P_0), ..., (S_i, P_0), (S_0, P_1), ..., (S_i,, P_1), ..., (S_i, P_i) + for (int i = 0; i < NF; i++) begin + for (int j = 0; j < SF; j++) begin + for (int k = 0; k < PE; k++) begin + for (int l = 0; l < SIMD; l++) begin + if (SIGNED_ACTIVATIONS) + res[i][k] = $signed(res[i][k]) + $signed(a[i*SF+j][k + l*PE]) * $signed(w[i][j][k][l]); + else + res[i][k] = $signed(res[i][k]) + $signed({1'b0, a[i*SF+j][k + l*PE]}) * $signed(w[i][j][k][l]); + end + end + end + end + return res; + endfunction : check_output; + + output_vector_t GOLDEN_OUTPUT = check_output(ACTIVATIONS, WEIGHTS); + + int unsigned NF_CNT = 0; + initial begin + outputs.rdy = 0; + while (NF_CNT < NF) begin + // Loop until both rdy & vld are asserted + do begin + outputs.rdy <= $urandom()%7 >= 0; + @(posedge clk iff ap_rst_n); + end while (!(outputs.rdy === 1 && outputs.vld === 1)); + + // Compare produced outputs against golden outputs + foreach(outputs.dat[i]) begin + assert ($signed(outputs.dat[i]) == $signed(GOLDEN_OUTPUT[NF_CNT][i])) $display(">>> [t=%0t] Test succeeded (NF=%0d)! Computed / GOLDEN = %0d / %0d", $time, NF_CNT, $signed(outputs.dat[i]), $signed(GOLDEN_OUTPUT[NF_CNT][i])); + else begin + $error(">>> [t=%0t] TEST failed (NF=%0d)! Computed / GOLDEN = %0d / %0d", $time, NF_CNT, $signed(outputs.dat[i]), $signed(GOLDEN_OUTPUT[NF_CNT][i])); + $stop; + end + end + + NF_CNT += 1; + end + + $finish; + end + + // Instantiate DUT + mvu_vvu_axi #( + .IS_MVU(IS_MVU), + .COMPUTE_CORE(COMPUTE_CORE), + .MW(MW), + .MH(MH), + .PE(PE), + .SIMD(SIMD), + .ACTIVATION_WIDTH(ACTIVATION_WIDTH), + .WEIGHT_WIDTH(WEIGHT_WIDTH), + .ACCU_WIDTH(ACCU_WIDTH), + .SIGNED_ACTIVATIONS(SIGNED_ACTIVATIONS), + .SEGMENTLEN(SEGMENTLEN), + .FORCE_BEHAVIORAL(FORCE_BEHAVIORAL), + .M_REG_LUT(M_REG_LUT) + ) + dut ( + .ap_clk, .ap_rst_n, .s_axis_weights_tdata({ {WEIGHT_WIDTH_BA_DELTA{1'b0}}, weights.dat }), .s_axis_weights_tvalid(weights.vld), + .s_axis_weights_tready(weights.rdy), .s_axis_input_tdata({ {ACTIVATION_WIDTH_BA_DELTA{1'b0}}, activations.dat }), .s_axis_input_tvalid(activations.vld), + .s_axis_input_tready(activations.rdy), .m_axis_output_tdata(outputs.dat), .m_axis_output_tvalid(outputs.vld), + .m_axis_output_tready(outputs.rdy) + ); + +endmodule : vvu_axi_tb From 7cf62c7017d146bd50377d05eb5689a49604629e Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 4 Mar 2024 12:21:14 +0000 Subject: [PATCH 538/665] [Tests] Specialize layers before checksum hook insertion --- tests/fpgadataflow/test_fpgadataflow_checksum.py | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/fpgadataflow/test_fpgadataflow_checksum.py b/tests/fpgadataflow/test_fpgadataflow_checksum.py index c51030764c..81a4e3e33c 100644 --- a/tests/fpgadataflow/test_fpgadataflow_checksum.py +++ b/tests/fpgadataflow/test_fpgadataflow_checksum.py @@ -141,6 +141,7 @@ def test_fpgadataflow_checksum(): # use a graph consisting of two fc layers to test # checksum node insertion model = create_two_fc_model() + model = model.transform(SpecializeLayers()) # set checksum output hook for n in model.graph.node: From 83fe7e83e8bbe7d2044b2d15520753530362cde3 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Mon, 4 Mar 2024 12:23:22 +0000 Subject: [PATCH 539/665] [rtl mvu]: added MVU_rtl layer --- .../rtl/matrixvectoractivation_rtl.py | 307 ++++++++++++++++++ 1 file changed, 307 insertions(+) create mode 100644 src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py diff --git a/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py new file mode 100644 index 0000000000..ae04b003bd --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py @@ -0,0 +1,307 @@ +# Copyright (C) 2024, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import numpy as np +import os +from pyverilator.util.axi_utils import reset_rtlsim, toggle_clk + +from finn.custom_op.fpgadataflow.matrixvectoractivation import MVAU +from finn.custom_op.fpgadataflow.rtlbackend import RTLBackend +from finn.util.basic import get_rtlsim_trace_depth, make_build_dir +from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy +from finn.util.fpgadataflow import is_versal + +try: + from pyverilator import PyVerilator +except ModuleNotFoundError: + PyVerilator = None + + +# ONNX i/o tensor shape assumptions for MatrixVectorActivation: +# input 0 is the input tensor, shape (.., i_size) = (..., MW) +# input 1 is the weight tensor, shape (i_size, o_size) = (MW, MH) +# (optional) input 2 is the thresholds tensor, shape (o_size, n_thres) +# output 0 is the output tensor, shape (.., o_size) = (..., MH) +# the ... here can be any shape (representing groups of vectors) + + +class MVAU_rtl(MVAU, RTLBackend): + """Class that corresponds to finn-rtl Matrix Vector Unit.""" + + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) + + def get_nodeattr_types(self): + my_attrs = {} + my_attrs.update(MVAU.get_nodeattr_types(self)) + my_attrs.update(RTLBackend.get_nodeattr_types(self)) + return my_attrs + + def execute_node(self, context, graph): + mode = self.get_nodeattr("exec_mode") + mem_mode = self.get_nodeattr("mem_mode") + node = self.onnx_node + + if mode == "cppsim": + raise Exception("cppsim not possible for RTL MVAU, please set exec_mode to rtlsim") + elif mode == "rtlsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + + # create a npy file fore each input of the node (in_ind is input index) + in_ind = 0 + for inputs in node.input: + # it is assumed that the first input of the node is the data input + # the second input are the weights + if in_ind == 0: + assert ( + str(context[inputs].dtype) == "float32" + ), """Input datatype is + not float32 as expected.""" + expected_inp_shape = self.get_folded_input_shape() + reshaped_input = context[inputs].reshape(expected_inp_shape) + export_idt = self.get_input_datatype() + # make copy before saving the array + reshaped_input = reshaped_input.copy() + np.save( + os.path.join(code_gen_dir, "input_{}.npy".format(in_ind)), + reshaped_input, + ) + elif in_ind > 2: + raise Exception("Unexpected input found for MatrixVectorActivation_rtl") + in_ind += 1 + + if mode == "rtlsim": + sim = self.get_rtlsim() + nbits = self.get_instream_width() + inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) + reset_rtlsim(sim) + toggle_clk(sim) + if mem_mode in ["external", "decoupled"]: + wnbits = self.get_weightstream_width() + export_wdt = self.get_weight_datatype() + wei = npy_to_rtlsim_input("{}/weights.npy".format(code_gen_dir), export_wdt, wnbits) + num_w_reps = np.prod(self.get_nodeattr("numInputVectors")) + io_dict = { + "inputs": {"in0": inp, "weights": wei * num_w_reps}, + "outputs": {"out": []}, + } + self.rtlsim_multi_io(sim, io_dict) + output = io_dict["outputs"]["out"] + else: + output = self.rtlsim(sim, inp) + odt = self.get_output_datatype() + target_bits = odt.bitwidth() + packed_bits = self.get_outstream_width() + out_npy_path = "{}/output.npy".format(code_gen_dir) + out_shape = self.get_folded_output_shape() + rtlsim_output_to_npy(output, out_npy_path, odt, out_shape, packed_bits, target_bits) + # load and reshape output + output = np.load(out_npy_path) + oshape = self.get_normal_output_shape() + output = np.asarray([output], dtype=np.float32).reshape(*oshape) + context[node.output[0]] = output + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to "rtlsim" """.format( + mode + ) + ) + + def lut_estimation(self): + return 0 + + def dsp_estimation(self): + # multiplication + P = self.get_nodeattr("PE") + res_type = self.get_nodeattr("resType") + Q = self.get_nodeattr("SIMD") + wdt = self.get_weight_datatype() + W = wdt.bitwidth() + idt = self.get_input_datatype() + A = idt.bitwidth() + if res_type == "dsp": + mult_dsp = P * Q * np.ceil((W + A) / 48) # TODO: more accurate modelling + else: + mult_dsp = 0 + return int(mult_dsp) + + def code_generation_ipgen(self, model, fpgapart, clk): + self.generate_hdl(model, fpgapart, clk) + + def instantiate_ip(self, cmd): + # instantiate the RTL IP + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + rtllib_dir = os.path.join(os.environ["FINN_ROOT"], "finn-rtllib/mvu/") + sourcefiles = [ + os.path.join(code_gen_dir, self.get_nodeattr("gen_top_module") + "_wrapper.v"), + rtllib_dir + "mvu_vvu_axi.sv", + rtllib_dir + "replay_buffer.sv", + rtllib_dir + "mvu_4sx4u.sv", + rtllib_dir + "mvu_vvu_8sx9_dsp58.sv", + rtllib_dir + "mvu_8sx8u_dsp48.sv", + ] + for f in sourcefiles: + cmd.append("add_files -norecurse %s" % (f)) + cmd.append( + "create_bd_cell -type hier -reference %s /%s/%s" + % ( + self.get_nodeattr("gen_top_module"), + self.onnx_node.name, + self.onnx_node.name, + ) + ) + + def _resolve_segment_len(self, clk): + # Insert pipeline registers in the DSP58 chain to meet target clock frequency + # ~0.741 ns seems the worst-case delay through first DSP + # ~0.605 ns seems to be (on average) delay for all subsequent DSPs + # clk >= (critical_path_dsps - 1) * 0.605 + 0.741 + assert ( + clk > 0.741 + ), """Infeasible clk target of {} ns has been set, + consider lowering the targeted clock frequency!""".format( + clk + ) + critical_path_dsps = np.floor((clk - 0.741) / 0.605 + 1) + max_chain_len = np.ceil(self.get_nodeattr("SIMD") / 3) + dsp_chain_len = critical_path_dsps if critical_path_dsps < max_chain_len else max_chain_len + return dsp_chain_len + + def _resolve_impl_style(self, fpgapart): + # Based on target device and activation/weight-width, choose the + # supported RTL compute core + assert ( + self.get_nodeattr("resType") != "lut" + ), """LUT-based RTL-MVU implementation currently not supported! + Please change resType for {}""".format( + self.onnx_node.name + ) + + act_width = self.get_input_datatype(0).bitwidth() + weight_width = self.get_input_datatype(1).bitwidth() + is_versal_family = is_versal(fpgapart) + + if is_versal_family: + return "mvu_vvu_8sx9_dsp58" + else: + act_width = self.get_input_datatype(0).bitwidth() + weight_width = self.get_input_datatype(1).bitwidth() + if (act_width == 4 and weight_width == 4) and not (is_versal_family): + return "mvu_4sx4u" + else: + return "mvu_8sx8u_dsp48" + + def generate_hdl(self, model, fpgapart, clk): + # Generate params as part of IP preparation + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + self.generate_params(model, code_gen_dir) + + template_path, code_gen_dict = self.prepare_codegen_default(fpgapart, clk) + # add general parameters to dictionary + code_gen_dict["$MODULE_NAME_AXI_WRAPPER$"] = [self.get_verilog_top_module_name()] + # save top module name so we can refer to it after this node has been renamed + # (e.g. by GiveUniqueNodeNames(prefix) during MakeZynqProject) + self.set_nodeattr("gen_top_module", self.get_verilog_top_module_name()) + + # apply code generation to template + with open(template_path, "r") as f: + template_wrapper = f.read() + for key in code_gen_dict: + # transform list into long string separated by '\n' + code_gen_line = "\n".join(code_gen_dict[key]) + template_wrapper = template_wrapper.replace(key, code_gen_line) + with open( + os.path.join(code_gen_dir, self.get_nodeattr("gen_top_module") + "_wrapper.v"), + "w", + ) as f: + f.write(template_wrapper.replace("$FORCE_BEHAVIORAL$", str(0))) + with open( + os.path.join(code_gen_dir, self.get_nodeattr("gen_top_module") + "_wrapper_sim.v"), + "w", + ) as f: + f.write(template_wrapper.replace("$FORCE_BEHAVIORAL$", str(1))) + + # set ipgen_path and ip_path so that HLS-Synth transformation + # and stich_ip transformation do not complain + self.set_nodeattr("ipgen_path", code_gen_dir) + self.set_nodeattr("ip_path", code_gen_dir) + + def prepare_codegen_default(self, fpgapart, clk): + template_path = os.environ["FINN_ROOT"] + "/finn-rtllib/mvu/mvu_vvu_axi_wrapper.v" + + code_gen_dict = {} + code_gen_dict["$IS_MVU$"] = [str(1)] + code_gen_dict["$COMPUTE_CORE$"] = [self._resolve_impl_style(fpgapart)] + # code_gen_dict["$PUMPED_COMPUTE$"] = [str(0)] + code_gen_dict["$MW$"] = [str(self.get_nodeattr("MW"))] + code_gen_dict["$MH$"] = [str(self.get_nodeattr("MH"))] + code_gen_dict["$PE$"] = [str(self.get_nodeattr("PE"))] + code_gen_dict["$SIMD$"] = [str(self.get_nodeattr("SIMD"))] + code_gen_dict["$ACTIVATION_WIDTH$"] = [str(self.get_input_datatype(0).bitwidth())] + code_gen_dict["$WEIGHT_WIDTH$"] = [str(self.get_input_datatype(1).bitwidth())] + code_gen_dict["$ACCU_WIDTH$"] = [str(self.get_output_datatype().bitwidth())] + code_gen_dict["$SIGNED_ACTIVATIONS$"] = ( + [str(1)] if (self.get_input_datatype(0).min() < 0) else [str(0)] + ) + code_gen_dict["$SEGMENTLEN$"] = [str(self._resolve_segment_len(clk))] + + return template_path, code_gen_dict + + def prepare_rtlsim(self): + """Creates a Verilator emulation library for the RTL code generated + for this node, sets the rtlsim_so attribute to its path and returns + a PyVerilator wrapper around it.""" + + if PyVerilator is None: + raise ImportError("Installation of PyVerilator is required.") + + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + # Path to (System-)Verilog files used by top-module & path to top-module + verilog_paths = [code_gen_dir, os.environ["FINN_ROOT"] + "/finn-rtllib/mvu"] + verilog_files = [self.get_nodeattr("gen_top_module") + "_wrapper_sim.v"] + + # build the Verilator emu library + sim = PyVerilator.build( + verilog_files, + build_dir=make_build_dir("pyverilator_" + self.onnx_node.name + "_"), + verilog_path=verilog_paths, + trace_depth=get_rtlsim_trace_depth(), + top_module_name=self.get_verilog_top_module_name(), + ) + # save generated lib filename in attribute + self.set_nodeattr("rtlsim_so", sim.lib._name) + + return sim From 4f19aa44238fd62b70e4f7cfeff12590694ce380 Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 4 Mar 2024 12:32:35 +0000 Subject: [PATCH 540/665] [Tests] Fix for cppsim with impl style rtl in SWG --- tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py index 1fe96d6bd7..5de6e7c1d1 100644 --- a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py +++ b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py @@ -217,7 +217,10 @@ def test_fpgadataflow_slidingwindow( # execute model y_produced = oxe.execute_onnx(model, input_dict)["outp"] - if dw == 0: + # if cppsim and impl style rtl is selected, the node execution is done by the hw op parent + # so, no reordering/shaping of the output is needed + # because there is no concept of SIMD parallelism in the hw abstraction layer execution + if dw == 0 or (impl_style == "rtl" and exec_mode == "cppsim"): assert (y_produced == y_expected).all() else: y_expected = y_expected.reshape(1, ofm_dim_h, ofm_dim_w, k_h * k_w, ifm_ch // simd, simd) From 649c4284b5348d159fc8819ce6690444c09ffc29 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Mon, 4 Mar 2024 15:30:53 +0000 Subject: [PATCH 541/665] [test]: added mvau_rtl test case --- tests/fpgadataflow/test_fpgadataflow_mvau.py | 101 +++++++++---------- 1 file changed, 45 insertions(+), 56 deletions(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_mvau.py b/tests/fpgadataflow/test_fpgadataflow_mvau.py index 85cca66835..5f979e0b76 100644 --- a/tests/fpgadataflow/test_fpgadataflow_mvau.py +++ b/tests/fpgadataflow/test_fpgadataflow_mvau.py @@ -26,8 +26,6 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import os -import pickle import pytest import numpy as np @@ -37,7 +35,12 @@ from qonnx.core.modelwrapper import ModelWrapper from qonnx.custom_op.general.multithreshold import multithreshold from qonnx.custom_op.registry import getCustomOp -from qonnx.transformation.general import GiveUniqueNodeNames, GiveReadableTensorNames, ApplyConfig +from qonnx.transformation.general import ( + ApplyConfig, + GiveReadableTensorNames, + GiveUniqueNodeNames, +) +from qonnx.transformation.infer_datatypes import InferDataTypes from qonnx.util.basic import ( calculate_signed_dot_prod_range, gen_finn_dt_tensor, @@ -45,19 +48,25 @@ ) import finn.core.onnx_exec as oxe +import finn.transformation.fpgadataflow.convert_to_hw_layers as to_hw from finn.analysis.fpgadataflow.exp_cycles_per_layer import exp_cycles_per_layer from finn.analysis.fpgadataflow.hls_synth_res_estimation import hls_synth_res_estimation from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim +from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP from finn.transformation.fpgadataflow.derive_characteristic import DeriveCharacteristic from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP +from finn.transformation.fpgadataflow.minimize_accumulator_width import ( + MinimizeAccumulatorWidth, +) +from finn.transformation.fpgadataflow.minimize_weight_bit_width import ( + MinimizeWeightBitWidth, +) from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode -from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers -import finn.transformation.fpgadataflow.convert_to_hw_layers as to_hw from finn.transformation.fpgadataflow.set_fifo_depths import InsertAndSetFIFODepths -from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP +from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers def make_single_fclayer_modelwrapper(W, pe, simd, wdt, idt, odt, T=None, tdt=None): @@ -394,6 +403,7 @@ def test_fpgadataflow_mvau_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): inst = getCustomOp(node) inst.set_nodeattr("mem_mode", mem_mode) inst.set_nodeattr("rtlsim_trace", "mvau_trace.vcd") + inst.set_nodeattr("preferred_impl_style", "hls") # prepare input data input_dict = prepare_inputs(x, idt, wdt) @@ -610,36 +620,26 @@ def test_mvau_fifocharacterize_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh, b assert chrc_out[0, exp_total_cycles] == nf -# @pytest.mark.parametrize("mh", [36]) -# @pytest.mark.parametrize("mw", [256]) -@pytest.mark.parametrize("mh", [1]) -@pytest.mark.parametrize("mw", [8]) -# @pytest.mark.parametrize("pe", [1, 4, 9, 36]) -# @pytest.mark.parametrize("simd", [1, 4, 16, 64, 256]) -# @pytest.mark.parametrize("pe", [1, 3, 9]) -# @pytest.mark.parametrize("simd", [1, 3, 6, 18, 36]) -@pytest.mark.parametrize("pe", [1]) -@pytest.mark.parametrize("simd", [4]) -# @pytest.mark.parametrize("idt", [DataType["UINT4"], DataType["UINT8"]]) -# @pytest.mark.parametrize("wdt", [DataType["INT4"], DataType["INT8"]]) -@pytest.mark.parametrize("idt", [DataType["UINT4"]]) -@pytest.mark.parametrize("wdt", [DataType["INT4"]]) -# @pytest.mark.parametrize("part", ["xcvc1902-vsva2197-2MP-e-S", "xcku3p-ffva676-1-e"]) -@pytest.mark.parametrize("part", ["xcvc1902-vsva2197-2MP-e-S"]) -# @pytest.mark.parametrize("clk_ns", [1.66, 4]) -@pytest.mark.parametrize("clk_ns", [4]) +@pytest.mark.parametrize("mh", [18]) +@pytest.mark.parametrize("mw", [128]) +@pytest.mark.parametrize("pe", [1, 6, 9, 18]) +@pytest.mark.parametrize("simd", [1, 4, 16, 64, 128]) +@pytest.mark.parametrize("idt", [DataType["UINT4"], DataType["UINT8"]]) +@pytest.mark.parametrize("wdt", [DataType["INT4"], DataType["INT8"]]) +@pytest.mark.parametrize("part", ["xcvc1902-vsva2197-2MP-e-S", "xcku3p-ffva676-1-e"]) +@pytest.mark.parametrize("clk_ns", [1.66, 4]) @pytest.mark.fpgadataflow @pytest.mark.slow @pytest.mark.vivado -def test_fpgadataflow_rtl_mvau( - mh, mw, pe, simd, idt, wdt, part, clk_ns -): +def test_fpgadataflow_rtl_mvau(mh, mw, pe, simd, idt, wdt, part, clk_ns): if part == "xcku3p-ffva676-1-e" and clk_ns != 1.66: - pytest.skip("Skip test for varying clk for devices other than Versal, since this variable doesn't change anything for this test") + pytest.skip( + """Skip test for varying clk for devices other than Versal, + since this variable only affects DSP58s""" + ) - build_dir = os.environ["FINN_BUILD_DIR"] # Create test input vector (produced by SWG) - ofm_shape = (2, 2) + ofm_shape = (3, 3) ofm_h, ofm_w = ofm_shape ifm = helper.make_tensor_value_info("ifm", TensorProto.FLOAT, [1, ofm_h, ofm_w, mw]) ofm = helper.make_tensor_value_info("ofm", TensorProto.FLOAT, (1, ofm_h, ofm_w, mh)) @@ -648,18 +648,15 @@ def test_fpgadataflow_rtl_mvau( model = model.transform(GiveUniqueNodeNames()) model = model.transform(GiveReadableTensorNames()) - model.save(build_dir + "/matmul.onnx") - # Create MatMul & obtain golden reference output - A = gen_finn_dt_tensor(model.get_tensor_datatype("global_in"), model.get_tensor_shape("global_in")) + A = gen_finn_dt_tensor( + model.get_tensor_datatype("global_in"), model.get_tensor_shape("global_in") + ) input_dict = prepare_inputs(A, idt, wdt, inp_name="global_in") # Execute ONNX model output_matmul = oxe.execute_onnx(model, input_dict)["global_out"] - with open(build_dir + "/onnx_output.pkl", "wb") as f: - pickle.dump(output_matmul, f) - # Create MVAU (HLS) model = model.transform(to_hw.InferQuantizedMatrixVectorActivation(mem_mode="decoupled")) model = model.transform(GiveUniqueNodeNames()) @@ -671,46 +668,38 @@ def test_fpgadataflow_rtl_mvau( "PE": pe, "SIMD": simd, "mem_mode": "decoupled", - "ram_style": "auto", "resType": "dsp", - "preferred_impl_style" : "rtl" + "preferred_impl_style": "rtl", }, } model = model.transform(ApplyConfig(folding_config)) - model.save(build_dir + "/mvau_hls.onnx") + model = model.transform(MinimizeWeightBitWidth()) + model = model.transform(MinimizeAccumulatorWidth()) + # make sure the changed datatypes are propagated through the network + model = model.transform(InferDataTypes()) # Apply convert-to-rtl step - model = model.transform(SpecializeLayers()) + model = model.transform(SpecializeLayers(part)) model = model.transform(GiveUniqueNodeNames()) - model.save(build_dir + "/mvau_rtl.onnx") - - # Reset rtlsim_so and ip-related paths such that new Pyverilator SO and IP is generated - for n in model.graph.node: - getCustomOp(n).set_nodeattr("rtlsim_trace", build_dir + "/mvu_trace_rtl_nodebynode.vcd") - model = model.transform(SetExecMode("rtlsim")) model = model.transform(PrepareIP(part, clk_ns)) model = model.transform(HLSSynthIP()) model = model.transform(PrepareRTLSim()) output_mvau_rtl = oxe.execute_onnx(model, input_dict)["global_out"] - with open(build_dir + "/mvau_rtl_output.pkl", "wb") as f: - pickle.dump(output_mvau_rtl, f) - - model.save(build_dir + "/mvau_rtl_sim.onnx") - import pdb; pdb.set_trace() - assert (output_matmul == output_mvau_rtl).all(), "Output of ONNX model not matching output of node-by-node sim!" + assert ( + output_matmul == output_mvau_rtl + ).all(), "Output of ONNX model not matching output of node-by-node sim!" model = model.transform(InsertAndSetFIFODepths(part, clk_ns)) model = model.transform(PrepareIP(part, clk_ns)) model = model.transform(HLSSynthIP()) model = model.transform(CreateStitchedIP(part, clk_ns)) - os.environ["RTLSIM_TRACE_DEPTH"] = "3" model.set_metadata_prop("rtlsim_so", "") model.set_metadata_prop("exec_mode", "rtlsim") - model.set_metadata_prop("rtlsim_trace", build_dir + "/mvu_trace_rtl_stitch.vcd") - model.save(build_dir + "/stitched_ip.onnx") output_mvau_rtl_stitch = oxe.execute_onnx(model, input_dict)["global_out"] - assert (output_matmul == output_mvau_rtl_stitch).all(), "Output of ONNX model not matching output of stitched-IP RTL model!" \ No newline at end of file + assert ( + output_matmul == output_mvau_rtl_stitch + ).all(), "Output of ONNX model not matching output of stitched-IP RTL model!" From 87f551fc3f237ffb35e8df823c8d88e5180d6e7c Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 5 Mar 2024 11:13:36 +0000 Subject: [PATCH 542/665] [Pre-commit] Run linting --- .../fpgadataflow/rtl/thresholding_rtl.py | 46 +++++----- .../custom_op/fpgadataflow/thresholding.py | 5 +- src/finn/util/basic.py | 4 +- .../test_convert_to_hw_thresholding.py | 2 +- .../test_fpgadataflow_thresholding.py | 83 ++++++++++--------- 5 files changed, 77 insertions(+), 63 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py index 4adde1452d..6ee940883a 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py @@ -31,7 +31,7 @@ import os import shutil import warnings -from pyverilator.util.axi_utils import rtlsim_multi_io, reset_rtlsim +from pyverilator.util.axi_utils import reset_rtlsim, rtlsim_multi_io from qonnx.core.datatype import DataType from qonnx.util.basic import roundup_to_integer_multiple @@ -76,7 +76,7 @@ def get_nodeattr_types(self): # setting to 0 may save some FFs but otherwise leave on "deep_pipeline": ("i", False, 1, {0, 1}), } - my_attrs.update(Thresholding.get_nodeattr_types(self)) + my_attrs.update(Thresholding.get_nodeattr_types(self)) my_attrs.update(RTLBackend.get_nodeattr_types(self)) return my_attrs @@ -314,7 +314,7 @@ def generate_hdl(self, model): weights = model.get_initializer(self.onnx_node.input[1]) weights_fname = f"{code_gen_dir}/memblock.dat" - self.make_weight_file(weights,"decoupled", weights_fname) + self.make_weight_file(weights, "decoupled", weights_fname) for rtl_file_path in self.get_rtl_file_paths(): # read in original RTL template file @@ -346,7 +346,9 @@ def prepare_rtlsim(self): code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") verilog_paths = [code_gen_dir] - verilog_files = [x.replace("template", self.onnx_node.name) for x in self.get_rtl_file_list()] + verilog_files = [ + x.replace("template", self.onnx_node.name) for x in self.get_rtl_file_list() + ] dat_files = self.get_all_meminit_filenames(abspath=True) single_src_dir = make_build_dir("pyverilator_" + self.onnx_node.name + "_") for dat_file in dat_files: @@ -376,7 +378,9 @@ def execute_node(self, context, graph): ) mode = self.get_nodeattr("exec_mode") if mode == "cppsim": - raise Exception("cppsim not possible for RTL Thresholding, please set exec_mode to rtlsim") + raise Exception( + "cppsim not possible for RTL Thresholding, please set exec_mode to rtlsim" + ) elif mode == "rtlsim": code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") else: @@ -442,13 +446,14 @@ def execute_node(self, context, graph): os.chdir(so_dir) num_out_values = self.get_number_output_values() reset_rtlsim(sim) - total_cycle_count = rtlsim_multi_io(sim, - io_dict, - num_out_values, - trace_file=trace_file, - sname=sname, - liveness_threshold=pyverilate_get_liveness_threshold_cycles() - ) + total_cycle_count = rtlsim_multi_io( + sim, + io_dict, + num_out_values, + trace_file=trace_file, + sname=sname, + liveness_threshold=pyverilate_get_liveness_threshold_cycles(), + ) self.set_nodeattr("cycles_rtlsim", total_cycle_count) os.chdir(olcwd) output = io_dict["outputs"][ostream_name] @@ -472,7 +477,9 @@ def execute_node(self, context, graph): def code_generation_ipi(self): """Constructs and returns the TCL commands for node instantiation as an RTL block.""" - rtl_file_list = [x.replace("template", self.onnx_node.name) for x in self.get_rtl_file_list()] + rtl_file_list = [ + x.replace("template", self.onnx_node.name) for x in self.get_rtl_file_list() + ] code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") source_target = "./ip/verilog/rtl_ops/%s" % self.onnx_node.name cmd = ["file mkdir %s" % source_target] @@ -565,6 +572,7 @@ def generate_params(self, model, path): """Please set mem_mode to "const", "decoupled", currently no other parameter value is supported!""" ) + def make_weight_file(self, weights, weight_file_mode, weight_file_name): """Produce a file containing given weights (thresholds) in appropriate format for this layer. This file can be used for either synthesis or @@ -587,24 +595,24 @@ def make_weight_file(self, weights, weight_file_mode, weight_file_name): n_thres_steps = self.get_nodeattr("numSteps") width_padded = roundup_to_integer_multiple(weights.shape[1], 4) - weight_padded = np.zeros((weights.shape[0],width_padded)) - weight_padded[:weights.shape[0], :n_thres_steps ] = weights + weight_padded = np.zeros((weights.shape[0], width_padded)) + weight_padded[: weights.shape[0], :n_thres_steps] = weights weight_stream = [] wdt = self.get_weight_datatype() bw_hexdigit = roundup_to_integer_multiple(wdt.bitwidth(), 32) padding = np.zeros(width_padded, dtype=np.int32) chan_ind = 0 - cf = ch//pe + cf = ch // pe for fold in range(cf): - for c in range(2**(pe-1).bit_length()): - if (c==0 or c%pe != 0) and c < pe: + for c in range(2 ** (pe - 1).bit_length()): + if (c == 0 or c % pe != 0) and c < pe: for w in weight_padded[chan_ind]: w_packed = pack_innermost_dim_as_hex_string( [w], wdt, bw_hexdigit, prefix="" ).item() weight_stream.append(w_packed) - chan_ind +=1 + chan_ind += 1 else: for z in padding: w_packed = pack_innermost_dim_as_hex_string( diff --git a/src/finn/custom_op/fpgadataflow/thresholding.py b/src/finn/custom_op/fpgadataflow/thresholding.py index d3ba724818..822bb1476f 100644 --- a/src/finn/custom_op/fpgadataflow/thresholding.py +++ b/src/finn/custom_op/fpgadataflow/thresholding.py @@ -31,6 +31,7 @@ from qonnx.core.datatype import DataType from qonnx.custom_op.general.multithreshold import multithreshold from qonnx.util.basic import interleave_matrix_outer_dim_from_partitions + from finn.custom_op.fpgadataflow.hwcustomop import HWCustomOp @@ -165,7 +166,6 @@ def get_outstream_width(self, ind=0): return o_bits * self.get_nodeattr("PE") def get_folded_input_shape(self, ind=0): - ich = self.get_nodeattr("NumChannels") pe = self.get_nodeattr("PE") fold = self.calc_tmem() vecs = list(self.get_nodeattr("numInputVectors")) @@ -194,7 +194,6 @@ def get_exp_cycles(self): # Channels/PE * batch size * fmdim * fmdim return np.prod(self.get_folded_output_shape()[:-1]) - def get_hw_compatible_threshold_tensor(self, orig_thres_matrix): """Convert the original numpy weight matrix orig_weight_matrix into a form suitable for passing to the hlslib call: @@ -259,4 +258,4 @@ def calc_tmem(self): """Calculates and returns TMEM.""" num_channels = self.get_nodeattr("NumChannels") pe = self.get_nodeattr("PE") - return num_channels // pe \ No newline at end of file + return num_channels // pe diff --git a/src/finn/util/basic.py b/src/finn/util/basic.py index 49220e9718..10edb7dc54 100644 --- a/src/finn/util/basic.py +++ b/src/finn/util/basic.py @@ -270,7 +270,7 @@ def find_next_power_of_2(n): def get_memutil_alternatives( req_mem_spec, mem_primitives=mem_primitives_versal, sort_min_waste=True ): - '''Computes how many instances of a memory primitive are necessary to + """Computes how many instances of a memory primitive are necessary to implement a desired memory size, where req_mem_spec is the desired size and the primitive_spec is the primitve size. The sizes are expressed as tuples of (mem_width, mem_depth). Returns a list of tuples of the form @@ -278,7 +278,7 @@ def get_memutil_alternatives( range [0,1] indicates how much of the total capacity is utilized, and waste indicates how many bits of storage are wasted. If sort_min_waste is True, the list is sorted by increasing waste. - ''' + """ ret = [ (primitive_name, memutil(req_mem_spec, primitive_spec)) for (primitive_name, primitive_spec) in mem_primitives.items() diff --git a/tests/fpgadataflow/test_convert_to_hw_thresholding.py b/tests/fpgadataflow/test_convert_to_hw_thresholding.py index 3f0487f9f7..ee161a9b95 100755 --- a/tests/fpgadataflow/test_convert_to_hw_thresholding.py +++ b/tests/fpgadataflow/test_convert_to_hw_thresholding.py @@ -32,10 +32,10 @@ from onnx import TensorProto, helper from qonnx.core.datatype import DataType from qonnx.core.modelwrapper import ModelWrapper +from qonnx.custom_op.registry import getCustomOp from qonnx.transformation.general import GiveUniqueNodeNames from qonnx.transformation.infer_datatypes import InferDataTypes from qonnx.transformation.infer_shapes import InferShapes -from qonnx.custom_op.registry import getCustomOp from finn.transformation.fpgadataflow.convert_to_hw_layers import InferThresholdingLayer from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers diff --git a/tests/fpgadataflow/test_fpgadataflow_thresholding.py b/tests/fpgadataflow/test_fpgadataflow_thresholding.py index 62d7b04278..899773b680 100644 --- a/tests/fpgadataflow/test_fpgadataflow_thresholding.py +++ b/tests/fpgadataflow/test_fpgadataflow_thresholding.py @@ -42,7 +42,7 @@ import finn.core.onnx_exec as oxe from finn.analysis.fpgadataflow.exp_cycles_per_layer import exp_cycles_per_layer from finn.analysis.fpgadataflow.hls_synth_res_estimation import hls_synth_res_estimation -from finn.core.rtlsim_exec import rtlsim_exec, reset_rtlsim +from finn.core.rtlsim_exec import rtlsim_exec from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP @@ -56,6 +56,7 @@ test_fpga_part = "xczu3eg-sbva484-1-e" target_clk_ns = 5 + def generate_random_threshold_values(input_data_type, num_input_channels, num_steps): return np.random.randint( input_data_type.min(), @@ -63,21 +64,26 @@ def generate_random_threshold_values(input_data_type, num_input_channels, num_st (num_input_channels, num_steps), ).astype(np.float32) + def sort_thresholds_increasing(thresholds): return np.sort(thresholds, axis=1) + # n = batch, c = channel, h = height, w = width of feature map # Standard = NCHW; FINN = NHWC # Convert from NHWC(FINN) to NCHW(Standard) def layout_FINN2NCHW(data): return np.transpose(data, (0, 3, 1, 2)) + # Convert from NCHW(Standard) to NHWC(FINN) def layout_NCHW2FINN(data): return np.transpose(data, (0, 2, 3, 1)) -def make_single_thresholding_modelwrapper(impl_style, T, pe, idt, odt, actval, mem_mode, n_inp_vecs): +def make_single_thresholding_modelwrapper( + impl_style, T, pe, idt, odt, actval, mem_mode, n_inp_vecs +): NumChannels = T.shape[0] inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, n_inp_vecs + [NumChannels]) @@ -100,7 +106,7 @@ def make_single_thresholding_modelwrapper(impl_style, T, pe, idt, odt, actval, m ActVal=actval, mem_mode=mem_mode, numInputVectors=n_inp_vecs, - preferred_impl_style=impl_style + preferred_impl_style=impl_style, ) graph = helper.make_graph( nodes=[Thresholding_node], @@ -136,7 +142,7 @@ def make_single_thresholding_modelwrapper(impl_style, T, pe, idt, odt, actval, m @pytest.mark.fpgadataflow @pytest.mark.vivado @pytest.mark.slow -def test_fpgadataflow_thresholding(impl_style,idt, act, nf, ich, exec_mode, mem_mode): +def test_fpgadataflow_thresholding(impl_style, idt, act, nf, ich, exec_mode, mem_mode): if impl_style == "rtl" and exec_mode == "cppsim": pytest.skip("rtl implstyle has no cppsim, skipping") if nf == -1: @@ -152,9 +158,7 @@ def test_fpgadataflow_thresholding(impl_style,idt, act, nf, ich, exec_mode, mem_ n_steps = act.get_num_possible_values() - 1 # Generate random, non-decreasing thresholds - thresholds = generate_random_threshold_values( - idt, ich, n_steps - ) + thresholds = generate_random_threshold_values(idt, ich, n_steps) thresholds = sort_thresholds_increasing(thresholds) @@ -165,15 +169,8 @@ def test_fpgadataflow_thresholding(impl_style,idt, act, nf, ich, exec_mode, mem_ # Build DUT model = make_single_thresholding_modelwrapper( - impl_style, - thresholds, - pe, - idt, - odt, - actval, - mem_mode, - n_inp_vecs - ) + impl_style, thresholds, pe, idt, odt, actval, mem_mode, n_inp_vecs + ) # Expected Reference output # multithreshold util fxn wants NCHW input, not NHWC @@ -238,17 +235,18 @@ def test_fpgadataflow_thresholding(impl_style,idt, act, nf, ich, exec_mode, mem_ assert np.isclose(exp_cycles, cycles_rtlsim, atol=15) assert exp_cycles != 0 + @pytest.mark.parametrize("impl_style", ["rtl", "hls"]) -@pytest.mark.parametrize("cfg", [(1,1), (6,2), (6,3), (8,2), (8,4)]) +@pytest.mark.parametrize("cfg", [(1, 1), (6, 2), (6, 3), (8, 2), (8, 4)]) @pytest.mark.fpgadataflow @pytest.mark.vivado -def test_runtime_thresholds_read(impl_style,cfg): - """ Read back threshold weights during runtime +def test_runtime_thresholds_read(impl_style, cfg): + """Read back threshold weights during runtime - 1. Create random initial weights T - 2. Execute model - 3. Read back weights via AXI - 4. Compare with initial weights T + 1. Create random initial weights T + 2. Execute model + 3. Read back weights via AXI + 4. Compare with initial weights T """ ch = cfg[0] pe = cfg[1] @@ -268,7 +266,9 @@ def test_runtime_thresholds_read(impl_style,cfg): else: actval = odt.min() - model = make_single_thresholding_modelwrapper(impl_style, T, pe, idt, odt, actval, mem_mode, n_inp_vecs) + model = make_single_thresholding_modelwrapper( + impl_style, T, pe, idt, odt, actval, mem_mode, n_inp_vecs + ) model = model.transform(SpecializeLayers()) # Make sure that specialize layer did not default to HLS implementation @@ -303,6 +303,7 @@ def test_runtime_thresholds_read(impl_style,cfg): exec_ctx = {"inp": in_tensor} extracted_weight_stream = [] + def read_weights(sim): addr = 0 for i in range(len(old_weight_stream)): @@ -331,20 +332,21 @@ def read_weights(sim): # Validate the output is as expected assert (y == expected).all() + @pytest.mark.parametrize("impl_style", ["hls", "rtl"]) -@pytest.mark.parametrize("cfg", [(1,1), (6,2), (6,3), (8,2), (8,4)]) +@pytest.mark.parametrize("cfg", [(1, 1), (6, 2), (6, 3), (8, 2), (8, 4)]) @pytest.mark.fpgadataflow @pytest.mark.vivado -def test_runtime_thresholds_write(impl_style,cfg): - """ Write threshold weights during runtime - - 1. Create random initial weights T_init - 2. Create model with initial weights - 3. Create new set of weights T_write - 4. Write T_write using AXI bus - 5. Read back using AXI bus to T_read - 6. Compare T_write and T_read - 7. Validate outputs with expected vectors +def test_runtime_thresholds_write(impl_style, cfg): + """Write threshold weights during runtime + + 1. Create random initial weights T_init + 2. Create model with initial weights + 3. Create new set of weights T_write + 4. Write T_write using AXI bus + 5. Read back using AXI bus to T_read + 6. Compare T_write and T_read + 7. Validate outputs with expected vectors """ ch = cfg[0] pe = cfg[1] @@ -366,7 +368,9 @@ def test_runtime_thresholds_write(impl_style,cfg): else: actval = odt.min() - model = make_single_thresholding_modelwrapper(impl_style, T_init, pe, idt, odt, actval, mem_mode, n_inp_vecs) + model = make_single_thresholding_modelwrapper( + impl_style, T_init, pe, idt, odt, actval, mem_mode, n_inp_vecs + ) model = model.transform(SpecializeLayers()) # Validate that specialize layer did not default to HLS implementation @@ -381,7 +385,7 @@ def test_runtime_thresholds_write(impl_style,cfg): # provide non-decreasing thresholds T_write = np.sort(T_write, axis=1) - dat_fname = f"T_write_{cfg}.dat" # distinguish fname per paramter for distributed testing + dat_fname = f"T_write_{cfg}.dat" # distinguish fname per paramter for distributed testing op_inst.make_weight_file(T_write, "decoupled_runtime", dat_fname) with open(dat_fname, "r") as f: T_write_stream = f.read().strip() @@ -407,12 +411,15 @@ def test_runtime_thresholds_write(impl_style,cfg): in_tensor = np.tile(in_tensor, (2, 1, 1, 1)) exec_ctx_write = {"inp": in_tensor} + def write_weights(sim): addr = 0 for nw in T_write_stream: axilite_write(sim, addr, nw, basename="s_axilite_0_") addr += 4 + T_read_stream = [] + def read_weights(sim): addr = 0 for i in range(len(T_write_stream)): @@ -438,4 +445,4 @@ def read_weights(sim): expected += act.min() # Validate the output is as expected - assert (y == expected).all() \ No newline at end of file + assert (y == expected).all() From f8c987ccccafe0b1bff449d325cfd74282e1f428 Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 5 Mar 2024 11:53:24 +0000 Subject: [PATCH 543/665] [RTL layers] Pass model by default to generate hdl functionality and clean up rtl thresholding class --- .../rtl/convolutioninputgenerator_rtl.py | 2 +- .../fpgadataflow/rtl/fmpadding_rtl.py | 2 +- .../rtl/streamingdatawidthconverter_rtl.py | 2 +- .../fpgadataflow/rtl/streamingfifo_rtl.py | 2 +- .../fpgadataflow/rtl/thresholding_rtl.py | 203 +++++++----------- src/finn/custom_op/fpgadataflow/rtlbackend.py | 2 +- .../test_fpgadataflow_thresholding.py | 2 - 7 files changed, 88 insertions(+), 127 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/rtl/convolutioninputgenerator_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/convolutioninputgenerator_rtl.py index 08564ca6da..4bce80c658 100755 --- a/src/finn/custom_op/fpgadataflow/rtl/convolutioninputgenerator_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/convolutioninputgenerator_rtl.py @@ -839,7 +839,7 @@ def select_impl_style(self): return impl_style - def generate_hdl(self): + def generate_hdl(self, model): """Generates HDL code and wrapper for the IP, depending on required implementation style.""" impl_style = self.select_impl_style() diff --git a/src/finn/custom_op/fpgadataflow/rtl/fmpadding_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/fmpadding_rtl.py index 19765d64c4..33293f45e1 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/fmpadding_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/fmpadding_rtl.py @@ -171,7 +171,7 @@ def get_dynamic_config(self, ifm_dims=None, pads=None): } return config - def generate_hdl(self): + def generate_hdl(self, model): rtlsrc = os.environ["FINN_ROOT"] + "/finn-rtllib/fmpadding/hdl" template_path = rtlsrc + "/fmpadding_template.v" dims = self.get_nodeattr("ImgDim") diff --git a/src/finn/custom_op/fpgadataflow/rtl/streamingdatawidthconverter_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/streamingdatawidthconverter_rtl.py index ef918b5db8..8afc6e7ad5 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/streamingdatawidthconverter_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/streamingdatawidthconverter_rtl.py @@ -137,7 +137,7 @@ def get_template_values(self): } return code_gen_dict - def generate_hdl(self): + def generate_hdl(self, model): rtlsrc = os.environ["FINN_ROOT"] + "/finn-rtllib/dwc/hdl" template_path = rtlsrc + "/dwc_template.v" code_gen_dict = self.get_template_values() diff --git a/src/finn/custom_op/fpgadataflow/rtl/streamingfifo_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/streamingfifo_rtl.py index a9d9e689eb..581d93394b 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/streamingfifo_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/streamingfifo_rtl.py @@ -82,7 +82,7 @@ def get_verilog_top_module_intf_names(self): ret["ap_none"] = ["maxcount"] return ret - def generate_hdl(self): + def generate_hdl(self, model): rtlsrc = os.environ["FINN_ROOT"] + "/finn-rtllib/fifo/hdl" template_path = rtlsrc + "/fifo_template.v" diff --git a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py index 6ee940883a..c39ae74a38 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py @@ -30,7 +30,6 @@ import numpy as np import os import shutil -import warnings from pyverilator.util.axi_utils import reset_rtlsim, rtlsim_multi_io from qonnx.core.datatype import DataType from qonnx.util.basic import roundup_to_integer_multiple @@ -116,28 +115,6 @@ def get_memory_estimate(self): res_dict[res_type] = res_dict.get(res_type, 0) + pe * res_count return res_dict - def infer_node_datatype(self, model): - """Used for FINN DataType inference: set the output tensors' datatypes - accordingly for this node""" - node = self.onnx_node - idt = model.get_tensor_datatype(node.input[0]) - if idt != self.get_input_datatype(): - warn_str = "inputDataType changing for %s: %s -> %s " % ( - node.name, - str(self.get_input_datatype().name), - str(idt.name), - ) - warnings.warn(warn_str) - self.set_nodeattr("inputDataType", idt.name) - # set output datatype from property - odt = self.get_output_datatype() - model.set_tensor_datatype(node.output[0], odt) - - def verify_node(self): - """Required by the FINN nalysis module. Checks if custom ops in graph - are correctly built, with all attributes and inputs.""" - return [] - def bram_estimation(self): res_dict = self.get_memory_estimate() return res_dict.get("BRAM", 0) @@ -301,9 +278,6 @@ def dump_rtl_data(self, dest_dir, filename, data): f.write(data) return - def code_generation_ipgen(self, model, fpgapart, clk): - self.generate_hdl(model) - def generate_hdl(self, model): """Prepare HDL files from templates for synthesis""" # Generate a dictionary of values to put in RTL template @@ -369,20 +343,92 @@ def prepare_rtlsim(self): return sim def execute_node(self, context, graph): - # Perform input checks - if self.get_nodeattr("exec_mode") != "rtlsim": - raise Exception( - "Invalid exec_mode value: {}; exec_mode must be set to '{}'".format( - self.get_nodeattr("exec_mode"), "rtlsim" - ) - ) mode = self.get_nodeattr("exec_mode") + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") if mode == "cppsim": - raise Exception( - "cppsim not possible for RTL Thresholding, please set exec_mode to rtlsim" - ) + Thresholding.execute_node(self, context, graph) elif mode == "rtlsim": - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + node = self.onnx_node + # create a npy file fore each input of the node (in_ind is input index) + in_ind = 0 + for inputs in node.input: + # it is assumed that the first input of the node is the data input + # the second input are the thresholds + if in_ind == 0: + assert ( + str(context[inputs].dtype) == "float32" + ), """Input datatype is + not float32 as expected.""" + expected_inp_shape = self.get_folded_input_shape() + reshaped_input = context[inputs].reshape(expected_inp_shape) + + if self.get_input_datatype() == DataType["BIPOLAR"]: + # store bipolar activations as binary + reshaped_input = (reshaped_input + 1) / 2 + export_idt = DataType["BINARY"] + else: + export_idt = self.get_input_datatype() + + # make copy before saving the array + reshaped_input = reshaped_input.copy() + np.save( + os.path.join(code_gen_dir, "input_{}.npy".format(in_ind)), + reshaped_input, + ) + elif in_ind > 2: + raise Exception("Unexpected input found for Thresholding_rtl") + in_ind += 1 + + # Create a PyVerilator wrapper of the RTLSim .so + sim = self.get_rtlsim() + nbits = self.get_instream_width() + inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) + io_names = self.get_verilog_top_module_intf_names() + istream_name = io_names["s_axis"][0][0] + ostream_name = io_names["m_axis"][0][0] + io_dict = { + "inputs": {istream_name: inp}, + "outputs": {ostream_name: []}, + } + + trace_file = self.get_nodeattr("rtlsim_trace") + if trace_file == "default": + trace_file = self.onnx_node.name + ".vcd" + sname = "_" + + # Change into so directory to ensure threshold files can be found + rtlsim_so = self.get_nodeattr("rtlsim_so") + so_dir = os.path.dirname(os.path.realpath(rtlsim_so)) + olcwd = os.getcwd() + os.chdir(so_dir) + num_out_values = self.get_number_output_values() + reset_rtlsim(sim) + total_cycle_count = rtlsim_multi_io( + sim, + io_dict, + num_out_values, + trace_file=trace_file, + sname=sname, + liveness_threshold=pyverilate_get_liveness_threshold_cycles(), + ) + self.set_nodeattr("cycles_rtlsim", total_cycle_count) + os.chdir(olcwd) + output = io_dict["outputs"][ostream_name] + + # Manage output data + odt = self.get_output_datatype() + target_bits = odt.bitwidth() + packed_bits = self.get_outstream_width() + out_npy_path = "{}/output.npy".format(code_gen_dir) + out_shape = self.get_folded_output_shape() + + rtlsim_output_to_npy(output, out_npy_path, odt, out_shape, packed_bits, target_bits) + + # load and reshape output + output = np.load(out_npy_path) + oshape = self.get_normal_output_shape() + output = np.asarray([output], dtype=np.float32).reshape(*oshape) + context[node.output[0]] = output else: raise Exception( """Invalid value for attribute exec_mode! Is currently set to: {} @@ -390,89 +436,6 @@ def execute_node(self, context, graph): mode ) ) - node = self.onnx_node - - # create a npy file fore each input of the node (in_ind is input index) - in_ind = 0 - for inputs in node.input: - # it is assumed that the first input of the node is the data input - # the second input are the thresholds - if in_ind == 0: - assert ( - str(context[inputs].dtype) == "float32" - ), """Input datatype is - not float32 as expected.""" - expected_inp_shape = self.get_folded_input_shape() - reshaped_input = context[inputs].reshape(expected_inp_shape) - - if self.get_input_datatype() == DataType["BIPOLAR"]: - # store bipolar activations as binary - reshaped_input = (reshaped_input + 1) / 2 - export_idt = DataType["BINARY"] - else: - export_idt = self.get_input_datatype() - - # make copy before saving the array - reshaped_input = reshaped_input.copy() - np.save( - os.path.join(code_gen_dir, "input_{}.npy".format(in_ind)), - reshaped_input, - ) - elif in_ind > 2: - raise Exception("Unexpected input found for Thresholding_rtl") - in_ind += 1 - - # Create a PyVerilator wrapper of the RTLSim .so - sim = self.get_rtlsim() - nbits = self.get_instream_width() - inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) - io_names = self.get_verilog_top_module_intf_names() - istream_name = io_names["s_axis"][0][0] - ostream_name = io_names["m_axis"][0][0] - io_dict = { - "inputs": {istream_name: inp}, - "outputs": {ostream_name: []}, - } - - trace_file = self.get_nodeattr("rtlsim_trace") - if trace_file == "default": - trace_file = self.onnx_node.name + ".vcd" - sname = "_" - - # Change into so directory to ensure threshold files can be found - rtlsim_so = self.get_nodeattr("rtlsim_so") - so_dir = os.path.dirname(os.path.realpath(rtlsim_so)) - olcwd = os.getcwd() - os.chdir(so_dir) - num_out_values = self.get_number_output_values() - reset_rtlsim(sim) - total_cycle_count = rtlsim_multi_io( - sim, - io_dict, - num_out_values, - trace_file=trace_file, - sname=sname, - liveness_threshold=pyverilate_get_liveness_threshold_cycles(), - ) - self.set_nodeattr("cycles_rtlsim", total_cycle_count) - os.chdir(olcwd) - output = io_dict["outputs"][ostream_name] - - # Manage output data - odt = self.get_output_datatype() - target_bits = odt.bitwidth() - packed_bits = self.get_outstream_width() - out_npy_path = "{}/output.npy".format(code_gen_dir) - out_shape = self.get_folded_output_shape() - - rtlsim_output_to_npy(output, out_npy_path, odt, out_shape, packed_bits, target_bits) - - # load and reshape output - output = np.load(out_npy_path) - oshape = self.get_normal_output_shape() - output = np.asarray([output], dtype=np.float32).reshape(*oshape) - context[node.output[0]] = output - return def code_generation_ipi(self): """Constructs and returns the TCL commands for node instantiation as an RTL diff --git a/src/finn/custom_op/fpgadataflow/rtlbackend.py b/src/finn/custom_op/fpgadataflow/rtlbackend.py index 96deb49161..264de25749 100644 --- a/src/finn/custom_op/fpgadataflow/rtlbackend.py +++ b/src/finn/custom_op/fpgadataflow/rtlbackend.py @@ -54,7 +54,7 @@ def code_generation_ipi(self): pass def code_generation_ipgen(self, model, fpgapart, clk): - self.generate_hdl() + self.generate_hdl(model) # TODO: Implement alternative def hls_sname(self): diff --git a/tests/fpgadataflow/test_fpgadataflow_thresholding.py b/tests/fpgadataflow/test_fpgadataflow_thresholding.py index 899773b680..ecf4384d34 100644 --- a/tests/fpgadataflow/test_fpgadataflow_thresholding.py +++ b/tests/fpgadataflow/test_fpgadataflow_thresholding.py @@ -143,8 +143,6 @@ def make_single_thresholding_modelwrapper( @pytest.mark.vivado @pytest.mark.slow def test_fpgadataflow_thresholding(impl_style, idt, act, nf, ich, exec_mode, mem_mode): - if impl_style == "rtl" and exec_mode == "cppsim": - pytest.skip("rtl implstyle has no cppsim, skipping") if nf == -1: nf = ich pe = ich // nf From 3244048e423ef16f7df67c87bc4ebd53b7ccf8eb Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 5 Mar 2024 12:23:47 +0000 Subject: [PATCH 544/665] [Thresholding HLS] Clean up weightstream width functions --- .../fpgadataflow/hls/thresholding_hls.py | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py b/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py index 7b9809f495..9127261dd3 100644 --- a/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py @@ -102,13 +102,6 @@ def lut_estimation(self): # total cost return comparator_cost + lutram_cost - def get_weightstream_width(self): - """Returns weight stream width. Used only in decoupled mode.""" - if self.get_nodeattr("mem_mode") == "decoupled": - return super().get_weightstream_width() - else: - return 0 - def get_weightstream_width_padded(self): """Returns weight stream width padded to a multiple of 8. This is required by the AXI Stream spec. Used in decoupled mode.""" @@ -116,9 +109,11 @@ def get_weightstream_width_padded(self): return roundup_to_integer_multiple(weight_width, 8) def get_ap_int_max_w(self): - temp_value = super().get_ap_int_max_w() - weightstream = self.get_weightstream_width() - return max([weightstream, temp_value]) + ap_int_max_w = super().get_ap_int_max_w() + if self.get_nodeattr("mem_mode") == "decoupled": + weightstream = self.get_weightstream_width() + ap_int_max_w = max([weightstream, ap_int_max_w]) + return ap_int_max_w def get_template_param_values(self): """Returns the template parameter values according to input, output and weight From bf17bc3ec184403a47f70c5f19f0a6edb857c6c3 Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 5 Mar 2024 14:11:08 +0000 Subject: [PATCH 545/665] [Threshold RTL] Remove unused generate params fct --- .../fpgadataflow/rtl/thresholding_rtl.py | 22 ------------------- 1 file changed, 22 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py index c39ae74a38..f9acece073 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py @@ -514,28 +514,6 @@ def get_dynamic_config(self, weights, address_stride=1): return config - def generate_params(self, model, path): - code_gen_dir = path - thresholds = model.get_initializer(self.onnx_node.input[1]) - mem_mode = self.get_nodeattr("mem_mode") - if mem_mode == "const": - # save thresholds in thresh.h - weight_filename = "{}/thresh.h".format(code_gen_dir) - self.make_weight_file(thresholds, "hls_header", weight_filename) - elif mem_mode == "decoupled": - # save decoupled weights for cppsim - weight_filename_sim = "{}/thresholds.npy".format(code_gen_dir) - self.make_weight_file(thresholds, "decoupled_npy", weight_filename_sim) - # also save weights as Verilog .dat file - # This file will be ignored when synthesizing UltraScale memory. - weight_filename_rtl = "{}/memblock.dat".format(code_gen_dir) - self.make_weight_file(thresholds, "decoupled_verilog_dat", weight_filename_rtl) - else: - raise Exception( - """Please set mem_mode to "const", "decoupled", - currently no other parameter value is supported!""" - ) - def make_weight_file(self, weights, weight_file_mode, weight_file_name): """Produce a file containing given weights (thresholds) in appropriate format for this layer. This file can be used for either synthesis or From 8a6832716e11ac25ce78e7644cab1f94bcef4729 Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 5 Mar 2024 14:34:06 +0000 Subject: [PATCH 546/665] [Thresholding] Code clean for generation of hw compatible tensor --- .../fpgadataflow/hls/thresholding_hls.py | 53 ++----------------- 1 file changed, 3 insertions(+), 50 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py b/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py index 9127261dd3..cedddf5dd5 100644 --- a/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py @@ -31,10 +31,7 @@ import textwrap from math import ceil, log2 from qonnx.core.datatype import DataType -from qonnx.util.basic import ( - interleave_matrix_outer_dim_from_partitions, - roundup_to_integer_multiple, -) +from qonnx.util.basic import roundup_to_integer_multiple from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend from finn.custom_op.fpgadataflow.thresholding import Thresholding @@ -109,7 +106,7 @@ def get_weightstream_width_padded(self): return roundup_to_integer_multiple(weight_width, 8) def get_ap_int_max_w(self): - ap_int_max_w = super().get_ap_int_max_w() + ap_int_max_w = HLSBackend.get_ap_int_max_w(self) if self.get_nodeattr("mem_mode") == "decoupled": weightstream = self.get_weightstream_width() ap_int_max_w = max([weightstream, ap_int_max_w]) @@ -128,50 +125,6 @@ def get_template_param_values(self): return ret - def get_hls_compatible_threshold_tensor(self, orig_thres_matrix): - """Convert the original numpy weight matrix orig_weight_matrix into - a form suitable for passing to the hlslib call: - * ensure MH % PE == 0 - * for unsigned inputs, ensure thresholds are positive - * interleave rows between PEs - * reshape into (PE, TMEM, n_thres_steps) and return - """ - mh = self.get_nodeattr("NumChannels") - pe = self.get_nodeattr("PE") - tmem = mh // pe - assert mh % pe == 0, "Requirement NumChannels divisable by PE is violated." - assert ( - orig_thres_matrix.ndim == 2 - ), """Threshold matrix dimension is - not as expected (2).""" - n_thres_steps = orig_thres_matrix.shape[1] - assert n_thres_steps == self.get_nodeattr("numSteps"), "Mismatch in threshold steps" - if not self.get_input_datatype().signed(): - # ensure all thresholds are nonnegative - assert (orig_thres_matrix >= 0).all() - # ensure all thresholds are integer - assert np.equal(np.mod(orig_thres_matrix, 1), 0).all(), "Need int threshold tensor" - ret = orig_thres_matrix - # ensure channels = mh , duplicating if necessary - if ret.shape[0] == 1: - ret = np.tile(ret, (mh, 1)) - assert ret.shape[0] == mh, "Channels of threshold matrix are not as expected (mh)" - # distribute rows between PEs - ret = interleave_matrix_outer_dim_from_partitions(ret, pe) - assert ( - ret.shape[0] == pe - ), """First dimension after distribution of the - rows between PEs is not as expected (pe)""" - assert ( - ret.shape[1] == tmem - ), """Second dimension after distribution of the - rows between PEs is not as expected (tmem)""" - assert ( - ret.shape[2] == n_thres_steps - ), """Third dimension after distribution of the - rows between PEs is not as expected (n_thres_steps)""" - return ret.reshape(1, pe, tmem, n_thres_steps) - def make_weight_file(self, weights, weight_file_mode, weight_file_name): """Produce a file containing given weights (thresholds) in appropriate format for this layer. This file can be used for either synthesis or @@ -185,7 +138,7 @@ def make_weight_file(self, weights, weight_file_mode, weight_file_name): * weight_file_name : filename for the weight file to be generated """ - threshold_tensor = self.get_hls_compatible_threshold_tensor(weights) + threshold_tensor = self.get_hw_compatible_threshold_tensor(weights) tdt = self.get_weight_datatype() assert np.vectorize(tdt.allowed)( threshold_tensor From 4e244a7c466512b9f865cfc3c675b27e13f2c655 Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 5 Mar 2024 14:50:47 +0000 Subject: [PATCH 547/665] [Tests] Add comment to params for thresholding test --- tests/fpgadataflow/test_fpgadataflow_thresholding.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/fpgadataflow/test_fpgadataflow_thresholding.py b/tests/fpgadataflow/test_fpgadataflow_thresholding.py index ecf4384d34..f8bc2df704 100644 --- a/tests/fpgadataflow/test_fpgadataflow_thresholding.py +++ b/tests/fpgadataflow/test_fpgadataflow_thresholding.py @@ -235,6 +235,7 @@ def test_fpgadataflow_thresholding(impl_style, idt, act, nf, ich, exec_mode, mem @pytest.mark.parametrize("impl_style", ["rtl", "hls"]) +# configuration (ch, pe) @pytest.mark.parametrize("cfg", [(1, 1), (6, 2), (6, 3), (8, 2), (8, 4)]) @pytest.mark.fpgadataflow @pytest.mark.vivado @@ -332,6 +333,7 @@ def read_weights(sim): @pytest.mark.parametrize("impl_style", ["hls", "rtl"]) +# configuration (ch, pe) @pytest.mark.parametrize("cfg", [(1, 1), (6, 2), (6, 3), (8, 2), (8, 4)]) @pytest.mark.fpgadataflow @pytest.mark.vivado From ac56bae4a56e9cd9282bc555ccdadb7557a9ea5f Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 5 Mar 2024 16:36:47 +0000 Subject: [PATCH 548/665] [NBs] Update folding notebook --- notebooks/advanced/3_folding.ipynb | 50 +++++++++++++------------ notebooks/advanced/cybsec_PE_SIMD.onnx | Bin 192234 -> 192077 bytes 2 files changed, 27 insertions(+), 23 deletions(-) diff --git a/notebooks/advanced/3_folding.ipynb b/notebooks/advanced/3_folding.ipynb index 07b66da52f..8c7b97d6c6 100644 --- a/notebooks/advanced/3_folding.ipynb +++ b/notebooks/advanced/3_folding.ipynb @@ -8,7 +8,7 @@ "--------------------------------------\n", "**Note: We will utilize one of the intermediate models generated in the process of the cybersecurity end2end example**\n", "\n", - "There is a local copy of `step_convert_to_hls.onnx` in this directory, which was renamed to `cybsec_PE_SIMD.onnx` to be able to go through this tutorial without requisites. But you can also generate it yourself with the [third cybersecurity Jupyter notebook](../end2end_example/cybersecurity/3-build-accelerator-with-finn.ipynb). After the execution of the estimates only build flow, it can be found in `../end2end_example/cybersecurity/output_estimates_only/intermediate_models/step_convert_to_hls.onnx`. \n", + "There is a local copy of `step_specialize_layers.onnx` in this directory, which was renamed to `cybsec_PE_SIMD.onnx` to be able to go through this tutorial without requisites. But you can also generate it yourself with the [third cybersecurity Jupyter notebook](../end2end_example/cybersecurity/3-build-accelerator-with-finn.ipynb). After the execution of the estimates only build flow, it can be found in `../end2end_example/cybersecurity/output_estimates_only/intermediate_models/step_specialize_layers.onnx`. \n", "\n", "This notebook describes the use of FINN parallelization parameters (PE & SIMD), also called folding factors, to efficiently optimize models so as to extract the maximum performance out of them. \n", "\n", @@ -41,7 +41,7 @@ "source": [ "This notebook shows the manual version of this step and explains how these attributes can improve performance and what are their effects on resource utilization for developers who need to maximize the performance of their network. \n", "\n", - "For that we will use the `cybsec_PE_SIMD.onnx` file as starting point. This intermediate model from the cybersecurity example is the model representation after the high-level ONNX layers are converted to HLS layers. Each node in the graph now corresponds to an HLS C++ function call and the parallelization parameters can be set using the node attributes.\n", + "For that we will use the `cybsec_PE_SIMD.onnx` file as starting point. This intermediate model from the cybersecurity example is the model representation after the high-level ONNX layers are converted to HW layers and then specialized to either HLS or RTL variants. In this example, all nodes were converted to HLS variants this means that each node in the graph now corresponds to an HLS C++ function call and the parallelization parameters can be set using the node attributes.\n", "\n", "We will take this model to show how to set the folding factors manually and analyze the estimated execution clock cycles and the resource utilization of each layer in the network." ] @@ -56,7 +56,7 @@ "\n", "![](finn-dataflow.png)\n", "\n", - "In practice, the layers are instantiated by function calls to optimized Vitis HLS building blocks from the [finn-hlslib](https://github.com/Xilinx/finn-hlslib) library.\n", + "In practice, the layers are instantiated by function calls to optimized Vitis HLS building blocks from the [finn-hlslib](https://github.com/Xilinx/finn-hlslib) library or by RTL modules from the [finn-rtllib](https://github.com/Xilinx/finn/tree/main/finn-rtllib).\n", "\n", "Since each layer will be instantiated, we can flexibly set the parallelization of each layer and thus control resources and throughput of our network, as visualized in the image below:\n", "\n", @@ -72,11 +72,11 @@ "As discussed above, the network needs to go through a few preparation steps before it can be fed into our estimation functions.\n", "\n", "The `.onnx` file loaded here is taken from the cybersecurity end2end example notebook. \n", - "We pick the onnx file `cybsec_PE_SIMD.onnx` to which the necessary transformations have been applied for this notebook. This means, network layers mapped to necessary FINN-HLS blocks. In this case, the `MatrixVectorActivation` units. \n", + "We pick the onnx file `cybsec_PE_SIMD.onnx` to which the necessary transformations have been applied for this notebook. This means, network layers mapped to necessary FINN-HW blocks. In this case, the HLS variants of MatrixVectorActivation, `MVAU_hls` units. \n", "\n", "To interact with the `.onnx` file we use `ModelWrapper()`. This wrapper simplifies the access to different model attributes and allows us to apply custom transformations on the model.\n", "\n", - "In the below cell, we load our onnx file and view the cybersecurity MLP network in Netron." + "In the below cell, we load our onnx file and view the cybersecurity MLP network in Netron. Additionally, we call the transformation `GiveUniqueNodeNames` as a preparation." ] }, { @@ -87,8 +87,12 @@ "source": [ "import os\n", "from qonnx.core.modelwrapper import ModelWrapper\n", - "model_path = os.environ[\"FINN_ROOT\"] + \"/notebooks/advanced/cybsec_PE_SIMD.onnx\" \n", - "model = ModelWrapper(model_path)\n", + "from qonnx.transformation.general import GiveUniqueNodeNames\n", + "\n", + "model = ModelWrapper(os.environ[\"FINN_ROOT\"] + \"/notebooks/advanced/cybsec_PE_SIMD.onnx\")\n", + "model = model.transform(GiveUniqueNodeNames())\n", + "model_path = os.environ[\"FINN_ROOT\"] + \"/notebooks/advanced/cybsec_PE_SIMD_named_nodes.onnx\"\n", + "model.save(model_path)\n", "\n", "showInNetron(model_path)" ] @@ -106,7 +110,7 @@ "source": [ "The computational parallelism can be varied by setting the folding factors or also called parallelization parameters **PE** and **SIMD** of each layer. These parallelization attributes are subject to certain constraints and should be selected accordingly.\n", "\n", - "To see more details about how this is implemented in the `MatrixVectorActivation` layer (MVAU), please have a look at [this documentation](https://github.com/Xilinx/finn/blob/github-pages/docs/finn-sheduling-and-folding.pptx). A schematic of the folding in an MVAU for a fully-connected layer is shown below:\n", + "To see more details about how this is implemented in the HLS variant of the MatrixVectorActivation layer (`MVAU_hls`), please have a look at [this documentation](https://github.com/Xilinx/finn/blob/github-pages/docs/finn-sheduling-and-folding.pptx). A schematic of the folding in an MVAU for a fully-connected layer is shown below:\n", "\n", "![](finn-folding-mvau.png)" ] @@ -220,7 +224,7 @@ "cell_type": "markdown", "metadata": {}, "source": [ - "Next to the absolute numbers of LUTs, BRAM, URAM and DSPs, the analysis pass also provides information about the efficiency of the memory usage. If the memory type is not utilized, the efficiency is by default 1. You can see that above for the `URAM_efficiency`. In all other cases the efficiency indicates the actual parameter storage needed divided by the allocated BRAM/URAM storage. So, this means in our example MVAU_0 uses 5 block ram and they are 83% utilized. " + "Next to the absolute numbers of LUTs, BRAM, URAM and DSPs, the analysis pass also provides information about the efficiency of the memory usage. If the memory type is not utilized, the efficiency is by default 1. You can see that above for the `URAM_efficiency`. In all other cases the efficiency indicates the actual parameter storage needed divided by the allocated BRAM/URAM storage. So, this means in our example MVAU_hls_0 uses 5 block ram and they are 83% utilized. " ] }, { @@ -262,7 +266,7 @@ "## Modify Parameters\n", "\n", "We now modify the parallelization parameters of the first network layer to reduce its latency.\n", - "We only extract the first `MatrixVectorActivation` block from the model and set the parallelization parameters manually.\n", + "We only extract the first `MVAU_hls` block from the model and set the parallelization parameters manually.\n", "\n", "In the first step, we left the `PE` & `SIMD` values for all the layers on default (=1) to establish a baseline and measure the estimated clock cycles and resource utilization for each of the individual layers.\n", "\n", @@ -277,7 +281,7 @@ "source": [ "from qonnx.custom_op.registry import getCustomOp\n", "\n", - "list_of_mvaus = model.get_nodes_by_op_type(\"MatrixVectorActivation\")\n", + "list_of_mvaus = model.get_nodes_by_op_type(\"MVAU_hls\")\n", "mvau0 = list_of_mvaus[0]\n", "\n", "mvau0_inst = getCustomOp(mvau0)\n", @@ -301,7 +305,7 @@ "cell_type": "markdown", "metadata": {}, "source": [ - "We save the model and view it. On expanding the first `MatrixVectorActivation` we can see the updated `PE` & `SIMD` parameters for that layer." + "We save the model and view it. On expanding the first `MVAU_hls` we can see the updated `PE` & `SIMD` parameters for that layer." ] }, { @@ -418,7 +422,7 @@ "outputs": [], "source": [ "dir_path = os.environ[\"FINN_ROOT\"] + \"/notebooks/advanced/\" \n", - "model_orig = ModelWrapper(dir_path + \"cybsec_PE_SIMD.onnx\")\n", + "model_orig = ModelWrapper(dir_path + \"cybsec_PE_SIMD_named_nodes.onnx\")\n", "model_updated = ModelWrapper(\"cybsec_PE_SIMD_modified.onnx\")" ] }, @@ -436,7 +440,7 @@ "outputs": [], "source": [ "# Original model\n", - "list_of_mvaus = model_orig.get_nodes_by_op_type(\"MatrixVectorActivation\")\n", + "list_of_mvaus = model_orig.get_nodes_by_op_type(\"MVAU_hls\")\n", "print(\"In the original model (pe=simd=1): \")\n", "for mvau in list_of_mvaus:\n", " mvau_inst = getCustomOp(mvau)\n", @@ -452,7 +456,7 @@ "outputs": [], "source": [ "# Updated model\n", - "list_of_mvaus = model_updated.get_nodes_by_op_type(\"MatrixVectorActivation\")\n", + "list_of_mvaus = model_updated.get_nodes_by_op_type(\"MVAU_hls\")\n", "print(\"In the original model (pe=simd=1): \")\n", "for mvau in list_of_mvaus:\n", " mvau_inst = getCustomOp(mvau)\n", @@ -465,7 +469,7 @@ "cell_type": "markdown", "metadata": {}, "source": [ - "We can see that the input and output shape for MatrixVectorActivation_0 has changed after we have changed the folding factors. These changes have direct influence on the in/out stream width. We can have a closer look at the formula to calculate the stream width of an MVAU." + "We can see that the input and output shape for MVAU_hls_0 has changed after we have changed the folding factors. These changes have direct influence on the in/out stream width. We can have a closer look at the formula to calculate the stream width of an MVAU." ] }, { @@ -507,7 +511,7 @@ "outputs": [], "source": [ "# Original model\n", - "list_of_mvaus = model_orig.get_nodes_by_op_type(\"MatrixVectorActivation\")\n", + "list_of_mvaus = model_orig.get_nodes_by_op_type(\"MVAU_hls\")\n", "print(\"In the original model (pe=simd=1): \")\n", "for mvau in list_of_mvaus:\n", " mvau_inst = getCustomOp(mvau)\n", @@ -537,7 +541,7 @@ "outputs": [], "source": [ "# Updated model\n", - "list_of_mvaus = model_updated.get_nodes_by_op_type(\"MatrixVectorActivation\")\n", + "list_of_mvaus = model_updated.get_nodes_by_op_type(\"MVAU_hls\")\n", "print(\"In the original model (pe=simd=1): \")\n", "for mvau in list_of_mvaus:\n", " mvau_inst = getCustomOp(mvau)\n", @@ -550,7 +554,7 @@ "cell_type": "markdown", "metadata": {}, "source": [ - "As we can see, the output stream width of MatrixVectorActivation_0 has now changed to `4`, while the input stream width of MatrixVectorActivation_1 stayed `2`. So, the FINN compiler would insert a DWC between these nodes, we can manually invoke this behavior by calling the transformation `InsertDWC` on our model." + "As we can see, the output stream width of MVAU_hls_0 has now changed to `4`, while the input stream width of MatrixVectorActivation_1 stayed `2`. So, the FINN compiler would insert a DWC between these nodes, we can manually invoke this behavior by first calling the transformation `InsertDWC` and then converting the resulting DWCs into an HLS or RTL variant by calling `SpecializeLayers`." ] }, { @@ -560,9 +564,10 @@ "outputs": [], "source": [ "from finn.transformation.fpgadataflow.insert_dwc import InsertDWC\n", - "from qonnx.transformation.general import GiveUniqueNodeNames\n", + "from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers\n", "\n", "model_updated = model_updated.transform(InsertDWC())\n", + "model_updated = model_updated.transform(SpecializeLayers())\n", "model_updated = model_updated.transform(GiveUniqueNodeNames())" ] }, @@ -610,7 +615,6 @@ "source": [ "layers = res_dict_dwc.keys()\n", "# replace names of layers with abbreviations\n", - "layers = [n.replace(\"MatrixVectorActivation_\", \"MVU\") for n in layers]\n", "layers = [n.replace(\"StreamingDataWidthConverter_Batch\", \"DWC\") for n in layers]" ] }, @@ -656,9 +660,9 @@ "name": "python", "nbconvert_exporter": "python", "pygments_lexer": "ipython3", - "version": "3.8.5" + "version": "3.10.12" } }, "nbformat": 4, - "nbformat_minor": 2 + "nbformat_minor": 4 } diff --git a/notebooks/advanced/cybsec_PE_SIMD.onnx b/notebooks/advanced/cybsec_PE_SIMD.onnx index b450cc9e43361e845fda8c95d743e1b461a1a9ad..d09d07d2bf1b502d93bc676c8901fdc29de51d6b 100644 GIT binary patch delta 241 zcmaELm;3A;Zb=SyA@+jGlKi6N3@J84JwszXL#w%WxVf4qiurOWarlNghQ?>)6i@!g zEIo0RM42vNWeQNTQX;%g@H$=%G3*p)%dX`Zac z>W8ENXqDLHJ*?j#M)84+65<3qFg`1@`953weKyAJ_t}`3pHA<3!{jpk(QBp^(|5dO ma-Dwe4b!XXf8R1)5aDwYcVni6C$Bf4i zBO(l8;abkjHMx*kZ1PnWGu-Ym#$^=HTVj*7S-(M?Bq$^R4lUiR%o5$yih}&2W^cB3 zZ#Ks5-fT?FPp40M&9q{=-)kn9>Gf}zUQM@p!{j30Y(5_RgC8V From 4a3eedade41a061aa6d7c97795ffb2ce70535c0b Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Wed, 6 Mar 2024 10:33:25 +0000 Subject: [PATCH 549/665] [Thresholding RTL] Add doc strings to class methods --- .../fpgadataflow/rtl/thresholding_rtl.py | 64 ++++++------------- 1 file changed, 18 insertions(+), 46 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py index f9acece073..ee101b1cc8 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py @@ -80,6 +80,20 @@ def get_nodeattr_types(self): return my_attrs def get_pe_mem_geometries(self): + ''' return a list of (bitwidth, depth) for PE memory configurations to be used in resource estimation + + for each bitwidth, the depth is calculated as the + number of thresholds that can be stored in a single + memory block + the bitwidth is the bitwidth of the threshold values + the depth is the number of thresholds that can be stored + in a single memory block + the number of memory blocks is calculated as the number + of thresholds divided by the depth + the number of memory blocks is then multiplied by the + number of PEs to get the total number of memory blocks + required for the entire layer + ''' pe = self.get_nodeattr("PE") wdt = self.get_weight_datatype() wdt_bits = wdt.bitwidth() @@ -95,6 +109,7 @@ def get_pe_mem_geometries(self): return ret def get_memory_estimate(self): + ''' return the memory estimate for this node ''' res_dict = {} depth_trigger_bram = self.get_nodeattr("depth_trigger_bram") depth_trigger_uram = self.get_nodeattr("depth_trigger_uram") @@ -116,14 +131,17 @@ def get_memory_estimate(self): return res_dict def bram_estimation(self): + ''' return the number of BRAMs required for this node ''' res_dict = self.get_memory_estimate() return res_dict.get("BRAM", 0) def uram_estimation(self): + ''' return the number of URAMs required for this node ''' res_dict = self.get_memory_estimate() return res_dict.get("URAM", 0) def lut_estimation(self): + ''' return the number of LUTs required for this node ''' res_dict = self.get_memory_estimate() return res_dict.get("LUTRAM", 0) @@ -468,52 +486,6 @@ def get_verilog_top_module_intf_names(self): return intf_names - def get_dynamic_config(self, weights, address_stride=1): - """Returns a configuration dictionary containing axilite write commands - in order to program the thresholds into the RTL core during runtime. - The default address stride for the weights is 1 byte.""" - - # thresholds = model.get_initializer(self.onnx_node.input[1]) - thresholds = weights - num_channels, num_weights_per_channel = thresholds.shape - - weight_addr_boundary = find_next_power_of_2(num_weights_per_channel) - # Make sure that the next power of 2 (output) is greater than the input - assert weight_addr_boundary >= num_weights_per_channel - - config = {} - channel_cntr = 0 - wdt = self.get_weight_datatype() - bw_hexdigit = roundup_to_integer_multiple(wdt.bitwidth(), 4) - for channel in thresholds: - channel_start_addr = channel_cntr * weight_addr_boundary * address_stride - weight_cntr = 0 - addr = 0 - for weight in channel: - key_name = "{}_{}{}_{}{}".format( - "axilite", "ch", str(channel_cntr), "w", str(weight_cntr) - ) - config[key_name] = ( - channel_start_addr + addr, - int( - str( - pack_innermost_dim_as_hex_string( - [weight], - wdt, - bw_hexdigit, - ) - ), - 0, - ), - ) - - weight_cntr += 1 - addr += address_stride - - channel_cntr += 1 - - return config - def make_weight_file(self, weights, weight_file_mode, weight_file_name): """Produce a file containing given weights (thresholds) in appropriate format for this layer. This file can be used for either synthesis or From f759400095adff49b2b715d0490e3cb657436852 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Wed, 6 Mar 2024 10:57:38 +0000 Subject: [PATCH 550/665] [tests] functional validation thresholding to_hw transform Signed-off-by: aziz bahri --- .../test_convert_to_hw_thresholding.py | 37 ++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/tests/fpgadataflow/test_convert_to_hw_thresholding.py b/tests/fpgadataflow/test_convert_to_hw_thresholding.py index ee161a9b95..9d44702152 100755 --- a/tests/fpgadataflow/test_convert_to_hw_thresholding.py +++ b/tests/fpgadataflow/test_convert_to_hw_thresholding.py @@ -36,9 +36,11 @@ from qonnx.transformation.general import GiveUniqueNodeNames from qonnx.transformation.infer_datatypes import InferDataTypes from qonnx.transformation.infer_shapes import InferShapes - +from qonnx.util.basic import gen_finn_dt_tensor +from qonnx.custom_op.general.multithreshold import multithreshold from finn.transformation.fpgadataflow.convert_to_hw_layers import InferThresholdingLayer from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers +import finn.core.onnx_exec as oxe test_fpga_part = "xczu3eg-sbva484-1-e" target_clk_ns = 5 @@ -48,6 +50,18 @@ def sort_thresholds_increasing(thresholds): return np.sort(thresholds, axis=1) +def prepare_inputs(input_tensor): + return {"inp": input_tensor} + +# n = batch, c = channel, h = height, w = width of feature map +# Standard = NCHW; FINN = NHWC +# Convert from NHWC(FINN) to NCHW(Standard) +def layout_FINN2NCHW(data): + return np.transpose(data, (0, 3, 1, 2)) + +# Convert from NCHW(Standard) to NHWC(FINN) +def layout_NCHW2FINN(data): + return np.transpose(data, (0, 2, 3, 1)) def generate_random_threshold_values(input_data_type, num_input_channels, num_steps): return np.random.randint( @@ -164,6 +178,27 @@ def test_convert_multithreshold_to_hardware( model = model.transform(InferThresholdingLayer()) + # Perform functional validation of the InferThresholdingLayer transform + x = gen_finn_dt_tensor(input_data_type, tuple(num_input_vecs + [num_input_channels])) + + x_nchw = layout_FINN2NCHW(x) + y_expected = multithreshold(x_nchw, thresholds) + + # convert back to NHWC for comparison to hw outputs + y_expected = layout_NCHW2FINN(y_expected) + if activation == DataType["BIPOLAR"]: + # binary to bipolar + y_expected = 2 * y_expected - 1 + else: + # signed offset + y_expected += activation.min() + + input_dict = prepare_inputs(x) + y_produced = oxe.execute_onnx(model, input_dict)["outp"] + + assert (y_produced == y_expected).all() + + # Transform to the specified implementation style, either the RTL or HLS according to test parameters node = model.get_nodes_by_op_type(model.graph.node[0].op_type)[0] inst = getCustomOp(node) inst.set_nodeattr("preferred_impl_style", impl_style) From 06607d52740716299fecb8583a83bf7ecf0b62c0 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 6 Mar 2024 13:50:46 +0000 Subject: [PATCH 551/665] [mem mode] Refactor mem_mode argument --- src/finn/builder/build_dataflow_config.py | 12 ---- src/finn/builder/build_dataflow_steps.py | 5 +- .../custom_op/fpgadataflow/hls/lookup_hls.py | 16 ++--- .../hls/matrixvectoractivation_hls.py | 42 ++++++------- .../fpgadataflow/hls/thresholding_hls.py | 59 ++++++++++--------- .../hls/vectorvectoractivation_hls.py | 34 +++++------ src/finn/custom_op/fpgadataflow/lookup.py | 10 ++-- .../fpgadataflow/matrixvectoractivation.py | 55 +++++++++-------- .../fpgadataflow/vectorvectoractivation.py | 53 +++++++++-------- .../fpgadataflow/convert_to_hw_layers.py | 14 +---- .../fpgadataflow/make_zynq_proj.py | 2 +- .../fpgadataflow/set_fifo_depths.py | 5 +- tests/end2end/test_end2end_bnn_pynq.py | 4 +- tests/end2end/test_end2end_mobilenet_v1.py | 2 +- .../test_convert_to_hw_layers_cnv.py | 2 +- tests/fpgadataflow/test_fifosizing.py | 1 - .../test_fpgadataflow_checksum.py | 13 ++-- .../test_fpgadataflow_ipstitch.py | 14 ++--- tests/fpgadataflow/test_fpgadataflow_mvau.py | 16 ++--- .../test_fpgadataflow_thresholding.py | 14 +++-- tests/fpgadataflow/test_fpgadataflow_vvau.py | 4 +- tests/fpgadataflow/test_runtime_weights.py | 2 +- tests/fpgadataflow/test_split_large_fifos.py | 1 - 23 files changed, 188 insertions(+), 192 deletions(-) diff --git a/src/finn/builder/build_dataflow_config.py b/src/finn/builder/build_dataflow_config.py index 4cbcfb21c3..e35c1cd346 100644 --- a/src/finn/builder/build_dataflow_config.py +++ b/src/finn/builder/build_dataflow_config.py @@ -65,15 +65,6 @@ class DataflowOutputType(str, Enum): DEPLOYMENT_PACKAGE = "deployment_package" -class ComputeEngineMemMode(str, Enum): - """Memory mode for generated compute engines. See - https://finn.readthedocs.io/en/latest/internals.html#matrixvectoractivation-mem-mode - for more information.""" - - CONST = "const" - DECOUPLED = "decoupled" - - class VitisOptStrategyCfg(str, Enum): """Vitis optimization strategy with serializable string enum values.""" @@ -293,9 +284,6 @@ class DataflowBuildConfig: #: If not specified it will default to synth_clk_period_ns hls_clk_period_ns: Optional[float] = None - #: Which memory mode will be used for compute layers - default_mem_mode: Optional[ComputeEngineMemMode] = ComputeEngineMemMode.DECOUPLED - #: Call CapConvolutionFIFODepths in InsertAndSetFIFODepths transform #: to make convolution FIFOs smaller where appropriate default_swg_exception: Optional[bool] = False diff --git a/src/finn/builder/build_dataflow_steps.py b/src/finn/builder/build_dataflow_steps.py index a75bbe98a1..f935d5c53e 100644 --- a/src/finn/builder/build_dataflow_steps.py +++ b/src/finn/builder/build_dataflow_steps.py @@ -337,14 +337,13 @@ def step_convert_to_hw(model: ModelWrapper, cfg: DataflowBuildConfig): In the end am empty json file is created which can be used to set user specific preferred implementation styles for each node.""" - mem_mode = cfg.default_mem_mode.value if cfg.standalone_thresholds: # doing this first causes all threshold layers to be standalone model = model.transform(to_hw.InferThresholdingLayer()) # needed for bipolar MatMul layers - model = model.transform(to_hw.InferBinaryMatrixVectorActivation(mem_mode)) + model = model.transform(to_hw.InferBinaryMatrixVectorActivation()) # needed for non-bipolar MatMul layers - model = model.transform(to_hw.InferQuantizedMatrixVectorActivation(mem_mode)) + model = model.transform(to_hw.InferQuantizedMatrixVectorActivation()) # TopK to LabelSelect model = model.transform(to_hw.InferLabelSelectLayer()) # input quantization (if any) as standalone threshold diff --git a/src/finn/custom_op/fpgadataflow/hls/lookup_hls.py b/src/finn/custom_op/fpgadataflow/hls/lookup_hls.py index feeca8719b..ba44deb898 100644 --- a/src/finn/custom_op/fpgadataflow/hls/lookup_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/lookup_hls.py @@ -57,7 +57,7 @@ def global_includes(self): mem_mode = self.get_nodeattr("mem_mode") global_incls = [] global_incls.append('#include "lookup.hpp"') - if mem_mode == "const": + if mem_mode == "internal_embedded": global_incls.append('#include "embeddings.hpp"') self.code_gen_dict["$GLOBALS$"] = global_incls @@ -80,7 +80,7 @@ def defines(self, var): my_defines.append("#define EmbeddingAlign %d" % ext_mem_emb_align) my_defines.append("#define T_SRC %s" % elem_hls_type) my_defines.append("#define T_DST ap_uint") - elif mem_mode == "const": + elif mem_mode == "internal_embedded": my_defines.append("#define NumEmbeddings %d" % self.get_nodeattr("NumEmbeddings")) my_defines.append("#define EmbeddingDim %d" % emb_dim) my_defines.append("#define InputType %s" % elem_hls_type) @@ -143,7 +143,7 @@ def dataoutstrm(self): def docompute(self): mem_mode = self.get_nodeattr("mem_mode") - if mem_mode == "const": + if mem_mode == "internal_embedded": self.code_gen_dict["$DOCOMPUTE$"] = [ """StreamingLookup(in0_%s, out_%s, embeddings);""" @@ -162,7 +162,7 @@ def blackboxfunction(self): packed_input_hls_type = "ap_uint<%d>" % ibits obits = self.get_outstream_width() packed_output_hls_type = "ap_uint<%d>" % obits - if mem_mode == "const": + if mem_mode == "internal_embedded": self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ "void %s(hls::stream<%s > &in0_%s, hls::stream<%s > &out_%s)" % ( @@ -188,7 +188,7 @@ def pragmas(self): my_pragmas = ["#pragma HLS INTERFACE axis port=in0_" + self.hls_sname()] my_pragmas.append("#pragma HLS INTERFACE axis port=out_" + self.hls_sname()) my_pragmas.append("#pragma HLS INTERFACE ap_ctrl_none port=return") - if mem_mode == "const": + if mem_mode == "internal_embedded": my_pragmas.append("#pragma HLS BIND_STORAGE variable=embeddings type=ROM_2P impl=BRAM") elif mem_mode == "external": my_pragmas.append("#pragma HLS INTERFACE m_axi offset=slave port=mem") @@ -203,7 +203,7 @@ def pragmas(self): def generate_params(self, model, path): mem_mode = self.get_nodeattr("mem_mode") embeddings = model.get_initializer(self.onnx_node.input[1]) - if mem_mode == "const": + if mem_mode == "internal_embedded": code_gen_dir = path weight_filename = "{}/embeddings.hpp".format(code_gen_dir) edt = DataType[self.get_nodeattr("EmbeddingType")] @@ -257,8 +257,8 @@ def execute_node(self, context, graph): folded_oshape = tuple(self.get_folded_output_shape()) mem_mode = self.get_nodeattr("mem_mode") assert ( - mem_mode == "const" - ), "Only mem_mode=const is supported for simulation of Lookup layer" + mem_mode == "internal_embedded" + ), "Only mem_mode=internal_embedded is supported for simulation of Lookup layer" if mode == "cppsim": code_gen_dir = self.get_nodeattr("code_gen_dir_cppsim") diff --git a/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py b/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py index e279d3953a..8c640f6534 100644 --- a/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py @@ -78,8 +78,8 @@ def lut_estimation(self): c2 = 0 mmode = self.get_nodeattr("mem_mode") mstyle = self.get_nodeattr("ram_style") - if (mmode == "decoupled" and mstyle == "distributed") or ( - mmode == "const" and self.calc_wmem() <= 128 + if (mmode == "internal_decoupled" and mstyle == "distributed") or ( + mmode == "internal_embedded" and self.calc_wmem() <= 128 ): c2 = (P * Q * W) * math.ceil(self.calc_wmem() / 64) @@ -178,7 +178,7 @@ def get_verilog_top_module_intf_names(self): sname = self.hls_sname() if mem_mode == "external": intf_names["s_axis"].append(("weights_" + sname, self.get_weightstream_width_padded())) - if mem_mode == "decoupled": + if mem_mode == "internal_decoupled": # only expose axilite interface if attribute is set runtime_writable = self.get_nodeattr("runtime_writeable_weights") == 1 if runtime_writable: @@ -190,9 +190,9 @@ def global_includes(self): self.code_gen_dict["$GLOBALS$"] += ['#include "activations.hpp"'] mem_mode = self.get_nodeattr("mem_mode") - if mem_mode not in ["const", "decoupled", "external"]: + if mem_mode not in ["internal_embedded", "internal_decoupled", "external"]: raise Exception( - """Please set mem_mode to "const", "decoupled", or "external", + """Please set mem_mode to "internal_embedded", "internal_decoupled", or "external", currently no other parameter value is supported!""" ) self.code_gen_dict["$GLOBALS$"] += ['#include "mvau.hpp"'] @@ -228,7 +228,7 @@ def defines(self, var): numReps, ) ] - if mem_mode == "decoupled" or mem_mode == "external": + if mem_mode == "internal_decoupled" or mem_mode == "external": wdt = self.get_weight_datatype() self.code_gen_dict["$DEFINES$"].append("#define WP1 {}\n".format(wdt.bitwidth())) @@ -259,7 +259,7 @@ def read_npy_data(self): ) mem_mode = self.get_nodeattr("mem_mode") - if mem_mode == "decoupled" or mem_mode == "external": + if mem_mode == "internal_decoupled" or mem_mode == "external": wdt = self.get_weight_datatype() elem_bits = wdt.bitwidth() packed_bits = self.get_weightstream_width() @@ -294,7 +294,7 @@ def strm_decl(self): ) ) - if mem_mode == "decoupled" or mem_mode == "external": + if mem_mode == "internal_decoupled" or mem_mode == "external": self.code_gen_dict["$STREAMDECLARATIONS$"].append( 'hls::stream> weights_{} ("weights_{}");'.format( self.get_weightstream_width(), self.hls_sname(), self.hls_sname() @@ -314,7 +314,7 @@ def docompute(self): threshs = "PassThroughActivation<%s>()" % odtype_hls_str else: threshs = "threshs" - if mem_mode == "const": + if mem_mode == "internal_embedded": self.code_gen_dict["$DOCOMPUTE$"] = [ """Matrix_Vector_Activate_Batch (in0_{}, out_{}, weights, {}, numReps, {});""".format( @@ -327,7 +327,7 @@ def docompute(self): map_to_hls_mult_style[self.get_nodeattr("resType")], ) ] - elif mem_mode == "decoupled" or mem_mode == "external": + elif mem_mode == "internal_decoupled" or mem_mode == "external": wdt = self.get_weight_datatype() if wdt == DataType["BIPOLAR"]: export_wdt = DataType["BINARY"] @@ -351,7 +351,7 @@ def docompute(self): else: raise Exception( - """Please set mem_mode to "const", "decoupled", or "external", + """Please set mem_mode to "internal_embedded", "internal_decoupled", or "external", currently no other parameter value is supported!""" ) @@ -389,7 +389,7 @@ def save_as_npy(self): def blackboxfunction(self): mem_mode = self.get_nodeattr("mem_mode") - if mem_mode == "const": + if mem_mode == "internal_embedded": self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ """void {}(hls::stream> &in0_{}, hls::stream> &out_{} @@ -401,7 +401,7 @@ def blackboxfunction(self): self.hls_sname(), ) ] - elif mem_mode == "decoupled" or mem_mode == "external": + elif mem_mode == "internal_decoupled" or mem_mode == "external": self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ """void {}( hls::stream> &in0_{}, @@ -420,8 +420,8 @@ def blackboxfunction(self): else: raise Exception( - """Please set mem_mode to "const" or "decoupled", currently no other - parameter value is supported!""" + """Please set mem_mode to "internal_embedded" or "internal_decoupled", + currently no other parameter value is supported!""" ) def pragmas(self): @@ -435,21 +435,21 @@ def pragmas(self): ) self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") - if mem_mode == "const": + if mem_mode == "internal_embedded": self.code_gen_dict["$PRAGMAS$"].append('#include "params.h"') # the weight tensor is ap_uint [PE][WMEM] # partition for parallel access along the PE dimension (dim 1) self.code_gen_dict["$PRAGMAS$"].append( ("#pragma HLS ARRAY_PARTITION variable=weights.m_weights " "complete dim=1") ) - elif mem_mode == "decoupled" or mem_mode == "external": + elif mem_mode == "internal_decoupled" or mem_mode == "external": self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE axis port=weights_" + self.hls_sname() ) else: raise Exception( - """Please set mem_mode to "const", "decoupled", or external, + """Please set mem_mode to "internal_embedded", "internal_decoupled", or external, currently no other parameter value is supported!""" ) @@ -482,7 +482,7 @@ def pragmas(self): def get_ap_int_max_w(self): # base class impl (max of inp/out stream widths) max_of_io = super().get_ap_int_max_w() - # decoupled mode weight stream + # internal_decoupled mode weight stream weightstream = self.get_weightstream_width() # single PE weight entry weight_bits = self.get_weight_datatype().bitwidth() @@ -556,7 +556,7 @@ def execute_node(self, context, graph): inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) self.reset_rtlsim(sim) self.toggle_clk(sim) - if mem_mode == "external" or mem_mode == "decoupled": + if mem_mode == "external" or mem_mode == "internal_decoupled": wnbits = self.get_weightstream_width() export_wdt = self.get_weight_datatype() # we have converted bipolar weights to binary for export, @@ -597,7 +597,7 @@ def instantiate_ip(self, cmd): # instantiate the HLS IP vlnv = self.get_nodeattr("ip_vlnv") node_name = self.onnx_node.name - if self.get_nodeattr("mem_mode") == "decoupled": + if self.get_nodeattr("mem_mode") == "internal_decoupled": cmd.append("create_bd_cell -type ip -vlnv %s /%s/%s" % (vlnv, node_name, node_name)) else: cmd.append("create_bd_cell -type ip -vlnv %s %s" % (vlnv, node_name)) diff --git a/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py b/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py index fb90365eef..5fb1843270 100644 --- a/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py @@ -63,10 +63,15 @@ def get_nodeattr_types(self): # string defining memory type "ram_style": ("s", False, "distributed", {"distributed", "block"}), # memory mode for the thresholds - # const -- embedded thresholds, default - # decoupled -- streaming thresholds with streamer packaged inside IP - "mem_mode": ("s", False, "const", {"const", "decoupled"}), - # (mem_mode = decoupled only) whether weights (thresholds) will be + # internal_embedded -- embedded thresholds + # internal_decoupled -- default, streaming thresholds with streamer packaged inside IP + "mem_mode": ( + "s", + False, + "internal_decoupled", + {"internal_embedded", "internal_decoupled"}, + ), + # (mem_mode = internal_decoupled only) whether weights (thresholds) will be # writable through an AXI-lite interface during runtime # 1 for enabled, 0 for disabled. # see finn-rtllib/memstream/doc/README for more about the memory @@ -119,8 +124,8 @@ def lut_estimation(self): return comparator_cost + lutram_cost def get_weightstream_width(self): - """Returns weight stream width. Used only in decoupled mode.""" - if self.get_nodeattr("mem_mode") == "decoupled": + """Returns weight stream width. Used only in internal_decoupled mode.""" + if self.get_nodeattr("mem_mode") == "internal_decoupled": pe = self.get_nodeattr("PE") wp = self.get_weight_datatype().bitwidth() n_thres_steps = self.get_nodeattr("numSteps") @@ -131,7 +136,7 @@ def get_weightstream_width(self): def get_weightstream_width_padded(self): """Returns weight stream width padded to a multiple of 8. This is required - by the AXI Stream spec. Used in decoupled mode.""" + by the AXI Stream spec. Used in internal_decoupled mode.""" weight_width = self.get_weightstream_width() return roundup_to_integer_multiple(weight_width, 8) @@ -304,12 +309,12 @@ def generate_params(self, model, path): code_gen_dir = path thresholds = model.get_initializer(self.onnx_node.input[1]) mem_mode = self.get_nodeattr("mem_mode") - if mem_mode == "const": + if mem_mode == "internal_embedded": # save thresholds in thresh.h weight_filename = "{}/thresh.h".format(code_gen_dir) self.make_weight_file(thresholds, "hls_header", weight_filename) - elif mem_mode == "decoupled": - # save decoupled weights for cppsim + elif mem_mode == "internal_decoupled": + # save internal_decoupled weights for cppsim weight_filename_sim = "{}/thresholds.npy".format(code_gen_dir) self.make_weight_file(thresholds, "decoupled_npy", weight_filename_sim) # also save weights as Verilog .dat file @@ -383,7 +388,7 @@ def execute_node(self, context, graph): inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) super().reset_rtlsim(sim) super().toggle_clk(sim) - if self.get_nodeattr("mem_mode") == "decoupled": + if self.get_nodeattr("mem_mode") == "internal_decoupled": wnbits = self.get_weightstream_width() export_wdt = self.get_weight_datatype() wei = npy_to_rtlsim_input( @@ -396,7 +401,7 @@ def execute_node(self, context, graph): } self.rtlsim_multi_io(sim, io_dict) output = io_dict["outputs"]["out"] - elif self.get_nodeattr("mem_mode") == "const": + elif self.get_nodeattr("mem_mode") == "internal_embedded": output = self.rtlsim(sim, inp) else: raise Exception("Unrecognized mem_mode") @@ -422,7 +427,7 @@ def execute_node(self, context, graph): def global_includes(self): self.code_gen_dict["$GLOBALS$"] = ['#include "activations.hpp"'] - if self.get_nodeattr("mem_mode") == "const": + if self.get_nodeattr("mem_mode") == "internal_embedded": self.code_gen_dict["$GLOBALS$"] += ['#include "thresh.h"'] # TODO check and add whatever missing @@ -440,7 +445,7 @@ def defines(self, var): total_spatial_size, ) ] - if self.get_nodeattr("mem_mode") == "decoupled": + if self.get_nodeattr("mem_mode") == "internal_decoupled": self.code_gen_dict["$DEFINES$"].append( "#define ActVal1 %d" % self.get_nodeattr("ActVal") ) @@ -474,7 +479,7 @@ def read_npy_data(self): ) ) mem_mode = self.get_nodeattr("mem_mode") - if mem_mode == "decoupled": + if mem_mode == "internal_decoupled": tdt = self.get_weight_datatype() elem_bits = tdt.bitwidth() packed_bits = self.get_weightstream_width() @@ -508,7 +513,7 @@ def strm_decl(self): ) ) mem_mode = self.get_nodeattr("mem_mode") - if mem_mode == "decoupled": + if mem_mode == "internal_decoupled": self.code_gen_dict["$STREAMDECLARATIONS$"].append( 'hls::stream> weights_{} ("weights_{}");'.format( self.get_weightstream_width(), self.hls_sname(), self.hls_sname() @@ -518,7 +523,7 @@ def strm_decl(self): def docompute(self): tmpl_args = self.get_template_param_values() mem_mode = self.get_nodeattr("mem_mode") - if mem_mode == "const": + if mem_mode == "internal_embedded": self.code_gen_dict["$DOCOMPUTE$"] = [ """Thresholding_Batch (in0_{}, out_{}, threshs, numReps);""".format( @@ -528,7 +533,7 @@ def docompute(self): self.hls_sname(), ) ] - elif mem_mode == "decoupled": + elif mem_mode == "internal_decoupled": # note that numReps is set to 1 in the invocation below, since # - for cppsim the repetition comes from the threshold stream reader+input # - for synth the unit runs continuously anyway (ap_ctrl_none) @@ -576,7 +581,7 @@ def dataoutstrm(self): ] def blackboxfunction(self): - if self.get_nodeattr("mem_mode") == "const": + if self.get_nodeattr("mem_mode") == "internal_embedded": self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ """void {}(hls::stream> &in0_{}, hls::stream> &out_{} @@ -588,7 +593,7 @@ def blackboxfunction(self): self.hls_sname(), ) ] - elif self.get_nodeattr("mem_mode") == "decoupled": + elif self.get_nodeattr("mem_mode") == "internal_decoupled": self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ """void {}(hls::stream> &in0_{}, hls::stream> &weights_{}, @@ -615,7 +620,7 @@ def pragmas(self): ) self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") - if self.get_nodeattr("mem_mode") == "const": + if self.get_nodeattr("mem_mode") == "internal_embedded": # the threshold tensor is acc_type [PE][TMEM][N_THRES] # partition for parallel access along PE and N_THRES # dimensions (dims 1 and 3) @@ -647,7 +652,7 @@ def pragmas(self): ram_style ) ) - elif self.get_nodeattr("mem_mode") == "decoupled": + elif self.get_nodeattr("mem_mode") == "internal_decoupled": self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE axis port=weights_" + self.hls_sname() ) @@ -656,7 +661,7 @@ def code_generation_ipi(self): cmd = [] # add streamer if needed mem_mode = self.get_nodeattr("mem_mode") - if mem_mode == "decoupled": + if mem_mode == "internal_decoupled": node_name = self.onnx_node.name runtime_writable = self.get_nodeattr("runtime_writeable_weights") == 1 sname = self.hls_sname() @@ -749,8 +754,8 @@ def code_generation_ipi(self): # TODO calculate and pass in segment size here cmd.append("assign_bd_address") cmd.append("save_bd_design") - elif mem_mode == "const": - # base class impl sufficient for const mode + elif mem_mode == "internal_embedded": + # base class impl sufficient for internal_embedded mode return super().code_generation_ipi() else: raise Exception("Unrecognized mem_mode for Thresholding_Batch") @@ -759,7 +764,7 @@ def code_generation_ipi(self): def get_verilog_top_module_intf_names(self): intf_names = super().get_verilog_top_module_intf_names() mem_mode = self.get_nodeattr("mem_mode") - if mem_mode == "decoupled": + if mem_mode == "internal_decoupled": # only expose axilite interface if attribute is set runtime_writable = self.get_nodeattr("runtime_writeable_weights") == 1 if runtime_writable: @@ -791,7 +796,7 @@ def derive_characteristic_fxns(self, period): "outputs": {"out": []}, } mem_mode = self.get_nodeattr("mem_mode") - if mem_mode in ["decoupled", "external"]: + if mem_mode in ["internal_decoupled", "external"]: n_weight_inps = self.calc_tmem() num_w_reps = np.prod(self.get_nodeattr("numInputVectors")) io_dict["inputs"]["weights"] = [0 for i in range(num_w_reps * n_weight_inps)] diff --git a/src/finn/custom_op/fpgadataflow/hls/vectorvectoractivation_hls.py b/src/finn/custom_op/fpgadataflow/hls/vectorvectoractivation_hls.py index 7e475ff67f..c7f0576495 100644 --- a/src/finn/custom_op/fpgadataflow/hls/vectorvectoractivation_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/vectorvectoractivation_hls.py @@ -114,7 +114,7 @@ def execute_node(self, context, graph): super().reset_rtlsim(sim) super().toggle_clk(sim) - if mem_mode == "external" or mem_mode == "decoupled": + if mem_mode == "external" or mem_mode == "internal_decoupled": wnbits = self.get_weightstream_width() export_wdt = self.get_weight_datatype() # we have converted bipolar weights to binary for export, @@ -196,9 +196,9 @@ def global_includes(self): self.code_gen_dict["$GLOBALS$"] = ['#include "weights.hpp"'] self.code_gen_dict["$GLOBALS$"] += ['#include "activations.hpp"'] mem_mode = self.get_nodeattr("mem_mode") - if mem_mode not in ["const", "decoupled", "external"]: + if mem_mode not in ["internal_embedded", "internal_decoupled", "external"]: raise Exception( - """Please set mem_mode to "const", "decoupled", or "external", + """Please set mem_mode to "internal_embedded", "internal_decoupled", or "external", currently no other parameter value is supported!""" ) if self.calc_tmem() != 0: @@ -221,7 +221,7 @@ def defines(self, var): numReps, ) ] - if mem_mode == "decoupled" or mem_mode == "external": + if mem_mode == "internal_decoupled" or mem_mode == "external": wdt = self.get_weight_datatype() self.code_gen_dict["$DEFINES$"].append("#define WP1 {}\n".format(wdt.bitwidth())) @@ -252,7 +252,7 @@ def read_npy_data(self): ) mem_mode = self.get_nodeattr("mem_mode") - if mem_mode == "decoupled" or mem_mode == "external": + if mem_mode == "internal_decoupled" or mem_mode == "external": wdt = self.get_weight_datatype() elem_bits = wdt.bitwidth() packed_bits = self.get_weightstream_width() @@ -286,7 +286,7 @@ def strm_decl(self): self.get_outstream_width(), self.hls_sname(), self.hls_sname() ) ) - if mem_mode == "decoupled" or mem_mode == "external": + if mem_mode == "internal_decoupled" or mem_mode == "external": self.code_gen_dict["$STREAMDECLARATIONS$"].append( 'hls::stream> weights_{} ("weights_{}");'.format( self.get_weightstream_width(), self.hls_sname(), self.hls_sname() @@ -307,7 +307,7 @@ def docompute(self): else: threshs = "threshs" - if mem_mode == "const": + if mem_mode == "internal_embedded": self.code_gen_dict["$DOCOMPUTE$"] = [ """Vector_Vector_Activate_Batch (in0_{}, out_{}, weights, {}, numReps, {});""".format( @@ -320,7 +320,7 @@ def docompute(self): map_to_hls_mult_style[self.get_nodeattr("resType")], ) ] - elif mem_mode == "decoupled" or mem_mode == "external": + elif mem_mode == "internal_decoupled" or mem_mode == "external": wdt = self.get_weight_datatype() if wdt == DataType["BIPOLAR"]: export_wdt = DataType["BINARY"] @@ -344,7 +344,7 @@ def docompute(self): ] else: raise Exception( - """Please set mem_mode to "const", "decoupled", or "external", + """Please set mem_mode to "internal_embedded", "internal_decoupled", or "external", currently no other parameter value is supported!""" ) @@ -382,7 +382,7 @@ def save_as_npy(self): def blackboxfunction(self): mem_mode = self.get_nodeattr("mem_mode") - if mem_mode == "const": + if mem_mode == "internal_embedded": self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ """void {}(hls::stream> &in0_{}, hls::stream> &out_{} @@ -394,7 +394,7 @@ def blackboxfunction(self): self.hls_sname(), ) ] - elif mem_mode == "decoupled" or mem_mode == "external": + elif mem_mode == "internal_decoupled" or mem_mode == "external": self.code_gen_dict["$BLACKBOXFUNCTION$"] = [ """void {}( hls::stream> &in0_{}, @@ -412,8 +412,8 @@ def blackboxfunction(self): ] else: raise Exception( - """Please set mem_mode to "const" or "decoupled", currently no other - parameter value is supported!""" + """Please set mem_mode to "internal_embedded" or "internal_decoupled", + currently no other parameter value is supported!""" ) def pragmas(self): @@ -426,20 +426,20 @@ def pragmas(self): ) self.code_gen_dict["$PRAGMAS$"].append("#pragma HLS INTERFACE ap_ctrl_none port=return") - if mem_mode == "const": + if mem_mode == "internal_embedded": self.code_gen_dict["$PRAGMAS$"].append('#include "params.h"') # the weight tensor is ap_uint [PE][WMEM] # partition for parallel access along the PE dimension (dim 1) self.code_gen_dict["$PRAGMAS$"].append( ("#pragma HLS ARRAY_PARTITION variable=weights.m_weights " "complete dim=1") ) - elif mem_mode == "decoupled" or mem_mode == "external": + elif mem_mode == "internal_decoupled" or mem_mode == "external": self.code_gen_dict["$PRAGMAS$"].append( "#pragma HLS INTERFACE axis port=weights_" + self.hls_sname() ) else: raise Exception( - """Please set mem_mode to "const", "decoupled", or external, + """Please set mem_mode to "internal_embedded", "internal_decoupled", or external, currently no other parameter value is supported!""" ) @@ -458,7 +458,7 @@ def get_verilog_top_module_intf_names(self): sname = self.hls_sname() if mem_mode == "external": intf_names["s_axis"].append(("weights_" + sname, self.get_weightstream_width_padded())) - if mem_mode == "decoupled": + if mem_mode == "internal_decoupled": # only expose axilite interface if attribute is set runtime_writable = self.get_nodeattr("runtime_writeable_weights") == 1 if runtime_writable: diff --git a/src/finn/custom_op/fpgadataflow/lookup.py b/src/finn/custom_op/fpgadataflow/lookup.py index 367bda1f07..ab6228a5d6 100644 --- a/src/finn/custom_op/fpgadataflow/lookup.py +++ b/src/finn/custom_op/fpgadataflow/lookup.py @@ -57,9 +57,9 @@ def get_nodeattr_types(self): # Input shape "InputShape": ("ints", False, [1]), # Memory mode - # const : parameters baked into bitfile (BRAM) + # internal_embedded : parameters baked into bitfile (BRAM) # external : lookup performed in external memory over AXI MM - "mem_mode": ("s", False, "const", ["const", "external"]), + "mem_mode": ("s", False, "internal_embedded", ["internal_embedded", "external"]), # Width for AXI-MM interface # only relevant when mem_mode="external" "ext_mem_width": ("i", False, 32), @@ -90,7 +90,7 @@ def get_folded_output_shape(self, ind=0): ishape = self.get_normal_input_shape() mem_mode = self.get_nodeattr("mem_mode") emb_dim = self.get_nodeattr("EmbeddingDim") - if mem_mode == "const": + if mem_mode == "internal_embedded": oshape = list(ishape) + [emb_dim] elif mem_mode == "external": ext_mem_width = self.get_nodeattr("ext_mem_width") @@ -187,9 +187,9 @@ def execute_node(self, context, graph): def bram_estimation(self): mem_mode = self.get_nodeattr("mem_mode") - if mem_mode == "const": + if mem_mode == "internal_embedded": # current calculation assumes embeddings always stored in BRAM_18Ks - # when mem_mode is const + # when mem_mode is internal_embedded width_factor = ceil(self.get_outstream_width() / 16) depth_factor = ceil(self.get_nodeattr("NumEmbeddings") / 1024) return width_factor * depth_factor diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index ac173e4af6..a9f62077bd 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -82,11 +82,16 @@ def get_nodeattr_types(self): # [1, 4, 4] is four * four vectors (like a conv layer with batch=1) "numInputVectors": ("ints", False, [1]), # memory mode for the FC weights - # const -- embedded weights, default, long compile/synth times - # decoupled -- streaming weights with weight streamer packaged inside IP + # internal_embedded -- embedded weights, long compile/synth times + # internal_decoupled -- default, streaming weights with streamer packaged inside IP # external -- streaming weights with external streamer - "mem_mode": ("s", False, "const", {"const", "decoupled", "external"}), - # FPGA resource type for memories in decoupled mode + "mem_mode": ( + "s", + False, + "internal_decoupled", + {"internal_embedded", "internal_decoupled", "external"}, + ), + # FPGA resource type for memories in internal_decoupled mode # auto -- let Vivado decide # block -- use BRAM # distributed -- use LUTRAM @@ -108,8 +113,8 @@ def get_nodeattr_types(self): "auto", {"auto", "block", "distributed"}, ), - # (mem_mode = decoupled only) whether weights will be writable through - # an AXI-lite interface during runtime + # (mem_mode = internal_decoupled only) whether weights will be + # writeable through an AXI-lite interface during runtime # 1 for enabled, 0 for disabled. # see finn-rtllib/memstream/doc/README for more about the memory # address map used for writable weights @@ -265,9 +270,10 @@ def get_outstream_width(self, ind=0): return out_width def get_weightstream_width(self): - """Returns weight stream width. Used only in decoupled mode.""" + """Returns weight stream width. + Used only in internal_decoupled and external mode.""" if ( - self.get_nodeattr("mem_mode") == "decoupled" + self.get_nodeattr("mem_mode") == "internal_decoupled" or self.get_nodeattr("mem_mode") == "external" ): pe = self.get_nodeattr("PE") @@ -280,7 +286,7 @@ def get_weightstream_width(self): def get_weightstream_width_padded(self): """Returns weight stream width padded to a multiple of 8. This is required - by the AXI Stream spec. Used in decoupled mode.""" + by the AXI Stream spec. Used in internal_decoupled mode.""" weight_width = self.get_weightstream_width() return roundup_to_integer_multiple(weight_width, 8) @@ -360,8 +366,8 @@ def uram_estimation(self): mmode = self.get_nodeattr("mem_mode") mstyle = self.get_nodeattr("ram_style") if ( - (mmode == "decoupled" and mstyle != "ultra") - or (mmode == "const" and self.calc_wmem() <= 128) + (mmode == "internal_decoupled" and mstyle != "ultra") + or (mmode == "internal_embedded" and self.calc_wmem() <= 128) or (mmode == "external") ): return 0 @@ -389,13 +395,14 @@ def bram_estimation(self): mmode = self.get_nodeattr("mem_mode") mstyle = self.get_nodeattr("ram_style") if ( - (mmode == "decoupled" and mstyle in ["distributed", "ultra"]) - or (mmode == "const" and self.calc_wmem() <= 128) + (mmode == "internal_decoupled" and mstyle in ["distributed", "ultra"]) + or (mmode == "internal_embedded" and self.calc_wmem() <= 128) or (mmode == "external") ): return 0 # assuming SDP mode RAMB18s (see UG573 Table 1-10) - # assuming decoupled (RTL) memory, which is more efficient than const (HLS) + # assuming internal_decoupled (RTL) memory, + # which is more efficient than internal_embedded (HLS) if mem_width == 1: return math.ceil(omega / 16384) elif mem_width == 2: @@ -674,7 +681,7 @@ def make_weight_file(self, weights, weight_file_mode, weight_file_name): f_weights.write(weight_hls_code) f_weights.close() elif "decoupled" in weight_file_mode: - # create a weight stream for various flavors of decoupled mode: + # create a weight stream for various flavors of internal_decoupled mode: # transpose weight tensor from (1, PE, WMEM, SIMD) to (1, WMEM, PE, SIMD) weight_tensor_unflipped = np.transpose(weight_tensor, (0, 2, 1, 3)) # reverse SIMD flip for saving weights in .npy @@ -739,22 +746,22 @@ def generate_params(self, model, path): code_gen_dir = path # weights, if not external weights = model.get_initializer(self.onnx_node.input[1]) - if mem_mode == "const": + if mem_mode == "internal_embedded": # save hlslib-compatible weights in params.h weight_filename = "{}/params.h".format(code_gen_dir) self.make_weight_file(weights, "hls_header", weight_filename) - elif mem_mode == "decoupled" or mem_mode == "external": + elif mem_mode == "internal_decoupled" or mem_mode == "external": weight_filename_sim = "{}/weights.npy".format(code_gen_dir) - # save decoupled weights for cppsim + # save internal_decoupled weights for cppsim self.make_weight_file(weights, "decoupled_npy", weight_filename_sim) - if mem_mode == "decoupled": + if mem_mode == "internal_decoupled": # also save weights as Verilog .dat file # This file will be ignored when synthesizing UltraScale memory. weight_filename_rtl = "{}/memblock.dat".format(code_gen_dir) self.make_weight_file(weights, "decoupled_verilog_dat", weight_filename_rtl) else: raise Exception( - """Please set mem_mode to "const", "decoupled", or "external", + """Please set mem_mode to "internal_embedded", "internal_decoupled", or "external", currently no other parameter value is supported!""" ) @@ -840,7 +847,7 @@ def derive_characteristic_fxns(self, period): "outputs": {"out": []}, } mem_mode = self.get_nodeattr("mem_mode") - if mem_mode in ["decoupled", "external"]: + if mem_mode in ["internal_decoupled", "external"]: n_weight_inps = self.calc_wmem() num_w_reps = np.prod(self.get_nodeattr("numInputVectors")) io_dict["inputs"]["weights"] = [0 for i in range(num_w_reps * n_weight_inps)] @@ -850,7 +857,7 @@ def code_generation_ipi(self): cmd = [] # add streamer if needed mem_mode = self.get_nodeattr("mem_mode") - if mem_mode == "decoupled": + if mem_mode == "internal_decoupled": runtime_writable = self.get_nodeattr("runtime_writeable_weights") == 1 if self.get_nodeattr("ram_style") == "ultra": assert ( @@ -945,8 +952,8 @@ def code_generation_ipi(self): # TODO calculate and pass in segment size here cmd.append("assign_bd_address") cmd.append("save_bd_design") - elif mem_mode == "const" or mem_mode == "external": - # base class impl sufficient for const/external modes + elif mem_mode == "internal_embedded" or mem_mode == "external": + # base class impl sufficient for internal_embedded/external modes self.instantiate_ip(cmd) else: raise Exception("Unrecognized mem_mode for MatrixVectorActivation") diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index 79265f8daa..c5ec7e0648 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -67,11 +67,16 @@ def get_nodeattr_types(self): # no-activation mode (produce accumulators) "noActivation": ("i", False, 0, {0, 1}), # memory mode for the layer weights - # const -- embedded weights, default, long compile/synth times - # decoupled -- streaming weights with weight streamer packaged inside IP + # internal_embedded -- embedded weights, long compile/synth times + # internal_decoupled -- default, streaming weights with streamer packaged inside IP # external -- streaming weights with external streamer - "mem_mode": ("s", False, "const", {"const", "decoupled", "external"}), - # (mem_mode = decoupled only) whether weights will be writable through + "mem_mode": ( + "s", + False, + "internal_decoupled", + {"internal_embedded", "internal_decoupled", "external"}, + ), + # (mem_mode = internal_decoupled only) whether weights will be writable through # an AXI-lite interface during runtime # 1 for enabled, 0 for disabled. # see finn-rtllib/memstream/doc/README for more about the memory @@ -81,7 +86,7 @@ def get_nodeattr_types(self): # vector through the accelerator. This will get rid of any old # weight data from the weight FIFOs. "runtime_writeable_weights": ("i", False, 0, {0, 1}), - # FPGA resource type for memories in decoupled mode + # FPGA resource type for memories in internal_decoupled mode # auto -- let Vivado decide # block -- use BRAM # distributed -- use LUTRAM @@ -200,9 +205,9 @@ def get_instream_width(self, ind=0): return in_width def get_weightstream_width(self): - """Returns weight stream width. Used only in decoupled mode.""" + """Returns weight stream width. Used only in internal_decoupled mode.""" if ( - self.get_nodeattr("mem_mode") == "decoupled" + self.get_nodeattr("mem_mode") == "internal_decoupled" or self.get_nodeattr("mem_mode") == "external" ): simd = self.get_nodeattr("SIMD") @@ -220,7 +225,7 @@ def get_outstream_width(self, ind=0): def get_weightstream_width_padded(self): """Returns weight stream width padded to a multiple of 8. This is required - by the AXI Stream spec. Used in decoupled mode.""" + by the AXI Stream spec. Used in internal_decoupled mode.""" weight_width = self.get_weightstream_width() return roundup_to_integer_multiple(weight_width, 8) @@ -300,8 +305,8 @@ def uram_estimation(self): mmode = self.get_nodeattr("mem_mode") mstyle = self.get_nodeattr("ram_style") if ( - (mmode == "decoupled" and mstyle != "ultra") - or (mmode == "const") + (mmode == "internal_decoupled" and mstyle != "ultra") + or (mmode == "internal_embedded") or (mmode == "external") ): return 0 @@ -324,9 +329,9 @@ def bram_estimation(self): mmode = self.get_nodeattr("mem_mode") mstyle = self.get_nodeattr("ram_style") if ( - (mmode == "decoupled" and mstyle in ["distributed", "ultra"]) + (mmode == "internal_decoupled" and mstyle in ["distributed", "ultra"]) or (mstyle == "auto" and self.calc_wmem() <= 128) - or (mmode == "const" and self.calc_wmem() <= 128) + or (mmode == "internal_embedded" and self.calc_wmem() <= 128) or (mmode == "external") ): return 0 @@ -392,8 +397,8 @@ def lut_estimation(self): c2 = 0 mmode = self.get_nodeattr("mem_mode") mstyle = self.get_nodeattr("ram_style") - if (mmode == "decoupled" and mstyle == "distributed") or ( - mmode == "const" and self.calc_wmem() <= 128 + if (mmode == "internal_decoupled" and mstyle == "distributed") or ( + mmode == "internal_embedded" and self.calc_wmem() <= 128 ): c2 = (P * Q * W) * math.ceil(self.calc_wmem() / 64) @@ -679,7 +684,7 @@ def make_weight_file(self, weights, weight_file_mode, weight_file_name): f_weights.write(weight_hls_code) f_weights.close() elif "decoupled" in weight_file_mode: - # create a weight stream for various flavors of decoupled mode: + # create a weight stream for various flavors of internal_decoupled mode: # transpose weight tensor from (1, PE, WMEM, SIMD) to (1, WMEM, PE, SIMD) weight_tensor_unflipped = np.transpose(weight_tensor, (0, 2, 1, 3)) # reverse SIMD flip for saving weights in .npy @@ -744,22 +749,22 @@ def generate_params(self, model, path): code_gen_dir = path # weights, if not external weights = model.get_initializer(self.onnx_node.input[1]) - if mem_mode == "const": + if mem_mode == "internal_embedded": # save hlslib-compatible weights in params.h weight_filename = "{}/params.h".format(code_gen_dir) self.make_weight_file(weights, "hls_header", weight_filename) - elif mem_mode == "decoupled" or mem_mode == "external": + elif mem_mode == "internal_decoupled" or mem_mode == "external": weight_filename_sim = "{}/weights.npy".format(code_gen_dir) - # save decoupled weights for cppsim + # save internal_decoupled weights for cppsim self.make_weight_file(weights, "decoupled_npy", weight_filename_sim) - if mem_mode == "decoupled": + if mem_mode == "internal_decoupled": # also save weights as Verilog .dat file # This file will be ignored when synthesizing UltraScale memory. weight_filename_rtl = "{}/memblock.dat".format(code_gen_dir) self.make_weight_file(weights, "decoupled_verilog_dat", weight_filename_rtl) else: raise Exception( - """Please set mem_mode to "const", "decoupled", or "external", + """Please set mem_mode to "internal_embedded", "internal_decoupled", or "external", currently no other parameter value is supported!""" ) @@ -845,7 +850,7 @@ def derive_characteristic_fxns(self, period): "outputs": {"out": []}, } mem_mode = self.get_nodeattr("mem_mode") - if mem_mode in ["decoupled", "external"]: + if mem_mode in ["internal_decoupled", "external"]: n_weight_inps = self.calc_wmem() num_w_reps = np.prod(self.get_nodeattr("numInputVectors")) io_dict["inputs"]["weights"] = [0 for i in range(num_w_reps * n_weight_inps)] @@ -855,7 +860,7 @@ def code_generation_ipi(self): cmd = [] # add streamer if needed mem_mode = self.get_nodeattr("mem_mode") - if mem_mode == "decoupled": + if mem_mode == "internal_decoupled": runtime_writable = self.get_nodeattr("runtime_writeable_weights") == 1 if self.get_nodeattr("ram_style") == "ultra": assert ( @@ -952,8 +957,8 @@ def code_generation_ipi(self): # TODO calculate and pass in segment size here cmd.append("assign_bd_address") cmd.append("save_bd_design") - elif mem_mode == "const" or mem_mode == "external": - # base class impl sufficient for const/external modes + elif mem_mode == "internal_embedded" or mem_mode == "external": + # base class impl sufficient for internal_embedded/external modes return super().code_generation_ipi() else: raise Exception("Unrecognized mem_mode for VectorVectorActivation") diff --git a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py index 014a5c82bd..fdb892e911 100644 --- a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py +++ b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py @@ -1287,9 +1287,8 @@ class InferBinaryMatrixVectorActivation(Transformation): MatrixVectorActivation layers. Any immediately following MultiThreshold layers will also be absorbed into the MVTU.""" - def __init__(self, mem_mode="const"): + def __init__(self): super().__init__() - self.mem_mode = mem_mode def apply(self, model): graph = model.graph @@ -1372,7 +1371,6 @@ def apply(self, model): binaryXnorMode=1, noActivation=0, numInputVectors=list(mm_in_shape[:-1]), - mem_mode=self.mem_mode, name=n.name, ) graph.node.insert(node_ind, new_node) @@ -1403,7 +1401,6 @@ def apply(self, model): binaryXnorMode=1, noActivation=1, numInputVectors=list(mm_in_shape[:-1]), - mem_mode=self.mem_mode, name=n.name, ) graph.node.insert(node_ind, new_node) @@ -1420,9 +1417,8 @@ class InferQuantizedMatrixVectorActivation(Transformation): """Convert MatMul layers with quantized inputs and weights to MatrixVectorActivation layers.""" - def __init__(self, mem_mode="const"): + def __init__(self): super().__init__() - self.mem_mode = mem_mode def apply(self, model): graph = model.graph @@ -1509,7 +1505,6 @@ def apply(self, model): binaryXnorMode=0, noActivation=0, numInputVectors=list(mm_in_shape[:-1]), - mem_mode=self.mem_mode, name="MVAU_" + n.name, ) graph.node.insert(node_ind, new_node) @@ -1540,7 +1535,6 @@ def apply(self, model): binaryXnorMode=0, noActivation=1, numInputVectors=list(mm_in_shape[:-1]), - mem_mode=self.mem_mode, name="MVAU_" + n.name, ) graph.node.insert(node_ind, new_node) @@ -1560,9 +1554,8 @@ class InferVectorVectorActivation(Transformation): a depthwise convolution. Any immediately following MultiThreshold layers will also be absorbed into the VVAU.""" - def __init__(self, mem_mode="const"): + def __init__(self): super().__init__() - self.mem_mode = mem_mode def apply(self, model): graph = model.graph @@ -1659,7 +1652,6 @@ def apply(self, model): ActVal=actval, noActivation=0, name="VectorVectorActivation_" + n.name, - mem_mode=self.mem_mode, ) graph.node.insert(node_ind, new_node) # remove old nodes diff --git a/src/finn/transformation/fpgadataflow/make_zynq_proj.py b/src/finn/transformation/fpgadataflow/make_zynq_proj.py index 7e3754e41e..ade38ddfbf 100644 --- a/src/finn/transformation/fpgadataflow/make_zynq_proj.py +++ b/src/finn/transformation/fpgadataflow/make_zynq_proj.py @@ -65,7 +65,7 @@ def collect_ip_dirs(model, ipstitch_path): contain the generated ip blocks doesn't exist.""" ip_dirs += [ip_dir_value] if node.op_type.startswith("MVAU") or node.op_type.startswith("Thresholding"): - if node_inst.get_nodeattr("mem_mode") == "decoupled": + if node_inst.get_nodeattr("mem_mode") == "internal_decoupled": need_memstreamer = True ip_dirs += [ipstitch_path + "/ip"] if need_memstreamer: diff --git a/src/finn/transformation/fpgadataflow/set_fifo_depths.py b/src/finn/transformation/fpgadataflow/set_fifo_depths.py index d81f1fe247..e150e7a10b 100644 --- a/src/finn/transformation/fpgadataflow/set_fifo_depths.py +++ b/src/finn/transformation/fpgadataflow/set_fifo_depths.py @@ -290,10 +290,11 @@ def apply(self, model): mmode = node.get_nodeattr("mem_mode") if mmode == "external": modified_fc_nodes.append(node.onnx_node.name) - node.set_nodeattr("mem_mode", "decoupled") + node.set_nodeattr("mem_mode", "internal_decoupled") reset_implementation(node) warnings.warn( - "Changed mem_mode from external to decoupled for " + node.onnx_node.name + "Changed mem_mode from external to internal_decoupled for " + + node.onnx_node.name ) # insert stream infrastructure (DWC/FIFO) diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index bdede35244..0fab1b298e 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -108,7 +108,7 @@ build_dir = os.environ["FINN_BUILD_DIR"] target_clk_ns = 20 -mem_mode = "decoupled" +mem_mode = "internal_decoupled" rtlsim_trace = False @@ -134,7 +134,7 @@ def fold_tfc(model): inp_qnt_node = model.get_nodes_by_op_type("Thresholding_hls")[0] inp_qnt = getCustomOp(inp_qnt_node) inp_qnt.set_nodeattr("PE", 49) - inp_qnt.set_nodeattr("mem_mode", "decoupled") + inp_qnt.set_nodeattr("mem_mode", "internal_decoupled") inp_qnt.set_nodeattr("runtime_writeable_weights", 1) return model diff --git a/tests/end2end/test_end2end_mobilenet_v1.py b/tests/end2end/test_end2end_mobilenet_v1.py index 1fceda8141..abd019c7bc 100644 --- a/tests/end2end/test_end2end_mobilenet_v1.py +++ b/tests/end2end/test_end2end_mobilenet_v1.py @@ -92,7 +92,7 @@ test_platform = alveo_default_platform[test_board] test_fpga_part = alveo_part_map[test_board] target_clk_ns = 3 -mem_mode = "decoupled" +mem_mode = "internal_decoupled" large_fifo_ram_style = "ultra" extra_fold = 1 first_layer_res_type = "dsp" diff --git a/tests/fpgadataflow/test_convert_to_hw_layers_cnv.py b/tests/fpgadataflow/test_convert_to_hw_layers_cnv.py index 64ccebf97a..96e945d083 100644 --- a/tests/fpgadataflow/test_convert_to_hw_layers_cnv.py +++ b/tests/fpgadataflow/test_convert_to_hw_layers_cnv.py @@ -113,7 +113,7 @@ def test_convert_to_hw_layers_cnv_w1a1(fused_activation): for node in model.graph.node: if node.op_type == "MVAU_hls": inst = getCustomOp(node) - inst.set_nodeattr("mem_mode", "decoupled") + inst.set_nodeattr("mem_mode", "internal_decoupled") mw = inst.get_nodeattr("MW") mh = inst.get_nodeattr("MH") if mh % 4 == 0: diff --git a/tests/fpgadataflow/test_fifosizing.py b/tests/fpgadataflow/test_fifosizing.py index f3716dea9b..338204c0c7 100644 --- a/tests/fpgadataflow/test_fifosizing.py +++ b/tests/fpgadataflow/test_fifosizing.py @@ -76,7 +76,6 @@ def test_fifosizing_linear(method, topology): build_cfg.DataflowOutputType.STITCHED_IP, build_cfg.DataflowOutputType.RTLSIM_PERFORMANCE, ], - default_mem_mode=build_cfg.ComputeEngineMemMode.DECOUPLED, ) build.build_dataflow_cfg(tmp_output_dir + "/model.onnx", cfg) with open(tmp_output_dir + "/report/estimate_network_performance.json") as f: diff --git a/tests/fpgadataflow/test_fpgadataflow_checksum.py b/tests/fpgadataflow/test_fpgadataflow_checksum.py index 81a4e3e33c..34a48996c9 100644 --- a/tests/fpgadataflow/test_fpgadataflow_checksum.py +++ b/tests/fpgadataflow/test_fpgadataflow_checksum.py @@ -72,10 +72,10 @@ def create_two_fc_model(): outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, [1, m]) fc0 = helper.make_node( - "MVAU", + "MVAU_hls", ["inp", "w0"], ["mid"], - domain="finn.custom_op.fpgadataflow", + domain="finn.custom_op.fpgadataflow.hls", backend="fpgadataflow", MW=m, MH=m, @@ -87,14 +87,14 @@ def create_two_fc_model(): ActVal=actval, binaryXnorMode=binary_xnor_mode, noActivation=no_act, - mem_mode="decoupled", + mem_mode="internal_decoupled", ) fc1 = helper.make_node( - "MVAU", + "MVAU_hls", ["mid", "w1"], ["outp"], - domain="finn.custom_op.fpgadataflow", + domain="finn.custom_op.fpgadataflow.hls", backend="fpgadataflow", MW=m, MH=m, @@ -106,7 +106,7 @@ def create_two_fc_model(): ActVal=actval, binaryXnorMode=binary_xnor_mode, noActivation=no_act, - mem_mode="decoupled", + mem_mode="internal_decoupled", ) graph = helper.make_graph( @@ -141,7 +141,6 @@ def test_fpgadataflow_checksum(): # use a graph consisting of two fc layers to test # checksum node insertion model = create_two_fc_model() - model = model.transform(SpecializeLayers()) # set checksum output hook for n in model.graph.node: diff --git a/tests/fpgadataflow/test_fpgadataflow_ipstitch.py b/tests/fpgadataflow/test_fpgadataflow_ipstitch.py index ab62b2d476..2061601b4a 100644 --- a/tests/fpgadataflow/test_fpgadataflow_ipstitch.py +++ b/tests/fpgadataflow/test_fpgadataflow_ipstitch.py @@ -62,7 +62,7 @@ ip_stitch_model_dir = os.environ["FINN_BUILD_DIR"] -def create_one_fc_model(mem_mode="const"): +def create_one_fc_model(mem_mode="internal_embedded"): # create a model with a MatrixVectorActivation instance with no activation # the wider range of the full accumulator makes debugging a bit easier wdt = DataType["INT2"] @@ -114,7 +114,7 @@ def create_one_fc_model(mem_mode="const"): return model -def create_two_fc_model(mem_mode="decoupled"): +def create_two_fc_model(mem_mode="internal_decoupled"): # create a model with two MatrixVectorActivation instances wdt = DataType["INT2"] idt = DataType["INT32"] @@ -195,7 +195,7 @@ def create_two_fc_model(mem_mode="decoupled"): return model -@pytest.mark.parametrize("mem_mode", ["const", "decoupled"]) +@pytest.mark.parametrize("mem_mode", ["internal_embedded", "internal_decoupled"]) @pytest.mark.fpgadataflow @pytest.mark.vivado def test_fpgadataflow_ipstitch_gen_model(mem_mode): @@ -214,7 +214,7 @@ def test_fpgadataflow_ipstitch_gen_model(mem_mode): model.save(ip_stitch_model_dir + "/test_fpgadataflow_ipstitch_gen_model_%s.onnx" % mem_mode) -@pytest.mark.parametrize("mem_mode", ["const", "decoupled"]) +@pytest.mark.parametrize("mem_mode", ["internal_embedded", "internal_decoupled"]) @pytest.mark.fpgadataflow @pytest.mark.vivado def test_fpgadataflow_ipstitch_do_stitch(mem_mode): @@ -232,7 +232,7 @@ def test_fpgadataflow_ipstitch_do_stitch(mem_mode): model.save(ip_stitch_model_dir + "/test_fpgadataflow_ip_stitch_%s.onnx" % mem_mode) -@pytest.mark.parametrize("mem_mode", ["const", "decoupled"]) +@pytest.mark.parametrize("mem_mode", ["internal_embedded", "internal_decoupled"]) @pytest.mark.fpgadataflow @pytest.mark.vivado def test_fpgadataflow_ipstitch_rtlsim(mem_mode): @@ -281,7 +281,7 @@ def test_fpgadataflow_ipstitch_rtlsim(mem_mode): assert (rtlsim_res == x).all() -@pytest.mark.parametrize("mem_mode", ["const", "decoupled"]) +@pytest.mark.parametrize("mem_mode", ["internal_embedded", "internal_decoupled"]) @pytest.mark.fpgadataflow @pytest.mark.vivado @pytest.mark.slow @@ -336,7 +336,7 @@ def test_fpgadataflow_ipstitch_vitis_end2end(board, period_ns, extw): pytest.skip("VITIS_PATH not set") platform = alveo_default_platform[board] fpga_part = alveo_part_map[board] - model = create_two_fc_model("external" if extw else "decoupled") + model = create_two_fc_model("external" if extw else "internal_decoupled") if model.graph.node[0].op_type == "StreamingDataflowPartition": sdp_node = getCustomOp(model.graph.node[0]) assert sdp_node.__class__.__name__ == "StreamingDataflowPartition" diff --git a/tests/fpgadataflow/test_fpgadataflow_mvau.py b/tests/fpgadataflow/test_fpgadataflow_mvau.py index 216b0f2937..c4112acfa4 100644 --- a/tests/fpgadataflow/test_fpgadataflow_mvau.py +++ b/tests/fpgadataflow/test_fpgadataflow_mvau.py @@ -217,8 +217,8 @@ def test_fpgadataflow_mvau_hwop(idt, wdt, act, nf, sf, mw, mh): assert (y_produced == y_expected).all(), "cppsim hw-op failed" -# mem_mode: const or decoupled -@pytest.mark.parametrize("mem_mode", ["const", "decoupled", "external"]) +# mem_mode: internal_embedded or internal_decoupled +@pytest.mark.parametrize("mem_mode", ["internal_embedded", "internal_decoupled", "external"]) # activation: None or DataType @pytest.mark.parametrize("act", [None, DataType["BIPOLAR"], DataType["INT4"]]) # weight datatype @@ -310,8 +310,8 @@ def test_fpgadataflow_mvau_cppsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): assert (y_produced == y_expected).all(), "cppsim hls-op failed" -# mem_mode: const or decoupled -@pytest.mark.parametrize("mem_mode", ["const", "decoupled", "external"]) +# mem_mode: internal_embedded or internal_decoupled +@pytest.mark.parametrize("mem_mode", ["internal_embedded", "internal_decoupled", "external"]) # activation: None or DataType @pytest.mark.parametrize("act", [None, DataType["BIPOLAR"], DataType["INT4"]]) # weight datatype @@ -411,8 +411,8 @@ def test_fpgadataflow_mvau_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): assert exp_cycles != 0 -# mem_mode: const or decoupled -@pytest.mark.parametrize("mem_mode", ["decoupled"]) +# mem_mode: internal_embedded or internal_decoupled +@pytest.mark.parametrize("mem_mode", ["internal_decoupled"]) # activation: None or DataType @pytest.mark.parametrize("act", [DataType["INT4"]]) # weight datatype @@ -513,8 +513,8 @@ def test_fpgadataflow_mvau_large_depth_decoupled_mode_rtlsim( assert exp_cycles != 0 -# mem_mode: const or decoupled -@pytest.mark.parametrize("mem_mode", ["decoupled", "const"]) +# mem_mode: internal_embedded or internal_decoupled +@pytest.mark.parametrize("mem_mode", ["internal_decoupled", "internal_embedded"]) # activation: None or DataType @pytest.mark.parametrize("act", [DataType["INT4"]]) # weight datatype diff --git a/tests/fpgadataflow/test_fpgadataflow_thresholding.py b/tests/fpgadataflow/test_fpgadataflow_thresholding.py index 43eca7b7c3..6cf7b4fd40 100644 --- a/tests/fpgadataflow/test_fpgadataflow_thresholding.py +++ b/tests/fpgadataflow/test_fpgadataflow_thresholding.py @@ -57,7 +57,7 @@ target_clk_ns = 5 -def make_single_thresholding_modelwrapper(T, pe, idt, odt, actval, mem_mode, n_inp_vecs): +def make_single_thresholding_modelwrapper(T, idt, odt, actval, n_inp_vecs): NumChannels = T.shape[0] inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, n_inp_vecs + [NumChannels]) @@ -72,13 +72,11 @@ def make_single_thresholding_modelwrapper(T, pe, idt, odt, actval, mem_mode, n_i domain="finn.custom_op.fpgadataflow", backend="fpgadataflow", NumChannels=NumChannels, - PE=pe, numSteps=T.shape[1], inputDataType=idt.name, weightDataType=idt.name, # will be set by MinimizeAccumulatorWidth outputDataType=odt.name, ActVal=actval, - mem_mode=mem_mode, numInputVectors=n_inp_vecs, ) graph = helper.make_graph( @@ -110,7 +108,7 @@ def make_single_thresholding_modelwrapper(T, pe, idt, odt, actval, mem_mode, n_i # execution mode @pytest.mark.parametrize("exec_mode", ["cppsim", "rtlsim"]) # memory mode -@pytest.mark.parametrize("mem_mode", ["const", "decoupled"]) +@pytest.mark.parametrize("mem_mode", ["internal_embedded", "internal_decoupled"]) @pytest.mark.fpgadataflow @pytest.mark.vivado @pytest.mark.slow @@ -135,7 +133,7 @@ def test_fpgadataflow_thresholding(idt, act, nf, ich, exec_mode, mem_mode): else: actval = odt.min() - model = make_single_thresholding_modelwrapper(T, pe, idt, odt, actval, mem_mode, n_inp_vecs) + model = make_single_thresholding_modelwrapper(T, idt, odt, actval, n_inp_vecs) # calculate reference output # multithreshold util fxn wants NCHW input, not NHWC @@ -163,6 +161,10 @@ def test_fpgadataflow_thresholding(idt, act, nf, ich, exec_mode, mem_mode): assert (y_produced == y_expected).all() model = model.transform(SpecializeLayers()) + node = model.graph.node[0] + inst = getCustomOp(node) + inst.set_nodeattr("PE", pe) + inst.set_nodeattr("mem_mode", mem_mode) if exec_mode == "cppsim": model = model.transform(PrepareCppSim()) @@ -201,7 +203,7 @@ def test_fpgadataflow_thresholding(idt, act, nf, ich, exec_mode, mem_mode): @pytest.mark.vivado def test_runtime_thresholds_single_layer(): n_inp_vecs = [1, 2, 2] - mem_mode = "decoupled" + mem_mode = "internal_decoupled" act = DataType["INT4"] idt = DataType["INT16"] nf = 8 diff --git a/tests/fpgadataflow/test_fpgadataflow_vvau.py b/tests/fpgadataflow/test_fpgadataflow_vvau.py index d4fef6952d..eb521f965a 100644 --- a/tests/fpgadataflow/test_fpgadataflow_vvau.py +++ b/tests/fpgadataflow/test_fpgadataflow_vvau.py @@ -91,7 +91,7 @@ def _make_single_vvau_modelwrapper( odt, T=None, tdt=None, - mem_mode="const", + mem_mode="internal_embedded", ): in_shape = [1, dim_h, dim_w, k_h * k_w * channels] # [N, H, W, K*K*CH] out_shape = [ @@ -181,7 +181,7 @@ def prepare_inputs(input_tensor): # Number of input and output channels @pytest.mark.parametrize("channels", [3, 6]) # memory mode -@pytest.mark.parametrize("mem_mode", ["const", "decoupled"]) +@pytest.mark.parametrize("mem_mode", ["internal_embedded", "internal_decoupled"]) # execution mode @pytest.mark.parametrize("exec_mode", ["cppsim", "rtlsim"]) @pytest.mark.fpgadataflow diff --git a/tests/fpgadataflow/test_runtime_weights.py b/tests/fpgadataflow/test_runtime_weights.py index 32534d4aa5..3e7822a077 100644 --- a/tests/fpgadataflow/test_runtime_weights.py +++ b/tests/fpgadataflow/test_runtime_weights.py @@ -73,7 +73,7 @@ def test_runtime_weights_single_layer(): model = model.transform(SpecializeLayers()) fcl = model.get_nodes_by_op_type("MVAU_hls")[0] op_inst = getCustomOp(fcl) - op_inst.set_nodeattr("mem_mode", "decoupled") + op_inst.set_nodeattr("mem_mode", "internal_decoupled") op_inst.set_nodeattr("runtime_writeable_weights", 1) old_weights = model.get_initializer(fcl.input[1]) op_inst.make_weight_file(old_weights, "decoupled_runtime", "old_weights.dat") diff --git a/tests/fpgadataflow/test_split_large_fifos.py b/tests/fpgadataflow/test_split_large_fifos.py index d4901c92ce..d192755d06 100644 --- a/tests/fpgadataflow/test_split_large_fifos.py +++ b/tests/fpgadataflow/test_split_large_fifos.py @@ -86,7 +86,6 @@ def test_split_large_fifos(depth, force_python_rtlsim): build_cfg.DataflowOutputType.STITCHED_IP, build_cfg.DataflowOutputType.RTLSIM_PERFORMANCE, ], - default_mem_mode=build_cfg.ComputeEngineMemMode.DECOUPLED, ) build.build_dataflow_cfg(tmp_output_dir + "/model.onnx", cfg) with open(tmp_output_dir + "/report/estimate_network_performance.json") as f: From 4b3737a670932bf31383f54eebe22f188e9ebbb2 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 6 Mar 2024 14:30:44 +0000 Subject: [PATCH 552/665] [NBs] Cleanup advanced builder nb and add placeholder for specialize layer explanation --- .../4_advanced_builder_settings.ipynb | 191 ++++++------------ .../3-build-accelerator-with-finn.ipynb | 2 +- 2 files changed, 60 insertions(+), 133 deletions(-) diff --git a/notebooks/advanced/4_advanced_builder_settings.ipynb b/notebooks/advanced/4_advanced_builder_settings.ipynb index e748d85a1c..d9db2c2bc1 100644 --- a/notebooks/advanced/4_advanced_builder_settings.ipynb +++ b/notebooks/advanced/4_advanced_builder_settings.ipynb @@ -9,7 +9,7 @@ "\n", "\"drawing\"\n", "\n", - "In this notebook, we'll use the FINN compiler to generate an FPGA accelerator with a streaming dataflow architecture from a small convolutional network trained on CIFAR-10. The key idea in streaming dataflow architectures is to parallelize across layers as well as within layers by dedicating a proportionate amount of compute resources to each layer, illustrated on the figure to the left. You can read more about the general concept in the [FINN](https://arxiv.org/pdf/1612.07119) and [FINN-R](https://dl.acm.org/doi/pdf/10.1145/3242897) papers. This is done by mapping each layer to a Vitis HLS description, parallelizing each layer's implementation to the appropriate degree and using on-chip FIFOs to link up the layers to create the full accelerator.\n", + "In this notebook, we'll use the FINN compiler to generate an FPGA accelerator with a streaming dataflow architecture from a small convolutional network trained on CIFAR-10. The key idea in streaming dataflow architectures is to parallelize across layers as well as within layers by dedicating a proportionate amount of compute resources to each layer, illustrated on the figure to the left. You can read more about the general concept in the [FINN](https://arxiv.org/pdf/1612.07119) and [FINN-R](https://dl.acm.org/doi/pdf/10.1145/3242897) papers. This is done by mapping each layer to a Vitis HLS or RTL description, parallelizing each layer's implementation to the appropriate degree and using on-chip FIFOs to link up the layers to create the full accelerator.\n", "These implementations offer a good balance of performance and flexibility, but building them by hand is difficult and time-consuming. This is where the FINN compiler comes in: it can build streaming dataflow accelerators from an ONNX description to match the desired throughput." ] }, @@ -32,9 +32,10 @@ "1. [Introduction to the CNV-w2a2 network](#intro_cnv)\n", "2. [Recap default builder flow](#recap_builder)\n", "3. [Build steps](#build_step)\n", - " 1. [How to make a custom build step](#custom_step)\n", - "4. [Folding configuration json](#folding_config)\n", - "5. [Additional builder arguments](#builder_arg)\n", + " 1. [How to create a custom build step](#custom_step)\n", + "4. [Specialize layers configuration json](#specialize_layers)\n", + "5. [Folding configuration json](#folding_config)\n", + "6. [Additional builder arguments](#builder_arg)\n", " 1. [Verification steps](#verify)\n", " 2. [Other builder arguments](#other_args)\n", " 3. [Examples for additional builder arguments & bitfile generation](#example_args)" @@ -198,7 +199,7 @@ "id": "d746eff3", "metadata": {}, "source": [ - "After each FINN builder step, the graph is saved as .onnx file. In the cell above we sort the intermediate models by time in descending order (`ls -t -r`) to visualize the builder flow. As you can see after the conversion to the FINN-ONNX format (`step_qonnx_to_finn`), the graph is prepared by tidy up and streamlining (`step_tidy_up` and `step_streamline`) and then the high level nodes are converted to HLS layers (`step_convert_to_hls`). Then there is a partition created from all layers that were converted to HLS layers (`step_create_dataflow_partition`), then optimizations are applied (`step_target_fps_parallelization`, `step_apply_folding_config` and `step_minimize_bit_width`). In the final step of this example we generate resource and performance reports for the network (`step_generate_estimate_reports`). Use the code below to investigate the network after each step." + "After each FINN builder step, the graph is saved as .onnx file. In the cell above we sort the intermediate models by time in descending order (`ls -t -r`) to visualize the builder flow. As you can see after the conversion to the FINN-ONNX format (`step_qonnx_to_finn`), the graph is prepared by tidy up and streamlining (`step_tidy_up` and `step_streamline`) and then the high level nodes are converted to HW abstraction layers (`step_convert_to_hw`). Then there is a partition created from all layers that were converted to HW layers (`step_create_dataflow_partition`), then we convert each of the HW abstraction layers into an HLS or RTL variant (`step_specialize_layers`). Afterwards optimizations are applied (`step_target_fps_parallelization`, `step_apply_folding_config` and `step_minimize_bit_width`). In the final step of this example we generate resource and performance reports for the network (`step_generate_estimate_reports`). Use the code below to investigate the network after each step." ] }, { @@ -217,7 +218,7 @@ "id": "bccebd0d", "metadata": {}, "source": [ - "The analysis of these .onnx files can help us identifying points in the flow in which we might need to intervene and provide the compiler with additional information. When investigating the network after the conversion to HLS layers, we can see that there are layers that were not converted. We can see this by clicking on the different nodes. HLS layers have the module `finn.custom_op.fpgadataflow`." + "The analysis of these .onnx files can help us identifying points in the flow in which we might need to intervene and provide the compiler with additional information. When investigating the network after the conversion to HW layers, we can see that there are layers that were not converted. We can see this by clicking on the different nodes. HW layers have the module `finn.custom_op.fpgadataflow`." ] }, { @@ -227,7 +228,7 @@ "metadata": {}, "outputs": [], "source": [ - "showInNetron(build_dir+\"/output_estimates_only/intermediate_models/step_convert_to_hls.onnx\")" + "showInNetron(build_dir+\"/output_estimates_only/intermediate_models/step_convert_to_hw.onnx\", localhost_url=\"xirxlabs60\")" ] }, { @@ -235,7 +236,7 @@ "id": "2719cc09", "metadata": {}, "source": [ - "As you can see in the graph, the first two nodes (a MultiThreshold and Transpose node) and the last two nodes (a Mul and Add node) are not converted into HLS layers. FINN currently only converts integer only operations into HLS layers, this means only when the input, output & weights are quantized to integer the node will be converted." + "As you can see in the graph, the first two nodes (a MultiThreshold and Transpose node) and the last two nodes (a Mul and Add node) are not converted into HW layers. FINN currently only converts integer only operations into HW layers, this means only when the input, output & weights are quantized to integer the node will be converted." ] }, { @@ -253,7 +254,7 @@ "id": "6e6d942e", "metadata": {}, "source": [ - "When we click on the `global_in` in the graph, we can see that the quantization annotation does not contain a data type. If no data type is set and it can not be derived from the preceeding node, the FINN compiler automatically assumes that the data type is floating point. This is why the first node does not get converted into an HLS layer, the input is assumed to be floating point." + "When we click on the `global_in` in the graph, we can see that the quantization annotation does not contain a data type. If no data type is set and it can not be derived from the preceeding node, the FINN compiler automatically assumes that the data type is floating point. This is why the first node does not get converted into an HW layer, the input is assumed to be floating point." ] }, { @@ -274,7 +275,7 @@ "Even though in the example of the CNVw2a2, the inputs are 32x32 RGB images, so the input values are 8 bit (UINT8) \"quantized\", the input to the exported model is floating point. For training in Brevitas, these values were normalized between 0 and 1.0 and so the exported model expects floating point values as input. \n", "This means we are in scenario 2. In the next section we will develop a custom step for the FINN builder flow to add preprocessing to our network.\n", "\n", - "But before we move to the next section, let's take a look at the last two nodes in the graph that were not converted to HLS layers." + "But before we move to the next section, let's take a look at the last two nodes in the graph that were not converted to HW layers." ] }, { @@ -368,7 +369,7 @@ "id": "e9c2c97f", "metadata": {}, "source": [ - "### How to make a custom build step " + "### How to create a custom build step " ] }, { @@ -439,8 +440,9 @@ " \"step_qonnx_to_finn\",\n", " \"step_tidy_up\",\n", " \"step_streamline\",\n", - " \"step_convert_to_hls\",\n", + " \"step_convert_to_hw\",\n", " \"step_create_dataflow_partition\",\n", + " \"step_specialize_layers\",\n", " \"step_target_fps_parallelization\",\n", " \"step_apply_folding_config\",\n", " \"step_minimize_bit_width\",\n", @@ -548,8 +550,9 @@ " \"step_qonnx_to_finn\",\n", " \"step_tidy_up\",\n", " \"step_streamline\",\n", - " \"step_convert_to_hls\",\n", + " \"step_convert_to_hw\",\n", " \"step_create_dataflow_partition\",\n", + " \"step_specialize_layers\",\n", " \"step_target_fps_parallelization\",\n", " \"step_apply_folding_config\",\n", " \"step_minimize_bit_width\",\n", @@ -614,7 +617,7 @@ "id": "5cc97505", "metadata": {}, "source": [ - "Let's have a look at the model after the conversion to hls, to verify that now all layers are correctly converted." + "Let's have a look at the model after the conversion to hw, to verify that now all layers are correctly converted." ] }, { @@ -624,7 +627,7 @@ "metadata": {}, "outputs": [], "source": [ - "showInNetron(build_dir+\"/output_pre_and_post_proc/intermediate_models/step_convert_to_hls.onnx\")" + "showInNetron(build_dir+\"/output_pre_and_post_proc/intermediate_models/step_convert_to_hw.onnx\")" ] }, { @@ -635,6 +638,14 @@ "The model contains now a `Thresholding` layer in the beginning and a `LabelSelect_Batch` layer at the end. Please note, that there is still a `Transpose` node as the first layer of the graph, but we can solve this by converting the input data to the NHWC format before streaming it into the FINN accelerator." ] }, + { + "cell_type": "markdown", + "id": "a6edf5c4-9213-45cd-834f-615c12685d9e", + "metadata": {}, + "source": [ + "## Specialize layers configuration json " + ] + }, { "cell_type": "markdown", "id": "5ffbadd1", @@ -648,7 +659,7 @@ "id": "c164040f", "metadata": {}, "source": [ - "The FINN compiler allows the user to implement a network in streaming dataflow architecture, this means every layer is implemented individually and the data is streamed through the accelerator. We can customize each layer for specific performance and resource requirements by adjusting the parallelism and resource type of each layer. In the FINN context we refer to this customization of parallelism in each layer as folding. To learn more details about the influence of folding factors/parallelism in FINN, please have a look at our [folding tutorial](3_folding.ipynb).\n", + "The FINN compiler allows the user to implement a network in streaming dataflow architecture, this means every layer is implemented individually and the data is streamed through the accelerator. We can customize each layer for specific performance and resource requirements by adjusting the parallelism and resource type of each layer. In the FINN context we refer to this customization of parallelism in each layer as folding. To learn more details about the influence of folding factors/parallelism in FINN, please have a look at our [folding tutorial](./3_folding.ipynb).\n", "\n", "In this section, we will look into the interface over which we can influence the customization of each layer using the FINN builder tool: A json file containing the folding configuration." ] @@ -683,7 +694,7 @@ "source": [ "As you can see from the printed cell above, the keys in the .json file are the node names of the layers in our network. For each of the layers, some node attributes are listed:\n", "* `PE` and `SIMD` are the folding parameters that determine the parallelism of each layer, depending on the layer they can be set to different values, for details refer to [this table](https://finn-dev.readthedocs.io/en/latest/internals.html#constraints-to-folding-factors-per-layer).\n", - "* `mem_mode`: determines if the parameter memory will be implemented as part of the HLS code (`const`) or instantiated separately and connected with the layer over a memory streamer unit (`decoupled`). You can find more details in this part of the documentation: https://finn-dev.readthedocs.io/en/latest/internals.html#matrixvectoractivation-mem-mode . It is also possible to set the mem_mode to external which allows for the implementation for external weights.\n", + "* `mem_mode`: determines if the parameter memory will be implemented as part of the HLS/RTL code (`const`) or instantiated separately and connected with the layer over a memory streamer unit (`decoupled`). You can find more details in this part of the documentation: https://finn-dev.readthedocs.io/en/latest/internals.html#matrixvectoractivation-mem-mode . It is also possible to set the mem_mode to external which allows for the implementation for external weights.\n", "* `ram_style`: when selecting `decoupled` mode, the FINN compiler allows us to choose which memory resource will be used for the layer. The argument `ram_style` is set to the selected memory type:\n", " * `auto`: Vivado will make the decision if the implementation is using LUTRAM or BRAM\n", " * `distributed`: LUTRAM will be used\n", @@ -795,8 +806,9 @@ " \"step_qonnx_to_finn\",\n", " \"step_tidy_up\",\n", " \"step_streamline\",\n", - " \"step_convert_to_hls\",\n", + " \"step_convert_to_hw\",\n", " \"step_create_dataflow_partition\",\n", + " \"step_specialize_layers\",\n", " \"step_apply_folding_config\",\n", " \"step_minimize_bit_width\",\n", " \"step_generate_estimate_reports\",\n", @@ -899,8 +911,9 @@ " \"step_qonnx_to_finn\",\n", " \"step_tidy_up\",\n", " \"step_streamline\",\n", - " \"step_convert_to_hls\",\n", + " \"step_convert_to_hw\",\n", " \"step_create_dataflow_partition\",\n", + " \"step_specialize_layers\",\n", " \"step_apply_folding_config\",\n", " \"step_minimize_bit_width\",\n", " \"step_generate_estimate_reports\",\n", @@ -937,7 +950,7 @@ "metadata": {}, "outputs": [], "source": [ - "showInNetron(build_dir+\"/output_all_bram/intermediate_models/step_generate_estimate_reports.onnx\")" + "showInNetron(build_dir+\"/output_all_bram/intermediate_models/step_generate_estimate_reports.onnx\", localhost_url=\"xirxlabs60\")" ] }, { @@ -958,7 +971,7 @@ "id": "97f87780", "metadata": {}, "source": [ - "The initial implementation already had a high utilization of BRAM, but the estimations went now up to 522 BRAMs while the LUT count went down to ~99k." + "The initial implementation already had a high utilization of BRAM, but the estimations went now up to ~500 BRAMs while the LUT count went down to ~99k." ] }, { @@ -1103,8 +1116,9 @@ " \"step_qonnx_to_finn\",\n", " \"step_tidy_up\",\n", " \"step_streamline\",\n", - " \"step_convert_to_hls\",\n", + " \"step_convert_to_hw\",\n", " \"step_create_dataflow_partition\",\n", + " \"step_specialize_layers\",\n", " \"step_target_fps_parallelization\",\n", " \"step_apply_folding_config\",\n", " \"step_minimize_bit_width\",\n", @@ -1239,7 +1253,7 @@ "source": [ "There are attributes that come from the dataclasses-json class: `to_dict`, `to_json`, `schema`, `from_json`, `from_dict`. This class is used for the implementation of the FINN builder. In this tutorial, we are mainly interested in the FINN specific arguments. \n", "\n", - "Some of these arguments we have seen already in the Cybersecurity notebook and in this notebook, e.g. target_fps, fpga_part and folding_config_file. In the code of the FINN builder, the function of each builder argument is documents, you can have a look [here](https://github.com/Xilinx/finn/blob/dev/src/finn/builder/build_dataflow_config.py#L155) and scroll through the available builder arguments." + "Some of these arguments we have seen already in the Cybersecurity notebook and in this notebook, e.g. `target_fps`, `fpga_part` and `folding_config_file`. In the code of the FINN builder, the function of each builder argument is documents, you can have a look [here](https://github.com/Xilinx/finn/blob/dev/src/finn/builder/build_dataflow_config.py#L155) and scroll through the available builder arguments." ] }, { @@ -1267,7 +1281,7 @@ "id": "b9bc5715", "metadata": {}, "source": [ - "You can see that after the generation of the estimate reports, the code generation and the ip generation is invoked (`step_hls_codegen` and `step_hls_ipgen`). The FIFO depths are determined and the FIFOs are inserted in the network (`step_set_fifo_depths`), we can then create an IP design of our whole network by stitching the IPs from each layer together (`step_create_stitched_ip`). At this point we have an implementation of the neural network that we can integrate within a bigger FPGA design, we can run performance measurements using simulation (`step_measure_rtlsim_performance`) and out-of-context synthesis (`step_out_of_context_synthesis`) for it.\n", + "You can see that after the generation of the estimate reports, the code generation and the ip generation is invoked (`step_hw_codegen` and `step_hw_ipgen`). The FIFO depths are determined and the FIFOs are inserted in the network (`step_set_fifo_depths`), we can then create an IP design of our whole network by stitching the IPs from each layer together (`step_create_stitched_ip`). At this point we have an implementation of the neural network that we can integrate within a bigger FPGA design, we can run performance measurements using simulation (`step_measure_rtlsim_performance`) and out-of-context synthesis (`step_out_of_context_synthesis`) for it.\n", "The FINN builder also provides automatic system integration for Zynq and Alveo devices, this can be invoked by running `step_synthesize_bitfile`, `step_make_pynq_driver` and `step_deployment_package`." ] }, @@ -1287,7 +1301,7 @@ "outputs": [], "source": [ "import finn.builder.build_dataflow_steps as build_dataflow_steps\n", - "print(build_dataflow_steps.step_hls_codegen.__doc__)" + "print(build_dataflow_steps.step_hw_codegen.__doc__)" ] }, { @@ -1297,7 +1311,7 @@ "metadata": {}, "outputs": [], "source": [ - "showSrc(build_dataflow_steps.step_hls_codegen)" + "showSrc(build_dataflow_steps.step_hw_codegen)" ] }, { @@ -1313,7 +1327,7 @@ "id": "3b98eb65", "metadata": {}, "source": [ - "### Examples for additional builder arguments & bitfile generation " + "### Example for additional builder arguments & bitfile generation " ] }, { @@ -1334,7 +1348,7 @@ "* A matrix multiplication\n", "* A MultiThreshold operation\n", "\n", - "When converting these nodes into HLS layers, by default the MatMul and the MultiThreshold gets converted into **one** component called Matrix-Vector-Activation Unit (MVAU). But the FINN compiler allows us to implement the activation separately. This gives an additional possibility for customization because we can adjust the folding parameters of the standalone threshold unit independently. \n", + "When converting these nodes into HW layers, by default the MatMul and the MultiThreshold gets converted into **one** component called Matrix-Vector-Activation Unit (MVAU). But the FINN compiler allows us to implement the activation separately. This gives an additional possibility for customization because we can adjust the folding parameters of the standalone threshold unit independently. \n", "\n", "If you would like to enable this feature, you can set the build argument `standalone_thresholds` to `True`. In the code below this feature is enabled and you can have a look at the generated .onnx file. Please note that you need to uncomment the code first." ] @@ -1365,8 +1379,9 @@ " \"step_qonnx_to_finn\",\n", " \"step_tidy_up\",\n", " \"step_streamline\",\n", - " \"step_convert_to_hls\",\n", + " \"step_convert_to_hw\",\n", " \"step_create_dataflow_partition\",\n", + " \"step_specialize_layers\",\n", " \"step_target_fps_parallelization\",\n", " \"step_apply_folding_config\",\n", " \"step_minimize_bit_width\",\n", @@ -1408,103 +1423,6 @@ "#showInNetron(build_dir+\"/output_standalone_thresholds/intermediate_models/step_generate_estimate_reports.onnx\")" ] }, - { - "cell_type": "markdown", - "id": "074d8253", - "metadata": {}, - "source": [ - "#### RTL Convolutional Input Generator" - ] - }, - { - "cell_type": "markdown", - "id": "b85e5ac7", - "metadata": {}, - "source": [ - "Recently, we have worked on the *Operator Hardening* in the FINN compiler. This means that we implement core building blocks in RTL instead of using HLS.\n", - "One of these components is already available in the FINN compiler, you can enable the RTL implementation of the ConvolutionInputGenerator (aka Sliding Window Generator) by setting the build argument `force_rtl_conv_inp_gen` to `True`.\n", - "In the code below this feature is enabled and you can have a look at the generated .onnx file. Please note that you need to uncomment the code first." - ] - }, - { - "cell_type": "markdown", - "id": "2a90b63f", - "metadata": {}, - "source": [ - "
    \n", - "Important notice: We are actively working on the integration of RTL components in the FINN flow, the enablement like shown below might change in the future.\n", - "
    " - ] - }, - { - "cell_type": "code", - "execution_count": null, - "id": "ab0c4974", - "metadata": {}, - "outputs": [], - "source": [ - "## Build flow with additional builder arguments enabled\n", - "## force_rtl_conv_inp_gen = True\n", - "\n", - "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/advanced\"\n", - "model_file = model_dir + \"/end2end_cnv_w2a2_export.onnx\"\n", - "\n", - "output_dir = build_dir + \"/output_rtl_swg\"\n", - "\n", - "#Delete previous run results if exist\n", - "if os.path.exists(output_dir):\n", - " shutil.rmtree(output_dir)\n", - " print(\"Previous run results deleted!\")\n", - "\n", - "build_steps = [\n", - " custom_step_add_pre_proc,\n", - " custom_step_add_post_proc,\n", - " \"step_qonnx_to_finn\",\n", - " \"step_tidy_up\",\n", - " \"step_streamline\",\n", - " \"step_convert_to_hls\",\n", - " \"step_create_dataflow_partition\",\n", - " \"step_target_fps_parallelization\",\n", - " \"step_apply_folding_config\",\n", - " \"step_minimize_bit_width\",\n", - " \"step_generate_estimate_reports\",\n", - "]\n", - "\n", - "cfg_estimates = build.DataflowBuildConfig(\n", - " output_dir = output_dir,\n", - " mvau_wwidth_max = 80,\n", - " target_fps = 10000,\n", - " synth_clk_period_ns = 10.0,\n", - " fpga_part = \"xc7z020clg400-1\",\n", - " force_rtl_conv_inp_gen = True,\n", - " steps = build_steps,\n", - " generate_outputs=[\n", - " build_cfg.DataflowOutputType.ESTIMATE_REPORTS,\n", - " ],\n", - ")" - ] - }, - { - "cell_type": "code", - "execution_count": null, - "id": "19fe4d85", - "metadata": {}, - "outputs": [], - "source": [ - "#%%time\n", - "#build.build_dataflow_cfg(model_file, cfg_estimates);" - ] - }, - { - "cell_type": "code", - "execution_count": null, - "id": "4c1f1ce9", - "metadata": {}, - "outputs": [], - "source": [ - "#showInNetron(build_dir+\"/output_rtl_swg/intermediate_models/step_generate_estimate_reports.onnx\")" - ] - }, { "cell_type": "markdown", "id": "601eb5f8", @@ -1569,14 +1487,15 @@ " \"step_qonnx_to_finn\",\n", " \"step_tidy_up\",\n", " \"step_streamline\",\n", - " \"step_convert_to_hls\",\n", + " \"step_convert_to_hw\",\n", " \"step_create_dataflow_partition\",\n", + " \"step_specialize_layers\",\n", " \"step_target_fps_parallelization\",\n", " \"step_apply_folding_config\",\n", " \"step_minimize_bit_width\",\n", " \"step_generate_estimate_reports\",\n", - " \"step_hls_codegen\",\n", - " \"step_hls_ipgen\",\n", + " \"step_hw_codegen\",\n", + " \"step_hw_ipgen\",\n", " \"step_set_fifo_depths\",\n", " \"step_create_stitched_ip\",\n", " \"step_measure_rtlsim_performance\",\n", @@ -1613,9 +1532,17 @@ "metadata": {}, "outputs": [], "source": [ - "#%%time\n", - "#build.build_dataflow_cfg(model_file, cfg_build);" + "%%time\n", + "build.build_dataflow_cfg(model_file, cfg_build);" ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "3eccb045-13b8-410b-bfcb-9e9c7146a1b4", + "metadata": {}, + "outputs": [], + "source": [] } ], "metadata": { @@ -1634,7 +1561,7 @@ "name": "python", "nbconvert_exporter": "python", "pygments_lexer": "ipython3", - "version": "3.10.6" + "version": "3.10.12" } }, "nbformat": 4, diff --git a/notebooks/end2end_example/cybersecurity/3-build-accelerator-with-finn.ipynb b/notebooks/end2end_example/cybersecurity/3-build-accelerator-with-finn.ipynb index 5e8bff3e04..73cd25cf20 100644 --- a/notebooks/end2end_example/cybersecurity/3-build-accelerator-with-finn.ipynb +++ b/notebooks/end2end_example/cybersecurity/3-build-accelerator-with-finn.ipynb @@ -265,7 +265,7 @@ "\n", "**Live FINN tutorial:** These next builds will take about 10 minutes to complete since multiple calls to Vivado and a call to RTL simulation are involved. While this is running, you can examine the generated files with noVNC -- it is running on **(your AWS URL):6080/vnc.html**\n", "\n", - "* Once the `step_hls_codegen [8/16]` below is completed, you can view the generated HLS code under its own folder for each layer: `/tmp/finn_dev_ubuntu/code_gen_ipgen_MatrixVectorActivation_XXXXXX`\n", + "* Once the `step_hls_codegen [8/16]` below is completed, you can view the generated HLS code under its own folder for each layer: `/tmp/finn_dev_ubuntu/code_gen_ipgen_MVAU_hls_XXXXXX`\n", " \n", "* Once the `step_create_stitched_ip [11/16]` below is completed, you can view the generated stitched IP in Vivado under `/home/ubuntu/finn/notebooks/end2end_example/cybersecurity/output_ipstitch_ooc_rtlsim/stitched_ip`\n", " " From c79f364243bd5d2346b413589c1e7a078b6f99df Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Wed, 6 Mar 2024 15:51:04 +0000 Subject: [PATCH 553/665] [Threshold RTL] Remove redundent functions Signed-off-by: aziz bahri --- .../fpgadataflow/rtl/thresholding_rtl.py | 1 - src/finn/util/basic.py | 20 ------------------- 2 files changed, 21 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py index ee101b1cc8..a7161a59bb 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py @@ -37,7 +37,6 @@ from finn.custom_op.fpgadataflow.rtlbackend import RTLBackend from finn.custom_op.fpgadataflow.thresholding import Thresholding from finn.util.basic import ( - find_next_power_of_2, get_memutil_alternatives, get_rtlsim_trace_depth, make_build_dir, diff --git a/src/finn/util/basic.py b/src/finn/util/basic.py index 10edb7dc54..a80abfc876 100644 --- a/src/finn/util/basic.py +++ b/src/finn/util/basic.py @@ -235,26 +235,6 @@ def is_exe(fpath): return None - -def find_next_power_of_2(n): - """For any integer 'n', find the next greatest power of 2""" - # Negative values will loop infinitely below - return 0 - if n <= 0: - return 0 - # If '1' is requested, output will be '0' in the loop below, avoid this now. - elif n == 1: - return 2 # i.e. 2**1 - - # decrement 'n' (to handle cases when `n` itself is a power of 2) - n = n - 1 - - # loop until only one bit is left - while n & n - 1: - # unset rightmost bit - n = n & n - 1 - return n << 1 - - mem_primitives_versal = { "URAM_72x4096": (72, 4096), "URAM_36x8192": (36, 8192), From 999ed82c4857fbfd0f963437fe22b0f1f7823b87 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Wed, 6 Mar 2024 23:23:38 +0000 Subject: [PATCH 554/665] [mvau]: renamed method to more generic name --- src/finn/custom_op/fpgadataflow/matrixvectoractivation.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index dc713c8b42..138cd9f3ad 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -476,7 +476,7 @@ def minimize_accumulator_width(self, model): # if the thresholds can be used to determine range, then adjust the range # according to the known values of the thresholds if thresholds is not None: - threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds) + threshold_tensor = self.get_hw_compatible_threshold_tensor(thresholds) # set threshold datatype (and accumulator datatype implicitly) min_threshold = thresholds.min() max_threshold = thresholds.max() @@ -485,7 +485,7 @@ def minimize_accumulator_width(self, model): warnings.warn("Clipping some thresholds in %s" % self.onnx_node.name) thresholds = np.clip(thresholds, acc_min, acc_max) model.set_initializer(self.onnx_node.input[2], thresholds) - threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds) + threshold_tensor = self.get_hw_compatible_threshold_tensor(thresholds) min_threshold = thresholds.min() max_threshold = thresholds.max() acc_min = min(min_threshold, acc_min) @@ -762,7 +762,7 @@ def generate_params(self, model, path): if len(self.onnx_node.input) > 2: thresholds = model.get_initializer(self.onnx_node.input[2]) if thresholds is not None: - threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds) + threshold_tensor = self.get_hw_compatible_threshold_tensor(thresholds) # use UINT32 threshold export for bipolar times bipolar inp_is_bipolar = self.get_input_datatype() == DataType["BIPOLAR"] wt_is_bipolar = self.get_weight_datatype() == DataType["BIPOLAR"] From 209b81ce767763d2c34a8c109e7435e2d75fc791 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Wed, 6 Mar 2024 23:24:23 +0000 Subject: [PATCH 555/665] [rtl mvau]: add CPPsim functionality (fall back to MVAU exec) --- .../rtl/matrixvectoractivation_rtl.py | 117 ++++++++---------- 1 file changed, 55 insertions(+), 62 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py index ae04b003bd..425d1b4e15 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py @@ -68,9 +68,63 @@ def execute_node(self, context, graph): node = self.onnx_node if mode == "cppsim": - raise Exception("cppsim not possible for RTL MVAU, please set exec_mode to rtlsim") + MVAU.execute_node(self, context, graph) elif mode == "rtlsim": code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + # create a npy file fore each input of the node (in_ind is input index) + in_ind = 0 + for inputs in node.input: + # it is assumed that the first input of the node is the data input + # the second input are the weights + if in_ind == 0: + assert ( + str(context[inputs].dtype) == "float32" + ), """Input datatype is + not float32 as expected.""" + expected_inp_shape = self.get_folded_input_shape() + reshaped_input = context[inputs].reshape(expected_inp_shape) + export_idt = self.get_input_datatype() + # make copy before saving the array + reshaped_input = reshaped_input.copy() + np.save( + os.path.join(code_gen_dir, "input_{}.npy".format(in_ind)), + reshaped_input, + ) + elif in_ind > 2: + raise Exception("Unexpected input found for MatrixVectorActivation_rtl") + in_ind += 1 + + sim = self.get_rtlsim() + nbits = self.get_instream_width() + inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) + reset_rtlsim(sim) + toggle_clk(sim) + if mem_mode in ["external", "decoupled"]: + wnbits = self.get_weightstream_width() + export_wdt = self.get_weight_datatype() + wei = npy_to_rtlsim_input( + "{}/weights.npy".format(code_gen_dir), export_wdt, wnbits + ) + num_w_reps = np.prod(self.get_nodeattr("numInputVectors")) + io_dict = { + "inputs": {"in0": inp, "weights": wei * num_w_reps}, + "outputs": {"out": []}, + } + self.rtlsim_multi_io(sim, io_dict) + output = io_dict["outputs"]["out"] + else: + output = self.rtlsim(sim, inp) + odt = self.get_output_datatype() + target_bits = odt.bitwidth() + packed_bits = self.get_outstream_width() + out_npy_path = "{}/output.npy".format(code_gen_dir) + out_shape = self.get_folded_output_shape() + rtlsim_output_to_npy(output, out_npy_path, odt, out_shape, packed_bits, target_bits) + # load and reshape output + output = np.load(out_npy_path) + oshape = self.get_normal_output_shape() + output = np.asarray([output], dtype=np.float32).reshape(*oshape) + context[node.output[0]] = output else: raise Exception( """Invalid value for attribute exec_mode! Is currently set to: {} @@ -79,67 +133,6 @@ def execute_node(self, context, graph): ) ) - # create a npy file fore each input of the node (in_ind is input index) - in_ind = 0 - for inputs in node.input: - # it is assumed that the first input of the node is the data input - # the second input are the weights - if in_ind == 0: - assert ( - str(context[inputs].dtype) == "float32" - ), """Input datatype is - not float32 as expected.""" - expected_inp_shape = self.get_folded_input_shape() - reshaped_input = context[inputs].reshape(expected_inp_shape) - export_idt = self.get_input_datatype() - # make copy before saving the array - reshaped_input = reshaped_input.copy() - np.save( - os.path.join(code_gen_dir, "input_{}.npy".format(in_ind)), - reshaped_input, - ) - elif in_ind > 2: - raise Exception("Unexpected input found for MatrixVectorActivation_rtl") - in_ind += 1 - - if mode == "rtlsim": - sim = self.get_rtlsim() - nbits = self.get_instream_width() - inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) - reset_rtlsim(sim) - toggle_clk(sim) - if mem_mode in ["external", "decoupled"]: - wnbits = self.get_weightstream_width() - export_wdt = self.get_weight_datatype() - wei = npy_to_rtlsim_input("{}/weights.npy".format(code_gen_dir), export_wdt, wnbits) - num_w_reps = np.prod(self.get_nodeattr("numInputVectors")) - io_dict = { - "inputs": {"in0": inp, "weights": wei * num_w_reps}, - "outputs": {"out": []}, - } - self.rtlsim_multi_io(sim, io_dict) - output = io_dict["outputs"]["out"] - else: - output = self.rtlsim(sim, inp) - odt = self.get_output_datatype() - target_bits = odt.bitwidth() - packed_bits = self.get_outstream_width() - out_npy_path = "{}/output.npy".format(code_gen_dir) - out_shape = self.get_folded_output_shape() - rtlsim_output_to_npy(output, out_npy_path, odt, out_shape, packed_bits, target_bits) - # load and reshape output - output = np.load(out_npy_path) - oshape = self.get_normal_output_shape() - output = np.asarray([output], dtype=np.float32).reshape(*oshape) - context[node.output[0]] = output - else: - raise Exception( - """Invalid value for attribute exec_mode! Is currently set to: {} - has to be set to "rtlsim" """.format( - mode - ) - ) - def lut_estimation(self): return 0 From 0f216a7455978ea83eb961a0c2f06726a05b7959 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Wed, 6 Mar 2024 23:28:27 +0000 Subject: [PATCH 556/665] [specialize layers]: minor bugfix and removed VVU-related support --- .../fpgadataflow/specialize_layers.py | 42 +++++-------------- 1 file changed, 10 insertions(+), 32 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/specialize_layers.py b/src/finn/transformation/fpgadataflow/specialize_layers.py index 4027b0c949..191d84a8d3 100644 --- a/src/finn/transformation/fpgadataflow/specialize_layers.py +++ b/src/finn/transformation/fpgadataflow/specialize_layers.py @@ -26,7 +26,6 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import numpy as np import warnings from onnx import helper from qonnx.core.datatype import DataType @@ -35,7 +34,6 @@ from finn.custom_op.fpgadataflow.hls import custom_op as hls_variants from finn.custom_op.fpgadataflow.rtl import custom_op as rtl_variants -from finn.util.fpgadataflow import is_versal def _determine_impl_style(node, fpgapart=""): @@ -55,10 +53,10 @@ def _determine_impl_style(node, fpgapart=""): if optype == "StreamingDataWidthConverter": return _dwc_determine_impl_style(node) if rtl_variant: - impl_style = "rtl" + return "rtl" # but if no rtl variant, set impl_style to hls elif hls_variant: - impl_style = "hls" + return "hls" # if there is neither an rtl nor hls variant # throw error else: @@ -126,15 +124,6 @@ def _determine_impl_style(node, fpgapart=""): node.name, ) warnings.warn(warn_str) - elif optype == "VectorVectorActivation": - if _vvu_rtl_possible(node, fpgapart): - return "rtl" - else: - warn_str = """There is no RTL variant for %s. The node will automatically be - set to HLS variant.""" % ( - node.name, - ) - warnings.warn(warn_str) if rtl_variant: return "rtl" @@ -221,27 +210,16 @@ def _mvu_rtl_possible(n): folding_supported = ( getCustomOp(n).get_nodeattr("MH") % getCustomOp(n).get_nodeattr("PE") == 0 ) and (getCustomOp(n).get_nodeattr("MW") % getCustomOp(n).get_nodeattr("SIMD") == 0) + targets_dsp = getCustomOp(n).get_nodeattr("resType") in ["dsp", "auto"] + external_memmode = getCustomOp(n).get_nodeattr("mem_mode") in ["decoupled", "external"] - return act_width_in_range and weight_width_in_range and folding_supported - - -def _vvu_rtl_possible(n, fpgapart): - # Checks whether RTL-based VVU is supported - act_width_in_range = ( - DataType[getCustomOp(n).get_nodeattr("inputDataType")].bitwidth() <= 8 - ) or ( - DataType[getCustomOp(n).get_nodeattr("inputDataType")].bitwidth() == 9 - and DataType[getCustomOp(n).get_nodeattr("inputDataType")].min() < 0 + return ( + act_width_in_range + and weight_width_in_range + and folding_supported + and targets_dsp + and external_memmode ) - weight_width_in_range = DataType[getCustomOp(n).get_nodeattr("weightDataType")].bitwidth() <= 8 - folding_supported = ( - getCustomOp(n).get_nodeattr("Channels") % getCustomOp(n).get_nodeattr("PE") == 0 - ) and ( - np.prod(getCustomOp(n).get_nodeattr("Kernel")) % getCustomOp(n).get_nodeattr("SIMD") == 0 - ) - is_versal_family = is_versal(fpgapart) - - return act_width_in_range and weight_width_in_range and folding_supported and is_versal_family class SpecializeLayers(Transformation): From dd0369c3752b04262a4b5a880558cb1f2b79a10f Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Wed, 6 Mar 2024 23:30:11 +0000 Subject: [PATCH 557/665] [test]: added RTL-MVAU CPPsim test --- tests/fpgadataflow/test_fpgadataflow_mvau.py | 22 +++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_mvau.py b/tests/fpgadataflow/test_fpgadataflow_mvau.py index 32edf36365..03f1293b74 100644 --- a/tests/fpgadataflow/test_fpgadataflow_mvau.py +++ b/tests/fpgadataflow/test_fpgadataflow_mvau.py @@ -654,10 +654,14 @@ def test_fpgadataflow_rtl_mvau(mh, mw, pe, simd, idt, wdt, part, clk_ns): model = model.transform(to_hw.InferQuantizedMatrixVectorActivation(mem_mode="decoupled")) model = model.transform(GiveUniqueNodeNames()) + # Apply convert-to-rtl step + model = model.transform(SpecializeLayers(part)) + model = model.transform(GiveUniqueNodeNames()) + # Apply folding (i.e. specify to use DSPs) folding_config = { "Defaults": {}, - "MVAU_0": { + "MVAU_rtl_0": { "PE": pe, "SIMD": simd, "mem_mode": "decoupled", @@ -671,9 +675,16 @@ def test_fpgadataflow_rtl_mvau(mh, mw, pe, simd, idt, wdt, part, clk_ns): # make sure the changed datatypes are propagated through the network model = model.transform(InferDataTypes()) - # Apply convert-to-rtl step - model = model.transform(SpecializeLayers(part)) - model = model.transform(GiveUniqueNodeNames()) + # Run CPPsim + model = model.transform(SetExecMode("cppsim")) + model = model.transform(PrepareCppSim()) + model = model.transform(CompileCppSim()) + output_mvau_hls = oxe.execute_onnx(model, input_dict)["global_out"] + assert ( + output_matmul == output_mvau_hls + ).all(), "Output of ONNX model not matching output of node-by-node CPPsim!" + + # Run node-by-node RTLsim model = model.transform(SetExecMode("rtlsim")) model = model.transform(PrepareIP(part, clk_ns)) model = model.transform(HLSSynthIP()) @@ -682,8 +693,9 @@ def test_fpgadataflow_rtl_mvau(mh, mw, pe, simd, idt, wdt, part, clk_ns): assert ( output_matmul == output_mvau_rtl - ).all(), "Output of ONNX model not matching output of node-by-node sim!" + ).all(), "Output of ONNX model not matching output of node-by-node RTLsim!" + # Run stitched-ip RTLsim model = model.transform(InsertAndSetFIFODepths(part, clk_ns)) model = model.transform(PrepareIP(part, clk_ns)) model = model.transform(HLSSynthIP()) From 41b76150ff9402e751d2cf3d17f8fc8956ec488e Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Thu, 7 Mar 2024 09:04:25 +0000 Subject: [PATCH 558/665] [tests] remove util test --- tests/util/test_basic.py | 60 ---------------------------------------- 1 file changed, 60 deletions(-) delete mode 100755 tests/util/test_basic.py diff --git a/tests/util/test_basic.py b/tests/util/test_basic.py deleted file mode 100755 index 97a8c50261..0000000000 --- a/tests/util/test_basic.py +++ /dev/null @@ -1,60 +0,0 @@ -# Copyright (C) 2023, Advanced Micro Devices, Inc. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# * Redistributions of source code must retain the above copyright notice, this -# list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# * Neither the name of FINN nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -import pytest - -import finn.util.basic as basic - - -@pytest.mark.util -def test_next_power_of_2(): - test_vector = [ - {"input": -2, "expected_result": 0}, - {"input": -1, "expected_result": 0}, - {"input": 0, "expected_result": 0}, - {"input": 1, "expected_result": 2}, - {"input": 2, "expected_result": 2}, - {"input": 3, "expected_result": 4}, - {"input": 4, "expected_result": 4}, - {"input": 7, "expected_result": 8}, - {"input": 8, "expected_result": 8}, - {"input": 11, "expected_result": 16}, - {"input": 15, "expected_result": 16}, - {"input": 16, "expected_result": 16}, - {"input": 18, "expected_result": 32}, - {"input": 27, "expected_result": 32}, - {"input": 31, "expected_result": 32}, - {"input": 32, "expected_result": 32}, - {"input": 42, "expected_result": 64}, - {"input": 65, "expected_result": 128}, - ] - - for test_dict in test_vector: - output = basic.find_next_power_of_2(test_dict["input"]) - assert output >= test_dict["input"] - assert output == test_dict["expected_result"] From 216cb0d549467c9856083fa97ff694adb6871890 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Thu, 7 Mar 2024 14:49:09 +0000 Subject: [PATCH 559/665] [tests] Dont skip BIPOLAR test for thresholding Signed-off-by: aziz bahri --- .../fpgadataflow/convert_to_hw_layers.py | 10 +++++++--- tests/fpgadataflow/test_convert_to_hw_thresholding.py | 8 -------- 2 files changed, 7 insertions(+), 11 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py index fdb892e911..c1d7dbc298 100644 --- a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py +++ b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py @@ -236,9 +236,13 @@ def apply(self, model): node.name + ": MultiThreshold out_bias must be integer for HLS conversion." ) actval = int(actval) - assert (not odt.signed()) or (actval < 0), ( - node.name + ": Signed output requires actval < 0" - ) + + # a signed activation should always have a negative bias, + # but BIPOLAR uses the -1 as 0 encoding so the assert does not apply + if odt != "BIPOLAR": + assert (not odt.signed()) or (actval < 0), ( + node.name + ": Signed output requires actval < 0" + ) new_node = helper.make_node( "Thresholding", diff --git a/tests/fpgadataflow/test_convert_to_hw_thresholding.py b/tests/fpgadataflow/test_convert_to_hw_thresholding.py index 9d44702152..ef08d87846 100755 --- a/tests/fpgadataflow/test_convert_to_hw_thresholding.py +++ b/tests/fpgadataflow/test_convert_to_hw_thresholding.py @@ -144,14 +144,6 @@ def test_convert_multithreshold_to_hardware( pe = generate_pe_value(fold, num_input_channels) num_steps = activation.get_num_possible_values() - 1 - # See convert_to_hw_layers::InferThresholdingLayer: - # assert (not odt.signed()) or (actval < 0) - # This implies that it expects a negative activation, BIPOLAR does not provide that - if activation == DataType["BIPOLAR"]: - pytest.skip( - "Only negative activations are supported for " "RTL Thresholding Binary Search node" - ) - # Other non-input parameters num_input_vecs = [1, 2, 2] output_data_type = activation From 00147454b4e2812d29c09d6eee89906bd8afd9cf Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Thu, 7 Mar 2024 15:01:48 +0000 Subject: [PATCH 560/665] [Thresholding] bipolar type do not require negative activation Signed-off-by: aziz bahri --- src/finn/transformation/fpgadataflow/convert_to_hw_layers.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py index c1d7dbc298..27f257b917 100644 --- a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py +++ b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py @@ -239,7 +239,7 @@ def apply(self, model): # a signed activation should always have a negative bias, # but BIPOLAR uses the -1 as 0 encoding so the assert does not apply - if odt != "BIPOLAR": + if odt != DataType["BIPOLAR"]: assert (not odt.signed()) or (actval < 0), ( node.name + ": Signed output requires actval < 0" ) From 95b51bad6cc1ffe423e0f1ae1cb5509a1a35b1b2 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Thu, 7 Mar 2024 15:14:34 +0000 Subject: [PATCH 561/665] [refactor] linting --- .../fpgadataflow/rtl/thresholding_rtl.py | 37 ++++++++++--------- src/finn/util/basic.py | 1 + .../test_convert_to_hw_thresholding.py | 12 ++++-- .../test_fpgadataflow_thresholding.py | 4 +- 4 files changed, 30 insertions(+), 24 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py index a7161a59bb..f30a305dfe 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py @@ -79,20 +79,21 @@ def get_nodeattr_types(self): return my_attrs def get_pe_mem_geometries(self): - ''' return a list of (bitwidth, depth) for PE memory configurations to be used in resource estimation - - for each bitwidth, the depth is calculated as the - number of thresholds that can be stored in a single - memory block - the bitwidth is the bitwidth of the threshold values - the depth is the number of thresholds that can be stored - in a single memory block - the number of memory blocks is calculated as the number - of thresholds divided by the depth - the number of memory blocks is then multiplied by the - number of PEs to get the total number of memory blocks - required for the entire layer - ''' + """return a list of (bitwidth, depth) for PE memory configurations to be used + in resource estimation + + for each bitwidth, the depth is calculated as the + number of thresholds that can be stored in a single + memory block + the bitwidth is the bitwidth of the threshold values + the depth is the number of thresholds that can be stored + in a single memory block + the number of memory blocks is calculated as the number + of thresholds divided by the depth + the number of memory blocks is then multiplied by the + number of PEs to get the total number of memory blocks + required for the entire layer + """ pe = self.get_nodeattr("PE") wdt = self.get_weight_datatype() wdt_bits = wdt.bitwidth() @@ -108,7 +109,7 @@ def get_pe_mem_geometries(self): return ret def get_memory_estimate(self): - ''' return the memory estimate for this node ''' + """return the memory estimate for this node""" res_dict = {} depth_trigger_bram = self.get_nodeattr("depth_trigger_bram") depth_trigger_uram = self.get_nodeattr("depth_trigger_uram") @@ -130,17 +131,17 @@ def get_memory_estimate(self): return res_dict def bram_estimation(self): - ''' return the number of BRAMs required for this node ''' + """return the number of BRAMs required for this node""" res_dict = self.get_memory_estimate() return res_dict.get("BRAM", 0) def uram_estimation(self): - ''' return the number of URAMs required for this node ''' + """return the number of URAMs required for this node""" res_dict = self.get_memory_estimate() return res_dict.get("URAM", 0) def lut_estimation(self): - ''' return the number of LUTs required for this node ''' + """return the number of LUTs required for this node""" res_dict = self.get_memory_estimate() return res_dict.get("LUTRAM", 0) diff --git a/src/finn/util/basic.py b/src/finn/util/basic.py index a80abfc876..1995d9f06a 100644 --- a/src/finn/util/basic.py +++ b/src/finn/util/basic.py @@ -235,6 +235,7 @@ def is_exe(fpath): return None + mem_primitives_versal = { "URAM_72x4096": (72, 4096), "URAM_36x8192": (36, 8192), diff --git a/tests/fpgadataflow/test_convert_to_hw_thresholding.py b/tests/fpgadataflow/test_convert_to_hw_thresholding.py index ef08d87846..63cb5986e1 100755 --- a/tests/fpgadataflow/test_convert_to_hw_thresholding.py +++ b/tests/fpgadataflow/test_convert_to_hw_thresholding.py @@ -32,15 +32,16 @@ from onnx import TensorProto, helper from qonnx.core.datatype import DataType from qonnx.core.modelwrapper import ModelWrapper +from qonnx.custom_op.general.multithreshold import multithreshold from qonnx.custom_op.registry import getCustomOp from qonnx.transformation.general import GiveUniqueNodeNames from qonnx.transformation.infer_datatypes import InferDataTypes from qonnx.transformation.infer_shapes import InferShapes from qonnx.util.basic import gen_finn_dt_tensor -from qonnx.custom_op.general.multithreshold import multithreshold + +import finn.core.onnx_exec as oxe from finn.transformation.fpgadataflow.convert_to_hw_layers import InferThresholdingLayer from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers -import finn.core.onnx_exec as oxe test_fpga_part = "xczu3eg-sbva484-1-e" target_clk_ns = 5 @@ -50,19 +51,23 @@ def sort_thresholds_increasing(thresholds): return np.sort(thresholds, axis=1) + def prepare_inputs(input_tensor): return {"inp": input_tensor} + # n = batch, c = channel, h = height, w = width of feature map # Standard = NCHW; FINN = NHWC # Convert from NHWC(FINN) to NCHW(Standard) def layout_FINN2NCHW(data): return np.transpose(data, (0, 3, 1, 2)) + # Convert from NCHW(Standard) to NHWC(FINN) def layout_NCHW2FINN(data): return np.transpose(data, (0, 2, 3, 1)) + def generate_random_threshold_values(input_data_type, num_input_channels, num_steps): return np.random.randint( input_data_type.min(), @@ -190,7 +195,8 @@ def test_convert_multithreshold_to_hardware( assert (y_produced == y_expected).all() - # Transform to the specified implementation style, either the RTL or HLS according to test parameters + # Transform to the specified implementation style, either the + # RTL or HLS according to test parameters node = model.get_nodes_by_op_type(model.graph.node[0].op_type)[0] inst = getCustomOp(node) inst.set_nodeattr("preferred_impl_style", impl_style) diff --git a/tests/fpgadataflow/test_fpgadataflow_thresholding.py b/tests/fpgadataflow/test_fpgadataflow_thresholding.py index 2a316e6c1b..fc3996ddab 100644 --- a/tests/fpgadataflow/test_fpgadataflow_thresholding.py +++ b/tests/fpgadataflow/test_fpgadataflow_thresholding.py @@ -81,9 +81,7 @@ def layout_NCHW2FINN(data): return np.transpose(data, (0, 2, 3, 1)) -def make_single_thresholding_modelwrapper( - impl_style, T, idt, odt, actval, n_inp_vecs -): +def make_single_thresholding_modelwrapper(impl_style, T, idt, odt, actval, n_inp_vecs): NumChannels = T.shape[0] inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, n_inp_vecs + [NumChannels]) From 0d240f63b378f64a205a5d0b1bdf8ebe65d4e07d Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Thu, 7 Mar 2024 15:26:04 +0000 Subject: [PATCH 562/665] [rtl mvau]: added methods related to RTL file retrieval and corrected DSP estimations --- .../rtl/matrixvectoractivation_rtl.py | 31 ++++++++++++------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py index 425d1b4e15..4f17aab5fd 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py @@ -139,17 +139,11 @@ def lut_estimation(self): def dsp_estimation(self): # multiplication P = self.get_nodeattr("PE") - res_type = self.get_nodeattr("resType") Q = self.get_nodeattr("SIMD") - wdt = self.get_weight_datatype() - W = wdt.bitwidth() - idt = self.get_input_datatype() - A = idt.bitwidth() - if res_type == "dsp": - mult_dsp = P * Q * np.ceil((W + A) / 48) # TODO: more accurate modelling - else: - mult_dsp = 0 - return int(mult_dsp) + dsp_res = {} + dsp_res["DSP48"] = np.ceil(P / 4) * Q + dsp_res["DSP58"] = P * np.ceil(Q / 3) + return dsp_res def code_generation_ipgen(self, model, fpgapart, clk): self.generate_hdl(model, fpgapart, clk) @@ -258,7 +252,6 @@ def prepare_codegen_default(self, fpgapart, clk): code_gen_dict = {} code_gen_dict["$IS_MVU$"] = [str(1)] code_gen_dict["$COMPUTE_CORE$"] = [self._resolve_impl_style(fpgapart)] - # code_gen_dict["$PUMPED_COMPUTE$"] = [str(0)] code_gen_dict["$MW$"] = [str(self.get_nodeattr("MW"))] code_gen_dict["$MH$"] = [str(self.get_nodeattr("MH"))] code_gen_dict["$PE$"] = [str(self.get_nodeattr("PE"))] @@ -298,3 +291,19 @@ def prepare_rtlsim(self): self.set_nodeattr("rtlsim_so", sim.lib._name) return sim + + def get_all_verilog_paths(self): + "Return list of all folders containing Verilog code for this node." + + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + # Path to (System-)Verilog files used by top-module & path to top-module + verilog_paths = [code_gen_dir, os.environ["FINN_ROOT"] + "/finn-rtllib/mvu"] + return verilog_paths + + def get_verilog_top_filename(self): + "Return the Verilog top module filename for this node." + + verilog_file = "{}/{}_wrapper.v".format( + self.get_nodeattr("code_gen_dir_ipgen"), self.get_nodeattr("gen_top_module") + ) + return verilog_file From 943dcf3b03125d057f73403db1aeae7db1a5927f Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Thu, 7 Mar 2024 15:33:30 +0000 Subject: [PATCH 563/665] updated copyright header --- finn-rtllib/mvu/mvu_4sx4u.sv | 33 ++++++ finn-rtllib/mvu/mvu_8sx8u_dsp48.sv | 33 ++++++ finn-rtllib/mvu/mvu_vvu_8sx9_dsp58.sv | 4 +- finn-rtllib/mvu/mvu_vvu_axi.sv | 9 +- finn-rtllib/mvu/mvu_vvu_axi_wrapper.v | 2 +- finn-rtllib/mvu/tb/mvu_8sx9_tb.sv | 165 ++++++++++++++++++++++++++ finn-rtllib/mvu/tb/mvu_axi_tb.sv | 4 +- finn-rtllib/mvu/tb/mvu_dsp58_tb.sv | 142 ++++++++++++++++++++++ finn-rtllib/mvu/tb/vvu_axi_tb.sv | 10 +- 9 files changed, 387 insertions(+), 15 deletions(-) create mode 100644 finn-rtllib/mvu/tb/mvu_8sx9_tb.sv create mode 100644 finn-rtllib/mvu/tb/mvu_dsp58_tb.sv diff --git a/finn-rtllib/mvu/mvu_4sx4u.sv b/finn-rtllib/mvu/mvu_4sx4u.sv index aafe0e3429..0ac2628ee5 100644 --- a/finn-rtllib/mvu/mvu_4sx4u.sv +++ b/finn-rtllib/mvu/mvu_4sx4u.sv @@ -1,3 +1,36 @@ +/****************************************************************************** + * Copyright (C) 2024, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * @brief Matrix Vector Unit (MVU) core compute kernel utilizing DSP48. + *****************************************************************************/ + module mvu_4sx4u #( int unsigned PE, int unsigned SIMD, diff --git a/finn-rtllib/mvu/mvu_8sx8u_dsp48.sv b/finn-rtllib/mvu/mvu_8sx8u_dsp48.sv index 1423153c97..fbf48784f0 100644 --- a/finn-rtllib/mvu/mvu_8sx8u_dsp48.sv +++ b/finn-rtllib/mvu/mvu_8sx8u_dsp48.sv @@ -1,3 +1,36 @@ +/****************************************************************************** + * Copyright (C) 2024, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * @brief Matrix Vector Unit (MVU) core compute kernel utilizing DSP48. + *****************************************************************************/ + module mvu_8sx8u_dsp48 #( int unsigned PE, int unsigned SIMD, diff --git a/finn-rtllib/mvu/mvu_vvu_8sx9_dsp58.sv b/finn-rtllib/mvu/mvu_vvu_8sx9_dsp58.sv index 53cf71fd5f..2cc6cf1bcf 100644 --- a/finn-rtllib/mvu/mvu_vvu_8sx9_dsp58.sv +++ b/finn-rtllib/mvu/mvu_vvu_8sx9_dsp58.sv @@ -1,5 +1,5 @@ /****************************************************************************** - * Copyright (C) 2022, Advanced Micro Devices, Inc. + * Copyright (C) 2024, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -28,7 +28,7 @@ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * @brief Matrix Vector Unit (MVU) core compute kernel utilizing DSP58. + * @brief Matrix/Vector Vector Unit (MVU/VVU) core compute kernel utilizing DSP58. *****************************************************************************/ module mvu_vvu_8sx9_dsp58 #( diff --git a/finn-rtllib/mvu/mvu_vvu_axi.sv b/finn-rtllib/mvu/mvu_vvu_axi.sv index 91e3b77216..d7b16319c8 100644 --- a/finn-rtllib/mvu/mvu_vvu_axi.sv +++ b/finn-rtllib/mvu/mvu_vvu_axi.sv @@ -1,5 +1,5 @@ /****************************************************************************** - * Copyright (C) 2022, Advanced Micro Devices, Inc. + * Copyright (C) 2024, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -31,10 +31,9 @@ * @brief Matrix Vector Unit (MVU) & Vector Vector Unit (VVU) AXI-lite interface wrapper. * @details * The following compute cores are supported: - * - 4-bit MVU on DSP48 & DSP58 achieving 4 MACs/DSP, - * (4,8]-bit MVU on DSP48 achieving 2 MACs/DSP, - * [4,9]-bit MVU and VVU on DSP58 achieving 3 MACs/DSP, - * 'unconstrained' LUT-based MVU and VVU. + * - 4-bit MVU on DSP48 achieving 4 MACs/DSP, + * - (4,8]-bit MVU on DSP48 achieving 2 MACs/DSP, + * - [4,9]-bit MVU and VVU on DSP58 achieving 3 MACs/DSP, * Folding hints: * - PE scaling should divide MH. * - SIMD scaling should divide MW. diff --git a/finn-rtllib/mvu/mvu_vvu_axi_wrapper.v b/finn-rtllib/mvu/mvu_vvu_axi_wrapper.v index ee067fa8b5..936f2ce0fc 100644 --- a/finn-rtllib/mvu/mvu_vvu_axi_wrapper.v +++ b/finn-rtllib/mvu/mvu_vvu_axi_wrapper.v @@ -1,5 +1,5 @@ /****************************************************************************** - * Copyright (C) 2022, Advanced Micro Devices, Inc. + * Copyright (C) 2024, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/finn-rtllib/mvu/tb/mvu_8sx9_tb.sv b/finn-rtllib/mvu/tb/mvu_8sx9_tb.sv new file mode 100644 index 0000000000..c8bfe5370a --- /dev/null +++ b/finn-rtllib/mvu/tb/mvu_8sx9_tb.sv @@ -0,0 +1,165 @@ +/****************************************************************************** + * Copyright (C) 2022, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * @brief Testbench for MVU core compute kernel. + *****************************************************************************/ + +module mvu_8sx9_tb(); + +//-------------------- Simulation parameters --------------------\\ + // Matrix & parallelism config + localparam int unsigned MH = 256; + localparam int unsigned PE = 16; + localparam int unsigned MW = 600; + localparam int unsigned SIMD = 60; + localparam int unsigned SEGMENTLEN = 4; + // Bit-width config + localparam int unsigned ACTIVATION_WIDTH = 8; + localparam int unsigned WEIGHT_WIDTH = 4; + localparam bit SIGNED_ACTIVATIONS = 1; + // Simulation constants + localparam int unsigned NF = MH/PE; + localparam int unsigned SF = MW/SIMD; + localparam int unsigned NUM_OF_DSP = SIMD/3; + + typedef logic [SIMD-1:0][ACTIVATION_WIDTH-1:0] activation_t; + typedef activation_t activation_vector_t[SF]; + + function activation_vector_t init_ACTIVATIONS; + automatic activation_vector_t res; + std::randomize(res); + return res; + endfunction : init_ACTIVATIONS + + typedef logic [PE-1:0][SIMD-1:0][WEIGHT_WIDTH-1:0] weight_t; + typedef weight_t weight_matrix_t[NF][SF]; + + function weight_matrix_t init_WEIGHTS; + automatic weight_matrix_t res; + std::randomize(res); + return res; + endfunction : init_WEIGHTS; + + typedef logic signed [PE-1:0][57:0] output_t; + typedef output_t output_vector_t [NF]; + + function output_vector_t check_output(activation_vector_t a, weight_matrix_t w); + automatic output_vector_t res = '{default: 0}; + for (int j = 0; j 1) && !rst; + end + + // Compare computed output against golden output when vld flag is raised by DUT + always_ff @(posedge clk iff (vld && en)) begin + foreach(p[i]) begin + assert ($signed(p[i]) == $signed(GOLDEN_OUTPUT[NF_CNT][i])) $display(">>> [t=%0t] Test succeeded (NF=%0d)! Computed / GOLDEN = %0d / %0d", $time, NF_CNT, $signed(p[i]), $signed(GOLDEN_OUTPUT[NF_CNT][i])); + else begin + $error(">>> [t=%0t] TEST failed (NF=%0d)! Computed / GOLDEN = %0d / %0d", $time, NF_CNT, $signed(p[i]), $signed(GOLDEN_OUTPUT[NF_CNT][i])); + $stop; + end + end + NF_CNT += 1; + end + + // Instantiate DUT + mvu_8sx9 #( + .PE(PE), + .SIMD(SIMD), + .WEIGHT_WIDTH(WEIGHT_WIDTH), + .SIGNED_ACTIVATIONS(SIGNED_ACTIVATIONS), + .ACTIVATION_WIDTH(ACTIVATION_WIDTH), + .SEGMENTLEN(SEGMENTLEN) + ) + dut ( + .clk, .rst, .en, .last, .zero, .a, .w, .vld, .p + ); + +endmodule : mvu_8sx9_tb diff --git a/finn-rtllib/mvu/tb/mvu_axi_tb.sv b/finn-rtllib/mvu/tb/mvu_axi_tb.sv index 2f35a112ab..51bf623831 100644 --- a/finn-rtllib/mvu/tb/mvu_axi_tb.sv +++ b/finn-rtllib/mvu/tb/mvu_axi_tb.sv @@ -1,5 +1,5 @@ /****************************************************************************** - * Copyright (C) 2022, Advanced Micro Devices, Inc. + * Copyright (C) 2024, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -28,7 +28,7 @@ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * @brief Testbench for MVU AXI-lite interface wrapper. + * @brief Testbench for MVU AXI wrapper module. *****************************************************************************/ module mvu_axi_tb(); diff --git a/finn-rtllib/mvu/tb/mvu_dsp58_tb.sv b/finn-rtllib/mvu/tb/mvu_dsp58_tb.sv new file mode 100644 index 0000000000..108980c497 --- /dev/null +++ b/finn-rtllib/mvu/tb/mvu_dsp58_tb.sv @@ -0,0 +1,142 @@ +module mvu_dsp58_tb; + + localparam int unsigned N = 1000; + + localparam int unsigned MW = 12; + localparam int unsigned MH = 4; + localparam int unsigned PE = 2; + localparam int unsigned SIMD = 6; + localparam int unsigned ACTIVATION_WIDTH = 8; + localparam int unsigned WEIGHT_WIDTH = 8; + localparam int unsigned ACCU_WIDTH = 24; + + //- Global Control ------------------ + logic clk = 1; + logic clk2x = 1; + always #5ns clk = !clk; + always #2.5ns clk2x = !clk2x; + + logic rst = 1; + initial begin + repeat(8) @(posedge clk); + rst <= 0; + end + + //- DUTs ---------------------------- + + // Weight Stream + logic [PE-1:0][SIMD-1:0][WEIGHT_WIDTH-1:0] s_axis_weights_tdata; + logic s_axis_weights_tvalid[2]; + uwire s_axis_weights_tready[2]; + + // Input Stream + logic [SIMD-1:0][ACTIVATION_WIDTH-1:0] s_axis_input_tdata; + logic s_axis_input_tvalid[2]; + uwire s_axis_input_tready[2]; + + // Output Stream + uwire [PE-1:0][ACCU_WIDTH-1:0] m_axis_output_tdata[2]; + uwire m_axis_output_tvalid[2]; + logic m_axis_output_tready[2]; + + for(genvar i = 0; i < 2; i++) begin : genDUTs + mvu_vvu_axi #( + .IS_MVU(1), + .COMPUTE_CORE("mvu_vvu_8sx9_dsp58"), + .MW(MW), .MH(MH), + .PE(PE), .SIMD(SIMD), + .ACTIVATION_WIDTH(ACTIVATION_WIDTH), + .WEIGHT_WIDTH(WEIGHT_WIDTH), + .ACCU_WIDTH(ACCU_WIDTH), + .PUMPED_COMPUTE(i) + ) dut ( + .ap_clk(clk), .ap_clk2x(clk2x), .ap_rst_n(!rst), + .s_axis_weights_tdata, .s_axis_weights_tvalid(s_axis_weights_tvalid[i]), .s_axis_weights_tready(s_axis_weights_tready[i]), + .s_axis_input_tdata, .s_axis_input_tvalid (s_axis_input_tvalid [i]), .s_axis_input_tready (s_axis_input_tready [i]), + .m_axis_output_tdata(m_axis_output_tdata[i]), .m_axis_output_tvalid (m_axis_output_tvalid [i]), .m_axis_output_tready (m_axis_output_tready [i]) + ); + end : genDUTs + + + //- Stimuli ------------------------- + + // Weight Feed + initial begin + s_axis_weights_tvalid = '{ default: 0 }; + s_axis_weights_tdata = 'x; + @(posedge clk iff !rst); + + repeat(N * (MH/PE)*(MW/SIMD)) begin + automatic type(s_axis_weights_tdata) weights; + std::randomize(weights); + s_axis_weights_tdata <= weights; + s_axis_weights_tvalid <= '{ default: 1 }; + fork + begin + @(posedge clk iff s_axis_weights_tready[0]); + s_axis_weights_tvalid[0] <= 0; + end + begin + @(posedge clk iff s_axis_weights_tready[1]); + s_axis_weights_tvalid[1] <= 0; + end + join + end + end + + // Input Feed + initial begin + s_axis_input_tvalid = '{ default: 0 }; + s_axis_input_tdata = 'x; + @(posedge clk iff !rst); + + repeat(N * (MW/SIMD)) begin + automatic type(s_axis_input_tdata) in; + std::randomize(in); + s_axis_input_tdata <= in; + s_axis_input_tvalid <= '{ default: 1 }; + fork + begin + @(posedge clk iff s_axis_input_tready[0]); + s_axis_input_tvalid[0] <= 0; + end + begin + @(posedge clk iff s_axis_input_tready[1]); + s_axis_input_tvalid[1] <= 0; + end + join + end + end + + // Output Capture and Comparison + initial begin + m_axis_output_tready = '{ default: 0 }; + @(posedge clk iff !rst); + + repeat(N * (MH/PE)) begin + automatic type(m_axis_output_tdata) res; + m_axis_output_tready <= '{ default: 1 }; + fork + begin + @(posedge clk iff m_axis_output_tvalid[0]); + m_axis_output_tready[0] <= 0; + res[0] = m_axis_output_tdata[0]; + end + begin + @(posedge clk iff m_axis_output_tvalid[1]); + m_axis_output_tready[1] <= 0; + res[1] = m_axis_output_tdata[1]; + end + join + assert(res[0] == res[1]) else begin + $error("Output mismatch: %0x <=> %0x", res[0], res[1]); + $stop; + end + while($urandom()%7 < MW/SIMD) @(posedge clk); // Occassional backpressure + end + + $display("Test completed."); + $finish; + end + +endmodule : mvu_dsp58_tb diff --git a/finn-rtllib/mvu/tb/vvu_axi_tb.sv b/finn-rtllib/mvu/tb/vvu_axi_tb.sv index fbb45845e1..853dcc6e17 100644 --- a/finn-rtllib/mvu/tb/vvu_axi_tb.sv +++ b/finn-rtllib/mvu/tb/vvu_axi_tb.sv @@ -1,5 +1,5 @@ /****************************************************************************** - * Copyright (C) 2022, Advanced Micro Devices, Inc. + * Copyright (C) 2024, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -28,7 +28,7 @@ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * @brief Testbench for MVU AXI-lite interface wrapper. + * @brief Testbench for VVU AXI wrapper module. *****************************************************************************/ module vvu_axi_tb(); @@ -39,9 +39,9 @@ module vvu_axi_tb(); localparam string COMPUTE_CORE = "mvu_vvu_8sx9_dsp58"; localparam int unsigned MW = 25; // Kernel*Kernel localparam int unsigned MH = 4; // Channels - localparam int unsigned SIMD = 25; // MW%SIMD == 0 - localparam int unsigned PE = 2; // MH%PE == 0 - localparam int unsigned SEGMENTLEN = 3.0; + localparam int unsigned SIMD = 1; // MW%SIMD == 0 + localparam int unsigned PE = 1; // MH%PE == 0 + localparam int unsigned SEGMENTLEN = 1.0; localparam bit FORCE_BEHAVIORAL = 1; localparam bit M_REG_LUT = 1; // Bit-width config From dde16a9e8029497d3a161b94239e4a0bcfafea0f Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Thu, 7 Mar 2024 15:36:41 +0000 Subject: [PATCH 564/665] [transform]: renamed variable --- src/finn/transformation/fpgadataflow/specialize_layers.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/specialize_layers.py b/src/finn/transformation/fpgadataflow/specialize_layers.py index 191d84a8d3..29921a97f5 100644 --- a/src/finn/transformation/fpgadataflow/specialize_layers.py +++ b/src/finn/transformation/fpgadataflow/specialize_layers.py @@ -200,7 +200,7 @@ def _swg_hls_possible(node): def _mvu_rtl_possible(n): # Checks whether RTL-based MVU is supported - act_width_in_range = ( + inp_width_in_range = ( DataType[getCustomOp(n).get_nodeattr("inputDataType")].bitwidth() <= 8 ) or ( DataType[getCustomOp(n).get_nodeattr("inputDataType")].bitwidth() == 9 @@ -214,7 +214,7 @@ def _mvu_rtl_possible(n): external_memmode = getCustomOp(n).get_nodeattr("mem_mode") in ["decoupled", "external"] return ( - act_width_in_range + inp_width_in_range and weight_width_in_range and folding_supported and targets_dsp @@ -255,4 +255,4 @@ def apply(self, model): # remove old nodes graph.node.remove(node) graph_modified = True - return (model, graph_modified) + return (model, graph_modified) \ No newline at end of file From 8986c23b890323cd3d044a53418211bd9ce27cb7 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Thu, 7 Mar 2024 15:40:07 +0000 Subject: [PATCH 565/665] [rtlbackend]: added additional parameters to generate_hdl --- src/finn/custom_op/fpgadataflow/rtlbackend.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/finn/custom_op/fpgadataflow/rtlbackend.py b/src/finn/custom_op/fpgadataflow/rtlbackend.py index 96deb49161..be2a9e75c1 100644 --- a/src/finn/custom_op/fpgadataflow/rtlbackend.py +++ b/src/finn/custom_op/fpgadataflow/rtlbackend.py @@ -54,7 +54,7 @@ def code_generation_ipi(self): pass def code_generation_ipgen(self, model, fpgapart, clk): - self.generate_hdl() + self.generate_hdl(model, fpgapart, clk) # TODO: Implement alternative def hls_sname(self): From ee5312ed3914b094d3c2ed0a4a0508e6e0f37051 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Thu, 7 Mar 2024 15:42:11 +0000 Subject: [PATCH 566/665] [rtl op]: extended generate_hdl argument list --- .../fpgadataflow/rtl/convolutioninputgenerator_rtl.py | 2 +- src/finn/custom_op/fpgadataflow/rtl/fmpadding_rtl.py | 2 +- .../custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py | 3 --- .../fpgadataflow/rtl/streamingdatawidthconverter_rtl.py | 2 +- src/finn/custom_op/fpgadataflow/rtl/streamingfifo_rtl.py | 2 +- 5 files changed, 4 insertions(+), 7 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/rtl/convolutioninputgenerator_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/convolutioninputgenerator_rtl.py index 08564ca6da..35026a169c 100755 --- a/src/finn/custom_op/fpgadataflow/rtl/convolutioninputgenerator_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/convolutioninputgenerator_rtl.py @@ -839,7 +839,7 @@ def select_impl_style(self): return impl_style - def generate_hdl(self): + def generate_hdl(self, model, fpgapart, clk): """Generates HDL code and wrapper for the IP, depending on required implementation style.""" impl_style = self.select_impl_style() diff --git a/src/finn/custom_op/fpgadataflow/rtl/fmpadding_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/fmpadding_rtl.py index 19765d64c4..cc49446ea3 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/fmpadding_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/fmpadding_rtl.py @@ -171,7 +171,7 @@ def get_dynamic_config(self, ifm_dims=None, pads=None): } return config - def generate_hdl(self): + def generate_hdl(self, model, fpgapart, clk): rtlsrc = os.environ["FINN_ROOT"] + "/finn-rtllib/fmpadding/hdl" template_path = rtlsrc + "/fmpadding_template.v" dims = self.get_nodeattr("ImgDim") diff --git a/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py index 4f17aab5fd..c50ca52077 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py @@ -145,9 +145,6 @@ def dsp_estimation(self): dsp_res["DSP58"] = P * np.ceil(Q / 3) return dsp_res - def code_generation_ipgen(self, model, fpgapart, clk): - self.generate_hdl(model, fpgapart, clk) - def instantiate_ip(self, cmd): # instantiate the RTL IP code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") diff --git a/src/finn/custom_op/fpgadataflow/rtl/streamingdatawidthconverter_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/streamingdatawidthconverter_rtl.py index ef918b5db8..e79782eb6d 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/streamingdatawidthconverter_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/streamingdatawidthconverter_rtl.py @@ -137,7 +137,7 @@ def get_template_values(self): } return code_gen_dict - def generate_hdl(self): + def generate_hdl(self, model, fpgapart, clk): rtlsrc = os.environ["FINN_ROOT"] + "/finn-rtllib/dwc/hdl" template_path = rtlsrc + "/dwc_template.v" code_gen_dict = self.get_template_values() diff --git a/src/finn/custom_op/fpgadataflow/rtl/streamingfifo_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/streamingfifo_rtl.py index a9d9e689eb..dfae607622 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/streamingfifo_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/streamingfifo_rtl.py @@ -82,7 +82,7 @@ def get_verilog_top_module_intf_names(self): ret["ap_none"] = ["maxcount"] return ret - def generate_hdl(self): + def generate_hdl(self, model, fpgapart, clk): rtlsrc = os.environ["FINN_ROOT"] + "/finn-rtllib/fifo/hdl" template_path = rtlsrc + "/fifo_template.v" From b69a0fdc9290aa5b770d2a42daaf8b017c023c90 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Thu, 7 Mar 2024 15:42:53 +0000 Subject: [PATCH 567/665] [rtlbackend]: extended argument list of abstractmethod accordingly --- src/finn/custom_op/fpgadataflow/rtlbackend.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/finn/custom_op/fpgadataflow/rtlbackend.py b/src/finn/custom_op/fpgadataflow/rtlbackend.py index be2a9e75c1..8a81b7028b 100644 --- a/src/finn/custom_op/fpgadataflow/rtlbackend.py +++ b/src/finn/custom_op/fpgadataflow/rtlbackend.py @@ -42,7 +42,7 @@ def get_nodeattr_types(self): } @abstractmethod - def generate_hdl(self): + def generate_hdl(model, fpgapart, clk): pass @abstractmethod From af84aaa8e3d1c552a71e365e24b5b8efcbbe38bd Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Thu, 7 Mar 2024 16:41:43 +0000 Subject: [PATCH 568/665] [QONNX] update to latest main --- fetch-repos.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fetch-repos.sh b/fetch-repos.sh index 1275ccf31c..a81b746921 100755 --- a/fetch-repos.sh +++ b/fetch-repos.sh @@ -27,7 +27,7 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -QONNX_COMMIT="47e4357faf66b5b0d1bf77bf908bb47752421e5b" +QONNX_COMMIT="fd61cfeebbdaba351abf7e9d54cd785d7776fa4f" FINN_EXP_COMMIT="de99347e936d51715f5356a1b6c64e37b91c23c2" BREVITAS_COMMIT="84f42259ec869eb151af4cb8a8b23ad925f493db" PYVERILATOR_COMMIT="766e457465f5c0dd315490d7b9cc5d74f9a76f4f" From 366db07511f92c636abec65bd071d4da558c1543 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 8 Mar 2024 10:28:30 +0000 Subject: [PATCH 569/665] [mvau]: renamed method to more generic name --- src/finn/custom_op/fpgadataflow/matrixvectoractivation.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index 138cd9f3ad..e1e098e676 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -593,7 +593,7 @@ def get_hw_compatible_threshold_tensor(self, orig_thres_matrix): rows between PEs is not as expected (n_thres_steps)""" return ret.reshape(1, pe, tmem, n_thres_steps) - def get_hls_compatible_weight_tensor(self, orig_weight_matrix): + def get_hw_compatible_weight_tensor(self, orig_weight_matrix): """Convert the original numpy weight matrix orig_weight_matrix into a form suitable for passing to the hlslib call: * ensure MH % PE == 0 and MW % SIMD == 0 @@ -644,7 +644,7 @@ def make_weight_file(self, weights, weight_file_mode, weight_file_name): """ # convert weights into hlslib-compatible format - weight_tensor = self.get_hls_compatible_weight_tensor(weights) + weight_tensor = self.get_hw_compatible_weight_tensor(weights) export_wdt = self.get_weight_datatype() # we have converted bipolar weights to binary for export, # so use it as such for weight generation From 4334dd95328d69b615b70ecb60efd350c5633b70 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 8 Mar 2024 10:30:53 +0000 Subject: [PATCH 570/665] minor fix to abstractmethod parameters --- src/finn/custom_op/fpgadataflow/rtlbackend.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/finn/custom_op/fpgadataflow/rtlbackend.py b/src/finn/custom_op/fpgadataflow/rtlbackend.py index 8a81b7028b..2e4d647b22 100644 --- a/src/finn/custom_op/fpgadataflow/rtlbackend.py +++ b/src/finn/custom_op/fpgadataflow/rtlbackend.py @@ -42,7 +42,7 @@ def get_nodeattr_types(self): } @abstractmethod - def generate_hdl(model, fpgapart, clk): + def generate_hdl(self, model, fpgapart, clk): pass @abstractmethod From 092979886335a939067779019e27cd0f545635ca Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 8 Mar 2024 12:37:25 +0000 Subject: [PATCH 571/665] minor fix to comment --- src/finn/custom_op/fpgadataflow/matrixvectoractivation.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index e1e098e676..b8dba2f9d1 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -643,7 +643,7 @@ def make_weight_file(self, weights, weight_file_mode, weight_file_name): * weight_file_name : filename for the weight file to be generated """ - # convert weights into hlslib-compatible format + # convert weights into hlslib/rtllib-compatible format weight_tensor = self.get_hw_compatible_weight_tensor(weights) export_wdt = self.get_weight_datatype() # we have converted bipolar weights to binary for export, From eb6e0ae0cf04fd41c156270e6132c2c2cc27bec9 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 8 Mar 2024 12:38:29 +0000 Subject: [PATCH 572/665] [test]: cleaned up test and minor modifications for supporting RTL-op --- tests/fpgadataflow/test_fpgadataflow_mvau.py | 43 ++++++++++++++------ 1 file changed, 30 insertions(+), 13 deletions(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_mvau.py b/tests/fpgadataflow/test_fpgadataflow_mvau.py index 03f1293b74..6c2940f8f7 100644 --- a/tests/fpgadataflow/test_fpgadataflow_mvau.py +++ b/tests/fpgadataflow/test_fpgadataflow_mvau.py @@ -312,7 +312,7 @@ def test_fpgadataflow_mvau_cppsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): inst.set_nodeattr("mem_mode", mem_mode) # Note: only HLS-based MVAU layers execute CPPsim inst.set_nodeattr("preferred_impl_style", "hls") - model = model.transform(SpecializeLayers()) + model = model.transform(SpecializeLayers("xc7z020clg400-1")) model = model.transform(GiveUniqueNodeNames()) model = model.transform(SetExecMode("cppsim")) model = model.transform(PrepareCppSim()) @@ -402,7 +402,6 @@ def test_fpgadataflow_mvau_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): # lookup op_type in registry of CustomOps inst = getCustomOp(node) inst.set_nodeattr("mem_mode", mem_mode) - inst.set_nodeattr("rtlsim_trace", "mvau_trace.vcd") inst.set_nodeattr("preferred_impl_style", "hls") # prepare input data @@ -424,13 +423,12 @@ def test_fpgadataflow_mvau_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): y_expected = y.reshape(oshape) # TODO split up into several dependent tests -- need to check how this # works for parametrized tests... - model = model.transform(SpecializeLayers()) + model = model.transform(SpecializeLayers("xc7z020clg400-1")) model = model.transform(SetExecMode("rtlsim")) model = model.transform(GiveUniqueNodeNames()) model = model.transform(PrepareIP("xc7z020clg400-1", 5)) model = model.transform(HLSSynthIP()) model = model.transform(PrepareRTLSim()) - model.save("mvau_rtl.onnx") y_produced = oxe.execute_onnx(model, input_dict)["outp"] assert (y_produced.reshape(y_expected.shape) == y_expected).all(), "rtlsim failed" @@ -449,7 +447,7 @@ def test_fpgadataflow_mvau_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): # mem_mode: const or decoupled @pytest.mark.parametrize("mem_mode", ["decoupled"]) # activation: None or DataType -@pytest.mark.parametrize("act", [DataType["INT4"]]) +@pytest.mark.parametrize("act", [None, DataType["INT4"]]) # weight datatype @pytest.mark.parametrize("wdt", [DataType["INT4"]]) # input datatype @@ -462,11 +460,15 @@ def test_fpgadataflow_mvau_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): @pytest.mark.parametrize("mw", [128]) # HLS matrix height (output features) @pytest.mark.parametrize("mh", [128]) +# Backend +@pytest.mark.parametrize("preferred_impl_style", ["hls", "rtl"]) @pytest.mark.fpgadataflow @pytest.mark.vivado def test_fpgadataflow_mvau_large_depth_decoupled_mode_rtlsim( - mem_mode, idt, wdt, act, nf, sf, mw, mh + mem_mode, idt, wdt, act, nf, sf, mw, mh, preferred_impl_style ): + if preferred_impl_style == "rtl" and act is not None: + pytest.skip("RTL-MVAU doesn't support const mem mode or embedded activations") if nf == -1: nf = mh if sf == -1: @@ -507,6 +509,8 @@ def test_fpgadataflow_mvau_large_depth_decoupled_mode_rtlsim( # lookup op_type in registry of CustomOps inst = getCustomOp(node) inst.set_nodeattr("mem_mode", mem_mode) + inst.set_nodeattr("resType", "auto") + inst.set_nodeattr("preferred_impl_style", preferred_impl_style) # prepare input data input_dict = prepare_inputs(x, idt, wdt) @@ -527,7 +531,9 @@ def test_fpgadataflow_mvau_large_depth_decoupled_mode_rtlsim( y_expected = y.reshape(oshape) # TODO split up into several dependent tests -- need to check how this # works for parametrized tests... - model = model.transform(SpecializeLayers()) + model = model.transform(SpecializeLayers("xc7z020clg400-1")) + model = model.transform(MinimizeWeightBitWidth()) + model = model.transform(MinimizeAccumulatorWidth()) model = model.transform(SetExecMode("rtlsim")) model = model.transform(GiveUniqueNodeNames()) model = model.transform(PrepareIP("xc7z020clg400-1", 5)) @@ -537,9 +543,10 @@ def test_fpgadataflow_mvau_large_depth_decoupled_mode_rtlsim( assert (y_produced.reshape(y_expected.shape) == y_expected).all(), "rtlsim failed" hls_synt_res_est = model.analysis(hls_synth_res_estimation) - assert "MVAU_hls_0" in hls_synt_res_est + if preferred_impl_style == "hls": + assert "MVAU_hls_0" in hls_synt_res_est - node = model.get_nodes_by_op_type("MVAU_hls")[0] + node = model.get_nodes_by_op_type("MVAU")[0] inst = getCustomOp(node) cycles_rtlsim = inst.get_nodeattr("cycles_rtlsim") exp_cycles_dict = model.analysis(exp_cycles_per_layer) @@ -551,7 +558,7 @@ def test_fpgadataflow_mvau_large_depth_decoupled_mode_rtlsim( # mem_mode: const or decoupled @pytest.mark.parametrize("mem_mode", ["decoupled", "const"]) # activation: None or DataType -@pytest.mark.parametrize("act", [DataType["INT4"]]) +@pytest.mark.parametrize("act", [None, DataType["INT4"]]) # weight datatype @pytest.mark.parametrize("wdt", [DataType["INT4"]]) # input datatype @@ -564,9 +571,15 @@ def test_fpgadataflow_mvau_large_depth_decoupled_mode_rtlsim( @pytest.mark.parametrize("mw", [32]) # HLS matrix height (output features) @pytest.mark.parametrize("mh", [32]) +# Backend +@pytest.mark.parametrize("preferred_impl_style", ["hls", "rtl"]) @pytest.mark.fpgadataflow @pytest.mark.vivado -def test_mvau_fifocharacterize_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): +def test_mvau_fifocharacterize_rtlsim( + mem_mode, idt, wdt, act, nf, sf, mw, mh, preferred_impl_style +): + if preferred_impl_style == "rtl" and (mem_mode == "const" or act is not None): + pytest.skip("RTL-MVAU doesn't support const mem mode or embedded activations") if nf == -1: nf = mh if sf == -1: @@ -591,9 +604,13 @@ def test_mvau_fifocharacterize_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): # lookup op_type in registry of CustomOps inst = getCustomOp(node) inst.set_nodeattr("mem_mode", mem_mode) + inst.set_nodeattr("resType", "auto") + inst.set_nodeattr("preferred_impl_style", preferred_impl_style) total_fold = nf * sf exp_total_cycles = total_fold + 10 - model = model.transform(SpecializeLayers()) + model = model.transform(SpecializeLayers("xc7z020clg400-1")) + model = model.transform(MinimizeWeightBitWidth()) + model = model.transform(MinimizeAccumulatorWidth()) model = model.transform(SetExecMode("rtlsim")) model = model.transform(GiveUniqueNodeNames()) model = model.transform(PrepareIP("xc7z020clg400-1", 5)) @@ -608,7 +625,7 @@ def test_mvau_fifocharacterize_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh): assert chrc_in.shape == (1, 2 * exp_total_cycles) assert chrc_out.shape == (1, 2 * exp_total_cycles) # first sf cycles should read input continuously - assert (chrc_in[0, :sf] == range(1, sf + 1)).all() + assert (chrc_in[0, :sf] == list(range(1, sf + 1))).all() # all outputs should be produced within the exp n of cycles assert chrc_out[0, exp_total_cycles] == nf From 5f7e9aea10d696b9dc478bee5af13a56a69c6aaa Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 8 Mar 2024 12:43:17 +0000 Subject: [PATCH 573/665] [test]: minor change to get_nodes_by_op_type call --- tests/fpgadataflow/test_fpgadataflow_mvau.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_mvau.py b/tests/fpgadataflow/test_fpgadataflow_mvau.py index 6c2940f8f7..9254c7ac5a 100644 --- a/tests/fpgadataflow/test_fpgadataflow_mvau.py +++ b/tests/fpgadataflow/test_fpgadataflow_mvau.py @@ -546,7 +546,10 @@ def test_fpgadataflow_mvau_large_depth_decoupled_mode_rtlsim( if preferred_impl_style == "hls": assert "MVAU_hls_0" in hls_synt_res_est - node = model.get_nodes_by_op_type("MVAU")[0] + if preferred_impl_style == "hls": + node = model.get_nodes_by_op_type("MVAU_hls")[0] + else: + node = model.get_nodes_by_op_type("MVAU_rtl")[0] inst = getCustomOp(node) cycles_rtlsim = inst.get_nodeattr("cycles_rtlsim") exp_cycles_dict = model.analysis(exp_cycles_per_layer) From 4bb2e88c73fab25671f103edf791a1dddbed20f5 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 8 Mar 2024 12:43:27 +0000 Subject: [PATCH 574/665] updated PyVerilator commit hash --- fetch-repos.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fetch-repos.sh b/fetch-repos.sh index 1275ccf31c..119d3f1172 100755 --- a/fetch-repos.sh +++ b/fetch-repos.sh @@ -30,7 +30,7 @@ QONNX_COMMIT="47e4357faf66b5b0d1bf77bf908bb47752421e5b" FINN_EXP_COMMIT="de99347e936d51715f5356a1b6c64e37b91c23c2" BREVITAS_COMMIT="84f42259ec869eb151af4cb8a8b23ad925f493db" -PYVERILATOR_COMMIT="766e457465f5c0dd315490d7b9cc5d74f9a76f4f" +PYVERILATOR_COMMIT="ce0a08c20cb8c1d1e84181d6f392390f846adbd1" CNPY_COMMIT="4e8810b1a8637695171ed346ce68f6984e585ef4" HLSLIB_COMMIT="16e5847a5e3ef76cffe84c8fad2f010d593457d3" OMX_COMMIT="0b59762f9e4c4f7e5aa535ee9bc29f292434ca7a" From dbd715da145d0b73ff8c51b512f30416ae413290 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 8 Mar 2024 13:32:12 +0000 Subject: [PATCH 575/665] [rtl mvau]: updated DSP resource estimates --- .../rtl/matrixvectoractivation_rtl.py | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py index c50ca52077..dccdc67d00 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py @@ -34,7 +34,6 @@ from finn.custom_op.fpgadataflow.rtlbackend import RTLBackend from finn.util.basic import get_rtlsim_trace_depth, make_build_dir from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy -from finn.util.fpgadataflow import is_versal try: from pyverilator import PyVerilator @@ -57,7 +56,10 @@ def __init__(self, onnx_node, **kwargs): super().__init__(onnx_node, **kwargs) def get_nodeattr_types(self): - my_attrs = {} + my_attrs = { + # Flag to indicate if Versal device is targeted + "is_versal": ("i", False, 0, {0, 1}), + } my_attrs.update(MVAU.get_nodeattr_types(self)) my_attrs.update(RTLBackend.get_nodeattr_types(self)) return my_attrs @@ -140,10 +142,11 @@ def dsp_estimation(self): # multiplication P = self.get_nodeattr("PE") Q = self.get_nodeattr("SIMD") - dsp_res = {} - dsp_res["DSP48"] = np.ceil(P / 4) * Q - dsp_res["DSP58"] = P * np.ceil(Q / 3) - return dsp_res + if self.get_nodeattr("is_versal"): + mult_dsp = P * np.ceil(Q / 3) + else: + mult_dsp = np.ceil(P / 4) * Q + return int(mult_dsp) def instantiate_ip(self, cmd): # instantiate the RTL IP @@ -196,7 +199,7 @@ def _resolve_impl_style(self, fpgapart): act_width = self.get_input_datatype(0).bitwidth() weight_width = self.get_input_datatype(1).bitwidth() - is_versal_family = is_versal(fpgapart) + is_versal_family = self.get_nodeattr("is_versal") if is_versal_family: return "mvu_vvu_8sx9_dsp58" From 8859d81970465b0912b13cfe4b910ccb8aa89913 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 8 Mar 2024 13:32:50 +0000 Subject: [PATCH 576/665] [transform]: added additional check for rtl-MVAU and added is_versal node attribute for rtl-MVAU --- .../transformation/fpgadataflow/specialize_layers.py | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/specialize_layers.py b/src/finn/transformation/fpgadataflow/specialize_layers.py index 29921a97f5..6349bdb713 100644 --- a/src/finn/transformation/fpgadataflow/specialize_layers.py +++ b/src/finn/transformation/fpgadataflow/specialize_layers.py @@ -34,6 +34,7 @@ from finn.custom_op.fpgadataflow.hls import custom_op as hls_variants from finn.custom_op.fpgadataflow.rtl import custom_op as rtl_variants +from finn.util.fpgadataflow import is_versal def _determine_impl_style(node, fpgapart=""): @@ -114,9 +115,6 @@ def _determine_impl_style(node, fpgapart=""): return "rtl" elif optype == "MVAU": if _mvu_rtl_possible(node): - if getCustomOp(node).get_nodeattr("noActivation") == 0: - # Split thresholding - pass return "rtl" else: warn_str = """There is no RTL variant for %s. The node will automatically be @@ -212,6 +210,7 @@ def _mvu_rtl_possible(n): ) and (getCustomOp(n).get_nodeattr("MW") % getCustomOp(n).get_nodeattr("SIMD") == 0) targets_dsp = getCustomOp(n).get_nodeattr("resType") in ["dsp", "auto"] external_memmode = getCustomOp(n).get_nodeattr("mem_mode") in ["decoupled", "external"] + no_activation = getCustomOp(n).get_nodeattr("noActivation") == 1 return ( inp_width_in_range @@ -219,6 +218,7 @@ def _mvu_rtl_possible(n): and folding_supported and targets_dsp and external_memmode + and no_activation ) @@ -251,8 +251,11 @@ def apply(self, model): for attribute in node.attribute: if attribute.name != "preferred_impl_style": new_node.attribute.append(attribute) + is_versal_family = is_versal(self.fpgapart) + if new_node.op_type == "MVAU_rtl": + getCustomOp(new_node).set_nodeattr("is_versal", is_versal_family) graph.node.insert(node_ind, new_node) # remove old nodes graph.node.remove(node) graph_modified = True - return (model, graph_modified) \ No newline at end of file + return (model, graph_modified) From f61ced89b4a915a397932ac60ea392a8485ea0e1 Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 8 Mar 2024 15:06:25 +0000 Subject: [PATCH 577/665] [Tests] Set mem_mode only if impl_style=hls for thresholding --- tests/fpgadataflow/test_fpgadataflow_thresholding.py | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_thresholding.py b/tests/fpgadataflow/test_fpgadataflow_thresholding.py index fc3996ddab..8dee95fa82 100644 --- a/tests/fpgadataflow/test_fpgadataflow_thresholding.py +++ b/tests/fpgadataflow/test_fpgadataflow_thresholding.py @@ -139,6 +139,14 @@ def make_single_thresholding_modelwrapper(impl_style, T, idt, odt, actval, n_inp @pytest.mark.vivado @pytest.mark.slow def test_fpgadataflow_thresholding(impl_style, idt, act, nf, ich, exec_mode, mem_mode): + # the mem_mode parameter can only be used for the hls thresholding + # so the test will only be executed once for impl_style=rtl and once skipped + # when the mem_mode is varied. Otherwise, the same test configuration would always + # run twice. + if impl_style == "rtl" and mem_mode == "internal_decoupled": + pytest.skip( + "Skip, because test is identical to impl_style=rtl and mem_mode=internal_embedded" + ) if nf == -1: nf = ich pe = ich // nf @@ -199,7 +207,8 @@ def test_fpgadataflow_thresholding(impl_style, idt, act, nf, ich, exec_mode, mem node = model.graph.node[0] inst = getCustomOp(node) inst.set_nodeattr("PE", pe) - inst.set_nodeattr("mem_mode", mem_mode) + if impl_style == "hls": + inst.set_nodeattr("mem_mode", mem_mode) if exec_mode == "cppsim": model = model.transform(PrepareCppSim()) From 5fe519d966ed33947863d515c1262cb3aada4007 Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 8 Mar 2024 15:27:59 +0000 Subject: [PATCH 578/665] [Thresholding] Rename mem mode to internal_decoupled --- src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py b/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py index 96d5f2d8b9..b753bc7a03 100644 --- a/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py @@ -133,7 +133,7 @@ def get_weightstream_width_padded(self): def get_ap_int_max_w(self): ap_int_max_w = HLSBackend.get_ap_int_max_w(self) - if self.get_nodeattr("mem_mode") == "decoupled": + if self.get_nodeattr("mem_mode") == "internal_decoupled": weightstream = self.get_weightstream_width() ap_int_max_w = max([weightstream, ap_int_max_w]) return ap_int_max_w From b67281b758b463457a079eb19664b4ef8f7afff5 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 8 Mar 2024 15:47:17 +0000 Subject: [PATCH 579/665] [transform]: add default empty string to fpgapart --- src/finn/transformation/fpgadataflow/specialize_layers.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/specialize_layers.py b/src/finn/transformation/fpgadataflow/specialize_layers.py index 6349bdb713..1563ef83ca 100644 --- a/src/finn/transformation/fpgadataflow/specialize_layers.py +++ b/src/finn/transformation/fpgadataflow/specialize_layers.py @@ -37,7 +37,7 @@ from finn.util.fpgadataflow import is_versal -def _determine_impl_style(node, fpgapart=""): +def _determine_impl_style(node): optype = node.op_type # check if there is an HLS or RTL variant or both @@ -225,7 +225,7 @@ def _mvu_rtl_possible(n): class SpecializeLayers(Transformation): """Specialize all layers to either HLS or RTL variants""" - def __init__(self, fpgapart): + def __init__(self, fpgapart=""): super().__init__() self.fpgapart = fpgapart @@ -251,8 +251,8 @@ def apply(self, model): for attribute in node.attribute: if attribute.name != "preferred_impl_style": new_node.attribute.append(attribute) - is_versal_family = is_versal(self.fpgapart) if new_node.op_type == "MVAU_rtl": + is_versal_family = is_versal(self.fpgapart) getCustomOp(new_node).set_nodeattr("is_versal", is_versal_family) graph.node.insert(node_ind, new_node) # remove old nodes From dfc1b208c8f7d22ef80da1309de96cd2ac3cabd6 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 8 Mar 2024 15:48:18 +0000 Subject: [PATCH 580/665] [transform]: minor fix to how fpgapart is propagated --- src/finn/transformation/fpgadataflow/specialize_layers.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/finn/transformation/fpgadataflow/specialize_layers.py b/src/finn/transformation/fpgadataflow/specialize_layers.py index 1563ef83ca..a8100a36d7 100644 --- a/src/finn/transformation/fpgadataflow/specialize_layers.py +++ b/src/finn/transformation/fpgadataflow/specialize_layers.py @@ -238,7 +238,7 @@ def apply(self, model): if not node.domain == "finn.custom_op.fpgadataflow": continue node_ind += 1 - impl_style = _determine_impl_style(node, self.fpgapart) + impl_style = _determine_impl_style(node) optype = node.op_type + "_" + impl_style new_node = helper.make_node( From e1a18c717b9e733314cd464fe75232f86bb5bc30 Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 8 Mar 2024 15:48:22 +0000 Subject: [PATCH 581/665] [Tests] Update runtime thresholding test with new mem mode --- .../test_fpgadataflow_thresholding.py | 22 ++++++++++--------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_thresholding.py b/tests/fpgadataflow/test_fpgadataflow_thresholding.py index 8dee95fa82..a6e7e41596 100644 --- a/tests/fpgadataflow/test_fpgadataflow_thresholding.py +++ b/tests/fpgadataflow/test_fpgadataflow_thresholding.py @@ -245,7 +245,7 @@ def test_fpgadataflow_thresholding(impl_style, idt, act, nf, ich, exec_mode, mem @pytest.mark.parametrize("impl_style", ["rtl", "hls"]) # configuration (ch, pe) -@pytest.mark.parametrize("cfg", [(1, 1), (6, 2), (6, 3), (8, 2), (8, 4)]) +@pytest.mark.parametrize("cfg", [(1, 1), (6, 2), (6, 3), (8, 4)]) @pytest.mark.fpgadataflow @pytest.mark.vivado def test_runtime_thresholds_read(impl_style, cfg): @@ -259,7 +259,7 @@ def test_runtime_thresholds_read(impl_style, cfg): ch = cfg[0] pe = cfg[1] n_inp_vecs = [1, 2, 2] - mem_mode = "internal_decoupled" + hls_mem_mode = "internal_decoupled" act = DataType["INT4"] idt = DataType["INT16"] odt = act @@ -274,9 +274,7 @@ def test_runtime_thresholds_read(impl_style, cfg): else: actval = odt.min() - model = make_single_thresholding_modelwrapper( - impl_style, T, pe, idt, odt, actval, mem_mode, n_inp_vecs - ) + model = make_single_thresholding_modelwrapper(impl_style, T, idt, odt, actval, n_inp_vecs) model = model.transform(SpecializeLayers()) # Make sure that specialize layer did not default to HLS implementation @@ -284,6 +282,9 @@ def test_runtime_thresholds_read(impl_style, cfg): node = model.get_nodes_by_op_type(f"Thresholding_{impl_style}")[0] op_inst = getCustomOp(node) + op_inst.set_nodeattr("PE", pe) + if impl_style == "hls": + op_inst.set_nodeattr("mem_mode", hls_mem_mode) op_inst.set_nodeattr("runtime_writeable_weights", 1) dat_fname = f"old_weights_{cfg}.dat" @@ -343,7 +344,7 @@ def read_weights(sim): @pytest.mark.parametrize("impl_style", ["hls", "rtl"]) # configuration (ch, pe) -@pytest.mark.parametrize("cfg", [(1, 1), (6, 2), (6, 3), (8, 2), (8, 4)]) +@pytest.mark.parametrize("cfg", [(1, 1), (6, 2), (6, 3), (8, 4)]) @pytest.mark.fpgadataflow @pytest.mark.vivado def test_runtime_thresholds_write(impl_style, cfg): @@ -361,7 +362,7 @@ def test_runtime_thresholds_write(impl_style, cfg): pe = cfg[1] n_inp_vecs = [1, 2, 2] - mem_mode = "decoupled" + hls_mem_mode = "internal_decoupled" act = DataType["INT4"] idt = DataType["INT16"] @@ -377,15 +378,16 @@ def test_runtime_thresholds_write(impl_style, cfg): else: actval = odt.min() - model = make_single_thresholding_modelwrapper( - impl_style, T_init, pe, idt, odt, actval, mem_mode, n_inp_vecs - ) + model = make_single_thresholding_modelwrapper(impl_style, T_init, idt, odt, actval, n_inp_vecs) model = model.transform(SpecializeLayers()) # Validate that specialize layer did not default to HLS implementation assert model.graph.node[0].op_type == "Thresholding_" + str(impl_style) op_inst = getCustomOp(model.graph.node[0]) + op_inst.set_nodeattr("PE", pe) + if impl_style == "hls": + op_inst.set_nodeattr("mem_mode", hls_mem_mode) op_inst.set_nodeattr("runtime_writeable_weights", 1) # Make new weights for runtime write From 62b1655a5322d3d37898ea5b42cc04506a9e81a7 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 8 Mar 2024 16:09:35 +0000 Subject: [PATCH 582/665] [transform]: minor fix to infer right MVAU type --- src/finn/transformation/fpgadataflow/specialize_layers.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/finn/transformation/fpgadataflow/specialize_layers.py b/src/finn/transformation/fpgadataflow/specialize_layers.py index a8100a36d7..94c0a87c03 100644 --- a/src/finn/transformation/fpgadataflow/specialize_layers.py +++ b/src/finn/transformation/fpgadataflow/specialize_layers.py @@ -54,6 +54,11 @@ def _determine_impl_style(node): if optype == "StreamingDataWidthConverter": return _dwc_determine_impl_style(node) if rtl_variant: + if optype == "MVAU": + if _mvu_rtl_possible(node): + return "rtl" + else: + return "hls" return "rtl" # but if no rtl variant, set impl_style to hls elif hls_variant: From f35dbf81a5fee7191fd7c507b8c614ac6548bde7 Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 8 Mar 2024 16:26:08 +0000 Subject: [PATCH 583/665] [Tests] Remove mem_mode from conversion to hw in end2end tests --- tests/end2end/test_end2end_bnn_pynq.py | 8 ++++++-- tests/end2end/test_end2end_mobilenet_v1.py | 3 +-- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index 0fab1b298e..e90c412dae 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -130,6 +130,7 @@ def fold_tfc(model): fcl_inst.set_nodeattr("PE", pe) fcl_inst.set_nodeattr("SIMD", simd) fcl_inst.set_nodeattr("ram_style", ramstyle) + fcl_inst.set_nodeattr("mem_mode", "internal_decoupled") # set parallelism for input quantizer to be same as first layer's SIMD inp_qnt_node = model.get_nodes_by_op_type("Thresholding_hls")[0] inp_qnt = getCustomOp(inp_qnt_node) @@ -154,6 +155,7 @@ def fold_lfc(model): fcl_inst.set_nodeattr("SIMD", simd) fcl_inst.set_nodeattr("ram_style", ramstyle) fcl_inst.set_nodeattr("runtime_writeable_weights", 1) + fcl_inst.set_nodeattr("mem_mode", "internal_decoupled") # set parallelism for input quantizer to be same as first layer's SIMD inp_qnt_node = model.get_nodes_by_op_type("Thresholding_hls")[0] inp_qnt = getCustomOp(inp_qnt_node) @@ -179,6 +181,7 @@ def fold_cnv_large(model): fcl_inst = getCustomOp(fcl) fcl_inst.set_nodeattr("PE", pe) fcl_inst.set_nodeattr("SIMD", simd) + fcl_inst.set_nodeattr("mem_mode", "internal_decoupled") swg_layers = model.get_nodes_by_op_type("ConvolutionInputGenerator_hls") for i in range(len(swg_layers)): @@ -207,6 +210,7 @@ def fold_cnv_small(model): fcl_inst.set_nodeattr("PE", pe) fcl_inst.set_nodeattr("SIMD", simd) fcl_inst.set_nodeattr("ram_style", ramstyle) + fcl_inst.set_nodeattr("mem_mode", "internal_decoupled") swg_layers = model.get_nodes_by_op_type("ConvolutionInputGenerator_hls") for i in range(len(swg_layers)): @@ -539,9 +543,9 @@ def test_convert_to_hw_layers(self, topology, wbits, abits, board): # use standalone thresholds for tfc-w1a1 to also exercise that option model = model.transform(to_hw.InferThresholdingLayer()) # needed for bipolar MatMul layers - model = model.transform(to_hw.InferBinaryMatrixVectorActivation(mem_mode)) + model = model.transform(to_hw.InferBinaryMatrixVectorActivation()) # needed for non-bipolar MatMul layers - model = model.transform(to_hw.InferQuantizedMatrixVectorActivation(mem_mode)) + model = model.transform(to_hw.InferQuantizedMatrixVectorActivation()) # TopK to LabelSelect model = model.transform(to_hw.InferLabelSelectLayer()) # input quantization (if any) to standalone thresholding diff --git a/tests/end2end/test_end2end_mobilenet_v1.py b/tests/end2end/test_end2end_mobilenet_v1.py index abd019c7bc..eec303d29e 100644 --- a/tests/end2end/test_end2end_mobilenet_v1.py +++ b/tests/end2end/test_end2end_mobilenet_v1.py @@ -92,7 +92,6 @@ test_platform = alveo_default_platform[test_board] test_fpga_part = alveo_part_map[test_board] target_clk_ns = 3 -mem_mode = "internal_decoupled" large_fifo_ram_style = "ultra" extra_fold = 1 first_layer_res_type = "dsp" @@ -226,7 +225,7 @@ def test_end2end_mobilenet_convert_to_hw_layers(): model = model.transform(to_hw.InferPool()) model = model.transform(to_hw.InferConvInpGen()) model = model.transform(to_hw.InferVectorVectorActivation()) - model = model.transform(to_hw.InferQuantizedMatrixVectorActivation(mem_mode)) + model = model.transform(to_hw.InferQuantizedMatrixVectorActivation()) model = model.transform(to_hw.InferChannelwiseLinearLayer()) model = model.transform(to_hw.InferLabelSelectLayer()) model = model.transform(InferShapes()) From c9b1d3782ee9c39daf59fa7fcc0d334072a57ea4 Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 11 Mar 2024 10:01:59 +0000 Subject: [PATCH 584/665] [Tests] Extend check to cover all cases for cppsim rtl swg --- tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py index 7482b789a9..02aaf85851 100644 --- a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py +++ b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py @@ -220,7 +220,7 @@ def test_fpgadataflow_slidingwindow( # if cppsim and impl style rtl is selected, the node execution is done by the hw op parent # so, no reordering/shaping of the output is needed # because there is no concept of SIMD parallelism in the hw abstraction layer execution - if dw == 0 or (impl_style == "rtl" and exec_mode == "cppsim"): + if dw == 0 or (optype == "ConvolutionInputGenerator_rtl" and exec_mode == "cppsim"): assert (y_produced == y_expected).all() else: y_expected = y_expected.reshape(1, ofm_dim_h, ofm_dim_w, k_h * k_w, ifm_ch // simd, simd) From 96712fdb4fd4c222301754f4ad8dac9e3c00a710 Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 11 Mar 2024 10:45:33 +0000 Subject: [PATCH 585/665] [RTL Thresholding] Temporarily defaulting to HLS variant in conversion --- src/finn/transformation/fpgadataflow/set_folding.py | 1 + src/finn/transformation/fpgadataflow/specialize_layers.py | 4 ++++ tests/fpgadataflow/test_convert_to_hw_layers_cnv.py | 4 ++++ 3 files changed, 9 insertions(+) diff --git a/src/finn/transformation/fpgadataflow/set_folding.py b/src/finn/transformation/fpgadataflow/set_folding.py index bff64d3885..a755d37a9d 100644 --- a/src/finn/transformation/fpgadataflow/set_folding.py +++ b/src/finn/transformation/fpgadataflow/set_folding.py @@ -105,6 +105,7 @@ def apply(self, model): "DuplicateStreams_hls", "GlobalAccPool_hls", "Thresholding_hls", + "Thresholding_rtl", ] # these ops use SIMD parallelism, up to a max value of NumChannels # ConvolutionInputGenerator* has a special case when depthwise=1 diff --git a/src/finn/transformation/fpgadataflow/specialize_layers.py b/src/finn/transformation/fpgadataflow/specialize_layers.py index a8e8fc72c1..7b8545db84 100644 --- a/src/finn/transformation/fpgadataflow/specialize_layers.py +++ b/src/finn/transformation/fpgadataflow/specialize_layers.py @@ -51,6 +51,10 @@ def _determine_impl_style(node): if impl_style == "": if optype == "StreamingDataWidthConverter": return _dwc_determine_impl_style(node) + # TODO extensively test RTL thresholding + # for now use HLS component for thresholding + if optype == "Thresholding": + return "hls" if rtl_variant: return "rtl" # but if no rtl variant, set impl_style to hls diff --git a/tests/fpgadataflow/test_convert_to_hw_layers_cnv.py b/tests/fpgadataflow/test_convert_to_hw_layers_cnv.py index 96e945d083..ff61867fde 100644 --- a/tests/fpgadataflow/test_convert_to_hw_layers_cnv.py +++ b/tests/fpgadataflow/test_convert_to_hw_layers_cnv.py @@ -101,6 +101,10 @@ def test_convert_to_hw_layers_cnv_w1a1(fused_activation): # subsequently, the FC inference will generate passthrough MVAUs if not fused_activation: model = model.transform(to_hw.InferThresholdingLayer()) + tr_nodes = model.get_nodes_by_op_type("Thresholding") + for tr in tr_nodes: + tr_inst = getCustomOp(tr) + tr_inst.set_nodeattr("preferred_impl_style", "hls") model = model.transform(to_hw.InferBinaryMatrixVectorActivation()) model = model.transform(to_hw.InferQuantizedMatrixVectorActivation()) model = model.transform(to_hw.InferConvInpGen()) From acd4c5523efceb195b3add69ee1dfe97cacbabf2 Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 11 Mar 2024 13:19:50 +0000 Subject: [PATCH 586/665] [NBs] Update tfc end2end notebooks to reflect new flow --- notebooks/advanced/cybsec_PE_SIMD.onnx | Bin 192077 -> 191973 bytes .../bnn-pynq/finn-design-flow-example.svg | 2 +- .../bnn-pynq/tfc_end2end_example.ipynb | 149 ++++++++++++------ .../bnn-pynq/tfc_end2end_verification.ipynb | 45 +++--- .../end2end_example/bnn-pynq/verification.png | Bin 55982 -> 0 bytes .../end2end_example/bnn-pynq/verification.svg | 1 + 6 files changed, 132 insertions(+), 65 deletions(-) delete mode 100755 notebooks/end2end_example/bnn-pynq/verification.png create mode 100755 notebooks/end2end_example/bnn-pynq/verification.svg diff --git a/notebooks/advanced/cybsec_PE_SIMD.onnx b/notebooks/advanced/cybsec_PE_SIMD.onnx index d09d07d2bf1b502d93bc676c8901fdc29de51d6b..8d42b2e37b16e42012e4d29fa365388e70537eef 100644 GIT binary patch delta 81 zcmX?mhx_Sm?g=7nTW@o7y=0mw^>p%XR^7>Nj1f$qm?ke^e22`{XNGf`Uovq`E@T#) We3j))^KRDm-K>n;ce650dI11K?;q>{ delta 164 zcmaEQoBQk??g=7nbMJ6-H8W3?dMYNt#gUtu8=sq>lB&d+lA4@fT9A{PGP!`MleveP vYhr-d + diff --git a/notebooks/end2end_example/bnn-pynq/tfc_end2end_example.ipynb b/notebooks/end2end_example/bnn-pynq/tfc_end2end_example.ipynb index a5c97328a5..bbaa74dbff 100644 --- a/notebooks/end2end_example/bnn-pynq/tfc_end2end_example.ipynb +++ b/notebooks/end2end_example/bnn-pynq/tfc_end2end_example.ipynb @@ -33,7 +33,7 @@ "cell_type": "markdown", "metadata": {}, "source": [ - "The white fields show the state of the network representation in the respective step. The colored fields represent the transformations that are applied to the network to achieve a certain result. The diagram is divided into 5 sections represented by a different color, each of it includes several flow steps. The flow starts in top left corner with Brevitas export (green section), followed by the preparation of the network (blue section) for the Vitis HLS synthesis and Vivado IPI stitching (orange section), and finally building a PYNQ overlay bitfile and testing it on a PYNQ board (yellow section).\n", + "The white fields show the state of the network representation in the respective step. The colored fields represent the transformations that are applied to the network to achieve a certain result. The diagram is divided into 5 sections represented by a different color, each of it includes several flow steps. The flow starts in top left corner with Brevitas export (green section), followed by the preparation of the network (blue section) to bring the network into a form in which each layer can be represented by either a Vitis HLS function or a Verilog module. The model then gets passed to Vivado IPI stitching (orange section), and finally a PYNQ overlay bitfile is built and can be tested on a PYNQ board (yellow section).\n", "There is an additional section for functional verification (red section) on the right side of the diagram, which we will not cover in this notebook. For details please take a look in the verification notebook which you can find [here](tfc_end2end_verification.ipynb)\n", "\n", "\n", @@ -114,7 +114,7 @@ "cell_type": "markdown", "metadata": {}, "source": [ - "Now that we have the model in .onnx format, we can work with it using FINN. For that, `ModelWrapper` is used. It is a wrapper around the ONNX model which provides several helper functions to make it easier to work with the model. 'ModelWrapper' is imported from the [QONNX repo](https://github.com/fastmachinelearning/qonnx), this repository contains several functionality that is used in FINN. The model was exported in QONNX format, to feed it into the FINN flow, our first step is to convert it to the FINN-ONNX format." + "Now that we have the model in .onnx format, we can work with it using FINN. For that, `ModelWrapper` is used. It is a wrapper around the ONNX model which provides several helper functions to make it easier to work with the model. `ModelWrapper` is imported from the [QONNX repo](https://github.com/fastmachinelearning/qonnx), this repository contains several functionality that is used in FINN. The model was exported in QONNX format, to feed it into the FINN flow, our first step is to convert it to the FINN-ONNX format." ] }, { @@ -129,6 +129,23 @@ "model = model.transform(ConvertQONNXtoFINN())" ] }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "After the conversion we save the model and visualize it using Netron. As you can see, quantization is now expressed differently. Where we had Quant nodes before, there are now MultiThreshold nodes present in the graph." + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": {}, + "outputs": [], + "source": [ + "model.save(build_dir+\"/tfc_w1_a1_finn.onnx\")\n", + "showInNetron(build_dir+\"/tfc_w1_a1_finn.onnx\")" + ] + }, { "cell_type": "markdown", "metadata": {}, @@ -149,8 +166,9 @@ "* [FINN-style Dataflow Architectures](#dataflow_arch)\n", "* [Tidy-up transformations](#basic_trafo)\n", "* [Streamlining](#streamline)\n", - "* [Conversion to HLS layers](#hls_layers)\n", + "* [Conversion to HW layers](#hw_layers)\n", "* [Creating a Dataflow Partition](#dataflow_partition)\n", + "* [Specialize layers](#specialize_layers)\n", "* [Folding and Datawidth Converter, FIFO and TLastMarker Insertion](#folding)\n", "\n", "\n", @@ -167,7 +185,7 @@ "\n", "![](finn-hw-arch.png)\n", "\n", - "In practice, the compute arrays are instantiated by function calls to optimized Vitis HLS building blocks from the [finn-hlslib](https://github.com/Xilinx/finn-hlslib) library. As these function calls can only handle certain patterns/cases, we need to transform the network into an appropriate form so that we can replace network layers with these function calls, which is the goal of the network preparation process." + "In practice, the compute arrays are instantiated by function calls to optimized Vitis HLS building blocks from the [finn-hlslib](https://github.com/Xilinx/finn-hlslib) library or by Verilog modules from the [finn-rtllib](https://github.com/Xilinx/finn/tree/main/finn-rtllib). As these function calls/modules can only handle certain patterns/cases, we need to transform the network into an appropriate form so that we can replace network layers with these function calls/modules, which is the goal of the network preparation process." ] }, { @@ -254,7 +272,7 @@ "\n", "In FINN, we can bake some of these pre/postprocessing operatings into the graph, and in some cases these can be highly beneficial for performance by allowing our accelerator to directly consume raw data instead of going through CPU preprocessing. \n", "\n", - "We'll demonstrate this for our small image classification network as follows. Brevitas preprocesses BNN-PYNQ network inputs with `torchvision.transforms.ToTensor()` [prior to training](https://github.com/Xilinx/brevitas/blob/master/src/brevitas_examples/bnn_pynq/trainer.py#L86), which converts 8-bit RGB values into floats between 0 and 1 by dividing the input by 255. We can achieve the same effect in FINN by exporting a single-node ONNX graph for division by 255 (which already exists as `finn.util.pytorch.ToTensor` and merging this with our original model. Finally, we're going to mark our input tensor as 8-bit to let FINN know which level of precision to use." + "We'll demonstrate this for our small image classification network as follows. Brevitas preprocesses BNN-PYNQ network inputs with `torchvision.transforms.ToTensor()` [prior to training](https://github.com/Xilinx/brevitas/blob/master/src/brevitas_examples/bnn_pynq/trainer.py#L93), which converts 8-bit RGB values into floats between 0 and 1 by dividing the input by 255. We can achieve the same effect in FINN by exporting a single-node ONNX graph for division by 255 (which already exists as `finn.util.pytorch.ToTensor` and merging this with our original model. Finally, we're going to mark our input tensor as 8-bit to let FINN know which level of precision to use." ] }, { @@ -407,32 +425,25 @@ "model = model.transform(InferDataLayouts())\n", "model = model.transform(RemoveUnusedTensors())\n", "\n", - "model.save(build_dir+\"/tfc_w1a1_ready_for_hls_conversion.onnx\")\n", - "showInNetron(build_dir+\"/tfc_w1a1_ready_for_hls_conversion.onnx\")" + "model.save(build_dir+\"/tfc_w1a1_ready_for_hw_conversion.onnx\")\n", + "showInNetron(build_dir+\"/tfc_w1a1_ready_for_hw_conversion.onnx\")" ] }, { "cell_type": "markdown", "metadata": {}, "source": [ - "Observe the pairs of `XnorPopcountmatMul` and `MultiThreshold` layers following each other -- this is the particular pattern that the next step will be looking for in order to convert them to HLS layers." + "Observe the pairs of `XnorPopcountmatMul` and `MultiThreshold` layers following each other -- this is the particular pattern that the next step will be looking for in order to convert them to hardware (HW) layers." ] }, { "cell_type": "markdown", "metadata": {}, "source": [ - "### Conversion to HLS layers \n", - "Converts the nodes to HLS layers that correspond to the functions in [finn-hls library](https://finn-hlslib.readthedocs.io/en/latest/). In our case this transformation converts pairs of binary XnorPopcountMatMul layers to MatrixVectorActivation layers. Any immediately following MultiThreshold layers will also be absorbed into the MVTU.\n", + "### Conversion to HW layers \n", + "Converts the nodes to HW layers, these layers are abstraction layers that do not directly correspond to an HLS or Verilog implementation but they will be converted in either one later in the flow. In our case this transformation converts pairs of binary XnorPopcountMatMul layers to MVAU layers (matrix vector activation unit). Any immediately following MultiThreshold layers will also be absorbed into the MVAU.\n", "\n", - "Below is the code for the transformation and the network is visualized using netron to create the new structure with `MatrixVectorActivation` nodes, which will correspond to a function call from the [finn-hlslib](https://finn-hlslib.readthedocs.io/en/latest/library/matrixvector.html) library." - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "**Note:** The transformation `to_hls.InferBinaryMatrixVectorActivation` gets the string \"decoupled\" as argument, this indicates the `mem_mode` for the weights. In FINN there are different options to set the way the weights are stored and accessed. For details please have a look on the [FINN readthedocs website](https://finn.readthedocs.io/) under Internals." + "Below is the code for the transformation and the network is visualized using netron to create the new structure with `MVAU` nodes." ] }, { @@ -441,22 +452,15 @@ "metadata": {}, "outputs": [], "source": [ - "import finn.transformation.fpgadataflow.convert_to_hls_layers as to_hls\n", - "model = ModelWrapper(build_dir+\"/tfc_w1a1_ready_for_hls_conversion.onnx\")\n", - "model = model.transform(to_hls.InferBinaryMatrixVectorActivation(\"decoupled\"))\n", + "import finn.transformation.fpgadataflow.convert_to_hw_layers as to_hw\n", + "model = ModelWrapper(build_dir+\"/tfc_w1a1_ready_for_hw_conversion.onnx\")\n", + "model = model.transform(to_hw.InferBinaryMatrixVectorActivation())\n", "# TopK to LabelSelect\n", - "model = model.transform(to_hls.InferLabelSelectLayer())\n", + "model = model.transform(to_hw.InferLabelSelectLayer())\n", "# input quantization (if any) to standalone thresholding\n", - "model = model.transform(to_hls.InferThresholdingLayer())\n", - "model.save(build_dir+\"/tfc_w1_a1_hls_layers.onnx\")\n", - "showInNetron(build_dir+\"/tfc_w1_a1_hls_layers.onnx\")" - ] - }, - { - "cell_type": "markdown", - "metadata": {}, - "source": [ - "Each MatrixVectorActivation node has two attributes that specify the degree of folding, PE and SIMD. In all nodes the values for these attributes are set as default to 1, which would correspond to a maximum folding (time multiplexing) and thus minimum performance. We will shortly cover how these can be adjusted, but first we want to separate the HLS layers from the non-HLS layers in this network." + "model = model.transform(to_hw.InferThresholdingLayer())\n", + "model.save(build_dir+\"/tfc_w1_a1_hw_layers.onnx\")\n", + "showInNetron(build_dir+\"/tfc_w1_a1_hw_layers.onnx\")" ] }, { @@ -465,7 +469,7 @@ "source": [ "### Creating a Dataflow Partition \n", "\n", - "In the graph above, you can see that there is a mixture of FINN HLS layers (MatrixVectorActivation and Thresholding_Batch) with one regular ONNX layers (Reshape). To create a bitstream, FINN needs a model with only HLS layers. In order to achieve this, we will use the `CreateDataflowPartition` transformation to create a \"dataflow partition\" in this graph, separating out the HLS layers into another model, and replacing them with a placeholder layer called StreamingDataflowPartition." + "In the graph above, you can see that there is a mixture of FINN HW layers (`MVAU` and `Thresholding`) with one regular ONNX layers (Reshape). To create a bitstream, FINN needs a model with only HW layers. In order to achieve this, we will use the `CreateDataflowPartition` transformation to create a \"dataflow partition\" in this graph, separating out the HLS layers into another model, and replacing them with a placeholder layer called StreamingDataflowPartition." ] }, { @@ -476,7 +480,7 @@ "source": [ "from finn.transformation.fpgadataflow.create_dataflow_partition import CreateDataflowPartition\n", "\n", - "model = ModelWrapper(build_dir+\"/tfc_w1_a1_hls_layers.onnx\")\n", + "model = ModelWrapper(build_dir+\"/tfc_w1_a1_hw_layers.onnx\")\n", "parent_model = model.transform(CreateDataflowPartition())\n", "parent_model.save(build_dir+\"/tfc_w1_a1_dataflow_parent.onnx\")\n", "showInNetron(build_dir+\"/tfc_w1_a1_dataflow_parent.onnx\")" @@ -486,7 +490,7 @@ "cell_type": "markdown", "metadata": {}, "source": [ - "We can see that the `MatrixVectorActivation` instances and the `Thresholding_Batch` in the beginning have all been replaced with a single `StreamingDataflowPartition`, which has an attribute `model` that points to the extracted, HLS dataflow-only graph:" + "We can see that the `MVAU` instances and the `Thresholding` in the beginning have all been replaced with a single `StreamingDataflowPartition`, which has an attribute `model` that points to the extracted, HW dataflow-only graph:" ] }, { @@ -506,7 +510,7 @@ "cell_type": "markdown", "metadata": {}, "source": [ - "We can see all the extracted `MatrixVectorActivation` instances and the `Thresholding_Batch` have been moved to the child (dataflow) model. We will load the child model with `ModelWrapper` and continue working on it." + "We can see all the extracted `MVAU` instances and the `Thresholding` have been moved to the child (dataflow) model. We will load the child model with `ModelWrapper` and continue working on it." ] }, { @@ -518,6 +522,60 @@ "model = ModelWrapper(dataflow_model_filename)" ] }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "### Specialize layers " + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "The network is converted to HW abstraction layers and we have excluded the non-HW layers to continue with the processing of the model. HW abstraction layers are abstract (placeholder) layers that can be either implemented in HLS or as an RTL module using FINN. In the next flow step, we convert each of these layers to either an HLS or RTL variant by calling the `SpecializeLayers` transformation. It is possible to let the FINN flow know a preference for the implementation style `{\"hls\", \"rtl\"}` and depending on the layer type this wish will be fulfilled or it will be set to a reasonable default. In the tfc example, we will set all layers to their HLS variants. To showcase how to set the preferred implementation, we will set the node attribute in the `Thresholding` layer to `\"hls\"`, for the `MVAUs` and the `LabelSelect` we will leave this node attribute empty and in this case by default it will be set to HLS." + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": {}, + "outputs": [], + "source": [ + "thresh_node = model.get_nodes_by_op_type(\"Thresholding\")[0]\n", + "thresh_node_inst = getCustomOp(thresh_node)\n", + "thresh_node_inst.set_nodeattr(\"preferred_impl_style\", \"hls\")" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "Then we will call `SpecializeLayers` to convert each HW abstraction layer to (in this case) an HLS variant." + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": {}, + "outputs": [], + "source": [ + "from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers\n", + "model = model.transform(SpecializeLayers())\n", + "\n", + "model.save(build_dir+\"/tfc_w1_a1_specialize_layers.onnx\")\n", + "showInNetron(build_dir+\"/tfc_w1_a1_specialize_layers.onnx\")" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "Each node type has now a suffix (`_hls`) and the module (`\n", + "finn.custom_op.fpgadataflow.hls` also indicates that that the HLS variant of the layer is selected.\n", + "We can now proceed by adjusting the parallelism of each node to customize the performance and resource usage.)" + ] + }, { "cell_type": "markdown", "metadata": {}, @@ -526,14 +584,17 @@ "\n", "*Folding* in FINN describes how much a layer is time-multiplexed in terms of execution resources. There are several *folding factors* for each layer, controlled by the PE (parallelization over outputs) and SIMD (parallelization over inputs) parameters as described by the original [FINN paper](https://arxiv.org/pdf/1612.07119). The higher the PE and SIMD values are set, the faster the generated accelerator will run, and the more FPGA resources it will consume. \n", "\n", - "Since the folding parameters are node attributes, they can be easily accessed and changed using a helper function of the `ModelWrapper`. But first we take a closer look at one of the nodes that implement a MatrixVectorActivation operation. This is where the Netron visualization helps us, in the above diagram we can see that the model contains four MatrixVectorActivation. So as an example we extract the second node of the graph." + "Each MVAU_hls node has two attributes that specify the degree of folding, PE and SIMD. In all nodes the values for these attributes are set as default to 1, which would correspond to a maximum folding (time multiplexing) and thus minimum performance. \n", + "\n", + "Since the folding parameters are node attributes, they can be easily accessed and changed using a helper function of the `ModelWrapper`. But first we take a closer look at one of the nodes that implement a Matrix-Vector-Activation operation. This is where the Netron visualization helps us, in the above diagram we can see that the model contains four `MVAUs`. So as an example we extract the second node of the graph." ] }, { "cell_type": "markdown", "metadata": {}, "source": [ - "We can use the higher-level [HLSCustomOp](https://github.com/Xilinx/finn/blob/main/src/finn/custom_op/fpgadataflow/hlscustomop.py) wrappers for this node. These wrappers provide easy access to specific properties of these nodes, such as the folding factors (PE and SIMD). Let's have a look at which node attributes are defined by the CustomOp wrapper, and adjust the SIMD and PE attributes." + "We can use the higher-level CustomOp wrappers for this node. These wrappers provide easy access to specific properties of these nodes, such as the folding factors (PE and SIMD). Above, we have already used this abstraction to set the node attribute of the Thresholding HW layer.\n", + "Let's have a look at which node attributes are defined by the CustomOp wrapper, and adjust the SIMD and PE attributes." ] }, { @@ -564,7 +625,7 @@ "metadata": {}, "outputs": [], "source": [ - "fc_layers = model.get_nodes_by_op_type(\"MatrixVectorActivation\")\n", + "fc_layers = model.get_nodes_by_op_type(\"MVAU_hls\")\n", "# (PE, SIMD, in_fifo_depth, out_fifo_depth, ramstyle) for each layer\n", "config = [\n", " (16, 49, [16], [64], \"block\"),\n", @@ -581,7 +642,7 @@ " fcl_inst.set_nodeattr(\"ram_style\", ramstyle)\n", " \n", "# set parallelism for input quantizer to be same as first layer's SIMD\n", - "inp_qnt_node = model.get_nodes_by_op_type(\"Thresholding_Batch\")[0]\n", + "inp_qnt_node = model.get_nodes_by_op_type(\"Thresholding_hls\")[0]\n", "inp_qnt = getCustomOp(inp_qnt_node)\n", "inp_qnt.set_nodeattr(\"PE\", 49)" ] @@ -658,7 +719,7 @@ "cell_type": "markdown", "metadata": {}, "source": [ - "In previous versions of FINN, we had to manually go through several steps to generate HLS code, stitch IP, create a PYNQ project and run synthesis. All these steps are now performed by the `ZynqBuild` transform (or the `VitisBuild` transform for Alveo). **As this involves calling HLS synthesis and Vivado synthesis, this transformation will run for some time (up to half an hour depending on your PC).**" + "In previous versions of FINN, we had to manually go through several steps to generate HLS/RTL code, stitch IP, create a PYNQ project and run synthesis. All these steps are now performed by the `ZynqBuild` transform (or the `VitisBuild` transform for Alveo). **As this involves calling HLS synthesis and Vivado synthesis, this transformation will run for some time (up to half an hour depending on your PC).**" ] }, { @@ -740,7 +801,7 @@ "cell_type": "markdown", "metadata": {}, "source": [ - "We can see that `StreamingFIFO` and `StreamingDataWidthConverter` instances have been automatically inserted into the graph prior to hardware build. Transformations like `ZynqBuild` use the `metadata_props` of the model to put in additional metadata information relevant to the results of the transformation. Let's examine the metadata for the current graph containing all layers:" + "We can see that `StreamingFIFO` and `StreamingDataWidthConverter` instances have been automatically inserted into the graph prior to hardware build. Both layer types are inserted as RTL variants. Transformations like `ZynqBuild` use the `metadata_props` of the model to put in additional metadata information relevant to the results of the transformation. Let's examine the metadata for the current graph containing all layers:" ] }, { @@ -1014,9 +1075,9 @@ "name": "python", "nbconvert_exporter": "python", "pygments_lexer": "ipython3", - "version": "3.10.6" + "version": "3.10.12" } }, "nbformat": 4, - "nbformat_minor": 2 + "nbformat_minor": 4 } diff --git a/notebooks/end2end_example/bnn-pynq/tfc_end2end_verification.ipynb b/notebooks/end2end_example/bnn-pynq/tfc_end2end_verification.ipynb index 2f6cde6e5b..a07a8d2254 100644 --- a/notebooks/end2end_example/bnn-pynq/tfc_end2end_verification.ipynb +++ b/notebooks/end2end_example/bnn-pynq/tfc_end2end_verification.ipynb @@ -7,16 +7,16 @@ "# FINN - Functional Verification of End-to-End Flow\n", "-----------------------------------------------------------------\n", "\n", - "**Important: This notebook depends on the tfc_end2end_example notebook, because we are using models that are available at intermediate steps in the end-to-end flow. So please make sure the needed .onnx files are generated to run this notebook.**\n", + "**Important: This notebook depends on the [tfc_end2end_example](tfc_end2end_example.ipynb) notebook, because we are using models that are available at intermediate steps in the end-to-end flow. So please make sure the needed .onnx files are generated to run this notebook.**\n", "\n", - "In this notebook, we will show how to take the intermediate results of the end-to-end tfc example and verify their functionality with different methods. In the following picture you can see the section in the end-to-end flow about the *Simulation & Emulation Flows*. Besides the methods in this notebook, there is another one that is covered in the Jupyter notebook [tfc_end2end_example](tfc_end2end_example.ipynb): remote execution. The remote execution allows functional verification directly on the PYNQ board, for details please have a look at the mentioned Jupyter notebook." + "In this notebook, we will show how to take the intermediate results of the end-to-end tfc example and verify their functionality with different methods. In the following picture you can see the section in the end-to-end flow about the *Simulation & Emulation Flows*. " ] }, { "cell_type": "markdown", "metadata": {}, "source": [ - "\"Drawing\"" + "\"Drawing\"" ] }, { @@ -72,9 +72,9 @@ "source": [ "## Simulation using Python \n", "\n", - "If an ONNX model consists of [standard ONNX](https://github.com/onnx/onnx/blob/main/docs/Operators.md) nodes and/or FINN custom operations that do not belong to the fpgadataflow (`backend` $\\neq$ `fpgadataflow`) this model can be checked for functionality using Python.\n", + "If an ONNX model consists of [standard ONNX](https://github.com/onnx/onnx/blob/main/docs/Operators.md) nodes and/or FINN custom operations that do not belong to the fpgadataflow (`backend` $\\neq$ `fpgadataflow.hls` or `backend` $\\neq$ `fpgadataflow.rtl`) this model can be checked for functionality using Python.\n", "\n", - "To simulate a standard ONNX node [onnxruntime](https://github.com/microsoft/onnxruntime) is used. onnxruntime is an open source tool developed by Microsoft to run standard ONNX nodes. For the FINN custom op nodes execution, functions are defined. The following is an example of the execution function of a XNOR popcount node.\n" + "To simulate a standard ONNX node [onnxruntime](https://github.com/microsoft/onnxruntime) is used. onnxruntime is an open source tool developed by Microsoft to run standard ONNX nodes. For the FINN custom op nodes execution, functions are defined. The following is an example of the execution function of an XNOR popcount node.\n" ] }, { @@ -95,7 +95,7 @@ "\n", "This execution function and onnxruntime is used when `execute_onnx` from `onnx_exec` is applied to the model. The model is then simulated node by node and the result is stored in a context dictionary, which contains the values of each tensor at the end of the execution. To get the result, only the output tensor has to be extracted.\n", "\n", - "The procedure is shown below. We take the model right before the nodes should be converted into HLS layers and generate an input tensor to pass to the execution function. The input tensor is generated from the Brevitas example inputs." + "The procedure is shown below. We take the model right before the nodes should be converted into HW layers and generate an input tensor to pass to the execution function. The input tensor is generated from the Brevitas example inputs." ] }, { @@ -108,7 +108,7 @@ "from qonnx.core.modelwrapper import ModelWrapper\n", "input_dict = {\"global_in\": nph.to_array(input_tensor)}\n", "\n", - "model_for_sim = ModelWrapper(build_dir+\"/tfc_w1a1_ready_for_hls_conversion.onnx\")" + "model_for_sim = ModelWrapper(build_dir+\"/tfc_w1a1_ready_for_hw_conversion.onnx\")" ] }, { @@ -141,7 +141,16 @@ "source": [ "## Simulation (cppsim) using C++\n", "\n", - "When dealing with HLS custom op nodes in FINN the simulation using Python is no longer sufficient. After the nodes have been converted to HLS layers, the simulation using C++ can be used. To do this, the input tensor is stored in a .npy file and C++ code is generated that reads the values from the .npy array, streams them to the corresponding finn-hlslib function and writes the result to a new .npy file. This in turn can be read in Python and processed in the FINN flow. For this example the model after setting the folding factors in the HLS layers is used, please be aware that this is not the full model, but the dataflow partition, so before executing at the end of this section we have to integrate the model back into the parent model." + "When dealing with HLS or RTL custom op nodes in FINN the simulation using Python is no longer sufficient. If the nodes are specialized to HLS layers, the simulation using C++ can be used. To do this, the input tensor is stored in a .npy file and C++ code is generated that reads the values from the .npy array, streams them to the corresponding `finn-hlslib` function and writes the result to a new .npy file. This in turn can be read in Python and processed in the FINN flow. For this example the model after setting the folding factors in the HLS variants of the layers, please be aware that this is not the full model, but the dataflow partition, so before executing at the end of this section we have to integrate the model back into the parent model." + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "
    \n", + "Note: HW layer can also be converted to RTL variants, in this case \"cppsim\" is not an option we can execute. If nevertheless \"cppsim\" is selected as execution mode for the layer, the execution defaults to the parent class. Like this, networks with a mix of HLS and RTL layers can be executed using \"cppsim\" for the HLS layers. \n", + "
    " ] }, { @@ -158,7 +167,7 @@ "metadata": {}, "source": [ "To generate the code for this simulation and to generate the executable two transformations are used:\n", - "* `PrepareCppSim` which generates the C++ code for the corresponding hls layer\n", + "* `PrepareCppSim` which generates the C++ code for the corresponding HLS layer\n", "* `CompileCppSim` which compules the C++ code and stores the path to the executable" ] }, @@ -280,9 +289,9 @@ "source": [ "## Emulation (rtlsim) using PyVerilator\n", "\n", - "The emulation using [PyVerilator](https://github.com/maltanar/pyverilator) can be done after IP blocks are generated from the corresponding HLS layers. Pyverilator is a tool which makes it possible to simulate verilog files using verilator via a python interface.\n", + "The emulation using [PyVerilator](https://github.com/maltanar/pyverilator) can be done after IP blocks are generated from the corresponding HLS layers or for RTL layers directly using the generated Verilog files. Pyverilator is a tool which makes it possible to simulate verilog files using verilator via a python interface.\n", "\n", - "We have two ways to use rtlsim, one is to run the model node-by-node as with the simulation methods, but if the model is in the form of the dataflow partition, the part of the graph that consist of only HLS nodes could also be executed as whole." + "We have two ways to use rtlsim, one is to run the model node-by-node as with the simulation methods, but if the model is in the form of the dataflow partition, the part of the graph that consist of only HLS/RTL nodes could also be executed as whole." ] }, { @@ -380,18 +389,14 @@ "source": [ "from finn.transformation.fpgadataflow.insert_dwc import InsertDWC\n", "from finn.transformation.fpgadataflow.insert_fifo import InsertFIFO\n", + "from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers\n", "from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP\n", "\n", "child_model = ModelWrapper(build_dir + \"/tfc_w1_a1_dataflow_child.onnx\")\n", - "child_model = child_model.transform(InsertDWC())\n", - "\n", - "# set all impl_styles of the DWCs to hls to enable emulation\n", - "dwc_nodes = child_model.get_nodes_by_op_type(\"StreamingDataWidthConverter_Batch\")\n", - "for dwc in dwc_nodes:\n", - " dwc_inst = getCustomOp(dwc)\n", - " dwc_inst.set_nodeattr(\"impl_style\", \"hls\")\n", - " \n", + "child_model = child_model.transform(InsertDWC()) \n", "child_model = child_model.transform(InsertFIFO(create_shallow_fifos=True))\n", + "# DWC and FIFOs need to be specialized to either HLS or RTL variants\n", + "child_model = child_model.transform(SpecializeLayers())\n", "child_model.save(build_dir + \"/test.onnx\");\n", "child_model = child_model.transform(GiveUniqueNodeNames())\n", "child_model = child_model.transform(PrepareIP(test_fpga_part, target_clk_ns))\n", @@ -455,7 +460,7 @@ "name": "python", "nbconvert_exporter": "python", "pygments_lexer": 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Subject: [PATCH 587/665] [NBs] Fix linting for verification svg --- notebooks/end2end_example/bnn-pynq/verification.svg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/notebooks/end2end_example/bnn-pynq/verification.svg b/notebooks/end2end_example/bnn-pynq/verification.svg index 9c6c4b91a4..9cf8e86088 100755 --- a/notebooks/end2end_example/bnn-pynq/verification.svg +++ b/notebooks/end2end_example/bnn-pynq/verification.svg @@ -1 +1 @@ - \ No newline at end of file + From c4aa418ef13ca87f13f5520e051a4baa5b857c72 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Tue, 12 Mar 2024 10:56:57 +0000 Subject: [PATCH 588/665] [mvu]: updated comments and removed mvu_vvu_lut module --- finn-rtllib/mvu/mvu_vvu_axi.sv | 9 +-------- finn-rtllib/mvu/mvu_vvu_axi_wrapper.v | 2 +- 2 files changed, 2 insertions(+), 9 deletions(-) diff --git a/finn-rtllib/mvu/mvu_vvu_axi.sv b/finn-rtllib/mvu/mvu_vvu_axi.sv index d7b16319c8..2a7403b6b3 100644 --- a/finn-rtllib/mvu/mvu_vvu_axi.sv +++ b/finn-rtllib/mvu/mvu_vvu_axi.sv @@ -57,7 +57,7 @@ module mvu_vvu_axi #( int unsigned ACCU_WIDTH, bit SIGNED_ACTIVATIONS = 0, - bit PUMPED_COMPUTE = 0, // requires an even SIMD % 2 == 0 + bit PUMPED_COMPUTE = 0, bit FORCE_BEHAVIORAL = 0, bit M_REG_LUT = 1, @@ -319,13 +319,6 @@ module mvu_vvu_axi #( .last(dsp_last), .zero(dsp_zero), .w(dsp_w), .a(dsp_a), .vld(dsp_vld), .p(dsp_p) ); - "mvu_vvu_lut": - mvu_vvu_lut #(.IS_MVU(IS_MVU), .PE(PE), .SIMD(DSP_SIMD), .ACCU_WIDTH(ACCU_WIDTH), .ACTIVATION_WIDTH(ACTIVATION_WIDTH), - .WEIGHT_WIDTH(WEIGHT_WIDTH), .SIGNED_ACTIVATIONS(SIGNED_ACTIVATIONS), .M_REG(M_REG_LUT)) core ( - .clk(dsp_clk), .rst, .en(dsp_en), - .last(dsp_last), .zero(dsp_zero), .w(dsp_w), .a(dsp_a), - .vld(dsp_vld), .p(dsp_p) - ); default: initial begin $error("Unrecognized COMPUTE_CORE '%s'", COMPUTE_CORE); $finish; diff --git a/finn-rtllib/mvu/mvu_vvu_axi_wrapper.v b/finn-rtllib/mvu/mvu_vvu_axi_wrapper.v index 936f2ce0fc..50c15c1b02 100644 --- a/finn-rtllib/mvu/mvu_vvu_axi_wrapper.v +++ b/finn-rtllib/mvu/mvu_vvu_axi_wrapper.v @@ -81,7 +81,7 @@ mvu_vvu_axi #( .SIGNED_ACTIVATIONS(SIGNED_ACTIVATIONS), .SEGMENTLEN(SEGMENTLEN), .FORCE_BEHAVIORAL(FORCE_BEHAVIORAL) ) inst ( .ap_clk(ap_clk), - .ap_clk2x(1'b0), + .ap_clk2x(1'b0), // wired to ground since double-pumped compute not enabled through FINN for now .ap_rst_n(ap_rst_n), .s_axis_weights_tdata(weights_V_TDATA), .s_axis_weights_tvalid(weights_V_TVALID), From 07ac1c9273c38a56c1e6d1bc0f144dda68dcf004 Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 12 Mar 2024 13:14:22 +0000 Subject: [PATCH 589/665] [Thresholding] Add NC case to HW op execution fct --- src/finn/custom_op/fpgadataflow/thresholding.py | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/thresholding.py b/src/finn/custom_op/fpgadataflow/thresholding.py index 822bb1476f..dde813a293 100644 --- a/src/finn/custom_op/fpgadataflow/thresholding.py +++ b/src/finn/custom_op/fpgadataflow/thresholding.py @@ -242,9 +242,16 @@ def execute_node(self, context, graph): node = self.onnx_node inp_values = context[node.input[0]] th_val = context[node.input[1]] - - y = multithreshold(np.transpose(inp_values, (0, 3, 1, 2)), th_val) - y = y.transpose(0, 2, 3, 1) + # MT expects inputs to be in the shape (N,C,H,W) or (N, C) + # if 4D then input values in context are (N,H,W,C) and need to + # be transposed. + # if 2D then inputs can be passed directly to MT function + is_4d = len(inp_values.shape) == 4 + if is_4d: + inp_values = np.transpose(inp_values, (0, 3, 1, 2)) + y = multithreshold(inp_values, th_val) + if is_4d: + y = y.transpose(0, 2, 3, 1) act = DataType[self.get_nodeattr("outputDataType")] if act == DataType["BIPOLAR"]: # binary to bipolar From 68ea1106214921d7ddbd5626548037309ac135c6 Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 12 Mar 2024 17:25:07 +0000 Subject: [PATCH 590/665] [NBs] Update cnv end2end and advanced builder settings notebook --- .../4_advanced_builder_settings.ipynb | 327 ++++++++++++++++-- .../advanced/cnv-w2a2_folding_config.json | 79 +++++ .../bnn-pynq/cnv_end2end_example.ipynb | 42 +-- 3 files changed, 401 insertions(+), 47 deletions(-) create mode 100644 notebooks/advanced/cnv-w2a2_folding_config.json diff --git a/notebooks/advanced/4_advanced_builder_settings.ipynb b/notebooks/advanced/4_advanced_builder_settings.ipynb index d9db2c2bc1..dccac6195d 100644 --- a/notebooks/advanced/4_advanced_builder_settings.ipynb +++ b/notebooks/advanced/4_advanced_builder_settings.ipynb @@ -228,7 +228,7 @@ "metadata": {}, "outputs": [], "source": [ - "showInNetron(build_dir+\"/output_estimates_only/intermediate_models/step_convert_to_hw.onnx\", localhost_url=\"xirxlabs60\")" + "showInNetron(build_dir+\"/output_estimates_only/intermediate_models/step_convert_to_hw.onnx\")" ] }, { @@ -635,7 +635,7 @@ "id": "8fd0af6b", "metadata": {}, "source": [ - "The model contains now a `Thresholding` layer in the beginning and a `LabelSelect_Batch` layer at the end. Please note, that there is still a `Transpose` node as the first layer of the graph, but we can solve this by converting the input data to the NHWC format before streaming it into the FINN accelerator." + "The model contains now a `Thresholding` layer in the beginning and a `LabelSelect` layer at the end. Please note, that there is still a `Transpose` node as the first layer of the graph, but we can solve this by converting the input data to the NHWC format before streaming it into the FINN accelerator." ] }, { @@ -646,6 +646,289 @@ "## Specialize layers configuration json " ] }, + { + "cell_type": "markdown", + "id": "4ae83d6e-c704-4c7f-a922-a4b470c0a55f", + "metadata": {}, + "source": [ + "The FINN compiler was developed with the assumption that the hardware blocks corresponding to the neural network layers are developed based on HLS. Although we do not want to abolish this HLS implementation at this time, it has become apparent over the years that for certain modules it makes sense to implement them in RTL. This allows us greater control over the resulting hardware and we can make optimal use of FPGA resources.\n" + ] + }, + { + "cell_type": "markdown", + "id": "ed72aabf-0517-422f-a686-6c70e7492114", + "metadata": {}, + "source": [ + "So, with the growth of more and more RTL variants of common FINN hardware building blocks, we introduced an additional builder step called `step_specialize_layers`. In this step HW nodes get specialized to either an HLS or RTL variant of the node. " + ] + }, + { + "cell_type": "markdown", + "id": "82a2bc39-8a37-49aa-a79d-2818e66ebd11", + "metadata": {}, + "source": [ + "They get converted either based on pre-determined rules or the user provides a configuration file which contains the desired setting. If the user preference cannot be fulfilled, a warning will be printed and the implementation style will be set to a default. " + ] + }, + { + "cell_type": "markdown", + "id": "bc90b589-7a92-4996-9704-02736ac4e60e", + "metadata": {}, + "source": [ + "The builder flow step before `step_specialize_layers` generates a template json file to set the preferred implementation style per layer. We can copy it from one of the previous runs to this folder and manipulate it to pass it to a new build." + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "ddb88eb1-3f11-4343-ae7c-3e5e8cbc34dc", + "metadata": {}, + "outputs": [], + "source": [ + "import json\n", + "\n", + "with open(build_dir+\"/output_pre_and_post_proc/template_specialize_layers_config.json\", 'r') as json_file:\n", + " specialize_layers_config = json.load(json_file)\n", + "\n", + "print(json.dumps(specialize_layers_config, indent=1))" + ] + }, + { + "cell_type": "markdown", + "id": "158d7d8c-a072-4a50-9714-43ebaefa53d1", + "metadata": {}, + "source": [ + "As you can see, each node is listed in the .json file and an empty string for the node attribute `preferred_impl_style` is instantiated by default. We can now use this .json and set the `preferred_impl_style` to pass to a new builder flow." + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "3f464d35-6774-4751-80b4-b6230e501539", + "metadata": {}, + "outputs": [], + "source": [ + "with open(build_dir+\"/output_pre_and_post_proc/template_specialize_layers_config.json\", 'r') as json_file:\n", + " specialize_layers_config = json.load(json_file)\n", + "\n", + "# Set all preferred_impl_style to all HLS\n", + "for key in specialize_layers_config:\n", + " if \"preferred_impl_style\" in specialize_layers_config[key]:\n", + " specialize_layers_config[key][\"preferred_impl_style\"] = \"hls\" \n", + "# Save as .json \n", + "with open(\"specialize_layers_all_hls.json\", \"w\") as jsonFile:\n", + " json.dump(specialize_layers_config, jsonFile)\n", + " \n", + "# Set SWG to RTL variant\n", + "for key in specialize_layers_config:\n", + " if \"preferred_impl_style\" in specialize_layers_config[key]:\n", + " if key.startswith(\"ConvolutionInputGenerator\"):\n", + " specialize_layers_config[key][\"preferred_impl_style\"] = \"rtl\"\n", + " else:\n", + " specialize_layers_config[key][\"preferred_impl_style\"] = \"hls\" \n", + "# Save as .json \n", + "with open(\"specialize_layers_swg_rtl.json\", \"w\") as jsonFile:\n", + " json.dump(specialize_layers_config, jsonFile)" + ] + }, + { + "cell_type": "markdown", + "id": "52592ea6-cd12-46b9-af91-5960b4749e7e", + "metadata": {}, + "source": [ + "We created two `specialize_layers_config_files`:\n", + "* One which sets all layers to `\"hls\"`\n", + "* One that sets `preferred_impl_style` for the ConvolutionInputGenerator to `\"rtl\"`" + ] + }, + { + "cell_type": "markdown", + "id": "701905d8-c5cc-4cc0-b872-156c5b9d0432", + "metadata": {}, + "source": [ + "In the following we will setup two build flows and run them to the estimate reports step. Afterwards we will investigate the intermediate .onnx files and compare the two runs." + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "22ff1a91-7ef7-44cb-86d3-60b9af7a8c5e", + "metadata": {}, + "outputs": [], + "source": [ + "## Build flow with custom folding configuration\n", + "## specialize_layers_config_file = \"specialize_layers_all_hls.json\"\n", + "\n", + "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/advanced\"\n", + "model_file = model_dir + \"/end2end_cnv_w2a2_export.onnx\"\n", + "\n", + "output_dir = build_dir + \"/output_all_hls\"\n", + "\n", + "#Delete previous run results if exist\n", + "if os.path.exists(output_dir):\n", + " shutil.rmtree(output_dir)\n", + " print(\"Previous run results deleted!\")\n", + "\n", + "build_steps = [\n", + " custom_step_add_pre_proc,\n", + " custom_step_add_post_proc,\n", + " \"step_qonnx_to_finn\",\n", + " \"step_tidy_up\",\n", + " \"step_streamline\",\n", + " \"step_convert_to_hw\",\n", + " \"step_create_dataflow_partition\",\n", + " \"step_specialize_layers\",\n", + " \"step_apply_folding_config\",\n", + " \"step_minimize_bit_width\",\n", + " \"step_generate_estimate_reports\",\n", + "]\n", + "\n", + "cfg_estimates = build.DataflowBuildConfig(\n", + " output_dir = output_dir,\n", + " mvau_wwidth_max = 80,\n", + " synth_clk_period_ns = 10.0,\n", + " fpga_part = \"xc7z020clg400-1\",\n", + " steps = build_steps,\n", + " specialize_layers_config_file = \"specialize_layers_all_hls.json\",\n", + " generate_outputs=[\n", + " build_cfg.DataflowOutputType.ESTIMATE_REPORTS,\n", + " ]\n", + ")" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "c9df41ff-ef6a-4d0e-ab36-241bb11ed241", + "metadata": {}, + "outputs": [], + "source": [ + "%%time\n", + "build.build_dataflow_cfg(model_file, cfg_estimates);" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "ff617f21-6001-4bb7-9cf7-2cc2acd3fbec", + "metadata": {}, + "outputs": [], + "source": [ + "## Build flow with custom folding configuration\n", + "## specialize_layers_config_file = \"specialize_layers_swg_rtl.json\"\n", + "\n", + "model_dir = os.environ['FINN_ROOT'] + \"/notebooks/advanced\"\n", + "model_file = model_dir + \"/end2end_cnv_w2a2_export.onnx\"\n", + "\n", + "output_dir = build_dir + \"/output_swg_rtl\"\n", + "\n", + "#Delete previous run results if exist\n", + "if os.path.exists(output_dir):\n", + " shutil.rmtree(output_dir)\n", + " print(\"Previous run results deleted!\")\n", + "\n", + "build_steps = [\n", + " custom_step_add_pre_proc,\n", + " custom_step_add_post_proc,\n", + " \"step_qonnx_to_finn\",\n", + " \"step_tidy_up\",\n", + " \"step_streamline\",\n", + " \"step_convert_to_hw\",\n", + " \"step_create_dataflow_partition\",\n", + " \"step_specialize_layers\",\n", + " \"step_apply_folding_config\",\n", + " \"step_minimize_bit_width\",\n", + " \"step_generate_estimate_reports\",\n", + "]\n", + "\n", + "cfg_estimates = build.DataflowBuildConfig(\n", + " output_dir = output_dir,\n", + " mvau_wwidth_max = 80,\n", + " synth_clk_period_ns = 10.0,\n", + " fpga_part = \"xc7z020clg400-1\",\n", + " steps = build_steps,\n", + " specialize_layers_config_file = \"specialize_layers_swg_rtl.json\",\n", + " generate_outputs=[\n", + " build_cfg.DataflowOutputType.ESTIMATE_REPORTS,\n", + " ]\n", + ")" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "8f48ba95-f7b5-455b-8041-25b7341ad115", + "metadata": {}, + "outputs": [], + "source": [ + "%%time\n", + "build.build_dataflow_cfg(model_file, cfg_estimates);" + ] + }, + { + "cell_type": "markdown", + "id": "bed4bedd-397d-4bd1-8531-c6ceac306715", + "metadata": {}, + "source": [ + "First we are looking into the intermediate model after `step_create_dataflow_partition` and then after `step_specialize_layers`." + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "4e64db23-98cb-494b-851f-3cc2c3847451", + "metadata": {}, + "outputs": [], + "source": [ + "showInNetron(build_dir+\"/output_all_hls/intermediate_models/step_create_dataflow_partition.onnx\")" + ] + }, + { + "cell_type": "markdown", + "id": "3e1a6351-367f-47a6-b802-a2613ea455a1", + "metadata": {}, + "source": [ + "Let's have a look first at the model which we specialize to \"all HLS\"." + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "f85d6c42-153d-4a40-b3cc-a4c8c89fe636", + "metadata": {}, + "outputs": [], + "source": [ + "showInNetron(build_dir+\"/output_all_hls/intermediate_models/step_specialize_layers.onnx\")" + ] + }, + { + "cell_type": "markdown", + "id": "e1520920-b7de-42a5-9ec8-e8503992fbd1", + "metadata": {}, + "source": [ + "As you can see, each op type has now a suffix indicating that it is an HLS variant of the node. Additionally, when you click on one of the node in the Netron visualization, you can see that module is set to `finn.custom_op.fpgadataflow.hls`.\n", + "\n", + "Let's now have a look at the model in which we specialized the ConvolutionInputGenerator to `\"rtl\"`." + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "9f1f26a0-3a62-4920-bf40-5b1b798fa02e", + "metadata": {}, + "outputs": [], + "source": [ + "showInNetron(build_dir+\"/output_swg_rtl/intermediate_models/step_specialize_layers.onnx\")" + ] + }, + { + "cell_type": "markdown", + "id": "3f9c4de4-61ef-4698-ab23-87bf5953c5ae", + "metadata": {}, + "source": [ + "You can use the cells above to try out different settings and pass it to the builder flow. Please note that not all layers have HLS and RTL variants, so it might be that the setting you define in `specialize_layers_config.json` gets ignored and a sensible default is set instead. The FINN compiler will display a warning in this case." + ] + }, { "cell_type": "markdown", "id": "5ffbadd1", @@ -950,7 +1233,7 @@ "metadata": {}, "outputs": [], "source": [ - "showInNetron(build_dir+\"/output_all_bram/intermediate_models/step_generate_estimate_reports.onnx\", localhost_url=\"xirxlabs60\")" + "showInNetron(build_dir+\"/output_all_bram/intermediate_models/step_generate_estimate_reports.onnx\")" ] }, { @@ -1444,17 +1727,15 @@ "id": "ffa2a352", "metadata": {}, "source": [ - "For an optimized design, we download the folding configuration for cnv-w2a2 on the Pynq-Z1 board from [finn-examples](https://github.com/Xilinx/finn-examples). And will pass it to the build flow. Please also note below that we now pass the board as argument to the builder (`board = \"Pynq-Z1\"`) instead of just the fpga part. This time we will select all possible outputs to generate. Please be aware that running the full build might take a few hours." + "For an optimized design, we saved a local copy of the folding configuration for cnv-w2a2 on the Pynq-Z1 board from [finn-examples](https://github.com/Xilinx/finn-examples) in this folder. And will pass it to the build flow. Please also note below that we now pass the board as argument to the builder (`board = \"Pynq-Z1\"`) instead of just the fpga part. This time we will select all possible outputs to generate. Please be aware that running the full build might take a few hours." ] }, { - "cell_type": "code", - "execution_count": null, - "id": "765e5ee7", + "cell_type": "markdown", + "id": "8d1b041f-027c-444e-81ac-98ce9b6d1b51", "metadata": {}, - "outputs": [], "source": [ - "!wget https://raw.githubusercontent.com/Xilinx/finn-examples/main/build/bnn-pynq/folding_config/cnv-w2a2_folding_config.json" + "Note that we set one additional argument: `default_swg_exception = True`. This is done because this example is customized to fit on the Pynq-Z1 board, to optimize the resources we remove FIFOs between SWGs and MVAUs manually to avoid unnecessary buffering." ] }, { @@ -1506,13 +1787,15 @@ "]\n", "\n", "cfg_build = build.DataflowBuildConfig(\n", - " output_dir = output_dir,\n", - " mvau_wwidth_max = 80,\n", - " synth_clk_period_ns = 10.0,\n", - " folding_config_file = \"cnv-w2a2_folding_config.json\",\n", - " board = \"Pynq-Z1\",\n", - " shell_flow_type = build_cfg.ShellFlowType.VIVADO_ZYNQ,\n", - " steps = build_steps,\n", + " output_dir = output_dir,\n", + " mvau_wwidth_max = 80,\n", + " synth_clk_period_ns = 10.0,\n", + " #specialize_layers_config_file = \"specialize_layers_all_hls.json\",\n", + " folding_config_file = \"cnv-w2a2_folding_config.json\",\n", + " board = \"Pynq-Z1\",\n", + " shell_flow_type = build_cfg.ShellFlowType.VIVADO_ZYNQ,\n", + " steps = build_steps,\n", + " default_swg_exception = True,\n", " generate_outputs=[\n", " build_cfg.DataflowOutputType.ESTIMATE_REPORTS,\n", " build_cfg.DataflowOutputType.STITCHED_IP,\n", @@ -1532,17 +1815,9 @@ "metadata": {}, "outputs": [], "source": [ - "%%time\n", - "build.build_dataflow_cfg(model_file, cfg_build);" + "#%%time\n", + "#build.build_dataflow_cfg(model_file, cfg_build);" ] - }, - { - "cell_type": "code", - "execution_count": null, - "id": "3eccb045-13b8-410b-bfcb-9e9c7146a1b4", - "metadata": {}, - "outputs": [], - "source": [] } ], "metadata": { diff --git a/notebooks/advanced/cnv-w2a2_folding_config.json b/notebooks/advanced/cnv-w2a2_folding_config.json new file mode 100644 index 0000000000..68409ff695 --- /dev/null +++ b/notebooks/advanced/cnv-w2a2_folding_config.json @@ -0,0 +1,79 @@ +{ + "Defaults": {}, + "Thresholding_hls_0": { + "PE": 1, + "ram_style": "distributed" + }, + "ConvolutionInputGenerator_rtl_0": { + "SIMD": 3, + "ram_style": "distributed" + }, + "MVAU_hls_0": { + "PE": 8, + "SIMD": 3, + "ram_style": "auto" + }, + "ConvolutionInputGenerator_rtl_1": { + "SIMD": 16, + "ram_style": "distributed" + }, + "MVAU_hls_1": { + "PE": 16, + "SIMD": 16, + "ram_style": "auto" + }, + "ConvolutionInputGenerator_rtl_2": { + "SIMD": 16, + "ram_style": "distributed" + }, + "MVAU_hls_2": { + "PE": 8, + "SIMD": 16, + "ram_style": "auto" + }, + "ConvolutionInputGenerator_rtl_3": { + "SIMD": 16, + "ram_style": "distributed" + }, + "MVAU_hls_3": { + "PE": 8, + "SIMD": 16, + "ram_style": "block" + }, + "ConvolutionInputGenerator_rtl_4": { + "SIMD": 8, + "ram_style": "distributed" + }, + "MVAU_hls_4": { + "PE": 4, + "SIMD": 8, + "ram_style": "auto" + }, + "ConvolutionInputGenerator_rtl_5": { + "SIMD": 8, + "ram_style": "distributed" + }, + "MVAU_hls_5": { + "PE": 1, + "SIMD": 8, + "ram_style": "auto" + }, + "MVAU_hls_6": { + "PE": 1, + "SIMD": 2, + "ram_style": "distributed" + }, + "MVAU_hls_7": { + "PE": 2, + "SIMD": 2, + "ram_style": "block" + }, + "MVAU_hls_8": { + "PE": 5, + "SIMD": 1, + "ram_style": "distributed" + }, + "LabelSelect_hls_0": { + "PE": 1 + } +} diff --git a/notebooks/end2end_example/bnn-pynq/cnv_end2end_example.ipynb b/notebooks/end2end_example/bnn-pynq/cnv_end2end_example.ipynb index 9e9d52e476..3141d54ddf 100644 --- a/notebooks/end2end_example/bnn-pynq/cnv_end2end_example.ipynb +++ b/notebooks/end2end_example/bnn-pynq/cnv_end2end_example.ipynb @@ -46,8 +46,8 @@ "cell_type": "markdown", "metadata": {}, "source": [ - "The white fields show the state of the network representation in the respective step. The colored fields represent the transformations that are applied to the network to achieve a certain result. The diagram is divided into 5 sections represented by a different color, each of it includes several flow steps. The flow starts in top left corner with Brevitas export (green section), followed by the preparation of the network (blue section) for the Vitis HLS synthesis and Vivado IPI stitching (orange section), and finally building a PYNQ overlay bitfile and testing it on a PYNQ board (yellow section).\n", - "There is an additional section for functional verification (red section) on the left side of the diagram, which we will not cover in this notebook. For details please take a look in the verification notebook which you can find [here](tfc_end2end_verification.ipynb)\n", + "The white fields show the state of the network representation in the respective step. The colored fields represent the transformations that are applied to the network to achieve a certain result. The diagram is divided into 5 sections represented by a different color, each of it includes several flow steps. The flow starts in top left corner with Brevitas export (green section), followed by the preparation of the network (blue section) to bring the network into a form in which each layer can be represented by either a Vitis HLS function or a Verilog module. The model then gets passed to Vivado IPI stitching (orange section), and finally a PYNQ overlay bitfile is built and can be tested on a PYNQ board (yellow section).\n", + "There is an additional section for functional verification (red section) on the right side of the diagram, which we will not cover in this notebook. For details please take a look in the verification notebook which you can find [here](tfc_end2end_verification.ipynb)\n", "\n", "\n", "We will use the helper function `showInNetron` to show the ONNX model at the current transformation step. The Netron displays are interactive, but they only work when running the notebook actively and not on GitHub (i.e. if you are viewing this on GitHub you'll only see blank squares)." @@ -207,7 +207,7 @@ "\n", "![](cnv-mp-fc.png)\n", "\n", - "Note how the convolution layer looks very similar to the fully connected one in terms of the matrix-vector-threshold unit (MVTU), but now the MVTU is preceded by a sliding window unit that produces the matrix from the input image. All of these building blocks, including the `MaxPool` layer you see in this figure, exist as templated Vitis HLS C++ functions in [finn-hlslib](https://github.com/Xilinx/finn-hlslib).\n", + "Note how the convolution layer looks very similar to the fully connected one in terms of the matrix-vector-threshold unit (MVTU) or sometimes called matrix-vector-activation unit (MVAU). But now the MVTU is preceded by a sliding window unit that produces the matrix from the input image. All of these building blocks, including the `MaxPool` layer you see in this figure, exist as templated Vitis HLS C++ functions in [finn-hlslib](https://github.com/Xilinx/finn-hlslib) and/or as RTL modules in [finn-rtllib](https://github.com/Xilinx/finn/tree/main/finn-rtllib).\n", "\n", "\n", "To target this kind of hardware architecture with our network we'll apply a convolution lowering transformation, in addition to streamlining. You may recall the *streamlining transformation* that we applied to the TFC-w1a1 network, which is a series of mathematical simplifications that allow us to get rid of floating point scaling operations by implementing few-bit activations as thresholding operations. \n", @@ -252,7 +252,7 @@ "\n", "* `Streamline` moves floating point scaling and addition operations closer to the input of the nearest thresholding activation and absorbs them into thresholds\n", "* `LowerConvsToMatMul` converts ONNX `Conv` nodes into sequences of `Im2Col, MatMul` nodes as discussed above. `Im2Col` is a custom FINN ONNX high-level node type that implements the sliding window operator.\n", - "* `MakeMaxPoolNHWC` and `AbsorbTransposeIntoMultiThreshold` convert the *data layout* of the network into the NHWC data layout that finn-hlslib primitives use. NCHW means the tensor dimensions are ordered as `(N : batch, H : height, W : width, C : channels)` (assuming 2D images). The ONNX standard ops normally use the NCHW layout, but the ONNX intermediate representation itself does not dictate any data layout.\n", + "* `MakeMaxPoolNHWC` and `AbsorbTransposeIntoMultiThreshold` convert the *data layout* of the network into the NHWC data layout that finn-hlslib and finn-rtllib primitives use. NCHW means the tensor dimensions are ordered as `(N : batch, H : height, W : width, C : channels)` (assuming 2D images). The ONNX standard ops normally use the NCHW layout, but the ONNX intermediate representation itself does not dictate any data layout.\n", "* You may recall `ConvertBipolarMatMulToXnorPopcount` from the TFC-w1a1 example, which is needed to implement bipolar-by-bipolar (w1a1) networks correctly using finn-hlslib.\n", "\n", "Let's visualize the streamlined and lowered network with Netron. Observe how all the `Conv` nodes have turned into pairs of `Im2Col, MatMul` nodes, and many nodes including `BatchNorm, Mul, Add` nodes have disappeared and replaced with `MultiThreshold` nodes." @@ -271,9 +271,9 @@ "cell_type": "markdown", "metadata": {}, "source": [ - "## 3. Partitioning, Conversion to HLS Layers and Folding\n", + "## 3. Partitioning, Conversion to HW Layers and Folding\n", "\n", - "The next steps will be (again) very similar to what we did for the TFC-w1a1 network. We'll first convert the layers that we can put into the FPGA into their HLS equivalents and separate them out into a *dataflow partition*:\n" + "The next steps will be (again) very similar to what we did for the TFC-w1a1 network. We'll first convert the layers that we can put into the FPGA into their HW equivalents, separate them out into a *dataflow partition* and specialize them to HLS variants:\n" ] }, { @@ -282,27 +282,25 @@ "metadata": {}, "outputs": [], "source": [ - "import finn.transformation.fpgadataflow.convert_to_hls_layers as to_hls\n", + "import finn.transformation.fpgadataflow.convert_to_hw_layers as to_hw\n", "from finn.transformation.fpgadataflow.create_dataflow_partition import (\n", " CreateDataflowPartition,\n", ")\n", "from finn.transformation.move_reshape import RemoveCNVtoFCFlatten\n", + "from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers\n", "from qonnx.custom_op.registry import getCustomOp\n", "from qonnx.transformation.infer_data_layouts import InferDataLayouts\n", "\n", - "# choose the memory mode for the MVTU units, decoupled or const\n", - "mem_mode = \"decoupled\"\n", - "\n", "model = ModelWrapper(build_dir + \"/end2end_cnv_w1a1_streamlined.onnx\")\n", - "model = model.transform(to_hls.InferBinaryMatrixVectorActivation(mem_mode))\n", - "model = model.transform(to_hls.InferQuantizedMatrixVectorActivation(mem_mode))\n", + "model = model.transform(to_hw.InferBinaryMatrixVectorActivation())\n", + "model = model.transform(to_hw.InferQuantizedMatrixVectorActivation())\n", "# TopK to LabelSelect\n", - "model = model.transform(to_hls.InferLabelSelectLayer())\n", + "model = model.transform(to_hw.InferLabelSelectLayer())\n", "# input quantization (if any) to standalone thresholding\n", - "model = model.transform(to_hls.InferThresholdingLayer())\n", - "model = model.transform(to_hls.InferConvInpGen())\n", - "model = model.transform(to_hls.InferStreamingMaxPool())\n", - "# get rid of Reshape(-1, 1) operation between hlslib nodes\n", + "model = model.transform(to_hw.InferThresholdingLayer())\n", + "model = model.transform(to_hw.InferConvInpGen())\n", + "model = model.transform(to_hw.InferStreamingMaxPool())\n", + "# get rid of Reshape(-1, 1) operation between hw nodes\n", "model = model.transform(RemoveCNVtoFCFlatten())\n", "# get rid of Tranpose -> Tranpose identity seq\n", "model = model.transform(absorb.AbsorbConsecutiveTransposes())\n", @@ -314,7 +312,9 @@ "sdp_node = getCustomOp(sdp_node)\n", "dataflow_model_filename = sdp_node.get_nodeattr(\"model\")\n", "# save the dataflow partition with a different name for easier access\n", + "# and specialize the layers to HLS variants\n", "dataflow_model = ModelWrapper(dataflow_model_filename)\n", + "dataflow_model = dataflow_model.transform(SpecializeLayers())\n", "dataflow_model.save(build_dir + \"/end2end_cnv_w1a1_dataflow_model.onnx\")" ] }, @@ -322,7 +322,7 @@ "cell_type": "markdown", "metadata": {}, "source": [ - "Notice the additional `RemoveCNVtoFCFlatten` transformation that was not used for TFC-w1a1. In the last Netron visualization you may have noticed a `Reshape` operation towards the end of the network where the convolutional part of the network ends and the fully-connected layers started. That `Reshape` is essentialy a tensor flattening operation, which we can remove for the purposes of hardware implementation. We can examine the contents of the dataflow partition with Netron, and observe the `ConvolutionInputGenerator`, `MatrixVectorActivation` and `StreamingMaxPool_Batch` nodes that implement the sliding window, matrix multiply and maxpool operations in hlslib. *Note that the MatrixVectorActivation instances following the ConvolutionInputGenerator nodes are really implementing the convolutions, despite the name. The final three MatrixVectorActivation instances implement actual FC layers.*" + "Notice the additional `RemoveCNVtoFCFlatten` transformation that was not used for TFC-w1a1. In the last Netron visualization you may have noticed a `Reshape` operation towards the end of the network where the convolutional part of the network ends and the fully-connected layers started. That `Reshape` is essentialy a tensor flattening operation, which we can remove for the purposes of hardware implementation. We can examine the contents of the dataflow partition with Netron, and observe the `ConvolutionInputGenerator`, `MatrixVectorActivation` and `StreamingMaxPool_Batch` nodes that implement the sliding window, matrix multiply and maxpool operations. *Note that the MatrixVectorActivation instances following the ConvolutionInputGenerator nodes are really implementing the convolutions, despite the name. The final three MatrixVectorActivation instances implement actual FC layers.*" ] }, { @@ -364,7 +364,7 @@ "outputs": [], "source": [ "model = ModelWrapper(build_dir + \"/end2end_cnv_w1a1_dataflow_model.onnx\")\n", - "fc_layers = model.get_nodes_by_op_type(\"MatrixVectorActivation\")\n", + "fc_layers = model.get_nodes_by_op_type(\"MVAU_hls\")\n", "# each tuple is (PE, SIMD, in_fifo_depth) for a layer\n", "folding = [\n", " (16, 3, [128]),\n", @@ -384,7 +384,7 @@ " fcl_inst.set_nodeattr(\"inFIFODepths\", ififodepth)\n", "\n", "# use same SIMD values for the sliding window operators\n", - "swg_layers = model.get_nodes_by_op_type(\"ConvolutionInputGenerator\")\n", + "swg_layers = model.get_nodes_by_op_type(\"ConvolutionInputGenerator_rtl\")\n", "for i in range(len(swg_layers)):\n", " swg_inst = getCustomOp(swg_layers[i])\n", " simd = folding[i][1]\n", @@ -398,7 +398,7 @@ "cell_type": "markdown", "metadata": {}, "source": [ - "Below we visualize in Netron to observe the `StreamingDataWidthConverter` and `StreamingFIFO` nodes that have been inserted into graph, as well as the folding factors in the `PE` and `SIMD` attributes of each `MatrixVectorActivation`." + "Below we visualize in Netron to observe the folding factors in the `PE` and `SIMD` attributes of each `MVAU_hls`." ] }, { From 9aab2a46ae76c5ae176ec9562afb95a97b58ca74 Mon Sep 17 00:00:00 2001 From: auphelia Date: Thu, 14 Mar 2024 09:25:15 +0000 Subject: [PATCH 591/665] [Docs] Update auto generated docs files --- docs/finn/conf.py | 2 +- docs/finn/source_code/finn.analysis.rst | 8 + .../finn.custom_op.fpgadataflow.hls.rst | 184 ++++++++++++++++++ .../finn.custom_op.fpgadataflow.rst | 153 +++++++-------- .../finn.custom_op.fpgadataflow.rtl.rst | 46 +++++ .../finn.transformation.fpgadataflow.rst | 41 ++-- docs/finn/source_code/finn.transformation.rst | 76 +++++++- docs/finn/source_code/finn.util.rst | 43 +++- docs/finn/verification.rst | 2 +- docs/requirements.txt | 3 + requirements.txt | 2 +- 11 files changed, 447 insertions(+), 113 deletions(-) create mode 100644 docs/finn/source_code/finn.custom_op.fpgadataflow.hls.rst create mode 100644 docs/finn/source_code/finn.custom_op.fpgadataflow.rtl.rst diff --git a/docs/finn/conf.py b/docs/finn/conf.py index 47ba99fb5f..a4416706c2 100644 --- a/docs/finn/conf.py +++ b/docs/finn/conf.py @@ -19,7 +19,7 @@ # -- Project information ----------------------------------------------------- project = "FINN" -copyright = "2020, Xilinx" +copyright = "2020-2022, Xilinx, 2022-2024, AMD" author = "Y. Umuroglu and J. Petri-Koenig" diff --git a/docs/finn/source_code/finn.analysis.rst b/docs/finn/source_code/finn.analysis.rst index f2321dbee7..d97c04eb62 100644 --- a/docs/finn/source_code/finn.analysis.rst +++ b/docs/finn/source_code/finn.analysis.rst @@ -31,6 +31,14 @@ qonnx.analysis.inference\_cost :undoc-members: :show-inheritance: +qonnx.analysis.tensor\_stats +----------------------------- + +.. automodule:: qonnx.analysis.tensor_stats + :members: + :undoc-members: + :show-inheritance: + qonnx.analysis.topology ----------------------------- diff --git a/docs/finn/source_code/finn.custom_op.fpgadataflow.hls.rst b/docs/finn/source_code/finn.custom_op.fpgadataflow.hls.rst new file mode 100644 index 0000000000..5a4fff6052 --- /dev/null +++ b/docs/finn/source_code/finn.custom_op.fpgadataflow.hls.rst @@ -0,0 +1,184 @@ +***************************** +Custom Op - fpgadataflow.hls +***************************** + +HLS Custom Op Nodes +=================== + +finn.custom\_op.fpgadataflow.addstreams\_hls +--------------------------------------------- + +.. automodule:: finn.custom_op.fpgadataflow.hls.addstreams_hls + :members: + :undoc-members: + :show-inheritance: + +finn.custom\_op.fpgadataflow.channelwise\_op\_hls +----------------------------------------------------- + +.. automodule:: finn.custom_op.fpgadataflow.hls.channelwise_op_hls + :members: + :undoc-members: + :show-inheritance: + +finn.custom\_op.fpgadataflow.checksum_hls +------------------------------------------ + +.. automodule:: finn.custom_op.fpgadataflow.hls.checksum_hls + :members: + :undoc-members: + :show-inheritance: + +finn.custom\_op.fpgadataflow.concat_hls +----------------------------------------- + +.. automodule:: finn.custom_op.fpgadataflow.hls.concat_hls + :members: + :undoc-members: + :show-inheritance: + + +finn.custom\_op.fpgadataflow.convolutioninputgenerator_hls +----------------------------------------------------------- + +.. automodule:: finn.custom_op.fpgadataflow.hls.convolutioninputgenerator_hls + :members: + :undoc-members: + :show-inheritance: + +finn.custom\_op.fpgadataflow.downsampler_hls +--------------------------------------------- + +.. automodule:: finn.custom_op.fpgadataflow.hls.downsampler_hls + :members: + :undoc-members: + :show-inheritance: + +finn.custom\_op.fpgadataflow.duplicatestreams\_hls +------------------------------------------------------- + +.. automodule:: finn.custom_op.fpgadataflow.hls.duplicatestreams_hls + :members: + :undoc-members: + :show-inheritance: + +finn.custom\_op.fpgadataflow.fmpadding\_hls +----------------------------------------------- + +.. automodule:: finn.custom_op.fpgadataflow.hls.fmpadding_hls + :members: + :undoc-members: + :show-inheritance: + +finn.custom\_op.fpgadataflow.fmpadding\_pixel\_hls +--------------------------------------------------- + +.. automodule:: finn.custom_op.fpgadataflow.hls.fmpadding_pixel_hls + :members: + :undoc-members: + :show-inheritance: + +finn.custom\_op.fpgadataflow.globalaccpool\_hls +--------------------------------------------------- + +.. automodule:: finn.custom_op.fpgadataflow.hls.globalaccpool_hls + :members: + :undoc-members: + :show-inheritance: + +finn.custom\_op.fpgadataflow.iodma\_hls +---------------------------------------- + +.. automodule:: finn.custom_op.fpgadataflow.hls.iodma_hls + :members: + :undoc-members: + :show-inheritance: + +finn.custom\_op.fpgadataflow.labelselect\_hls +----------------------------------------------- + +.. automodule:: finn.custom_op.fpgadataflow.hls.labelselect_hls + :members: + :undoc-members: + :show-inheritance: + +finn.custom\_op.fpgadataflow.lookup\_hls +------------------------------------------ + +.. automodule:: finn.custom_op.fpgadataflow.hls.lookup_hls + :members: + :undoc-members: + :show-inheritance: + +finn.custom\_op.fpgadataflow.matrixvectoractivation_hls +-------------------------------------------------------- + +.. automodule:: finn.custom_op.fpgadataflow.hls.matrixvectoractivation_hls + :members: + :undoc-members: + :show-inheritance: + + +finn.custom\_op.fpgadataflow.pool\_hls +----------------------------------------------- + +.. automodule:: finn.custom_op.fpgadataflow.hls.pool_hls + :members: + :undoc-members: + :show-inheritance: + +finn.custom\_op.fpgadataflow.streamingdatawidthconverter\_hls +---------------------------------------------------------------------- + +.. automodule:: finn.custom_op.fpgadataflow.hls.streamingdatawidthconverter_hls + :members: + :undoc-members: + :show-inheritance: + +finn.custom\_op.fpgadataflow.streamingeltwise\_hls +---------------------------------------------------------------------- + +.. automodule:: finn.custom_op.fpgadataflow.hls.streamingeltwise_hls + :members: + :undoc-members: + :show-inheritance: + +finn.custom\_op.fpgadataflow.streamingmaxpool\_hls +----------------------------------------------------------- + +.. automodule:: finn.custom_op.fpgadataflow.hls.streamingmaxpool_hls + :members: + :undoc-members: + :show-inheritance: + +finn.custom\_op.fpgadataflow.thresholding\_hls +------------------------------------------------------- + +.. automodule:: finn.custom_op.fpgadataflow.hls.thresholding_hls + :members: + :undoc-members: + :show-inheritance: + +finn.custom\_op.fpgadataflow.tlastmarker\_hls +----------------------------------------------- + +.. automodule:: finn.custom_op.fpgadataflow.hls.tlastmarker_hls + :members: + :undoc-members: + :show-inheritance: + +finn.custom\_op.fpgadataflow.upsampler\_hls +--------------------------------------------- + +.. automodule:: finn.custom_op.fpgadataflow.hls.upsampler_hls + :members: + :undoc-members: + :show-inheritance: + +finn.custom\_op.fpgadataflow.vectorvectoractivation\_hls +--------------------------------------------------------- + +.. automodule:: finn.custom_op.fpgadataflow.hls.vectorvectoractivation_hls + :members: + :undoc-members: + :show-inheritance: diff --git a/docs/finn/source_code/finn.custom_op.fpgadataflow.rst b/docs/finn/source_code/finn.custom_op.fpgadataflow.rst index 3627855cfb..25aafc324e 100644 --- a/docs/finn/source_code/finn.custom_op.fpgadataflow.rst +++ b/docs/finn/source_code/finn.custom_op.fpgadataflow.rst @@ -2,71 +2,71 @@ Custom Op - fpgadataflow ************************ -HLS Custom Op Nodes -=================== +Submodules +========== -Base Class ----------- +.. toctree:: + :maxdepth: 2 -.. automodule:: finn.custom_op.fpgadataflow.hlscustomop - :members: - :undoc-members: - :show-inheritance: + finn.custom_op.fpgadataflow.hls + finn.custom_op.fpgadataflow.rtl -finn.custom\_op.fpgadataflow.addstreams\_batch ------------------------------------------------ -.. automodule:: finn.custom_op.fpgadataflow.addstreams_batch +HW Custom Op Nodes +=================== + +Base Class - HWCustomOp +------------------------ + +.. automodule:: finn.custom_op.fpgadataflow.hwcustomop :members: :undoc-members: :show-inheritance: -finn.custom\_op.fpgadataflow.channelwise\_op\_batch ------------------------------------------------------ +HLSBackend +----------- -.. automodule:: finn.custom_op.fpgadataflow.channelwise_op_batch +.. automodule:: finn.custom_op.fpgadataflow.hlsbackend :members: :undoc-members: :show-inheritance: -finn.custom\_op.fpgadataflow.checksum --------------------------------------- +RTLBackend +----------- -.. automodule:: finn.custom_op.fpgadataflow.checksum +.. automodule:: finn.custom_op.fpgadataflow.rtlbackend :members: :undoc-members: :show-inheritance: -finn.custom\_op.fpgadataflow.concat -------------------------------------- +finn.custom\_op.fpgadataflow.addstreams +---------------------------------------- -.. automodule:: finn.custom_op.fpgadataflow.concat +.. automodule:: finn.custom_op.fpgadataflow.addstreams :members: :undoc-members: :show-inheritance: +finn.custom\_op.fpgadataflow.channelwise\_op +--------------------------------------------- -finn.custom\_op.fpgadataflow.convolutioninputgenerator --------------------------------------------------------- - -.. automodule:: finn.custom_op.fpgadataflow.convolutioninputgenerator +.. automodule:: finn.custom_op.fpgadataflow.channelwise_op :members: :undoc-members: :show-inheritance: -finn.custom\_op.fpgadataflow.convolutioninputgenerator1d -------------------------------------------------------------- +finn.custom\_op.fpgadataflow.concat +------------------------------------- -.. automodule:: finn.custom_op.fpgadataflow.convolutioninputgenerator1d +.. automodule:: finn.custom_op.fpgadataflow.concat :members: :undoc-members: :show-inheritance: +finn.custom\_op.fpgadataflow.convolutioninputgenerator +-------------------------------------------------------- -finn.custom\_op.fpgadataflow.convolutioninputgenerator\_rtl ------------------------------------------------------------- - -.. automodule:: finn.custom_op.fpgadataflow.convolutioninputgenerator_rtl +.. automodule:: finn.custom_op.fpgadataflow.convolutioninputgenerator :members: :undoc-members: :show-inheritance: @@ -79,52 +79,42 @@ finn.custom\_op.fpgadataflow.downsampler :undoc-members: :show-inheritance: -finn.custom\_op.fpgadataflow.duplicatestreams\_batch -------------------------------------------------------- +finn.custom\_op.fpgadataflow.duplicatestreams +---------------------------------------------- -.. automodule:: finn.custom_op.fpgadataflow.duplicatestreams_batch +.. automodule:: finn.custom_op.fpgadataflow.duplicatestreams :members: :undoc-members: :show-inheritance: +finn.custom\_op.fpgadataflow.fmpadding +--------------------------------------- -finn.custom\_op.fpgadataflow.eltwise -------------------------------------- - -.. automodule:: finn.custom_op.fpgadataflow.eltwise +.. automodule:: finn.custom_op.fpgadataflow.fmpadding :members: :undoc-members: :show-inheritance: - -finn.custom\_op.fpgadataflow.fmpadding\_batch +finn.custom\_op.fpgadataflow.fmpadding\_pixel ----------------------------------------------- -.. automodule:: finn.custom_op.fpgadataflow.fmpadding_batch +.. automodule:: finn.custom_op.fpgadataflow.fmpadding_pixel :members: :undoc-members: :show-inheritance: -finn.custom\_op.fpgadataflow.globalaccpool\_batch ---------------------------------------------------- +finn.custom\_op.fpgadataflow.globalaccpool +------------------------------------------- -.. automodule:: finn.custom_op.fpgadataflow.globalaccpool_batch +.. automodule:: finn.custom_op.fpgadataflow.globalaccpool :members: :undoc-members: :show-inheritance: -finn.custom\_op.fpgadataflow.iodma ------------------------------------- - -.. automodule:: finn.custom_op.fpgadataflow.iodma - :members: - :undoc-members: - :show-inheritance: - -finn.custom\_op.fpgadataflow.labelselect\_batch ------------------------------------------------ +finn.custom\_op.fpgadataflow.labelselect +----------------------------------------- -.. automodule:: finn.custom_op.fpgadataflow.labelselect_batch +.. automodule:: finn.custom_op.fpgadataflow.labelselect :members: :undoc-members: :show-inheritance: @@ -138,7 +128,7 @@ finn.custom\_op.fpgadataflow.lookup :show-inheritance: finn.custom\_op.fpgadataflow.matrixvectoractivation ------------------------------------------------------------ +----------------------------------------------------- .. automodule:: finn.custom_op.fpgadataflow.matrixvectoractivation :members: @@ -146,10 +136,10 @@ finn.custom\_op.fpgadataflow.matrixvectoractivation :show-inheritance: -finn.custom\_op.fpgadataflow.pool\_batch ------------------------------------------------ +finn.custom\_op.fpgadataflow.pool +---------------------------------- -.. automodule:: finn.custom_op.fpgadataflow.pool_batch +.. automodule:: finn.custom_op.fpgadataflow.pool :members: :undoc-members: :show-inheritance: @@ -163,59 +153,50 @@ finn.custom\_op.fpgadataflow.streamingdataflowpartition :show-inheritance: -finn.custom\_op.fpgadataflow.streamingdatawidthconverter\_batch ----------------------------------------------------------------------- - -.. automodule:: finn.custom_op.fpgadataflow.streamingdatawidthconverter_batch - :members: - :undoc-members: - :show-inheritance: - -finn.custom\_op.fpgadataflow.streamingfifo -------------------------------------------------- +finn.custom\_op.fpgadataflow.streamingdatawidthconverter +--------------------------------------------------------- -.. automodule:: finn.custom_op.fpgadataflow.streamingfifo +.. automodule:: finn.custom_op.fpgadataflow.streamingdatawidthconverter :members: :undoc-members: :show-inheritance: -finn.custom\_op.fpgadataflow.streamingmaxpool\_batch ------------------------------------------------------------ +finn.custom\_op.fpgadataflow.streamingeltwise +---------------------------------------------- -.. automodule:: finn.custom_op.fpgadataflow.streamingmaxpool_batch +.. automodule:: finn.custom_op.fpgadataflow.streamingeltwise :members: :undoc-members: :show-inheritance: -finn.custom\_op.fpgadataflow.templates ---------------------------------------------- +finn.custom\_op.fpgadataflow.streamingfifo +------------------------------------------- -.. automodule:: finn.custom_op.fpgadataflow.templates +.. automodule:: finn.custom_op.fpgadataflow.streamingfifo :members: :undoc-members: :show-inheritance: -finn.custom\_op.fpgadataflow.thresholding\_batch -------------------------------------------------------- +finn.custom\_op.fpgadataflow.streamingmaxpool +---------------------------------------------- -.. automodule:: finn.custom_op.fpgadataflow.thresholding_batch +.. automodule:: finn.custom_op.fpgadataflow.streamingmaxpool :members: :undoc-members: :show-inheritance: -finn.custom\_op.fpgadataflow.thresholding\_binary\_search ------------------------------------------------------------ +finn.custom\_op.fpgadataflow.templates +---------------------------------------- -.. automodule:: finn.custom_op.fpgadataflow.thresholding_binary_search +.. automodule:: finn.custom_op.fpgadataflow.templates :members: :undoc-members: :show-inheritance: +finn.custom\_op.fpgadataflow.thresholding +------------------------------------------ -finn.custom\_op.fpgadataflow.tlastmarker ------------------------------------------------ - -.. automodule:: finn.custom_op.fpgadataflow.tlastmarker +.. automodule:: finn.custom_op.fpgadataflow.thresholding :members: :undoc-members: :show-inheritance: diff --git a/docs/finn/source_code/finn.custom_op.fpgadataflow.rtl.rst b/docs/finn/source_code/finn.custom_op.fpgadataflow.rtl.rst new file mode 100644 index 0000000000..b8a7f0d9e9 --- /dev/null +++ b/docs/finn/source_code/finn.custom_op.fpgadataflow.rtl.rst @@ -0,0 +1,46 @@ +***************************** +Custom Op - fpgadataflow.rtl +***************************** + +RTL Custom Op Nodes +=================== + +finn.custom\_op.fpgadataflow.convolutioninputgenerator\_rtl +------------------------------------------------------------ + +.. automodule:: finn.custom_op.fpgadataflow.rtl.convolutioninputgenerator_rtl + :members: + :undoc-members: + :show-inheritance: + +finn.custom\_op.fpgadataflow.fmpadding\_rtl +--------------------------------------------- + +.. automodule:: finn.custom_op.fpgadataflow.rtl.fmpadding_rtl + :members: + :undoc-members: + :show-inheritance: + +finn.custom\_op.fpgadataflow.streamingdatawidthconverter\_rtl +--------------------------------------------------------------- + +.. automodule:: finn.custom_op.fpgadataflow.rtl.streamingdatawidthconverter_rtl + :members: + :undoc-members: + :show-inheritance: + +finn.custom\_op.fpgadataflow.streamingfifo\_rtl +------------------------------------------------- + +.. automodule:: finn.custom_op.fpgadataflow.rtl.streamingfifo_rtl + :members: + :undoc-members: + :show-inheritance: + +finn.custom\_op.fpgadataflow.thresholding\_rtl +------------------------------------------------------- + +.. automodule:: finn.custom_op.fpgadataflow.rtl.thresholding_rtl + :members: + :undoc-members: + :show-inheritance: diff --git a/docs/finn/source_code/finn.transformation.fpgadataflow.rst b/docs/finn/source_code/finn.transformation.fpgadataflow.rst index f7137ae347..f56b5fcf01 100644 --- a/docs/finn/source_code/finn.transformation.fpgadataflow.rst +++ b/docs/finn/source_code/finn.transformation.fpgadataflow.rst @@ -38,10 +38,10 @@ finn.transformation.fpgadataflow.compile\_cppsim :undoc-members: :show-inheritance: -finn.transformation.fpgadataflow.convert\_to\_hls\_layers ----------------------------------------------------------------- +finn.transformation.fpgadataflow.convert\_to\_hw\_layers +---------------------------------------------------------- -.. automodule:: finn.transformation.fpgadataflow.convert_to_hls_layers +.. automodule:: finn.transformation.fpgadataflow.convert_to_hw_layers :members: :undoc-members: :show-inheritance: @@ -79,22 +79,29 @@ finn.transformation.fpgadataflow.externalize\_params :show-inheritance: finn.transformation.fpgadataflow.floorplan ----------------------------------------------------- +----------------------------------------------- .. automodule:: finn.transformation.fpgadataflow.floorplan :members: :undoc-members: :show-inheritance: - finn.transformation.fpgadataflow.hlssynth\_ip ----------------------------------------------------- +----------------------------------------------- .. automodule:: finn.transformation.fpgadataflow.hlssynth_ip :members: :undoc-members: :show-inheritance: +finn.transformation.fpgadataflow.infer\_pixel\_padding\_deconv +---------------------------------------------------------------- + +.. automodule:: finn.transformation.fpgadataflow.infer_pixel_padding_deconv + :members: + :undoc-members: + :show-inheritance: + finn.transformation.fpgadataflow.insert\_dwc --------------------------------------------------- @@ -139,14 +146,6 @@ finn.transformation.fpgadataflow.insert\_tlastmarker :undoc-members: :show-inheritance: -finn.transformation.fpgadataflow.make\_deployment --------------------------------------------------------- - -.. automodule:: finn.transformation.fpgadataflow.make_deployment - :members: - :undoc-members: - :show-inheritance: - finn.transformation.fpgadataflow.make\_pynq\_driver ---------------------------------------------------------- @@ -238,16 +237,24 @@ finn.transformation.fpgadataflow.set\_folding :undoc-members: :show-inheritance: -finn.transformation.fpgadataflow.synth\_ooc +finn.transformation.fpgadataflow.specialize\_layers ------------------------------------------------------- +.. automodule:: finn.transformation.fpgadataflow.specialize_layers + :members: + :undoc-members: + :show-inheritance: + +finn.transformation.fpgadataflow.synth\_ooc +--------------------------------------------- + .. automodule:: finn.transformation.fpgadataflow.synth_ooc :members: :undoc-members: :show-inheritance: finn.transformation.fpgadataflow.template\_driver -------------------------------------------------- +--------------------------------------------------- .. automodule:: finn.transformation.fpgadataflow.template_driver :members: @@ -255,7 +262,7 @@ finn.transformation.fpgadataflow.template\_driver :show-inheritance: finn.transformation.fpgadataflow.templates -------------------------------------------------- +----------------------------------------------- .. automodule:: finn.transformation.fpgadataflow.templates :members: diff --git a/docs/finn/source_code/finn.transformation.rst b/docs/finn/source_code/finn.transformation.rst index f42b595a50..1f4c9e495b 100644 --- a/docs/finn/source_code/finn.transformation.rst +++ b/docs/finn/source_code/finn.transformation.rst @@ -49,6 +49,14 @@ qonnx.transformation.change\_3d\_tensors\_to\_4d :undoc-members: :show-inheritance: +qonnx.transformation.change\_batchsize +---------------------------------------- + +.. automodule:: qonnx.transformation.change_batchsize + :members: + :undoc-members: + :show-inheritance: + qonnx.transformation.change\_datalayout -------------------------------------------- @@ -83,6 +91,14 @@ qonnx.transformation.double\_to\_single\_float :undoc-members: :show-inheritance: +qonnx.transformation.expose\_intermediate +------------------------------------------ + +.. automodule:: qonnx.transformation.expose_intermediate + :members: + :undoc-members: + :show-inheritance: + qonnx.transformation.extend\_partition ------------------------------------------ @@ -99,9 +115,16 @@ qonnx.transformation.extract\_conv\_bias :undoc-members: :show-inheritance: +qonnx.transformation.extract\_quant\_scale\_zeropt +------------------------------------------------ + +.. automodule:: qonnx.transformation.extract_quant_scale_zeropt + :members: + :undoc-members: + :show-inheritance: qonnx.transformation.fold\_constants ------------------------------------------- +-------------------------------------- .. automodule:: qonnx.transformation.fold_constants :members: @@ -117,7 +140,7 @@ qonnx.transformation.gemm\_to\_matmul :show-inheritance: qonnx.transformation.general ----------------------------------- +------------------------------ .. automodule:: qonnx.transformation.general :members: @@ -165,7 +188,7 @@ qonnx.transformation.lower\_convs\_to\_matmul :show-inheritance: qonnx.transformation.make\_input\_chanlast ------------------------------------------- +--------------------------------------------- .. automodule:: qonnx.transformation.make_input_chanlast :members: @@ -180,6 +203,29 @@ qonnx.transformation.merge\_onnx\_models :undoc-members: :show-inheritance: +qonnx.transformation.pruning +------------------------------ + +.. automodule:: qonnx.transformation.pruning + :members: + :undoc-members: + :show-inheritance: + +qonnx.transformation.qcdq\_to\_qonnx +---------------------------------------- + +.. automodule:: qonnx.transformation.qcdq_to_qonnx + :members: + :undoc-members: + :show-inheritance: + +qonnx.transformation.qonnx\_to\_qcdq +------------------------------------- + +.. automodule:: qonnx.transformation.qonnx_to_qcdq + :members: + :undoc-members: + :show-inheritance: qonnx.transformation.quant\_constant\_folding ---------------------------------------------- @@ -189,6 +235,13 @@ qonnx.transformation.quant\_constant\_folding :undoc-members: :show-inheritance: +qonnx.transformation.quantize\_graph +------------------------------------- + +.. automodule:: qonnx.transformation.quantize_graph + :members: + :undoc-members: + :show-inheritance: qonnx.transformation.rebalance\_conv ---------------------------------------- @@ -199,13 +252,28 @@ qonnx.transformation.rebalance\_conv :show-inheritance: qonnx.transformation.remove -------------------------------------- +---------------------------- .. automodule:: qonnx.transformation.remove :members: :undoc-members: :show-inheritance: +qonnx.transformation.resize\_conv\_to\_deconv +----------------------------------------------- + +.. automodule:: qonnx.transformation.resize_conv_to_deconv + :members: + :undoc-members: + :show-inheritance: + +qonnx.transformation.subpixel\_to\_deconv +----------------------------------------------- + +.. automodule:: qonnx.transformation.subpixel_to_deconv + :members: + :undoc-members: + :show-inheritance: finn.transformation.move\_reshape ---------------------------------------- diff --git a/docs/finn/source_code/finn.util.rst b/docs/finn/source_code/finn.util.rst index aebd0604f4..2ec1502441 100644 --- a/docs/finn/source_code/finn.util.rst +++ b/docs/finn/source_code/finn.util.rst @@ -31,8 +31,16 @@ qonnx.util.config :undoc-members: :show-inheritance: +qonnx.util.convert +-------------------- + +.. automodule:: qonnx.util.convert + :members: + :undoc-members: + :show-inheritance: + qonnx.util.exec\_qonnx ----------------------- +------------------------ .. automodule:: qonnx.util.exec_qonnx :members: @@ -55,6 +63,37 @@ qonnx.util.onnx :undoc-members: :show-inheritance: +qonnx.util.prune\_channels +--------------------------- + +.. automodule:: qonnx.util.prune_channels + :members: + :undoc-members: + :show-inheritance: + +qonnx.util.random\_reseed +-------------------------- + +.. automodule:: qonnx.util.random_reseed + :members: + :undoc-members: + :show-inheritance: + +qonnx.util.range\_analysis +--------------------------- + +.. automodule:: qonnx.util.range_analysis + :members: + :undoc-members: + :show-inheritance: + +qonnx.util.test +-------------------- + +.. automodule:: qonnx.util.test + :members: + :undoc-members: + :show-inheritance: qonnx.util.to\_channels\_last ------------------------------ @@ -81,8 +120,6 @@ finn.util.create :undoc-members: :show-inheritance: - - finn.util.data\_packing ------------------------------ diff --git a/docs/finn/verification.rst b/docs/finn/verification.rst index e1a9ac4b31..4b1821aca1 100644 --- a/docs/finn/verification.rst +++ b/docs/finn/verification.rst @@ -4,7 +4,7 @@ Functional Verification *********************** -.. image:: ../../notebooks/end2end_example/bnn-pynq/verification.png +.. image:: ../../notebooks/end2end_example/bnn-pynq/verification.svg :scale: 70% :align: center diff --git a/docs/requirements.txt b/docs/requirements.txt index 26c05d0025..85bc1d0dcd 100644 --- a/docs/requirements.txt +++ b/docs/requirements.txt @@ -2,7 +2,9 @@ brevitas@git+https://github.com/Xilinx/brevitas@master#egg=brevitas_examples dataclasses-json==0.5.7 docutils==0.17.1 gspread==3.6.0 +importlib_resources IPython +matplotlib netron pytest pyverilator@git+https://github.com/maltanar/pyverilator@master#egg=pyverilator @@ -10,4 +12,5 @@ qonnx@git+https://github.com/fastmachinelearning/qonnx@main#egg=qonnx sphinx_rtd_theme==0.5.0 torch torchvision +tqdm vcdvcd diff --git a/requirements.txt b/requirements.txt index e03eff2c98..c2973f9432 100644 --- a/requirements.txt +++ b/requirements.txt @@ -7,7 +7,7 @@ ipython==8.12.2 numpy==1.24.1 onnx==1.13.0 onnxoptimizer -onnxruntime==1.15.0 +onnxruntime==1.16.1 pre-commit==3.3.2 protobuf==3.20.3 psutil==5.9.4 From 13afb71ee71e3f6e5120d6c2517fb7c8145c98f3 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Thu, 14 Mar 2024 10:31:37 +0000 Subject: [PATCH 592/665] updated mvu_rtl checker --- .../fpgadataflow/specialize_layers.py | 17 +++-------------- 1 file changed, 3 insertions(+), 14 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/specialize_layers.py b/src/finn/transformation/fpgadataflow/specialize_layers.py index 94c0a87c03..25dfc0cc87 100644 --- a/src/finn/transformation/fpgadataflow/specialize_layers.py +++ b/src/finn/transformation/fpgadataflow/specialize_layers.py @@ -123,7 +123,8 @@ def _determine_impl_style(node): return "rtl" else: warn_str = """There is no RTL variant for %s. The node will automatically be - set to HLS variant.""" % ( + set to HLS variant. Please check the bit-widths to be <= 8 and ensure the + thresholds are implemented as standalone layer""" % ( node.name, ) warnings.warn(warn_str) @@ -210,21 +211,9 @@ def _mvu_rtl_possible(n): and DataType[getCustomOp(n).get_nodeattr("inputDataType")].min() < 0 ) weight_width_in_range = DataType[getCustomOp(n).get_nodeattr("weightDataType")].bitwidth() <= 8 - folding_supported = ( - getCustomOp(n).get_nodeattr("MH") % getCustomOp(n).get_nodeattr("PE") == 0 - ) and (getCustomOp(n).get_nodeattr("MW") % getCustomOp(n).get_nodeattr("SIMD") == 0) - targets_dsp = getCustomOp(n).get_nodeattr("resType") in ["dsp", "auto"] - external_memmode = getCustomOp(n).get_nodeattr("mem_mode") in ["decoupled", "external"] no_activation = getCustomOp(n).get_nodeattr("noActivation") == 1 - return ( - inp_width_in_range - and weight_width_in_range - and folding_supported - and targets_dsp - and external_memmode - and no_activation - ) + return inp_width_in_range and weight_width_in_range and no_activation class SpecializeLayers(Transformation): From f1d4c2c7fdde83197dd6dc5b98789848ae4f924e Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Thu, 14 Mar 2024 10:34:44 +0000 Subject: [PATCH 593/665] [rtl mvau]: added more info to assertion message --- .../custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py index dccdc67d00..24de50e8c3 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py @@ -193,7 +193,7 @@ def _resolve_impl_style(self, fpgapart): assert ( self.get_nodeattr("resType") != "lut" ), """LUT-based RTL-MVU implementation currently not supported! - Please change resType for {}""".format( + Please change resType for {} to 'dsp' or consider switching to HLS-based MVAU!""".format( self.onnx_node.name ) From 15ce083cf0a03e14267f0a46b53216feb8ac28bf Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Thu, 14 Mar 2024 10:49:57 +0000 Subject: [PATCH 594/665] minor fix to if-branch --- src/finn/transformation/fpgadataflow/specialize_layers.py | 1 + 1 file changed, 1 insertion(+) diff --git a/src/finn/transformation/fpgadataflow/specialize_layers.py b/src/finn/transformation/fpgadataflow/specialize_layers.py index 25dfc0cc87..bac92b27e1 100644 --- a/src/finn/transformation/fpgadataflow/specialize_layers.py +++ b/src/finn/transformation/fpgadataflow/specialize_layers.py @@ -128,6 +128,7 @@ def _determine_impl_style(node): node.name, ) warnings.warn(warn_str) + return "hls" if rtl_variant: return "rtl" From cfdf0bcec20fe6b4524c9efe642b97070ff54011 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Thu, 14 Mar 2024 10:49:57 +0000 Subject: [PATCH 595/665] minor fix to if-branch --- src/finn/transformation/fpgadataflow/specialize_layers.py | 1 + 1 file changed, 1 insertion(+) diff --git a/src/finn/transformation/fpgadataflow/specialize_layers.py b/src/finn/transformation/fpgadataflow/specialize_layers.py index 25dfc0cc87..bac92b27e1 100644 --- a/src/finn/transformation/fpgadataflow/specialize_layers.py +++ b/src/finn/transformation/fpgadataflow/specialize_layers.py @@ -128,6 +128,7 @@ def _determine_impl_style(node): node.name, ) warnings.warn(warn_str) + return "hls" if rtl_variant: return "rtl" From f87d29074cf802e5d9ae055e7f09f5c1296c88f2 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Thu, 14 Mar 2024 15:45:54 +0000 Subject: [PATCH 596/665] [tests]: fixed assert statement for fifo characterization --- tests/fpgadataflow/test_fpgadataflow_mvau.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_mvau.py b/tests/fpgadataflow/test_fpgadataflow_mvau.py index 7f76cf0af1..4be9e2bc2f 100644 --- a/tests/fpgadataflow/test_fpgadataflow_mvau.py +++ b/tests/fpgadataflow/test_fpgadataflow_mvau.py @@ -581,7 +581,7 @@ def test_fpgadataflow_mvau_large_depth_decoupled_mode_rtlsim( def test_mvau_fifocharacterize_rtlsim( mem_mode, idt, wdt, act, nf, sf, mw, mh, preferred_impl_style ): - if preferred_impl_style == "rtl" and (mem_mode == "const" or act is not None): + if preferred_impl_style == "rtl" and (mem_mode == "internal_embedded" or act is not None): pytest.skip("RTL-MVAU doesn't support const mem mode or embedded activations") if nf == -1: nf = mh @@ -627,8 +627,8 @@ def test_mvau_fifocharacterize_rtlsim( chrc_out = node_inst.get_nodeattr("io_chrc_out") assert chrc_in.shape == (1, 2 * exp_total_cycles) assert chrc_out.shape == (1, 2 * exp_total_cycles) - # first sf cycles should read input continuously - assert (chrc_in[0, :sf] == list(range(1, sf + 1))).all() + # total number of transactions == 2*SF + assert chrc_in[0, -1] == 2 * sf # all outputs should be produced within the exp n of cycles assert chrc_out[0, exp_total_cycles] == nf From a6e4376d3599c806fa9eba367cfec1067ea5f2d5 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Thu, 14 Mar 2024 15:45:54 +0000 Subject: [PATCH 597/665] [tests]: fixed assert statement for fifo characterization --- tests/fpgadataflow/test_fpgadataflow_mvau.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_mvau.py b/tests/fpgadataflow/test_fpgadataflow_mvau.py index 7f76cf0af1..4be9e2bc2f 100644 --- a/tests/fpgadataflow/test_fpgadataflow_mvau.py +++ b/tests/fpgadataflow/test_fpgadataflow_mvau.py @@ -581,7 +581,7 @@ def test_fpgadataflow_mvau_large_depth_decoupled_mode_rtlsim( def test_mvau_fifocharacterize_rtlsim( mem_mode, idt, wdt, act, nf, sf, mw, mh, preferred_impl_style ): - if preferred_impl_style == "rtl" and (mem_mode == "const" or act is not None): + if preferred_impl_style == "rtl" and (mem_mode == "internal_embedded" or act is not None): pytest.skip("RTL-MVAU doesn't support const mem mode or embedded activations") if nf == -1: nf = mh @@ -627,8 +627,8 @@ def test_mvau_fifocharacterize_rtlsim( chrc_out = node_inst.get_nodeattr("io_chrc_out") assert chrc_in.shape == (1, 2 * exp_total_cycles) assert chrc_out.shape == (1, 2 * exp_total_cycles) - # first sf cycles should read input continuously - assert (chrc_in[0, :sf] == list(range(1, sf + 1))).all() + # total number of transactions == 2*SF + assert chrc_in[0, -1] == 2 * sf # all outputs should be produced within the exp n of cycles assert chrc_out[0, exp_total_cycles] == nf From 79ca5726938195cd8a14917e2f267db80493b988 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Thu, 14 Mar 2024 16:15:07 +0000 Subject: [PATCH 598/665] [rtl mvau]: update mem_mode options --- .../custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py index 24de50e8c3..a00ba72717 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py @@ -101,7 +101,7 @@ def execute_node(self, context, graph): inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) reset_rtlsim(sim) toggle_clk(sim) - if mem_mode in ["external", "decoupled"]: + if mem_mode in ["external", "internal_decoupled"]: wnbits = self.get_weightstream_width() export_wdt = self.get_weight_datatype() wei = npy_to_rtlsim_input( From e2e0a4ccdb64b1f94da58d6add799343db9be457 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Thu, 14 Mar 2024 16:15:20 +0000 Subject: [PATCH 599/665] [tests]: clean-up --- tests/fpgadataflow/test_fpgadataflow_mvau.py | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_mvau.py b/tests/fpgadataflow/test_fpgadataflow_mvau.py index 4be9e2bc2f..2a22f3fc41 100644 --- a/tests/fpgadataflow/test_fpgadataflow_mvau.py +++ b/tests/fpgadataflow/test_fpgadataflow_mvau.py @@ -671,7 +671,7 @@ def test_fpgadataflow_rtl_mvau(mh, mw, pe, simd, idt, wdt, part, clk_ns): output_matmul = oxe.execute_onnx(model, input_dict)["global_out"] # Create MVAU (HLS) - model = model.transform(to_hw.InferQuantizedMatrixVectorActivation(mem_mode="decoupled")) + model = model.transform(to_hw.InferQuantizedMatrixVectorActivation()) model = model.transform(GiveUniqueNodeNames()) # Apply convert-to-rtl step @@ -684,9 +684,7 @@ def test_fpgadataflow_rtl_mvau(mh, mw, pe, simd, idt, wdt, part, clk_ns): "MVAU_rtl_0": { "PE": pe, "SIMD": simd, - "mem_mode": "decoupled", "resType": "dsp", - "preferred_impl_style": "rtl", }, } model = model.transform(ApplyConfig(folding_config)) @@ -710,7 +708,6 @@ def test_fpgadataflow_rtl_mvau(mh, mw, pe, simd, idt, wdt, part, clk_ns): model = model.transform(HLSSynthIP()) model = model.transform(PrepareRTLSim()) output_mvau_rtl = oxe.execute_onnx(model, input_dict)["global_out"] - assert ( output_matmul == output_mvau_rtl ).all(), "Output of ONNX model not matching output of node-by-node RTLsim!" From f38e7edd6754b54f4dc29bc8d7e618d5b7bdef50 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Thu, 14 Mar 2024 16:15:07 +0000 Subject: [PATCH 600/665] [rtl mvau]: update mem_mode options --- .../custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py index 24de50e8c3..a00ba72717 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py @@ -101,7 +101,7 @@ def execute_node(self, context, graph): inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) reset_rtlsim(sim) toggle_clk(sim) - if mem_mode in ["external", "decoupled"]: + if mem_mode in ["external", "internal_decoupled"]: wnbits = self.get_weightstream_width() export_wdt = self.get_weight_datatype() wei = npy_to_rtlsim_input( From 7c8dc6ddad4e1fa815c776288105862b40f665ab Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Thu, 14 Mar 2024 16:15:20 +0000 Subject: [PATCH 601/665] [tests]: clean-up --- tests/fpgadataflow/test_fpgadataflow_mvau.py | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_mvau.py b/tests/fpgadataflow/test_fpgadataflow_mvau.py index 4be9e2bc2f..2a22f3fc41 100644 --- a/tests/fpgadataflow/test_fpgadataflow_mvau.py +++ b/tests/fpgadataflow/test_fpgadataflow_mvau.py @@ -671,7 +671,7 @@ def test_fpgadataflow_rtl_mvau(mh, mw, pe, simd, idt, wdt, part, clk_ns): output_matmul = oxe.execute_onnx(model, input_dict)["global_out"] # Create MVAU (HLS) - model = model.transform(to_hw.InferQuantizedMatrixVectorActivation(mem_mode="decoupled")) + model = model.transform(to_hw.InferQuantizedMatrixVectorActivation()) model = model.transform(GiveUniqueNodeNames()) # Apply convert-to-rtl step @@ -684,9 +684,7 @@ def test_fpgadataflow_rtl_mvau(mh, mw, pe, simd, idt, wdt, part, clk_ns): "MVAU_rtl_0": { "PE": pe, "SIMD": simd, - "mem_mode": "decoupled", "resType": "dsp", - "preferred_impl_style": "rtl", }, } model = model.transform(ApplyConfig(folding_config)) @@ -710,7 +708,6 @@ def test_fpgadataflow_rtl_mvau(mh, mw, pe, simd, idt, wdt, part, clk_ns): model = model.transform(HLSSynthIP()) model = model.transform(PrepareRTLSim()) output_mvau_rtl = oxe.execute_onnx(model, input_dict)["global_out"] - assert ( output_matmul == output_mvau_rtl ).all(), "Output of ONNX model not matching output of node-by-node RTLsim!" From a17bb19e03f639b8c4f029681a60163cba44e2cf Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Thu, 14 Mar 2024 16:43:27 +0000 Subject: [PATCH 602/665] [renaming]: renamed VectorVectorActivation to VVAU due to buffer overflow PyVerilator for long names --- .../analysis/fpgadataflow/res_estimation.py | 2 +- src/finn/custom_op/fpgadataflow/__init__.py | 4 ++-- src/finn/custom_op/fpgadataflow/hls/__init__.py | 6 ++---- .../fpgadataflow/convert_to_hw_layers.py | 8 ++++---- .../transformation/fpgadataflow/set_folding.py | 17 +++++------------ tests/fpgadataflow/test_minimize_bit_width.py | 16 ++++++++-------- 6 files changed, 22 insertions(+), 31 deletions(-) diff --git a/src/finn/analysis/fpgadataflow/res_estimation.py b/src/finn/analysis/fpgadataflow/res_estimation.py index c2d0cf7048..a6be1f1f53 100644 --- a/src/finn/analysis/fpgadataflow/res_estimation.py +++ b/src/finn/analysis/fpgadataflow/res_estimation.py @@ -62,7 +62,7 @@ def res_estimation_complete(model): if is_hls_node(node) or is_rtl_node(node): inst = registry.getCustomOp(node) op_type = node.op_type - if op_type.startswith("MVAU") or op_type.startswith("VectorVectorActivation"): + if op_type.startswith("MVAU") or op_type.startswith("VVAU"): orig_restype = inst.get_nodeattr("resType") res_dict[node.name] = [] inst.set_nodeattr("resType", "dsp") diff --git a/src/finn/custom_op/fpgadataflow/__init__.py b/src/finn/custom_op/fpgadataflow/__init__.py index 6154bdc924..aed2ab7fe1 100644 --- a/src/finn/custom_op/fpgadataflow/__init__.py +++ b/src/finn/custom_op/fpgadataflow/__init__.py @@ -53,7 +53,7 @@ from finn.custom_op.fpgadataflow.streamingmaxpool import StreamingMaxPool from finn.custom_op.fpgadataflow.thresholding import Thresholding from finn.custom_op.fpgadataflow.upsampler import UpsampleNearestNeighbour -from finn.custom_op.fpgadataflow.vectorvectoractivation import VectorVectorActivation +from finn.custom_op.fpgadataflow.vectorvectoractivation import VVAU custom_op = dict() @@ -62,7 +62,7 @@ custom_op["MVAU"] = MVAU custom_op["StreamingFIFO"] = StreamingFIFO custom_op["Thresholding"] = Thresholding -custom_op["VectorVectorActivation"] = VectorVectorActivation +custom_op["VVAU"] = VVAU custom_op["StreamingDataflowPartition"] = StreamingDataflowPartition custom_op["AddStreams"] = AddStreams diff --git a/src/finn/custom_op/fpgadataflow/hls/__init__.py b/src/finn/custom_op/fpgadataflow/hls/__init__.py index 6e465fd0f2..405c47a08d 100644 --- a/src/finn/custom_op/fpgadataflow/hls/__init__.py +++ b/src/finn/custom_op/fpgadataflow/hls/__init__.py @@ -51,9 +51,7 @@ from finn.custom_op.fpgadataflow.hls.thresholding_hls import Thresholding_hls from finn.custom_op.fpgadataflow.hls.tlastmarker_hls import TLastMarker_hls from finn.custom_op.fpgadataflow.hls.upsampler_hls import UpsampleNearestNeighbour_hls -from finn.custom_op.fpgadataflow.hls.vectorvectoractivation_hls import ( - VectorVectorActivation_hls, -) +from finn.custom_op.fpgadataflow.hls.vectorvectoractivation_hls import VVAU_hls custom_op = dict() @@ -80,4 +78,4 @@ custom_op["TLastMarker_hls"] = TLastMarker_hls custom_op["UpsampleNearestNeighbour_hls"] = UpsampleNearestNeighbour_hls custom_op["MVAU_hls"] = MVAU_hls -custom_op["VectorVectorActivation_hls"] = VectorVectorActivation_hls +custom_op["VVAU_hls"] = VVAU_hls diff --git a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py index fdb892e911..59c9f6f38d 100644 --- a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py +++ b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py @@ -1636,7 +1636,7 @@ def apply(self, model): model.set_tensor_shape(mt_output, mt_out_shape) # create and insert new VectorVectorActivation node new_node = helper.make_node( - "VectorVectorActivation", + "VVAU", [mm_input, mm_weight, mt_thres], [mt_output], domain="finn.custom_op.fpgadataflow", @@ -1651,7 +1651,7 @@ def apply(self, model): outputDataType=odt.name, ActVal=actval, noActivation=0, - name="VectorVectorActivation_" + n.name, + name="VVAU_" + n.name, ) graph.node.insert(node_ind, new_node) # remove old nodes @@ -1665,7 +1665,7 @@ def apply(self, model): model.set_tensor_shape(mm_output, mm_out_shape) # create and insert new VVAU node new_node = helper.make_node( - "VectorVectorActivation", + "VVAU", [mm_input, mm_weight], [mm_output], domain="finn.custom_op.fpgadataflow", @@ -1680,7 +1680,7 @@ def apply(self, model): outputDataType=odt.name, ActVal=0, noActivation=1, - name="VectorVectorActivation_" + n.name, + name="VVAU_" + n.name, ) graph.node.insert(node_ind, new_node) # remove old node diff --git a/src/finn/transformation/fpgadataflow/set_folding.py b/src/finn/transformation/fpgadataflow/set_folding.py index bff64d3885..10dd829971 100644 --- a/src/finn/transformation/fpgadataflow/set_folding.py +++ b/src/finn/transformation/fpgadataflow/set_folding.py @@ -119,7 +119,7 @@ def apply(self, model): ] # these ops are preceded by depthwise SWG and have special behavior, # as explained in the SetFolding docstring - depthwise_op_exceptions = ["VectorVectorActivation_hls", "Pool_hls"] + depthwise_op_exceptions = ["VVAU_hls", "Pool_hls"] for node in graph.node: if not (is_hls_node(node) or is_rtl_node(node)): continue @@ -157,18 +157,14 @@ def apply(self, model): self.optimize_attribute_val(node_inst, max_pe, "PE") elif op_type in depthwise_op_exceptions: # init/reset SIMD of VVAU - if op_type == "VectorVectorActivation_hls": + if op_type == "VVAU_hls": node_inst.set_nodeattr("SIMD", 1) max_pe = node_inst.get_nodeattr("Channels") self.optimize_attribute_val(node_inst, max_pe, "PE") # increase SIMD for VVAU once PE is exhausted pe = node_inst.get_nodeattr("PE") cyc = node_inst.get_exp_cycles() - if ( - op_type == "VectorVectorActivation_hls" - and pe == max_pe - and cyc > self.target_cycles_per_frame - ): + if op_type == "VVAU_hls" and pe == max_pe and cyc > self.target_cycles_per_frame: max_simd = np.prod(node_inst.get_nodeattr("Kernel")) self.optimize_attribute_val(node_inst, max_simd, "SIMD") # also set the folding of the upsteam DW SWU @@ -179,15 +175,12 @@ def apply(self, model): swu_node_inst.set_nodeattr("SIMD", pe) # enable parallel_window mode of RTL SWG if needed if swu_node.op_type == "ConvolutionInputGenerator_rtl": - if ( - op_type == "VectorVectorActivation" - and node_inst.get_nodeattr("SIMD") > 1 - ): + if op_type.startswith("VVAU") and node_inst.get_nodeattr("SIMD") > 1: swu_node_inst.set_nodeattr("parallel_window", 1) else: swu_node_inst.set_nodeattr("parallel_window", 0) else: - if op_type == "VectorVectorActivation_hls": + if op_type == "VVAU_hls": ksize = np.prod(node_inst.get_nodeattr("Kernel")) elif op_type == "Pool_hls": ksize = node_inst.get_nodeattr("KernelSize") diff --git a/tests/fpgadataflow/test_minimize_bit_width.py b/tests/fpgadataflow/test_minimize_bit_width.py index 2b765610ab..4b26e7ac00 100644 --- a/tests/fpgadataflow/test_minimize_bit_width.py +++ b/tests/fpgadataflow/test_minimize_bit_width.py @@ -37,7 +37,7 @@ from typing import Optional, Union from finn.custom_op.fpgadataflow.matrixvectoractivation import MVAU -from finn.custom_op.fpgadataflow.vectorvectoractivation import VectorVectorActivation +from finn.custom_op.fpgadataflow.vectorvectoractivation import VVAU from finn.transformation.fpgadataflow.minimize_accumulator_width import ( MinimizeAccumulatorWidth, ) @@ -52,7 +52,7 @@ def make_unit_test_model(wdt: DataType, idt: DataType, tdt: Optional[DataType] = inp = helper.make_tensor_value_info("inp", TensorProto.FLOAT, [1, 32, 32, 288]) outp = helper.make_tensor_value_info("outp", TensorProto.FLOAT, [1, 32, 32, 64]) layer1 = helper.make_node( - "VectorVectorActivation", + "VVAU", ["inp", "params0", "thresh0"] if tdt is not None else ["inp", "params0"], ["hid"], domain="finn.custom_op.fpgadataflow", @@ -170,7 +170,7 @@ def test_minimize_weight_bit_width(wdt: DataType, rww: bool): # If runtime-writeable weights, specify as a node attribute for node in model.graph.node: inst = getCustomOp(node) - if isinstance(inst, (MVAU, VectorVectorActivation)): + if isinstance(inst, (MVAU, VVAU)): inst.set_nodeattr("runtime_writeable_weights", int(rww)) # Apply the optimization @@ -179,14 +179,14 @@ def test_minimize_weight_bit_width(wdt: DataType, rww: bool): # Iterate through each node to make sure it functioned properly for node in model.graph.node: inst = getCustomOp(node) - if isinstance(inst, (MVAU, VectorVectorActivation)): + if isinstance(inst, (MVAU, VVAU)): cur_wdt = DataType[inst.get_nodeattr("weightDataType")] exp_wdt = def_wdt if rww else wdt assert cur_wdt.bitwidth() == exp_wdt.bitwidth(), "Mismatched data types" def calculate_accumulator_bit_width( - inst: Union[MVAU, VectorVectorActivation], model: ModelWrapper + inst: Union[MVAU, VVAU], model: ModelWrapper ) -> Union[DataType, IntType]: """Calculate the accumulator bit width using the closed-form expressions derived in `Quantized Neural Networks for Low-Precision Accumulation @@ -208,7 +208,7 @@ def phi(x: float) -> float: # modify the weights based on if the node is a VVAU or MVAU if isinstance(inst, MVAU): K = inst.get_nodeattr("MW") # matrix_width = num_inputs - elif isinstance(inst, VectorVectorActivation): + elif isinstance(inst, VVAU): k_h, k_w = inst.get_nodeattr("Kernel") K = k_h * k_w # size of kernels = num_inputs fm = inst.get_nodeattr("Channels") @@ -275,7 +275,7 @@ def test_minimize_accumulator_width(wdt: DataType, idt: DataType, tdt: DataType, # If runtime-writeable weights, specify as a node attribute for node in model.graph.node: inst = getCustomOp(node) - if isinstance(inst, (MVAU, VectorVectorActivation)): + if isinstance(inst, (MVAU, VVAU)): inst.set_nodeattr("runtime_writeable_weights", int(rww)) cur_adt = DataType[inst.get_nodeattr("accDataType")] assert cur_adt.bitwidth() == def_adt.bitwidth(), "Default data type is incorrect" @@ -286,7 +286,7 @@ def test_minimize_accumulator_width(wdt: DataType, idt: DataType, tdt: DataType, # Iterate through each node to make sure it functioned properly for node in model.graph.node: inst = getCustomOp(node) - if isinstance(inst, (MVAU, VectorVectorActivation)): + if isinstance(inst, (MVAU, VVAU)): cur_adt = DataType[inst.get_nodeattr("accDataType")] cur_odt = DataType[inst.get_nodeattr("outputDataType")] # Calculating expected accumulator bit width using a closed-form expression From 8a48cac635c9312be542e3425223e9335b71672f Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Thu, 14 Mar 2024 16:44:13 +0000 Subject: [PATCH 603/665] [hls vvau]: renamed layer and added method to instantiate ip --- .../hls/vectorvectoractivation_hls.py | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/hls/vectorvectoractivation_hls.py b/src/finn/custom_op/fpgadataflow/hls/vectorvectoractivation_hls.py index c7f0576495..dc38a18f4e 100644 --- a/src/finn/custom_op/fpgadataflow/hls/vectorvectoractivation_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/vectorvectoractivation_hls.py @@ -31,11 +31,11 @@ from qonnx.core.datatype import DataType from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend -from finn.custom_op.fpgadataflow.vectorvectoractivation import VectorVectorActivation +from finn.custom_op.fpgadataflow.vectorvectoractivation import VVAU from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy -class VectorVectorActivation_hls(VectorVectorActivation, HLSBackend): +class VVAU_hls(VVAU, HLSBackend): """Corresponds to finn-hlslib Vector_Vector_Activate_Batch function""" def __init__(self, onnx_node, **kwargs): @@ -43,7 +43,7 @@ def __init__(self, onnx_node, **kwargs): def get_nodeattr_types(self): my_attrs = {} - my_attrs.update(VectorVectorActivation.get_nodeattr_types(self)) + my_attrs.update(VVAU.get_nodeattr_types(self)) my_attrs.update(HLSBackend.get_nodeattr_types(self)) return my_attrs @@ -464,3 +464,12 @@ def get_verilog_top_module_intf_names(self): if runtime_writable: intf_names["axilite"] = ["s_axilite"] return intf_names + + def instantiate_ip(self, cmd): + # instantiate the HLS IP + vlnv = self.get_nodeattr("ip_vlnv") + node_name = self.onnx_node.name + if self.get_nodeattr("mem_mode") == "internal_decoupled": + cmd.append("create_bd_cell -type ip -vlnv %s /%s/%s" % (vlnv, node_name, node_name)) + else: + cmd.append("create_bd_cell -type ip -vlnv %s %s" % (vlnv, node_name)) From 400c04350846680caf315140199ec9e70658249a Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Thu, 14 Mar 2024 16:44:57 +0000 Subject: [PATCH 604/665] [rtl vvau]: RTL VVAU custom-op --- .../custom_op/fpgadataflow/rtl/__init__.py | 2 + .../rtl/vectorvectoractivation_rtl.py | 301 ++++++++++++++++++ 2 files changed, 303 insertions(+) create mode 100644 src/finn/custom_op/fpgadataflow/rtl/vectorvectoractivation_rtl.py diff --git a/src/finn/custom_op/fpgadataflow/rtl/__init__.py b/src/finn/custom_op/fpgadataflow/rtl/__init__.py index b7a798be98..1996539042 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/__init__.py +++ b/src/finn/custom_op/fpgadataflow/rtl/__init__.py @@ -35,6 +35,7 @@ StreamingDataWidthConverter_rtl, ) from finn.custom_op.fpgadataflow.rtl.streamingfifo_rtl import StreamingFIFO_rtl +from finn.custom_op.fpgadataflow.rtl.vectorvectoractivation_rtl import VVAU_rtl custom_op = dict() @@ -45,3 +46,4 @@ custom_op["StreamingDataWidthConverter_rtl"] = StreamingDataWidthConverter_rtl custom_op["StreamingFIFO_rtl"] = StreamingFIFO_rtl custom_op["MVAU_rtl"] = MVAU_rtl +custom_op["VVAU_rtl"] = VVAU_rtl diff --git a/src/finn/custom_op/fpgadataflow/rtl/vectorvectoractivation_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/vectorvectoractivation_rtl.py new file mode 100644 index 0000000000..c138cf05d5 --- /dev/null +++ b/src/finn/custom_op/fpgadataflow/rtl/vectorvectoractivation_rtl.py @@ -0,0 +1,301 @@ +# Copyright (C) 2024, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of FINN nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import numpy as np +import os +from pyverilator.util.axi_utils import reset_rtlsim, toggle_clk +from qonnx.core.datatype import DataType + +from finn.custom_op.fpgadataflow.rtlbackend import RTLBackend +from finn.custom_op.fpgadataflow.vectorvectoractivation import VVAU +from finn.util.basic import get_rtlsim_trace_depth, make_build_dir +from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy +from finn.util.fpgadataflow import is_versal + +try: + from pyverilator import PyVerilator +except ModuleNotFoundError: + PyVerilator = None + + +class VVAU_rtl(VVAU, RTLBackend): + """Class that corresponds to finn-rtl Vector Vector Unit.""" + + def __init__(self, onnx_node, **kwargs): + super().__init__(onnx_node, **kwargs) + + def get_nodeattr_types(self): + my_attrs = {} + my_attrs.update(VVAU.get_nodeattr_types(self)) + my_attrs.update(RTLBackend.get_nodeattr_types(self)) + return my_attrs + + def execute_node(self, context, graph): + mode = self.get_nodeattr("exec_mode") + mem_mode = self.get_nodeattr("mem_mode") + node = self.onnx_node + + if mode == "cppsim": + VVAU.execute_node(self, context, graph) + elif mode == "rtlsim": + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + # create a npy file fore each input of the node (in_ind is input index) + in_ind = 0 + for inputs in node.input: + # it is assumed that the first input of the node is the data input + # the second input are the weights + # the third input are the thresholds + if in_ind == 0: + assert ( + str(context[inputs].dtype) == "float32" + ), """Input datatype is + not float32 as expected.""" + expected_inp_shape = self.get_folded_input_shape() + reshaped_input = context[inputs].reshape(expected_inp_shape) + if self.get_input_datatype() == DataType["BIPOLAR"]: + # store bipolar activations as binary + reshaped_input = (reshaped_input + 1) / 2 + export_idt = DataType["BINARY"] + else: + export_idt = self.get_input_datatype() + # make copy before saving the array + reshaped_input = reshaped_input.copy() + np.save( + os.path.join(code_gen_dir, "input_{}.npy".format(in_ind)), + reshaped_input, + ) + elif in_ind > 2: + raise Exception("Unexpected input found for VectorVectorActivation") + in_ind += 1 + + sim = self.get_rtlsim() + nbits = self.get_instream_width() + inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) + reset_rtlsim(sim) + toggle_clk(sim) + + if mem_mode in ["external", "internal_decoupled"]: + wnbits = self.get_weightstream_width() + export_wdt = self.get_weight_datatype() + # we have converted bipolar weights to binary for export, + # so use it as such for weight generation + if self.get_weight_datatype() == DataType["BIPOLAR"]: + export_wdt = DataType["BINARY"] + wei = npy_to_rtlsim_input( + "{}/weights.npy".format(code_gen_dir), export_wdt, wnbits + ) + dim_h, dim_w = self.get_nodeattr("Dim") + num_w_reps = dim_h * dim_w + + io_dict = { + "inputs": {"in0": inp, "weights": wei * num_w_reps}, + "outputs": {"out": []}, + } + self.rtlsim_multi_io(sim, io_dict) + output = io_dict["outputs"]["out"] + else: + output = self.rtlsim(sim, inp) + odt = self.get_output_datatype() + target_bits = odt.bitwidth() + packed_bits = self.get_outstream_width() + out_npy_path = "{}/output.npy".format(code_gen_dir) + out_shape = self.get_folded_output_shape() + rtlsim_output_to_npy(output, out_npy_path, odt, out_shape, packed_bits, target_bits) + + # load and reshape output + output = np.load(out_npy_path) + oshape = self.get_normal_output_shape() + output = np.asarray([output], dtype=np.float32).reshape(*oshape) + context[node.output[0]] = output + else: + raise Exception( + """Invalid value for attribute exec_mode! Is currently set to: {} + has to be set to one of the following value ("cppsim", "rtlsim")""".format( + mode + ) + ) + + def lut_estimation(self): + return 0 + + def dsp_estimation(self): + Q = self.get_nodeattr("SIMD") + return int(np.ceil(Q / 3)) + + def instantiate_ip(self, cmd): + # instantiate the RTL IP + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + rtllib_dir = os.path.join(os.environ["FINN_ROOT"], "finn-rtllib/mvu/") + sourcefiles = [ + os.path.join(code_gen_dir, self.get_nodeattr("gen_top_module") + "_wrapper.v"), + rtllib_dir + "mvu_vvu_axi.sv", + rtllib_dir + "replay_buffer.sv", + rtllib_dir + "mvu_4sx4u.sv", + rtllib_dir + "mvu_vvu_8sx9_dsp58.sv", + rtllib_dir + "mvu_8sx8u_dsp48.sv", + ] + for f in sourcefiles: + cmd.append("add_files -norecurse %s" % (f)) + cmd.append( + "create_bd_cell -type hier -reference %s /%s/%s" + % ( + self.get_nodeattr("gen_top_module"), + self.onnx_node.name, + self.onnx_node.name, + ) + ) + + def generate_hdl(self, model, fpgapart, clk): + # Generate params as part of IP preparation + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + self.generate_params(model, code_gen_dir) + + template_path, code_gen_dict = self.prepare_codegen_default(fpgapart, clk) + # add general parameters to dictionary + code_gen_dict["$MODULE_NAME_AXI_WRAPPER$"] = [self.get_verilog_top_module_name()] + # save top module name so we can refer to it after this node has been renamed + # (e.g. by GiveUniqueNodeNames(prefix) during MakeZynqProject) + self.set_nodeattr("gen_top_module", self.get_verilog_top_module_name()) + + # apply code generation to template + with open(template_path, "r") as f: + template_wrapper = f.read() + for key in code_gen_dict: + # transform list into long string separated by '\n' + code_gen_line = "\n".join(code_gen_dict[key]) + template_wrapper = template_wrapper.replace(key, code_gen_line) + with open( + os.path.join(code_gen_dir, self.get_nodeattr("gen_top_module") + "_wrapper.v"), + "w", + ) as f: + f.write(template_wrapper.replace("$FORCE_BEHAVIORAL$", str(0))) + with open( + os.path.join(code_gen_dir, self.get_nodeattr("gen_top_module") + "_wrapper_sim.v"), + "w", + ) as f: + f.write(template_wrapper.replace("$FORCE_BEHAVIORAL$", str(1))) + + # set ipgen_path and ip_path so that HLS-Synth transformation + # and stich_ip transformation do not complain + self.set_nodeattr("ipgen_path", code_gen_dir) + self.set_nodeattr("ip_path", code_gen_dir) + + def _resolve_segment_len(self, clk): + # Insert pipeline registers in the DSP58 chain to meet target clock frequency + # ~0.741 ns seems the worst-case delay through first DSP + # ~0.605 ns seems to be (on average) delay for all subsequent DSPs + # clk >= (critical_path_dsps - 1) * 0.605 + 0.741 + assert ( + clk > 0.741 + ), """Infeasible clk target of {} ns has been set, + consider lowering the targeted clock frequency!""".format( + clk + ) + critical_path_dsps = np.floor((clk - 0.741) / 0.605 + 1) + max_chain_len = np.ceil(self.get_nodeattr("SIMD") / 3) + dsp_chain_len = critical_path_dsps if critical_path_dsps < max_chain_len else max_chain_len + return dsp_chain_len + + def _resolve_impl_style(self, fpgapart): + # Based on target device and activation/weight-width, choose the + # supported RTL compute core + assert ( + self.get_nodeattr("resType") != "lut" + ), """LUT-based RTL-VVU implementation currently not supported! + Please change resType for {} to 'dsp' or consider switching to HLS-based VVAU!""".format( + self.onnx_node.name + ) + is_versal_family = is_versal(fpgapart) + assert ( + is_versal_family + ), "DSP-based (RTL) VVU currently only supported on Versal (DSP58) devices" + + return "mvu_vvu_8sx9_dsp58" + + def prepare_codegen_default(self, fpgapart, clk): + template_path = os.environ["FINN_ROOT"] + "/finn-rtllib/mvu/mvu_vvu_axi_wrapper.v" + + code_gen_dict = {} + code_gen_dict["$IS_MVU$"] = [str(0)] + code_gen_dict["$COMPUTE_CORE$"] = [self._resolve_impl_style(fpgapart)] + mw = int(np.prod(self.get_nodeattr("Kernel"))) + code_gen_dict["$MW$"] = [str(mw)] + code_gen_dict["$MH$"] = [str(self.get_nodeattr("Channels"))] + code_gen_dict["$PE$"] = [str(self.get_nodeattr("PE"))] + code_gen_dict["$SIMD$"] = [str(self.get_nodeattr("SIMD"))] + code_gen_dict["$ACTIVATION_WIDTH$"] = [str(self.get_input_datatype(0).bitwidth())] + code_gen_dict["$WEIGHT_WIDTH$"] = [str(self.get_input_datatype(1).bitwidth())] + code_gen_dict["$ACCU_WIDTH$"] = [str(self.get_output_datatype().bitwidth())] + code_gen_dict["$SIGNED_ACTIVATIONS$"] = ( + [str(1)] if (self.get_input_datatype(0).min() < 0) else [str(0)] + ) + code_gen_dict["$SEGMENTLEN$"] = [str(self._resolve_segment_len(clk))] + + return template_path, code_gen_dict + + def prepare_rtlsim(self): + """Creates a Verilator emulation library for the RTL code generated + for this node, sets the rtlsim_so attribute to its path and returns + a PyVerilator wrapper around it.""" + + if PyVerilator is None: + raise ImportError("Installation of PyVerilator is required.") + + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + # Path to (System-)Verilog files used by top-module & path to top-module + verilog_paths = [code_gen_dir, os.environ["FINN_ROOT"] + "/finn-rtllib/mvu"] + verilog_files = [self.get_nodeattr("gen_top_module") + "_wrapper_sim.v"] + + # build the Verilator emu library + sim = PyVerilator.build( + verilog_files, + build_dir=make_build_dir("pyverilator_" + self.onnx_node.name + "_"), + verilog_path=verilog_paths, + trace_depth=get_rtlsim_trace_depth(), + top_module_name=self.get_verilog_top_module_name(), + ) + # save generated lib filename in attribute + self.set_nodeattr("rtlsim_so", sim.lib._name) + + return sim + + def get_all_verilog_paths(self): + "Return list of all folders containing Verilog code for this node." + + code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + # Path to (System-)Verilog files used by top-module & path to top-module + verilog_paths = [code_gen_dir, os.environ["FINN_ROOT"] + "/finn-rtllib/mvu"] + return verilog_paths + + def get_verilog_top_filename(self): + "Return the Verilog top module filename for this node." + + verilog_file = "{}/{}_wrapper.v".format( + self.get_nodeattr("code_gen_dir_ipgen"), self.get_nodeattr("gen_top_module") + ) + return verilog_file From 84243422afbbc772d169b1f48ed06091b859da63 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Thu, 14 Mar 2024 16:46:08 +0000 Subject: [PATCH 605/665] [vvau]: changed weight file generation and execution_node; accounted for possiblity of VVAU being either RTL/HLS based (influences weight storage) or parent layer being Im2Col-variant or SWG_rtl/hls --- .../fpgadataflow/vectorvectoractivation.py | 71 +++++++++++++------ 1 file changed, 49 insertions(+), 22 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index c5ec7e0648..efe78a6339 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -43,7 +43,7 @@ from finn.util.data_packing import numpy_to_hls_code, pack_innermost_dim_as_hex_string -class VectorVectorActivation(HWCustomOp): +class VVAU(HWCustomOp): """Abstraction layer for HW implementation of VectorVectorActivation layers.""" def __init__(self, onnx_node, **kwargs): @@ -105,9 +105,6 @@ def get_nodeattr_types(self): my_attrs.update(super().get_nodeattr_types()) return my_attrs - def base_op_type(self): - return "VectorVectorActivation" - def _infer_sparse_weight_tensor(self, W_conv, k_h, k_w, channels): W_sparse = np.zeros((channels, channels, k_h, k_w), dtype=np.float32) for ch in range(channels): @@ -124,7 +121,17 @@ def execute_node(self, context, graph): (_, dim_h, dim_w, _) = in_act.shape (k_h, k_w) = self.get_nodeattr("Kernel") channels = self.get_nodeattr("Channels") - pe = self.get_nodeattr("PE") + producer = [x for x in graph.node if x.output[0] == node.input[0]] + exec_mode = self.get_nodeattr("exec_mode") + if ( + not bool(producer) + or producer[0].op_type == "ConvolutionInputGenerator_hls" + or (producer[0].op_type == "ConvolutionInputGenerator_rtl" and exec_mode == "rtlsim") + ): + pe = self.get_nodeattr("PE") + else: + pe = channels + # Reorder the input activations. Note that PE gets interleaved by the SWG, # so we have to untangle and for simplicity of computation assume pe=1. # Note that PE has no effect on the QONNX node @@ -183,7 +190,14 @@ def infer_node_datatype(self, model): def get_input_datatype(self, ind=0): """Returns FINN DataType of input.""" - return DataType[self.get_nodeattr("inputDataType")] + # when performing FIFO insertion on an FC layer with ext weights, the ind + # parameter can be > 0 (referring to the weights) so handle that here + if ind == 0: + return DataType[self.get_nodeattr("inputDataType")] + elif ind == 1: + return DataType[self.get_nodeattr("weightDataType")] + else: + raise Exception("Undefined input ind for this layer type") def get_weight_datatype(self): """Returns FINN DataType of weights.""" @@ -198,7 +212,7 @@ def get_output_datatype(self, ind=0): return DataType[self.get_nodeattr("outputDataType")] def get_instream_width(self, ind=0): - i_bits = self.get_input_datatype().bitwidth() + i_bits = self.get_input_datatype(ind).bitwidth() simd = self.get_nodeattr("SIMD") pe = self.get_nodeattr("PE") in_width = i_bits * simd * pe @@ -499,7 +513,7 @@ def minimize_accumulator_width(self, model): # if the thresholds can be used to determine range, then adjust the range # according to the known values of the thresholds if thresholds is not None: - threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds) + threshold_tensor = self.get_hw_compatible_threshold_tensor(thresholds) # set threshold datatype (and accumulator datatype implicitly) min_threshold = thresholds.min() max_threshold = thresholds.max() @@ -508,7 +522,7 @@ def minimize_accumulator_width(self, model): warnings.warn("Clipping some thresholds in %s" % self.onnx_node.name) thresholds = np.clip(thresholds, acc_min, acc_max) model.set_initializer(self.onnx_node.input[2], thresholds) - threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds) + threshold_tensor = self.get_hw_compatible_threshold_tensor(thresholds) min_threshold = thresholds.min() max_threshold = thresholds.max() acc_min = min(min_threshold, acc_min) @@ -566,7 +580,7 @@ def minimize_weight_bit_width(self, model): self.set_nodeattr("weightDataType", wdt.name) return DataType[self.get_nodeattr("weightDataType")] - def get_hls_compatible_threshold_tensor(self, orig_thres_matrix): + def get_hw_compatible_threshold_tensor(self, orig_thres_matrix): """Convert the original numpy weight matrix orig_weight_matrix into a form suitable for passing to the hlslib call: * ensure MH % PE == 0 @@ -691,6 +705,8 @@ def make_weight_file(self, weights, weight_file_mode, weight_file_name): weight_tensor_simd_flipped = np.flip(weight_tensor_unflipped, axis=-1) # PE flip for saving weights in .dat weight_tensor_pe_flipped = np.flip(weight_tensor_unflipped, axis=-2) + # SIMD & PE flip + weight_tensor_pe_simd_flipped = np.flip(weight_tensor_pe_flipped, axis=-1) # reshape weight tensor (simd_flipped and pe_flipped) to desired shape pe = self.get_nodeattr("PE") simd = self.get_nodeattr("SIMD") @@ -700,19 +716,32 @@ def make_weight_file(self, weights, weight_file_mode, weight_file_name): # flipped weight_tensor_pe_flipped = weight_tensor_pe_flipped.reshape(1, -1, pe * simd) weight_tensor_pe_flipped = weight_tensor_pe_flipped.copy() + # SIMD & PE flipped + weight_tensor_pe_simd_flipped = weight_tensor_pe_simd_flipped.reshape(1, -1, pe * simd) + weight_tensor_pe_simd_flipped = weight_tensor_pe_simd_flipped.copy() if weight_file_mode == "decoupled_npy": # save weight stream into npy for cppsim - np.save(weight_file_name, weight_tensor_simd_flipped) + if self.onnx_node.op_type == "VVAU_rtl": + weight_tensor_unflipped = weight_tensor_unflipped.reshape(1, -1, pe * simd) + weight_tensor_unflipped = weight_tensor_unflipped.copy() + np.save(weight_file_name, weight_tensor_unflipped) + else: + np.save(weight_file_name, weight_tensor_simd_flipped) elif weight_file_mode == "decoupled_verilog_dat": # convert weight values into hexstring weight_width = self.get_weightstream_width() # pad to nearest 4 bits to get hex strings weight_width_padded = roundup_to_integer_multiple(weight_width, 4) - weight_tensor_pe_flipped = pack_innermost_dim_as_hex_string( - weight_tensor_pe_flipped, export_wdt, weight_width_padded, prefix="" - ) + if self.onnx_node.op_type == "VVAU_rtl": + weight_arr = pack_innermost_dim_as_hex_string( + weight_tensor_pe_simd_flipped, export_wdt, weight_width_padded, prefix="" + ) + else: + weight_arr = pack_innermost_dim_as_hex_string( + weight_tensor_pe_flipped, export_wdt, weight_width_padded, prefix="" + ) # add zeroes to pad out file to 1024 entries - weight_stream = weight_tensor_pe_flipped.flatten() + weight_stream = weight_arr.flatten() weight_stream = weight_stream.copy() with open(weight_file_name, "w") as f: for val in weight_stream: @@ -772,7 +801,7 @@ def generate_params(self, model, path): if len(self.onnx_node.input) > 2: thresholds = model.get_initializer(self.onnx_node.input[2]) if thresholds is not None: - threshold_tensor = self.get_hls_compatible_threshold_tensor(thresholds) + threshold_tensor = self.get_hw_compatible_threshold_tensor(thresholds) # use UINT32 threshold export for bipolar times bipolar inp_is_bipolar = self.get_input_datatype() == DataType["BIPOLAR"] wt_is_bipolar = self.get_weight_datatype() == DataType["BIPOLAR"] @@ -884,11 +913,9 @@ def code_generation_ipi(self): "create_bd_intf_pin -mode Slave " "-vlnv xilinx.com:interface:axis_rtl:1.0 /%s/%s" % (node_name, din_name) ) - # instantiate the hls ip - cmd.append( - "create_bd_cell -type ip -vlnv %s /%s/%s" - % (self.get_nodeattr("ip_vlnv"), node_name, node_name) - ) + # Instantiate either the HLS or RTL IP depending on operator + self.instantiate_ip(cmd) + # instantiate a streamer and connect it to the HLS IP strm_vlnv = "amd.com:finn:memstream:1.0" strm_inst = node_name + "_wstrm" @@ -959,7 +986,7 @@ def code_generation_ipi(self): cmd.append("save_bd_design") elif mem_mode == "internal_embedded" or mem_mode == "external": # base class impl sufficient for internal_embedded/external modes - return super().code_generation_ipi() + self.instantiate_ip(cmd) else: raise Exception("Unrecognized mem_mode for VectorVectorActivation") return cmd From 0f25d43a2938dc1950fb56a1bcd050fdc5493090 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Thu, 14 Mar 2024 16:46:41 +0000 Subject: [PATCH 606/665] [transform]: added support for converting to VVAU-RTL layer --- .../fpgadataflow/specialize_layers.py | 36 +++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/specialize_layers.py b/src/finn/transformation/fpgadataflow/specialize_layers.py index bac92b27e1..080f7ca5a2 100644 --- a/src/finn/transformation/fpgadataflow/specialize_layers.py +++ b/src/finn/transformation/fpgadataflow/specialize_layers.py @@ -37,7 +37,7 @@ from finn.util.fpgadataflow import is_versal -def _determine_impl_style(node): +def _determine_impl_style(node, fpgapart): optype = node.op_type # check if there is an HLS or RTL variant or both @@ -59,6 +59,11 @@ def _determine_impl_style(node): return "rtl" else: return "hls" + elif optype == "VVAU": + if _vvu_rtl_possible(node, fpgapart): + return "rtl" + else: + return "hls" return "rtl" # but if no rtl variant, set impl_style to hls elif hls_variant: @@ -129,6 +134,18 @@ def _determine_impl_style(node): ) warnings.warn(warn_str) return "hls" + elif optype == "VVAU": + if _vvu_rtl_possible(node, fpgapart): + return "rtl" + else: + warn_str = """There is no RTL variant for %s. The node will automatically be + set to HLS variant. Please check the bit-widths to be <= 8 and ensure the + thresholds are implemented as standalone layer. Note that the RTL-variant + of this layer is only supported on Versal boards""" % ( + node.name, + ) + warnings.warn(warn_str) + return "hls" if rtl_variant: return "rtl" @@ -217,6 +234,21 @@ def _mvu_rtl_possible(n): return inp_width_in_range and weight_width_in_range and no_activation +def _vvu_rtl_possible(n, fpgapart): + # Checks whether RTL-based VVU is supported + in_width_in_range = ( + DataType[getCustomOp(n).get_nodeattr("inputDataType")].bitwidth() <= 8 + ) or ( + DataType[getCustomOp(n).get_nodeattr("inputDataType")].bitwidth() == 9 + and DataType[getCustomOp(n).get_nodeattr("inputDataType")].min() < 0 + ) + weight_width_in_range = DataType[getCustomOp(n).get_nodeattr("weightDataType")].bitwidth() <= 8 + is_versal_family = is_versal(fpgapart) + no_activation = getCustomOp(n).get_nodeattr("noActivation") == 1 + + return in_width_in_range and weight_width_in_range and is_versal_family and no_activation + + class SpecializeLayers(Transformation): """Specialize all layers to either HLS or RTL variants""" @@ -233,7 +265,7 @@ def apply(self, model): if not node.domain == "finn.custom_op.fpgadataflow": continue node_ind += 1 - impl_style = _determine_impl_style(node) + impl_style = _determine_impl_style(node, self.fpgapart) optype = node.op_type + "_" + impl_style new_node = helper.make_node( From 94f0830861092b52b55b01d787f47157d6272ea1 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Thu, 14 Mar 2024 17:55:15 +0000 Subject: [PATCH 607/665] [test]: added test for RTL-VVAU --- tests/fpgadataflow/test_fpgadataflow_vvau.py | 201 ++++++++++++++++++- 1 file changed, 192 insertions(+), 9 deletions(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_vvau.py b/tests/fpgadataflow/test_fpgadataflow_vvau.py index eb521f965a..98df27e3dd 100644 --- a/tests/fpgadataflow/test_fpgadataflow_vvau.py +++ b/tests/fpgadataflow/test_fpgadataflow_vvau.py @@ -32,21 +32,39 @@ from onnx import TensorProto, helper from qonnx.core.datatype import DataType from qonnx.core.modelwrapper import ModelWrapper +from qonnx.custom_op.general.im2col import compute_conv_output_dim from qonnx.custom_op.general.multithreshold import multithreshold from qonnx.custom_op.registry import getCustomOp -from qonnx.transformation.general import GiveUniqueNodeNames +from qonnx.transformation.general import ( + ApplyConfig, + GiveReadableTensorNames, + GiveUniqueNodeNames, +) from qonnx.transformation.infer_datatypes import InferDataTypes from qonnx.transformation.infer_shapes import InferShapes +from qonnx.transformation.lower_convs_to_matmul import LowerConvsToMatMul from qonnx.util.basic import gen_finn_dt_tensor, qonnx_make_model import finn.core.onnx_exec as oxe +import finn.transformation.fpgadataflow.convert_to_hw_layers as to_hw from finn.analysis.fpgadataflow.exp_cycles_per_layer import exp_cycles_per_layer from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim +from finn.transformation.fpgadataflow.create_dataflow_partition import ( + CreateDataflowPartition, +) +from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP +from finn.transformation.fpgadataflow.minimize_accumulator_width import ( + MinimizeAccumulatorWidth, +) +from finn.transformation.fpgadataflow.minimize_weight_bit_width import ( + MinimizeWeightBitWidth, +) from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode +from finn.transformation.fpgadataflow.set_fifo_depths import InsertAndSetFIFODepths from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers @@ -117,7 +135,7 @@ def _make_single_vvau_modelwrapper( actval = 0 VVAU_node = helper.make_node( - "VectorVectorActivation", + "VVAU", node_inp_list, ["outp"], domain="finn.custom_op.fpgadataflow", @@ -158,10 +176,6 @@ def _make_single_vvau_modelwrapper( return model -def prepare_inputs(input_tensor): - return {"inp": input_tensor} - - # input datatype @pytest.mark.parametrize("idt", [DataType["BIPOLAR"], DataType["UINT4"]]) # weight datatype @@ -233,10 +247,12 @@ def test_fpgadataflow_vvau( model = _make_single_vvau_modelwrapper( W, pe, simd, k_h, k_w, channels, dim_h, dim_w, wdt, idt, odt, T, tdt, mem_mode ) + model = model.transform(GiveUniqueNodeNames()) + model = model.transform(GiveReadableTensorNames()) input_dict = prepare_inputs(x_vvau) - y_hwop = oxe.execute_onnx(model, input_dict)["outp"] - model = model.transform(SpecializeLayers()) + y_hwop = oxe.execute_onnx(model, input_dict)["global_out"] + model = model.transform(SpecializeLayers("xc7z020clg400-1")) if exec_mode == "cppsim": model = model.transform(SetExecMode("cppsim")) @@ -272,7 +288,7 @@ def test_fpgadataflow_vvau( # signed offset y_expected += act.min() - y_produced = oxe.execute_onnx(model, input_dict, return_full_exec_context=False)["outp"] + y_produced = oxe.execute_onnx(model, input_dict, return_full_exec_context=False)["global_out"] assert (y_hwop == y_expected).all(), "VVAU HW-op mismatches with golden output!" assert (y_produced == y_expected).all(), "VVAU specialized-op mismatches with golden output!" @@ -285,3 +301,170 @@ def test_fpgadataflow_vvau( exp_cycles = exp_cycles_dict[node.name] assert np.isclose(exp_cycles, cycles_rtlsim, atol=10) assert exp_cycles != 0 + + +def make_single_dw_conv_modelwrapper(conv_config, idt, wdt): + kernel_size, in_feature_dim, in_chn = conv_config + stride = 1 + pad = 0 + + out_feature_dim = compute_conv_output_dim(in_feature_dim, kernel_size, stride, pad) + group = out_chn = in_chn + + conv_param_shape = [out_chn, 1, kernel_size, kernel_size] + input_shape = [1, in_chn, in_feature_dim, in_feature_dim] + output_shape = [1, out_chn, out_feature_dim, out_feature_dim] + + conv_config = {} + conv_config["dilations"] = [1, 1] + conv_config["group"] = group + conv_config["kernel_shape"] = [kernel_size, kernel_size] + conv_config["pads"] = [pad, pad, pad, pad] + conv_config["strides"] = [stride, stride] + + ifm = helper.make_tensor_value_info("ifm", TensorProto.FLOAT, input_shape) + ofm = helper.make_tensor_value_info("ofm", TensorProto.FLOAT, output_shape) + weights = [helper.make_tensor_value_info("weights", TensorProto.FLOAT, conv_param_shape)] + + modelproto = qonnx_make_model( + helper.make_graph( + name="conv_test", + inputs=[ifm], + outputs=[ofm], + value_info=weights, + nodes=[helper.make_node("Conv", ["ifm", "weights"], ["ofm"], **conv_config)], + ) + ) + + model = ModelWrapper(modelproto) + model.set_tensor_datatype("ifm", idt) + model.set_tensor_datatype("weights", wdt) + model.set_initializer("weights", gen_finn_dt_tensor(wdt, conv_param_shape)) + + model = model.transform(InferShapes()) + model = model.transform(InferDataTypes()) + + return model + + +def prepare_inputs(input_tensor): + return {"global_in": input_tensor} + + +# kernel size (square) +@pytest.mark.parametrize("kernel_size", [3]) +# IFM size (square) +@pytest.mark.parametrize("in_feature_dim", [5]) +# input channels +@pytest.mark.parametrize("in_chn", [4]) +# input datatype +@pytest.mark.parametrize("idt", [DataType["INT8"]]) +# weight datatype +@pytest.mark.parametrize("wdt", [DataType["INT6"]]) +# targeted board +@pytest.mark.parametrize("part", ["xcvm1802-vsvd1760-2MP-e-S"]) +# pe +@pytest.mark.parametrize("pe", [1, 2, 4]) +# simd +@pytest.mark.parametrize("simd", [1, 3, 9]) +@pytest.mark.fpgadataflow +@pytest.mark.slow +@pytest.mark.vivado +def test_fpgadataflow_vvau_rtl(kernel_size, in_feature_dim, in_chn, idt, wdt, part, pe, simd): + # Create depthwise-separable convolution + conv_config = (kernel_size, in_feature_dim, in_chn) + model = make_single_dw_conv_modelwrapper(conv_config, idt, wdt) + model = model.transform(GiveUniqueNodeNames()) + model = model.transform(GiveReadableTensorNames()) + + # Obtain golden reference output + golden_in = gen_finn_dt_tensor( + model.get_tensor_datatype("global_in"), model.get_tensor_shape("global_in") + ) + input_dict = prepare_inputs(golden_in) + golden_out = oxe.execute_onnx(model, input_dict, return_full_exec_context=True)["global_out"] + + # Convert to HLS custom-op first + model = model.transform(LowerConvsToMatMul()) + model = model.transform(to_hw.InferConvInpGen()) + model = model.transform(to_hw.InferVectorVectorActivation()) + model = model.transform(GiveUniqueNodeNames()) + model = model.transform(GiveReadableTensorNames()) + + output_vvau_hw = oxe.execute_onnx(model, input_dict, return_full_exec_context=True)[ + "global_out" + ] + assert ( + golden_out == output_vvau_hw + ).all(), "Output of ONNX model not matching output of HW-ops!" + + # Obtain second reference from HLS-based VVAU layer + model = model.transform(SpecializeLayers(part)) + model = model.transform(GiveUniqueNodeNames()) + + # Apply folding (i.e. specify to use DSPs) + folding_config = { + "Defaults": {}, + "ConvolutionInputGenerator_rtl_0": { + "SIMD": pe, + "parallel_window": 1, + }, + "VVAU_rtl_0": { + "PE": pe, + "SIMD": simd, + "resType": "dsp", + }, + } + model = model.transform(ApplyConfig(folding_config)) + model = model.transform(GiveUniqueNodeNames()) + model = model.transform(MinimizeWeightBitWidth()) + model = model.transform(MinimizeAccumulatorWidth()) + # make sure the changed datatypes are propagated through the network + model = model.transform(InferDataTypes()) + + # Run CPPsim + model = model.transform(SetExecMode("cppsim")) + model = model.transform(PrepareCppSim()) + model = model.transform(CompileCppSim()) + output_vvau_cppsim = oxe.execute_onnx(model, input_dict)["global_out"] + assert ( + golden_out == output_vvau_cppsim + ).all(), "Output of ONNX model not matching output of node-by-node CPPsim!" + + # Run node-by-node RTLsim + model = model.transform(SetExecMode("rtlsim")) + model = model.transform(PrepareIP(part, 5)) + model = model.transform(HLSSynthIP()) + model = model.transform(PrepareRTLSim()) + output_vvau_rtlsim = oxe.execute_onnx(model, input_dict, return_full_exec_context=True)[ + "global_out" + ] + + assert ( + golden_out == output_vvau_rtlsim + ).all(), "Output of ONNX model not matching output of specialized HW-ops!" + + # Stitched-IP RTLsim + model = model.transform(CreateDataflowPartition()) + partition_model_path = getCustomOp( + model.get_nodes_by_op_type("StreamingDataflowPartition")[0] + ).get_nodeattr("model") + partitioned_model = ModelWrapper(partition_model_path) + # FIFOs needed for stitched-ip RTLsim, DWC needed for VVU operating on SIMD parallelism + partitioned_model = partitioned_model.transform(InsertAndSetFIFODepths(part, 5)) + partitioned_model = partitioned_model.transform(PrepareIP(part, 5)) + partitioned_model = partitioned_model.transform(HLSSynthIP()) + partitioned_model = partitioned_model.transform(CreateStitchedIP(part, 5)) + # set top-level prop for stitched-ip rtlsim and launch + partitioned_model.set_metadata_prop("exec_mode", "rtlsim") + # transpose input since we're now simulating HW layers (NCHW --> NHWC) + input_dict["global_in"] = np.transpose(input_dict["global_in"], (0, 2, 3, 1)) + output_vvau_stitched = oxe.execute_onnx( + partitioned_model, input_dict, return_full_exec_context=True + )["global_out"] + # tranpose hardware-generated outputs NHWC -> NCHW to be comparable + output_vvau_stitched = output_vvau_stitched.transpose(0, 3, 1, 2) + + assert ( + golden_out == output_vvau_stitched + ).all(), "Output of ONNX model not matching output of stitched-IP RTL model!" From 3fe3e06052d8f11258e31009d5e52e8f30aeb3c3 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Wed, 13 Mar 2024 13:49:15 +0000 Subject: [PATCH 608/665] Broadcast quantization scale to channel dimension Added workaround to enable per tensor quantization based on channel dimensions, providing consistency with per channel quantization. --- .../qonnx/qonnx_activation_handlers.py | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/src/finn/transformation/qonnx/qonnx_activation_handlers.py b/src/finn/transformation/qonnx/qonnx_activation_handlers.py index 323e391df4..2617f803e7 100644 --- a/src/finn/transformation/qonnx/qonnx_activation_handlers.py +++ b/src/finn/transformation/qonnx/qonnx_activation_handlers.py @@ -515,7 +515,8 @@ def _calculate_thresholds(self): if bit_width == 1.0: thresholds = np.empty([1, 1], dtype=np_default_dtype) thresholds[0] = 0 - return thresholds + num_thresholds = 1 + else: if narrow: num_distinct_values = 2**bit_width - 1 @@ -537,13 +538,13 @@ def _calculate_thresholds(self): for t in range(num_thresholds): thresholds[c][t] = min_threshold[c] + step[c] * t - # ToDo: The index 1 needs to be changed to -1 for the channels last format - num_output_channels = self._model.get_tensor_shape(self._q_node.output[0])[1] - final_shape = (num_output_channels, num_thresholds) - if thresholds.shape != final_shape: - thresholds = np.broadcast_to(thresholds, final_shape) + # ToDo: The index 1 needs to be changed to -1 for the channels last format + num_output_channels = self._model.get_tensor_shape(self._q_node.output[0])[1] + final_shape = (num_output_channels, num_thresholds) + if thresholds.shape != final_shape: + thresholds = np.broadcast_to(thresholds, final_shape) - return thresholds + return thresholds def _calculate_act_scale(self): # Gather parameters From 88f59b32c55cfb5f099e7f955180a8fbe3f0b9ee Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Fri, 15 Mar 2024 10:55:18 +0000 Subject: [PATCH 609/665] Broadcast per tensor threshold weights to all channels --- .../custom_op/fpgadataflow/rtl/thresholding_rtl.py | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py index f30a305dfe..eaef2f30f2 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py @@ -188,6 +188,12 @@ def prepare_codegen_rtl_values(self, model): o_bitwidth = DataType[output_data_type].bitwidth() num_channels = self.get_nodeattr("NumChannels") # number of channels + # If a single threshold value is found, broadcast it to all channels + n_thres_steps = self.get_nodeattr("numSteps") + expected_shape = (num_channels, n_thres_steps) + if t_packed.shape != expected_shape: + t_packed = np.broadcast_to(t_packed, expected_shape) + channel_fold = int(num_channels / pe) for stage in range(o_bitwidth): @@ -507,6 +513,12 @@ def make_weight_file(self, weights, weight_file_mode, weight_file_name): ch = self.get_nodeattr("NumChannels") n_thres_steps = self.get_nodeattr("numSteps") + # If a single threshold value is found, broadcast it to all channels + n_thres_steps = self.get_nodeattr("numSteps") + expected_shape = (ch, n_thres_steps) + if weights.shape != expected_shape: + weights = np.broadcast_to(weights, expected_shape) + width_padded = roundup_to_integer_multiple(weights.shape[1], 4) weight_padded = np.zeros((weights.shape[0], width_padded)) weight_padded[: weights.shape[0], :n_thres_steps] = weights From e7d5af3d2644a4591c52ccb22d3d236845cef2be Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Fri, 15 Mar 2024 11:00:08 +0000 Subject: [PATCH 610/665] Revert "Broadcast quantization scale to channel dimension" This reverts commit 3fe3e06052d8f11258e31009d5e52e8f30aeb3c3. --- .../qonnx/qonnx_activation_handlers.py | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/src/finn/transformation/qonnx/qonnx_activation_handlers.py b/src/finn/transformation/qonnx/qonnx_activation_handlers.py index 2617f803e7..323e391df4 100644 --- a/src/finn/transformation/qonnx/qonnx_activation_handlers.py +++ b/src/finn/transformation/qonnx/qonnx_activation_handlers.py @@ -515,8 +515,7 @@ def _calculate_thresholds(self): if bit_width == 1.0: thresholds = np.empty([1, 1], dtype=np_default_dtype) thresholds[0] = 0 - num_thresholds = 1 - + return thresholds else: if narrow: num_distinct_values = 2**bit_width - 1 @@ -538,13 +537,13 @@ def _calculate_thresholds(self): for t in range(num_thresholds): thresholds[c][t] = min_threshold[c] + step[c] * t - # ToDo: The index 1 needs to be changed to -1 for the channels last format - num_output_channels = self._model.get_tensor_shape(self._q_node.output[0])[1] - final_shape = (num_output_channels, num_thresholds) - if thresholds.shape != final_shape: - thresholds = np.broadcast_to(thresholds, final_shape) + # ToDo: The index 1 needs to be changed to -1 for the channels last format + num_output_channels = self._model.get_tensor_shape(self._q_node.output[0])[1] + final_shape = (num_output_channels, num_thresholds) + if thresholds.shape != final_shape: + thresholds = np.broadcast_to(thresholds, final_shape) - return thresholds + return thresholds def _calculate_act_scale(self): # Gather parameters From c0a1d73ffe09c141133cb9a71fc962e4ac0d71cf Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 15 Mar 2024 11:38:48 +0000 Subject: [PATCH 611/665] [mvau]: update mem_mode name --- src/finn/custom_op/fpgadataflow/matrixvectoractivation.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index db8a04b0d3..92e7b169c6 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -859,7 +859,7 @@ def get_verilog_top_module_intf_names(self): sname = self.hls_sname() if mem_mode == "external": intf_names["s_axis"].append(("weights_" + sname, self.get_weightstream_width_padded())) - if mem_mode == "decoupled": + if mem_mode == "internal_decoupled": # only expose axilite interface if attribute is set runtime_writable = self.get_nodeattr("runtime_writeable_weights") == 1 if runtime_writable: From a43d96ccc586e08013d0670da07bc133c605a9f0 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 15 Mar 2024 11:38:48 +0000 Subject: [PATCH 612/665] [mvau]: update mem_mode name --- src/finn/custom_op/fpgadataflow/matrixvectoractivation.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index db8a04b0d3..92e7b169c6 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -859,7 +859,7 @@ def get_verilog_top_module_intf_names(self): sname = self.hls_sname() if mem_mode == "external": intf_names["s_axis"].append(("weights_" + sname, self.get_weightstream_width_padded())) - if mem_mode == "decoupled": + if mem_mode == "internal_decoupled": # only expose axilite interface if attribute is set runtime_writable = self.get_nodeattr("runtime_writeable_weights") == 1 if runtime_writable: From 73bfb3440fb4e590a3da7307ebed3a79b75d3ea3 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 15 Mar 2024 11:46:11 +0000 Subject: [PATCH 613/665] [vvau]: moved/added get_verilog_top_module_intf_names to HW-custom op --- .../fpgadataflow/hls/vectorvectoractivation_hls.py | 13 ------------- .../fpgadataflow/vectorvectoractivation.py | 13 +++++++++++++ 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/hls/vectorvectoractivation_hls.py b/src/finn/custom_op/fpgadataflow/hls/vectorvectoractivation_hls.py index dc38a18f4e..fbae9eb9b8 100644 --- a/src/finn/custom_op/fpgadataflow/hls/vectorvectoractivation_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/vectorvectoractivation_hls.py @@ -452,19 +452,6 @@ def pragmas(self): ("#pragma HLS ARRAY_PARTITION variable=threshs.m_thresholds " "complete dim=3") ) - def get_verilog_top_module_intf_names(self): - intf_names = super().get_verilog_top_module_intf_names() - mem_mode = self.get_nodeattr("mem_mode") - sname = self.hls_sname() - if mem_mode == "external": - intf_names["s_axis"].append(("weights_" + sname, self.get_weightstream_width_padded())) - if mem_mode == "internal_decoupled": - # only expose axilite interface if attribute is set - runtime_writable = self.get_nodeattr("runtime_writeable_weights") == 1 - if runtime_writable: - intf_names["axilite"] = ["s_axilite"] - return intf_names - def instantiate_ip(self, cmd): # instantiate the HLS IP vlnv = self.get_nodeattr("ip_vlnv") diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index efe78a6339..7f1bf72964 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -885,6 +885,19 @@ def derive_characteristic_fxns(self, period): io_dict["inputs"]["weights"] = [0 for i in range(num_w_reps * n_weight_inps)] super().derive_characteristic_fxns(period, override_rtlsim_dict=io_dict) + def get_verilog_top_module_intf_names(self): + intf_names = super().get_verilog_top_module_intf_names() + mem_mode = self.get_nodeattr("mem_mode") + sname = self.hls_sname() + if mem_mode == "external": + intf_names["s_axis"].append(("weights_" + sname, self.get_weightstream_width_padded())) + if mem_mode == "internal_decoupled": + # only expose axilite interface if attribute is set + runtime_writable = self.get_nodeattr("runtime_writeable_weights") == 1 + if runtime_writable: + intf_names["axilite"] = ["s_axilite"] + return intf_names + def code_generation_ipi(self): cmd = [] # add streamer if needed From b2a87d62f7b844d991d46bf037e0c93d24b0d9aa Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 15 Mar 2024 14:54:14 +0000 Subject: [PATCH 614/665] cleaned up comments and obsolete methods --- .../hls/matrixvectoractivation_hls.py | 2 +- .../rtl/matrixvectoractivation_rtl.py | 21 ++----------------- 2 files changed, 3 insertions(+), 20 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py b/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py index 9043496328..94f8cc0845 100644 --- a/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py @@ -35,7 +35,7 @@ from finn.custom_op.fpgadataflow.matrixvectoractivation import MVAU from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy -# ONNX i/o tensor shape assumptions for MatrixVectorActivation: +# ONNX i/o tensor shape assumptions for MatrixVectorActivation_hls: # input 0 is the input tensor, shape (.., i_size) = (..., MW) # input 1 is the weight tensor, shape (i_size, o_size) = (MW, MH) # (optional) input 2 is the thresholds tensor, shape (o_size, n_thres) diff --git a/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py index a00ba72717..d48b3a918d 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py @@ -41,10 +41,9 @@ PyVerilator = None -# ONNX i/o tensor shape assumptions for MatrixVectorActivation: +# ONNX i/o tensor shape assumptions for MatrixVectorActivation_rtl: # input 0 is the input tensor, shape (.., i_size) = (..., MW) # input 1 is the weight tensor, shape (i_size, o_size) = (MW, MH) -# (optional) input 2 is the thresholds tensor, shape (o_size, n_thres) # output 0 is the output tensor, shape (.., o_size) = (..., MH) # the ... here can be any shape (representing groups of vectors) @@ -92,7 +91,7 @@ def execute_node(self, context, graph): os.path.join(code_gen_dir, "input_{}.npy".format(in_ind)), reshaped_input, ) - elif in_ind > 2: + elif in_ind > 1: raise Exception("Unexpected input found for MatrixVectorActivation_rtl") in_ind += 1 @@ -291,19 +290,3 @@ def prepare_rtlsim(self): self.set_nodeattr("rtlsim_so", sim.lib._name) return sim - - def get_all_verilog_paths(self): - "Return list of all folders containing Verilog code for this node." - - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - # Path to (System-)Verilog files used by top-module & path to top-module - verilog_paths = [code_gen_dir, os.environ["FINN_ROOT"] + "/finn-rtllib/mvu"] - return verilog_paths - - def get_verilog_top_filename(self): - "Return the Verilog top module filename for this node." - - verilog_file = "{}/{}_wrapper.v".format( - self.get_nodeattr("code_gen_dir_ipgen"), self.get_nodeattr("gen_top_module") - ) - return verilog_file From 9eb746ad4fb9d1a688df7b9e2d925a4e2223de42 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 15 Mar 2024 14:54:41 +0000 Subject: [PATCH 615/665] [mvau]: set default resType to auto --- src/finn/custom_op/fpgadataflow/matrixvectoractivation.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py index 92e7b169c6..7bbe4c04e9 100644 --- a/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/matrixvectoractivation.py @@ -63,7 +63,7 @@ def get_nodeattr_types(self): "SIMD": ("i", True, 0), "MW": ("i", True, 0), "MH": ("i", True, 0), - "resType": ("s", False, "lut", {"auto", "lut", "dsp"}), + "resType": ("s", False, "auto", {"auto", "lut", "dsp"}), "ActVal": ("i", False, 0), # FINN DataTypes for inputs, weights, outputs "inputDataType": ("s", True, ""), From c3bfa3f6ce0e533a11943633b648c659d0cedd7e Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 15 Mar 2024 14:55:11 +0000 Subject: [PATCH 616/665] [folding]: add MVAU_rtl in auto-folding --- src/finn/transformation/fpgadataflow/set_folding.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/finn/transformation/fpgadataflow/set_folding.py b/src/finn/transformation/fpgadataflow/set_folding.py index a755d37a9d..cd117f835b 100644 --- a/src/finn/transformation/fpgadataflow/set_folding.py +++ b/src/finn/transformation/fpgadataflow/set_folding.py @@ -126,7 +126,7 @@ def apply(self, model): continue op_type = node.op_type node_inst = getCustomOp(node) - if op_type == "MVAU_hls": + if op_type in ["MVAU_hls", "MVAU_rtl"]: max_simd = node_inst.get_nodeattr("MW") max_pe = node_inst.get_nodeattr("MH") node_inst.set_nodeattr("PE", 1) From 2f2db73dab0960dc7691bc439bec03facbbf8ac7 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 15 Mar 2024 14:55:47 +0000 Subject: [PATCH 617/665] [transform]: added comments and extra check to prevent binaryxnor_mode MVAU to be converted to (unsupported) RTL-MVAU --- src/finn/transformation/fpgadataflow/specialize_layers.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/finn/transformation/fpgadataflow/specialize_layers.py b/src/finn/transformation/fpgadataflow/specialize_layers.py index 5ba7bfac60..fa0285692f 100644 --- a/src/finn/transformation/fpgadataflow/specialize_layers.py +++ b/src/finn/transformation/fpgadataflow/specialize_layers.py @@ -209,6 +209,9 @@ def _swg_hls_possible(node): def _mvu_rtl_possible(n): # Checks whether RTL-based MVU is supported + # Currently, for DSP48 we only support 8sx8s and for + # DSP58 we support 8sx9s. Next to that, embedded thresholding + # functionality is not supported and neither binaryxnormode computation inp_width_in_range = ( DataType[getCustomOp(n).get_nodeattr("inputDataType")].bitwidth() <= 8 ) or ( @@ -217,8 +220,9 @@ def _mvu_rtl_possible(n): ) weight_width_in_range = DataType[getCustomOp(n).get_nodeattr("weightDataType")].bitwidth() <= 8 no_activation = getCustomOp(n).get_nodeattr("noActivation") == 1 + not_binaryxnor_mode = getCustomOp(n).get_nodeattr("binaryXnorMode") == 0 - return inp_width_in_range and weight_width_in_range and no_activation + return inp_width_in_range and weight_width_in_range and no_activation and not_binaryxnor_mode class SpecializeLayers(Transformation): From b05002416181d364c7f46ce89d0535823f6b7c53 Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 15 Mar 2024 15:49:50 +0000 Subject: [PATCH 618/665] [HWop/Tests] Cleanup of unsused fct in HWCustomOp and invalid skipping in test --- src/finn/custom_op/fpgadataflow/hwcustomop.py | 10 ---------- tests/fpgadataflow/test_convert_to_hw_1d_conv_layer.py | 3 --- 2 files changed, 13 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/hwcustomop.py b/src/finn/custom_op/fpgadataflow/hwcustomop.py index 854587afc4..57c0fec067 100644 --- a/src/finn/custom_op/fpgadataflow/hwcustomop.py +++ b/src/finn/custom_op/fpgadataflow/hwcustomop.py @@ -126,16 +126,6 @@ def get_verilog_top_module_intf_names(self): intf_names["ap_none"] = [] return intf_names - def get_verilog_top_filename(self): - "Return the Verilog top module filename for this node." - - verilog_file = "{}/project_{}/sol1/impl/verilog/{}.v".format( - self.get_nodeattr("code_gen_dir_ipgen"), - self.onnx_node.name, - self.get_verilog_top_module_name(), - ) - return verilog_file - def get_rtlsim(self): """Return a PyVerilator wrapper for the Verilator emulation library for this node.""" diff --git a/tests/fpgadataflow/test_convert_to_hw_1d_conv_layer.py b/tests/fpgadataflow/test_convert_to_hw_1d_conv_layer.py index 5e06cf9904..cdc3a7e423 100644 --- a/tests/fpgadataflow/test_convert_to_hw_1d_conv_layer.py +++ b/tests/fpgadataflow/test_convert_to_hw_1d_conv_layer.py @@ -88,9 +88,6 @@ def test_convert_to_hw_1d_conv_layer(conv_config, depthwise, use_rtl_swg, exec_m pad_h = pad[0] + pad[2] pad_w = pad[1] + pad[3] - if use_rtl_swg and exec_mode == "cppsim": - pytest.skip("Skip cppsim if SWG is in rtl") - if depthwise is True: group = out_chn = in_chn conv_param_shape = [out_chn, 1, k_h, k_w] From f61aa0d5e36370498791a6c0f4caa9a544bd5116 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 15 Mar 2024 16:03:58 +0000 Subject: [PATCH 619/665] add MVAU_rtl extension --- src/finn/transformation/fpgadataflow/insert_iodma.py | 2 +- src/finn/transformation/fpgadataflow/set_fifo_depths.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/insert_iodma.py b/src/finn/transformation/fpgadataflow/insert_iodma.py index 96f23ca320..1c4b4d7398 100644 --- a/src/finn/transformation/fpgadataflow/insert_iodma.py +++ b/src/finn/transformation/fpgadataflow/insert_iodma.py @@ -199,7 +199,7 @@ def apply(self, model): # attached IODMA fc_extw_nodes = list( filter( - lambda x: x.op_type in ["MVAU_hls", "VectorVectorActivation_hls"] + lambda x: x.op_type in ["MVAU_hls", "MVAU_rtl", "VectorVectorActivation_hls"] and getCustomOp(x).get_nodeattr("mem_mode") == "external" and model.find_producer(x.input[1]) is None, all_nodes, diff --git a/src/finn/transformation/fpgadataflow/set_fifo_depths.py b/src/finn/transformation/fpgadataflow/set_fifo_depths.py index c60348876a..d3aab968d5 100644 --- a/src/finn/transformation/fpgadataflow/set_fifo_depths.py +++ b/src/finn/transformation/fpgadataflow/set_fifo_depths.py @@ -259,7 +259,7 @@ def __init__( def apply(self, model): # these optypes may potentially use external weights # we'll temporarily change them to use decoupled mode for FIFO sizing - extw_optypes = ["MVAU_hls", "VectorVectorActivation_hls"] + extw_optypes = ["MVAU_hls", "MVAU_rtl", "VectorVectorActivation_hls"] # change external to decoupled and warn user # this way we are sure we have exactly one input/output modified_fc_nodes = [] From e4caf06d83d83f9f3889c7ded03e9f078f6b6fc3 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 15 Mar 2024 16:10:06 +0000 Subject: [PATCH 620/665] update comments --- src/finn/transformation/fpgadataflow/specialize_layers.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/specialize_layers.py b/src/finn/transformation/fpgadataflow/specialize_layers.py index fa0285692f..a68b69aa45 100644 --- a/src/finn/transformation/fpgadataflow/specialize_layers.py +++ b/src/finn/transformation/fpgadataflow/specialize_layers.py @@ -209,9 +209,10 @@ def _swg_hls_possible(node): def _mvu_rtl_possible(n): # Checks whether RTL-based MVU is supported - # Currently, for DSP48 we only support 8sx8s and for - # DSP58 we support 8sx9s. Next to that, embedded thresholding - # functionality is not supported and neither binaryxnormode computation + # Currently, for DSP48 we only support computations up to + # 8sx8s and for DSP58 we support up to 8sx9s. Next to that, + # embedded thresholding functionality is not supported and + # neither binaryxnormode computation inp_width_in_range = ( DataType[getCustomOp(n).get_nodeattr("inputDataType")].bitwidth() <= 8 ) or ( From 6f07732cedc07bbf7a09ad94a7ad537f9de47a9c Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Fri, 15 Mar 2024 16:48:54 +0000 Subject: [PATCH 621/665] cleaned up with pre-commit --- finn-rtllib/mvu/mvu_vvu_8sx9_dsp58.sv | 36 +++++++++++++-------------- finn-rtllib/mvu/mvu_vvu_axi.sv | 4 +-- finn-rtllib/mvu/tb/mvu_8sx9_tb.sv | 10 ++++---- finn-rtllib/mvu/tb/mvu_axi_tb.sv | 12 +-------- 4 files changed, 26 insertions(+), 36 deletions(-) diff --git a/finn-rtllib/mvu/mvu_vvu_8sx9_dsp58.sv b/finn-rtllib/mvu/mvu_vvu_8sx9_dsp58.sv index 2cc6cf1bcf..3bbc7051b9 100644 --- a/finn-rtllib/mvu/mvu_vvu_8sx9_dsp58.sv +++ b/finn-rtllib/mvu/mvu_vvu_8sx9_dsp58.sv @@ -78,7 +78,8 @@ module mvu_vvu_8sx9_dsp58 #( //-------------------- Shift register for opmode select signal --------------------\\ localparam int unsigned MAX_PIPELINE_STAGES = (CHAINLEN + SEGLEN-1)/SEGLEN; // >=1 (== number of pipeline registers + 1 (A/B inputs always have 1 register)) - logic L [0:1+MAX_PIPELINE_STAGES] = '{default: 0}; // After MAX_PIPELINE_STAGES (== number of pipeline stages for input data), we have 3 additional cycles latency (A/B reg, Mreg, Preg). Thus, we add +2 (since OPMODE is buffered by 1 cycle in the DSP fabric) + logic L [0:1+MAX_PIPELINE_STAGES] = '{default: 0}; // After MAX_PIPELINE_STAGES (== number of pipeline stages for input data), we have 3 additional cycles latency (A/B reg, Mreg, Preg). + // Thus, we add +2 (since OPMODE is buffered by 1 cycle in the DSP fabric) always_ff @(posedge clk) begin if(rst) L <= '{default: 0}; @@ -115,16 +116,16 @@ module mvu_vvu_8sx9_dsp58 #( always_ff @(posedge clk) begin if (rst) A <= '{default: 0}; else if(en) begin - A[EXTERNAL_PREGS-1] <= - // synthesis translate_off - zero ? '1 : - // synthesis translate_on + A[EXTERNAL_PREGS-1] <= +// synthesis translate_off + zero ? '1 : +// synthesis translate_on a[SIMD*k + 3*i +: LANES_OCCUPIED]; if (EXTERNAL_PREGS > 1) A[0:EXTERNAL_PREGS-2] <= A[1:EXTERNAL_PREGS-1]; end end for (genvar j=0; j 1) B[i][0:EXTERNAL_PREGS-2] <= B[i][1:EXTERNAL_PREGS-1]; @@ -179,11 +180,10 @@ module mvu_vvu_8sx9_dsp58 #( end : genExternalPregWeight else begin : genInpDSPWeight for (genvar k = 0; k < LANES_OCCUPIED; k++) begin : genBin - assign b_in_i[i][j][8*k +: 8] = -// synthesis translate_off - zero ? '1 : -// synthesis translate_on - //PAD_BITS_WEIGHT == 0 ? w[i][3*j+k] : { {PAD_BITS_WEIGHT{w[i][3*j+k][WEIGHT_WIDTH-1]}}, w[i][3*j+k] }; + assign b_in_i[i][j][8*k +: 8] = +// synthesis translate_off + zero ? '1 : +// synthesis translate_on PAD_BITS_WEIGHT == 0 ? w[SIMD*i+3*j+k] : { {PAD_BITS_WEIGHT{w[SIMD*i+3*j+k][WEIGHT_WIDTH-1]}}, w[SIMD*i+3*j+k] }; end : genBin for (genvar k=LANES_OCCUPIED; k<3; k++) begin : genBinZero diff --git a/finn-rtllib/mvu/mvu_vvu_axi.sv b/finn-rtllib/mvu/mvu_vvu_axi.sv index 2a7403b6b3..6498530113 100644 --- a/finn-rtllib/mvu/mvu_vvu_axi.sv +++ b/finn-rtllib/mvu/mvu_vvu_axi.sv @@ -31,7 +31,7 @@ * @brief Matrix Vector Unit (MVU) & Vector Vector Unit (VVU) AXI-lite interface wrapper. * @details * The following compute cores are supported: - * - 4-bit MVU on DSP48 achieving 4 MACs/DSP, + * - 4-bit MVU on DSP48 achieving 4 MACs/DSP, * - (4,8]-bit MVU on DSP48 achieving 2 MACs/DSP, * - [4,9]-bit MVU and VVU on DSP58 achieving 3 MACs/DSP, * Folding hints: @@ -184,7 +184,7 @@ module mvu_vvu_axi #( uwire ovld; uwire dsp_p_t odat; if(1) begin : blkDsp - localparam int unsigned EFFECTIVE_SIMD = SIMD_UNEVEN && PUMPED_COMPUTE ? SIMD+1 : SIMD; + localparam int unsigned EFFECTIVE_SIMD = SIMD_UNEVEN && PUMPED_COMPUTE ? SIMD+1 : SIMD; localparam int unsigned DSP_SIMD = EFFECTIVE_SIMD/(PUMPED_COMPUTE+1); typedef logic [PE -1:0][DSP_SIMD-1:0][WEIGHT_WIDTH -1:0] dsp_w_t; typedef logic [ACT_PE-1:0][DSP_SIMD-1:0][ACTIVATION_WIDTH-1:0] dsp_a_t; diff --git a/finn-rtllib/mvu/tb/mvu_8sx9_tb.sv b/finn-rtllib/mvu/tb/mvu_8sx9_tb.sv index c8bfe5370a..34b5d8eb53 100644 --- a/finn-rtllib/mvu/tb/mvu_8sx9_tb.sv +++ b/finn-rtllib/mvu/tb/mvu_8sx9_tb.sv @@ -40,7 +40,7 @@ module mvu_8sx9_tb(); localparam int unsigned MW = 600; localparam int unsigned SIMD = 60; localparam int unsigned SEGMENTLEN = 4; - // Bit-width config + // Bit-width config localparam int unsigned ACTIVATION_WIDTH = 8; localparam int unsigned WEIGHT_WIDTH = 4; localparam bit SIGNED_ACTIVATIONS = 1; @@ -76,7 +76,7 @@ module mvu_8sx9_tb(); for (int i = 0; i>> [t=%0t] Test succeeded (NF=%0d)! Computed / GOLDEN = %0d / %0d", $time, NF_CNT, $signed(p[i]), $signed(GOLDEN_OUTPUT[NF_CNT][i])); - else begin + else begin $error(">>> [t=%0t] TEST failed (NF=%0d)! Computed / GOLDEN = %0d / %0d", $time, NF_CNT, $signed(p[i]), $signed(GOLDEN_OUTPUT[NF_CNT][i])); $stop; - end + end end NF_CNT += 1; end diff --git a/finn-rtllib/mvu/tb/mvu_axi_tb.sv b/finn-rtllib/mvu/tb/mvu_axi_tb.sv index 51bf623831..4ed7b4bf5f 100644 --- a/finn-rtllib/mvu/tb/mvu_axi_tb.sv +++ b/finn-rtllib/mvu/tb/mvu_axi_tb.sv @@ -156,16 +156,6 @@ module mvu_axi_tb(); function output_vector_t check_output(activation_vector_t a, weight_matrix_t w); automatic output_vector_t res = '{default: 0}; - // for (int j = 0; j 1 ? $signed(a[i/SIMD/PE][i % (SIMD*PE)]) : $signed(a[i/SIMD/PE][(i)%(SIMD*PE)]) ) * $signed(w[0][i/SIMD/PE][i/PE][i%SIMD]); - // else - // res[j/PE][j%PE] = IS_MVU ? $signed(res[j/PE][j%PE]) + $signed({1'b0, a[i/SIMD][i%SIMD]}) * $signed(w[j/PE][i/SIMD][j%PE][i%SIMD]) : - // $signed(res[j/PE][j%PE]) + ( PE > 1 ? $signed({1'b0, a[i/SIMD/PE][i % (SIMD*PE)]}) : $signed({1'b0, a[i/SIMD/PE][i%(SIMD*PE)]}) ) * $signed(w[0][i/SIMD][0][i%SIMD]); - // end - // end // The input stream will have the channels interleaved for VVU when PE>1 // Hence, we need to 'untangle' the input stream, i.e. [..][SIMD*PE][..] --> [..][PE][SIMD][..] // Note that for each 'SIMD' (S) and 'PE' (P) element, we have something like: @@ -236,4 +226,4 @@ module mvu_axi_tb(); .m_axis_output_tready(outputs.rdy) ); -endmodule : mvu_axi_tb \ No newline at end of file +endmodule : mvu_axi_tb From bd16f2e611e8b28a513d2b3417bdc8c4e87f47f5 Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 19 Mar 2024 11:55:44 +0000 Subject: [PATCH 622/665] [Tests] Fix checks for tests if converted to RTL MVU --- .../fpgadataflow/rtl/thresholding_rtl.py | 2 +- .../test_convert_to_hw_1d_conv_layer.py | 6 +++++- .../test_convert_to_hw_conv_layer.py | 6 +++++- .../test_convert_to_hw_layers_cnv.py | 14 ++++++-------- .../fpgadataflow/test_convert_to_hw_layers_fc.py | 16 ++++++++-------- 5 files changed, 25 insertions(+), 19 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py index f30a305dfe..84fcc01439 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py @@ -296,7 +296,7 @@ def dump_rtl_data(self, dest_dir, filename, data): f.write(data) return - def generate_hdl(self, model): + def generate_hdl(self, model, fpgapart, clk): """Prepare HDL files from templates for synthesis""" # Generate a dictionary of values to put in RTL template code_gen_dict = self.prepare_codegen_rtl_values(model) diff --git a/tests/fpgadataflow/test_convert_to_hw_1d_conv_layer.py b/tests/fpgadataflow/test_convert_to_hw_1d_conv_layer.py index cdc3a7e423..3e8f30422b 100644 --- a/tests/fpgadataflow/test_convert_to_hw_1d_conv_layer.py +++ b/tests/fpgadataflow/test_convert_to_hw_1d_conv_layer.py @@ -147,7 +147,11 @@ def test_convert_to_hw_1d_conv_layer(conv_config, depthwise, use_rtl_swg, exec_m else: new_model = new_model.transform(to_hw.InferQuantizedMatrixVectorActivation()) new_model = new_model.transform(SpecializeLayers()) - fc_node = new_model.get_nodes_by_op_type("MVAU_hls")[0] + # set folding parameters for MVAU + if new_model.get_nodes_by_op_type("MVAU_hls"): + fc_node = new_model.get_nodes_by_op_type("MVAU_hls")[0] + else: + fc_node = new_model.get_nodes_by_op_type("MVAU_rtl")[0] fc_inst = getCustomOp(fc_node) mw = fc_inst.get_nodeattr("MW") mh = fc_inst.get_nodeattr("MH") diff --git a/tests/fpgadataflow/test_convert_to_hw_conv_layer.py b/tests/fpgadataflow/test_convert_to_hw_conv_layer.py index ddcf386377..18fce769fc 100644 --- a/tests/fpgadataflow/test_convert_to_hw_conv_layer.py +++ b/tests/fpgadataflow/test_convert_to_hw_conv_layer.py @@ -135,7 +135,11 @@ def test_convert_to_hw_conv_layer(conv_config, depthwise, use_rtl_swg, exec_mode else: new_model = new_model.transform(to_hw.InferQuantizedMatrixVectorActivation()) new_model = new_model.transform(SpecializeLayers()) - fc_node = new_model.get_nodes_by_op_type("MVAU_hls")[0] + # set folding parameters for MVAU + if new_model.get_nodes_by_op_type("MVAU_hls"): + fc_node = new_model.get_nodes_by_op_type("MVAU_hls")[0] + else: + fc_node = new_model.get_nodes_by_op_type("MVAU_rtl")[0] fc_inst = getCustomOp(fc_node) mw = fc_inst.get_nodeattr("MW") mh = fc_inst.get_nodeattr("MH") diff --git a/tests/fpgadataflow/test_convert_to_hw_layers_cnv.py b/tests/fpgadataflow/test_convert_to_hw_layers_cnv.py index ff61867fde..71f383ca23 100644 --- a/tests/fpgadataflow/test_convert_to_hw_layers_cnv.py +++ b/tests/fpgadataflow/test_convert_to_hw_layers_cnv.py @@ -58,6 +58,7 @@ from finn.transformation.qonnx.convert_qonnx_to_finn import ConvertQONNXtoFINN from finn.transformation.streamline import Streamline from finn.transformation.streamline.reorder import MakeMaxPoolNHWC +from finn.util.fpgadataflow import is_fpgadataflow_node from finn.util.test import get_test_model_trained export_onnx_path_cnv = "test_convert_to_hw_layers_cnv.onnx" @@ -101,18 +102,15 @@ def test_convert_to_hw_layers_cnv_w1a1(fused_activation): # subsequently, the FC inference will generate passthrough MVAUs if not fused_activation: model = model.transform(to_hw.InferThresholdingLayer()) - tr_nodes = model.get_nodes_by_op_type("Thresholding") - for tr in tr_nodes: - tr_inst = getCustomOp(tr) - tr_inst.set_nodeattr("preferred_impl_style", "hls") + model = model.transform(to_hw.InferBinaryMatrixVectorActivation()) model = model.transform(to_hw.InferQuantizedMatrixVectorActivation()) model = model.transform(to_hw.InferConvInpGen()) - conv_nodes = model.get_nodes_by_op_type("ConvolutionInputGenerator") - for cnv in conv_nodes: - cnv_inst = getCustomOp(cnv) - cnv_inst.set_nodeattr("preferred_impl_style", "hls") model = model.transform(to_hw.InferStreamingMaxPool()) + for node in model.graph.node: + if is_fpgadataflow_node(node): + inst = getCustomOp(node) + inst.set_nodeattr("preferred_impl_style", "hls") model = model.transform(SpecializeLayers()) for node in model.graph.node: if node.op_type == "MVAU_hls": diff --git a/tests/fpgadataflow/test_convert_to_hw_layers_fc.py b/tests/fpgadataflow/test_convert_to_hw_layers_fc.py index d00521f09f..746ded9074 100644 --- a/tests/fpgadataflow/test_convert_to_hw_layers_fc.py +++ b/tests/fpgadataflow/test_convert_to_hw_layers_fc.py @@ -84,22 +84,22 @@ def test_convert_to_hw_layers_tfc_w1a1(): model = model.transform(to_hw.InferBinaryMatrixVectorActivation()) model = model.transform(SpecializeLayers()) fc0 = model.graph.node[2] - assert fc0.op_type == "MVAU_hls" + assert fc0.op_type.startswith("MVAU") assert model.get_tensor_shape(fc0.input[0]) == [1, 784] assert model.get_tensor_shape(fc0.input[1]) == [784, 64] assert model.get_tensor_shape(fc0.input[2]) == [64, 1] fc1 = model.graph.node[3] - assert fc1.op_type == "MVAU_hls" + assert fc1.op_type.startswith("MVAU") assert model.get_tensor_shape(fc1.input[0]) == [1, 64] assert model.get_tensor_shape(fc1.input[1]) == [64, 64] assert model.get_tensor_shape(fc1.input[2]) == [64, 1] fc2 = model.graph.node[4] - assert fc2.op_type == "MVAU_hls" + assert fc2.op_type.startswith("MVAU") assert model.get_tensor_shape(fc2.input[0]) == [1, 64] assert model.get_tensor_shape(fc2.input[1]) == [64, 64] assert model.get_tensor_shape(fc2.input[2]) == [64, 1] fc3 = model.graph.node[5] - assert fc3.op_type == "MVAU_hls" + assert fc3.op_type.startswith("MVAU") assert model.get_tensor_shape(fc3.input[0]) == [1, 64] assert model.get_tensor_shape(fc3.input[1]) == [64, 10] @@ -157,22 +157,22 @@ def test_convert_to_hw_layers_tfc_w1a2(): model = model.transform(SpecializeLayers()) fc0 = model.graph.node[2] - assert fc0.op_type == "MVAU_hls" + assert fc0.op_type.startswith("MVAU") assert model.get_tensor_shape(fc0.input[0]) == [1, 784] assert model.get_tensor_shape(fc0.input[1]) == [784, 64] assert model.get_tensor_shape(fc0.input[2]) == [64, 2] fc1 = model.graph.node[3] - assert fc1.op_type == "MVAU_hls" + assert fc1.op_type.startswith("MVAU") assert model.get_tensor_shape(fc1.input[0]) == [1, 64] assert model.get_tensor_shape(fc1.input[1]) == [64, 64] assert model.get_tensor_shape(fc1.input[2]) == [64, 2] fc2 = model.graph.node[4] - assert fc2.op_type == "MVAU_hls" + assert fc2.op_type.startswith("MVAU") assert model.get_tensor_shape(fc2.input[0]) == [1, 64] assert model.get_tensor_shape(fc2.input[1]) == [64, 64] assert model.get_tensor_shape(fc2.input[2]) == [64, 2] fc3 = model.graph.node[5] - assert fc3.op_type == "MVAU_hls" + assert fc3.op_type.startswith("MVAU") assert model.get_tensor_shape(fc3.input[0]) == [1, 64] assert model.get_tensor_shape(fc3.input[1]) == [64, 10] fc0w = getCustomOp(fc0) From f70f53127e6ed1ce180e70f387630aa17942ed9f Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 19 Mar 2024 13:13:37 +0000 Subject: [PATCH 623/665] [Tests] Update tests --- .../fpgadataflow/convert_to_hw_layers.py | 3 +-- ...pgadataflow_convinputgenerator_rtl_dynamic.py | 1 + tests/fpgadataflow/test_fpgadataflow_deconv.py | 16 ++++++++++++---- 3 files changed, 14 insertions(+), 6 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py index 27f257b917..d5f5fb4dee 100644 --- a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py +++ b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py @@ -44,9 +44,8 @@ class InferConvInpGen(Transformation): """Convert Im2Col layers to ConvolutionInputGenerator layers.""" - def __init__(self, use_rtl_variant=False): + def __init__(self): super().__init__() - self.use_rtl_variant = use_rtl_variant def apply(self, model): graph = model.graph diff --git a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py index 766a294977..3ad0bc4324 100644 --- a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py +++ b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py @@ -270,6 +270,7 @@ def test_fpgadataflow_conv_dynamic(cfg): getCustomOp(swg_node).set_nodeattr("inFIFODepths", [16]) getCustomOp(swg_node).set_nodeattr("outFIFODepths", [16]) comp_nodes = model.get_nodes_by_op_type("MVAU_hls") + comp_nodes += model.get_nodes_by_op_type("MVAU_rtl") comp_nodes += model.get_nodes_by_op_type("VectorVectorActivation_hls") for comp_node in comp_nodes: if depthwise: diff --git a/tests/fpgadataflow/test_fpgadataflow_deconv.py b/tests/fpgadataflow/test_fpgadataflow_deconv.py index ce8e1ce003..28e58bfba9 100644 --- a/tests/fpgadataflow/test_fpgadataflow_deconv.py +++ b/tests/fpgadataflow/test_fpgadataflow_deconv.py @@ -166,7 +166,7 @@ def test_fpgadataflow_deconv(idim, stride, ifm_ch, ofm_ch, simd, pe, k, padding, y_expected = oxe.execute_onnx(ref_model, input_dict)["outp"] model = ref_model.transform(InferPixelPaddingDeconv()) - model = model.transform(InferConvInpGen(use_rtl_variant=convinpgen_rtl)) + model = model.transform(InferConvInpGen()) model = model.transform(InferQuantizedMatrixVectorActivation()) model = model.transform(InferShapes()) model = model.transform(GiveUniqueNodeNames()) @@ -174,7 +174,6 @@ def test_fpgadataflow_deconv(idim, stride, ifm_ch, ofm_ch, simd, pe, k, padding, for n in model.graph.node: if n.op_type == "ConvolutionInputGenerator" and not convinpgen_rtl: convinputgen_node = getCustomOp(n) - convinputgen_node.set_nodeattr("SIMD", simd) # to test cppsim, set preferred_impl_style for swg to hls convinputgen_node.set_nodeattr("preferred_impl_style", "hls") elif n.op_type == "FMPadding": @@ -182,13 +181,22 @@ def test_fpgadataflow_deconv(idim, stride, ifm_ch, ofm_ch, simd, pe, k, padding, pad_node.set_nodeattr("preferred_impl_style", "hls") elif n.op_type == "MVAU": mvau_node = getCustomOp(n) - mvau_node.set_nodeattr("PE", pe) - mvau_node.set_nodeattr("SIMD", simd) + mvau_node.set_nodeattr("preferred_impl_style", "hls") y_produced = oxe.execute_onnx(model, input_dict)["outp"] assert (y_produced == y_expected).all() model = model.transform(SpecializeLayers()) + + for n in model.graph.node: + if n.op_type.startswith("ConvolutionInputGenerator"): + convinputgen_node = getCustomOp(n) + convinputgen_node.set_nodeattr("SIMD", simd) + elif n.op_type.startswith("MVAU"): + mvau_node = getCustomOp(n) + mvau_node.set_nodeattr("PE", pe) + mvau_node.set_nodeattr("SIMD", simd) + expected_oshape = (1, ofm_ch, odim_h, odim_w) # cppsim From 3524e169f2ba96dfcfa008e6932b66ccb54fd589 Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 19 Mar 2024 17:26:59 +0000 Subject: [PATCH 624/665] [Tests] Add minimize accumulator width to deconv test --- .../fpgadataflow/test_fpgadataflow_deconv.py | 24 ++++--------------- 1 file changed, 4 insertions(+), 20 deletions(-) diff --git a/tests/fpgadataflow/test_fpgadataflow_deconv.py b/tests/fpgadataflow/test_fpgadataflow_deconv.py index 28e58bfba9..f1fc989066 100644 --- a/tests/fpgadataflow/test_fpgadataflow_deconv.py +++ b/tests/fpgadataflow/test_fpgadataflow_deconv.py @@ -49,6 +49,9 @@ from finn.transformation.fpgadataflow.infer_pixel_padding_deconv import ( InferPixelPaddingDeconv, ) +from finn.transformation.fpgadataflow.minimize_accumulator_width import ( + MinimizeAccumulatorWidth, +) from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim from finn.transformation.fpgadataflow.prepare_ip import PrepareIP from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim @@ -147,14 +150,6 @@ def test_fpgadataflow_deconv(idim, stride, ifm_ch, ofm_ch, simd, pe, k, padding, idim_h, idim_w = idim stride_h, stride_w = stride - if idim_h == idim_w and stride_h == stride_w: - convinpgen_rtl = False - else: - convinpgen_rtl = True - - if exec_mode == "cppsim" and convinpgen_rtl: - pytest.skip("ConvolutionInputGenerator_rtl has no cppsim, skipping cppsim") - ref_model = set_up_reference_model(idt, wdt, k, idim, ifm_ch, ofm_ch, stride, padding) odim_h = (idim_h - 1) * stride_h - 2 * padding + (k - 1) + 1 @@ -171,22 +166,11 @@ def test_fpgadataflow_deconv(idim, stride, ifm_ch, ofm_ch, simd, pe, k, padding, model = model.transform(InferShapes()) model = model.transform(GiveUniqueNodeNames()) - for n in model.graph.node: - if n.op_type == "ConvolutionInputGenerator" and not convinpgen_rtl: - convinputgen_node = getCustomOp(n) - # to test cppsim, set preferred_impl_style for swg to hls - convinputgen_node.set_nodeattr("preferred_impl_style", "hls") - elif n.op_type == "FMPadding": - pad_node = getCustomOp(n) - pad_node.set_nodeattr("preferred_impl_style", "hls") - elif n.op_type == "MVAU": - mvau_node = getCustomOp(n) - mvau_node.set_nodeattr("preferred_impl_style", "hls") - y_produced = oxe.execute_onnx(model, input_dict)["outp"] assert (y_produced == y_expected).all() model = model.transform(SpecializeLayers()) + model = model.transform(MinimizeAccumulatorWidth()) for n in model.graph.node: if n.op_type.startswith("ConvolutionInputGenerator"): From 9c8406bb682de6a8fe141e71a8f5914b14c5d09b Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Tue, 19 Mar 2024 17:51:51 +0000 Subject: [PATCH 625/665] [transform]: updated comment VVU-RTL checker --- src/finn/transformation/fpgadataflow/specialize_layers.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/finn/transformation/fpgadataflow/specialize_layers.py b/src/finn/transformation/fpgadataflow/specialize_layers.py index fbcc2a48b4..628de08a3e 100644 --- a/src/finn/transformation/fpgadataflow/specialize_layers.py +++ b/src/finn/transformation/fpgadataflow/specialize_layers.py @@ -245,6 +245,8 @@ def _mvu_rtl_possible(n): def _vvu_rtl_possible(n, fpgapart): # Checks whether RTL-based VVU is supported + # Currently, we only support RTL-VVU on DSP58 up to 8sx9s inputs. + # Next to that, embedded thresholding functionality is not supported in_width_in_range = ( DataType[getCustomOp(n).get_nodeattr("inputDataType")].bitwidth() <= 8 ) or ( From 212c44aab785a5b129a9403d578634c50a63b360 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Wed, 20 Mar 2024 11:35:42 +0000 Subject: [PATCH 626/665] [transform]: fix to default to HLS MVAU if bit-width < 4 --- src/finn/transformation/fpgadataflow/specialize_layers.py | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/finn/transformation/fpgadataflow/specialize_layers.py b/src/finn/transformation/fpgadataflow/specialize_layers.py index a68b69aa45..cabbd26a65 100644 --- a/src/finn/transformation/fpgadataflow/specialize_layers.py +++ b/src/finn/transformation/fpgadataflow/specialize_layers.py @@ -59,7 +59,13 @@ def _determine_impl_style(node): return "hls" if rtl_variant: if optype == "MVAU": - if _mvu_rtl_possible(node): + inp_width_fit = ( + DataType[getCustomOp(node).get_nodeattr("inputDataType")].bitwidth() >= 4 + ) + weight_width_fit = ( + DataType[getCustomOp(node).get_nodeattr("weightDataType")].bitwidth() >= 4 + ) + if inp_width_fit and weight_width_fit and _mvu_rtl_possible(node): return "rtl" else: return "hls" From f7e1a83a58969fe8bbd1e37193f2c147233726ec Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Wed, 20 Mar 2024 11:50:06 +0000 Subject: [PATCH 627/665] [rtl vvau]: removed unused methods --- .../rtl/vectorvectoractivation_rtl.py | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/rtl/vectorvectoractivation_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/vectorvectoractivation_rtl.py index c138cf05d5..b315d913e4 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/vectorvectoractivation_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/vectorvectoractivation_rtl.py @@ -283,19 +283,3 @@ def prepare_rtlsim(self): self.set_nodeattr("rtlsim_so", sim.lib._name) return sim - - def get_all_verilog_paths(self): - "Return list of all folders containing Verilog code for this node." - - code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") - # Path to (System-)Verilog files used by top-module & path to top-module - verilog_paths = [code_gen_dir, os.environ["FINN_ROOT"] + "/finn-rtllib/mvu"] - return verilog_paths - - def get_verilog_top_filename(self): - "Return the Verilog top module filename for this node." - - verilog_file = "{}/{}_wrapper.v".format( - self.get_nodeattr("code_gen_dir_ipgen"), self.get_nodeattr("gen_top_module") - ) - return verilog_file From 77046541ef020be2c89d1ed581045167b210956a Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Wed, 20 Mar 2024 11:52:48 +0000 Subject: [PATCH 628/665] renamed VectorVectorActivation_{hls,rtl} to VVAU_{hls,rtl} --- src/finn/transformation/fpgadataflow/insert_iodma.py | 2 +- .../transformation/fpgadataflow/set_fifo_depths.py | 2 +- src/finn/transformation/fpgadataflow/set_folding.py | 12 ++++++++---- tests/end2end/test_end2end_mobilenet_v1.py | 2 +- .../fpgadataflow/test_convert_to_hw_1d_conv_layer.py | 2 +- tests/fpgadataflow/test_convert_to_hw_conv_layer.py | 2 +- ...st_fpgadataflow_convinputgenerator_rtl_dynamic.py | 3 ++- tests/fpgadataflow/test_fpgadataflow_vvau.py | 2 +- 8 files changed, 16 insertions(+), 11 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/insert_iodma.py b/src/finn/transformation/fpgadataflow/insert_iodma.py index 1c4b4d7398..91d4ab1559 100644 --- a/src/finn/transformation/fpgadataflow/insert_iodma.py +++ b/src/finn/transformation/fpgadataflow/insert_iodma.py @@ -199,7 +199,7 @@ def apply(self, model): # attached IODMA fc_extw_nodes = list( filter( - lambda x: x.op_type in ["MVAU_hls", "MVAU_rtl", "VectorVectorActivation_hls"] + lambda x: x.op_type in ["MVAU_hls", "MVAU_rtl", "VVAU_hls", "VVAU_rtl"] and getCustomOp(x).get_nodeattr("mem_mode") == "external" and model.find_producer(x.input[1]) is None, all_nodes, diff --git a/src/finn/transformation/fpgadataflow/set_fifo_depths.py b/src/finn/transformation/fpgadataflow/set_fifo_depths.py index d3aab968d5..82ee536d50 100644 --- a/src/finn/transformation/fpgadataflow/set_fifo_depths.py +++ b/src/finn/transformation/fpgadataflow/set_fifo_depths.py @@ -259,7 +259,7 @@ def __init__( def apply(self, model): # these optypes may potentially use external weights # we'll temporarily change them to use decoupled mode for FIFO sizing - extw_optypes = ["MVAU_hls", "MVAU_rtl", "VectorVectorActivation_hls"] + extw_optypes = ["MVAU_hls", "MVAU_rtl", "VVAU_hls", "VVAU_rtl"] # change external to decoupled and warn user # this way we are sure we have exactly one input/output modified_fc_nodes = [] diff --git a/src/finn/transformation/fpgadataflow/set_folding.py b/src/finn/transformation/fpgadataflow/set_folding.py index 1d11e91125..eaee499e6a 100644 --- a/src/finn/transformation/fpgadataflow/set_folding.py +++ b/src/finn/transformation/fpgadataflow/set_folding.py @@ -120,7 +120,7 @@ def apply(self, model): ] # these ops are preceded by depthwise SWG and have special behavior, # as explained in the SetFolding docstring - depthwise_op_exceptions = ["VVAU_hls", "Pool_hls"] + depthwise_op_exceptions = ["VVAU_hls", "VVAU_rtl", "Pool_hls"] for node in graph.node: if not (is_hls_node(node) or is_rtl_node(node)): continue @@ -158,14 +158,18 @@ def apply(self, model): self.optimize_attribute_val(node_inst, max_pe, "PE") elif op_type in depthwise_op_exceptions: # init/reset SIMD of VVAU - if op_type == "VVAU_hls": + if op_type in ["VVAU_hls", "VVAU_rtl"]: node_inst.set_nodeattr("SIMD", 1) max_pe = node_inst.get_nodeattr("Channels") self.optimize_attribute_val(node_inst, max_pe, "PE") # increase SIMD for VVAU once PE is exhausted pe = node_inst.get_nodeattr("PE") cyc = node_inst.get_exp_cycles() - if op_type == "VVAU_hls" and pe == max_pe and cyc > self.target_cycles_per_frame: + if ( + op_type in ["VVAU_hls", "VVAU_rtl"] + and pe == max_pe + and cyc > self.target_cycles_per_frame + ): max_simd = np.prod(node_inst.get_nodeattr("Kernel")) self.optimize_attribute_val(node_inst, max_simd, "SIMD") # also set the folding of the upsteam DW SWU @@ -181,7 +185,7 @@ def apply(self, model): else: swu_node_inst.set_nodeattr("parallel_window", 0) else: - if op_type == "VVAU_hls": + if op_type in ["VVAU_hls", "VVAU_rtl"]: ksize = np.prod(node_inst.get_nodeattr("Kernel")) elif op_type == "Pool_hls": ksize = node_inst.get_nodeattr("KernelSize") diff --git a/tests/end2end/test_end2end_mobilenet_v1.py b/tests/end2end/test_end2end_mobilenet_v1.py index eec303d29e..86b698278e 100644 --- a/tests/end2end/test_end2end_mobilenet_v1.py +++ b/tests/end2end/test_end2end_mobilenet_v1.py @@ -284,7 +284,7 @@ def test_end2end_mobilenet_folding(): getCustomOp(fc_layers[0]).set_nodeattr("resType", first_layer_res_type) # set up folding for the depthwise conv layers impl'd by VVAUs # each value is PE for a layer - vvau_layers = model.get_nodes_by_op_type("VectorVectorActivation_hls") + vvau_layers = model.get_nodes_by_op_type("VVAU_hls") folding = [32, 32, 64, 16, 32, 8, 16, 16, 16, 16, 16, 4, 8] for vvau, pe in zip(vvau_layers, folding): vvau_inst = getCustomOp(vvau) diff --git a/tests/fpgadataflow/test_convert_to_hw_1d_conv_layer.py b/tests/fpgadataflow/test_convert_to_hw_1d_conv_layer.py index 3e8f30422b..c5d0281203 100644 --- a/tests/fpgadataflow/test_convert_to_hw_1d_conv_layer.py +++ b/tests/fpgadataflow/test_convert_to_hw_1d_conv_layer.py @@ -187,7 +187,7 @@ def test_convert_to_hw_1d_conv_layer(conv_config, depthwise, use_rtl_swg, exec_m assert padding_inst.get_nodeattr("SIMD") == in_chn if depthwise is True and exec_mode == "rtlsim": - node = new_model.get_nodes_by_op_type("VectorVectorActivation_hls")[0] + node = new_model.get_nodes_by_op_type("VVAU_hls")[0] inst = getCustomOp(node) cycles_rtlsim = inst.get_nodeattr("cycles_rtlsim") exp_cycles_dict = new_model.analysis(exp_cycles_per_layer) diff --git a/tests/fpgadataflow/test_convert_to_hw_conv_layer.py b/tests/fpgadataflow/test_convert_to_hw_conv_layer.py index 18fce769fc..61f8af7806 100644 --- a/tests/fpgadataflow/test_convert_to_hw_conv_layer.py +++ b/tests/fpgadataflow/test_convert_to_hw_conv_layer.py @@ -189,7 +189,7 @@ def test_convert_to_hw_conv_layer(conv_config, depthwise, use_rtl_swg, exec_mode assert padding_inst.get_nodeattr("SIMD") == in_chn if depthwise is True and exec_mode == "rtlsim": - node = new_model.get_nodes_by_op_type("VectorVectorActivation_hls")[0] + node = new_model.get_nodes_by_op_type("VVAU_hls")[0] inst = getCustomOp(node) cycles_rtlsim = inst.get_nodeattr("cycles_rtlsim") exp_cycles_dict = new_model.analysis(exp_cycles_per_layer) diff --git a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py index 3ad0bc4324..6c0712b7b0 100644 --- a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py +++ b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py @@ -271,7 +271,8 @@ def test_fpgadataflow_conv_dynamic(cfg): getCustomOp(swg_node).set_nodeattr("outFIFODepths", [16]) comp_nodes = model.get_nodes_by_op_type("MVAU_hls") comp_nodes += model.get_nodes_by_op_type("MVAU_rtl") - comp_nodes += model.get_nodes_by_op_type("VectorVectorActivation_hls") + comp_nodes += model.get_nodes_by_op_type("VVAU_hls") + comp_nodes += model.get_nodes_by_op_type("VVAU_rtl") for comp_node in comp_nodes: if depthwise: getCustomOp(comp_node).set_nodeattr("PE", 4) diff --git a/tests/fpgadataflow/test_fpgadataflow_vvau.py b/tests/fpgadataflow/test_fpgadataflow_vvau.py index 98df27e3dd..236176faa6 100644 --- a/tests/fpgadataflow/test_fpgadataflow_vvau.py +++ b/tests/fpgadataflow/test_fpgadataflow_vvau.py @@ -294,7 +294,7 @@ def test_fpgadataflow_vvau( assert (y_produced == y_expected).all(), "VVAU specialized-op mismatches with golden output!" if exec_mode == "rtlsim": - node = model.get_nodes_by_op_type("VectorVectorActivation_hls")[0] + node = model.get_nodes_by_op_type("VVAU_hls")[0] inst = getCustomOp(node) cycles_rtlsim = inst.get_nodeattr("cycles_rtlsim") exp_cycles_dict = model.analysis(exp_cycles_per_layer) From d8b251c3fa62f05f6e82c6a9612b9afbb21ec9b0 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Wed, 20 Mar 2024 11:53:21 +0000 Subject: [PATCH 629/665] [transform]: fix to default to HLS VVAU if bit-width < 4 --- src/finn/transformation/fpgadataflow/specialize_layers.py | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/finn/transformation/fpgadataflow/specialize_layers.py b/src/finn/transformation/fpgadataflow/specialize_layers.py index 628de08a3e..4e7c64bc02 100644 --- a/src/finn/transformation/fpgadataflow/specialize_layers.py +++ b/src/finn/transformation/fpgadataflow/specialize_layers.py @@ -64,7 +64,13 @@ def _determine_impl_style(node, fpgapart): else: return "hls" elif optype == "VVAU": - if _vvu_rtl_possible(node, fpgapart): + inp_width_fit = ( + DataType[getCustomOp(node).get_nodeattr("inputDataType")].bitwidth() >= 4 + ) + weight_width_fit = ( + DataType[getCustomOp(node).get_nodeattr("weightDataType")].bitwidth() >= 4 + ) + if inp_width_fit and weight_width_fit and _vvu_rtl_possible(node, fpgapart): return "rtl" else: return "hls" From ff31d9f3f45ccc4fbafbd0d3654ee943cf73e585 Mon Sep 17 00:00:00 2001 From: auphelia Date: Wed, 20 Mar 2024 15:45:52 +0000 Subject: [PATCH 630/665] [Tests] Infer RTL VVAUs in end2end mobilenet test --- tests/end2end/test_end2end_mobilenet_v1.py | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/tests/end2end/test_end2end_mobilenet_v1.py b/tests/end2end/test_end2end_mobilenet_v1.py index 86b698278e..cbf89c2eae 100644 --- a/tests/end2end/test_end2end_mobilenet_v1.py +++ b/tests/end2end/test_end2end_mobilenet_v1.py @@ -77,7 +77,6 @@ from finn.transformation.streamline.collapse_repeated import CollapseRepeatedMul from finn.transformation.streamline.round_thresholds import RoundAndClipThresholds from finn.util.basic import alveo_default_platform, alveo_part_map, get_finn_root -from finn.util.fpgadataflow import is_fpgadataflow_node from finn.util.pytorch import NormalizePreProc from finn.util.test import ( crop_center, @@ -224,6 +223,7 @@ def test_end2end_mobilenet_convert_to_hw_layers(): model = load_test_checkpoint_or_skip(build_dir + "/end2end_mobilenet_lowered.onnx") model = model.transform(to_hw.InferPool()) model = model.transform(to_hw.InferConvInpGen()) + model = model.transform(to_hw.InferThresholdingLayer()) model = model.transform(to_hw.InferVectorVectorActivation()) model = model.transform(to_hw.InferQuantizedMatrixVectorActivation()) model = model.transform(to_hw.InferChannelwiseLinearLayer()) @@ -237,10 +237,6 @@ def test_end2end_mobilenet_convert_to_hw_layers(): @pytest.mark.end2end def test_end2end_mobilenet_specialize_layers(): model = load_test_checkpoint_or_skip(build_dir + "/end2end_mobilenet_hw_layers.onnx") - for node in model.graph.node: - if is_fpgadataflow_node(node): - inst = getCustomOp(node) - inst.set_nodeattr("preferred_impl_style", "hls") model = model.transform(SpecializeLayers()) model = model.transform(GiveUniqueNodeNames()) model = model.transform(GiveReadableTensorNames()) @@ -253,9 +249,10 @@ def test_end2end_mobilenet_folding(): # optional extra folding to use fewer resources # applied while setting the attributes on each node assert extra_fold in [1, 2, 4] - # set up folding for the depthwise conv layers impl'd by VVAUs + # set up folding for the conv layers impl'd by MVAUs # each value is PE for a layer fc_layers = model.get_nodes_by_op_type("MVAU_hls") + fc_layers += model.get_nodes_by_op_type("MVAU_rtl") # each tuple is (PE, SIMD, ram_style) for a layer folding = [ (32, 3, "block"), @@ -285,6 +282,7 @@ def test_end2end_mobilenet_folding(): # set up folding for the depthwise conv layers impl'd by VVAUs # each value is PE for a layer vvau_layers = model.get_nodes_by_op_type("VVAU_hls") + vvau_layers += model.get_nodes_by_op_type("VVAU_rtl") folding = [32, 32, 64, 16, 32, 8, 16, 16, 16, 16, 16, 4, 8] for vvau, pe in zip(vvau_layers, folding): vvau_inst = getCustomOp(vvau) From e0cfeee9853bdb03fd95491e2ccf09c6b8325303 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Wed, 20 Mar 2024 20:48:28 +0000 Subject: [PATCH 631/665] [Thresholding rtl] Update template wrapper file names to match top module name. --- .../custom_op/fpgadataflow/rtl/thresholding_rtl.py | 14 ++++++++------ .../transformation/fpgadataflow/make_zynq_proj.py | 2 +- 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py index 84fcc01439..2db52dad50 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py @@ -291,7 +291,8 @@ def dump_rtl_data(self, dest_dir, filename, data): # when generating template files, handle a special case: # if the filename contains the word "template", replace that # with the node name to distinguish between instances - filename = filename.replace("template", self.onnx_node.name) + if "template" in filename: + filename = self.get_nodeattr("gen_top_module") + ".v" with open(os.path.join(dest_dir, filename), "w") as f: f.write(data) return @@ -304,6 +305,10 @@ def generate_hdl(self, model, fpgapart, clk): # Retrieve the destination directory for the final RTL files code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") + # Set the 'gen_top_module' attribute for use later + # by PyVerilator and IPI generation + self.set_nodeattr("gen_top_module", code_gen_dict["$TOP_MODULE$"][0]) + weights = model.get_initializer(self.onnx_node.input[1]) weights_fname = f"{code_gen_dir}/memblock.dat" self.make_weight_file(weights, "decoupled", weights_fname) @@ -317,10 +322,6 @@ def generate_hdl(self, model, fpgapart, clk): file_only_path = rtl_file_path.split("/")[-1] self.dump_rtl_data(code_gen_dir, file_only_path, data) - # Before we return - set the 'gen_top_module' attribute for use later - # by PyVerilator and IPI generation - self.set_nodeattr("gen_top_module", code_gen_dict["$TOP_MODULE$"][0]) - # set ipgen_path and ip_path so that HLS-Synth transformation # and stich_ip transformation do not complain # i.e. during the HLSSynthIP() transformation @@ -459,7 +460,8 @@ def code_generation_ipi(self): """Constructs and returns the TCL commands for node instantiation as an RTL block.""" rtl_file_list = [ - x.replace("template", self.onnx_node.name) for x in self.get_rtl_file_list() + x.replace("thresholding_template_wrapper", self.get_nodeattr("gen_top_module")) + for x in self.get_rtl_file_list() ] code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") source_target = "./ip/verilog/rtl_ops/%s" % self.onnx_node.name diff --git a/src/finn/transformation/fpgadataflow/make_zynq_proj.py b/src/finn/transformation/fpgadataflow/make_zynq_proj.py index ade38ddfbf..fc2047b08e 100644 --- a/src/finn/transformation/fpgadataflow/make_zynq_proj.py +++ b/src/finn/transformation/fpgadataflow/make_zynq_proj.py @@ -64,7 +64,7 @@ def collect_ip_dirs(model, ipstitch_path): ), """The directory that should contain the generated ip blocks doesn't exist.""" ip_dirs += [ip_dir_value] - if node.op_type.startswith("MVAU") or node.op_type.startswith("Thresholding"): + if node.op_type.startswith("MVAU") or node.op_type == "Thresholding_hls": if node_inst.get_nodeattr("mem_mode") == "internal_decoupled": need_memstreamer = True ip_dirs += [ipstitch_path + "/ip"] From 1e71186ef06e5f9a4c50912f1d44f9de3e8e3b8f Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Wed, 20 Mar 2024 22:53:37 +0000 Subject: [PATCH 632/665] Update comment --- .../custom_op/fpgadataflow/rtl/thresholding_rtl.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py index eaef2f30f2..aabce81a03 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py @@ -188,11 +188,11 @@ def prepare_codegen_rtl_values(self, model): o_bitwidth = DataType[output_data_type].bitwidth() num_channels = self.get_nodeattr("NumChannels") # number of channels - # If a single threshold value is found, broadcast it to all channels + # If a single threshold value is found, broadcast the value n_thres_steps = self.get_nodeattr("numSteps") expected_shape = (num_channels, n_thres_steps) - if t_packed.shape != expected_shape: - t_packed = np.broadcast_to(t_packed, expected_shape) + if t_packed.shape == (1, 1): + t_packed = np.broadcast_to(t_packed, expected_shape) channel_fold = int(num_channels / pe) @@ -513,11 +513,11 @@ def make_weight_file(self, weights, weight_file_mode, weight_file_name): ch = self.get_nodeattr("NumChannels") n_thres_steps = self.get_nodeattr("numSteps") - # If a single threshold value is found, broadcast it to all channels + # If a single threshold value is found, broadcast the value n_thres_steps = self.get_nodeattr("numSteps") expected_shape = (ch, n_thres_steps) - if weights.shape != expected_shape: - weights = np.broadcast_to(weights, expected_shape) + if weights.shape == (1, 1): + weights = np.broadcast_to(weights, expected_shape) width_padded = roundup_to_integer_multiple(weights.shape[1], 4) weight_padded = np.zeros((weights.shape[0], width_padded)) From 755dacb90b2eeeec2c3314cf7c608bcb3f46c0b6 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Thu, 21 Mar 2024 12:29:05 +0000 Subject: [PATCH 633/665] [transform]: unsigned weights currently not supported --- .../transformation/fpgadataflow/specialize_layers.py | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/specialize_layers.py b/src/finn/transformation/fpgadataflow/specialize_layers.py index cabbd26a65..04f37cde0d 100644 --- a/src/finn/transformation/fpgadataflow/specialize_layers.py +++ b/src/finn/transformation/fpgadataflow/specialize_layers.py @@ -216,7 +216,8 @@ def _swg_hls_possible(node): def _mvu_rtl_possible(n): # Checks whether RTL-based MVU is supported # Currently, for DSP48 we only support computations up to - # 8sx8s and for DSP58 we support up to 8sx9s. Next to that, + # 8sx8u (8-bit signed weights x 8-bit (un)signed activations) + # and for DSP58 we support up to 8sx9s. Next to that, # embedded thresholding functionality is not supported and # neither binaryxnormode computation inp_width_in_range = ( @@ -226,10 +227,17 @@ def _mvu_rtl_possible(n): and DataType[getCustomOp(n).get_nodeattr("inputDataType")].min() < 0 ) weight_width_in_range = DataType[getCustomOp(n).get_nodeattr("weightDataType")].bitwidth() <= 8 + signed_weights = DataType[getCustomOp(n).get_nodeattr("weightDataType")].min() < 0 no_activation = getCustomOp(n).get_nodeattr("noActivation") == 1 not_binaryxnor_mode = getCustomOp(n).get_nodeattr("binaryXnorMode") == 0 - return inp_width_in_range and weight_width_in_range and no_activation and not_binaryxnor_mode + return ( + inp_width_in_range + and weight_width_in_range + and signed_weights + and no_activation + and not_binaryxnor_mode + ) class SpecializeLayers(Transformation): From 7f29a42df00ce72133d4f16b381baa578ba9d96b Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Thu, 21 Mar 2024 14:19:55 +0000 Subject: [PATCH 634/665] [transform]: RTL-VVU exclude unsigned weights --- .../fpgadataflow/specialize_layers.py | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/specialize_layers.py b/src/finn/transformation/fpgadataflow/specialize_layers.py index e987d21c66..917481edba 100644 --- a/src/finn/transformation/fpgadataflow/specialize_layers.py +++ b/src/finn/transformation/fpgadataflow/specialize_layers.py @@ -242,7 +242,7 @@ def _mvu_rtl_possible(n): # 8sx8u (8-bit signed weights x 8-bit (un)signed activations) # and for DSP58 we support up to 8sx9s. Next to that, # embedded thresholding functionality is not supported and - # neither binaryxnormode computation + # neither binaryxnormode computation. inp_width_in_range = ( DataType[getCustomOp(n).get_nodeattr("inputDataType")].bitwidth() <= 8 ) or ( @@ -265,8 +265,9 @@ def _mvu_rtl_possible(n): def _vvu_rtl_possible(n, fpgapart): # Checks whether RTL-based VVU is supported - # Currently, we only support RTL-VVU on DSP58 up to 8sx9s inputs. - # Next to that, embedded thresholding functionality is not supported + # Currently, we only support RTL-VVU on DSP58 up to 8sx9s inputs + # (8-bit signed weights x (9-bit signed OR 8-bit (un)signed) activations). + # Next to that, embedded thresholding functionality is not supported. in_width_in_range = ( DataType[getCustomOp(n).get_nodeattr("inputDataType")].bitwidth() <= 8 ) or ( @@ -274,10 +275,17 @@ def _vvu_rtl_possible(n, fpgapart): and DataType[getCustomOp(n).get_nodeattr("inputDataType")].min() < 0 ) weight_width_in_range = DataType[getCustomOp(n).get_nodeattr("weightDataType")].bitwidth() <= 8 + signed_weights = DataType[getCustomOp(n).get_nodeattr("weightDataType")].min() < 0 is_versal_family = is_versal(fpgapart) no_activation = getCustomOp(n).get_nodeattr("noActivation") == 1 - return in_width_in_range and weight_width_in_range and is_versal_family and no_activation + return ( + in_width_in_range + and weight_width_in_range + and signed_weights + and is_versal_family + and no_activation + ) class SpecializeLayers(Transformation): From a4a2ae429f5ef017231322ecdc2eced44b639861 Mon Sep 17 00:00:00 2001 From: auphelia Date: Thu, 21 Mar 2024 14:19:55 +0000 Subject: [PATCH 635/665] [Tests] Update bnn pynq to use rtl components - thresh and swg --- .../fpgadataflow/specialize_layers.py | 4 ---- tests/end2end/test_end2end_bnn_pynq.py | 19 +++++++------------ 2 files changed, 7 insertions(+), 16 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/specialize_layers.py b/src/finn/transformation/fpgadataflow/specialize_layers.py index 04f37cde0d..c4768f2399 100644 --- a/src/finn/transformation/fpgadataflow/specialize_layers.py +++ b/src/finn/transformation/fpgadataflow/specialize_layers.py @@ -53,10 +53,6 @@ def _determine_impl_style(node): if impl_style == "": if optype == "StreamingDataWidthConverter": return _dwc_determine_impl_style(node) - # TODO extensively test RTL thresholding - # for now use HLS component for thresholding - if optype == "Thresholding": - return "hls" if rtl_variant: if optype == "MVAU": inp_width_fit = ( diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index e90c412dae..fac50fc48b 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -95,7 +95,6 @@ MoveScalarLinearPastInvariants, ) from finn.util.basic import get_finn_root, make_build_dir, test_board_map -from finn.util.fpgadataflow import is_fpgadataflow_node from finn.util.pytorch import ToTensor from finn.util.test import ( execute_parent, @@ -132,7 +131,7 @@ def fold_tfc(model): fcl_inst.set_nodeattr("ram_style", ramstyle) fcl_inst.set_nodeattr("mem_mode", "internal_decoupled") # set parallelism for input quantizer to be same as first layer's SIMD - inp_qnt_node = model.get_nodes_by_op_type("Thresholding_hls")[0] + inp_qnt_node = model.get_nodes_by_op_type("Thresholding_rtl")[0] inp_qnt = getCustomOp(inp_qnt_node) inp_qnt.set_nodeattr("PE", 49) inp_qnt.set_nodeattr("mem_mode", "internal_decoupled") @@ -157,7 +156,7 @@ def fold_lfc(model): fcl_inst.set_nodeattr("runtime_writeable_weights", 1) fcl_inst.set_nodeattr("mem_mode", "internal_decoupled") # set parallelism for input quantizer to be same as first layer's SIMD - inp_qnt_node = model.get_nodes_by_op_type("Thresholding_hls")[0] + inp_qnt_node = model.get_nodes_by_op_type("Thresholding_rtl")[0] inp_qnt = getCustomOp(inp_qnt_node) inp_qnt.set_nodeattr("PE", 49) return model @@ -600,36 +599,32 @@ def test_specialize_layers(self, topology, wbits, abits, board): prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, "convert_to_hw_layers") model = load_test_checkpoint_or_skip(prev_chkpt_name) # set preferred impl style to hls for all layers - for node in model.graph.node: - if is_fpgadataflow_node(node): - inst = getCustomOp(node) - inst.set_nodeattr("preferred_impl_style", "hls") model = model.transform(SpecializeLayers()) model = model.transform(GiveUniqueNodeNames()) model.save(get_checkpoint_name(topology, wbits, abits, "specialize_layers")) exp_layer_counts = { "tfc": [ ("Reshape", 1), - ("Thresholding_hls", 1), + ("Thresholding_rtl", 1), ("MVAU_hls", 4), ("LabelSelect_hls", 1), ], "tfc-1-1": [ ("Reshape", 1), - ("Thresholding_hls", 4), + ("Thresholding_rtl", 4), ("MVAU_hls", 4), ("LabelSelect_hls", 1), ], "lfc": [ ("Reshape", 1), - ("Thresholding_hls", 1), + ("Thresholding_rtl", 1), ("MVAU_hls", 4), ("LabelSelect_hls", 1), ], "cnv": [ ("Transpose", 1), - ("Thresholding_hls", 1), - ("ConvolutionInputGenerator_hls", 6), + ("Thresholding_rtl", 1), + ("ConvolutionInputGenerator_rtl", 6), ("MVAU_hls", 9), ("StreamingMaxPool_hls", 2), ("LabelSelect_hls", 1), From 942735db544064e5039f324042d26cf3e205a4d0 Mon Sep 17 00:00:00 2001 From: auphelia Date: Thu, 21 Mar 2024 16:21:29 +0000 Subject: [PATCH 636/665] [Tests] Remove mem mode setting for RTL Thresholding --- tests/end2end/test_end2end_bnn_pynq.py | 1 - 1 file changed, 1 deletion(-) diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index fac50fc48b..a25d7e6725 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -134,7 +134,6 @@ def fold_tfc(model): inp_qnt_node = model.get_nodes_by_op_type("Thresholding_rtl")[0] inp_qnt = getCustomOp(inp_qnt_node) inp_qnt.set_nodeattr("PE", 49) - inp_qnt.set_nodeattr("mem_mode", "internal_decoupled") inp_qnt.set_nodeattr("runtime_writeable_weights", 1) return model From 2fc9590a7c1a378f112c1234041bc34b4a4456f5 Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 22 Mar 2024 09:29:50 +0000 Subject: [PATCH 637/665] [Thresholding] Use new wrapper name in prepare rtlsim --- src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py index 9193db750b..3cbb2ba427 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py @@ -346,7 +346,8 @@ def prepare_rtlsim(self): code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen") verilog_paths = [code_gen_dir] verilog_files = [ - x.replace("template", self.onnx_node.name) for x in self.get_rtl_file_list() + x.replace("thresholding_template_wrapper", self.get_nodeattr("gen_top_module")) + for x in self.get_rtl_file_list() ] dat_files = self.get_all_meminit_filenames(abspath=True) single_src_dir = make_build_dir("pyverilator_" + self.onnx_node.name + "_") From 5df52b9c1f740f32a899417ede7042b4e0da3f28 Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 22 Mar 2024 10:34:16 +0000 Subject: [PATCH 638/665] Fix linting --- src/finn/custom_op/fpgadataflow/rtl/__init__.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/finn/custom_op/fpgadataflow/rtl/__init__.py b/src/finn/custom_op/fpgadataflow/rtl/__init__.py index 3bcad9e8dd..06067a4fca 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/__init__.py +++ b/src/finn/custom_op/fpgadataflow/rtl/__init__.py @@ -35,8 +35,8 @@ StreamingDataWidthConverter_rtl, ) from finn.custom_op.fpgadataflow.rtl.streamingfifo_rtl import StreamingFIFO_rtl -from finn.custom_op.fpgadataflow.rtl.vectorvectoractivation_rtl import VVAU_rtl from finn.custom_op.fpgadataflow.rtl.thresholding_rtl import Thresholding_rtl +from finn.custom_op.fpgadataflow.rtl.vectorvectoractivation_rtl import VVAU_rtl custom_op = dict() From e1c326d38c824895d23171787c73c49977eab93f Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 22 Mar 2024 17:10:54 +0000 Subject: [PATCH 639/665] [Docs] First sweep to update the documentation --- docs/finn/brevitas_export.rst | 10 ++-- docs/finn/command_line.rst | 48 ++++++++++-------- docs/finn/end_to_end_flow.rst | 6 ++- docs/finn/getting_started.rst | 38 +++++--------- docs/finn/hw_build.rst | 14 ++--- docs/finn/img/finn-hw-build.png | Bin 57109 -> 59034 bytes docs/finn/img/finn-stack.png | Bin 66753 -> 82992 bytes docs/finn/img/nw-prep.png | Bin 31538 -> 54279 bytes docs/finn/index.rst | 12 ++--- docs/finn/nw_prep.rst | 17 +++++-- .../finn.custom_op.fpgadataflow.rtl.rst | 16 ++++++ docs/finn/source_code/finn.transformation.rst | 4 +- docs/finn/tutorials.rst | 11 +++- docs/finn/verification.rst | 8 +-- 14 files changed, 109 insertions(+), 75 deletions(-) diff --git a/docs/finn/brevitas_export.rst b/docs/finn/brevitas_export.rst index 950b601f98..0a1c788324 100644 --- a/docs/finn/brevitas_export.rst +++ b/docs/finn/brevitas_export.rst @@ -8,11 +8,11 @@ Brevitas Export :scale: 70% :align: center -FINN expects an ONNX model as input. This can be a model trained with `Brevitas `_. Brevitas is a PyTorch library for quantization-aware training and the FINN Docker image comes with several `example Brevitas networks `_. Brevitas provides an export of a quantized network in ONNX representation in several flavors. -Two of the Brevitas-exported ONNX variants can be ingested by FINN: - - * FINN-ONNX: Quantized weights exported as tensors with additional attributes to mark low-precision datatypes. Quantized activations exported as MultiThreshold nodes. - * QONNX: All quantization is represented using Quant, BinaryQuant or Trunc nodes. QONNX must be converted into FINN-ONNX by :py:mod:`finn.transformation.qonnx.convert_qonnx_to_finn` +FINN expects an ONNX model as input. This can be a model trained with `Brevitas `_. Brevitas is a PyTorch library for quantization-aware training and the FINN Docker image comes with several `example Brevitas networks `_. +Brevitas provides an export of a quantized network in QONNX representation, which is the format that can be ingested by FINN. +In a QONNX graph, all quantization is represented using Quant, BinaryQuant or Trunc nodes. +QONNX must be converted into FINN-ONNX by :py:mod:`finn.transformation.qonnx.convert_qonnx_to_finn`. FINN-ONNX is the intermediate representation (IR) FINN uses internally. +In this IR, quantized weights are indicated through tensors with additional attributes to mark low-precision datatypes and quantized activations are expressed as MultiThreshold nodes. To work with either type of ONNX model, it is loaded into a :ref:`modelwrapper` provided by FINN. diff --git a/docs/finn/command_line.rst b/docs/finn/command_line.rst index 8c37479a28..110a522847 100644 --- a/docs/finn/command_line.rst +++ b/docs/finn/command_line.rst @@ -20,7 +20,7 @@ two command line entry points for productivity and ease-of-use: Jupyter notebook as a starting point, visualizing the model at intermediate steps and adding calls to new transformations as needed. Once you have a working flow, you can implement a command line entry for this - by using the "advanced mode" described here. + by using the "advanced mode". Simple dataflow build mode @@ -28,7 +28,7 @@ Simple dataflow build mode This mode is intended for simpler networks whose topologies resemble the FINN end-to-end examples. -It runs a fixed build flow spanning tidy-up, streamlining, HLS conversion +It runs a fixed build flow spanning tidy-up, streamlining, HW conversion and hardware synthesis. It can be configured to produce different outputs, including stitched IP for integration in Vivado IPI as well as bitfiles. @@ -43,7 +43,9 @@ To use it, first create a folder with the necessary configuration and model file 3. Create a JSON file with the build configuration. It must be named ``dataflow_build_dir/dataflow_build_config.json``. Read more about the build configuration options on :py:mod:`finn.builder.build_dataflow_config.DataflowBuildConfig`. You can find an example .json file under ``src/finn/qnn-data/build_dataflow/dataflow_build_config.json`` -4. (Optional) create a JSON file with the folding configuration. It must be named ``dataflow_build_dir/folding_config.json``. +4. (Optional) create a JSON file with the specialize layers configuration. It must be named ``dataflow_build_dir/specialize_layers_config.json`` + You can find an example .json file under ``src/finn/qnn-data/build_dataflow/specialize_layers_config.json``. +5. (Optional) create a JSON file with the folding configuration. It must be named ``dataflow_build_dir/folding_config.json``. You can find an example .json file under ``src/finn/qnn-data/build_dataflow/folding_config.json``. Instead of specifying the folding configuration, you can use the `target_fps` option in the build configuration to control the degree of parallelization for your network. @@ -59,25 +61,28 @@ as it goes through numerous steps: .. code-block:: none - Building dataflow accelerator from /home/maltanar/sandbox/build_dataflow/model.onnx + Building dataflow accelerator from build_dataflow/model.onnx Outputs will be generated at output_tfc_w1a1_Pynq-Z1 Build log is at output_tfc_w1a1_Pynq-Z1/build_dataflow.log - Running step: step_tidy_up [1/16] - Running step: step_streamline [2/16] - Running step: step_convert_to_hls [3/16] - Running step: step_create_dataflow_partition [4/16] - Running step: step_target_fps_parallelization [5/16] - Running step: step_apply_folding_config [6/16] - Running step: step_generate_estimate_reports [7/16] - Running step: step_hls_codegen [8/16] - Running step: step_hls_ipgen [9/16] - Running step: step_set_fifo_depths [10/16] - Running step: step_create_stitched_ip [11/16] - Running step: step_measure_rtlsim_performance [12/16] - Running step: step_make_pynq_driver [13/16] - Running step: step_out_of_context_synthesis [14/16] - Running step: step_synthesize_bitfile [15/16] - Running step: step_deployment_package [16/16] + Running step: step_qonnx_to_finn [1/19] + Running step: step_tidy_up [2/19] + Running step: step_streamline [3/19] + Running step: step_convert_to_hw [4/19] + Running step: step_create_dataflow_partition [5/19] + Running step: step_specialize_layers [6/19] + Running step: step_target_fps_parallelization [7/19] + Running step: step_apply_folding_config [8/19] + Running step: step_minimize_bit_width [9/19] + Running step: step_generate_estimate_reports [10/19] + Running step: step_hw_codegen [11/19] + Running step: step_hw_ipgen [12/19] + Running step: step_set_fifo_depths [13/19] + Running step: step_create_stitched_ip [14/19] + Running step: step_measure_rtlsim_performance [15/19] + Running step: step_out_of_context_synthesis [16/19] + Running step: step_synthesize_bitfile [17/19] + Running step: step_make_pynq_driver [18/19] + Running step: step_deployment_package [19/19] You can read a brief description of what each step does on @@ -99,6 +104,7 @@ The following outputs will be generated regardless of which particular outputs a * ``build_dataflow.log`` is the build logfile that will contain any warnings/errors * ``time_per_step.json`` will report the time (in seconds) each build step took * ``final_hw_config.json`` will contain the final (after parallelization, FIFO sizing etc) hardware configuration for the build +* ``template_specialize_layers_config.json`` is an example json file that can be used to set the specialize layers config * ``intermediate_models/`` will contain the ONNX file(s) produced after each build step @@ -206,3 +212,5 @@ You can launch the desired custom build flow using: This will mount the specified folder into the FINN Docker container and launch the build flow. If ```` is not specified it will default to ``build`` and thus execute ``build.py``. If it is specified, it will be ``.py``. + +If you would like to learn more about advance builder settings, please have a look at `our tutorial about this topic `_. diff --git a/docs/finn/end_to_end_flow.rst b/docs/finn/end_to_end_flow.rst index 0a022067c3..8fafde5a5e 100644 --- a/docs/finn/end_to_end_flow.rst +++ b/docs/finn/end_to_end_flow.rst @@ -2,7 +2,11 @@ End-to-End Flow *************** -The following image shows an example end-to-end flow in FINN, starting from a trained PyTorch/Brevitas network and going all the way to a running FPGA accelerator. +The following image shows an example end-to-end flow in FINN for a PYNQ board. +Please note that you can build an IP block for your neural network **for every Xilinx-AMD FPGA**, but we only provide automatic system integration for a limited number of boards. +However, you can use Vivado to integrate an IP block generated by FINN into your own design. + +The example flow in this image starts from a trained PyTorch/Brevitas network and goes all the way to a running FPGA accelerator. As you can see in the picture, FINN has a high modularity and has the property that the flow can be stopped at any point and the intermediate result can be used for further processing or other purposes. This enables a wide range of users to benefit from FINN, even if they do not use the whole flow. .. image:: ../../notebooks/end2end_example/bnn-pynq/finn-design-flow-example.svg diff --git a/docs/finn/getting_started.rst b/docs/finn/getting_started.rst index 6bb0f3ab1a..eae61b1a55 100644 --- a/docs/finn/getting_started.rst +++ b/docs/finn/getting_started.rst @@ -8,7 +8,7 @@ Quickstart ========== 1. Install Docker to run `without root `_ -2. Set up ``FINN_XILINX_PATH`` and ``FINN_XILINX_VERSION`` environment variables pointing respectively to the Xilinx tools installation directory and version (e.g. ``FINN_XILINX_PATH=/opt/Xilinx`` and ``FINN_XILINX_VERSION=2022.1``) +2. Set up ``FINN_XILINX_PATH`` and ``FINN_XILINX_VERSION`` environment variables pointing respectively to the Xilinx tools installation directory and version (e.g. ``FINN_XILINX_PATH=/opt/Xilinx`` and ``FINN_XILINX_VERSION=2022.2``) 3. Clone the FINN compiler from the repo: ``git clone https://github.com/Xilinx/finn/`` and go into the directory where it is cloned 4. Execute ``./run-docker.sh quicktest`` to verify your installation. 5. Optionally, follow the instructions on :ref:`PYNQ board first-time setup` or :ref:`Alveo first-time setup` for board setup. @@ -28,8 +28,8 @@ to train *customized* networks and create highly-efficient FPGA implementations In general, the approach for using the FINN framework is as follows: 1. Train your own quantized neural network (QNN) in `Brevitas `_. We have some `guidelines `_ on quantization-aware training (QAT). -2. Export to FINN-ONNX by following `this tutorial `_ . -3. Use FINN's ``build_dataflow`` system on the exported model by following this `tutorial `_ +2. Export to QONNX and convert to FINN-ONNX by following `this tutorial `_ . +3. Use FINN's ``build_dataflow`` system on the exported model by following this `tutorial `_ or for advanced settings have a look at this `tutorial `_ . 4. Adjust your QNN topology, quantization settings and ``build_dataflow`` configuration to get the desired results. Please note that the framework is still under development, and how well this works will depend on how similar your custom network is to the examples we provide. @@ -49,13 +49,12 @@ Running FINN in Docker ====================== FINN runs inside a Docker container, it comes with a script to easily build and launch the container. If you are not familiar with Docker, there are many excellent `online resources `_ to get started. You may want to review the :ref:`General FINN Docker tips` and :ref:`Environment variables` as well. -If you want to use prebuilt images, read :ref:`Using a prebuilt image`. The above mentioned script to build and launch the FINN docker container is called `run-docker.sh `_ . It can be launched in the following modes: Launch interactive shell ************************ -Simply running sh run-docker.sh without any additional arguments will create a Docker container with all dependencies and give you a terminal with you can use for development for experimentation: +Simply running bash run-docker.sh without any additional arguments will create a Docker container with all dependencies and give you a terminal with you can use for development for experimentation: :: @@ -93,11 +92,12 @@ This will launch the `Jupyter notebook `_ server inside a Environment variables ********************** -Prior to running the `run-docker.sh` script, there are several environment variables you can set to configure certain aspects of FINN. -These are summarized below: +Prior to running the ``run-docker.sh`` script, there are several environment variables you can set to configure certain aspects of FINN. +For a complete list, please have a look in the `run-docker.sh `_ file. +The most relevant are summarized below: * (required) ``FINN_XILINX_PATH`` points to your Xilinx tools installation on the host (e.g. ``/opt/Xilinx``) -* (required) ``FINN_XILINX_VERSION`` sets the Xilinx tools version to be used (e.g. ``2022.1``) +* (required) ``FINN_XILINX_VERSION`` sets the Xilinx tools version to be used (e.g. ``2022.2``) * (required for Alveo) ``PLATFORM_REPO_PATHS`` points to the Vitis platform files (DSA). * (required for Alveo) ``XRT_DEB_VERSION`` specifies the .deb to be installed for XRT inside the container (see default value in ``run-docker.sh``). * (optional) ``NUM_DEFAULT_WORKERS`` (default 4) specifies the degree of parallelization for the transformations that can be run in parallel, potentially reducing build time @@ -108,10 +108,8 @@ These are summarized below: * (optional) ``NETRON_PORT`` (default 8081) changes the port for Netron inside Docker * (optional) ``PYNQ_BOARD`` or ``ALVEO_BOARD`` specifies the type of PYNQ/Alveo board used (see "supported hardware" below) for the test suite * (optional) ``IMAGENET_VAL_PATH`` specifies the path to the ImageNet validation directory for tests. -* (optional) ``FINN_DOCKER_PREBUILT`` (default 0) if set to 1 then skip Docker image building and use the image tagged with ``FINN_DOCKER_TAG``. * (optional) ``FINN_DOCKER_TAG`` (autogenerated) specifies the Docker image tag to use. * (optional) ``FINN_DOCKER_RUN_AS_ROOT`` (default 0) if set to 1 then run Docker container as root, default is the current user. -* (optional) ``FINN_DOCKER_GPU`` (autodetected) if not 0 then expose all Nvidia GPUs or those selected by ``NVIDIA_VISIBLE_DEVICES`` to Docker container for accelerated DNN training. Requires `Nvidia Container Toolkit `_ * (optional) ``FINN_DOCKER_EXTRA`` (default "") pass extra arguments to the ``docker run`` command when executing ``./run-docker.sh`` * (optional) ``FINN_SKIP_DEP_REPOS`` (default "0") skips the download of FINN dependency repos (uses the ones already downloaded under deps/. * (optional) ``NVIDIA_VISIBLE_DEVICES`` (default "") specifies specific Nvidia GPUs to use in Docker container. Possible values are a comma-separated list of GPU UUID(s) or index(es) e.g. ``0,1,2``, ``all``, ``none``, or void/empty/unset. @@ -125,23 +123,11 @@ General FINN Docker tips * If you want a new terminal on an already-running container, you can do this with ``docker exec -it bash``. * The container is spawned with the `--rm` option, so make sure that any important files you created inside the container are either in the finn compiler folder (which is mounted from the host computer) or otherwise backed up. -Using a prebuilt image -********************** - -By default the ``run-docker.sh`` script tries to re-build the Docker image with each run. After the first run this should go quite fast thanks to Docker caching. -If you are having trouble building the Docker image or need offline access, you can use prebuilt images by following these steps: - -1. Pull a prebuilt Docker image with ``docker pull maltanar/finn:`` where ```` can be ``dev_latest`` or ``main_latest`` -2. Set the ``FINN_DOCKER_TAG`` to the name of the image you just pulled e.g. ``FINN_DOCKER_TAG=maltanar/finn:dev_latest`` -3. Set ``FINN_DOCKER_PREBUILT=1`` -4. You can now launch the Docker image in all modes without re-building or any internet access. - - Supported FPGA Hardware ======================= -**Shell-integrated accelerator + driver:** For quick deployment, we target boards supported by `PYNQ `_ . For these platforms, we can build a full bitfile including DMAs to move data into and out of the FINN-generated accelerator, as well as a Python driver to launch the accelerator. We support the Pynq-Z1, Pynq-Z2, Ultra96, ZCU102 and ZCU104 boards, as well as Alveo cards. +**Vivado IPI support for any Xilinx FPGA:** FINN generates a Vivado IP Integrator (IPI) design from the neural network with AXI stream (FIFO) in-o> -**Vivado IPI support for any Xilinx FPGA:** FINN generates a Vivado IP Integrator (IPI) design from the neural network with AXI stream (FIFO) in-out interfaces, which can be integrated onto any Xilinx FPGA as part of a larger system. It's up to you to take the FINN-generated accelerator (what we call "stitched IP" in the tutorials), wire it up to your FPGA design and send/receive neural network data to/from the accelerator. +**Shell-integrated accelerator + driver:** For quick deployment, we target boards supported by `PYNQ `_ . For these platforms, we can build a full bitfile including DMAs to move data into and out of the FINN-generated accelerator, as well as a Python driver to launch the accelerator. We support the Pynq-Z1, Pynq-Z2, Kria SOM, Ultra96, ZCU102 and ZCU104 boards, as well as Alveo cards. PYNQ board first-time setup **************************** @@ -177,7 +163,7 @@ On the target side: On the host side: -1. Install Vitis 2022.1 and set up the ``VITIS_PATH`` environment variable to point to your installation. +1. Install Vitis 2022.2 and set up the ``VITIS_PATH`` environment variable to point to your installation. 2. Install Xilinx XRT. Ensure that the ``XRT_DEB_VERSION`` environment variable reflects which version of XRT you have installed. 3. Install the Vitis platform files for Alveo and set up the ``PLATFORM_REPO_PATHS`` environment variable to point to your installation. *This must be the same path as the target's platform files (target step 2)* 4. Set up the ``ALVEO_*`` environment variables accordingly for your target, see description of environment variables above. @@ -201,7 +187,7 @@ System Requirements * Ubuntu 18.04 with ``bash`` installed * Docker `without root `_ -* A working Vitis/Vivado 2022.1 installation +* A working Vitis/Vivado 2022.2 installation * ``FINN_XILINX_PATH`` and ``FINN_XILINX_VERSION`` environment variables correctly set, see `Quickstart`_ * *(optional)* `Vivado/Vitis license`_ if targeting non-WebPack FPGA parts. * *(optional)* A PYNQ board with a network connection, see `PYNQ board first-time setup`_ diff --git a/docs/finn/hw_build.rst b/docs/finn/hw_build.rst index a5c486935d..9e34edc9d1 100644 --- a/docs/finn/hw_build.rst +++ b/docs/finn/hw_build.rst @@ -8,7 +8,7 @@ Hardware Build and Deployment :scale: 70% :align: center -A model where all layers have been converted to HLS layers can be processed by +A model where all layers have been converted to either HLS or RTL layers can be processed by FINN to build a bitfile and driver targeting a Zynq or Alveo system or to generate a Vivado IP Integrator (IPI) design with AXI stream (FIFO) in-out interfaces, which can be integrated onto any Xilinx FPGA as part of a larger system. @@ -69,9 +69,11 @@ FINN will descend into each partition and insert FIFO nodes between streaming no where FIFO depths dictated by the node attributes, using the :py:mod:`finn.transformation.fpgadataflow.insert_fifo.InsertFIFO` transformation. Afterwards, IP blocks will be created for each partition, which in turn contain the -IP blocks for each layer stitched together. The layer-level IP blocks -are generated by Vivado HLS, using a sequence of :py:mod:`finn.transformation.fpgadataflow.prepare_ip.PrepareIP` +IP blocks for HLS layers and RTL modules for RTL layers stitched together. The layer-level IP blocks for HLS layers +are generated by Vitis HLS, using a sequence of :py:mod:`finn.transformation.fpgadataflow.prepare_ip.PrepareIP` and :py:mod:`finn.transformation.fpgadataflow.hlssynth_ip.HLSSynthIP` transformations. +For RTL layers calling :py:mod:`finn.transformation.fpgadataflow.prepare_ip.PrepareIP` will fill out the RTL wrapper files and store all files belonging to the RTL module in a folder. + The top-level IP blocks are generated in Vivado IPI, using the :py:mod:`finn.transformation.fpgadataflow.create_stitched_ip.CreateStitchedIP` transformation. Vivado/Vitis Project Generation and Synthesis @@ -86,7 +88,7 @@ Deployment ========== -Deployment and Remote Execution -------------------------------- +Deployment +----------- -The bitfile and the driver file(s) are copied to the PYNQ board and can be executed there. For more information see the description in the `end2end_example `_ Jupyter notebooks. +The bitfile and the driver file(s) can be copied to the PYNQ board and be executed there. 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What is FINN? -============= +============== .. image:: img/finn-stack.png - :scale: 40% + :scale: 15% :align: center 'FINN' is colloquially used to refer to two separate but highly related things: -* The FINN **project**, which is an experimental framework from Xilinx Research Labs - to explore deep neural network inference on FPGAs. It specifically targets - quantized neural networks (QNNs), with emphasis on generating dataflow-style +* The FINN **project**, which is an experimental framework from AMD Research and + Advanced Development (RAD) to explore deep neural network inference on FPGAs. + It specifically targets quantized neural networks (QNNs), with emphasis on generating dataflow-style architectures customized for each network. The key components are illustrated in the figure above; including tools for training quantized neural networks (Brevitas), the FINN compiler, and the finn-hlslib - Vivado HLS library of FPGA components for QNNs. + Vitis HLS library of FPGA components for QNNs. Read more on the `FINN project homepage `_. * The FINN **compiler**, which this Read the Docs website is the documentation for. diff --git a/docs/finn/nw_prep.rst b/docs/finn/nw_prep.rst index 6fea992cf7..5b1d59b99d 100644 --- a/docs/finn/nw_prep.rst +++ b/docs/finn/nw_prep.rst @@ -32,19 +32,28 @@ The idea behind streamlining is to eliminate floating point operations in a mode After this transformation the ONNX model is streamlined and contains now custom nodes in addition to the standard nodes. At this point we can use the :ref:`verification` to simulate the model using Python and in the next step some of the nodes can be converted into HLS layers that correspond to finn_hlslib functions. -Convert to HLS Layers +Convert to HW Layers ===================== -In this step standard or custom layers are converted to HLS layers. HLS layers are layers that directly correspond to a finn-hlslib function call. For example pairs of binary XNORPopcountMatMul and MultiThreshold layers are converted to MatrixVectorActivation layers. The result is a model consisting of a mixture of HLS and non-HLS layers. For more details, see :py:mod:`finn.transformation.fpgadataflow.convert_to_hls_layers`. The MatrixVectorActivation layer can be implemented in three different modes, *const*, *decoupled* (see chapter :ref:`mem_mode`) and *external*. +In this step standard or custom layers are converted to HW layers. HW abstraction layers are abstract (placeholder) layers that can be either implemented in HLS or as an RTL module using FINN. These layers are abstraction layers that do not directly correspond to an HLS or Verilog implementation but they will be converted in either one later in the flow. + +The result is a model consisting of a mixture of HW and non-HW layers. For more details, see :py:mod:`finn.transformation.fpgadataflow.convert_to_hw_layers`. Dataflow Partitioning ===================== -In the next step the graph is split and the part consisting of HLS layers is further processed in the FINN flow. The parent graph containing the non-HLS layers remains. The PE and SIMD are set to 1 by default, so the result is a network of only HLS layers with maximum folding. The model can be verified using the *cppsim* simulation. It is a simulation using C++ and is described in more detail in chapter :ref:`verification`. +In the next step the graph is split and the part consisting of HW layers is further processed in the FINN flow. The parent graph containing the non-HW layers remains. + +Specialize Layers +===================== + +The network is converted to HW abstraction layers and we have excluded the non-HW layers to continue with the processing of the model. HW abstraction layers are abstract (placeholder) layers that can be either implemented in HLS or as an RTL module using FINN. In the next flow step, we convert each of these layers to either an HLS or RTL variant by calling the SpecializeLayers transformation. It is possible to let the FINN flow know a preference for the implementation style {"hls", "rtl"} and depending on the layer type this wish will be fulfilled or it will be set to a reasonable default. Folding ========= +The PE and SIMD are set to 1 by default, so the result is a network of only HLS/RTL layers with maximum folding. The HLS layers of the model can be verified using the *cppsim* simulation. It is a simulation using C++ and is described in more detail in chapter :ref:`verification`. + To adjust the folding, the values for PE and SIMD can be increased to achieve also an increase in the performance. The result can be verified using the same simulation flow as for the network with maximum folding (*cppsim* using C++), for details please have a look at chapter :ref:`verification`. -The result is a network of HLS layers with desired folding and it can be passed to :ref:`hw_build`. +The result is a network of HLS/RTL layers with desired folding and it can be passed to :ref:`hw_build`. diff --git a/docs/finn/source_code/finn.custom_op.fpgadataflow.rtl.rst b/docs/finn/source_code/finn.custom_op.fpgadataflow.rtl.rst index b8a7f0d9e9..346eddb073 100644 --- a/docs/finn/source_code/finn.custom_op.fpgadataflow.rtl.rst +++ b/docs/finn/source_code/finn.custom_op.fpgadataflow.rtl.rst @@ -21,6 +21,14 @@ finn.custom\_op.fpgadataflow.fmpadding\_rtl :undoc-members: :show-inheritance: +finn.custom\_op.fpgadataflow.matrixvectoractivation\_rtl +--------------------------------------------------------------- + +.. automodule:: finn.custom_op.fpgadataflow.rtl.matrixvectoractivation_rtl + :members: + :undoc-members: + :show-inheritance: + finn.custom\_op.fpgadataflow.streamingdatawidthconverter\_rtl --------------------------------------------------------------- @@ -44,3 +52,11 @@ finn.custom\_op.fpgadataflow.thresholding\_rtl :members: :undoc-members: :show-inheritance: + +finn.custom\_op.fpgadataflow.vectorvectoractivation\_rtl +--------------------------------------------------------------- + +.. automodule:: finn.custom_op.fpgadataflow.rtl.vectorvectoractivation_rtl + :members: + :undoc-members: + :show-inheritance: diff --git a/docs/finn/source_code/finn.transformation.rst b/docs/finn/source_code/finn.transformation.rst index 1f4c9e495b..8dc7e1afc2 100644 --- a/docs/finn/source_code/finn.transformation.rst +++ b/docs/finn/source_code/finn.transformation.rst @@ -15,7 +15,7 @@ Submodules finn.transformation.streamline Transformation Passes -===================== +====================== Base Class ---------- @@ -116,7 +116,7 @@ qonnx.transformation.extract\_conv\_bias :show-inheritance: qonnx.transformation.extract\_quant\_scale\_zeropt ------------------------------------------------- +---------------------------------------------------- .. automodule:: qonnx.transformation.extract_quant_scale_zeropt :members: diff --git a/docs/finn/tutorials.rst b/docs/finn/tutorials.rst index 7ac54501cf..39d25c2634 100644 --- a/docs/finn/tutorials.rst +++ b/docs/finn/tutorials.rst @@ -16,7 +16,7 @@ The notebooks in this folder should give a basic insight into FINN, how to get s * This notebook can help you to learn how to create and manipulate a simple ONNX model, also by using FINN -* 1_brevitas_network_import +* 1_brevitas_network_import_via_QONNX * This notebook shows how to import a Brevitas network and prepare it for the FINN flow. @@ -47,6 +47,15 @@ The notebooks in this folder are more developer oriented. They should help you t * Explains the basics of FINN custom ops and how to define a new one. +* 3_folding + + * Describes the use of FINN parallelization parameters (PE & SIMD), also called folding factors, to efficiently optimize models so as to extract the maximum performance out of them. + +* 4_advanced_builder_settings + + * Provides a more detailed look into the FINN builder tool and explores different options to customize your FINN design. + + FINN Example FPGA Flow Using MNIST Numerals ============================================ diff --git a/docs/finn/verification.rst b/docs/finn/verification.rst index 4b1821aca1..578c941c36 100644 --- a/docs/finn/verification.rst +++ b/docs/finn/verification.rst @@ -5,17 +5,17 @@ Functional Verification *********************** .. image:: ../../notebooks/end2end_example/bnn-pynq/verification.svg - :scale: 70% + :scale: 40% :align: center This part of the flow is covered by the Jupyter notebook about the verification of a simple fully-connected network, which you can find in the `end2end notebook folder `_. -When the network is transformed it is important to verify the functionality to make sure the transformation did not change the behaviour of the model. There are multiple ways of verification that can be applied in different stages of the network inside FINN. All can be accessed using the execution function in module :py:mod:`finn.core.onnx_exec`. The execution happens in most cases node by node, which supports networks that have a mixture of standard ONNX nodes, custom nodes and HLS custom nodes. A single node can be executed using one or more of the following methods: +When the network is transformed it is important to verify the functionality to make sure the transformation did not change the behaviour of the model. There are multiple ways of verification that can be applied in different stages of the network inside FINN. All can be accessed using the execution function in module :py:mod:`finn.core.onnx_exec`. The execution happens in most cases node by node, which supports networks that have a mixture of standard ONNX nodes, custom nodes and HLS/RTL custom nodes. A single node can be executed using one or more of the following methods: Simulation using Python ======================= -This simulation can be used right after the :ref:`brevitas_export` or when the network does not contain any HLS custom nodes, so right after the streamlining transformations and before the nodes are converted into HLS layers. +This simulation can be used right after the :ref:`brevitas_export` or when the network does not contain any HLS/RTL custom nodes yet, so right after the streamlining transformations and before the nodes are specialized into HLS/RTL layers. Simulation using C++ ==================== @@ -26,7 +26,7 @@ This simulation can be used for a model containing several HLS custom operations Emulation using PyVerilator =========================== -The emulation using PyVerilator can be used when IP blocks were generated, either node by node or of a whole (IP-stitched) design. For that purpose PyVerilator gets the generated verilog files. +The emulation using PyVerilator can be used when IP blocks/RTL modules were generated, either node by node or of a whole (IP-stitched) design. For that purpose PyVerilator gets the generated verilog files. For debugging purposes, it's possible to generate .vcd trace files that show the value of external & internal signals as the emuation is running. To enable this: - for node-by-node rtlsim, set the `rtlsim_trace` attribute of each node of interest to either a file name for the vcd or `default` to use the node name as the filename. From fc6877b4a97122f3bd991356d98cb249027779a2 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Fri, 22 Mar 2024 17:30:06 +0000 Subject: [PATCH 640/665] [Thresholding RTL] Prepend dummy threshold for narrow range quantization --- .../fpgadataflow/rtl/thresholding_rtl.py | 21 ++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py index 3cbb2ba427..67b41d0165 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/thresholding_rtl.py @@ -168,9 +168,21 @@ def prepare_codegen_rtl_values(self, model): code_gen_dict = {} # TODO check for sortedness and size here? - # RTL component currently always expects 2^N-1 thresholds, but - # sometimes we have fewer due to e.g. narrow range quantization thresholds = model.get_initializer(self.onnx_node.input[1]) + bias = self.get_nodeattr("ActVal") # activation bias value + output_data_type = self.get_nodeattr("outputDataType") # output precision + input_data_type = self.get_nodeattr("inputDataType") # input/threshold precision + o_bitwidth = DataType[output_data_type].bitwidth() + + # The RTL expects 2^N-1 thresholds, but narrow range quantization will result in + # one less threshold, prepending a dummy threshold and reducing bias by 1 to compensate. + expected_thresholds = 2**o_bitwidth - 1 + n_thres_steps = self.get_nodeattr("numSteps") + if expected_thresholds != n_thres_steps and DataType[input_data_type].signed() is not True: + min_val = np.amin(thresholds, axis=1) + thresholds = np.insert(thresholds, 0, min_val, axis=1) + bias = bias - 1 + # add dummy dimension as final dimension (that's what gets packed with next call) thresholds = np.expand_dims(thresholds, axis=-1) wdt = self.get_weight_datatype() @@ -184,12 +196,9 @@ def prepare_codegen_rtl_values(self, model): t_path = self.get_nodeattr("code_gen_dir_ipgen") pe = self.get_nodeattr("PE") - output_data_type = self.get_nodeattr("outputDataType") # output precision - o_bitwidth = DataType[output_data_type].bitwidth() num_channels = self.get_nodeattr("NumChannels") # number of channels # If a single threshold value is found, broadcast the value - n_thres_steps = self.get_nodeattr("numSteps") expected_shape = (num_channels, n_thres_steps) if t_packed.shape == (1, 1): t_packed = np.broadcast_to(t_packed, expected_shape) @@ -223,8 +232,6 @@ def prepare_codegen_rtl_values(self, model): code_gen_dict["$TOP_MODULE$"] = code_gen_dict["$MODULE_NAME_AXI_WRAPPER$"] # Identify the module variables - input_data_type = self.get_nodeattr("inputDataType") # input/threshold precision - bias = self.get_nodeattr("ActVal") # activation bias value i_bitwidth = DataType[input_data_type].bitwidth() code_gen_dict["$N$"] = [str(o_bitwidth)] # output precision - convert bitwidth to string From 85baad01cfb57cebc6a3b1109814651cdd422cb7 Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 25 Mar 2024 09:51:09 +0000 Subject: [PATCH 641/665] [Test] Apply parallelism independent if it is HLS or RTL variant --- tests/fpgadataflow/test_depthwise_convolution.py | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/tests/fpgadataflow/test_depthwise_convolution.py b/tests/fpgadataflow/test_depthwise_convolution.py index 6ad8618981..bde5e918e3 100644 --- a/tests/fpgadataflow/test_depthwise_convolution.py +++ b/tests/fpgadataflow/test_depthwise_convolution.py @@ -56,7 +56,6 @@ from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers -from finn.util.fpgadataflow import is_fpgadataflow_node def set_up_reference_model(act, idt, wdt, k, ifm_dim, ifm_ch, stride, padding): @@ -182,21 +181,16 @@ def test_depthwise_conv_hw_cppsim(act, pe, k, stride, padding): new_model = model.transform(InferConvInpGen()) new_model = new_model.transform(InferVectorVectorActivation()) - # for cppsim set all layers to preferred impl style = "hls" - for node in new_model.graph.node: - if is_fpgadataflow_node(node): - inst = getCustomOp(node) - inst.set_nodeattr("preferred_impl_style", "hls") new_model = new_model.transform(SpecializeLayers()) # set SIMD in ConvInputGen node and PE in VVAU node for n in new_model.graph.node: - if n.op_type == "ConvolutionInputGenerator_hls": + if n.op_type.startswith("ConvolutionInputGenerator"): convinputgen_node = getCustomOp(n) convinputgen_node.set_nodeattr("SIMD", pe) - elif n.op_type == "VectorVectorActivation_hls": + elif n.op_type.startswith("VectorVectorActivation"): vvau_node = getCustomOp(n) vvau_node.set_nodeattr("PE", pe) new_model = new_model.transform(SetExecMode("cppsim")) @@ -234,13 +228,14 @@ def test_depthwise_conv_hw_rtlsim(act, pe, k, stride, padding): new_model = new_model.transform(InferVectorVectorActivation()) new_model = new_model.transform(SpecializeLayers()) + # set SIMD in ConvInputGen node and PE in VVAU node for n in new_model.graph.node: - if n.op_type == "ConvolutionInputGenerator_rtl": + if n.op_type.startswith("ConvolutionInputGenerator"): convinputgen_node = getCustomOp(n) convinputgen_node.set_nodeattr("SIMD", pe) - elif n.op_type == "VectorVectorActivation_hls": + elif n.op_type.startswith("VectorVectorActivation"): vvau_node = getCustomOp(n) vvau_node.set_nodeattr("PE", pe) From 7b50f168a6b55c4ffe84fc1793ec1b77d3d903e1 Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 25 Mar 2024 11:25:35 +0000 Subject: [PATCH 642/665] [Docs] Update manually written docs --- docs/finn/developers.rst | 31 +++++++--------- docs/finn/faq.rst | 21 +---------- docs/finn/img/repo-structure.png | Bin 83241 -> 83069 bytes docs/finn/internals.rst | 60 +++++++++++++------------------ 4 files changed, 37 insertions(+), 75 deletions(-) diff --git a/docs/finn/developers.rst b/docs/finn/developers.rst index 1e1c48e2b5..3b182b8db8 100644 --- a/docs/finn/developers.rst +++ b/docs/finn/developers.rst @@ -10,7 +10,7 @@ Power users may also find this information useful. Prerequisites ================ -Before starting to do development on FINN it's a good idea to start +Before starting to do development on FINN it is a good idea to start with understanding the basics as a user. Going through all of the :ref:`tutorials` is strongly recommended if you haven't already done so. Additionally, please review the documentation available on :ref:`internals`. @@ -61,7 +61,7 @@ further detailed below: Docker images =============== -If you want to add new dependencies (packages, repos) to FINN it's +If you want to add new dependencies (packages, repos) to FINN it is important to understand how we handle this in Docker. The finn.dev image is built and launched as follows: @@ -70,7 +70,7 @@ The finn.dev image is built and launched as follows: 2. run-docker.sh launches the build of the Docker image with `docker build` (unless ``FINN_DOCKER_PREBUILT=1``). Docker image is built from docker/Dockerfile.finn using the following steps: - * Base: PyTorch dev image + * Base: Ubuntu 22.04 LTS image * Set up apt dependencies: apt-get install a few packages for verilator and * Set up pip dependencies: Python packages FINN depends on are listed in requirements.txt, which is copied into the container and pip-installed. Some additional packages (such as Jupyter and Netron) are also installed. * Install XRT deps, if needed: For Vitis builds we need to install the extra dependencies for XRT. This is only triggered if the image is built with the INSTALL_XRT_DEPS=1 argument. @@ -84,9 +84,9 @@ The finn.dev image is built and launched as follows: 4. Entrypoint script (docker/finn_entrypoint.sh) upon launching container performs the following: - * Source Vivado settings64.sh from specified path to make vivado and vivado_hls available. - * Download PYNQ board files into the finn root directory, unless they already exist. - * Source Vitits settings64.sh if Vitis is mounted. + * Source Vivado settings64.sh from specified path to make vivado and vitis_hls available. + * Download board files into the finn root directory, unless they already exist or ``FINN_SKIP_BOARD_FILES=1``. + * Source Vitis settings64.sh if Vitis is mounted. 5. Depending on the arguments to run-docker.sh a different application is launched. run-docker.sh notebook launches a Jupyter server for the tutorials, whereas run-docker.sh build_custom and run-docker.sh build_dataflow trigger a dataflow build (see documentation). Running without arguments yields an interactive shell. See run-docker.sh for other options. @@ -106,7 +106,7 @@ Linting We use a pre-commit hook to auto-format Python code and check for issues. See https://pre-commit.com/ for installation. Once you have pre-commit, you can install the hooks into your local clone of the FINN repo. -It's recommended to do this **on the host** and not inside the Docker container: +It is recommended to do this **on the host** and not inside the Docker container: :: @@ -119,7 +119,7 @@ you may have to fix it manually, then run `git commit` once again. The checks are configured in .pre-commit-config.yaml under the repo root. Testing -======= +======== Tests are vital to keep FINN running. All the FINN tests can be found at https://github.com/Xilinx/finn/tree/main/tests. These tests can be roughly grouped into three categories: @@ -132,7 +132,7 @@ These tests can be roughly grouped into three categories: Additionally, qonnx, brevitas and finn-hlslib also include their own test suites. The full FINN compiler test suite -(which will take several hours to run and require a PYNQ board) can be executed +(which will take several hours to run) can be executed by: :: @@ -146,7 +146,7 @@ requiring Vivado or as slow-running tests: bash ./run-docker.sh quicktest -When developing a new feature it's useful to be able to run just a single test, +When developing a new feature it is useful to be able to run just a single test, or a group of tests that e.g. share the same prefix. You can do this inside the Docker container from the FINN root directory as follows: @@ -178,16 +178,9 @@ FINN provides two types of documentation: * manually written documentation, like this page * autogenerated API docs from Sphinx -Everything is built using Sphinx, which is installed into the finn.dev -Docker image. You can build the documentation locally by running the following -inside the container: - -:: - - python setup.py docs +Everything is built using Sphinx. -You can view the generated documentation on build/html/index.html. -The documentation is also built online by readthedocs: +The documentation is built online by readthedocs: * finn.readthedocs.io contains the docs from the master branch * finn-dev.readthedocs.io contains the docs from the dev branch diff --git a/docs/finn/faq.rst b/docs/finn/faq.rst index ef4457f53a..70c2f24ed2 100644 --- a/docs/finn/faq.rst +++ b/docs/finn/faq.rst @@ -7,16 +7,6 @@ Frequently Asked Questions Can't find the answer to your question here? Check `FINN GitHub Discussions `_. -Can I install FINN out of the Docker container? - We do not support out of the Docker implementations at the moment. This is due - to the high complexity of the FINN project dependencies. - -Since FINN uses ONNX, can I compile any model from the ONNX Model Zoo to an FPGA accelerator? - The short answer is no. FINN uses ONNX in a specific (non-standard) way, including custom layer - types and quantization annotations. Networks must be first quantized using Brevitas and exported - to FINN-ONNX to be converted to FPGA accelerators. - - Can I install FINN out of the Docker container? We do not support out of the Docker implementations at the moment. This is due to the high complexity of the FINN project dependencies. @@ -52,7 +42,6 @@ What operating systems are supported by FINN? FINN should work fine under any Linux-based OS capable of running Vivado/Vitis, as long as you install Docker (``docker-ce``) on your machine. - I am getting DocNav and Model_Composer errors when launching the Docker image. We do not mount those particular directories into the Docker container because they are not used. The errors are Vivado related but you can safely ignore them. @@ -74,16 +63,8 @@ How can I target an arbitrary Xilinx FPGA without PYNQ support? Why does FINN-generated architectures need FIFOs between layers? See https://github.com/Xilinx/finn/discussions/383 -How do I tell FINN to utilize DSPs instead of LUTs for MAC operations in particular layers? - This is done with the ``resType="dsp"`` attribute on ``MatrixVectorActivation`` and ``Vector_Vector_Activate`` instances. - When using the ``build_dataflow`` system, this can be specified at a per layer basis by specifying it as part of one or more layers’ - folding config (:py:mod:`finn.builder.build_dataflow_config.DataflowBuildConfig.folding_config_file`). - This is a good idea for layers with more weight/input act bits and high PE*SIMD. - See the `MobileNet-v1 build config for ZCU104 in finn-examples `_ for reference. - - How do I tell FINN to utilize a particular type of memory resource in particular layers? - This is done with the ``ram_style`` attribute. Check the particular ``HLSCustomOp`` attribute definition to see + This is done with the ``ram_style`` attribute. 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Custom Operations/Nodes FINN uses many custom operations (op_type in ONNX NodeProto) that are not defined in the ONNX operator schema. These custom nodes are marked with domain="finn.*" or domain="qonnx.*" in the protobuf to identify them as such. These nodes can represent specific operations that we need for low-bit networks, or operations that are specific to a particular hardware backend. To get more familiar with custom operations and how they are created, please take a look in the Jupyter notebook about CustomOps (see chapter :ref:`tutorials` for details) or directly in the module :py:mod:`finn.custom_op`. -.. note:: See the description of `this PR `_ for more on how the operator wrapper library is organized. - Custom ONNX Execution Flow ========================== @@ -137,7 +135,7 @@ ModelWrapper contains more useful functions, if you are interested please have a Analysis Pass ============= -An analysis pass traverses the graph structure and produces information about certain properties. It gets the model in the ModelWrapper as input and returns a dictionary of the properties the analysis extracts. If you are interested in how to write an analysis pass for FINN, please take a look at the Jupyter notebook about how to write an analysis pass, see chapter :ref:`tutorials` for details. For more information about existing analysis passes in FINN, see module :py:mod:`finn.analysis` . +An analysis pass traverses the graph structure and produces information about certain properties. It gets the model in the ModelWrapper as input and returns a dictionary of the properties the analysis extracts. If you are interested in how to write an analysis pass for FINN, please take a look at the Jupyter notebook about how to write an analysis pass, see chapter :ref:`tutorials` for details. For more information about existing analysis passes in FINN, see module :py:mod:`finn.analysis`. .. _transformation_pass: @@ -148,26 +146,26 @@ A transformation passes changes (transforms) the given model, it gets the model .. _mem_mode: -MatrixVectorActivation *mem_mode* -================================== +HLS variant of MatrixVectorActivation: *mem_mode* +================================================= FINN supports three types of the so-called *mem_mode* attrıbute for the node MatrixVectorActivation. This mode controls how the weight values are accessed during the execution. That means the mode setting has direct influence on the resulting circuit. Currently three settings for the *mem_mode* are supported in FINN: -* "const" +* "internal_embedded" (former "const" mode) -* "decoupled" +* "internal_decoupled" (former "decoupled" mode) * "external" -The following picture shows the idea behind the "const" and "decoupled" mode. +The following picture shows the idea behind the "internal_embedded" and "internal_decoupled" mode. .. image:: img/mem_mode.png :scale: 55% :align: center -Const mode ----------- -In *const* mode the weights are "baked in" into the Matrix-Vector-Activate-Unit (MVAU), which means they are part of the HLS code. During the IP block generation the weight values are integrated as *params.h* file in the HLS code and synthesized together with it. For the *const* mode IP block generation the `Matrix_Vector_Activate_Batch function `_ from the finn-hls library is used, which implements a standard MVAU. The resulting IP block has an input and an output stream, as shown in the above picture on the left. FIFOs in the form of verilog components are connected to these. +Internal_embedded mode +------------------------ +In *internal_embedded* mode the weights are "baked in" into the Matrix-Vector-Activate-Unit (MVAU), which means they are part of the HLS code. During the IP block generation the weight values are integrated as *params.h* file in the HLS code and synthesized together with it. For the *internal_embedded* mode IP block generation the `Matrix_Vector_Activate_Batch function `_ from the finn-hls library is used, which implements a standard MVAU. The resulting IP block has an input and an output stream, as shown in the above picture on the left. FIFOs in the form of verilog components are connected to these. Advantages: @@ -175,17 +173,15 @@ Advantages: * easier to debug layer in cppsim since no additional components -* well-tested and mature components - Disadvantages: * can lead to very long HLS synthesis times for certain weight array shapes * less control over the weight memory FPGA primitives, Vivado HLS doesn't always make the best resource allocation decisions -Decoupled mode --------------- -In *decoupled* mode a different variant of the MVAU with three ports is used. Besides the input and output streams, which are fed into the circuit via Verilog FIFOs, there is another input, which is used to stream the weights. For this the `streaming MVAU `_ from the finn-hls library is used. To make the streaming possible a Verilog weight streamer component accesses the weight memory and sends the values via another FIFO to the MVAU. This component can be found in the `finn-rtllib `_ under the name *memstream.v*. For the IP block generation this component, the IP block resulting from the synthesis of the HLS code of the streaming MVAU and a FIFO for the weight stream are combined in a verilog wrapper. The weight values are saved in .dat files and stored in the weight memory from which the weight streamer reads. The resulting verilog component, which is named after the name of the node and has the suffix "_memstream.v", exposes only two ports to the outside, the data input and output. It therefore behaves externally in the same way as the MVAU in *const* mode. +Internal_decoupled mode +------------------------ +In *internal_decoupled* mode a different variant of the MVAU with three ports is used. Besides the input and output streams, which are fed into the circuit via Verilog FIFOs, there is another input, which is used to stream the weights. For this the `streaming MVAU `_ from the finn-hls library is used. To make the streaming possible a Verilog weight streamer component accesses the weight memory and sends the values via another FIFO to the MVAU. This component can be found in the `finn-rtllib `_ under the name *memstream.v*. For the IP block generation this component, the IP block resulting from the synthesis of the HLS code of the streaming MVAU and a FIFO for the weight stream are combined in a verilog wrapper. The weight values are saved in .dat files and stored in the weight memory from which the weight streamer reads. The resulting verilog component, which is named after the name of the node and has the suffix "_memstream.v", exposes only two ports to the outside, the data input and output. It therefore behaves externally in the same way as the MVAU in *internal_embedded* mode. Advantages: @@ -197,14 +193,12 @@ Advantages: Disadvantages: -* somewhat less well-tested compared to the const mode - -* higher resource footprint due to additional weight streamer and weight FIFO +* slightly higher resource footprint due to additional weight streamer and weight FIFO How to set *mem_mode* --------------------- -When the nodes in the network are converted to HLS layers, the *mem_mode* can be passed. More detailed information about the transformations that prepare the network and the transformation that performs the conversion to HLS layers can be found in chapter :ref:`nw_prep`. The *mem_mode* is passed as argument. Note that if no argument is passed, the default is *const*. +When the nodes in the network are specialized to HLS layers, the *mem_mode* can be passed. More detailed information about the transformations that prepare the network and the transformation that performs the specialization to HLS layers can be found in chapter :ref:`nw_prep`. The *mem_mode* is set in the node attributes of the nodes and can be passed as part of the folding configuration. The default is *internal_decoupled*. .. _folding_factors: @@ -217,46 +211,43 @@ Constraints to folding factors per layer * - **Layers** - **Parameters** - **Constraints** - * - Addstreams_Batch + * - Addstreams - PE - inp_channels % PE == 0 - * - ChannelwiseOp_Batch + * - ChannelwiseOp - PE - channels % PE == 0 * - ConvolutionInputGenerator - SIMD - inp_channels % SIMD == 0 - * - ConvolutionInputGenerator1d - - SIMD - - inp_channels % SIMD == 0 * - Downsampler - SIMD - inp_channels % SIMD == 0 - * - DuplicateStreams_Batch + * - DuplicateStreams - PE - channels % PE == 0 - * - Eltwise + * - StreamingEltwise - PE - inp_channels % PE == 0 - * - FMPadding_batch + * - FMPadding - SIMD - inp_channels % SIMD == 0 - * - FMPadding_rtl + * - FMPadding_Pixel - SIMD - inp_channels % SIMD == 0 - * - Globalaccpool_Batch + * - Globalaccpool - PE - channels % PE == 0 - * - Labelselect_Batch + * - Labelselect - PE - num_labels % PE == 0 * - MatrixVectorActivation - PE & SIMD - MH % PE == 0 & MW % SIMD == 0 - * - Pool_Batch + * - Pool - PE - inp_channels % PE == 0 - * - Thresholding_Batch + * - Thresholding - PE - MH % PE == 0 * - VectorVectorActivation @@ -280,9 +271,6 @@ This RTL version is an alternative to the original `HLS implementation Date: Mon, 25 Mar 2024 11:37:51 +0000 Subject: [PATCH 643/665] [transform]: remove resType selection of VVAU --- src/finn/transformation/fpgadataflow/convert_to_hw_layers.py | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py index e2f638ed62..897d714bf8 100644 --- a/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py +++ b/src/finn/transformation/fpgadataflow/convert_to_hw_layers.py @@ -1644,7 +1644,6 @@ def apply(self, model): [mt_output], domain="finn.custom_op.fpgadataflow", backend="fpgadataflow", - resType="lut", PE=pe, Dim=[mm_in_shape[1], mm_in_shape[2]], Channels=channels, @@ -1673,7 +1672,6 @@ def apply(self, model): [mm_output], domain="finn.custom_op.fpgadataflow", backend="fpgadataflow", - resType="lut", PE=pe, Dim=[mm_in_shape[1], mm_in_shape[2]], Channels=channels, From e8ae3c44eaf91d93ee298c00e71d68b4fdaa645b Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Mon, 25 Mar 2024 11:38:07 +0000 Subject: [PATCH 644/665] [tests]: renamed VectorVectorActivation to VVAU --- tests/fpgadataflow/test_depthwise_convolution.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/fpgadataflow/test_depthwise_convolution.py b/tests/fpgadataflow/test_depthwise_convolution.py index bde5e918e3..24bc2f3afe 100644 --- a/tests/fpgadataflow/test_depthwise_convolution.py +++ b/tests/fpgadataflow/test_depthwise_convolution.py @@ -190,7 +190,7 @@ def test_depthwise_conv_hw_cppsim(act, pe, k, stride, padding): if n.op_type.startswith("ConvolutionInputGenerator"): convinputgen_node = getCustomOp(n) convinputgen_node.set_nodeattr("SIMD", pe) - elif n.op_type.startswith("VectorVectorActivation"): + elif n.op_type.startswith("VVAU"): vvau_node = getCustomOp(n) vvau_node.set_nodeattr("PE", pe) new_model = new_model.transform(SetExecMode("cppsim")) @@ -235,7 +235,7 @@ def test_depthwise_conv_hw_rtlsim(act, pe, k, stride, padding): if n.op_type.startswith("ConvolutionInputGenerator"): convinputgen_node = getCustomOp(n) convinputgen_node.set_nodeattr("SIMD", pe) - elif n.op_type.startswith("VectorVectorActivation"): + elif n.op_type.startswith("VVAU"): vvau_node = getCustomOp(n) vvau_node.set_nodeattr("PE", pe) From e057fc9a121fefbe2410f255e4fff08ea39bff44 Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 25 Mar 2024 11:48:02 +0000 Subject: [PATCH 645/665] [Docs] Update top level markdown files Signed-off-by: auphelia --- CHANGELOG.rst | 10 --------- CONTRIBUTING.md | 54 ++++++++++++++++++++++++++++++++++++++++++++++++- LICENSE.txt | 3 ++- README.md | 7 +++---- 4 files changed, 58 insertions(+), 16 deletions(-) delete mode 100644 CHANGELOG.rst diff --git a/CHANGELOG.rst b/CHANGELOG.rst deleted file mode 100644 index 226e6f5931..0000000000 --- a/CHANGELOG.rst +++ /dev/null @@ -1,10 +0,0 @@ -========= -Changelog -========= - -Version 0.1 -=========== - -- Feature A added -- FIX: nasty bug #1729 fixed -- add your changes here! diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index d376a1b42b..53a505fb41 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -29,6 +29,58 @@ Please follow the steps below and be sure that your contribution complies with o 1. The main branch should always be treated as stable and clean. Only hot fixes are allowed to be pull-requested. The hot fix is supposed to be very important such that without this fix, a lot of things will break. 2. For new features, smaller bug fixes, doc updates, and many other fixes, users should pull request against the development branch. -3. We will review your contribution and, if any additional fixes or modifications are +3. ### 3. Sign Your Work + +Please use the *Signed-off-by* line at the end of your patch which indicates that you accept the Developer Certificate of Origin (DCO) defined by https://developercertificate.org/ reproduced below:: + +``` + Developer Certificate of Origin + Version 1.1 + + Copyright (C) 2004, 2006 The Linux Foundation and its contributors. + 1 Letterman Drive + Suite D4700 + San Francisco, CA, 94129 + + Everyone is permitted to copy and distribute verbatim copies of this + license document, but changing it is not allowed. + + + Developer's Certificate of Origin 1.1 + + By making a contribution to this project, I certify that: + + (a) The contribution was created in whole or in part by me and I + have the right to submit it under the open source license + indicated in the file; or + + (b) The contribution is based upon previous work that, to the best + of my knowledge, is covered under an appropriate open source + license and I have the right under that license to submit that + work with modifications, whether created in whole or in part + by me, under the same open source license (unless I am + permitted to submit under a different license), as indicated + in the file; or + + (c) The contribution was provided directly to me by some other + person who certified (a), (b) or (c) and I have not modified + it. + + (d) I understand and agree that this project and the contribution + are public and that a record of the contribution (including all + personal information I submit with it, including my sign-off) is + maintained indefinitely and may be redistributed consistent with + this project or the open source license(s) involved. +``` + +Here is an example Signed-off-by line which indicates that the contributor accepts DCO:: + +``` + This is my commit message + + Signed-off-by: Jane Doe +``` + +4. We will review your contribution and, if any additional fixes or modifications are necessary, may provide feedback to guide you. When accepted, your pull request will be merged to the repository. If you have more questions please contact us. diff --git a/LICENSE.txt b/LICENSE.txt index 278564a5a4..cec78d6043 100644 --- a/LICENSE.txt +++ b/LICENSE.txt @@ -1,4 +1,5 @@ -Copyright (c) 2020, Xilinx +Copyright (C) 2020-2022, Xilinx, Inc. +Copyright (C) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/README.md b/README.md index 2e1faf8f0c..0856701908 100644 --- a/README.md +++ b/README.md @@ -2,13 +2,12 @@ -drawing +drawing [![GitHub Discussions](https://img.shields.io/badge/discussions-join-green)](https://github.com/Xilinx/finn/discussions) [![ReadTheDocs](https://readthedocs.org/projects/finn/badge/?version=latest&style=plastic)](http://finn.readthedocs.io/) -FINN is an experimental framework from Xilinx Research Labs to explore deep neural network -inference on FPGAs. +FINN is an experimental framework from Integrated Communications and AI Lab of AMD Research & Advanced Development to explore deep neural network inference on FPGAs. It specifically targets quantized neural networks, with emphasis on generating dataflow-style architectures customized for each network. @@ -28,7 +27,7 @@ Please see the [Getting Started](https://finn.readthedocs.io/en/latest/getting_s ## Documentation -You can view the documentation on [readthedocs](https://finn.readthedocs.io) or build them locally using `python setup.py doc` from inside the Docker container. Additionally, there is a series of [Jupyter notebook tutorials](https://github.com/Xilinx/finn/tree/main/notebooks), which we recommend running from inside Docker for a better experience. +You can view the documentation on [readthedocs](https://finn.readthedocs.io). Additionally, there is a series of [Jupyter notebook tutorials](https://github.com/Xilinx/finn/tree/main/notebooks), which we recommend running from inside Docker for a better experience. ## Community From 7b138408166ce574a85ea1b4e62655262a36fe88 Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 25 Mar 2024 11:50:18 +0000 Subject: [PATCH 646/665] [Docs] Fix typo in CONTRIBUTING markdown Signed-off-by: auphelia --- CONTRIBUTING.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index 53a505fb41..3f4529c400 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -29,7 +29,7 @@ Please follow the steps below and be sure that your contribution complies with o 1. The main branch should always be treated as stable and clean. Only hot fixes are allowed to be pull-requested. The hot fix is supposed to be very important such that without this fix, a lot of things will break. 2. For new features, smaller bug fixes, doc updates, and many other fixes, users should pull request against the development branch. -3. ### 3. Sign Your Work +3. Sign Your Work Please use the *Signed-off-by* line at the end of your patch which indicates that you accept the Developer Certificate of Origin (DCO) defined by https://developercertificate.org/ reproduced below:: From d4fbd21e1320e05a03ffe58a2cb35e5ce3b6c954 Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 25 Mar 2024 12:02:02 +0000 Subject: [PATCH 647/665] [Docs] Update AUTHORS md Signed-off-by: auphelia --- AUTHORS.rst | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/AUTHORS.rst b/AUTHORS.rst index 861b81924b..5a11497fc8 100644 --- a/AUTHORS.rst +++ b/AUTHORS.rst @@ -28,3 +28,9 @@ Contributors * Matthias Gehre (@mgehre-amd) * Hugo Le Blevec (@hleblevec) * Patrick Geel (@patrickgeel) +* John Monks (@jmonks-amd) +* Tim Paine (@timkpaine) +* Linus Jungemann (@LinusJungemann) +* Shashwat Khandelwal (@shashwat1198) +* Ian Colbert (@i-colbert) +* Rachit Garg (@rstar900) From 6d036947dea5ad7a75e1bbdda644017ae3b59c9a Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 25 Mar 2024 15:33:55 +0000 Subject: [PATCH 648/665] [Tests/Docs] Set SWG to HLS for depthwise conv cppsim tests --- CONTRIBUTING.md | 4 +++- tests/fpgadataflow/test_depthwise_convolution.py | 6 ++++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index 3f4529c400..5e34624790 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -73,7 +73,9 @@ Please use the *Signed-off-by* line at the end of your patch which indicates tha this project or the open source license(s) involved. ``` -Here is an example Signed-off-by line which indicates that the contributor accepts DCO:: +You can enable Signed-off-by automatically by adding the `-s` flag to the `git commit` command. + +Here is an example Signed-off-by line which indicates that the contributor accepts DCO: ``` This is my commit message diff --git a/tests/fpgadataflow/test_depthwise_convolution.py b/tests/fpgadataflow/test_depthwise_convolution.py index 24bc2f3afe..a45f253530 100644 --- a/tests/fpgadataflow/test_depthwise_convolution.py +++ b/tests/fpgadataflow/test_depthwise_convolution.py @@ -182,6 +182,12 @@ def test_depthwise_conv_hw_cppsim(act, pe, k, stride, padding): new_model = model.transform(InferConvInpGen()) new_model = new_model.transform(InferVectorVectorActivation()) + # CPPsim of RTL SWG defaults to Im2Col emulation which has no concept + # of parallelism. So, we're using the HLS-SWG for cppsim testing for now. + # Set preferred_impl_style to hls to instantiate HLS-SWG + swg_nodes = new_model.get_nodes_by_op_type("ConvolutionInputGenerator")[0] + getCustomOp(swg_nodes).set_nodeattr("preferred_impl_style", "hls") + new_model = new_model.transform(SpecializeLayers()) # set SIMD in ConvInputGen node and PE in VVAU node From 00e6e51ac70522afa7f15a08d2536c328ff9746f Mon Sep 17 00:00:00 2001 From: auphelia Date: Mon, 25 Mar 2024 17:30:20 +0000 Subject: [PATCH 649/665] [Deps] Update dockerfile with new copyright header --- docker/Dockerfile.finn | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/docker/Dockerfile.finn b/docker/Dockerfile.finn index 9d7ca809db..2ceb1f4195 100644 --- a/docker/Dockerfile.finn +++ b/docker/Dockerfile.finn @@ -1,4 +1,5 @@ -# Copyright (c) 2021, Xilinx +# Copyright (C) 2021-2022, Xilinx, Inc. +# Copyright (C) 2022-2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -27,7 +28,7 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. FROM ubuntu:jammy-20230126 -LABEL maintainer="Yaman Umuroglu " +LABEL maintainer="Jakoba Petri-Koenig , Yaman Umuroglu " ARG XRT_DEB_VERSION="xrt_202220.2.14.354_22.04-amd64-xrt" From 1e97e9721b30b16f5436fb0fce4d1df215dc7574 Mon Sep 17 00:00:00 2001 From: johnnoel Date: Tue, 26 Mar 2024 10:05:06 +0000 Subject: [PATCH 650/665] [Tests] Force HLS components for special case cnv-2-2 on u250 and pynq-z1 --- tests/end2end/test_end2end_bnn_pynq.py | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index a25d7e6725..5b295655df 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -104,6 +104,7 @@ get_trained_network_and_ishape, load_test_checkpoint_or_skip, ) +from finn.util.fpgadataflow import is_fpgadataflow_node build_dir = os.environ["FINN_BUILD_DIR"] target_clk_ns = 20 @@ -598,6 +599,12 @@ def test_specialize_layers(self, topology, wbits, abits, board): prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, "convert_to_hw_layers") model = load_test_checkpoint_or_skip(prev_chkpt_name) # set preferred impl style to hls for all layers + force_hls_boards = ["Pynq-Z1", "U250"] + if topology == "cnv" and wbits == 2 and abits == 2 and board in force_hls_boards: + for node in model.graph.node: + if is_fpgadataflow_node(node): + inst = getCustomOp(node) + inst.set_nodeattr("preferred_impl_style", "hls") model = model.transform(SpecializeLayers()) model = model.transform(GiveUniqueNodeNames()) model.save(get_checkpoint_name(topology, wbits, abits, "specialize_layers")) @@ -628,9 +635,19 @@ def test_specialize_layers(self, topology, wbits, abits, board): ("StreamingMaxPool_hls", 2), ("LabelSelect_hls", 1), ], + "cnv-2-2": [ + ("Transpose", 1), + ("Thresholding_hls", 1), + ("ConvolutionInputGenerator_hls", 6), + ("MVAU_hls", 9), + ("StreamingMaxPool_hls", 2), + ("LabelSelect_hls", 1), + ], } if topology == "tfc" and wbits == 1 and abits == 1: exp_key = "tfc-1-1" + elif topology == "cnv" and wbits == 2 and abits == 2 and board in force_hls_boards: + exp_key = "cnv-2-2" else: exp_key = topology exp_layer_counts = exp_layer_counts[exp_key] From aa361f5d8a1b083538da3dcb8f07f47879823588 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Tue, 26 Mar 2024 11:49:47 +0000 Subject: [PATCH 651/665] [rtl swg]: interleave channels for CPPsim --- .../rtl/convolutioninputgenerator_rtl.py | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/finn/custom_op/fpgadataflow/rtl/convolutioninputgenerator_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/convolutioninputgenerator_rtl.py index 68760227d7..cb4ce1e884 100755 --- a/src/finn/custom_op/fpgadataflow/rtl/convolutioninputgenerator_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/convolutioninputgenerator_rtl.py @@ -33,6 +33,7 @@ from qonnx.core.datatype import DataType from qonnx.custom_op.general import im2col from qonnx.custom_op.general.im2col import compute_conv_output_dim +from qonnx.custom_op.registry import getCustomOp from qonnx.util.basic import roundup_to_integer_multiple from finn.custom_op.fpgadataflow.convolutioninputgenerator import ( @@ -290,6 +291,19 @@ def execute_node(self, context, graph): if mode == "cppsim": ConvolutionInputGenerator.execute_node(self, context, graph) + # Interleave channels such that cppsim of ConvolutionInputGenerator_rtl + # has a notion of SIMD parallelism. Subsequent VVAU_{hls/rtl} expects + # the channels to be interleaved (i.e. to match their PE parallelism). + node = self.onnx_node + im2col_out = context[node.output[0]] + simd = getCustomOp(node).get_nodeattr("SIMD") + ofm_h, ofm_w = getCustomOp(node).get_nodeattr("OFMDim") + k_h, k_w = getCustomOp(node).get_nodeattr("ConvKernelDim") + ifm_ch = getCustomOp(node).get_nodeattr("IFMChannels") + im2col_out = im2col_out.reshape(1, ofm_h, ofm_w, k_h * k_w, ifm_ch // simd, simd) + im2col_out = im2col_out.transpose(0, 1, 2, 4, 3, 5) + im2col_out = im2col_out.reshape(1, ofm_h, ofm_w, ifm_ch * k_h * k_w) + context[node.output[0]] = im2col_out elif mode == "rtlsim": node = self.onnx_node exp_ishape = self.get_normal_input_shape() From 87d11c6c3659ca060274eb76f49bdddc54119208 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Tue, 26 Mar 2024 11:50:40 +0000 Subject: [PATCH 652/665] [vvau]: RTL-swg in cppsim now interleaves channels -- updated 'pe' selection --- .../custom_op/fpgadataflow/vectorvectoractivation.py | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index 7f1bf72964..ef80b24a2e 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -122,15 +122,12 @@ def execute_node(self, context, graph): (k_h, k_w) = self.get_nodeattr("Kernel") channels = self.get_nodeattr("Channels") producer = [x for x in graph.node if x.output[0] == node.input[0]] - exec_mode = self.get_nodeattr("exec_mode") - if ( - not bool(producer) - or producer[0].op_type == "ConvolutionInputGenerator_hls" - or (producer[0].op_type == "ConvolutionInputGenerator_rtl" and exec_mode == "rtlsim") + if bool(producer) and ( + producer[0].op_type == "Im2Col" or producer[0].op_type == "ConvolutionInputGenerator" ): - pe = self.get_nodeattr("PE") - else: pe = channels + else: + pe = self.get_nodeattr("PE") # Reorder the input activations. Note that PE gets interleaved by the SWG, # so we have to untangle and for simplicity of computation assume pe=1. From 42852dfe87899969974bc47f897d66e77d2829d9 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Tue, 26 Mar 2024 13:56:34 +0000 Subject: [PATCH 653/665] [tests]: remove defaulting SWG to HLS --- tests/fpgadataflow/test_depthwise_convolution.py | 8 -------- 1 file changed, 8 deletions(-) diff --git a/tests/fpgadataflow/test_depthwise_convolution.py b/tests/fpgadataflow/test_depthwise_convolution.py index a45f253530..b8242df933 100644 --- a/tests/fpgadataflow/test_depthwise_convolution.py +++ b/tests/fpgadataflow/test_depthwise_convolution.py @@ -182,16 +182,9 @@ def test_depthwise_conv_hw_cppsim(act, pe, k, stride, padding): new_model = model.transform(InferConvInpGen()) new_model = new_model.transform(InferVectorVectorActivation()) - # CPPsim of RTL SWG defaults to Im2Col emulation which has no concept - # of parallelism. So, we're using the HLS-SWG for cppsim testing for now. - # Set preferred_impl_style to hls to instantiate HLS-SWG - swg_nodes = new_model.get_nodes_by_op_type("ConvolutionInputGenerator")[0] - getCustomOp(swg_nodes).set_nodeattr("preferred_impl_style", "hls") - new_model = new_model.transform(SpecializeLayers()) # set SIMD in ConvInputGen node and PE in VVAU node - for n in new_model.graph.node: if n.op_type.startswith("ConvolutionInputGenerator"): convinputgen_node = getCustomOp(n) @@ -236,7 +229,6 @@ def test_depthwise_conv_hw_rtlsim(act, pe, k, stride, padding): new_model = new_model.transform(SpecializeLayers()) # set SIMD in ConvInputGen node and PE in VVAU node - for n in new_model.graph.node: if n.op_type.startswith("ConvolutionInputGenerator"): convinputgen_node = getCustomOp(n) From 86e28e4765347f5ccd0bfcbde675f5b631a3f95f Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 26 Mar 2024 15:39:13 +0000 Subject: [PATCH 654/665] [Tests] Enable interleaving of output for dw only --- .../rtl/convolutioninputgenerator_rtl.py | 24 ++++++++++--------- .../test_fpgadataflow_convinputgenerator.py | 5 +--- 2 files changed, 14 insertions(+), 15 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/rtl/convolutioninputgenerator_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/convolutioninputgenerator_rtl.py index cb4ce1e884..321522e7ba 100755 --- a/src/finn/custom_op/fpgadataflow/rtl/convolutioninputgenerator_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/convolutioninputgenerator_rtl.py @@ -291,19 +291,21 @@ def execute_node(self, context, graph): if mode == "cppsim": ConvolutionInputGenerator.execute_node(self, context, graph) - # Interleave channels such that cppsim of ConvolutionInputGenerator_rtl + # if depthwise = 1 + # interleave channels such that cppsim of ConvolutionInputGenerator_rtl # has a notion of SIMD parallelism. Subsequent VVAU_{hls/rtl} expects # the channels to be interleaved (i.e. to match their PE parallelism). - node = self.onnx_node - im2col_out = context[node.output[0]] - simd = getCustomOp(node).get_nodeattr("SIMD") - ofm_h, ofm_w = getCustomOp(node).get_nodeattr("OFMDim") - k_h, k_w = getCustomOp(node).get_nodeattr("ConvKernelDim") - ifm_ch = getCustomOp(node).get_nodeattr("IFMChannels") - im2col_out = im2col_out.reshape(1, ofm_h, ofm_w, k_h * k_w, ifm_ch // simd, simd) - im2col_out = im2col_out.transpose(0, 1, 2, 4, 3, 5) - im2col_out = im2col_out.reshape(1, ofm_h, ofm_w, ifm_ch * k_h * k_w) - context[node.output[0]] = im2col_out + if self.get_nodeattr("depthwise"): + node = self.onnx_node + im2col_out = context[node.output[0]] + simd = getCustomOp(node).get_nodeattr("SIMD") + ofm_h, ofm_w = getCustomOp(node).get_nodeattr("OFMDim") + k_h, k_w = getCustomOp(node).get_nodeattr("ConvKernelDim") + ifm_ch = getCustomOp(node).get_nodeattr("IFMChannels") + im2col_out = im2col_out.reshape(1, ofm_h, ofm_w, k_h * k_w, ifm_ch // simd, simd) + im2col_out = im2col_out.transpose(0, 1, 2, 4, 3, 5) + im2col_out = im2col_out.reshape(1, ofm_h, ofm_w, ifm_ch * k_h * k_w) + context[node.output[0]] = im2col_out elif mode == "rtlsim": node = self.onnx_node exp_ishape = self.get_normal_input_shape() diff --git a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py index 02aaf85851..45ca74fbea 100644 --- a/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py +++ b/tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py @@ -217,10 +217,7 @@ def test_fpgadataflow_slidingwindow( # execute model y_produced = oxe.execute_onnx(model, input_dict)["outp"] - # if cppsim and impl style rtl is selected, the node execution is done by the hw op parent - # so, no reordering/shaping of the output is needed - # because there is no concept of SIMD parallelism in the hw abstraction layer execution - if dw == 0 or (optype == "ConvolutionInputGenerator_rtl" and exec_mode == "cppsim"): + if dw == 0: assert (y_produced == y_expected).all() else: y_expected = y_expected.reshape(1, ofm_dim_h, ofm_dim_w, k_h * k_w, ifm_ch // simd, simd) From 84654a34170819c035f021590970fa82b49973bb Mon Sep 17 00:00:00 2001 From: auphelia Date: Tue, 26 Mar 2024 17:24:24 +0000 Subject: [PATCH 655/665] Fix linting --- tests/end2end/test_end2end_bnn_pynq.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index 5b295655df..94134967fa 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -95,6 +95,7 @@ MoveScalarLinearPastInvariants, ) from finn.util.basic import get_finn_root, make_build_dir, test_board_map +from finn.util.fpgadataflow import is_fpgadataflow_node from finn.util.pytorch import ToTensor from finn.util.test import ( execute_parent, @@ -104,7 +105,6 @@ get_trained_network_and_ishape, load_test_checkpoint_or_skip, ) -from finn.util.fpgadataflow import is_fpgadataflow_node build_dir = os.environ["FINN_BUILD_DIR"] target_clk_ns = 20 From 9507e234d2a458c847ce8e43cac47df4bbe36192 Mon Sep 17 00:00:00 2001 From: aziz bahri Date: Wed, 27 Mar 2024 14:44:10 +0000 Subject: [PATCH 656/665] [Thresholding RTL] extract RAM trigger to json config --- src/finn/builder/build_dataflow_steps.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/finn/builder/build_dataflow_steps.py b/src/finn/builder/build_dataflow_steps.py index 7508981485..443d2df54c 100644 --- a/src/finn/builder/build_dataflow_steps.py +++ b/src/finn/builder/build_dataflow_steps.py @@ -432,6 +432,8 @@ def step_target_fps_parallelization(model: ModelWrapper, cfg: DataflowBuildConfi "resType", "mem_mode", "runtime_writeable_weights", + "depth_trigger_uram", + "depth_trigger_bram", ] extract_model_config_to_json(model, cfg.output_dir + "/auto_folding_config.json", hw_attrs) @@ -607,6 +609,8 @@ def step_set_fifo_depths(model: ModelWrapper, cfg: DataflowBuildConfig): "runtime_writeable_weights", "inFIFODepths", "outFIFODepths", + "depth_trigger_uram", + "depth_trigger_bram", ] extract_model_config_to_json(model, cfg.output_dir + "/final_hw_config.json", hw_attrs) From 10fa01e1d78dd47062acab7a835e00dd04bf9d4a Mon Sep 17 00:00:00 2001 From: auphelia Date: Thu, 28 Mar 2024 14:17:54 +0000 Subject: [PATCH 657/665] [Docs] Update recommended Vivado/Vitis version --- docker/finn_entrypoint.sh | 2 +- run-docker.sh | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/docker/finn_entrypoint.sh b/docker/finn_entrypoint.sh index 971f92beb6..61c8f78665 100644 --- a/docker/finn_entrypoint.sh +++ b/docker/finn_entrypoint.sh @@ -112,7 +112,7 @@ if [ -f "$HLS_PATH/settings64.sh" ];then else yecho "Unable to find $HLS_PATH/settings64.sh" yecho "Functionality dependent on Vitis HLS will not be available." - yecho "Please note that FINN needs at least version 2020.2 for Vitis HLS support." + yecho "Please note that FINN needs at least version 2020.2 for Vitis HLS support. Our recommendation is to use version 2022.2" yecho "If you need Vitis HLS, ensure HLS_PATH is set correctly and mounted into the Docker container." fi diff --git a/run-docker.sh b/run-docker.sh index 60fc7c4d6b..e732492728 100755 --- a/run-docker.sh +++ b/run-docker.sh @@ -47,7 +47,7 @@ if [ -z "$FINN_XILINX_PATH" ];then fi if [ -z "$FINN_XILINX_VERSION" ];then - recho "Please set the FINN_XILINX_VERSION to the version of the Xilinx tools to use (e.g. 2020.1)" + recho "Please set the FINN_XILINX_VERSION to the version of the Xilinx tools to use (e.g. 2022.2)" recho "FINN functionality depending on Vivado, Vitis or HLS will not be available." fi From dfd501eec5b503c23d933875a65e33448bf9ef0a Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Thu, 28 Mar 2024 14:30:57 +0000 Subject: [PATCH 658/665] [vvau]: removed estimation methods for lut/dsp (moved to specialized custom-ops) --- .../fpgadataflow/vectorvectoractivation.py | 78 ------------------- 1 file changed, 78 deletions(-) diff --git a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py index ef80b24a2e..d95c6eb7cc 100644 --- a/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py +++ b/src/finn/custom_op/fpgadataflow/vectorvectoractivation.py @@ -386,84 +386,6 @@ def uram_efficiency_estimation(self): uram_est_capacity = uram_est * 72 * 4096 return wbits / uram_est_capacity - def lut_estimation(self): - """Calculates resource estimations for LUTs based on: - - FINN-R: An End-to-End Deep-Learning Framework for Fast - Exploration of Quantized Neural Networks - - M. Blott, T. B. Preusser, N. J. Fraser, G. Gambardella, K. O'Brien, - Y. Umuroglu, M. Leeser and K. Vissers - - 12. Sep 2018 - """ - # TODO add in/out FIFO contributions - P = self.get_nodeattr("PE") - Q = self.get_nodeattr("SIMD") - wdt = self.get_weight_datatype() - W = wdt.bitwidth() - # determine tdt with input and weight data types - idt = self.get_input_datatype() - A = idt.bitwidth() - # parameters from experiments in paper mentioned above - c0 = 300 - c1 = 1.1 - c2 = 0 - mmode = self.get_nodeattr("mem_mode") - mstyle = self.get_nodeattr("ram_style") - if (mmode == "internal_decoupled" and mstyle == "distributed") or ( - mmode == "internal_embedded" and self.calc_wmem() <= 128 - ): - c2 = (P * Q * W) * math.ceil(self.calc_wmem() / 64) - - # multiplication - res_type = self.get_nodeattr("resType") - if res_type == "dsp": - mult_luts = 0 - else: - mult_luts = Q * (2 * math.ceil((W + A) / 6) - 1) * (W + A) - # adder tree - addertree_luts = (W + A) * (2 * Q - 1) - # accumulator - acc_datatype = self.get_accumulator_datatype() - acc_bits = acc_datatype.bitwidth() - k_h, k_w = self.get_nodeattr("Kernel") - # if accDataType is not set, then it will default to INT32, which would - # be a large overestimate in most (if not all) cases. In this scenario, - # we would use the minimum accumulator as determined by the data types - # bound, derived in https://arxiv.org/abs/2301.13376 - alpha = math.log(k_h * k_w, 2) + W + A - 1 - int(idt.signed()) - acc_bits = min( - acc_datatype.bitwidth(), - np.ceil(alpha + math.log(1 + pow(2, -alpha), 2) + 1), - ) - acc_luts = acc_bits - # thresholds and threshold comparators - thr_luts = 0 - comp_luts = 0 - noact = self.get_nodeattr("noActivation") - # TODO - add 'ram_style_threshold' node attribute - if noact == 0: - odt = self.get_output_datatype() - B = odt.bitwidth() - thr_luts = (2**B - 1) * acc_bits * self.calc_tmem() / 64 - comp_luts = (2**B - 1) * acc_bits - - return int( - c0 + c1 * (P * (mult_luts + addertree_luts + acc_luts + thr_luts + comp_luts)) + c2 - ) - - def dsp_estimation(self): - # multiplication - P = self.get_nodeattr("PE") - res_type = self.get_nodeattr("resType") - wdt = self.get_weight_datatype() - W = wdt.bitwidth() - idt = self.get_input_datatype() - A = idt.bitwidth() - if res_type == "dsp": - mult_dsp = P * np.ceil((W + A) / 48) # TODO: more accurate modelling - else: - mult_dsp = 0 - return int(mult_dsp) - def get_exp_cycles(self): pe = self.get_nodeattr("PE") simd = self.get_nodeattr("SIMD") From b84de7b3c196f73fc1e3688c3ce6a60148032c2b Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Thu, 28 Mar 2024 14:31:14 +0000 Subject: [PATCH 659/665] [rtl vvau]: minor fix to dsp estimation --- .../custom_op/fpgadataflow/rtl/vectorvectoractivation_rtl.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/finn/custom_op/fpgadataflow/rtl/vectorvectoractivation_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/vectorvectoractivation_rtl.py index b315d913e4..27fc9f10a1 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/vectorvectoractivation_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/vectorvectoractivation_rtl.py @@ -144,8 +144,9 @@ def lut_estimation(self): return 0 def dsp_estimation(self): + P = self.get_nodeattr("PE") Q = self.get_nodeattr("SIMD") - return int(np.ceil(Q / 3)) + return int(P * np.ceil(Q / 3)) def instantiate_ip(self, cmd): # instantiate the RTL IP From ae97e38e9304e017cdd90ee99fd5dd01169ab90e Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Thu, 28 Mar 2024 14:31:27 +0000 Subject: [PATCH 660/665] [hls vvau]: added lut and dsp estimation methods --- .../hls/vectorvectoractivation_hls.py | 79 +++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/src/finn/custom_op/fpgadataflow/hls/vectorvectoractivation_hls.py b/src/finn/custom_op/fpgadataflow/hls/vectorvectoractivation_hls.py index fbae9eb9b8..3e10b640c5 100644 --- a/src/finn/custom_op/fpgadataflow/hls/vectorvectoractivation_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/vectorvectoractivation_hls.py @@ -26,6 +26,7 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +import math import numpy as np import os from qonnx.core.datatype import DataType @@ -47,6 +48,84 @@ def get_nodeattr_types(self): my_attrs.update(HLSBackend.get_nodeattr_types(self)) return my_attrs + def lut_estimation(self): + """Calculates resource estimations for LUTs based on: + - FINN-R: An End-to-End Deep-Learning Framework for Fast + Exploration of Quantized Neural Networks + - M. Blott, T. B. Preusser, N. J. Fraser, G. Gambardella, K. O'Brien, + Y. Umuroglu, M. Leeser and K. Vissers + - 12. Sep 2018 + """ + # TODO add in/out FIFO contributions + P = self.get_nodeattr("PE") + Q = self.get_nodeattr("SIMD") + wdt = self.get_weight_datatype() + W = wdt.bitwidth() + # determine tdt with input and weight data types + idt = self.get_input_datatype() + A = idt.bitwidth() + # parameters from experiments in paper mentioned above + c0 = 300 + c1 = 1.1 + c2 = 0 + mmode = self.get_nodeattr("mem_mode") + mstyle = self.get_nodeattr("ram_style") + if (mmode == "internal_decoupled" and mstyle == "distributed") or ( + mmode == "internal_embedded" and self.calc_wmem() <= 128 + ): + c2 = (P * Q * W) * math.ceil(self.calc_wmem() / 64) + + # multiplication + res_type = self.get_nodeattr("resType") + if res_type == "dsp": + mult_luts = 0 + else: + mult_luts = Q * (2 * math.ceil((W + A) / 6) - 1) * (W + A) + # adder tree + addertree_luts = (W + A) * (2 * Q - 1) + # accumulator + acc_datatype = self.get_accumulator_datatype() + acc_bits = acc_datatype.bitwidth() + k_h, k_w = self.get_nodeattr("Kernel") + # if accDataType is not set, then it will default to INT32, which would + # be a large overestimate in most (if not all) cases. In this scenario, + # we would use the minimum accumulator as determined by the data types + # bound, derived in https://arxiv.org/abs/2301.13376 + alpha = math.log(k_h * k_w, 2) + W + A - 1 - int(idt.signed()) + acc_bits = min( + acc_datatype.bitwidth(), + np.ceil(alpha + math.log(1 + pow(2, -alpha), 2) + 1), + ) + acc_luts = acc_bits + # thresholds and threshold comparators + thr_luts = 0 + comp_luts = 0 + noact = self.get_nodeattr("noActivation") + # TODO - add 'ram_style_threshold' node attribute + if noact == 0: + odt = self.get_output_datatype() + B = odt.bitwidth() + thr_luts = (2**B - 1) * acc_bits * self.calc_tmem() / 64 + comp_luts = (2**B - 1) * acc_bits + + return int( + c0 + c1 * (P * (mult_luts + addertree_luts + acc_luts + thr_luts + comp_luts)) + c2 + ) + + def dsp_estimation(self): + # multiplication + P = self.get_nodeattr("PE") + res_type = self.get_nodeattr("resType") + wdt = self.get_weight_datatype() + W = wdt.bitwidth() + idt = self.get_input_datatype() + A = idt.bitwidth() + if res_type == "dsp": + mult_dsp = P * np.ceil((W + A) / 48) # TODO: more accurate modelling + else: + mult_dsp = 0 + return int(mult_dsp) + def execute_node(self, context, graph): mode = self.get_nodeattr("exec_mode") mem_mode = self.get_nodeattr("mem_mode") From 22de8a61b19496316f4fb6199875d71803dd2215 Mon Sep 17 00:00:00 2001 From: auphelia Date: Thu, 28 Mar 2024 14:46:23 +0000 Subject: [PATCH 661/665] [NBs] Fix referenced builder step in advanced nb --- .../4_advanced_builder_settings.ipynb | 22 +++++++++---------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/notebooks/advanced/4_advanced_builder_settings.ipynb b/notebooks/advanced/4_advanced_builder_settings.ipynb index dccac6195d..5139377342 100644 --- a/notebooks/advanced/4_advanced_builder_settings.ipynb +++ b/notebooks/advanced/4_advanced_builder_settings.ipynb @@ -46,7 +46,7 @@ "id": "5dbed63f", "metadata": {}, "source": [ - "## Introduction to the CNV-w2a2 network \n", + "## Introduction to the CNV-w2a2 network \n", "\n", "The particular quantized neural network (QNN) we will be targeting in this notebook is referred to as CNV-w2a2 and it classifies 32x32 RGB images into one of ten CIFAR-10 classes. All weights and activations in this network are quantized to two bit, with the exception of the input (which is RGB with 8 bits per channel) and the final output (which is 32-bit numbers). It is similar to the convolutional neural network used in the [cnv_end2end_example](../end2end_example/bnn-pynq/cnv_end2end_example.ipynb) Jupyter notebook.\n", "\n", @@ -116,7 +116,7 @@ "id": "c764ed76", "metadata": {}, "source": [ - "## Quick recap, how to setup up default builder flow for resource estimations " + "## Quick recap, how to setup up default builder flow for resource estimations " ] }, { @@ -305,7 +305,7 @@ "id": "7e561a91", "metadata": {}, "source": [ - "## Build steps " + "## Build steps " ] }, { @@ -369,7 +369,7 @@ "id": "e9c2c97f", "metadata": {}, "source": [ - "### How to create a custom build step " + "### How to create a custom build step " ] }, { @@ -643,7 +643,7 @@ "id": "a6edf5c4-9213-45cd-834f-615c12685d9e", "metadata": {}, "source": [ - "## Specialize layers configuration json " + "## Specialize layers configuration json " ] }, { @@ -675,7 +675,7 @@ "id": "bc90b589-7a92-4996-9704-02736ac4e60e", "metadata": {}, "source": [ - "The builder flow step before `step_specialize_layers` generates a template json file to set the preferred implementation style per layer. We can copy it from one of the previous runs to this folder and manipulate it to pass it to a new build." + "The builder flow step before `step_create_dataflow_partition` generates a template json file to set the preferred implementation style per layer. We can copy it from one of the previous runs to this folder and manipulate it to pass it to a new build." ] }, { @@ -934,7 +934,7 @@ "id": "5ffbadd1", "metadata": {}, "source": [ - "## Folding configuration json " + "## Folding configuration json " ] }, { @@ -1270,7 +1270,7 @@ "id": "4a675834", "metadata": {}, "source": [ - "## Additional builder arguments " + "## Additional builder arguments " ] }, { @@ -1294,7 +1294,7 @@ "id": "e0c167f4", "metadata": {}, "source": [ - "### Verification steps " + "### Verification steps " ] }, { @@ -1505,7 +1505,7 @@ "id": "4609f94d", "metadata": {}, "source": [ - "### Other builder arguments " + "### Other builder arguments " ] }, { @@ -1610,7 +1610,7 @@ "id": "3b98eb65", "metadata": {}, "source": [ - "### Example for additional builder arguments & bitfile generation " + "### Example for additional builder arguments & bitfile generation " ] }, { From 1294eba11a430f99b025c14cbffb2e87ff70ca2f Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 29 Mar 2024 09:52:09 +0000 Subject: [PATCH 662/665] [Docs] Upgrade rtd requirements --- docs/requirements.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/requirements.txt b/docs/requirements.txt index 85bc1d0dcd..3a3730d2b9 100644 --- a/docs/requirements.txt +++ b/docs/requirements.txt @@ -1,6 +1,6 @@ brevitas@git+https://github.com/Xilinx/brevitas@master#egg=brevitas_examples dataclasses-json==0.5.7 -docutils==0.17.1 +docutils==0.19 gspread==3.6.0 importlib_resources IPython @@ -9,7 +9,7 @@ netron pytest pyverilator@git+https://github.com/maltanar/pyverilator@master#egg=pyverilator qonnx@git+https://github.com/fastmachinelearning/qonnx@main#egg=qonnx -sphinx_rtd_theme==0.5.0 +sphinx_rtd_theme==2.0.0 torch torchvision tqdm From 769f81f8a0fa0b91c247ec1995d7b0647891d69c Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 29 Mar 2024 10:45:17 +0000 Subject: [PATCH 663/665] [Docs] Minor fixes in rtd documentation --- docs/finn/developers.rst | 2 -- docs/finn/getting_started.rst | 2 +- docs/finn/hw_build.rst | 4 ---- docs/finn/img/mem_mode.png | Bin 41236 -> 59848 bytes docs/finn/internals.rst | 2 +- 5 files changed, 2 insertions(+), 8 deletions(-) diff --git a/docs/finn/developers.rst b/docs/finn/developers.rst index 3b182b8db8..2a5e26959b 100644 --- a/docs/finn/developers.rst +++ b/docs/finn/developers.rst @@ -2,8 +2,6 @@ Developer documentation *********************** -.. note:: **This page is under construction.** - This page is intended to serve as a starting point for new FINN developers. Power users may also find this information useful. diff --git a/docs/finn/getting_started.rst b/docs/finn/getting_started.rst index eae61b1a55..217f982702 100644 --- a/docs/finn/getting_started.rst +++ b/docs/finn/getting_started.rst @@ -125,7 +125,7 @@ General FINN Docker tips Supported FPGA Hardware ======================= -**Vivado IPI support for any Xilinx FPGA:** FINN generates a Vivado IP Integrator (IPI) design from the neural network with AXI stream (FIFO) in-o> +**Vivado IPI support for any Xilinx FPGA:** FINN generates a Vivado IP Integrator (IPI) design from the neural network with AXI stream (FIFO) in-out interfaces, which can be integrated onto any Xilinx-AMD FPGA as part of a larger system. It’s up to you to take the FINN-generated accelerator (what we call “stitched IP” in the tutorials), wire it up to your FPGA design and send/receive neural network data to/from the accelerator. **Shell-integrated accelerator + driver:** For quick deployment, we target boards supported by `PYNQ `_ . For these platforms, we can build a full bitfile including DMAs to move data into and out of the FINN-generated accelerator, as well as a Python driver to launch the accelerator. We support the Pynq-Z1, Pynq-Z2, Kria SOM, Ultra96, ZCU102 and ZCU104 boards, as well as Alveo cards. diff --git a/docs/finn/hw_build.rst b/docs/finn/hw_build.rst index 9e34edc9d1..39c39eb7df 100644 --- a/docs/finn/hw_build.rst +++ b/docs/finn/hw_build.rst @@ -87,8 +87,4 @@ transformation for Zynq, and the `VitisLink` transformation for Alveo. Deployment ========== - -Deployment ------------ - The bitfile and the driver file(s) can be copied to the PYNQ board and be executed there. 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zeYr=YR8IJ*OwXROnY~2=yz8q7out3zP#$+m*AGg9JQ5>qHav=oYuO94JZ-lWL~1DP zLepU#Wcw&Fqx*j4{A$m2>Qn0tr7batlSbqG!dgA!Mlr8`-StTgd*S!S`nEfG3eNxV z15}+3UtyJSs7g(rIq@a){H=xWiXwi0Qsi^D$yue6tcX{zi`gx@$BW*Dv;CRI=H~^X zRUP6-T)8YN{1sgJ>KxT?pvIgYko#-~z}O6YJfu z_xXrug~D4LYn8p74~nAUMDi$u%|D@WZxbqq%>UTg(&itU4B#${c#JF(eRu@d%WrRK zOnl^7Dvu90_*{r+no8PLCmT$D_i^d4CBD^H<7ADPe`9t>zJIqLIB!4cR+d|WgAK?x zSqJFD26#T$cE68DBWP)XggT0lE0xTpc(rMDwPok=vaGFTO-b=0$wN{~ewmYGAn!CI z^p^ZRHYN+8X#)vx4Vj5WtL(}qFVT`Qqrfl8lInR!F07DLM-5#PFd=#(Km(yXoDASh z^rzj+Ye0h|14u~GDUi=Lor@I*V6B& zT(0e@V|tmDKk7%?ZZJ@u&c?=LRJji6U@D~ti`x>wwVC#>OE26tHY0QLfEy)h_rC4$ zKCnx|Qnk8iT&B}kAw~d0LoW5ow>72GiIu_jCMV6^$g&!g(>>ReD1YNJgU4aI>kTDR z<3wk&O!8|(EKs5pm|*zSS%|UuKk=TB*GDfeHp0n^GO7RWi*cVL&0*bf=L#J}RmQMs zhlV}{4ia)__Qn`_ from the finn-hls library is used. To make the streaming possible a Verilog weight streamer component accesses the weight memory and sends the values via another FIFO to the MVAU. This component can be found in the `finn-rtllib `_ under the name *memstream.v*. For the IP block generation this component, the IP block resulting from the synthesis of the HLS code of the streaming MVAU and a FIFO for the weight stream are combined in a verilog wrapper. The weight values are saved in .dat files and stored in the weight memory from which the weight streamer reads. The resulting verilog component, which is named after the name of the node and has the suffix "_memstream.v", exposes only two ports to the outside, the data input and output. It therefore behaves externally in the same way as the MVAU in *internal_embedded* mode. +In *internal_decoupled* mode a different variant of the MVAU with three ports is used. Besides the input and output streams, which are fed into the circuit via Verilog FIFOs, there is another input, which is used to stream the weights. For this the `streaming MVAU `_ from the finn-hls library is used. To make the streaming possible a Verilog weight streamer component accesses the weight memory and sends the values via another FIFO to the MVAU. This component can be found in the `finn-rtllib `_ under the name *memstream.v*. For the IP block generation this component, the IP block resulting from the synthesis of the HLS code of the streaming MVAU and a FIFO for the weight stream are combined. The weight values are saved in .dat files and stored in the weight memory from which the weight streamer reads. The resulting verilog component, which is named after the name of the node and has the suffix "_memstream.v", exposes only two ports to the outside, the data input and output. It therefore behaves externally in the same way as the MVAU in *internal_embedded* mode. Advantages: From 038d3068c6b3014172f0830918bd1c12274a8570 Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 29 Mar 2024 13:56:34 +0000 Subject: [PATCH 664/665] [Docs] Update build dataflow example folder --- src/finn/qnn-data/build_dataflow/build.py | 3 ++- .../build_dataflow/dataflow_build_config.json | 3 ++- src/finn/qnn-data/build_dataflow/folding_config.json | 5 ++--- .../build_dataflow/specialize_layers_config.json | 11 +---------- src/finn/qnn-data/test_ext_weights/tfc-w1a1-extw.json | 5 ++--- tests/end2end/test_ext_weights.py | 3 ++- 6 files changed, 11 insertions(+), 19 deletions(-) diff --git a/src/finn/qnn-data/build_dataflow/build.py b/src/finn/qnn-data/build_dataflow/build.py index 13d58d2c91..58d566a6e6 100644 --- a/src/finn/qnn-data/build_dataflow/build.py +++ b/src/finn/qnn-data/build_dataflow/build.py @@ -1,4 +1,5 @@ -# Copyright (c) 2020 Xilinx, Inc. +# Copyright (C) 2020-2022 Xilinx, Inc. +# Copyright (C) 2022-2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/src/finn/qnn-data/build_dataflow/dataflow_build_config.json b/src/finn/qnn-data/build_dataflow/dataflow_build_config.json index a053c1a22f..8165055fd5 100644 --- a/src/finn/qnn-data/build_dataflow/dataflow_build_config.json +++ b/src/finn/qnn-data/build_dataflow/dataflow_build_config.json @@ -4,7 +4,8 @@ "mvau_wwidth_max": 10000, "synth_clk_period_ns": 10.0, "board": "Pynq-Z1", - "standalone_thresholds": true, + "standalone_thresholds": false, + "folding_config_file": "folding_config.json", "shell_flow_type": "vivado_zynq", "verify_save_rtlsim_waveforms": true, "force_python_rtlsim": true, diff --git a/src/finn/qnn-data/build_dataflow/folding_config.json b/src/finn/qnn-data/build_dataflow/folding_config.json index 46f1d6236d..124876c3db 100644 --- a/src/finn/qnn-data/build_dataflow/folding_config.json +++ b/src/finn/qnn-data/build_dataflow/folding_config.json @@ -1,8 +1,7 @@ { "Defaults": {}, - "Thresholding_hls_0": { - "PE": 49, - "ram_style": "distributed" + "Thresholding_rtl_0": { + "PE": 49 }, "MVAU_hls_0": { "PE": 16, diff --git a/src/finn/qnn-data/build_dataflow/specialize_layers_config.json b/src/finn/qnn-data/build_dataflow/specialize_layers_config.json index c2a8bd4553..9224a72907 100644 --- a/src/finn/qnn-data/build_dataflow/specialize_layers_config.json +++ b/src/finn/qnn-data/build_dataflow/specialize_layers_config.json @@ -1,26 +1,17 @@ { "Defaults": {}, "Thresholding_0": { - "preferred_impl_style": "hls" + "preferred_impl_style": "rtl" }, "MVAU_0": { "preferred_impl_style": "hls" }, - "Thresholding_1": { - "preferred_impl_style": "" - }, "MVAU_1": { "preferred_impl_style": "" }, - "Thresholding_2": { - "preferred_impl_style": "" - }, "MVAU_2": { "preferred_impl_style": "" }, - "Thresholding_3": { - "preferred_impl_style": "rtl" - }, "MVAU_3": { "preferred_impl_style": "" }, diff --git a/src/finn/qnn-data/test_ext_weights/tfc-w1a1-extw.json b/src/finn/qnn-data/test_ext_weights/tfc-w1a1-extw.json index 498d329ba3..9fe22443dc 100644 --- a/src/finn/qnn-data/test_ext_weights/tfc-w1a1-extw.json +++ b/src/finn/qnn-data/test_ext_weights/tfc-w1a1-extw.json @@ -1,8 +1,7 @@ { "Defaults": {}, - "Thresholding_hls_0": { - "PE": 49, - "ram_style": "distributed" + "Thresholding_rtl_0": { + "PE": 49 }, "MVAU_hls_0": { "PE": 16, diff --git a/tests/end2end/test_ext_weights.py b/tests/end2end/test_ext_weights.py index 2f5f136d3a..bac343bedf 100644 --- a/tests/end2end/test_ext_weights.py +++ b/tests/end2end/test_ext_weights.py @@ -1,4 +1,5 @@ -# Copyright (c) 2021, Xilinx +# Copyright (C) 2021-2022, Xilinx, Inc. +# Copyright (C) 2022-2024, Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without From b318693ff1c11e00b63434b11c276c66554bfd6e Mon Sep 17 00:00:00 2001 From: auphelia Date: Fri, 29 Mar 2024 14:11:26 +0000 Subject: [PATCH 665/665] [Tests] Runtime writeable weights = 0 for RTL thresholding in tfc test --- tests/end2end/test_end2end_bnn_pynq.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index 94134967fa..556ba1d187 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -135,7 +135,8 @@ def fold_tfc(model): inp_qnt_node = model.get_nodes_by_op_type("Thresholding_rtl")[0] inp_qnt = getCustomOp(inp_qnt_node) inp_qnt.set_nodeattr("PE", 49) - inp_qnt.set_nodeattr("runtime_writeable_weights", 1) + # TODO: update PYNQ driver to support runtime writeable weights for RTL Thresholding + # inp_qnt.set_nodeattr("runtime_writeable_weights", 1) return model