Lutram example (#112)

* WIP: lutram example first commmit

* lutram example

Author: trcwm

examples/lutram/README.md

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+# LUTRAM test project
+

examples/lutram/build.sh

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+#!/bin/sh
+
+yosys -p "read_verilog lutram.v; read_verilog prbs.v; read_verilog top.v; synth_gowin -json lutram.json"
+nextpnr-gowin --json lutram.json --write lutram-tec0117-synth.json --device GW1NR-LV9QN88C6/I5 --cst ../tec0117.cst
+gowin_pack -d GW1N-9 -o lutram-tec0117.fs lutram-tec0117-synth.json

examples/lutram/lutram.v

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+// Author: Niels A. Moseley, [email protected]
+
+`default_nettype none
+
+/* 1-bit by 16 element SRAM */
+module LUTRAM16S1(
+    input wire clk, 
+    input wire [3:0] ad,
+    input wire wre,
+    input wire di,
+    output wire do);
+
+reg memory[0:15];
+
+always@(posedge clk)
+begin
+    if (wre == 1)
+    begin
+        memory[ad] <= di;
+    end
+end
+
+assign do = memory[ad];
+
+endmodule

examples/lutram/prbs.v

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+// Author: Niels A. Moseley, [email protected]
+
+`default_nettype none
+
+/* 1-bit random bit generator */
+module PRBS7(
+    input wire clk, 
+    input wire next,
+    output wire out);
+
+reg [6:0] d;
+
+always @(posedge clk) 
+begin
+    if (next == 1)
+        d <= { d[5:0], d[6] ^ d[5] };
+    
+    if (d == 0)
+        d <= 1;
+end
+
+assign out = d[0];
+
+endmodule

examples/lutram/top.v

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+// Top level of lutram test 
+//
+// A PRBS generator is used to write random bits into the RAM
+// and checks if the resulting data out is the same.
+// 
+// For each error, a counter is incremented. The counter is displayed
+// on the LEDs of the TEC0117 board.
+//
+// Author: Niels A. Moseley, [email protected]
+//
+
+`default_nettype none
+
+module top(clk, led, rst);
+
+    // inputs
+    input wire  clk;        // clock 12 MHz
+    input wire  rst;
+
+    wire dout;
+    reg  wre = 0;
+    wire din;
+    wire random_bit;
+    
+    reg next_bit        = 0;
+    reg [3:0] address   = 0;
+    reg [1:0] state     = 0;
+    reg [23:0] blinkCounter = 0;
+
+    // outputs
+    output reg [7:0] led = 0;  // leds for debugging
+
+    // test state machine
+    always @(posedge clk)
+    begin
+        next_bit <= 0;
+        wre <= 0;
+        if (rst == 0)
+        begin
+            blinkCounter <= 0;
+            led[6:0]     <= 0;
+        end
+        else
+        begin
+            blinkCounter <= blinkCounter + 1;
+            case(state)
+                2'b00:  begin next_bit <= 1; address <= address + 1; end    /* setup for next test */
+                2'b01:  begin wre <= 1; end                                 /* write bit */
+                2'b10:  begin ; end
+                2'b11:  
+                    begin 
+                        if (random_bit != dout)
+                            led[6:0] <= led[6:0] + 1;
+                    end                
+            endcase
+            state  <= state + 1;
+
+        end
+
+        led[7] <= blinkCounter[23];
+    end
+
+    PRBS7 prbs
+    (
+        .clk(clk),
+        .next(next_bit),
+        .out(random_bit)
+    );
+
+    LUTRAM16S1 ram
+    (
+        .clk(clk),
+        .wre(wre),
+        .ad(address),
+        .di(random_bit),
+        .do(dout)
+    );
+
+endmodule