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yrabbityrabbit
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Merge pull request #199 from yrabbit/clk
Himbaechel. Improve dedicated clock router
2 parents 180dfef + 984885f commit cff0cd8

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‎.github/workflows/chipdb.yml

+2-1
Original file line numberDiff line numberDiff line change
@@ -279,6 +279,7 @@ jobs:
279279
path: dist
280280
- name: Set up Python
281281
uses: actions/setup-python@v4
282+
id: pysetup
282283
with:
283284
python-version: '3.9'
284285
- name: Install and build
@@ -301,7 +302,7 @@ jobs:
301302
sudo make install
302303
cd ../nextpnr
303304
git checkout ${{ matrix.nextpnr }}
304-
cmake . -DBUILD_PYTHON=OFF -DARCH="gowin;himbaechel" -DHIMBAECHEL_GOWIN_DEVICES="GW1N-1;GW1NZ-1;GW1N-4;GW1N-9;GW1N-9C;GW1NS-4;GW2A-18;GW2A-18C" -DPython3_EXECUTABLE=/opt/hostedtoolcache/Python/3.9.17/x64/bin/python
305+
cmake . -DBUILD_PYTHON=OFF -DARCH="gowin;himbaechel" -DHIMBAECHEL_GOWIN_DEVICES="GW1N-1;GW1NZ-1;GW1N-4;GW1N-9;GW1N-9C;GW1NS-4;GW2A-18;GW2A-18C" -DPython3_EXECUTABLE=${{ steps.pysetup.outputs.python-path }}
305306
make -j$(nproc)
306307
sudo make install
307308
cd ../examples

‎apycula/chipdb.py

+86-6
Original file line numberDiff line numberDiff line change
@@ -113,6 +113,7 @@ class Device:
113113
# - OSER16/IDES16
114114
# - ref to hclk_pips
115115
# - disabled blocks
116+
# - BUF(G)
116117
extra_func: Dict[Tuple[int, int], Dict[str, Any]] = field(default_factory=dict)
117118

118119
@property
@@ -154,6 +155,40 @@ def bank_tiles(self):
154155
res.update({ bel[4:] : pos })
155156
return res
156157

158+
# XXX GW1N-4 and GW1NS-4 have next data in dat['CmuxIns']:
159+
# 62 [11, 1, 126]
160+
# 63 [11, 1, 126]
161+
# this means that the same wire (11, 1, 126) is connected implicitly to two
162+
# other logical wires. Let's remember such connections.
163+
# If suddenly a command is given to assign an already used wire to another
164+
# node, then all the contents of this node are combined with the existing one,
165+
# and the node itself is destroyed. only for HCLK and clock nets for now
166+
wire2node = {}
167+
def add_node(dev, node_name, wire_type, row, col, wire):
168+
if (row, col, wire) not in wire2node:
169+
wire2node[row, col, wire] = node_name
170+
dev.nodes.setdefault(node_name, (wire_type, set()))[1].add((row, col, wire))
171+
else:
172+
if node_name != wire2node[row, col, wire] and node_name in dev.nodes:
173+
#print(f'{node_name} -> {wire2node[row, col, wire]} share ({row}, {col}, {wire})')
174+
dev.nodes[wire2node[row, col, wire]][1].update(dev.nodes[node_name][1])
175+
del dev.nodes[node_name]
176+
177+
# create bels for entry potints to the global clock nets
178+
def add_buf_bel(dev, row, col, wire, buf_type = 'BUFG'):
179+
# clock pins
180+
if not wire.startswith('CLK'):
181+
return
182+
extra_func = dev.extra_func.setdefault((row, col), {})
183+
if 'buf' not in extra_func or buf_type not in extra_func['buf']:
184+
extra_func.update({'buf': {buf_type: [wire]}})
185+
else:
186+
# dups not allowed for now
187+
if wire in extra_func['buf'][buf_type]:
188+
#print(f'extra buf dup ({row}, {col}) {buf_type}/{wire}')
189+
return
190+
extra_func['buf'][buf_type].append(wire)
191+
157192
def unpad(fuses, pad=-1):
158193
try:
159194
return fuses[:fuses.index(pad)]
@@ -962,7 +997,10 @@ def fse_create_hclk_nodes(dev, device, fse, dat):
962997
# entries to the HCLK from logic
963998
for hclk_idx, row, col, wire_idx in {(i, dat['CmuxIns'][str(i - 80)][0] - 1, dat['CmuxIns'][str(i - 80)][1] - 1, dat['CmuxIns'][str(i - 80)][2]) for i in range(hclknumbers['TBDHCLK0'], hclknumbers['RBDHCLK3'] + 1)}:
964999
if row != -2:
965-
dev.nodes.setdefault(hclknames[hclk_idx], ("HCLK", set()))[1].add((row, col, wirenames[wire_idx]))
1000+
add_node(dev, hclknames[hclk_idx], "HCLK", row, col, wirenames[wire_idx])
1001+
# XXX clock router is doing fine with HCLK w/o any buffering
1002+
# may be placement suffers a bit
1003+
#add_buf_bel(dev, row, col, wirenames[wire_idx], buf_type = 'BUFH')
9661004

9671005
if 'hclk' in hclk_info[side]:
9681006
# create HCLK cells pips
@@ -975,7 +1013,7 @@ def fse_create_hclk_nodes(dev, device, fse, dat):
9751013
for src in srcs.keys():
9761014
for pfx in _global_wire_prefixes:
9771015
if src.startswith(pfx):
978-
dev.nodes.setdefault(src, ('HCLK', set()))[1].add((row, col, src))
1016+
add_node(dev, src, "HCLK", row, col, src)
9791017
# strange GW1N-9C input-input aliases
9801018
for i in {0, 2}:
9811019
dev.nodes.setdefault(f'X{col}Y{row}/HCLK9-{i}', ('HCLK', {(row, col, f'HCLK_IN{i}')}))[1].add((row, col, f'HCLK_9IN{i}'))
@@ -1249,19 +1287,20 @@ def fse_create_clocks(dev, device, dat, fse):
12491287
# find center muxes
12501288
for clk_idx, row, col, wire_idx in {(i, dat['CmuxIns'][str(i - 80)][0] - 1, dat['CmuxIns'][str(i - 80)][1] - 1, dat['CmuxIns'][str(i - 80)][2]) for i in range(clknumbers['PCLKT0'], clknumbers['PCLKR1'] + 1)}:
12511289
if row != -2:
1252-
dev.nodes.setdefault(clknames[clk_idx], ("GLOBAL_CLK", set()))[1].add((row, col, wirenames[wire_idx]))
1290+
add_node(dev, clknames[clk_idx], "GLOBAL_CLK", row, col, wirenames[wire_idx])
1291+
add_buf_bel(dev, row, col, wirenames[wire_idx])
12531292

12541293
spines = {f'SPINE{i}' for i in range(32)}
12551294
for row, rd in enumerate(dev.grid):
12561295
for col, rc in enumerate(rd):
12571296
for dest, srcs in rc.pure_clock_pips.items():
12581297
for src in srcs.keys():
12591298
if src in spines and not dest.startswith('GT'):
1260-
dev.nodes.setdefault(src, ("GLOBAL_CLK", set()))[1].add((row, col, src))
1299+
add_node(dev, src, "GLOBAL_CLK", row, col, src)
12611300
if dest in spines:
1262-
dev.nodes.setdefault(dest, ("GLOBAL_CLK", set()))[1].add((row, col, dest))
1301+
add_node(dev, dest, "GLOBAL_CLK", row, col, dest)
12631302
for src in { wire for wire in srcs.keys() if wire not in {'VCC', 'VSS'}}:
1264-
dev.nodes.setdefault(src, ("GLOBAL_CLK", set()))[1].add((row, col, src))
1303+
add_node(dev, src, "GLOBAL_CLK", row, col, src)
12651304
# GBx0 <- GBOx
12661305
for spine_pair in range(4): # GB00/GB40, GB10/GB50, GB20/GB60, GB30/GB70
12671306
tap_start = _clock_data[device]['tap_start'][0]
@@ -1428,6 +1467,46 @@ def fse_create_io16(dev, device):
14281467
('OSCW', 'GW2AN-18'): ({'OSCOUT': 'Q4'}, {}),
14291468
}
14301469

1470+
# from logic to global clocks. An interesting piece of dat['CmuxIns'], it was
1471+
# found out experimentally that this range is responsible for the wires
1472+
# 129: 'TRBDCLK0' - 152: 'TRMDCLK1'. Again we have a shift of 80 from the wire number
1473+
# (see create clock aliases).
1474+
# 124-126 equal CLK0-CLK2 so these are clearly inputs to the clock system
1475+
# (GW1N-1 data)
1476+
# 49 [1, 11, 124]
1477+
# 50 [1, 11, 125]
1478+
# 51 [6, 20, 124]
1479+
# 52 [6, 20, 125]
1480+
# 53 [1, 10, 125]
1481+
# 54 [6, 1, 124]
1482+
# 55 [6, 1, 125]
1483+
# 56 [1, 10, 124]
1484+
# 57 [11, 11, 124]
1485+
# 58 [11, 11, 125]
1486+
# 59 [7, 20, 126]
1487+
# 60 [8, 20, 126]
1488+
# 61 [11, 10, 125]
1489+
# 62 [7, 1, 126]
1490+
# 63 [8, 1, 126]
1491+
# 64 [11, 10, 124]
1492+
# 65 [-1, -1, -1]
1493+
# 66 [-1, -1, -1]
1494+
# 67 [-1, -1, -1]
1495+
# 68 [-1, -1, -1]
1496+
# 69 [-1, -1, -1]
1497+
# 70 [-1, -1, -1]
1498+
# 71 [6, 10, 126]
1499+
# 72 [6, 11, 126]
1500+
# We don't need to worry about routing TRBDCLK0 and the family - this was
1501+
# already done when we created pure clock pips. But what we need to do is
1502+
# indicate that these CLKs at these coordinates are TRBDCLK0, etc. Therefore,
1503+
# we create Himbaechel nodes.
1504+
def fse_create_logic2clk(dev, device, dat):
1505+
for clkwire_idx, row, col, wire_idx in {(i, dat['CmuxIns'][str(i - 80)][0] - 1, dat['CmuxIns'][str(i - 80)][1] - 1, dat['CmuxIns'][str(i - 80)][2]) for i in range(clknumbers['TRBDCLK0'], clknumbers['TRMDCLK1'] + 1)}:
1506+
if row != -2:
1507+
add_node(dev, clknames[clkwire_idx], "GLOBAL_CLK", row, col, wirenames[wire_idx])
1508+
add_buf_bel(dev, row, col, wirenames[wire_idx])
1509+
14311510
def fse_create_osc(dev, device, fse):
14321511
for row, rd in enumerate(dev.grid):
14331512
for col, rc in enumerate(rd):
@@ -1503,6 +1582,7 @@ def from_fse(device, fse, dat):
15031582
fse_create_io16(dev, device)
15041583
fse_create_osc(dev, device, fse)
15051584
fse_create_gsr(dev, device)
1585+
fse_create_logic2clk(dev, device, dat)
15061586
disable_plls(dev, device)
15071587
sync_extra_func(dev)
15081588
return dev

‎apycula/gowin_pack.py

+4-2
Original file line numberDiff line numberDiff line change
@@ -82,7 +82,7 @@ def extra_pll_bels(cell, row, col, num, cellname):
8282
def get_bels(data):
8383
later = []
8484
if is_himbaechel:
85-
belre = re.compile(r"X(\d+)Y(\d+)/(?:GSR|LUT|DFF|IOB|MUX|ALU|ODDR|OSC[ZFHWO]?|BUFS|RAM16SDP4|RAM16SDP2|RAM16SDP1|PLL|IOLOGIC)(\w*)")
85+
belre = re.compile(r"X(\d+)Y(\d+)/(?:GSR|LUT|DFF|IOB|MUX|ALU|ODDR|OSC[ZFHWO]?|BUF[GS]|RAM16SDP4|RAM16SDP2|RAM16SDP1|PLL|IOLOGIC)(\w*)")
8686
else:
8787
belre = re.compile(r"R(\d+)C(\d+)_(?:GSR|SLICE|IOB|MUX2_LUT5|MUX2_LUT6|MUX2_LUT7|MUX2_LUT8|ODDR|OSC[ZFHWO]?|BUFS|RAMW|rPLL|PLLVR|IOLOGIC)(\w*)")
8888

@@ -572,7 +572,7 @@ def __init__(self, row, col, idx, attrs, flags, connections):
572572
'TBUF': {'ODMUX_1': 'UNKNOWN', 'PULLMODE': 'UP', 'SLEWRATE': 'FAST',
573573
'DRIVE': '8', 'HYSTERESIS': 'NONE', 'CLAMP': 'OFF', 'DIFFRESISTOR': 'OFF',
574574
'SINGLERESISTOR': 'OFF', 'VCCIO': '1.8', 'LVDS_OUT': 'OFF', 'DDR_DYNTERM': 'NA',
575-
'TO': 'INV', 'PERSISTENT': 'OFF', 'ODMUX': 'TRIMUX'},
575+
'TO': 'INV', 'PERSISTENT': 'OFF', 'ODMUX': 'TRIMUX', 'OPENDRAIN': 'OFF'},
576576
'IOBUF': {'ODMUX_1': 'UNKNOWN', 'PULLMODE': 'UP', 'SLEWRATE': 'FAST',
577577
'DRIVE': '8', 'HYSTERESIS': 'NONE', 'CLAMP': 'OFF', 'DIFFRESISTOR': 'OFF',
578578
'SINGLERESISTOR': 'OFF', 'VCCIO': '1.8', 'LVDS_OUT': 'OFF', 'DDR_DYNTERM': 'NA',
@@ -700,6 +700,8 @@ def place(db, tilemap, bels, cst, args):
700700
bits2zero.update(tiledata.bels[f'BUFS{num}'].flags[fuses])
701701
for r, c in bits2zero:
702702
tile[r][c] = 0
703+
elif typ.startswith("BUFG"):
704+
continue
703705

704706
elif typ in {'OSC', 'OSCZ', 'OSCF', 'OSCH', 'OSCW', 'OSCO'}:
705707
# XXX turn on (GW1NZ-1)

‎examples/himbaechel/Makefile.himbaechel

+33-34
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,6 @@
11
YOSYS ?= yosys
2-
NEXTPNR ?= nextpnr-himbaechel --uarch gowin
2+
NEXTPNR ?= nextpnr-himbaechel
33

4-
CHIPDB_PATH ?= /usr/local/share/nextpnr/himbaechel/gowin
54
HIMBAECHEL_OUT ?= ./himbaechel-out
65

76
.DEFAULT_GOAL := all
@@ -144,92 +143,92 @@ clean:
144143
gowin_pack -d GW2A-18C -o $@ $<
145144

146145
%-tangnano20k.json: %-tangnano20k-synth.json tangnano20k.cst
147-
$(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW2A-18C.bin --vopt partno=GW2AR-LV18QN88C8/I7 --vopt cst=tangnano20k.cst
146+
$(NEXTPNR) --json $< --write $@ --device GW2AR-LV18QN88C8/I7 --vopt family=GW2A-18C --vopt cst=tangnano20k.cst
148147

149-
%-tangnano20k-synth.json: tangnano20k/%.v
150-
$(YOSYS) -D LEDS_NR=6 -D OSC_TYPE_OSC -p "read_verilog $^; synth_gowin -json $@"
148+
%-tangnano20k-synth.json: %.v
149+
$(YOSYS) -D LEDS_NR=6 -D OSC_TYPE_OSC -D INV_BTN=1 -p "read_verilog $^; synth_gowin -json $@"
151150

152-
pll-nanolcd-tangnano20k-synth.json: pll/GW2A-18-dyn.vh tangnano20k/TOP.v pll-nanolcd/VGAMod.v
153-
$(YOSYS) -p "read_verilog $^; synth_gowin -json $@"
151+
pll-nanolcd-tangnano20k-synth.json: pll/GW2A-18-dyn.vh pll-nanolcd/TOP.v pll-nanolcd/VGAMod.v
152+
$(YOSYS) -D INV_BTN=1 -p "read_verilog $^; synth_gowin -json $@"
154153

155-
attosoc-tangnano20k-synth.json: tangnano20k/attosoc.v attosoc/picorv32.v
156-
$(YOSYS) -p "read_verilog $^; synth_gowin -json $@"
154+
attosoc-tangnano20k-synth.json: attosoc/attosoc.v attosoc/picorv32.v
155+
$(YOSYS) -D INV_BTN=1 -p "read_verilog $^; synth_gowin -json $@"
157156

158157
# ============================================================
159158
# TangPrimer20k
160159
%-primer20k.fs: %-primer20k.json
161160
gowin_pack -d GW2A-18 -o $@ $<
162161

163162
%-primer20k.json: %-primer20k-synth.json primer20k.cst
164-
$(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW2A-18.bin --vopt partno=GW2A-LV18PG256C8/I7 --vopt cst=primer20k.cst
163+
$(NEXTPNR) --json $< --write $@ --device GW2A-LV18PG256C8/I7 --vopt family=GW2A-18 --vopt cst=primer20k.cst
165164

166165
%-primer20k-synth.json: %.v
167-
$(YOSYS) -D LEDS_NR=6 -D OSC_TYPE_OSC -p "read_verilog $^; synth_gowin -json $@"
166+
$(YOSYS) -D LEDS_NR=6 -D OSC_TYPE_OSC -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@"
168167

169168
pll-nanolcd-primer20k-synth.json: pll/GW2A-18-dyn.vh pll-nanolcd/TOP.v pll-nanolcd/VGAMod.v
170-
$(YOSYS) -p "read_verilog $^; synth_gowin -json $@"
169+
$(YOSYS) -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@"
171170

172171
attosoc-%-synth.json: attosoc/attosoc.v attosoc/picorv32.v
173-
$(YOSYS) -p "read_verilog $^; synth_gowin -json $@"
172+
$(YOSYS) -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@"
174173

175174
# ============================================================
176175
# Tangnano (GW1N-1)
177176
%-tangnano.fs: %-tangnano.json
178177
gowin_pack -d GW1N-1 -o $@ $^
179178

180179
%-tangnano.json: %-tangnano-synth.json tangnano.cst
181-
$(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW1N-1.bin --vopt partno=GW1N-LV1QN48C6/I5 --vopt cst=tangnano.cst
180+
$(NEXTPNR) --json $< --write $@ --device GW1N-LV1QN48C6/I5 --vopt cst=tangnano.cst
182181

183182
%-tangnano-synth.json: %.v
184-
$(YOSYS) -D LEDS_NR=3 -D OSC_TYPE_OSCH -p "read_verilog $^; synth_gowin -json $@"
183+
$(YOSYS) -D LEDS_NR=3 -D OSC_TYPE_OSCH -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@"
185184

186185
pll-nanolcd-tangnano-synth.json: pll/GW1N-1-dyn.vh pll-nanolcd/TOP.v pll-nanolcd/VGAMod.v
187-
$(YOSYS) -p "read_verilog $^; synth_gowin -noalu -json $@"
186+
$(YOSYS) -D INV_BTN=0 -p "read_verilog $^; synth_gowin -noalu -json $@"
188187

189188
# ============================================================
190189
# Tangnano1k (GW1NZ-1)
191190
%-tangnano1k.fs: %-tangnano1k.json
192191
gowin_pack -d GW1NZ-1 -o $@ $^
193192

194193
%-tangnano1k.json: %-tangnano1k-synth.json tangnano1k.cst
195-
$(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW1NZ-1.bin --vopt partno=GW1NZ-LV1QN48C6/I5 --vopt cst=tangnano1k.cst
194+
$(NEXTPNR) --json $< --write $@ --device GW1NZ-LV1QN48C6/I5 --vopt cst=tangnano1k.cst
196195

197196
%-tangnano1k-synth.json: %.v
198-
$(YOSYS) -D LEDS_NR=3 -D OSC_TYPE_OSCZ -p "read_verilog $^; synth_gowin -json $@"
197+
$(YOSYS) -D LEDS_NR=3 -D OSC_TYPE_OSCZ -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@"
199198

200199
pll-nanolcd-tangnano1k.fs: pll-nanolcd-tangnano1k.json
201200
gowin_pack -d GW1NZ-1 --sspi_as_gpio --mspi_as_gpio -o $@ $^
202201

203202
pll-nanolcd-tangnano1k-synth.json: pll/GW1NZ-1-dyn.vh pll-nanolcd/TOP.v pll-nanolcd/VGAMod.v
204-
$(YOSYS) -p "read_verilog $^; synth_gowin -noalu -json $@"
203+
$(YOSYS) -D INV_BTN=0 -p "read_verilog $^; synth_gowin -noalu -json $@"
205204

206205
# ============================================================
207206
# Tangnano4k (GW1NS-4)
208207
%-tangnano4k.fs: %-tangnano4k.json
209208
gowin_pack -d GW1NS-4 -o $@ $^
210209

211210
%-tangnano4k.json: %-tangnano4k-synth.json tangnano4k.cst
212-
$(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW1NS-4.bin --vopt partno=GW1NSR-LV4CQN48PC7/I6 --vopt cst=tangnano4k.cst
211+
$(NEXTPNR) --json $< --write $@ --device GW1NSR-LV4CQN48PC7/I6 --vopt cst=tangnano4k.cst
213212

214213
%-tangnano4k-synth.json: %.v
215-
$(YOSYS) -D LEDS_NR=6 -D OSC_TYPE_OSCZ -p "read_verilog $^; synth_gowin -json $@"
214+
$(YOSYS) -D LEDS_NR=6 -D OSC_TYPE_OSCZ -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@"
216215

217216
blinky-pll-tangnano4k-synth.json: pll/GW1NS-4-dyn.vh blinky-pll-vr.v
218-
$(YOSYS) -D LEDS_NR=6 -p "read_verilog $^; synth_gowin -json $@"
217+
$(YOSYS) -D INV_BTN=0 -D LEDS_NR=6 -p "read_verilog $^; synth_gowin -json $@"
219218

220219
# ============================================================
221220
# Tangnano9k (GW1N-9C)
222221
%-tangnano9k.fs: %-tangnano9k.json
223222
gowin_pack -d GW1N-9C -o $@ $^
224223

225224
%-tangnano9k.json: %-tangnano9k-synth.json tangnano9k.cst
226-
$(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW1N-9C.bin --vopt partno=GW1NR-LV9QN88PC6/I5 --vopt cst=tangnano9k.cst
225+
$(NEXTPNR) --json $< --write $@ --device GW1NR-LV9QN88PC6/I5 --vopt family=GW1N-9C --vopt cst=tangnano9k.cst
227226

228227
%-tangnano9k-synth.json: %.v
229-
$(YOSYS) -D LEDS_NR=6 -D OSC_TYPE_OSC -p "read_verilog $^; synth_gowin -json $@"
228+
$(YOSYS) -D LEDS_NR=6 -D OSC_TYPE_OSC -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@"
230229

231230
pll-nanolcd-tangnano9k-synth.json: pll/GW1N-9C-dyn.vh pll-nanolcd/TOP.v pll-nanolcd/VGAMod.v
232-
$(YOSYS) -p "read_verilog $^; synth_gowin -json $@"
231+
$(YOSYS) -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@"
233232

234233
pll-nanolcd-tangnano9k.fs: pll-nanolcd-tangnano9k.json
235234
gowin_pack -d GW1N-9C --sspi_as_gpio --mspi_as_gpio -o $@ $^
@@ -240,41 +239,41 @@ pll-nanolcd-tangnano9k.fs: pll-nanolcd-tangnano9k.json
240239
gowin_pack -d GW1N-9 -o $@ $<
241240

242241
%-szfpga.json: %-szfpga-synth.json szfpga.cst
243-
$(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW1N-9.bin --vopt partno=GW1NR-LV9LQ144PC6/I5 --vopt cst=szfpga.cst
242+
$(NEXTPNR) --json $< --write $@ --device GW1NR-LV9LQ144PC6/I5 --vopt family=GW1N-9 --vopt cst=szfpga.cst
244243

245244
%-szfpga-synth.json: %.v
246-
$(YOSYS) -D LEDS_NR=4 -D OSC_TYPE_OSC -p "read_verilog $^; synth_gowin -json $@"
245+
$(YOSYS) -D LEDS_NR=4 -D OSC_TYPE_OSC -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@"
247246

248247
blinky-pll-szfpga-synth.json: pll/GW1N-9-dyn.vh blinky-pll.v
249-
$(YOSYS) -D LEDS_NR=4 -p "read_verilog $^; synth_gowin -json $@"
248+
$(YOSYS) -D INV_BTN=0 -D LEDS_NR=4 -p "read_verilog $^; synth_gowin -json $@"
250249

251250
# ============================================================
252251
# tec0117 (GW1N-9)
253252
%-tec0117.fs: %-tec0117.json
254253
gowin_pack -d GW1N-9 -o $@ $<
255254

256255
%-tec0117.json: %-tec0117-synth.json tec0117.cst
257-
$(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW1N-9.bin --vopt partno=GW1NR-LV9QN88C6/I5 --vopt cst=tec0117.cst
256+
$(NEXTPNR) --json $< --write $@ --device GW1NR-LV9QN88C6/I5 --vopt family=GW1N-9 --vopt cst=tec0117.cst
258257

259258
%-tec0117-synth.json: %.v
260-
$(YOSYS) -D LEDS_NR=8 -D OSC_TYPE_OSC -p "read_verilog $^; synth_gowin -json $@"
259+
$(YOSYS) -D LEDS_NR=8 -D OSC_TYPE_OSC -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@"
261260

262261
blinky-pll-tec0117-synth.json: pll/GW1N-9-dyn.vh blinky-pll.v
263-
$(YOSYS) -D LEDS_NR=8 -p "read_verilog $^; synth_gowin -json $@"
262+
$(YOSYS) -D INV_BTN=0 -D LEDS_NR=8 -p "read_verilog $^; synth_gowin -json $@"
264263

265264
# ============================================================
266265
# runber (GW1N-4)
267266
%-runber.fs: %-runber.json
268267
gowin_pack -d GW1N-4 -o $@ $<
269268

270269
%-runber.json: %-runber-synth.json runber.cst
271-
$(NEXTPNR) --json $< --write $@ --chipdb ${CHIPDB_PATH}/chipdb-GW1N-4.bin --vopt partno=GW1N-UV4LQ144C6/I5 --vopt cst=runber.cst
270+
$(NEXTPNR) --json $< --write $@ --device GW1N-UV4LQ144C6/I5 --vopt cst=runber.cst
272271

273272
%-runber-synth.json: %.v
274-
$(YOSYS) -D LEDS_NR=8 -D OSC_TYPE_OSC -p "read_verilog $^; synth_gowin -json $@"
273+
$(YOSYS) -D LEDS_NR=8 -D OSC_TYPE_OSC -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@"
275274

276275
blinky-pll-runber-synth.json: pll/GW1N-4-dyn.vh blinky-pll.v
277-
$(YOSYS) -D LEDS_NR=8 -p "read_verilog $^; synth_gowin -json $@"
276+
$(YOSYS) -D INV_BTN=0 -D LEDS_NR=8 -p "read_verilog $^; synth_gowin -json $@"
278277

279278
# ============================================================
280279
# Upack

‎examples/himbaechel/blinky-oddr.v

+5-2
Original file line numberDiff line numberDiff line change
@@ -3,11 +3,14 @@
33
*/
44
module top (
55
input clk,
6-
input key,
7-
input rst,
6+
input key_i,
7+
input rst_i,
88
output [`LEDS_NR-1:0] led
99
);
1010

11+
wire key = key_i ^ `INV_BTN;
12+
wire rst = rst_i ^ `INV_BTN;
13+
1114
reg [24:0] ctr_q;
1215
wire [24:0] ctr_d;
1316

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