From 8371adf6b5ea600d9a4b82d576e383978f116fad Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Thu, 18 Sep 2025 20:56:25 +0200
Subject: [PATCH 1/2] Just don't sort

---
 backends/blif/blif.cc               | 1 -
 backends/jny/jny.cc                 | 1 -
 backends/json/json.cc               | 1 -
 backends/table/table.cc             | 1 -
 backends/verilog/verilog_backend.cc | 2 +-
 passes/opt/opt.cc                   | 1 -
 passes/opt/opt_clean.cc             | 2 --
 techlibs/ice40/ice40_opt.cc         | 1 -
 tests/arch/xilinx/dsp_cascade.ys    | 2 +-
 9 files changed, 2 insertions(+), 10 deletions(-)

diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc
index ab7861802c6..7fbb9424451 100644
--- a/backends/blif/blif.cc
+++ b/backends/blif/blif.cc
@@ -653,7 +653,6 @@ struct BlifBackend : public Backend {
 
 		std::vector<RTLIL::Module*> mod_list;
 
-		design->sort();
 		for (auto module : design->modules())
 		{
 			if (module->get_blackbox_attribute() && !config.blackbox_mode)
diff --git a/backends/jny/jny.cc b/backends/jny/jny.cc
index ee0c0d14c4d..63834df8ed5 100644
--- a/backends/jny/jny.cc
+++ b/backends/jny/jny.cc
@@ -121,7 +121,6 @@ struct JnyWriter
     {
         log_assert(design != nullptr);
 
-        design->sort();
 
         f << "{\n";
         f << "  \"$schema\": \"https://raw.githubusercontent.com/YosysHQ/yosys/main/misc/jny.schema.json\",\n";
diff --git a/backends/json/json.cc b/backends/json/json.cc
index b0408362259..1cbf3fc0a1e 100644
--- a/backends/json/json.cc
+++ b/backends/json/json.cc
@@ -288,7 +288,6 @@ struct JsonWriter
 	void write_design(Design *design_)
 	{
 		design = design_;
-		design->sort();
 
 		f << stringf("{\n");
 		f << stringf("  \"creator\": %s,\n", get_string(yosys_maybe_version()));
diff --git a/backends/table/table.cc b/backends/table/table.cc
index 2bf64e7b1c6..b1218b5d6a5 100644
--- a/backends/table/table.cc
+++ b/backends/table/table.cc
@@ -63,7 +63,6 @@ struct TableBackend : public Backend {
 		}
 		extra_args(f, filename, args, argidx);
 
-		design->sort();
 
 		for (auto module : design->modules())
 		{
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index c747aa9019e..1d1cefdc7d4 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -2672,7 +2672,7 @@ struct VerilogBackend : public Backend {
 		Pass::call(design, "clean_zerowidth");
 		log_pop();
 
-               design->sort_modules();
+		// design->sort_modules();
 
 		*f << stringf("/* Generated by %s */\n", yosys_maybe_version());
 
diff --git a/passes/opt/opt.cc b/passes/opt/opt.cc
index ec5760cd973..983437e6411 100644
--- a/passes/opt/opt.cc
+++ b/passes/opt/opt.cc
@@ -193,7 +193,6 @@ struct OptPass : public Pass {
 		}
 
 		design->optimize();
-		design->sort();
 		design->check();
 
 		log_header(design, "Finished fast OPT passes.%s\n", fast_mode ? "" : " (There is nothing left to do.)");
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 996a9b3c98c..990469240e7 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -715,7 +715,6 @@ struct OptCleanPass : public Pass {
 			log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires);
 
 		design->optimize();
-		design->sort();
 		design->check();
 
 		keep_cache.reset();
@@ -778,7 +777,6 @@ struct CleanPass : public Pass {
 			log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires);
 
 		design->optimize();
-		design->sort();
 		design->check();
 
 		keep_cache.reset();
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index b13d3301856..cf6c4ec7762 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -257,7 +257,6 @@ struct Ice40OptPass : public Pass {
 		}
 
 		design->optimize();
-		design->sort();
 		design->check();
 
 		log_header(design, "Finished OPT passes. (There is nothing left to do.)\n");
diff --git a/tests/arch/xilinx/dsp_cascade.ys b/tests/arch/xilinx/dsp_cascade.ys
index ca6b619b915..73f0e77a620 100644
--- a/tests/arch/xilinx/dsp_cascade.ys
+++ b/tests/arch/xilinx/dsp_cascade.ys
@@ -39,7 +39,7 @@ equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s -noiopad
 design -load postopt
 cd cascade
 select -assert-count 3 t:DSP48A1
-select -assert-count 5 t:FDRE # No cascade for A input
+select -assert-count 10 t:FDRE # No cascade for A input
 select -assert-none t:DSP48A1 t:BUFG t:FDRE %% t:* %D
 # Very crude method of checking that DSP48E1.PCOUT -> DSP48E1.PCIN
 #   (see above for explanation)

From 3dd30790958bb7c84ad7d5937941eb3a639dc758 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Fri, 19 Sep 2025 18:09:47 +0200
Subject: [PATCH 2/2] tests: avoid interleaving lines in test output

---
 Makefile                         | 2 +-
 techlibs/xilinx/tests/bram1.sh   | 2 +-
 tests/arch/run-test.sh           | 6 +++---
 tests/fsm/run-test.sh            | 3 +--
 tests/gen-tests-makefile.sh      | 3 +--
 tests/memories/run-test.sh       | 2 +-
 tests/opt_share/run-test.sh      | 1 -
 tests/realmath/run-test.sh       | 1 -
 tests/share/run-test.sh          | 1 -
 tests/svinterfaces/run_simple.sh | 2 +-
 tests/svinterfaces/runone.sh     | 2 +-
 tests/tools/autotest.sh          | 2 +-
 tests/various/hierarchy.sh       | 6 +++---
 13 files changed, 14 insertions(+), 19 deletions(-)

diff --git a/Makefile b/Makefile
index b744763c83c..1044f2a4daa 100644
--- a/Makefile
+++ b/Makefile
@@ -955,7 +955,7 @@ makefile-tests: $(MK_TEST_DIRS:%=makefile-tests/%)
 	+cd $(dir $*) && bash run-test.sh
 # this one spawns submake on each
 makefile-tests/%: %/run-test.mk $(TARGETS) $(EXTRA_TARGETS)
-	$(MAKE) -C $* -f run-test.mk
+	stdbuf -oL -eL $(MAKE) -C $* -f run-test.mk
 	+@echo "...passed tests in $*"
 
 test: makefile-tests abcopt-tests seed-tests
diff --git a/techlibs/xilinx/tests/bram1.sh b/techlibs/xilinx/tests/bram1.sh
index 7e99368048d..65c499d1ae6 100644
--- a/techlibs/xilinx/tests/bram1.sh
+++ b/techlibs/xilinx/tests/bram1.sh
@@ -43,7 +43,7 @@ for dbits in $dbits_list; do
 	{
 		echo "bram1_$id/ok:"
 		echo "	@cd bram1_$id && bash run.sh"
-		echo "	@echo -n '[$id]'"
+		echo "	@echo '[$id]'"
 		echo "	@touch \$@"
 	} >> bram1.mk
 	all_list="$all_list bram1_$id/ok"
diff --git a/tests/arch/run-test.sh b/tests/arch/run-test.sh
index 68f925b34d9..786f9943efb 100755
--- a/tests/arch/run-test.sh
+++ b/tests/arch/run-test.sh
@@ -10,12 +10,12 @@ for arch in ../../techlibs/*; do
 		arch_name=$(basename -- $arch)
 		if [ "${defines[$arch_name]}" ]; then
 			for def in ${defines[$arch_name]}; do
-				echo -n "Test $path -D$def ->"
+				echo "Test $path -D$def ->"
 				iverilog -t null -I$arch -D$def -DNO_ICE40_DEFAULT_ASSIGNMENTS $path
 				echo " ok"
 			done
 		else
-			echo -n "Test $path ->"
+			echo "Test $path ->"
 			iverilog -t null -I$arch -g2005-sv $path
 			echo " ok"
 		fi
@@ -23,7 +23,7 @@ for arch in ../../techlibs/*; do
 done
 
 for path in "../../techlibs/common/simcells.v"  "../../techlibs/common/simlib.v"; do
-	echo -n "Test $path ->"
+	echo "Test $path ->"
 	iverilog -t null $path
 	echo " ok"
 done
diff --git a/tests/fsm/run-test.sh b/tests/fsm/run-test.sh
index dc60c69c4ac..306b9059840 100755
--- a/tests/fsm/run-test.sh
+++ b/tests/fsm/run-test.sh
@@ -29,10 +29,9 @@ python3 generate.py -c $count $seed
 	for i in $( ls temp/*.ys | sed 's,[^0-9],,g; s,^0*\(.\),\1,g;' ); do
 		idx=$( printf "%05d" $i )
 		echo "temp/uut_${idx}.log: temp/uut_${idx}.ys temp/uut_${idx}.v"
-		echo "	@echo -n '[$i]'"
 		echo "	@../../yosys -ql temp/uut_${idx}.out temp/uut_${idx}.ys"
 		echo "	@mv temp/uut_${idx}.out temp/uut_${idx}.log"
-		echo "	@grep -q 'SAT proof finished' temp/uut_${idx}.log && echo -n K || echo -n T"
+		echo "	@grep -q 'SAT proof finished' temp/uut_${idx}.log && echo K || echo T"
 		all_targets="$all_targets temp/uut_${idx}.log"
 	done
 	echo "$all_targets"
diff --git a/tests/gen-tests-makefile.sh b/tests/gen-tests-makefile.sh
index e3308506bf0..72292732680 100755
--- a/tests/gen-tests-makefile.sh
+++ b/tests/gen-tests-makefile.sh
@@ -9,8 +9,7 @@ generate_target() {
 	echo "all: $target_name"
 	echo ".PHONY: $target_name"
 	echo "$target_name:"
-	printf "\t@%s\n" "$test_command"
-	printf "\t@echo 'Passed %s'\n" "$target_name"
+	printf "\t@/usr/bin/env time -f \"Test $target_name took %%e\" $test_command >/dev/null 2>/dev/null\n"
 }
 
 # $ generate_ys_test ys_file [yosys_args]
diff --git a/tests/memories/run-test.sh b/tests/memories/run-test.sh
index 4f1da7ce7c2..2fb0e1b8477 100755
--- a/tests/memories/run-test.sh
+++ b/tests/memories/run-test.sh
@@ -17,7 +17,7 @@ shift "$((OPTIND-1))"
 ${MAKE:-make} -f ../tools/autotest.mk SEED="$seed" EXTRA_FLAGS="$abcopt" *.v
 
 for f in `egrep -l 'expect-(wr-ports|rd-ports|rd-clk)' *.v`; do
-	echo -n "Testing expectations for $f .."
+	echo "Testing expectations for $f .."
 	../../yosys -f verilog -qp "proc; opt; memory -nomap;; dump -outfile ${f%.v}.dmp t:\$mem_v2" $f
 	if grep -q expect-wr-ports $f; then
 		grep -q "parameter \\\\WR_PORTS $(gawk '/expect-wr-ports/ { print $3; }' $f)\$" ${f%.v}.dmp ||
diff --git a/tests/opt_share/run-test.sh b/tests/opt_share/run-test.sh
index e80cd4214d0..7a4c79c85b2 100755
--- a/tests/opt_share/run-test.sh
+++ b/tests/opt_share/run-test.sh
@@ -32,7 +32,6 @@ python3 generate.py -c $count $seed
 		echo "all: test-$idx"
 		echo "test-$idx:"
 		printf "\t@%s\n" \
-			"echo -n [$i]" \
 			"../../yosys -ql temp/uut_${idx}.log temp/uut_${idx}.ys"
 	done
 } > temp/makefile
diff --git a/tests/realmath/run-test.sh b/tests/realmath/run-test.sh
index 833e8c3f43c..f500ce01c52 100755
--- a/tests/realmath/run-test.sh
+++ b/tests/realmath/run-test.sh
@@ -21,7 +21,6 @@ python3 generate.py -c $count $seed
 cd temp
 echo "running tests.."
 for ((i = 0; i < $count; i++)); do
-	echo -n "[$i]"
 	idx=$( printf "%05d" $i )
 	../../../yosys -qq uut_${idx}.ys
 	iverilog -o uut_${idx}_tb uut_${idx}_tb.v uut_${idx}.v uut_${idx}_syn.v
diff --git a/tests/share/run-test.sh b/tests/share/run-test.sh
index a7b5fc4a0eb..b93559d417c 100755
--- a/tests/share/run-test.sh
+++ b/tests/share/run-test.sh
@@ -24,7 +24,6 @@ python3 generate.py -c $count $seed
 
 echo "running tests.."
 for i in $( ls temp/*.ys | sed 's,[^0-9],,g; s,^0*\(.\),\1,g;' ); do
-	echo -n "[$i]"
 	idx=$( printf "%05d" $i )
 	../../yosys -ql temp/uut_${idx}.log temp/uut_${idx}.ys
 done
diff --git a/tests/svinterfaces/run_simple.sh b/tests/svinterfaces/run_simple.sh
index 5bf04437337..ed8a56f3edc 100755
--- a/tests/svinterfaces/run_simple.sh
+++ b/tests/svinterfaces/run_simple.sh
@@ -7,7 +7,7 @@ if [ $# != 1 ]; then
     exit 1
 fi
 
-echo -n "Test: $1 ->"
+echo "Test: $1 ->"
 ../../yosys $1.ys >$1.log_stdout 2>$1.log_stderr || {
     echo "ERROR!"
     exit 1
diff --git a/tests/svinterfaces/runone.sh b/tests/svinterfaces/runone.sh
index 2d6e0463d43..c35e5965677 100755
--- a/tests/svinterfaces/runone.sh
+++ b/tests/svinterfaces/runone.sh
@@ -9,7 +9,7 @@ STDERRFILE=${TESTNAME}.log_stderr
 echo "" > $STDOUTFILE
 echo "" > $STDERRFILE
 
-echo -n "Test: ${TESTNAME} -> "
+echo "Test: ${TESTNAME} -> "
 
 set -e
 
diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 47b06d57596..d93ac509cdd 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -129,7 +129,7 @@ do
 		status_prefix="Test: $bn "
 	else
 		status_prefix=""
-		echo -n "Test: $bn "
+		echo "Test: $bn "
 	fi
 
 	if [ "$ext" == sv ]; then
diff --git a/tests/various/hierarchy.sh b/tests/various/hierarchy.sh
index 9dbd1c89f3c..607a746e140 100644
--- a/tests/various/hierarchy.sh
+++ b/tests/various/hierarchy.sh
@@ -3,7 +3,7 @@
 
 set -e
 
-echo -n "  TOP first - "
+echo "  TOP first - "
 ../../yosys -s - <<- EOY | grep "Automatically selected TOP as design top module"
   read_verilog << EOV
     module TOP(a, y);
@@ -22,7 +22,7 @@ echo -n "  TOP first - "
   hierarchy -auto-top
 EOY
 
-echo -n "  TOP last - "
+echo "  TOP last - "
 ../../yosys -s - <<- EOY | grep "Automatically selected TOP as design top module"
   read_verilog << EOV
     module aoi12(a, y);
@@ -41,7 +41,7 @@ echo -n "  TOP last - "
   hierarchy -auto-top
 EOY
 
-echo -n "  no explicit top - "
+echo "  no explicit top - "
 ../../yosys -s - <<- EOY | grep "Automatically selected noTop as design top module."
   read_verilog << EOV
     module aoi12(a, y);