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@bhagwat-rahul bhagwat-rahul commented Nov 8, 2025

Reason for change:-

Support non wildcard system verilog package imports.
Late follow-up to earlier PR for imports, addresses non-wildcard imports.

How it works:-
Parser emits AST_IMPORT for each import statement:

  1. Wildcard: AST_IMPORT with no children.
  2. Specific: AST_IMPORT with child nodes (names).

During simplify, for each AST_IMPORT:

  1. Locate the package.
  2. For wildcard, import all relevant symbols and enum items.
  3. For specific, import only the listed names.
  4. Wildcard skips names already present to preserve specific-import precedence.

How to Test:-
Build minimal required (frontends & yosys) and run test yosys package_import_specific.ys

Like so:-

make clean && make frontends/verilog/verilog_parser.tab.cc frontends/verilog/verilog_parser.tab.o frontends/verilog/verilog_lexer.o yosys


cd tests/verilog && ../../yosys package_import_specific.ys

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@widlarizer widlarizer left a comment

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Makes sense, I refactored the logic out though. simplify.cc isn't the prettiest part of the codebase but we can incrementally improve the parts we touch. Another nitpick: in VS Code you can watch and trim your trailing newspace with this extension

@widlarizer widlarizer merged commit 6a22397 into YosysHQ:main Nov 10, 2025
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2 participants