diff --git a/.mailmap b/.mailmap
index 3cc78251f31..5125666bbc8 100644
--- a/.mailmap
+++ b/.mailmap
@@ -331,4 +331,3 @@ Marjan Fariborz <mfariborz@ucdavis.edu> marjanfariborz <mfariborz@ucdavis.edu>
 Mike Upton <michaelupton@gmail.com>
 seanzw <seanyukigeek@gmail.com>
 Trivikram Reddy <tvreddy@ucdavis.edu> tv-reddy <tvreddy@ucdavis.edu>
-
diff --git a/TESTING.md b/TESTING.md
index 88d1f295718..f5d8198e563 100644
--- a/TESTING.md
+++ b/TESTING.md
@@ -246,10 +246,9 @@ maintainer (see MAINTAINERS).*
 ## Running Tests in Parallel
 
 Whimsy has support for parallel testing baked in. This system supports
-running multiple suites at the same time on the same computer. To run 
+running multiple suites at the same time on the same computer. To run
 suites in parallel, supply the `-t <number-tests>` flag to the run command.
 
 For example, to run up to three test suites at the same time::
 
     ./main.py run --skip-build -t 3
-
diff --git a/build_tools/blob.py b/build_tools/blob.py
index 3d93c45cc81..b3d2d0f0e6a 100644
--- a/build_tools/blob.py
+++ b/build_tools/blob.py
@@ -26,16 +26,17 @@
 import array
 import functools
 
+
 def bytesToCppArray(code, symbol, data):
-    '''
+    """
     Output an array of bytes to a code formatter as a c++ array declaration.
-    '''
-    code('const std::uint8_t ${symbol}[] = {')
+    """
+    code("const std::uint8_t ${symbol}[] = {")
     code.indent()
     step = 16
     for i in range(0, len(data), step):
-        x = array.array('B', data[i:i+step])
-        strs = map(lambda i: f'{i},', x)
+        x = array.array("B", data[i : i + step])
+        strs = map(lambda i: f"{i},", x)
         code(functools.reduce(lambda x, y: x + y, strs))
     code.dedent()
-    code('};')
+    code("};")
diff --git a/build_tools/code_formatter.py b/build_tools/code_formatter.py
index 0aee74201e4..a2651c9dd0e 100644
--- a/build_tools/code_formatter.py
+++ b/build_tools/code_formatter.py
@@ -45,6 +45,7 @@
 import os
 import re
 
+
 class lookup(object):
     def __init__(self, formatter, frame, *args, **kwargs):
         self.frame = frame
@@ -64,10 +65,10 @@ def __getitem__(self, item):
         if item in self.kwargs:
             return self.kwargs[item]
 
-        if item == '__file__':
+        if item == "__file__":
             return self.frame.f_code.co_filename
 
-        if item == '__line__':
+        if item == "__line__":
             return self.frame.f_lineno
 
         if self.formatter.locals and item in self.frame.f_locals:
@@ -89,6 +90,7 @@ def __getitem__(self, item):
             pass
         raise IndexError("Could not find '%s'" % item)
 
+
 class code_formatter_meta(type):
     pattern = r"""
     (?:
@@ -102,44 +104,48 @@ class code_formatter_meta(type):
       %(delim)s(?P<invalid>)                       # ill-formed delimiter exprs
     )
     """
+
     def __init__(cls, name, bases, dct):
         super(code_formatter_meta, cls).__init__(name, bases, dct)
-        if 'pattern' in dct:
+        if "pattern" in dct:
             pat = cls.pattern
         else:
             # tuple expansion to ensure strings are proper length
-            lb,rb = cls.braced
-            lb1,lb2,rb2,rb1 = cls.double_braced
+            lb, rb = cls.braced
+            lb1, lb2, rb2, rb1 = cls.double_braced
             pat = code_formatter_meta.pattern % {
-                'delim' : re.escape(cls.delim),
-                'ident' : cls.ident,
-                'pos' : cls.pos,
-                'lb' : re.escape(lb),
-                'rb' : re.escape(rb),
-                'ldb' : re.escape(lb1+lb2),
-                'rdb' : re.escape(rb2+rb1),
-                }
+                "delim": re.escape(cls.delim),
+                "ident": cls.ident,
+                "pos": cls.pos,
+                "lb": re.escape(lb),
+                "rb": re.escape(rb),
+                "ldb": re.escape(lb1 + lb2),
+                "rdb": re.escape(rb2 + rb1),
+            }
         cls.pattern = re.compile(pat, re.VERBOSE | re.DOTALL | re.MULTILINE)
 
+
 class code_formatter(object, metaclass=code_formatter_meta):
-    delim = r'$'
-    ident = r'[_A-z]\w*'
-    pos = r'[0-9]+'
-    braced = r'{}'
-    double_braced = r'{{}}'
+    delim = r"$"
+    ident = r"[_A-z]\w*"
+    pos = r"[0-9]+"
+    braced = r"{}"
+    double_braced = r"{{}}"
 
     globals = True
     locals = True
     fix_newlines = True
+
     def __init__(self, *args, **kwargs):
         self._data = []
         self._dict = {}
         self._indent_level = 0
         self._indent_spaces = 4
-        self.globals = kwargs.pop('globals', type(self).globals)
-        self.locals = kwargs.pop('locals', type(self).locals)
-        self._fix_newlines = \
-                kwargs.pop('fix_newlines', type(self).fix_newlines)
+        self.globals = kwargs.pop("globals", type(self).globals)
+        self.locals = kwargs.pop("locals", type(self).locals)
+        self._fix_newlines = kwargs.pop(
+            "fix_newlines", type(self).fix_newlines
+        )
 
         if args:
             self.__call__(args)
@@ -171,38 +177,44 @@ def write(self, *args):
         # Add a comment to inform which file generated the generated file
         # to make it easier to backtrack and modify generated code
         frame = inspect.currentframe().f_back
-        if re.match(r'^\.(cc|hh|c|h)$', extension) is not None:
-            f.write(f'''/**
+        if re.match(r"^\.(cc|hh|c|h)$", extension) is not None:
+            f.write(
+                f"""/**
  * DO NOT EDIT THIS FILE!
  * File automatically generated by
  *   {frame.f_code.co_filename}:{frame.f_lineno}
  */
 
-''')
-        elif re.match(r'^\.py$', extension) is not None:
-            f.write(f'''#
+"""
+            )
+        elif re.match(r"^\.py$", extension) is not None:
+            f.write(
+                f"""#
 # DO NOT EDIT THIS FILE!
 # File automatically generated by
 #   {frame.f_code.co_filename}:{frame.f_lineno}
 #
 
-''')
-        elif re.match(r'^\.html$', extension) is not None:
-            f.write(f'''<!--
+"""
+            )
+        elif re.match(r"^\.html$", extension) is not None:
+            f.write(
+                f"""<!--
  DO NOT EDIT THIS FILE!
  File automatically generated by
    {frame.f_code.co_filename}:{frame.f_lineno}
 -->
 
-''')
+"""
+            )
 
         for data in self._data:
             f.write(data)
         f.close()
 
     def __str__(self):
-        data = ''.join(self._data)
-        self._data = [ data ]
+        data = "".join(self._data)
+        self._data = [data]
         return data
 
     def __getitem__(self, item):
@@ -231,21 +243,21 @@ def _append(self, data):
             self._data.append(data)
             return
 
-        initial_newline = not self._data or self._data[-1] == '\n'
+        initial_newline = not self._data or self._data[-1] == "\n"
         for line in data.splitlines():
             if line:
                 if self._indent_level:
-                    self._data.append(' ' * self._indent_level)
+                    self._data.append(" " * self._indent_level)
                 self._data.append(line)
 
             if line or not initial_newline:
-                self._data.append('\n')
+                self._data.append("\n")
 
             initial_newline = False
 
     def __call__(self, *args, **kwargs):
         if not args:
-            self._data.append('\n')
+            self._data.append("\n")
             return
 
         format = args[0]
@@ -254,51 +266,56 @@ def __call__(self, *args, **kwargs):
         frame = inspect.currentframe().f_back
 
         l = lookup(self, frame, *args, **kwargs)
+
         def convert(match):
-            ident = match.group('lone')
+            ident = match.group("lone")
             # check for a lone identifier
             if ident:
-                indent = match.group('indent') # must be spaces
-                lone = '%s' % (l[ident], )
+                indent = match.group("indent")  # must be spaces
+                lone = "%s" % (l[ident],)
 
                 def indent_lines(gen):
                     for line in gen:
                         yield indent
                         yield line
-                return ''.join(indent_lines(lone.splitlines(True)))
+
+                return "".join(indent_lines(lone.splitlines(True)))
 
             # check for an identifier, braced or not
-            ident = match.group('ident') or match.group('b_ident')
+            ident = match.group("ident") or match.group("b_ident")
             if ident is not None:
-                return '%s' % (l[ident], )
+                return "%s" % (l[ident],)
 
             # check for a positional parameter, braced or not
-            pos = match.group('pos') or match.group('b_pos')
+            pos = match.group("pos") or match.group("b_pos")
             if pos is not None:
                 pos = int(pos)
                 if pos > len(args):
-                    raise ValueError \
-                        ('Positional parameter #%d not found in pattern' % pos,
-                         code_formatter.pattern)
-                return '%s' % (args[int(pos)], )
+                    raise ValueError(
+                        "Positional parameter #%d not found in pattern" % pos,
+                        code_formatter.pattern,
+                    )
+                return "%s" % (args[int(pos)],)
 
             # check for a double braced expression
-            eval_expr = match.group('eval')
+            eval_expr = match.group("eval")
             if eval_expr is not None:
                 result = eval(eval_expr, {}, l)
-                return '%s' % (result, )
+                return "%s" % (result,)
 
             # check for an escaped delimiter
-            if match.group('escaped') is not None:
-                return '$'
+            if match.group("escaped") is not None:
+                return "$"
 
             # At this point, we have to match invalid
-            if match.group('invalid') is None:
+            if match.group("invalid") is None:
                 # didn't match invalid!
-                raise ValueError('Unrecognized named group in pattern',
-                                 code_formatter.pattern)
+                raise ValueError(
+                    "Unrecognized named group in pattern",
+                    code_formatter.pattern,
+                )
 
-            i = match.start('invalid')
+            i = match.start("invalid")
             if i == 0:
                 colno = 1
                 lineno = 1
@@ -307,52 +324,64 @@ def indent_lines(gen):
                 colno = i - sum(len(z) for z in lines)
                 lineno = len(lines)
 
-                raise ValueError('Invalid format string: line %d, col %d' %
-                                 (lineno, colno))
+                raise ValueError(
+                    "Invalid format string: line %d, col %d" % (lineno, colno)
+                )
 
         d = code_formatter.pattern.sub(convert, format)
         self._append(d)
 
-__all__ = [ "code_formatter" ]
 
-if __name__ == '__main__':
+__all__ = ["code_formatter"]
+
+if __name__ == "__main__":
     from .code_formatter import code_formatter
+
     f = code_formatter()
 
     class Foo(dict):
         def __init__(self, **kwargs):
             self.update(kwargs)
+
         def __getattr__(self, attr):
             return self[attr]
 
     x = "this is a test"
-    l = [ [Foo(x=[Foo(y=9)])] ]
+    l = [[Foo(x=[Foo(y=9)])]]
 
     y = code_formatter()
-    y('''
+    y(
+        """
 {
     this_is_a_test();
 }
-''')
-    f('    $y')
-    f('''$__file__:$__line__
-{''')
+"""
+    )
+    f("    $y")
+    f(
+        """$__file__:$__line__
+{"""
+    )
     f("${{', '.join(str(x) for x in range(4))}}")
-    f('${x}')
-    f('$x')
+    f("${x}")
+    f("$x")
     f.indent()
     for i in range(5):
-        f('$x')
-        f('$i')
-        f('$0', "zero")
-        f('$1 $0', "zero", "one")
-        f('${0}', "he went")
-        f('${0}asdf', "he went")
+        f("$x")
+        f("$i")
+        f("$0", "zero")
+        f("$1 $0", "zero", "one")
+        f("${0}", "he went")
+        f("${0}asdf", "he went")
     f.dedent()
 
-    f('''
+    f(
+        """
     ${{l[0][0]["x"][0].y}}
 }
-''', 1, 9)
+""",
+        1,
+        9,
+    )
 
-    print(f, end=' ')
+    print(f, end=" ")
diff --git a/build_tools/cxx_config_cc.py b/build_tools/cxx_config_cc.py
index c4a2d8957f3..a908aa8c176 100644
--- a/build_tools/cxx_config_cc.py
+++ b/build_tools/cxx_config_cc.py
@@ -46,8 +46,8 @@
 from code_formatter import code_formatter
 
 parser = argparse.ArgumentParser()
-parser.add_argument('modpath', help='module the simobject belongs to')
-parser.add_argument('cxx_config_cc', help='cxx config cc file to generate')
+parser.add_argument("modpath", help="module the simobject belongs to")
+parser.add_argument("cxx_config_cc", help="cxx config cc file to generate")
 
 args = parser.parse_args()
 
@@ -63,22 +63,25 @@
 
 code = code_formatter()
 
-entry_class = 'CxxConfigDirectoryEntry_%s' % sim_object_name
-param_class = '%sCxxConfigParams' % sim_object_name
+entry_class = "CxxConfigDirectoryEntry_%s" % sim_object_name
+param_class = "%sCxxConfigParams" % sim_object_name
+
 
 def cxx_bool(b):
-    return 'true' if b else 'false'
+    return "true" if b else "false"
+
 
 code('#include "params/%s.hh"' % sim_object_name)
 
 for param in sim_object._params.values():
     if isSimObjectClass(param.ptype):
-        code('#include "%s"' % param.ptype._value_dict['cxx_header'])
+        code('#include "%s"' % param.ptype._value_dict["cxx_header"])
         code('#include "params/%s.hh"' % param.ptype.__name__)
     else:
         param.ptype.cxx_ini_predecls(code)
 
-code('''#include "${{sim_object._value_dict['cxx_header']}}"
+code(
+    """#include "${{sim_object._value_dict['cxx_header']}}"
 #include "base/str.hh"
 #include "cxx_config/${sim_object_name}.hh"
 
@@ -87,34 +90,39 @@ def cxx_bool(b):
 
 ${param_class}::DirectoryEntry::DirectoryEntry()
 {
-''')
+"""
+)
 code.indent()
 for param in sim_object._params.values():
     is_vector = isinstance(param, m5.params.VectorParamDesc)
     is_simobj = issubclass(param.ptype, m5.SimObject.SimObject)
 
-    code('parameters["%s"] = new ParamDesc("%s", %s, %s);' %
-        (param.name, param.name, cxx_bool(is_vector),
-        cxx_bool(is_simobj)));
+    code(
+        'parameters["%s"] = new ParamDesc("%s", %s, %s);'
+        % (param.name, param.name, cxx_bool(is_vector), cxx_bool(is_simobj))
+    )
 
 for port in sim_object._ports.values():
     is_vector = isinstance(port, m5.params.VectorPort)
-    is_requestor = port.role == 'GEM5 REQUESTOR'
+    is_requestor = port.role == "GEM5 REQUESTOR"
 
-    code('ports["%s"] = new PortDesc("%s", %s, %s);' %
-        (port.name, port.name, cxx_bool(is_vector),
-        cxx_bool(is_requestor)))
+    code(
+        'ports["%s"] = new PortDesc("%s", %s, %s);'
+        % (port.name, port.name, cxx_bool(is_vector), cxx_bool(is_requestor))
+    )
 
 code.dedent()
 
-code('''}
+code(
+    """}
 
 bool
 ${param_class}::setSimObject(const std::string &name, SimObject *simObject)
 {
     bool ret = true;
     if (false) {
-''')
+"""
+)
 
 code.indent()
 for param in sim_object._params.values():
@@ -124,14 +132,17 @@ def cxx_bool(b):
     if is_simobj and not is_vector:
         code('} else if (name == "${{param.name}}") {')
         code.indent()
-        code('this->${{param.name}} = '
-            'dynamic_cast<${{param.ptype.cxx_type}}>(simObject);')
-        code('if (simObject && !this->${{param.name}})')
-        code('   ret = false;')
+        code(
+            "this->${{param.name}} = "
+            "dynamic_cast<${{param.ptype.cxx_type}}>(simObject);"
+        )
+        code("if (simObject && !this->${{param.name}})")
+        code("   ret = false;")
         code.dedent()
 code.dedent()
 
-code('''
+code(
+    """
     } else {
         ret = false;
     }
@@ -146,7 +157,8 @@ def cxx_bool(b):
     bool ret = true;
 
     if (false) {
-''')
+"""
+)
 
 code.indent()
 for param in sim_object._params.values():
@@ -156,23 +168,28 @@ def cxx_bool(b):
     if is_simobj and is_vector:
         code('} else if (name == "${{param.name}}") {')
         code.indent()
-        code('this->${{param.name}}.clear();')
-        code('for (auto i = simObjects.begin(); '
-            'ret && i != simObjects.end(); i ++)')
-        code('{')
+        code("this->${{param.name}}.clear();")
+        code(
+            "for (auto i = simObjects.begin(); "
+            "ret && i != simObjects.end(); i ++)"
+        )
+        code("{")
         code.indent()
-        code('${{param.ptype.cxx_type}} object = '
-            'dynamic_cast<${{param.ptype.cxx_type}}>(*i);')
-        code('if (*i && !object)')
-        code('    ret = false;')
-        code('else')
-        code('    this->${{param.name}}.push_back(object);')
+        code(
+            "${{param.ptype.cxx_type}} object = "
+            "dynamic_cast<${{param.ptype.cxx_type}}>(*i);"
+        )
+        code("if (*i && !object)")
+        code("    ret = false;")
+        code("else")
+        code("    this->${{param.name}}.push_back(object);")
         code.dedent()
-        code('}')
+        code("}")
         code.dedent()
 code.dedent()
 
-code('''
+code(
+    """
     } else {
         ret = false;
     }
@@ -193,7 +210,8 @@ def cxx_bool(b):
     bool ret = true;
 
     if (false) {
-''')
+"""
+)
 
 code.indent()
 for param in sim_object._params.values():
@@ -203,12 +221,14 @@ def cxx_bool(b):
     if not is_simobj and not is_vector:
         code('} else if (name == "${{param.name}}") {')
         code.indent()
-        param.ptype.cxx_ini_parse(code,
-            'value', 'this->%s' % param.name, 'ret =')
+        param.ptype.cxx_ini_parse(
+            code, "value", "this->%s" % param.name, "ret ="
+        )
         code.dedent()
 code.dedent()
 
-code('''
+code(
+    """
     } else {
         ret = false;
     }
@@ -223,7 +243,8 @@ def cxx_bool(b):
     bool ret = true;
 
     if (false) {
-''')
+"""
+)
 
 code.indent()
 for param in sim_object._params.values():
@@ -233,22 +254,23 @@ def cxx_bool(b):
     if not is_simobj and is_vector:
         code('} else if (name == "${{param.name}}") {')
         code.indent()
-        code('${{param.name}}.clear();')
-        code('for (auto i = values.begin(); '
-            'ret && i != values.end(); i ++)')
-        code('{')
+        code("${{param.name}}.clear();")
+        code(
+            "for (auto i = values.begin(); " "ret && i != values.end(); i ++)"
+        )
+        code("{")
         code.indent()
-        code('${{param.ptype.cxx_type}} elem;')
-        param.ptype.cxx_ini_parse(code,
-            '*i', 'elem', 'ret =')
-        code('if (ret)')
-        code('    this->${{param.name}}.push_back(elem);')
+        code("${{param.ptype.cxx_type}} elem;")
+        param.ptype.cxx_ini_parse(code, "*i", "elem", "ret =")
+        code("if (ret)")
+        code("    this->${{param.name}}.push_back(elem);")
         code.dedent()
-        code('}')
+        code("}")
         code.dedent()
 code.dedent()
 
-code('''
+code(
+    """
     } else {
         ret = false;
     }
@@ -263,15 +285,17 @@ def cxx_bool(b):
     bool ret = true;
 
     if (false) {
-''')
+"""
+)
 
 code.indent()
 for port in sim_object._ports.values():
     code('} else if (name == "${{port.name}}") {')
-    code('    this->port_${{port.name}}_connection_count = count;')
+    code("    this->port_${{port.name}}_connection_count = count;")
 code.dedent()
 
-code('''
+code(
+    """
     } else {
         ret = false;
     }
@@ -282,18 +306,21 @@ def cxx_bool(b):
 SimObject *
 ${param_class}::simObjectCreate()
 {
-''')
+"""
+)
 
 code.indent()
-if hasattr(sim_object, 'abstract') and sim_object.abstract:
-    code('return nullptr;')
+if hasattr(sim_object, "abstract") and sim_object.abstract:
+    code("return nullptr;")
 else:
-    code('return this->create();')
+    code("return this->create();")
 code.dedent()
 
-code('''}
+code(
+    """}
 
 } // namespace gem5
-''')
+"""
+)
 
 code.write(args.cxx_config_cc)
diff --git a/build_tools/cxx_config_hh.py b/build_tools/cxx_config_hh.py
index 652c4886686..55828e37b79 100644
--- a/build_tools/cxx_config_hh.py
+++ b/build_tools/cxx_config_hh.py
@@ -46,8 +46,8 @@
 from code_formatter import code_formatter
 
 parser = argparse.ArgumentParser()
-parser.add_argument('modpath', help='module the simobject belongs to')
-parser.add_argument('cxx_config_hh', help='cxx config header file to generate')
+parser.add_argument("modpath", help="module the simobject belongs to")
+parser.add_argument("cxx_config_hh", help="cxx config header file to generate")
 
 args = parser.parse_args()
 
@@ -60,10 +60,11 @@
 
 code = code_formatter()
 
-entry_class = 'CxxConfigDirectoryEntry_%s' % sim_object_name
-param_class = '%sCxxConfigParams' % sim_object_name
+entry_class = "CxxConfigDirectoryEntry_%s" % sim_object_name
+param_class = "%sCxxConfigParams" % sim_object_name
 
-code('''#include "params/${sim_object_name}.hh"
+code(
+    """#include "params/${sim_object_name}.hh"
 
 #include "sim/cxx_config.hh"
 
@@ -110,6 +111,7 @@ class DirectoryEntry : public CxxConfigDirectoryEntry
 };
 
 } // namespace gem5
-''')
+"""
+)
 
 code.write(args.cxx_config_hh)
diff --git a/build_tools/debugflaghh.py b/build_tools/debugflaghh.py
index fc86cb0dc50..2e861e27903 100644
--- a/build_tools/debugflaghh.py
+++ b/build_tools/debugflaghh.py
@@ -44,35 +44,41 @@
 parser.add_argument("hh", help="the path of the debug flag header file")
 parser.add_argument("name", help="the name of the debug flag")
 parser.add_argument("desc", help="a description of the debug flag")
-parser.add_argument("fmt",
-        help="whether the flag is a format flag (True or False)")
-parser.add_argument("components",
-        help="components of a compound flag, if applicable, joined with :")
+parser.add_argument(
+    "fmt", help="whether the flag is a format flag (True or False)"
+)
+parser.add_argument(
+    "components",
+    help="components of a compound flag, if applicable, joined with :",
+)
 
 args = parser.parse_args()
 
 fmt = args.fmt.lower()
-if fmt == 'true':
+if fmt == "true":
     fmt = True
-elif fmt == 'false':
+elif fmt == "false":
     fmt = False
 else:
     print(f'Unrecognized "FMT" value {fmt}', file=sys.stderr)
     sys.exit(1)
-components = args.components.split(':') if args.components else []
+components = args.components.split(":") if args.components else []
 
 code = code_formatter()
 
-code('''
+code(
+    """
 #ifndef __DEBUG_${{args.name}}_HH__
 #define __DEBUG_${{args.name}}_HH__
 
 #include "base/compiler.hh" // For namespace deprecation
 #include "base/debug.hh"
-''')
+"""
+)
 for flag in components:
     code('#include "debug/${flag}.hh"')
-code('''
+code(
+    """
 namespace gem5
 {
 
@@ -82,14 +88,16 @@
 
 namespace unions
 {
-''')
+"""
+)
 
 # Use unions to prevent debug flags from being destructed. It's the
 # responsibility of the programmer to handle object destruction for members
 # of the union. We purposefully leave that destructor empty so that we can
 # use debug flags even in the destructors of other objects.
 if components:
-    code('''
+    code(
+        """
 inline union ${{args.name}}
 {
     ~${{args.name}}() {}
@@ -100,9 +108,11 @@
         }
     };
 } ${{args.name}};
-''')
+"""
+    )
 else:
-    code('''
+    code(
+        """
 inline union ${{args.name}}
 {
     ~${{args.name}}() {}
@@ -110,18 +120,21 @@
         "${{args.name}}", "${{args.desc}}", ${{"true" if fmt else "false"}}
     };
 } ${{args.name}};
-''')
+"""
+    )
 
-code('''
+code(
+    """
 } // namespace unions
 
-inline constexpr const auto& ${{args.name}} = 
+inline constexpr const auto& ${{args.name}} =
     ::gem5::debug::unions::${{args.name}}.${{args.name}};
 
 } // namespace debug
 } // namespace gem5
 
 #endif // __DEBUG_${{args.name}}_HH__
-''')
+"""
+)
 
 code.write(args.hh)
diff --git a/build_tools/enum_cc.py b/build_tools/enum_cc.py
index c706ffe31f4..476e49d750c 100644
--- a/build_tools/enum_cc.py
+++ b/build_tools/enum_cc.py
@@ -46,17 +46,18 @@
 from code_formatter import code_formatter
 
 parser = argparse.ArgumentParser()
-parser.add_argument('modpath', help='module the enum belongs to')
-parser.add_argument('enum_cc', help='enum cc file to generate')
-parser.add_argument('use_python',
-        help='whether python is enabled in gem5 (True or False)')
+parser.add_argument("modpath", help="module the enum belongs to")
+parser.add_argument("enum_cc", help="enum cc file to generate")
+parser.add_argument(
+    "use_python", help="whether python is enabled in gem5 (True or False)"
+)
 
 args = parser.parse_args()
 
 use_python = args.use_python.lower()
-if use_python == 'true':
+if use_python == "true":
     use_python = True
-elif use_python == 'false':
+elif use_python == "false":
     use_python = False
 else:
     print(f'Unrecognized "use_python" value {use_python}', file=sys.stderr)
@@ -75,41 +76,46 @@
 file_name = enum.__name__
 name = enum.__name__ if enum.enum_name is None else enum.enum_name
 
-code('''#include "base/compiler.hh"
+code(
+    """#include "base/compiler.hh"
 #include "enums/$file_name.hh"
 
 namespace gem5
 {
 
-''')
+"""
+)
 
 if enum.wrapper_is_struct:
-    code('const char *${wrapper_name}::${name}Strings'
-        '[Num_${name}] =')
+    code("const char *${wrapper_name}::${name}Strings" "[Num_${name}] =")
 else:
     if enum.is_class:
-        code('''\
+        code(
+            """\
 const char *${name}Strings[static_cast<int>(${name}::Num_${name})] =
-''')
+"""
+        )
     else:
-        code('''GEM5_DEPRECATED_NAMESPACE(Enums, enums);
+        code(
+            """GEM5_DEPRECATED_NAMESPACE(Enums, enums);
 namespace enums
-{''')
+{"""
+        )
         code.indent(1)
-        code('const char *${name}Strings[Num_${name}] =')
+        code("const char *${name}Strings[Num_${name}] =")
 
-code('{')
+code("{")
 code.indent(1)
 for val in enum.vals:
     code('"$val",')
 code.dedent(1)
-code('};')
+code("};")
 
 if not enum.wrapper_is_struct and not enum.is_class:
     code.dedent(1)
-    code('} // namespace enums')
+    code("} // namespace enums")
 
-code('} // namespace gem5')
+code("} // namespace gem5")
 
 
 if use_python:
@@ -118,7 +124,8 @@
     enum_name = enum.__name__ if enum.enum_name is None else enum.enum_name
     wrapper_name = enum_name if enum.is_class else enum.wrapper_name
 
-    code('''#include "pybind11/pybind11.h"
+    code(
+        """#include "pybind11/pybind11.h"
 #include "pybind11/stl.h"
 
 #include <sim/init.hh>
@@ -133,7 +140,8 @@
 {
     py::module_ m = m_internal.def_submodule("enum_${name}");
 
-''')
+"""
+    )
     if enum.is_class:
         code('py::enum_<${enum_name}>(m, "enum_${name}")')
     else:
@@ -145,16 +153,18 @@
         code('.value("${val}", ${wrapper_name}::${val})')
     code('.value("Num_${name}", ${wrapper_name}::Num_${enum_name})')
     if not enum.is_class:
-        code('.export_values()')
-    code(';')
+        code(".export_values()")
+    code(";")
     code.dedent()
 
-    code('}')
+    code("}")
     code.dedent()
-    code('''
+    code(
+        """
 static EmbeddedPyBind embed_enum("enum_${name}", module_init);
 
 } // namespace gem5
-    ''')
+    """
+    )
 
 code.write(args.enum_cc)
diff --git a/build_tools/enum_hh.py b/build_tools/enum_hh.py
index 2c4a7bb2ce7..a5b9f42cba4 100644
--- a/build_tools/enum_hh.py
+++ b/build_tools/enum_hh.py
@@ -46,8 +46,8 @@
 from code_formatter import code_formatter
 
 parser = argparse.ArgumentParser()
-parser.add_argument('modpath', help='module the enum belongs to')
-parser.add_argument('enum_hh', help='enum header file to generate')
+parser.add_argument("modpath", help="module the enum belongs to")
+parser.add_argument("enum_hh", help="enum header file to generate")
 
 args = parser.parse_args()
 
@@ -64,53 +64,61 @@
 # Note that we wrap the enum in a class/struct to act as a namespace,
 # so that the enum strings can be brief w/o worrying about collisions.
 wrapper_name = enum.wrapper_name
-wrapper = 'struct' if enum.wrapper_is_struct else 'namespace'
+wrapper = "struct" if enum.wrapper_is_struct else "namespace"
 name = enum.__name__ if enum.enum_name is None else enum.enum_name
-idem_macro = '__ENUM__%s__%s__' % (wrapper_name, name)
+idem_macro = "__ENUM__%s__%s__" % (wrapper_name, name)
 
-code('''\
+code(
+    """\
 #ifndef $idem_macro
 #define $idem_macro
 
 namespace gem5
 {
-''')
+"""
+)
 if enum.is_class:
-    code('''\
+    code(
+        """\
 enum class $name
 {
-''')
+"""
+    )
 else:
-    code('''\
+    code(
+        """\
 $wrapper $wrapper_name {
 enum $name
 {
-''')
+"""
+    )
     code.indent(1)
 code.indent(1)
 for val in enum.vals:
-    code('$val = ${{enum.map[val]}},')
-code('Num_$name = ${{len(enum.vals)}}')
+    code("$val = ${{enum.map[val]}},")
+code("Num_$name = ${{len(enum.vals)}}")
 code.dedent(1)
-code('};')
+code("};")
 
 if enum.is_class:
-    code('''\
+    code(
+        """\
 extern const char *${name}Strings[static_cast<int>(${name}::Num_${name})];
-''')
+"""
+    )
 elif enum.wrapper_is_struct:
-    code('static const char *${name}Strings[Num_${name}];')
+    code("static const char *${name}Strings[Num_${name}];")
 else:
-    code('extern const char *${name}Strings[Num_${name}];')
+    code("extern const char *${name}Strings[Num_${name}];")
 
 if not enum.is_class:
     code.dedent(1)
-    code('}; // $wrapper_name')
+    code("}; // $wrapper_name")
 
 code()
-code('} // namespace gem5')
+code("} // namespace gem5")
 
 code()
-code('#endif // $idem_macro')
+code("#endif // $idem_macro")
 
 code.write(args.enum_hh)
diff --git a/build_tools/grammar.py b/build_tools/grammar.py
index 9aba746260c..6ac638bcd0d 100644
--- a/build_tools/grammar.py
+++ b/build_tools/grammar.py
@@ -29,73 +29,77 @@
 import ply.lex
 import ply.yacc
 
+
 class ParseError(Exception):
     def __init__(self, message, token=None):
         Exception.__init__(self, message)
         self.token = token
 
+
 class Grammar(object):
     def setupLexerFactory(self, **kwargs):
-        if 'module' in kwargs:
+        if "module" in kwargs:
             raise AttributeError("module is an illegal attribute")
         self.lex_kwargs = kwargs
 
     def setupParserFactory(self, **kwargs):
-        if 'module' in kwargs:
+        if "module" in kwargs:
             raise AttributeError("module is an illegal attribute")
 
-        if 'output' in kwargs:
-            dir,tab = os.path.split(output)
-            if not tab.endswith('.py'):
-                raise AttributeError('The output file must end with .py')
-            kwargs['outputdir'] = dir
-            kwargs['tabmodule'] = tab[:-3]
+        if "output" in kwargs:
+            dir, tab = os.path.split(output)
+            if not tab.endswith(".py"):
+                raise AttributeError("The output file must end with .py")
+            kwargs["outputdir"] = dir
+            kwargs["tabmodule"] = tab[:-3]
 
         self.yacc_kwargs = kwargs
 
     def __getattr__(self, attr):
-        if attr == 'lexers':
+        if attr == "lexers":
             self.lexers = []
             return self.lexers
 
-        if attr == 'lex_kwargs':
+        if attr == "lex_kwargs":
             self.setupLexerFactory()
             return self.lex_kwargs
 
-        if attr == 'yacc_kwargs':
+        if attr == "yacc_kwargs":
             self.setupParserFactory()
             return self.yacc_kwargs
 
-        if attr == 'lex':
+        if attr == "lex":
             self.lex = ply.lex.lex(module=self, **self.lex_kwargs)
             return self.lex
 
-        if attr == 'yacc':
+        if attr == "yacc":
             self.yacc = ply.yacc.yacc(module=self, **self.yacc_kwargs)
             return self.yacc
 
-        if attr == 'current_lexer':
+        if attr == "current_lexer":
             if not self.lexers:
                 return None
             return self.lexers[-1][0]
 
-        if attr == 'current_source':
+        if attr == "current_source":
             if not self.lexers:
-                return '<none>'
+                return "<none>"
             return self.lexers[-1][1]
 
-        if attr == 'current_line':
+        if attr == "current_line":
             if not self.lexers:
                 return -1
             return self.current_lexer.lineno
 
         raise AttributeError(
-            "'%s' object has no attribute '%s'" % (type(self), attr))
+            "'%s' object has no attribute '%s'" % (type(self), attr)
+        )
 
-    def parse_string(self, data, source='<string>', debug=None, tracking=0):
+    def parse_string(self, data, source="<string>", debug=None, tracking=0):
         if not isinstance(data, str):
             raise AttributeError(
-                "argument must be a string, was '%s'" % type(f))
+                "argument must be a string, was '%s'" % type(f)
+            )
 
         lexer = self.lex.clone()
         lexer.input(data)
@@ -114,24 +118,32 @@ def parse_string(self, data, source='<string>', debug=None, tracking=0):
     def parse_file(self, f, **kwargs):
         if isinstance(f, str):
             source = f
-            f = open(f, 'r')
+            f = open(f, "r")
         elif isinstance(f, file):
             source = f.name
         else:
             raise AttributeError(
-                "argument must be either a string or file, was '%s'" % type(f))
+                "argument must be either a string or file, was '%s'" % type(f)
+            )
 
         return self.parse_string(f.read(), source, **kwargs)
 
     def p_error(self, t):
         if t:
-            msg = "Syntax error at %s:%d:%d\n>>%s<<" % \
-                  (self.current_source, t.lineno, t.lexpos + 1, t.value)
+            msg = "Syntax error at %s:%d:%d\n>>%s<<" % (
+                self.current_source,
+                t.lineno,
+                t.lexpos + 1,
+                t.value,
+            )
         else:
-            msg = "Syntax error at end of %s" % (self.current_source, )
+            msg = "Syntax error at end of %s" % (self.current_source,)
         raise ParseError(msg, t)
 
     def t_error(self, t):
-        msg = "Illegal character %s @ %d:%d" % \
-            (repr(t.value[0]), t.lineno, t.lexpos)
+        msg = "Illegal character %s @ %d:%d" % (
+            repr(t.value[0]),
+            t.lineno,
+            t.lexpos,
+        )
         raise ParseError(msg, t)
diff --git a/build_tools/infopy.py b/build_tools/infopy.py
index a58cf3967bd..4f15f24f988 100644
--- a/build_tools/infopy.py
+++ b/build_tools/infopy.py
@@ -42,8 +42,8 @@
 from code_formatter import code_formatter
 
 parser = argparse.ArgumentParser()
-parser.add_argument('info_py', help='info.py file path')
-parser.add_argument('files', help='file to include in info.py', nargs='*')
+parser.add_argument("info_py", help="info.py file path")
+parser.add_argument("files", help="file to include in info.py", nargs="*")
 
 args = parser.parse_args()
 
@@ -52,8 +52,8 @@
 
 for source in args.files:
     src = os.path.basename(source)
-    with open(source, 'r') as f:
-        data = ''.join(f)
-    code('${src} = ${{repr(data)}}')
+    with open(source, "r") as f:
+        data = "".join(f)
+    code("${src} = ${{repr(data)}}")
 
 code.write(args.info_py)
diff --git a/build_tools/marshal.py b/build_tools/marshal.py
index 9c2964b4777..18afe2ca526 100644
--- a/build_tools/marshal.py
+++ b/build_tools/marshal.py
@@ -67,16 +67,17 @@
 
 _, cpp, python, modpath, abspath = sys.argv
 
-with open(python, 'r') as f:
+with open(python, "r") as f:
     src = f.read()
 
-compiled = compile(src, python, 'exec')
+compiled = compile(src, python, "exec")
 marshalled = marshal.dumps(compiled)
 
 compressed = zlib.compress(marshalled)
 
 code = code_formatter()
-code('''\
+code(
+    """\
 #include "python/embedded.hh"
 
 namespace gem5
@@ -84,14 +85,16 @@
 namespace
 {
 
-''')
+"""
+)
 
-bytesToCppArray(code, 'embedded_module_data', compressed)
+bytesToCppArray(code, "embedded_module_data", compressed)
 
 # The name of the EmbeddedPython object doesn't matter since it's in an
 # anonymous namespace, and it's constructor takes care of installing it into a
 # global list.
-code('''
+code(
+    """
 EmbeddedPython embedded_module_info(
     "${abspath}",
     "${modpath}",
@@ -101,6 +104,7 @@
 
 } // anonymous namespace
 } // namespace gem5
-''')
+"""
+)
 
 code.write(cpp)
diff --git a/build_tools/sim_object_param_struct_cc.py b/build_tools/sim_object_param_struct_cc.py
index 1b72e3cb415..03848094567 100644
--- a/build_tools/sim_object_param_struct_cc.py
+++ b/build_tools/sim_object_param_struct_cc.py
@@ -46,17 +46,18 @@
 from code_formatter import code_formatter
 
 parser = argparse.ArgumentParser()
-parser.add_argument('modpath', help='module the simobject belongs to')
-parser.add_argument('param_cc', help='parameter cc file to generate')
-parser.add_argument('use_python',
-        help='whether python is enabled in gem5 (True or False)')
+parser.add_argument("modpath", help="module the simobject belongs to")
+parser.add_argument("param_cc", help="parameter cc file to generate")
+parser.add_argument(
+    "use_python", help="whether python is enabled in gem5 (True or False)"
+)
 
 args = parser.parse_args()
 
 use_python = args.use_python.lower()
-if use_python == 'true':
+if use_python == "true":
     use_python = True
-elif use_python == 'false':
+elif use_python == "false":
     use_python = False
 else:
     print(f'Unrecognized "use_python" value {use_python}', file=sys.stderr)
@@ -64,7 +65,7 @@
 
 basename = os.path.basename(args.param_cc)
 no_ext = os.path.splitext(basename)[0]
-sim_object_name = '_'.join(no_ext.split('_')[1:])
+sim_object_name = "_".join(no_ext.split("_")[1:])
 
 importer.install()
 module = importlib.import_module(args.modpath)
@@ -80,14 +81,16 @@
 # the object itself, not including inherited params (which
 # will also be inherited from the base class's param struct
 # here). Sort the params based on their key
-params = list(map(lambda k_v: k_v[1],
-                  sorted(sim_object._params.local.items())))
+params = list(
+    map(lambda k_v: k_v[1], sorted(sim_object._params.local.items()))
+)
 ports = sim_object._ports.local
 
 # only include pybind if python is enabled in the build
 if use_python:
 
-    code('''#include "pybind11/pybind11.h"
+    code(
+        """#include "pybind11/pybind11.h"
 #include "pybind11/stl.h"
 
 #include <type_traits>
@@ -99,9 +102,11 @@
 
 #include "${{sim_object.cxx_header}}"
 
-''')
+"""
+    )
 else:
-    code('''
+    code(
+        """
 #include <type_traits>
 
 #include "base/compiler.hh"
@@ -109,13 +114,15 @@
 
 #include "${{sim_object.cxx_header}}"
 
-''')
+"""
+    )
 # only include the python params code if python is enabled.
 if use_python:
     for param in params:
         param.pybind_predecls(code)
 
-    code('''namespace py = pybind11;
+    code(
+        """namespace py = pybind11;
 
 namespace gem5
 {
@@ -124,39 +131,48 @@
 module_init(py::module_ &m_internal)
 {
 py::module_ m = m_internal.def_submodule("param_${sim_object}");
-''')
+"""
+    )
     code.indent()
     if sim_object._base:
-        code('py::class_<${sim_object}Params, ' \
-             '${{sim_object._base.type}}Params, ' \
-             'std::unique_ptr<${{sim_object}}Params, py::nodelete>>(' \
-             'm, "${sim_object}Params")')
+        code(
+            "py::class_<${sim_object}Params, "
+            "${{sim_object._base.type}}Params, "
+            "std::unique_ptr<${{sim_object}}Params, py::nodelete>>("
+            'm, "${sim_object}Params")'
+        )
     else:
-        code('py::class_<${sim_object}Params, ' \
-            'std::unique_ptr<${sim_object}Params, py::nodelete>>(' \
-            'm, "${sim_object}Params")')
+        code(
+            "py::class_<${sim_object}Params, "
+            "std::unique_ptr<${sim_object}Params, py::nodelete>>("
+            'm, "${sim_object}Params")'
+        )
 
     code.indent()
-    if not hasattr(sim_object, 'abstract') or not sim_object.abstract:
-        code('.def(py::init<>())')
+    if not hasattr(sim_object, "abstract") or not sim_object.abstract:
+        code(".def(py::init<>())")
         code('.def("create", &${sim_object}Params::create)')
 
-    param_exports = sim_object.cxx_param_exports + [
-        PyBindProperty(k)
-        for k, v in sorted(sim_object._params.local.items())
-    ] + [
-        PyBindProperty(f"port_{port.name}_connection_count")
-        for port in ports.values()
-    ]
+    param_exports = (
+        sim_object.cxx_param_exports
+        + [
+            PyBindProperty(k)
+            for k, v in sorted(sim_object._params.local.items())
+        ]
+        + [
+            PyBindProperty(f"port_{port.name}_connection_count")
+            for port in ports.values()
+        ]
+    )
     for exp in param_exports:
         exp.export(code, f"{sim_object}Params")
 
-    code(';')
+    code(";")
     code()
     code.dedent()
 
     bases = []
-    if 'cxx_base' in sim_object._value_dict:
+    if "cxx_base" in sim_object._value_dict:
         # If the c++ base class implied by python inheritance was
         # overridden, use that value.
         if sim_object.cxx_base:
@@ -170,32 +186,39 @@
 
     if bases:
         base_str = ", ".join(bases)
-        code('py::class_<${{sim_object.cxx_class}}, ${base_str}, ' \
-            'std::unique_ptr<${{sim_object.cxx_class}}, py::nodelete>>(' \
-            'm, "${py_class_name}")')
+        code(
+            "py::class_<${{sim_object.cxx_class}}, ${base_str}, "
+            "std::unique_ptr<${{sim_object.cxx_class}}, py::nodelete>>("
+            'm, "${py_class_name}")'
+        )
     else:
-        code('py::class_<${{sim_object.cxx_class}}, ' \
-            'std::unique_ptr<${{sim_object.cxx_class}}, py::nodelete>>(' \
-            'm, "${py_class_name}")')
+        code(
+            "py::class_<${{sim_object.cxx_class}}, "
+            "std::unique_ptr<${{sim_object.cxx_class}}, py::nodelete>>("
+            'm, "${py_class_name}")'
+        )
     code.indent()
     for exp in sim_object.cxx_exports:
         exp.export(code, sim_object.cxx_class)
-    code(';')
+    code(";")
     code.dedent()
     code()
     code.dedent()
-    code('}')
+    code("}")
     code()
-    code('static EmbeddedPyBind '
-         'embed_obj("${0}", module_init, "${1}");',
-        sim_object, sim_object._base.type if sim_object._base else "")
+    code(
+        "static EmbeddedPyBind " 'embed_obj("${0}", module_init, "${1}");',
+        sim_object,
+        sim_object._base.type if sim_object._base else "",
+    )
     code()
-    code('} // namespace gem5')
+    code("} // namespace gem5")
 
 # include the create() methods whether or not python is enabled.
-if not hasattr(sim_object, 'abstract') or not sim_object.abstract:
-    if 'type' in sim_object.__dict__:
-        code('''
+if not hasattr(sim_object, "abstract") or not sim_object.abstract:
+    if "type" in sim_object.__dict__:
+        code(
+            """
 namespace gem5
 {
 
@@ -268,6 +291,7 @@ class Dummy${sim_object}Shunt<CxxClass, std::enable_if_t<
 }
 
 } // namespace gem5
-''')
+"""
+        )
 
 code.write(args.param_cc)
diff --git a/build_tools/sim_object_param_struct_hh.py b/build_tools/sim_object_param_struct_hh.py
index 261ac9bf750..bf37da2a07b 100644
--- a/build_tools/sim_object_param_struct_hh.py
+++ b/build_tools/sim_object_param_struct_hh.py
@@ -46,8 +46,8 @@
 from code_formatter import code_formatter
 
 parser = argparse.ArgumentParser()
-parser.add_argument('modpath', help='module the simobject belongs to')
-parser.add_argument('param_hh', help='parameter header file to generate')
+parser.add_argument("modpath", help="module the simobject belongs to")
+parser.add_argument("param_hh", help="parameter header file to generate")
 
 args = parser.parse_args()
 
@@ -67,8 +67,9 @@
 # the object itself, not including inherited params (which
 # will also be inherited from the base class's param struct
 # here). Sort the params based on their key
-params = list(map(lambda k_v: k_v[1],
-    sorted(sim_object._params.local.items())))
+params = list(
+    map(lambda k_v: k_v[1], sorted(sim_object._params.local.items()))
+)
 ports = sim_object._ports.local
 try:
     ptypes = [p.ptype for p in params]
@@ -79,41 +80,44 @@
 
 warned_about_nested_templates = False
 
+
 class CxxClass(object):
     def __init__(self, sig, template_params=[]):
         # Split the signature into its constituent parts. This could
         # potentially be done with regular expressions, but
         # it's simple enough to pick appart a class signature
         # manually.
-        parts = sig.split('<', 1)
+        parts = sig.split("<", 1)
         base = parts[0]
         t_args = []
         if len(parts) > 1:
             # The signature had template arguments.
-            text = parts[1].rstrip(' \t\n>')
-            arg = ''
+            text = parts[1].rstrip(" \t\n>")
+            arg = ""
             # Keep track of nesting to avoid splitting on ","s embedded
             # in the arguments themselves.
             depth = 0
             for c in text:
-                if c == '<':
+                if c == "<":
                     depth = depth + 1
                     if depth > 0 and not warned_about_nested_templates:
                         warned_about_nested_templates = True
-                        print('Nested template argument in cxx_class.'
-                              ' This feature is largely untested and '
-                              ' may not work.')
-                elif c == '>':
+                        print(
+                            "Nested template argument in cxx_class."
+                            " This feature is largely untested and "
+                            " may not work."
+                        )
+                elif c == ">":
                     depth = depth - 1
-                elif c == ',' and depth == 0:
+                elif c == "," and depth == 0:
                     t_args.append(arg.strip())
-                    arg = ''
+                    arg = ""
                 else:
                     arg = arg + c
             if arg:
                 t_args.append(arg.strip())
         # Split the non-template part on :: boundaries.
-        class_path = base.split('::')
+        class_path = base.split("::")
 
         # The namespaces are everything except the last part of the class path.
         self.namespaces = class_path[:-1]
@@ -125,7 +129,7 @@ def __init__(self, sig, template_params=[]):
         # Iterate through the template arguments and their values. This
         # will likely break if parameter packs are used.
         for arg, param in zip(t_args, template_params):
-            type_keys = ('class', 'typename')
+            type_keys = ("class", "typename")
             # If a parameter is a type, parse it recursively. Otherwise
             # assume it's a constant, and store it verbatim.
             if any(param.strip().startswith(kw) for kw in type_keys):
@@ -140,21 +144,24 @@ def declare(self, code):
                 arg.declare(code)
         # Re-open the target namespace.
         for ns in self.namespaces:
-            code('namespace $ns {')
+            code("namespace $ns {")
         # If this is a class template...
         if self.template_params:
             code('template <${{", ".join(self.template_params)}}>')
         # The actual class declaration.
-        code('class ${{self.name}};')
+        code("class ${{self.name}};")
         # Close the target namespaces.
         for ns in reversed(self.namespaces):
-            code('} // namespace $ns')
+            code("} // namespace $ns")
+
 
-code('''\
+code(
+    """\
 #ifndef __PARAMS__${sim_object}__
 #define __PARAMS__${sim_object}__
 
-''')
+"""
+)
 
 
 # The base SimObject has a couple of params that get
@@ -162,10 +169,12 @@ def declare(self, code):
 # the normal Param mechanism; we slip them in here (needed
 # predecls now, actual declarations below)
 if sim_object == SimObject:
-    code('''#include <string>''')
+    code("""#include <string>""")
 
-cxx_class = CxxClass(sim_object._value_dict['cxx_class'],
-                     sim_object._value_dict['cxx_template_params'])
+cxx_class = CxxClass(
+    sim_object._value_dict["cxx_class"],
+    sim_object._value_dict["cxx_template_params"],
+)
 
 # A forward class declaration is sufficient since we are just
 # declaring a pointer.
@@ -186,27 +195,29 @@ def declare(self, code):
         code('#include "enums/${{ptype.__name__}}.hh"')
         code()
 
-code('namespace gem5')
-code('{')
-code('')
+code("namespace gem5")
+code("{")
+code("")
 
 # now generate the actual param struct
 code("struct ${sim_object}Params")
 if sim_object._base:
     code("    : public ${{sim_object._base.type}}Params")
 code("{")
-if not hasattr(sim_object, 'abstract') or not sim_object.abstract:
-    if 'type' in sim_object.__dict__:
+if not hasattr(sim_object, "abstract") or not sim_object.abstract:
+    if "type" in sim_object.__dict__:
         code("    ${{sim_object.cxx_type}} create() const;")
 
 code.indent()
 if sim_object == SimObject:
-    code('''
+    code(
+        """
 SimObjectParams() {}
 virtual ~SimObjectParams() {}
 
 std::string name;
-    ''')
+    """
+    )
 
 for param in params:
     param.cxx_decl(code)
@@ -214,11 +225,11 @@ def declare(self, code):
     port.cxx_decl(code)
 
 code.dedent()
-code('};')
+code("};")
 code()
-code('} // namespace gem5')
+code("} // namespace gem5")
 
 code()
-code('#endif // __PARAMS__${sim_object}__')
+code("#endif // __PARAMS__${sim_object}__")
 
 code.write(args.param_hh)
diff --git a/configs/common/FileSystemConfig.py b/configs/common/FileSystemConfig.py
index 8f0a57f2623..066eb9a811e 100644
--- a/configs/common/FileSystemConfig.py
+++ b/configs/common/FileSystemConfig.py
@@ -50,7 +50,7 @@
 
 
 def hex_mask(terms):
-    dec_mask = reduce(operator.or_, [2 ** i for i in terms], 0)
+    dec_mask = reduce(operator.or_, [2**i for i in terms], 0)
     return "%08x" % dec_mask
 
 
@@ -66,7 +66,7 @@ def replace_tree(path):
 
 
 def config_filesystem(system, options=None):
-    """ This function parses the system object to create the pseudo file system
+    """This function parses the system object to create the pseudo file system
     @param system: The system to create the config for
     @param options: An optional argument which contains an Options.py options
            object. This is useful if when use se.py and will set the L2 cache
diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py
index 80fd570a308..baa0d233af1 100644
--- a/configs/common/MemConfig.py
+++ b/configs/common/MemConfig.py
@@ -177,7 +177,7 @@ def config_mem(options, system):
     from m5.util import fatal
 
     intlv_bits = int(math.log(nbr_mem_ctrls, 2))
-    if 2 ** intlv_bits != nbr_mem_ctrls:
+    if 2**intlv_bits != nbr_mem_ctrls:
         fatal("Number of memory channels must be a power of 2")
 
     if opt_mem_type:
diff --git a/configs/common/ObjectList.py b/configs/common/ObjectList.py
index 7b6cac9c69f..ad27d9e656c 100644
--- a/configs/common/ObjectList.py
+++ b/configs/common/ObjectList.py
@@ -42,11 +42,11 @@
 
 
 class ObjectList(object):
-    """ Creates a list of objects that are sub-classes of a given class. """
+    """Creates a list of objects that are sub-classes of a given class."""
 
     def _is_obj_class(self, cls):
         """Determine if a class is a a sub class of the provided base class
-           that can be instantiated.
+        that can be instantiated.
         """
 
         # We can't use the normal inspect.isclass because the ParamFactory
@@ -161,10 +161,10 @@ def _add_objects(self):
 
 
 class EnumList(ObjectList):
-    """ Creates a list of possible values for a given enum class. """
+    """Creates a list of possible values for a given enum class."""
 
     def _add_objects(self):
-        """ Add all enum values to the ObjectList """
+        """Add all enum values to the ObjectList"""
         self._sub_classes = {}
         for (key, value) in list(self.base_cls.__members__.items()):
             # All Enums have a value Num_NAME at the end which we
diff --git a/configs/common/SimpleOpts.py b/configs/common/SimpleOpts.py
index 35fac643372..96c73f57b83 100644
--- a/configs/common/SimpleOpts.py
+++ b/configs/common/SimpleOpts.py
@@ -46,8 +46,7 @@
 
 
 def add_option(*args, **kwargs):
-    """Call "add_option" to the global options parser
-    """
+    """Call "add_option" to the global options parser"""
 
     if called_parse_args:
         m5.fatal("Can't add an option after calling SimpleOpts.parse_args")
diff --git a/configs/dist/sw.py b/configs/dist/sw.py
index 41edf9e21b6..726735773ef 100644
--- a/configs/dist/sw.py
+++ b/configs/dist/sw.py
@@ -35,33 +35,39 @@
 from m5.objects import *
 from m5.util import addToPath, fatal
 
-addToPath('../')
+addToPath("../")
 
 from common import Simulation
 from common import Options
 
+
 def build_switch(args):
     # instantiate an EtherSwitch
     switch = EtherSwitch()
     # instantiate distEtherLinks to connect switch ports
     # to other gem5 instances
-    switch.portlink = [DistEtherLink(speed = args.ethernet_linkspeed,
-                                      delay = args.ethernet_linkdelay,
-                                      dist_rank = args.dist_rank,
-                                      dist_size = args.dist_size,
-                                      server_name = args.dist_server_name,
-                                      server_port = args.dist_server_port,
-                                      sync_start = args.dist_sync_start,
-                                      sync_repeat = args.dist_sync_repeat,
-                                      is_switch = True,
-                                      num_nodes = args.dist_size)
-                       for i in range(args.dist_size)]
+    switch.portlink = [
+        DistEtherLink(
+            speed=args.ethernet_linkspeed,
+            delay=args.ethernet_linkdelay,
+            dist_rank=args.dist_rank,
+            dist_size=args.dist_size,
+            server_name=args.dist_server_name,
+            server_port=args.dist_server_port,
+            sync_start=args.dist_sync_start,
+            sync_repeat=args.dist_sync_repeat,
+            is_switch=True,
+            num_nodes=args.dist_size,
+        )
+        for i in range(args.dist_size)
+    ]
 
     for (i, link) in enumerate(switch.portlink):
         link.int0 = switch.interface[i]
 
     return switch
 
+
 def main():
     # Add options
     parser = argparse.ArgumentParser()
@@ -70,8 +76,9 @@ def main():
     args = parser.parse_args()
 
     system = build_switch(args)
-    root = Root(full_system = True, system = system)
+    root = Root(full_system=True, system=system)
     Simulation.run(args, root, None, None)
 
+
 if __name__ == "__m5_main__":
     main()
diff --git a/configs/example/arm/baremetal.py b/configs/example/arm/baremetal.py
index a12f5397b2f..9eeba37ff7c 100644
--- a/configs/example/arm/baremetal.py
+++ b/configs/example/arm/baremetal.py
@@ -74,7 +74,7 @@ def create_cow_image(name):
 
 
 def create(args):
-    """ Create and configure the system object. """
+    """Create and configure the system object."""
 
     if args.readfile and not os.path.isfile(args.readfile):
         print("Error: Bootscript %s does not exist" % args.readfile)
diff --git a/configs/example/arm/ruby_fs.py b/configs/example/arm/ruby_fs.py
index 8ef38a36862..d58184522ce 100644
--- a/configs/example/arm/ruby_fs.py
+++ b/configs/example/arm/ruby_fs.py
@@ -97,7 +97,7 @@ def config_ruby(system, args):
 
 
 def create(args):
-    """ Create and configure the system object. """
+    """Create and configure the system object."""
 
     if args.script and not os.path.isfile(args.script):
         print("Error: Bootscript %s does not exist" % args.script)
diff --git a/configs/example/arm/starter_fs.py b/configs/example/arm/starter_fs.py
index 3434630e7bb..3a9a8762d6c 100644
--- a/configs/example/arm/starter_fs.py
+++ b/configs/example/arm/starter_fs.py
@@ -85,7 +85,7 @@ def create_cow_image(name):
 
 
 def create(args):
-    """ Create and configure the system object. """
+    """Create and configure the system object."""
 
     if args.script and not os.path.isfile(args.script):
         print("Error: Bootscript %s does not exist" % args.script)
diff --git a/configs/example/arm/starter_se.py b/configs/example/arm/starter_se.py
index f5d4810b76c..08c3d74fbdf 100644
--- a/configs/example/arm/starter_se.py
+++ b/configs/example/arm/starter_se.py
@@ -142,7 +142,7 @@ def get_processes(cmd):
 
 
 def create(args):
-    """ Create and configure the system object. """
+    """Create and configure the system object."""
 
     system = SimpleSeSystem(args)
 
diff --git a/configs/example/arm/workloads.py b/configs/example/arm/workloads.py
index a2228e8d936..5c70dabfc28 100644
--- a/configs/example/arm/workloads.py
+++ b/configs/example/arm/workloads.py
@@ -44,7 +44,7 @@
 
 
 class ArmBaremetal(ArmFsWorkload):
-    """ Baremetal workload """
+    """Baremetal workload"""
 
     dtb_addr = 0
 
diff --git a/configs/example/gem5_library/checkpoints/riscv-hello-save-checkpoint.py b/configs/example/gem5_library/checkpoints/riscv-hello-save-checkpoint.py
index ef5a12af550..c00b43d404a 100644
--- a/configs/example/gem5_library/checkpoints/riscv-hello-save-checkpoint.py
+++ b/configs/example/gem5_library/checkpoints/riscv-hello-save-checkpoint.py
@@ -92,7 +92,7 @@
 )
 
 # Lastly we run the simulation.
-max_ticks = 10 ** 6
+max_ticks = 10**6
 simulator = Simulator(board=board, full_system=False)
 simulator.run(max_ticks=max_ticks)
 
diff --git a/configs/example/lupv/README.md b/configs/example/lupv/README.md
index d5895db4af8..4f1e33c520d 100644
--- a/configs/example/lupv/README.md
+++ b/configs/example/lupv/README.md
@@ -41,4 +41,4 @@ m5term localhost 3456
 ```
 
 This should allow you to run busybox, in which you can see the LupIO device at
-work!
\ No newline at end of file
+work!
diff --git a/configs/learning_gem5/part1/caches.py b/configs/learning_gem5/part1/caches.py
index 52bc93e1340..9bb06ab2e62 100644
--- a/configs/learning_gem5/part1/caches.py
+++ b/configs/learning_gem5/part1/caches.py
@@ -64,7 +64,7 @@ def connectBus(self, bus):
 
     def connectCPU(self, cpu):
         """Connect this cache's port to a CPU-side port
-           This must be defined in a subclass"""
+        This must be defined in a subclass"""
         raise NotImplementedError
 
 
diff --git a/configs/learning_gem5/part3/msi_caches.py b/configs/learning_gem5/part3/msi_caches.py
index 64ab78d8d2d..3a8f51136de 100644
--- a/configs/learning_gem5/part3/msi_caches.py
+++ b/configs/learning_gem5/part3/msi_caches.py
@@ -52,9 +52,9 @@ def __init__(self):
 
     def setup(self, system, cpus, mem_ctrls):
         """Set up the Ruby cache subsystem. Note: This can't be done in the
-           constructor because many of these items require a pointer to the
-           ruby system (self). This causes infinite recursion in initialize()
-           if we do this in the __init__.
+        constructor because many of these items require a pointer to the
+        ruby system (self). This causes infinite recursion in initialize()
+        if we do this in the __init__.
         """
         # Ruby's global network.
         self.network = MyNetwork(self)
@@ -120,7 +120,7 @@ def versionCount(cls):
 
     def __init__(self, system, ruby_system, cpu):
         """CPUs are needed to grab the clock domain and system is needed for
-           the cache block size.
+        the cache block size.
         """
         super(L1Cache, self).__init__()
 
@@ -136,24 +136,23 @@ def __init__(self, system, ruby_system, cpu):
 
     def getBlockSizeBits(self, system):
         bits = int(math.log(system.cache_line_size, 2))
-        if 2 ** bits != system.cache_line_size.value:
+        if 2**bits != system.cache_line_size.value:
             panic("Cache line size not a power of 2!")
         return bits
 
     def sendEvicts(self, cpu):
         """True if the CPU model or ISA requires sending evictions from caches
-           to the CPU. Two scenarios warrant forwarding evictions to the CPU:
-           1. The O3 model must keep the LSQ coherent with the caches
-           2. The x86 mwait instruction is built on top of coherence
-           3. The local exclusive monitor in ARM systems
+        to the CPU. Two scenarios warrant forwarding evictions to the CPU:
+        1. The O3 model must keep the LSQ coherent with the caches
+        2. The x86 mwait instruction is built on top of coherence
+        3. The local exclusive monitor in ARM systems
         """
         if type(cpu) is DerivO3CPU or buildEnv["TARGET_ISA"] in ("x86", "arm"):
             return True
         return False
 
     def connectQueues(self, ruby_system):
-        """Connect all of the queues for this controller.
-        """
+        """Connect all of the queues for this controller."""
         # mandatoryQueue is a special variable. It is used by the sequencer to
         # send RubyRequests from the CPU (or other processor). It isn't
         # explicitly connected to anything.
@@ -184,8 +183,7 @@ def versionCount(cls):
         return cls._version - 1
 
     def __init__(self, ruby_system, ranges, mem_ctrls):
-        """ranges are the memory ranges assigned to this controller.
-        """
+        """ranges are the memory ranges assigned to this controller."""
         if len(mem_ctrls) > 1:
             panic("This cache system can only be connected to one mem ctrl")
         super(DirController, self).__init__()
@@ -217,8 +215,7 @@ def connectQueues(self, ruby_system):
 
 
 class MyNetwork(SimpleNetwork):
-    """A simple point-to-point network. This doesn't not use garnet.
-    """
+    """A simple point-to-point network. This doesn't not use garnet."""
 
     def __init__(self, ruby_system):
         super(MyNetwork, self).__init__()
@@ -227,7 +224,7 @@ def __init__(self, ruby_system):
 
     def connectControllers(self, controllers):
         """Connect all of the controllers to routers and connec the routers
-           together in a point-to-point network.
+        together in a point-to-point network.
         """
         # Create one router/switch per controller in the system
         self.routers = [Switch(router_id=i) for i in range(len(controllers))]
diff --git a/configs/learning_gem5/part3/ruby_caches_MI_example.py b/configs/learning_gem5/part3/ruby_caches_MI_example.py
index 599225be9c9..29b14fb3407 100644
--- a/configs/learning_gem5/part3/ruby_caches_MI_example.py
+++ b/configs/learning_gem5/part3/ruby_caches_MI_example.py
@@ -54,9 +54,9 @@ def __init__(self):
 
     def setup(self, system, cpus, mem_ctrls):
         """Set up the Ruby cache subsystem. Note: This can't be done in the
-           constructor because many of these items require a pointer to the
-           ruby system (self). This causes infinite recursion in initialize()
-           if we do this in the __init__.
+        constructor because many of these items require a pointer to the
+        ruby system (self). This causes infinite recursion in initialize()
+        if we do this in the __init__.
         """
         # Ruby's global network.
         self.network = MyNetwork(self)
@@ -118,7 +118,7 @@ def versionCount(cls):
 
     def __init__(self, system, ruby_system, cpu):
         """CPUs are needed to grab the clock domain and system is needed for
-           the cache block size.
+        the cache block size.
         """
         super(L1Cache, self).__init__()
 
@@ -134,24 +134,23 @@ def __init__(self, system, ruby_system, cpu):
 
     def getBlockSizeBits(self, system):
         bits = int(math.log(system.cache_line_size, 2))
-        if 2 ** bits != system.cache_line_size.value:
+        if 2**bits != system.cache_line_size.value:
             panic("Cache line size not a power of 2!")
         return bits
 
     def sendEvicts(self, cpu):
         """True if the CPU model or ISA requires sending evictions from caches
-           to the CPU. Two scenarios warrant forwarding evictions to the CPU:
-           1. The O3 model must keep the LSQ coherent with the caches
-           2. The x86 mwait instruction is built on top of coherence
-           3. The local exclusive monitor in ARM systems
+        to the CPU. Two scenarios warrant forwarding evictions to the CPU:
+        1. The O3 model must keep the LSQ coherent with the caches
+        2. The x86 mwait instruction is built on top of coherence
+        3. The local exclusive monitor in ARM systems
         """
         if type(cpu) is DerivO3CPU or buildEnv["TARGET_ISA"] in ("x86", "arm"):
             return True
         return False
 
     def connectQueues(self, ruby_system):
-        """Connect all of the queues for this controller.
-        """
+        """Connect all of the queues for this controller."""
         self.mandatoryQueue = MessageBuffer()
         self.requestFromCache = MessageBuffer(ordered=True)
         self.requestFromCache.out_port = ruby_system.network.in_port
@@ -173,8 +172,7 @@ def versionCount(cls):
         return cls._version - 1
 
     def __init__(self, ruby_system, ranges, mem_ctrls):
-        """ranges are the memory ranges assigned to this controller.
-        """
+        """ranges are the memory ranges assigned to this controller."""
         if len(mem_ctrls) > 1:
             panic("This cache system can only be connected to one mem ctrl")
         super(DirController, self).__init__()
@@ -203,8 +201,7 @@ def connectQueues(self, ruby_system):
 
 
 class MyNetwork(SimpleNetwork):
-    """A simple point-to-point network. This doesn't not use garnet.
-    """
+    """A simple point-to-point network. This doesn't not use garnet."""
 
     def __init__(self, ruby_system):
         super(MyNetwork, self).__init__()
@@ -213,7 +210,7 @@ def __init__(self, ruby_system):
 
     def connectControllers(self, controllers):
         """Connect all of the controllers to routers and connec the routers
-           together in a point-to-point network.
+        together in a point-to-point network.
         """
         # Create one router/switch per controller in the system
         self.routers = [Switch(router_id=i) for i in range(len(controllers))]
diff --git a/configs/learning_gem5/part3/test_caches.py b/configs/learning_gem5/part3/test_caches.py
index 93847291e06..7b0ce52dadf 100644
--- a/configs/learning_gem5/part3/test_caches.py
+++ b/configs/learning_gem5/part3/test_caches.py
@@ -52,11 +52,11 @@ def __init__(self):
 
     def setup(self, system, tester, mem_ctrls):
         """Set up the Ruby cache subsystem. Note: This can't be done in the
-           constructor because many of these items require a pointer to the
-           ruby system (self). This causes infinite recursion in initialize()
-           if we do this in the __init__.
-           Setting up for running the RubyRandomTester is a little different
-           than when we're using CPUs.
+        constructor because many of these items require a pointer to the
+        ruby system (self). This causes infinite recursion in initialize()
+        if we do this in the __init__.
+        Setting up for running the RubyRandomTester is a little different
+        than when we're using CPUs.
         """
         num_testers = tester.num_cpus
 
diff --git a/configs/ruby/CHI.py b/configs/ruby/CHI.py
index 21434ca2d79..d31d2336ba4 100644
--- a/configs/ruby/CHI.py
+++ b/configs/ruby/CHI.py
@@ -52,7 +52,7 @@ def define_options(parser):
 
 
 def read_config_file(file):
-    """ Read file as a module and return it """
+    """Read file as a module and return it"""
     import types
     import importlib.machinery
 
diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py
index 8b227fab61d..db096aaec47 100644
--- a/configs/ruby/Ruby.py
+++ b/configs/ruby/Ruby.py
@@ -200,10 +200,10 @@ def setup_memory_controllers(system, ruby, dir_cntrls, options):
 
 
 def create_topology(controllers, options):
-    """ Called from create_system in configs/ruby/<protocol>.py
-        Must return an object which is a subclass of BaseTopology
-        found in configs/topologies/BaseTopology.py
-        This is a wrapper for the legacy topologies.
+    """Called from create_system in configs/ruby/<protocol>.py
+    Must return an object which is a subclass of BaseTopology
+    found in configs/topologies/BaseTopology.py
+    This is a wrapper for the legacy topologies.
     """
     exec("import topologies.%s as Topo" % options.topology)
     topology = eval("Topo.%s(controllers)" % options.topology)
diff --git a/configs/topologies/BaseTopology.py b/configs/topologies/BaseTopology.py
index 13658ebc616..cdcca3f7eb5 100644
--- a/configs/topologies/BaseTopology.py
+++ b/configs/topologies/BaseTopology.py
@@ -31,37 +31,37 @@ class BaseTopology(object):
     description = "BaseTopology"
 
     def __init__(self):
-        """ When overriding place any objects created in
-            configs/ruby/<protocol>.py that are needed in
-            makeTopology (below) here. The minimum is usually
-            all of the controllers created in the above file.
+        """When overriding place any objects created in
+        configs/ruby/<protocol>.py that are needed in
+        makeTopology (below) here. The minimum is usually
+        all of the controllers created in the above file.
         """
 
     def makeTopology(self, options, network, IntLink, ExtLink, Router):
-        """ Called from configs/ruby/Ruby.py
-            The return value is ( list(Router), list(IntLink), list(ExtLink))
-            The API of this function cannot change when subclassing!!
-            Any additional information needed to create this topology should
-            be passed into the constructor when it's instantiated in
-            configs/ruby/<protocol>.py
+        """Called from configs/ruby/Ruby.py
+        The return value is ( list(Router), list(IntLink), list(ExtLink))
+        The API of this function cannot change when subclassing!!
+        Any additional information needed to create this topology should
+        be passed into the constructor when it's instantiated in
+        configs/ruby/<protocol>.py
         """
         m5.util.fatal("BaseTopology should have been overridden!!")
 
     def registerTopology(self, options):
-        """ Called from configs/ruby/Ruby.py
-            There is no return value. This should only be called in
-            SE mode. It is used by some topology objects to populate
-            the faux filesystem with accurate file contents.
-            No need to implement if not using FilesystemRegister
-            functionality.
+        """Called from configs/ruby/Ruby.py
+        There is no return value. This should only be called in
+        SE mode. It is used by some topology objects to populate
+        the faux filesystem with accurate file contents.
+        No need to implement if not using FilesystemRegister
+        functionality.
         """
 
 
 class SimpleTopology(BaseTopology):
-    """ Provides methods needed for the topologies included in Ruby before
-        topology changes.
-        These topologies are "simple" in the sense that they only use a flat
-        list of controllers to construct the topology.
+    """Provides methods needed for the topologies included in Ruby before
+    topology changes.
+    These topologies are "simple" in the sense that they only use a flat
+    list of controllers to construct the topology.
     """
 
     description = "SimpleTopology"
diff --git a/configs/topologies/Cluster.py b/configs/topologies/Cluster.py
index d949c382d2f..e0504f60430 100644
--- a/configs/topologies/Cluster.py
+++ b/configs/topologies/Cluster.py
@@ -28,10 +28,10 @@
 
 
 class Cluster(BaseTopology):
-    """ A cluster is a group of nodes which are all one hop from eachother
-        Clusters can also contain other clusters
-        When creating this kind of topology, return a single cluster (usually
-        the root cluster) from create_system in configs/ruby/<protocol>.py
+    """A cluster is a group of nodes which are all one hop from eachother
+    Clusters can also contain other clusters
+    When creating this kind of topology, return a single cluster (usually
+    the root cluster) from create_system in configs/ruby/<protocol>.py
     """
 
     _num_int_links = 0
@@ -55,13 +55,13 @@ def num_routers(cls):
         return cls._num_routers - 1
 
     def __init__(self, intBW=0, extBW=0, intLatency=0, extLatency=0):
-        """ internalBandwidth is bandwidth of all links within the cluster
-            externalBandwidth is bandwidth from this cluster to any cluster
-                connecting to it.
-            internal/externalLatency are similar
-            **** When creating a cluster with sub-clusters, the sub-cluster
-                 external bandwidth overrides the internal bandwidth of the
-                 super cluster
+        """internalBandwidth is bandwidth of all links within the cluster
+        externalBandwidth is bandwidth from this cluster to any cluster
+            connecting to it.
+        internal/externalLatency are similar
+        **** When creating a cluster with sub-clusters, the sub-cluster
+             external bandwidth overrides the internal bandwidth of the
+             super cluster
         """
         self.nodes = []
         self.router = None  # created in makeTopology
@@ -74,8 +74,7 @@ def add(self, node):
         self.nodes.append(node)
 
     def makeTopology(self, options, network, IntLink, ExtLink, Router):
-        """ Recursively make all of the links and routers
-        """
+        """Recursively make all of the links and routers"""
 
         # make a router to connect all of the nodes
         self.router = Router(router_id=self.num_routers())
diff --git a/site_scons/gem5_python_paths.py b/site_scons/gem5_python_paths.py
index 2e51e2f8ede..26e95947066 100644
--- a/site_scons/gem5_python_paths.py
+++ b/site_scons/gem5_python_paths.py
@@ -41,13 +41,13 @@
 import SCons.Node.FS
 
 fs = SCons.Node.FS.get_default_fs()
-root = fs.Dir('#')
+root = fs.Dir("#")
 extra_python_nodes = [
-    root.Dir('src').Dir('python').srcnode(), # gem5 includes
-    root.Dir('ext').Dir('ply').srcnode(), # ply is used by several files
-    root.Dir('ext').Dir('Kconfiglib').Dir('import').srcnode(), # kconfiglib
+    root.Dir("src").Dir("python").srcnode(),  # gem5 includes
+    root.Dir("ext").Dir("ply").srcnode(),  # ply is used by several files
+    root.Dir("ext").Dir("Kconfiglib").Dir("import").srcnode(),  # kconfiglib
 ]
 
-extra_python_paths = [ node.abspath for node in extra_python_nodes ]
+extra_python_paths = [node.abspath for node in extra_python_nodes]
 
-__all__ = ['extra_python_paths']
+__all__ = ["extra_python_paths"]
diff --git a/site_scons/gem5_scons/__init__.py b/site_scons/gem5_scons/__init__.py
index bf7b85d35df..c958e22cc04 100644
--- a/site_scons/gem5_scons/__init__.py
+++ b/site_scons/gem5_scons/__init__.py
@@ -52,34 +52,38 @@
 
 termcap = get_termcap()
 
+
 def strip_build_path(path, env):
     path = str(path)
-    build_base = 'build/'
-    variant_base = env['BUILDROOT'] + os.path.sep
+    build_base = "build/"
+    variant_base = env["BUILDROOT"] + os.path.sep
     if path.startswith(variant_base):
-        path = path[len(variant_base):]
+        path = path[len(variant_base) :]
     elif path.startswith(build_base):
-        path = path[len(build_base):]
+        path = path[len(build_base) :]
     return path
 
+
 def TempFileSpawn(scons_env):
-    old_pspawn = scons_env['PSPAWN']
-    old_spawn = scons_env['SPAWN']
+    old_pspawn = scons_env["PSPAWN"]
+    old_spawn = scons_env["SPAWN"]
 
     def wrapper(old, sh, esc, cmd, sh_args, *py_args):
         with tempfile.NamedTemporaryFile() as temp:
-            temp.write(' '.join(sh_args).encode())
+            temp.write(" ".join(sh_args).encode())
             temp.flush()
             sh_args = [sh, esc(temp.name)]
             return old(sh, esc, sh, sh_args, *py_args)
 
     def new_pspawn(sh, esc, cmd, args, sh_env, stdout, stderr):
         return wrapper(old_pspawn, sh, esc, cmd, args, sh_env, stdout, stderr)
+
     def new_spawn(sh, esc, cmd, args, sh_env):
         return wrapper(old_spawn, sh, esc, cmd, args, sh_env)
 
-    scons_env['PSPAWN'] = new_pspawn
-    scons_env['SPAWN'] = new_spawn
+    scons_env["PSPAWN"] = new_pspawn
+    scons_env["SPAWN"] = new_spawn
+
 
 # Generate a string of the form:
 #   common/path/prefix/src1, src2 -> tgt1, tgt2
@@ -93,23 +97,32 @@ class Transform(object):
     tgts_color = termcap.Yellow + termcap.Bold
 
     def __init__(self, tool, max_sources=99):
-        self.format = self.tool_color + (" [%8s] " % tool) \
-                      + self.pfx_color + "%s" \
-                      + self.srcs_color + "%s" \
-                      + self.arrow_color + " -> " \
-                      + self.tgts_color + "%s" \
-                      + termcap.Normal
+        self.format = (
+            self.tool_color
+            + (" [%8s] " % tool)
+            + self.pfx_color
+            + "%s"
+            + self.srcs_color
+            + "%s"
+            + self.arrow_color
+            + " -> "
+            + self.tgts_color
+            + "%s"
+            + termcap.Normal
+        )
         self.max_sources = max_sources
 
     def __call__(self, target, source, env, for_signature=None):
         # truncate source list according to max_sources param
-        source = source[0:self.max_sources]
+        source = source[0 : self.max_sources]
+
         def strip(f):
             return strip_build_path(str(f), env)
+
         if len(source) > 0:
             srcs = list(map(strip, source))
         else:
-            srcs = ['']
+            srcs = [""]
         tgts = list(map(strip, target))
         # surprisingly, os.path.commonprefix is a dumb char-by-char string
         # operation that has nothing to do with paths.
@@ -137,20 +150,23 @@ def strip(f):
                     if sep_idx != -1:
                         com_pfx = com_pfx[0:sep_idx]
                     else:
-                        com_pfx = ''
+                        com_pfx = ""
                 elif src0_len > com_pfx_len and srcs[0][com_pfx_len] == ".":
                     # still splitting at file extension: ok
                     pass
                 else:
                     # probably a fluke; ignore it
-                    com_pfx = ''
+                    com_pfx = ""
         # recalculate length in case com_pfx was modified
         com_pfx_len = len(com_pfx)
+
         def fmt(files):
             f = list(map(lambda s: s[com_pfx_len:], files))
-            return ', '.join(f)
+            return ", ".join(f)
+
         return self.format % (com_pfx, fmt(srcs), fmt(tgts))
 
+
 # The width warning and error messages should be wrapped at.
 text_width = None
 
@@ -162,6 +178,7 @@ def fmt(files):
 if text_width is None:
     try:
         import shutil
+
         text_width = shutil.get_terminal_size().columns
     except:
         pass
@@ -170,6 +187,7 @@ def fmt(files):
 if text_width is None:
     try:
         import curses
+
         try:
             _, text_width = curses.initscr().getmaxyx()
         finally:
@@ -181,21 +199,22 @@ def fmt(files):
 if text_width is None:
     text_width = 80
 
+
 def print_message(prefix, color, message, **kwargs):
     prefix_len = len(prefix)
     if text_width > prefix_len:
         wrap_width = text_width - prefix_len
-        padding = ' ' * prefix_len
+        padding = " " * prefix_len
 
         # First split on newlines.
-        lines = message.split('\n')
+        lines = message.split("\n")
         # Then wrap each line to the required width.
         wrapped_lines = []
         for line in lines:
             wrapped_lines.extend(textwrap.wrap(line, wrap_width))
         # Finally add the prefix and padding on extra lines, and glue it all
         # back together.
-        message = prefix + ('\n' + padding).join(wrapped_lines)
+        message = prefix + ("\n" + padding).join(wrapped_lines)
     else:
         # We have very small terminal, indent formatting doesn't help.
         message = prefix + message
@@ -205,27 +224,36 @@ def print_message(prefix, color, message, **kwargs):
     print(message, **kwargs)
     return message
 
+
 all_warnings = []
+
+
 def summarize_warnings():
     if not all_warnings:
         return
-    print(termcap.Yellow + termcap.Bold +
-            '*** Summary of Warnings ***' +
-            termcap.Normal)
+    print(
+        termcap.Yellow
+        + termcap.Bold
+        + "*** Summary of Warnings ***"
+        + termcap.Normal
+    )
     list(map(print, all_warnings))
 
+
 def warning(*args, **kwargs):
-    message = ' '.join(args)
-    printed = print_message('Warning: ', termcap.Yellow, message, **kwargs)
+    message = " ".join(args)
+    printed = print_message("Warning: ", termcap.Yellow, message, **kwargs)
     all_warnings.append(printed)
 
+
 def error(*args, **kwargs):
-    message = ' '.join(args)
-    print_message('Error: ', termcap.Red, message, **kwargs)
+    message = " ".join(args)
+    print_message("Error: ", termcap.Red, message, **kwargs)
     SCons.Script.Exit(1)
 
+
 def parse_build_path(target):
-    path_dirs = target.split('/')
+    path_dirs = target.split("/")
 
     # Pop off the target file.
     path_dirs.pop()
@@ -233,40 +261,55 @@ def parse_build_path(target):
     # Search backwards for the "build" directory. Whatever was just before it
     # was the name of the variant.
     variant_dir = path_dirs.pop()
-    while path_dirs and path_dirs[-1] != 'build':
+    while path_dirs and path_dirs[-1] != "build":
         variant_dir = path_dirs.pop()
     if not path_dirs:
         error("No non-leaf 'build' dir found on target path.", t)
 
-    return os.path.join('/', *path_dirs), variant_dir
+    return os.path.join("/", *path_dirs), variant_dir
+
 
 # The MakeAction wrapper, and a SCons tool to set up the *COMSTR variables.
-if SCons.Script.GetOption('verbose'):
+if SCons.Script.GetOption("verbose"):
+
     def MakeAction(action, string, *args, **kwargs):
         return SCons.Script.Action(action, *args, **kwargs)
 
     def MakeActionTool(env):
         pass
+
 else:
     MakeAction = SCons.Script.Action
 
     def MakeActionTool(env):
-        env['CCCOMSTR']        = Transform("CC")
-        env['CXXCOMSTR']       = Transform("CXX")
-        env['ASCOMSTR']        = Transform("AS")
-        env['ARCOMSTR']        = Transform("AR", 0)
-        env['LINKCOMSTR']      = Transform("LINK", 0)
-        env['SHLINKCOMSTR']    = Transform("SHLINK", 0)
-        env['RANLIBCOMSTR']    = Transform("RANLIB", 0)
-        env['M4COMSTR']        = Transform("M4")
-        env['SHCCCOMSTR']      = Transform("SHCC")
-        env['SHCXXCOMSTR']     = Transform("SHCXX")
+        env["CCCOMSTR"] = Transform("CC")
+        env["CXXCOMSTR"] = Transform("CXX")
+        env["ASCOMSTR"] = Transform("AS")
+        env["ARCOMSTR"] = Transform("AR", 0)
+        env["LINKCOMSTR"] = Transform("LINK", 0)
+        env["SHLINKCOMSTR"] = Transform("SHLINK", 0)
+        env["RANLIBCOMSTR"] = Transform("RANLIB", 0)
+        env["M4COMSTR"] = Transform("M4")
+        env["SHCCCOMSTR"] = Transform("SHCC")
+        env["SHCXXCOMSTR"] = Transform("SHCXX")
+
 
 def ToValue(obj):
     return SCons.Node.Python.Value(pickle.dumps(obj))
 
+
 def FromValue(node):
     return pickle.loads(node.read())
 
-__all__ = ['Configure', 'EnvDefaults', 'Transform', 'warning', 'error',
-           'MakeAction', 'MakeActionTool', 'ToValue', 'FromValue']
+
+__all__ = [
+    "Configure",
+    "EnvDefaults",
+    "Transform",
+    "warning",
+    "error",
+    "MakeAction",
+    "MakeActionTool",
+    "ToValue",
+    "FromValue",
+]
diff --git a/site_scons/gem5_scons/builders/add_local_rpath.py b/site_scons/gem5_scons/builders/add_local_rpath.py
index ce26575614a..fb7ffb88f65 100755
--- a/site_scons/gem5_scons/builders/add_local_rpath.py
+++ b/site_scons/gem5_scons/builders/add_local_rpath.py
@@ -43,26 +43,23 @@
 
 import SCons.Node.FS
 
+
 def AddLocalRPATH(env):
     def add_local_rpath(env, *targets):
-        '''Set up an RPATH for a library which lives in the build directory.
+        """Set up an RPATH for a library which lives in the build directory.
 
         The construction environment variable BIN_RPATH_PREFIX should be set
         to the relative path of the build directory starting from the location
-        of the binary.'''
+        of the binary."""
         for target in targets:
             target = env.Entry(target)
             if not isinstance(target, SCons.Node.FS.Dir):
                 target = target.dir
-            relpath = os.path.relpath(target.abspath, env['BUILDDIR'])
-            components = [
-                '\\$$ORIGIN',
-                '${BIN_RPATH_PREFIX}',
-                relpath
-            ]
+            relpath = os.path.relpath(target.abspath, env["BUILDDIR"])
+            components = ["\\$$ORIGIN", "${BIN_RPATH_PREFIX}", relpath]
             env.Append(RPATH=[env.Literal(os.path.join(*components))])
 
     if sys.platform != "darwin":
-        env.Append(LINKFLAGS=env.Split('-z origin'))
+        env.Append(LINKFLAGS=env.Split("-z origin"))
 
-    env.AddMethod(add_local_rpath, 'AddLocalRPATH')
+    env.AddMethod(add_local_rpath, "AddLocalRPATH")
diff --git a/site_scons/gem5_scons/builders/blob.py b/site_scons/gem5_scons/builders/blob.py
index 20d804a2e99..f4e6d3a0eae 100644
--- a/site_scons/gem5_scons/builders/blob.py
+++ b/site_scons/gem5_scons/builders/blob.py
@@ -46,19 +46,21 @@
 
 import SCons.Node.Python
 
+
 def build_blob(target, source, env):
-    '''
+    """
     Embed an arbitrary blob into the gem5 executable,
     and make it accessible to C++ as a byte array.
-    '''
+    """
 
-    with open(str(source[0]), 'rb') as f:
+    with open(str(source[0]), "rb") as f:
         data = f.read()
     symbol = str(source[1])
     cc, hh = target
 
     hh_code = code_formatter()
-    hh_code('''\
+    hh_code(
+        """\
 #include <cstddef>
 #include <cstdint>
 
@@ -72,13 +74,15 @@ def build_blob(target, source, env):
 
 } // namespace Blobs
 } // namespace gem5
-''')
+"""
+    )
     hh_code.write(str(hh))
 
-    include_path = os.path.relpath(hh.abspath, env['BUILDDIR'])
+    include_path = os.path.relpath(hh.abspath, env["BUILDDIR"])
 
     cc_code = code_formatter()
-    cc_code('''\
+    cc_code(
+        """\
 #include "${include_path}"
 
 namespace gem5
@@ -87,22 +91,28 @@ def build_blob(target, source, env):
 {
 
 const std::size_t ${symbol}_len = ${{len(data)}};
-''')
+"""
+    )
     bytesToCppArray(cc_code, symbol, data)
-    cc_code('''
+    cc_code(
+        """
 } // namespace Blobs
 } // namespace gem5
-''')
+"""
+    )
     cc_code.write(str(cc))
 
+
 blob_action = MakeAction(build_blob, Transform("EMBED BLOB"))
 
+
 def blob_emitter(target, source, env):
     symbol = str(target[0])
-    cc_file = env.File(symbol + '.cc')
-    hh_file = env.File(symbol + '.hh')
+    cc_file = env.File(symbol + ".cc")
+    hh_file = env.File(symbol + ".hh")
     return [cc_file, hh_file], [source, SCons.Node.Python.Value(symbol)]
 
+
 def Blob(env):
     blob_builder = env.Builder(action=blob_action, emitter=blob_emitter)
-    env.Append(BUILDERS={'Blob': blob_builder})
+    env.Append(BUILDERS={"Blob": blob_builder})
diff --git a/site_scons/gem5_scons/builders/config_file.py b/site_scons/gem5_scons/builders/config_file.py
index 85820b9fb73..2ab7bf87b40 100755
--- a/site_scons/gem5_scons/builders/config_file.py
+++ b/site_scons/gem5_scons/builders/config_file.py
@@ -46,15 +46,16 @@
 #
 ###################################################
 
+
 def ConfigFile(env):
     # This function generates a config header file that #defines the
     # variable symbol to the current variable setting (0 or 1).  The source
     # operands are the name of the variable and a Value node containing the
     # value of the variable.
     def build_config_file(target, source, env):
-        (variable, value) = [s.get_contents().decode('utf-8') for s in source]
-        with open(str(target[0].abspath), 'w') as f:
-            print('#define', variable, value, file=f)
+        (variable, value) = [s.get_contents().decode("utf-8") for s in source]
+        with open(str(target[0].abspath), "w") as f:
+            print("#define", variable, value, file=f)
         return None
 
     # Combine the two functions into a scons Action object.
@@ -66,8 +67,8 @@ def config_emitter(target, source, env):
         # extract variable name from Builder arg
         variable = str(target[0])
         # True target is config header file
-        target = env.Dir('config').File(variable.lower() + '.hh')
-        val = env['CONF'][variable]
+        target = env.Dir("config").File(variable.lower() + ".hh")
+        val = env["CONF"][variable]
         if isinstance(val, bool):
             # Force value to 0/1
             val = str(int(val))
@@ -79,4 +80,4 @@ def config_emitter(target, source, env):
 
     config_builder = env.Builder(emitter=config_emitter, action=config_action)
 
-    env.Append(BUILDERS = { 'ConfigFile' : config_builder })
+    env.Append(BUILDERS={"ConfigFile": config_builder})
diff --git a/site_scons/gem5_scons/builders/switching_headers.py b/site_scons/gem5_scons/builders/switching_headers.py
index 881d568cd17..a56ab51c86c 100755
--- a/site_scons/gem5_scons/builders/switching_headers.py
+++ b/site_scons/gem5_scons/builders/switching_headers.py
@@ -51,27 +51,32 @@
 #
 ###################################################
 
+
 def SwitchingHeaders(env):
     def build_switching_header(target, source, env):
         path = str(target[0])
         subdir = str(source[0])
         dp, fp = os.path.split(path)
-        dp = os.path.relpath(os.path.realpath(dp),
-                             os.path.realpath(env['BUILDDIR']))
-        with open(path, 'w') as hdr:
+        dp = os.path.relpath(
+            os.path.realpath(dp), os.path.realpath(env["BUILDDIR"])
+        )
+        with open(path, "w") as hdr:
             print('#include "%s/%s/%s"' % (dp, subdir, fp), file=hdr)
 
-    switching_header_action = MakeAction(build_switching_header,
-                                         Transform('GENERATE'))
+    switching_header_action = MakeAction(
+        build_switching_header, Transform("GENERATE")
+    )
 
-    switching_header_builder = env.Builder(action=switching_header_action,
-                                           source_factory=env.Value,
-                                           single_source=True)
+    switching_header_builder = env.Builder(
+        action=switching_header_action,
+        source_factory=env.Value,
+        single_source=True,
+    )
 
-    env.Append(BUILDERS = { 'SwitchingHeader': switching_header_builder })
+    env.Append(BUILDERS={"SwitchingHeader": switching_header_builder})
 
     def switching_headers(self, headers, source):
         for header in headers:
             self.SwitchingHeader(header, source)
 
-    env.AddMethod(switching_headers, 'SwitchingHeaders')
+    env.AddMethod(switching_headers, "SwitchingHeaders")
diff --git a/site_scons/gem5_scons/configure.py b/site_scons/gem5_scons/configure.py
index 53ee14a103d..55a0d7d3996 100644
--- a/site_scons/gem5_scons/configure.py
+++ b/site_scons/gem5_scons/configure.py
@@ -44,39 +44,41 @@
 import SCons.Script
 import SCons.Util
 
+
 def CheckCxxFlag(context, flag, autoadd=True):
     context.Message("Checking for compiler %s support... " % flag)
-    last_cxxflags = context.env['CXXFLAGS']
+    last_cxxflags = context.env["CXXFLAGS"]
     context.env.Append(CXXFLAGS=[flag])
-    pre_werror = context.env['CXXFLAGS']
-    context.env.Append(CXXFLAGS=['-Werror'])
-    ret = context.TryCompile('// CheckCxxFlag DO NOTHING', '.cc')
-    context.env['CXXFLAGS'] = pre_werror
+    pre_werror = context.env["CXXFLAGS"]
+    context.env.Append(CXXFLAGS=["-Werror"])
+    ret = context.TryCompile("// CheckCxxFlag DO NOTHING", ".cc")
+    context.env["CXXFLAGS"] = pre_werror
     if not (ret and autoadd):
-        context.env['CXXFLAGS'] = last_cxxflags
+        context.env["CXXFLAGS"] = last_cxxflags
     context.Result(ret)
     return ret
 
+
 def CheckLinkFlag(context, flag, autoadd=True, set_for_shared=True):
     context.Message("Checking for linker %s support... " % flag)
-    last_linkflags = context.env['LINKFLAGS']
+    last_linkflags = context.env["LINKFLAGS"]
     context.env.Append(LINKFLAGS=[flag])
-    pre_werror = context.env['LINKFLAGS']
-    context.env.Append(LINKFLAGS=['-Werror'])
-    ret = context.TryLink('int main(int, char *[]) { return 0; }', '.cc')
-    context.env['LINKFLAGS'] = pre_werror
+    pre_werror = context.env["LINKFLAGS"]
+    context.env.Append(LINKFLAGS=["-Werror"])
+    ret = context.TryLink("int main(int, char *[]) { return 0; }", ".cc")
+    context.env["LINKFLAGS"] = pre_werror
     if not (ret and autoadd):
-        context.env['LINKFLAGS'] = last_linkflags
-    if (ret and set_for_shared):
-        assert(autoadd)
+        context.env["LINKFLAGS"] = last_linkflags
+    if ret and set_for_shared:
+        assert autoadd
         context.env.Append(SHLINKFLAGS=[flag])
     context.Result(ret)
     return ret
 
+
 # Add a custom Check function to test for structure members.
 def CheckMember(context, include, decl, member, include_quotes="<>"):
-    context.Message("Checking for member %s in %s..." %
-                    (member, decl))
+    context.Message("Checking for member %s in %s..." % (member, decl))
     text = """
 #include %(header)s
 int main(){
@@ -84,18 +86,21 @@ def CheckMember(context, include, decl, member, include_quotes="<>"):
   (void)test.%(member)s;
   return 0;
 };
-""" % { "header" : include_quotes[0] + include + include_quotes[1],
-        "decl" : decl,
-        "member" : member,
-        }
+""" % {
+        "header": include_quotes[0] + include + include_quotes[1],
+        "decl": decl,
+        "member": member,
+    }
 
     ret = context.TryCompile(text, extension=".cc")
     context.Result(ret)
     return ret
 
+
 def CheckPythonLib(context):
-    context.Message('Checking Python version... ')
-    ret = context.TryRun(r"""
+    context.Message("Checking Python version... ")
+    ret = context.TryRun(
+        r"""
 #include <pybind11/embed.h>
 
 int
@@ -107,21 +112,24 @@ def CheckPythonLib(context):
         "sys.stdout.write('%i.%i.%i' % (vi.major, vi.minor, vi.micro));\n");
     return 0;
 }
-    """, extension=".cc")
+    """,
+        extension=".cc",
+    )
     context.Result(ret[1] if ret[0] == 1 else 0)
     if ret[0] == 0:
         return None
     else:
         return tuple(map(int, ret[1].split(".")))
 
+
 def CheckPkgConfig(context, pkgs, *args):
     if not SCons.Util.is_List(pkgs):
         pkgs = [pkgs]
-    assert(pkgs)
+    assert pkgs
 
     for pkg in pkgs:
-        context.Message('Checking for pkg-config package %s... ' % pkg)
-        ret = context.TryAction('pkg-config %s' % pkg)[0]
+        context.Message("Checking for pkg-config package %s... " % pkg)
+        ret = context.TryAction("pkg-config %s" % pkg)[0]
         if not ret:
             context.Result(ret)
             continue
@@ -129,7 +137,7 @@ def CheckPkgConfig(context, pkgs, *args):
         if len(args) == 0:
             break
 
-        cmd = ' '.join(['pkg-config'] + list(args) + [pkg])
+        cmd = " ".join(["pkg-config"] + list(args) + [pkg])
         try:
             context.env.ParseConfig(cmd)
             ret = 1
@@ -141,20 +149,25 @@ def CheckPkgConfig(context, pkgs, *args):
 
     return ret
 
+
 @contextlib.contextmanager
 def Configure(env, *args, **kwargs):
-    kwargs.setdefault('conf_dir',
-            os.path.join(env['GEM5BUILD'], 'scons_config'))
-    kwargs.setdefault('log_file',
-            os.path.join(env['GEM5BUILD'], 'scons_config.log'))
-    kwargs.setdefault('custom_tests', {})
-    kwargs['custom_tests'].update({
-            'CheckCxxFlag' : CheckCxxFlag,
-            'CheckLinkFlag' : CheckLinkFlag,
-            'CheckMember' : CheckMember,
-            'CheckPkgConfig' : CheckPkgConfig,
-            'CheckPythonLib' : CheckPythonLib,
-    })
+    kwargs.setdefault(
+        "conf_dir", os.path.join(env["GEM5BUILD"], "scons_config")
+    )
+    kwargs.setdefault(
+        "log_file", os.path.join(env["GEM5BUILD"], "scons_config.log")
+    )
+    kwargs.setdefault("custom_tests", {})
+    kwargs["custom_tests"].update(
+        {
+            "CheckCxxFlag": CheckCxxFlag,
+            "CheckLinkFlag": CheckLinkFlag,
+            "CheckMember": CheckMember,
+            "CheckPkgConfig": CheckPkgConfig,
+            "CheckPythonLib": CheckPythonLib,
+        }
+    )
     conf = SCons.Script.Configure(env, *args, **kwargs)
 
     # Recent versions of scons substitute a "Null" object for Configure()
@@ -163,14 +176,17 @@ def Configure(env, *args, **kwargs):
     # breaking all our configuration checks.  We replace it with our own
     # more optimistic null object that returns True instead.
     if not conf:
+
         def NullCheck(*args, **kwargs):
             return True
 
         class NullConf:
             def __init__(self, env):
                 self.env = env
+
             def Finish(self):
                 return self.env
+
             def __getattr__(self, mname):
                 return NullCheck
 
diff --git a/site_scons/gem5_scons/defaults.py b/site_scons/gem5_scons/defaults.py
index 7a245892f4c..2a4e0204c8d 100644
--- a/site_scons/gem5_scons/defaults.py
+++ b/site_scons/gem5_scons/defaults.py
@@ -42,56 +42,76 @@
 
 from gem5_python_paths import extra_python_paths
 
+
 def EnvDefaults(env):
     # export TERM so that clang reports errors in color
-    use_vars = set([ 'AS', 'AR', 'CC', 'CXX', 'HOME', 'LD_LIBRARY_PATH',
-                     'LIBRARY_PATH', 'PATH', 'PKG_CONFIG_PATH', 'PROTOC',
-                     'PYTHONPATH', 'RANLIB', 'TERM', 'PYTHON_CONFIG',
-                     'CCFLAGS_EXTRA', 'GEM5PY_CCFLAGS_EXTRA',
-                     'GEM5PY_LINKFLAGS_EXTRA', 'LINKFLAGS_EXTRA', 'LANG'])
+    use_vars = set(
+        [
+            "AS",
+            "AR",
+            "CC",
+            "CXX",
+            "HOME",
+            "LD_LIBRARY_PATH",
+            "LIBRARY_PATH",
+            "PATH",
+            "PKG_CONFIG_PATH",
+            "PROTOC",
+            "PYTHONPATH",
+            "RANLIB",
+            "TERM",
+            "PYTHON_CONFIG",
+            "CCFLAGS_EXTRA",
+            "GEM5PY_CCFLAGS_EXTRA",
+            "GEM5PY_LINKFLAGS_EXTRA",
+            "LINKFLAGS_EXTRA",
+            "LANG",
+        ]
+    )
 
     use_prefixes = [
-        "ASAN_",           # address sanitizer symbolizer path and settings
-        "CCACHE_",         # ccache (caching compiler wrapper) configuration
-        "CCC_",            # clang static analyzer configuration
-        "DISTCC_",         # distcc (distributed compiler wrapper) config
-        "INCLUDE_SERVER_", # distcc pump server settings
-        "M5",              # M5 configuration (e.g., path to kernels)
-        "NIX_",            # wrapped binaries if using nix package manager
-        ]
+        "ASAN_",  # address sanitizer symbolizer path and settings
+        "CCACHE_",  # ccache (caching compiler wrapper) configuration
+        "CCC_",  # clang static analyzer configuration
+        "DISTCC_",  # distcc (distributed compiler wrapper) config
+        "INCLUDE_SERVER_",  # distcc pump server settings
+        "M5",  # M5 configuration (e.g., path to kernels)
+        "NIX_",  # wrapped binaries if using nix package manager
+    ]
 
-    for key,val in sorted(os.environ.items()):
-        if key in use_vars or \
-                any([key.startswith(prefix) for prefix in use_prefixes]):
-            env['ENV'][key] = val
+    for key, val in sorted(os.environ.items()):
+        if key in use_vars or any(
+            [key.startswith(prefix) for prefix in use_prefixes]
+        ):
+            env["ENV"][key] = val
 
     # These variables from the environment override/become SCons variables,
     # with a default if they weren't in the host environment.
     var_overrides = {
-        'CC': env['CC'],
-        'CXX': env['CXX'],
-        'PROTOC': 'protoc',
-        'PYTHON_CONFIG': [ 'python3-config', 'python-config' ],
-        'CCFLAGS_EXTRA': '',
-        'GEM5PY_CCFLAGS_EXTRA': '',
-        'GEM5PY_LINKFLAGS_EXTRA': '',
-        'LINKFLAGS_EXTRA': '',
+        "CC": env["CC"],
+        "CXX": env["CXX"],
+        "PROTOC": "protoc",
+        "PYTHON_CONFIG": ["python3-config", "python-config"],
+        "CCFLAGS_EXTRA": "",
+        "GEM5PY_CCFLAGS_EXTRA": "",
+        "GEM5PY_LINKFLAGS_EXTRA": "",
+        "LINKFLAGS_EXTRA": "",
     }
-    for key,default in var_overrides.items():
-        env[key] = env['ENV'].get(key, default)
+    for key, default in var_overrides.items():
+        env[key] = env["ENV"].get(key, default)
 
     # Tell scons to avoid implicit command dependencies to avoid issues
     # with the param wrappes being compiled twice (see
     # https://github.com/SCons/scons/issues/2811
-    env['IMPLICIT_COMMAND_DEPENDENCIES'] = 0
-    env.Decider('MD5-timestamp')
+    env["IMPLICIT_COMMAND_DEPENDENCIES"] = 0
+    env.Decider("MD5-timestamp")
 
     # add useful python code PYTHONPATH so it can be used by subprocesses
     # as well
-    env.AppendENVPath('PYTHONPATH', extra_python_paths)
+    env.AppendENVPath("PYTHONPATH", extra_python_paths)
 
     # Default duplicate option is to use hard links, but this messes up
     # when you use emacs to edit a file in the target dir, as emacs moves
     # file to file~ then copies to file, breaking the link.  Symbolic
     # (soft) links work better.
-    env.SetOption('duplicate', 'soft-copy')
+    env.SetOption("duplicate", "soft-copy")
diff --git a/site_scons/gem5_scons/sources.py b/site_scons/gem5_scons/sources.py
index 85b0b4e453a..548e9386eaf 100644
--- a/site_scons/gem5_scons/sources.py
+++ b/site_scons/gem5_scons/sources.py
@@ -47,8 +47,9 @@
 # When specifying a source file of some type, a set of tags can be
 # specified for that file.
 
+
 def tag_implies(env, tag, tag_list):
-    '''
+    """
     Associates a tag X to a list of tags which are implied by X.
 
     For example, assume:
@@ -72,10 +73,10 @@ def tag_implies(env, tag, tag_list):
 
     So that any use of a tag will automatically include its transitive tags
     after being resolved.
-    '''
+    """
 
     env.SetDefault(_tag_implies={})
-    implications = env['_tag_implies']
+    implications = env["_tag_implies"]
 
     if isinstance(tag_list, str):
         tag_list = frozenset([tag_list])
@@ -95,21 +96,23 @@ def tag_implies(env, tag, tag_list):
 
     # Check if another tag depends on this tag. If so, add this tag's
     # implications to that tag.
-    for t,implied in implications.items():
+    for t, implied in implications.items():
         if tag in implied:
             implications[t] |= implications[tag]
 
+
 def TagImpliesTool(env):
-    env.AddMethod(tag_implies, 'TagImplies')
+    env.AddMethod(tag_implies, "TagImplies")
+
 
 def resolve_tags(env, tags):
-    '''
+    """
     Returns the complete set of tags implied (dependencies) by the
     supplied tags.
-    '''
+    """
 
     implications = env.SetDefault(_tag_implies={})
-    implications = env['_tag_implies']
+    implications = env["_tag_implies"]
 
     if isinstance(tags, str):
         tags = frozenset([tags])
@@ -122,53 +125,71 @@ def resolve_tags(env, tags):
             tags |= implications[tag]
     return tags
 
+
 class SourceFilter(object):
     factories = {}
+
     def __init__(self, predicate):
         self.predicate = predicate
 
     def __or__(self, other):
-        return SourceFilter(lambda env, tags: self.predicate(env, tags) or
-                                              other.predicate(env, tags))
+        return SourceFilter(
+            lambda env, tags: self.predicate(env, tags)
+            or other.predicate(env, tags)
+        )
 
     def __and__(self, other):
-        return SourceFilter(lambda env, tags: self.predicate(env, tags) and
-                                              other.predicate(env, tags))
+        return SourceFilter(
+            lambda env, tags: self.predicate(env, tags)
+            and other.predicate(env, tags)
+        )
+
 
 def with_any_tags(*tags):
-    '''Return a list of sources with any of the supplied tags.'''
-    return SourceFilter(lambda env, stags: \
-        len(resolve_tags(env, tags) & stags) > 0)
+    """Return a list of sources with any of the supplied tags."""
+    return SourceFilter(
+        lambda env, stags: len(resolve_tags(env, tags) & stags) > 0
+    )
+
 
 def with_all_tags(*tags):
-    '''Return a list of sources with all of the supplied tags.'''
+    """Return a list of sources with all of the supplied tags."""
     return SourceFilter(lambda env, stags: resolve_tags(env, tags) <= stags)
 
+
 def with_tag(tag):
-    '''Return a list of sources with the supplied tag.'''
+    """Return a list of sources with the supplied tag."""
     return with_any_tags(*[tag])
 
+
 def without_tags(*tags):
-    '''Return a list of sources without any of the supplied tags.'''
-    return SourceFilter(lambda env, stags: \
-        len(resolve_tags(env, tags) & stags) == 0)
+    """Return a list of sources without any of the supplied tags."""
+    return SourceFilter(
+        lambda env, stags: len(resolve_tags(env, tags) & stags) == 0
+    )
+
 
 def without_tag(tag):
-    '''Return a list of sources without the supplied tag.'''
+    """Return a list of sources without the supplied tag."""
     return without_tags(*[tag])
 
-SourceFilter.factories.update({
-    'with_any_tags': with_any_tags,
-    'with_all_tags': with_all_tags,
-    'with_tag': with_tag,
-    'without_tags': without_tags,
-    'without_tag': without_tag,
-})
+
+SourceFilter.factories.update(
+    {
+        "with_any_tags": with_any_tags,
+        "with_all_tags": with_all_tags,
+        "with_tag": with_tag,
+        "without_tags": without_tags,
+        "without_tag": without_tag,
+    }
+)
+
 
 class SourceList(list):
     def apply_filter(self, env, f):
         def match(source):
             return f.predicate(env, resolve_tags(env, source.tags))
+
         return SourceList(filter(match, self))
 
     def __getattr__(self, name):
@@ -179,33 +200,38 @@ def __getattr__(self, name):
         @functools.wraps(func)
         def wrapper(env, *args, **kwargs):
             return self.apply_filter(env, func(*args, **kwargs))
+
         return wrapper
 
+
 class SourceMeta(type):
-    '''Meta class for source files that keeps track of all files of a
-    particular type.'''
+    """Meta class for source files that keeps track of all files of a
+    particular type."""
+
     def __init__(cls, name, bases, dict):
         super(SourceMeta, cls).__init__(name, bases, dict)
         cls.all = SourceList()
 
+
 class SourceItem(object, metaclass=SourceMeta):
-    '''Base object that encapsulates the notion of a source component for
+    """Base object that encapsulates the notion of a source component for
     gem5. This specifies a set of tags which help group components into groups
-    based on arbitrary properties.'''
+    based on arbitrary properties."""
+
     def __init__(self, source, tags=None, add_tags=None, append=None):
         self.source = source
 
         if tags is None:
-            tags='gem5 lib'
+            tags = "gem5 lib"
         if isinstance(tags, str):
-            tags = { tags }
+            tags = {tags}
         if not isinstance(tags, set):
             tags = set(tags)
         self.tags = tags.copy()
 
         if add_tags:
             if isinstance(add_tags, str):
-                add_tags = { add_tags }
+                add_tags = {add_tags}
             if not isinstance(add_tags, set):
                 add_tags = set(add_tags)
             self.tags |= add_tags
@@ -216,10 +242,11 @@ def __init__(self, source, tags=None, add_tags=None, append=None):
             if issubclass(base, SourceItem):
                 base.all.append(self)
 
+
 class SourceFile(SourceItem):
-    '''Base object that encapsulates the notion of a source file.
+    """Base object that encapsulates the notion of a source file.
     This includes, the source node, target node, various manipulations
-    of those.'''
+    of those."""
 
     def __init__(self, source, tags=None, add_tags=None, append=None):
         super().__init__(source, tags=tags, add_tags=add_tags, append=append)
@@ -243,6 +270,15 @@ def shared(self, env):
         return env.SharedObject(self.tnode)
 
 
-__all__ = ['TagImpliesTool', 'SourceFilter', 'SourceList', 'SourceFile',
-           'SourceItem', 'with_any_tags', 'with_all_tags', 'with_tag',
-           'without_tags', 'without_tag']
+__all__ = [
+    "TagImpliesTool",
+    "SourceFilter",
+    "SourceList",
+    "SourceFile",
+    "SourceItem",
+    "with_any_tags",
+    "with_all_tags",
+    "with_tag",
+    "without_tags",
+    "without_tag",
+]
diff --git a/site_scons/gem5_scons/util.py b/site_scons/gem5_scons/util.py
index b62cc0164e0..045fd4ef324 100644
--- a/site_scons/gem5_scons/util.py
+++ b/site_scons/gem5_scons/util.py
@@ -46,12 +46,15 @@
 
 import m5.util.terminal
 
+
 def ignore_style():
     """Determine whether we should ignore style checks"""
-    return SCons.Script.GetOption('ignore_style') or not sys.stdin.isatty()
+    return SCons.Script.GetOption("ignore_style") or not sys.stdin.isatty()
+
 
 def get_termcap():
-    return m5.util.terminal.get_termcap(SCons.Script.GetOption('use_colors'))
+    return m5.util.terminal.get_termcap(SCons.Script.GetOption("use_colors"))
+
 
 def readCommand(cmd, **kwargs):
     """
@@ -68,13 +71,13 @@ def readCommand(cmd, **kwargs):
     if isinstance(cmd, str):
         cmd = cmd.split()
 
-    no_exception = 'exception' in kwargs
-    exception = kwargs.pop('exception', None)
+    no_exception = "exception" in kwargs
+    exception = kwargs.pop("exception", None)
 
-    kwargs.setdefault('shell', False)
-    kwargs.setdefault('stdout', PIPE)
-    kwargs.setdefault('stderr', STDOUT)
-    kwargs.setdefault('close_fds', True)
+    kwargs.setdefault("shell", False)
+    kwargs.setdefault("stdout", PIPE)
+    kwargs.setdefault("stderr", STDOUT)
+    kwargs.setdefault("close_fds", True)
     try:
         subp = Popen(cmd, **kwargs)
     except Exception as e:
@@ -82,20 +85,23 @@ def readCommand(cmd, **kwargs):
             return -1, exception
         raise
 
-    output = subp.communicate()[0].decode('utf-8')
+    output = subp.communicate()[0].decode("utf-8")
     return output
 
+
 def compareVersions(v1, v2):
     """helper function: compare arrays or strings of version numbers.
     E.g., compare_version((1,3,25), (1,4,1)')
     returns -1, 0, 1 if v1 is <, ==, > v2
     """
+
     def make_version_list(v):
-        if isinstance(v, (list,tuple)):
+        if isinstance(v, (list, tuple)):
             return v
         elif isinstance(v, str):
-            return list(map(lambda x: int(re.match('\d+', x).group()),
-                            v.split('.')))
+            return list(
+                map(lambda x: int(re.match("\d+", x).group()), v.split("."))
+            )
         else:
             raise TypeError()
 
@@ -104,8 +110,10 @@ def make_version_list(v):
 
     # Compare corresponding elements of lists
     # The shorter list is filled with 0 till the lists have the same length
-    for n1,n2 in itertools.zip_longest(v1, v2, fillvalue=0):
-        if n1 < n2: return -1
-        if n1 > n2: return  1
+    for n1, n2 in itertools.zip_longest(v1, v2, fillvalue=0):
+        if n1 < n2:
+            return -1
+        if n1 > n2:
+            return 1
 
     return 0
diff --git a/site_scons/site_init.py b/site_scons/site_init.py
index 5eeb29012a5..480dfa74da5 100644
--- a/site_scons/site_init.py
+++ b/site_scons/site_init.py
@@ -44,10 +44,12 @@
 try:
     EnsureSConsVersion(3, 0, 0)
 except SystemExit as e:
-    print("""
+    print(
+        """
 For more details, see:
     http://gem5.org/documentation/general_docs/building
-""")
+"""
+    )
     raise
 
 
@@ -55,7 +57,8 @@
 try:
     EnsurePythonVersion(3, 6)
 except SystemExit as e:
-    print("""\033[93m
+    print(
+        """\033[93m
 Python 3 is now required.
 
 The following are steps to compile gem5 in Python 3 environment,
@@ -81,7 +84,8 @@
 
 (Optional) For convenience reasons, you can set up an alias for the Python3 \
 scons phrase in your environment. \033[0m
-""")
+"""
+    )
     raise
 
 from gem5_python_paths import extra_python_paths
diff --git a/site_scons/site_tools/git.py b/site_scons/site_tools/git.py
index fe083b75668..73007311bed 100644
--- a/site_scons/site_tools/git.py
+++ b/site_scons/site_tools/git.py
@@ -50,15 +50,20 @@
 This script will now install the hook in your .git/hooks/ directory.
 Press enter to continue, or ctrl-c to abort: """
 
+
 def install_style_hooks(env):
     try:
-        gitdir = env.Dir(gem5_scons.util.readCommand(
-            ["git", "rev-parse", "--git-dir"]).strip("\n"))
+        gitdir = env.Dir(
+            gem5_scons.util.readCommand(
+                ["git", "rev-parse", "--git-dir"]
+            ).strip("\n")
+        )
     except Exception as e:
         print("Warning: Failed to find git repo directory: %s" % e)
         return
 
     git_hooks = gitdir.Dir("hooks")
+
     def hook_exists(hook_name):
         hook = git_hooks.File(hook_name)
         return hook.exists()
@@ -66,8 +71,9 @@ def hook_exists(hook_name):
     def hook_install(hook_name, script):
         hook = git_hooks.File(hook_name)
         if hook.exists():
-            print("Warning: Can't install %s, hook already exists." %
-                    hook_name)
+            print(
+                "Warning: Can't install %s, hook already exists." % hook_name
+            )
             return
 
         if hook.islink():
@@ -78,15 +84,17 @@ def hook_install(hook_name, script):
             os.mkdir(git_hooks.get_abspath())
             git_hooks.clear()
 
-        abs_symlink_hooks = git_hooks.islink() and \
-            os.path.isabs(os.readlink(git_hooks.get_abspath()))
+        abs_symlink_hooks = git_hooks.islink() and os.path.isabs(
+            os.readlink(git_hooks.get_abspath())
+        )
 
         # Use a relative symlink if the hooks live in the source directory,
         # and the hooks directory is not a symlink to an absolute path.
         if hook.is_under(env.Dir("#")) and not abs_symlink_hooks:
             script_path = os.path.relpath(
                 os.path.realpath(script.get_abspath()),
-                os.path.realpath(hook.Dir(".").get_abspath()))
+                os.path.realpath(hook.Dir(".").get_abspath()),
+            )
         else:
             script_path = script.get_abspath()
 
@@ -99,8 +107,8 @@ def hook_install(hook_name, script):
     if hook_exists("pre-commit") and hook_exists("commit-msg"):
         return
 
-    print(git_style_message, end=' ')
-    if SCons.Script.GetOption('install_hooks'):
+    print(git_style_message, end=" ")
+    if SCons.Script.GetOption("install_hooks"):
         print("Installing revision control hooks automatically.")
     else:
         try:
@@ -115,9 +123,11 @@ def hook_install(hook_name, script):
     hook_install("pre-commit", git_style_script)
     hook_install("commit-msg", git_msg_script)
 
+
 def generate(env):
     if exists(env) and not gem5_scons.util.ignore_style():
         install_style_hooks(env)
 
+
 def exists(env):
-    return env.Entry('#.git').exists()
+    return env.Entry("#.git").exists()
diff --git a/src/arch/arm/fastmodel/GIC/FastModelGIC.py b/src/arch/arm/fastmodel/GIC/FastModelGIC.py
index 7d8bbb15ff4..1ad5a979cd4 100644
--- a/src/arch/arm/fastmodel/GIC/FastModelGIC.py
+++ b/src/arch/arm/fastmodel/GIC/FastModelGIC.py
@@ -865,7 +865,7 @@ def get_redist_bases(self):
         return [int(r.split("=")[1], 16) for r in redists]
 
     def get_addr_ranges(self):
-        """ Return address ranges that should be served by this GIC """
+        """Return address ranges that should be served by this GIC"""
         sc_gic = self.sc_gic
         gic_frame_size = 0x10000
         # Add range of distributor
diff --git a/src/arch/arm/fastmodel/arm_fast_model.py b/src/arch/arm/fastmodel/arm_fast_model.py
index 033f56b6b87..11004177c66 100644
--- a/src/arch/arm/fastmodel/arm_fast_model.py
+++ b/src/arch/arm/fastmodel/arm_fast_model.py
@@ -31,9 +31,9 @@
 
 def set_armlmd_license_file(force=False):
     """Set the ARMLMD_LICENSE_FILE environment variable. If "force" is
-       False, then it will only be set if it wasn't already set in the
-       environment. The value it's set to is the one gem5 was built with.
-       """
+    False, then it will only be set if it wasn't already set in the
+    environment. The value it's set to is the one gem5 was built with.
+    """
     key = "ARMLMD_LICENSE_FILE"
     license_file = buildEnv[key]
     if force or key not in os.environ:
diff --git a/src/arch/arm/isa/copyright.txt b/src/arch/arm/isa/copyright.txt
index 899a8df8b3c..75647747fda 100644
--- a/src/arch/arm/isa/copyright.txt
+++ b/src/arch/arm/isa/copyright.txt
@@ -35,4 +35,3 @@
 // ARISING OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE, EVEN
 // IF IT HAS BEEN OR IS HEREAFTER ADVISED OF THE POSSIBILITY OF SUCH
 // DAMAGES.
-
diff --git a/src/arch/arm/isa/decoder/aarch64.isa b/src/arch/arm/isa/decoder/aarch64.isa
index f2f09648294..34a17f23714 100644
--- a/src/arch/arm/isa/decoder/aarch64.isa
+++ b/src/arch/arm/isa/decoder/aarch64.isa
@@ -43,4 +43,3 @@
 
 
 Aarch64::aarch64();
-
diff --git a/src/arch/arm/isa/decoder/arm.isa b/src/arch/arm/isa/decoder/arm.isa
index 0349b398b43..70802a072d4 100644
--- a/src/arch/arm/isa/decoder/arm.isa
+++ b/src/arch/arm/isa/decoder/arm.isa
@@ -132,4 +132,3 @@ format DataOp {
 }
 }
 }
-
diff --git a/src/arch/arm/isa/formats/breakpoint.isa b/src/arch/arm/isa/formats/breakpoint.isa
index d94c943bce3..d8e43f36504 100644
--- a/src/arch/arm/isa/formats/breakpoint.isa
+++ b/src/arch/arm/isa/formats/breakpoint.isa
@@ -56,4 +56,3 @@ def format ArmBkptHlt() {{
     }
     '''
 }};
-
diff --git a/src/arch/arm/isa/formats/mem.isa b/src/arch/arm/isa/formats/mem.isa
index aecd378613f..235bcfae25a 100644
--- a/src/arch/arm/isa/formats/mem.isa
+++ b/src/arch/arm/isa/formats/mem.isa
@@ -1154,4 +1154,3 @@ def format Thumb16MemLit() {{
     }
     ''' % loadImmClassName(False, True, False)
 }};
-
diff --git a/src/arch/arm/isa/formats/pred.isa b/src/arch/arm/isa/formats/pred.isa
index 689a71d3405..e971ccf603a 100644
--- a/src/arch/arm/isa/formats/pred.isa
+++ b/src/arch/arm/isa/formats/pred.isa
@@ -202,4 +202,3 @@ def format PredImmOp(code, *opt_flags) {{
     decode_block = BasicDecode.subst(iop)
     exec_output = PredOpExecute.subst(iop)
 }};
-
diff --git a/src/arch/arm/isa/insts/crypto64.isa b/src/arch/arm/isa/insts/crypto64.isa
index 35ea4fef6ef..1ae580fa970 100644
--- a/src/arch/arm/isa/insts/crypto64.isa
+++ b/src/arch/arm/isa/insts/crypto64.isa
@@ -167,4 +167,3 @@ let {{
     cryptoRegRegRegInst("sha256su1", "SHA256SU164", "SimdShaSigma3Op",
                         sha2_enabled, sha256_su1Code)
 }};
-
diff --git a/src/arch/arm/isa/insts/mem.isa b/src/arch/arm/isa/insts/mem.isa
index a7add8a6d62..5c9273851e0 100644
--- a/src/arch/arm/isa/insts/mem.isa
+++ b/src/arch/arm/isa/insts/mem.isa
@@ -229,4 +229,3 @@ let {{
             raise Exception("Illegal combination of post and writeback")
         return base
 }};
-
diff --git a/src/arch/arm/isa/templates/branch.isa b/src/arch/arm/isa/templates/branch.isa
index b886a974024..2ba16f1d068 100644
--- a/src/arch/arm/isa/templates/branch.isa
+++ b/src/arch/arm/isa/templates/branch.isa
@@ -186,5 +186,3 @@ def template BranchTarget {{
         return std::unique_ptr<PCStateBase>{pc_ptr};
     }
 }};
-
-
diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa
index 35af77577f3..41b1586030a 100644
--- a/src/arch/arm/isa/templates/mem.isa
+++ b/src/arch/arm/isa/templates/mem.isa
@@ -1288,4 +1288,3 @@ def template LoadImmConstructor {{
 #endif
     }
 }};
-
diff --git a/src/arch/isa_parser/isa_parser.py b/src/arch/isa_parser/isa_parser.py
index 859a3203819..62f33828a12 100755
--- a/src/arch/isa_parser/isa_parser.py
+++ b/src/arch/isa_parser/isa_parser.py
@@ -112,12 +112,11 @@ def subst(self, d):
 
             operands = SubOperandList(self.parser, compositeCode, d.operands)
 
-            myDict["reg_idx_arr_decl"] = (
-                "RegId srcRegIdxArr[%d]; RegId destRegIdxArr[%d]"
-                % (
-                    d.operands.numSrcRegs + d.srcRegIdxPadding,
-                    d.operands.numDestRegs + d.destRegIdxPadding,
-                )
+            myDict[
+                "reg_idx_arr_decl"
+            ] = "RegId srcRegIdxArr[%d]; RegId destRegIdxArr[%d]" % (
+                d.operands.numSrcRegs + d.srcRegIdxPadding,
+                d.operands.numDestRegs + d.destRegIdxPadding,
             )
 
             # The reinterpret casts are largely because an array with a known
@@ -960,15 +959,15 @@ def p_defs_and_outputs_1(self, t):
     # They are all processed as they are seen.
     def p_def_or_output(self, t):
         """def_or_output : name_decl
-                         | def_format
-                         | def_bitfield
-                         | def_bitfield_struct
-                         | def_template
-                         | def_operand_types
-                         | def_operands
-                         | output
-                         | global_let
-                         | split"""
+        | def_format
+        | def_bitfield
+        | def_bitfield_struct
+        | def_template
+        | def_operand_types
+        | def_operands
+        | output
+        | global_let
+        | split"""
 
     # Utility function used by both invocations of splitting - explicit
     # 'split' keyword and split() function inside "let {{ }};" blocks.
@@ -992,8 +991,8 @@ def p_split(self, t):
 
     def p_output_type(self, t):
         """output_type : DECODER
-                       | HEADER
-                       | EXEC"""
+        | HEADER
+        | EXEC"""
         t[0] = t[1]
 
     # ISA name declaration looks like "namespace <foo>;"
@@ -1175,7 +1174,7 @@ def p_param_list_0(self, t):
 
     def p_param_list_1(self, t):
         """param_list : positional_param_list
-                      | nonpositional_param_list"""
+        | nonpositional_param_list"""
         t[0] = t[1]
 
     def p_positional_param_list_0(self, t):
@@ -1196,7 +1195,7 @@ def p_nonpositional_param_list_0(self, t):
 
     def p_nonpositional_param_list_1(self, t):
         """nonpositional_param_list : keyword_param_list
-                                    | excess_args_param"""
+        | excess_args_param"""
         t[0] = t[1]
 
     def p_keyword_param_list_0(self, t):
@@ -1360,7 +1359,7 @@ def p_case_list_0(self, t):
         t[0] = ["default:"]
 
     def prep_int_lit_case_label(self, lit):
-        if lit >= 2 ** 32:
+        if lit >= 2**32:
             return "case %#xULL: " % lit
         else:
             return "case %#x: " % lit
@@ -1468,9 +1467,9 @@ def p_keyword_arg(self, t):
     #
     def p_expr_0(self, t):
         """expr : ID
-                | INTLIT
-                | STRLIT
-                | CODELIT"""
+        | INTLIT
+        | STRLIT
+        | CODELIT"""
         t[0] = t[1]
 
     def p_expr_1(self, t):
diff --git a/src/arch/micro_asm.py b/src/arch/micro_asm.py
index ffa16609278..5b4378881ec 100644
--- a/src/arch/micro_asm.py
+++ b/src/arch/micro_asm.py
@@ -375,7 +375,7 @@ def p_file(t):
 
 
 def p_opt_rom_or_macros_0(t):
-    "opt_rom_or_macros : "
+    "opt_rom_or_macros :"
 
 
 def p_opt_rom_or_macros_1(t):
@@ -392,7 +392,7 @@ def p_rom_or_macros_1(t):
 
 def p_rom_or_macro_0(t):
     """rom_or_macro : rom_block
-                    | macroop_def"""
+    | macroop_def"""
 
 
 # Defines a section of microcode that should go in the current ROM
@@ -466,20 +466,20 @@ def p_statement(t):
 # A statement can be a microop or an assembler directive
 def p_content_of_statement_0(t):
     """content_of_statement : microop
-                            | directive"""
+    | directive"""
     t[0] = t[1]
 
 
 # Ignore empty statements
 def p_content_of_statement_1(t):
-    "content_of_statement : "
+    "content_of_statement :"
     pass
 
 
 # Statements are ended by newlines or a semi colon
 def p_end_of_statement(t):
     """end_of_statement : NEWLINE
-                        | SEMI"""
+    | SEMI"""
     pass
 
 
diff --git a/src/arch/mips/isa/base.isa b/src/arch/mips/isa/base.isa
index 8e9b50be040..a06debcce85 100644
--- a/src/arch/mips/isa/base.isa
+++ b/src/arch/mips/isa/base.isa
@@ -145,4 +145,3 @@ output decoder {{
     }
 
 }};
-
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index fcb60b3d472..db2bfa4a321 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -2545,5 +2545,3 @@ decode OPCODE_HI default Unknown::unknown() {
         0x6: CP2Unimpl::sdc2();
     }
 }
-
-
diff --git a/src/arch/mips/isa/formats/branch.isa b/src/arch/mips/isa/formats/branch.isa
index 96841cfa4a1..1b7c1057b6d 100644
--- a/src/arch/mips/isa/formats/branch.isa
+++ b/src/arch/mips/isa/formats/branch.isa
@@ -326,7 +326,3 @@ def format Jump(code, *opt_flags) {{
     decode_block = BasicDecode.subst(iop)
     exec_output = BasicExecute.subst(iop)
 }};
-
-
-
-
diff --git a/src/arch/mips/isa/formats/control.isa b/src/arch/mips/isa/formats/control.isa
index 45bbd76b6a6..8bad976133e 100644
--- a/src/arch/mips/isa/formats/control.isa
+++ b/src/arch/mips/isa/formats/control.isa
@@ -241,5 +241,3 @@ def format CP1Control(code, *flags) {{
     decode_block = BasicDecode.subst(iop)
     exec_output = CP1Execute.subst(iop)
 }};
-
-
diff --git a/src/arch/mips/isa/formats/dsp.isa b/src/arch/mips/isa/formats/dsp.isa
index 8233d43d423..431cc9831be 100644
--- a/src/arch/mips/isa/formats/dsp.isa
+++ b/src/arch/mips/isa/formats/dsp.isa
@@ -208,6 +208,3 @@ def format DspHiLoOp(code, *opt_flags) {{
     exec_output = DspHiLoExecute.subst(iop)
 
 }};
-
-
-
diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa
index 877a2b14ac3..ccf446233c4 100644
--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -363,4 +363,3 @@ def format FloatPSCompareOp(cond_code1, cond_code2, *flags) {{
     decode_block = BasicDecode.subst(iop)
     exec_output = BasicExecute.subst(iop)
 }};
-
diff --git a/src/arch/mips/isa/formats/noop.isa b/src/arch/mips/isa/formats/noop.isa
index 8ca30b9c054..917148b6bc0 100644
--- a/src/arch/mips/isa/formats/noop.isa
+++ b/src/arch/mips/isa/formats/noop.isa
@@ -134,4 +134,3 @@ def format BasicOperateWithNopCheck(code, *opt_args) {{
 def format Nop() {{
         decode_block = 'return new Nop(\"\",machInst);\n'
 }};
-
diff --git a/src/arch/mips/isa/formats/unimp.isa b/src/arch/mips/isa/formats/unimp.isa
index 5a40a6cd392..6b4aaba0228 100644
--- a/src/arch/mips/isa/formats/unimp.isa
+++ b/src/arch/mips/isa/formats/unimp.isa
@@ -273,4 +273,3 @@ def format WarnUnimpl() {{
     iop = InstObjParams(name, 'WarnUnimplemented')
     decode_block = BasicDecodeWithMnemonic.subst(iop)
 }};
-
diff --git a/src/arch/mips/isa/formats/unknown.isa b/src/arch/mips/isa/formats/unknown.isa
index fead3c44949..c243ecdab30 100644
--- a/src/arch/mips/isa/formats/unknown.isa
+++ b/src/arch/mips/isa/formats/unknown.isa
@@ -77,4 +77,3 @@ output exec {{
 def format Unknown() {{
     decode_block = 'return new Unknown(machInst);\n'
 }};
-
diff --git a/src/arch/power/isa/formats/unimp.isa b/src/arch/power/isa/formats/unimp.isa
index 3f709e501eb..e7d1d06642e 100644
--- a/src/arch/power/isa/formats/unimp.isa
+++ b/src/arch/power/isa/formats/unimp.isa
@@ -141,4 +141,3 @@ def format WarnUnimpl() {{
     iop = InstObjParams(name, 'WarnUnimplemented')
     decode_block = BasicDecodeWithMnemonic.subst(iop)
 }};
-
diff --git a/src/arch/power/isa/formats/unknown.isa b/src/arch/power/isa/formats/unknown.isa
index f68aff8efb9..0c879aa1584 100644
--- a/src/arch/power/isa/formats/unknown.isa
+++ b/src/arch/power/isa/formats/unknown.isa
@@ -82,4 +82,3 @@ output exec {{
 def format Unknown() {{
     decode_block = 'return new Unknown(machInst);\n'
 }};
-
diff --git a/src/arch/power/isa/formats/util.isa b/src/arch/power/isa/formats/util.isa
index 1a8d34e6314..8c8fa9ce037 100644
--- a/src/arch/power/isa/formats/util.isa
+++ b/src/arch/power/isa/formats/util.isa
@@ -224,5 +224,3 @@ output decoder {{
     }
 
 }};
-
-
diff --git a/src/arch/riscv/gdb-xml/riscv-64bit-cpu.xml b/src/arch/riscv/gdb-xml/riscv-64bit-cpu.xml
index ca59ac307df..7de083d25c4 100644
--- a/src/arch/riscv/gdb-xml/riscv-64bit-cpu.xml
+++ b/src/arch/riscv/gdb-xml/riscv-64bit-cpu.xml
@@ -45,4 +45,4 @@
   <reg name="t5" bitsize="64" type="int"/>
   <reg name="t6" bitsize="64" type="int"/>
   <reg name="pc" bitsize="64" type="code_ptr"/>
-</feature>
\ No newline at end of file
+</feature>
diff --git a/src/arch/riscv/gdb-xml/riscv-64bit-csr.xml b/src/arch/riscv/gdb-xml/riscv-64bit-csr.xml
index 6b2ae790fe9..3c9d2e90f4d 100644
--- a/src/arch/riscv/gdb-xml/riscv-64bit-csr.xml
+++ b/src/arch/riscv/gdb-xml/riscv-64bit-csr.xml
@@ -245,4 +245,4 @@
   <reg name="mucounteren" bitsize="64"/>
   <reg name="mscounteren" bitsize="64"/>
   <reg name="mhcounteren" bitsize="64"/> -->
-</feature>
\ No newline at end of file
+</feature>
diff --git a/src/arch/riscv/gdb-xml/riscv-64bit-fpu.xml b/src/arch/riscv/gdb-xml/riscv-64bit-fpu.xml
index 7b68ba4d601..9661b0e0047 100644
--- a/src/arch/riscv/gdb-xml/riscv-64bit-fpu.xml
+++ b/src/arch/riscv/gdb-xml/riscv-64bit-fpu.xml
@@ -55,4 +55,4 @@
   <reg name="frm" bitsize="32" type="int" regnum="67"/>
   <reg name="fcsr" bitsize="32" type="int" regnum="68"/>
   <reg name="placeholder" bitsize="32" type="int" regnum="69"/>
-</feature>
\ No newline at end of file
+</feature>
diff --git a/src/arch/riscv/gdb-xml/riscv.xml b/src/arch/riscv/gdb-xml/riscv.xml
index cae8bf7abc2..e39ae98e827 100644
--- a/src/arch/riscv/gdb-xml/riscv.xml
+++ b/src/arch/riscv/gdb-xml/riscv.xml
@@ -10,4 +10,4 @@
   <xi:include href="riscv-64bit-cpu.xml"/>
   <xi:include href="riscv-64bit-fpu.xml"/>
   <xi:include href="riscv-64bit-csr.xml"/>
-</target>
\ No newline at end of file
+</target>
diff --git a/src/arch/riscv/isa/bitfields.isa b/src/arch/riscv/isa/bitfields.isa
index 38764484770..60636c68f81 100644
--- a/src/arch/riscv/isa/bitfields.isa
+++ b/src/arch/riscv/isa/bitfields.isa
@@ -128,4 +128,4 @@ def bitfield M5FUNC <31:25>;
 def bitfield BIT24         <24>;
 def bitfield RNUM       <23:20>;
 def bitfield KFUNCT5    <29:25>;
-def bitfield BS         <31:30>;
\ No newline at end of file
+def bitfield BS         <31:30>;
diff --git a/src/arch/sparc/isa/base.isa b/src/arch/sparc/isa/base.isa
index 8b118f4f0c5..d250266decf 100644
--- a/src/arch/sparc/isa/base.isa
+++ b/src/arch/sparc/isa/base.isa
@@ -132,5 +132,3 @@ output exec {{
         }
     }
 }};
-
-
diff --git a/src/arch/sparc/isa/formats/branch.isa b/src/arch/sparc/isa/formats/branch.isa
index d1107e64bdc..c1d9d6a8f45 100644
--- a/src/arch/sparc/isa/formats/branch.isa
+++ b/src/arch/sparc/isa/formats/branch.isa
@@ -187,4 +187,3 @@ def format BranchSplit(code=default_branch_code,
          decode_block) = doUncondBranch(name, Name,
              "BranchSplit", code, annul_code, opt_flags)
 }};
-
diff --git a/src/arch/sparc/isa/formats/formats.isa b/src/arch/sparc/isa/formats/formats.isa
index 6d2b0d74940..c7aa6fabeef 100644
--- a/src/arch/sparc/isa/formats/formats.isa
+++ b/src/arch/sparc/isa/formats/formats.isa
@@ -51,4 +51,3 @@
 
 // Include the branch format
 ##include "branch.isa"
-
diff --git a/src/arch/sparc/isa/formats/integerop.isa b/src/arch/sparc/isa/formats/integerop.isa
index aa67b7c637f..39326e8ff49 100644
--- a/src/arch/sparc/isa/formats/integerop.isa
+++ b/src/arch/sparc/isa/formats/integerop.isa
@@ -162,4 +162,3 @@ def format SetHi(code, *opt_flags) {{
     exec_output = IntOpExecute.subst(iop)
     decode_block = SetHiDecode.subst(iop)
 }};
-
diff --git a/src/arch/sparc/isa/formats/mem/basicmem.isa b/src/arch/sparc/isa/formats/mem/basicmem.isa
index 83377ae8fe5..14758d73cb5 100644
--- a/src/arch/sparc/isa/formats/mem/basicmem.isa
+++ b/src/arch/sparc/isa/formats/mem/basicmem.isa
@@ -166,4 +166,3 @@ def format TwinLoad(code, *opt_flags) {{
             AlternateASIPrivFaultCheck + TwinAlignmentFaultCheck,
             name, Name, "EXT_ASI", opt_flags)
 }};
-
diff --git a/src/arch/sparc/isa/formats/mem/swap.isa b/src/arch/sparc/isa/formats/mem/swap.isa
index 62348b4f67c..5b617cd6676 100644
--- a/src/arch/sparc/isa/formats/mem/swap.isa
+++ b/src/arch/sparc/isa/formats/mem/swap.isa
@@ -174,5 +174,3 @@ def format CasAlt(code, postacc_code, mem_flags, *opt_flags) {{
      decode_block) = doCasFormat(code, SwapFuncs, AlternateASIPrivFaultCheck,
          name, Name, flags, ["IsStoreConditional"], postacc_code)
 }};
-
-
diff --git a/src/arch/sparc/isa/formats/priv.isa b/src/arch/sparc/isa/formats/priv.isa
index a0c3a18d451..1dc12e48fdb 100644
--- a/src/arch/sparc/isa/formats/priv.isa
+++ b/src/arch/sparc/isa/formats/priv.isa
@@ -133,4 +133,3 @@ def format HPriv(code, check_tl=false, *opt_flags) {{
             doPrivFormat(code, check_code, name, Name, opt_flags,
                          check_tl=(check_tl != 'false'))
 }};
-
diff --git a/src/arch/sparc/isa/formats/unimp.isa b/src/arch/sparc/isa/formats/unimp.isa
index 2e7787e1ed6..37cbaabd04b 100644
--- a/src/arch/sparc/isa/formats/unimp.isa
+++ b/src/arch/sparc/isa/formats/unimp.isa
@@ -40,4 +40,3 @@ def format WarnUnimpl() {{
     iop = InstObjParams(name, 'WarnUnimplemented')
     decode_block = BasicDecodeWithMnemonic.subst(iop)
 }};
-
diff --git a/src/arch/x86/isa/formats/cpuid.isa b/src/arch/x86/isa/formats/cpuid.isa
index 3a69e4c5063..48557a2821a 100644
--- a/src/arch/x86/isa/formats/cpuid.isa
+++ b/src/arch/x86/isa/formats/cpuid.isa
@@ -85,4 +85,3 @@ def format CPUIDInst(code, *opt_flags) {{
     decode_block = BasicDecode.subst(iop)
     exec_output = CPUIDExecute.subst(iop)
 }};
-
diff --git a/src/arch/x86/isa/formats/error.isa b/src/arch/x86/isa/formats/error.isa
index 5ad0f229a0f..25ba2774779 100644
--- a/src/arch/x86/isa/formats/error.isa
+++ b/src/arch/x86/isa/formats/error.isa
@@ -54,4 +54,3 @@ def format M5InternalError(error_message) {{
     iop.message = error_message
     decode_block = ErrorDecode.subst(iop)
 }};
-
diff --git a/src/arch/x86/isa/formats/monitor_mwait.isa b/src/arch/x86/isa/formats/monitor_mwait.isa
index 59baf3cac9f..de4343eabf4 100644
--- a/src/arch/x86/isa/formats/monitor_mwait.isa
+++ b/src/arch/x86/isa/formats/monitor_mwait.isa
@@ -122,4 +122,3 @@ def format MwaitInst(code, *opt_flags) {{
     exec_output += MwaitInitiateAcc.subst(iop)
     exec_output += MwaitCompleteAcc.subst(iop)
 }};
-
diff --git a/src/arch/x86/isa/formats/nop.isa b/src/arch/x86/isa/formats/nop.isa
index c0f6e130824..24cbd1ebec3 100644
--- a/src/arch/x86/isa/formats/nop.isa
+++ b/src/arch/x86/isa/formats/nop.isa
@@ -84,4 +84,3 @@ def format NopInst(*opt_flags) {{
     decode_block = BasicDecode.subst(iop)
     exec_output = NopExecute.subst(iop)
 }};
-
diff --git a/src/arch/x86/isa/formats/syscall.isa b/src/arch/x86/isa/formats/syscall.isa
index 65fa9a25a5e..59a3526ae3a 100644
--- a/src/arch/x86/isa/formats/syscall.isa
+++ b/src/arch/x86/isa/formats/syscall.isa
@@ -88,4 +88,3 @@ def format SyscallInst(code, *opt_flags) {{
     decode_block = BasicDecode.subst(iop)
     exec_output = SyscallExecute.subst(iop)
 }};
-
diff --git a/src/arch/x86/isa/formats/unimp.isa b/src/arch/x86/isa/formats/unimp.isa
index ac7fad7c6e2..9044a4425bc 100644
--- a/src/arch/x86/isa/formats/unimp.isa
+++ b/src/arch/x86/isa/formats/unimp.isa
@@ -149,4 +149,3 @@ def format WarnUnimpl() {{
     iop = InstObjParams(name, 'WarnUnimplemented')
     decode_block = BasicDecodeWithMnemonic.subst(iop)
 }};
-
diff --git a/src/base/bitfield.test.cc b/src/base/bitfield.test.cc
index 37830eabcf7..1711ea68bff 100644
--- a/src/base/bitfield.test.cc
+++ b/src/base/bitfield.test.cc
@@ -456,4 +456,3 @@ TEST(BitfieldTest, CountLeadingZero64AllZeros)
     uint64_t value = 0;
     EXPECT_EQ(64, clz64(value));
 }
-
diff --git a/src/base/filters/multi_bit_sel_bloom_filter.cc b/src/base/filters/multi_bit_sel_bloom_filter.cc
index 4bb3d083151..f12d1f766dc 100644
--- a/src/base/filters/multi_bit_sel_bloom_filter.cc
+++ b/src/base/filters/multi_bit_sel_bloom_filter.cc
@@ -100,4 +100,3 @@ MultiBitSel::hash(Addr addr, int hash_number) const
 
 } // namespace bloom_filter
 } // namespace gem5
-
diff --git a/src/cpu/testers/gpu_ruby_test/README b/src/cpu/testers/gpu_ruby_test/README
index 73fd55421c9..00e4c8e7816 100644
--- a/src/cpu/testers/gpu_ruby_test/README
+++ b/src/cpu/testers/gpu_ruby_test/README
@@ -124,4 +124,4 @@ For more detail, please see the following paper:
 T. Ta, X. Zhang, A. Gutierrez and B. M. Beckmann, "Autonomous Data-Race-Free
 GPU Testing," 2019 IEEE International Symposium on Workload Characterization
 (IISWC), Orlando, FL, USA, 2019, pp. 81-92, doi:
-10.1109/IISWC47752.2019.9042019.
\ No newline at end of file
+10.1109/IISWC47752.2019.9042019.
diff --git a/src/cpu/testers/traffic_gen/SConscript b/src/cpu/testers/traffic_gen/SConscript
index 098bd7b1d7f..f31bd53cdd1 100644
--- a/src/cpu/testers/traffic_gen/SConscript
+++ b/src/cpu/testers/traffic_gen/SConscript
@@ -68,4 +68,3 @@ if env['USE_PYTHON']:
 SimObject('TrafficGen.py', sim_objects=['TrafficGen'], tags='protobuf')
 Source('trace_gen.cc', tags='protobuf')
 Source('traffic_gen.cc', tags='protobuf')
-
diff --git a/src/cpu/trace/TraceCPU.py b/src/cpu/trace/TraceCPU.py
index a98a3dd5ab8..e2dc1db6c5f 100644
--- a/src/cpu/trace/TraceCPU.py
+++ b/src/cpu/trace/TraceCPU.py
@@ -39,7 +39,7 @@
 
 class TraceCPU(BaseCPU):
     """Trace CPU model which replays traces generated in a prior simulation
-     using DerivO3CPU or its derived classes. It interfaces with L1 caches.
+    using DerivO3CPU or its derived classes. It interfaces with L1 caches.
     """
 
     type = "TraceCPU"
diff --git a/src/dev/amdgpu/hwreg_defines.hh b/src/dev/amdgpu/hwreg_defines.hh
index 4e609ff56a7..f5097c8994d 100644
--- a/src/dev/amdgpu/hwreg_defines.hh
+++ b/src/dev/amdgpu/hwreg_defines.hh
@@ -72,4 +72,3 @@ enum amdgpu_hwreg
 } // namespace gem5
 
 #endif // __DEV_GPU_HWREG_DEFINES_H__
-
diff --git a/src/dev/arm/GenericTimer.py b/src/dev/arm/GenericTimer.py
index 3328b73b1d8..a44cd6fd7e7 100644
--- a/src/dev/arm/GenericTimer.py
+++ b/src/dev/arm/GenericTimer.py
@@ -43,12 +43,12 @@
 
 class SystemCounter(SimObject):
     """
-Shared by both PE-implementations and memory-mapped timers. It provides a
-uniform view of system time through its counter value.
+    Shared by both PE-implementations and memory-mapped timers. It provides a
+    uniform view of system time through its counter value.
 
-Reference:
-    Arm ARM (ARM DDI 0487E.a)
-    D11.1.2 - The system counter
+    Reference:
+        Arm ARM (ARM DDI 0487E.a)
+        D11.1.2 - The system counter
     """
 
     type = "SystemCounter"
@@ -71,14 +71,14 @@ def generateDtb(self):
 
 class GenericTimer(SimObject):
     """
-Architected timers per PE in the system. Each of them provides a physical
-counter, a virtual counter and several timers accessible from different
-exception levels and security states.
-
-Reference:
-    Arm ARM (ARM DDI 0487E.a)
-    D11.2 - The AArch64 view of the Generic Timer
-    G6.2  - The AArch32 view of the Generic Timer
+    Architected timers per PE in the system. Each of them provides a physical
+    counter, a virtual counter and several timers accessible from different
+    exception levels and security states.
+
+    Reference:
+        Arm ARM (ARM DDI 0487E.a)
+        D11.2 - The AArch64 view of the Generic Timer
+        G6.2  - The AArch32 view of the Generic Timer
     """
 
     type = "GenericTimer"
@@ -135,12 +135,12 @@ def generateDeviceTree(self, state):
 
 class GenericTimerFrame(PioDevice):
     """
-Memory-mapped timer frame implementation. Controlled from GenericTimerMem,
-may be used by peripherals without a system register interface.
+    Memory-mapped timer frame implementation. Controlled from GenericTimerMem,
+    may be used by peripherals without a system register interface.
 
-Reference:
-    Arm ARM (ARM DDI 0487E.a)
-    I2.3.2 - The CNTBaseN and CNTEL0BaseN frames
+    Reference:
+        Arm ARM (ARM DDI 0487E.a)
+        I2.3.2 - The CNTBaseN and CNTEL0BaseN frames
     """
 
     type = "GenericTimerFrame"
@@ -178,16 +178,16 @@ def generateDeviceTree(self, state, gic):
 
 class GenericTimerMem(PioDevice):
     """
-System level implementation. It provides three main components:
-- Memory-mapped counter module: controls the system timer through the
-  CNTControlBase frame, and provides its value through the CNTReadBase frame
-- Memory-mapped timer control module: controls the memory-mapped timers
-- Memory-mapped timers: implementations of the GenericTimer for system
-  peripherals
-
-Reference:
-    Arm ARM (ARM DDI 0487E.a)
-    I2 - System Level Implementation of the Generic Timer
+    System level implementation. It provides three main components:
+    - Memory-mapped counter module: controls the system timer through the
+      CNTControlBase frame, and provides its value through the CNTReadBase frame
+    - Memory-mapped timer control module: controls the memory-mapped timers
+    - Memory-mapped timers: implementations of the GenericTimer for system
+      peripherals
+
+    Reference:
+        Arm ARM (ARM DDI 0487E.a)
+        I2 - System Level Implementation of the Generic Timer
     """
 
     type = "GenericTimerMem"
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 06182ef6cf6..87f5630b112 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -339,9 +339,9 @@ class RealViewTemperatureSensor(SimObject):
 class VExpressMCC(SubSystem):
     """ARM V2M-P1 Motherboard Configuration Controller
 
-This subsystem describes a subset of the devices that sit behind the
-motherboard configuration controller on the the ARM Motherboard
-Express (V2M-P1) motherboard. See ARM DUI 0447J for details.
+    This subsystem describes a subset of the devices that sit behind the
+    motherboard configuration controller on the the ARM Motherboard
+    Express (V2M-P1) motherboard. See ARM DUI 0447J for details.
     """
 
     class Osc(RealViewOsc):
@@ -380,9 +380,9 @@ def generateDeviceTree(self, state):
 class CoreTile2A15DCC(SubSystem):
     """ARM CoreTile Express A15x2 Daughterboard Configuration Controller
 
-This subsystem describes a subset of the devices that sit behind the
-daughterboard configuration controller on a CoreTile Express A15x2. See
-ARM DUI 0604E for details.
+    This subsystem describes a subset of the devices that sit behind the
+    daughterboard configuration controller on a CoreTile Express A15x2. See
+    ARM DUI 0604E for details.
     """
 
     class Osc(RealViewOsc):
@@ -491,10 +491,10 @@ class Sp804(AmbaPioDevice):
 
 class Sp805(AmbaIntDevice):
     """
-Arm Watchdog Module (SP805)
-Reference:
-    Arm Watchdog Module (SP805) - Technical Reference Manual - rev. r1p0
-    Doc. ID: ARM DDI 0270B
+    Arm Watchdog Module (SP805)
+    Reference:
+        Arm Watchdog Module (SP805) - Technical Reference Manual - rev. r1p0
+        Doc. ID: ARM DDI 0270B
     """
 
     type = "Sp805"
@@ -746,10 +746,10 @@ def generateDeviceTree(self, state):
 
 class FVPBasePwrCtrl(BasicPioDevice):
     """
-Based on Fast Models Base_PowerController v11.8
-Reference:
-    Fast Models Reference Manual - Section 7.7.2 - Version 11.8
-    Document ID: 100964_1180_00_en
+    Based on Fast Models Base_PowerController v11.8
+    Reference:
+        Fast Models Reference Manual - Section 7.7.2 - Version 11.8
+        Document ID: 100964_1180_00_en
     """
 
     type = "FVPBasePwrCtrl"
@@ -1100,148 +1100,148 @@ def setupBootLoader(self, cur_sys, loc, boot_loader=None):
 
 class VExpress_GEM5_Base(RealView):
     """
-The VExpress gem5 memory map is loosely based on a modified
-Versatile Express RS1 memory map.
+    The VExpress gem5 memory map is loosely based on a modified
+    Versatile Express RS1 memory map.
+
+    The gem5 platform has been designed to implement a subset of the
+    original Versatile Express RS1 memory map. Off-chip peripherals should,
+    when possible, adhere to the Versatile Express memory map. Non-PCI
+    off-chip devices that are gem5-specific should live in the CS5 memory
+    space to avoid conflicts with existing devices that we might want to
+    model in the future. Such devices should normally have interrupts in
+    the gem5-specific SPI range.
+
+    On-chip peripherals are loosely modeled after the ARM CoreTile Express
+    A15x2 memory and interrupt map. In particular, the GIC and
+    Generic Timer have the same interrupt lines and base addresses. Other
+    on-chip devices are gem5 specific.
+
+    Unlike the original Versatile Express RS2 extended platform, gem5 implements a
+    large contigious DRAM space, without aliases or holes, starting at the
+    2GiB boundary. This means that PCI memory is limited to 1GiB.
+
+    References:
+
+        Technical Reference Manuals:
+            Arm Motherboard Express uATX (V2M-P1) - ARM DUI 0447J
+            Arm CoreTile Express A15x2 (V2P-CA15) - ARM DUI 0604E
+
+        Official Linux device tree specifications:
+            V2M-P1   - arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
+            V2P-CA15 - arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
+
+        Memory map:
+            Arm CoreTile Express A15x2 (V2P-CA15) - ARM DUI 0604E
+            Daughterboard (global)
+                Section 3.2.1 - Table 3-1 - Daughterboard memory map
+            On-chip
+                Section 3.2.3 - Table 3-2 - Cortex-A15 MPCore on-chip peripheral
+                                            memory map
+
+        Interrupts:
+            Armv8-A Foundation Platform - User Guide - Version 11.8
+            Document ID: 100961_1180_00_en
 
-The gem5 platform has been designed to implement a subset of the
-original Versatile Express RS1 memory map. Off-chip peripherals should,
-when possible, adhere to the Versatile Express memory map. Non-PCI
-off-chip devices that are gem5-specific should live in the CS5 memory
-space to avoid conflicts with existing devices that we might want to
-model in the future. Such devices should normally have interrupts in
-the gem5-specific SPI range.
+    Memory map:
+       0x00000000-0x03ffffff: Boot memory (CS0)
+       0x04000000-0x07ffffff: Trusted Memory/Reserved
+            0x04000000-0x0403FFFF: 256kB Trusted SRAM
+            0x06000000-0x07ffffff: 32MB Trusted DRAM
+       0x08000000-0x0bffffff: NOR FLASH0 (CS0 alias)
+       0x0c000000-0x0fffffff: NOR FLASH1 (Off-chip, CS4)
+       0x10000000-0x13ffffff: gem5-specific peripherals (Off-chip, CS5)
+           0x10000000-0x1000ffff: gem5 energy controller
+           0x10010000-0x1001ffff: gem5 pseudo-ops
+           0x10020000-0x1002ffff: gem5 MHU
 
-On-chip peripherals are loosely modeled after the ARM CoreTile Express
-A15x2 memory and interrupt map. In particular, the GIC and
-Generic Timer have the same interrupt lines and base addresses. Other
-on-chip devices are gem5 specific.
+       0x14000000-0x17ffffff: Reserved (Off-chip, PSRAM, CS1)
 
-Unlike the original Versatile Express RS2 extended platform, gem5 implements a
-large contigious DRAM space, without aliases or holes, starting at the
-2GiB boundary. This means that PCI memory is limited to 1GiB.
+       0x18000000-0x1bffffff: Off-chip, Peripherals, CS2
+           0x18000000-0x19ffffff: VRAM
+           0x1a000000-0x1bffffff: Reserved
 
-References:
+       0x1c000000-0x1fffffff: Peripheral block 1 (Off-chip, CS3):
+           0x1c010000-0x1c01ffff: realview_io (VE system control regs.)
+           0x1c060000-0x1c06ffff: KMI0 (keyboard)
+           0x1c070000-0x1c07ffff: KMI1 (mouse)
+           0x1c090000-0x1c09ffff: UART0
+           0x1c0a0000-0x1c0affff: UART1
+           0x1c0b0000-0x1c0bffff: UART2
+           0x1c0c0000-0x1c0cffff: UART3
+           0x1c0f0000-0x1c0fffff: Watchdog (SP805)
+           0x1c130000-0x1c13ffff: VirtIO (gem5/FM extension)
+           0x1c140000-0x1c14ffff: VirtIO (gem5/FM extension)
+           0x1c170000-0x1c17ffff: RTC
 
-    Technical Reference Manuals:
-        Arm Motherboard Express uATX (V2M-P1) - ARM DUI 0447J
-        Arm CoreTile Express A15x2 (V2P-CA15) - ARM DUI 0604E
+       0x20000000-0x3fffffff: On-chip peripherals:
+           0x2a430000-0x2a43ffff: System Counter (control)
+           0x2a490000-0x2a49ffff: Trusted Watchdog (SP805)
+           0x2a800000-0x2a800fff: System Counter (read)
+           0x2a810000-0x2a810fff: System Timer (control)
 
-    Official Linux device tree specifications:
-        V2M-P1   - arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
-        V2P-CA15 - arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
+           0x2a820000-0x2a820fff: System Timer (frame 0)
+           0x2a830000-0x2a830fff: System Timer (frame 1)
 
-    Memory map:
-        Arm CoreTile Express A15x2 (V2P-CA15) - ARM DUI 0604E
-        Daughterboard (global)
-            Section 3.2.1 - Table 3-1 - Daughterboard memory map
-        On-chip
-            Section 3.2.3 - Table 3-2 - Cortex-A15 MPCore on-chip peripheral
-                                        memory map
+           0x2b000000-0x2b00ffff: HDLCD
 
-    Interrupts:
-        Armv8-A Foundation Platform - User Guide - Version 11.8
-        Document ID: 100961_1180_00_en
+           0x2b060000-0x2b060fff: System Watchdog (SP805)
+
+           0x2b400000-0x2b41ffff: SMMUv3
+
+           0x2c001000-0x2c001fff: GIC (distributor)
+           0x2c002000-0x2c003fff: GIC (CPU interface)
+           0x2c004000-0x2c005fff: vGIC (HV)
+           0x2c006000-0x2c007fff: vGIC (VCPU)
+           0x2c1c0000-0x2c1cffff: GICv2m MSI frame 0
 
-Memory map:
-   0x00000000-0x03ffffff: Boot memory (CS0)
-   0x04000000-0x07ffffff: Trusted Memory/Reserved
-        0x04000000-0x0403FFFF: 256kB Trusted SRAM
-        0x06000000-0x07ffffff: 32MB Trusted DRAM
-   0x08000000-0x0bffffff: NOR FLASH0 (CS0 alias)
-   0x0c000000-0x0fffffff: NOR FLASH1 (Off-chip, CS4)
-   0x10000000-0x13ffffff: gem5-specific peripherals (Off-chip, CS5)
-       0x10000000-0x1000ffff: gem5 energy controller
-       0x10010000-0x1001ffff: gem5 pseudo-ops
-       0x10020000-0x1002ffff: gem5 MHU
-
-   0x14000000-0x17ffffff: Reserved (Off-chip, PSRAM, CS1)
-
-   0x18000000-0x1bffffff: Off-chip, Peripherals, CS2
-       0x18000000-0x19ffffff: VRAM
-       0x1a000000-0x1bffffff: Reserved
-
-   0x1c000000-0x1fffffff: Peripheral block 1 (Off-chip, CS3):
-       0x1c010000-0x1c01ffff: realview_io (VE system control regs.)
-       0x1c060000-0x1c06ffff: KMI0 (keyboard)
-       0x1c070000-0x1c07ffff: KMI1 (mouse)
-       0x1c090000-0x1c09ffff: UART0
-       0x1c0a0000-0x1c0affff: UART1
-       0x1c0b0000-0x1c0bffff: UART2
-       0x1c0c0000-0x1c0cffff: UART3
-       0x1c0f0000-0x1c0fffff: Watchdog (SP805)
-       0x1c130000-0x1c13ffff: VirtIO (gem5/FM extension)
-       0x1c140000-0x1c14ffff: VirtIO (gem5/FM extension)
-       0x1c170000-0x1c17ffff: RTC
-
-   0x20000000-0x3fffffff: On-chip peripherals:
-       0x2a430000-0x2a43ffff: System Counter (control)
-       0x2a490000-0x2a49ffff: Trusted Watchdog (SP805)
-       0x2a800000-0x2a800fff: System Counter (read)
-       0x2a810000-0x2a810fff: System Timer (control)
-
-       0x2a820000-0x2a820fff: System Timer (frame 0)
-       0x2a830000-0x2a830fff: System Timer (frame 1)
-
-       0x2b000000-0x2b00ffff: HDLCD
-
-       0x2b060000-0x2b060fff: System Watchdog (SP805)
-
-       0x2b400000-0x2b41ffff: SMMUv3
-
-       0x2c001000-0x2c001fff: GIC (distributor)
-       0x2c002000-0x2c003fff: GIC (CPU interface)
-       0x2c004000-0x2c005fff: vGIC (HV)
-       0x2c006000-0x2c007fff: vGIC (VCPU)
-       0x2c1c0000-0x2c1cffff: GICv2m MSI frame 0
-
-       0x2d000000-0x2d00ffff: GPU (reserved)
-
-       0x2e000000-0x2e007fff: Non-trusted SRAM
-
-       0x2f000000-0x2fffffff: PCI IO space
-       0x30000000-0x3fffffff: PCI config space
-
-   0x40000000-0x7fffffff: Ext. AXI: Used as PCI memory
-
-   0x80000000-X: DRAM
-
-Interrupts:
-      0- 15: Software generated interrupts (SGIs)
-     16- 31: On-chip private peripherals (PPIs)
-        19   : generic_timer (virt sec EL2)
-        20   : generic_timer (phys sec EL2)
-        25   : vgic
-        26   : generic_timer (phys non-sec EL2)
-        27   : generic_timer (virt EL1)
-        28   : generic_timer (virt non-sec EL2)
-        29   : generic_timer (phys EL3)
-        30   : generic_timer (phys EL1)
-        31   : Reserved (Legacy IRQ)
-    32- 95: Mother board peripherals (SPIs)
-        32   : Watchdog (SP805)
-        33   : Reserved (IOFPGA SW int)
-        34-35: Reserved (SP804)
-        36   : RTC
-        37-40: uart0-uart3
-        41-42: Reserved (PL180)
-        43   : Reserved (AACI)
-        44-45: kmi0-kmi1
-        46   : Reserved (CLCD)
-        47   : Reserved (Ethernet)
-        48   : Reserved (USB)
-        56   : Trusted Watchdog (SP805)
-        57   : System timer0 (phys)
-        58   : System timer1 (phys)
-    95-255: On-chip interrupt sources (we use these for
-            gem5-specific devices, SPIs)
-         74    : VirtIO (gem5/FM extension)
-         75    : VirtIO (gem5/FM extension)
-         95    : HDLCD
-         96- 98: GPU (reserved)
-        100-103: PCI
-        130    : System Watchdog (SP805)
-   256-319: MSI frame 0 (gem5-specific, SPIs)
-   320-511: Unused
+           0x2d000000-0x2d00ffff: GPU (reserved)
+
+           0x2e000000-0x2e007fff: Non-trusted SRAM
+
+           0x2f000000-0x2fffffff: PCI IO space
+           0x30000000-0x3fffffff: PCI config space
+
+       0x40000000-0x7fffffff: Ext. AXI: Used as PCI memory
+
+       0x80000000-X: DRAM
+
+    Interrupts:
+          0- 15: Software generated interrupts (SGIs)
+         16- 31: On-chip private peripherals (PPIs)
+            19   : generic_timer (virt sec EL2)
+            20   : generic_timer (phys sec EL2)
+            25   : vgic
+            26   : generic_timer (phys non-sec EL2)
+            27   : generic_timer (virt EL1)
+            28   : generic_timer (virt non-sec EL2)
+            29   : generic_timer (phys EL3)
+            30   : generic_timer (phys EL1)
+            31   : Reserved (Legacy IRQ)
+        32- 95: Mother board peripherals (SPIs)
+            32   : Watchdog (SP805)
+            33   : Reserved (IOFPGA SW int)
+            34-35: Reserved (SP804)
+            36   : RTC
+            37-40: uart0-uart3
+            41-42: Reserved (PL180)
+            43   : Reserved (AACI)
+            44-45: kmi0-kmi1
+            46   : Reserved (CLCD)
+            47   : Reserved (Ethernet)
+            48   : Reserved (USB)
+            56   : Trusted Watchdog (SP805)
+            57   : System timer0 (phys)
+            58   : System timer1 (phys)
+        95-255: On-chip interrupt sources (we use these for
+                gem5-specific devices, SPIs)
+             74    : VirtIO (gem5/FM extension)
+             75    : VirtIO (gem5/FM extension)
+             95    : HDLCD
+             96- 98: GPU (reserved)
+            100-103: PCI
+            130    : System Watchdog (SP805)
+       256-319: MSI frame 0 (gem5-specific, SPIs)
+       320-511: Unused
 
     """
 
diff --git a/src/dev/arm/a9scu.hh b/src/dev/arm/a9scu.hh
index 4f0ecefccbb..5a8a6dad7d8 100644
--- a/src/dev/arm/a9scu.hh
+++ b/src/dev/arm/a9scu.hh
@@ -84,4 +84,3 @@ class A9SCU : public BasicPioDevice
 } // namespace gem5
 
 #endif // __DEV_ARM_A9SCU_HH__
-
diff --git a/src/dev/hsa/hsa.h b/src/dev/hsa/hsa.h
index 09380d3a96a..41117a4ecde 100644
--- a/src/dev/hsa/hsa.h
+++ b/src/dev/hsa/hsa.h
@@ -2,24 +2,24 @@
 //
 // The University of Illinois/NCSA
 // Open Source License (NCSA)
-// 
+//
 // Copyright (c) 2014-2015, Advanced Micro Devices, Inc. All rights reserved.
-// 
+//
 // Developed by:
-// 
+//
 //                 AMD Research and AMD HSA Software Development
-// 
+//
 //                 Advanced Micro Devices, Inc.
-// 
+//
 //                 www.amd.com
-// 
+//
 // Permission is hereby granted, free of charge, to any person obtaining a copy
 // of this software and associated documentation files (the "Software"), to
 // deal with the Software without restriction, including without limitation
 // the rights to use, copy, modify, merge, publish, distribute, sublicense,
 // and/or sell copies of the Software, and to permit persons to whom the
 // Software is furnished to do so, subject to the following conditions:
-// 
+//
 //  - Redistributions of source code must retain the above copyright notice,
 //    this list of conditions and the following disclaimers.
 //  - Redistributions in binary form must reproduce the above copyright
@@ -29,7 +29,7 @@
 //    nor the names of its contributors may be used to endorse or promote
 //    products derived from this Software without specific prior written
 //    permission.
-// 
+//
 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
@@ -632,7 +632,7 @@ hsa_status_t HSA_API hsa_system_major_extension_supported(
     uint16_t version_major,
     uint16_t *version_minor,
     bool* result);
-    
+
 
 /**
  * @deprecated
@@ -711,7 +711,7 @@ hsa_status_t HSA_API hsa_system_get_major_extension_table(
     uint16_t extension,
     uint16_t version_major,
     size_t table_length,
-    void *table);    
+    void *table);
 
 /**
  * @brief Struct containing an opaque handle to an agent, a device that participates in
@@ -1291,7 +1291,7 @@ hsa_status_t HSA_API hsa_agent_major_extension_supported(
     uint16_t version_major,
     uint16_t *version_minor,
     bool* result);
-    
+
 
 /** @} */
 
diff --git a/src/dev/lupio/lupio_ipi.cc b/src/dev/lupio/lupio_ipi.cc
index ecc1aadc101..892f4d4ee9a 100644
--- a/src/dev/lupio/lupio_ipi.cc
+++ b/src/dev/lupio/lupio_ipi.cc
@@ -148,4 +148,3 @@ LupioIPI::write(PacketPtr pkt)
     return pioDelay;
 }
 } // namespace gem5
-
diff --git a/src/dev/lupio/lupio_ipi.hh b/src/dev/lupio/lupio_ipi.hh
index 02c116631ec..ab50661ddc5 100644
--- a/src/dev/lupio/lupio_ipi.hh
+++ b/src/dev/lupio/lupio_ipi.hh
@@ -96,4 +96,3 @@ class LupioIPI : public BasicPioDevice
 } // namespace gem5
 
 #endif // __DEV_LUPIO_LUPIO_IPI_HH
-
diff --git a/src/dev/ps2/mouse.hh b/src/dev/ps2/mouse.hh
index 3304d950c0b..9ec3f68b948 100644
--- a/src/dev/ps2/mouse.hh
+++ b/src/dev/ps2/mouse.hh
@@ -81,4 +81,3 @@ class PS2Mouse : public Device
 } // namespace gem5
 
 #endif // __DEV_PS2_MOUSE_hH__
-
diff --git a/src/dev/riscv/HiFive.py b/src/dev/riscv/HiFive.py
index 0945ad6c3e3..466968602ba 100755
--- a/src/dev/riscv/HiFive.py
+++ b/src/dev/riscv/HiFive.py
@@ -142,13 +142,11 @@ class HiFive(Platform):
     terminal = Terminal()
 
     def _on_chip_devices(self):
-        """Returns a list of on-chip peripherals
-        """
+        """Returns a list of on-chip peripherals"""
         return [self.clint, self.plic]
 
     def _off_chip_devices(self):
-        """Returns a list of off-chip peripherals
-        """
+        """Returns a list of off-chip peripherals"""
         devices = [self.uart]
         if hasattr(self, "disk"):
             devices.append(self.disk)
@@ -158,7 +156,7 @@ def _off_chip_devices(self):
 
     def _on_chip_ranges(self):
         """Returns a list of on-chip peripherals
-            address range
+        address range
         """
         return [
             AddrRange(dev.pio_addr, size=dev.pio_size)
@@ -167,7 +165,7 @@ def _on_chip_ranges(self):
 
     def _off_chip_ranges(self):
         """Returns a list of off-chip peripherals
-            address range
+        address range
         """
         return [
             AddrRange(dev.pio_addr, size=dev.pio_size)
@@ -175,8 +173,7 @@ def _off_chip_ranges(self):
         ]
 
     def attachPlic(self):
-        """Count number of PLIC interrupt sources
-        """
+        """Count number of PLIC interrupt sources"""
         plic_srcs = [
             self.uart_int_id,
             self.pci_host.int_base + self.pci_host.int_count,
@@ -188,21 +185,21 @@ def attachPlic(self):
 
     def attachOnChipIO(self, bus):
         """Attach on-chip IO devices, needs modification
-            to support DMA
+        to support DMA
         """
         for device in self._on_chip_devices():
             device.pio = bus.mem_side_ports
 
     def attachOffChipIO(self, bus):
         """Attach off-chip IO devices, needs modification
-            to support DMA
+        to support DMA
         """
         for device in self._off_chip_devices():
             device.pio = bus.mem_side_ports
 
     def setNumCores(self, num_cpu):
-        """ Sets the PLIC and CLINT to have the right number of threads and
-            contexts. Assumes that the cores have a single hardware thread.
+        """Sets the PLIC and CLINT to have the right number of threads and
+        contexts. Assumes that the cores have a single hardware thread.
         """
         self.plic.n_contexts = num_cpu * 2
         self.clint.num_threads = num_cpu
diff --git a/src/dev/rtcreg.h b/src/dev/rtcreg.h
index 93fc1c7996f..ea742590b4a 100644
--- a/src/dev/rtcreg.h
+++ b/src/dev/rtcreg.h
@@ -52,4 +52,3 @@ static const int RTC_STAT_REGB = 0x0B;
 
 static const int RTC_STAT_REGC = 0x0C;
 static const int RTC_STAT_REGD = 0x0D;
-
diff --git a/src/mem/SysBridge.py b/src/mem/SysBridge.py
index 731d7df6d32..54479d8bb3b 100644
--- a/src/mem/SysBridge.py
+++ b/src/mem/SysBridge.py
@@ -29,7 +29,7 @@
 
 class SysBridge(SimObject):
     """Use this bridge to connect the memory systems belonging to two different
-       Systems SimObjects. See the header file for more information."""
+    Systems SimObjects. See the header file for more information."""
 
     type = "SysBridge"
     cxx_header = "mem/sys_bridge.hh"
diff --git a/src/mem/cache/SConscript b/src/mem/cache/SConscript
index f1bd83a82b1..dd8f2b145bd 100644
--- a/src/mem/cache/SConscript
+++ b/src/mem/cache/SConscript
@@ -56,4 +56,3 @@ DebugFlag('HWPrefetchQueue')
 # it explicitly even above and beyond CacheAll.
 CompoundFlag('CacheAll', ['Cache', 'CacheComp', 'CachePort', 'CacheRepl',
                           'CacheVerbose', 'HWPrefetch', 'MSHR'])
-
diff --git a/src/mem/port_terminator.cc b/src/mem/port_terminator.cc
index 57263b4aa24..725acdb2d8d 100644
--- a/src/mem/port_terminator.cc
+++ b/src/mem/port_terminator.cc
@@ -54,4 +54,4 @@ PortTerminator::getPort(const std::string &if_name, PortID idx)
     }
 }
 
-}
\ No newline at end of file
+}
diff --git a/src/mem/ruby/network/fault_model/SConscript b/src/mem/ruby/network/fault_model/SConscript
index 701b59a19fe..bd559477956 100644
--- a/src/mem/ruby/network/fault_model/SConscript
+++ b/src/mem/ruby/network/fault_model/SConscript
@@ -38,4 +38,3 @@ if env['CONF']['PROTOCOL'] == 'None':
 
 SimObject('FaultModel.py', sim_objects=['FaultModel'])
 Source('FaultModel.cc')
-
diff --git a/src/mem/ruby/network/garnet/README.txt b/src/mem/ruby/network/garnet/README.txt
index 573ab607273..6d383cb6280 100644
--- a/src/mem/ruby/network/garnet/README.txt
+++ b/src/mem/ruby/network/garnet/README.txt
@@ -76,4 +76,3 @@ instantiated, then the Network Brisge takes over the flit in HeteroGarnet.
     serializing or deserializing the flits
     * Check if CDC is enabled and schedule all the flits according
     to the consumers clock domain.
-
diff --git a/src/mem/ruby/protocol/MI_example-dma.sm b/src/mem/ruby/protocol/MI_example-dma.sm
index 85d0b7f7dfe..01c95122f68 100644
--- a/src/mem/ruby/protocol/MI_example-dma.sm
+++ b/src/mem/ruby/protocol/MI_example-dma.sm
@@ -27,7 +27,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-machine(MachineType:DMA, "DMA Controller") 
+machine(MachineType:DMA, "DMA Controller")
     : DMASequencer * dma_sequencer;
       Cycles request_latency := 6;
 
@@ -134,7 +134,7 @@ machine(MachineType:DMA, "DMA Controller")
     peek(dmaRequestQueue_in, SequencerMsg) {
       enqueue(requestToDir_out, DMARequestMsg, request_latency) {
         out_msg.PhysicalAddress := in_msg.PhysicalAddress;
-        out_msg.LineAddress := in_msg.LineAddress; 
+        out_msg.LineAddress := in_msg.LineAddress;
         out_msg.Type := DMARequestType:READ;
         out_msg.Requestor := machineID;
         out_msg.DataBlk := in_msg.DataBlk;
@@ -149,7 +149,7 @@ machine(MachineType:DMA, "DMA Controller")
     peek(dmaRequestQueue_in, SequencerMsg) {
       enqueue(requestToDir_out, DMARequestMsg, request_latency) {
           out_msg.PhysicalAddress := in_msg.PhysicalAddress;
-          out_msg.LineAddress := in_msg.LineAddress; 
+          out_msg.LineAddress := in_msg.LineAddress;
           out_msg.Type := DMARequestType:WRITE;
           out_msg.Requestor := machineID;
           out_msg.DataBlk := in_msg.DataBlk;
diff --git a/src/mem/ruby/protocol/MOESI_AMD_Base-CorePair.sm b/src/mem/ruby/protocol/MOESI_AMD_Base-CorePair.sm
index 12270cde2fd..7d1bde04dda 100644
--- a/src/mem/ruby/protocol/MOESI_AMD_Base-CorePair.sm
+++ b/src/mem/ruby/protocol/MOESI_AMD_Base-CorePair.sm
@@ -2978,5 +2978,3 @@ machine(MachineType:CorePair, "CP-like Core Coherence")
 
   // END TRANSITIONS
 }
-
-
diff --git a/src/mem/ruby/protocol/MOESI_AMD_Base-Region-CorePair.sm b/src/mem/ruby/protocol/MOESI_AMD_Base-Region-CorePair.sm
index a5e75e94e8c..ae44f09510a 100644
--- a/src/mem/ruby/protocol/MOESI_AMD_Base-Region-CorePair.sm
+++ b/src/mem/ruby/protocol/MOESI_AMD_Base-Region-CorePair.sm
@@ -3008,5 +3008,3 @@ machine(MachineType:CorePair, "CP-like Core Coherence")
 
   // END TRANSITIONS
 }
-
-
diff --git a/src/mem/ruby/protocol/MOESI_AMD_Base-RegionBuffer.sm b/src/mem/ruby/protocol/MOESI_AMD_Base-RegionBuffer.sm
index 3eeece229dc..5987d7cf764 100644
--- a/src/mem/ruby/protocol/MOESI_AMD_Base-RegionBuffer.sm
+++ b/src/mem/ruby/protocol/MOESI_AMD_Base-RegionBuffer.sm
@@ -1371,4 +1371,3 @@ machine(MachineType:RegionBuffer, "Region Buffer for AMD_Base-like protocol")
   }
 
 }
-
diff --git a/src/mem/ruby/protocol/MOESI_AMD_Base-RegionDir.sm b/src/mem/ruby/protocol/MOESI_AMD_Base-RegionDir.sm
index 1b03286411e..2464e038ffe 100644
--- a/src/mem/ruby/protocol/MOESI_AMD_Base-RegionDir.sm
+++ b/src/mem/ruby/protocol/MOESI_AMD_Base-RegionDir.sm
@@ -1180,5 +1180,3 @@ machine(MachineType:RegionDir, "Region Directory for AMD_Base-like protocol")
   }
 
 }
-
-
diff --git a/src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm b/src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm
index c9fe135ae71..865fce4e3c4 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm
@@ -51,7 +51,7 @@ machine(MachineType:L1Cache, "Token protocol")
 
    // Message Queues
    // From this node's L1 cache TO the network
- 
+
    // a local L1 -> this L2 bank
    MessageBuffer * responseFromL1Cache, network="To", virtual_network="4",
         vnet_type="response";
@@ -60,7 +60,7 @@ machine(MachineType:L1Cache, "Token protocol")
    // a local L1 -> this L2 bank, currently ordered with directory forwarded requests
    MessageBuffer * requestFromL1Cache, network="To", virtual_network="1",
         vnet_type="request";
- 
+
    // To this node's L1 cache FROM the network
 
    // a L2 bank -> this L1
diff --git a/src/mem/ruby/protocol/MOESI_hammer-dir.sm b/src/mem/ruby/protocol/MOESI_hammer-dir.sm
index 8c4c63556fb..8fd447fdf4a 100644
--- a/src/mem/ruby/protocol/MOESI_hammer-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_hammer-dir.sm
@@ -26,11 +26,11 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * AMD's contributions to the MOESI hammer protocol do not constitute an 
+ * AMD's contributions to the MOESI hammer protocol do not constitute an
  * endorsement of its similarity to any AMD products.
  */
 
-machine(MachineType:Directory, "AMD Hammer-like protocol") 
+machine(MachineType:Directory, "AMD Hammer-like protocol")
     : DirectoryMemory * directory;
       CacheMemory * probeFilter;
       Cycles from_memory_controller_latency := 2;
@@ -44,7 +44,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
       MessageBuffer * responseFromDir, network="To", virtual_network="4",
             vnet_type="response";
 
-      // For a finite buffered network, note that the DMA response network only 
+      // For a finite buffered network, note that the DMA response network only
       // works at this relatively lower numbered (lower priority) virtual network
       // because the trigger queue decouples cache responses from DMA responses.
       MessageBuffer * dmaResponseFromDir, network="To", virtual_network="1",
@@ -107,7 +107,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
   enumeration(Event, desc="Directory events") {
     GETX,                      desc="A GETX arrives";
     GETS,                      desc="A GETS arrives";
-    PUT,                       desc="A PUT arrives"; 
+    PUT,                       desc="A PUT arrives";
     Unblock,                   desc="An unblock message arrives";
     UnblockS,                   desc="An unblock message arrives";
     UnblockM,                   desc="An unblock message arrives";
@@ -244,7 +244,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
         assert(is_valid(pf_entry) == false);
       }
     }
-    if (state == State:E || state == State:NX || state == State:NO || state == State:S || 
+    if (state == State:E || state == State:NX || state == State:NO || state == State:S ||
         state == State:O) {
       assert(is_valid(tbe) == false);
     }
@@ -456,17 +456,17 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
   }
 
   // Actions
-  
+
   action(r_setMRU, "\rr", desc="manually set the MRU bit for pf entry" ) {
     if (probe_filter_enabled || full_bit_dir_enabled) {
-      assert(is_valid(cache_entry)); 
+      assert(is_valid(cache_entry));
       probeFilter.setMRU(address);
     }
   }
 
   action(auno_assertUnblockerNotOwner, "auno", desc="assert unblocker not owner") {
     if (probe_filter_enabled || full_bit_dir_enabled) {
-      assert(is_valid(cache_entry)); 
+      assert(is_valid(cache_entry));
       peek(unblockNetwork_in, ResponseMsg) {
         assert(cache_entry.Owner != in_msg.Sender);
         if (full_bit_dir_enabled) {
@@ -478,7 +478,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
 
   action(uo_updateOwnerIfPf, "uo", desc="update owner") {
     if (probe_filter_enabled || full_bit_dir_enabled) {
-      assert(is_valid(cache_entry)); 
+      assert(is_valid(cache_entry));
       peek(unblockNetwork_in, ResponseMsg) {
         cache_entry.Owner := in_msg.Sender;
         if (full_bit_dir_enabled) {
@@ -637,7 +637,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
         tbe.Acks := 1;
       }
     }
-  } 
+  }
 
   action(saa_setAcksToAllIfPF, "saa", desc="Non-forwarded request, set the ack amount to all") {
     assert(is_valid(tbe));
@@ -647,7 +647,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
     } else {
       tbe.Acks := 1;
     }
-  }   
+  }
 
   action(m_decrementNumberOfMessages, "m", desc="Decrement the number of messages for which we're waiting") {
     peek(responseToDir_in, ResponseMsg) {
@@ -655,8 +655,8 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
       assert(in_msg.Acks > 0);
       DPRINTF(RubySlicc, "%d\n", tbe.NumPendingMsgs);
       //
-      // Note that cache data responses will have an ack count of 2.  However, 
-      // directory DMA requests must wait for acks from all LLC caches, so 
+      // Note that cache data responses will have an ack count of 2.  However,
+      // directory DMA requests must wait for acks from all LLC caches, so
       // only decrement by 1.
       //
       if ((in_msg.Type == CoherenceResponseType:DATA_SHARED) ||
@@ -763,7 +763,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
         out_msg.LineAddress := address;
         out_msg.Type := DMAResponseType:DATA;
         //
-        // we send the entire data block and rely on the dma controller to 
+        // we send the entire data block and rely on the dma controller to
         // split it up if need be
         //
         out_msg.DataBlk := in_msg.DataBlk;
@@ -781,7 +781,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
         out_msg.LineAddress := address;
         out_msg.Type := DMAResponseType:DATA;
         //
-        // we send the entire data block and rely on the dma controller to 
+        // we send the entire data block and rely on the dma controller to
         // split it up if need be
         //
         out_msg.DataBlk := tbe.DataBlk;
@@ -797,7 +797,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
       out_msg.PhysicalAddress := address;
       out_msg.LineAddress := address;
       out_msg.Type := DMAResponseType:ACK;
-      out_msg.Destination.add(tbe.DmaRequestor); 
+      out_msg.Destination.add(tbe.DmaRequestor);
       out_msg.MessageSize := MessageSizeType:Writeback_Control;
     }
   }
@@ -935,7 +935,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
   action(io_invalidateOwnerRequest, "io", desc="invalidate all copies") {
     if (machineCount(MachineType:L1Cache) > 1) {
       enqueue(forwardNetwork_out, RequestMsg, from_memory_controller_latency) {
-        assert(is_valid(cache_entry)); 
+        assert(is_valid(cache_entry));
         out_msg.addr := address;
         out_msg.Type := CoherenceRequestType:INV;
         out_msg.Requestor := machineID;
@@ -1015,7 +1015,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
         out_msg.MessageSize := MessageSizeType:Request_Control;
         out_msg.InitialRequestTime := zero_time();
         out_msg.ForwardRequestTime := curCycle();
-      }      
+      }
     }
   }
 
@@ -1024,7 +1024,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
     if (probe_filter_enabled || full_bit_dir_enabled) {
       peek(requestQueue_in, RequestMsg) {
         enqueue(forwardNetwork_out, RequestMsg, from_memory_controller_latency) {
-          assert(is_valid(cache_entry)); 
+          assert(is_valid(cache_entry));
           out_msg.addr := address;
           out_msg.Type := in_msg.Type;
           out_msg.Requestor := in_msg.Requestor;
@@ -1034,7 +1034,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
           out_msg.InitialRequestTime := in_msg.InitialRequestTime;
           out_msg.ForwardRequestTime := curCycle();
         }
-      }      
+      }
     } else {
       peek(requestQueue_in, RequestMsg) {
         enqueue(forwardNetwork_out, RequestMsg, from_memory_controller_latency) {
@@ -1099,7 +1099,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
           // itself
           //
           out_msg.Requestor := machineID;
-          out_msg.Destination.broadcast(MachineType:L1Cache); 
+          out_msg.Destination.broadcast(MachineType:L1Cache);
           out_msg.MessageSize := MessageSizeType:Broadcast_Control;
         }
       }
@@ -1118,7 +1118,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
           // itself
           //
           out_msg.Requestor := machineID;
-          out_msg.Destination.broadcast(MachineType:L1Cache); 
+          out_msg.Destination.broadcast(MachineType:L1Cache);
           out_msg.MessageSize := MessageSizeType:Broadcast_Control;
         }
       }
@@ -1132,7 +1132,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
   action(j_popIncomingUnblockQueue, "j", desc="Pop incoming unblock queue") {
     peek(unblockNetwork_in, ResponseMsg) {
         APPEND_TRANSITION_COMMENT(in_msg.Sender);
-    } 
+    }
     unblockNetwork_in.dequeue(clockEdge());
   }
 
@@ -1155,7 +1155,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
   action(zd_stallAndWaitDMARequest, "zd", desc="Stall and wait the dma request queue") {
     peek(dmaRequestQueue_in, DMARequestMsg) {
         APPEND_TRANSITION_COMMENT(in_msg.Requestor);
-    } 
+    }
     stall_and_wait(dmaRequestQueue_in, address);
   }
 
@@ -1184,7 +1184,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
   action(ano_assertNotOwner, "ano", desc="Assert that request is not current owner") {
     if (probe_filter_enabled || full_bit_dir_enabled) {
       peek(requestQueue_in, RequestMsg) {
-        assert(is_valid(cache_entry)); 
+        assert(is_valid(cache_entry));
         assert(cache_entry.Owner != in_msg.Requestor);
       }
     }
@@ -1263,7 +1263,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
   action(z_stallAndWaitRequest, "z", desc="Recycle the request queue") {
     peek(requestQueue_in, RequestMsg) {
         APPEND_TRANSITION_COMMENT(in_msg.Requestor);
-    } 
+    }
     stall_and_wait(requestQueue_in, address);
   }
 
@@ -1467,7 +1467,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
     //
     // note that the PUT requestor may not be the current owner if an invalidate
     // raced with PUT
-    //    
+    //
     a_sendWriteBackAck;
     i_popIncomingRequestQueue;
   }
@@ -1485,9 +1485,9 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
   }
 
   // Blocked transient states
-  transition({NO_B_X, O_B, NO_DR_B_W, NO_DW_B_W, NO_B_W, NO_DR_B_D, 
+  transition({NO_B_X, O_B, NO_DR_B_W, NO_DW_B_W, NO_B_W, NO_DR_B_D,
               NO_DR_B, O_DR_B, O_B_W, O_DR_B_W, NO_DW_W, NO_B_S_W,
-              NO_W, O_W, WB, WB_E_W, WB_O_W, O_R, S_R, NO_R, NO_F_W}, 
+              NO_W, O_W, WB, WB_E_W, WB_O_W, O_R, S_R, NO_R, NO_F_W},
              {GETS, GETX, GETF, PUT, Pf_Replacement}) {
     z_stallAndWaitRequest;
   }
@@ -1508,9 +1508,9 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
     z_stallAndWaitRequest;
   }
 
-  transition({NO_B_X, NO_B, NO_B_S, O_B, NO_DR_B_W, NO_DW_B_W, NO_B_W, NO_DR_B_D, 
+  transition({NO_B_X, NO_B, NO_B_S, O_B, NO_DR_B_W, NO_DW_B_W, NO_B_W, NO_DR_B_D,
               NO_DR_B, O_DR_B, O_B_W, O_DR_B_W, NO_DW_W, NO_B_S_W,
-              NO_W, O_W, WB, WB_E_W, WB_O_W, O_R, S_R, NO_R, NO_F_W}, 
+              NO_W, O_W, WB, WB_E_W, WB_O_W, O_R, S_R, NO_R, NO_F_W},
              {DMA_READ, DMA_WRITE}) {
     zd_stallAndWaitDMARequest;
   }
diff --git a/src/mem/ruby/protocol/MOESI_hammer-dma.sm b/src/mem/ruby/protocol/MOESI_hammer-dma.sm
index 6a4c5ace425..ed45cb4e017 100644
--- a/src/mem/ruby/protocol/MOESI_hammer-dma.sm
+++ b/src/mem/ruby/protocol/MOESI_hammer-dma.sm
@@ -27,7 +27,7 @@
  */
 
 
-machine(MachineType:DMA, "DMA Controller") 
+machine(MachineType:DMA, "DMA Controller")
     : DMASequencer * dma_sequencer;
       Cycles request_latency := 6;
 
@@ -134,7 +134,7 @@ machine(MachineType:DMA, "DMA Controller")
     peek(dmaRequestQueue_in, SequencerMsg) {
       enqueue(requestToDir_out, DMARequestMsg, request_latency) {
         out_msg.PhysicalAddress := in_msg.PhysicalAddress;
-        out_msg.LineAddress := in_msg.LineAddress; 
+        out_msg.LineAddress := in_msg.LineAddress;
         out_msg.Type := DMARequestType:READ;
         out_msg.Requestor := machineID;
         out_msg.DataBlk := in_msg.DataBlk;
@@ -149,7 +149,7 @@ machine(MachineType:DMA, "DMA Controller")
     peek(dmaRequestQueue_in, SequencerMsg) {
       enqueue(requestToDir_out, DMARequestMsg, request_latency) {
           out_msg.PhysicalAddress := in_msg.PhysicalAddress;
-          out_msg.LineAddress := in_msg.LineAddress; 
+          out_msg.LineAddress := in_msg.LineAddress;
           out_msg.Type := DMARequestType:WRITE;
           out_msg.Requestor := machineID;
           out_msg.DataBlk := in_msg.DataBlk;
diff --git a/src/mem/ruby/protocol/MOESI_hammer-msg.sm b/src/mem/ruby/protocol/MOESI_hammer-msg.sm
index 3262903861d..2beaf50d566 100644
--- a/src/mem/ruby/protocol/MOESI_hammer-msg.sm
+++ b/src/mem/ruby/protocol/MOESI_hammer-msg.sm
@@ -25,7 +25,7 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * AMD's contributions to the MOESI hammer protocol do not constitute an 
+ * AMD's contributions to the MOESI hammer protocol do not constitute an
  * endorsement of its similarity to any AMD products.
  */
 
diff --git a/src/mem/ruby/protocol/SConscript b/src/mem/ruby/protocol/SConscript
index 238ce2fe129..07545c3ae0c 100644
--- a/src/mem/ruby/protocol/SConscript
+++ b/src/mem/ruby/protocol/SConscript
@@ -118,4 +118,3 @@ for f in nodes:
         # for it to contain a single SimObject with the same name.
         assert(filename.endswith('_Controller.py'))
         SimObject(f, sim_objects=[os.path.splitext(filename)[0]])
-
diff --git a/src/mem/ruby/protocol/chi/CHI-dvm-misc-node-transitions.sm b/src/mem/ruby/protocol/chi/CHI-dvm-misc-node-transitions.sm
index 24d524b70d6..8a00d78d8c1 100644
--- a/src/mem/ruby/protocol/chi/CHI-dvm-misc-node-transitions.sm
+++ b/src/mem/ruby/protocol/chi/CHI-dvm-misc-node-transitions.sm
@@ -181,4 +181,4 @@ transition(DvmOp_Complete, Final, Unallocated) {
   Pop_TriggerQueue; // "Final" event is applied from the trigger queue
 
   Finalize_DeallocateRequest; // Deallocate the DVM TBE
-}
\ No newline at end of file
+}
diff --git a/src/mem/ruby/protocol/chi/CHI-msg.sm b/src/mem/ruby/protocol/chi/CHI-msg.sm
index 04379826843..63648a5920a 100644
--- a/src/mem/ruby/protocol/chi/CHI-msg.sm
+++ b/src/mem/ruby/protocol/chi/CHI-msg.sm
@@ -247,5 +247,3 @@ structure(CHIDataMsg, desc="", interface="Message") {
     return testAndWrite(addr, dataBlk, pkt);
   }
 }
-
-
diff --git a/src/mem/ruby/protocol/chi/CHI.slicc b/src/mem/ruby/protocol/chi/CHI.slicc
index 49c92882d86..cdb49ed4ac4 100644
--- a/src/mem/ruby/protocol/chi/CHI.slicc
+++ b/src/mem/ruby/protocol/chi/CHI.slicc
@@ -4,4 +4,4 @@ include "RubySlicc_interfaces.slicc";
 include "CHI-msg.sm";
 include "CHI-cache.sm";
 include "CHI-mem.sm";
-include "CHI-dvm-misc-node.sm";
\ No newline at end of file
+include "CHI-dvm-misc-node.sm";
diff --git a/src/mem/ruby/slicc_interface/RubySlicc_includes.hh b/src/mem/ruby/slicc_interface/RubySlicc_includes.hh
index 3a8df919b0f..f68c6c19a94 100644
--- a/src/mem/ruby/slicc_interface/RubySlicc_includes.hh
+++ b/src/mem/ruby/slicc_interface/RubySlicc_includes.hh
@@ -33,4 +33,3 @@
 #include "mem/ruby/slicc_interface/RubySlicc_Util.hh"
 
 #endif // __MEM_RUBY_SLICC_INTERFACE_RUBYSLICC_INCLUDES_HH__
-
diff --git a/src/mem/slicc/parser.py b/src/mem/slicc/parser.py
index 36f74b20191..2d33cd30b51 100644
--- a/src/mem/slicc/parser.py
+++ b/src/mem/slicc/parser.py
@@ -381,8 +381,8 @@ def p_type_members__empty(self, p):
 
     def p_type_member__0(self, p):
         """type_member : obj_decl
-                       | func_decl
-                       | func_def"""
+        | func_decl
+        | func_def"""
         p[0] = p[1]
 
     # Member / Variable declarations
@@ -417,12 +417,12 @@ def p_decl__func_decl(self, p):
 
     def p_func_decl__0(self, p):
         """func_decl :  void ident '(' params ')' pairs SEMI
-                | type ident '(' params ')' pairs SEMI"""
+        | type ident '(' params ')' pairs SEMI"""
         p[0] = ast.FuncDeclAST(self, p[1], p[2], p[4], p[6], None)
 
     def p_func_decl__1(self, p):
         """func_decl :  void ident '(' types ')' pairs SEMI
-                | type ident '(' types ')' pairs SEMI"""
+        | type ident '(' types ')' pairs SEMI"""
         p[0] = ast.FuncDeclAST(self, p[1], p[2], p[4], p[6], None)
 
     def p_decl__func_def(self, p):
@@ -431,7 +431,7 @@ def p_decl__func_def(self, p):
 
     def p_func_def__0(self, p):
         """func_def : void ident '(' params ')' pairs statements
-            | type ident '(' params ')' pairs statements"""
+        | type ident '(' params ')' pairs statements"""
         p[0] = ast.FuncDeclAST(self, p[1], p[2], p[4], p[6], p[7])
 
     # Enum fields
@@ -545,7 +545,7 @@ def p_idents__bare(self, p):
 
     def p_identx__multiple_1(self, p):
         """identx : ident SEMI identx
-                  | ident ',' identx"""
+        | ident ',' identx"""
         p[0] = [p[1]] + p[3]
 
     def p_identx__multiple_2(self, p):
@@ -562,7 +562,7 @@ def p_ident(self, p):
 
     def p_ident_or_star(self, p):
         """ident_or_star : ident
-                         | STAR"""
+        | STAR"""
         p[0] = p[1]
 
     # Pair and pair lists
@@ -586,8 +586,8 @@ def p_pairsx__one(self, p):
 
     def p_pair__assign(self, p):
         """pair : ident '=' STRING
-                | ident '=' ident
-                | ident '=' NUMBER"""
+        | ident '=' ident
+        | ident '=' NUMBER"""
         p[0] = ast.PairAST(self, p[1], p[3])
 
     def p_pair__literal(self, p):
@@ -757,28 +757,28 @@ def p_expr__aexpr(self, p):
 
     def p_expr__binary_op(self, p):
         """expr : expr STAR  expr
-                | expr SLASH expr
-                | expr MOD   expr
-                | expr PLUS  expr
-                | expr DASH  expr
-                | expr LT    expr
-                | expr GT    expr
-                | expr LE    expr
-                | expr GE    expr
-                | expr EQ    expr
-                | expr NE    expr
-                | expr AND   expr
-                | expr OR    expr
-                | expr RIGHTSHIFT expr
-                | expr LEFTSHIFT  expr"""
+        | expr SLASH expr
+        | expr MOD   expr
+        | expr PLUS  expr
+        | expr DASH  expr
+        | expr LT    expr
+        | expr GT    expr
+        | expr LE    expr
+        | expr GE    expr
+        | expr EQ    expr
+        | expr NE    expr
+        | expr AND   expr
+        | expr OR    expr
+        | expr RIGHTSHIFT expr
+        | expr LEFTSHIFT  expr"""
         p[0] = ast.InfixOperatorExprAST(self, p[1], p[2], p[3])
 
     # FIXME - unary not
     def p_expr__unary_op(self, p):
         """expr : NOT expr
-                | INCR expr
-                | DECR expr
-                | DASH expr %prec UMINUS"""
+        | INCR expr
+        | DECR expr
+        | DASH expr %prec UMINUS"""
         p[0] = ast.PrefixOperatorExprAST(self, p[1], p[2])
 
     def p_expr__parens(self, p):
diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py
index 28bc372f085..55ee527c413 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -920,7 +920,7 @@ def printControllerCC(self, path, includes):
     AbstractController::regStats();
 
     // For each type of controllers, one controller of that type is picked
-    // to aggregate stats of all controllers of that type. 
+    // to aggregate stats of all controllers of that type.
     if (m_version == 0) {
 
         Profiler *profiler = params().ruby_system->getProfiler();
diff --git a/src/proto/inst.proto b/src/proto/inst.proto
index 00b9579c545..fadb82952b1 100644
--- a/src/proto/inst.proto
+++ b/src/proto/inst.proto
@@ -112,4 +112,3 @@ message Inst {
   }
   repeated MemAccess mem_access = 8;
 }
-
diff --git a/src/python/gem5/components/boards/x86_board.py b/src/python/gem5/components/boards/x86_board.py
index 96a67907373..04fec617c1f 100644
--- a/src/python/gem5/components/boards/x86_board.py
+++ b/src/python/gem5/components/boards/x86_board.py
@@ -105,7 +105,7 @@ def _setup_board(self) -> None:
         self.m5ops_base = 0xFFFF0000
 
     def _setup_io_devices(self):
-        """ Sets up the x86 IO devices.
+        """Sets up the x86 IO devices.
 
         Note: This is mostly copy-paste from prior X86 FS setups. Some of it
         may not be documented and there may be bugs.
diff --git a/src/python/gem5/components/cachehierarchies/chi/nodes/memory_controller.py b/src/python/gem5/components/cachehierarchies/chi/nodes/memory_controller.py
index bacd0ffb726..4d0589499d0 100644
--- a/src/python/gem5/components/cachehierarchies/chi/nodes/memory_controller.py
+++ b/src/python/gem5/components/cachehierarchies/chi/nodes/memory_controller.py
@@ -38,8 +38,7 @@
 
 
 class MemoryController(Memory_Controller):
-    """A controller that connects to memory
-    """
+    """A controller that connects to memory"""
 
     _version = 0
 
diff --git a/src/python/gem5/components/memory/dramsim_3.py b/src/python/gem5/components/memory/dramsim_3.py
index 8acb727bdc2..b7eba919fc9 100644
--- a/src/python/gem5/components/memory/dramsim_3.py
+++ b/src/python/gem5/components/memory/dramsim_3.py
@@ -128,7 +128,9 @@ def set_memory_range(self, ranges: List[AddrRange]) -> None:
         self.mem_ctrl.range = ranges[0]
 
 
-def SingleChannelDDR3_1600(size: Optional[str] = "2048MB",) -> SingleChannel:
+def SingleChannelDDR3_1600(
+    size: Optional[str] = "2048MB",
+) -> SingleChannel:
     """
     A single channel DDR3_1600.
 
diff --git a/src/python/gem5/components/memory/memory.py b/src/python/gem5/components/memory/memory.py
index aef596d5c0a..c7f20c5941c 100644
--- a/src/python/gem5/components/memory/memory.py
+++ b/src/python/gem5/components/memory/memory.py
@@ -45,7 +45,7 @@ def _try_convert(val, cls):
 
 def _isPow2(num):
     log_num = int(log(num, 2))
-    if 2 ** log_num != num:
+    if 2**log_num != num:
         return False
     else:
         return True
diff --git a/src/python/gem5/components/memory/multi_channel.py b/src/python/gem5/components/memory/multi_channel.py
index f98e0be7dbf..b4b30ba0795 100644
--- a/src/python/gem5/components/memory/multi_channel.py
+++ b/src/python/gem5/components/memory/multi_channel.py
@@ -34,21 +34,27 @@
 from .dram_interfaces.hbm import HBM_1000_4H_1x64
 
 
-def DualChannelDDR3_1600(size: Optional[str] = None,) -> AbstractMemorySystem:
+def DualChannelDDR3_1600(
+    size: Optional[str] = None,
+) -> AbstractMemorySystem:
     """
     A dual channel memory system using DDR3_1600_8x8 based DIMM
     """
     return ChanneledMemory(DDR3_1600_8x8, 2, 64, size=size)
 
 
-def DualChannelDDR3_2133(size: Optional[str] = None,) -> AbstractMemorySystem:
+def DualChannelDDR3_2133(
+    size: Optional[str] = None,
+) -> AbstractMemorySystem:
     """
     A dual channel memory system using DDR3_2133_8x8 based DIMM
     """
     return ChanneledMemory(DDR3_2133_8x8, 2, 64, size=size)
 
 
-def DualChannelDDR4_2400(size: Optional[str] = None,) -> AbstractMemorySystem:
+def DualChannelDDR4_2400(
+    size: Optional[str] = None,
+) -> AbstractMemorySystem:
     """
     A dual channel memory system using DDR4_2400_8x8 based DIMM
     """
@@ -61,7 +67,9 @@ def DualChannelLPDDR3_1600(
     return ChanneledMemory(LPDDR3_1600_1x32, 2, 64, size=size)
 
 
-def HBM2Stack(size: Optional[str] = None,) -> AbstractMemorySystem:
+def HBM2Stack(
+    size: Optional[str] = None,
+) -> AbstractMemorySystem:
     if not size:
         size = "4GiB"
     return ChanneledMemory(HBM_1000_4H_1x64, 16, 64, size=size)
diff --git a/src/python/gem5/components/memory/single_channel.py b/src/python/gem5/components/memory/single_channel.py
index 0cd5316a5f0..43aab45d761 100644
--- a/src/python/gem5/components/memory/single_channel.py
+++ b/src/python/gem5/components/memory/single_channel.py
@@ -68,7 +68,9 @@ def SingleChannelLPDDR3_1600(
     return ChanneledMemory(LPDDR3_1600_1x32, 1, 64, size=size)
 
 
-def SingleChannelHBM(size: Optional[str] = None,) -> AbstractMemorySystem:
+def SingleChannelHBM(
+    size: Optional[str] = None,
+) -> AbstractMemorySystem:
     if not size:
         size = "256MiB"
     return ChanneledMemory(HBM_1000_4H_1x128, 1, 64, size=size)
diff --git a/src/python/gem5/components/processors/simple_switchable_processor.py b/src/python/gem5/components/processors/simple_switchable_processor.py
index f4af2571915..3c84d2ee6ee 100644
--- a/src/python/gem5/components/processors/simple_switchable_processor.py
+++ b/src/python/gem5/components/processors/simple_switchable_processor.py
@@ -52,9 +52,9 @@ def __init__(
         isa: Optional[ISA] = None,
     ) -> None:
         """
-        param starting_core_type: The CPU type for each type in the processor
+        :param starting_core_type: The CPU type for each type in the processor
         to start with (i.e., when the simulation has just started).
-:
+
         :param switch_core_types: The CPU type for each core, to be switched
         to..
 
diff --git a/src/python/m5/params.py b/src/python/m5/params.py
index 504494c5a8c..8e96f4668e6 100644
--- a/src/python/m5/params.py
+++ b/src/python/m5/params.py
@@ -594,7 +594,7 @@ def __init__(cls, name, bases, dict):
                 )
             if cls.unsigned:
                 cls.min = 0
-                cls.max = 2 ** cls.size - 1
+                cls.max = 2**cls.size - 1
             else:
                 cls.min = -(2 ** (cls.size - 1))
                 cls.max = (2 ** (cls.size - 1)) - 1
diff --git a/src/python/m5/simulate.py b/src/python/m5/simulate.py
index 30e71ecc8a5..a47d4cacd61 100644
--- a/src/python/m5/simulate.py
+++ b/src/python/m5/simulate.py
@@ -58,7 +58,7 @@
 from .util import attrdict
 
 # define a MaxTick parameter, unsigned 64 bit
-MaxTick = 2 ** 64 - 1
+MaxTick = 2**64 - 1
 
 _drain_manager = _m5.drain.DrainManager.instance()
 
diff --git a/src/python/m5/util/terminal.py b/src/python/m5/util/terminal.py
index b3578da4c4b..f3d53ac4605 100644
--- a/src/python/m5/util/terminal.py
+++ b/src/python/m5/util/terminal.py
@@ -80,7 +80,6 @@ def cap_string(s, *args):
         else:
             return ""
 
-
 except:
     cap_string = null_cap_string
 
diff --git a/src/sim/RedirectPath.py b/src/sim/RedirectPath.py
index bcb3de175be..c6c63e25585 100644
--- a/src/sim/RedirectPath.py
+++ b/src/sim/RedirectPath.py
@@ -30,7 +30,7 @@
 
 
 class RedirectPath(SimObject):
-    """ Stores paths for filesystem redirection during syscalls. If a path
+    """Stores paths for filesystem redirection during syscalls. If a path
     matches 'appPath', then the syscall is redirected to the first 'hostPath'
     that contains the non-overlapping portion of the path as a valid file. If
      there are no hits, then the syscall is redirected to the first value.
diff --git a/src/sim/drain.hh b/src/sim/drain.hh
index eb6712a5ae9..55c22eb77d8 100644
--- a/src/sim/drain.hh
+++ b/src/sim/drain.hh
@@ -118,11 +118,11 @@ class DrainManager
     /**
      * Run state fixups before a checkpoint restore operation.
      *
-     * This is called before restoring the checkpoint and to make 
+     * This is called before restoring the checkpoint and to make
      * sure that everything has been set to drained.
      *
-     * When restoring from a checkpoint, this function should be called 
-     * first before calling the resume() function. And also before 
+     * When restoring from a checkpoint, this function should be called
+     * first before calling the resume() function. And also before
      * calling loadstate() on any object.
      *
      * The drain state of an object isn't stored in a checkpoint since
diff --git a/src/sst/sst_responder_interface.cc b/src/sst/sst_responder_interface.cc
index faee1082bf0..283c1885c71 100644
--- a/src/sst/sst_responder_interface.cc
+++ b/src/sst/sst_responder_interface.cc
@@ -33,4 +33,4 @@ SSTResponderInterface::SSTResponderInterface()
 {
 }
 
-}; // namespace gem5
\ No newline at end of file
+}; // namespace gem5
diff --git a/src/sst/sst_responder_interface.hh b/src/sst/sst_responder_interface.hh
index 9010907b842..0e827abfdc7 100644
--- a/src/sst/sst_responder_interface.hh
+++ b/src/sst/sst_responder_interface.hh
@@ -66,4 +66,4 @@ class SSTResponderInterface
 
 } // namespace gem5
 
-#endif // __SST_RESPONDER_INTERFACE_HH__
\ No newline at end of file
+#endif // __SST_RESPONDER_INTERFACE_HH__
diff --git a/src/systemc/dt/int/sc_nbcommon.inc b/src/systemc/dt/int/sc_nbcommon.inc
index 13317a6fa5e..6fbbf986a61 100644
--- a/src/systemc/dt/int/sc_nbcommon.inc
+++ b/src/systemc/dt/int/sc_nbcommon.inc
@@ -2575,7 +2575,7 @@ void
 CLASS_TYPE::dump(::std::ostream &os) const
 {
     // Save the current setting, and set the base to decimal.
-    ::std::ios::fmtflags old_flags = 
+    ::std::ios::fmtflags old_flags =
         os.setf(::std::ios::dec, ::std::ios::basefield);
 
     os << "width = " << length() << ::std::endl;
diff --git a/src/systemc/dt/int/sc_nbfriends.inc b/src/systemc/dt/int/sc_nbfriends.inc
index 9161692f0fd..b3a1de0d57b 100644
--- a/src/systemc/dt/int/sc_nbfriends.inc
+++ b/src/systemc/dt/int/sc_nbfriends.inc
@@ -53,7 +53,7 @@
 // ----------------------------------------------------------------------------
 //  Naming conventions:
 //  For sc_signed or sc_unsigned number u:
-//    us : u's sign, unb : u's number of bits, 
+//    us : u's sign, unb : u's number of bits,
 //    und : u's number of digits, ud : u's digits array.
 // ----------------------------------------------------------------------------
 
@@ -63,7 +63,7 @@
 
 // Handles cases 3 and 4 and returns the result.
 CLASS_TYPE
-ADD_HELPER(small_type us, int unb, int und, const sc_digit *ud, 
+ADD_HELPER(small_type us, int unb, int und, const sc_digit *ud,
            small_type vs, int vnb, int vnd, const sc_digit *vd)
 {
     und = vec_skip_leading_zeros(und, ud);
@@ -78,7 +78,7 @@ ADD_HELPER(small_type us, int unb, int und, const sc_digit *ud,
 #else
     sc_digit *d = new sc_digit[nd];
 #endif
-    
+
     d[nd - 1] = d[nd - 2] = 0;
 
     // case 3
@@ -98,14 +98,14 @@ ADD_HELPER(small_type us, int unb, int und, const sc_digit *ud,
     } else {
         // case 4
         int cmp_res = vec_cmp(und, ud, vnd, vd);
-        
+
         if (cmp_res == 0) { // u == v
 #ifndef SC_MAX_NBITS
             delete[] d;
 #endif
             return CLASS_TYPE();
         }
-        
+
         if (cmp_res > 0) { // u > v
             if ((und == 1) && (vnd == 1))
                 d[0] = (*ud) - (*vd);
@@ -128,8 +128,8 @@ ADD_HELPER(small_type us, int unb, int und, const sc_digit *ud,
 // ----------------------------------------------------------------------------
 
 // Handles the case 4 and returns the result.
-CLASS_TYPE 
-MUL_HELPER(small_type s, int unb, int und,  const sc_digit *ud, 
+CLASS_TYPE
+MUL_HELPER(small_type s, int unb, int und,  const sc_digit *ud,
            int vnb, int vnd, const sc_digit *vd)
 {
     und = vec_skip_leading_zeros(und, ud);
@@ -137,7 +137,7 @@ MUL_HELPER(small_type s, int unb, int und,  const sc_digit *ud,
 
     int nb = unb + vnb;
     int nd = und + vnd;
-    
+
 #ifdef SC_MAX_NBITS
     test_bound(nb);
     sc_digit d[MAX_NDIGITS];
@@ -146,7 +146,7 @@ MUL_HELPER(small_type s, int unb, int und,  const sc_digit *ud,
 #endif
 
     vec_zero(nd, d);
-        
+
     sc_digit ud0 = (*ud);
     sc_digit vd0 = (*vd);
 
@@ -154,7 +154,7 @@ MUL_HELPER(small_type s, int unb, int und,  const sc_digit *ud,
         vec_copy(und, d, ud);
     } else if ((und == 1) && (ud0 == 1)) {
         vec_copy(vnd, d, vd);
-    } else if ((und == 1) && (vnd == 1) && 
+    } else if ((und == 1) && (vnd == 1) &&
                (ud0 < HALF_DIGIT_RADIX) && (vd0 < HALF_DIGIT_RADIX)) {
         d[0] = ud0 * vd0;
     } else if ((und == 1) && (ud0 < HALF_DIGIT_RADIX)) {
@@ -175,8 +175,8 @@ MUL_HELPER(small_type s, int unb, int und,  const sc_digit *ud,
 // ----------------------------------------------------------------------------
 
 // Handles the cases 3-4 and returns the result.
-CLASS_TYPE 
-DIV_HELPER(small_type s, int unb, int und, const sc_digit *ud, 
+CLASS_TYPE
+DIV_HELPER(small_type s, int unb, int und, const sc_digit *ud,
            int vnb, int vnd, const sc_digit *vd)
 {
     und = vec_skip_leading_zeros(und, ud);
@@ -185,7 +185,7 @@ DIV_HELPER(small_type s, int unb, int und, const sc_digit *ud,
     int cmp_res = vec_cmp(und, ud, vnd, vd);
 
     // u < v => u / v = 0 - case 4
-    if (cmp_res < 0) 
+    if (cmp_res < 0)
         return CLASS_TYPE();
 
     // One extra digit for d is allocated to simplify vec_div_*().
@@ -223,8 +223,8 @@ DIV_HELPER(small_type s, int unb, int und, const sc_digit *ud,
 // ----------------------------------------------------------------------------
 
 // Handles the cases 3-4 and returns the result.
-CLASS_TYPE 
-MOD_HELPER(small_type us, int unb, int und, const sc_digit *ud, 
+CLASS_TYPE
+MOD_HELPER(small_type us, int unb, int und, const sc_digit *ud,
            int vnb, int vnd, const sc_digit *vd)
 {
     und = vec_skip_leading_zeros(und, ud);
@@ -232,7 +232,7 @@ MOD_HELPER(small_type us, int unb, int und, const sc_digit *ud,
 
     int cmp_res = vec_cmp(und, ud, vnd, vd);
     // u = v => u % v = 0 - case 3
-    if (cmp_res == 0) 
+    if (cmp_res == 0)
         return CLASS_TYPE();
 
     sc_digit vd0 = (*vd);
@@ -280,8 +280,8 @@ MOD_HELPER(small_type us, int unb, int und, const sc_digit *ud,
 // ----------------------------------------------------------------------------
 
 // Handles the cases 2-5 and returns the result.
-CLASS_TYPE 
-AND_HELPER(small_type us, int unb, int und, const sc_digit *ud, 
+CLASS_TYPE
+AND_HELPER(small_type us, int unb, int und, const sc_digit *ud,
            small_type vs, int vnb, int vnd, const sc_digit *vd)
 {
     int nb = sc_max(unb, vnb);
@@ -327,7 +327,7 @@ AND_HELPER(small_type us, int unb, int und, const sc_digit *ud,
         if (xs > 0) { // case 2
             while (y < yend)
                 (*d++) = (*x++) & (*y++);
-            while (x++ < xend) 
+            while (x++ < xend)
                 (*d++) = 0;
         } else { // case 3
             sc_digit xcarry = 1;
@@ -372,7 +372,7 @@ AND_HELPER(small_type us, int unb, int und, const sc_digit *ud,
         }
     }
     s = convert_signed_2C_to_SM(nb, nd, dbegin);
-    return CLASS_TYPE(s, nb, nd, dbegin);    
+    return CLASS_TYPE(s, nb, nd, dbegin);
 }
 
 
@@ -381,8 +381,8 @@ AND_HELPER(small_type us, int unb, int und, const sc_digit *ud,
 // ----------------------------------------------------------------------------
 
 // Handles the cases 3-5 and returns the result.
-CLASS_TYPE 
-OR_HELPER(small_type us, int unb, int und, const sc_digit *ud, 
+CLASS_TYPE
+OR_HELPER(small_type us, int unb, int und, const sc_digit *ud,
           small_type vs, int vnb, int vnd, const sc_digit *vd)
 {
     int nb = sc_max(unb, vnb);
@@ -483,8 +483,8 @@ OR_HELPER(small_type us, int unb, int und, const sc_digit *ud,
 // ----------------------------------------------------------------------------
 
 // Handles the cases 3-5 and returns the result.
-CLASS_TYPE 
-XOR_HELPER(small_type us, int unb, int und, const sc_digit *ud, 
+CLASS_TYPE
+XOR_HELPER(small_type us, int unb, int und, const sc_digit *ud,
            small_type vs, int vnb, int vnd, const sc_digit *vd)
 {
     int nb = sc_max(unb, vnb);
diff --git a/src/systemc/dt/int/sc_signed_bitref.inc b/src/systemc/dt/int/sc_signed_bitref.inc
index c20301c6802..0b24c5ed0a6 100644
--- a/src/systemc/dt/int/sc_signed_bitref.inc
+++ b/src/systemc/dt/int/sc_signed_bitref.inc
@@ -121,8 +121,8 @@ sc_signed_bitref::operator ^= (bool b)
 
 // #### OPTIMIZE
 void
-sc_signed_bitref::concat_set(int64 src, int low_i)  
-{    
+sc_signed_bitref::concat_set(int64 src, int low_i)
+{
     bool value = 1 & ((low_i < 64) ? (src >> low_i) : (src >> 63));
     m_obj_p->set(low_i, value);
 }
@@ -134,7 +134,7 @@ sc_signed_bitref::concat_set(const sc_signed &src, int low_i)
         m_obj_p->set(low_i, src.test(low_i));
     else
         m_obj_p->set(low_i, src < 0);
-}       
+}
 
 void
 sc_signed_bitref::concat_set(const sc_unsigned &src, int low_i)
diff --git a/src/systemc/dt/int/sc_unsigned_bitref.inc b/src/systemc/dt/int/sc_unsigned_bitref.inc
index 09eccd03cc4..38f1007178e 100644
--- a/src/systemc/dt/int/sc_unsigned_bitref.inc
+++ b/src/systemc/dt/int/sc_unsigned_bitref.inc
@@ -19,10 +19,10 @@
 
 /*****************************************************************************
 
-  sc_unsigned_bitref.h -- Proxy class that is declared in sc_unsigned.h.  
+  sc_unsigned_bitref.h -- Proxy class that is declared in sc_unsigned.h.
 
   Original Author: Ali Dasdan, Synopsys, Inc.
- 
+
  *****************************************************************************/
 
 /*****************************************************************************
@@ -138,7 +138,7 @@ sc_unsigned_bitref::concat_set(const sc_signed &src, int low_i)
 
 void
 sc_unsigned_bitref::concat_set(const sc_unsigned &src, int low_i)
-{       
+{
     if (low_i < src.nbits)
         m_obj_p->set(low_i, src.test(low_i));
     else
diff --git a/tests/gem5/cpu_tests/run.py b/tests/gem5/cpu_tests/run.py
index 6a129a0cd54..c54f149b12e 100644
--- a/tests/gem5/cpu_tests/run.py
+++ b/tests/gem5/cpu_tests/run.py
@@ -48,7 +48,7 @@ def connectBus(self, bus):
 
     def connectCPU(self, cpu):
         """Connect this cache's port to a CPU-side port
-           This must be defined in a subclass"""
+        This must be defined in a subclass"""
         raise NotImplementedError
 
 
diff --git a/tests/gem5/fixture.py b/tests/gem5/fixture.py
index 8ac8c394ce0..5d6ae0cd059 100644
--- a/tests/gem5/fixture.py
+++ b/tests/gem5/fixture.py
@@ -269,8 +269,8 @@ def setup(self, testitem):
 
 
 class DownloadedProgram(UniqueFixture):
-    """ Like TestProgram, but checks the version in the gem5 binary repository
-        and downloads an updated version if it is needed.
+    """Like TestProgram, but checks the version in the gem5 binary repository
+    and downloads an updated version if it is needed.
     """
 
     def __new__(cls, url, path, filename, gzip_decompress=False):
@@ -349,8 +349,8 @@ def _setup(self, testitem):
 
 
 class DownloadedArchive(DownloadedProgram):
-    """ Like TestProgram, but checks the version in the gem5 binary repository
-        and downloads an updated version if it is needed.
+    """Like TestProgram, but checks the version in the gem5 binary repository
+    and downloads an updated version if it is needed.
     """
 
     def _extract(self):
diff --git a/tests/gem5/m5threads_test_atomic/caches.py b/tests/gem5/m5threads_test_atomic/caches.py
index 4ac857cafbc..fd87d0484d4 100755
--- a/tests/gem5/m5threads_test_atomic/caches.py
+++ b/tests/gem5/m5threads_test_atomic/caches.py
@@ -60,7 +60,7 @@ def connectBus(self, bus):
 
     def connectCPU(self, cpu):
         """Connect this cache's port to a CPU-side port
-           This must be defined in a subclass"""
+        This must be defined in a subclass"""
         raise NotImplementedError
 
 
diff --git a/tests/pyunit/__init__.py b/tests/pyunit/__init__.py
index 8b137891791..e69de29bb2d 100644
--- a/tests/pyunit/__init__.py
+++ b/tests/pyunit/__init__.py
@@ -1 +0,0 @@
-
diff --git a/tests/pyunit/util/__init__.py b/tests/pyunit/util/__init__.py
index 8b137891791..e69de29bb2d 100644
--- a/tests/pyunit/util/__init__.py
+++ b/tests/pyunit/util/__init__.py
@@ -1 +0,0 @@
-
diff --git a/tests/pyunit/util/pyunit_convert_check.py b/tests/pyunit/util/pyunit_convert_check.py
index 0dba171f145..91b89e64ad7 100644
--- a/tests/pyunit/util/pyunit_convert_check.py
+++ b/tests/pyunit/util/pyunit_convert_check.py
@@ -61,12 +61,12 @@ def conv(x):
         self.assertEqual(conv("42PX"), 42e15)
         self.assertEqual(conv("42EX"), 42e18)
 
-        self.assertEqual(conv("42KiX"), 42 * 2 ** 10)
-        self.assertEqual(conv("42MiX"), 42 * 2 ** 20)
-        self.assertEqual(conv("42GiX"), 42 * 2 ** 30)
-        self.assertEqual(conv("42TiX"), 42 * 2 ** 40)
-        self.assertEqual(conv("42PiX"), 42 * 2 ** 50)
-        self.assertEqual(conv("42EiX"), 42 * 2 ** 60)
+        self.assertEqual(conv("42KiX"), 42 * 2**10)
+        self.assertEqual(conv("42MiX"), 42 * 2**20)
+        self.assertEqual(conv("42GiX"), 42 * 2**30)
+        self.assertEqual(conv("42TiX"), 42 * 2**40)
+        self.assertEqual(conv("42PiX"), 42 * 2**50)
+        self.assertEqual(conv("42EiX"), 42 * 2**60)
 
         self.assertRaises(ValueError, conv, "42k")
         self.assertRaises(ValueError, conv, "42KX")
@@ -80,20 +80,20 @@ def test_toMetricInteger(self):
         def conv(x):
             return convert.toMetricInteger(x, "value", "X")
 
-        self.assertEqual(conv("42"), 42 * 10 ** 0)
-        self.assertEqual(conv("42kX"), 42 * 10 ** 3)
-        self.assertEqual(conv("42MX"), 42 * 10 ** 6)
-        self.assertEqual(conv("42GX"), 42 * 10 ** 9)
-        self.assertEqual(conv("42TX"), 42 * 10 ** 12)
-        self.assertEqual(conv("42PX"), 42 * 10 ** 15)
-        self.assertEqual(conv("42EX"), 42 * 10 ** 18)
-
-        self.assertEqual(conv("42KiX"), 42 * 2 ** 10)
-        self.assertEqual(conv("42MiX"), 42 * 2 ** 20)
-        self.assertEqual(conv("42GiX"), 42 * 2 ** 30)
-        self.assertEqual(conv("42TiX"), 42 * 2 ** 40)
-        self.assertEqual(conv("42PiX"), 42 * 2 ** 50)
-        self.assertEqual(conv("42EiX"), 42 * 2 ** 60)
+        self.assertEqual(conv("42"), 42 * 10**0)
+        self.assertEqual(conv("42kX"), 42 * 10**3)
+        self.assertEqual(conv("42MX"), 42 * 10**6)
+        self.assertEqual(conv("42GX"), 42 * 10**9)
+        self.assertEqual(conv("42TX"), 42 * 10**12)
+        self.assertEqual(conv("42PX"), 42 * 10**15)
+        self.assertEqual(conv("42EX"), 42 * 10**18)
+
+        self.assertEqual(conv("42KiX"), 42 * 2**10)
+        self.assertEqual(conv("42MiX"), 42 * 2**20)
+        self.assertEqual(conv("42GiX"), 42 * 2**30)
+        self.assertEqual(conv("42TiX"), 42 * 2**40)
+        self.assertEqual(conv("42PiX"), 42 * 2**50)
+        self.assertEqual(conv("42EiX"), 42 * 2**60)
 
         self.assertRaises(ValueError, conv, "42.1")
         self.assertRaises(ValueError, conv, "42.1kX")
@@ -193,8 +193,8 @@ def test_toMemoryBandwidth(self):
         self.assertEqual(conv("42"), 42.0)
         self.assertEqual(conv("42B/s"), 42.0)
 
-        self.assertEqual(conv("42MB/s"), 42 * 2 ** 20)
-        self.assertEqual(conv("42MiB/s"), 42 * 2 ** 20)
+        self.assertEqual(conv("42MB/s"), 42 * 2**20)
+        self.assertEqual(conv("42MiB/s"), 42 * 2**20)
 
         self.assertRaises(ValueError, conv, "42KB/s")
         self.assertRaises(ValueError, conv, "42Mi")
@@ -205,11 +205,11 @@ def test_toMemorySize(self):
         self.assertEqual(conv("42"), 42.0)
         self.assertEqual(conv("42B"), 42.0)
 
-        self.assertEqual(conv("42kB"), 42 * 2 ** 10)
-        self.assertEqual(conv("42MB"), 42 * 2 ** 20)
+        self.assertEqual(conv("42kB"), 42 * 2**10)
+        self.assertEqual(conv("42MB"), 42 * 2**20)
 
-        self.assertEqual(conv("42KiB"), 42 * 2 ** 10)
-        self.assertEqual(conv("42MiB"), 42 * 2 ** 20)
+        self.assertEqual(conv("42KiB"), 42 * 2**10)
+        self.assertEqual(conv("42MiB"), 42 * 2**20)
 
     def test_toIpAddress(self):
         conv = convert.toIpAddress
diff --git a/tests/test-progs/hello/src/hello.c b/tests/test-progs/hello/src/hello.c
index 9bf4ed5174d..866e5622eb6 100644
--- a/tests/test-progs/hello/src/hello.c
+++ b/tests/test-progs/hello/src/hello.c
@@ -33,4 +33,3 @@ int main(int argc, char* argv[])
     printf("Hello world!\n");
     return 0;
 }
-
diff --git a/util/checktrace.sh b/util/checktrace.sh
index a63cdd4b6be..b3f1aeaa2fa 100755
--- a/util/checktrace.sh
+++ b/util/checktrace.sh
@@ -29,7 +29,7 @@ do
     bad=`tethereal -r $trace -q  -z "io,stat,100,tcp.analysis.retransmission||tcp.analysis.fast_retransmission||tcp.analysis.out_of_order||tcp.analysis.lost_segment||tcp.analysis.ack_lost_segment||tcp.analysis.window_full||tcp.analysis.duplicate_ack||tcp.analysis.duplicate_ack_num||tcp.analysis.duplicate_ack_frame"  | grep 000.000 | awk '{print $2}'`
     name=`dirname $trace`
 
-    if [ "$bad" != "0" ] 
+    if [ "$bad" != "0" ]
     then
        echo "Run $name had problems."
     fi
diff --git a/util/cpt_upgraders/register-files.py b/util/cpt_upgraders/register-files.py
index c088e135d93..81698b7d2d5 100644
--- a/util/cpt_upgraders/register-files.py
+++ b/util/cpt_upgraders/register-files.py
@@ -1,10 +1,10 @@
 # Rename register files to their new systematic names.
 def upgrader(cpt):
-    is_arm = cpt.get('root', 'isa', fallback='') == 'arm'
+    is_arm = cpt.get("root", "isa", fallback="") == "arm"
 
     import re
 
-    is_cpu = lambda sec: 'intRegs' in cpt[sec]
+    is_cpu = lambda sec: "intRegs" in cpt[sec]
     cpu_sections = filter(is_cpu, cpt.sections())
 
     for sec in cpu_sections:
@@ -19,14 +19,14 @@ def upgrader(cpt):
         byte_mask = (0x1 << byte_bits) - 1
 
         # If there's vecRegs, create regs.vector_element from it.
-        vec_regs = items.get('vecRegs')
+        vec_regs = items.get("vecRegs")
         if vec_regs is not None:
             reg_vals = vec_regs.split()
             if is_arm:
                 full_bits = arm_vec_bits
             else:
                 full_bits = regval_bits
-                reg_vals = ['0']
+                reg_vals = ["0"]
             elem_bits = 32
             elem_mask = (0x1 << elem_bits) - 1
 
@@ -41,40 +41,41 @@ def upgrader(cpt):
                     # Treat the element as a RegVal value, even if it's
                     # fewer bits in the vector registers.
                     for chunk in range(regval_bits // byte_bits):
-                        bytes.append(f'{elem & byte_mask}')
+                        bytes.append(f"{elem & byte_mask}")
                         elem = elem >> byte_bits
 
-            items['regs.vector_element'] = ' '.join(bytes)
+            items["regs.vector_element"] = " ".join(bytes)
 
         name_map = {
-            'floatRegs.i': 'regs.floating_point',
-            'vecRegs': 'regs.vector',
-            'vecPredRegs': 'regs.vector_predicate',
-            'intRegs': 'regs.integer',
-            'ccRegs': 'regs.condition_code',
+            "floatRegs.i": "regs.floating_point",
+            "vecRegs": "regs.vector",
+            "vecPredRegs": "regs.vector_predicate",
+            "intRegs": "regs.integer",
+            "ccRegs": "regs.condition_code",
         }
 
         for old, new in name_map.items():
             if old in items:
-                if is_arm and old in ('vecRegs', 'vecPredRegs'):
+                if is_arm and old in ("vecRegs", "vecPredRegs"):
                     reg_bits = 2048
                 else:
                     reg_bits = regval_bits
 
                 reg_vals = items[old].split()
-                if not is_arm and old in ('vecRegs', 'vecPredRegs'):
-                    reg_vals = ['0']
+                if not is_arm and old in ("vecRegs", "vecPredRegs"):
+                    reg_vals = ["0"]
 
                 bytes = []
                 for reg in reg_vals:
                     reg = int(reg)
                     for chunk in range(reg_bits // byte_bits):
-                        bytes.append(f'{reg & byte_mask}')
+                        bytes.append(f"{reg & byte_mask}")
                         reg = reg >> byte_bits
 
-                items[new] = ' '.join(bytes)
+                items[new] = " ".join(bytes)
                 del items[old]
 
-        items.setdefault('regs.condition_code', '')
+        items.setdefault("regs.condition_code", "")
+
 
 legacy_version = 16
diff --git a/util/decode_inst_dep_trace.py b/util/decode_inst_dep_trace.py
index 939bd77e16f..2a43f52d54a 100755
--- a/util/decode_inst_dep_trace.py
+++ b/util/decode_inst_dep_trace.py
@@ -206,8 +206,8 @@ def main():
         ascii_out.write(":")
         if packet.reg_dep:
             num_regdeps += (
-                1
-            )  # No. of packets with atleast 1 register dependency
+                1  # No. of packets with atleast 1 register dependency
+            )
             for dep in packet.reg_dep:
                 ascii_out.write(",%s" % dep)
         # New line
diff --git a/util/dist/test/test-2nodes-AArch64.sh b/util/dist/test/test-2nodes-AArch64.sh
index cafcf1cdec2..795dace5f86 100644
--- a/util/dist/test/test-2nodes-AArch64.sh
+++ b/util/dist/test/test-2nodes-AArch64.sh
@@ -76,4 +76,3 @@ $GEM5_DIST_SH -n $NNODES                                                     \
                   --script=$BOOT_SCRIPT                                      \
               --cf-args                                                      \
                   $CHKPT_RESTORE
-
diff --git a/util/dockerfiles/llvm-gnu-cross-compiler-riscv64/Dockerfile b/util/dockerfiles/llvm-gnu-cross-compiler-riscv64/Dockerfile
index df7a58cd977..0f01e7931d5 100644
--- a/util/dockerfiles/llvm-gnu-cross-compiler-riscv64/Dockerfile
+++ b/util/dockerfiles/llvm-gnu-cross-compiler-riscv64/Dockerfile
@@ -70,4 +70,3 @@ FROM stage1
 RUN mkdir -p /riscv/
 COPY --from=stage2 /riscv/_install/ /riscv/_install
 ENV PATH=/riscv/_install/bin:$PATH
-
diff --git a/util/dockerfiles/sst-11.1.0/Dockerfile b/util/dockerfiles/sst-11.1.0/Dockerfile
index c9853746c76..970e6979b41 100644
--- a/util/dockerfiles/sst-11.1.0/Dockerfile
+++ b/util/dockerfiles/sst-11.1.0/Dockerfile
@@ -62,4 +62,3 @@ RUN ./configure --prefix=$SST_CORE_HOME --with-python=/usr/bin/python3-config \
 # Setting the environmental variables
 ENV PATH=$PATH:$SST_CORE_HOME/bin
 ENV PKG_CONFIG_PATH=$PKG_CONFIG_PATH:$SST_CORE_HOME/lib/pkgconfig/
-
diff --git a/util/gem5art/artifact/mypy.ini b/util/gem5art/artifact/mypy.ini
index 2fb5fc6b147..9d68ba8f5a4 100644
--- a/util/gem5art/artifact/mypy.ini
+++ b/util/gem5art/artifact/mypy.ini
@@ -1,3 +1,3 @@
 [mypy]
 namespace_packages = True
-warn_unreachable = True
\ No newline at end of file
+warn_unreachable = True
diff --git a/util/gem5art/run/mypy.ini b/util/gem5art/run/mypy.ini
index e0b81f832b3..46ef1454544 100644
--- a/util/gem5art/run/mypy.ini
+++ b/util/gem5art/run/mypy.ini
@@ -1,4 +1,4 @@
 [mypy]
 namespace_packages = True
 warn_unreachable = True
-mypy_path = ../artifact
\ No newline at end of file
+mypy_path = ../artifact
diff --git a/util/gem5art/tasks/mypy.ini b/util/gem5art/tasks/mypy.ini
index e0b81f832b3..46ef1454544 100644
--- a/util/gem5art/tasks/mypy.ini
+++ b/util/gem5art/tasks/mypy.ini
@@ -1,4 +1,4 @@
 [mypy]
 namespace_packages = True
 warn_unreachable = True
-mypy_path = ../artifact
\ No newline at end of file
+mypy_path = ../artifact
diff --git a/util/gerrit-bot/README.md b/util/gerrit-bot/README.md
index 19eb26a8ab7..0f806d9cbee 100644
--- a/util/gerrit-bot/README.md
+++ b/util/gerrit-bot/README.md
@@ -68,4 +68,4 @@ To run the Gerrit bot every 30 minutes, add the following line to the
 crontable,
 ```python
 */1 * * * * cd /path/to/gerrit/bot/directory && ./bot.py
-```
\ No newline at end of file
+```
diff --git a/util/gerrit-bot/gerrit.py b/util/gerrit-bot/gerrit.py
index 51ae93c06ef..2e68a70645a 100644
--- a/util/gerrit-bot/gerrit.py
+++ b/util/gerrit-bot/gerrit.py
@@ -87,13 +87,13 @@ def _post(self, endpoint, json_content):
     # https://gerrit-review.googlesource.com/Documentation/
     # rest-api-accounts.html#get-account
     def get_account(self, account_id="self"):
-        """ get an account detail from an account_id """
+        """get an account detail from an account_id"""
         return self._get(f"/accounts/{account_id}")
 
     # https://gerrit-review.googlesource.com/Documentation/
     # rest-api-accounts.html#query-account
     def query_account(self, query, limit=None):
-        """ get accounts based on the query """
+        """get accounts based on the query"""
         params = {"q": query}
         if limit:
             params["n"] = str(limit)
@@ -103,7 +103,7 @@ def query_account(self, query, limit=None):
     # https://gerrit-review.googlesource.com/Documentation/
     # rest-api-changes.html#list-changes
     def query_changes(self, query, limit=None, optional_field=None):
-        """ query changes with maximum limit returned queries """
+        """query changes with maximum limit returned queries"""
         endpoint = f"/changes/"
         params = {"q": query}
         if limit:
@@ -116,10 +116,10 @@ def query_changes(self, query, limit=None, optional_field=None):
     # https://gerrit-review.googlesource.com/Documentation/
     # rest-api-changes.html#list-reviewers
     def list_reviewers(self, change_id):
-        """ list reviewers of a change """
+        """list reviewers of a change"""
         return self._get(f"/changes/{change_id}/reviewers")
 
     def add_reviewer(self, change_id, reviewer_email):
-        """ add a reviewer using an email address """
+        """add a reviewer using an email address"""
         data = {"reviewer": reviewer_email}
         return self._post(f"/changes/{change_id}/reviewers/", data)
diff --git a/util/git-commit-msg.py b/util/git-commit-msg.py
index c996f90a9a9..12baad8c19a 100755
--- a/util/git-commit-msg.py
+++ b/util/git-commit-msg.py
@@ -39,10 +39,10 @@
 
 def _printErrorQuit(error_message):
     """
-        Print an error message, followed my a help message and inform failure.
+    Print an error message, followed my a help message and inform failure.
 
-        @param error_message A message describing the error that caused the
-            failure.
+    @param error_message A message describing the error that caused the
+        failure.
     """
     print(error_message)
 
@@ -90,10 +90,10 @@ def _printErrorQuit(error_message):
 
 def _validateTags(commit_header):
     """
-        Check if all tags in the commit header belong to the list of valid
-        gem5 tags.
+    Check if all tags in the commit header belong to the list of valid
+    gem5 tags.
 
-        @param commit_header The first line of the commit message.
+    @param commit_header The first line of the commit message.
     """
 
     # List of valid tags
diff --git a/util/m5/README.md b/util/m5/README.md
index 0257d133dc7..2362eed51b0 100644
--- a/util/m5/README.md
+++ b/util/m5/README.md
@@ -410,5 +410,3 @@ subtley broken, when used to target a different ABI. To build these objects
 correctly, we would need to use a proper cross build environment for their
 corresponding languages. Something like this could likely be set up using a
 tool like buildroot.
-
-
diff --git a/util/m5/src/java/gem5/ops.cc b/util/m5/src/java/gem5/ops.cc
index da21840766b..ef524a0e8e0 100644
--- a/util/m5/src/java/gem5/ops.cc
+++ b/util/m5/src/java/gem5/ops.cc
@@ -327,4 +327,3 @@ Java_gem5_Ops_work_1end(JNIEnv *env, jobject obj,
 {
     getDispatchTable(env, obj)->m5_work_end(j_workid, j_threadid);
 }
-
diff --git a/util/maint/list_changes.py b/util/maint/list_changes.py
index 326c63a059f..9ada2b52f06 100755
--- a/util/maint/list_changes.py
+++ b/util/maint/list_changes.py
@@ -211,9 +211,13 @@ def _main():
 
     args = parser.parse_args()
 
-    incoming, outgoing, common, upstream_unknown, feature_unknown = list_changes(
-        args.upstream, args.feature, paths=args.paths
-    )
+    (
+        incoming,
+        outgoing,
+        common,
+        upstream_unknown,
+        feature_unknown,
+    ) = list_changes(args.upstream, args.feature, paths=args.paths)
 
     if incoming:
         print("Incoming changes:")
diff --git a/util/minorview/model.py b/util/minorview/model.py
index b05ac33688d..86f49a3da09 100644
--- a/util/minorview/model.py
+++ b/util/minorview/model.py
@@ -208,9 +208,13 @@ def from_string(self, string):
         m = re.match("^(\w+);(\d+)\.(\d+);([0-9a-fA-Fx]+);(.*)$", string)
 
         if m is not None:
-            self.reason, newStreamSeqNum, newPredictionSeqNum, newPC, id = (
-                m.groups()
-            )
+            (
+                self.reason,
+                newStreamSeqNum,
+                newPredictionSeqNum,
+                newPC,
+                id,
+            ) = m.groups()
 
             self.newStreamSeqNum = int(newStreamSeqNum)
             self.newPredictionSeqNum = int(newPredictionSeqNum)
@@ -1151,7 +1155,7 @@ def get_line(f):
                     new_line = f.readline()
 
                     if new_line is not None and not line_is_comment(new_line):
-                        line_wo_backslash, = extend_match.groups()
+                        (line_wo_backslash,) = extend_match.groups()
                         ret = line_wo_backslash + new_line
                         extend_match = re.match("^(.*)\\\\$", ret)
                     else:
diff --git a/util/minorview/parse.py b/util/minorview/parse.py
index 511d189aee0..5b6bea0c790 100644
--- a/util/minorview/parse.py
+++ b/util/minorview/parse.py
@@ -67,7 +67,7 @@ def list_parser(names):
 
 def map2(f, ls):
     """map to a depth of 2.  That is, given a list of lists, apply
-    f to those innermost elements """
+    f to those innermost elements"""
     return [list(map(f, l)) for l in ls]
 
 
@@ -110,5 +110,5 @@ def parse_indexed_list(string):
 
 def parse_pairs(pairString):
     """parse a string like 'name=value name2=value2' into a
-    dictionary of {'name': 'value', 'name2': 'value2'} """
+    dictionary of {'name': 'value', 'name2': 'value2'}"""
     return dict(parse_pairs_list(pairString))
diff --git a/util/protolib.py b/util/protolib.py
index e34de286f33..dcfb7aabb53 100644
--- a/util/protolib.py
+++ b/util/protolib.py
@@ -146,10 +146,10 @@ def decodeMessage(in_file, message):
 
 def _EncodeVarint32(out_file, value):
     """
-  The encoding of the Varint32 is copied from
-  google.protobuf.internal.encoder and is only repeated here to
-  avoid depending on the internal functions in the library.
-  """
+    The encoding of the Varint32 is copied from
+    google.protobuf.internal.encoder and is only repeated here to
+    avoid depending on the internal functions in the library.
+    """
     bits = value & 0x7F
     value >>= 7
     while value:
diff --git a/util/slicc b/util/slicc
index 201008ba01a..d660510b587 100755
--- a/util/slicc
+++ b/util/slicc
@@ -35,4 +35,5 @@ if __name__ == "__main__":
     sys.path.insert(1, join(base, "../ext/ply"))
 
     import slicc.main
+
     slicc.main.main()
diff --git a/util/statetrace/arch/arm/tracechild.cc b/util/statetrace/arch/arm/tracechild.cc
index df7e42e04a6..a2ffdd133ad 100644
--- a/util/statetrace/arch/arm/tracechild.cc
+++ b/util/statetrace/arch/arm/tracechild.cc
@@ -280,4 +280,3 @@ genTraceChild()
 {
     return new ARMTraceChild;
 }
-
diff --git a/util/statetrace/arch/arm/tracechild.hh b/util/statetrace/arch/arm/tracechild.hh
index d0150e178ec..a2ce69dc3f0 100644
--- a/util/statetrace/arch/arm/tracechild.hh
+++ b/util/statetrace/arch/arm/tracechild.hh
@@ -117,4 +117,3 @@ class ARMTraceChild : public TraceChild
 };
 
 #endif
-
diff --git a/util/statetrace/arch/sparc/tracechild.cc b/util/statetrace/arch/sparc/tracechild.cc
index afb6f74e86b..110f5a4850b 100644
--- a/util/statetrace/arch/sparc/tracechild.cc
+++ b/util/statetrace/arch/sparc/tracechild.cc
@@ -468,4 +468,3 @@ genTraceChild()
 {
     return new SparcTraceChild;
 }
-
diff --git a/util/statetrace/base/statetrace.cc b/util/statetrace/base/statetrace.cc
index d2a9e2083be..be5ce83001c 100644
--- a/util/statetrace/base/statetrace.cc
+++ b/util/statetrace/base/statetrace.cc
@@ -151,4 +151,3 @@ main(int argc, char * argv[], char * envp[])
     }
     return 0;
 }
-
diff --git a/util/style/verifiers.py b/util/style/verifiers.py
index 392d01c241e..4ccd35af48b 100644
--- a/util/style/verifiers.py
+++ b/util/style/verifiers.py
@@ -54,9 +54,9 @@
 
 
 def safefix(fix_func):
-    """ Decorator for the fix functions of the Verifier class.
-        This function wraps the fix function and creates a backup file
-        just in case there is an error.
+    """Decorator for the fix functions of the Verifier class.
+    This function wraps the fix function and creates a backup file
+    just in case there is an error.
     """
 
     def safefix_wrapper(*args, **kwargs):
@@ -474,29 +474,29 @@ def fix_line(self, line, **kwargs):
 
 
 class StructureBraces(LineVerifier):
-    """ Check if the opening braces of structures are not on the same line of
-        the structure name. This includes classes, structs, enums and unions.
-
-        This verifier matches lines starting in optional indent, followed by
-        an optional typedef and the structure's keyword, followed by any
-        character until the first opening brace is seen. Any extra characters
-        after the opening brace are saved for a recursive check, if needed.
-
-        This fixes, for example:
-            1) "struct A {"
-            2) "enum{"
-            3) "    class B { // This is a class"
-            4) "union { struct C {"
-        to:
-            1) "struct A\n{"
-            2) "enum\n{"
-            3) "    class B\n    {\n        // This is a class"
-            4) "union\n{\n        struct C\n        {"
-
-        @todo Make this work for multi-line structure declarations. e.g.,
-
-            class MultiLineClass
-              : public BaseClass {
+    """Check if the opening braces of structures are not on the same line of
+    the structure name. This includes classes, structs, enums and unions.
+
+    This verifier matches lines starting in optional indent, followed by
+    an optional typedef and the structure's keyword, followed by any
+    character until the first opening brace is seen. Any extra characters
+    after the opening brace are saved for a recursive check, if needed.
+
+    This fixes, for example:
+        1) "struct A {"
+        2) "enum{"
+        3) "    class B { // This is a class"
+        4) "union { struct C {"
+    to:
+        1) "struct A\n{"
+        2) "enum\n{"
+        3) "    class B\n    {\n        // This is a class"
+        4) "union\n{\n        struct C\n        {"
+
+    @todo Make this work for multi-line structure declarations. e.g.,
+
+        class MultiLineClass
+          : public BaseClass {
     """
 
     languages = set(("C", "C++"))
diff --git a/util/tlm/conf/tgen.cfg b/util/tlm/conf/tgen.cfg
index 8204959083c..67830a8b285 100644
--- a/util/tlm/conf/tgen.cfg
+++ b/util/tlm/conf/tgen.cfg
@@ -1,21 +1,21 @@
 # Copyright (c) 2015, University of Kaiserslautern
 # All rights reserved.
-# 
+#
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions are
 # met:
-# 
+#
 # 1. Redistributions of source code must retain the above copyright notice,
 #    this list of conditions and the following disclaimer.
-# 
+#
 # 2. Redistributions in binary form must reproduce the above copyright
 #    notice, this list of conditions and the following disclaimer in the
 #    documentation and/or other materials provided with the distribution.
-# 
+#
 # 3. Neither the name of the copyright holder nor the names of its
 #    contributors may be used to endorse or promote products derived from
 #    this software without specific prior written permission.
-# 
+#
 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 # TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
diff --git a/util/tlm/examples/slave_port/sc_target.hh b/util/tlm/examples/slave_port/sc_target.hh
index 5d93cfd1842..e3624e15552 100644
--- a/util/tlm/examples/slave_port/sc_target.hh
+++ b/util/tlm/examples/slave_port/sc_target.hh
@@ -98,4 +98,3 @@ struct Target: sc_module
 };
 
 #endif //__SIM_SC_TARGET_HH__
-
diff --git a/util/tlm/run_gem5_fs.sh b/util/tlm/run_gem5_fs.sh
index 8f81be0f88a..9065cbf9f5d 100755
--- a/util/tlm/run_gem5_fs.sh
+++ b/util/tlm/run_gem5_fs.sh
@@ -1,22 +1,22 @@
 #!/bin/bash
 # Copyright (c) 2015, University of Kaiserslautern
 # All rights reserved.
-# 
+#
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions are
 # met:
-# 
+#
 # 1. Redistributions of source code must retain the above copyright notice,
 #    this list of conditions and the following disclaimer.
-# 
+#
 # 2. Redistributions in binary form must reproduce the above copyright
 #    notice, this list of conditions and the following disclaimer in the
 #    documentation and/or other materials provided with the distribution.
-# 
+#
 # 3. Neither the name of the copyright holder nor the names of its
 #    contributors may be used to endorse or promote products derived from
 #    this software without specific prior written permission.
-# 
+#
 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 # TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
diff --git a/util/tracediff b/util/tracediff
index ebe34d452b8..89cef9ab98a 100755
--- a/util/tracediff
+++ b/util/tracediff
@@ -146,6 +146,3 @@ $fullcmd = "$FindBin::Bin/rundiff '$cmd1' '$cmd2' 2>&1 > tracediff-$$.out";
 
 print "Executing $fullcmd\n";
 system($fullcmd);
-
-
-