lab2 finished

Author: liukangxu

README.md

@@ -5,7 +5,7 @@ Porting MIPS operating system kernel to Raspberry Pi 3 on AArch64.
 
 ## TODO
 - [X] Boot
-- [ ] Memory management
+- [X] Memory management
 - [ ] Process management and exception handling
 - [ ] System call
 - [ ] File system

os/boot/asm.s

@@ -2,112 +2,112 @@
 
 .globl _start
 _start:
-    MRS X0, MPIDR_EL1       // Check Core Id, we only use one core. 
-    MOV X1, #0XC1000000
-    BIC X0, X0, X1
-    CBZ X0, master
-    B hang
+    mrs x0, mpidr_el1       // check core id, we only use one core.
+    mov x1, #0xc1000000
+    bic x0, x0, x1
+    cbz x0, master
+    b hang
 
 master:
-    LDR X0, =0X04008000
-    MOV SP, X0               // Set EL3 SP
-    BL el2_main
+    ldr x0, =0x1000000
+    mov sp, x0               // set el3 sp
+    bl el2_main
 
 hang:
-    B hang
-    
+    b hang
+
 .globl get_current_el
 get_current_el:
-    MRS X0, CURRENTEL
-    MOV X1, #2
-    LSR X0, X0, #2
-    RET
-    
+    mrs x0, currentel
+    mov x1, #2
+    lsr x0, x0, #2
+    ret
+
 .globl el1_mmu_activate
 el1_mmu_activate:
-    LDR X0, =0X04CC
-    MSR MAIR_EL1, X0
-    ISB
-
-    LDR X1, =0X02000000
-    MSR TTBR0_EL1, X1
-    ISB
-
-    MRS X2, TCR_EL1
-    LDR X3, =0x70040FFBF
-    BIC X2, X2, X3
-
-    LDR X3, =0X200803F18
-    ORR X2, X2, X3
-    MSR TCR_EL1, X2
-    ISB
-
-    MRS X3, SCTLR_EL1
-    LDR X4, =0X80000
-    BIC X3, X3, X4
-    
-    LDR X4, =0X1005
-    ORR X3, X3, X4
-    MSR SCTLR_EL1, X3
-    ISB
-    RET
+    ldr x0, =0x04cc
+    msr mair_el1, x0
+    isb
+
+    ldr x1, =0x02000000
+    msr ttbr0_el1, x1
+    isb
+
+    mrs x2, tcr_el1
+    ldr x3, =0x70040ffbf
+    bic x2, x2, x3
+
+    ldr x3, =0x200803f18
+    orr x2, x2, x3
+    msr tcr_el1, x2
+    isb
+
+    mrs x3, sctlr_el1
+    ldr x4, =0x80000
+    bic x3, x3, x4
+
+    ldr x4, =0x1005
+    orr x3, x3, x4
+    msr sctlr_el1, x3
+    isb
+    ret
 
 .globl jump_to_el1
 jump_to_el1:
-	MRS	X0, CURRENTEL		// Check if already in EL1
-	CMP	X0, #4
-	BEQ	1f
-
-	LDR	X0, =0X03C08000
-	MSR	SP_EL1, X0	        // Init the stack of EL1
-
-    // Disable coprocessor traps
-	MOV	X0, #0X33ff
-	MSR	CPTR_EL2, X0	    // Disable coprocessor traps to EL2
-	MSR	HSTR_EL2, xzr		// Disable coprocessor traps to EL2
-	MOV	X0, #3 << 20
-	MSR	CPACR_EL1, X0	    // Enable FP/SIMD at EL1
-
-	// Initialize HCR_EL2
-	MOV	X0, #(1 << 31)
-	MSR	HCR_EL2, X0		    // Set EL1 to 64 bit
-	MOV	X0, #0X0800
-	MOVK X0, #0X30d0, LSL #16
-	MSR	SCTLR_EL1, X0
-
-	// Return to the EL1_SP1 mode from EL2
-	MOV	X0, #0X3C5
-	MSR	SPSR_EL2, X0	    // EL1_SP0 | D | A | I | F
-	ADR	X0, 1f
-	MSR	ELR_EL2, X0
-	ERET
-    
+	mrs	x0, currentel		// check if already in el1
+	cmp	x0, #4
+	beq	1f
+
+	ldr	x0, =0xf00000
+	msr	sp_el1, x0	        // init the stack of el1
+
+    // disable coprocessor traps
+	mov	x0, #0x33ff
+	msr	cptr_el2, x0	    // disable coprocessor traps to el2
+	msr	hstr_el2, xzr		// disable coprocessor traps to el2
+	mov	x0, #3 << 20
+	msr	cpacr_el1, x0	    // enable fp/simd at el1
+
+	// initialize hcr_el2
+	mov	x0, #(1 << 31)
+	msr	hcr_el2, x0		    // set el1 to 64 bit
+	mov	x0, #0x0800
+	movk x0, #0x30d0, lsl #16
+	msr	sctlr_el1, x0
+
+	// return to the el1_sp1 mode from el2
+	mov	x0, #0x3c5
+	msr	spsr_el2, x0	    // el1_sp0 | d | a | i | f
+	adr	x0, 1f
+	msr	elr_el2, x0
+	eret
+
 1:
-	MRS	X0, SCTLR_EL1
-	ORR	X0, X0, #(1 << 12)
-	MSR	SCTLR_EL1, X0		// enable instruction cache
-
-    B main
-    
+	mrs	x0, sctlr_el1
+	orr	x0, x0, #(1 << 12)
+	msr	sctlr_el1, x0		// enable instruction cache
+    b main
+
 .globl tlb_invalidate
 tlb_invalidate:
-    DSB ISHST               // ensure write has completed
-    LDR X0, [X0]            // load VA from X0
-    TLBI VAAE1, X0          // invalidate TLB by VA, All ASID, EL1.
-    DSB ISH                 // ensure completion of TLB invalidation
-    ISB                     // synchronize context and ensure that no instructions are fetched using the old translation
-    RET
-
-.globl PUT32
-PUT32:
-    STR W1,[X0]
-    RET
-
-.globl GET32
-GET32:
-    LDR W0,[X0]
-    RET
+    dsb ishst               // ensure write has completed
+    ldr x0, [x0]            // load va from x0
+    tlbi vmalle1            // invalidate tlb by va, all asid, el1.
+    dsb ish                 // ensure completion of tlb invalidation
+    isb                     // synchronize context and ensure that no instructions
+                            // are fetched using the old translation
+    ret
+
+.globl put32
+put32:
+    str w1,[x0]
+    ret
+
+.globl get32
+get32:
+    ldr w0,[x0]
+    ret
 
 .globl dummy
 dummy:
-    RET
+    ret

os/boot/el2.c

@@ -10,16 +10,19 @@ void el2_main(void)
 {
     // initialize uart
     uart_init();
-    
-    // create page dir and page map 
+
+    printf("\n\nInitializing...\n");
+
+    // create page dir and page map
     vm_init();
-    
+    printf("vm_init success.\n");
+
     // fill page map
-	page_init();
-    
+    page_init();
+
     // jump to el1
     printf("Now in EL%lx. Jumping to EL1...\n", get_current_el());
     jump_to_el1();
-    
-    panic("failed to jump");
+
+    panic("failed to jump EL");
 }

os/boot/main.c

@@ -6,26 +6,28 @@
 extern u_long get_current_el();
 extern void el1_mmu_activate();
 
-void main (void)
+void main(void)
 {
-    printf("We are finally at EL%lx!\n", get_current_el());
-    
+    printf("We are now at EL%lx.\n", get_current_el());
+
     // activate mmu for el1
-    el1_mmu_activate();
-    
-    page_check();
-    
-    printf("Page check passed!\n\n\n\n");
-    
+    // el1_mmu_activate();
+    // printf("MMU activated.\n");
+
+    //printf("%s\n", "Page check start");
+    //page_check();
+    //printf("Page check passed!\n\n\n\n");
+
+    printf("Activating LED...\n");
     gpio_output_init(17);
-    for (;;)
+    for ( ; ; )
     {
         gpio_set(17);
         sleep(1000);
-        
+
         gpio_clr(17);
         sleep(1000);
     }
-    
+
     panic("The end of main()\n");
 }

os/driver/gpio.c

@@ -1,21 +1,21 @@
 #include "rpslib.h"
 #include "rpsio.h"
 
-#define MIN_GPIO 2
-#define MAX_GPIO 27
+#define MIN_GPIO           2
+#define MAX_GPIO           27
 
-#define PHYSADDR_OFFSET 0x3F200000
+#define PHYSADDR_OFFSET    0x3F200000
 
-#define GPFSEL0 (PHYSADDR_OFFSET + 0x00000000)
-#define GPSET0  (PHYSADDR_OFFSET + 0x0000001C)
-#define GPCLR0  (PHYSADDR_OFFSET + 0x00000028)
+#define GPFSEL0            (PHYSADDR_OFFSET + 0x00000000)
+#define GPSET0             (PHYSADDR_OFFSET + 0x0000001C)
+#define GPCLR0             (PHYSADDR_OFFSET + 0x00000028)
 
-extern unsigned int GET32(unsigned int);
-extern void PUT32 ( unsigned int, unsigned int );
+extern unsigned int get32(unsigned int);
+extern void put32(unsigned int, unsigned int);
 
 static int check_if_gpio_legal(int n)
 {
-    if (n >= MIN_GPIO && n <= MAX_GPIO)
+    if ((n >= MIN_GPIO) && (n <= MAX_GPIO))
     {
         return 1;
     }
@@ -25,6 +25,7 @@ static int check_if_gpio_legal(int n)
     }
 }
 
+
 void gpio_output_init(int n)
 {
     if (!check_if_gpio_legal(n))
@@ -35,31 +36,33 @@ void gpio_output_init(int n)
     int ra;
 
     // Set GPIO n as Output
-    ra = GET32(GPFSEL0 + 4 * (n / 10));
+    ra = get32(GPFSEL0 + 4 * (n / 10));
     ra &= ~(7 << ((n % 10) * 3));
     ra |= 1 << ((n % 10) * 3);
-    PUT32(GPFSEL0 + 4 * (n / 10), ra);
+    put32(GPFSEL0 + 4 * (n / 10), ra);
     sleep(0);
 }
 
+
 void gpio_set(int n)
 {
     if (!check_if_gpio_legal(n))
     {
         panic("GPIO%d out of range", n);
     }
 
-    PUT32(GPSET0 + 4 * (n / 32), 1 << (n % 32));
+    put32(GPSET0 + 4 * (n / 32), 1 << (n % 32));
     sleep(0);
 }
 
+
 void gpio_clr(int n)
 {
     if (!check_if_gpio_legal(n))
     {
         panic("GPIO%d out of range", n);
     }
 
-    PUT32(GPCLR0 + 4 * (n / 32), 1 << (n % 32));
+    put32(GPCLR0 + 4 * (n / 32), 1 << (n % 32));
     sleep(0);
-}
+}