riscv32im target support

[staaason]

Testing simple transfer example we encounter an access violation error. Disabling address_translation results in a LoadAccessFault from the RISC0 circuit. Otherwise, running on a 64-bit target produces a SIGBUS signal with an access to undefined memory.

The current memory mapping system assumes that the 64-bit address space is used for pointers, which are divided into a 32-bit region index and a 32-bit address within each region.

The exact issue described in the solana rbpf repository

The place where the error occurs is when we try to call SyscallInvokeSignedRust::translate_instruction and translate account metadata from virtual memory to host memory.

impl SyscallInvokeSigned for SyscallInvokeSignedRust {
    fn translate_instruction(
        addr: u64,
        memory_mapping: &MemoryMapping,
        invoke_context: &mut InvokeContext,
    ) -> Result<StableInstruction, Error> {
        let ix = translate_type::<StableInstruction>(
            memory_mapping,
            addr,
            invoke_context.get_check_aligned(),
        )?;
        let account_metas = translate_slice::<AccountMeta>(
            memory_mapping,
            ix.accounts.as_ptr() as u64,
            ix.accounts.len() as u64,
            invoke_context.get_check_aligned(),
        )?;
        let data = translate_slice::<u8>(
            memory_mapping,
            ix.data.as_ptr() as u64,
            ix.data.len() as u64,
            invoke_context.get_check_aligned(),
        )?
        .to_vec();

        check_instruction_size(account_metas.len(), data.len(), invoke_context)?;

        if invoke_context
            .get_feature_set()
            .is_active(&feature_set::loosen_cpi_size_restriction::id())
        {
            consume_compute_meter(
                invoke_context,
                (data.len() as u64)
                    .checked_div(invoke_context.get_compute_budget().cpi_bytes_per_unit)
                    .unwrap_or(u64::MAX),
            )?;
        }

        let mut accounts = Vec::with_capacity(account_metas.len());
        #[allow(clippy::needless_range_loop)]
        for account_index in 0..account_metas.len() {
            #[allow(clippy::indexing_slicing)]
            let account_meta = &account_metas[account_index];
            if unsafe {
                std::ptr::read_volatile(&account_meta.is_signer as *const _ as *const u8) > 1
                    || std::ptr::read_volatile(&account_meta.is_writable as *const _ as *const u8)
                        > 1
            } {
                return Err(Box::new(InstructionError::InvalidArgument));
            }
            accounts.push(account_meta.clone());
        }

        Ok(StableInstruction {
            accounts: accounts.into(),
            data: data.into(),
            program_id: ix.program_id,
        })
    }
}

The current implementation is based on executing eBPF as x86 instructions, which work fully only on a 64-bit architecture. To support the full transaction processing cycle, we need to treat eBPF bytecode as RISC-V instructions that are compatible with the riscv32 architecture. This requires modifying the virtual machine to process these instructions according to the RISC-V manual and natively support 32-bit pointers.