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| 1 | +# nmigen: UnusedElaboratable=no |
| 2 | + |
| 3 | +import unittest |
| 4 | +from nmigen import * |
| 5 | +from nmigen.back.pysim import * |
| 6 | + |
| 7 | +from ..event import * |
| 8 | + |
| 9 | + |
| 10 | +def simulation_test(dut, process): |
| 11 | + with Simulator(dut, vcd_file=open("test.vcd", "w")) as sim: |
| 12 | + sim.add_clock(1e-6) |
| 13 | + sim.add_sync_process(process) |
| 14 | + sim.run() |
| 15 | + |
| 16 | + |
| 17 | +class SourceTestCase(unittest.TestCase): |
| 18 | + def test_level(self): |
| 19 | + src = Source(trigger="level") |
| 20 | + self.assertEqual(src.trigger, Source.Trigger.LEVEL) |
| 21 | + |
| 22 | + def test_rise(self): |
| 23 | + src = Source(trigger="rise") |
| 24 | + self.assertEqual(src.trigger, Source.Trigger.RISE) |
| 25 | + |
| 26 | + def test_fall(self): |
| 27 | + src = Source(trigger="fall") |
| 28 | + self.assertEqual(src.trigger, Source.Trigger.FALL) |
| 29 | + |
| 30 | + def test_trigger_wrong(self): |
| 31 | + with self.assertRaisesRegex(ValueError, |
| 32 | + r"Invalid trigger mode 'foo'; must be one of level, rise, fall"): |
| 33 | + src = Source(trigger="foo") |
| 34 | + |
| 35 | + |
| 36 | +class EventMapTestCase(unittest.TestCase): |
| 37 | + def test_add(self): |
| 38 | + src_0 = Source() |
| 39 | + src_1 = Source() |
| 40 | + event_map = EventMap() |
| 41 | + event_map.add(src_0) |
| 42 | + event_map.add(src_1) |
| 43 | + self.assertTrue(src_0 in event_map._sources) |
| 44 | + self.assertTrue(src_1 in event_map._sources) |
| 45 | + |
| 46 | + def test_add_wrong(self): |
| 47 | + event_map = EventMap() |
| 48 | + with self.assertRaisesRegex(TypeError, |
| 49 | + r"Event source must be an instance of event.Source, not 'foo'"): |
| 50 | + event_map.add("foo") |
| 51 | + |
| 52 | + def test_add_wrong_frozen(self): |
| 53 | + event_map = EventMap() |
| 54 | + event_map.freeze() |
| 55 | + with self.assertRaisesRegex(ValueError, |
| 56 | + r"Event map has been frozen. Cannot add source."): |
| 57 | + event_map.add(Source()) |
| 58 | + |
| 59 | + def test_size(self): |
| 60 | + event_map = EventMap() |
| 61 | + event_map.add(Source()) |
| 62 | + event_map.add(Source()) |
| 63 | + self.assertEqual(event_map.size, 2) |
| 64 | + |
| 65 | + def test_index(self): |
| 66 | + src_0 = Source() |
| 67 | + src_1 = Source() |
| 68 | + event_map = EventMap() |
| 69 | + event_map.add(src_0) |
| 70 | + event_map.add(src_1) |
| 71 | + self.assertEqual(event_map.index(src_0), 0) |
| 72 | + self.assertEqual(event_map.index(src_1), 1) |
| 73 | + |
| 74 | + def test_index_add_twice(self): |
| 75 | + src = Source() |
| 76 | + event_map = EventMap() |
| 77 | + event_map.add(src) |
| 78 | + event_map.add(src) |
| 79 | + self.assertEqual(event_map.index(src), 0) |
| 80 | + self.assertEqual(event_map.size, 1) |
| 81 | + |
| 82 | + def test_index_wrong(self): |
| 83 | + event_map = EventMap() |
| 84 | + with self.assertRaisesRegex(TypeError, |
| 85 | + r"Event source must be an instance of event.Source, not 'foo'"): |
| 86 | + event_map.index("foo") |
| 87 | + |
| 88 | + def test_index_not_found(self): |
| 89 | + src = Source() |
| 90 | + event_map = EventMap() |
| 91 | + with self.assertRaises(KeyError): |
| 92 | + event_map.index(src) |
| 93 | + |
| 94 | + def test_iter_sources(self): |
| 95 | + src_0 = Source() |
| 96 | + src_1 = Source() |
| 97 | + event_map = EventMap() |
| 98 | + event_map.add(src_0) |
| 99 | + event_map.add(src_1) |
| 100 | + self.assertEqual(list(event_map.sources()), [ |
| 101 | + (src_0, 0), |
| 102 | + (src_1, 1), |
| 103 | + ]) |
| 104 | + |
| 105 | + |
| 106 | +class MonitorTestCase(unittest.TestCase): |
| 107 | + def test_simple(self): |
| 108 | + src_0 = Source() |
| 109 | + src_1 = Source() |
| 110 | + event_map = EventMap() |
| 111 | + event_map.add(src_0) |
| 112 | + event_map.add(src_1) |
| 113 | + dut = Monitor(event_map) |
| 114 | + self.assertEqual(dut.enable.width, 2) |
| 115 | + self.assertEqual(dut.pending.width, 2) |
| 116 | + self.assertEqual(dut.clear.width, 2) |
| 117 | + |
| 118 | + def test_event_map_wrong(self): |
| 119 | + with self.assertRaisesRegex(TypeError, |
| 120 | + r"Event map must be an instance of EventMap, not 'foo'"): |
| 121 | + dut = Monitor("foo") |
| 122 | + |
| 123 | + def test_events(self): |
| 124 | + src_0 = Source(trigger="level") |
| 125 | + src_1 = Source(trigger="rise") |
| 126 | + src_2 = Source(trigger="fall") |
| 127 | + event_map = EventMap() |
| 128 | + event_map.add(src_0) |
| 129 | + event_map.add(src_1) |
| 130 | + event_map.add(src_2) |
| 131 | + dut = Monitor(event_map) |
| 132 | + |
| 133 | + def process(): |
| 134 | + yield src_0.i.eq(1) |
| 135 | + yield src_1.i.eq(0) |
| 136 | + yield src_2.i.eq(1) |
| 137 | + yield |
| 138 | + self.assertEqual((yield src_0.trg), 1) |
| 139 | + self.assertEqual((yield src_1.trg), 0) |
| 140 | + self.assertEqual((yield src_2.trg), 0) |
| 141 | + yield |
| 142 | + self.assertEqual((yield dut.pending), 0b001) |
| 143 | + self.assertEqual((yield dut.irq), 0) |
| 144 | + |
| 145 | + yield dut.enable.eq(0b111) |
| 146 | + yield |
| 147 | + self.assertEqual((yield dut.irq), 1) |
| 148 | + |
| 149 | + yield dut.clear.eq(0b001) |
| 150 | + yield |
| 151 | + self.assertEqual((yield dut.pending), 0b001) |
| 152 | + self.assertEqual((yield dut.irq), 1) |
| 153 | + |
| 154 | + yield src_0.i.eq(0) |
| 155 | + yield |
| 156 | + self.assertEqual((yield src_0.trg), 0) |
| 157 | + self.assertEqual((yield src_1.trg), 0) |
| 158 | + self.assertEqual((yield src_2.trg), 0) |
| 159 | + yield |
| 160 | + self.assertEqual((yield dut.pending), 0b000) |
| 161 | + self.assertEqual((yield dut.irq), 0) |
| 162 | + |
| 163 | + yield src_1.i.eq(1) |
| 164 | + yield |
| 165 | + self.assertEqual((yield src_0.trg), 0) |
| 166 | + self.assertEqual((yield src_1.trg), 1) |
| 167 | + self.assertEqual((yield src_2.trg), 0) |
| 168 | + yield |
| 169 | + self.assertEqual((yield dut.pending), 0b010) |
| 170 | + self.assertEqual((yield dut.irq), 1) |
| 171 | + |
| 172 | + yield src_2.i.eq(0) |
| 173 | + yield |
| 174 | + self.assertEqual((yield src_0.trg), 0) |
| 175 | + self.assertEqual((yield src_1.trg), 0) |
| 176 | + self.assertEqual((yield src_2.trg), 1) |
| 177 | + yield |
| 178 | + self.assertEqual((yield dut.pending), 0b110) |
| 179 | + self.assertEqual((yield dut.irq), 1) |
| 180 | + |
| 181 | + yield dut.clear.eq(0b110) |
| 182 | + yield |
| 183 | + self.assertEqual((yield src_0.trg), 0) |
| 184 | + self.assertEqual((yield src_1.trg), 0) |
| 185 | + self.assertEqual((yield src_2.trg), 0) |
| 186 | + yield |
| 187 | + self.assertEqual((yield dut.pending), 0b000) |
| 188 | + self.assertEqual((yield dut.irq), 0) |
| 189 | + |
| 190 | + simulation_test(dut, process) |
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