From 1bc51d8bb8c4bf65b6c47248bd0edff8ee50d8c9 Mon Sep 17 00:00:00 2001 From: bluncan Date: Mon, 6 Nov 2023 21:58:10 +0200 Subject: [PATCH] ad9081: vck190: Added support for JESD204B ad9209: vck190: Changed serial connections and added reset signals Signed-off-by: Bogdan Luncan --- .../jesd204_versal_gt_adapter_rx/Makefile | 3 +- .../jesd204_versal_gt_adapter_rx.v | 123 +- .../jesd204_versal_gt_adapter_rx_ip.tcl | 11 +- .../jesd204_versal_gt_adapter_rx/lane_align.v | 81 ++ .../jesd204_versal_gt_adapter_tx/Makefile | 2 +- .../jesd204_versal_gt_adapter_tx.v | 58 +- .../jesd204_versal_gt_adapter_tx_ip.tcl | 6 +- .../common/ad9081_fmca_ebz_bd.tcl | 128 +- .../common/versal_transceiver.tcl | 1240 ++++++++++++++--- projects/ad9081_fmca_ebz/vck190/Makefile | 2 +- .../ad9081_fmca_ebz/vck190/system_constr.xdc | 8 +- .../ad9081_fmca_ebz/vck190/system_project.tcl | 44 +- projects/ad9081_fmca_ebz/vck190/system_top.v | 42 +- .../ad9081_fmca_ebz/vck190/timing_constr.xdc | 2 +- projects/ad9209_fmca_ebz/vck190/system_top.v | 40 +- 15 files changed, 1400 insertions(+), 390 deletions(-) create mode 100644 library/jesd204/jesd204_versal_gt_adapter_rx/lane_align.v diff --git a/library/jesd204/jesd204_versal_gt_adapter_rx/Makefile b/library/jesd204/jesd204_versal_gt_adapter_rx/Makefile index 9450aa62c6..6979a6606f 100644 --- a/library/jesd204/jesd204_versal_gt_adapter_rx/Makefile +++ b/library/jesd204/jesd204_versal_gt_adapter_rx/Makefile @@ -1,5 +1,5 @@ #################################################################################### -## Copyright (c) 2018 - 2023 Analog Devices, Inc. +## Copyright (c) 2018 - 2024 Analog Devices, Inc. ### SPDX short identifier: BSD-1-Clause ## Auto-generated, do not modify! #################################################################################### @@ -7,6 +7,7 @@ LIBRARY_NAME := jesd204_versal_gt_adapter_rx GENERIC_DEPS += jesd204_versal_gt_adapter_rx.v +GENERIC_DEPS += lane_align.v XILINX_DEPS += ../jesd204_common/sync_header_align.v XILINX_DEPS += jesd204_versal_gt_adapter_rx_ip.tcl diff --git a/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.v b/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.v index 7e8f38ff17..7669f2efb4 100644 --- a/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.v +++ b/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.v @@ -1,24 +1,41 @@ // *************************************************************************** // *************************************************************************** +<<<<<<< HEAD // Copyright (C) 2017, 2018, 2020-2022, 2024 Analog Devices, Inc. All rights reserved. +======= +// Copyright (C) 2017, 2018, 2020-2024 Analog Devices, Inc. All rights reserved. +>>>>>>> cbd399e80 (ad9081: vck190: Added support for JESD204B) // SPDX short identifier: ADIJESD204 // *************************************************************************** // *************************************************************************** `timescale 1ns/100ps -module jesd204_versal_gt_adapter_rx ( +module jesd204_versal_gt_adapter_rx #( + parameter LINK_MODE = 2 // 1 - 8B10B, 2 - 64B66B +) ( + // Interface to Physical Layer input [127 : 0] rxdata, - input [5 : 0] rxheader, + input [ 5 : 0] rxheader, + input [ 15 : 0] rxctrl0, + input [ 15 : 0] rxctrl1, + input [ 7 : 0] rxctrl2, + input [ 7 : 0] rxctrl3, output rxgearboxslip, - input [1 : 0] rxheadervalid, + input [ 1 : 0] rxheadervalid, + output rxslide, // Interface to Link layer core - output [63:0] rx_data, - output [1:0] rx_header, - output rx_block_sync, + output [ 63 : 0] rx_data, + output [ 3 : 0] rx_charisk, + output [ 3 : 0] rx_disperr, + output [ 3 : 0] rx_notintable, + output [ 1 : 0] rx_header, + output rx_block_sync, + input en_char_align, - input usr_clk + input resetn, + input usr_clk ); wire rxgearboxslip_s; @@ -26,48 +43,78 @@ module jesd204_versal_gt_adapter_rx ( reg [ 1:0] rxheader_d; reg rxgearboxslip_d; reg [ 1:0] rxheadervalid_d; + reg [15:0] rxctrl0_d; + reg [15:0] rxctrl1_d; + reg [ 7:0] rxctrl3_d; always @(posedge usr_clk) begin rxdata_d <= rxdata[63:0]; rxheader_d <= rxheader[1:0]; rxgearboxslip_d <= rxgearboxslip_s; + rxctrl0_d <= rxctrl0; + rxctrl1_d <= rxctrl1; + rxctrl3_d <= rxctrl3; end - // Sync header alignment - wire rx_bitslip_req_s; - reg [5:0] rx_bitslip_done_cnt = 'h0; - always @(posedge usr_clk) begin - if (rx_bitslip_done_cnt[5]) begin - rx_bitslip_done_cnt <= 'b0; - end else if (rx_bitslip_req_s & ~rx_bitslip_done_cnt[5]) begin - rx_bitslip_done_cnt <= rx_bitslip_done_cnt + 1; + generate if (LINK_MODE == 2) begin + // Sync header alignment + wire rx_bitslip_req_s; + reg [5:0] rx_bitslip_done_cnt = 'h0; + always @(posedge usr_clk) begin + if (rx_bitslip_done_cnt[5]) begin + rx_bitslip_done_cnt <= 'b0; + end else if (rx_bitslip_req_s & ~rx_bitslip_done_cnt[5]) begin + rx_bitslip_done_cnt <= rx_bitslip_done_cnt + 1; + end end - end - reg rx_bitslip_req_s_d = 1'b0; - always @(posedge usr_clk) begin - rx_bitslip_req_s_d <= rx_bitslip_req_s; - end + reg rx_bitslip_req_s_d = 1'b0; + always @(posedge usr_clk) begin + rx_bitslip_req_s_d <= rx_bitslip_req_s; + end - assign rxgearboxslip_s = rx_bitslip_req_s & ~rx_bitslip_req_s_d; - assign rxgearboxslip = rxgearboxslip_d; + assign rxgearboxslip_s = rx_bitslip_req_s & ~rx_bitslip_req_s_d; + assign rxgearboxslip = rxgearboxslip_d; - wire [63:0] rxdata_flip; - genvar i; - for (i = 0; i < 64; i=i+1) begin - assign rxdata_flip[63-i] = rxdata_d[i]; - end + wire [63:0] rxdata_flip; + genvar i; + for (i = 0; i < 64; i=i+1) begin + assign rxdata_flip[63-i] = rxdata_d[i]; + end + + // Sync header alignment + sync_header_align i_sync_header_align ( + .clk(usr_clk), + .reset(~rxheadervalid[0]), + // Flip header bits and data + .i_data({rxheader_d[0],rxheader_d[1],rxdata_flip[63:0]}), + .i_slip(rx_bitslip_req_s), + .i_slip_done(rx_bitslip_done_cnt[5]), + .o_data(rx_data), + .o_header(rx_header), + .o_block_sync(rx_block_sync)); + + assign rx_disperr = 4'b0; + assign rx_charisk = 4'b0; + assign rx_notintable = 4'b0; + assign rxslide = 1'b0; + end else begin + assign rx_data = {32'b0, rxdata_d[31:0]}; + assign rx_header = rxheader_d[1:0]; - // Sync header alignment - sync_header_align i_sync_header_align ( - .clk(usr_clk), - .reset(~rxheadervalid[0]), - // Flip header bits and data - .i_data({rxheader_d[0],rxheader_d[1],rxdata_flip[63:0]}), - .i_slip(rx_bitslip_req_s), - .i_slip_done(rx_bitslip_done_cnt[5]), - .o_data(rx_data), - .o_header(rx_header), - .o_block_sync(rx_block_sync)); + assign rx_charisk = rxctrl0_d[3:0]; + assign rx_disperr = rxctrl1_d[3:0]; + assign rx_notintable = rxctrl3_d[3:0]; + assign rx_block_sync = 1'b0; + assign rxgearboxslip = 1'b0; + + lane_align i_lane_align ( + .usr_clk (usr_clk), + .resetn (resetn), + .rxdata (rxdata[31:0]), + .rx_slide (rxslide), + .en_char_align (en_char_align)); + end + endgenerate endmodule diff --git a/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_ip.tcl b/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_ip.tcl index b2f37d867e..97e945cbd0 100644 --- a/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_ip.tcl +++ b/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_ip.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2017-2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIJESD204 ############################################################################### @@ -9,6 +9,7 @@ source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl adi_ip_create jesd204_versal_gt_adapter_rx adi_ip_files jesd204_versal_gt_adapter_rx [list \ jesd204_versal_gt_adapter_rx.v \ + lane_align.v \ ../jesd204_common/sync_header_align.v \ ] @@ -23,6 +24,9 @@ adi_add_bus "RX" "master" \ { \ { "rx_data" "rxdata" } \ { "rx_header" "rxheader" } \ + { "rx_charisk" "rxcharisk"} \ + { "rx_disperr" "rxdisperr"} \ + { "rx_notintable" "rxnotintable"} \ { "rx_block_sync" "rxblock_sync" } \ } @@ -32,6 +36,11 @@ adi_add_bus "RX_GT_IP_Interface" "master" \ { \ { "rxdata" "ch_rxdata" } \ { "rxheader" "ch_rxheader" } \ + { "rxctrl0" "ch_rxctrl0" } \ + { "rxctrl1" "ch_rxctrl1" } \ + { "rxctrl2" "ch_rxctrl2" } \ + { "rxctrl3" "ch_rxctrl3" } \ + { "rxslide" "ch_rxslide" } \ { "rxheadervalid" "ch_rxheadervalid" } \ { "rxgearboxslip" "ch_rxgearboxslip" } \ } diff --git a/library/jesd204/jesd204_versal_gt_adapter_rx/lane_align.v b/library/jesd204/jesd204_versal_gt_adapter_rx/lane_align.v new file mode 100644 index 0000000000..e1e5ac5a43 --- /dev/null +++ b/library/jesd204/jesd204_versal_gt_adapter_rx/lane_align.v @@ -0,0 +1,81 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2024 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +module lane_align ( + input usr_clk, + input resetn, + input [31:0] rxdata, + input en_char_align, + output rx_slide +); + + localparam K_CHARACTER = 32'hBCBCBCBC; + + localparam WAIT_FOR_CHAR_ALIGN = 0; + localparam CHECK_ALIGNMENT = 1; + localparam PULSE_SLIDE = 2; + localparam WAIT_DELAY = 3; + + reg [2:0] state; + reg [2:0] next_state; + reg [5:0] counter; + reg [5:0] next_counter; + wire rx_slide_s; + + always @(negedge resetn or posedge usr_clk) begin + if (!resetn) begin + state <= WAIT_FOR_CHAR_ALIGN; + counter <= 'd0; + end else begin + state <= next_state; + counter <= next_counter; + end + end + + always @(*) begin + next_counter <= counter; + case (state) + WAIT_FOR_CHAR_ALIGN: begin + if (en_char_align) begin + next_state <= CHECK_ALIGNMENT; + end else begin + next_state <= WAIT_FOR_CHAR_ALIGN; + end + end + CHECK_ALIGNMENT: begin + if (rxdata == K_CHARACTER) begin + next_state <= WAIT_FOR_CHAR_ALIGN; + end else begin + next_counter <= 'd0; + next_state <= PULSE_SLIDE; + end + end + PULSE_SLIDE: begin // a pulse is valid only if it takes 2 usr_clk cycles + if (counter == 'd1) begin + next_state <= WAIT_DELAY; + next_counter <= 'd0; + end else begin + next_state <= PULSE_SLIDE; + next_counter <= counter + 1'b1; + end + end + WAIT_DELAY: begin // wait 32 usr_clk cycles between each pulse + if (counter[5]) begin + next_state <= CHECK_ALIGNMENT; + end else begin + next_state <= WAIT_DELAY; + next_counter <= counter + 1'b1; + end + end + endcase + end + + assign rx_slide_s = (state == PULSE_SLIDE)? 1'b1 : 1'b0; + + assign rx_slide = rx_slide_s; + +endmodule diff --git a/library/jesd204/jesd204_versal_gt_adapter_tx/Makefile b/library/jesd204/jesd204_versal_gt_adapter_tx/Makefile index 1fabb1912a..0baea0f93e 100644 --- a/library/jesd204/jesd204_versal_gt_adapter_tx/Makefile +++ b/library/jesd204/jesd204_versal_gt_adapter_tx/Makefile @@ -1,5 +1,5 @@ #################################################################################### -## Copyright (c) 2018 - 2023 Analog Devices, Inc. +## Copyright (c) 2018 - 2024 Analog Devices, Inc. ### SPDX short identifier: BSD-1-Clause ## Auto-generated, do not modify! #################################################################################### diff --git a/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx.v b/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx.v index 9ad7ba7b0e..ad260b9240 100644 --- a/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx.v +++ b/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx.v @@ -1,33 +1,63 @@ // *************************************************************************** // *************************************************************************** +<<<<<<< HEAD // Copyright (C) 2017-2019, 2021, 2024 Analog Devices, Inc. All rights reserved. +======= +// Copyright (C) 2017-2019, 2021-2024 Analog Devices, Inc. All rights reserved. +>>>>>>> cbd399e80 (ad9081: vck190: Added support for JESD204B) // SPDX short identifier: ADIJESD204 // *************************************************************************** // *************************************************************************** `timescale 1ns/100ps -module jesd204_versal_gt_adapter_tx ( - output reg [127 : 0] txdata, - output reg [5 : 0] txheader, - +module jesd204_versal_gt_adapter_tx #( + parameter LINK_MODE = 2 // 1 - 8B10B, 2 - 64B66B +) ( + output [127 : 0] txdata, + output [ 5 : 0] txheader, + output [ 15 : 0] txctrl0, + output [ 15 : 0] txctrl1, + output [ 7 : 0] txctrl2, // Interface to Link layer core - input [63:0] tx_data, - input [1:0] tx_header, + input [ 63 : 0] tx_data, + input [ 1 : 0] tx_header, + input [ 3 : 0] tx_charisk, input usr_clk ); - wire [63:0] tx_data_flip; - genvar i; - for (i = 0; i < 64; i=i+1) begin - assign tx_data_flip[63-i] = tx_data[i]; - end + wire [63:0] txdata_d; + wire [ 5:0] txheader_d; + wire [ 7:0] txctrl2_d; - // Flip header bits and data always @(posedge usr_clk) begin - txdata <= {64'b0, tx_data_flip}; - txheader <= {4'b0, tx_header[0], tx_header[1]}; + txdata_d <= tx_data; + txheader_d <= tx_header; + txctrl2_d <= {4'b0, tx_charisk}; + end + + generate if (LINK_MODE == 2) begin + wire [63:0] tx_data_flip; + genvar i; + for (i = 0; i < 64; i=i+1) begin + assign tx_data_flip[63-i] = txdata_d[i]; + end + + // Flip header bits and data + assign txdata <= {64'b0, tx_data_flip}; + assign txheader <= {4'b0, txheader_d[0], txheader_d[1]}; + + assign txctrl0 = 16'b0; + assign txctrl1 = 16'b0; + assign txctrl2 = 16'b0; + end else begin + assign txdata = {96'b0, txdata_d[31:0]}; + assign txheader = {4'b0, txheader_d}; + assign txctrl0 = 16'b0; + assign txctrl1 = 16'b0; + assign txctrl2 = txctrl2_d; end + endgenerate endmodule diff --git a/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_ip.tcl b/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_ip.tcl index 04fbb58476..91ce07e6c1 100644 --- a/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_ip.tcl +++ b/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_ip.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2017-2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIJESD204 ############################################################################### @@ -22,6 +22,9 @@ adi_add_bus "TX_GT_IP_Interface" "master" \ { \ { "txdata" "ch_txdata" } \ { "txheader" "ch_txheader" } \ + { "txctrl0" "ch_txctrl0" } \ + { "txctrl1" "ch_txctrl1" } \ + { "txctrl2" "ch_txctrl2" } \ } adi_add_bus "TX" "slave" \ @@ -30,6 +33,7 @@ adi_add_bus "TX" "slave" \ { \ { "tx_data" "txdata" } \ { "tx_header" "txheader" } \ + { "tx_charisk" "txcharisk" } \ } ipx::save_core [ipx::current_core] diff --git a/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl b/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl index 71c295c17c..5d02c04d78 100644 --- a/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl +++ b/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl @@ -10,6 +10,7 @@ # # RX_LANE_RATE : Lane rate of the Rx link ( MxFE to FPGA ) # TX_LANE_RATE : Lane rate of the Tx link ( FPGA to MxFE ) +# GENERATE_LINK_CLK : If 1 use the generated link clocks from the physical layer, else use the reference clock as the link clock (versal only) # [RX/TX]_JESD_M : Number of converters per link # [RX/TX]_JESD_L : Number of lanes per link # [RX/TX]_JESD_NP : Number of bits per sample @@ -128,7 +129,7 @@ set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 8 * $TX_DATAPATH_WIDTH / ($T # TODO: Increase the maximum number of quads if necessary set max_num_quads 2 -set num_quads [expr int(ceil(1.0 * $RX_NUM_OF_LANES / 4))] +set num_quads [expr int(round(1.0 * $RX_NUM_OF_LANES / 4))] source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl @@ -142,6 +143,16 @@ set dac_data_width [expr $TX_DMA_SAMPLE_WIDTH*$TX_NUM_OF_CONVERTERS*$TX_SAMPLES_ set dac_dma_data_width $dac_data_width set dac_fifo_address_width [expr int(ceil(log(($dac_fifo_samples_per_converter*$TX_NUM_OF_CONVERTERS) / ($dac_data_width/$TX_DMA_SAMPLE_WIDTH))/log(2)))] +# Common ports +create_bd_port -dir I ref_clk_q0 +create_bd_port -dir I ref_clk_q1 +create_bd_port -dir I tx_device_clk +create_bd_port -dir I rx_device_clk +create_bd_port -dir I rx_sysref_0 +create_bd_port -dir O rx_sync_0 +create_bd_port -dir I tx_sysref_0 +create_bd_port -dir I tx_sync_0 + # common xcvr if {$ADI_PHY_SEL == 1} { ad_ip_instance util_adxcvr util_mxfe_xcvr @@ -182,41 +193,55 @@ if {$ADI_PHY_SEL == 1} { ? $ad_project_params(REF_CLK_RATE) : 375 } ] create_bd_port -dir I gt_reset - create_bd_port -dir I gt_reset_rx_pll_and_datapath - create_bd_port -dir I gt_reset_tx_pll_and_datapath - create_bd_port -dir I gt_reset_rx_datapath - create_bd_port -dir I gt_reset_tx_datapath - create_bd_port -dir O gt_powergood create_bd_port -dir O rx_resetdone create_bd_port -dir O tx_resetdone + create_bd_port -dir O gt_powergood switch $INTF_CFG { "RXTX" { - # Assumption is that number of Tx and Rx lane is the same - create_versal_phy jesd204_phy $TX_NUM_OF_LANES $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $INTF_CFG + create_versal_phy jesd204_phy_rxtx $JESD_MODE $RX_NUM_OF_LANES $TX_NUM_OF_LANES $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $INTF_CFG + set rx_phy jesd204_phy_rxtx + set tx_phy jesd204_phy_rxtx + ad_connect ref_clk_q0 ${rx_phy}/GT_REFCLK + ad_connect gt_reset ${rx_phy}/gtreset_in + ad_connect $sys_cpu_clk ${rx_phy}/s_axi_clk + ad_connect $sys_cpu_resetn ${rx_phy}/s_axi_resetn + ad_connect ${rx_phy}/gtpowergood gt_powergood + ad_connect ${rx_phy}/gtreset_rx_datapath gt_reset_rx_datapath + ad_connect ${rx_phy}/gtreset_tx_datapath gt_reset_tx_datapath + ad_connect ${rx_phy}/gtreset_rx_pll_and_datapath gt_reset_rx_pll_and_datapath + ad_connect ${rx_phy}/gtreset_tx_pll_and_datapath gt_reset_tx_pll_and_datapath + ad_connect ${rx_phy}/rx_resetdone rx_resetdone + ad_connect ${rx_phy}/tx_resetdone tx_resetdone } "RX" { - create_versal_phy jesd204_phy $RX_NUM_OF_LANES $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $INTF_CFG + create_versal_phy jesd204_phy_rx $JESD_MODE $RX_NUM_OF_LANES $RX_NUM_OF_LANES $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $INTF_CFG + set rx_phy jesd204_phy_rx + ad_connect ref_clk_q0 ${rx_phy}/GT_REFCLK + ad_connect gt_reset ${rx_phy}/gtreset_in + ad_connect $sys_cpu_clk ${rx_phy}/s_axi_clk + ad_connect $sys_cpu_resetn ${rx_phy}/s_axi_resetn + ad_connect ${rx_phy}/gtpowergood gt_powergood + ad_connect ${rx_phy}/gtreset_rx_datapath gt_reset_rx_datapath + ad_connect ${rx_phy}/gtreset_rx_pll_and_datapath gt_reset_rx_pll_and_datapath + ad_connect ${rx_phy}/rx_resetdone rx_resetdone } "TX" { - create_versal_phy jesd204_phy $TX_NUM_OF_LANES $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $INTF_CFG + create_versal_phy jesd204_phy_tx $JESD_MODE $TX_NUM_OF_LANES $TX_NUM_OF_LANES $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $INTF_CFG + set tx_phy jesd204_phy_tx + ad_connect ref_clk_q0 ${tx_phy}/GT_REFCLK + ad_connect gt_reset ${tx_phy}/gtreset_in + ad_connect $sys_cpu_clk ${tx_phy}/apb3clk + ad_connect ${rx_phy}/gtpowergood gt_powergood + ad_connect ${rx_phy}/gtreset_tx_datapath gt_reset_tx_datapath + ad_connect ${rx_phy}/gtreset_tx_pll_and_datapath gt_reset_tx_pll_and_datapath + ad_connect ${rx_phy}/tx_resetdone tx_resetdone } } - - ad_connect gt_reset jesd204_phy/gtreset_in - ad_connect gt_reset_rx_datapath jesd204_phy/gtreset_rx_datapath - ad_connect gt_reset_tx_datapath jesd204_phy/gtreset_tx_datapath - ad_connect gt_reset_rx_pll_and_datapath jesd204_phy/gtreset_rx_pll_and_datapath - ad_connect gt_reset_tx_pll_and_datapath jesd204_phy/gtreset_tx_pll_and_datapath - ad_connect gt_powergood jesd204_phy/gtpowergood - ad_connect rx_resetdone jesd204_phy/rx_resetdone - ad_connect tx_resetdone jesd204_phy/tx_resetdone } # Instantiate ADC (Rx) path if {$INTF_CFG != "TX"} { - create_bd_port -dir I rx_device_clk - if {$ADI_PHY_SEL == 1} { ad_ip_instance axi_adxcvr axi_mxfe_rx_xcvr ad_ip_parameter axi_mxfe_rx_xcvr CONFIG.ID 0 @@ -280,8 +305,6 @@ if {$INTF_CFG != "TX"} { # Instantiate DAC (Tx) path if {$INTF_CFG != "RX"} { - create_bd_port -dir I tx_device_clk - if {$ADI_PHY_SEL == 1} { ad_ip_instance axi_adxcvr axi_mxfe_tx_xcvr ad_ip_parameter axi_mxfe_tx_xcvr CONFIG.ID 0 @@ -344,9 +367,6 @@ if {$INTF_CFG != "RX"} { ad_ip_parameter axi_mxfe_tx_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_dma_data_width } -create_bd_port -dir I ref_clk_q0 -create_bd_port -dir I ref_clk_q1 - if {$ADI_PHY_SEL == 1} { for {set i 0} {$i < [expr max($TX_NUM_OF_LANES,$RX_NUM_OF_LANES)]} {incr i} { set quad_index [expr int($i / 4)] @@ -368,38 +388,40 @@ if {$ADI_PHY_SEL == 1} { } } else { ad_connect ref_clk_q0 jesd204_phy/GT_REFCLK - + ad_connect gt_reset jesd204_phy/gtreset_in if {$INTF_CFG != "TX"} { - set rx_link_clock jesd204_phy/rxusrclk_out + set rx_link_clock ${rx_phy}/rxusrclk_out # Connect PHY to Link Layer for {set j 0} {$j < $RX_NUM_OF_LANES} {incr j} { - ad_connect axi_mxfe_rx_jesd/rx_phy${j} jesd204_phy/rx${j} + ad_connect axi_mxfe_rx_jesd/rx_phy${j} ${rx_phy}/rx${j} } ad_connect $rx_link_clock /axi_mxfe_rx_jesd/link_clk ad_connect rx_device_clk /axi_mxfe_rx_jesd/device_clk - create_bd_port -dir I rx_sysref_0 - ad_connect axi_mxfe_rx_jesd/sysref rx_sysref_0 - create_bd_port -dir O rx_sync_0 + ad_connect axi_mxfe_rx_jesd/sysref rx_sysref_0 + if {$JESD_MODE == "8B10B"} { + ad_connect axi_mxfe_rx_jesd/phy_en_char_align ${rx_phy}/en_char_align + ad_connect axi_mxfe_rx_jesd/sync rx_sync_0 + } else { + ad_connect GND ${rx_phy}/en_char_align + } } if {$INTF_CFG != "RX"} { - set tx_link_clock jesd204_phy/txusrclk_out + set tx_link_clock ${tx_phy}/txusrclk_out # Connect PHY to Link Layer for {set j 0} {$j < $TX_NUM_OF_LANES} {incr j} { - ad_connect axi_mxfe_tx_jesd/tx_phy${j} jesd204_phy/tx${j} + ad_connect axi_mxfe_tx_jesd/tx_phy${j} ${tx_phy}/tx${j} } ad_connect $tx_link_clock /axi_mxfe_tx_jesd/link_clk ad_connect tx_device_clk /axi_mxfe_tx_jesd/device_clk - - create_bd_port -dir I tx_sysref_0 ad_connect axi_mxfe_tx_jesd/sysref tx_sysref_0 - - create_bd_port -dir I tx_sync_0 + if {$JESD_MODE == "8B10B"} { + ad_connect axi_mxfe_tx_jesd/sync tx_sync_0 + } } - ad_connect $sys_cpu_clk jesd204_phy/s_axi_clk - ad_connect $sys_cpu_resetn jesd204_phy/s_axi_resetn + ad_connect $sys_cpu_clk jesd204_phy/apb3clk } if {$INTF_CFG != "TX"} { @@ -429,8 +451,8 @@ if {$INTF_CFG != "TX"} { ad_connect rx_mxfe_tpl_core/adc_enable_$i util_mxfe_cpack/enable_$i ad_connect rx_mxfe_tpl_core/adc_data_$i util_mxfe_cpack/fifo_wr_data_$i } - ad_connect rx_mxfe_tpl_core/adc_dovf util_mxfe_cpack/fifo_wr_overflow + ad_connect util_mxfe_cpack/fifo_wr_overflow rx_mxfe_tpl_core/adc_dovf ad_connect util_mxfe_cpack/packed_fifo_wr_data $adc_data_offload_name/s_axis_tdata ad_connect util_mxfe_cpack/packed_fifo_wr_en $adc_data_offload_name/s_axis_tvalid ad_connect $adc_data_offload_name/s_axis_tlast GND @@ -480,7 +502,6 @@ if {$INTF_CFG != "RX"} { # Link Layer to Transport Layer ad_connect tx_mxfe_tpl_core/link axi_mxfe_tx_jesd/tx_data - ad_connect tx_mxfe_tpl_core/dac_valid_0 util_mxfe_upack/fifo_rd_en for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} { ad_connect util_mxfe_upack/fifo_rd_data_$i tx_mxfe_tpl_core/dac_data_$i @@ -531,17 +552,28 @@ if {$ADI_PHY_SEL == 1} { } } else { for {set j 0} {$j < $num_quads} {incr j} { - make_bd_intf_pins_external [get_bd_intf_pins jesd204_phy/GT_Serial_${j}] + if {$INTF_CFG != "TX"} { + create_bd_port -dir I -from 3 -to 0 rx_${j}_p + create_bd_port -dir I -from 3 -to 0 rx_${j}_n + ad_connect rx_${j}_p ${rx_phy}/rx_${j}_p + ad_connect rx_${j}_n ${rx_phy}/rx_${j}_n + } + if {$INTF_CFG != "RX"} { + create_bd_port -dir O -from 3 -to 0 tx_${j}_p + create_bd_port -dir O -from 3 -to 0 tx_${j}_n + ad_connect tx_${j}_p ${rx_phy}/tx_${j}_p + ad_connect tx_${j}_n ${rx_phy}/tx_${j}_n + } } # Unused serial lanes - for {set i $num_quads} {$i < $max_num_quads} {incr i} { + for {set j $num_quads} {$j < $max_num_quads} {incr j} { if {$INTF_CFG != "TX"} { - create_bd_port -dir I -from 3 -to 0 GT_Serial_${i}_0_grx_p - create_bd_port -dir I -from 3 -to 0 GT_Serial_${i}_0_grx_n + create_bd_port -dir I -from 3 -to 0 rx_${j}_p + create_bd_port -dir I -from 3 -to 0 rx_${j}_n } if {$INTF_CFG != "RX"} { - create_bd_port -dir O -from 3 -to 0 GT_Serial_${i}_0_gtx_p - create_bd_port -dir O -from 3 -to 0 GT_Serial_${i}_0_gtx_n + create_bd_port -dir O -from 3 -to 0 tx_${j}_p + create_bd_port -dir O -from 3 -to 0 tx_${j}_n } } } diff --git a/projects/ad9081_fmca_ebz/common/versal_transceiver.tcl b/projects/ad9081_fmca_ebz/common/versal_transceiver.tcl index d4c511213a..5a4f8a86b5 100644 --- a/projects/ad9081_fmca_ebz/common/versal_transceiver.tcl +++ b/projects/ad9081_fmca_ebz/common/versal_transceiver.tcl @@ -3,10 +3,19 @@ ### SPDX short identifier: ADIBSD ############################################################################### +# Parameter description: +# ip_name : The name of the versal phy ip +# rx_num_lanes : The number of used RX lanes for the JESD mode +# tx_num_lanes : The number of used TX lanes for the JESD mode proc create_reset_logic { {ip_name versal_phy} - {num_lanes 4} + {rx_num_lanes 4} + {tx_num_lanes 0} } { + set rx_bridge gt_bridge_ip_0 + set asymmetric_mode [expr $rx_num_lanes != $tx_num_lanes] + set tx_bridge [expr {$asymmetric_mode == 0 ? gt_bridge_ip_0 : gt_bridge_ip_1}] + create_bd_pin -dir I ${ip_name}/gtreset_in create_bd_pin -dir I ${ip_name}/gtreset_rx_pll_and_datapath create_bd_pin -dir I ${ip_name}/gtreset_tx_pll_and_datapath @@ -22,25 +31,24 @@ proc create_reset_logic { ad_connect ${ip_name}/s_axi_clk ${ip_name}/gtreset_sync/out_clk ad_connect ${ip_name}/s_axi_resetn ${ip_name}/gtreset_sync/out_resetn ad_connect ${ip_name}/gtreset_in ${ip_name}/gtreset_sync/in_bits - ad_connect ${ip_name}/gtreset_sync/out_bits ${ip_name}/gt_bridge_ip_0/gtreset_in + ad_connect ${ip_name}/gtreset_sync/out_bits ${ip_name}/${rx_bridge}/gtreset_in + if {$asymmetric_mode} { + ad_connect ${ip_name}/gtreset_sync/out_bits ${ip_name}/${tx_bridge}/gtreset_in + } foreach port {pll_and_datapath datapath} { foreach rx_tx {rx tx} { + set bridge [expr {rx_tx == "rx" ? $rx_bridge : $tx_bridge}] create_bd_cell -type module -reference sync_bits ${ip_name}/gtreset_${rx_tx}_${port}_sync ad_connect ${ip_name}/s_axi_clk ${ip_name}/gtreset_${rx_tx}_${port}_sync/out_clk ad_connect ${ip_name}/s_axi_resetn ${ip_name}/gtreset_${rx_tx}_${port}_sync/out_resetn ad_connect ${ip_name}/gtreset_${rx_tx}_${port} ${ip_name}/gtreset_${rx_tx}_${port}_sync/in_bits - ad_connect ${ip_name}/gtreset_${rx_tx}_${port}_sync/out_bits ${ip_name}/gt_bridge_ip_0/reset_${rx_tx}_${port}_in + ad_connect ${ip_name}/gtreset_${rx_tx}_${port}_sync/out_bits ${ip_name}/${bridge}/reset_${rx_tx}_${port}_in } } - set num_quads [expr int(ceil(1.0 * $num_lanes / 4))] - - for {set j 0} {$j < ${num_lanes}} {incr j} { - set quad_index [expr int($j / 4)] - set ch_index [expr $j % 4] - ad_connect ${ip_name}/gt_bridge_ip_0/pcie_rstb ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_pcierstb - } + set max_lanes [expr max($rx_num_lanes, $tx_num_lanes)] + set num_quads [expr int(ceil(1.0 * $max_lanes / 4))] ad_ip_instance xlconcat ${ip_name}/concat_powergood [list \ NUM_PORTS $num_quads \ @@ -55,30 +63,55 @@ proc create_reset_logic { } ad_connect ${ip_name}/concat_powergood/dout ${ip_name}/and_powergood/Op1 - ad_connect ${ip_name}/and_powergood/Res ${ip_name}/gt_bridge_ip_0/gtpowergood + ad_connect ${ip_name}/and_powergood/Res ${ip_name}/${rx_bridge}/gtpowergood + if {$asymmetric_mode} { + ad_connect ${ip_name}/and_powergood/Res ${ip_name}/${tx_bridge}/gtpowergood + } - for {set j 0} {$j < ${num_lanes}} {incr j} { + for {set j 0} {$j < ${rx_num_lanes}} {incr j} { set quad_index [expr int($j / 4)] set ch_index [expr $j % 4] - ad_connect ${ip_name}/gt_bridge_ip_0/gt_ilo_reset ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_iloreset + ad_connect ${ip_name}/${rx_bridge}/gt_ilo_reset ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_iloreset + } + if {$asymmetric_mode} { + for {set j 0} {$j < ${rx_num_lanes}} {incr j} { + set quad_index [expr int($j / 4)] + set ch_index [expr $j % 4] + ad_connect ${ip_name}/${tx_bridge}/gt_ilo_reset ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_iloreset + } } ad_ip_instance xlconcat ${ip_name}/xlconcat_iloresetdone [list \ - NUM_PORTS ${num_lanes} \ + NUM_PORTS ${rx_num_lanes} \ ] ad_ip_instance util_reduced_logic ${ip_name}/and_iloresetdone [list \ - C_SIZE ${num_lanes} \ + C_SIZE ${rx_num_lanes} \ ] - for {set j 0} {$j < ${num_lanes}} {incr j} { + for {set j 0} {$j < ${rx_num_lanes}} {incr j} { set quad_index [expr int($j / 4)] set ch_index [expr $j % 4] ad_connect ${ip_name}/xlconcat_iloresetdone/In${j} ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_iloresetdone } ad_connect ${ip_name}/xlconcat_iloresetdone/dout ${ip_name}/and_iloresetdone/Op1 - ad_connect ${ip_name}/and_iloresetdone/Res ${ip_name}/gt_bridge_ip_0/ilo_resetdone + ad_connect ${ip_name}/and_iloresetdone/Res ${ip_name}/${rx_bridge}/ilo_resetdone + if {$asymmetric_mode} { + ad_ip_instance xlconcat ${ip_name}/xlconcat_iloresetdone_tx [list \ + NUM_PORTS ${tx_num_lanes} \ + ] + ad_ip_instance util_reduced_logic ${ip_name}/and_iloresetdone_tx [list \ + C_SIZE ${tx_num_lanes} \ + ] + for {set j 0} {$j < ${tx_num_lanes}} {incr j} { + set quad_index [expr int($j / 4)] + set ch_index [expr $j % 4] + ad_connect ${ip_name}/xlconcat_iloresetdone_tx/In${j} ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_iloresetdone + } + ad_connect ${ip_name}/xlconcat_iloresetdone_tx/dout ${ip_name}/and_iloresetdone_tx/Op1 + ad_connect ${ip_name}/and_iloresetdone_tx/Res ${ip_name}/${tx_bridge}/ilo_resetdone + } for {set j 0} {$j < ${num_quads}} {incr j} { - ad_connect ${ip_name}/gt_bridge_ip_0/gt_pll_reset ${ip_name}/gt_quad_base_${j}/hsclk0_lcpllreset - ad_connect ${ip_name}/gt_bridge_ip_0/gt_pll_reset ${ip_name}/gt_quad_base_${j}/hsclk1_lcpllreset + ad_connect ${ip_name}/${rx_bridge}/gt_pll_reset ${ip_name}/gt_quad_base_${j}/hsclk0_lcpllreset + ad_connect ${ip_name}/${rx_bridge}/gt_pll_reset ${ip_name}/gt_quad_base_${j}/hsclk1_lcpllreset } set num_cplllocks [expr 2 * ${num_quads}] @@ -97,28 +130,57 @@ proc create_reset_logic { } ad_connect ${ip_name}/concat_cplllock/dout ${ip_name}/and_cplllock/Op1 - ad_connect ${ip_name}/and_cplllock/Res ${ip_name}/gt_bridge_ip_0/gt_lcpll_lock + ad_connect ${ip_name}/and_cplllock/Res ${ip_name}/${rx_bridge}/gt_lcpll_lock + if {$asymmetric_mode} { + ad_connect ${ip_name}/and_cplllock/Res ${ip_name}/${tx_bridge}/gt_lcpll_lock + } ad_ip_instance xlconcat ${ip_name}/concat_phystatus [list \ - NUM_PORTS ${num_lanes} \ + NUM_PORTS ${rx_num_lanes} \ ] - for {set j 0} {$j < ${num_lanes}} {incr j} { + for {set j 0} {$j < ${rx_num_lanes}} {incr j} { set quad_index [expr int($j / 4)] set ch_index [expr $j % 4] ad_connect ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_phystatus ${ip_name}/concat_phystatus/In${j} } - ad_connect ${ip_name}/concat_phystatus/dout ${ip_name}/gt_bridge_ip_0/ch_phystatus_in + ad_connect ${ip_name}/concat_phystatus/dout ${ip_name}/${rx_bridge}/ch_phystatus_in + if {$asymmetric_mode} { + ad_ip_instance xlconcat ${ip_name}/concat_phystatus_tx [list \ + NUM_PORTS ${rx_num_lanes} \ + ] + for {set j 0} {$j < ${rx_num_lanes}} {incr j} { + set quad_index [expr int($j / 4)] + set ch_index [expr $j % 4] + + ad_connect ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_phystatus ${ip_name}/concat_phystatus_tx/In${j} + } + ad_connect ${ip_name}/concat_phystatus_tx/dout ${ip_name}/${tx_bridge}/ch_phystatus_in + } # Outputs ad_connect ${ip_name}/and_powergood/Res ${ip_name}/gtpowergood - ad_connect ${ip_name}/gt_bridge_ip_0/rx_resetdone_out ${ip_name}/rx_resetdone - ad_connect ${ip_name}/gt_bridge_ip_0/tx_resetdone_out ${ip_name}/tx_resetdone + ad_connect ${ip_name}/${rx_bridge}/rx_resetdone_out ${ip_name}/rx_resetdone + ad_connect ${ip_name}/${tx_bridge}/tx_resetdone_out ${ip_name}/tx_resetdone } +# Parameter description: +# ip_name : The name of the created ip +# jesd_mode : Used physical layer encoder mode +# rx_num_lanes : Number of RX lanes +# tx_num_lanes : Number of TX lanes +# ref_clock : Frequency of reference clock in MHz used in 64B66B mode (LANE_RATE/66) or 8B10B mode (LANE_RATE/40) +# rx_lane_rate : Line rate of the Rx link ( e.g. MxFE to FPGA ) in GHz +# tx_lane_rate : Line rate of the Tx link ( e.g. FPGA to MxFE ) in GHz +# intf_cfg : Direction of the transceivers +# RXTX : Duplex mode +# RX : Rx link only +# TX : Tx link only proc create_versal_phy { {ip_name versal_phy} - {num_lanes 4} + {jesd_mode 64B66B} + {rx_num_lanes 4} + {tx_num_lanes 4} {rx_lane_rate 24.75} {tx_lane_rate 24.75} {ref_clock 375} @@ -126,8 +188,22 @@ proc create_versal_phy { } { set num_quads [expr int(ceil(1.0 * $num_lanes / 4))] - set rx_progdiv_clock [format %.3f [expr $rx_lane_rate * 1000 / 66]] - set tx_progdiv_clock [format %.3f [expr $tx_lane_rate * 1000 / 66]] + set clk_divider [expr { $jesd_mode == "64B66B" ? 66 : 40} ] + set datapath_width [expr { $jesd_mode == "64B66B" ? 64 : 32} ] + set internal_datapath_width [expr { $jesd_mode == "64B66B" ? 64 : 40} ] + set data_encoding [expr { $jesd_mode == "64B66B" ? "64B66B_ASYNC" : "8B10B"} ] + set link_mode [expr { $jesd_mode == "64B66B" ? 2 : 1} ] + set comma_mask [expr { $jesd_mode == "64B66B" ? "0000000000" : "1111111111"} ] + set comma_p_enable [expr { $jesd_mode == "64B66B" ? false : false} ] + set comma_m_enable [expr { $jesd_mode == "64B66B" ? false : false} ] + set num_quads [expr int(ceil(1.0 * max($rx_num_lanes, $tx_num_lanes) / 4))] + set asymmetric_mode [expr { [expr $rx_num_lanes != $tx_num_lanes] ? true : false } ] + # When asymmetric_mode is true it means that the number of lanes on the Rx side is different from the number of lanes on the Tx side + # The 'gt_bridge_ip' can only be configured with the same number of lanes so we need to instantiate two ips, one for the Rx and one for the Tx + # Both 'gt_bridge_ip' will still share the same quad + + set rx_progdiv_clock [format %.3f [expr $rx_lane_rate * 1000 / ${clk_divider}]] + set tx_progdiv_clock [format %.3f [expr $tx_lane_rate * 1000 / ${clk_divider}]] if {$intf_cfg == "RX"} { set gt_direction "SIMPLEX_RX" @@ -143,253 +219,953 @@ proc create_versal_phy { create_bd_cell -type hier ${ip_name} # Common interface + create_bd_pin -dir I ${ip_name}/GT_REFCLK -type clk if {$intf_cfg != "TX"} { create_bd_pin -dir O ${ip_name}/rxusrclk_out -type clk + create_bd_pin -dir I ${ip_name}/resetn + create_bd_pin -dir I ${ip_name}/en_char_align } if {$intf_cfg != "RX"} { create_bd_pin -dir O ${ip_name}/txusrclk_out -type clk } - create_bd_pin -dir I ${ip_name}/GT_REFCLK -type clk - create_bd_pin -dir I ${ip_name}/s_axi_clk -type clk - create_bd_pin -dir I ${ip_name}/s_axi_resetn - ad_ip_instance gt_bridge_ip ${ip_name}/gt_bridge_ip_0 - set_property -dict [list \ - CONFIG.BYPASS_MODE {true} \ - CONFIG.IP_PRESET {GTY-JESD204_64B66B} \ - CONFIG.REG_CONF_INTF {AXI_LITE} \ - CONFIG.IP_GT_DIRECTION ${gt_direction} \ - CONFIG.MASTER_RESET_EN {true} \ - ${no_lanes_property} ${num_lanes} \ - CONFIG.IP_LR0_SETTINGS [list \ - PRESET GTY-JESD204_64B66B \ - INTERNAL_PRESET JESD204_64B66B \ - GT_TYPE GTY \ - GT_DIRECTION $gt_direction \ - TX_LINE_RATE $tx_lane_rate \ - TX_PLL_TYPE LCPLL \ - TX_REFCLK_FREQUENCY $ref_clock \ - TX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ - TX_FRACN_ENABLED true \ - TX_FRACN_NUMERATOR 0 \ - TX_REFCLK_SOURCE R0 \ - TX_DATA_ENCODING 64B66B_ASYNC \ - TX_USER_DATA_WIDTH 64 \ - TX_INT_DATA_WIDTH 64 \ - TX_BUFFER_MODE 1 \ - TX_BUFFER_BYPASS_MODE Fast_Sync \ - TX_PIPM_ENABLE false \ - TX_OUTCLK_SOURCE TXPROGDIVCLK \ - TXPROGDIV_FREQ_ENABLE true \ - TXPROGDIV_FREQ_SOURCE LCPLL \ - TXPROGDIV_FREQ_VAL $tx_progdiv_clock \ - TX_DIFF_SWING_EMPH_MODE CUSTOM \ - TX_64B66B_SCRAMBLER false \ - TX_64B66B_ENCODER false \ - TX_64B66B_CRC false \ - TX_RATE_GROUP A \ - RX_LINE_RATE $rx_lane_rate \ - RX_PLL_TYPE LCPLL \ - RX_REFCLK_FREQUENCY $ref_clock \ - RX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ - RX_FRACN_ENABLED true \ - RX_FRACN_NUMERATOR 0 \ - RX_REFCLK_SOURCE R0 \ - RX_DATA_DECODING 64B66B_ASYNC \ - RX_USER_DATA_WIDTH 64 \ - RX_INT_DATA_WIDTH 64 \ - RX_BUFFER_MODE 1 \ - RX_OUTCLK_SOURCE RXPROGDIVCLK \ - RXPROGDIV_FREQ_ENABLE true \ - RXPROGDIV_FREQ_SOURCE LCPLL \ - RXPROGDIV_FREQ_VAL $rx_progdiv_clock \ - INS_LOSS_NYQ 12 \ - RX_EQ_MODE LPM \ - RX_COUPLING AC \ - RX_TERMINATION PROGRAMMABLE \ - RX_RATE_GROUP A \ - RX_TERMINATION_PROG_VALUE 800 \ - RX_PPM_OFFSET 0 \ - RX_64B66B_DESCRAMBLER false \ - RX_64B66B_DECODER false \ - RX_64B66B_CRC false \ - OOB_ENABLE false \ - RX_COMMA_ALIGN_WORD 1 \ - RX_COMMA_SHOW_REALIGN_ENABLE true \ - PCIE_ENABLE false \ - RX_COMMA_P_ENABLE false \ - RX_COMMA_M_ENABLE false \ - RX_COMMA_DOUBLE_ENABLE false \ - RX_COMMA_P_VAL 0101111100 \ - RX_COMMA_M_VAL 1010000011 \ - RX_COMMA_MASK 0000000000 \ - RX_SLIDE_MODE OFF \ - RX_SSC_PPM 0 \ - RX_CB_NUM_SEQ 0 \ - RX_CB_LEN_SEQ 1 \ - RX_CB_MAX_SKEW 1 \ - RX_CB_MAX_LEVEL 1 \ - RX_CB_MASK_0_0 false \ - RX_CB_VAL_0_0 00000000 \ - RX_CB_K_0_0 false \ - RX_CB_DISP_0_0 false \ - RX_CB_MASK_0_1 false \ - RX_CB_VAL_0_1 00000000 \ - RX_CB_K_0_1 false \ - RX_CB_DISP_0_1 false \ - RX_CB_MASK_0_2 false \ - RX_CB_VAL_0_2 00000000 \ - RX_CB_K_0_2 false \ - RX_CB_DISP_0_2 false \ - RX_CB_MASK_0_3 false \ - RX_CB_VAL_0_3 00000000 \ - RX_CB_K_0_3 false \ - RX_CB_DISP_0_3 false \ - RX_CB_MASK_1_0 false \ - RX_CB_VAL_1_0 00000000 \ - RX_CB_K_1_0 false \ - RX_CB_DISP_1_0 false \ - RX_CB_MASK_1_1 false \ - RX_CB_VAL_1_1 00000000 \ - RX_CB_K_1_1 false \ - RX_CB_DISP_1_1 false \ - RX_CB_MASK_1_2 false \ - RX_CB_VAL_1_2 00000000 \ - RX_CB_K_1_2 false \ - RX_CB_DISP_1_2 false \ - RX_CB_MASK_1_3 false \ - RX_CB_VAL_1_3 00000000 \ - RX_CB_K_1_3 false \ - RX_CB_DISP_1_3 false \ - RX_CC_NUM_SEQ 0 \ - RX_CC_LEN_SEQ 1 \ - RX_CC_PERIODICITY 5000 \ - RX_CC_KEEP_IDLE DISABLE \ - RX_CC_PRECEDENCE ENABLE \ - RX_CC_REPEAT_WAIT 0 \ - RX_CC_VAL 00000000000000000000000000000000000000000000000000000000000000000000000000000000 \ - RX_CC_MASK_0_0 false \ - RX_CC_VAL_0_0 00000000 \ - RX_CC_K_0_0 false \ - RX_CC_DISP_0_0 false \ - RX_CC_MASK_0_1 false \ - RX_CC_VAL_0_1 00000000 \ - RX_CC_K_0_1 false \ - RX_CC_DISP_0_1 false \ - RX_CC_MASK_0_2 false \ - RX_CC_VAL_0_2 00000000 \ - RX_CC_K_0_2 false \ - RX_CC_DISP_0_2 false \ - RX_CC_MASK_0_3 false \ - RX_CC_VAL_0_3 00000000 \ - RX_CC_K_0_3 false \ - RX_CC_DISP_0_3 false \ - RX_CC_MASK_1_0 false \ - RX_CC_VAL_1_0 00000000 \ - RX_CC_K_1_0 false \ - RX_CC_DISP_1_0 false \ - RX_CC_MASK_1_1 false \ - RX_CC_VAL_1_1 00000000 \ - RX_CC_K_1_1 false \ - RX_CC_DISP_1_1 false \ - RX_CC_MASK_1_2 false \ - RX_CC_VAL_1_2 00000000 \ - RX_CC_K_1_2 false \ - RX_CC_DISP_1_2 false \ - RX_CC_MASK_1_3 false \ - RX_CC_VAL_1_3 00000000 \ - RX_CC_K_1_3 false \ - RX_CC_DISP_1_3 false \ - PCIE_USERCLK2_FREQ 250 \ - PCIE_USERCLK_FREQ 250 \ - RX_JTOL_FC 10 \ - RX_JTOL_LF_SLOPE -20 \ - RX_BUFFER_BYPASS_MODE Fast_Sync \ - RX_BUFFER_BYPASS_MODE_LANE MULTI \ - RX_BUFFER_RESET_ON_CB_CHANGE ENABLE \ - RX_BUFFER_RESET_ON_COMMAALIGN DISABLE \ - RX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ - TX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ - RESET_SEQUENCE_INTERVAL 0 \ - RX_COMMA_PRESET NONE \ - RX_COMMA_VALID_ONLY 0 \ - ] \ - ] [get_bd_cells ${ip_name}/gt_bridge_ip_0] + set rx_bridge gt_bridge_ip_0 + set tx_bridge gt_bridge_ip_0 + if {$asymmetric_mode} { + ad_ip_instance gt_bridge_ip ${ip_name}/gt_bridge_ip_1 + set tx_bridge gt_bridge_ip_1 + } + if {!$asymmetric_mode} { + set num_lanes [expr max($rx_num_lanes, $tx_num_lanes)] + set_property -dict [list \ + CONFIG.BYPASS_MODE {true} \ + CONFIG.IP_PRESET GTY-JESD204_${jesd_mode} \ + CONFIG.IP_GT_DIRECTION ${gt_direction} \ + ${no_lanes_property} ${num_lanes} \ + CONFIG.IP_LR0_SETTINGS [list \ + PRESET GTY-JESD204_${jesd_mode} \ + INTERNAL_PRESET JESD204_${jesd_mode} \ + GT_TYPE GTY \ + GT_DIRECTION $gt_direction \ + TX_LINE_RATE $tx_lane_rate \ + TX_PLL_TYPE LCPLL \ + TX_REFCLK_FREQUENCY $ref_clock \ + TX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ + TX_FRACN_ENABLED true \ + TX_FRACN_NUMERATOR 0 \ + TX_REFCLK_SOURCE R0 \ + TX_DATA_ENCODING $data_encoding \ + TX_USER_DATA_WIDTH $datapath_width \ + TX_INT_DATA_WIDTH $internal_datapath_width \ + TX_BUFFER_MODE 1 \ + TX_BUFFER_BYPASS_MODE Fast_Sync \ + TX_PIPM_ENABLE false \ + TX_OUTCLK_SOURCE TXPROGDIVCLK \ + TXPROGDIV_FREQ_ENABLE true \ + TXPROGDIV_FREQ_SOURCE LCPLL \ + TXPROGDIV_FREQ_VAL $tx_progdiv_clock \ + TX_DIFF_SWING_EMPH_MODE CUSTOM \ + TX_64B66B_SCRAMBLER false \ + TX_64B66B_ENCODER false \ + TX_64B66B_CRC false \ + TX_RATE_GROUP A \ + RX_LINE_RATE $rx_lane_rate \ + RX_PLL_TYPE LCPLL \ + RX_REFCLK_FREQUENCY $ref_clock \ + RX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ + RX_FRACN_ENABLED true \ + RX_FRACN_NUMERATOR 0 \ + RX_REFCLK_SOURCE R0 \ + RX_DATA_DECODING $data_encoding \ + RX_USER_DATA_WIDTH $datapath_width \ + RX_INT_DATA_WIDTH $internal_datapath_width \ + RX_BUFFER_MODE 1 \ + RX_OUTCLK_SOURCE RXPROGDIVCLK \ + RXPROGDIV_FREQ_ENABLE true \ + RXPROGDIV_FREQ_SOURCE LCPLL \ + RXPROGDIV_FREQ_VAL $rx_progdiv_clock \ + INS_LOSS_NYQ 12 \ + RX_EQ_MODE LPM \ + RX_COUPLING AC \ + RX_TERMINATION PROGRAMMABLE \ + RX_RATE_GROUP A \ + RX_TERMINATION_PROG_VALUE 800 \ + RX_PPM_OFFSET 0 \ + RX_64B66B_DESCRAMBLER false \ + RX_64B66B_DECODER false \ + RX_64B66B_CRC false \ + OOB_ENABLE false \ + RX_COMMA_ALIGN_WORD 1 \ + RX_COMMA_SHOW_REALIGN_ENABLE false \ + PCIE_ENABLE false \ + RX_COMMA_P_ENABLE $comma_p_enable \ + RX_COMMA_M_ENABLE $comma_m_enable \ + RX_COMMA_DOUBLE_ENABLE false \ + RX_COMMA_P_VAL 0101111100 \ + RX_COMMA_M_VAL 1010000011 \ + RX_COMMA_MASK $comma_mask \ + RX_SLIDE_MODE PCS \ + RX_SSC_PPM 0 \ + RX_CB_NUM_SEQ 0 \ + RX_CB_LEN_SEQ 1 \ + RX_CB_MAX_SKEW 1 \ + RX_CB_MAX_LEVEL 1 \ + RX_CB_MASK_0_0 false \ + RX_CB_VAL_0_0 00000000 \ + RX_CB_K_0_0 false \ + RX_CB_DISP_0_0 false \ + RX_CB_MASK_0_1 false \ + RX_CB_VAL_0_1 00000000 \ + RX_CB_K_0_1 false \ + RX_CB_DISP_0_1 false \ + RX_CB_MASK_0_2 false \ + RX_CB_VAL_0_2 00000000 \ + RX_CB_K_0_2 false \ + RX_CB_DISP_0_2 false \ + RX_CB_MASK_0_3 false \ + RX_CB_VAL_0_3 00000000 \ + RX_CB_K_0_3 false \ + RX_CB_DISP_0_3 false \ + RX_CB_MASK_1_0 false \ + RX_CB_VAL_1_0 00000000 \ + RX_CB_K_1_0 false \ + RX_CB_DISP_1_0 false \ + RX_CB_MASK_1_1 false \ + RX_CB_VAL_1_1 00000000 \ + RX_CB_K_1_1 false \ + RX_CB_DISP_1_1 false \ + RX_CB_MASK_1_2 false \ + RX_CB_VAL_1_2 00000000 \ + RX_CB_K_1_2 false \ + RX_CB_DISP_1_2 false \ + RX_CB_MASK_1_3 false \ + RX_CB_VAL_1_3 00000000 \ + RX_CB_K_1_3 false \ + RX_CB_DISP_1_3 false \ + RX_CC_NUM_SEQ 0 \ + RX_CC_LEN_SEQ 1 \ + RX_CC_PERIODICITY 5000 \ + RX_CC_KEEP_IDLE DISABLE \ + RX_CC_PRECEDENCE ENABLE \ + RX_CC_REPEAT_WAIT 0 \ + RX_CC_VAL 00000000000000000000000000000000000000000000000000000000000000000000000000000000 \ + RX_CC_MASK_0_0 false \ + RX_CC_VAL_0_0 00000000 \ + RX_CC_K_0_0 false \ + RX_CC_DISP_0_0 false \ + RX_CC_MASK_0_1 false \ + RX_CC_VAL_0_1 00000000 \ + RX_CC_K_0_1 false \ + RX_CC_DISP_0_1 false \ + RX_CC_MASK_0_2 false \ + RX_CC_VAL_0_2 00000000 \ + RX_CC_K_0_2 false \ + RX_CC_DISP_0_2 false \ + RX_CC_MASK_0_3 false \ + RX_CC_VAL_0_3 00000000 \ + RX_CC_K_0_3 false \ + RX_CC_DISP_0_3 false \ + RX_CC_MASK_1_0 false \ + RX_CC_VAL_1_0 00000000 \ + RX_CC_K_1_0 false \ + RX_CC_DISP_1_0 false \ + RX_CC_MASK_1_1 false \ + RX_CC_VAL_1_1 00000000 \ + RX_CC_K_1_1 false \ + RX_CC_DISP_1_1 false \ + RX_CC_MASK_1_2 false \ + RX_CC_VAL_1_2 00000000 \ + RX_CC_K_1_2 false \ + RX_CC_DISP_1_2 false \ + RX_CC_MASK_1_3 false \ + RX_CC_VAL_1_3 00000000 \ + RX_CC_K_1_3 false \ + RX_CC_DISP_1_3 false \ + PCIE_USERCLK2_FREQ 250 \ + PCIE_USERCLK_FREQ 250 \ + RX_JTOL_FC 10 \ + RX_JTOL_LF_SLOPE -20 \ + RX_BUFFER_BYPASS_MODE Fast_Sync \ + RX_BUFFER_BYPASS_MODE_LANE MULTI \ + RX_BUFFER_RESET_ON_CB_CHANGE ENABLE \ + RX_BUFFER_RESET_ON_COMMAALIGN DISABLE \ + RX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ + TX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ + RESET_SEQUENCE_INTERVAL 0 \ + RX_COMMA_PRESET NONE \ + RX_COMMA_VALID_ONLY 0 \ + ] \ + ] [get_bd_cells ${ip_name}/${rx_bridge}] + } else { + set_property -dict [list \ + CONFIG.BYPASS_MODE {true} \ + CONFIG.IP_PRESET GTY-JESD204_${jesd_mode} \ + CONFIG.IP_GT_DIRECTION {SIMPLEX_RX} \ + CONFIG.IP_NO_OF_RX_LANES ${rx_num_lanes} \ + CONFIG.IP_LR0_SETTINGS [list \ + PRESET GTY-JESD204_${jesd_mode} \ + INTERNAL_PRESET JESD204_${jesd_mode} \ + GT_TYPE GTY \ + GT_DIRECTION SIMPLEX_RX \ + TX_LINE_RATE $tx_lane_rate \ + TX_PLL_TYPE LCPLL \ + TX_REFCLK_FREQUENCY $ref_clock \ + TX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ + TX_FRACN_ENABLED true \ + TX_FRACN_NUMERATOR 0 \ + TX_REFCLK_SOURCE R0 \ + TX_DATA_ENCODING $data_encoding \ + TX_USER_DATA_WIDTH $datapath_width \ + TX_INT_DATA_WIDTH $internal_datapath_width \ + TX_BUFFER_MODE 1 \ + TX_BUFFER_BYPASS_MODE Fast_Sync \ + TX_PIPM_ENABLE false \ + TX_OUTCLK_SOURCE TXPROGDIVCLK \ + TXPROGDIV_FREQ_ENABLE true \ + TXPROGDIV_FREQ_SOURCE LCPLL \ + TXPROGDIV_FREQ_VAL $tx_progdiv_clock \ + TX_DIFF_SWING_EMPH_MODE CUSTOM \ + TX_64B66B_SCRAMBLER false \ + TX_64B66B_ENCODER false \ + TX_64B66B_CRC false \ + TX_RATE_GROUP A \ + RX_LINE_RATE $rx_lane_rate \ + RX_PLL_TYPE LCPLL \ + RX_REFCLK_FREQUENCY $ref_clock \ + RX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ + RX_FRACN_ENABLED true \ + RX_FRACN_NUMERATOR 0 \ + RX_REFCLK_SOURCE R0 \ + RX_DATA_DECODING $data_encoding \ + RX_USER_DATA_WIDTH $datapath_width \ + RX_INT_DATA_WIDTH $internal_datapath_width \ + RX_BUFFER_MODE 1 \ + RX_OUTCLK_SOURCE RXPROGDIVCLK \ + RXPROGDIV_FREQ_ENABLE true \ + RXPROGDIV_FREQ_SOURCE LCPLL \ + RXPROGDIV_FREQ_VAL $rx_progdiv_clock \ + INS_LOSS_NYQ 12 \ + RX_EQ_MODE LPM \ + RX_COUPLING AC \ + RX_TERMINATION PROGRAMMABLE \ + RX_RATE_GROUP A \ + RX_TERMINATION_PROG_VALUE 800 \ + RX_PPM_OFFSET 0 \ + RX_64B66B_DESCRAMBLER false \ + RX_64B66B_DECODER false \ + RX_64B66B_CRC false \ + OOB_ENABLE false \ + RX_COMMA_ALIGN_WORD 1 \ + RX_COMMA_SHOW_REALIGN_ENABLE false \ + PCIE_ENABLE false \ + RX_COMMA_P_ENABLE $comma_p_enable \ + RX_COMMA_M_ENABLE $comma_m_enable \ + RX_COMMA_DOUBLE_ENABLE false \ + RX_COMMA_P_VAL 0101111100 \ + RX_COMMA_M_VAL 1010000011 \ + RX_COMMA_MASK $comma_mask \ + RX_SLIDE_MODE PCS \ + RX_SSC_PPM 0 \ + RX_CB_NUM_SEQ 0 \ + RX_CB_LEN_SEQ 1 \ + RX_CB_MAX_SKEW 1 \ + RX_CB_MAX_LEVEL 1 \ + RX_CB_MASK_0_0 false \ + RX_CB_VAL_0_0 00000000 \ + RX_CB_K_0_0 false \ + RX_CB_DISP_0_0 false \ + RX_CB_MASK_0_1 false \ + RX_CB_VAL_0_1 00000000 \ + RX_CB_K_0_1 false \ + RX_CB_DISP_0_1 false \ + RX_CB_MASK_0_2 false \ + RX_CB_VAL_0_2 00000000 \ + RX_CB_K_0_2 false \ + RX_CB_DISP_0_2 false \ + RX_CB_MASK_0_3 false \ + RX_CB_VAL_0_3 00000000 \ + RX_CB_K_0_3 false \ + RX_CB_DISP_0_3 false \ + RX_CB_MASK_1_0 false \ + RX_CB_VAL_1_0 00000000 \ + RX_CB_K_1_0 false \ + RX_CB_DISP_1_0 false \ + RX_CB_MASK_1_1 false \ + RX_CB_VAL_1_1 00000000 \ + RX_CB_K_1_1 false \ + RX_CB_DISP_1_1 false \ + RX_CB_MASK_1_2 false \ + RX_CB_VAL_1_2 00000000 \ + RX_CB_K_1_2 false \ + RX_CB_DISP_1_2 false \ + RX_CB_MASK_1_3 false \ + RX_CB_VAL_1_3 00000000 \ + RX_CB_K_1_3 false \ + RX_CB_DISP_1_3 false \ + RX_CC_NUM_SEQ 0 \ + RX_CC_LEN_SEQ 1 \ + RX_CC_PERIODICITY 5000 \ + RX_CC_KEEP_IDLE DISABLE \ + RX_CC_PRECEDENCE ENABLE \ + RX_CC_REPEAT_WAIT 0 \ + RX_CC_VAL 00000000000000000000000000000000000000000000000000000000000000000000000000000000 \ + RX_CC_MASK_0_0 false \ + RX_CC_VAL_0_0 00000000 \ + RX_CC_K_0_0 false \ + RX_CC_DISP_0_0 false \ + RX_CC_MASK_0_1 false \ + RX_CC_VAL_0_1 00000000 \ + RX_CC_K_0_1 false \ + RX_CC_DISP_0_1 false \ + RX_CC_MASK_0_2 false \ + RX_CC_VAL_0_2 00000000 \ + RX_CC_K_0_2 false \ + RX_CC_DISP_0_2 false \ + RX_CC_MASK_0_3 false \ + RX_CC_VAL_0_3 00000000 \ + RX_CC_K_0_3 false \ + RX_CC_DISP_0_3 false \ + RX_CC_MASK_1_0 false \ + RX_CC_VAL_1_0 00000000 \ + RX_CC_K_1_0 false \ + RX_CC_DISP_1_0 false \ + RX_CC_MASK_1_1 false \ + RX_CC_VAL_1_1 00000000 \ + RX_CC_K_1_1 false \ + RX_CC_DISP_1_1 false \ + RX_CC_MASK_1_2 false \ + RX_CC_VAL_1_2 00000000 \ + RX_CC_K_1_2 false \ + RX_CC_DISP_1_2 false \ + RX_CC_MASK_1_3 false \ + RX_CC_VAL_1_3 00000000 \ + RX_CC_K_1_3 false \ + RX_CC_DISP_1_3 false \ + PCIE_USERCLK2_FREQ 250 \ + PCIE_USERCLK_FREQ 250 \ + RX_JTOL_FC 10 \ + RX_JTOL_LF_SLOPE -20 \ + RX_BUFFER_BYPASS_MODE Fast_Sync \ + RX_BUFFER_BYPASS_MODE_LANE MULTI \ + RX_BUFFER_RESET_ON_CB_CHANGE ENABLE \ + RX_BUFFER_RESET_ON_COMMAALIGN DISABLE \ + RX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ + TX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ + RESET_SEQUENCE_INTERVAL 0 \ + RX_COMMA_PRESET NONE \ + RX_COMMA_VALID_ONLY 0 \ + ] \ + ] [get_bd_cells ${ip_name}/${rx_bridge}] + + set_property -dict [list \ + CONFIG.BYPASS_MODE {true} \ + CONFIG.IP_PRESET GTY-JESD204_${jesd_mode} \ + CONFIG.IP_GT_DIRECTION {SIMPLEX_TX} \ + CONFIG.IP_NO_OF_TX_LANES ${tx_num_lanes} \ + CONFIG.IP_LR0_SETTINGS [list \ + PRESET GTY-JESD204_${jesd_mode} \ + INTERNAL_PRESET JESD204_${jesd_mode} \ + GT_TYPE GTY \ + GT_DIRECTION SIMPLEX_TX \ + TX_LINE_RATE $tx_lane_rate \ + TX_PLL_TYPE LCPLL \ + TX_REFCLK_FREQUENCY $ref_clock \ + TX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ + TX_FRACN_ENABLED true \ + TX_FRACN_NUMERATOR 0 \ + TX_REFCLK_SOURCE R0 \ + TX_DATA_ENCODING $data_encoding \ + TX_USER_DATA_WIDTH $datapath_width \ + TX_INT_DATA_WIDTH $internal_datapath_width \ + TX_BUFFER_MODE 1 \ + TX_BUFFER_BYPASS_MODE Fast_Sync \ + TX_PIPM_ENABLE false \ + TX_OUTCLK_SOURCE TXPROGDIVCLK \ + TXPROGDIV_FREQ_ENABLE true \ + TXPROGDIV_FREQ_SOURCE LCPLL \ + TXPROGDIV_FREQ_VAL $tx_progdiv_clock \ + TX_DIFF_SWING_EMPH_MODE CUSTOM \ + TX_64B66B_SCRAMBLER false \ + TX_64B66B_ENCODER false \ + TX_64B66B_CRC false \ + TX_RATE_GROUP A \ + RX_LINE_RATE $rx_lane_rate \ + RX_PLL_TYPE LCPLL \ + RX_REFCLK_FREQUENCY $ref_clock \ + RX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ + RX_FRACN_ENABLED true \ + RX_FRACN_NUMERATOR 0 \ + RX_REFCLK_SOURCE R0 \ + RX_DATA_DECODING $data_encoding \ + RX_USER_DATA_WIDTH $datapath_width \ + RX_INT_DATA_WIDTH $internal_datapath_width \ + RX_BUFFER_MODE 1 \ + RX_OUTCLK_SOURCE RXPROGDIVCLK \ + RXPROGDIV_FREQ_ENABLE true \ + RXPROGDIV_FREQ_SOURCE LCPLL \ + RXPROGDIV_FREQ_VAL $rx_progdiv_clock \ + INS_LOSS_NYQ 12 \ + RX_EQ_MODE LPM \ + RX_COUPLING AC \ + RX_TERMINATION PROGRAMMABLE \ + RX_RATE_GROUP A \ + RX_TERMINATION_PROG_VALUE 800 \ + RX_PPM_OFFSET 0 \ + RX_64B66B_DESCRAMBLER false \ + RX_64B66B_DECODER false \ + RX_64B66B_CRC false \ + OOB_ENABLE false \ + RX_COMMA_ALIGN_WORD 1 \ + RX_COMMA_SHOW_REALIGN_ENABLE false \ + PCIE_ENABLE false \ + RX_COMMA_P_ENABLE $comma_p_enable \ + RX_COMMA_M_ENABLE $comma_m_enable \ + RX_COMMA_DOUBLE_ENABLE false \ + RX_COMMA_P_VAL 0101111100 \ + RX_COMMA_M_VAL 1010000011 \ + RX_COMMA_MASK $comma_mask \ + RX_SLIDE_MODE PCS \ + RX_SSC_PPM 0 \ + RX_CB_NUM_SEQ 0 \ + RX_CB_LEN_SEQ 1 \ + RX_CB_MAX_SKEW 1 \ + RX_CB_MAX_LEVEL 1 \ + RX_CB_MASK_0_0 false \ + RX_CB_VAL_0_0 00000000 \ + RX_CB_K_0_0 false \ + RX_CB_DISP_0_0 false \ + RX_CB_MASK_0_1 false \ + RX_CB_VAL_0_1 00000000 \ + RX_CB_K_0_1 false \ + RX_CB_DISP_0_1 false \ + RX_CB_MASK_0_2 false \ + RX_CB_VAL_0_2 00000000 \ + RX_CB_K_0_2 false \ + RX_CB_DISP_0_2 false \ + RX_CB_MASK_0_3 false \ + RX_CB_VAL_0_3 00000000 \ + RX_CB_K_0_3 false \ + RX_CB_DISP_0_3 false \ + RX_CB_MASK_1_0 false \ + RX_CB_VAL_1_0 00000000 \ + RX_CB_K_1_0 false \ + RX_CB_DISP_1_0 false \ + RX_CB_MASK_1_1 false \ + RX_CB_VAL_1_1 00000000 \ + RX_CB_K_1_1 false \ + RX_CB_DISP_1_1 false \ + RX_CB_MASK_1_2 false \ + RX_CB_VAL_1_2 00000000 \ + RX_CB_K_1_2 false \ + RX_CB_DISP_1_2 false \ + RX_CB_MASK_1_3 false \ + RX_CB_VAL_1_3 00000000 \ + RX_CB_K_1_3 false \ + RX_CB_DISP_1_3 false \ + RX_CC_NUM_SEQ 0 \ + RX_CC_LEN_SEQ 1 \ + RX_CC_PERIODICITY 5000 \ + RX_CC_KEEP_IDLE DISABLE \ + RX_CC_PRECEDENCE ENABLE \ + RX_CC_REPEAT_WAIT 0 \ + RX_CC_VAL 00000000000000000000000000000000000000000000000000000000000000000000000000000000 \ + RX_CC_MASK_0_0 false \ + RX_CC_VAL_0_0 00000000 \ + RX_CC_K_0_0 false \ + RX_CC_DISP_0_0 false \ + RX_CC_MASK_0_1 false \ + RX_CC_VAL_0_1 00000000 \ + RX_CC_K_0_1 false \ + RX_CC_DISP_0_1 false \ + RX_CC_MASK_0_2 false \ + RX_CC_VAL_0_2 00000000 \ + RX_CC_K_0_2 false \ + RX_CC_DISP_0_2 false \ + RX_CC_MASK_0_3 false \ + RX_CC_VAL_0_3 00000000 \ + RX_CC_K_0_3 false \ + RX_CC_DISP_0_3 false \ + RX_CC_MASK_1_0 false \ + RX_CC_VAL_1_0 00000000 \ + RX_CC_K_1_0 false \ + RX_CC_DISP_1_0 false \ + RX_CC_MASK_1_1 false \ + RX_CC_VAL_1_1 00000000 \ + RX_CC_K_1_1 false \ + RX_CC_DISP_1_1 false \ + RX_CC_MASK_1_2 false \ + RX_CC_VAL_1_2 00000000 \ + RX_CC_K_1_2 false \ + RX_CC_DISP_1_2 false \ + RX_CC_MASK_1_3 false \ + RX_CC_VAL_1_3 00000000 \ + RX_CC_K_1_3 false \ + RX_CC_DISP_1_3 false \ + PCIE_USERCLK2_FREQ 250 \ + PCIE_USERCLK_FREQ 250 \ + RX_JTOL_FC 10 \ + RX_JTOL_LF_SLOPE -20 \ + RX_BUFFER_BYPASS_MODE Fast_Sync \ + RX_BUFFER_BYPASS_MODE_LANE MULTI \ + RX_BUFFER_RESET_ON_CB_CHANGE ENABLE \ + RX_BUFFER_RESET_ON_COMMAALIGN DISABLE \ + RX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ + TX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ + RESET_SEQUENCE_INTERVAL 0 \ + RX_COMMA_PRESET NONE \ + RX_COMMA_VALID_ONLY 0 \ + ] \ + ] [get_bd_cells ${ip_name}/${tx_bridge}] + } for {set j 0} {$j < $num_quads} {incr j} { ad_ip_instance gt_quad_base ${ip_name}/gt_quad_base_${j} set_property -dict [list \ CONFIG.REG_CONF_INTF.VALUE_MODE {MANUAL} \ CONFIG.REG_CONF_INTF {AXI_LITE} \ - CONFIG.PROT0_GT_DIRECTION ${gt_direction} \ ] [get_bd_cells ${ip_name}/gt_quad_base_${j}] + if {!$asymmetric_mode} { + set_property -dict [list \ + CONFIG.REG_CONF_INTF.VALUE_MODE {MANUAL} \ + ] [get_bd_cells ${ip_name}/gt_quad_base_${j}] + } else { + # When we have multiple protocols (different number of lanes on Rx and Tx) we have to manually set the protocols to pass design validation + set_property -dict [list \ + CONFIG.PROT1_LR0_SETTINGS.VALUE_MODE MANUAL \ + CONFIG.GT_TYPE.VALUE_MODE AUTO \ + CONFIG.PROT0_RX_MASTERCLK_SRC.VALUE_MODE MANUAL \ + CONFIG.PROT1_TX_MASTERCLK_SRC.VALUE_MODE MANUAL \ + CONFIG.PROT0_TX_MASTERCLK_SRC.VALUE_MODE MANUAL \ + CONFIG.PROT1_PRESET.VALUE_MODE MANUAL \ + CONFIG.PROT1_ENABLE.VALUE_MODE MANUAL \ + CONFIG.PROT0_PRESET.VALUE_MODE MANUAL \ + CONFIG.PROT0_GT_DIRECTION.VALUE_MODE MANUAL \ + CONFIG.TX0_LANE_SEL.VALUE_MODE AUTO \ + CONFIG.PROT0_NO_OF_LANES.VALUE_MODE MANUAL \ + CONFIG.PROT0_NO_OF_RX_LANES.VALUE_MODE MANUAL \ + CONFIG.PROT1_NO_OF_TX_LANES.VALUE_MODE MANUAL \ + CONFIG.PROT1_GT_DIRECTION.VALUE_MODE MANUAL \ + CONFIG.PROT0_LR0_SETTINGS.VALUE_MODE MANUAL \ + ] [get_bd_cells ${ip_name}/gt_quad_base_${j}] - if {$intf_cfg != "TX" && $j == 0} { - ad_ip_instance bufg_gt ${ip_name}/bufg_gt_rx_${j} - ad_connect ${ip_name}/gt_quad_base_${j}/ch0_rxoutclk ${ip_name}/bufg_gt_rx_${j}/outclk - ad_connect ${ip_name}/gt_bridge_ip_0/rx_clr_out ${ip_name}/bufg_gt_rx_${j}/gt_bufgtclr - } - if {$intf_cfg != "RX" && $j == 0} { - ad_ip_instance bufg_gt ${ip_name}/bufg_gt_tx_${j} - ad_connect ${ip_name}/gt_quad_base_${j}/ch0_txoutclk ${ip_name}/bufg_gt_tx_${j}/outclk - ad_connect ${ip_name}/gt_bridge_ip_0/tx_clr_out ${ip_name}/bufg_gt_tx_${j}/gt_bufgtclr + set_property -dict [list \ + CONFIG.PROT0_GT_DIRECTION {SIMPLEX_RX} \ + CONFIG.PROT0_LR0_SETTINGS [list \ + PRESET GTY-JESD204_${jesd_mode} \ + INTERNAL_PRESET JESD204_${jesd_mode} \ + GT_TYPE GTY \ + GT_DIRECTION {SIMPLEX_RX} \ + TX_LINE_RATE $tx_lane_rate \ + TX_PLL_TYPE LCPLL \ + TX_REFCLK_FREQUENCY $ref_clock \ + TX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ + TX_FRACN_ENABLED true \ + TX_FRACN_NUMERATOR 0 \ + TX_REFCLK_SOURCE R0 \ + TX_DATA_ENCODING $data_encoding \ + TX_USER_DATA_WIDTH $datapath_width \ + TX_INT_DATA_WIDTH $internal_datapath_width \ + TX_BUFFER_MODE 1 \ + TX_BUFFER_BYPASS_MODE Fast_Sync \ + TX_PIPM_ENABLE false \ + TX_OUTCLK_SOURCE TXPROGDIVCLK \ + TXPROGDIV_FREQ_ENABLE true \ + TXPROGDIV_FREQ_SOURCE LCPLL \ + TXPROGDIV_FREQ_VAL $tx_progdiv_clock \ + TX_DIFF_SWING_EMPH_MODE CUSTOM \ + TX_64B66B_SCRAMBLER false \ + TX_64B66B_ENCODER false \ + TX_64B66B_CRC false \ + TX_RATE_GROUP A \ + RX_LINE_RATE $rx_lane_rate \ + RX_PLL_TYPE LCPLL \ + RX_REFCLK_FREQUENCY $ref_clock \ + RX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ + RX_FRACN_ENABLED true \ + RX_FRACN_NUMERATOR 0 \ + RX_REFCLK_SOURCE R0 \ + RX_DATA_DECODING $data_encoding \ + RX_USER_DATA_WIDTH $datapath_width \ + RX_INT_DATA_WIDTH $internal_datapath_width \ + RX_BUFFER_MODE 1 \ + RX_OUTCLK_SOURCE RXPROGDIVCLK \ + RXPROGDIV_FREQ_ENABLE true \ + RXPROGDIV_FREQ_SOURCE LCPLL \ + RXPROGDIV_FREQ_VAL $rx_progdiv_clock \ + INS_LOSS_NYQ 12 \ + RX_EQ_MODE LPM \ + RX_COUPLING AC \ + RX_TERMINATION PROGRAMMABLE \ + RX_RATE_GROUP A \ + RX_TERMINATION_PROG_VALUE 800 \ + RX_PPM_OFFSET 0 \ + RX_64B66B_DESCRAMBLER false \ + RX_64B66B_DECODER false \ + RX_64B66B_CRC false \ + OOB_ENABLE false \ + RX_COMMA_ALIGN_WORD 1 \ + RX_COMMA_SHOW_REALIGN_ENABLE false \ + PCIE_ENABLE false \ + RX_COMMA_P_ENABLE $comma_p_enable \ + RX_COMMA_M_ENABLE $comma_m_enable \ + RX_COMMA_DOUBLE_ENABLE false \ + RX_COMMA_P_VAL 0101111100 \ + RX_COMMA_M_VAL 1010000011 \ + RX_COMMA_MASK $comma_mask \ + RX_SLIDE_MODE PCS \ + RX_SSC_PPM 0 \ + RX_CB_NUM_SEQ 0 \ + RX_CB_LEN_SEQ 1 \ + RX_CB_MAX_SKEW 1 \ + RX_CB_MAX_LEVEL 1 \ + RX_CB_MASK_0_0 false \ + RX_CB_VAL_0_0 00000000 \ + RX_CB_K_0_0 false \ + RX_CB_DISP_0_0 false \ + RX_CB_MASK_0_1 false \ + RX_CB_VAL_0_1 00000000 \ + RX_CB_K_0_1 false \ + RX_CB_DISP_0_1 false \ + RX_CB_MASK_0_2 false \ + RX_CB_VAL_0_2 00000000 \ + RX_CB_K_0_2 false \ + RX_CB_DISP_0_2 false \ + RX_CB_MASK_0_3 false \ + RX_CB_VAL_0_3 00000000 \ + RX_CB_K_0_3 false \ + RX_CB_DISP_0_3 false \ + RX_CB_MASK_1_0 false \ + RX_CB_VAL_1_0 00000000 \ + RX_CB_K_1_0 false \ + RX_CB_DISP_1_0 false \ + RX_CB_MASK_1_1 false \ + RX_CB_VAL_1_1 00000000 \ + RX_CB_K_1_1 false \ + RX_CB_DISP_1_1 false \ + RX_CB_MASK_1_2 false \ + RX_CB_VAL_1_2 00000000 \ + RX_CB_K_1_2 false \ + RX_CB_DISP_1_2 false \ + RX_CB_MASK_1_3 false \ + RX_CB_VAL_1_3 00000000 \ + RX_CB_K_1_3 false \ + RX_CB_DISP_1_3 false \ + RX_CC_NUM_SEQ 0 \ + RX_CC_LEN_SEQ 1 \ + RX_CC_PERIODICITY 5000 \ + RX_CC_KEEP_IDLE DISABLE \ + RX_CC_PRECEDENCE ENABLE \ + RX_CC_REPEAT_WAIT 0 \ + RX_CC_VAL 00000000000000000000000000000000000000000000000000000000000000000000000000000000 \ + RX_CC_MASK_0_0 false \ + RX_CC_VAL_0_0 00000000 \ + RX_CC_K_0_0 false \ + RX_CC_DISP_0_0 false \ + RX_CC_MASK_0_1 false \ + RX_CC_VAL_0_1 00000000 \ + RX_CC_K_0_1 false \ + RX_CC_DISP_0_1 false \ + RX_CC_MASK_0_2 false \ + RX_CC_VAL_0_2 00000000 \ + RX_CC_K_0_2 false \ + RX_CC_DISP_0_2 false \ + RX_CC_MASK_0_3 false \ + RX_CC_VAL_0_3 00000000 \ + RX_CC_K_0_3 false \ + RX_CC_DISP_0_3 false \ + RX_CC_MASK_1_0 false \ + RX_CC_VAL_1_0 00000000 \ + RX_CC_K_1_0 false \ + RX_CC_DISP_1_0 false \ + RX_CC_MASK_1_1 false \ + RX_CC_VAL_1_1 00000000 \ + RX_CC_K_1_1 false \ + RX_CC_DISP_1_1 false \ + RX_CC_MASK_1_2 false \ + RX_CC_VAL_1_2 00000000 \ + RX_CC_K_1_2 false \ + RX_CC_DISP_1_2 false \ + RX_CC_MASK_1_3 false \ + RX_CC_VAL_1_3 00000000 \ + RX_CC_K_1_3 false \ + RX_CC_DISP_1_3 false \ + PCIE_USERCLK2_FREQ 250 \ + PCIE_USERCLK_FREQ 250 \ + RX_JTOL_FC 10 \ + RX_JTOL_LF_SLOPE -20 \ + RX_BUFFER_BYPASS_MODE Fast_Sync \ + RX_BUFFER_BYPASS_MODE_LANE MULTI \ + RX_BUFFER_RESET_ON_CB_CHANGE ENABLE \ + RX_BUFFER_RESET_ON_COMMAALIGN DISABLE \ + RX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ + TX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ + RESET_SEQUENCE_INTERVAL 0 \ + RX_COMMA_PRESET NONE \ + RX_COMMA_VALID_ONLY 0 \ + ] \ + CONFIG.PROT0_NO_OF_RX_LANES $rx_num_lanes \ + CONFIG.PROT0_PRESET GTY-JESD204_${jesd_mode} \ + CONFIG.PROT1_ENABLE {true} \ + CONFIG.PROT1_GT_DIRECTION {SIMPLEX_TX} \ + CONFIG.PROT1_LR0_SETTINGS [list \ + PRESET GTY-JESD204_${jesd_mode} \ + INTERNAL_PRESET JESD204_${jesd_mode} \ + GT_TYPE GTY \ + GT_DIRECTION {SIMPLEX_TX} \ + TX_LINE_RATE $tx_lane_rate \ + TX_PLL_TYPE LCPLL \ + TX_REFCLK_FREQUENCY $ref_clock \ + TX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ + TX_FRACN_ENABLED true \ + TX_FRACN_NUMERATOR 0 \ + TX_REFCLK_SOURCE R0 \ + TX_DATA_ENCODING $data_encoding \ + TX_USER_DATA_WIDTH $datapath_width \ + TX_INT_DATA_WIDTH $internal_datapath_width \ + TX_BUFFER_MODE 1 \ + TX_BUFFER_BYPASS_MODE Fast_Sync \ + TX_PIPM_ENABLE false \ + TX_OUTCLK_SOURCE TXPROGDIVCLK \ + TXPROGDIV_FREQ_ENABLE true \ + TXPROGDIV_FREQ_SOURCE LCPLL \ + TXPROGDIV_FREQ_VAL $tx_progdiv_clock \ + TX_DIFF_SWING_EMPH_MODE CUSTOM \ + TX_64B66B_SCRAMBLER false \ + TX_64B66B_ENCODER false \ + TX_64B66B_CRC false \ + TX_RATE_GROUP A \ + RX_LINE_RATE $rx_lane_rate \ + RX_PLL_TYPE LCPLL \ + RX_REFCLK_FREQUENCY $ref_clock \ + RX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ + RX_FRACN_ENABLED true \ + RX_FRACN_NUMERATOR 0 \ + RX_REFCLK_SOURCE R0 \ + RX_DATA_DECODING $data_encoding \ + RX_USER_DATA_WIDTH $datapath_width \ + RX_INT_DATA_WIDTH $internal_datapath_width \ + RX_BUFFER_MODE 1 \ + RX_OUTCLK_SOURCE RXPROGDIVCLK \ + RXPROGDIV_FREQ_ENABLE true \ + RXPROGDIV_FREQ_SOURCE LCPLL \ + RXPROGDIV_FREQ_VAL $rx_progdiv_clock \ + INS_LOSS_NYQ 12 \ + RX_EQ_MODE LPM \ + RX_COUPLING AC \ + RX_TERMINATION PROGRAMMABLE \ + RX_RATE_GROUP A \ + RX_TERMINATION_PROG_VALUE 800 \ + RX_PPM_OFFSET 0 \ + RX_64B66B_DESCRAMBLER false \ + RX_64B66B_DECODER false \ + RX_64B66B_CRC false \ + OOB_ENABLE false \ + RX_COMMA_ALIGN_WORD 1 \ + RX_COMMA_SHOW_REALIGN_ENABLE false \ + PCIE_ENABLE false \ + RX_COMMA_P_ENABLE $comma_p_enable \ + RX_COMMA_M_ENABLE $comma_m_enable \ + RX_COMMA_DOUBLE_ENABLE false \ + RX_COMMA_P_VAL 0101111100 \ + RX_COMMA_M_VAL 1010000011 \ + RX_COMMA_MASK $comma_mask \ + RX_SLIDE_MODE PCS \ + RX_SSC_PPM 0 \ + RX_CB_NUM_SEQ 0 \ + RX_CB_LEN_SEQ 1 \ + RX_CB_MAX_SKEW 1 \ + RX_CB_MAX_LEVEL 1 \ + RX_CB_MASK_0_0 false \ + RX_CB_VAL_0_0 00000000 \ + RX_CB_K_0_0 false \ + RX_CB_DISP_0_0 false \ + RX_CB_MASK_0_1 false \ + RX_CB_VAL_0_1 00000000 \ + RX_CB_K_0_1 false \ + RX_CB_DISP_0_1 false \ + RX_CB_MASK_0_2 false \ + RX_CB_VAL_0_2 00000000 \ + RX_CB_K_0_2 false \ + RX_CB_DISP_0_2 false \ + RX_CB_MASK_0_3 false \ + RX_CB_VAL_0_3 00000000 \ + RX_CB_K_0_3 false \ + RX_CB_DISP_0_3 false \ + RX_CB_MASK_1_0 false \ + RX_CB_VAL_1_0 00000000 \ + RX_CB_K_1_0 false \ + RX_CB_DISP_1_0 false \ + RX_CB_MASK_1_1 false \ + RX_CB_VAL_1_1 00000000 \ + RX_CB_K_1_1 false \ + RX_CB_DISP_1_1 false \ + RX_CB_MASK_1_2 false \ + RX_CB_VAL_1_2 00000000 \ + RX_CB_K_1_2 false \ + RX_CB_DISP_1_2 false \ + RX_CB_MASK_1_3 false \ + RX_CB_VAL_1_3 00000000 \ + RX_CB_K_1_3 false \ + RX_CB_DISP_1_3 false \ + RX_CC_NUM_SEQ 0 \ + RX_CC_LEN_SEQ 1 \ + RX_CC_PERIODICITY 5000 \ + RX_CC_KEEP_IDLE DISABLE \ + RX_CC_PRECEDENCE ENABLE \ + RX_CC_REPEAT_WAIT 0 \ + RX_CC_VAL 00000000000000000000000000000000000000000000000000000000000000000000000000000000 \ + RX_CC_MASK_0_0 false \ + RX_CC_VAL_0_0 00000000 \ + RX_CC_K_0_0 false \ + RX_CC_DISP_0_0 false \ + RX_CC_MASK_0_1 false \ + RX_CC_VAL_0_1 00000000 \ + RX_CC_K_0_1 false \ + RX_CC_DISP_0_1 false \ + RX_CC_MASK_0_2 false \ + RX_CC_VAL_0_2 00000000 \ + RX_CC_K_0_2 false \ + RX_CC_DISP_0_2 false \ + RX_CC_MASK_0_3 false \ + RX_CC_VAL_0_3 00000000 \ + RX_CC_K_0_3 false \ + RX_CC_DISP_0_3 false \ + RX_CC_MASK_1_0 false \ + RX_CC_VAL_1_0 00000000 \ + RX_CC_K_1_0 false \ + RX_CC_DISP_1_0 false \ + RX_CC_MASK_1_1 false \ + RX_CC_VAL_1_1 00000000 \ + RX_CC_K_1_1 false \ + RX_CC_DISP_1_1 false \ + RX_CC_MASK_1_2 false \ + RX_CC_VAL_1_2 00000000 \ + RX_CC_K_1_2 false \ + RX_CC_DISP_1_2 false \ + RX_CC_MASK_1_3 false \ + RX_CC_VAL_1_3 00000000 \ + RX_CC_K_1_3 false \ + RX_CC_DISP_1_3 false \ + PCIE_USERCLK2_FREQ 250 \ + PCIE_USERCLK_FREQ 250 \ + RX_JTOL_FC 10 \ + RX_JTOL_LF_SLOPE -20 \ + RX_BUFFER_BYPASS_MODE Fast_Sync \ + RX_BUFFER_BYPASS_MODE_LANE MULTI \ + RX_BUFFER_RESET_ON_CB_CHANGE ENABLE \ + RX_BUFFER_RESET_ON_COMMAALIGN DISABLE \ + RX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ + TX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ + RESET_SEQUENCE_INTERVAL 0 \ + RX_COMMA_PRESET NONE \ + RX_COMMA_VALID_ONLY 0 \ + ] \ + CONFIG.PROT1_NO_OF_TX_LANES $tx_num_lanes \ + CONFIG.PROT1_PRESET GTY-JESD204_${jesd_mode} \ + ] [get_bd_cells ${ip_name}/gt_quad_base_${j}] + + for {set i 0} {$i < 4} {incr i} { + set_property -dict [list \ + CONFIG.TX${i}_LANE_SEL.VALUE_MODE MANUAL \ + CONFIG.RX${i}_LANE_SEL.VALUE_MODE MANUAL \ + ] [get_bd_cells ${ip_name}/gt_quad_base_${j}] + } } - create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 ${ip_name}/GT_Serial_${j} - ad_connect ${ip_name}/gt_quad_base_${j}/GT_Serial ${ip_name}/GT_Serial_${j} + if {$intf_cfg != "TX"} { + # Share the link clock generated by the first quad + if {$j == 0} { + ad_ip_instance bufg_gt ${ip_name}/bufg_gt_rx + ad_connect ${ip_name}/gt_quad_base_0/ch0_rxoutclk ${ip_name}/bufg_gt_rx/outclk + ad_connect ${ip_name}/${rx_bridge}/rx_clr_out ${ip_name}/bufg_gt_rx/gt_bufgtclr + ad_connect ${ip_name}/${rx_bridge}/rxusrclk_out ${ip_name}/rxusrclk_out + } + create_bd_pin -dir I -from 3 -to 0 ${ip_name}/rx_${j}_p + create_bd_pin -dir I -from 3 -to 0 ${ip_name}/rx_${j}_n + ad_connect ${ip_name}/gt_quad_base_${j}/rxp ${ip_name}/rx_${j}_p + ad_connect ${ip_name}/gt_quad_base_${j}/rxn ${ip_name}/rx_${j}_n + } + if {$intf_cfg != "RX"} { + # Share the link clock generated by the first quad + if {$j == 0} { + ad_ip_instance bufg_gt ${ip_name}/bufg_gt_tx + ad_connect ${ip_name}/gt_quad_base_0/ch0_txoutclk ${ip_name}/bufg_gt_tx/outclk + ad_connect ${ip_name}/${tx_bridge}/tx_clr_out ${ip_name}/bufg_gt_tx/gt_bufgtclr + ad_connect ${ip_name}/${tx_bridge}/txusrclk_out ${ip_name}/txusrclk_out + } + create_bd_pin -dir O -from 3 -to 0 ${ip_name}/tx_${j}_p + create_bd_pin -dir O -from 3 -to 0 ${ip_name}/tx_${j}_n + ad_connect ${ip_name}/gt_quad_base_${j}/txp ${ip_name}/tx_${j}_p + ad_connect ${ip_name}/gt_quad_base_${j}/txn ${ip_name}/tx_${j}_n + } } if {$intf_cfg != "TX"} { - ad_connect ${ip_name}/bufg_gt_rx_0/usrclk ${ip_name}/gt_bridge_ip_0/gt_rxusrclk - ad_connect ${ip_name}/gt_bridge_ip_0/rxusrclk_out ${ip_name}/rxusrclk_out - - for {set j 0} {$j < $num_lanes} {incr j} { + for {set j 0} {$j < $rx_num_lanes} {incr j} { set quad_index [expr int($j / 4)] set rx_index [expr $j % 4] - ad_ip_instance jesd204_versal_gt_adapter_rx ${ip_name}/rx_adapt_${j} - ad_connect ${ip_name}/rx_adapt_${j}/RX_GT_IP_Interface ${ip_name}/gt_bridge_ip_0/GT_RX${j}_EXT - ad_connect ${ip_name}/gt_bridge_ip_0/GT_RX${j} ${ip_name}/gt_quad_base_${quad_index}/RX${rx_index}_GT_IP_Interface + ad_connect ${ip_name}/bufg_gt_rx/usrclk ${ip_name}/gt_quad_base_${i}/ch${j}_rxusrclk + + ad_ip_instance jesd204_versal_gt_adapter_rx ${ip_name}/rx_adapt_${j} [list \ + LINK_MODE $link_mode \ + ] + ad_connect ${ip_name}/rx_adapt_${j}/RX_GT_IP_Interface ${ip_name}/${rx_bridge}/GT_RX${j}_EXT + ad_connect ${ip_name}/${rx_bridge}/GT_RX${j} ${ip_name}/gt_quad_base_${quad_index}/RX${rx_index}_GT_IP_Interface create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 ${ip_name}/rx${j} ad_connect ${ip_name}/rx${j} ${ip_name}/rx_adapt_${j}/RX + ad_connect ${ip_name}/rx_adapt_${j}/usr_clk ${ip_name}/bufg_gt_rx/usrclk + ad_connect ${ip_name}/rx_adapt_${j}/resetn ${ip_name}/resetn + ad_connect ${ip_name}/rx_adapt_${j}/en_char_align ${ip_name}/en_char_align - ad_connect ${ip_name}/bufg_gt_rx_0/usrclk ${ip_name}/rx_adapt_${j}/usr_clk + set_property CONFIG.RX${rx_index}_LANE_SEL {PROT0} [get_bd_cells ${ip_name}/gt_quad_base_${quad_index}] } } if {$intf_cfg != "RX"} { - ad_connect ${ip_name}/bufg_gt_tx_0/usrclk ${ip_name}/gt_bridge_ip_0/gt_txusrclk - ad_connect ${ip_name}/gt_bridge_ip_0/txusrclk_out ${ip_name}/txusrclk_out - - for {set j 0} {$j < $num_lanes} {incr j} { + for {set j 0} {$j < $tx_num_lanes} {incr j} { set quad_index [expr int($j / 4)] set tx_index [expr $j % 4] - ad_ip_instance jesd204_versal_gt_adapter_tx ${ip_name}/tx_adapt_${j} - ad_connect ${ip_name}/tx_adapt_${j}/TX_GT_IP_Interface ${ip_name}/gt_bridge_ip_0/GT_TX${j}_EXT - ad_connect ${ip_name}/gt_bridge_ip_0/GT_TX${j} ${ip_name}/gt_quad_base_${quad_index}/TX${tx_index}_GT_IP_Interface + ad_connect ${ip_name}/bufg_gt_tx/usrclk ${ip_name}/gt_quad_base_${i}/ch${j}_txusrclk + + ad_ip_instance jesd204_versal_gt_adapter_tx ${ip_name}/tx_adapt_${j} [list \ + LINK_MODE $link_mode \ + ] + ad_connect ${ip_name}/tx_adapt_${j}/TX_GT_IP_Interface ${ip_name}/${tx_bridge}/GT_TX${j}_EXT + ad_connect ${ip_name}/${tx_bridge}/GT_TX${j} ${ip_name}/gt_quad_base_${quad_index}/TX${tx_index}_GT_IP_Interface create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 ${ip_name}/tx${j} ad_connect ${ip_name}/tx${j} ${ip_name}/tx_adapt_${j}/TX + ad_connect ${ip_name}/tx_adapt_${j}/usr_clk ${ip_name}/bufg_gt_tx/usrclk - ad_connect ${ip_name}/bufg_gt_tx_0/usrclk ${ip_name}/tx_adapt_${j}/usr_clk + if {!$asymmetric_mode} { + set_property CONFIG.TX${tx_index}_LANE_SEL {PROT0} [get_bd_cells ${ip_name}/gt_quad_base_${quad_index}] + } else { + set_property CONFIG.TX${tx_index}_LANE_SEL {PROT1} [get_bd_cells ${ip_name}/gt_quad_base_${quad_index}] + } } } - for {set i 0} {$i < $num_quads} {incr i} { - for {set j 0} {$j < 4} {incr j} { - if {$intf_cfg != "TX"} { - ad_connect ${ip_name}/bufg_gt_rx_0/usrclk ${ip_name}/gt_quad_base_${i}/ch${j}_rxusrclk - } - if {$intf_cfg != "RX"} { - ad_connect ${ip_name}/bufg_gt_tx_0/usrclk ${ip_name}/gt_quad_base_${i}/ch${j}_txusrclk - } - } + # Map unused quad lanes as unconnected + set max_num_of_lanes [expr $num_quads * 4] + for {set j $rx_num_lanes} {$j < $max_num_of_lanes} {incr j} { + set quad_index [expr $j / 4] + set lane_index [expr $j % 4] + set_property CONFIG.RX${lane_index}_LANE_SEL {unconnected} [get_bd_cells ${ip_name}/gt_quad_base_${quad_index}] + } + for {set j $tx_num_lanes} {$j < $max_num_of_lanes} {incr j} { + set quad_index [expr $j / 4] + set lane_index [expr $j % 4] + set_property CONFIG.TX${lane_index}_LANE_SEL {unconnected} [get_bd_cells ${ip_name}/gt_quad_base_${quad_index}] } # Clocks - ad_connect ${ip_name}/s_axi_clk ${ip_name}/gt_bridge_ip_0/apb3clk + ad_connect ${ip_name}/s_axi_clk ${ip_name}/${rx_bridge}/apb3clk + if {$asymmetric_mode} { + ad_connect ${ip_name}/s_axi_clk ${ip_name}/${tx_bridge}/apb3clk + } for {set j 0} {$j < $num_quads} {incr j} { ad_connect ${ip_name}/GT_REFCLK ${ip_name}/gt_quad_base_${j}/GT_REFCLK0 ad_connect ${ip_name}/s_axi_clk ${ip_name}/gt_quad_base_${j}/s_axi_lite_clk @@ -397,5 +1173,5 @@ proc create_versal_phy { } # Instantiate reset helper logic - create_reset_logic $ip_name $num_lanes + create_reset_logic $ip_name $rx_num_lanes $tx_num_lanes } diff --git a/projects/ad9081_fmca_ebz/vck190/Makefile b/projects/ad9081_fmca_ebz/vck190/Makefile index f445e1455f..14af9a41f1 100644 --- a/projects/ad9081_fmca_ebz/vck190/Makefile +++ b/projects/ad9081_fmca_ebz/vck190/Makefile @@ -1,5 +1,5 @@ #################################################################################### -## Copyright (c) 2018 - 2023 Analog Devices, Inc. +## Copyright (c) 2018 - 2024 Analog Devices, Inc. ### SPDX short identifier: BSD-1-Clause ## Auto-generated, do not modify! #################################################################################### diff --git a/projects/ad9081_fmca_ebz/vck190/system_constr.xdc b/projects/ad9081_fmca_ebz/vck190/system_constr.xdc index b44f395551..3014616e2c 100644 --- a/projects/ad9081_fmca_ebz/vck190/system_constr.xdc +++ b/projects/ad9081_fmca_ebz/vck190/system_constr.xdc @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -7,7 +7,7 @@ ## mxfe # -set_property -dict {PACKAGE_PIN BB16 IOSTANDARD LVCMOS15 } [get_ports agc0[0] ] ; ## FMC0_LA17_CC_P IO_L13P_T2L_N0_GC_QBC_67 +set_property -dict {PACKAGE_PIN BB16 IOSTANDARD LVCMOS15 } [get_ports agc0[0] ] ; ## FMC0_LA17_CC_P IO_L13P_T2L_N0_GC_QBC_67 set_property -dict {PACKAGE_PIN BC16 IOSTANDARD LVCMOS15 } [get_ports agc0[1] ] ; ## FMC0_LA17_CC_N IO_L13N_T2L_N1_GC_QBC_67 set_property -dict {PACKAGE_PIN BE17 IOSTANDARD LVCMOS15 } [get_ports agc1[0] ] ; ## FMC0_LA18_CC_P IO_L16P_T2U_N6_QBC_AD3P_67 set_property -dict {PACKAGE_PIN BD17 IOSTANDARD LVCMOS15 } [get_ports agc1[1] ] ; ## FMC0_LA18_CC_N IO_L16N_T2U_N7_QBC_AD3N_67 @@ -15,8 +15,8 @@ set_property -dict {PACKAGE_PIN BE16 IOSTANDARD LVCMOS15 set_property -dict {PACKAGE_PIN BF17 IOSTANDARD LVCMOS15 } [get_ports agc2[1] ] ; ## FMC0_LA20_N IO_L22N_T3U_N7_DBC_AD0N_67 set_property -dict {PACKAGE_PIN BE19 IOSTANDARD LVCMOS15 } [get_ports agc3[0] ] ; ## FMC0_LA21_P IO_L21P_T3L_N4_AD8P_67 set_property -dict {PACKAGE_PIN BD19 IOSTANDARD LVCMOS15 } [get_ports agc3[1] ] ; ## FMC0_LA21_N IO_L21N_T3L_N5_AD8N_67 -set_property -dict {PACKAGE_PIN BD24 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports clkin10_n ] ; ## FMC0_CLK2_IO_N IO_L13N_T2L_N1_GC_QBC_66 -set_property -dict {PACKAGE_PIN BD23 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports clkin10_p ] ; ## FMC0_CLK2_IO_P IO_L13P_T2L_N0_GC_QBC_66 +set_property -dict {PACKAGE_PIN BD24 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports clkin10_n ] ; ## FMC0_CLK2_IO_N IO_L13N_T2L_N1_GC_QBC_66 +set_property -dict {PACKAGE_PIN BD23 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports clkin10_p ] ; ## FMC0_CLK2_IO_P IO_L13P_T2L_N0_GC_QBC_66 set_property -dict {PACKAGE_PIN AP18 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports clkin6_n ] ; ## FMC0_CLK1_M2C_N IO_L12N_T1U_N11_GC_67 set_property -dict {PACKAGE_PIN AP19 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports clkin6_p ] ; ## FMC0_CLK1_M2C_P IO_L12P_T1U_N10_GC_67 set_property -dict {PACKAGE_PIN M14 } [get_ports fpga_refclk_in_n ] ; ## FMC0_GBTCLK0_M2C_N MGTREFCLK0N_229 diff --git a/projects/ad9081_fmca_ebz/vck190/system_project.tcl b/projects/ad9081_fmca_ebz/vck190/system_project.tcl index 02a6341276..d2e7ff9c5b 100644 --- a/projects/ad9081_fmca_ebz/vck190/system_project.tcl +++ b/projects/ad9081_fmca_ebz/vck190/system_project.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2019-2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -19,12 +19,12 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # # Parameter description: # JESD_MODE : Used link layer encoder mode -# 64B66B - 64b66b link layer defined in JESD 204C, uses Xilinx IP as Physical layer -# 8B10B - 8b10b link layer defined in JESD 204B, uses ADI IP as Physical layer +# 64B66B - 64b66b link layer defined in JESD 204C, uses AMD IP as Physical layer +# 8B10B - 8b10b link layer defined in JESD 204B, uses AMD IP as Physical layer # # RX_LANE_RATE : Line rate of the Rx link ( MxFE to FPGA ) # TX_LANE_RATE : Line rate of the Tx link ( FPGA to MxFE ) -# REF_CLK_RATE : Frequency of reference clock in MHz used in 64B66B mode +# REF_CLK_RATE : Frequency of reference clock in MHz used in 64B66B mode (LANE_RATE/66) or 8B10B mode (LANE_RATE/40) # [RX/TX]_JESD_M : Number of converters per link # [RX/TX]_JESD_L : Number of lanes per link # [RX/TX]_JESD_S : Number of samples per frame @@ -32,25 +32,26 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # [RX/TX]_NUM_LINKS : Number of links, matches numer of MxFE devices # [RX/TX]_KS_PER_CHANNEL : Number of samples stored in internal buffers in kilosamples per converter (M) -# make JESD_MODE=64B66B RX_LANE_RATE=24.75 TX_LANE_RATE=24.75 RX_JESD_M=8 RX_JESD_L=8 RX_JESD_S=2 RX_JESD_NP=12 TX_JESD_M=8 TX_JESD_L=8 TX_JESD_S=2 TX_JESD_NP=12 +# make JESD_MODE=64B66B RX_LANE_RATE=24.75 TX_LANE_RATE=24.75 REF_CLK_RATE=375 RX_JESD_M=8 RX_JESD_L=8 RX_JESD_S=2 RX_JESD_NP=12 TX_JESD_M=8 TX_JESD_L=8 TX_JESD_S=2 TX_JESD_NP=12 +# make JESD_MODE=8B10B RX_LANE_RATE=4 TX_LANE_RATE=4 REF_CLK_RATE=100 RX_JESD_M=8 RX_JESD_L=4 RX_JESD_S=1 RX_JESD_NP=16 TX_JESD_M=8 TX_JESD_L=2 TX_JESD_S=1 TX_JESD_NP=16 adi_project ad9081_fmca_ebz_vck190 0 [list \ - JESD_MODE [get_env_param JESD_MODE 64B66B ]\ - RX_LANE_RATE [get_env_param RX_LANE_RATE 24.75 ] \ - TX_LANE_RATE [get_env_param TX_LANE_RATE 24.75 ] \ - REF_CLK_RATE [get_env_param REF_CLK_RATE 375 ] \ - RX_JESD_M [get_env_param RX_JESD_M 8 ] \ - RX_JESD_L [get_env_param RX_JESD_L 8 ] \ - RX_JESD_S [get_env_param RX_JESD_S 2 ] \ - RX_JESD_NP [get_env_param RX_JESD_NP 12 ] \ - RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \ - TX_JESD_M [get_env_param TX_JESD_M 8 ] \ - TX_JESD_L [get_env_param TX_JESD_L 8 ] \ - TX_JESD_S [get_env_param TX_JESD_S 2 ] \ - TX_JESD_NP [get_env_param TX_JESD_NP 12 ] \ - TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \ - RX_KS_PER_CHANNEL [get_env_param RX_KS_PER_CHANNEL 64 ] \ - TX_KS_PER_CHANNEL [get_env_param TX_KS_PER_CHANNEL 64 ] \ + JESD_MODE [get_env_param JESD_MODE 64B66B ]\ + RX_LANE_RATE [get_env_param RX_LANE_RATE 24.75 ] \ + TX_LANE_RATE [get_env_param TX_LANE_RATE 24.75 ] \ + REF_CLK_RATE [get_env_param REF_CLK_RATE 375 ] \ + RX_JESD_M [get_env_param RX_JESD_M 8 ] \ + RX_JESD_L [get_env_param RX_JESD_L 8 ] \ + RX_JESD_S [get_env_param RX_JESD_S 2 ] \ + RX_JESD_NP [get_env_param RX_JESD_NP 12 ] \ + RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \ + TX_JESD_M [get_env_param TX_JESD_M 8 ] \ + TX_JESD_L [get_env_param TX_JESD_L 8 ] \ + TX_JESD_S [get_env_param TX_JESD_S 2 ] \ + TX_JESD_NP [get_env_param TX_JESD_NP 12 ] \ + TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \ + RX_KS_PER_CHANNEL [get_env_param RX_KS_PER_CHANNEL 64 ] \ + TX_KS_PER_CHANNEL [get_env_param TX_KS_PER_CHANNEL 64 ] \ ] adi_project_files ad9081_fmca_ebz_vck190 [list \ @@ -64,4 +65,3 @@ adi_project_files ad9081_fmca_ebz_vck190 [list \ set_property strategy Performance_Explore [get_runs impl_1] adi_project_run ad9081_fmca_ebz_vck190 - diff --git a/projects/ad9081_fmca_ebz/vck190/system_top.v b/projects/ad9081_fmca_ebz/vck190/system_top.v index e75e37bea3..4d42c84fbb 100644 --- a/projects/ad9081_fmca_ebz/vck190/system_top.v +++ b/projects/ad9081_fmca_ebz/vck190/system_top.v @@ -40,7 +40,8 @@ module system_top #( parameter TX_NUM_LINKS = 1, parameter RX_JESD_L = 4, parameter RX_NUM_LINKS = 1, - parameter JESD_MODE = "8B10B" + parameter JESD_MODE = "8B10B", + parameter INTF_CFG = "RXTX" ) ( input sys_clk_n, input sys_clk_p, @@ -129,6 +130,8 @@ module system_top #( wire clkin10; wire tx_device_clk; wire rx_device_clk; + wire rx_sysref; + wire tx_sysref; wire gt_reset; wire rx_reset_pll_and_datapath; @@ -136,18 +139,19 @@ module system_top #( wire rx_reset_datapath; wire tx_reset_datapath; wire rx_resetdone; + wire rx_resetdone_s; wire tx_resetdone; + wire tx_resetdone_s; wire gt_powergood; wire gt_reset_s; wire mst_resetdone; // instantiations IBUFDS_GTE5 i_ibufds_ref_clk ( - .CEB (1'd0), + .CEB (1'b0), .I (fpga_refclk_in_p), .IB (fpga_refclk_in_n), - .O (ref_clk), - .ODIV2 ()); + .O (ref_clk)); IBUFDS i_ibufds_sysref ( .I (sysref2_p), @@ -265,8 +269,8 @@ module system_top #( endgenerate /* Board GPIOS. Buttons, LEDs, etc... */ - assign gpio_led = gpio_o[3:0]; - assign gpio_i[3:0] = gpio_o[3:0]; + assign gpio_led = gpio_o[3:0]; + assign gpio_i[3:0] = gpio_o[3:0]; assign gpio_i[7: 4] = gpio_dip_sw; assign gpio_i[9: 8] = gpio_pb; @@ -279,6 +283,10 @@ module system_top #( assign gt_reset_s = gt_reset & gt_powergood; assign mst_resetdone = rx_resetdone & tx_resetdone; + /* Hardwired to 1 if the RX/TX reset doesn't exit */ + assign rx_resetdone = INTF_CFG != "TX" ? rx_resetdone_s : 1'b1; + assign tx_resetdone = INTF_CFG != "RX" ? tx_resetdone_s : 1'b1; + system_wrapper i_system_wrapper ( .gpio0_i (gpio_i[31:0]), .gpio0_o (gpio_o[31:0]), @@ -314,14 +322,14 @@ module system_top #( .spi1_mosi (spi1_mosi), .spi1_sclk (spi1_sclk), // FMC HPC - .GT_Serial_0_0_gtx_p (tx_data_p_loc[3:0]), - .GT_Serial_0_0_gtx_n (tx_data_n_loc[3:0]), - .GT_Serial_0_0_grx_p (rx_data_p_loc[3:0]), - .GT_Serial_0_0_grx_n (rx_data_n_loc[3:0]), - .GT_Serial_1_0_gtx_p (tx_data_p_loc[7:4]), - .GT_Serial_1_0_gtx_n (tx_data_n_loc[7:4]), - .GT_Serial_1_0_grx_p (rx_data_p_loc[7:4]), - .GT_Serial_1_0_grx_n (rx_data_n_loc[7:4]), + .rx_0_p (rx_data_p_loc[3:0]), + .rx_0_n (rx_data_n_loc[3:0]), + .tx_0_p (tx_data_p_loc[3:0]), + .tx_0_n (tx_data_n_loc[3:0]), + .rx_1_p (rx_data_p_loc[7:4]), + .rx_1_n (rx_data_n_loc[7:4]), + .tx_1_p (tx_data_p_loc[7:4]), + .tx_1_n (tx_data_n_loc[7:4]), .gt_reset (gt_reset_s), .gt_reset_rx_datapath (rx_reset_datapath), @@ -329,11 +337,11 @@ module system_top #( .gt_reset_rx_pll_and_datapath (rx_reset_pll_and_datapath), .gt_reset_tx_pll_and_datapath (tx_reset_pll_and_datapath), .gt_powergood (gt_powergood), - .rx_resetdone (rx_resetdone), - .tx_resetdone (tx_resetdone), + .rx_resetdone (rx_resetdone_s), + .tx_resetdone (tx_resetdone_s), + .ref_clk_q0 (ref_clk), .ref_clk_q1 (ref_clk), - .rx_device_clk (rx_device_clk), .tx_device_clk (tx_device_clk), .rx_sync_0 (rx_syncout), diff --git a/projects/ad9081_fmca_ebz/vck190/timing_constr.xdc b/projects/ad9081_fmca_ebz/vck190/timing_constr.xdc index 36882858d7..b03a82f609 100644 --- a/projects/ad9081_fmca_ebz/vck190/timing_constr.xdc +++ b/projects/ad9081_fmca_ebz/vck190/timing_constr.xdc @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### diff --git a/projects/ad9209_fmca_ebz/vck190/system_top.v b/projects/ad9209_fmca_ebz/vck190/system_top.v index 0acbb1c97a..55b37ca861 100644 --- a/projects/ad9209_fmca_ebz/vck190/system_top.v +++ b/projects/ad9209_fmca_ebz/vck190/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -114,6 +114,14 @@ module system_top #( wire clkin10; wire rx_device_clk; + wire gt_reset; + wire gt_reset_s; + wire rx_reset_pll_and_datapath; + wire rx_reset_datapath; + wire rx_resetdone; + wire gt_powergood; + wire mst_resetdone; + // instantiations IBUFDS_GTE5 i_ibufds_ref_clk ( .CEB (1'd0), @@ -183,6 +191,12 @@ module system_top #( assign rxen[0] = gpio_o[56]; assign rxen[1] = gpio_o[57]; + assign gpio_i[64] = rx_resetdone; + assign gpio_i[66] = mst_resetdone; + assign gt_reset = gpio_o[67]; + assign rx_reset_pll_and_datapath = gpio_o[68]; + assign rx_reset_datapath = gpio_o[70]; + generate if (RX_NUM_LINKS > 1 & JESD_MODE == "8B10B") begin assign fpga_syncout_1_p = rx_syncout[1]; @@ -206,10 +220,14 @@ module system_top #( assign gpio_i[9: 8] = gpio_pb; // Unused GPIOs - assign gpio_i[59:54] = gpio_o[59:54]; - assign gpio_i[94:64] = gpio_o[94:64]; + assign gpio_i[59:54] = gpio_o[59:57]; + assign gpio_i[94:64] = gpio_o[94:72]; assign gpio_i[31:10] = gpio_o[31:10]; + /* Reset should only be asserted if powergood is high */ + assign gt_reset_s = gt_reset & gt_powergood; + assign mst_resetdone = rx_resetdone; + system_wrapper i_system_wrapper ( .gpio0_i (gpio_i[31:0]), .gpio0_o (gpio_o[31:0]), @@ -245,15 +263,19 @@ module system_top #( .spi1_mosi (spi1_mosi), .spi1_sclk (spi1_sclk), // FMC HPC - .GT_Serial_0_0_grx_p (rx_data_p_loc[3:0]), - .GT_Serial_0_0_grx_n (rx_data_n_loc[3:0]), - .GT_Serial_1_0_grx_p (rx_data_p_loc[7:4]), - .GT_Serial_1_0_grx_n (rx_data_n_loc[7:4]), + .rx_0_p (rx_data_p_loc[3:0]), + .rx_0_n (rx_data_n_loc[3:0]), + .rx_1_p (rx_data_p_loc[7:4]), + .rx_1_n (rx_data_n_loc[7:4]), + + .gt_reset (gt_reset_s), + .gt_reset_rx_datapath (rx_reset_datapath), + .gt_reset_rx_pll_and_datapath (rx_reset_pll_and_datapath), + .gt_powergood (gt_powergood), + .rx_resetdone (rx_resetdone), - .gt_reset (~rstb), .ref_clk_q0 (ref_clk), .ref_clk_q1 (ref_clk), - .rx_device_clk (rx_device_clk), .rx_sync_0 (rx_syncout), .rx_sysref_0 (sysref));