From 2f459b0e639a5e4e981cc567a27da7ef8cb863cf Mon Sep 17 00:00:00 2001
From: "Liviu.Iacob" <liviu.iacob@analog.com>
Date: Thu, 6 Oct 2022 09:35:49 +0100
Subject: [PATCH] adi_jesd204_hw.tcl: add ref_clock.out_clock phy.ref_clk
 connection only for a10soc and s10soc on the rx side

---
 library/intel/adi_jesd204/adi_jesd204_hw.tcl | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/library/intel/adi_jesd204/adi_jesd204_hw.tcl b/library/intel/adi_jesd204/adi_jesd204_hw.tcl
index 43d89bbd24..8cbaffe263 100644
--- a/library/intel/adi_jesd204/adi_jesd204_hw.tcl
+++ b/library/intel/adi_jesd204/adi_jesd204_hw.tcl
@@ -601,8 +601,9 @@ proc jesd204_compose {} {
     set data_direction source
     set jesd204_intfs {config device_config ilas_config device_event status}
     set tx_rx "rx"
-
-    # add_connection ref_clock.out_clk phy.ref_clk
+    if {$device_family == "Arria 10" || $device_family == "Stratix 10"} {
+      add_connection ref_clock.out_clk phy.ref_clk
+    }
   }
 
   add_instance axi_jesd204_${tx_rx} axi_jesd204_${tx_rx}