From 75c266bf2a346ea604519b2b5749ad293a63e78b Mon Sep 17 00:00:00 2001 From: Jorge Marques Date: Fri, 22 Sep 2023 14:34:19 -0300 Subject: [PATCH] i3c_controller: redesign bit_mod Redesign bit modulation module to allow register configurable speed grades. Signed-off-by: Jorge Marques --- .../i3c_controller_bit_mod.v | 282 ++++++------------ .../i3c_controller_bit_mod_cmd.v | 50 ++-- .../i3c_controller_core/i3c_controller_core.v | 34 +-- .../i3c_controller_framing.v | 13 +- .../i3c_controller_phy_sda.v | 13 +- .../i3c_controller_core/i3c_controller_word.v | 282 +++++++++--------- .../i3c_controller_cmd_parser.v | 6 +- .../i3c_controller_host_interface.v | 1 + .../i3c_controller_regmap.v | 18 +- .../i3c_controller_write_byte.v | 17 +- .../interfaces/i3c_controller_rmap_rtl.xml | 4 +- .../{__i3c_ardz => ad405x_i3c_ardz}/Makefile | 0 .../common/ad405x_i3c_ardz_bd.tcl} | 0 .../coraz7s/Makefile | 7 +- .../coraz7s/system_bd.tcl | 2 +- .../coraz7s/system_constr.xdc | 2 +- .../coraz7s/system_project.tcl | 6 +- .../coraz7s/system_top.v | 3 +- 18 files changed, 335 insertions(+), 405 deletions(-) rename projects/{__i3c_ardz => ad405x_i3c_ardz}/Makefile (100%) rename projects/{__i3c_ardz/common/__i3c_ardz_bd.tcl => ad405x_i3c_ardz/common/ad405x_i3c_ardz_bd.tcl} (100%) rename projects/{__i3c_ardz => ad405x_i3c_ardz}/coraz7s/Makefile (84%) rename projects/{__i3c_ardz => ad405x_i3c_ardz}/coraz7s/system_bd.tcl (90%) rename projects/{__i3c_ardz => ad405x_i3c_ardz}/coraz7s/system_constr.xdc (98%) rename projects/{__i3c_ardz => ad405x_i3c_ardz}/coraz7s/system_project.tcl (71%) rename projects/{__i3c_ardz => ad405x_i3c_ardz}/coraz7s/system_top.v (99%) diff --git a/library/i3c_controller/i3c_controller_core/i3c_controller_bit_mod.v b/library/i3c_controller/i3c_controller_core/i3c_controller_bit_mod.v index 3307c0de8cf..5e7c4f40377 100644 --- a/library/i3c_controller/i3c_controller_core/i3c_controller_bit_mod.v +++ b/library/i3c_controller/i3c_controller_core/i3c_controller_bit_mod.v @@ -32,221 +32,133 @@ // // *************************************************************************** // *************************************************************************** -/** - * Translate simple commands into SCL/SDA transitions - * Each command has 8 states and shall jump to a new command - * without returning to idle, A/B/C/D/*, where * is a next command - * first state A or idle. - * - * start SCL ====--------\____ - * SDA -~-~-~-~\________ - * x | A | B | C | D | * - * - * stop SCL ___/----------- - * SDA ==____/~~~~~~~~ - * x | A | B | C | D | * - * - * write SCL ____/-------\____ - * SDA X===============X - * x | A | B | C | D | * - * - * read SCL ____/-------\____ - * SDA ~~~~~~~~~~~~~~~~~ - * x | A | B | C | D | * - * - * T(read) SCL ____/-------\____ - * SDA ~~~~S============ - * x | A | B | C | D | * - * - * S: sample lane and drive it to the value. - * =: keep last value. - * X: set lane to value - * ~: open-drain high - * ~: push-pull high - * _: low - * ~-: either pp or od - * The clk_1 is scaled depending on the requirements, e.g. in open-drain, is - * slower and must be in synced with clk. - * - * Note: clk_1 must be at least 3x slower than clk_0. - */ `timescale 1ns/100ps -`default_nettype none +`default_nettype wire `include "i3c_controller_bit_mod_cmd.v" module i3c_controller_bit_mod ( - input wire reset_n, - input wire clk_0, // 100MHz - input wire clk_1, // 12.5MHz - input wire clk_sel, + input reset_n, + input clk, // 100 MHz // Bit Modulation Command - input wire [`MOD_BIT_CMD_WIDTH:0] cmd, - input wire cmd_valid, - output wire cmd_ready, + input [`MOD_BIT_CMD_WIDTH:0] cmd, + input cmd_valid, + output cmd_ready, + // Indicates that the bus is not transfering, + // is different from bus idle because does not wait 200us after Stop. + output cmd_nop, + // 0: 12.50MHz + // 1: 6.25MHz + // 2: 3.12MHz + // 3: 1.56MHz + input [1:0] scl_pp_sg, // SCL Push-pull speed grade - // RX and ACK + output reg rx, + output reg rx_raw, + output reg rx_valid, - output wire rx, - output wire rx_valid, - output wire rx_stop, - output wire rx_nack, - - // Status - - output wire idle_bus, // Bus drive signals - output reg scl, - output reg sdi, - input wire sdo, - output wire t + output reg sdo, + output scl, + input sdi, + output t ); - reg reset_n_ctrl; - reg reset_n_clr; - - reg pp; - reg [2:0] i; - reg [7:0] scl_ = 8'b00001110; - reg [7:0] sdi_; - - reg [1:0] rx_valid_reg; - reg [1:0] rx_stop_reg; - reg [1:0] rx_nack_reg; - - reg [1:0] st; - reg [`MOD_BIT_CMD_WIDTH:2] sm; - - reg sdo_reg; + reg [`MOD_BIT_CMD_WIDTH:0] cmd_r; + reg [1:0] pp_sg; + reg [5:0] count; // Worst-case: 1.56MHz, 32-bits per half-bit. + reg transfer; + reg sr; + + reg scl_high_reg; + wire scl_high = count[pp_sg+2]; + wire sdo_w; + wire t_w; + + wire scl_end; + wire [3:0] scl_end_multi; + genvar i; + for (i = 0; i < 4; i = i+1) begin + assign scl_end_multi[i] = &count[i+2:0]; + end + assign scl_end = scl_end_multi[pp_sg]; - localparam [2:0] i_ = 7; + assign cmd_ready = (scl_end | !transfer) & reset_n; - always @(sm) begin - case (sm) - `MOD_BIT_CMD_START_ : sdi_ = 8'b11111000; - `MOD_BIT_CMD_STOP_ : sdi_ = 8'b00000011; - `MOD_BIT_CMD_ACK_IBI_ : sdi_ = 8'b00001111; - default : sdi_ = 8'b00000000; - endcase - end + wire [1:0] st = cmd_r[1:0]; + wire [`MOD_BIT_CMD_WIDTH:2] sm = cmd_r[`MOD_BIT_CMD_WIDTH:2]; - always @(posedge clk_0) begin + always @(posedge clk) begin if (!reset_n) begin - reset_n_ctrl <= 1'b0; - sm <= `MOD_BIT_CMD_NOP_; - cmd_ready_reg_ctrl <= 1'b0; - end else if (reset_n_clr) begin - reset_n_ctrl <= 1'b1; - end else begin - if ((cmd_ready_reg & !cmd_ready_reg_ctrl) | sm == `MOD_BIT_CMD_NOP_) begin + cmd_r <= {`MOD_BIT_CMD_NOP_, 2'b01}; + pp_sg <= 2'b11; + end else begin + if (cmd_ready) begin if (cmd_valid) begin - sm <= cmd[`MOD_BIT_CMD_WIDTH:2]; - st <= cmd[1:0]; + cmd_r <= cmd; + pp_sg <= cmd[1] ? scl_pp_sg : 2'b11; end else begin - sm <= `MOD_BIT_CMD_NOP_; + cmd_r <= {`MOD_BIT_CMD_NOP_, 2'b01}; end - end else begin - sm <= sm; - st <= st; - end - if (cmd_ready_reg) begin - cmd_ready_reg_ctrl <= 1'b1; - end else begin - cmd_ready_reg_ctrl <= 1'b0; end - end - rx_valid_reg [1] <= rx_valid_reg [0]; - rx_stop_reg [1] <= rx_stop_reg [0]; - rx_nack_reg [1] <= rx_nack_reg [0]; + end end - reg cmd_ready_reg; - reg cmd_ready_reg_ctrl; - always @(posedge clk_1) begin - rx_nack_reg[0] <= 1'b0; - rx_valid_reg[0] <= 1'b0; - rx_stop_reg[0] <= 1'b0; - if (!reset_n_ctrl) begin - reset_n_clr <= 1'b1; - i <= 0; - cmd_ready_reg <= 1'b0; + always @(posedge clk) begin + count <= 0; + if (!reset_n) begin + transfer <= 1'b0; + sr <= 1'b0; end else begin - reset_n_clr <= 1'b0; - cmd_ready_reg <= (i == i_ - 1 & clk_sel) | (i == i_ & ~clk_sel); - i <= sm == `MOD_BIT_CMD_NOP_ ? 0 : i + 1; - end - - scl <= scl_[7-i]; - sdi <= sdi_[7-i]; - pp <= st[1]; - case (sm) - `MOD_BIT_CMD_NOP_: begin - sdi <= 1'b1; - pp <= 1'b0; - scl <= 1'b1; - end - `MOD_BIT_CMD_WRITE_: begin - sdi <= st[0]; - end - `MOD_BIT_CMD_READ_: begin - sdi <= 1'b1; - pp <= 1'b0; - if (i == 5) begin - rx_valid_reg[0] <= 1'b1; - end - end - `MOD_BIT_CMD_START_: begin - // For Sr - if (i <= 3) begin - scl <= scl; - end - end - `MOD_BIT_CMD_STOP_: begin - if (i == 3'd7) begin - scl <= scl; - end - end - `MOD_BIT_CMD_ACK_SDR_: begin - if (i == 0 || i == 1) begin - sdi <= 1'b1; - pp <= 1'b0; - end else if (i == 2) begin - sdi <= sdo_reg; - rx_nack_reg[0] <= sdo_reg; - end else begin - sdi <= sdi; - end + if (cmd_valid) begin + transfer <= 1'b1; + end else if (scl_end) begin + transfer <= 1'b0; end - `MOD_BIT_CMD_T_READ_: begin - if (~|i[2:1]) begin - sdi <= 1'b1; - pp <= 1'b0; - end else begin - sdi <= st[0] ? 1'b0 : sdo_reg; - end - if (i == 2) begin - rx_stop_reg[0] <= ~sdo_reg; - end - end - `MOD_BIT_CMD_ACK_IBI_: begin - pp <= 1'b0; + if (transfer & ~scl_end) begin + count <= count + 1; end - default: begin + + if (scl_end) begin + sr <= cmd_valid & sm != `MOD_BIT_CMD_NOP_ ? 1'b1 : 1'b0; end - endcase - sdo_reg <= sdo === 1'b0 ? 1'b0 : 1'b1; + end end - assign rx_valid = rx_valid_reg[0] & ~rx_valid_reg[1]; - assign rx_stop = rx_stop_reg [0] & ~rx_stop_reg [1]; - assign rx_nack = rx_nack_reg [0] & ~rx_nack_reg [1]; - assign rx = sdo_reg; + always @(posedge clk) begin + scl_high_reg <= scl_high; + rx_valid <= 1'b0; + sdo <= sdo_w; + rx_raw <= sdi; + if (~scl_high_reg & scl_high) begin + rx <= sdi; // Multi-cycle-path worst-case: 4 clks (12.5MHz, half-bit ack) + rx_valid <= 1'b1; + end + end - assign cmd_ready = (cmd_ready_reg | sm == `MOD_BIT_CMD_NOP_) & !cmd_ready_reg_ctrl & reset_n; - assign t = ~pp & sdi ? 1'b1 : 1'b0; - assign idle_bus = sm == `MOD_BIT_CMD_NOP_; + assign sdo_w = sm == `MOD_BIT_CMD_START_ ? (scl_high ? ~count[pp_sg+1] : 1'b1) : + sm == `MOD_BIT_CMD_STOP_ ? (scl_high ? count[pp_sg+1] : 1'b0) : + sm == `MOD_BIT_CMD_WRITE_ ? st[0] : + sm == `MOD_BIT_CMD_ACK_SDR_ ? (scl_high ? rx : 1'b1) : + sm == `MOD_BIT_CMD_ACK_IBI_ ? (scl_high ? 1'b1 : 1'b0) : + 1'b1; + + // Gets optimized to + assign t_w = sm[4] ? 1'b0 : st[1]; + //assign t_w = sm == `MOD_BIT_CMD_STOP_ ? 1'b0 : + // sm == `MOD_BIT_CMD_START_ ? 1'b0 : + // sm == `MOD_BIT_CMD_READ_ ? 1'b0 : + // sm == `MOD_BIT_CMD_ACK_SDR_ ? 1'b0 : + // st[1]; + assign t = ~t_w & sdo ? 1'b1 : 1'b0; + + assign scl = sm == `MOD_BIT_CMD_START_ ? (sr ? scl_high : 1'b1) : + sm == `MOD_BIT_CMD_NOP_ ? 1'b1 : + scl_high; + + assign cmd_nop = sm == `MOD_BIT_CMD_NOP_; endmodule diff --git a/library/i3c_controller/i3c_controller_core/i3c_controller_bit_mod_cmd.v b/library/i3c_controller/i3c_controller_core/i3c_controller_bit_mod_cmd.v index 047b439ad07..3287b66a46d 100644 --- a/library/i3c_controller/i3c_controller_core/i3c_controller_bit_mod_cmd.v +++ b/library/i3c_controller/i3c_controller_core/i3c_controller_bit_mod_cmd.v @@ -41,32 +41,42 @@ // Modulation bit commands `define MOD_BIT_CMD_NOP_ 3'b000 -`define MOD_BIT_CMD_START_ 3'b001 -`define MOD_BIT_CMD_STOP_ 3'b010 -`define MOD_BIT_CMD_WRITE_ 3'b011 -`define MOD_BIT_CMD_READ_ 3'b100 -`define MOD_BIT_CMD_T_READ_ 3'b101 +`define MOD_BIT_CMD_WRITE_ 3'b001 +`define MOD_BIT_CMD_ACK_IBI_ 3'b010 + +`define MOD_BIT_CMD_START_ 3'b100 +`define MOD_BIT_CMD_STOP_ 3'b101 `define MOD_BIT_CMD_ACK_SDR_ 3'b110 -`define MOD_BIT_CMD_ACK_IBI_ 3'b111 +`define MOD_BIT_CMD_READ_ 3'b111 // Read and ACK are modulated identically // The mod_byte shall send a CMD_READ to assert ACK // T-bit LOW is a low write // T-bit HIGH is either a open-drain high write or repeated start +// Start, stop, read, ack_sdr have PP variants to preserve the PP +// speed-grade, but the they never active drive SDA High. +// T_READ bit: +// To continue, yield ACK_SDR (read RX to check if the peripheral wishes to +// continue). +// To stop, yield Start, creating a Sr. +// ACK_IBI bit: +// To ACK, yield ACK_IBI. +// to NACK, yield WRITE_OD_1 +// Per specification, ACK_IBI could be replaced by WRITE_OD_0. -`define MOD_BIT_CMD_NOP {`MOD_BIT_CMD_NOP_, 2'b00} -`define MOD_BIT_CMD_START_OD {`MOD_BIT_CMD_START_, 2'b00} -`define MOD_BIT_CMD_START_PP {`MOD_BIT_CMD_START_, 2'b10} -`define MOD_BIT_CMD_STOP_OD {`MOD_BIT_CMD_STOP_, 2'b00} -`define MOD_BIT_CMD_STOP_PP {`MOD_BIT_CMD_STOP_, 2'b10} -`define MOD_BIT_CMD_WRITE_OD_0 {`MOD_BIT_CMD_WRITE_, 2'b00} -`define MOD_BIT_CMD_WRITE_OD_1 {`MOD_BIT_CMD_WRITE_, 2'b01} -`define MOD_BIT_CMD_WRITE_PP_0 {`MOD_BIT_CMD_WRITE_, 2'b10} -`define MOD_BIT_CMD_WRITE_PP_1 {`MOD_BIT_CMD_WRITE_, 2'b11} -`define MOD_BIT_CMD_READ {`MOD_BIT_CMD_READ_, 2'b00} -`define MOD_BIT_CMD_T_READ_CONT {`MOD_BIT_CMD_T_READ_ ,2'b00} -`define MOD_BIT_CMD_T_READ_STOP {`MOD_BIT_CMD_T_READ_ ,2'b01} -`define MOD_BIT_CMD_ACK_SDR {`MOD_BIT_CMD_ACK_SDR_,2'b00} -`define MOD_BIT_CMD_ACK_IBI {`MOD_BIT_CMD_ACK_IBI_,2'b00} +`define MOD_BIT_CMD_NOP {`MOD_BIT_CMD_NOP_, 2'b00} +`define MOD_BIT_CMD_START_OD {`MOD_BIT_CMD_START_, 2'b00} +`define MOD_BIT_CMD_START_PP {`MOD_BIT_CMD_START_, 2'b10} +`define MOD_BIT_CMD_STOP_OD {`MOD_BIT_CMD_STOP_, 2'b00} +`define MOD_BIT_CMD_STOP_PP {`MOD_BIT_CMD_STOP_, 2'b10} +`define MOD_BIT_CMD_WRITE_OD_0 {`MOD_BIT_CMD_WRITE_, 2'b00} +`define MOD_BIT_CMD_WRITE_OD_1 {`MOD_BIT_CMD_WRITE_, 2'b01} +`define MOD_BIT_CMD_WRITE_PP_0 {`MOD_BIT_CMD_WRITE_, 2'b10} +`define MOD_BIT_CMD_WRITE_PP_1 {`MOD_BIT_CMD_WRITE_, 2'b11} +`define MOD_BIT_CMD_READ_OD {`MOD_BIT_CMD_READ_, 2'b00} +`define MOD_BIT_CMD_READ_PP {`MOD_BIT_CMD_READ_, 2'b10} +`define MOD_BIT_CMD_ACK_SDR_OD {`MOD_BIT_CMD_ACK_SDR_,2'b00} +`define MOD_BIT_CMD_ACK_SDR_PP {`MOD_BIT_CMD_ACK_SDR_,2'b10} +`define MOD_BIT_CMD_ACK_IBI {`MOD_BIT_CMD_ACK_IBI_,2'b00} `endif diff --git a/library/i3c_controller/i3c_controller_core/i3c_controller_core.v b/library/i3c_controller/i3c_controller_core/i3c_controller_core.v index 7fc91ed1687..c037f97caaf 100644 --- a/library/i3c_controller/i3c_controller_core/i3c_controller_core.v +++ b/library/i3c_controller/i3c_controller_core/i3c_controller_core.v @@ -103,6 +103,7 @@ module i3c_controller_core #( wire sdi_bit; wire rx; + wire rx_raw; wire rx_valid; wire rx_stop; wire rx_nack; @@ -126,10 +127,9 @@ module i3c_controller_core #( wire [31:0] pid_bcr_dcr; wire pid_bcr_dcr_tick; - wire clk_sel; wire clk_clr; - wire idle_bus; + wire cmd_nop; i3c_controller_framing #( .MAX_DEVS(`MAX_DEVS) @@ -161,8 +161,8 @@ module i3c_controller_core #( .cmdw_rx_ready(cmdw_rx_ready), .cmdw_rx_valid(cmdw_rx_valid), .cmdw_rx(cmdw_rx), - .rx(rx), - .idle_bus(idle_bus), + .rx_raw(rx_raw), + .cmd_nop(cmd_nop), .ibi_requested(ibi_requested), .ibi_requested_auto(ibi_requested_auto), .pid_bcr_dcr_tick(pid_bcr_dcr_tick), @@ -192,9 +192,6 @@ module i3c_controller_core #( .cmd_ready(cmd_ready), .rx(rx), .rx_valid(rx_valid), - .rx_stop(rx_stop), - .rx_nack(rx_nack), - .clk_sel(clk_sel), .ibi_requested(ibi_requested), .ibi_requested_auto(ibi_requested_auto), .ibi_tick(ibi_tick), @@ -204,30 +201,19 @@ module i3c_controller_core #( .pid_bcr_dcr(pid_bcr_dcr), .rmap_ibi_config(rmap_ibi_config)); - i3c_controller_clk_div #( - .SIM_DEVICE(SIM_DEVICE), - .CLK_DIV(`CLK_DIV) - ) i_i3c_controller_clk_div ( - .reset_n(reset_n), - .sel(clk_sel), - .cmd_ready(cmd_ready), - .clk(clk), - .clk_out(clk_out)); - + reg [1:0] scl_pp_sg = 2'b10; i3c_controller_bit_mod #( ) i_i3c_controller_bit_mod ( .reset_n(reset_n), - .clk_0(clk), - .clk_1(clk_out), - .clk_sel(clk_sel), + .clk(clk), .cmd(cmd), + .scl_pp_sg(scl_pp_sg), .cmd_valid(cmd_valid), .cmd_ready(cmd_ready), .rx(rx), + .rx_raw(rx_raw), .rx_valid(rx_valid), - .rx_stop(rx_stop), - .rx_nack(rx_nack), - .idle_bus(idle_bus), + .cmd_nop(cmd_nop), .scl(scl), .sdi(sdi_bit), .sdo(sdo_bit), @@ -242,5 +228,5 @@ module i3c_controller_core #( assign ibi = {ibi_da, ibi_mdb}; assign ibi_valid = ibi_tick; - assign cmdp_idle_bus = idle_bus; + assign cmdp_idle_bus = cmd_nop; endmodule diff --git a/library/i3c_controller/i3c_controller_core/i3c_controller_framing.v b/library/i3c_controller/i3c_controller_core/i3c_controller_framing.v index 8924942497b..a5278c87dad 100644 --- a/library/i3c_controller/i3c_controller_core/i3c_controller_framing.v +++ b/library/i3c_controller/i3c_controller_core/i3c_controller_framing.v @@ -107,8 +107,8 @@ module i3c_controller_framing #( // Raw SDO input & bus condition - input rx, - input idle_bus, + input rx_raw, + input cmd_nop, // IBI interface @@ -177,9 +177,10 @@ module i3c_controller_framing #( ctrl_daa <= 1'b0; rmap_devs_ctrl <= 'd0; j <= 0; + ibi_requested_auto <= 1'b0; end else if (cmdw_nack) begin sm <= `CMDW_NOP; - smt <= cleanup; + smt <= cmdp_rnw_reg ? setup : cleanup; smr <= request; ctrl_daa <= 1'b0; end else begin @@ -190,7 +191,7 @@ module i3c_controller_framing #( case (smt) setup: begin sr <= cmdw_ready ? 1'b0 : sr; - if (idle_bus & ibi_auto & ibi_enable & ~rx) begin + if (cmd_nop & ibi_auto & ibi_enable & rx_raw === 1'b0) begin sm <= `CMDW_BCAST_7E_W0; smt <= transfer; ibi_requested_auto <= 1'b1; @@ -327,7 +328,9 @@ module i3c_controller_framing #( if (sdo_valid) begin cmdp_buffer_len_reg <= cmdp_buffer_len_reg - 1; end - smt <= cmdp_buffer_len_reg == 0 ? setup : smt; + if (cmdp_buffer_len_reg == 0) begin + smt <= setup; + end end seek: begin case (smr) diff --git a/library/i3c_controller/i3c_controller_core/i3c_controller_phy_sda.v b/library/i3c_controller/i3c_controller_core/i3c_controller_phy_sda.v index b35af697921..e53a27dbbf4 100644 --- a/library/i3c_controller/i3c_controller_core/i3c_controller_phy_sda.v +++ b/library/i3c_controller/i3c_controller_core/i3c_controller_phy_sda.v @@ -37,20 +37,19 @@ */ `timescale 1ns/100ps -`default_nettype none module i3c_controller_phy_sda ( - output wire sdo, - input wire sdi, - input wire t, - inout wire sda + input sdo, + output sdi, + input t, + inout sda ); // TODO: Add Intel tristate primitive, select dependin on target. IOBUF #( ) IOBUF_inst ( - .O(sdo), + .O(sdi), .IO(sda), - .I(sdi), + .I(sdo), .T(t) ); // Same as, but sometimes Xilinx was not inferring IOBUF from this... diff --git a/library/i3c_controller/i3c_controller_core/i3c_controller_word.v b/library/i3c_controller/i3c_controller_core/i3c_controller_word.v index af5c279ec3c..4a7878c83b5 100644 --- a/library/i3c_controller/i3c_controller_core/i3c_controller_word.v +++ b/library/i3c_controller/i3c_controller_core/i3c_controller_word.v @@ -50,8 +50,8 @@ module i3c_controller_word ( output reg cmdw_nack, // NACK is HIGH when an ACK is not satisfied in the I3C bus, acts as reset. - output wire cmdw_valid, output wire cmdw_ready, + input wire cmdw_valid, input wire [`CMDW_HEADER_WIDTH+8:0] cmdw, input wire cmdw_rx_ready, @@ -60,7 +60,7 @@ module i3c_controller_word ( // Bit Modulation Command - output reg [`MOD_BIT_CMD_WIDTH:0] cmd, + output wire [`MOD_BIT_CMD_WIDTH:0] cmd, output wire cmd_valid, input wire cmd_ready, @@ -68,12 +68,6 @@ module i3c_controller_word ( input wire rx, input wire rx_valid, - input wire rx_stop, - input wire rx_nack, - - // Modulation clock selection - - output wire clk_sel, // IBI interface @@ -96,13 +90,11 @@ module i3c_controller_word ( wire ibi_auto; wire [`CMDW_HEADER_WIDTH:0] cmdw_header; - reg cmd_ready_reg; reg [7:0] cmdw_body; reg [`CMDW_HEADER_WIDTH:0] sm; - reg [`CMDW_HEADER_WIDTH:0] sm_reg; - reg [`CMDW_HEADER_WIDTH:0] sm_reg_2; reg [8:0] cmdw_rx_reg; + reg cmdw_nacked; reg [8:0] ibi_da_reg; reg [8:0] ibi_mdb_reg; @@ -110,11 +102,12 @@ module i3c_controller_word ( localparam [6:0] I3C_RESERVED = 7'h7e; - reg [1:0] do_ack; // Peripheral did NACK? - reg [1:0] do_rx_t; // Peripheral end Message at T in Read Data? + reg do_ack; // Peripheral did NACK? + reg do_rx_t; // Peripheral end Message at T in Read Data? reg rx_sampled; - reg clk_sel_lut; - reg [1:0] clk_sel_reg; + reg sg; + reg [`MOD_BIT_CMD_WIDTH:2] cmd_r; + reg cmd_wr; reg [5:0] i; reg [5:0] i_reg; @@ -144,33 +137,33 @@ module i3c_controller_word ( endcase case (sm) - `CMDW_NOP : clk_sel_lut = 0; - `CMDW_START : clk_sel_lut = 0; - `CMDW_BCAST_7E_W0 : clk_sel_lut = 0; - `CMDW_CCC_OD : clk_sel_lut = 0; - `CMDW_CCC_PP : clk_sel_lut = 1; - `CMDW_TARGET_ADDR_OD : clk_sel_lut = 0; - `CMDW_TARGET_ADDR_PP : clk_sel_lut = 1; - `CMDW_MSG_SR : clk_sel_lut = 1; - `CMDW_MSG_RX : clk_sel_lut = 1; - `CMDW_MSG_TX : clk_sel_lut = 1; - `CMDW_STOP : clk_sel_lut = 1; - `CMDW_BCAST_7E_W1 : clk_sel_lut = 0; - `CMDW_DAA_DEV_CHAR_1 : clk_sel_lut = 0; - `CMDW_DAA_DEV_CHAR_2 : clk_sel_lut = 0; - `CMDW_DYN_ADDR : clk_sel_lut = 0; - `CMDW_IBI_MDB : clk_sel_lut = 1; - `CMDW_SR : clk_sel_lut = 1; - default : clk_sel_lut = 0; + `CMDW_NOP : sg = 0; + `CMDW_START : sg = 0; + `CMDW_BCAST_7E_W0 : sg = 0; + `CMDW_CCC_OD : sg = 0; + `CMDW_CCC_PP : sg = 1; + `CMDW_TARGET_ADDR_OD : sg = 0; + `CMDW_TARGET_ADDR_PP : sg = 1; + `CMDW_MSG_SR : sg = 1; + `CMDW_MSG_RX : sg = 1; + `CMDW_MSG_TX : sg = 1; + `CMDW_STOP : sg = 1; + `CMDW_BCAST_7E_W1 : sg = 0; + `CMDW_DAA_DEV_CHAR_1 : sg = 0; + `CMDW_DAA_DEV_CHAR_2 : sg = 0; + `CMDW_DYN_ADDR : sg = 0; + `CMDW_IBI_MDB : sg = 1; + `CMDW_SR : sg = 1; + default : sg = 0; endcase end - reg [0:0] smt; - localparam [0:0] - setup = 0, - transfer = 1; - reg ibi_da_valid; - wire ibi_should_ack; + reg [1:0] smt; + localparam [1:0] + get = 0, + setup = 1, + transfer = 2, + resolve = 3; always @(posedge clk) begin cmdw_nack <= 1'b0; @@ -178,86 +171,36 @@ module i3c_controller_word ( ibi_tick <= 1'b0; pid_bcr_dcr_tick <= 1'b0; if (!reset_n) begin - cmd <= `MOD_BIT_CMD_NOP; - smt <= setup; + smt <= get; sm <= `CMDW_NOP; - sm_reg <= `CMDW_NOP; - sm_reg_2 <= `CMDW_NOP; i <= 0; - i_reg <= 0; - i_reg_2 <= 0; - clk_sel_reg <= 2'b00; ibi_requested <= 1'b0; - end if ((do_ack[1] & rx_nack) | (do_rx_t[1] & rx_stop)) begin - sm <= `CMDW_NOP; - cmd <= {`MOD_BIT_CMD_STOP_, 1'b0,1'b0}; - clk_sel_reg <= 2'b00; - cmdw_nack <= 1'b1; + cmd_r <= `MOD_BIT_CMD_NOP_; + cmd_wr <= 1'b0; end else begin case (smt) - setup: begin + get: begin if (cmdw_valid) begin - smt <= transfer; + smt <= setup; end sm <= cmdw_header; cmdw_body <= cmdw[7:0]; ibi_requested <= ibi_requested_auto; i <= 0; + cmdw_nacked <= 1'b0; end - transfer: begin - if (cmd_ready) begin - clk_sel_reg <= {clk_sel_reg[0], clk_sel_lut}; - do_ack <= {do_ack[0], 1'b0}; - do_rx_t <= {do_rx_t[0], 1'b0}; - i <= i + 1; - i_reg <= i; - i_reg_2 <= i_reg; - sm_reg <= sm; - sm_reg_2 <= sm_reg; - if (i == i_) begin - smt <= setup; - end + setup: begin + smt <= transfer; ibi_requested <= 1'b0; - - // RX pipelines, delayed twice to match bit_mod - case (sm_reg_2) - `CMDW_NOP, - `CMDW_STOP: begin - ibi_requested <= ibi_requested; - end - `CMDW_BCAST_7E_W0: begin - ibi_da_reg[8-i_reg_2] <= rx_sampled; - ibi_requested <= i_reg_2 < 6 & rx_sampled === 1'b0 ? 1'b1 : ibi_requested; - end - `CMDW_MSG_RX: begin - if (i_reg_2 == 8) begin - cmdw_rx_valid <= 1'b1; - end - cmdw_rx_reg[8-i_reg_2] <= rx_sampled; - end - `CMDW_IBI_MDB: begin - if (i_reg_2 == 8) begin - ibi_tick <= 1'b1; - end - ibi_mdb_reg[8-i_reg_2] <= rx_sampled; - end - `CMDW_DAA_DEV_CHAR_1, - `CMDW_DAA_DEV_CHAR_2: begin - if (i_reg_2 == 31) begin - pid_bcr_dcr_tick <= 1'b1; - end - pid_bcr_dcr[31 - i_reg_2] <= rx_sampled; - end - default: begin - end - endcase + do_ack <= 1'b0; + do_rx_t <= 1'b0; case (sm) `CMDW_NOP: begin - cmd <= `MOD_BIT_CMD_NOP; + cmd_r <= `MOD_BIT_CMD_NOP_; end `CMDW_START: begin - cmd <= `MOD_BIT_CMD_START_OD; + cmd_r <= `MOD_BIT_CMD_START_; end `CMDW_BCAST_7E_W0: begin // During the header broadcast, the peripheral shall issue an IBI, due @@ -268,38 +211,34 @@ module i3c_controller_word ( // resolved; if (i[2:1] == 2'b11) begin // 1'b0+RnW=0 - cmd <= ibi_requested ? `MOD_BIT_CMD_READ : {`MOD_BIT_CMD_WRITE_,1'b0,1'b0}; + cmd_r <= `MOD_BIT_CMD_WRITE_; + cmd_wr <= 1'b0; end else if (i == 8) begin if (ibi_requested) begin // also ibi_len ... - cmd <= ibi_enable ? `MOD_BIT_CMD_ACK_IBI : `MOD_BIT_CMD_READ; // & ibi_ack + cmd_r <= ibi_enable ? `MOD_BIT_CMD_ACK_IBI_ : `MOD_BIT_CMD_READ_; // & ibi_ack end else begin // ACK - cmd <= `MOD_BIT_CMD_ACK_SDR; - do_ack[0] <= 1'b1; + cmd_r <= `MOD_BIT_CMD_ACK_SDR_; + do_ack <= 1'b1; end end else begin // 6'b111111 - cmd <= `MOD_BIT_CMD_READ; - end - - if (i == 7) begin - if (ibi_requested) begin - ibi_da_valid <= 1'b1; - end + cmd_r <= `MOD_BIT_CMD_READ_; end - end `CMDW_BCAST_7E_W1: begin if (i == 7) begin // RnW=1 - cmd <= {`MOD_BIT_CMD_WRITE_,1'b0,1'b1}; + cmd_r <= `MOD_BIT_CMD_WRITE_; + cmd_wr <= 1'b1; end else if (i == 8) begin // ACK - cmd <= `MOD_BIT_CMD_ACK_SDR; - do_ack[0] <= 1'b1; + cmd_r <= `MOD_BIT_CMD_ACK_SDR_; + do_ack <= 1'b1; end else begin // 7'h7e - cmd <= {`MOD_BIT_CMD_WRITE_,1'b0,I3C_RESERVED[6 - i[2:0]]}; + cmd_r <= `MOD_BIT_CMD_WRITE_; + cmd_wr <= I3C_RESERVED[6 - i[2:0]]; end end `CMDW_DYN_ADDR, @@ -307,29 +246,30 @@ module i3c_controller_word ( `CMDW_TARGET_ADDR_PP: begin if (i == 8) begin // ACK - cmd <= `MOD_BIT_CMD_ACK_SDR; - do_ack[0] <= 1'b1; + cmd_r <= `MOD_BIT_CMD_ACK_SDR_; + do_ack <= 1'b1; end else begin // DA+RnW/DA+T - cmd <= {`MOD_BIT_CMD_WRITE_,clk_sel_lut,cmdw_body[7 - i[2:0]]}; + cmd_r <= `MOD_BIT_CMD_WRITE_; + cmd_wr <= cmdw_body[7 - i[2:0]]; end end `CMDW_SR, `CMDW_MSG_SR: begin - cmd <= `MOD_BIT_CMD_START_PP; + cmd_r <= `MOD_BIT_CMD_START_; end `CMDW_MSG_RX: begin if (i == 8) begin // T if (cmdw_rx_ready) begin - do_rx_t[0] <= 1'b1; - cmd <= `MOD_BIT_CMD_T_READ_CONT; // continue, if peripheral wishes to do so + do_rx_t <= 1'b1; + cmd_r <= `MOD_BIT_CMD_ACK_SDR_; // continue, if peripheral wishes to do so end else begin - cmd <= `MOD_BIT_CMD_T_READ_STOP; // stop + cmd_r <= `MOD_BIT_CMD_START_; // stop end end else begin // SDI - cmd <= `MOD_BIT_CMD_READ; + cmd_r <= `MOD_BIT_CMD_READ_; end end `CMDW_CCC_OD, @@ -337,48 +277,120 @@ module i3c_controller_word ( `CMDW_MSG_TX: begin if (i == 8) begin // T - cmd <= {`MOD_BIT_CMD_WRITE_,clk_sel_lut,~^cmdw_body}; + cmd_r <= `MOD_BIT_CMD_WRITE_; + cmd_wr <= ~^cmdw_body; end else begin // SDO/BCAST+CCC - cmd <= {`MOD_BIT_CMD_WRITE_,clk_sel_lut,cmdw_body[7 - i[2:0]]}; + cmd_r <= `MOD_BIT_CMD_WRITE_; + cmd_wr <= cmdw_body[7 - i[2:0]]; end end `CMDW_STOP: begin - cmd <= `MOD_BIT_CMD_STOP_OD; + cmd_r <= `MOD_BIT_CMD_STOP_; end `CMDW_DAA_DEV_CHAR_1, `CMDW_DAA_DEV_CHAR_2: begin - cmd <= `MOD_BIT_CMD_READ; + cmd_r <= `MOD_BIT_CMD_READ_; end `CMDW_IBI_MDB: begin if (i == 8) begin // T - cmd <= `MOD_BIT_CMD_READ; + cmd_r <= `MOD_BIT_CMD_READ_; end else begin // MDB - cmd <= `MOD_BIT_CMD_READ; + cmd_r <= `MOD_BIT_CMD_READ_; end end default: begin sm <= `CMDW_NOP; end endcase + end + transfer: begin + if (cmd_ready) begin + smt <= resolve; + end + end + resolve: begin + if (rx_valid) begin + i <= i + 1; + smt <= i == i_ | cmdw_nacked ? get : setup; + + case (sm) + `CMDW_DYN_ADDR, + `CMDW_TARGET_ADDR_OD, + `CMDW_TARGET_ADDR_PP, + `CMDW_BCAST_7E_W1, + `CMDW_BCAST_7E_W0: begin + if (do_ack & rx !== 1'b0) begin + sm <= `CMDW_STOP; + smt <= setup; + cmdw_nack <= 1'b1; // Tick + // Due to NACK'ED STOP inheriting NACK'ED word i value, + // this flag makes sm goto get after STOP cmd. + cmdw_nacked <= 1'b1; + end + end + `CMDW_MSG_RX: begin + if (do_rx_t & rx === 1'b0) begin + sm <= `CMDW_STOP; + smt <= setup; + cmdw_nack <= 1'b1; + cmdw_nacked <= 1'b1; + end + end + default: begin + end + endcase + + case (sm) + `CMDW_NOP, + `CMDW_STOP: begin + ibi_requested <= ibi_requested; + end + `CMDW_BCAST_7E_W0: begin + ibi_da_reg[8-i] <= rx; + ibi_requested <= i < 6 & rx === 1'b0 ? 1'b1 : ibi_requested; + end + `CMDW_MSG_RX: begin + if (i == 8) begin + cmdw_rx_valid <= 1'b1; + end + cmdw_rx_reg[8-i] <= rx; + end + `CMDW_IBI_MDB: begin + if (i == 8) begin + ibi_tick <= 1'b1; + end + ibi_mdb_reg[8-i] <= rx; + end + `CMDW_DAA_DEV_CHAR_1, + `CMDW_DAA_DEV_CHAR_2: begin + if (i == 31) begin + pid_bcr_dcr_tick <= 1'b1; + end + pid_bcr_dcr[31 - i] <= rx; + end + default: begin + end + endcase end end + default: begin + smt <= get; + end endcase end - rx_sampled <= rx_valid ? rx : rx_sampled; - cmd_ready_reg <= cmd_ready; end - assign cmdw_ready = smt == setup; // i == 0 & cmd_ready_reg & reset_n; + assign cmdw_ready = smt == get; assign cmdw_header = cmdw[`CMDW_HEADER_WIDTH+8 -: `CMDW_HEADER_WIDTH+1]; assign cmdw_rx = cmdw_rx_reg[8:1]; - assign clk_sel = clk_sel_reg[1]; assign ibi_da = ibi_da_reg [8:2]; assign ibi_mdb = ibi_mdb_reg[8:1]; assign ibi_enable = rmap_ibi_config[0]; assign ibi_auto = rmap_ibi_config[1]; assign cmd_valid = smt == transfer; + assign cmd = {cmd_r, sg, cmd_wr}; endmodule diff --git a/library/i3c_controller/i3c_controller_host_interface/i3c_controller_cmd_parser.v b/library/i3c_controller/i3c_controller_host_interface/i3c_controller_cmd_parser.v index 498321d1962..54ab3f6e75c 100644 --- a/library/i3c_controller/i3c_controller_host_interface/i3c_controller_cmd_parser.v +++ b/library/i3c_controller/i3c_controller_host_interface/i3c_controller_cmd_parser.v @@ -150,7 +150,9 @@ module i3c_controller_cmd_parser ( end ccc_await: begin cmdr2 <= cmd[7:0]; - sm <= cmd_valid ? xfer_await : sm; + if (cmd_valid) begin + sm <= xfer_await; + end end receipt: begin if (cmdr_ready) begin @@ -181,7 +183,7 @@ module i3c_controller_cmd_parser ( assign cmdr = {4'd0, cmdr_error, 4'd0, cmdr1_len, cmdr_sync}; assign cmdr_valid = sm == receipt; - assign buffer_len_valid = sm == buffer_setup & cmdp_buffer_len != 0; + assign buffer_len_valid = sm == buffer_setup; assign rd_bytes_valid = buffer_len_valid & ~cmdp_rnw; assign wr_bytes_valid = buffer_len_valid & cmdp_rnw; // For read bytes (write to peripheral), it is either all transfered or none, diff --git a/library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface.v b/library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface.v index 6ea260575b4..c449f9428e0 100644 --- a/library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface.v +++ b/library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface.v @@ -241,6 +241,7 @@ module i3c_controller_host_interface #( ) i_i3c_controller_write_byte ( .clk(clk_w), .reset_n(reset_n), + .cancel(cmdp_cancelled), .u32_ready(sdi_ready_w), .u32_valid(sdi_valid_w), .u32(sdi_w), diff --git a/library/i3c_controller/i3c_controller_host_interface/i3c_controller_regmap.v b/library/i3c_controller/i3c_controller_host_interface/i3c_controller_regmap.v index bb317cbd838..31c152baf35 100644 --- a/library/i3c_controller/i3c_controller_host_interface/i3c_controller_regmap.v +++ b/library/i3c_controller/i3c_controller_host_interface/i3c_controller_regmap.v @@ -461,17 +461,17 @@ module i3c_controller_regmap #( smt <= cmd_setup; k <= 'd0; end else begin + // The same BRAM provides both cmd and sdo, + // thefore a request-like interface is used + if (smt[1] == 1'b0) begin + j <= 0; + end case (smt) cmd_setup: begin if (offload_trigger | k != 0) begin smt <= cmd_transfer; - if (k == ops_offload_len - 1) begin - k <= 0; - end else begin - k <= k + 1; - end + k <= k == ops_offload_len - 1 ? 0 : k + 1; end - j <= 0; end cmd_transfer: begin if (cmd_ready) begin @@ -480,18 +480,16 @@ module i3c_controller_regmap #( end sdo_setup: begin smt <= sdo_transfer; + j <= j + 1; end sdo_transfer: begin + // New payload requested is cmd or sdo? if (cmd_ready) begin smt <= cmd_setup; end else if (sdo_ready) begin smt <= sdo_setup; - j <= j + 1; end end - default: begin - smt <= cmd_setup; - end endcase end end diff --git a/library/i3c_controller/i3c_controller_host_interface/i3c_controller_write_byte.v b/library/i3c_controller/i3c_controller_host_interface/i3c_controller_write_byte.v index 6a4c4152a18..62d834f89b6 100644 --- a/library/i3c_controller/i3c_controller_host_interface/i3c_controller_write_byte.v +++ b/library/i3c_controller/i3c_controller_host_interface/i3c_controller_write_byte.v @@ -43,8 +43,9 @@ `default_nettype wire module i3c_controller_write_byte ( - input clk, - input reset_n, + input clk, + input reset_n, + input cancel, input u32_ready, output u32_valid, @@ -68,6 +69,7 @@ module i3c_controller_write_byte ( reg [7:0] u32_reg [3:0]; reg [11:0] u8_lvl_reg; reg [1:0] c; + reg cancel_reg; always @(posedge clk) begin if (!reset_n) begin @@ -77,23 +79,28 @@ module i3c_controller_write_byte ( case (sm) idle: begin if (u8_len_valid) begin + // In if to hold old lvl until next cmd, after cmdr resolves. u8_lvl_reg <= u8_len; end - sm <= u8_len_valid & u8_len != 0 & u32_ready ? transfer : idle; + sm <= u8_len_valid & u8_len != 0 ? transfer : idle; c <= 2'b00; + cancel_reg <= 1'b0; end transfer: begin if (u8_valid) begin // tick u32_reg[c] <= u8; u8_lvl_reg <= u8_lvl_reg - 12'b1; c <= c + 1; - if (c == 2'b11 | u8_lvl_reg == 12'd1) begin + // Cancel always occur with at least 1 byte at the same cc as + // u8_valid + if (c == 2'b11 | u8_lvl_reg == 12'd1 | cancel) begin sm <= move; end + cancel_reg <= cancel; end end move: begin - sm <= u32_ready ? (~|u8_lvl_reg ? idle : transfer) : sm; + sm <= u32_ready ? (~|u8_lvl_reg | cancel_reg ? idle : transfer) : sm; end default: begin sm <= idle; diff --git a/library/i3c_controller/interfaces/i3c_controller_rmap_rtl.xml b/library/i3c_controller/interfaces/i3c_controller_rmap_rtl.xml index 7be2541b652..ca1679573df 100644 --- a/library/i3c_controller/interfaces/i3c_controller_rmap_rtl.xml +++ b/library/i3c_controller/interfaces/i3c_controller_rmap_rtl.xml @@ -122,12 +122,12 @@ required 9 - in + out optional 9 - out + in diff --git a/projects/__i3c_ardz/Makefile b/projects/ad405x_i3c_ardz/Makefile similarity index 100% rename from projects/__i3c_ardz/Makefile rename to projects/ad405x_i3c_ardz/Makefile diff --git a/projects/__i3c_ardz/common/__i3c_ardz_bd.tcl b/projects/ad405x_i3c_ardz/common/ad405x_i3c_ardz_bd.tcl similarity index 100% rename from projects/__i3c_ardz/common/__i3c_ardz_bd.tcl rename to projects/ad405x_i3c_ardz/common/ad405x_i3c_ardz_bd.tcl diff --git a/projects/__i3c_ardz/coraz7s/Makefile b/projects/ad405x_i3c_ardz/coraz7s/Makefile similarity index 84% rename from projects/__i3c_ardz/coraz7s/Makefile rename to projects/ad405x_i3c_ardz/coraz7s/Makefile index 3ca77e1c656..751376bcb86 100644 --- a/projects/__i3c_ardz/coraz7s/Makefile +++ b/projects/ad405x_i3c_ardz/coraz7s/Makefile @@ -4,15 +4,16 @@ ## Auto-generated, do not modify! #################################################################################### -PROJECT_NAME := __i3c_ardz_coraz7s +PROJECT_NAME := ad405x_i3c_ardz_coraz7s -M_DEPS += ../common/__i3c_ardz_bd.tcl +M_DEPS += ../common/ad405x_i3c_ardz_bd.tcl M_DEPS += ../../scripts/adi_pd.tcl M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl M_DEPS += ../../../library/i3c_controller/scripts/i3c_controller.tcl -LIB_DEPS += axi_clkgen +LIB_DEPS += axi_dmac +LIB_DEPS += axi_pwm_gen LIB_DEPS += axi_sysid LIB_DEPS += i3c_controller/i3c_controller_host_interface LIB_DEPS += i3c_controller/i3c_controller_core diff --git a/projects/__i3c_ardz/coraz7s/system_bd.tcl b/projects/ad405x_i3c_ardz/coraz7s/system_bd.tcl similarity index 90% rename from projects/__i3c_ardz/coraz7s/system_bd.tcl rename to projects/ad405x_i3c_ardz/coraz7s/system_bd.tcl index 1f9d6b7cd86..e313de658d6 100644 --- a/projects/__i3c_ardz/coraz7s/system_bd.tcl +++ b/projects/ad405x_i3c_ardz/coraz7s/system_bd.tcl @@ -1,6 +1,6 @@ source $ad_hdl_dir/projects/common/coraz7s/coraz7s_system_bd.tcl source $ad_hdl_dir/projects/scripts/adi_pd.tcl -source ../common/__i3c_ardz_bd.tcl +source ../common/ad405x_i3c_ardz_bd.tcl set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt; diff --git a/projects/__i3c_ardz/coraz7s/system_constr.xdc b/projects/ad405x_i3c_ardz/coraz7s/system_constr.xdc similarity index 98% rename from projects/__i3c_ardz/coraz7s/system_constr.xdc rename to projects/ad405x_i3c_ardz/coraz7s/system_constr.xdc index 25a45f47966..e313afd9c7d 100644 --- a/projects/__i3c_ardz/coraz7s/system_constr.xdc +++ b/projects/ad405x_i3c_ardz/coraz7s/system_constr.xdc @@ -1,4 +1,4 @@ -# __i3c_ardz I3C interface +# ad405x_i3c_ardz I3C interface # Ultrascale devices could use IOB_TRI_REG. # Since IOB_TRI_REG is not available in the zynq7000 the tristate flip-flop is placed in the device fabric. diff --git a/projects/__i3c_ardz/coraz7s/system_project.tcl b/projects/ad405x_i3c_ardz/coraz7s/system_project.tcl similarity index 71% rename from projects/__i3c_ardz/coraz7s/system_project.tcl rename to projects/ad405x_i3c_ardz/coraz7s/system_project.tcl index f722e57acef..9aa7d9ce54e 100644 --- a/projects/__i3c_ardz/coraz7s/system_project.tcl +++ b/projects/ad405x_i3c_ardz/coraz7s/system_project.tcl @@ -2,12 +2,12 @@ source ../../../scripts/adi_env.tcl source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl source $ad_hdl_dir/projects/scripts/adi_board.tcl -adi_project __i3c_ardz_coraz7s +adi_project ad405x_i3c_ardz_coraz7s -adi_project_files __i3c_ardz_coraz7s [list \ +adi_project_files ad405x_i3c_ardz_coraz7s [list \ "$ad_hdl_dir/library/common/ad_iobuf.v" \ "system_top.v" \ "system_constr.xdc" \ "$ad_hdl_dir/projects/common/coraz7s/coraz7s_system_constr.xdc"] -adi_project_run __i3c_ardz_coraz7s +adi_project_run ad405x_i3c_ardz_coraz7s diff --git a/projects/__i3c_ardz/coraz7s/system_top.v b/projects/ad405x_i3c_ardz/coraz7s/system_top.v similarity index 99% rename from projects/__i3c_ardz/coraz7s/system_top.v rename to projects/ad405x_i3c_ardz/coraz7s/system_top.v index 44a95f12ef7..d9fae2f3bb0 100644 --- a/projects/__i3c_ardz/coraz7s/system_top.v +++ b/projects/ad405x_i3c_ardz/coraz7s/system_top.v @@ -63,8 +63,7 @@ module system_top ( inout i3c_controller_0_sda, inout [ 1:0] btn, - inout [ 5:0] led -); + inout [ 5:0] led); // internal signals