diff --git a/.github/CODEOWNERS b/.github/CODEOWNERS index 92909d3341..72933fa101 100644 --- a/.github/CODEOWNERS +++ b/.github/CODEOWNERS @@ -139,6 +139,9 @@ # Code owners for adrv9026 folder /projects/adrv9026/ andrei.dragomir@analog.com iulia.moldovan@analog.com +# Code owners for adrv904x folder +/projects/adrv904x/ andrei.dragomir@analog.com iulia.moldovan@analog.com + # Code owners for adrv9361z7035 folder /projects/adrv9361z7035/ andrei.grozav@analog.com jorge.marques@analog.com diff --git a/docs/projects/adrv904x/index.rst b/docs/projects/adrv904x/index.rst index c4fafd8a46..b5b29b13bc 100644 --- a/docs/projects/adrv904x/index.rst +++ b/docs/projects/adrv904x/index.rst @@ -35,6 +35,9 @@ Supported carriers * - EVAL-ADRV904x - :xilinx:`ZCU102` - FMC HPC0 + * - + - :xilinx:`VCK190` + - FMCP1 Block design ------------------------------------------------------------------------------- @@ -87,9 +90,8 @@ for each project. **system_project.tcl** file, located in hdl/projects/adrv904x/$CARRIER/system_project.tcl -.. warning:: - - ``Lane Rate = I/Q Sample Rate x M x N' x (66 \ 64) \ L`` +.. math:: + Lane Rate = Sample Rate*\frac{M}{L}*N'* \frac{66}{64} The following are the parameters of this project that can be configured: @@ -120,18 +122,18 @@ CPU/Memory interconnects addresses The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL (see more at :ref:`architecture`). -==================== =========== -Instance ZynqMP -==================== =========== -axi_adrv904x_tx_jesd 0x84A90000 -axi_adrv904x_rx_jesd 0x84AA0000 -axi_adrv904x_tx_dma 0x9c420000 -axi_adrv904x_rx_dma 0x9c400000 -tx_adrv904x_tpl_core 0x84A04000 -rx_adrv904x_tpl_core 0x84A00000 -axi_adrv904x_tx_xcvr 0x84A80000 -axi_adrv904x_rx_xcvr 0x84A60000 -==================== =========== +==================== =========== =========== +Instance ZynqMP Versal +==================== =========== =========== +axi_adrv904x_tx_jesd 0x84A90000 0xA4A90000 +axi_adrv904x_rx_jesd 0x84AA0000 0xA4AA0000 +axi_adrv904x_tx_dma 0x9C420000 0xBC420000 +axi_adrv904x_rx_dma 0x9C400000 0xBC400000 +tx_adrv904x_tpl_core 0x84A04000 0xA4A04000 +rx_adrv904x_tpl_core 0x84A00000 0xA4A00000 +axi_adrv904x_tx_xcvr 0x84A80000 0xA4A80000 +axi_adrv904x_rx_xcvr 0x84A60000 0xA4A60000 +==================== =========== =========== SPI connections ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -275,9 +277,9 @@ for that project (adrv904x/carrier or adrv904x/carrier). +-------------------+------------------------------------------------------+ | Parameter | Default value of the parameters depending on carrier | +-------------------+---------------------------+--------------------------+ - | | ZCU102 | + | | ZCU102/VCK190 | +===================+===========================+==========================+ - | JESD_MODE | 64B66B | + | JESD_MODE | 64B66B | +-------------------+---------------------------+--------------------------+ | RX_LANE_RATE | 16.22 | +-------------------+---------------------------+--------------------------+ @@ -361,7 +363,8 @@ Here you can find the quick start guides available for these evaluation boards: Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheet: :adi:`ADRV9040 ` +- Product datasheets: + - `ADRV9040 `__ HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/projects/adrv904x/common/adrv904x_bd.tcl b/projects/adrv904x/common/adrv904x_bd.tcl index f75329af4b..9a00113962 100644 --- a/projects/adrv904x/common/adrv904x_bd.tcl +++ b/projects/adrv904x/common/adrv904x_bd.tcl @@ -3,6 +3,18 @@ ### SPDX short identifier: ADIBSD ############################################################################### +if {![info exists ADI_PHY_SEL]} { + set ADI_PHY_SEL 1 +} + +if {![info exists INTF_CFG]} { + set INTF_CFG RXTX +} + +if {![info exists TRANSCEIVER_TYPE]} { + set TRANSCEIVER_TYPE GTY +} + set JESD_MODE $ad_project_params(JESD_MODE) set TX_LANE_RATE $ad_project_params(TX_LANE_RATE) set RX_LANE_RATE $ad_project_params(RX_LANE_RATE) @@ -31,6 +43,7 @@ if {$JESD_MODE == "8B10B"} { } source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl +source $ad_hdl_dir/projects/common/xilinx/adi_fir_filter_bd.tcl source $ad_hdl_dir/projects/common/xilinx/data_offload_bd.tcl # TX parameters @@ -79,14 +92,15 @@ set do_axi_data_width 512 create_bd_port -dir I core_clk # dac peripherals - -ad_ip_instance axi_adxcvr axi_adrv904x_tx_xcvr -ad_ip_parameter axi_adrv904x_tx_xcvr CONFIG.LINK_MODE $ENCODER_SEL -ad_ip_parameter axi_adrv904x_tx_xcvr CONFIG.NUM_OF_LANES $TX_NUM_OF_LANES -ad_ip_parameter axi_adrv904x_tx_xcvr CONFIG.QPLL_ENABLE 1 -ad_ip_parameter axi_adrv904x_tx_xcvr CONFIG.TX_OR_RX_N 1 -ad_ip_parameter axi_adrv904x_tx_xcvr CONFIG.SYS_CLK_SEL 3 -ad_ip_parameter axi_adrv904x_tx_xcvr CONFIG.OUT_CLK_SEL 3 +if {$ADI_PHY_SEL == 1} { + ad_ip_instance axi_adxcvr axi_adrv904x_tx_xcvr + ad_ip_parameter axi_adrv904x_tx_xcvr CONFIG.LINK_MODE $ENCODER_SEL + ad_ip_parameter axi_adrv904x_tx_xcvr CONFIG.NUM_OF_LANES $TX_NUM_OF_LANES + ad_ip_parameter axi_adrv904x_tx_xcvr CONFIG.QPLL_ENABLE 1 + ad_ip_parameter axi_adrv904x_tx_xcvr CONFIG.TX_OR_RX_N 1 + ad_ip_parameter axi_adrv904x_tx_xcvr CONFIG.SYS_CLK_SEL 3 + ad_ip_parameter axi_adrv904x_tx_xcvr CONFIG.OUT_CLK_SEL 3 +} adi_axi_jesd204_tx_create axi_adrv904x_tx_jesd $TX_NUM_OF_LANES $TX_NUM_LINKS $ENCODER_SEL ad_ip_parameter axi_adrv904x_tx_jesd/tx CONFIG.TPL_DATA_PATH_WIDTH $TX_DATAPATH_WIDTH @@ -117,7 +131,6 @@ adi_tpl_jesd204_tx_create tx_adrv904x_tpl_core $TX_NUM_OF_LANES \ ad_ip_parameter tx_adrv904x_tpl_core/dac_tpl_core CONFIG.IQCORRECTION_DISABLE 0 - ad_ip_instance axi_dmac axi_adrv904x_tx_dma ad_ip_parameter axi_adrv904x_tx_dma CONFIG.DMA_TYPE_SRC 0 ad_ip_parameter axi_adrv904x_tx_dma CONFIG.DMA_TYPE_DEST 1 @@ -131,18 +144,25 @@ ad_ip_parameter axi_adrv904x_tx_dma CONFIG.DMA_DATA_WIDTH_SRC [expr min(512, $da ad_ip_parameter axi_adrv904x_tx_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_dma_data_width # adc peripherals - -ad_ip_instance axi_adxcvr axi_adrv904x_rx_xcvr -ad_ip_parameter axi_adrv904x_rx_xcvr CONFIG.LINK_MODE $ENCODER_SEL -ad_ip_parameter axi_adrv904x_rx_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES -ad_ip_parameter axi_adrv904x_rx_xcvr CONFIG.QPLL_ENABLE 0 -ad_ip_parameter axi_adrv904x_rx_xcvr CONFIG.TX_OR_RX_N 0 -ad_ip_parameter axi_adrv904x_rx_xcvr CONFIG.SYS_CLK_SEL 3 -ad_ip_parameter axi_adrv904x_rx_xcvr CONFIG.OUT_CLK_SEL 3 - +if {$ADI_PHY_SEL == 1} { + ad_ip_instance axi_adxcvr axi_adrv904x_rx_xcvr + ad_ip_parameter axi_adrv904x_rx_xcvr CONFIG.LINK_MODE $ENCODER_SEL + ad_ip_parameter axi_adrv904x_rx_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES + ad_ip_parameter axi_adrv904x_rx_xcvr CONFIG.QPLL_ENABLE 0 + ad_ip_parameter axi_adrv904x_rx_xcvr CONFIG.TX_OR_RX_N 0 + ad_ip_parameter axi_adrv904x_rx_xcvr CONFIG.SYS_CLK_SEL 3 + ad_ip_parameter axi_adrv904x_rx_xcvr CONFIG.OUT_CLK_SEL 3 +} adi_axi_jesd204_rx_create axi_adrv904x_rx_jesd $RX_NUM_OF_LANES $RX_NUM_LINKS $ENCODER_SEL ad_ip_parameter axi_adrv904x_rx_jesd/rx CONFIG.TPL_DATA_PATH_WIDTH $RX_DATAPATH_WIDTH +if {$ADI_PHY_SEL == 0} { + # reset generator + ad_ip_instance proc_sys_reset core_clk_rstgen + ad_connect core_clk core_clk_rstgen/slowest_sync_clk + ad_connect $sys_cpu_resetn core_clk_rstgen/ext_reset_in +} + ad_ip_instance util_cpack2 util_adrv904x_rx_cpack [list \ NUM_OF_CHANNELS $RX_NUM_OF_CONVERTERS \ SAMPLES_PER_CHANNEL $RX_SAMPLES_PER_CHANNEL \ @@ -179,59 +199,6 @@ ad_ip_instance axi_dmac axi_adrv904x_rx_dma ad_ip_parameter axi_adrv904x_rx_dma CONFIG.DMA_DATA_WIDTH_SRC $adc_dma_data_width ad_ip_parameter axi_adrv904x_rx_dma CONFIG.DMA_DATA_WIDTH_DEST [expr min(512, $adc_dma_data_width)] -# common cores - -ad_ip_instance util_adxcvr util_adrv904x_xcvr -ad_ip_parameter util_adrv904x_xcvr CONFIG.RX_NUM_OF_LANES $RX_NUM_OF_LANES -ad_ip_parameter util_adrv904x_xcvr CONFIG.TX_NUM_OF_LANES $TX_NUM_OF_LANES -ad_ip_parameter util_adrv904x_xcvr CONFIG.LINK_MODE $ENCODER_SEL -ad_ip_parameter util_adrv904x_xcvr CONFIG.RX_LANE_RATE $RX_LANE_RATE -ad_ip_parameter util_adrv904x_xcvr CONFIG.TX_LANE_RATE $TX_LANE_RATE -ad_ip_parameter util_adrv904x_xcvr CONFIG.RX_OUT_DIV 1 -ad_ip_parameter util_adrv904x_xcvr CONFIG.TX_OUT_DIV 1 -ad_ip_parameter util_adrv904x_xcvr CONFIG.CPLL_FBDIV 2 -ad_ip_parameter util_adrv904x_xcvr CONFIG.CPLL_FBDIV_4_5 5 -ad_ip_parameter util_adrv904x_xcvr CONFIG.RX_CLK25_DIV 20 -ad_ip_parameter util_adrv904x_xcvr CONFIG.TX_CLK25_DIV 20 -ad_ip_parameter util_adrv904x_xcvr CONFIG.RX_PMA_CFG 0x280A -ad_ip_parameter util_adrv904x_xcvr CONFIG.RX_CDR_CFG 0x0b000023ff10400020 -ad_ip_parameter util_adrv904x_xcvr CONFIG.QPLL_FBDIV 33 -ad_ip_parameter util_adrv904x_xcvr CONFIG.QPLL_REFCLK_DIV 1 -ad_ip_parameter util_adrv904x_xcvr CONFIG.TX_LANE_INVERT 15 -ad_ip_parameter util_adrv904x_xcvr CONFIG.RX_LANE_INVERT 255 -ad_ip_parameter util_adrv904x_xcvr CONFIG.CPLL_CFG0 0x1fa -ad_ip_parameter util_adrv904x_xcvr CONFIG.CPLL_CFG1 0x23 -ad_ip_parameter util_adrv904x_xcvr CONFIG.CPLL_CFG2 0x2 -ad_ip_parameter util_adrv904x_xcvr CONFIG.A_TXDIFFCTRL 0xC -ad_ip_parameter util_adrv904x_xcvr CONFIG.RXCDR_CFG0 0x3 -ad_ip_parameter util_adrv904x_xcvr CONFIG.RXCDR_CFG2_GEN2 0x269 -ad_ip_parameter util_adrv904x_xcvr CONFIG.RXCDR_CFG2_GEN4 0x164 -ad_ip_parameter util_adrv904x_xcvr CONFIG.RXCDR_CFG3 0x12 -ad_ip_parameter util_adrv904x_xcvr CONFIG.RXCDR_CFG3_GEN2 0x12 -ad_ip_parameter util_adrv904x_xcvr CONFIG.RXCDR_CFG3_GEN3 0x12 -ad_ip_parameter util_adrv904x_xcvr CONFIG.RXCDR_CFG3_GEN4 0x12 -ad_ip_parameter util_adrv904x_xcvr CONFIG.CH_HSPMUX 0x6868 -ad_ip_parameter util_adrv904x_xcvr CONFIG.PREIQ_FREQ_BST 1 -ad_ip_parameter util_adrv904x_xcvr CONFIG.RXPI_CFG0 0x4 -ad_ip_parameter util_adrv904x_xcvr CONFIG.RXPI_CFG1 0x0 -ad_ip_parameter util_adrv904x_xcvr CONFIG.TXPI_CFG 0x0 -ad_ip_parameter util_adrv904x_xcvr CONFIG.TX_PI_BIASSET 3 -ad_ip_parameter util_adrv904x_xcvr CONFIG.POR_CFG 0x0 -ad_ip_parameter util_adrv904x_xcvr CONFIG.QPLL_CFG0 0x333c -ad_ip_parameter util_adrv904x_xcvr CONFIG.QPLL_CFG4 0x45 -ad_ip_parameter util_adrv904x_xcvr CONFIG.PPF0_CFG 0xF00 -ad_ip_parameter util_adrv904x_xcvr CONFIG.QPLL_CP 0xFF -ad_ip_parameter util_adrv904x_xcvr CONFIG.QPLL_CP_G3 0xF -ad_ip_parameter util_adrv904x_xcvr CONFIG.QPLL_LPF 0x31D -ad_ip_parameter util_adrv904x_xcvr CONFIG.RXDFE_KH_CFG2 {0x2631} -ad_ip_parameter util_adrv904x_xcvr CONFIG.RXDFE_KH_CFG3 {0x411C} -ad_ip_parameter util_adrv904x_xcvr CONFIG.RX_WIDEMODE_CDR {"01"} -ad_ip_parameter util_adrv904x_xcvr CONFIG.RX_XMODE_SEL {"0"} -ad_ip_parameter util_adrv904x_xcvr CONFIG.TXPI_CFG0 {0x0000} -ad_ip_parameter util_adrv904x_xcvr CONFIG.TXPI_CFG1 {0x0000} - -# xcvr interfaces - set tx_ref_clk tx_ref_clk_0 set rx_ref_clk rx_ref_clk_0 set tx_ref_clk_1 tx_ref_clk_1 @@ -241,29 +208,149 @@ create_bd_port -dir I $tx_ref_clk create_bd_port -dir I $rx_ref_clk create_bd_port -dir I $tx_ref_clk_1 create_bd_port -dir I $rx_ref_clk_1 -ad_connect $sys_cpu_resetn util_adrv904x_xcvr/up_rstn -ad_connect $sys_cpu_clk util_adrv904x_xcvr/up_clk - -# Tx -ad_xcvrcon util_adrv904x_xcvr axi_adrv904x_tx_xcvr axi_adrv904x_tx_jesd {} {} core_clk - -ad_xcvrpll $tx_ref_clk util_adrv904x_xcvr/qpll_ref_clk_0 -ad_xcvrpll axi_adrv904x_tx_xcvr/up_pll_rst util_adrv904x_xcvr/up_qpll_rst_0 -ad_xcvrpll $tx_ref_clk_1 util_adrv904x_xcvr/qpll_ref_clk_4 -ad_xcvrpll axi_adrv904x_tx_xcvr/up_pll_rst util_adrv904x_xcvr/up_qpll_rst_4 - -# Rx -ad_xcvrcon util_adrv904x_xcvr axi_adrv904x_rx_xcvr axi_adrv904x_rx_jesd {} {} core_clk - -for {set i 0} {$i < $RX_NUM_OF_LANES} {incr i} { - if {$i < [expr $RX_NUM_OF_LANES/2]} { - ad_xcvrpll $rx_ref_clk util_adrv904x_xcvr/cpll_ref_clk_$i - ad_xcvrpll axi_adrv904x_rx_xcvr/up_pll_rst util_adrv904x_xcvr/up_cpll_rst_$i - } else { - ad_xcvrpll $rx_ref_clk_1 util_adrv904x_xcvr/cpll_ref_clk_$i - ad_xcvrpll axi_adrv904x_rx_xcvr/up_pll_rst util_adrv904x_xcvr/up_cpll_rst_$i + +# common cores +if {$ADI_PHY_SEL == 1} { + ad_ip_instance util_adxcvr util_adrv904x_xcvr + ad_ip_parameter util_adrv904x_xcvr CONFIG.RX_NUM_OF_LANES $RX_NUM_OF_LANES + ad_ip_parameter util_adrv904x_xcvr CONFIG.TX_NUM_OF_LANES $TX_NUM_OF_LANES + ad_ip_parameter util_adrv904x_xcvr CONFIG.LINK_MODE $ENCODER_SEL + ad_ip_parameter util_adrv904x_xcvr CONFIG.RX_LANE_RATE $RX_LANE_RATE + ad_ip_parameter util_adrv904x_xcvr CONFIG.TX_LANE_RATE $TX_LANE_RATE + ad_ip_parameter util_adrv904x_xcvr CONFIG.RX_OUT_DIV 1 + ad_ip_parameter util_adrv904x_xcvr CONFIG.TX_OUT_DIV 1 + ad_ip_parameter util_adrv904x_xcvr CONFIG.CPLL_FBDIV 4 + ad_ip_parameter util_adrv904x_xcvr CONFIG.CPLL_FBDIV_4_5 5 + ad_ip_parameter util_adrv904x_xcvr CONFIG.RX_CLK25_DIV 20 + ad_ip_parameter util_adrv904x_xcvr CONFIG.TX_CLK25_DIV 20 + ad_ip_parameter util_adrv904x_xcvr CONFIG.RX_PMA_CFG 0x001E7080 + ad_ip_parameter util_adrv904x_xcvr CONFIG.RX_CDR_CFG 0x0b000023ff10400020 + ad_ip_parameter util_adrv904x_xcvr CONFIG.QPLL_FBDIV 33 + ad_ip_parameter util_adrv904x_xcvr CONFIG.QPLL_REFCLK_DIV 1 + ad_ip_parameter util_adrv904x_xcvr CONFIG.TX_LANE_INVERT 15 + ad_ip_parameter util_adrv904x_xcvr CONFIG.RX_LANE_INVERT 255 +} else { + source ../common/versal_transceiver.tcl + + set REF_CLK_RATE [ expr { [info exists ad_project_params(REF_CLK_RATE)] \ + ? $ad_project_params(REF_CLK_RATE) : 245.76 } ] + + create_bd_port -dir I gt_reset + create_bd_port -dir O gt_powergood + create_bd_port -dir O tx_resetdone + create_bd_port -dir O rx_resetdone + create_bd_port -dir I gt_reset_rx_pll_and_datapath + create_bd_port -dir I gt_reset_tx_pll_and_datapath + create_bd_port -dir I gt_reset_rx_datapath + create_bd_port -dir I gt_reset_tx_datapath + + switch $INTF_CFG { + "RXTX" { + create_versal_phy jesd204_phy_rxtx $JESD_MODE $RX_NUM_OF_LANES $TX_NUM_OF_LANES $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE $INTF_CFG + set rx_phy jesd204_phy_rxtx + set tx_phy jesd204_phy_rxtx + ad_connect $rx_ref_clk ${rx_phy}/GT_REFCLK + ad_connect gt_reset ${rx_phy}/gtreset_in + ad_connect $sys_cpu_clk ${rx_phy}/s_axi_clk + ad_connect $sys_cpu_resetn ${rx_phy}/s_axi_resetn + ad_connect ${rx_phy}/gtpowergood gt_powergood + ad_connect ${rx_phy}/gtreset_rx_datapath gt_reset_rx_datapath + ad_connect ${rx_phy}/gtreset_tx_datapath gt_reset_tx_datapath + ad_connect ${rx_phy}/gtreset_rx_pll_and_datapath gt_reset_rx_pll_and_datapath + ad_connect ${rx_phy}/gtreset_tx_pll_and_datapath gt_reset_tx_pll_and_datapath + ad_connect ${rx_phy}/rx_resetdone rx_resetdone + ad_connect ${tx_phy}/tx_resetdone tx_resetdone + } + "RX" { + create_versal_phy jesd204_phy_rx $JESD_MODE $RX_NUM_OF_LANES $RX_NUM_OF_LANES $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE $INTF_CFG + set rx_phy jesd204_phy_rx + ad_connect $tx_ref_clk ${rx_phy}/GT_REFCLK + ad_connect gt_reset ${rx_phy}/gtreset_in + ad_connect $sys_cpu_clk ${rx_phy}/s_axi_clk + ad_connect $sys_cpu_resetn ${rx_phy}/s_axi_resetn + ad_connect ${rx_phy}/gtpowergood gt_powergood + ad_connect ${rx_phy}/gtreset_rx_datapath gt_reset_rx_datapath + ad_connect ${rx_phy}/gtreset_rx_pll_and_datapath gt_reset_rx_pll_and_datapath + ad_connect ${rx_phy}/rx_resetdone rx_resetdone + } + "TX" { + create_versal_phy jesd204_phy_tx $JESD_MODE $TX_NUM_OF_LANES $TX_NUM_OF_LANES $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE $INTF_CFG + set tx_phy jesd204_phy_tx + ad_connect $ref_clock ${tx_phy}/GT_REFCLK + ad_connect gt_reset ${tx_phy}/gtreset_in + ad_connect $sys_cpu_clk ${tx_phy}/s_axi_clk + ad_connect $sys_cpu_resetn ${tx_phy}/s_axi_resetn + ad_connect ${tx_phy}/gtpowergood gt_powergood + ad_connect ${tx_phy}/gtreset_tx_datapath gt_reset_tx_datapath + ad_connect ${tx_phy}/gtreset_tx_pll_and_datapath gt_reset_tx_pll_and_datapath + ad_connect ${tx_phy}/tx_resetdone tx_resetdone + } } } +# xcvr interfaces + +if {$ADI_PHY_SEL == 1} { + ad_connect $sys_cpu_resetn util_adrv904x_xcvr/up_rstn + ad_connect $sys_cpu_clk util_adrv904x_xcvr/up_clk + + # Tx + ad_xcvrcon util_adrv904x_xcvr axi_adrv904x_tx_xcvr axi_adrv904x_tx_jesd {} {} core_clk + + ad_xcvrpll $tx_ref_clk util_adrv904x_xcvr/qpll_ref_clk_0 + ad_xcvrpll axi_adrv904x_tx_xcvr/up_pll_rst util_adrv904x_xcvr/up_qpll_rst_0 + ad_xcvrpll $tx_ref_clk_1 util_adrv904x_xcvr/qpll_ref_clk_4 + ad_xcvrpll axi_adrv904x_tx_xcvr/up_pll_rst util_adrv904x_xcvr/up_qpll_rst_4 + + # Rx + ad_xcvrcon util_adrv904x_xcvr axi_adrv904x_rx_xcvr axi_adrv904x_rx_jesd {} {} core_clk + + for {set i 0} {$i < $RX_NUM_OF_LANES} {incr i} { + if {$i < [expr $RX_NUM_OF_LANES/2]} { + ad_xcvrpll $rx_ref_clk util_adrv904x_xcvr/cpll_ref_clk_$i + ad_xcvrpll axi_adrv904x_rx_xcvr/up_pll_rst util_adrv904x_xcvr/up_cpll_rst_$i + } else { + ad_xcvrpll $rx_ref_clk_1 util_adrv904x_xcvr/cpll_ref_clk_$i + ad_xcvrpll axi_adrv904x_rx_xcvr/up_pll_rst util_adrv904x_xcvr/up_cpll_rst_$i + } + } +} else { + set rx_link_clock ${rx_phy}/rxusrclk_out + # Connect PHY to Link Layer + for {set i 0} {$i < $RX_NUM_OF_LANES} {incr i} { + ad_connect axi_adrv904x_rx_jesd/rx_phy${i} ${rx_phy}/rx${i} + } + + ad_connect $rx_link_clock /axi_adrv904x_rx_jesd/link_clk + ad_connect core_clk /axi_adrv904x_rx_jesd/device_clk + + if {$JESD_MODE == "8B10B"} { + create_bd_port -dir O rx_sync_0 + ad_connect axi_adrv904x_rx_jesd/phy_en_char_align ${rx_phy}/en_char_align + ad_connect axi_adrv904x_rx_jesd/sync rx_sync_0 + } else { + ad_connect GND ${rx_phy}/en_char_align + } + + create_bd_port -dir I rx_sysref_0 + ad_connect axi_adrv904x_rx_jesd/sysref rx_sysref_0 + + set tx_link_clock ${tx_phy}/txusrclk_out + # Connect PHY to Link Layer + for {set i 0} {$i < $TX_NUM_OF_LANES} {incr i} { + ad_connect axi_adrv904x_tx_jesd/tx_phy${i} ${tx_phy}/tx${i} + } + + ad_connect $tx_link_clock /axi_adrv904x_tx_jesd/link_clk + ad_connect core_clk /axi_adrv904x_tx_jesd/device_clk + + create_bd_port -dir I tx_sysref_0 + ad_connect axi_adrv904x_tx_jesd/sysref tx_sysref_0 + + if {$JESD_MODE == "8B10B"} { + create_bd_port -dir O tx_sync_0 + ad_connect axi_adrv904x_tx_jesd/sync tx_sync_0 + } +} # connections (dac) @@ -350,18 +437,21 @@ ad_connect manual_sync_or/Res tx_adrv904x_tpl_core/dac_tpl_core/dac_sync_manual_ ad_cpu_interconnect 0x44A00000 rx_adrv904x_tpl_core ad_cpu_interconnect 0x44A04000 tx_adrv904x_tpl_core -ad_cpu_interconnect 0x44A80000 axi_adrv904x_tx_xcvr +if {$ADI_PHY_SEL == 1} { + ad_cpu_interconnect 0x44A80000 axi_adrv904x_tx_xcvr + ad_cpu_interconnect 0x44A60000 axi_adrv904x_rx_xcvr +} ad_cpu_interconnect 0x44A90000 axi_adrv904x_tx_jesd ad_cpu_interconnect 0x7c420000 axi_adrv904x_tx_dma -ad_cpu_interconnect 0x44A60000 axi_adrv904x_rx_xcvr ad_cpu_interconnect 0x44AA0000 axi_adrv904x_rx_jesd ad_cpu_interconnect 0x7c400000 axi_adrv904x_rx_dma ad_cpu_interconnect 0x7c440000 $dac_data_offload_name ad_cpu_interconnect 0x7c450000 $adc_data_offload_name ad_mem_hp0_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP0 -ad_mem_hp0_interconnect $sys_cpu_clk axi_adrv904x_rx_xcvr/m_axi - +if {$ADI_PHY_SEL == 1} { + ad_mem_hp0_interconnect $sys_cpu_clk axi_adrv904x_rx_xcvr/m_axi +} # interconnect (mem/dac) ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2 @@ -374,4 +464,45 @@ ad_mem_hp3_interconnect $sys_dma_clk axi_adrv904x_tx_dma/m_src_axi ad_cpu_interrupt ps-10 mb-15 axi_adrv904x_tx_jesd/irq ad_cpu_interrupt ps-11 mb-14 axi_adrv904x_rx_jesd/irq ad_cpu_interrupt ps-13 mb-12 axi_adrv904x_tx_dma/irq -ad_cpu_interrupt ps-14 mb-11 axi_adrv904x_rx_dma/irq \ No newline at end of file +ad_cpu_interrupt ps-14 mb-11 axi_adrv904x_rx_dma/irq + +# Dummy outputs for unused lanes +if {$ADI_PHY_SEL == 1} { + if {$INTF_CFG != "TX"} { + # Unused Rx lanes + for {set i $RX_NUM_OF_LANES} {$i < 8} {incr i} { + create_bd_port -dir I rx_data_${i}_n + create_bd_port -dir I rx_data_${i}_p + } + } + if {$INTF_CFG != "RX"} { + # Unused Tx lanes + for {set i $TX_NUM_OF_LANES} {$i < 8} {incr i} { + create_bd_port -dir O tx_data_${i}_n + create_bd_port -dir O tx_data_${i}_p + } + } +} else { + if {$INTF_CFG != "TX"} { + create_bd_port -dir I -from 3 -to 0 rx_0_p + create_bd_port -dir I -from 3 -to 0 rx_0_n + ad_connect rx_0_p ${rx_phy}/rx_0_p + ad_connect rx_0_n ${rx_phy}/rx_0_n + + create_bd_port -dir I -from 3 -to 0 rx_1_p + create_bd_port -dir I -from 3 -to 0 rx_1_n + ad_connect rx_1_p ${rx_phy}/rx_1_p + ad_connect rx_1_n ${rx_phy}/rx_1_n + } + if {$INTF_CFG != "RX"} { + create_bd_port -dir O -from 3 -to 0 tx_0_p + create_bd_port -dir O -from 3 -to 0 tx_0_n + ad_connect tx_0_p ${rx_phy}/tx_0_p + ad_connect tx_0_n ${rx_phy}/tx_0_n + + create_bd_port -dir O -from 3 -to 0 tx_1_p + create_bd_port -dir O -from 3 -to 0 tx_1_n + ad_connect tx_1_p ${rx_phy}/tx_1_p + ad_connect tx_1_n ${rx_phy}/tx_1_n + } +} diff --git a/projects/adrv904x/common/adrv904x_fmc.txt b/projects/adrv904x/common/adrv904x_fmc.txt index 04abc988d5..9386756702 100755 --- a/projects/adrv904x/common/adrv904x_fmc.txt +++ b/projects/adrv904x/common/adrv904x_fmc.txt @@ -14,31 +14,31 @@ G7 LA00_CC_N FMC_CLK2TRXIC- dev_clk_n #N/A #N/A J2 CLK3_IO_P FMC_CLK2CLKCHIP+ dev_clk_buff_p #N/A #N/A J3 CLK3_IO_N FMC_CLK2CLKCHIP- dev_clk_buff_n #N/A #N/A -C6 DP0_M2C_P SERDOUT7- rx_data_n[0] #N/A #N/A -C7 DP0_M2C_N SERDOUT7+ rx_data_p[0] #N/A #N/A -A2 DP1_M2C_P SERDOUT6- rx_data_n[1] #N/A #N/A -A3 DP1_M2C_N SERDOUT6+ rx_data_p[1] #N/A #N/A -A6 DP2_M2C_P SERDOUT4- rx_data_n[2] #N/A #N/A -A7 DP2_M2C_N SERDOUT4+ rx_data_p[2] #N/A #N/A -A10 DP3_M2C_P SERDOUT5- rx_data_n[3] #N/A #N/A -A11 DP3_M2C_N SERDOUT5+ rx_data_p[3] #N/A #N/A -A14 DP4_M2C_P SERDOUT2- rx_data_n[4] #N/A #N/A -A15 DP4_M2C_N SERDOUT2+ rx_data_p[4] #N/A #N/A -A18 DP5_M2C_P SERDOUT0- rx_data_n[5] #N/A #N/A -A19 DP5_M2C_N SERDOUT0+ rx_data_p[5] #N/A #N/A -B16 DP6_M2C_P SERDOUT1- rx_data_n[6] #N/A #N/A -B17 DP6_M2C_N SERDOUT1+ rx_data_p[6] #N/A #N/A -B12 DP7_M2C_P SERDOUT3- rx_data_n[7] #N/A #N/A -B13 DP7_M2C_N SERDOUT3+ rx_data_p[7] #N/A #N/A +C6 DP0_M2C_P SERDOUT7- rx_data_p[0] #N/A #N/A +C7 DP0_M2C_N SERDOUT7+ rx_data_n[0] #N/A #N/A +A2 DP1_M2C_P SERDOUT6- rx_data_p[1] #N/A #N/A +A3 DP1_M2C_N SERDOUT6+ rx_data_n[1] #N/A #N/A +A6 DP2_M2C_P SERDOUT4- rx_data_p[2] #N/A #N/A +A7 DP2_M2C_N SERDOUT4+ rx_data_n[2] #N/A #N/A +A10 DP3_M2C_P SERDOUT5- rx_data_p[3] #N/A #N/A +A11 DP3_M2C_N SERDOUT5+ rx_data_n[3] #N/A #N/A +A14 DP4_M2C_P SERDOUT2- rx_data_p[4] #N/A #N/A +A15 DP4_M2C_N SERDOUT2+ rx_data_n[4] #N/A #N/A +A18 DP5_M2C_P SERDOUT0- rx_data_p[5] #N/A #N/A +A19 DP5_M2C_N SERDOUT0+ rx_data_n[5] #N/A #N/A +B16 DP6_M2C_P SERDOUT1- rx_data_p[6] #N/A #N/A +B17 DP6_M2C_N SERDOUT1+ rx_data_n[6] #N/A #N/A +B12 DP7_M2C_P SERDOUT3- rx_data_p[7] #N/A #N/A +B13 DP7_M2C_N SERDOUT3+ rx_data_n[7] #N/A #N/A -C2 DP0_C2M_P SERDIN0- tx_data_n[0] #N/A #N/A -C3 DP0_C2M_N SERDIN0+ tx_data_p[0] #N/A #N/A -A22 DP1_C2M_P SERDIN1- tx_data_n[1] #N/A #N/A -A23 DP1_C2M_N SERDIN1+ tx_data_p[1] #N/A #N/A -A26 DP2_C2M_P SERDIN2- tx_data_n[2] #N/A #N/A -A27 DP2_C2M_N SERDIN2+ tx_data_p[2] #N/A #N/A -A30 DP3_C2M_P SERDIN3- tx_data_n[3] #N/A #N/A -A31 DP3_C2M_N SERDIN3+ tx_data_p[3] #N/A #N/A +C2 DP0_C2M_P SERDIN0- tx_data_p[0] #N/A #N/A +C3 DP0_C2M_N SERDIN0+ tx_data_n[0] #N/A #N/A +A22 DP1_C2M_P SERDIN1- tx_data_p[1] #N/A #N/A +A23 DP1_C2M_N SERDIN1+ tx_data_n[1] #N/A #N/A +A26 DP2_C2M_P SERDIN2- tx_data_p[2] #N/A #N/A +A27 DP2_C2M_N SERDIN2+ tx_data_n[2] #N/A #N/A +A30 DP3_C2M_P SERDIN3- tx_data_p[3] #N/A #N/A +A31 DP3_C2M_N SERDIN3+ tx_data_n[3] #N/A #N/A A34 DP4_C2M_P SERDIN7+ tx_data_p[4] #N/A #N/A A35 DP4_C2M_N SERDIN7- tx_data_n[4] #N/A #N/A A38 DP5_C2M_P SERDIN6+ tx_data_p[5] #N/A #N/A @@ -52,12 +52,12 @@ H7 LA02_P SYNCOUT0+ rx_sync_p LVDS #N/A H8 LA02_N SYNCOUT0- rx_sync_n LVDS #N/A H37 LA32_P SYNCOUT1+ rx_sync_1_p LVDS #N/A H38 LA32_N SYNCOUT1- rx_sync_1_n LVDS #N/A -G33 LA31_P SYNCIN0- tx_sync_n LVDS DIFF_TERM_ADV TERM_100 -G34 LA31_N SYNCIN0+ tx_sync_p LVDS DIFF_TERM_ADV TERM_100 -G27 LA25_P SYNCIN1- tx_sync_1_n LVDS DIFF_TERM_ADV TERM_100 -G28 LA25_N SYNCIN1+ tx_sync_1_p LVDS DIFF_TERM_ADV TERM_100 -G36 LA33_P SYNCIN2- tx_sync_2_n LVDS DIFF_TERM_ADV TERM_100 -G37 LA33_N SYNCIN2+ tx_sync_2_p LVDS DIFF_TERM_ADV TERM_100 +G33 LA31_P SYNCIN0- tx_sync_p LVDS DIFF_TERM_ADV TERM_100 +G34 LA31_N SYNCIN0+ tx_sync_n LVDS DIFF_TERM_ADV TERM_100 +G27 LA25_P SYNCIN1- tx_sync_1_p LVDS DIFF_TERM_ADV TERM_100 +G28 LA25_N SYNCIN1+ tx_sync_1_n LVDS DIFF_TERM_ADV TERM_100 +G36 LA33_P SYNCIN2- tx_sync_2_p LVDS DIFF_TERM_ADV TERM_100 +G37 LA33_N SYNCIN2+ tx_sync_2_n LVDS DIFF_TERM_ADV TERM_100 D8 LA01_CC_P FPGA_SYSREF+ sysref_p LVDS DIFF_TERM_ADV TERM_100 D9 LA01_CC_N FPGA_SYSREF- sysref_n LVDS DIFF_TERM_ADV TERM_100 diff --git a/projects/adrv904x/common/versal_transceiver.tcl b/projects/adrv904x/common/versal_transceiver.tcl new file mode 100644 index 0000000000..7453e16508 --- /dev/null +++ b/projects/adrv904x/common/versal_transceiver.tcl @@ -0,0 +1,896 @@ +############################################################################### +## Copyright (C) 2024 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# Parameter description: +# ip_name : The name of the versal phy ip +# rx_num_lanes : The number of used RX lanes for the JESD mode +# tx_num_lanes : The number of used TX lanes for the JESD mode +proc create_reset_logic { + {ip_name versal_phy} + {rx_num_lanes 8} + {tx_num_lanes 8} + {intf_cfg RXTX} +} { + set rx_bridge gt_bridge_ip_0 + set asymmetric_mode [expr {$intf_cfg == "RXTX" && $rx_num_lanes != $tx_num_lanes}] + set tx_bridge [expr {$asymmetric_mode == 0 ? "gt_bridge_ip_0" : "gt_bridge_ip_1"}] + + create_bd_pin -dir I ${ip_name}/gtreset_in + create_bd_pin -dir O ${ip_name}/gtpowergood + if {$intf_cfg != "TX"} { + create_bd_pin -dir I ${ip_name}/gtreset_rx_pll_and_datapath + create_bd_pin -dir I ${ip_name}/gtreset_rx_datapath + create_bd_pin -dir O ${ip_name}/rx_resetdone + } + if {$intf_cfg != "RX"} { + create_bd_pin -dir I ${ip_name}/gtreset_tx_pll_and_datapath + create_bd_pin -dir I ${ip_name}/gtreset_tx_datapath + create_bd_pin -dir O ${ip_name}/tx_resetdone + } + # Sync resets to apb3clk + + create_bd_cell -type module -reference sync_bits ${ip_name}/gtreset_sync + ad_connect ${ip_name}/s_axi_clk ${ip_name}/gtreset_sync/out_clk + ad_connect ${ip_name}/s_axi_resetn ${ip_name}/gtreset_sync/out_resetn + ad_connect ${ip_name}/gtreset_in ${ip_name}/gtreset_sync/in_bits + ad_connect ${ip_name}/gtreset_sync/out_bits ${ip_name}/${rx_bridge}/gtreset_in + if {$asymmetric_mode} { + ad_connect ${ip_name}/gtreset_sync/out_bits ${ip_name}/${tx_bridge}/gtreset_in + } + + foreach port {pll_and_datapath datapath} { + foreach rx_tx {rx tx} { + if {($rx_tx == "rx" && $intf_cfg == "TX") || ($rx_tx == "tx" && $intf_cfg == "RX")} { + continue + } + set bridge [expr {$rx_tx == "rx" ? $rx_bridge : $tx_bridge}] + create_bd_cell -type module -reference sync_bits ${ip_name}/gtreset_${rx_tx}_${port}_sync + ad_connect ${ip_name}/s_axi_clk ${ip_name}/gtreset_${rx_tx}_${port}_sync/out_clk + ad_connect ${ip_name}/s_axi_resetn ${ip_name}/gtreset_${rx_tx}_${port}_sync/out_resetn + ad_connect ${ip_name}/gtreset_${rx_tx}_${port} ${ip_name}/gtreset_${rx_tx}_${port}_sync/in_bits + ad_connect ${ip_name}/gtreset_${rx_tx}_${port}_sync/out_bits ${ip_name}/${bridge}/reset_${rx_tx}_${port}_in + } + } + + set max_lanes [expr max($rx_num_lanes, $tx_num_lanes)] + set num_quads [expr int(ceil(1.0 * $max_lanes / 4))] + + ad_ip_instance xlconcat ${ip_name}/concat_powergood [list \ + NUM_PORTS $num_quads \ + ] + + ad_ip_instance util_reduced_logic ${ip_name}/and_powergood [list \ + C_SIZE $num_quads \ + ] + + for {set j 0} {$j < $num_quads} {incr j} { + ad_connect ${ip_name}/concat_powergood/In${j} ${ip_name}/gt_quad_base_${j}/gtpowergood + } + + ad_connect ${ip_name}/concat_powergood/dout ${ip_name}/and_powergood/Op1 + ad_connect ${ip_name}/and_powergood/Res ${ip_name}/${rx_bridge}/gtpowergood + if {$asymmetric_mode} { + ad_connect ${ip_name}/and_powergood/Res ${ip_name}/${tx_bridge}/gtpowergood + } + + for {set j 0} {$j < ${rx_num_lanes}} {incr j} { + set quad_index [expr int($j / 4)] + set ch_index [expr $j % 4] + ad_connect ${ip_name}/${rx_bridge}/gt_ilo_reset ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_iloreset + } + if {$asymmetric_mode} { + for {set j ${rx_num_lanes}} {$j < ${tx_num_lanes}} {incr j} { + set quad_index [expr int($j / 4)] + set ch_index [expr $j % 4] + ad_connect ${ip_name}/${tx_bridge}/gt_ilo_reset ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_iloreset + } + } + ad_ip_instance xlconcat ${ip_name}/xlconcat_iloresetdone [list \ + NUM_PORTS ${rx_num_lanes} \ + ] + ad_ip_instance util_reduced_logic ${ip_name}/and_iloresetdone [list \ + C_SIZE ${rx_num_lanes} \ + ] + for {set j 0} {$j < ${rx_num_lanes}} {incr j} { + set quad_index [expr int($j / 4)] + set ch_index [expr $j % 4] + ad_connect ${ip_name}/xlconcat_iloresetdone/In${j} ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_iloresetdone + } + ad_connect ${ip_name}/xlconcat_iloresetdone/dout ${ip_name}/and_iloresetdone/Op1 + ad_connect ${ip_name}/and_iloresetdone/Res ${ip_name}/${rx_bridge}/ilo_resetdone + if {$asymmetric_mode} { + ad_ip_instance xlconcat ${ip_name}/xlconcat_iloresetdone_tx [list \ + NUM_PORTS ${tx_num_lanes} \ + ] + ad_ip_instance util_reduced_logic ${ip_name}/and_iloresetdone_tx [list \ + C_SIZE ${tx_num_lanes} \ + ] + for {set j 0} {$j < ${tx_num_lanes}} {incr j} { + set quad_index [expr int($j / 4)] + set ch_index [expr $j % 4] + ad_connect ${ip_name}/xlconcat_iloresetdone_tx/In${j} ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_iloresetdone + } + ad_connect ${ip_name}/xlconcat_iloresetdone_tx/dout ${ip_name}/and_iloresetdone_tx/Op1 + ad_connect ${ip_name}/and_iloresetdone_tx/Res ${ip_name}/${tx_bridge}/ilo_resetdone + } + + for {set j 0} {$j < ${num_quads}} {incr j} { + ad_connect ${ip_name}/${rx_bridge}/gt_pll_reset ${ip_name}/gt_quad_base_${j}/hsclk0_lcpllreset + ad_connect ${ip_name}/${rx_bridge}/gt_pll_reset ${ip_name}/gt_quad_base_${j}/hsclk1_lcpllreset + } + + set num_cplllocks [expr 2 * ${num_quads}] + ad_ip_instance xlconcat ${ip_name}/concat_cplllock [list \ + NUM_PORTS ${num_cplllocks} \ + ] + ad_ip_instance util_reduced_logic ${ip_name}/and_cplllock [list \ + C_SIZE ${num_cplllocks} \ + ] + + for {set j 0} {$j < ${num_quads}} {incr j} { + set in_index_0 [expr $j * 2 + 0] + set in_index_1 [expr $j * 2 + 1] + ad_connect ${ip_name}/concat_cplllock/In${in_index_0} ${ip_name}/gt_quad_base_${j}/hsclk0_lcplllock + ad_connect ${ip_name}/concat_cplllock/In${in_index_1} ${ip_name}/gt_quad_base_${j}/hsclk1_lcplllock + } + + ad_connect ${ip_name}/concat_cplllock/dout ${ip_name}/and_cplllock/Op1 + ad_connect ${ip_name}/and_cplllock/Res ${ip_name}/${rx_bridge}/gt_lcpll_lock + if {$asymmetric_mode} { + ad_connect ${ip_name}/and_cplllock/Res ${ip_name}/${tx_bridge}/gt_lcpll_lock + } + + ad_ip_instance xlconcat ${ip_name}/concat_phystatus [list \ + NUM_PORTS ${rx_num_lanes} \ + ] + for {set j 0} {$j < ${rx_num_lanes}} {incr j} { + set quad_index [expr int($j / 4)] + set ch_index [expr $j % 4] + + ad_connect ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_phystatus ${ip_name}/concat_phystatus/In${j} + } + ad_connect ${ip_name}/concat_phystatus/dout ${ip_name}/${rx_bridge}/ch_phystatus_in + if {$asymmetric_mode} { + ad_ip_instance xlconcat ${ip_name}/concat_phystatus_tx [list \ + NUM_PORTS ${rx_num_lanes} \ + ] + for {set j 0} {$j < ${rx_num_lanes}} {incr j} { + set quad_index [expr int($j / 4)] + set ch_index [expr $j % 4] + + ad_connect ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_phystatus ${ip_name}/concat_phystatus_tx/In${j} + } + ad_connect ${ip_name}/concat_phystatus_tx/dout ${ip_name}/${tx_bridge}/ch_phystatus_in + } + + # Outputs + ad_connect ${ip_name}/and_powergood/Res ${ip_name}/gtpowergood + if {$intf_cfg != "TX"} { + ad_connect ${ip_name}/${rx_bridge}/rx_resetdone_out ${ip_name}/rx_resetdone + } + if {$intf_cfg != "RX"} { + ad_connect ${ip_name}/${tx_bridge}/tx_resetdone_out ${ip_name}/tx_resetdone + } +} + +# Parameter description: +# ip_name : The name of the created ip +# jesd_mode : Used physical layer encoder mode +# rx_num_lanes : Number of RX lanes +# tx_num_lanes : Number of TX lanes +# ref_clock : Frequency of reference clock in MHz used in 64B66B mode (LANE_RATE/66) or 8B10B mode (LANE_RATE/40) +# rx_lane_rate : Line rate of the Rx link ( e.g. MxFE to FPGA ) in GHz +# tx_lane_rate : Line rate of the Tx link ( e.g. FPGA to MxFE ) in GHz +# intf_cfg : Direction of the transceivers +# RXTX : Duplex mode +# RX : Rx link only +# TX : Tx link only +proc create_versal_phy { + {ip_name versal_phy} + {jesd_mode 64B66B} + {rx_num_lanes 8} + {tx_num_lanes 8} + {rx_lane_rate 16.22} + {tx_lane_rate 16.22} + {ref_clock 245.76} + {transceiver GTY} + {intf_cfg RXTX} +} { + + set clk_divider [expr { $jesd_mode == "64B66B" ? 66 : 40} ] + set datapath_width [expr { $jesd_mode == "64B66B" ? 64 : 32} ] + set internal_datapath_width [expr { $jesd_mode == "64B66B" ? 64 : 40} ] + set data_encoding [expr { $jesd_mode == "64B66B" ? "64B66B_ASYNC" : "8B10B"} ] + set link_mode [expr { $jesd_mode == "64B66B" ? 2 : 1} ] + set comma_mask [expr { $jesd_mode == "64B66B" ? "0000000000" : "1111111111"} ] + set comma_p_enable [expr { $jesd_mode == "64B66B" ? false : false} ] + set comma_m_enable [expr { $jesd_mode == "64B66B" ? false : false} ] + set num_quads [expr int(ceil(1.0 * max($rx_num_lanes, $tx_num_lanes) / 4))] + set asymmetric_mode [expr { $intf_cfg == "RXTX" && $rx_num_lanes != $tx_num_lanes ? true : false } ] + # When asymmetric_mode is true it means that the number of lanes on the Rx side is different from the number of lanes on the Tx side + # The 'gt_bridge_ip' can only be configured with the same number of lanes so we need to instantiate two ips, one for the Rx and one for the Tx + # Both 'gt_bridge_ip' will still share the same quad + puts "intf_cfg: ${intf_cfg}" + puts "assymmetric_mode: ${asymmetric_mode}" + + set rx_progdiv_clock [format %.3f [expr $rx_lane_rate * 1000 / ${clk_divider}]] + set tx_progdiv_clock [format %.3f [expr $tx_lane_rate * 1000 / ${clk_divider}]] + set preset ${transceiver}-JESD204_64B66B + + if {$intf_cfg == "RX"} { + set gt_direction "SIMPLEX_RX" + set no_lanes_property "CONFIG.IP_NO_OF_RX_LANES" + } elseif {$intf_cfg == "TX"} { + set gt_direction "SIMPLEX_TX" + set no_lanes_property "CONFIG.IP_NO_OF_TX_LANES" + } else { + set gt_direction "DUPLEX" + set no_lanes_property "CONFIG.IP_NO_OF_LANES" + } + + create_bd_cell -type hier ${ip_name} + + # Common interface + create_bd_pin -dir I ${ip_name}/GT_REFCLK -type clk + create_bd_pin -dir I ${ip_name}/s_axi_clk + create_bd_pin -dir I ${ip_name}/s_axi_resetn + if {$intf_cfg != "TX"} { + create_bd_pin -dir O ${ip_name}/rxusrclk_out -type clk + create_bd_pin -dir I ${ip_name}/en_char_align + } + if {$intf_cfg != "RX"} { + create_bd_pin -dir O ${ip_name}/txusrclk_out -type clk + } + + ad_ip_instance gt_bridge_ip ${ip_name}/gt_bridge_ip_0 + set rx_bridge gt_bridge_ip_0 + set tx_bridge gt_bridge_ip_0 + if {$asymmetric_mode} { + ad_ip_instance gt_bridge_ip ${ip_name}/gt_bridge_ip_1 + set tx_bridge gt_bridge_ip_1 + } + if {!$asymmetric_mode} { + set num_lanes [expr max($rx_num_lanes, $tx_num_lanes)] + set_property -dict [list \ + CONFIG.BYPASS_MODE {true} \ + CONFIG.REG_CONF_INTF {AXI_LITE} \ + CONFIG.IP_PRESET ${preset} \ + CONFIG.IP_GT_DIRECTION ${gt_direction} \ + ${no_lanes_property} ${num_lanes} \ + CONFIG.IP_LR0_SETTINGS [list \ + PRESET $preset \ + INTERNAL_PRESET JESD204_${jesd_mode} \ + GT_TYPE $transceiver \ + GT_DIRECTION $gt_direction \ + TX_LINE_RATE $tx_lane_rate \ + TX_PLL_TYPE LCPLL \ + TX_REFCLK_FREQUENCY $ref_clock \ + TX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ + TX_FRACN_ENABLED true \ + TX_FRACN_NUMERATOR 0 \ + TX_REFCLK_SOURCE R0 \ + TX_DATA_ENCODING $data_encoding \ + TX_USER_DATA_WIDTH $datapath_width \ + TX_INT_DATA_WIDTH $internal_datapath_width \ + TX_BUFFER_MODE 1 \ + TX_BUFFER_BYPASS_MODE Fast_Sync \ + TX_PIPM_ENABLE false \ + TX_OUTCLK_SOURCE TXPROGDIVCLK \ + TXPROGDIV_FREQ_ENABLE true \ + TXPROGDIV_FREQ_SOURCE LCPLL \ + TXPROGDIV_FREQ_VAL $tx_progdiv_clock \ + TX_DIFF_SWING_EMPH_MODE CUSTOM \ + TX_64B66B_SCRAMBLER false \ + TX_64B66B_ENCODER false \ + TX_64B66B_CRC false \ + TX_RATE_GROUP A \ + RX_LINE_RATE $rx_lane_rate \ + RX_PLL_TYPE LCPLL \ + RX_REFCLK_FREQUENCY $ref_clock \ + RX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ + RX_FRACN_ENABLED true \ + RX_FRACN_NUMERATOR 0 \ + RX_REFCLK_SOURCE R0 \ + RX_DATA_DECODING $data_encoding \ + RX_USER_DATA_WIDTH $datapath_width \ + RX_INT_DATA_WIDTH $internal_datapath_width \ + RX_BUFFER_MODE 1 \ + RX_OUTCLK_SOURCE RXPROGDIVCLK \ + RXPROGDIV_FREQ_ENABLE true \ + RXPROGDIV_FREQ_SOURCE LCPLL \ + RXPROGDIV_FREQ_VAL $rx_progdiv_clock \ + INS_LOSS_NYQ 12 \ + RX_EQ_MODE LPM \ + RX_COUPLING AC \ + RX_TERMINATION PROGRAMMABLE \ + RX_RATE_GROUP A \ + RX_TERMINATION_PROG_VALUE 800 \ + RX_PPM_OFFSET 0 \ + RX_64B66B_DESCRAMBLER false \ + RX_64B66B_DECODER false \ + RX_64B66B_CRC false \ + OOB_ENABLE false \ + RX_COMMA_ALIGN_WORD 1 \ + RX_COMMA_SHOW_REALIGN_ENABLE false \ + PCIE_ENABLE false \ + RX_COMMA_P_ENABLE $comma_p_enable \ + RX_COMMA_M_ENABLE $comma_m_enable \ + RX_COMMA_DOUBLE_ENABLE false \ + RX_COMMA_P_VAL 0101111100 \ + RX_COMMA_M_VAL 1010000011 \ + RX_COMMA_MASK $comma_mask \ + RX_SLIDE_MODE PCS \ + RX_SSC_PPM 0 \ + RX_CB_NUM_SEQ 0 \ + RX_CB_LEN_SEQ 1 \ + RX_CB_MAX_SKEW 1 \ + RX_CB_MAX_LEVEL 1 \ + RX_CB_MASK_0_0 false \ + RX_CB_VAL_0_0 00000000 \ + RX_CB_K_0_0 false \ + RX_CB_DISP_0_0 false \ + RX_CB_MASK_0_1 false \ + RX_CB_VAL_0_1 00000000 \ + RX_CB_K_0_1 false \ + RX_CB_DISP_0_1 false \ + RX_CB_MASK_0_2 false \ + RX_CB_VAL_0_2 00000000 \ + RX_CB_K_0_2 false \ + RX_CB_DISP_0_2 false \ + RX_CB_MASK_0_3 false \ + RX_CB_VAL_0_3 00000000 \ + RX_CB_K_0_3 false \ + RX_CB_DISP_0_3 false \ + RX_CB_MASK_1_0 false \ + RX_CB_VAL_1_0 00000000 \ + RX_CB_K_1_0 false \ + RX_CB_DISP_1_0 false \ + RX_CB_MASK_1_1 false \ + RX_CB_VAL_1_1 00000000 \ + RX_CB_K_1_1 false \ + RX_CB_DISP_1_1 false \ + RX_CB_MASK_1_2 false \ + RX_CB_VAL_1_2 00000000 \ + RX_CB_K_1_2 false \ + RX_CB_DISP_1_2 false \ + RX_CB_MASK_1_3 false \ + RX_CB_VAL_1_3 00000000 \ + RX_CB_K_1_3 false \ + RX_CB_DISP_1_3 false \ + RX_CC_NUM_SEQ 0 \ + RX_CC_LEN_SEQ 1 \ + RX_CC_PERIODICITY 5000 \ + RX_CC_KEEP_IDLE DISABLE \ + RX_CC_PRECEDENCE ENABLE \ + RX_CC_REPEAT_WAIT 0 \ + RX_CC_VAL 00000000000000000000000000000000000000000000000000000000000000000000000000000000 \ + RX_CC_MASK_0_0 false \ + RX_CC_VAL_0_0 00000000 \ + RX_CC_K_0_0 false \ + RX_CC_DISP_0_0 false \ + RX_CC_MASK_0_1 false \ + RX_CC_VAL_0_1 00000000 \ + RX_CC_K_0_1 false \ + RX_CC_DISP_0_1 false \ + RX_CC_MASK_0_2 false \ + RX_CC_VAL_0_2 00000000 \ + RX_CC_K_0_2 false \ + RX_CC_DISP_0_2 false \ + RX_CC_MASK_0_3 false \ + RX_CC_VAL_0_3 00000000 \ + RX_CC_K_0_3 false \ + RX_CC_DISP_0_3 false \ + RX_CC_MASK_1_0 false \ + RX_CC_VAL_1_0 00000000 \ + RX_CC_K_1_0 false \ + RX_CC_DISP_1_0 false \ + RX_CC_MASK_1_1 false \ + RX_CC_VAL_1_1 00000000 \ + RX_CC_K_1_1 false \ + RX_CC_DISP_1_1 false \ + RX_CC_MASK_1_2 false \ + RX_CC_VAL_1_2 00000000 \ + RX_CC_K_1_2 false \ + RX_CC_DISP_1_2 false \ + RX_CC_MASK_1_3 false \ + RX_CC_VAL_1_3 00000000 \ + RX_CC_K_1_3 false \ + RX_CC_DISP_1_3 false \ + PCIE_USERCLK2_FREQ 250 \ + PCIE_USERCLK_FREQ 250 \ + RX_JTOL_FC 10 \ + RX_JTOL_LF_SLOPE -20 \ + RX_BUFFER_BYPASS_MODE Fast_Sync \ + RX_BUFFER_BYPASS_MODE_LANE MULTI \ + RX_BUFFER_RESET_ON_CB_CHANGE ENABLE \ + RX_BUFFER_RESET_ON_COMMAALIGN DISABLE \ + RX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ + TX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ + RESET_SEQUENCE_INTERVAL 0 \ + RX_COMMA_PRESET NONE \ + RX_COMMA_VALID_ONLY 0 \ + ] \ + ] [get_bd_cells ${ip_name}/${rx_bridge}] + } else { + set_property -dict [list \ + CONFIG.BYPASS_MODE {true} \ + CONFIG.REG_CONF_INTF {AXI_LITE} \ + CONFIG.IP_PRESET ${preset} \ + CONFIG.IP_GT_DIRECTION {SIMPLEX_RX} \ + CONFIG.IP_NO_OF_RX_LANES ${rx_num_lanes} \ + CONFIG.IP_LR0_SETTINGS [list \ + PRESET $preset \ + INTERNAL_PRESET JESD204_${jesd_mode} \ + GT_TYPE $transceiver \ + GT_DIRECTION SIMPLEX_RX \ + TX_LINE_RATE $tx_lane_rate \ + TX_PLL_TYPE LCPLL \ + TX_REFCLK_FREQUENCY $ref_clock \ + TX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ + TX_FRACN_ENABLED true \ + TX_FRACN_NUMERATOR 0 \ + TX_REFCLK_SOURCE R0 \ + TX_DATA_ENCODING $data_encoding \ + TX_USER_DATA_WIDTH $datapath_width \ + TX_INT_DATA_WIDTH $internal_datapath_width \ + TX_BUFFER_MODE 1 \ + TX_BUFFER_BYPASS_MODE Fast_Sync \ + TX_PIPM_ENABLE false \ + TX_OUTCLK_SOURCE TXPROGDIVCLK \ + TXPROGDIV_FREQ_ENABLE true \ + TXPROGDIV_FREQ_SOURCE LCPLL \ + TXPROGDIV_FREQ_VAL $tx_progdiv_clock \ + TX_DIFF_SWING_EMPH_MODE CUSTOM \ + TX_64B66B_SCRAMBLER false \ + TX_64B66B_ENCODER false \ + TX_64B66B_CRC false \ + TX_RATE_GROUP A \ + RX_LINE_RATE $rx_lane_rate \ + RX_PLL_TYPE LCPLL \ + RX_REFCLK_FREQUENCY $ref_clock \ + RX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ + RX_FRACN_ENABLED true \ + RX_FRACN_NUMERATOR 0 \ + RX_REFCLK_SOURCE R0 \ + RX_DATA_DECODING $data_encoding \ + RX_USER_DATA_WIDTH $datapath_width \ + RX_INT_DATA_WIDTH $internal_datapath_width \ + RX_BUFFER_MODE 1 \ + RX_OUTCLK_SOURCE RXPROGDIVCLK \ + RXPROGDIV_FREQ_ENABLE true \ + RXPROGDIV_FREQ_SOURCE LCPLL \ + RXPROGDIV_FREQ_VAL $rx_progdiv_clock \ + INS_LOSS_NYQ 12 \ + RX_EQ_MODE LPM \ + RX_COUPLING AC \ + RX_TERMINATION PROGRAMMABLE \ + RX_RATE_GROUP A \ + RX_TERMINATION_PROG_VALUE 800 \ + RX_PPM_OFFSET 0 \ + RX_64B66B_DESCRAMBLER false \ + RX_64B66B_DECODER false \ + RX_64B66B_CRC false \ + OOB_ENABLE false \ + RX_COMMA_ALIGN_WORD 1 \ + RX_COMMA_SHOW_REALIGN_ENABLE false \ + PCIE_ENABLE false \ + RX_COMMA_P_ENABLE $comma_p_enable \ + RX_COMMA_M_ENABLE $comma_m_enable \ + RX_COMMA_DOUBLE_ENABLE false \ + RX_COMMA_P_VAL 0101111100 \ + RX_COMMA_M_VAL 1010000011 \ + RX_COMMA_MASK $comma_mask \ + RX_SLIDE_MODE PCS \ + RX_SSC_PPM 0 \ + RX_CB_NUM_SEQ 0 \ + RX_CB_LEN_SEQ 1 \ + RX_CB_MAX_SKEW 1 \ + RX_CB_MAX_LEVEL 1 \ + RX_CB_MASK_0_0 false \ + RX_CB_VAL_0_0 00000000 \ + RX_CB_K_0_0 false \ + RX_CB_DISP_0_0 false \ + RX_CB_MASK_0_1 false \ + RX_CB_VAL_0_1 00000000 \ + RX_CB_K_0_1 false \ + RX_CB_DISP_0_1 false \ + RX_CB_MASK_0_2 false \ + RX_CB_VAL_0_2 00000000 \ + RX_CB_K_0_2 false \ + RX_CB_DISP_0_2 false \ + RX_CB_MASK_0_3 false \ + RX_CB_VAL_0_3 00000000 \ + RX_CB_K_0_3 false \ + RX_CB_DISP_0_3 false \ + RX_CB_MASK_1_0 false \ + RX_CB_VAL_1_0 00000000 \ + RX_CB_K_1_0 false \ + RX_CB_DISP_1_0 false \ + RX_CB_MASK_1_1 false \ + RX_CB_VAL_1_1 00000000 \ + RX_CB_K_1_1 false \ + RX_CB_DISP_1_1 false \ + RX_CB_MASK_1_2 false \ + RX_CB_VAL_1_2 00000000 \ + RX_CB_K_1_2 false \ + RX_CB_DISP_1_2 false \ + RX_CB_MASK_1_3 false \ + RX_CB_VAL_1_3 00000000 \ + RX_CB_K_1_3 false \ + RX_CB_DISP_1_3 false \ + RX_CC_NUM_SEQ 0 \ + RX_CC_LEN_SEQ 1 \ + RX_CC_PERIODICITY 5000 \ + RX_CC_KEEP_IDLE DISABLE \ + RX_CC_PRECEDENCE ENABLE \ + RX_CC_REPEAT_WAIT 0 \ + RX_CC_VAL 00000000000000000000000000000000000000000000000000000000000000000000000000000000 \ + RX_CC_MASK_0_0 false \ + RX_CC_VAL_0_0 00000000 \ + RX_CC_K_0_0 false \ + RX_CC_DISP_0_0 false \ + RX_CC_MASK_0_1 false \ + RX_CC_VAL_0_1 00000000 \ + RX_CC_K_0_1 false \ + RX_CC_DISP_0_1 false \ + RX_CC_MASK_0_2 false \ + RX_CC_VAL_0_2 00000000 \ + RX_CC_K_0_2 false \ + RX_CC_DISP_0_2 false \ + RX_CC_MASK_0_3 false \ + RX_CC_VAL_0_3 00000000 \ + RX_CC_K_0_3 false \ + RX_CC_DISP_0_3 false \ + RX_CC_MASK_1_0 false \ + RX_CC_VAL_1_0 00000000 \ + RX_CC_K_1_0 false \ + RX_CC_DISP_1_0 false \ + RX_CC_MASK_1_1 false \ + RX_CC_VAL_1_1 00000000 \ + RX_CC_K_1_1 false \ + RX_CC_DISP_1_1 false \ + RX_CC_MASK_1_2 false \ + RX_CC_VAL_1_2 00000000 \ + RX_CC_K_1_2 false \ + RX_CC_DISP_1_2 false \ + RX_CC_MASK_1_3 false \ + RX_CC_VAL_1_3 00000000 \ + RX_CC_K_1_3 false \ + RX_CC_DISP_1_3 false \ + PCIE_USERCLK2_FREQ 250 \ + PCIE_USERCLK_FREQ 250 \ + RX_JTOL_FC 10 \ + RX_JTOL_LF_SLOPE -20 \ + RX_BUFFER_BYPASS_MODE Fast_Sync \ + RX_BUFFER_BYPASS_MODE_LANE MULTI \ + RX_BUFFER_RESET_ON_CB_CHANGE ENABLE \ + RX_BUFFER_RESET_ON_COMMAALIGN DISABLE \ + RX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ + TX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ + RESET_SEQUENCE_INTERVAL 0 \ + RX_COMMA_PRESET NONE \ + RX_COMMA_VALID_ONLY 0 \ + ] \ + ] [get_bd_cells ${ip_name}/${rx_bridge}] + + set_property -dict [list \ + CONFIG.BYPASS_MODE {true} \ + CONFIG.REG_CONF_INTF {AXI_LITE} \ + CONFIG.IP_PRESET ${preset} \ + CONFIG.IP_GT_DIRECTION {SIMPLEX_TX} \ + CONFIG.IP_NO_OF_TX_LANES ${tx_num_lanes} \ + CONFIG.IP_LR0_SETTINGS [list \ + PRESET $preset \ + INTERNAL_PRESET JESD204_${jesd_mode} \ + GT_TYPE $transceiver \ + GT_DIRECTION SIMPLEX_TX \ + TX_LINE_RATE $tx_lane_rate \ + TX_PLL_TYPE LCPLL \ + TX_REFCLK_FREQUENCY $ref_clock \ + TX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ + TX_FRACN_ENABLED true \ + TX_FRACN_NUMERATOR 0 \ + TX_REFCLK_SOURCE R0 \ + TX_DATA_ENCODING $data_encoding \ + TX_USER_DATA_WIDTH $datapath_width \ + TX_INT_DATA_WIDTH $internal_datapath_width \ + TX_BUFFER_MODE 1 \ + TX_BUFFER_BYPASS_MODE Fast_Sync \ + TX_PIPM_ENABLE false \ + TX_OUTCLK_SOURCE TXPROGDIVCLK \ + TXPROGDIV_FREQ_ENABLE true \ + TXPROGDIV_FREQ_SOURCE LCPLL \ + TXPROGDIV_FREQ_VAL $tx_progdiv_clock \ + TX_DIFF_SWING_EMPH_MODE CUSTOM \ + TX_64B66B_SCRAMBLER false \ + TX_64B66B_ENCODER false \ + TX_64B66B_CRC false \ + TX_RATE_GROUP A \ + RX_LINE_RATE $rx_lane_rate \ + RX_PLL_TYPE LCPLL \ + RX_REFCLK_FREQUENCY $ref_clock \ + RX_ACTUAL_REFCLK_FREQUENCY $ref_clock \ + RX_FRACN_ENABLED true \ + RX_FRACN_NUMERATOR 0 \ + RX_REFCLK_SOURCE R0 \ + RX_DATA_DECODING $data_encoding \ + RX_USER_DATA_WIDTH $datapath_width \ + RX_INT_DATA_WIDTH $internal_datapath_width \ + RX_BUFFER_MODE 1 \ + RX_OUTCLK_SOURCE RXPROGDIVCLK \ + RXPROGDIV_FREQ_ENABLE true \ + RXPROGDIV_FREQ_SOURCE LCPLL \ + RXPROGDIV_FREQ_VAL $rx_progdiv_clock \ + INS_LOSS_NYQ 12 \ + RX_EQ_MODE LPM \ + RX_COUPLING AC \ + RX_TERMINATION PROGRAMMABLE \ + RX_RATE_GROUP A \ + RX_TERMINATION_PROG_VALUE 800 \ + RX_PPM_OFFSET 0 \ + RX_64B66B_DESCRAMBLER false \ + RX_64B66B_DECODER false \ + RX_64B66B_CRC false \ + OOB_ENABLE false \ + RX_COMMA_ALIGN_WORD 1 \ + RX_COMMA_SHOW_REALIGN_ENABLE false \ + PCIE_ENABLE false \ + RX_COMMA_P_ENABLE $comma_p_enable \ + RX_COMMA_M_ENABLE $comma_m_enable \ + RX_COMMA_DOUBLE_ENABLE false \ + RX_COMMA_P_VAL 0101111100 \ + RX_COMMA_M_VAL 1010000011 \ + RX_COMMA_MASK $comma_mask \ + RX_SLIDE_MODE PCS \ + RX_SSC_PPM 0 \ + RX_CB_NUM_SEQ 0 \ + RX_CB_LEN_SEQ 1 \ + RX_CB_MAX_SKEW 1 \ + RX_CB_MAX_LEVEL 1 \ + RX_CB_MASK_0_0 false \ + RX_CB_VAL_0_0 00000000 \ + RX_CB_K_0_0 false \ + RX_CB_DISP_0_0 false \ + RX_CB_MASK_0_1 false \ + RX_CB_VAL_0_1 00000000 \ + RX_CB_K_0_1 false \ + RX_CB_DISP_0_1 false \ + RX_CB_MASK_0_2 false \ + RX_CB_VAL_0_2 00000000 \ + RX_CB_K_0_2 false \ + RX_CB_DISP_0_2 false \ + RX_CB_MASK_0_3 false \ + RX_CB_VAL_0_3 00000000 \ + RX_CB_K_0_3 false \ + RX_CB_DISP_0_3 false \ + RX_CB_MASK_1_0 false \ + RX_CB_VAL_1_0 00000000 \ + RX_CB_K_1_0 false \ + RX_CB_DISP_1_0 false \ + RX_CB_MASK_1_1 false \ + RX_CB_VAL_1_1 00000000 \ + RX_CB_K_1_1 false \ + RX_CB_DISP_1_1 false \ + RX_CB_MASK_1_2 false \ + RX_CB_VAL_1_2 00000000 \ + RX_CB_K_1_2 false \ + RX_CB_DISP_1_2 false \ + RX_CB_MASK_1_3 false \ + RX_CB_VAL_1_3 00000000 \ + RX_CB_K_1_3 false \ + RX_CB_DISP_1_3 false \ + RX_CC_NUM_SEQ 0 \ + RX_CC_LEN_SEQ 1 \ + RX_CC_PERIODICITY 5000 \ + RX_CC_KEEP_IDLE DISABLE \ + RX_CC_PRECEDENCE ENABLE \ + RX_CC_REPEAT_WAIT 0 \ + RX_CC_VAL 00000000000000000000000000000000000000000000000000000000000000000000000000000000 \ + RX_CC_MASK_0_0 false \ + RX_CC_VAL_0_0 00000000 \ + RX_CC_K_0_0 false \ + RX_CC_DISP_0_0 false \ + RX_CC_MASK_0_1 false \ + RX_CC_VAL_0_1 00000000 \ + RX_CC_K_0_1 false \ + RX_CC_DISP_0_1 false \ + RX_CC_MASK_0_2 false \ + RX_CC_VAL_0_2 00000000 \ + RX_CC_K_0_2 false \ + RX_CC_DISP_0_2 false \ + RX_CC_MASK_0_3 false \ + RX_CC_VAL_0_3 00000000 \ + RX_CC_K_0_3 false \ + RX_CC_DISP_0_3 false \ + RX_CC_MASK_1_0 false \ + RX_CC_VAL_1_0 00000000 \ + RX_CC_K_1_0 false \ + RX_CC_DISP_1_0 false \ + RX_CC_MASK_1_1 false \ + RX_CC_VAL_1_1 00000000 \ + RX_CC_K_1_1 false \ + RX_CC_DISP_1_1 false \ + RX_CC_MASK_1_2 false \ + RX_CC_VAL_1_2 00000000 \ + RX_CC_K_1_2 false \ + RX_CC_DISP_1_2 false \ + RX_CC_MASK_1_3 false \ + RX_CC_VAL_1_3 00000000 \ + RX_CC_K_1_3 false \ + RX_CC_DISP_1_3 false \ + PCIE_USERCLK2_FREQ 250 \ + PCIE_USERCLK_FREQ 250 \ + RX_JTOL_FC 10 \ + RX_JTOL_LF_SLOPE -20 \ + RX_BUFFER_BYPASS_MODE Fast_Sync \ + RX_BUFFER_BYPASS_MODE_LANE MULTI \ + RX_BUFFER_RESET_ON_CB_CHANGE ENABLE \ + RX_BUFFER_RESET_ON_COMMAALIGN DISABLE \ + RX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ + TX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ + RESET_SEQUENCE_INTERVAL 0 \ + RX_COMMA_PRESET NONE \ + RX_COMMA_VALID_ONLY 0 \ + ] \ + ] [get_bd_cells ${ip_name}/${tx_bridge}] + } + set quad_num_rx_lane $rx_num_lanes + set quad_num_tx_lane $tx_num_lanes + for {set j 0} {$j < $num_quads} {incr j} { + set rx_num [expr min($quad_num_rx_lane, 4)] + set tx_num [expr min($quad_num_tx_lane, 4)] + ad_ip_instance gt_quad_base ${ip_name}/gt_quad_base_${j} + set_property -dict [list \ + CONFIG.REG_CONF_INTF.VALUE_MODE {MANUAL} \ + CONFIG.REG_CONF_INTF {AXI_LITE} \ + CONFIG.PROT0_GT_DIRECTION ${gt_direction} \ + ] [get_bd_cells ${ip_name}/gt_quad_base_${j}] + if {$asymmetric_mode} { + # When we have multiple protocols (different number of lanes on Rx and Tx) we have to manually set the protocols to pass design validation + set_property -dict [list \ + CONFIG.GT_TYPE.VALUE_MODE AUTO \ + CONFIG.PROT0_RX_MASTERCLK_SRC.VALUE_MODE RX0 \ + CONFIG.PROT1_TX_MASTERCLK_SRC.VALUE_MODE TX0 \ + CONFIG.PROT1_ENABLE.VALUE_MODE MANUAL \ + CONFIG.PROT0_GT_DIRECTION.VALUE_MODE MANUAL \ + CONFIG.TX0_LANE_SEL.VALUE_MODE AUTO \ + CONFIG.PROT0_NO_OF_RX_LANES.VALUE_MODE MANUAL \ + CONFIG.PROT1_NO_OF_TX_LANES.VALUE_MODE MANUAL \ + CONFIG.PROT1_GT_DIRECTION.VALUE_MODE MANUAL \ + ] [get_bd_cells ${ip_name}/gt_quad_base_${j}] + + if {$rx_num > 0} { + set_property -dict [list \ + CONFIG.PROT0_GT_DIRECTION {SIMPLEX_RX} \ + CONFIG.PROT0_NO_OF_RX_LANES $rx_num \ + ] [get_bd_cells ${ip_name}/gt_quad_base_${j}] + for {set i 0} {$i < $rx_num} {incr i} { + set_property -dict [list \ + CONFIG.RX${i}_LANE_SEL.VALUE_MODE MANUAL \ + ] [get_bd_cells ${ip_name}/gt_quad_base_${j}] + } + } + if {$tx_num > 0} { + set_property -dict [list \ + CONFIG.PROT1_ENABLE {true} \ + CONFIG.PROT1_GT_DIRECTION {SIMPLEX_TX} \ + CONFIG.PROT1_NO_OF_TX_LANES $tx_num \ + ] [get_bd_cells ${ip_name}/gt_quad_base_${j}] + for {set i 0} {$i < $tx_num} {incr i} { + set_property -dict [list \ + CONFIG.TX${i}_LANE_SEL.VALUE_MODE MANUAL \ + ] [get_bd_cells ${ip_name}/gt_quad_base_${j}] + } + } + + set quad_num_rx_lane [expr $quad_num_rx_lane - $rx_num] + set quad_num_tx_lane [expr $quad_num_tx_lane - $tx_num] + } + + if {$intf_cfg != "TX"} { + # Share the link clock generated by the first quad + if {$j == 0} { + ad_ip_instance bufg_gt ${ip_name}/bufg_gt_rx + ad_connect ${ip_name}/gt_quad_base_0/ch0_rxoutclk ${ip_name}/bufg_gt_rx/outclk + ad_connect ${ip_name}/${rx_bridge}/rx_clr_out ${ip_name}/bufg_gt_rx/gt_bufgtclr + ad_connect ${ip_name}/${rx_bridge}/rxusrclk_out ${ip_name}/rxusrclk_out + ad_connect ${ip_name}/bufg_gt_rx/usrclk ${ip_name}/${rx_bridge}/gt_rxusrclk + } + create_bd_pin -dir I -from 3 -to 0 ${ip_name}/rx_${j}_p + create_bd_pin -dir I -from 3 -to 0 ${ip_name}/rx_${j}_n + ad_connect ${ip_name}/gt_quad_base_${j}/rxp ${ip_name}/rx_${j}_p + ad_connect ${ip_name}/gt_quad_base_${j}/rxn ${ip_name}/rx_${j}_n + } + if {$intf_cfg != "RX"} { + # Share the link clock generated by the first quad + if {$j == 0} { + ad_ip_instance bufg_gt ${ip_name}/bufg_gt_tx + ad_connect ${ip_name}/gt_quad_base_0/ch0_txoutclk ${ip_name}/bufg_gt_tx/outclk + ad_connect ${ip_name}/${tx_bridge}/tx_clr_out ${ip_name}/bufg_gt_tx/gt_bufgtclr + ad_connect ${ip_name}/${tx_bridge}/txusrclk_out ${ip_name}/txusrclk_out + ad_connect ${ip_name}/bufg_gt_tx/usrclk ${ip_name}/${tx_bridge}/gt_txusrclk + } + create_bd_pin -dir O -from 3 -to 0 ${ip_name}/tx_${j}_p + create_bd_pin -dir O -from 3 -to 0 ${ip_name}/tx_${j}_n + ad_connect ${ip_name}/gt_quad_base_${j}/txp ${ip_name}/tx_${j}_p + ad_connect ${ip_name}/gt_quad_base_${j}/txn ${ip_name}/tx_${j}_n + } + } + + if {$intf_cfg != "TX"} { + for {set j 0} {$j < $rx_num_lanes} {incr j} { + set quad_index [expr int($j / 4)] + set rx_index [expr $j % 4] + + ad_connect ${ip_name}/bufg_gt_rx/usrclk ${ip_name}/gt_quad_base_${quad_index}/ch${rx_index}_rxusrclk + + ad_ip_instance jesd204_versal_gt_adapter_rx ${ip_name}/rx_adapt_${j} [list \ + LINK_MODE $link_mode \ + ] + ad_connect ${ip_name}/rx_adapt_${j}/RX_GT_IP_Interface ${ip_name}/${rx_bridge}/GT_RX${j}_EXT + ad_connect ${ip_name}/${rx_bridge}/GT_RX${j} ${ip_name}/gt_quad_base_${quad_index}/RX${rx_index}_GT_IP_Interface + + create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 ${ip_name}/rx${j} + ad_connect ${ip_name}/rx${j} ${ip_name}/rx_adapt_${j}/RX + ad_connect ${ip_name}/rx_adapt_${j}/usr_clk ${ip_name}/bufg_gt_rx/usrclk + ad_connect ${ip_name}/rx_adapt_${j}/en_char_align ${ip_name}/en_char_align + + if {$asymmetric_mode} { + set_property CONFIG.RX${rx_index}_LANE_SEL {PROT0} [get_bd_cells ${ip_name}/gt_quad_base_${quad_index}] + } + } + } + if {$intf_cfg != "RX"} { + for {set j 0} {$j < $tx_num_lanes} {incr j} { + set quad_index [expr int($j / 4)] + set tx_index [expr $j % 4] + + ad_connect ${ip_name}/bufg_gt_tx/usrclk ${ip_name}/gt_quad_base_${quad_index}/ch${tx_index}_txusrclk + + ad_ip_instance jesd204_versal_gt_adapter_tx ${ip_name}/tx_adapt_${j} [list \ + LINK_MODE $link_mode \ + ] + ad_connect ${ip_name}/tx_adapt_${j}/TX_GT_IP_Interface ${ip_name}/${tx_bridge}/GT_TX${j}_EXT + ad_connect ${ip_name}/${tx_bridge}/GT_TX${j} ${ip_name}/gt_quad_base_${quad_index}/TX${tx_index}_GT_IP_Interface + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 ${ip_name}/tx${j} + ad_connect ${ip_name}/tx${j} ${ip_name}/tx_adapt_${j}/TX + ad_connect ${ip_name}/tx_adapt_${j}/usr_clk ${ip_name}/bufg_gt_tx/usrclk + + if {$asymmetric_mode} { + set_property CONFIG.TX${tx_index}_LANE_SEL {PROT1} [get_bd_cells ${ip_name}/gt_quad_base_${quad_index}] + } + } + } + + if {$asymmetric_mode} { + # Map unused quad lanes as unconnected + set max_num_of_lanes [expr $num_quads * 4] + for {set j $rx_num_lanes} {$intf_cfg != "TX" && $j < $max_num_of_lanes} {incr j} { + set quad_index [expr $j / 4] + set lane_index [expr $j % 4] + set_property CONFIG.RX${lane_index}_LANE_SEL {unconnected} [get_bd_cells ${ip_name}/gt_quad_base_${quad_index}] + } + for {set j $tx_num_lanes} {$intf_cfg != "RX" && $j < $max_num_of_lanes} {incr j} { + set quad_index [expr $j / 4] + set lane_index [expr $j % 4] + set_property CONFIG.TX${lane_index}_LANE_SEL {unconnected} [get_bd_cells ${ip_name}/gt_quad_base_${quad_index}] + } + } + + # Clocks + ad_connect ${ip_name}/s_axi_clk ${ip_name}/${rx_bridge}/apb3clk + if {$asymmetric_mode} { + ad_connect ${ip_name}/s_axi_clk ${ip_name}/${tx_bridge}/apb3clk + } + for {set j 0} {$j < $num_quads} {incr j} { + ad_connect ${ip_name}/GT_REFCLK ${ip_name}/gt_quad_base_${j}/GT_REFCLK0 + ad_connect ${ip_name}/s_axi_clk ${ip_name}/gt_quad_base_${j}/s_axi_lite_clk + ad_connect ${ip_name}/s_axi_resetn ${ip_name}/gt_quad_base_${j}/s_axi_lite_resetn + } + + # Instantiate reset helper logic + create_reset_logic $ip_name $rx_num_lanes $tx_num_lanes $intf_cfg +} diff --git a/projects/adrv904x/vck190/Makefile b/projects/adrv904x/vck190/Makefile new file mode 100644 index 0000000000..dd1de164f1 --- /dev/null +++ b/projects/adrv904x/vck190/Makefile @@ -0,0 +1,41 @@ +#################################################################################### +## Copyright (c) 2018 - 2024 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := adrv904x_vck190 + +M_DEPS += ../common/versal_transceiver.tcl +M_DEPS += ../common/adrv904x_bd.tcl +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/vck190/vck190_system_constr.xdc +M_DEPS += ../../common/vck190/vck190_system_bd.tcl +M_DEPS += ../../common/xilinx/data_offload_bd.tcl +M_DEPS += ../../common/xilinx/adi_fir_filter_constr.xdc +M_DEPS += ../../common/xilinx/adi_fir_filter_bd.tcl +M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl +M_DEPS += ../../../library/util_cdc/sync_bits.v +M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl +M_DEPS += ../../../library/common/util_pulse_gen.v +M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/common/ad_bus_mux.v + +LIB_DEPS += axi_dmac +LIB_DEPS += axi_sysid +LIB_DEPS += data_offload +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac +LIB_DEPS += jesd204/axi_jesd204_rx +LIB_DEPS += jesd204/axi_jesd204_tx +LIB_DEPS += jesd204/jesd204_rx +LIB_DEPS += jesd204/jesd204_tx +LIB_DEPS += jesd204/jesd204_versal_gt_adapter_rx +LIB_DEPS += jesd204/jesd204_versal_gt_adapter_tx +LIB_DEPS += sysid_rom +LIB_DEPS += util_do_ram +LIB_DEPS += util_hbm +LIB_DEPS += util_pack/util_cpack2 +LIB_DEPS += util_pack/util_upack2 + +include ../../scripts/project-xilinx.mk diff --git a/projects/adrv904x/vck190/system_bd.tcl b/projects/adrv904x/vck190/system_bd.tcl new file mode 100644 index 0000000000..ac91e4d593 --- /dev/null +++ b/projects/adrv904x/vck190/system_bd.tcl @@ -0,0 +1,53 @@ +############################################################################### +## Copyright (C) 2024 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +## ADC FIFO depth in samples per converter +set adc_fifo_samples_per_converter [expr 32*1024] +## DAC FIFO depth in samples per converter +set dac_fifo_samples_per_converter [expr 32*1024] + +set ADI_PHY_SEL 0 + +adi_project_files adrv904x_vck190 [list \ + "$ad_hdl_dir/library/util_cdc/sync_bits.v" ] + +source $ad_hdl_dir/projects/common/vck190/vck190_system_bd.tcl +source $ad_hdl_dir/projects/scripts/adi_pd.tcl +source ../common/adrv904x_bd.tcl + +#lane polarity + +ad_connect VCC ${rx_phy}/gt_bridge_ip_0/ch0_txpolarity_ext +ad_connect VCC ${rx_phy}/gt_bridge_ip_0/ch1_txpolarity_ext +ad_connect VCC ${rx_phy}/gt_bridge_ip_0/ch2_txpolarity_ext +ad_connect VCC ${rx_phy}/gt_bridge_ip_0/ch3_txpolarity_ext +ad_connect VCC ${rx_phy}/gt_bridge_ip_0/ch0_rxpolarity_ext +ad_connect VCC ${rx_phy}/gt_bridge_ip_0/ch1_rxpolarity_ext +ad_connect VCC ${rx_phy}/gt_bridge_ip_0/ch2_rxpolarity_ext +ad_connect VCC ${rx_phy}/gt_bridge_ip_0/ch3_rxpolarity_ext +ad_connect VCC ${rx_phy}/gt_bridge_ip_0/ch4_rxpolarity_ext +ad_connect VCC ${rx_phy}/gt_bridge_ip_0/ch5_rxpolarity_ext +ad_connect VCC ${rx_phy}/gt_bridge_ip_0/ch6_rxpolarity_ext +ad_connect VCC ${rx_phy}/gt_bridge_ip_0/ch7_rxpolarity_ext + +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 10 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_sys.txt" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 10 + +set sys_cstring "$ad_project_params(JESD_MODE)\ +RX:RATE=$ad_project_params(RX_LANE_RATE)\ +M=$ad_project_params(RX_JESD_M)\ +L=$ad_project_params(RX_JESD_L)\ +S=$ad_project_params(RX_JESD_S)\ +NP=$ad_project_params(RX_JESD_NP)\ +LINKS=$ad_project_params(RX_NUM_LINKS)\ +TX:RATE=$ad_project_params(TX_LANE_RATE)\ +M=$ad_project_params(TX_JESD_M)\ +L=$ad_project_params(TX_JESD_L)\ +S=$ad_project_params(TX_JESD_S)\ +NP=$ad_project_params(TX_JESD_NP)\ +LINKS=$ad_project_params(TX_NUM_LINKS)" + +sysid_gen_sys_init_file $sys_cstring 10 diff --git a/projects/adrv904x/vck190/system_constr.xdc b/projects/adrv904x/vck190/system_constr.xdc new file mode 100644 index 0000000000..50886f8757 --- /dev/null +++ b/projects/adrv904x/vck190/system_constr.xdc @@ -0,0 +1,117 @@ +############################################################################### +## Copyright (C) 2024 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +#adrv904x + +set_property -dict {PACKAGE_PIN M15} [get_ports ref_clk0_p] ; ## D4 FMC1_GBTCLK0_M2C_C_P GTY_REFCLKP1_201 +set_property -dict {PACKAGE_PIN M14} [get_ports ref_clk0_n] ; ## D5 FMC1_GBTCLK0_M2C_C_N GTY_REFCLKN1_201 +set_property -dict {PACKAGE_PIN K15} [get_ports ref_clk1_p] ; ## B20 FMC1_GBTCLK1_M2C_C_P GTY_REFCLKP1_202 +set_property -dict {PACKAGE_PIN K14} [get_ports ref_clk1_n] ; ## B21 FMC1_GBTCLK1_M2C_C_N GTY_REFCLKN1_202 + +set_property -dict {PACKAGE_PIN AV23 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100} [get_ports core_clk_p] ; ## H4 FMC1_CLK0_M2C_P IO_L12P_GC_XCC_N4P0_M2P24_706 +set_property -dict {PACKAGE_PIN AW23 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100} [get_ports core_clk_n] ; ## H5 FMC1_CLK0_M2C_N IO_L12N_GC_XCC_N4P1_M2P25_706 + +set_property -dict {PACKAGE_PIN AB2} [get_ports rx_data_p[0]] ; ## C6 FMC1_DP0_M2C_P GTY_RXP0_201 +set_property -dict {PACKAGE_PIN AB1} [get_ports rx_data_n[0]] ; ## C7 FMC1_DP0_M2C_N GTY_RXN0_201 +set_property -dict {PACKAGE_PIN AA4} [get_ports rx_data_p[1]] ; ## A2 FMC1_DP1_M2C_P GTY_RXP1_201 +set_property -dict {PACKAGE_PIN AA3} [get_ports rx_data_n[1]] ; ## A3 FMC1_DP1_M2C_N GTY_RXN1_201 +set_property -dict {PACKAGE_PIN Y2} [get_ports rx_data_p[2]] ; ## A6 FMC1_DP2_M2C_P GTY_RXP2_201 +set_property -dict {PACKAGE_PIN Y1} [get_ports rx_data_n[2]] ; ## A7 FMC1_DP2_M2C_N GTY_RXN2_201 +set_property -dict {PACKAGE_PIN W4} [get_ports rx_data_p[3]] ; ## A10 FMC1_DP3_M2C_P GTY_RXP3_201 +set_property -dict {PACKAGE_PIN W3} [get_ports rx_data_n[3]] ; ## A11 FMC1_DP3_M2C_N GTY_RXN3_201 +set_property -dict {PACKAGE_PIN V2} [get_ports rx_data_p[4]] ; ## A14 FMC1_DP4_M2C_P GTY_RXP0_202 +set_property -dict {PACKAGE_PIN V1} [get_ports rx_data_n[4]] ; ## A15 FMC1_DP4_M2C_N GTY_RXN0_202 +set_property -dict {PACKAGE_PIN U4} [get_ports rx_data_p[5]] ; ## A18 FMC1_DP5_M2C_P GTY_RXP1_202 +set_property -dict {PACKAGE_PIN U3} [get_ports rx_data_n[5]] ; ## A19 FMC1_DP5_M2C_N GTY_RXN1_202 +set_property -dict {PACKAGE_PIN T2} [get_ports rx_data_p[6]] ; ## B16 FMC1_DP6_M2C_P GTY_RXP2_202 +set_property -dict {PACKAGE_PIN T1} [get_ports rx_data_n[6]] ; ## B17 FMC1_DP6_M2C_N GTY_RXN2_202 +set_property -dict {PACKAGE_PIN R4} [get_ports rx_data_p[7]] ; ## B12 FMC1_DP7_M2C_P GTY_RXP3_202 +set_property -dict {PACKAGE_PIN R3} [get_ports rx_data_n[7]] ; ## B13 FMC1_DP7_M2C_N GTY_RXN3_202 + +set_property -dict {PACKAGE_PIN AB7} [get_ports tx_data_p[0]] ; ## C2 FMC1_DP0_C2M_P GTY_TXP0_201 +set_property -dict {PACKAGE_PIN AB6} [get_ports tx_data_n[0]] ; ## C3 FMC1_DP0_C2M_N GTY_TXN0_201 +set_property -dict {PACKAGE_PIN AA9} [get_ports tx_data_p[1]] ; ## A22 FMC1_DP1_C2M_P GTY_TXP1_201 +set_property -dict {PACKAGE_PIN AA8} [get_ports tx_data_n[1]] ; ## A23 FMC1_DP1_C2M_N GTY_TXN1_201 +set_property -dict {PACKAGE_PIN Y7} [get_ports tx_data_p[2]] ; ## A26 FMC1_DP2_C2M_P GTY_TXP2_201 +set_property -dict {PACKAGE_PIN Y6} [get_ports tx_data_n[2]] ; ## A27 FMC1_DP2_C2M_N GTY_TXN2_201 +set_property -dict {PACKAGE_PIN W9} [get_ports tx_data_p[3]] ; ## A30 FMC1_DP3_C2M_P GTY_TXP3_201 +set_property -dict {PACKAGE_PIN W8} [get_ports tx_data_n[3]] ; ## A31 FMC1_DP3_C2M_N GTY_TXN3_201 +set_property -dict {PACKAGE_PIN V7} [get_ports tx_data_p[4]] ; ## A34 FMC1_DP4_C2M_P GTY_TXP0_202 +set_property -dict {PACKAGE_PIN V6} [get_ports tx_data_n[4]] ; ## A35 FMC1_DP4_C2M_N GTY_TXN0_202 +set_property -dict {PACKAGE_PIN U9} [get_ports tx_data_p[5]] ; ## A38 FMC1_DP5_C2M_P GTY_TXP1_202 +set_property -dict {PACKAGE_PIN U8} [get_ports tx_data_n[5]] ; ## A39 FMC1_DP5_C2M_N GTY_TXN1_202 +set_property -dict {PACKAGE_PIN T7} [get_ports tx_data_p[6]] ; ## B36 FMC1_DP6_C2M_P GTY_TXP2_202 +set_property -dict {PACKAGE_PIN T6} [get_ports tx_data_n[6]] ; ## B37 FMC1_DP6_C2M_N GTY_TXN2_202 +set_property -dict {PACKAGE_PIN R9} [get_ports tx_data_p[7]] ; ## B32 FMC1_DP7_C2M_P GTY_TXP3_202 +set_property -dict {PACKAGE_PIN R8} [get_ports tx_data_n[7]] ; ## B33 FMC1_DP7_C2M_N GTY_TXN3_202 + +set_property -dict {PACKAGE_PIN AW24 IOSTANDARD LVDS15} [get_ports rx_sync_p] ; ## H7 FMC1_LA02_P IO_L17P_N5P4_M2P34_706 +set_property -dict {PACKAGE_PIN AY25 IOSTANDARD LVDS15} [get_ports rx_sync_n] ; ## H8 FMC1_LA02_N IO_L17N_N5P5_M2P35_706 +set_property -dict {PACKAGE_PIN AN20 IOSTANDARD LVDS15} [get_ports rx_sync_1_p] ; ## H37 FMC1_LA32_P IO_L17P_N5P4_M2P88_707 +set_property -dict {PACKAGE_PIN AN19 IOSTANDARD LVDS15} [get_ports rx_sync_1_n] ; ## H38 FMC1_LA32_N IO_L17N_N5P5_M2P89_707 +set_property -dict {PACKAGE_PIN AR18 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100} [get_ports tx_sync_p] ; ## G33 FMC1_LA31_P IO_L14P_N4P4_M2P82_707 +set_property -dict {PACKAGE_PIN AT19 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100} [get_ports tx_sync_n] ; ## G34 FMC1_LA31_N IO_L14N_N4P5_M2P83_707 +set_property -dict {PACKAGE_PIN BF16 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100} [get_ports tx_sync_1_p] ; ## G27 FMC1_LA25_P IO_L10P_N3P2_M2P74_707 +set_property -dict {PACKAGE_PIN BG16 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100} [get_ports tx_sync_1_n] ; ## G28 FMC1_LA25_N IO_L10N_N3P3_M2P75_707 +set_property -dict {PACKAGE_PIN AU20 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100} [get_ports tx_sync_2_p] ; ## G36 FMC1_LA33_P IO_L16P_N5P2_M2P86_707 +set_property -dict {PACKAGE_PIN AU19 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100} [get_ports tx_sync_2_n] ; ## G37 FMC1_LA33_N IO_L16N_N5P3_M2P87_707 + +set_property -dict {PACKAGE_PIN BC23 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100} [get_ports sysref_p] ; ## D8 FMC1_LA01_CC_P IO_L9P_GC_XCC_N3P0_M2P18_706 +set_property -dict {PACKAGE_PIN BD22 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100} [get_ports sysref_n] ; ## D9 FMC1_LA01_CC_N IO_L9N_GC_XCC_N3P1_M2P19_706 +set_property -dict {PACKAGE_PIN AV22 IOSTANDARD LVDS15} [get_ports sysref_out_p] ; ## G9 FMC1_LA03_P IO_L14P_N4P4_M2P28_706 +set_property -dict {PACKAGE_PIN AW21 IOSTANDARD LVDS15} [get_ports sysref_out_n] ; ## G10 FMC1_LA03_N IO_L14N_N4P5_M2P29_706 + +set_property -dict {PACKAGE_PIN BG19 IOSTANDARD LVCMOS15} [get_ports ad9528_sysref_req] ; ## C27 FMC1_LA27_N IO_L2N_N0P5_M2P59_707 +set_property -dict {PACKAGE_PIN BF24 IOSTANDARD LVCMOS15} [get_ports adrv904x_test] ; ## D11 FMC1_LA05_P IO_L5P_N1P4_M2P10_706 + +set_property -dict {PACKAGE_PIN BC20 IOSTANDARD LVCMOS15} [get_ports adrv904x_orx0_enable] ; ## C10 FMC1_LA06_P IO_L10P_N3P2_M2P20_706 +set_property -dict {PACKAGE_PIN BD20 IOSTANDARD LVCMOS15} [get_ports adrv904x_orx1_enable] ; ## C11 FMC1_LA06_N IO_L10N_N3P3_M2P21_706 +set_property -dict {PACKAGE_PIN BE21 IOSTANDARD LVCMOS15} [get_ports adrv904x_trx0_enable] ; ## D17 FMC1_LA13_P IO_L4P_N1P2_M2P8_706 +set_property -dict {PACKAGE_PIN BE20 IOSTANDARD LVCMOS15} [get_ports adrv904x_trx1_enable] ; ## D18 FMC1_LA13_N IO_L4N_N1P3_M2P9_706 +set_property -dict {PACKAGE_PIN BG25 IOSTANDARD LVCMOS15} [get_ports adrv904x_trx2_enable] ; ## C14 FMC1_LA10_P IO_L1P_N0P2_M2P2_706 +set_property -dict {PACKAGE_PIN BG24 IOSTANDARD LVCMOS15} [get_ports adrv904x_trx3_enable] ; ## C15 FMC1_LA10_N IO_L1N_N0P3_M2P3_706 +set_property -dict {PACKAGE_PIN BB20 IOSTANDARD LVCMOS15} [get_ports adrv904x_trx4_enable] ; ## D23 FMC1_LA23_P IO_L1P_N0P2_M2P56_707 +set_property -dict {PACKAGE_PIN BB19 IOSTANDARD LVCMOS15} [get_ports adrv904x_trx5_enable] ; ## D24 FMC1_LA23_N IO_L1N_N0P3_M2P57_707 +set_property -dict {PACKAGE_PIN AU24 IOSTANDARD LVCMOS15} [get_ports adrv904x_trx6_enable] ; ## C18 FMC1_LA14_P IO_L13P_N4P2_M2P26_706 +set_property -dict {PACKAGE_PIN AU23 IOSTANDARD LVCMOS15} [get_ports adrv904x_trx7_enable] ; ## C19 FMC1_LA14_N IO_L13N_N4P3_M2P27_706 + +set_property -dict {PACKAGE_PIN AY22 IOSTANDARD LVCMOS15} [get_ports adrv904x_gpio[0]] ; ## H19 FMC1_LA15_P IO_L15P_XCC_N5P0_M2P30_706 +set_property -dict {PACKAGE_PIN AY23 IOSTANDARD LVCMOS15} [get_ports adrv904x_gpio[1]] ; ## H20 FMC1_LA15_N IO_L15N_XCC_N5P1_M2P31_706 +set_property -dict {PACKAGE_PIN BF21 IOSTANDARD LVCMOS15} [get_ports adrv904x_gpio[2]] ; ## G18 FMC1_LA16_P IO_L2P_N0P4_M2P4_706 +set_property -dict {PACKAGE_PIN BG20 IOSTANDARD LVCMOS15} [get_ports adrv904x_gpio[3]] ; ## G19 FMC1_LA16_N IO_L2N_N0P5_M2P5_706 +set_property -dict {PACKAGE_PIN BE19 IOSTANDARD LVCMOS15} [get_ports adrv904x_gpio[4]] ; ## H25 FMC1_LA21_P IO_L0P_XCC_N0P0_M2P54_707 +set_property -dict {PACKAGE_PIN BD19 IOSTANDARD LVCMOS15} [get_ports adrv904x_gpio[5]] ; ## H26 FMC1_LA21_N IO_L0N_XCC_N0P1_M2P55_707 +set_property -dict {PACKAGE_PIN BE17 IOSTANDARD LVCMOS15} [get_ports adrv904x_gpio[6]] ; ## C22 FMC1_LA18_CC_P IO_L9P_GC_XCC_N3P0_M2P72_707 +set_property -dict {PACKAGE_PIN BD17 IOSTANDARD LVCMOS15} [get_ports adrv904x_gpio[7]] ; ## C23 FMC1_LA18_CC_N IO_L9N_GC_XCC_N3P1_M2P73_707 +set_property -dict {PACKAGE_PIN BA17 IOSTANDARD LVCMOS15} [get_ports adrv904x_gpio[8]] ; ## H22 FMC1_LA19_P IO_L7P_N2P2_M2P68_707 +set_property -dict {PACKAGE_PIN BA16 IOSTANDARD LVCMOS15} [get_ports adrv904x_gpio[9]] ; ## H23 FMC1_LA19_N IO_L7N_N2P3_M2P69_707 +set_property -dict {PACKAGE_PIN BF18 IOSTANDARD LVCMOS15} [get_ports adrv904x_gpio[10]] ; ## G24 FMC1_LA22_P IO_L4P_N1P2_M2P62_707 +set_property -dict {PACKAGE_PIN BG18 IOSTANDARD LVCMOS15} [get_ports adrv904x_gpio[11]] ; ## G25 FMC1_LA22_N IO_L4N_N1P3_M2P63_707 +set_property -dict {PACKAGE_PIN AU21 IOSTANDARD LVCMOS15} [get_ports adrv904x_gpio[12]] ; ## H10 FMC1_LA04_P IO_L16P_N5P2_M2P32_706 +set_property -dict {PACKAGE_PIN AV21 IOSTANDARD LVCMOS15} [get_ports adrv904x_gpio[13]] ; ## H11 FMC1_LA04_N IO_L16N_N5P3_M2P33_706 +set_property -dict {PACKAGE_PIN AM21 IOSTANDARD LVCMOS15} [get_ports adrv904x_gpio[14]] ; ## G30 FMC1_LA29_P IO_L13P_N4P2_M2P80_707 +set_property -dict {PACKAGE_PIN AM20 IOSTANDARD LVCMOS15} [get_ports adrv904x_gpio[15]] ; ## G31 FMC1_LA29_N IO_L13N_N4P3_M2P81_707 +set_property -dict {PACKAGE_PIN BG21 IOSTANDARD LVCMOS15} [get_ports adrv904x_gpio[16]] ; ## G15 FMC1_LA12_P IO_L3P_XCC_N1P0_M2P6_706 +set_property -dict {PACKAGE_PIN BF22 IOSTANDARD LVCMOS15} [get_ports adrv904x_gpio[17]] ; ## G16 FMC1_LA12_N IO_L3N_XCC_N1P1_M2P7_706 +set_property -dict {PACKAGE_PIN BG23 IOSTANDARD LVCMOS15} [get_ports adrv904x_gpio[18]] ; ## D12 FMC1_LA05_N IO_L5N_N1P5_M2P11_706 +set_property -dict {PACKAGE_PIN BE16 IOSTANDARD LVCMOS15} [get_ports adrv904x_gpio[19]] ; ## G21 FMC1_LA20_P IO_L8P_N2P4_M2P70_707 +set_property -dict {PACKAGE_PIN AT20 IOSTANDARD LVCMOS15} [get_ports adrv904x_gpio[20]] ; ## H34 FMC1_LA30_P IO_L15P_XCC_N5P0_M2P84_707 +set_property -dict {PACKAGE_PIN AR20 IOSTANDARD LVCMOS15} [get_ports adrv904x_gpio[21]] ; ## H35 FMC1_LA30_N IO_L15N_XCC_N5P1_M2P85_707 +set_property -dict {PACKAGE_PIN BA20 IOSTANDARD LVCMOS15} [get_ports adrv904x_gpio[22]] ; ## H28 FMC1_LA24_P IO_L5P_N1P4_M2P64_707 +set_property -dict {PACKAGE_PIN BA19 IOSTANDARD LVCMOS15} [get_ports adrv904x_gpio[23]] ; ## H29 FMC1_LA24_N IO_L5N_N1P5_M2P65_707 + +set_property -dict {PACKAGE_PIN BF19 IOSTANDARD LVCMOS15} [get_ports ad9528_reset_b] ; ## C26 FMC1_LA27_P IO_L2P_N0P4_M2P58_707 +set_property -dict {PACKAGE_PIN BF17 IOSTANDARD LVCMOS15} [get_ports adrv904x_reset_b] ; ## G22 FMC1_LA20_N IO_L8N_N2P5_M2P71_707 + +set_property -dict {PACKAGE_PIN BE25 IOSTANDARD LVCMOS15} [get_ports spi_csn_adrv904x] ; ## D14 FMC1_LA09_P IO_L7P_N2P2_M2P14_706 +set_property -dict {PACKAGE_PIN BE24 IOSTANDARD LVCMOS15} [get_ports spi_csn_ad9528] ; ## D15 FMC1_LA09_N IO_L7N_N2P3_M2P15_706 +set_property -dict {PACKAGE_PIN BC25 IOSTANDARD LVCMOS15} [get_ports spi_clk] ; ## H13 FMC1_LA07_P IO_L11P_N3P4_M2P22_706 +set_property -dict {PACKAGE_PIN BC22 IOSTANDARD LVCMOS15} [get_ports spi_miso] ; ## G12 FMC1_LA08_P IO_L8P_N2P4_M2P16_706 +set_property -dict {PACKAGE_PIN BD25 IOSTANDARD LVCMOS15} [get_ports spi_mosi] ; ## H14 FMC1_LA07_N IO_L11N_N3P5_M2P23_706 + +# clocks + +create_clock -period 4.069 -name device_clk [get_ports core_clk_p] +create_clock -period 4.069 -name ref_clk [get_ports ref_clk0_p] diff --git a/projects/adrv904x/vck190/system_project.tcl b/projects/adrv904x/vck190/system_project.tcl new file mode 100644 index 0000000000..623824e025 --- /dev/null +++ b/projects/adrv904x/vck190/system_project.tcl @@ -0,0 +1,43 @@ +############################################################################### +## Copyright (C) 2024 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +# get_env_param retrieves parameter value from the environment if exists, +# other case use the default value +# +# Use over-writable parameters from the environment. +# +# Parameter description: +# [TX/RX/RX_OS]_JESD_M : Number of converters per link +# [TX/RX/RX_OS]_JESD_L : Number of lanes per link +# [TX/RX/RX_OS]_JESD_S : Number of samples per frame +# [TX/RX/RX_OS]_JESD_NP : Number of bits per sample + +adi_project adrv904x_vck190 0 [list \ + JESD_MODE [get_env_param JESD_MODE 64B66B] \ + TX_LANE_RATE [get_env_param TX_LANE_RATE 16.22] \ + RX_LANE_RATE [get_env_param RX_LANE_RATE 16.22] \ + TX_NUM_LINKS [get_env_param RX_NUM_LINKS 1] \ + RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1] \ + TX_JESD_M [get_env_param TX_JESD_M 16] \ + TX_JESD_L [get_env_param TX_JESD_L 8] \ + TX_JESD_S [get_env_param TX_JESD_S 1] \ + TX_JESD_NP [get_env_param TX_JESD_NP 16] \ + RX_JESD_M [get_env_param RX_JESD_M 16] \ + RX_JESD_L [get_env_param RX_JESD_L 8] \ + RX_JESD_S [get_env_param RX_JESD_S 1] \ + RX_JESD_NP [get_env_param RX_JESD_NP 16] \ +] + +adi_project_files adrv904x_vck190 [list \ + "system_top.v" \ + "system_constr.xdc"\ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/vck190/vck190_system_constr.xdc"] + +adi_project_run adrv904x_vck190 diff --git a/projects/adrv904x/vck190/system_top.v b/projects/adrv904x/vck190/system_top.v new file mode 100644 index 0000000000..11d80fc401 --- /dev/null +++ b/projects/adrv904x/vck190/system_top.v @@ -0,0 +1,309 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2024 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + input sys_clk_n, + input sys_clk_p, + + output ddr4_act_n, + output [16:0] ddr4_adr, + output [1:0] ddr4_ba, + output [1:0] ddr4_bg, + output ddr4_ck_c, + output ddr4_ck_t, + output ddr4_cke, + output ddr4_cs_n, + inout [7:0] ddr4_dm_n, + inout [63:0] ddr4_dq, + inout [7:0] ddr4_dqs_c, + inout [7:0] ddr4_dqs_t, + output ddr4_odt, + output ddr4_reset_n, + + output [ 3:0] gpio_led, + input [ 3:0] gpio_dip_sw, + input [ 1:0] gpio_pb, + + input core_clk_p, + input core_clk_n, + input ref_clk0_p, + input ref_clk0_n, + input ref_clk1_p, + input ref_clk1_n, + input [ 7:0] rx_data_p, + input [ 7:0] rx_data_n, + output [ 7:0] tx_data_p, + output [ 7:0] tx_data_n, + output rx_sync_p, + output rx_sync_n, + output rx_sync_1_p, + output rx_sync_1_n, + input tx_sync_p, + input tx_sync_n, + input tx_sync_1_p, + input tx_sync_1_n, + input tx_sync_2_p, + input tx_sync_2_n, + + input sysref_p, + input sysref_n, + output sysref_out_p, + output sysref_out_n, + + output spi_csn_ad9528, + output spi_csn_adrv904x, + output spi_clk, + output spi_mosi, + input spi_miso, + + inout ad9528_reset_b, + inout ad9528_sysref_req, + inout adrv904x_trx0_enable, + inout adrv904x_trx1_enable, + inout adrv904x_trx2_enable, + inout adrv904x_trx3_enable, + inout adrv904x_trx4_enable, + inout adrv904x_trx5_enable, + inout adrv904x_trx6_enable, + inout adrv904x_trx7_enable, + inout adrv904x_orx0_enable, + inout adrv904x_orx1_enable, + inout adrv904x_test, + output adrv904x_reset_b, + + inout [23:0] adrv904x_gpio +); + + // internal signals + wire [95:0] gpio_i; + wire [95:0] gpio_o; + wire [95:0] gpio_t; + + // Board GPIOS. Buttons, LEDs, etc... + assign gpio_led = gpio_o[3:0]; + assign gpio_i[3:0] = gpio_o[3:0]; + assign gpio_i[7:4] = gpio_dip_sw; + assign gpio_i[9:8] = gpio_pb; + + // Unused GPIOs + assign gpio_i[95:77] = gpio_o[95:77]; + assign gpio_i[31:10] = gpio_o[31:10]; + + wire [ 2:0] spi_csn; + wire rx_sync; + wire tx_sync; + wire sysref; + wire ref_clk0; + wire ref_clk1; + wire [ 7:0] rx_data_p_loc; + wire [ 7:0] rx_data_n_loc; + wire [ 7:0] tx_data_p_loc; + wire [ 7:0] tx_data_n_loc; + + wire gt_reset; + wire gt_reset_s; + wire rx_reset_pll_and_datapath; + wire tx_reset_pll_and_datapath; + wire rx_reset_datapath; + wire tx_reset_datapath; + wire gt_resetdone; + wire gt_powergood; + wire mst_resetdone; + + // instantiations + + IBUFDS i_ibufds_core_clk ( + .I (core_clk_p), + .IB (core_clk_n), + .O (core_clk)); + + BUFG i_ibufg_core_clk ( + .I (core_clk), + .O (core_clk_buf)); + + IBUFDS_GTE5 i_ibufds_ref_clk0 ( + .CEB (1'd0), + .I (ref_clk0_p), + .IB (ref_clk0_n), + .O (ref_clk0), + .ODIV2 (ref_clk0_odiv2)); + + IBUFDS_GTE5 i_ibufds_ref_clk1 ( + .CEB (1'd0), + .I (ref_clk1_p), + .IB (ref_clk1_n), + .O (ref_clk1), + .ODIV2 (ref_clk1_odiv2)); + + OBUFDS i_obufds_rx_sync ( + .I (rx_sync), + .O (rx_sync_p), + .OB (rx_sync_n)); + + OBUFDS i_obufds_rx_sync_1 ( + .I (rx_sync_1), + .O (rx_sync_1_p), + .OB (rx_sync_1_n)); + + OBUFDS i_obufds_sysref_out ( + .I (sysref_out), + .O (sysref_out_p), + .OB (sysref_out_n)); + + IBUFDS i_ibufds_tx_sync ( + .I (tx_sync_p), + .IB (tx_sync_n), + .O (tx_sync)); + + IBUFDS i_ibufds_tx_sync_1 ( + .I (tx_sync_1_p), + .IB (tx_sync_1_n), + .O (tx_sync_1)); + + IBUFDS i_ibufds_tx_sync_2 ( + .I (tx_sync_2_p), + .IB (tx_sync_2_n), + .O (tx_sync_2)); + + IBUFDS i_ibufds_sysref ( + .I (sysref_p), + .IB (sysref_n), + .O (sysref)); + + ad_iobuf #( + .DATA_WIDTH(37) + ) i_iobuf ( + .dio_t ({gpio_t[68:32]}), + .dio_i ({gpio_o[68:32]}), + .dio_o ({gpio_i[68:32]}), + .dio_p ({ ad9528_reset_b, // 68 + ad9528_sysref_req, // 67 + adrv904x_trx0_enable, // 66 + adrv904x_trx1_enable, // 65 + adrv904x_trx2_enable, // 64 + adrv904x_trx3_enable, // 63 + adrv904x_trx4_enable, // 62 + adrv904x_trx5_enable, // 61 + adrv904x_trx6_enable, // 60 + adrv904x_trx7_enable, // 59 + adrv904x_orx0_enable, // 58 + adrv904x_orx1_enable, // 57 + adrv904x_test, // 56 + adrv904x_gpio})); // 55-32 + + assign adrv904x_reset_b = gpio_o[69]; + + assign gpio_i[70] = gt_resetdone; + assign gpio_i[71] = mst_resetdone; + assign gt_reset = gpio_o[72]; + assign rx_reset_pll_and_datapath = gpio_o[73]; + assign tx_reset_pll_and_datapath = gpio_o[74]; + assign rx_reset_datapath = gpio_o[75]; + assign tx_reset_datapath = gpio_o[76]; + + assign gt_reset_s = gt_reset & gt_powergood; + assign mst_resetdone = gt_resetdone; + + assign spi_csn_ad9528 = spi_csn[1]; + assign spi_csn_adrv904x = spi_csn[0]; + + system_wrapper i_system_wrapper ( + .gpio0_i (gpio_i[31:0]), + .gpio0_o (gpio_o[31:0]), + .gpio0_t (gpio_t[31:0]), + .gpio1_i (gpio_i[63:32]), + .gpio1_o (gpio_o[63:32]), + .gpio1_t (gpio_t[63:32]), + .gpio2_i (gpio_i[95:64]), + .gpio2_o (gpio_o[95:64]), + .gpio2_t (gpio_t[95:64]), + .ddr4_dimm1_sma_clk_clk_n (sys_clk_n), + .ddr4_dimm1_sma_clk_clk_p (sys_clk_p), + .ddr4_dimm1_act_n (ddr4_act_n), + .ddr4_dimm1_adr (ddr4_adr), + .ddr4_dimm1_ba (ddr4_ba), + .ddr4_dimm1_bg (ddr4_bg), + .ddr4_dimm1_ck_c (ddr4_ck_c), + .ddr4_dimm1_ck_t (ddr4_ck_t), + .ddr4_dimm1_cke (ddr4_cke), + .ddr4_dimm1_cs_n (ddr4_cs_n), + .ddr4_dimm1_dm_n (ddr4_dm_n), + .ddr4_dimm1_dq (ddr4_dq), + .ddr4_dimm1_dqs_c (ddr4_dqs_c), + .ddr4_dimm1_dqs_t (ddr4_dqs_t), + .ddr4_dimm1_odt (ddr4_odt), + .ddr4_dimm1_reset_n (ddr4_reset_n), + .gt_reset (gt_reset_s), + .gt_reset_rx_datapath (rx_reset_datapath), + .gt_reset_tx_datapath (tx_reset_datapath), + .gt_reset_rx_pll_and_datapath (rx_reset_pll_and_datapath), + .gt_reset_tx_pll_and_datapath (tx_reset_pll_and_datapath), + .gt_powergood (gt_powergood), + .rx_resetdone (gt_resetdone), + .tx_resetdone (gt_resetdone), + .core_clk(core_clk_buf), + .rx_0_p (rx_data_p_loc[3:0]), + .rx_0_n (rx_data_n_loc[3:0]), + .rx_1_p (rx_data_p_loc[7:4]), + .rx_1_n (rx_data_n_loc[7:4]), + .rx_ref_clk_0 (ref_clk0), + .rx_ref_clk_1 (ref_clk0), + .rx_sysref_0 (sysref), + .spi0_sclk (spi_clk), + .spi0_csn (spi_csn), + .spi0_miso (spi_miso), + .spi0_mosi (spi_mosi), + .spi1_sclk (), + .spi1_csn (), + .spi1_miso (1'b0), + .spi1_mosi (), + .tx_0_p (tx_data_p_loc[3:0]), + .tx_0_n (tx_data_n_loc[3:0]), + .tx_1_p (tx_data_p_loc[7:4]), + .tx_1_n (tx_data_n_loc[7:4]), + .tx_ref_clk_0 (ref_clk0), + .tx_ref_clk_1 (ref_clk0), + .tx_sysref_0 (sysref), + .ext_sync_in (sysref)); + + assign rx_data_p_loc[7:0] = rx_data_p[7:0]; + assign rx_data_n_loc[7:0] = rx_data_n[7:0]; + + assign tx_data_p[7:0] = tx_data_p_loc[7:0]; + assign tx_data_n[7:0] = tx_data_n_loc[7:0]; + +endmodule