diff --git a/docs/projects/images/ad7616_sdz/ad7616_parallel_hdl.svg b/docs/projects/images/ad7616_sdz/ad7616_parallel_hdl.svg index 6ab89f6ede..a1e53bcd12 100644 --- a/docs/projects/images/ad7616_sdz/ad7616_parallel_hdl.svg +++ b/docs/projects/images/ad7616_sdz/ad7616_parallel_hdl.svg @@ -1,22 +1,21 @@ + width="891.4917" + xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape" + xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd" + xmlns:xlink="http://www.w3.org/1999/xlink" + xmlns="http://www.w3.org/2000/svg" + xmlns:svg="http://www.w3.org/2000/svg" + xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" + xmlns:cc="http://creativecommons.org/ns#" + xmlns:dc="http://purl.org/dc/elements/1.1/"> + id="linearGradient5412" + inkscape:swatch="solid"> + + + + + + + id="base" + inkscape:showpageshadow="2" + inkscape:pagecheckerboard="0" + inkscape:deskcolor="#d1d1d1"> Zed ZC706 - + sodipodi:role="line">Zed FMC CONNECTOR - - AD7616_DMA AD7616PARALLEL - sys_clk = 100MHz + RX_CNVST trigger + + + + AXI CLKGEN + spi_clk = 100MHz + + + + + + + AD7616_DMA + + sys_clk = 100MHz + width="891.4917" + xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape" + xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd" + xmlns:xlink="http://www.w3.org/1999/xlink" + xmlns="http://www.w3.org/2000/svg" + xmlns:svg="http://www.w3.org/2000/svg" + xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" + xmlns:cc="http://creativecommons.org/ns#" + xmlns:dc="http://purl.org/dc/elements/1.1/"> + id="linearGradient5412" + inkscape:swatch="solid"> + + + + + + + + + + + + @@ -1049,23 +1108,26 @@ inkscape:snap-page="true" showguides="false" inkscape:window-maximized="1" - inkscape:window-y="1072" + inkscape:window-y="1342" inkscape:window-x="-8" - inkscape:window-height="1017" + inkscape:window-height="1122" inkscape:window-width="1920" units="px" showgrid="true" - inkscape:current-layer="layer1" + inkscape:current-layer="g11134" inkscape:document-units="px" - inkscape:cy="407.31" - inkscape:cx="333.05362" + inkscape:cy="358.09908" + inkscape:cx="471.23616" inkscape:zoom="0.98994949" inkscape:pageshadow="2" inkscape:pageopacity="0.0" borderopacity="1.0" bordercolor="#666666" pagecolor="#ffffff" - id="base"> + id="base" + inkscape:showpageshadow="2" + inkscape:pagecheckerboard="0" + inkscape:deskcolor="#d1d1d1"> Zed ZC706 + sodipodi:role="line">Zed + style="display:inline;opacity:1;fill:none;fill-opacity:1;stroke:#3f4b55;stroke-width:1.74916497;stroke-linecap:round;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:1.74916497,5.2474947;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" /> + INTER- sys_clk = 100MHz + y="289.00757" + x="27.253187" + sodipodi:role="line"> sys_clk = 100MHz + RX_CNVST AXI PWM GEN + + AXI CLKGEN + spi_clk = 100MHz + + + + + + = t_conversion + t_aquisition - // See the AD7616 datasheet for more information. - - always @(posedge up_clk) begin - if(up_resetn == 1'b0) begin - cnvst_counter <= 32'b0; - end else begin - cnvst_counter <= (cnvst_counter < up_conv_rate) ? cnvst_counter + 1 : 32'b0; - end - end - - always @(cnvst_counter, up_conv_rate) begin - cnvst_pulse <= (cnvst_counter == up_conv_rate) ? 1'b1 : 1'b0; - end - - always @(posedge up_clk) begin - if(up_resetn == 1'b0) begin - pulse_counter <= 3'b0; - cnvst_buf <= 1'b0; - end else begin - pulse_counter <= (cnvst == 1'b1) ? pulse_counter + 1 : 3'b0; - if(cnvst_pulse == 1'b1) begin - cnvst_buf <= 1'b1; - end else if (pulse_counter[2] == 1'b1) begin - cnvst_buf <= 1'b0; - end - end - end - - assign cnvst = (up_cnvst_en == 1'b1) ? cnvst_buf : 1'b0; - endmodule diff --git a/library/axi_ad7616/axi_ad7616_ip.tcl b/library/axi_ad7616/axi_ad7616_ip.tcl index fdc8e5f4b0..ca1c98e2a2 100644 --- a/library/axi_ad7616/axi_ad7616_ip.tcl +++ b/library/axi_ad7616/axi_ad7616_ip.tcl @@ -11,24 +11,15 @@ global VIVADO_IP_LIBRARY adi_ip_create axi_ad7616 adi_ip_files axi_ad7616 [list \ - "$ad_hdl_dir/library/common/ad_edge_detect.v" \ "$ad_hdl_dir/library/common/up_axi.v" \ "axi_ad7616_control.v" \ "axi_ad7616_pif.v" \ - "axi_ad7616_maxis2wrfifo.v" \ "axi_ad7616.v" ] adi_ip_properties axi_ad7616 set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_ad7616} [ipx::current_core] -adi_ip_add_core_dependencies [list \ - analog.com:$VIVADO_IP_LIBRARY:spi_engine_execution:1.0 \ - analog.com:$VIVADO_IP_LIBRARY:axi_spi_engine:1.0 \ - analog.com:$VIVADO_IP_LIBRARY:spi_engine_offload:1.0 \ - analog.com:$VIVADO_IP_LIBRARY:spi_engine_interconnect:1.0 \ -] - set_property DRIVER_VALUE "0" [ipx::get_ports rx_db_i] ipx::save_core [ipx::current_core] diff --git a/library/axi_ad7616/axi_ad7616_maxis2wrfifo.v b/library/axi_ad7616/axi_ad7616_maxis2wrfifo.v deleted file mode 100644 index 6db5dbef1e..0000000000 --- a/library/axi_ad7616/axi_ad7616_maxis2wrfifo.v +++ /dev/null @@ -1,82 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module axi_ad7616_maxis2wrfifo #( - - parameter DATA_WIDTH = 16 -) ( - input clk, - input rstn, - input sync_in, - - // m_axis interface - - input [DATA_WIDTH-1:0] m_axis_data, - output reg m_axis_ready, - input m_axis_valid, - output reg m_axis_xfer_req, - - // write fifo interface - - output reg fifo_wr_en, - output reg [DATA_WIDTH-1:0] fifo_wr_data, - output reg fifo_wr_sync, - input fifo_wr_xfer_req -); - - always @(posedge clk) begin - if (rstn == 1'b0) begin - m_axis_ready <= 1'b0; - m_axis_xfer_req <= 1'b0; - fifo_wr_data <= 'b0; - fifo_wr_en <= 1'b0; - fifo_wr_sync <= 1'b0; - end else begin - m_axis_ready <= 1'b1; - m_axis_xfer_req <= fifo_wr_xfer_req; - fifo_wr_data <= m_axis_data; - fifo_wr_en <= m_axis_valid; - if (sync_in == 1'b1) begin - fifo_wr_sync <= 1'b1; - end else if ((m_axis_valid == 1'b1) && - (fifo_wr_sync == 1'b1)) begin - fifo_wr_sync <= 1'b0; - end - end - end - -endmodule diff --git a/projects/ad7616_sdz/common/ad7616_bd.tcl b/projects/ad7616_sdz/common/ad7616_bd.tcl index 5dc107bdbb..6c6bb0256e 100644 --- a/projects/ad7616_sdz/common/ad7616_bd.tcl +++ b/projects/ad7616_sdz/common/ad7616_bd.tcl @@ -2,87 +2,176 @@ ## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### - -# system level parameters -set SI_OR_PI $ad_project_params(SI_OR_PI) - -puts "build parameters: SI_OR_PI: $SI_OR_PI" - -# data interfaces - -create_bd_port -dir O rx_sclk -create_bd_port -dir O rx_sdo -create_bd_port -dir I -from 1 -to 0 rx_sdi - -create_bd_port -dir O -from 15 -to 0 rx_db_o -create_bd_port -dir I -from 15 -to 0 rx_db_i -create_bd_port -dir O rx_db_t -create_bd_port -dir O rx_rd_n -create_bd_port -dir O rx_wr_n +##-------------------------------------------------------------- + +# IMPORTANT: Set AD7616 operation and interface mode +# +# The get_env_param procedure retrieves parameter value from the environment if exists, +# other case returns the default value specified in its second parameter field. +# +# How to use over-writable parameters from the environment: +# +# e.g. +# make SER_PAR_N=0 +# +# SER_PAR_N - Defines the interface type (serial OR parallel) +# - Default value is 1 +# +# LEGEND: Serial - 1 +# Parallel - 0 +# +# NOTE : This switch is a 'hardware' switch. Please rebuild the design if the +# variable has been changed. +# SL5 - mounted - Serial +# SL5 - unmounted - Parallel +# +##-------------------------------------------------------------- + +set SER_PAR_N $ad_project_params(SER_PAR_N) +puts "build parameters: SER_PAR_N: $SER_PAR_N" # control lines create_bd_port -dir O rx_cnvst -create_bd_port -dir O rx_cs_n create_bd_port -dir I rx_busy # instantiation -ad_ip_instance axi_ad7616 axi_ad7616 -ad_ip_parameter axi_ad7616 CONFIG.IF_TYPE $SI_OR_PI +# dma ad_ip_instance axi_dmac axi_ad7616_dma -ad_ip_parameter axi_ad7616_dma CONFIG.DMA_TYPE_SRC 2 ad_ip_parameter axi_ad7616_dma CONFIG.DMA_TYPE_DEST 0 ad_ip_parameter axi_ad7616_dma CONFIG.CYCLIC 0 ad_ip_parameter axi_ad7616_dma CONFIG.DMA_2D_TRANSFER 0 -ad_ip_parameter axi_ad7616_dma CONFIG.DMA_DATA_WIDTH_SRC 16 ad_ip_parameter axi_ad7616_dma CONFIG.DMA_DATA_WIDTH_DEST 64 -# interface connections -if {$SI_OR_PI == 0} { +# axi_pwm_gen - ad_connect rx_sclk axi_ad7616/rx_sclk - ad_connect rx_sdo axi_ad7616/rx_sdo - ad_connect rx_sdi axi_ad7616/rx_sdi - ad_connect rx_cs_n axi_ad7616/rx_cs_n +ad_ip_instance axi_pwm_gen ad7616_pwm_gen +ad_ip_parameter ad7616_pwm_gen CONFIG.PULSE_0_PERIOD 100 +ad_ip_parameter ad7616_pwm_gen CONFIG.PULSE_0_WIDTH 5 +ad_ip_parameter ad7616_pwm_gen CONFIG.ASYNC_CLK_EN 1 + +# axi_clkgen + +ad_ip_instance axi_clkgen spi_clkgen +ad_ip_parameter spi_clkgen CONFIG.CLK0_DIV 6 +ad_ip_parameter spi_clkgen CONFIG.VCO_DIV 1 +ad_ip_parameter spi_clkgen CONFIG.VCO_MUL 6 + +# trigger to BUSY's negative edge + +create_bd_cell -type module -reference sync_bits busy_sync +create_bd_cell -type module -reference ad_edge_detect busy_capture +set_property -dict [list CONFIG.EDGE 1] [get_bd_cells busy_capture] + +ad_connect spi_clk busy_capture/clk +ad_connect busy_capture/rst GND +ad_connect spi_clk busy_sync/out_clk +ad_connect busy_sync/in_bits rx_busy +ad_connect busy_sync/out_bits busy_capture/signal_in + +if {$SER_PAR_N == 1} { + create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 ad7616_spi + + source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl + + set data_width 16 + set async_spi_clk 1 + set num_cs 1 + set num_sdi 2 + set sdi_delay 1 + set hier_spi_engine spi_ad7616 + + spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $sdi_delay + + ad_ip_parameter axi_ad7616_dma CONFIG.DMA_DATA_WIDTH_SRC 32 + ad_ip_parameter axi_ad7616_dma CONFIG.DMA_TYPE_SRC 1 + ad_ip_parameter axi_ad7616_dma CONFIG.SYNC_TRANSFER_START 0 + ad_ip_parameter axi_ad7616_dma CONFIG.AXI_SLICE_SRC 0 + ad_ip_parameter axi_ad7616_dma CONFIG.AXI_SLICE_DEST 1 + + # interface connections - ad_connect rx_cnvst axi_ad7616/rx_cnvst - ad_connect rx_busy axi_ad7616/rx_busy + ad_connect $sys_cpu_clk $hier_spi_engine/clk + ad_connect spi_clk $hier_spi_engine/spi_clk + ad_connect sys_cpu_resetn $hier_spi_engine/resetn + ad_connect $hier_spi_engine/m_spi ad7616_spi + + ad_connect spi_clk axi_ad7616_dma/s_axis_aclk + ad_connect axi_ad7616_dma/s_axis $hier_spi_engine/m_axis_sample + + ad_connect busy_sync/out_resetn $hier_spi_engine/${hier_spi_engine}_axi_regmap/spi_resetn + ad_connect busy_capture/signal_out $hier_spi_engine/${hier_spi_engine}_offload/trigger + + # interconnect + + ad_cpu_interconnect 0x44A00000 $hier_spi_engine/${hier_spi_engine}_axi_regmap + + # interrupts + + ad_cpu_interrupt ps-12 mb-12 /$hier_spi_engine/irq } else { + # data interfaces + + create_bd_port -dir O -from 15 -to 0 rx_db_o + create_bd_port -dir I -from 15 -to 0 rx_db_i + create_bd_port -dir O rx_db_t + create_bd_port -dir O rx_rd_n + create_bd_port -dir O rx_wr_n + create_bd_port -dir O rx_cs_n + + ad_ip_parameter axi_ad7616_dma CONFIG.DMA_DATA_WIDTH_SRC 16 + ad_ip_parameter axi_ad7616_dma CONFIG.DMA_TYPE_SRC 2 + + ad_ip_instance axi_ad7616 axi_ad7616 + + # interface connections ad_connect rx_db_o axi_ad7616/rx_db_o ad_connect rx_db_i axi_ad7616/rx_db_i ad_connect rx_db_t axi_ad7616/rx_db_t ad_connect rx_rd_n axi_ad7616/rx_rd_n ad_connect rx_wr_n axi_ad7616/rx_wr_n - ad_connect rx_cs_n axi_ad7616/rx_cs_n - ad_connect rx_cnvst axi_ad7616/rx_cnvst - ad_connect rx_busy axi_ad7616/rx_busy + + ad_connect $sys_cpu_clk axi_ad7616_dma/fifo_wr_clk + ad_connect axi_ad7616/adc_valid axi_ad7616_dma/fifo_wr_en + ad_connect axi_ad7616/adc_data axi_ad7616_dma/fifo_wr_din + ad_connect axi_ad7616/adc_sync axi_ad7616_dma/fifo_wr_sync + + ad_connect busy_capture/signal_out axi_ad7616/rx_trigger + ad_connect busy_sync/out_resetn sys_cpu_resetn + + # interconnect + + ad_cpu_interconnect 0x44A80000 axi_ad7616 } -ad_connect sys_cpu_clk axi_ad7616_dma/s_axi_aclk -ad_connect sys_cpu_clk axi_ad7616_dma/fifo_wr_clk -ad_connect axi_ad7616/adc_valid axi_ad7616_dma/fifo_wr_en -ad_connect axi_ad7616/adc_data axi_ad7616_dma/fifo_wr_din -ad_connect axi_ad7616/adc_sync axi_ad7616_dma/fifo_wr_sync +# interface connections +ad_connect $sys_cpu_clk spi_clkgen/clk +ad_connect spi_clk spi_clkgen/clk_0 + +ad_connect ad7616_pwm_gen/pwm_0 rx_cnvst +ad_connect $sys_cpu_clk ad7616_pwm_gen/s_axi_aclk +ad_connect sys_cpu_resetn ad7616_pwm_gen/s_axi_aresetn +ad_connect spi_clk ad7616_pwm_gen/ext_clk +ad_connect $sys_cpu_clk axi_ad7616_dma/s_axi_aclk +ad_connect sys_cpu_resetn axi_ad7616_dma/m_dest_axi_aresetn # interconnect -ad_cpu_interconnect 0x44A00000 axi_ad7616 ad_cpu_interconnect 0x44A30000 axi_ad7616_dma +ad_cpu_interconnect 0x44A70000 spi_clkgen +ad_cpu_interconnect 0x44B00000 ad7616_pwm_gen # memory interconnect -ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1 -ad_mem_hp1_interconnect sys_cpu_clk axi_ad7616_dma/m_dest_axi -ad_connect sys_cpu_resetn axi_ad7616_dma/m_dest_axi_aresetn +ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1 +ad_mem_hp1_interconnect $sys_cpu_clk axi_ad7616_dma/m_dest_axi # interrupts -ad_cpu_interrupt ps-13 mb-12 axi_ad7616_dma/irq -ad_cpu_interrupt ps-12 mb-13 axi_ad7616/irq - +ad_cpu_interrupt ps-13 mb-13 axi_ad7616_dma/irq diff --git a/projects/ad7616_sdz/common/ad7616_parallel_fmc.txt b/projects/ad7616_sdz/common/ad7616_parallel_fmc.txt new file mode 100644 index 0000000000..1706b56022 --- /dev/null +++ b/projects/ad7616_sdz/common/ad7616_parallel_fmc.txt @@ -0,0 +1,35 @@ +FMC_pin FMC_port Schematic_name System_top_name IOSTANDARD Termination + +# ad7616 - Parallel mode +# Note: The design uses an SDP to FMC interposer. + +R19 FMC_LPC_LA10_P DB0 adc_db[0] LVCMOS25 #N/A +M21 FMC_LPC_LA04_P DB1 adc_db[1] LVCMOS25 #N/A +R20 FMC_LPC_LA09_P DB2 adc_db[2] LVCMOS25 #N/A +N22 FMC_LPC_LA03_P DB3 adc_db[3] LVCMOS25 #N/A +K18 FMC_LPC_LA05_N DB4 adc_db[4] LVCMOS25 #N/A +P18 FMC_LPC_LA02_N DB5 adc_db[5] LVCMOS25 #N/A +L22 FMC_LPC_LA06_N DB6 adc_db[6] LVCMOS25 #N/A +M20 FMC_LPC_LA00_CC_N DB7 adc_db[7] LVCMOS25 #N/A +J18 FMC_LPC_LA05_P DB8 adc_db[8] LVCMOS25 #N/A +P17 FMC_LPC_LA02_P DB9 adc_db[9] LVCMOS25 #N/A +L21 FMC_LPC_LA06_P DB10 adc_db[10] LVCMOS25 #N/A +M19 FMC_LPC_LA00_CC_P DB11 adc_db[11] LVCMOS25 #N/A +N20 FMC_LPC_LA01_CC_N DB12 adc_db[12] LVCMOS25 #N/A +L19 FMC_LPC_CLK0_M2C_N DB13 adc_db[13] LVCMOS25 #N/A +L18 FMC_LPC_CLK0_M2C_P DB14 adc_db[14] LVCMOS25 #N/A +N19 FMC_LPC_LA01_CC_P DB15 adc_db[15] LVCMOS25 #N/A + +P22 FMC_LPC_LA03_N SCLK/RDn adc_rd_n LVCMOS25 #N/A +R21 FMC_LPC_LA09_N WRn adc_wr_n LVCMOS25 #N/A + +A18 FMC_LPC_LA24_P CONVST adc_cnvst LVCMOS25 #N/A +E20 FMC_LPC_LA21_N CHSEL0 adc_chsel[0] LVCMOS25 #N/A +E18 FMC_LPC_LA26_N CHSEL1 adc_chsel[1] LVCMOS25 #N/A +D22 FMC_LPC_LA25_P CHSEL2 adc_chsel[2] LVCMOS25 #N/A +E19 FMC_LPC_LA21_P HW_RNGSEL0 adc_hw_rngsel[0] LVCMOS25 #N/A +F18 FMC_LPC_LA26_P HW_RNGSEL1 adc_hw_rngsel[1] LVCMOS25 #N/A +T19 FMC_LPC_LA10_N BUSY adc_busy LVCMOS25 #N/A +E21 FMC_LPC_LA27_P SEQEN adc_seq_en LVCMOS25 #N/A +F19 FMC_LPC_LA22_N RESETn adc_reset_n LVCMOS25 #N/A +M22 FMC_LPC_LA04_N CSn adc_cs_n LVCMOS25 #N/A diff --git a/projects/ad7616_sdz/common/ad7616_serial_fmc.txt b/projects/ad7616_sdz/common/ad7616_serial_fmc.txt new file mode 100644 index 0000000000..ca3fab6904 --- /dev/null +++ b/projects/ad7616_sdz/common/ad7616_serial_fmc.txt @@ -0,0 +1,26 @@ +FMC_pin FMC_port Schematic_name System_top_name IOSTANDARD Termination + +# ad7616 - Serial mode +# Note: The design uses an SDP to FMC interposer. + +P22 FMC_LPC_LA03_N SCLK/RDn ad7616_spi_sclk LVCOMOS25 #N/A +L21 FMC_LPC_LA03_P DB3 ad7616_spi_sdo LVCOMOS25 #N/A +M19 FMC_LPC_LA00_CC_P DB11/DOUT0 ad7616_spi_sdi[0] LVCOMOS25 #N/A +N20 FMC_LPC_LA01_CC_N DB7 ad7616_spi_sdi[1] LVCOMOS25 #N/A +M22 FMC_LPC_LA04_N CSn ad7616_spi_cs LVCOMOS25 #N/A + +A18 FMC_LPC_LA24_P CONVST adc_cnvst LVCOMOS25 #N/A +E20 FMC_LPC_LA21_N CHSEL0 adc_chsel[0] LVCOMOS25 #N/A +E18 FMC_LPC_LA26_N CHSEL1 adc_chsel[1] LVCOMOS25 #N/A +D22 FMC_LPC_LA25_P CHSEL2 adc_chsel[2 LVCOMOS25 #N/A +E19 FMC_LPC_LA21_P HW_RNGSEL0 adc_hw_rngsel[0] LVCOMOS25 #N/A +F18 FMC_LPC_LA26_P HW_RNGSEL1 adc_hw_rngsel[1] LVCOMOS25 #N/A +T19 FMC_LPC_LA10_N BUSY adc_busy LVCOMOS25 #N/A +E21 FMC_LPC_LA27_P SEQEN adc_seq_en LVCOMOS25 #N/A +F19 FMC_LPC_LA22_N RESETn adc_reset_n LVCOMOS25 #N/A + +L19 FMC_LPC_CLK0_M2C_N DB13 adc_os[0] LVCOMOS25 #N/A +L18 FMC_LPC_CLK0_M2C_P DB14 adc_os[1] LVCOMOS25 #N/A +N19 FMC_LPC_LA01_CC_P DB15 adc_os[2] LVCOMOS25 #N/A +R21 FMC_LPC_LA09_N WRn adc_burst LVCOMOS25 #N/A +P18 FMC_LPC_LA02_N DB5 adc_crcen LVCOMOS25 #N/A diff --git a/projects/ad7616_sdz/zc706/Makefile b/projects/ad7616_sdz/zc706/Makefile deleted file mode 100644 index ea319ce62f..0000000000 --- a/projects/ad7616_sdz/zc706/Makefile +++ /dev/null @@ -1,25 +0,0 @@ -#################################################################################### -## Copyright (c) 2018 - 2023 Analog Devices, Inc. -### SPDX short identifier: BSD-1-Clause -## Auto-generated, do not modify! -#################################################################################### - -PROJECT_NAME := ad7616_sdz_zc706 - -M_DEPS += serial_if_constr.xdc -M_DEPS += parallel_if_constr.xdc -M_DEPS += ../common/ad7616_bd.tcl -M_DEPS += ../../scripts/adi_pd.tcl -M_DEPS += ../../common/zc706/zc706_system_constr.xdc -M_DEPS += ../../common/zc706/zc706_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v - -LIB_DEPS += axi_ad7616 -LIB_DEPS += axi_clkgen -LIB_DEPS += axi_dmac -LIB_DEPS += axi_hdmi_tx -LIB_DEPS += axi_spdif_tx -LIB_DEPS += axi_sysid -LIB_DEPS += sysid_rom - -include ../../scripts/project-xilinx.mk diff --git a/projects/ad7616_sdz/zc706/parallel_if_constr.xdc b/projects/ad7616_sdz/zc706/parallel_if_constr.xdc deleted file mode 100644 index fcc8b038a2..0000000000 --- a/projects/ad7616_sdz/zc706/parallel_if_constr.xdc +++ /dev/null @@ -1,39 +0,0 @@ -############################################################################### -## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -# ad7616 - -set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVCMOS25} [get_ports adc_db[0] ] ; ## FMC_LPC_LA10_P -set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVCMOS25} [get_ports adc_db[1] ] ; ## FMC_LPC_LA04_P -set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVCMOS25} [get_ports adc_db[2] ] ; ## FMC_LPC_LA09_P -set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVCMOS25} [get_ports adc_db[3] ] ; ## FMC_LPC_LA03_P -set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVCMOS25} [get_ports adc_db[4] ] ; ## FMC_LPC_LA05_N -set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS25} [get_ports adc_db[5] ] ; ## FMC_LPC_LA02_N -set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS25} [get_ports adc_db[6] ] ; ## FMC_LPC_LA06_N -set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS25} [get_ports adc_db[7] ] ; ## FMC_LPC_LA00_CC_N -set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVCMOS25} [get_ports adc_db[8] ] ; ## FMC_LPC_LA05_P -set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS25} [get_ports adc_db[9] ] ; ## FMC_LPC_LA02_P -set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS25} [get_ports adc_db[10]] ; ## FMC_LPC_LA06_P -set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS25} [get_ports adc_db[11]] ; ## FMC_LPC_LA00_CC_P -set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVCMOS25} [get_ports adc_db[12]] ; ## FMC_LPC_LA01_CC_N -set_property -dict {PACKAGE_PIN AG16 IOSTANDARD LVCMOS25} [get_ports adc_db[13]] ; ## FMC_LPC_CLK0_M2C_N -set_property -dict {PACKAGE_PIN AG17 IOSTANDARD LVCMOS25} [get_ports adc_db[14]] ; ## FMC_LPC_CLK0_M2C_P -set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS25} [get_ports adc_db[15]] ; ## FMC_LPC_LA01_CC_P - -set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVCMOS25} [get_ports adc_rd_n] ; ## FMC_LPC_LA03_N -set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVCMOS25} [get_ports adc_wr_n] ; ## FMC_LPC_LA09_N - -# control lines - -set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVCMOS25} [get_ports adc_convst] ; ## FMC_LPC_LA24_P -set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVCMOS25} [get_ports adc_chsel[0]] ; ## FMC_LPC_LA21_N -set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS25} [get_ports adc_chsel[1]] ; ## FMC_LPC_LA26_N -set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVCMOS25} [get_ports adc_chsel[2]] ; ## FMC_LPC_LA25_P -set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[0]] ; ## FMC_LPC_LA21_P -set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[1]] ; ## FMC_LPC_LA26_P -set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVCMOS25} [get_ports adc_busy] ; ## FMC_LPC_LA10_N -set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVCMOS25} [get_ports adc_seq_en] ; ## FMC_LPC_LA27_P -set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVCMOS25} [get_ports adc_reset_n] ; ## FMC_LPC_LA22_N -set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVCMOS25} [get_ports adc_cs_n] ; ## FMC_LPC_LA04_N diff --git a/projects/ad7616_sdz/zc706/serial_if_constr.xdc b/projects/ad7616_sdz/zc706/serial_if_constr.xdc deleted file mode 100644 index 853facaab3..0000000000 --- a/projects/ad7616_sdz/zc706/serial_if_constr.xdc +++ /dev/null @@ -1,33 +0,0 @@ -############################################################################### -## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -# ad7616 - -# data interface - -set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVCMOS25} [get_ports spi_sclk] ; ## FMC_LPC_LA03_N -set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS25} [get_ports spi_sdo] ; ## FMC_LPC_LA06_P -set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS25} [get_ports spi_sdi[0]] ; ## FMC_LPC_LA00_CC_P -set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVCMOS25} [get_ports spi_sdi[1]] ; ## FMC_LPC_LA01_CC_N -set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVCMOS25} [get_ports spi_cs_n] ; ## FMC_LPC_LA04_N - -# control lines - -set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVCMOS25} [get_ports adc_convst] ; ## FMC_LPC_LA24_P -set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVCMOS25} [get_ports adc_chsel[0]] ; ## FMC_LPC_LA21_N -set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS25} [get_ports adc_chsel[1]] ; ## FMC_LPC_LA26_N -set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVCMOS25} [get_ports adc_chsel[2]] ; ## FMC_LPC_LA25_P -set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[0]] ; ## FMC_LPC_LA21_P -set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[1]] ; ## FMC_LPC_LA26_P -set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVCMOS25} [get_ports adc_busy] ; ## FMC_LPC_LA10_N -set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVCMOS25} [get_ports adc_seq_en] ; ## FMC_LPC_LA27_P -set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVCMOS25} [get_ports adc_reset_n] ; ## FMC_LPC_LA22_N - -set_property -dict {PACKAGE_PIN AG16 IOSTANDARD LVCMOS25} [get_ports adc_os[0]] ; ## FMC_LPC_CLK0_M2C_N -set_property -dict {PACKAGE_PIN AG17 IOSTANDARD LVCMOS25} [get_ports adc_os[1]] ; ## FMC_LPC_CLK0_M2C_P -set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS25} [get_ports adc_os[2]] ; ## FMC_LPC_LA01_CC_P -set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVCMOS25} [get_ports adc_burst] ; ## FMC_LPC_LA09_N -set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS25} [get_ports adc_crcen] ; ## FMC_LPC_LA02_N - diff --git a/projects/ad7616_sdz/zc706/system_bd.tcl b/projects/ad7616_sdz/zc706/system_bd.tcl deleted file mode 100644 index ed8efbbf42..0000000000 --- a/projects/ad7616_sdz/zc706/system_bd.tcl +++ /dev/null @@ -1,19 +0,0 @@ -############################################################################### -## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl -source $ad_hdl_dir/projects/scripts/adi_pd.tcl - -set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt; - -#system ID -ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 -ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path" -ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 - -sysid_gen_sys_init_file - -source ../common/ad7616_bd.tcl - diff --git a/projects/ad7616_sdz/zc706/system_project.tcl b/projects/ad7616_sdz/zc706/system_project.tcl deleted file mode 100644 index be056425eb..0000000000 --- a/projects/ad7616_sdz/zc706/system_project.tcl +++ /dev/null @@ -1,60 +0,0 @@ -############################################################################### -## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -source ../../../scripts/adi_env.tcl -source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl -source $ad_hdl_dir/projects/scripts/adi_board.tcl - -##-------------------------------------------------------------- -# IMPORTANT: Set AD7616 operation and interface mode -# -# The get_env_param procedure retrieves parameter value from the environment if exists, -# other case returns the default value specified in its second parameter field. -# -# How to use over-writable parameters from the environment: -# -# e.g. -# make SI_OR_PI=0 -# -# SI_OR_PI - Defines the interface type (serial OR parallel) -# -# LEGEND: Serial - 0 -# Parallel - 1 -# -# NOTE : This switch is a 'hardware' switch. Please reimplenent the -# design if the variable has been changed. -# -##-------------------------------------------------------------- - -if {[info exists ::env(SI_OR_PI)]} { - set S_SI_OR_PI [get_env_param SI_OR_PI 0] -} elseif {![info exists SI_OR_PI]} { - set S_SI_OR_PI 0 -} - -adi_project ad7616_sdz_zc706 0 [list \ - SI_OR_PI $S_SI_OR_PI \ -] - -adi_project_files ad7616_sdz_zc706 [list \ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ - "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc"] - -switch $S_SI_OR_PI { - 0 { - adi_project_files ad7616_sdz_zc706 [list \ - "system_top_si.v" \ - "serial_if_constr.xdc" - ] - } - 1 { - adi_project_files ad7616_sdz_zc706 [list \ - "system_top_pi.v" \ - "parallel_if_constr.xdc" - ] - } -} - -adi_project_run ad7616_sdz_zc706 diff --git a/projects/ad7616_sdz/zc706/system_top_pi.v b/projects/ad7616_sdz/zc706/system_top_pi.v deleted file mode 100644 index 6de7fae263..0000000000 --- a/projects/ad7616_sdz/zc706/system_top_pi.v +++ /dev/null @@ -1,174 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module system_top ( - - inout [14:0] ddr_addr, - inout [ 2:0] ddr_ba, - inout ddr_cas_n, - inout ddr_ck_n, - inout ddr_ck_p, - inout ddr_cke, - inout ddr_cs_n, - inout [ 3:0] ddr_dm, - inout [31:0] ddr_dq, - inout [ 3:0] ddr_dqs_n, - inout [ 3:0] ddr_dqs_p, - inout ddr_odt, - inout ddr_ras_n, - inout ddr_reset_n, - inout ddr_we_n, - - inout fixed_io_ddr_vrn, - inout fixed_io_ddr_vrp, - inout [53:0] fixed_io_mio, - inout fixed_io_ps_clk, - inout fixed_io_ps_porb, - inout fixed_io_ps_srstb, - - inout [14:0] gpio_bd, - - output hdmi_out_clk, - output hdmi_vsync, - output hdmi_hsync, - output hdmi_data_e, - output [23:0] hdmi_data, - - output spdif, - - inout iic_scl, - inout iic_sda, - - inout [15:0] adc_db, - output adc_rd_n, - output adc_wr_n, - - output adc_cs_n, - output adc_reset_n, - output adc_convst, - input adc_busy, - output adc_seq_en, - output [ 1:0] adc_hw_rngsel, - output [ 2:0] adc_chsel -); - - // internal signals - - wire [63:0] gpio_i; - wire [63:0] gpio_o; - wire [63:0] gpio_t; - - wire adc_db_t; - wire [15:0] adc_db_o; - wire [15:0] adc_db_i; - - genvar i; - - // instantiations - - ad_iobuf #( - .DATA_WIDTH(7) - ) i_iobuf_adc_cntrl ( - .dio_t ({gpio_t[43:41], gpio_t[37], gpio_t[35:33]}), - .dio_i ({gpio_o[43:41], gpio_o[37], gpio_o[35:33]}), - .dio_o ({gpio_i[43:41], gpio_i[37], gpio_i[35:33]}), - .dio_p ({adc_reset_n, // 43 - adc_hw_rngsel, // 42:41 - adc_seq_en, // 37 - adc_chsel})); // 35:33 - - generate - for (i = 0; i < 16; i = i + 1) begin: adc_db_io - ad_iobuf i_iobuf_adc_db ( - .dio_t(adc_db_t), - .dio_i(adc_db_o[i]), - .dio_o(adc_db_i[i]), - .dio_p(adc_db[i])); - end - endgenerate - - ad_iobuf #( - .DATA_WIDTH(15) - ) i_iobuf_gpio ( - .dio_t(gpio_t[14:0]), - .dio_i(gpio_o[14:0]), - .dio_o(gpio_i[14:0]), - .dio_p(gpio_bd)); - - system_wrapper i_system_wrapper ( - .ddr_addr (ddr_addr), - .ddr_ba (ddr_ba), - .ddr_cas_n (ddr_cas_n), - .ddr_ck_n (ddr_ck_n), - .ddr_ck_p (ddr_ck_p), - .ddr_cke (ddr_cke), - .ddr_cs_n (ddr_cs_n), - .ddr_dm (ddr_dm), - .ddr_dq (ddr_dq), - .ddr_dqs_n (ddr_dqs_n), - .ddr_dqs_p (ddr_dqs_p), - .ddr_odt (ddr_odt), - .ddr_ras_n (ddr_ras_n), - .ddr_reset_n (ddr_reset_n), - .ddr_we_n (ddr_we_n), - .fixed_io_ddr_vrn (fixed_io_ddr_vrn), - .fixed_io_ddr_vrp (fixed_io_ddr_vrp), - .fixed_io_mio (fixed_io_mio), - .fixed_io_ps_clk (fixed_io_ps_clk), - .fixed_io_ps_porb (fixed_io_ps_porb), - .fixed_io_ps_srstb (fixed_io_ps_srstb), - .gpio_i (gpio_i), - .gpio_o (gpio_o), - .gpio_t (gpio_t), - .hdmi_data (hdmi_data), - .hdmi_data_e (hdmi_data_e), - .hdmi_hsync (hdmi_hsync), - .hdmi_out_clk (hdmi_out_clk), - .hdmi_vsync (hdmi_vsync), - .iic_main_scl_io (iic_scl), - .iic_main_sda_io (iic_sda), - .spdif (spdif), - .rx_cnvst (adc_convst), - .rx_cs_n (adc_cs_n), - .rx_busy (adc_busy), - .rx_db_o (adc_db_o), - .rx_db_i (adc_db_i), - .rx_db_t (adc_db_t), - .rx_rd_n (adc_rd_n), - .rx_wr_n (adc_wr_n)); - -endmodule diff --git a/projects/ad7616_sdz/zc706/system_top_si.v b/projects/ad7616_sdz/zc706/system_top_si.v deleted file mode 100644 index 9f7ef0209b..0000000000 --- a/projects/ad7616_sdz/zc706/system_top_si.v +++ /dev/null @@ -1,162 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module system_top ( - - inout [14:0] ddr_addr, - inout [ 2:0] ddr_ba, - inout ddr_cas_n, - inout ddr_ck_n, - inout ddr_ck_p, - inout ddr_cke, - inout ddr_cs_n, - inout [ 3:0] ddr_dm, - inout [31:0] ddr_dq, - inout [ 3:0] ddr_dqs_n, - inout [ 3:0] ddr_dqs_p, - inout ddr_odt, - inout ddr_ras_n, - inout ddr_reset_n, - inout ddr_we_n, - - inout fixed_io_ddr_vrn, - inout fixed_io_ddr_vrp, - inout [53:0] fixed_io_mio, - inout fixed_io_ps_clk, - inout fixed_io_ps_porb, - inout fixed_io_ps_srstb, - - inout [14:0] gpio_bd, - - output hdmi_out_clk, - output hdmi_vsync, - output hdmi_hsync, - output hdmi_data_e, - output [23:0] hdmi_data, - - output spdif, - - inout iic_scl, - inout iic_sda, - - output spi_sclk, - output spi_sdo, - input [ 1:0] spi_sdi, - output spi_cs_n, - - output adc_reset_n, - output adc_convst, - input adc_busy, - output adc_seq_en, - output [ 1:0] adc_hw_rngsel, - output [ 2:0] adc_chsel, - output adc_crcen, - output adc_burst, - output [ 2:0] adc_os -); - - // internal signals - - wire [63:0] gpio_i; - wire [63:0] gpio_o; - wire [63:0] gpio_t; - - // instantiations - - ad_iobuf #( - .DATA_WIDTH(12) - ) i_iobuf_adc_cntrl ( - .dio_t (gpio_t[43:32]), - .dio_i (gpio_o[43:32]), - .dio_o (gpio_i[43:32]), - .dio_p ({adc_reset_n, // 43 - adc_hw_rngsel, // 42:41 - adc_os, // 40:38 - adc_seq_en, // 37 - adc_burst, // 36 - adc_chsel, // 35:33 - adc_crcen})); // 32 - - ad_iobuf #( - .DATA_WIDTH(15) - ) i_iobuf_gpio ( - .dio_t(gpio_t[14:0]), - .dio_i(gpio_o[14:0]), - .dio_o(gpio_i[14:0]), - .dio_p(gpio_bd)); - - system_wrapper i_system_wrapper ( - .ddr_addr (ddr_addr), - .ddr_ba (ddr_ba), - .ddr_cas_n (ddr_cas_n), - .ddr_ck_n (ddr_ck_n), - .ddr_ck_p (ddr_ck_p), - .ddr_cke (ddr_cke), - .ddr_cs_n (ddr_cs_n), - .ddr_dm (ddr_dm), - .ddr_dq (ddr_dq), - .ddr_dqs_n (ddr_dqs_n), - .ddr_dqs_p (ddr_dqs_p), - .ddr_odt (ddr_odt), - .ddr_ras_n (ddr_ras_n), - .ddr_reset_n (ddr_reset_n), - .ddr_we_n (ddr_we_n), - .fixed_io_ddr_vrn (fixed_io_ddr_vrn), - .fixed_io_ddr_vrp (fixed_io_ddr_vrp), - .fixed_io_mio (fixed_io_mio), - .fixed_io_ps_clk (fixed_io_ps_clk), - .fixed_io_ps_porb (fixed_io_ps_porb), - .fixed_io_ps_srstb (fixed_io_ps_srstb), - .gpio_i (gpio_i), - .gpio_o (gpio_o), - .gpio_t (gpio_t), - .hdmi_data (hdmi_data), - .hdmi_data_e (hdmi_data_e), - .hdmi_hsync (hdmi_hsync), - .hdmi_out_clk (hdmi_out_clk), - .hdmi_vsync (hdmi_vsync), - .iic_main_scl_io (iic_scl), - .iic_main_sda_io (iic_sda), - .spdif (spdif), - .rx_sclk (spi_sclk), - .rx_sdo (spi_sdo), - .rx_sdi (spi_sdi), - .rx_cnvst (adc_convst), - .rx_cs_n (spi_cs_n), - .rx_busy (adc_busy)); - -endmodule diff --git a/projects/ad7616_sdz/zed/Makefile b/projects/ad7616_sdz/zed/Makefile index 1b25ef3fbd..85ac8e849a 100644 --- a/projects/ad7616_sdz/zed/Makefile +++ b/projects/ad7616_sdz/zed/Makefile @@ -12,15 +12,23 @@ M_DEPS += ../common/ad7616_bd.tcl M_DEPS += ../../scripts/adi_pd.tcl M_DEPS += ../../common/zed/zed_system_constr.xdc M_DEPS += ../../common/zed/zed_system_bd.tcl +M_DEPS += ../../../library/util_cdc/sync_bits.v +M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/common/ad_edge_detect.v LIB_DEPS += axi_ad7616 LIB_DEPS += axi_clkgen LIB_DEPS += axi_dmac LIB_DEPS += axi_hdmi_tx LIB_DEPS += axi_i2s_adi +LIB_DEPS += axi_pwm_gen LIB_DEPS += axi_spdif_tx LIB_DEPS += axi_sysid +LIB_DEPS += spi_engine/axi_spi_engine +LIB_DEPS += spi_engine/spi_engine_execution +LIB_DEPS += spi_engine/spi_engine_interconnect +LIB_DEPS += spi_engine/spi_engine_offload LIB_DEPS += sysid_rom LIB_DEPS += util_i2c_mixer diff --git a/projects/ad7616_sdz/zed/parallel_if_constr.xdc b/projects/ad7616_sdz/zed/parallel_if_constr.xdc index 5032540ba6..503dcf51d3 100644 --- a/projects/ad7616_sdz/zed/parallel_if_constr.xdc +++ b/projects/ad7616_sdz/zed/parallel_if_constr.xdc @@ -28,7 +28,7 @@ set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS25} [get_ports adc_wr_n # control lines -set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS25} [get_ports adc_convst] ; ## FMC_LPC_LA24_P +set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS25} [get_ports adc_cnvst] ; ## FMC_LPC_LA24_P set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS25} [get_ports adc_chsel[0]] ; ## FMC_LPC_LA21_N set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports adc_chsel[1]] ; ## FMC_LPC_LA26_N set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS25} [get_ports adc_chsel[2]] ; ## FMC_LPC_LA25_P diff --git a/projects/ad7616_sdz/zed/serial_if_constr.xdc b/projects/ad7616_sdz/zed/serial_if_constr.xdc index a1336b63af..d420049c34 100644 --- a/projects/ad7616_sdz/zed/serial_if_constr.xdc +++ b/projects/ad7616_sdz/zed/serial_if_constr.xdc @@ -7,15 +7,15 @@ # data interface -set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports spi_sclk] ; ## FMC_LPC_LA03_N -set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25} [get_ports spi_sdo] ; ## FMC_LPC_LA06_P -set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports spi_sdi[0]] ; ## FMC_LPC_LA00_CC_P -set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports spi_sdi[1]] ; ## FMC_LPC_LA01_CC_N -set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports spi_cs_n] ; ## FMC_LPC_LA04_N +set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports ad7616_spi_sclk] ; ## FMC_LPC_LA03_N +set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25} [get_ports ad7616_spi_sdo] ; ## FMC_LPC_LA06_P +set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports ad7616_spi_sdi[0]] ; ## FMC_LPC_LA00_CC_P +set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports ad7616_spi_sdi[1]] ; ## FMC_LPC_LA01_CC_N +set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports ad7616_spi_cs] ; ## FMC_LPC_LA04_N # control lines -set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS25} [get_ports adc_convst] ; ## FMC_LPC_LA24_P +set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS25} [get_ports adc_cnvst] ; ## FMC_LPC_LA24_P set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS25} [get_ports adc_chsel[0]] ; ## FMC_LPC_LA21_N set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports adc_chsel[1]] ; ## FMC_LPC_LA26_N set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS25} [get_ports adc_chsel[2]] ; ## FMC_LPC_LA25_P diff --git a/projects/ad7616_sdz/zed/system_bd.tcl b/projects/ad7616_sdz/zed/system_bd.tcl index 628a6ff903..3e97e8563a 100644 --- a/projects/ad7616_sdz/zed/system_bd.tcl +++ b/projects/ad7616_sdz/zed/system_bd.tcl @@ -15,5 +15,12 @@ ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 sysid_gen_sys_init_file +# system level parameters +set SER_PAR_N $ad_project_params(SER_PAR_N) + +adi_project_files ad7616_sdz_zed [list \ + "../../../library/common/ad_edge_detect.v" \ + "../../../library/util_cdc/sync_bits.v"] + source ../common/ad7616_bd.tcl diff --git a/projects/ad7616_sdz/zed/system_project.tcl b/projects/ad7616_sdz/zed/system_project.tcl index 75b8f776df..7262df3092 100644 --- a/projects/ad7616_sdz/zed/system_project.tcl +++ b/projects/ad7616_sdz/zed/system_project.tcl @@ -16,40 +16,43 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # How to use over-writable parameters from the environment: # # e.g. -# make SI_OR_PI=0 +# make SER_PAR_N=0 # -# SI_OR_PI - Defines the interface type (serial OR parallel) +# SER_PAR_N - Defines the interface type (serial OR parallel) +# - Default value is 1 # -# LEGEND: Serial - 0 -# Parallel - 1 +# LEGEND: Serial - 1 +# Parallel - 0 # -# NOTE : This switch is a 'hardware' switch. Please reimplenent the -# design if the variable has been changed. +# NOTE : This switch is a 'hardware' switch. Please rebuild the design if the +# variable has been changed. +# SL5 - mounted - Serial +# SL5 - unmounted - Parallel # ##-------------------------------------------------------------- -if {[info exists ::env(SI_OR_PI)]} { - set S_SI_OR_PI [get_env_param SI_OR_PI 0] -} elseif {![info exists SI_OR_PI]} { - set S_SI_OR_PI 0 +if {[info exists ::env(SER_PAR_N)]} { + set S_SER_PAR_N [get_env_param SER_PAR_N 0] +} elseif {![info exists SER_PAR_N]} { + set S_SER_PAR_N 1 } adi_project ad7616_sdz_zed 0 [list \ - SI_OR_PI $S_SI_OR_PI \ + SER_PAR_N $S_SER_PAR_N \ ] adi_project_files ad7616_sdz_zed [list \ "$ad_hdl_dir/library/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"] -switch $S_SI_OR_PI { - 0 { +switch $S_SER_PAR_N { + 1 { adi_project_files ad7616_sdz_zed [list \ "system_top_si.v" \ "serial_if_constr.xdc" ] } - 1 { + 0 { adi_project_files ad7616_sdz_zed [list \ "system_top_pi.v" \ "parallel_if_constr.xdc" diff --git a/projects/ad7616_sdz/zed/system_top_pi.v b/projects/ad7616_sdz/zed/system_top_pi.v index 91a16f3e39..de78bb9a8f 100644 --- a/projects/ad7616_sdz/zed/system_top_pi.v +++ b/projects/ad7616_sdz/zed/system_top_pi.v @@ -89,7 +89,7 @@ module system_top ( output adc_cs_n, output adc_reset_n, - output adc_convst, + output adc_cnvst, input adc_busy, output adc_seq_en, output [ 1:0] adc_hw_rngsel, @@ -130,16 +130,15 @@ module system_top ( assign gpio_i[63:44] = gpio_o[63:44]; assign gpio_i[40:38] = gpio_o[40:38]; assign gpio_i[36] = gpio_o[36]; + assign gpio_i[32] = gpio_o[32]; - generate - for (i = 0; i < 16; i = i + 1) begin: adc_db_io - ad_iobuf i_iobuf_adc_db ( - .dio_t(adc_db_t), - .dio_i(adc_db_o[i]), - .dio_o(adc_db_i[i]), - .dio_p(adc_db[i])); - end - endgenerate + ad_iobuf #( + .DATA_WIDTH(16) + ) i_iobuf_adc_db ( + .dio_t(adc_db_t), + .dio_i(adc_db_o[15:0]), + .dio_o(adc_db_i[15:0]), + .dio_p(adc_db[15:0])); ad_iobuf #( .DATA_WIDTH(32) @@ -210,7 +209,7 @@ module system_top ( .iic_mux_sda_t (iic_mux_sda_t_s), .otg_vbusoc (otg_vbusoc), .spdif (spdif), - .rx_cnvst (adc_convst), + .rx_cnvst (adc_cnvst), .rx_cs_n (adc_cs_n), .rx_busy (adc_busy), .rx_db_o (adc_db_o), diff --git a/projects/ad7616_sdz/zed/system_top_si.v b/projects/ad7616_sdz/zed/system_top_si.v index 62d98150c9..c800e5587c 100644 --- a/projects/ad7616_sdz/zed/system_top_si.v +++ b/projects/ad7616_sdz/zed/system_top_si.v @@ -83,13 +83,13 @@ module system_top ( input otg_vbusoc, - output spi_sclk, - output spi_sdo, - input [ 1:0] spi_sdi, - output spi_cs_n, + output ad7616_spi_sclk, + output ad7616_spi_sdo, + input [ 1:0] ad7616_spi_sdi, + output ad7616_spi_cs, output adc_reset_n, - output adc_convst, + output adc_cnvst, input adc_busy, output adc_seq_en, output [ 1:0] adc_hw_rngsel, @@ -198,11 +198,11 @@ module system_top ( .iic_mux_sda_t (iic_mux_sda_t_s), .otg_vbusoc (otg_vbusoc), .spdif (spdif), - .rx_cnvst (adc_convst), - .rx_sclk (spi_sclk), - .rx_sdo (spi_sdo), - .rx_sdi (spi_sdi), - .rx_cs_n (spi_cs_n), - .rx_busy (adc_busy)); + .ad7616_spi_sdo (ad7616_spi_sdo), + .ad7616_spi_sdi (ad7616_spi_sdi), + .ad7616_spi_cs (ad7616_spi_cs), + .ad7616_spi_sclk (ad7616_spi_sclk), + .rx_busy (adc_busy), + .rx_cnvst (adc_cnvst)); endmodule