diff --git a/docs/projects/ad9081_fmca_ebz/index.rst b/docs/projects/ad9081_fmca_ebz/index.rst index c881038d50..5eaaf35c9f 100644 --- a/docs/projects/ad9081_fmca_ebz/index.rst +++ b/docs/projects/ad9081_fmca_ebz/index.rst @@ -83,6 +83,9 @@ Supported carriers * - :adi:`AD9081-FMCA-EBZ ` - `A10SoC`_ - FMCA + * - + - :intel:`FM87 ` + - FMCA * - - :xilinx:`VCK190` - FMC0 @@ -141,6 +144,22 @@ Supported carriers For the carrier, `A10SoC`_, the following reworks are mandatory: :dokuwiki:`[Wiki] FMC Pin Connection Configuration ` +.. warning:: + For `FM87`_ setups, the following reworks are required on the evaluation + board: + + - C39B, C40B: 50 ohm + + For the carrier, `FM87`_, the following reworks are required: + + - R1433, R1434: 50 ohm + - R1777, R1778: 50 ohm + - C2488, C4289: 0 ohm + - R1231, R1234: 1k ohm + - R1230, R1233: 1k ohm + + :red:`This project requires Quartus Pro 24.1!` + Block design ------------------------------------------------------------------------------- @@ -296,6 +315,7 @@ The following are the parameters of this project that can be configured: - RX_LANE_RATE: lane rate of the Rx link (MxFE to FPGA) - TX_LANE_RATE: lane rate of the Tx link (FPGA to MxFE) - REF_CLK_RATE: the rate of the reference clock +- DEVICE_CLK_RATE: the rate of the device clock (Intel only) - [RX/TX]_JESD_M: number of converters per link - [RX/TX]_JESD_L: number of lanes per link - [RX/TX]_JESD_S: number of samples per frame @@ -528,65 +548,67 @@ for that project (ad9081_fmca_ebz/carrier or ad9082_fmca_ebz/carrier). .. collapsible:: Default values of the ``make`` parameters for AD9081-FMCA-EBZ - +-------------------+---------------------------------------------------------------+ - | Parameter | Default value of the parameters depending on carrier | - | +----------+--------+--------+--------+-------+--------+--------+ - | | A10SoC | VCK190 | VPK180 | VCU118 | VCU128 | ZC706 | ZCU102 | - +===================+==========+========+========+========+========+=======+========+ - | JESD_MODE | --- | 64B66B | 64B66B | 8B10B | 8B10B | 8B10B | 8B10B| - +-------------------+----------+--------+--------+--------+--------+-------+--------+ - | RX_LANE_RATE | 10 | 24.75 | 24.75 | 10 | 10 | 10 | 10 | - +-------------------+----------+--------+--------+--------+--------+-------+--------+ - | TX_LANE_RATE | 10 | 24.75 | 24.75 | 10 | 10 | 10 | 10 | - +-------------------+----------+--------+--------+--------+--------+-------+--------+ - | REF_CLK_RATE | --- | 375 | 375 | --- | --- | --- | --- | - +-------------------+----------+--------+--------+--------+--------+-------+--------+ - | RX_JESD_M | 8 | 8 | 8 | 8 | 8 | 8 | 8 | - +-------------------+----------+--------+--------+--------+--------+-------+--------+ - | RX_JESD_L | 4 | 8 | 8 | 4 | 4 | 4 | 4 | - +-------------------+----------+--------+--------+--------+--------+-------+--------+ - | RX_JESD_S | 1 | 2 | 2 | 1 | 1 | 1 | 1 | - +-------------------+----------+--------+--------+--------+--------+-------+--------+ - | RX_JESD_NP | 16 | 12 | 12 | 16 | 16 | 16 | 16 | - +-------------------+----------+--------+--------+--------+--------+-------+--------+ - | RX_NUM_LINKS | 1 | 1 | 1 | 1 | 1 | 1 | 1 | - +-------------------+----------+--------+--------+--------+--------+-------+--------+ - | RX_TPL_WIDTH | --- | --- | --- | --- | --- | --- | {} | - +-------------------+----------+--------+--------+--------+--------+-------+--------+ - | TX_JESD_M | 8 | 8 | 8 | 8 | 8 | 8 | 8 | - +-------------------+----------+--------+--------+--------+--------+-------+--------+ - | TX_JESD_L | 4 | 8 | 8 | 4 | 4 | 4 | 4 | - +-------------------+----------+--------+--------+--------+--------+-------+--------+ - | TX_JESD_S | 1 | 2 | 2 | 1 | 1 | 1 | 1 | - +-------------------+----------+--------+--------+--------+--------+-------+--------+ - | TX_JESD_NP | 16 | 12 | 12 | 16 | 16 | 16 | 16 | - +-------------------+----------+--------+--------+--------+--------+-------+--------+ - | TX_NUM_LINKS | 1 | 1 | 1 | 1 | 1 | 1 | 1 | - +-------------------+----------+--------+--------+--------+--------+-------+--------+ - | TX_TPL_WIDTH | --- | --- | --- | --- | --- | --- | {} | - +-------------------+----------+--------+--------+--------+--------+-------+--------+ - | TDD_SUPPORT | --- | --- | --- | --- | --- | --- | 0 | - +-------------------+----------+--------+--------+--------+--------+-------+--------+ - | SHARED_DEVCLK | --- | --- | --- | --- | --- | --- | 0 | - +-------------------+----------+--------+--------+--------+--------+-------+--------+ - | TDD_CHANNEL_CNT | --- | --- | --- | --- | --- | --- | 2 | - +-------------------+----------+--------+--------+--------+--------+-------+--------+ - | TDD_SYNC_WIDTH | --- | --- | --- | --- | --- | --- | 32 | - +-------------------+----------+--------+--------+--------+--------+-------+--------+ - | TDD_SYNC_INT | --- | --- | --- | --- | --- | --- | 1 | - +-------------------+----------+--------+--------+--------+--------+-------+--------+ - | TDD_SYNC_EXT | --- | --- | --- | --- | --- | --- | 0 | - +-------------------+----------+--------+--------+--------+--------+-------+--------+ - | TDD_SYNC_EXT_CDC | --- | --- | --- | --- | --- | --- | 0 | - +-------------------+----------+--------+--------+--------+--------+-------+--------+ - | RX_KS_PER_CHANNEL | 32 | 64 | 64 | 64 | 16384 | --- | --- | - +-------------------+----------+--------+--------+--------+--------+-------+--------+ - | TX_KS_PER_CHANNEL | 32 | 64 | 64 | 64 | 16384 | --- | --- | - +-------------------+----------+--------+--------+--------+--------+-------+--------+ - | ADC_DO_MEM_TYPE | --- | --- | --- | --- | 2 | --- | --- | - +-------------------+----------+--------+--------+--------+--------+-------+--------+ - | DAC_DO_MEM_TYPE | --- | --- | --- | --- | 2 | --- | --- | - +-------------------+----------+--------+--------+--------+-------+--------+--------+ + +-------------------+--------------------------------------------------------------------------+ + | Parameter | Default value of the parameters depending on carrier | + | +----------+----------+--------+--------+--------+--------+-------+--------+ + | | A10SoC | FM87 | VCK190 | VPK180 | VCU118 | VCU128 | ZC706 | ZCU102 | + +===================+==========+==========+========+========+========+========+=======+========+ + | JESD_MODE | --- | 8B10B | 64B66B | 64B66B | 8B10B | 8B10B | 8B10B | 8B10B | + +-------------------+----------+----------+--------+--------+--------+--------+-------+--------+ + | RX_LANE_RATE | 10 | 15 | 24.75 | 24.75 | 10 | 10 | 10 | 10 | + +-------------------+----------+----------+--------+--------+--------+--------+-------+--------+ + | TX_LANE_RATE | 10 | 15 | 24.75 | 24.75 | 10 | 10 | 10 | 10 | + +-------------------+----------+----------+--------+--------+--------+--------+-------+--------+ + | REF_CLK_RATE | 250 | 375 | 375 | --- | 375 | --- | --- | --- | + +-------------------+----------+----------+--------+--------+--------+--------+-------+--------+ + | DEVICE_CLK_RATE | 250 | 375 | --- | --- | --- | --- | --- | --- | + +-------------------+----------+----------+--------+--------+--------+--------+-------+--------+ + | RX_JESD_M | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | + +-------------------+----------+----------+--------+--------+--------+--------+-------+--------+ + | RX_JESD_L | 4 | 8 | 8 | 8 | 4 | 4 | 4 | 4 | + +-------------------+----------+----------+--------+--------+--------+--------+-------+--------+ + | RX_JESD_S | 1 | 1 | 2 | 2 | 1 | 1 | 1 | 1 | + +-------------------+----------+----------+--------+--------+--------+--------+-------+--------+ + | RX_JESD_NP | 16 | 16 | 12 | 12 | 16 | 16 | 16 | 16 | + +-------------------+----------+----------+--------+--------+--------+--------+-------+--------+ + | RX_NUM_LINKS | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | + +-------------------+----------+----------+--------+--------+--------+--------+-------+--------+ + | RX_TPL_WIDTH | --- | --- | --- | --- | --- | --- | --- | {} | + +-------------------+----------+----------+--------+--------+--------+--------+-------+--------+ + | TX_JESD_M | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | + +-------------------+----------+----------+--------+--------+--------+--------+-------+--------+ + | TX_JESD_L | 4 | 8 | 8 | 8 | 4 | 4 | 4 | 4 | + +-------------------+----------+----------+--------+--------+--------+--------+-------+--------+ + | TX_JESD_S | 1 | 1 | 2 | 2 | 1 | 1 | 1 | 1 | + +-------------------+----------+----------+--------+--------+--------+--------+-------+--------+ + | TX_JESD_NP | 16 | 16 | 12 | 12 | 16 | 16 | 16 | 16 | + +-------------------+----------+----------+--------+--------+--------+--------+-------+--------+ + | TX_NUM_LINKS | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | + +-------------------+----------+----------+--------+--------+--------+--------+-------+--------+ + | TX_TPL_WIDTH | --- | --- | --- | --- | --- | --- | --- | {} | + +-------------------+----------+----------+--------+--------+--------+--------+-------+--------+ + | TDD_SUPPORT | --- | --- | --- | --- | --- | --- | --- | 0 | + +-------------------+----------+----------+--------+--------+--------+--------+-------+--------+ + | SHARED_DEVCLK | --- | --- | --- | --- | --- | --- | --- | 0 | + +-------------------+----------+----------+--------+--------+--------+--------+-------+--------+ + | TDD_CHANNEL_CNT | --- | --- | --- | --- | --- | --- | --- | 2 | + +-------------------+----------+----------+--------+--------+--------+--------+-------+--------+ + | TDD_SYNC_WIDTH | --- | --- | --- | --- | --- | --- | --- | 32 | + +-------------------+----------+----------+--------+--------+--------+--------+-------+--------+ + | TDD_SYNC_INT | --- | --- | --- | --- | --- | --- | --- | 1 | + +-------------------+----------+----------+--------+--------+--------+--------+-------+--------+ + | TDD_SYNC_EXT | --- | --- | --- | --- | --- | --- | --- | 0 | + +-------------------+----------+----------+--------+--------+--------+--------+-------+--------+ + | TDD_SYNC_EXT_CDC | --- | --- | --- | --- | --- | --- | --- | 0 | + +-------------------+----------+----------+--------+--------+--------+--------+-------+--------+ + | RX_KS_PER_CHANNEL | 16 | 32 | 64 | 64 | 64 | 16384 | --- | --- | + +-------------------+----------+----------+--------+--------+--------+--------+-------+--------+ + | TX_KS_PER_CHANNEL | 16 | 32 | 64 | 64 | 64 | 16384 | --- | --- | + +-------------------+----------+----------+--------+--------+--------+--------+-------+--------+ + | ADC_DO_MEM_TYPE | --- | --- | --- | --- | --- | 2 | --- | --- | + +-------------------+----------+----------+--------+--------+--------+--------+-------+--------+ + | DAC_DO_MEM_TYPE | --- | --- | --- | --- | --- | 2 | --- | --- | + +-------------------+----------+----------+--------+--------+--------+--------+-------+--------+ .. collapsible:: Default values of the ``make`` parameters for AD9082-FMCA-EBZ @@ -715,7 +737,7 @@ Systems related Here you can find the quick start guides available for these evaluation boards: .. list-table:: - :widths: 20 10 20 20 20 10 + :widths: 20 10 20 20 10 10 10 :header-rows: 1 * - Evaluation board @@ -724,12 +746,14 @@ Here you can find the quick start guides available for these evaluation boards: - Microblaze - Versal - Arria 10 + - FM87 * - AD9081/AD9082/AD9986/AD9988 - :dokuwiki:`ZC706 ` - :dokuwiki:`ZCU102 ` - :dokuwiki:`VCU118 ` - :dokuwiki:`VCK190/VMK180/VPK180 ` - :dokuwiki:`A10SoC ` + - :dokuwiki:`FM87 ` Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -810,3 +834,5 @@ Software related .. include:: ../common/support.rst .. _A10SoC: https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/arria/10-sx.html + +.. _FM87: https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/si-agi027.html diff --git a/library/intel/adi_jesd204/adi_jesd204_hw.tcl b/library/intel/adi_jesd204/adi_jesd204_hw.tcl index 41487aa700..34e1ade5f3 100644 --- a/library/intel/adi_jesd204/adi_jesd204_hw.tcl +++ b/library/intel/adi_jesd204/adi_jesd204_hw.tcl @@ -1,9 +1,10 @@ ############################################################################### -## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2016-2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIJESD204 ############################################################################### package require qsys 14.0 +package require quartus::device source ../../../scripts/adi_env.tcl source ../../scripts/adi_ip_intel.tcl @@ -276,9 +277,9 @@ proc jesd204_validate {{quiet false}} { set num_of_lanes [get_parameter_value "NUM_OF_LANES"] set tx_or_rx_n [get_parameter_value "TX_OR_RX_N"] - if {$device_family != "Arria 10" && $device_family != "Stratix 10"} { + if {$device_family != "Arria 10" && $device_family != "Stratix 10" && $device_family != "Agilex 7"} { if {!$quiet} { - send_message error "Only Arria 10 and Startix 10 are supported." + send_message error "Only Arria 10/Startix 10/Agilex 7 are supported." } return false } @@ -321,6 +322,8 @@ proc jesd204_compose {} { set input_pipeline [get_parameter_value "INPUT_PIPELINE_STAGES"] set tpl_data_path_width [get_parameter_value "TPL_DATA_PATH_WIDTH"] + set sip_tile [quartus::device::get_part_info -sip_tile $device] + set pllclk_frequency [expr $lane_rate / 2] set linkclk_frequency [expr $lane_rate / 40] set deviceclk_frequency [expr $linkclk_frequency * 4 / $tpl_data_path_width] @@ -339,11 +342,13 @@ proc jesd204_compose {} { add_interface sys_resetn reset sink set_interface_property sys_resetn EXPORT_OF sys_clock.clk_in_reset - add_instance ref_clock altera_clock_bridge - set_instance_parameter_value ref_clock {EXPLICIT_CLOCK_RATE} [expr $refclk_frequency*1000000] - set_instance_parameter_value ref_clock {NUM_CLOCK_OUTPUTS} 2 - add_interface ref_clk clock sink - set_interface_property ref_clk EXPORT_OF ref_clock.in_clk + if {$device_family == "Arria 10" || $device_family == "Stratix 10"} { + add_instance ref_clock altera_clock_bridge + set_instance_parameter_value ref_clock {EXPLICIT_CLOCK_RATE} [expr $refclk_frequency*1000000] + set_instance_parameter_value ref_clock {NUM_CLOCK_OUTPUTS} 2 + add_interface ref_clk clock sink + set_interface_property ref_clk EXPORT_OF ref_clock.in_clk + } set outclk_name "" @@ -392,6 +397,7 @@ proc jesd204_compose {} { set_instance_parameter_value link_pll {gui_desired_outclk1_frequency} $pfdclk_frequency set outclk_name "outclk0" + add_connection link_pll.$outclk_name link_clock.in_clk add_instance link_pll_reset_control altera_xcvr_reset_control set_instance_parameter_value link_pll_reset_control {SYNCHRONIZE_RESET} {0} @@ -405,7 +411,7 @@ proc jesd204_compose {} { add_connection sys_clock.clk_reset link_pll_reset_control.reset add_connection link_pll_reset_control.pll_powerdown link_pll.pll_powerdown - } elseif {$device_family == "Stratix 10"} { + } elseif {$device_family == "Stratix 10" && $sip_tile == "{H-Tile}"} { send_message info "Instantiate a fpll_s10_htile for link_pll." add_instance link_pll altera_xcvr_fpll_s10_htile @@ -423,26 +429,36 @@ proc jesd204_compose {} { set_instance_parameter_value link_pll {set_capability_reg_enable} {1} set outclk_name "outclk_div1" + add_connection link_pll.$outclk_name link_clock.in_clk + + } elseif {$device_family == "Stratix 10" && $sip_tile == "E-Tile"} { + + ## No fPLL here, PLL embedded in Native PHY + + } elseif {$device_family == "Agilex 7"} { + + ## No fPLL here, PLL embedded in Native PHY } else { - ## Unsupported device - send_message error "Only Arria 10 and Stratix 10 are supported." + ## Unsupported device + send_message error "Only Arria 10/Stratix 10/Agilex 7 are supported." } - add_connection link_pll.$outclk_name link_clock.in_clk add_interface link_clk clock source add_connection sys_clock.clk link_reset.clk add_interface link_reset reset source set_interface_property link_reset EXPORT_OF link_reset.out_reset_1 - set_instance_parameter_value link_pll {set_capability_reg_enable} {1} - set_instance_parameter_value link_pll {set_csr_soft_logic_enable} {1} - set_instance_parameter_value link_pll {rcfg_separate_avmm_busy} {1} - add_connection ref_clock.out_clk link_pll.pll_refclk0 + if {$device_family == "Arria 10" || $device_family == "Stratix 10"} { + set_instance_parameter_value link_pll {set_capability_reg_enable} {1} + set_instance_parameter_value link_pll {set_csr_soft_logic_enable} {1} + set_instance_parameter_value link_pll {rcfg_separate_avmm_busy} {1} + add_connection ref_clock.out_clk link_pll.pll_refclk0 - add_connection sys_clock.clk_reset link_pll.reconfig_reset0 - add_connection sys_clock.clk link_pll.reconfig_clk0 + add_connection sys_clock.clk_reset link_pll.reconfig_reset0 + add_connection sys_clock.clk link_pll.reconfig_clk0 + } add_instance axi_xcvr axi_adxcvr set_instance_parameter_value axi_xcvr {ID} $id @@ -452,18 +468,20 @@ proc jesd204_compose {} { add_connection sys_clock.clk axi_xcvr.s_axi_clock add_connection sys_clock.clk_reset axi_xcvr.s_axi_reset add_connection axi_xcvr.if_up_rst link_reset.in_reset - add_connection link_pll.pll_locked axi_xcvr.core_pll_locked add_interface link_management axi4lite slave set_interface_property link_management EXPORT_OF axi_xcvr.s_axi - add_interface link_pll_reconfig avalon slave - set_interface_property link_pll_reconfig EXPORT_OF link_pll.reconfig_avmm0 - set_interface_property link_pll_reconfig associatedClock sys_clk - set_interface_property link_pll_reconfig associatedReset sys_resetn + if {$device_family == "Arria 10" || $device_family == "Stratix 10"} { + add_connection link_pll.pll_locked axi_xcvr.core_pll_locked + add_interface link_pll_reconfig avalon slave + set_interface_property link_pll_reconfig EXPORT_OF link_pll.reconfig_avmm0 + set_interface_property link_pll_reconfig associatedClock sys_clk + set_interface_property link_pll_reconfig associatedReset sys_resetn - create_phy_reset_control $tx_or_rx_n $num_of_lanes $sysclk_frequency + create_phy_reset_control $tx_or_rx_n $num_of_lanes $sysclk_frequency + } add_instance phy jesd204_phy set_instance_parameter_value phy ID $id @@ -493,32 +511,60 @@ proc jesd204_compose {} { add_connection $link_clock phy.link_clk set_interface_property link_clk EXPORT_OF $device_clock_export - set phy_reset_intfs_s10 {analogreset_stat digitalreset_stat} + if {$device_family == "Arria 10" || $device_family == "Stratix 10"} { + if {$tx_or_rx_n} { + create_lane_pll $id $tx_or_rx_n $pllclk_frequency $refclk_frequency $num_of_lanes $bonding_clocks_en + if {$num_of_lanes > 6} { + if {$bonding_clocks_en} { + add_connection lane_pll.tx_bonding_clocks phy.bonding_clocks + } else { + add_connection lane_pll.tx_serial_clk phy.serial_clk_x1 + add_connection lane_pll.mcgb_serial_clk phy.serial_clk_xN + } + } else { + add_connection lane_pll.tx_serial_clk phy.serial_clk_x1 + } + } + } + + if {$device_family == "Arria 10" || $device_family == "Stratix 10"} { + # add_connection ref_clock.out_clk phy.ref_clk + + } elseif {$device_family == "Agilex 7"} { + add_connection phy.clkout link_clock.in_clk + + # PHY <-> AXI_XCVR + if {$tx_or_rx_n} { + add_connection axi_xcvr.core_pll_locked phy.pll_locked + } else { + add_connection axi_xcvr.rx_lockedtodata phy.rx_lockedtodata + } + add_connection axi_xcvr.ready phy.ready + add_connection axi_xcvr.reset phy.reset + add_connection axi_xcvr.reset_ack phy.reset_ack + + add_connection axi_xcvr.if_up_rst phy.link_reset + + ## Export ref clocks + add_interface ref_clk ftile_hssi_reference_clock sink + set_interface_property ref_clk EXPORT_OF phy.ref_clk + + } else { + ## Unsupported device + send_message error "Only Arria 10/Stratix 10/Agilex 7 are supported." + } if {$tx_or_rx_n} { - set tx_rx "tx" set data_direction sink set jesd204_intfs {config device_config control ilas_config device_event status} - set phy_reset_intfs {analogreset digitalreset cal_busy} - - create_lane_pll $id $tx_or_rx_n $pllclk_frequency $refclk_frequency $num_of_lanes $bonding_clocks_en - if {$num_of_lanes > 6} { - if {$bonding_clocks_en} { - add_connection lane_pll.tx_bonding_clocks phy.bonding_clocks - } else { - add_connection lane_pll.tx_serial_clk phy.serial_clk_x1 - add_connection lane_pll.mcgb_serial_clk phy.serial_clk_xN - } - } else { - add_connection lane_pll.tx_serial_clk phy.serial_clk_x1 - } + set tx_rx "tx" } else { - set tx_rx "rx" set data_direction source set jesd204_intfs {config device_config ilas_config device_event status} - set phy_reset_intfs {analogreset digitalreset cal_busy is_lockedtodata} - - add_connection ref_clock.out_clk phy.ref_clk + set tx_rx "rx" + if {$device_family == "Arria 10" || $device_family == "Stratix 10"} { + add_connection ref_clock.out_clk phy.ref_clk + } } add_instance axi_jesd204_${tx_rx} axi_jesd204_${tx_rx} @@ -531,6 +577,8 @@ proc jesd204_compose {} { set_instance_parameter_value jesd204_${tx_rx} {NUM_LANES} $num_of_lanes set_instance_parameter_value jesd204_${tx_rx} {ASYNC_CLK} $dual_clk_mode set_instance_parameter_value jesd204_${tx_rx} {TPL_DATA_PATH_WIDTH} $tpl_data_path_width + set_instance_parameter_value jesd204_${tx_rx} {LINK_MODE} 1; # 8B10B + add_connection $link_clock axi_jesd204_${tx_rx}.core_clock add_connection $device_clock axi_jesd204_${tx_rx}.device_clock @@ -545,16 +593,27 @@ proc jesd204_compose {} { add_connection axi_jesd204_${tx_rx}.${intf} jesd204_${tx_rx}.${intf} } - foreach intf $phy_reset_intfs { - add_connection phy_reset_control.${tx_rx}_${intf} phy.${intf} - } + if {$device_family == "Arria 10" || $device_family == "Stratix 10"} { + + set phy_reset_intfs_s10 {analogreset_stat digitalreset_stat} + + if {$tx_or_rx_n} { + set phy_reset_intfs {analogreset digitalreset cal_busy} + + } else { + set phy_reset_intfs {analogreset digitalreset cal_busy is_lockedtodata} + } - ## connect phy_reset_control interfaces specific to Stratix 10 - if {$device_family == "Stratix 10"} { - foreach intf $phy_reset_intfs_s10 { + foreach intf $phy_reset_intfs { add_connection phy_reset_control.${tx_rx}_${intf} phy.${intf} } + ## connect phy_reset_control interfaces specific to Stratix 10 + if {$device_family == "Stratix 10"} { + foreach intf $phy_reset_intfs_s10 { + add_connection phy_reset_control.${tx_rx}_${intf} phy.${intf} + } + } } set lane_map [regexp -all -inline {\S+} $lane_map] @@ -568,9 +627,14 @@ proc jesd204_compose {} { add_connection jesd204_${tx_rx}.${tx_rx}_phy${j} phy.phy_${i} } - for {set i 0} {$i < $num_of_lanes} {incr i} { - add_interface phy_reconfig_${i} avalon slave - set_interface_property phy_reconfig_${i} EXPORT_OF phy.reconfig_avmm_${i} + if {$device_family == "Arria 10" || $device_family == "Stratix 10"} { + for {set i 0} {$i < $num_of_lanes} {incr i} { + add_interface phy_reconfig_${i} avalon slave + set_interface_property phy_reconfig_${i} EXPORT_OF phy.reconfig_avmm_${i} + } + } elseif {$device_family == "Agilex 7"} { + add_interface phy_reconfig avalon slave + set_interface_property phy_reconfig EXPORT_OF phy.reconfig_avmm } add_interface interrupt interrupt end @@ -595,4 +659,8 @@ proc jesd204_compose {} { add_interface serial_data conduit end set_interface_property serial_data EXPORT_OF phy.serial_data + if {$device_family == "Agilex 7"} { + add_interface serial_data_n conduit end + set_interface_property serial_data_n EXPORT_OF phy.serial_data_n + } } diff --git a/library/intel/axi_adxcvr/axi_adxcvr.v b/library/intel/axi_adxcvr/axi_adxcvr.v index 9a44116329..51b193b0f4 100644 --- a/library/intel/axi_adxcvr/axi_adxcvr.v +++ b/library/intel/axi_adxcvr/axi_adxcvr.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -47,14 +47,20 @@ module axi_adxcvr #( parameter [15:0] FPGA_VOLTAGE = 0, parameter integer XCVR_TYPE = 0, parameter integer TX_OR_RX_N = 0, - parameter integer NUM_OF_LANES = 4 + parameter integer NUM_OF_LANES = 4, + parameter LOCKED_W = (FPGA_TECHNOLOGY == 105) ? NUM_OF_LANES : 1, + parameter READY_W = (FPGA_TECHNOLOGY != 105) ? NUM_OF_LANES : 1 ) ( // xcvr, lane-pll and ref-pll are shared output up_rst, - input up_pll_locked, - input [(NUM_OF_LANES-1):0] up_ready, + input [LOCKED_W-1 : 0] up_pll_locked, + input [NUM_OF_LANES-1:0] up_rx_lockedtodata, + input [READY_W-1 : 0] up_ready, + input [READY_W-1 : 0] up_reset_ack, + + output xcvr_reset, input s_axi_aclk, input s_axi_aresetn, @@ -97,6 +103,8 @@ module axi_adxcvr #( assign up_rstn = s_axi_aresetn; assign up_clk = s_axi_aclk; + assign xcvr_reset = up_rst; + // instantiations axi_adxcvr_up #( @@ -108,11 +116,14 @@ module axi_adxcvr #( .DEV_PACKAGE (DEV_PACKAGE), .FPGA_VOLTAGE (FPGA_VOLTAGE), .TX_OR_RX_N (TX_OR_RX_N), - .NUM_OF_LANES (NUM_OF_LANES) + .NUM_OF_LANES (NUM_OF_LANES), + .READY_W (READY_W) ) i_up ( .up_rst (up_rst), - .up_pll_locked (up_pll_locked), + .up_pll_locked (&up_pll_locked), + .up_rx_lockedtodata (&up_rx_lockedtodata), .up_ready (up_ready), + .up_reset_ack (up_reset_ack), .up_rstn (up_rstn), .up_clk (up_clk), .up_wreq (up_wreq), diff --git a/library/intel/axi_adxcvr/axi_adxcvr_hw.tcl b/library/intel/axi_adxcvr/axi_adxcvr_hw.tcl index 64e352a5dd..e621e85e09 100644 --- a/library/intel/axi_adxcvr/axi_adxcvr_hw.tcl +++ b/library/intel/axi_adxcvr/axi_adxcvr_hw.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2016-2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -60,24 +60,52 @@ ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 12 ad_interface reset up_rst output 1 s_axi_clock set_interface_property if_up_rst associatedResetSinks s_axi_reset -add_interface core_pll_locked conduit end -add_interface_port core_pll_locked up_pll_locked pll_locked Input 1 - # name changes proc p_axi_adxcvr {} { + set fpga_technology [get_parameter_value FPGA_TECHNOLOGY] set m_tx_or_rx_n [get_parameter_value TX_OR_RX_N] set m_num_of_lanes [get_parameter_value NUM_OF_LANES] - if {$m_tx_or_rx_n == 1} { - add_interface ready conduit end - add_interface_port ready up_ready tx_ready input $m_num_of_lanes + if {$m_tx_or_rx_n} { + set rx_tx "tx" + } else { + set rx_tx "rx" } - if {$m_tx_or_rx_n == 0} { + # 105 = Agilex, see adi_intel_device_info_enc.tcl + if {$fpga_technology == 105} { + add_interface core_pll_locked conduit end + add_interface_port core_pll_locked up_pll_locked ${rx_tx}_pll_locked Input $m_num_of_lanes + add_interface ready conduit end - add_interface_port ready up_ready rx_ready input $m_num_of_lanes + add_interface_port ready up_ready ${rx_tx}_ready input 1 + + add_interface reset conduit start + add_interface_port reset xcvr_reset ${rx_tx}_reset output 1 + + add_interface reset_ack conduit end + add_interface_port reset_ack up_reset_ack ${rx_tx}_reset_ack input 1 + + if {$m_tx_or_rx_n == 0} { + add_interface rx_lockedtodata conduit end + add_interface_port rx_lockedtodata up_rx_lockedtodata rx_is_lockedtodata input $m_num_of_lanes + } + + } else { + + add_interface core_pll_locked conduit end + add_interface_port core_pll_locked up_pll_locked pll_locked Input 1 + + if {$m_tx_or_rx_n == 1} { + add_interface ready conduit end + add_interface_port ready up_ready tx_ready input $m_num_of_lanes + } + + if {$m_tx_or_rx_n == 0} { + add_interface ready conduit end + add_interface_port ready up_ready rx_ready input $m_num_of_lanes + } } } - diff --git a/library/intel/axi_adxcvr/axi_adxcvr_up.v b/library/intel/axi_adxcvr/axi_adxcvr_up.v index c213b270868..203c693d8c 100644 --- a/library/intel/axi_adxcvr/axi_adxcvr_up.v +++ b/library/intel/axi_adxcvr/axi_adxcvr_up.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -47,14 +47,16 @@ module axi_adxcvr_up #( parameter [15:0] FPGA_VOLTAGE = 0, parameter integer XCVR_TYPE = 0, parameter integer TX_OR_RX_N = 0, - parameter integer NUM_OF_LANES = 4 + parameter integer NUM_OF_LANES = 4, + parameter READY_W = (FPGA_TECHNOLOGY != 105) ? NUM_OF_LANES : 1 ) ( - // xcvr, lane-pll and ref-pll are shared output up_rst, input up_pll_locked, - input [(NUM_OF_LANES-1):0] up_ready, + input up_rx_lockedtodata, + input [READY_W-1:0] up_ready, + input [READY_W-1:0] up_reset_ack, // bus interface @@ -118,11 +120,11 @@ module axi_adxcvr_up #( end end - assign up_rst = up_rst_cnt[3]; - assign up_ready_s = & up_status_32_s[NUM_OF_LANES:1]; + assign up_ready_s = & up_status_32_s[(NUM_OF_LANES-1):0]; assign up_status_32_s[31:(NUM_OF_LANES+1)] = 'd0; - assign up_status_32_s[NUM_OF_LANES] = up_pll_locked; - assign up_status_32_s[(NUM_OF_LANES-1):0] = up_ready; + assign up_status_32_s[NUM_OF_LANES] = FPGA_TECHNOLOGY == 105 ? TX_OR_RX_N ? up_pll_locked : up_rx_lockedtodata : + up_pll_locked; + assign up_status_32_s[(NUM_OF_LANES-1):0] = FPGA_TECHNOLOGY == 105 ? {NUM_OF_LANES{up_ready}} : up_ready; always @(negedge up_rstn or posedge up_clk) begin if (up_rstn == 0) begin @@ -142,6 +144,29 @@ module axi_adxcvr_up #( end end + generate if (FPGA_TECHNOLOGY == 105) begin + reg up_reset_ack_d = 'd0; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_reset_ack_d <= 1'b0; + end else begin + if (up_resetn == 1'b0) begin + up_reset_ack_d <= 1'b0; + end else begin + if (up_reset_ack_d == 1'b0) begin + up_reset_ack_d <= up_reset_ack; + end + end + end + end + + assign up_rst = ~up_reset_ack_d; + end else begin + assign up_rst = up_rst_cnt[3]; + end + endgenerate + // Specific to Intel assign up_rparam_s[31:28] = 8'd0; diff --git a/library/intel/jesd204_phy/Makefile b/library/intel/jesd204_phy/Makefile index 6e0ea83cb6..40ab75cde4 100644 --- a/library/intel/jesd204_phy/Makefile +++ b/library/intel/jesd204_phy/Makefile @@ -1,5 +1,5 @@ #################################################################################### -## Copyright (c) 2018 - 2023 Analog Devices, Inc. +## Copyright (c) 2018 - 2024 Analog Devices, Inc. ### SPDX short identifier: BSD-1-Clause ## Auto-generated, do not modify! #################################################################################### diff --git a/library/intel/jesd204_phy/jesd204_phy_glue_hw.tcl b/library/intel/jesd204_phy/jesd204_phy_glue_hw.tcl index 268a263091..9bd0fb7b18 100644 --- a/library/intel/jesd204_phy/jesd204_phy_glue_hw.tcl +++ b/library/intel/jesd204_phy/jesd204_phy_glue_hw.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2016-2022 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2016-2022, 2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIJESD204 ############################################################################### @@ -49,7 +49,7 @@ proc glue_add_if {num name type dir {bcast false}} { add_interface phy_${name} conduit end } -proc glue_add_if_port {num ifname port role dir width {bcast false}} { +proc glue_add_if_port {num ifname port role dir width {bcast false} {phy_role {}}} { variable sig_offset set phy_width [expr $num * $width] @@ -77,7 +77,15 @@ proc glue_add_if_port {num ifname port role dir width {bcast false}} { } } - add_interface_port phy_${ifname} phy_${port} $role $phy_dir $phy_width + set device [get_parameter DEVICE] + if {[string equal $device "Agilex 7"]} { + if {$phy_role == {}} { + set phy_role $port + } + add_interface_port phy_${ifname} phy_${port} $phy_role $phy_dir $phy_width + } else { + add_interface_port phy_${ifname} phy_${port} $role $phy_dir $phy_width + } if {$bcast} { set _frag [format "%s(%d:%d)" $phy_sig [expr $sig_offset + $width - 1] $sig_offset] @@ -196,46 +204,89 @@ proc jesd204_phy_glue_elab {} { set sig_offset 0 set const_offset 0 + set parallel_data_w 40 + if {[string equal $device "Arria 10"]} { set reconfig_avmm_address_width 10 set unused_width_per_lane 88 } elseif {[string equal $device "Stratix 10"]} { set reconfig_avmm_address_width 11 set unused_width_per_lane 40 + } elseif {[string equal $device "Agilex 7"]} { + set parallel_data_w 80 + set reconfig_avmm_address_width [expr 18 + int(ceil((log($num_of_lanes) / log(2))))] + # Unused are unused here + set unused_width_per_lane 88 } else { - send_message error "Only Arria 10 and Stratix 10 are supported." + send_message error "Only Arria 10/Stratix 10/Agilex 7 are supported." } - glue_add_if $num_of_lanes reconfig_clk clock sink true - glue_add_if_port $num_of_lanes reconfig_clk reconfig_clk clk Input 1 true + if {[string equal $device "Agilex 7"]} { + glue_add_if 1 reconfig_clk clock sink true + glue_add_if_port 1 reconfig_clk reconfig_clk clk Input 1 true clk + + glue_add_if 1 reconfig_reset reset sink true + glue_add_if_port 1 reconfig_reset reconfig_reset reset Input 1 true reset - glue_add_if $num_of_lanes reconfig_reset reset sink true - glue_add_if_port $num_of_lanes reconfig_reset reconfig_reset reset Input 1 true + glue_add_if 1 reconfig_avmm avalon sink true + set_interface_property reconfig_avmm associatedClock reconfig_clk + set_interface_property reconfig_avmm associatedReset reconfig_reset + + glue_add_if_port 1 reconfig_avmm reconfig_address address Input $reconfig_avmm_address_width true address + glue_add_if_port 1 reconfig_avmm reconfig_read read Input 1 true read + glue_add_if_port 1 reconfig_avmm reconfig_readdata readdata Output 32 true readdata + glue_add_if_port 1 reconfig_avmm reconfig_waitrequest waitrequest Output 1 true waitrequest + glue_add_if_port 1 reconfig_avmm reconfig_write write Input 1 true write + glue_add_if_port 1 reconfig_avmm reconfig_writedata writedata Input 32 true writedata + glue_add_if_port 1 reconfig_avmm reconfig_byteenable byteenable Input 4 true byteenable + + } else { + + glue_add_if $num_of_lanes reconfig_clk clock sink true + glue_add_if_port $num_of_lanes reconfig_clk reconfig_clk clk Input 1 true + + glue_add_if $num_of_lanes reconfig_reset reset sink true + glue_add_if_port $num_of_lanes reconfig_reset reconfig_reset reset Input 1 true + + glue_add_if $num_of_lanes reconfig_avmm avalon sink + for {set i 0} {$i < $num_of_lanes} {incr i} { + set_interface_property reconfig_avmm_${i} associatedClock reconfig_clk + set_interface_property reconfig_avmm_${i} associatedReset reconfig_reset + } + glue_add_if_port $num_of_lanes reconfig_avmm reconfig_address address Input $reconfig_avmm_address_width + glue_add_if_port $num_of_lanes reconfig_avmm reconfig_read read Input 1 + glue_add_if_port $num_of_lanes reconfig_avmm reconfig_readdata readdata Output 32 + glue_add_if_port $num_of_lanes reconfig_avmm reconfig_waitrequest waitrequest Output 1 + glue_add_if_port $num_of_lanes reconfig_avmm reconfig_write write Input 1 + glue_add_if_port $num_of_lanes reconfig_avmm reconfig_writedata writedata Input 32 - glue_add_if $num_of_lanes reconfig_avmm avalon sink - for {set i 0} {$i < $num_of_lanes} {incr i} { - set_interface_property reconfig_avmm_${i} associatedClock reconfig_clk - set_interface_property reconfig_avmm_${i} associatedReset reconfig_reset } - glue_add_if_port $num_of_lanes reconfig_avmm reconfig_address address Input $reconfig_avmm_address_width - glue_add_if_port $num_of_lanes reconfig_avmm reconfig_read read Input 1 - glue_add_if_port $num_of_lanes reconfig_avmm reconfig_readdata readdata Output 32 - glue_add_if_port $num_of_lanes reconfig_avmm reconfig_waitrequest waitrequest Output 1 - glue_add_if_port $num_of_lanes reconfig_avmm reconfig_write write Input 1 - glue_add_if_port $num_of_lanes reconfig_avmm reconfig_writedata writedata Input 32 + + set_interface_property reconfig_reset associatedClock reconfig_clk + set_interface_property reconfig_reset synchronousEdges DEASSERT if {[get_parameter TX_OR_RX_N]} { - glue_add_if $num_of_lanes tx_clkout clock source - glue_add_if_port $num_of_lanes tx_clkout tx_clkout clk Output 1 + glue_add_if $num_of_lanes tx_coreclkin clock sink true glue_add_if_port $num_of_lanes tx_coreclkin tx_coreclkin clk Input 1 true - if {$bonding_clocks_en && $num_of_lanes > 6} { - glue_add_if $num_of_lanes tx_bonding_clocks hssi_bonded_clock sink true - glue_add_if_port $num_of_lanes tx_bonding_clocks tx_bonding_clocks clk Input 6 true + if {[string equal $device "Agilex 7"]} { + glue_add_if $num_of_lanes ref_clk ftile_hssi_reference_clock sink true + glue_add_if_port $num_of_lanes ref_clk ref_clk clk Input 1 true clk + + glue_add_if $num_of_lanes tx_clkout2 clock source + glue_add_if_port $num_of_lanes tx_clkout2 tx_clkout2 clk Output 1 } else { - glue_add_tx_serial_clk $num_of_lanes + glue_add_if $num_of_lanes tx_clkout clock source + glue_add_if_port $num_of_lanes tx_clkout tx_clkout clk Output 1 + + if {$bonding_clocks_en && $num_of_lanes > 6} { + glue_add_if $num_of_lanes tx_bonding_clocks hssi_bonded_clock sink true + glue_add_if_port $num_of_lanes tx_bonding_clocks tx_bonding_clocks clk Input 6 true + } else { + glue_add_tx_serial_clk $num_of_lanes + } } if {$soft_pcs} { @@ -246,7 +297,7 @@ proc jesd204_phy_glue_elab {} { for {set i 0} {$i < $num_of_lanes} {incr i} { add_interface tx_raw_data_${i} conduit start } - glue_add_if_port_conduit $num_of_lanes tx_raw_data raw_data tx_parallel_data Input 40 + glue_add_if_port_conduit $num_of_lanes tx_raw_data raw_data tx_parallel_data Input $parallel_data_w } else { set unused_width [expr $num_of_lanes * 92] @@ -263,20 +314,29 @@ proc jesd204_phy_glue_elab {} { add_interface_port phy_tx_polinv polinv tx_polinv Output $num_of_lanes set_port_property polinv TERMINATION $soft_pcs } else { - glue_add_if 1 rx_cdr_refclk0 clock sink true - glue_add_if_port 1 rx_cdr_refclk0 rx_cdr_refclk0 clk Input 1 true glue_add_if $num_of_lanes rx_coreclkin clock sink true glue_add_if_port $num_of_lanes rx_coreclkin rx_coreclkin clk Input 1 true - glue_add_if $num_of_lanes rx_clkout clock source - glue_add_if_port $num_of_lanes rx_clkout rx_clkout clk Output 1 + if {[string equal $device "Agilex 7"]} { + glue_add_if $num_of_lanes ref_clk ftile_hssi_reference_clock sink true + glue_add_if_port $num_of_lanes ref_clk ref_clk clk Input 1 true clk + + glue_add_if $num_of_lanes rx_clkout2 clock source + glue_add_if_port $num_of_lanes rx_clkout2 rx_clkout2 clk Output 1 + } else { + glue_add_if 1 rx_cdr_refclk0 clock sink true + glue_add_if_port 1 rx_cdr_refclk0 rx_cdr_refclk0 clk Input 1 true + + glue_add_if $num_of_lanes rx_clkout clock source + glue_add_if_port $num_of_lanes rx_clkout rx_clkout clk Output 1 + } if {$soft_pcs} { for {set i 0} {$i < $num_of_lanes} {incr i} { add_interface rx_raw_data_${i} conduit start } - glue_add_if_port_conduit $num_of_lanes rx_raw_data raw_data rx_parallel_data Output 40 + glue_add_if_port_conduit $num_of_lanes rx_raw_data raw_data rx_parallel_data Output $parallel_data_w } else { for {set i 0} {$i < $num_of_lanes} {incr i} { add_interface rx_phy_${i} conduit start @@ -298,9 +358,6 @@ proc jesd204_phy_glue_elab {} { set_port_property polinv TERMINATION $soft_pcs } - set_interface_property reconfig_reset associatedClock reconfig_clk - set_interface_property reconfig_reset synchronousEdges DEASSERT - set_parameter_value WIDTH $sig_offset set_parameter_value CONST_WIDTH $const_offset } diff --git a/library/intel/jesd204_phy/jesd204_phy_hw.tcl b/library/intel/jesd204_phy/jesd204_phy_hw.tcl index b4c37e6a1c..ef8a7c3ccb 100644 --- a/library/intel/jesd204_phy/jesd204_phy_hw.tcl +++ b/library/intel/jesd204_phy/jesd204_phy_hw.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2016-2022 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2016-2022, 2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIJESD204 ############################################################################### @@ -33,6 +33,14 @@ ad_ip_parameter REGISTER_INPUTS INTEGER 0 false ad_ip_parameter LANE_INVERT INTEGER 0 false ad_ip_parameter BONDING_CLOCKS_EN BOOLEAN false false +proc log2 {x} { + expr (log($x) / log(2)) +} + +#proc log2 {x} { +# return [tcl::mathfunc::int [tcl::mathfunc::ceil [expr [tcl::mathfunc::log $x] / [tcl::mathfunc::log 2]]]] +#} + proc jesd204_phy_composition_callback {} { set device [get_parameter_value "DEVICE"] @@ -52,6 +60,8 @@ proc jesd204_phy_composition_callback {} { set device_type 1 } elseif {[string equal $device "Stratix 10"]} { set device_type 2 + } elseif {[string equal $device "Agilex 7"]} { + set device_type 3 } else { set device_type 0 } @@ -75,66 +85,109 @@ proc jesd204_phy_composition_callback {} { add_instance native_phy altera_xcvr_native_s10_htile set_instance_parameter_value native_phy {tx_fifo_mode} "Phase compensation" set_instance_parameter_value native_phy {rx_fifo_mode} "Phase compensation" + ## Agilex F-Tile + } elseif {$device_type == 3} { + add_instance native_phy directphy_f + set_instance_parameter_value native_phy xcvr_type "FGT" + set_instance_parameter_value native_phy num_xcvr_per_sys $num_of_lanes + set_instance_parameter_value native_phy clocking_mode "xcvr" + set_instance_parameter_value native_phy pma_modulation "NRZ" + set_instance_parameter_value native_phy pma_data_rate $lane_rate + set_instance_parameter_value native_phy pma_width 20 + set_instance_parameter_value native_phy rx_deskew_en 0 + ## Unsupported device } else { - send_message error "Only Arria 10 and Stratix 10 are supported." + send_message error "Only Arria 10/Stratix 10/Agilex 7 are supported." } - if {$soft_pcs} { - set_instance_parameter_value native_phy {protocol_mode} "basic_enh" + # Common paramters to all PHYs + if {$tx} { + set tx_rx "tx" } else { - set_instance_parameter_value native_phy {protocol_mode} "basic_std" - set_instance_parameter_value native_phy {std_pcs_pma_width} 20 + set tx_rx "rx" + } + set_instance_parameter_value native_phy {duplex_mode} $tx_rx + + if {$device_type == 1 || $device_type == 2} { + if {$soft_pcs} { + set_instance_parameter_value native_phy {protocol_mode} "basic_enh" + } else { + set_instance_parameter_value native_phy {protocol_mode} "basic_std" + set_instance_parameter_value native_phy {std_pcs_pma_width} 20 + + if {$tx} { + set_instance_parameter_value native_phy {std_tx_byte_ser_mode} "Serialize x2" + set_instance_parameter_value native_phy {std_tx_8b10b_enable} 1 + set_instance_parameter_value native_phy {std_tx_polinv_enable} 1 + set_instance_parameter_value native_phy {enable_port_tx_polinv} 1 + } else { + set_instance_parameter_value native_phy {std_rx_byte_deser_mode} "Deserialize x2" + set_instance_parameter_value native_phy {std_rx_8b10b_enable} 1 + set_instance_parameter_value native_phy {std_rx_word_aligner_mode} "manual (PLD controlled)" + set_instance_parameter_value native_phy {std_rx_word_aligner_pattern_len} 20 + set_instance_parameter_value native_phy {std_rx_word_aligner_pattern} 0xA0D7C + set_instance_parameter_value native_phy {enable_port_rx_std_wa_patternalign} 1 + set_instance_parameter_value native_phy {std_rx_polinv_enable} 1 + set_instance_parameter_value native_phy {enable_port_rx_polinv} 1 + } + } if {$tx} { - set_instance_parameter_value native_phy {std_tx_byte_ser_mode} "Serialize x2" - set_instance_parameter_value native_phy {std_tx_8b10b_enable} 1 - set_instance_parameter_value native_phy {std_tx_polinv_enable} 1 - set_instance_parameter_value native_phy {enable_port_tx_polinv} 1 + if {$bonding_clocks_en && $num_of_lanes > 6} { + set_instance_parameter_value native_phy {bonded_mode} "pma_only" + } else { + set_instance_parameter_value native_phy {bonded_mode} "not_bonded" + } + set_instance_parameter_value native_phy {enable_port_tx_pma_elecidle} 0 } else { - set_instance_parameter_value native_phy {std_rx_byte_deser_mode} "Deserialize x2" - set_instance_parameter_value native_phy {std_rx_8b10b_enable} 1 - set_instance_parameter_value native_phy {std_rx_word_aligner_mode} "manual (PLD controlled)" - set_instance_parameter_value native_phy {std_rx_word_aligner_pattern_len} 20 - set_instance_parameter_value native_phy {std_rx_word_aligner_pattern} 0xA0D7C - set_instance_parameter_value native_phy {enable_port_rx_std_wa_patternalign} 1 - set_instance_parameter_value native_phy {std_rx_polinv_enable} 1 - set_instance_parameter_value native_phy {enable_port_rx_polinv} 1 + set_instance_parameter_value native_phy {set_cdr_refclk_freq} $refclk_frequency + set_instance_parameter_value native_phy {enable_port_rx_is_lockedtodata} 1 + set_instance_parameter_value native_phy {enable_port_rx_is_lockedtoref} 0 + set_instance_parameter_value native_phy {enable_ports_rx_manual_cdr_mode} 0 } - } - if {$tx} { - set_instance_parameter_value native_phy {duplex_mode} "tx" - if {$bonding_clocks_en && $num_of_lanes > 6} { - set_instance_parameter_value native_phy {bonded_mode} "pma_only" + set_instance_parameter_value native_phy {channels} $num_of_lanes + set_instance_parameter_value native_phy {set_data_rate} $lane_rate + set_instance_parameter_value native_phy {enable_simple_interface} 1 + set_instance_parameter_value native_phy {enh_pcs_pma_width} 40 + set_instance_parameter_value native_phy {enh_pld_pcs_width} 40 + set_instance_parameter_value native_phy {rcfg_enable} 1 + set_instance_parameter_value native_phy {rcfg_shared} 0 + set_instance_parameter_value native_phy {rcfg_jtag_enable} 0 + set_instance_parameter_value native_phy {rcfg_sv_file_enable} 0 + set_instance_parameter_value native_phy {rcfg_h_file_enable} 0 + set_instance_parameter_value native_phy {rcfg_mif_file_enable} 0 + set_instance_parameter_value native_phy {set_user_identifier} $id + set_instance_parameter_value native_phy {set_capability_reg_enable} 1 + set_instance_parameter_value native_phy {set_csr_soft_logic_enable} 1 + set_instance_parameter_value native_phy {set_prbs_soft_logic_enable} 0 + + } elseif {$device_type == 3} { + if {$tx} { + set_instance_parameter_value native_phy fgt_tx_pll_refclk_freq_mhz [format {%.6f} $refclk_frequency] + set_instance_parameter_value native_phy pmaif_tx_fifo_mode_s "phase_comp" + set_instance_parameter_value native_phy pldif_tx_double_width_transfer_enable 1 + set_instance_parameter_value native_phy pldif_tx_fifo_mode "phase_comp" + set_instance_parameter_value native_phy pldif_tile_tx_fifo_mode "phase_comp" + set_instance_parameter_value native_phy pldif_tx_fifo_pfull_thld 10 + set_instance_parameter_value native_phy enable_port_tx_clkout2 1 + set_instance_parameter_value native_phy pldif_tx_clkout2_sel "TX_WORD_CLK" + set_instance_parameter_value native_phy pldif_tx_clkout2_div 2 + set_instance_parameter_value native_phy avmm2_enable 1 + #set_instance_parameter_value native_phy avmm2_split [expr $num_of_lanes > 1] + #set_instance_parameter_value native_phy avmm2_split 1 } else { - set_instance_parameter_value native_phy {bonded_mode} "not_bonded" + set_instance_parameter_value native_phy fgt_rx_pll_refclk_freq_mhz [format {%.6f} $refclk_frequency] + set_instance_parameter_value native_phy pmaif_rx_fifo_mode_s "register" + set_instance_parameter_value native_phy pldif_rx_double_width_transfer_enable 1 + set_instance_parameter_value native_phy enable_port_rx_clkout2 1 + set_instance_parameter_value native_phy pldif_rx_clkout2_sel "RX_WORD_CLK" + set_instance_parameter_value native_phy pldif_rx_clkout2_div 2 + set_instance_parameter_value native_phy avmm2_enable 1 } - set_instance_parameter_value native_phy {enable_port_tx_pma_elecidle} 0 - } else { - set_instance_parameter_value native_phy {duplex_mode} "rx" - set_instance_parameter_value native_phy {set_cdr_refclk_freq} $refclk_frequency - set_instance_parameter_value native_phy {enable_port_rx_is_lockedtodata} 1 - set_instance_parameter_value native_phy {enable_port_rx_is_lockedtoref} 0 - set_instance_parameter_value native_phy {enable_ports_rx_manual_cdr_mode} 0 } - set_instance_parameter_value native_phy {channels} $num_of_lanes - set_instance_parameter_value native_phy {set_data_rate} $lane_rate - set_instance_parameter_value native_phy {enable_simple_interface} 1 - set_instance_parameter_value native_phy {enh_pcs_pma_width} 40 - set_instance_parameter_value native_phy {enh_pld_pcs_width} 40 - set_instance_parameter_value native_phy {rcfg_enable} 1 - set_instance_parameter_value native_phy {rcfg_shared} 0 - set_instance_parameter_value native_phy {rcfg_jtag_enable} 0 - set_instance_parameter_value native_phy {rcfg_sv_file_enable} 0 - set_instance_parameter_value native_phy {rcfg_h_file_enable} 0 - set_instance_parameter_value native_phy {rcfg_mif_file_enable} 0 - set_instance_parameter_value native_phy {set_user_identifier} $id - set_instance_parameter_value native_phy {set_capability_reg_enable} 1 - set_instance_parameter_value native_phy {set_csr_soft_logic_enable} 1 - set_instance_parameter_value native_phy {set_prbs_soft_logic_enable} 0 - add_instance phy_glue jesd204_phy_glue set_instance_parameter_value phy_glue DEVICE $device set_instance_parameter_value phy_glue TX_OR_RX_N $tx @@ -149,107 +202,199 @@ proc jesd204_phy_composition_callback {} { add_interface reconfig_reset reset sink set_interface_property reconfig_reset EXPORT_OF phy_glue.reconfig_reset + # Connect PHY with GLUE + if {$device_type == 1 || $device_type == 2} { + + if {$tx} { + if {$bonding_clocks_en && $num_of_lanes > 6} { + add_interface bonding_clocks hssi_bonded_clock end + set_interface_property bonding_clocks EXPORT_OF phy_glue.tx_bonding_clocks + add_connection phy_glue.phy_tx_bonding_clocks native_phy.tx_bonding_clocks + } else { + add_interface serial_clk_x1 hssi_serial_clock end + set_interface_property serial_clk_x1 EXPORT_OF phy_glue.tx_serial_clk_x1 + if {$num_of_lanes > 6} { + add_interface serial_clk_xN hssi_serial_clock end + set_interface_property serial_clk_xN EXPORT_OF phy_glue.tx_serial_clk_xN + } + add_connection phy_glue.phy_tx_serial_clk0 native_phy.tx_serial_clk0 + } + + add_connection link_clock.clk phy_glue.tx_coreclkin + + if { $soft_pcs == true && $device_type == 1 } { + add_connection phy_glue.phy_tx_enh_data_valid native_phy.tx_enh_data_valid + } + + foreach x {reconfig_clk reconfig_reset reconfig_avmm tx_coreclkin \ + tx_clkout tx_parallel_data unused_tx_parallel_data} { + add_connection phy_glue.phy_${x} native_phy.${x} + } + + foreach x {serial_data analogreset digitalreset cal_busy} { + add_interface ${x} conduit end + set_interface_property ${x} EXPORT_OF native_phy.tx_${x} + } + + if {$soft_pcs == false} { + add_connection phy_glue.phy_tx_datak native_phy.tx_datak + add_connection phy_glue.phy_tx_polinv native_phy.tx_polinv + } + + ## Startix 10 + if {$device_type == 2} { + foreach x {analogreset_stat digitalreset_stat} { + add_interface ${x} conduit end + set_interface_property ${x} EXPORT_OF native_phy.tx_${x} + } + } - if {$tx} { - if {$bonding_clocks_en && $num_of_lanes > 6} { - add_interface bonding_clocks hssi_bonded_clock end - set_interface_property bonding_clocks EXPORT_OF phy_glue.tx_bonding_clocks - add_connection phy_glue.phy_tx_bonding_clocks native_phy.tx_bonding_clocks } else { - add_interface serial_clk_x1 hssi_serial_clock end - set_interface_property serial_clk_x1 EXPORT_OF phy_glue.tx_serial_clk_x1 - if {$num_of_lanes > 6} { - add_interface serial_clk_xN hssi_serial_clock end - set_interface_property serial_clk_xN EXPORT_OF phy_glue.tx_serial_clk_xN + + add_interface ref_clk clock sink + set_interface_property ref_clk EXPORT_OF phy_glue.rx_cdr_refclk0 + + add_connection link_clock.clk phy_glue.rx_coreclkin + + foreach x {serial_data analogreset digitalreset cal_busy is_lockedtodata} { + add_interface ${x} conduit end + set_interface_property ${x} EXPORT_OF native_phy.rx_${x} + } + + foreach x {reconfig_clk reconfig_reset reconfig_avmm rx_coreclkin \ + rx_clkout rx_parallel_data rx_cdr_refclk0} { + add_connection phy_glue.phy_${x} native_phy.${x} + } + + if {$soft_pcs == false} { + foreach x {rx_datak rx_disperr rx_errdetect rx_std_wa_patternalign} { + add_connection phy_glue.phy_${x} native_phy.${x} } - add_connection phy_glue.phy_tx_serial_clk0 native_phy.tx_serial_clk0 - } + add_connection phy_glue.phy_rx_polinv native_phy.rx_polinv + } - add_connection link_clock.clk phy_glue.tx_coreclkin + ## Startix 10 + if {$device_type == 2} { + foreach x {analogreset_stat digitalreset_stat} { + add_interface ${x} conduit end + set_interface_property ${x} EXPORT_OF native_phy.rx_${x} + } + } - if { $soft_pcs == true && $device_type == 1 } { - add_connection phy_glue.phy_tx_enh_data_valid native_phy.tx_enh_data_valid } - foreach x {reconfig_clk reconfig_reset reconfig_avmm tx_coreclkin \ - tx_clkout tx_parallel_data unused_tx_parallel_data} { - add_connection phy_glue.phy_${x} native_phy.${x} + # Connect GLUE with PCS + for {set i 0} {$i < $num_of_lanes} {incr i} { + add_interface reconfig_avmm_${i} avalon slave + set_interface_property reconfig_avmm_${i} EXPORT_OF phy_glue.reconfig_avmm_${i} + + add_interface phy_${i} conduit start + + if {$tx} { + if {$soft_pcs} { + add_instance soft_pcs_${i} jesd204_soft_pcs_tx + set_instance_parameter_value soft_pcs_${i} INVERT_OUTPUTS \ + [expr ($lane_invert >> $i) & 1] + add_connection link_clock.clk soft_pcs_${i}.clock + add_connection link_clock.clk_reset soft_pcs_${i}.reset + add_connection soft_pcs_${i}.tx_raw_data phy_glue.tx_raw_data_${i} + + set_interface_property phy_${i} EXPORT_OF soft_pcs_${i}.tx_phy + } else { + set_interface_property phy_${i} EXPORT_OF phy_glue.tx_phy_${i} + } + } else { + if {$soft_pcs} { + add_instance soft_pcs_${i} jesd204_soft_pcs_rx + set_instance_parameter_value soft_pcs_${i} REGISTER_INPUTS $register_inputs + set_instance_parameter_value soft_pcs_${i} INVERT_INPUTS \ + [expr ($lane_invert >> $i) & 1] + add_connection link_clock.clk soft_pcs_${i}.clock + add_connection link_clock.clk_reset soft_pcs_${i}.reset + add_connection phy_glue.rx_raw_data_${i} soft_pcs_${i}.rx_raw_data + + set_interface_property phy_${i} EXPORT_OF soft_pcs_${i}.rx_phy + } else { + set_interface_property phy_${i} EXPORT_OF phy_glue.rx_phy_${i} + } + } } - foreach x {serial_data analogreset digitalreset cal_busy} { + # Agilex + } elseif {$device_type == 3} { + + add_interface ref_clk ftile_hssi_reference_clock end + set_interface_property ref_clk EXPORT_OF phy_glue.ref_clk + + # export ${tx_rx}_reset, ${tx_rx}_ready, ${tx_rx}_reset_ack + # This conects to axi_xcvr + foreach x {reset reset_ack ready} { add_interface ${x} conduit end - set_interface_property ${x} EXPORT_OF native_phy.tx_${x} + set_interface_property ${x} EXPORT_OF native_phy.${tx_rx}_${x} } - if {$soft_pcs == false} { - add_connection phy_glue.phy_tx_datak native_phy.tx_datak - add_connection phy_glue.phy_tx_polinv native_phy.tx_polinv + if {$tx} { + add_interface pll_locked conduit end + set_interface_property pll_locked EXPORT_OF native_phy.tx_pll_locked + } else { + add_interface rx_lockedtodata conduit end + set_interface_property rx_lockedtodata EXPORT_OF native_phy.rx_is_lockedtodata } - ## Startix 10 - if {$device_type == 2} { - foreach x {analogreset_stat digitalreset_stat} { - add_interface ${x} conduit end - set_interface_property ${x} EXPORT_OF native_phy.tx_${x} - } + # export ${tx_rx}_serial_data, ${tx_rx}_serial_data_n + foreach x {serial_data serial_data_n} { + add_interface ${x} conduit end + set_interface_property ${x} EXPORT_OF native_phy.${tx_rx}_${x} } - } else { + # connect link clock and output clock from - to GLUE - add_interface ref_clk clock sink - set_interface_property ref_clk EXPORT_OF phy_glue.rx_cdr_refclk0 + add_connection link_clock.clk phy_glue.${tx_rx}_coreclkin + add_connection phy_glue.phy_${tx_rx}_coreclkin native_phy.${tx_rx}_coreclkin - add_connection link_clock.clk phy_glue.rx_coreclkin + # Reconfig interface + add_connection phy_glue.phy_reconfig_clk native_phy.reconfig_xcvr_clk + add_connection phy_glue.phy_reconfig_reset native_phy.reconfig_xcvr_reset + add_connection phy_glue.phy_reconfig_avmm native_phy.reconfig_xcvr_avmm - foreach x {serial_data analogreset digitalreset cal_busy is_lockedtodata} { - add_interface ${x} conduit end - set_interface_property ${x} EXPORT_OF native_phy.rx_${x} - } + add_interface reconfig_avmm avalon slave + set_interface_property reconfig_avmm EXPORT_OF phy_glue.reconfig_avmm - foreach x {reconfig_clk reconfig_reset reconfig_avmm rx_coreclkin \ - rx_clkout rx_parallel_data rx_cdr_refclk0} { - add_connection phy_glue.phy_${x} native_phy.${x} - } - - if {$soft_pcs == false} { - foreach x {rx_datak rx_disperr rx_errdetect rx_std_wa_patternalign} { - add_connection phy_glue.phy_${x} native_phy.${x} - } - add_connection phy_glue.phy_rx_polinv native_phy.rx_polinv + # connect ref clock and output clock from - to GLUE + # tx_pll_refclk_link + if {$tx} { + set tx_rx_ref_name "pll" + } else { + set tx_rx_ref_name "cdr" } + add_connection phy_glue.phy_ref_clk native_phy.${tx_rx}_${tx_rx_ref_name}_refclk_link - ## Startix 10 - if {$device_type == 2} { - foreach x {analogreset_stat digitalreset_stat} { - add_interface ${x} conduit end - set_interface_property ${x} EXPORT_OF native_phy.rx_${x} - } + foreach x [list ${tx_rx}_parallel_data ${tx_rx}_clkout2] { + add_connection phy_glue.phy_${x} native_phy.${x} } - } + # This is lane rate / 40 + add_interface clkout clock source + set_interface_property clkout EXPORT_OF phy_glue.${tx_rx}_clkout2_0 - for {set i 0} {$i < $num_of_lanes} {incr i} { - add_interface reconfig_avmm_${i} avalon slave - set_interface_property reconfig_avmm_${i} EXPORT_OF phy_glue.reconfig_avmm_${i} + # Connect GLUE with PCS + for {set i 0} {$i < $num_of_lanes} {incr i} { - add_interface phy_${i} conduit start + add_interface phy_${i} conduit start - if {$tx} { - if {$soft_pcs} { + if {$tx} { add_instance soft_pcs_${i} jesd204_soft_pcs_tx + set_instance_parameter_value soft_pcs_${i} IFC_TYPE 1 set_instance_parameter_value soft_pcs_${i} INVERT_OUTPUTS \ [expr ($lane_invert >> $i) & 1] add_connection link_clock.clk soft_pcs_${i}.clock add_connection link_clock.clk_reset soft_pcs_${i}.reset - add_connection soft_pcs_${i}.tx_raw_data phy_glue.tx_raw_data_${i} + add_connection phy_glue.tx_raw_data_${i} soft_pcs_${i}.tx_raw_data set_interface_property phy_${i} EXPORT_OF soft_pcs_${i}.tx_phy } else { - set_interface_property phy_${i} EXPORT_OF phy_glue.tx_phy_${i} - } - } else { - if {$soft_pcs} { add_instance soft_pcs_${i} jesd204_soft_pcs_rx + set_instance_parameter_value soft_pcs_${i} IFC_TYPE 1 set_instance_parameter_value soft_pcs_${i} REGISTER_INPUTS $register_inputs set_instance_parameter_value soft_pcs_${i} INVERT_INPUTS \ [expr ($lane_invert >> $i) & 1] @@ -258,9 +403,8 @@ proc jesd204_phy_composition_callback {} { add_connection phy_glue.rx_raw_data_${i} soft_pcs_${i}.rx_raw_data set_interface_property phy_${i} EXPORT_OF soft_pcs_${i}.rx_phy - } else { - set_interface_property phy_${i} EXPORT_OF phy_glue.rx_phy_${i} } } } + } diff --git a/library/jesd204/jesd204_rx/jesd204_rx_hw.tcl b/library/jesd204/jesd204_rx/jesd204_rx_hw.tcl index 4186ddb13b..4bb7d94d21 100755 --- a/library/jesd204/jesd204_rx/jesd204_rx_hw.tcl +++ b/library/jesd204/jesd204_rx/jesd204_rx_hw.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2017-2022, 2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIJESD204 ############################################################################### @@ -22,7 +22,10 @@ ad_ip_files jesd204_rx [list \ jesd204_lane_latency_monitor.v \ jesd204_rx_cgs.v \ jesd204_rx_ctrl.v \ + jesd204_rx_ctrl_64b.v \ jesd204_rx_lane.v \ + jesd204_rx_lane_64b.v \ + jesd204_rx_header.v \ jesd204_rx_frame_align.v \ jesd204_rx_constr.sdc \ ../jesd204_common/jesd204_eof_generator.v \ @@ -40,6 +43,11 @@ ad_ip_files jesd204_rx [list \ ] # parameters +ad_ip_parameter LINK_MODE INTEGER 1 true { \ + DISPLAY_NAME "Link Layer mode" \ + ALLOWED_RANGES {"1:8B10B" "2:64B66B"} \ + HDL_PARAMETER true \ +} add_parameter NUM_LANES INTEGER 1 set_parameter_property NUM_LANES DISPLAY_NAME "Number of Lanes" @@ -60,6 +68,12 @@ add_parameter ASYNC_CLK BOOLEAN false set_parameter_property ASYNC_CLK DISPLAY_NAME "Link and device clock asynchronous" set_parameter_property ASYNC_CLK HDL_PARAMETER true +ad_ip_parameter DATA_PATH_WIDTH INTEGER 4 true { \ + DISPLAY_NAME "Physical layer datapath widthin" \ + DISPLAY_UNITS "octets" \ + ALLOWED_RANGES {4 8} \ +} + ad_ip_parameter TPL_DATA_PATH_WIDTH INTEGER 4 true { \ DISPLAY_NAME "Transport layer datapath width" \ DISPLAY_UNITS "octets" \ @@ -210,6 +224,7 @@ set_port_property lmfc_edge TERMINATION TRUE proc jesd204_rx_elaboration_callback {} { set num_lanes [get_parameter_value "NUM_LANES"] set tpl_width [get_parameter_value "TPL_DATA_PATH_WIDTH"] + set phy_width [get_parameter_value "DATA_PATH_WIDTH"] # rx_data interface @@ -224,21 +239,36 @@ proc jesd204_rx_elaboration_callback {} { for {set i 0 } {$i < $num_lanes} {incr i} { add_interface rx_phy${i} conduit end -# set_interface_property rx_phy${i} associatedClock clock -# set_interface_property rx_phy${i} associatedReset reset - add_interface_port rx_phy${i} rx_phy${i}_data char Input 32 + + add_interface_port rx_phy${i} rx_phy${i}_data char Input [expr 8*$phy_width] set_port_property rx_phy${i}_data fragment_list \ - [format "phy_data(%d:%d)" [expr 32*$i+31] [expr 32*$i]] - add_interface_port rx_phy${i} rx_phy${i}_charisk charisk Input 4 - set_port_property rx_phy${i}_charisk fragment_list \ - [format "phy_charisk(%d:%d)" [expr 4*$i+3] [expr 4*$i]] - add_interface_port rx_phy${i} rx_phy${i}_disperr disperr Input 4 - set_port_property rx_phy${i}_disperr fragment_list \ - [format "phy_disperr(%d:%d)" [expr 4*$i+3] [expr 4*$i]] - add_interface_port rx_phy${i} rx_phy${i}_notintable notintable Input 4 - set_port_property rx_phy${i}_notintable fragment_list \ - [format "phy_notintable(%d:%d)" [expr 4*$i+3] [expr 4*$i]] - add_interface_port rx_phy${i} rx_phy${i}_patternalign_en patternalign_en Output 1 - set_port_property rx_phy${i}_patternalign_en fragment_list "phy_en_char_align" + [format "phy_data(%d:%d)" [expr (8*$phy_width)*($i+1)-1] [expr 8*$phy_width*$i]] + + if {[get_parameter_value "LINK_MODE"]==1} { + add_interface_port rx_phy${i} rx_phy${i}_charisk charisk Input $phy_width + set_port_property rx_phy${i}_charisk fragment_list \ + [format "phy_charisk(%d:%d)" [expr $phy_width*($i+1)-1] [expr $phy_width*$i]] + + add_interface_port rx_phy${i} rx_phy${i}_disperr disperr Input $phy_width + set_port_property rx_phy${i}_disperr fragment_list \ + [format "phy_disperr(%d:%d)" [expr $phy_width*($i+1)-1] [expr $phy_width*$i]] + + add_interface_port rx_phy${i} rx_phy${i}_notintable notintable Input $phy_width + set_port_property rx_phy${i}_notintable fragment_list \ + [format "phy_notintable(%d:%d)" [expr $phy_width*($i+1)-1] [expr $phy_width*$i]] + + add_interface_port rx_phy${i} rx_phy${i}_patternalign_en patternalign_en Output 1 + set_port_property rx_phy${i}_patternalign_en fragment_list "phy_en_char_align" + } + + if {[get_parameter_value "LINK_MODE"]==2} { + add_interface_port rx_phy${i} rx_phy${i}_header header Input 2 + set_port_property rx_phy${i}_header fragment_list \ + [format "phy_header(%d:%d)" [expr 2*($i+1)-1] [expr 2*$i]] + + add_interface_port rx_phy${i} rx_phy${i}_block_sync block_sync Input 1 + set_port_property rx_phy${i}_block_sync fragment_list \ + [format "phy_header(%d:%d)" [expr 1*($i+1)-1] [expr 1*$i]] + } } } diff --git a/library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v b/library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v index 2da67b43b8..ae0240c881 100644 --- a/library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v +++ b/library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017, 2018, 2020, 2022, 2024 Analog Devices, Inc. All rights reserved. // SPDX short identifier: ADIJESD204 // *************************************************************************** // *************************************************************************** @@ -11,14 +11,15 @@ module jesd204_soft_pcs_rx #( parameter NUM_LANES = 1, parameter DATA_PATH_WIDTH = 4, parameter REGISTER_INPUTS = 0, - parameter INVERT_INPUTS = 0 + parameter INVERT_INPUTS = 0, + parameter IFC_TYPE = 0 ) ( input clk, input reset, input patternalign_en, - input [NUM_LANES*DATA_PATH_WIDTH*10-1:0] data, + input [NUM_LANES*(DATA_PATH_WIDTH*10 + IFC_TYPE*40)-1:0] data, output reg [NUM_LANES*DATA_PATH_WIDTH*8-1:0] char, output reg [NUM_LANES*DATA_PATH_WIDTH-1:0] charisk, @@ -35,7 +36,7 @@ module jesd204_soft_pcs_rx #( wire [NUM_LANES*DATA_PATH_WIDTH-1:0] notintable_s; wire [NUM_LANES*DATA_PATH_WIDTH-1:0] disperr_s; - reg [NUM_LANES-1:0] disparity = {NUM_LANES{1'b0}}; + reg [NUM_LANES-1:0] disparity = {NUM_LANES{1'b0}}; wire [DATA_PATH_WIDTH:0] disparity_chain[0:NUM_LANES-1]; wire [NUM_LANES*DATA_PATH_WIDTH*10-1:0] data_s; @@ -49,70 +50,68 @@ module jesd204_soft_pcs_rx #( end generate - genvar lane; - genvar i; - if (REGISTER_INPUTS > 0) begin - reg patternalign_en_r; - reg [NUM_LANES*DATA_PATH_WIDTH*10-1:0] data_r; - always @(posedge clk) begin - patternalign_en_r <= patternalign_en; - data_r <= data; - end - assign patternalign_en_s = patternalign_en_r; - assign data_s = data_r; - end else begin - assign patternalign_en_s = patternalign_en; - assign data_s = data; - end - - for (lane = 0; lane < NUM_LANES; lane = lane + 1) begin: gen_lane - - jesd204_pattern_align #( - .DATA_PATH_WIDTH(DATA_PATH_WIDTH) - ) i_pattern_align ( - .clk(clk), - .reset(reset), - - .patternalign_en(patternalign_en_s), - .in_data(data_s[LANE_DATA_WIDTH*lane+:LANE_DATA_WIDTH]), - .out_data(data_aligned[LANE_DATA_WIDTH*lane+:LANE_DATA_WIDTH])); - - assign disparity_chain[lane][0] = disparity[lane]; - - always @(posedge clk) begin - if (reset == 1'b1) begin - disparity[lane] <= 1'b0; - end else begin - disparity[lane] <= disparity_chain[lane][DATA_PATH_WIDTH]; + genvar lane; + genvar i; + if (REGISTER_INPUTS > 0) begin + reg patternalign_en_r; + reg [NUM_LANES*DATA_PATH_WIDTH*10-1:0] data_r; + + always @(posedge clk) begin + patternalign_en_r <= patternalign_en; + data_r <= IFC_TYPE == 0 ? data : {data[59:40],data[19:0]}; end + assign patternalign_en_s = patternalign_en_r; + assign data_s = data_r; + end else begin + assign patternalign_en_s = patternalign_en; + assign data_s = IFC_TYPE == 0 ? data : {data[59:40],data[19:0]}; end - for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: gen_dpw - localparam j = DATA_PATH_WIDTH * lane + i; - wire [9:0] in_char; - if (REGISTER_INPUTS > 1) begin - reg [9:0] in_char_r = 10'b0; - always @(posedge clk) begin - in_char_r <= INVERT_INPUTS ? ~data_aligned[j*10+:10] : - data_aligned[j*10+:10]; + for (lane = 0; lane < NUM_LANES; lane = lane + 1) begin: gen_lane + jesd204_pattern_align #( + .DATA_PATH_WIDTH(DATA_PATH_WIDTH) + ) i_pattern_align ( + .clk(clk), + .reset(reset), + .patternalign_en(patternalign_en_s), + .in_data(data_s[LANE_DATA_WIDTH*lane+:LANE_DATA_WIDTH]), + .out_data(data_aligned[LANE_DATA_WIDTH*lane+:LANE_DATA_WIDTH])); + + assign disparity_chain[lane][0] = disparity[lane]; + + always @(posedge clk) begin + if (reset == 1'b1) begin + disparity[lane] <= 1'b0; + end else begin + disparity[lane] <= disparity_chain[lane][DATA_PATH_WIDTH]; end - assign in_char = in_char_r; - end else begin - assign in_char = INVERT_INPUTS ? ~data_aligned[j*10+:10] : - data_aligned[j*10+:10]; end - jesd204_8b10b_decoder i_dec ( - .in_char(in_char), - .out_char(char_s[j*8+:8]), - .out_charisk(charisk_s[j]), - .out_notintable(notintable_s[j]), - .out_disperr(disperr_s[j]), + for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: gen_dpw + localparam j = DATA_PATH_WIDTH * lane + i; + wire [9:0] in_char; + if (REGISTER_INPUTS > 1) begin + reg [9:0] in_char_r = 10'b0; + always @(posedge clk) begin + in_char_r <= INVERT_INPUTS ? ~data_aligned[j*10+:10] : + data_aligned[j*10+:10]; + end + assign in_char = in_char_r; + end else begin + assign in_char = INVERT_INPUTS ? ~data_aligned[j*10+:10] : + data_aligned[j*10+:10]; + end - .in_disparity(disparity_chain[lane][i]), - .out_disparity(disparity_chain[lane][i+1])); + jesd204_8b10b_decoder i_dec ( + .in_char(in_char), + .out_char(char_s[j*8+:8]), + .out_charisk(charisk_s[j]), + .out_notintable(notintable_s[j]), + .out_disperr(disperr_s[j]), + .in_disparity(disparity_chain[lane][i]), + .out_disparity(disparity_chain[lane][i+1])); + end end - end endgenerate endmodule diff --git a/library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx_hw.tcl b/library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx_hw.tcl index 2995ba2ecd..d8390d0998 100644 --- a/library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx_hw.tcl +++ b/library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx_hw.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2017-2019, 2021, 2022 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2017-2019, 2021, 2022, 2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIJESD204 ############################################################################### @@ -8,13 +8,18 @@ package require qsys 14.0 source ../../../scripts/adi_env.tcl source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl -ad_ip_create jesd204_soft_pcs_rx "ADI JESD204 Transmit Soft PCS" +ad_ip_create jesd204_soft_pcs_rx "ADI JESD204 Receive Soft PCS" ad_ip_parameter REGISTER_INPUTS INTEGER 0 ad_ip_parameter INVERT_INPUTS INTEGER 0 set_module_property INTERNAL true +add_parameter IFC_TYPE INTEGER 0 +set_parameter_property IFC_TYPE DISPLAY_NAME "Interface type" +set_parameter_property IFC_TYPE HDL_PARAMETER true +set_parameter_property IFC_TYPE ALLOWED_RANGES { "0:Legacy" "1:F-Type" } + # files ad_ip_files jesd204_soft_pcs_rx [list \ @@ -50,4 +55,4 @@ add_interface_port rx_phy patternalign_en patternalign_en Input 1 add_interface rx_raw_data conduit end #set_interface_property rx_raw_data associatedClock clock #set_interface_property rx_raw_data associatedReset reset -add_interface_port rx_raw_data data raw_data Input 40 +add_interface_port rx_raw_data data raw_data Input "(IFC_TYPE+1)*40" diff --git a/library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v b/library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v index 870054b69c..bb2b37cba5 100644 --- a/library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v +++ b/library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2017, 2018, 2022 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017, 2018, 2022, 2024 Analog Devices, Inc. All rights reserved. // SPDX short identifier: ADIJESD204 // *************************************************************************** // *************************************************************************** @@ -10,7 +10,8 @@ module jesd204_soft_pcs_tx #( parameter NUM_LANES = 1, parameter DATA_PATH_WIDTH = 4, - parameter INVERT_OUTPUTS = 0 + parameter INVERT_OUTPUTS = 0, + parameter IFC_TYPE = 0 ) ( input clk, input reset, @@ -18,44 +19,53 @@ module jesd204_soft_pcs_tx #( input [NUM_LANES*DATA_PATH_WIDTH*8-1:0] char, input [NUM_LANES*DATA_PATH_WIDTH-1:0] charisk, - output reg [NUM_LANES*DATA_PATH_WIDTH*10-1:0] data + output reg [NUM_LANES*(DATA_PATH_WIDTH*10 + IFC_TYPE*40)-1:0] data ); reg [NUM_LANES-1:0] disparity = 'h00; wire [DATA_PATH_WIDTH:0] disparity_chain[0:NUM_LANES-1]; wire [NUM_LANES*DATA_PATH_WIDTH*10-1:0] data_s; + wire [NUM_LANES*DATA_PATH_WIDTH*10-1:0] data_inv_s; + + assign data_inv_s = INVERT_OUTPUTS ? ~data_s : data_s; always @(posedge clk) begin - data <= INVERT_OUTPUTS ? ~data_s : data_s; + data <= IFC_TYPE == 0 ? data_inv_s : { // F-Tile padding + /* 79 */ 1'b1, + /* 78-60 */ 19'b0, + /* 59-40 */ data_inv_s[39:20], + /* 39 */ 1'b0, + /* 38 */ 1'b1, + /* 37-20 */ 18'b0, + /* 19-00 */ data_inv_s[19: 0]}; end generate - genvar lane; - genvar i; - for (lane = 0; lane < NUM_LANES; lane = lane + 1) begin: gen_lane - assign disparity_chain[lane][0] = disparity[lane]; - - always @(posedge clk) begin - if (reset == 1'b1) begin - disparity[lane] <= 1'b0; - end else begin - disparity[lane] <= disparity_chain[lane][DATA_PATH_WIDTH]; - end - end + genvar lane; + genvar i; + for (lane = 0; lane < NUM_LANES; lane = lane + 1) begin: gen_lane + assign disparity_chain[lane][0] = disparity[lane]; - for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: gen_dpw - localparam j = DATA_PATH_WIDTH * lane + i; + always @(posedge clk) begin + if (reset == 1'b1) begin + disparity[lane] <= 1'b0; + end else begin + disparity[lane] <= disparity_chain[lane][DATA_PATH_WIDTH]; + end + end - jesd204_8b10b_encoder i_enc ( - .in_char(char[j*8+:8]), - .in_charisk(charisk[j]), - .out_char(data_s[j*10+:10]), + for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: gen_dpw + localparam j = DATA_PATH_WIDTH * lane + i; - .in_disparity(disparity_chain[lane][i]), - .out_disparity(disparity_chain[lane][i+1])); + jesd204_8b10b_encoder i_enc ( + .in_char(char[j*8+:8]), + .in_charisk(charisk[j]), + .out_char(data_s[j*10+:10]), + .in_disparity(disparity_chain[lane][i]), + .out_disparity(disparity_chain[lane][i+1])); + end end - end endgenerate endmodule diff --git a/library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx_hw.tcl b/library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx_hw.tcl index 8e84d44a9b..2d43bea643 100644 --- a/library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx_hw.tcl +++ b/library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx_hw.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2017-2019, 2021, 2022 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2017-2019, 2021, 2022, 2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIJESD204 ############################################################################### @@ -14,6 +14,11 @@ set_module_property INTERNAL true ad_ip_parameter INVERT_OUTPUTS INTEGER 0 +add_parameter IFC_TYPE INTEGER 0 +set_parameter_property IFC_TYPE DISPLAY_NAME "Interface type" +set_parameter_property IFC_TYPE HDL_PARAMETER true +set_parameter_property IFC_TYPE ALLOWED_RANGES { "0:Legacy" "1:F-Type" } + # files ad_ip_files jesd204_soft_pcs_tx [list \ @@ -45,4 +50,4 @@ add_interface_port tx_phy charisk charisk Input 4 add_interface tx_raw_data conduit end #set_interface_property data associatedClock clock #set_interface_property data associatedReset reset -add_interface_port tx_raw_data data raw_data Output 40 +add_interface_port tx_raw_data data raw_data Output "(IFC_TYPE+1)*40" diff --git a/library/jesd204/jesd204_tx/jesd204_tx_hw.tcl b/library/jesd204/jesd204_tx/jesd204_tx_hw.tcl index b852dceb59..1c71e05325 100644 --- a/library/jesd204/jesd204_tx/jesd204_tx_hw.tcl +++ b/library/jesd204/jesd204_tx/jesd204_tx_hw.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2017-2022, 2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIJESD204 ############################################################################### @@ -18,6 +18,8 @@ ad_ip_files jesd204_tx [list \ jesd204_tx.v \ jesd204_tx_ctrl.v \ jesd204_tx_lane.v \ + jesd204_tx_lane_64b.v \ + jesd204_tx_header.v \ jesd204_tx_gearbox.v \ jesd204_tx_constr.sdc \ ../jesd204_common/jesd204_eof_generator.v \ @@ -25,6 +27,7 @@ ad_ip_files jesd204_tx [list \ ../jesd204_common/jesd204_frame_mark.v \ ../jesd204_common/jesd204_lmfc.v \ ../jesd204_common/jesd204_scrambler.v \ + ../jesd204_common/jesd204_scrambler_64b.v \ ../jesd204_common/pipeline_stage.v \ $ad_hdl_dir/library/util_cdc/sync_bits.v \ $ad_hdl_dir/library/util_cdc/sync_event.v \ @@ -35,6 +38,12 @@ ad_ip_files jesd204_tx [list \ # parameters +ad_ip_parameter LINK_MODE INTEGER 1 true { \ + DISPLAY_NAME "Link Layer mode" \ + ALLOWED_RANGES {"1:8B10B" "2:64B66B"} \ + HDL_PARAMETER true \ +} + add_parameter NUM_LANES INTEGER 1 set_parameter_property NUM_LANES DISPLAY_NAME "Number of Lanes" set_parameter_property NUM_LANES ALLOWED_RANGES 1:32 @@ -54,6 +63,12 @@ add_parameter ASYNC_CLK BOOLEAN false set_parameter_property ASYNC_CLK DISPLAY_NAME "Link and device clock asynchronous" set_parameter_property ASYNC_CLK HDL_PARAMETER true +ad_ip_parameter DATA_PATH_WIDTH INTEGER 4 true { \ + DISPLAY_NAME "Physical layer datapath widthin" \ + DISPLAY_UNITS "octets" \ + ALLOWED_RANGES {4 8} \ +} + ad_ip_parameter TPL_DATA_PATH_WIDTH INTEGER 4 true { \ DISPLAY_NAME "Transport layer datapath width" \ DISPLAY_UNITS "octets" \ @@ -187,6 +202,7 @@ set_port_property lmfc_edge TERMINATION TRUE proc jesd204_tx_elaboration_callback {} { set num_lanes [get_parameter_value "NUM_LANES"] set tpl_width [get_parameter_value "TPL_DATA_PATH_WIDTH"] + set phy_width [get_parameter_value "DATA_PATH_WIDTH"] # tx_data interface @@ -204,11 +220,22 @@ proc jesd204_tx_elaboration_callback {} { add_interface tx_phy${i} conduit start # set_interface_property tx_phy${i} associatedClock clock # set_interface_property tx_phy${i} associatedReset reset - add_interface_port tx_phy${i} tx_phy${i}_data char Output 32 + + add_interface_port tx_phy${i} tx_phy${i}_data char Output [expr 8*$phy_width] set_port_property tx_phy${i}_data fragment_list \ - [format "phy_data(%d:%d)" [expr 32*$i+31] [expr 32*$i]] - add_interface_port tx_phy${i} tx_phy${i}_charisk charisk Output 4 - set_port_property tx_phy${i}_charisk fragment_list \ - [format "phy_charisk(%d:%d)" [expr 4*$i+3] [expr 4*$i]] + [format "phy_data(%d:%d)" [expr (8*$phy_width)*($i+1)-1] [expr 8*$phy_width*$i]] + + if {[get_parameter_value "LINK_MODE"]==1} { + add_interface_port tx_phy${i} tx_phy${i}_charisk charisk Output $phy_width + set_port_property tx_phy${i}_charisk fragment_list \ + [format "phy_charisk(%d:%d)" [expr $phy_width*($i+1)-1] [expr $phy_width*$i]] + } + + if {[get_parameter_value "LINK_MODE"]==2} { + add_interface_port tx_phy${i} tx_phy${i}_header header Output 2 + set_port_property tx_phy${i}_header fragment_list \ + [format "phy_header(%d:%d)" [expr 2*($i+1)-1] [expr 2*$i]] + } } + } diff --git a/library/scripts/adi_intel_device_info_enc.tcl b/library/scripts/adi_intel_device_info_enc.tcl index 04b26ed4df..62f8d1d9e7 100644 --- a/library/scripts/adi_intel_device_info_enc.tcl +++ b/library/scripts/adi_intel_device_info_enc.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2019-2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -41,7 +41,8 @@ set fpga_technology_list { \ { "Cyclone V" 101 } \ { "Cyclone 10" 102 } \ { "Arria 10" 103 } \ - { "Stratix 10" 104 }} + { "Stratix 10" 104 } \ + { "Agilex 7" 105 }} set fpga_family_list { \ { Unknown 0 } \ @@ -49,7 +50,9 @@ set fpga_family_list { \ { GX 2 } \ { GT 3 } \ { GZ 4 } \ - { "SE Base" 5 }} + { "SE Base" 5 } \ + { "I-Series with HPS only" 6 } \ + { TX 6 }} #technology 5 generation # family Arria SX @@ -132,8 +135,13 @@ proc get_part_param {} { } # user and system values (sys_val) - regsub {V} $fpga_voltage "" fpga_voltage - set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) + if { $fpga_technology == "{{Agilex 7}}" } { + # TODO : Transform VID2 to some voltage + set fpga_voltage "0" + } else { + regsub {V} $fpga_voltage "" fpga_voltage + set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) + } } diff --git a/projects/ad9081_fmca_ebz/a10soc/Makefile b/projects/ad9081_fmca_ebz/a10soc/Makefile index 81837861e7..83d26e3e26 100644 --- a/projects/ad9081_fmca_ebz/a10soc/Makefile +++ b/projects/ad9081_fmca_ebz/a10soc/Makefile @@ -1,5 +1,5 @@ #################################################################################### -## Copyright (c) 2018 - 2023 Analog Devices, Inc. +## Copyright (c) 2018 - 2024 Analog Devices, Inc. ### SPDX short identifier: BSD-1-Clause ## Auto-generated, do not modify! #################################################################################### diff --git a/projects/ad9081_fmca_ebz/a10soc/system_constr.sdc b/projects/ad9081_fmca_ebz/a10soc/system_constr.sdc index 712c83fdf0..97d7a76e9c 100755 --- a/projects/ad9081_fmca_ebz/a10soc/system_constr.sdc +++ b/projects/ad9081_fmca_ebz/a10soc/system_constr.sdc @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -14,3 +14,11 @@ set_false_path -to [get_registers *sys_gpio_bd|readdata[12]*] set_false_path -to [get_registers *sys_gpio_bd|readdata[13]*] set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*] + +# Constraint SYSREFs +# Assumption is that REFCLK and SYSREF have similar propagation delay, +# and the SYSREF is a source synchronous Edge-Aligned signal to REFCLK +set_input_delay \ + -clock tx_device_clk \ + [get_clock_info -period device_clk] \ + [get_ports {sysref2}] diff --git a/projects/ad9081_fmca_ebz/a10soc/system_project.tcl b/projects/ad9081_fmca_ebz/a10soc/system_project.tcl index 854f57d6c7..7dc1380837 100755 --- a/projects/ad9081_fmca_ebz/a10soc/system_project.tcl +++ b/projects/ad9081_fmca_ebz/a10soc/system_project.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -33,6 +33,8 @@ source ../../scripts/adi_project_intel.tcl adi_project ad9081_fmca_ebz_a10soc [list \ RX_LANE_RATE [get_env_param RX_LANE_RATE 10 ] \ TX_LANE_RATE [get_env_param TX_LANE_RATE 10 ] \ + REF_CLK_RATE [get_env_param REF_CLK_RATE 250 ] \ + DEVICE_CLK_RATE [get_env_param DEVICE_CLK_RATE 250 ] \ RX_JESD_M [get_env_param RX_JESD_M 8 ] \ RX_JESD_L [get_env_param RX_JESD_L 4 ] \ RX_JESD_S [get_env_param RX_JESD_S 1 ] \ @@ -43,8 +45,8 @@ adi_project ad9081_fmca_ebz_a10soc [list \ TX_JESD_S [get_env_param TX_JESD_S 1 ] \ TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \ TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \ - RX_KS_PER_CHANNEL [get_env_param RX_KS_PER_CHANNEL 32 ] \ - TX_KS_PER_CHANNEL [get_env_param TX_KS_PER_CHANNEL 32 ] \ + RX_KS_PER_CHANNEL [get_env_param RX_KS_PER_CHANNEL 16 ] \ + TX_KS_PER_CHANNEL [get_env_param TX_KS_PER_CHANNEL 16 ] \ ] source $ad_hdl_dir/projects/common/a10soc/a10soc_system_assign.tcl diff --git a/projects/ad9081_fmca_ebz/a10soc/system_qsys.tcl b/projects/ad9081_fmca_ebz/a10soc/system_qsys.tcl index 119d26a8b6..1726351ec8 100755 --- a/projects/ad9081_fmca_ebz/a10soc/system_qsys.tcl +++ b/projects/ad9081_fmca_ebz/a10soc/system_qsys.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -13,6 +13,7 @@ source $ad_hdl_dir/projects/common/a10soc/a10soc_system_qsys.tcl source $ad_hdl_dir/projects/common/intel/dacfifo_qsys.tcl source $ad_hdl_dir/projects/common/intel/adcfifo_qsys.tcl +set TRANSCEIVER_TYPE "SX" if [info exists ad_project_dir] { source ../../common/ad9081_fmca_ebz_qsys.tcl } else { @@ -37,6 +38,8 @@ L=$ad_project_params(TX_JESD_L)\ S=$ad_project_params(TX_JESD_S)\ NP=$ad_project_params(TX_JESD_NP)\ LINKS=$ad_project_params(TX_NUM_LINKS)\ -KS/CH=$ad_project_params(TX_KS_PER_CHANNEL)" +KS/CH=$ad_project_params(TX_KS_PER_CHANNEL)\ +REF_CLK=$ad_project_params(REF_CLK_RATE)\ +DEV_CLK=$ad_project_params(DEVICE_CLK_RATE)" sysid_gen_sys_init_file sys_cstring diff --git a/projects/ad9081_fmca_ebz/a10soc/system_top.v b/projects/ad9081_fmca_ebz/a10soc/system_top.v index 2cd407d71a..9dc6e38b9a 100755 --- a/projects/ad9081_fmca_ebz/a10soc/system_top.v +++ b/projects/ad9081_fmca_ebz/a10soc/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -39,6 +39,8 @@ module system_top #( // Dummy parameters to workaround critical warning parameter RX_LANE_RATE = 10, parameter TX_LANE_RATE = 10, + parameter REF_CLK_RATE = 250, + parameter DEVICE_CLK_RATE = 250, parameter RX_JESD_M = 8, parameter RX_JESD_L = 4, parameter RX_JESD_S = 1, diff --git a/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_qsys.tcl b/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_qsys.tcl index cd87cc9112..f329e76172 100644 --- a/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_qsys.tcl +++ b/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_qsys.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -50,8 +50,14 @@ set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 8*$TX_TPL_DATA_PATH_WIDTH / ($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)] # Lane Rate = I/Q Sample Rate x M x N' x (10 \ 8) \ L -set TX_LANE_RATE [expr $ad_project_params(RX_LANE_RATE)*1000] -set RX_LANE_RATE [expr $ad_project_params(TX_LANE_RATE)*1000] +set RX_LANE_RATE [expr $ad_project_params(RX_LANE_RATE)*1000] +set TX_LANE_RATE [expr $ad_project_params(TX_LANE_RATE)*1000] + +# Reference Clock Rate = Lane Rate / 40 +set REF_CLK_RATE $ad_project_params(REF_CLK_RATE) + +# Device Clock Rate +set DEVICE_CLK_RATE [expr $ad_project_params(DEVICE_CLK_RATE)*1000000] set adc_fifo_name mxfe_adc_fifo set adc_data_width [expr 8*$RX_TPL_DATA_PATH_WIDTH*$RX_NUM_OF_LANES*$RX_DMA_SAMPLE_WIDTH/$RX_SAMPLE_WIDTH] @@ -66,10 +72,10 @@ set dac_fifo_address_width [expr int(ceil(log(($dac_fifo_samples_per_converter*$ # JESD204B clock bridges add_instance tx_device_clk altera_clock_bridge -set_instance_parameter_value tx_device_clk {EXPLICIT_CLOCK_RATE} {250000000} +set_instance_parameter_value tx_device_clk {EXPLICIT_CLOCK_RATE} $DEVICE_CLK_RATE add_instance rx_device_clk altera_clock_bridge -set_instance_parameter_value rx_device_clk {EXPLICIT_CLOCK_RATE} {250000000} +set_instance_parameter_value rx_device_clk {EXPLICIT_CLOCK_RATE} $DEVICE_CLK_RATE # ## IP instantions and configuration @@ -83,11 +89,12 @@ set_instance_parameter_value mxfe_rx_jesd204 {TX_OR_RX_N} {0} set_instance_parameter_value mxfe_rx_jesd204 {SOFT_PCS} {true} set_instance_parameter_value mxfe_rx_jesd204 {LANE_RATE} $RX_LANE_RATE set_instance_parameter_value mxfe_rx_jesd204 {SYSCLK_FREQUENCY} {100.0} -set_instance_parameter_value mxfe_rx_jesd204 {REFCLK_FREQUENCY} {250.0} +set_instance_parameter_value mxfe_rx_jesd204 {REFCLK_FREQUENCY} $REF_CLK_RATE set_instance_parameter_value mxfe_rx_jesd204 {INPUT_PIPELINE_STAGES} {2} set_instance_parameter_value mxfe_rx_jesd204 {NUM_OF_LANES} $RX_NUM_OF_LANES set_instance_parameter_value mxfe_rx_jesd204 {EXT_DEVICE_CLK_EN} {1} set_instance_parameter_value mxfe_rx_jesd204 {TPL_DATA_PATH_WIDTH} $RX_TPL_DATA_PATH_WIDTH +# set_instance_parameter_value mxfe_rx_jesd204 {LANE_MAP} {5 7 0 1 2 3 4 6} add_instance mxfe_rx_tpl ad_ip_jesd204_tpl_adc @@ -108,10 +115,11 @@ set_instance_parameter_value mxfe_tx_jesd204 {TX_OR_RX_N} {1} set_instance_parameter_value mxfe_tx_jesd204 {SOFT_PCS} {true} set_instance_parameter_value mxfe_tx_jesd204 {LANE_RATE} $TX_LANE_RATE set_instance_parameter_value mxfe_tx_jesd204 {SYSCLK_FREQUENCY} {100.0} -set_instance_parameter_value mxfe_tx_jesd204 {REFCLK_FREQUENCY} {250.0} +set_instance_parameter_value mxfe_tx_jesd204 {REFCLK_FREQUENCY} $REF_CLK_RATE set_instance_parameter_value mxfe_tx_jesd204 {NUM_OF_LANES} $TX_NUM_OF_LANES set_instance_parameter_value mxfe_tx_jesd204 {EXT_DEVICE_CLK_EN} {1} set_instance_parameter_value mxfe_tx_jesd204 {TPL_DATA_PATH_WIDTH} $TX_TPL_DATA_PATH_WIDTH +# set_instance_parameter_value mxfe_tx_jesd204 {LANE_MAP} {5 7 0 1 2 3 4 6} add_instance mxfe_tx_tpl ad_ip_jesd204_tpl_dac @@ -178,14 +186,14 @@ set_instance_parameter_value mxfe_rx_dma {MAX_BYTES_PER_BURST} {4096} # mxfe gpio -add_instance avl_mxfe_gpio altera_avalon_pio -set_instance_parameter_value avl_mxfe_gpio {direction} {Bidir} -set_instance_parameter_value avl_mxfe_gpio {generateIRQ} {1} -set_instance_parameter_value avl_mxfe_gpio {width} {19} -add_connection sys_clk.clk avl_mxfe_gpio.clk -add_connection sys_clk.clk_reset avl_mxfe_gpio.reset +add_instance mxfe_gpio altera_avalon_pio +set_instance_parameter_value mxfe_gpio {direction} {Input} +set_instance_parameter_value mxfe_gpio {generateIRQ} {1} +set_instance_parameter_value mxfe_gpio {width} {15} +add_connection sys_clk.clk mxfe_gpio.clk +add_connection sys_clk.clk_reset mxfe_gpio.reset add_interface mxfe_gpio conduit end -set_interface_property mxfe_gpio EXPORT_OF avl_mxfe_gpio.external_connection +set_interface_property mxfe_gpio EXPORT_OF mxfe_gpio.external_connection # ## clocks and resets @@ -267,6 +275,14 @@ set_interface_property tx_sync EXPORT_OF mxfe_tx_jesd204.sync set_interface_property tx_serial_data EXPORT_OF mxfe_tx_jesd204.serial_data set_interface_property tx_device_clk EXPORT_OF tx_device_clk.in_clk +if {$TRANSCEIVER_TYPE == "F-Tile"} { + add_interface tx_serial_data_n conduit end + add_interface rx_serial_data_n conduit end + + set_interface_property rx_serial_data_n EXPORT_OF mxfe_rx_jesd204.serial_data_n + set_interface_property tx_serial_data_n EXPORT_OF mxfe_tx_jesd204.serial_data_n +} + # ## Data interface / data path # @@ -304,21 +320,22 @@ add_connection mxfe_tx_dma.m_axis $dac_fifo_name.s_axis # TX dma to HPS ad_dma_interconnect mxfe_tx_dma.m_src_axi -# reconfiguration interface sharing - -set MAX_NUM_OF_LANES $TX_NUM_OF_LANES -if {$RX_NUM_OF_LANES > $TX_NUM_OF_LANES} { - set MAX_NUM_OF_LANES $RX_NUM_OF_LANES -} -for {set i 0} {$i < $MAX_NUM_OF_LANES} {incr i} { - add_instance avl_adxcfg_${i} avl_adxcfg - add_connection sys_clk.clk avl_adxcfg_${i}.rcfg_clk - add_connection sys_clk.clk_reset avl_adxcfg_${i}.rcfg_reset_n - add_connection avl_adxcfg_${i}.rcfg_m0 mxfe_tx_jesd204.phy_reconfig_${i} - add_connection avl_adxcfg_${i}.rcfg_m1 mxfe_rx_jesd204.phy_reconfig_${i} - - set_instance_parameter_value avl_adxcfg_${i} {ADDRESS_WIDTH} $xcvr_reconfig_addr_width - +# reconfiguration interface sharing for A10soc + +if {$TRANSCEIVER_TYPE != "F-Tile"} { + set MAX_NUM_OF_LANES $TX_NUM_OF_LANES + if {$RX_NUM_OF_LANES > $TX_NUM_OF_LANES} { + set MAX_NUM_OF_LANES $RX_NUM_OF_LANES + } + for {set i 0} {$i < $MAX_NUM_OF_LANES} {incr i} { + add_instance avl_adxcfg_${i} avl_adxcfg + add_connection sys_clk.clk avl_adxcfg_${i}.rcfg_clk + add_connection sys_clk.clk_reset avl_adxcfg_${i}.rcfg_reset_n + add_connection avl_adxcfg_${i}.rcfg_m0 mxfe_tx_jesd204.phy_reconfig_${i} + add_connection avl_adxcfg_${i}.rcfg_m1 mxfe_rx_jesd204.phy_reconfig_${i} + + set_instance_parameter_value avl_adxcfg_${i} {ADDRESS_WIDTH} $xcvr_reconfig_addr_width + } } # @@ -328,36 +345,42 @@ for {set i 0} {$i < $MAX_NUM_OF_LANES} {incr i} { ## NOTE: if bridge is used, the address will be bridge_base_addr + peripheral_base_addr # -ad_cpu_interconnect 0x00020000 mxfe_rx_jesd204.link_pll_reconfig "avl_mm_bridge_0" 0x00040000 -if {$RX_NUM_OF_LANES > 0} {ad_cpu_interconnect 0x00000000 avl_adxcfg_0.rcfg_s0 "avl_mm_bridge_0"} -if {$RX_NUM_OF_LANES > 1} {ad_cpu_interconnect 0x00002000 avl_adxcfg_1.rcfg_s0 "avl_mm_bridge_0"} -if {$RX_NUM_OF_LANES > 2} {ad_cpu_interconnect 0x00004000 avl_adxcfg_2.rcfg_s0 "avl_mm_bridge_0"} -if {$RX_NUM_OF_LANES > 3} {ad_cpu_interconnect 0x00006000 avl_adxcfg_3.rcfg_s0 "avl_mm_bridge_0"} -if {$RX_NUM_OF_LANES > 4} {ad_cpu_interconnect 0x00008000 avl_adxcfg_4.rcfg_s0 "avl_mm_bridge_0"} -if {$RX_NUM_OF_LANES > 5} {ad_cpu_interconnect 0x0000A000 avl_adxcfg_5.rcfg_s0 "avl_mm_bridge_0"} -if {$RX_NUM_OF_LANES > 6} {ad_cpu_interconnect 0x0000C000 avl_adxcfg_6.rcfg_s0 "avl_mm_bridge_0"} -if {$RX_NUM_OF_LANES > 7} {ad_cpu_interconnect 0x0000E000 avl_adxcfg_7.rcfg_s0 "avl_mm_bridge_0"} - -ad_cpu_interconnect 0x00020000 mxfe_tx_jesd204.link_pll_reconfig "avl_mm_bridge_1" 0x00080000 -if {$TX_NUM_OF_LANES > 0} {ad_cpu_interconnect 0x00000000 avl_adxcfg_0.rcfg_s1 "avl_mm_bridge_1"} -if {$TX_NUM_OF_LANES > 1} {ad_cpu_interconnect 0x00002000 avl_adxcfg_1.rcfg_s1 "avl_mm_bridge_1"} -if {$TX_NUM_OF_LANES > 2} {ad_cpu_interconnect 0x00004000 avl_adxcfg_2.rcfg_s1 "avl_mm_bridge_1"} -if {$TX_NUM_OF_LANES > 3} {ad_cpu_interconnect 0x00006000 avl_adxcfg_3.rcfg_s1 "avl_mm_bridge_1"} -if {$TX_NUM_OF_LANES > 4} {ad_cpu_interconnect 0x00008000 avl_adxcfg_4.rcfg_s1 "avl_mm_bridge_1"} -if {$TX_NUM_OF_LANES > 5} {ad_cpu_interconnect 0x0000A000 avl_adxcfg_5.rcfg_s1 "avl_mm_bridge_1"} -if {$TX_NUM_OF_LANES > 6} {ad_cpu_interconnect 0x0000C000 avl_adxcfg_6.rcfg_s1 "avl_mm_bridge_1"} -if {$TX_NUM_OF_LANES > 7} {ad_cpu_interconnect 0x0000E000 avl_adxcfg_7.rcfg_s1 "avl_mm_bridge_1"} +if {$TRANSCEIVER_TYPE == "F-Tile"} { + ad_cpu_interconnect 0x00000000 mxfe_rx_jesd204.phy_reconfig "avl_mm_bridge_0" 0x10000000 25 + ad_cpu_interconnect 0x00800000 mxfe_tx_jesd204.phy_reconfig "avl_mm_bridge_0" +} else { + ad_cpu_interconnect 0x00020000 mxfe_rx_jesd204.link_pll_reconfig "avl_mm_bridge_0" 0x00040000 + if {$RX_NUM_OF_LANES > 0} {ad_cpu_interconnect 0x00000000 avl_adxcfg_0.rcfg_s0 "avl_mm_bridge_0"} + if {$RX_NUM_OF_LANES > 1} {ad_cpu_interconnect 0x00002000 avl_adxcfg_1.rcfg_s0 "avl_mm_bridge_0"} + if {$RX_NUM_OF_LANES > 2} {ad_cpu_interconnect 0x00004000 avl_adxcfg_2.rcfg_s0 "avl_mm_bridge_0"} + if {$RX_NUM_OF_LANES > 3} {ad_cpu_interconnect 0x00006000 avl_adxcfg_3.rcfg_s0 "avl_mm_bridge_0"} + if {$RX_NUM_OF_LANES > 4} {ad_cpu_interconnect 0x00008000 avl_adxcfg_4.rcfg_s0 "avl_mm_bridge_0"} + if {$RX_NUM_OF_LANES > 5} {ad_cpu_interconnect 0x0000A000 avl_adxcfg_5.rcfg_s0 "avl_mm_bridge_0"} + if {$RX_NUM_OF_LANES > 6} {ad_cpu_interconnect 0x0000C000 avl_adxcfg_6.rcfg_s0 "avl_mm_bridge_0"} + if {$RX_NUM_OF_LANES > 7} {ad_cpu_interconnect 0x0000E000 avl_adxcfg_7.rcfg_s0 "avl_mm_bridge_0"} + + ad_cpu_interconnect 0x00020000 mxfe_tx_jesd204.link_pll_reconfig "avl_mm_bridge_1" 0x00080000 + if {$TX_NUM_OF_LANES > 0} {ad_cpu_interconnect 0x00000000 avl_adxcfg_0.rcfg_s1 "avl_mm_bridge_1"} + if {$TX_NUM_OF_LANES > 1} {ad_cpu_interconnect 0x00002000 avl_adxcfg_1.rcfg_s1 "avl_mm_bridge_1"} + if {$TX_NUM_OF_LANES > 2} {ad_cpu_interconnect 0x00004000 avl_adxcfg_2.rcfg_s1 "avl_mm_bridge_1"} + if {$TX_NUM_OF_LANES > 3} {ad_cpu_interconnect 0x00006000 avl_adxcfg_3.rcfg_s1 "avl_mm_bridge_1"} + if {$TX_NUM_OF_LANES > 4} {ad_cpu_interconnect 0x00008000 avl_adxcfg_4.rcfg_s1 "avl_mm_bridge_1"} + if {$TX_NUM_OF_LANES > 5} {ad_cpu_interconnect 0x0000A000 avl_adxcfg_5.rcfg_s1 "avl_mm_bridge_1"} + if {$TX_NUM_OF_LANES > 6} {ad_cpu_interconnect 0x0000C000 avl_adxcfg_6.rcfg_s1 "avl_mm_bridge_1"} + if {$TX_NUM_OF_LANES > 7} {ad_cpu_interconnect 0x0000E000 avl_adxcfg_7.rcfg_s1 "avl_mm_bridge_1"} + + ad_cpu_interconnect 0x000D0000 mxfe_tx_jesd204.lane_pll_reconfig +} ad_cpu_interconnect 0x000C0000 mxfe_rx_jesd204.link_reconfig ad_cpu_interconnect 0x000C4000 mxfe_rx_jesd204.link_management ad_cpu_interconnect 0x000C8000 mxfe_tx_jesd204.link_reconfig ad_cpu_interconnect 0x000CC000 mxfe_tx_jesd204.link_management -ad_cpu_interconnect 0x000D0000 mxfe_tx_jesd204.lane_pll_reconfig ad_cpu_interconnect 0x000D2000 mxfe_rx_tpl.s_axi ad_cpu_interconnect 0x000D4000 mxfe_tx_tpl.s_axi ad_cpu_interconnect 0x000D8000 mxfe_rx_dma.s_axi ad_cpu_interconnect 0x000DC000 mxfe_tx_dma.s_axi -ad_cpu_interconnect 0x000E0000 avl_mxfe_gpio.s1 +ad_cpu_interconnect 0x000E0000 mxfe_gpio.s1 # ## interrupts @@ -367,6 +390,4 @@ ad_cpu_interrupt 11 mxfe_rx_dma.interrupt_sender ad_cpu_interrupt 12 mxfe_tx_dma.interrupt_sender ad_cpu_interrupt 13 mxfe_rx_jesd204.interrupt ad_cpu_interrupt 14 mxfe_tx_jesd204.interrupt -ad_cpu_interrupt 15 avl_mxfe_gpio.irq - - +ad_cpu_interrupt 15 mxfe_gpio.irq diff --git a/projects/ad9081_fmca_ebz/fm87/Makefile b/projects/ad9081_fmca_ebz/fm87/Makefile new file mode 100644 index 0000000000..392adb60ca --- /dev/null +++ b/projects/ad9081_fmca_ebz/fm87/Makefile @@ -0,0 +1,27 @@ +#################################################################################### +## Copyright (c) 2018 - 2024 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := ad9081_fmca_ebz_fm87 + +M_DEPS += ../common/ad9081_fmca_ebz_qsys.tcl +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/intel/dacfifo_qsys.tcl +M_DEPS += ../../common/intel/adcfifo_qsys.tcl +M_DEPS += ../../common/fm87/fm87_system_qsys.tcl +M_DEPS += ../../common/fm87/fm87_system_assign.tcl +M_DEPS += ../../common/fm87/gpio_slave.v +M_DEPS += ../../../library/common/ad_3w_spi.v + +LIB_DEPS += axi_dmac +LIB_DEPS += axi_sysid +LIB_DEPS += intel/adi_jesd204 +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac +LIB_DEPS += sysid_rom +LIB_DEPS += util_pack/util_cpack2 +LIB_DEPS += util_pack/util_upack2 + +include ../../scripts/project-intel.mk diff --git a/projects/ad9081_fmca_ebz/fm87/system_constr.sdc b/projects/ad9081_fmca_ebz/fm87/system_constr.sdc new file mode 100644 index 0000000000..a43f559f16 --- /dev/null +++ b/projects/ad9081_fmca_ebz/fm87/system_constr.sdc @@ -0,0 +1,22 @@ +############################################################################### +## Copyright (C) 2024 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}] +create_clock -period "2.6666 ns" -name ref_clk [get_ports {fpga_refclk_in}] +create_clock -period "2.6666 ns" -name tx_device_clk [get_ports {clkin6}] +create_clock -period "2.6666 ns" -name rx_device_clk [get_ports {clkin10}] + +derive_pll_clocks +derive_clock_uncertainty + +set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*] + +# Constraint SYSREFs +# Assumption is that REFCLK and SYSREF have similar propagation delay, +# and the SYSREF is a source synchronous Edge-Aligned signal to REFCLK +set_input_delay \ + -clock rx_device_clk \ + [get_clock_info -period rx_device_clk] \ + [get_ports {sysref2}] diff --git a/projects/ad9081_fmca_ebz/fm87/system_project.tcl b/projects/ad9081_fmca_ebz/fm87/system_project.tcl new file mode 100644 index 0000000000..73e05d35a0 --- /dev/null +++ b/projects/ad9081_fmca_ebz/fm87/system_project.tcl @@ -0,0 +1,223 @@ +############################################################################### +## Copyright (C) 2024 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +source ../../scripts/adi_project_intel.tcl + +# get_env_param retrieves parameter value from the environment if exists, +# other case use the default value +# +# Use over-writable parameters from the environment. +# +# e.g. +# make RX_RATE=10 TX_RATE=10 RX_JESD_L=4 RX_JESD_M=8 RX_JESD_S=1 RX_JESD_NP=16 TX_JESD_L=4 TX_JESD_M=8 TX_JESD_S=1 TX_JESD_NP=16 +# make RX_RATE=2.5 TX_RATE=2.5 RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1 RX_JESD_NP=16 TX_JESD_L=8 TX_JESD_M=4 TX_JESD_S=1 TX_JESD_NP=16 +# make RX_RATE=10 TX_RATE=10 RX_JESD_L=2 RX_JESD_M=8 RX_JESD_S=1 RX_JESD_NP=12 TX_JESD_L=2 TX_JESD_M=8 TX_JESD_S=1 TX_JESD_NP=12 +# +# Lane Rate = I/Q Sample Rate x M x N' x (10 \ 8) \ L + +# Parameter description: +# +# RX_RATE : Lane rate of the Rx link ( MxFE to FPGA ) +# TX_RATE : Lane rate of the Tx link ( FPGA to MxFE ) +# [RX/TX]_JESD_M : Number of converters per link +# [RX/TX]_JESD_L : Number of lanes per link +# [RX/TX]_JESD_S : Number of samples per frame +# [RX/TX]_JESD_NP : Number of bits per sample +# [RX/TX]_NUM_LINKS : Number of links +# [RX/TX]_KS_PER_CHANNEL : Number of samples stored in internal buffers in kilosamples per converter (M) +# + +adi_project ad9081_fmca_ebz_fm87 [list \ + RX_LANE_RATE [get_env_param RX_LANE_RATE 15 ] \ + TX_LANE_RATE [get_env_param TX_LANE_RATE 15 ] \ + REF_CLK_RATE [get_env_param REF_CLK_RATE 375 ] \ + DEVICE_CLK_RATE [get_env_param DEVICE_CLK_RATE 375 ] \ + RX_JESD_M [get_env_param RX_JESD_M 8 ] \ + RX_JESD_L [get_env_param RX_JESD_L 8 ] \ + RX_JESD_S [get_env_param RX_JESD_S 1 ] \ + RX_JESD_NP [get_env_param RX_JESD_NP 16 ] \ + RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \ + TX_JESD_M [get_env_param TX_JESD_M 8 ] \ + TX_JESD_L [get_env_param TX_JESD_L 8 ] \ + TX_JESD_S [get_env_param TX_JESD_S 1 ] \ + TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \ + TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \ + RX_KS_PER_CHANNEL [get_env_param RX_KS_PER_CHANNEL 32 ] \ + TX_KS_PER_CHANNEL [get_env_param TX_KS_PER_CHANNEL 32 ] \ +] + +source $ad_hdl_dir/projects/common/fm87/fm87_system_assign.tcl + +# files + +set_global_assignment -name VERILOG_FILE ../../../library/common/ad_3w_spi.v +set_global_assignment -name VERILOG_FILE ../../common/fm87/gpio_slave.v + +# Note: This projects requires a hardware rework to function correctly. +# +# Changes required (Agilex FMC A): +# R1433, R1434: 50 ohm +# R1777, R1778: 50 ohm +# C2488, C4289: 0 ohm +# R1231, R1234: 1k ohm +# R1230, R1233: 1k ohm + +# Changes required (MxFE): +# C39B, C40B: 50 ohm + +set_instance_assignment -name IO_STANDARD "True Differential Signaling" -to fpga_syncin_0 +set_instance_assignment -name IO_STANDARD "Differential 1.2-V HSTL" -to fpga_syncout_0 +set_instance_assignment -name IO_STANDARD "True Differential Signaling" -to sysref2 +set_instance_assignment -name IO_STANDARD "True Differential Signaling" -to clkin6 +set_instance_assignment -name IO_STANDARD "True Differential Signaling" -to clkin10 +set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to fpga_refclk_in + +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to fpga_syncin_0 +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to sysref2 + +set_location_assignment PIN_J50 -to "agc0[0]" ; ## D20 LA17_CC_P +set_location_assignment PIN_K51 -to "agc0[1]" ; ## D21 LA17_CC_N +set_location_assignment PIN_G50 -to "agc1[0]" ; ## C22 LA18_CC_P +set_location_assignment PIN_F51 -to "agc1[1]" ; ## C23 LA18_CC_N +set_location_assignment PIN_A60 -to "agc2[0]" ; ## G21 LA20_P +set_location_assignment PIN_B61 -to "agc2[1]" ; ## G22 LA20_N +set_location_assignment PIN_J46 -to "agc3[0]" ; ## H25 LA21_P +set_location_assignment PIN_K47 -to "agc3[1]" ; ## H26 LA21_N +set_location_assignment PIN_T43 -to "clkin6(n)" ; ## G03 CLK1_M2C_N +set_location_assignment PIN_U42 -to "clkin6" ; ## G02 CLK1_M2C_P +set_location_assignment PIN_P47 -to "clkin10(n)" ; ## G07 LA00_P_CC +set_location_assignment PIN_R46 -to "clkin10" ; ## G06 LA00_N_CC +set_location_assignment PIN_BB57 -to "fpga_refclk_in" ; ## D04 GBTCLK0_M2C_P + +set_location_assignment PIN_AP69 -to "rx_data[0]" ; ## C06 DP0_M2C_P +set_location_assignment PIN_AR68 -to "rx_data_n[0]" ; ## C07 DP0_M2C_N +set_location_assignment PIN_AU66 -to "rx_data[1]" ; ## A02 DP1_M2C_P +set_location_assignment PIN_AT65 -to "rx_data_n[1]" ; ## A03 DP1_M2C_N +set_location_assignment PIN_AV69 -to "rx_data[2]" ; ## A06 DP2_M2C_P +set_location_assignment PIN_AW68 -to "rx_data_n[2]" ; ## A07 DP2_M2C_N +set_location_assignment PIN_BA66 -to "rx_data[3]" ; ## A10 DP3_M2C_P +set_location_assignment PIN_AY65 -to "rx_data_n[3]" ; ## A11 DP3_M2C_N +set_location_assignment PIN_BB69 -to "rx_data[4]" ; ## A14 DP4_M2C_P +set_location_assignment PIN_BC68 -to "rx_data_n[4]" ; ## A15 DP4_M2C_N +set_location_assignment PIN_BE66 -to "rx_data[5]" ; ## A18 DP5_M2C_P +set_location_assignment PIN_BD65 -to "rx_data_n[5]" ; ## A19 DP5_M2C_N +set_location_assignment PIN_BF69 -to "rx_data[6]" ; ## B16 DP6_M2C_P +set_location_assignment PIN_BG68 -to "rx_data_n[6]" ; ## B17 DP6_M2C_N +set_location_assignment PIN_BJ66 -to "rx_data[7]" ; ## B12 DP7_M2C_P +set_location_assignment PIN_BH65 -to "rx_data_n[7]" ; ## B13 DP7_M2C_N + +set_location_assignment PIN_AP63 -to "tx_data[0]" ; ## C02 DP0_C2M_P +set_location_assignment PIN_AR62 -to "tx_data_n[0]" ; ## C03 DP0_C2M_N +set_location_assignment PIN_AU60 -to "tx_data[1]" ; ## A22 DP1_C2M_P +set_location_assignment PIN_AT59 -to "tx_data_n[1]" ; ## A23 DP1_C2M_N +set_location_assignment PIN_AV63 -to "tx_data[2]" ; ## A26 DP2_C2M_P +set_location_assignment PIN_AW62 -to "tx_data_n[2]" ; ## A27 DP2_C2M_N +set_location_assignment PIN_BA60 -to "tx_data[3]" ; ## A30 DP3_C2M_P +set_location_assignment PIN_AY59 -to "tx_data_n[3]" ; ## A31 DP3_C2M_N +set_location_assignment PIN_BB63 -to "tx_data[4]" ; ## A34 DP4_C2M_P +set_location_assignment PIN_BC62 -to "tx_data_n[4]" ; ## A35 DP4_C2M_N +set_location_assignment PIN_BE60 -to "tx_data[5]" ; ## A38 DP5_C2M_P +set_location_assignment PIN_BD59 -to "tx_data_n[5]" ; ## A39 DP5_C2M_N +set_location_assignment PIN_BF63 -to "tx_data[6]" ; ## B36 DP6_C2M_P +set_location_assignment PIN_BG62 -to "tx_data_n[6]" ; ## B37 DP6_C2M_N +set_location_assignment PIN_BJ60 -to "tx_data[7]" ; ## B32 DP7_C2M_P +set_location_assignment PIN_BH59 -to "tx_data_n[7]" ; ## B33 DP7_C2M_N + +set_location_assignment PIN_AB47 -to "fpga_syncin_0(n)" ; ## H08 LA02_N +set_location_assignment PIN_AA46 -to "fpga_syncin_0" ; ## H07 LA02_P +set_location_assignment PIN_P49 -to "fpga_syncin_1_n" ; ## G10 LA03_N +set_location_assignment PIN_R48 -to "fpga_syncin_1_p" ; ## G09 LA03_P +set_location_assignment PIN_T45 -to "fpga_syncout_0(n)" ; ## D09 LA01_CC_N +set_location_assignment PIN_U44 -to "fpga_syncout_0" ; ## D08 LA01_CC_P +set_location_assignment PIN_AB43 -to "fpga_syncout_1_n" ; ## C11 LA06_N +set_location_assignment PIN_AA42 -to "fpga_syncout_1_p" ; ## C10 LA06_P +set_location_assignment PIN_W44 -to "gpio[0]" ; ## H19 LA15_P +set_location_assignment PIN_Y45 -to "gpio[1]" ; ## H20 LA15_N +set_location_assignment PIN_J48 -to "gpio[2]" ; ## H22 LA19_P +set_location_assignment PIN_K49 -to "gpio[3]" ; ## H23 LA19_N +set_location_assignment PIN_E60 -to "gpio[4]" ; ## D17 LA13_P +set_location_assignment PIN_D61 -to "gpio[5]" ; ## D18 LA13_N +set_location_assignment PIN_J56 -to "gpio[6]" ; ## C18 LA14_P +set_location_assignment PIN_K57 -to "gpio[7]" ; ## C19 LA14_N +set_location_assignment PIN_W42 -to "gpio[8]" ; ## G18 LA16_P +set_location_assignment PIN_Y43 -to "gpio[9]" ; ## G19 LA16_N +set_location_assignment PIN_B59 -to "gpio[10]" ; ## G25 LA22_N +set_location_assignment PIN_T47 -to "hmc_gpio1" ; ## H17 LA11_N +set_location_assignment PIN_Y47 -to "hmc_sync" ; ## H14 LA07_N +set_location_assignment PIN_AE46 -to "irqb[0]" ; ## G12 LA08_P +set_location_assignment PIN_AD47 -to "irqb[1]" ; ## G13 LA08_N +set_location_assignment PIN_W46 -to "rstb" ; ## H13 LA07_P +set_location_assignment PIN_J52 -to "rxen[0]" ; ## C14 LA10_P +set_location_assignment PIN_K53 -to "rxen[1]" ; ## C15 LA10_N +set_location_assignment PIN_L50 -to "spi0_csb" ; ## D11 LA05_P +set_location_assignment PIN_M51 -to "spi0_miso" ; ## D12 LA05_N +set_location_assignment PIN_AB45 -to "spi0_mosi" ; ## H10 LA04_P +set_location_assignment PIN_AA44 -to "spi0_sclk" ; ## H11 LA04_N +set_location_assignment PIN_AE44 -to "spi1_csb" ; ## G15 LA12_P +set_location_assignment PIN_U46 -to "spi1_sclk" ; ## H16 LA11_P +set_location_assignment PIN_AD45 -to "spi1_sdio" ; ## G16 LA12_N +set_location_assignment PIN_D55 -to "sysref2(n)" ; ## H05 CLK0_M2C_N +set_location_assignment PIN_E54 -to "sysref2" ; ## H04 CLK0_M2C_P +set_location_assignment PIN_J54 -to "txen[0]" ; ## D14 LA09_P +set_location_assignment PIN_K55 -to "txen[1]" ; ## D15 LA09_N + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to tx_data[*] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to rx_data[*] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to tx_data_n[*] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to rx_data_n[*] + +set_instance_assignment -name HSSI_PARAMETER "txeq_main_tap=35" -to tx_data[*] +set_instance_assignment -name HSSI_PARAMETER "txeq_main_tap=35" -to tx_data_n[*] +set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_1=5" -to tx_data[*] +set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_1=5" -to tx_data_n[*] +set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_2=0" -to tx_data[*] +set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_2=0" -to tx_data_n[*] +set_instance_assignment -name HSSI_PARAMETER "txeq_post_tap_1=0" -to tx_data[*] +set_instance_assignment -name HSSI_PARAMETER "txeq_post_tap_1=0" -to tx_data_n[*] + +set_instance_assignment -name HSSI_PARAMETER "rx_ac_couple_enable=ENABLE" -to rx_data[*] +set_instance_assignment -name HSSI_PARAMETER "rx_onchip_termination=RX_ONCHIP_TERMINATION_R_2" -to rx_data[*] + +set_instance_assignment -name IO_STANDARD "1.2 V" -to agc0[0] +set_instance_assignment -name IO_STANDARD "1.2 V" -to agc0[1] +set_instance_assignment -name IO_STANDARD "1.2 V" -to agc1[0] +set_instance_assignment -name IO_STANDARD "1.2 V" -to agc1[1] +set_instance_assignment -name IO_STANDARD "1.2 V" -to agc2[0] +set_instance_assignment -name IO_STANDARD "1.2 V" -to agc2[1] +set_instance_assignment -name IO_STANDARD "1.2 V" -to agc3[0] +set_instance_assignment -name IO_STANDARD "1.2 V" -to agc3[1] +set_instance_assignment -name IO_STANDARD "1.2 V" -to gpio[0] +set_instance_assignment -name IO_STANDARD "1.2 V" -to gpio[1] +set_instance_assignment -name IO_STANDARD "1.2 V" -to gpio[2] +set_instance_assignment -name IO_STANDARD "1.2 V" -to gpio[3] +set_instance_assignment -name IO_STANDARD "1.2 V" -to gpio[4] +set_instance_assignment -name IO_STANDARD "1.2 V" -to gpio[5] +set_instance_assignment -name IO_STANDARD "1.2 V" -to gpio[6] +set_instance_assignment -name IO_STANDARD "1.2 V" -to gpio[7] +set_instance_assignment -name IO_STANDARD "1.2 V" -to gpio[8] +set_instance_assignment -name IO_STANDARD "1.2 V" -to gpio[9] +set_instance_assignment -name IO_STANDARD "1.2 V" -to gpio[10] +set_instance_assignment -name IO_STANDARD "1.2 V" -to hmc_gpio1 +set_instance_assignment -name IO_STANDARD "1.2 V" -to hmc_sync +set_instance_assignment -name IO_STANDARD "1.2 V" -to irqb[0] +set_instance_assignment -name IO_STANDARD "1.2 V" -to irqb[1] +set_instance_assignment -name IO_STANDARD "1.2 V" -to rstb +set_instance_assignment -name IO_STANDARD "1.2 V" -to rxen[0] +set_instance_assignment -name IO_STANDARD "1.2 V" -to rxen[1] +set_instance_assignment -name IO_STANDARD "1.2 V" -to spi0_csb +set_instance_assignment -name IO_STANDARD "1.2 V" -to spi0_miso +set_instance_assignment -name IO_STANDARD "1.2 V" -to spi0_mosi +set_instance_assignment -name IO_STANDARD "1.2 V" -to spi0_sclk +set_instance_assignment -name IO_STANDARD "1.2 V" -to spi1_csb +set_instance_assignment -name IO_STANDARD "1.2 V" -to spi1_sclk +set_instance_assignment -name IO_STANDARD "1.2 V" -to spi1_sdio +set_instance_assignment -name IO_STANDARD "1.2 V" -to txen[0] +set_instance_assignment -name IO_STANDARD "1.2 V" -to txen[1] + +# set optimization to get a better timing closure +set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" + +execute_flow -compile diff --git a/projects/ad9081_fmca_ebz/fm87/system_qsys.tcl b/projects/ad9081_fmca_ebz/fm87/system_qsys.tcl new file mode 100644 index 0000000000..62eb948441 --- /dev/null +++ b/projects/ad9081_fmca_ebz/fm87/system_qsys.tcl @@ -0,0 +1,60 @@ +############################################################################### +## Copyright (C) 2024 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +## ADC FIFO depth in samples per converter +set adc_fifo_samples_per_converter [expr $ad_project_params(RX_KS_PER_CHANNEL)*1024] +## DAC FIFO depth in samples per converter +set dac_fifo_samples_per_converter [expr $ad_project_params(TX_KS_PER_CHANNEL)*1024] + +source $ad_hdl_dir/projects/scripts/adi_pd.tcl +source $ad_hdl_dir/projects/common/fm87/fm87_system_qsys.tcl +source $ad_hdl_dir/projects/common/intel/dacfifo_qsys.tcl +source $ad_hdl_dir/projects/common/intel/adcfifo_qsys.tcl + +set jesd204_ref_clock [format {%.6f} $ad_project_params(REF_CLK_RATE)] +# DUT F-Tile Ref clock +add_instance systemclk systemclk_f +set_instance_parameter_value systemclk syspll_mod_0 {User Configuration} +set_instance_parameter_value systemclk syspll_refclk_src_0 {RefClk #2} +set_instance_parameter_value systemclk syspll_freq_mhz_0 200.000000 +set_instance_parameter_value systemclk refclk_fgt_output_enable_2 1 +set_instance_parameter_value systemclk refclk_fgt_freq_mhz_2 $jesd204_ref_clock + +add_interface ref_clk_fgt_2 clock sink +set_interface_property ref_clk_fgt_2 EXPORT_OF systemclk.out_refclk_fgt_2 + +add_interface ref_clk_in clock sink +set_interface_property ref_clk_in EXPORT_OF systemclk.refclk_fgt + +set TRANSCEIVER_TYPE "F-Tile" +if [info exists ad_project_dir] { + source ../../common/ad9081_fmca_ebz_qsys.tcl +} else { + source ../common/ad9081_fmca_ebz_qsys.tcl +} + +#system ID +set_instance_parameter_value axi_sysid_0 {ROM_ADDR_BITS} {9} +set_instance_parameter_value rom_sys_0 {PATH_TO_FILE} "$mem_init_sys_file_path/mem_init_sys.txt" +set_instance_parameter_value rom_sys_0 {ROM_ADDR_BITS} {9} + +set sys_cstring "RX:RATE=$ad_project_params(RX_LANE_RATE)\ +M=$ad_project_params(RX_JESD_M)\ +L=$ad_project_params(RX_JESD_L)\ +S=$ad_project_params(RX_JESD_S)\ +NP=$ad_project_params(RX_JESD_NP)\ +LINKS=$ad_project_params(RX_NUM_LINKS)\ +KS/CH=$ad_project_params(RX_KS_PER_CHANNEL)\ +TX:RATE=$ad_project_params(TX_LANE_RATE)\ +M=$ad_project_params(TX_JESD_M)\ +L=$ad_project_params(TX_JESD_L)\ +S=$ad_project_params(TX_JESD_S)\ +NP=$ad_project_params(TX_JESD_NP)\ +LINKS=$ad_project_params(TX_NUM_LINKS)\ +KS/CH=$ad_project_params(TX_KS_PER_CHANNEL)\ +REF_CLK=$ad_project_params(REF_CLK_RATE)\ +DEV_CLK=$ad_project_params(DEVICE_CLK_RATE)" + +sysid_gen_sys_init_file sys_cstring diff --git a/projects/ad9081_fmca_ebz/fm87/system_top.v b/projects/ad9081_fmca_ebz/fm87/system_top.v new file mode 100644 index 0000000000..b62a1d2bc4 --- /dev/null +++ b/projects/ad9081_fmca_ebz/fm87/system_top.v @@ -0,0 +1,376 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2024 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top #( + // Dummy parameters to workaround critical warning + parameter RX_LANE_RATE = 10, + parameter TX_LANE_RATE = 10, + parameter REF_CLK_RATE = 375, + parameter DEVICE_CLK_RATE = 375, + parameter RX_JESD_M = 8, + parameter RX_JESD_L = 8, + parameter RX_JESD_S = 1, + parameter RX_JESD_NP = 16, + parameter RX_NUM_LINKS = 1, + parameter TX_JESD_M = 8, + parameter TX_JESD_L = 8, + parameter TX_JESD_S = 1, + parameter TX_JESD_NP = 16, + parameter TX_NUM_LINKS = 1, + parameter RX_KS_PER_CHANNEL = 32, + parameter TX_KS_PER_CHANNEL = 32 +) ( + + // clock and resets + input sys_clk, + input hps_io_ref_clk, + input sys_resetn, + + // board gpio + input [12:0] fpga_gpio, + input fpga_sgpio_sync, + input fpga_sgpio_clk, + input fpga_sgpi, + output fpga_sgpo, + + // hps-emif + input emif_hps_pll_ref_clk, + output emif_hps_mem_clk_p, + output emif_hps_mem_clk_n, + output [16:0] emif_hps_mem_a, + output [ 1:0] emif_hps_mem_ba, + output emif_hps_mem_bg, + output emif_hps_mem_cke, + output emif_hps_mem_cs_n, + output emif_hps_mem_odt, + output emif_hps_mem_reset_n, + output emif_hps_mem_act_n, + output emif_hps_mem_par, + input emif_hps_mem_alert_n, + inout [ 8:0] emif_hps_mem_dqs_p, + inout [ 8:0] emif_hps_mem_dqs_n, + inout [ 8:0] emif_hps_mem_dbi_n, + inout [71:0] emif_hps_mem_dq, + input emif_hps_oct_rzq, + + // hps-emac + input hps_emac_rxclk, + input hps_emac_rxctl, + input [ 3:0] hps_emac_rxd, + output hps_emac_txclk, + output hps_emac_txctl, + output [ 3:0] hps_emac_txd, + output hps_emac_mdc, + inout hps_emac_mdio, + + // hps-sdio + output hps_sdio_clk, + inout hps_sdio_cmd, + inout [ 3:0] hps_sdio_d, + + // hps-usb + input hps_usb_clk, + input hps_usb_dir, + input hps_usb_nxt, + output hps_usb_stp, + inout [ 7:0] hps_usb_d, + + // hps-uart + input hps_uart_rx, + output hps_uart_tx, + + // hps-i2c + inout hps_i2c_sda, + inout hps_i2c_scl, + + // hps-jtag + input hps_jtag_tck, + input hps_jtag_tms, + output hps_jtag_tdo, + input hps_jtag_tdi, + + // hps-OOBE daughter card peripherals + inout hps_gpio_eth_irq, + inout hps_gpio_usb_oci, + inout [ 1:0] hps_gpio_btn, + inout [ 2:0] hps_gpio_led, + + // FMC HPC IOs + + // lane interface + input clkin6, + input clkin10, + input fpga_refclk_in, + input [RX_JESD_L-1:0] rx_data, + output [TX_JESD_L-1:0] tx_data, + input [RX_JESD_L-1:0] rx_data_n, + output [TX_JESD_L-1:0] tx_data_n, + input fpga_syncin_0, + input fpga_syncin_1_n, + input fpga_syncin_1_p, + output fpga_syncout_0, + input fpga_syncout_1_n, + input fpga_syncout_1_p, + input sysref2, + + // spi + output spi0_csb, + input spi0_miso, + output spi0_mosi, + output spi0_sclk, + output spi1_csb, + output spi1_sclk, + inout spi1_sdio, + + // gpio + input [1:0] agc0, + input [1:0] agc1, + input [1:0] agc2, + input [1:0] agc3, + input [10:0] gpio, + inout hmc_gpio1, + output hmc_sync, + input [1:0] irqb, + output rstb, + output [1:0] rxen, + output [1:0] txen +); + + // internal signals + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [ 7:0] fpga_dipsw; + wire [ 7:0] fpga_led; + + wire ninit_done; + wire sys_reset_n; + wire [43:0] stm_hw_events; + wire h2f_reset; + + wire [ 7:0] spi_csn_s; + wire spi_clk; + wire spi_mosi; + wire refclk_fgt_2; + + // Board GPIOs + assign fpga_led = gpio_o[7:0]; + assign gpio_i[ 7: 0] = gpio_o[7:0]; + assign gpio_i[15: 8] = fpga_dipsw; + assign gpio_i[17:16] = fpga_gpio[ 1:0]; // push buttons + assign gpio_i[28:18] = fpga_gpio[12:2]; + + // HMC GPIOs + assign gpio_i[44] = agc0[0]; + assign gpio_i[45] = agc0[1]; + assign gpio_i[46] = agc1[0]; + assign gpio_i[47] = agc1[1]; + assign gpio_i[48] = agc2[0]; + assign gpio_i[49] = agc2[1]; + assign gpio_i[50] = agc3[0]; + assign gpio_i[51] = agc3[1]; + assign gpio_i[52] = irqb[0]; + assign gpio_i[53] = irqb[1]; + + assign hmc_gpio1 = gpio_o[43]; + assign hmc_sync = gpio_o[54]; + assign rstb = gpio_o[55]; + assign rxen[0] = gpio_o[56]; + assign rxen[1] = gpio_o[57]; + assign txen[0] = gpio_o[58]; + assign txen[1] = gpio_o[59]; + + // Unused GPIOs + assign gpio_i[63:54] = gpio_o[63:54]; + assign gpio_i[43:32] = gpio_o[43:32]; + assign gpio_i[31:29] = gpio_o[31:29]; + + // assignmnets + assign sys_reset_n = sys_resetn & ~h2f_reset & ~ninit_done; + assign stm_hw_events = {14'b0, fpga_led, fpga_dipsw, fpga_gpio[1:0]}; + + assign spi0_csb = spi_csn_s[0]; + assign spi1_csb = spi_csn_s[1]; + + assign spi0_sclk = spi_clk; + assign spi1_sclk = spi_clk; + + assign spi0_mosi = spi_mosi; + + ad_3w_spi #( + .NUM_OF_SLAVES(1) + ) i_spi_hmc ( + .spi_csn (spi_csn_s[1]), + .spi_clk (spi_clk), + .spi_mosi (spi_mosi), + .spi_miso (spi_hmc_miso), + .spi_sdio (spi1_sdio), + .spi_dir ()); + + assign spi_miso = ~spi_csn_s[0] ? spi0_miso : + ~spi_csn_s[1] ? spi_hmc_miso : + 1'b0; + + gpio_slave i_gpio_slave ( + .reset_n (sys_reset_n), + .clk (fpga_sgpio_clk), + .sync (fpga_sgpio_sync), + .miso (fpga_sgpo), + .mosi (fpga_sgpi), + .leds (fpga_led), + .dipsw (fpga_dipsw)); + + system_bd i_system_bd ( + .sys_clk_clk (sys_clk), + .sys_hps_io_hps_osc_clk (hps_io_ref_clk), + + .sys_rst_reset_n (sys_reset_n), + .rst_ninit_done (ninit_done), + .sys_gpio_bd_in_port (gpio_i[31: 0]), + .sys_gpio_bd_out_port (gpio_o[31: 0]), + .sys_gpio_in_export (gpio_i[63:32]), + .sys_gpio_out_export (gpio_o[63:32]), + + .emif_hps_ddr_mem_ck (emif_hps_mem_clk_p), + .emif_hps_ddr_mem_ck_n (emif_hps_mem_clk_n), + .emif_hps_ddr_mem_a (emif_hps_mem_a), + .emif_hps_ddr_mem_act_n (emif_hps_mem_act_n), + .emif_hps_ddr_mem_ba (emif_hps_mem_ba), + .emif_hps_ddr_mem_bg (emif_hps_mem_bg), + .emif_hps_ddr_mem_cke (emif_hps_mem_cke), + .emif_hps_ddr_mem_cs_n (emif_hps_mem_cs_n), + .emif_hps_ddr_mem_odt (emif_hps_mem_odt), + .emif_hps_ddr_mem_reset_n (emif_hps_mem_reset_n), + .emif_hps_ddr_mem_par (emif_hps_mem_par), + .emif_hps_ddr_mem_alert_n (emif_hps_mem_alert_n), + .emif_hps_ddr_mem_dqs (emif_hps_mem_dqs_p), + .emif_hps_ddr_mem_dqs_n (emif_hps_mem_dqs_n), + .emif_hps_ddr_mem_dq (emif_hps_mem_dq), + .emif_hps_ddr_mem_dbi_n (emif_hps_mem_dbi_n), + .emif_hps_oct_rzqin (emif_hps_oct_rzq), + .emif_hps_pll_ref_clk (emif_hps_pll_ref_clk), + + .sys_hps_io_EMAC0_TX_CLK (hps_emac_txclk), + .sys_hps_io_EMAC0_TX_CTL (hps_emac_txctl), + .sys_hps_io_EMAC0_TXD0 (hps_emac_txd[0]), + .sys_hps_io_EMAC0_TXD1 (hps_emac_txd[1]), + .sys_hps_io_EMAC0_TXD2 (hps_emac_txd[2]), + .sys_hps_io_EMAC0_TXD3 (hps_emac_txd[3]), + .sys_hps_io_EMAC0_RX_CLK (hps_emac_rxclk), + .sys_hps_io_EMAC0_RX_CTL (hps_emac_rxctl), + .sys_hps_io_EMAC0_RXD0 (hps_emac_rxd[0]), + .sys_hps_io_EMAC0_RXD1 (hps_emac_rxd[1]), + .sys_hps_io_EMAC0_RXD2 (hps_emac_rxd[2]), + .sys_hps_io_EMAC0_RXD3 (hps_emac_rxd[3]), + .sys_hps_io_EMAC0_MDIO (hps_emac_mdio), + .sys_hps_io_EMAC0_MDC (hps_emac_mdc), + + .sys_hps_io_SDMMC_CCLK (hps_sdio_clk), + .sys_hps_io_SDMMC_CMD (hps_sdio_cmd), + .sys_hps_io_SDMMC_D0 (hps_sdio_d[0]), + .sys_hps_io_SDMMC_D1 (hps_sdio_d[1]), + .sys_hps_io_SDMMC_D2 (hps_sdio_d[2]), + .sys_hps_io_SDMMC_D3 (hps_sdio_d[3]), + + .sys_hps_io_USB0_CLK (hps_usb_clk), + .sys_hps_io_USB0_STP (hps_usb_stp), + .sys_hps_io_USB0_DIR (hps_usb_dir), + .sys_hps_io_USB0_NXT (hps_usb_nxt), + .sys_hps_io_USB0_DATA0 (hps_usb_d[0]), + .sys_hps_io_USB0_DATA1 (hps_usb_d[1]), + .sys_hps_io_USB0_DATA2 (hps_usb_d[2]), + .sys_hps_io_USB0_DATA3 (hps_usb_d[3]), + .sys_hps_io_USB0_DATA4 (hps_usb_d[4]), + .sys_hps_io_USB0_DATA5 (hps_usb_d[5]), + .sys_hps_io_USB0_DATA6 (hps_usb_d[6]), + .sys_hps_io_USB0_DATA7 (hps_usb_d[7]), + + .sys_hps_io_UART0_RX (hps_uart_rx), + .sys_hps_io_UART0_TX (hps_uart_tx), + + .sys_hps_io_I2C1_SDA (hps_i2c_sda), + .sys_hps_io_I2C1_SCL (hps_i2c_scl), + + .sys_hps_io_jtag_tck (hps_jtag_tck), + .sys_hps_io_jtag_tms (hps_jtag_tms), + .sys_hps_io_jtag_tdo (hps_jtag_tdo), + .sys_hps_io_jtag_tdi (hps_jtag_tdi), + //Terminate the CS_JTAG. + .sys_hps_h2f_cs_ntrst (1'b1), + .sys_hps_h2f_cs_tck (1'b1), + .sys_hps_h2f_cs_tdi (1'b1), + .sys_hps_h2f_cs_tdo (), + .sys_hps_h2f_cs_tdoen (), + .sys_hps_h2f_cs_tms (1'b1), + + .sys_hps_io_gpio1_io0 (hps_gpio_eth_irq), + .sys_hps_io_gpio1_io1 (hps_gpio_usb_oci), + .sys_hps_io_gpio1_io4 (hps_gpio_btn[0]), + .sys_hps_io_gpio1_io5 (hps_gpio_btn[1]), + .sys_hps_io_gpio1_io19 (hps_gpio_led[1]), + .sys_hps_io_gpio1_io20 (hps_gpio_led[0]), + .sys_hps_io_gpio1_io21 (hps_gpio_led[2]), + + .h2f_reset_reset (h2f_reset), + + .sys_hps_f2h_stm_hwevents (stm_hw_events), + + // FMC HPC + .sys_spi_MISO (spi_miso), + .sys_spi_MOSI (spi_mosi), + .sys_spi_SCLK (spi_clk), + .sys_spi_SS_n (spi_csn_s), + .ref_clk_in_in_refclk_fgt_2 (fpga_refclk_in), + .ref_clk_fgt_2_clk (refclk_fgt_2), + .tx_serial_data_tx_serial_data (tx_data[TX_JESD_L-1:0]), + .tx_serial_data_n_tx_serial_data_n (tx_data_n[TX_JESD_L-1:0]), + .tx_ref_clk_clk (refclk_fgt_2), + .tx_sync_export (fpga_syncin_0), + .tx_sysref_export (sysref2), + .tx_device_clk_clk (clkin6), + .rx_serial_data_rx_serial_data (rx_data[RX_JESD_L-1:0]), + .rx_serial_data_n_rx_serial_data_n (rx_data_n[RX_JESD_L-1:0]), + .rx_ref_clk_clk (refclk_fgt_2), + .rx_sync_export (fpga_syncout_0), + .rx_sysref_export (sysref2), + .rx_device_clk_clk (clkin10), + .mxfe_gpio_export ({fpga_syncout_1_n, // 14 + fpga_syncout_1_p, // 13 + fpga_syncin_1_n, // 12 + fpga_syncin_1_p, // 11 + gpio})); // 10:0 + +endmodule diff --git a/projects/ad9081_fmca_ebz/s10soc/system_project.tcl b/projects/ad9081_fmca_ebz/s10soc/system_project.tcl index 2db5902e42..3b68fc4ab4 100644 --- a/projects/ad9081_fmca_ebz/s10soc/system_project.tcl +++ b/projects/ad9081_fmca_ebz/s10soc/system_project.tcl @@ -33,6 +33,8 @@ source ../../scripts/adi_project_intel.tcl adi_project ad9081_fmca_ebz_s10soc [list \ RX_LANE_RATE [get_env_param RX_LANE_RATE 10 ] \ TX_LANE_RATE [get_env_param TX_LANE_RATE 10 ] \ + REF_CLK_RATE [get_env_param REF_CLK_RATE 250 ] \ + DEVICE_CLK_RATE [get_env_param DEVICE_CLK_RATE 250 ] \ RX_JESD_M [get_env_param RX_JESD_M 8 ] \ RX_JESD_L [get_env_param RX_JESD_L 4 ] \ RX_JESD_S [get_env_param RX_JESD_S 1 ] \ diff --git a/projects/ad9081_fmca_ebz/s10soc/system_qsys.tcl b/projects/ad9081_fmca_ebz/s10soc/system_qsys.tcl index 9fd1261c3a..a236de7c5f 100644 --- a/projects/ad9081_fmca_ebz/s10soc/system_qsys.tcl +++ b/projects/ad9081_fmca_ebz/s10soc/system_qsys.tcl @@ -13,6 +13,7 @@ source $ad_hdl_dir/projects/common/s10soc/s10soc_system_qsys.tcl source $ad_hdl_dir/projects/common/intel/dacfifo_qsys.tcl source $ad_hdl_dir/projects/common/intel/adcfifo_qsys.tcl +set TRANSCEIVER_TYPE "H-Tile" if [info exists ad_project_dir] { source ../../common/ad9081_fmca_ebz_qsys.tcl } else { diff --git a/projects/common/fm87/Makefile b/projects/common/fm87/Makefile new file mode 100644 index 0000000000..e9aa5a32ed --- /dev/null +++ b/projects/common/fm87/Makefile @@ -0,0 +1,15 @@ +#################################################################################### +## Copyright (c) 2018 - 2024 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := template_fm87 + +M_DEPS += ../../common/fm87/fm87_system_qsys.tcl +M_DEPS += ../../common/fm87/fm87_system_assign.tcl + +LIB_DEPS += axi_sysid +LIB_DEPS += sysid_rom + +include ../../scripts/project-intel.mk diff --git a/projects/common/fm87/fm87_system_assign.tcl b/projects/common/fm87/fm87_system_assign.tcl new file mode 100644 index 0000000000..e6093d48a2 --- /dev/null +++ b/projects/common/fm87/fm87_system_assign.tcl @@ -0,0 +1,359 @@ +############################################################################### +## Copyright (C) 2024 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# fm87 carrier defaults +# clocks and resets + +set_location_assignment PIN_CM29 -to sys_clk +set_location_assignment PIN_CL30 -to "sys_clk(n)" +set_location_assignment PIN_AB53 -to sys_resetn +set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to sys_clk +set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to "sys_clk(n)" +set_instance_assignment -name IO_STANDARD "1.2 V" -to sys_resetn + +# hps-mem + +set_location_assignment PIN_U34 -to emif_hps_pll_ref_clk +set_location_assignment PIN_T35 -to "emif_hps_pll_ref_clk(n)" +set_location_assignment PIN_W34 -to emif_hps_oct_rzq +set_location_assignment PIN_L32 -to emif_hps_mem_a[0] +set_location_assignment PIN_M33 -to emif_hps_mem_a[1] +set_location_assignment PIN_R32 -to emif_hps_mem_a[2] +set_location_assignment PIN_P33 -to emif_hps_mem_a[3] +set_location_assignment PIN_L30 -to emif_hps_mem_a[4] +set_location_assignment PIN_M31 -to emif_hps_mem_a[5] +set_location_assignment PIN_R30 -to emif_hps_mem_a[6] +set_location_assignment PIN_P31 -to emif_hps_mem_a[7] +set_location_assignment PIN_L28 -to emif_hps_mem_a[8] +set_location_assignment PIN_M29 -to emif_hps_mem_a[9] +set_location_assignment PIN_R28 -to emif_hps_mem_a[10] +set_location_assignment PIN_P29 -to emif_hps_mem_a[11] +set_location_assignment PIN_Y35 -to emif_hps_mem_a[12] +set_location_assignment PIN_U32 -to emif_hps_mem_a[13] +set_location_assignment PIN_T33 -to emif_hps_mem_a[14] +set_location_assignment PIN_W32 -to emif_hps_mem_a[15] +set_location_assignment PIN_Y33 -to emif_hps_mem_a[16] +set_location_assignment PIN_T31 -to emif_hps_mem_ba[0] +set_location_assignment PIN_W30 -to emif_hps_mem_ba[1] +set_location_assignment PIN_Y31 -to emif_hps_mem_bg +set_location_assignment PIN_P39 -to emif_hps_mem_act_n +set_location_assignment PIN_U30 -to emif_hps_mem_alert_n +set_location_assignment PIN_L34 -to emif_hps_mem_clk_p +set_location_assignment PIN_M35 -to emif_hps_mem_clk_n +set_location_assignment PIN_R36 -to emif_hps_mem_cke +set_location_assignment PIN_R38 -to emif_hps_mem_cs_n +set_location_assignment PIN_L36 -to emif_hps_mem_odt +set_location_assignment PIN_P35 -to emif_hps_mem_par +set_location_assignment PIN_M39 -to emif_hps_mem_reset_n +set_location_assignment PIN_G24 -to emif_hps_mem_dqs_p[0] +set_location_assignment PIN_E28 -to emif_hps_mem_dqs_p[1] +set_location_assignment PIN_G30 -to emif_hps_mem_dqs_p[2] +set_location_assignment PIN_A34 -to emif_hps_mem_dqs_p[3] +set_location_assignment PIN_AA38 -to emif_hps_mem_dqs_p[4] +set_location_assignment PIN_U38 -to emif_hps_mem_dqs_p[5] +set_location_assignment PIN_G42 -to emif_hps_mem_dqs_p[6] +set_location_assignment PIN_L42 -to emif_hps_mem_dqs_p[7] +set_location_assignment PIN_AA32 -to emif_hps_mem_dqs_p[8] +set_location_assignment PIN_F25 -to emif_hps_mem_dqs_n[0] +set_location_assignment PIN_D29 -to emif_hps_mem_dqs_n[1] +set_location_assignment PIN_F31 -to emif_hps_mem_dqs_n[2] +set_location_assignment PIN_B35 -to emif_hps_mem_dqs_n[3] +set_location_assignment PIN_AB39 -to emif_hps_mem_dqs_n[4] +set_location_assignment PIN_T39 -to emif_hps_mem_dqs_n[5] +set_location_assignment PIN_F43 -to emif_hps_mem_dqs_n[6] +set_location_assignment PIN_M43 -to emif_hps_mem_dqs_n[7] +set_location_assignment PIN_AB33 -to emif_hps_mem_dqs_n[8] +set_location_assignment PIN_J24 -to emif_hps_mem_dbi_n[0] +set_location_assignment PIN_A28 -to emif_hps_mem_dbi_n[1] +set_location_assignment PIN_J30 -to emif_hps_mem_dbi_n[2] +set_location_assignment PIN_E34 -to emif_hps_mem_dbi_n[3] +set_location_assignment PIN_AE38 -to emif_hps_mem_dbi_n[4] +set_location_assignment PIN_W38 -to emif_hps_mem_dbi_n[5] +set_location_assignment PIN_J42 -to emif_hps_mem_dbi_n[6] +set_location_assignment PIN_R42 -to emif_hps_mem_dbi_n[7] +set_location_assignment PIN_AE32 -to emif_hps_mem_dbi_n[8] +set_location_assignment PIN_G26 -to emif_hps_mem_dq[0] +set_location_assignment PIN_F27 -to emif_hps_mem_dq[1] +set_location_assignment PIN_J26 -to emif_hps_mem_dq[2] +set_location_assignment PIN_K27 -to emif_hps_mem_dq[3] +set_location_assignment PIN_G22 -to emif_hps_mem_dq[4] +set_location_assignment PIN_F23 -to emif_hps_mem_dq[5] +set_location_assignment PIN_J22 -to emif_hps_mem_dq[6] +set_location_assignment PIN_K23 -to emif_hps_mem_dq[7] +set_location_assignment PIN_A30 -to emif_hps_mem_dq[8] +set_location_assignment PIN_B31 -to emif_hps_mem_dq[9] +set_location_assignment PIN_D31 -to emif_hps_mem_dq[10] +set_location_assignment PIN_E30 -to emif_hps_mem_dq[11] +set_location_assignment PIN_A26 -to emif_hps_mem_dq[12] +set_location_assignment PIN_B27 -to emif_hps_mem_dq[13] +set_location_assignment PIN_E26 -to emif_hps_mem_dq[14] +set_location_assignment PIN_D27 -to emif_hps_mem_dq[15] +set_location_assignment PIN_G32 -to emif_hps_mem_dq[16] +set_location_assignment PIN_K33 -to emif_hps_mem_dq[17] +set_location_assignment PIN_J32 -to emif_hps_mem_dq[18] +set_location_assignment PIN_F33 -to emif_hps_mem_dq[19] +set_location_assignment PIN_G28 -to emif_hps_mem_dq[20] +set_location_assignment PIN_F29 -to emif_hps_mem_dq[21] +set_location_assignment PIN_J28 -to emif_hps_mem_dq[22] +set_location_assignment PIN_K29 -to emif_hps_mem_dq[23] +set_location_assignment PIN_A36 -to emif_hps_mem_dq[24] +set_location_assignment PIN_B37 -to emif_hps_mem_dq[25] +set_location_assignment PIN_E36 -to emif_hps_mem_dq[26] +set_location_assignment PIN_D37 -to emif_hps_mem_dq[27] +set_location_assignment PIN_A32 -to emif_hps_mem_dq[28] +set_location_assignment PIN_B33 -to emif_hps_mem_dq[29] +set_location_assignment PIN_E32 -to emif_hps_mem_dq[30] +set_location_assignment PIN_D33 -to emif_hps_mem_dq[31] +set_location_assignment PIN_AE40 -to emif_hps_mem_dq[32] +set_location_assignment PIN_AA40 -to emif_hps_mem_dq[33] +set_location_assignment PIN_AD41 -to emif_hps_mem_dq[34] +set_location_assignment PIN_AB41 -to emif_hps_mem_dq[35] +set_location_assignment PIN_AD37 -to emif_hps_mem_dq[36] +set_location_assignment PIN_AE36 -to emif_hps_mem_dq[37] +set_location_assignment PIN_AB37 -to emif_hps_mem_dq[38] +set_location_assignment PIN_AA36 -to emif_hps_mem_dq[39] +set_location_assignment PIN_T41 -to emif_hps_mem_dq[40] +set_location_assignment PIN_U40 -to emif_hps_mem_dq[41] +set_location_assignment PIN_Y41 -to emif_hps_mem_dq[42] +set_location_assignment PIN_W40 -to emif_hps_mem_dq[43] +set_location_assignment PIN_U36 -to emif_hps_mem_dq[44] +set_location_assignment PIN_T37 -to emif_hps_mem_dq[45] +set_location_assignment PIN_W36 -to emif_hps_mem_dq[46] +set_location_assignment PIN_Y37 -to emif_hps_mem_dq[47] +set_location_assignment PIN_F45 -to emif_hps_mem_dq[48] +set_location_assignment PIN_G44 -to emif_hps_mem_dq[49] +set_location_assignment PIN_K45 -to emif_hps_mem_dq[50] +set_location_assignment PIN_J44 -to emif_hps_mem_dq[51] +set_location_assignment PIN_J40 -to emif_hps_mem_dq[52] +set_location_assignment PIN_K41 -to emif_hps_mem_dq[53] +set_location_assignment PIN_G40 -to emif_hps_mem_dq[54] +set_location_assignment PIN_F41 -to emif_hps_mem_dq[55] +set_location_assignment PIN_L44 -to emif_hps_mem_dq[56] +set_location_assignment PIN_P45 -to emif_hps_mem_dq[57] +set_location_assignment PIN_M45 -to emif_hps_mem_dq[58] +set_location_assignment PIN_R44 -to emif_hps_mem_dq[59] +set_location_assignment PIN_L40 -to emif_hps_mem_dq[60] +set_location_assignment PIN_M41 -to emif_hps_mem_dq[61] +set_location_assignment PIN_R40 -to emif_hps_mem_dq[62] +set_location_assignment PIN_P41 -to emif_hps_mem_dq[63] +set_location_assignment PIN_AA34 -to emif_hps_mem_dq[64] +set_location_assignment PIN_AB35 -to emif_hps_mem_dq[65] +set_location_assignment PIN_AE34 -to emif_hps_mem_dq[66] +set_location_assignment PIN_AD35 -to emif_hps_mem_dq[67] +set_location_assignment PIN_AA30 -to emif_hps_mem_dq[68] +set_location_assignment PIN_AB31 -to emif_hps_mem_dq[69] +set_location_assignment PIN_AE30 -to emif_hps_mem_dq[70] +set_location_assignment PIN_AD31 -to emif_hps_mem_dq[71] + +# hps-emac + +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_emac_rxclk +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_emac_rxctl +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_emac_rxd[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_emac_rxd[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_emac_rxd[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_emac_rxd[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_emac_txclk +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_emac_txctl +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_emac_txd[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_emac_txd[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_emac_txd[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_emac_txd[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_emac_mdio +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_emac_mdc + +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to hps_emac_txclk +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hps_emac_txctl +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hps_emac_txd[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hps_emac_txd[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hps_emac_txd[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hps_emac_txd[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to hps_emac_mdio +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to hps_emac_mdc +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_emac_rxclk +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_emac_rxctl +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_emac_rxd[0] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_emac_rxd[1] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_emac_rxd[2] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_emac_rxd[3] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_emac_mdio + +set_instance_assignment -name AUTO_OPEN_DRAIN_PINS ON -to hps_emac_mdio + +# hps-sdio + +set_location_assignment PIN_T21 -to hps_io_ref_clk + +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_cmd +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_clk +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_d[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_d[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_d[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_d[3] + +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hps_sdio_cmd +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hps_sdio_clk +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hps_sdio_d[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hps_sdio_d[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hps_sdio_d[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hps_sdio_d[3] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_sdio_cmd +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_sdio_d[0] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_sdio_d[1] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_sdio_d[2] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_sdio_d[3] + +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_io_ref_clk +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_jtag_tck +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_jtag_tms +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_jtag_tdo +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_jtag_tdi +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to hps_jtag_tdo +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_jtag_tck +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_jtag_tms +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_jtag_tdi + +# hps-usb + +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_clk +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_dir +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_stp +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_nxt +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d[7] + +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hps_usb_stp +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_usb_clk +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_usb_dir +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_usb_nxt + +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hps_usb_d[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hps_usb_d[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hps_usb_d[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hps_usb_d[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hps_usb_d[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hps_usb_d[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hps_usb_d[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hps_usb_d[7] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_usb_d[0] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_usb_d[1] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_usb_d[2] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_usb_d[3] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_usb_d[4] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_usb_d[5] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_usb_d[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_usb_d[7] + +# hps-uart + +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_uart_tx +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_uart_rx + +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to hps_uart_tx +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_uart_rx + +# hps-i2c + +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_i2c_sda +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_i2c_scl + +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to hps_i2c_sda +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to hps_i2c_scl +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_i2c_sda +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_i2c_scl +set_instance_assignment -name AUTO_OPEN_DRAIN_PINS ON -to hps_i2c_sda +set_instance_assignment -name AUTO_OPEN_DRAIN_PINS ON -to hps_i2c_scl + +# hps-gpio + +set_instance_assignment -name IO_STANDARD "1.8V" -to hps_gpio_eth_irq +set_instance_assignment -name IO_STANDARD "1.8V" -to hps_gpio_usb_oci +set_instance_assignment -name IO_STANDARD "1.8V" -to hps_gpio_btn[0] +set_instance_assignment -name IO_STANDARD "1.8V" -to hps_gpio_btn[1] +set_instance_assignment -name IO_STANDARD "1.8V" -to hps_gpio_led[0] +set_instance_assignment -name IO_STANDARD "1.8V" -to hps_gpio_led[1] +set_instance_assignment -name IO_STANDARD "1.8V" -to hps_gpio_led[2] + +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to hps_gpio_eth_irq +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to hps_gpio_usb_oci +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to hps_gpio_btn[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to hps_gpio_btn[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to hps_gpio_led[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to hps_gpio_led[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to hps_gpio_led[2] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_gpio_eth_irq +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_gpio_usb_oci +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_gpio_btn[0] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_gpio_btn[1] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_gpio_led[0] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_gpio_led[1] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_gpio_led[2] + +# gpio + +set_location_assignment PIN_CY47 -to fpga_gpio[0] +set_location_assignment PIN_CW48 -to fpga_gpio[1] +set_location_assignment PIN_CT47 -to fpga_gpio[2] +set_location_assignment PIN_CU48 -to fpga_gpio[3] +set_location_assignment PIN_CY49 -to fpga_gpio[4] +set_location_assignment PIN_CW50 -to fpga_gpio[5] +set_location_assignment PIN_CT49 -to fpga_gpio[6] +set_location_assignment PIN_CU50 -to fpga_gpio[7] +set_location_assignment PIN_CY51 -to fpga_gpio[8] +set_location_assignment PIN_CW52 -to fpga_gpio[9] +set_location_assignment PIN_CT51 -to fpga_gpio[10] +set_location_assignment PIN_CU52 -to fpga_gpio[11] +set_location_assignment PIN_DA50 -to fpga_gpio[12] + +set_location_assignment PIN_Y49 -to fpga_sgpio_sync +set_location_assignment PIN_W48 -to fpga_sgpio_clk +set_location_assignment PIN_T49 -to fpga_sgpi +set_location_assignment PIN_U48 -to fpga_sgpo + +set_instance_assignment -name IO_STANDARD "1.2 V" -to fpga_gpio[0] +set_instance_assignment -name IO_STANDARD "1.2 V" -to fpga_gpio[1] +set_instance_assignment -name IO_STANDARD "1.2 V" -to fpga_gpio[2] +set_instance_assignment -name IO_STANDARD "1.2 V" -to fpga_gpio[3] +set_instance_assignment -name IO_STANDARD "1.2 V" -to fpga_gpio[4] +set_instance_assignment -name IO_STANDARD "1.2 V" -to fpga_gpio[5] +set_instance_assignment -name IO_STANDARD "1.2 V" -to fpga_gpio[6] +set_instance_assignment -name IO_STANDARD "1.2 V" -to fpga_gpio[7] +set_instance_assignment -name IO_STANDARD "1.2 V" -to fpga_gpio[8] +set_instance_assignment -name IO_STANDARD "1.2 V" -to fpga_gpio[9] +set_instance_assignment -name IO_STANDARD "1.2 V" -to fpga_gpio[10] +set_instance_assignment -name IO_STANDARD "1.2 V" -to fpga_gpio[11] +set_instance_assignment -name IO_STANDARD "1.2 V" -to fpga_gpio[12] + +set_instance_assignment -name IO_STANDARD "1.2 V" -to fpga_sgpio_sync +set_instance_assignment -name IO_STANDARD "1.2 V" -to fpga_sgpio_clk +set_instance_assignment -name IO_STANDARD "1.2 V" -to fpga_sgpi +set_instance_assignment -name IO_STANDARD "1.2 V" -to fpga_sgpo + +# Agilex development kit's global assignments + +set_global_assignment -name HPS_INITIALIZATION "HPS FIRST" +set_global_assignment -name HPS_DAP_SPLIT_MODE "SDM PINS" + +set_global_assignment -name INI_VARS "ASM_ENABLE_ADVANCED_DEVICES=ON;" +set_global_assignment -name USE_PWRMGT_SCL SDM_IO0 +set_global_assignment -name USE_HPS_COLD_RESET SDM_IO11 +set_global_assignment -name USE_PWRMGT_SDA SDM_IO12 +set_global_assignment -name USE_CONF_DONE SDM_IO16 +set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER" +set_global_assignment -name PWRMGT_BUS_SPEED_MODE "100 KHZ" +set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE LTC3888 +set_global_assignment -name NUMBER_OF_SLAVE_DEVICE 1 +set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 62 +set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT" +set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-12" +set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS + +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHz diff --git a/projects/common/fm87/fm87_system_qsys.tcl b/projects/common/fm87/fm87_system_qsys.tcl new file mode 100644 index 0000000000..b346c60cb8 --- /dev/null +++ b/projects/common/fm87/fm87_system_qsys.tcl @@ -0,0 +1,432 @@ +############################################################################### +## Copyright (C) 2024 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# fm87 carrier qsys + +set system_type "Agilex 7" + +# clocks & reset + +add_instance sys_clk clock_source +add_interface sys_clk clock sink +set_interface_property sys_clk EXPORT_OF sys_clk.clk_in +add_interface sys_rst reset sink +set_interface_property sys_rst EXPORT_OF sys_clk.clk_in_reset +set_instance_parameter_value sys_clk {clockFrequency} {100000000.0} +set_instance_parameter_value sys_clk {clockFrequencyKnown} {1} +set_instance_parameter_value sys_clk {resetSynchronousEdges} {DEASSERT} + +add_instance agilex_reset altera_s10_user_rst_clkgate +add_interface rst_ninit_done reset source +set_interface_property rst EXPORT_OF agilex_reset.ninit_done + +# hps +# round-about way - qsys-script doesn't support {*}? + +variable hps_io_list + +proc set_hps_io {io_index io_type} { + + global hps_io_list + lappend hps_io_list $io_type +} + +set_hps_io HPS_IOA_1 USB0:CLK +set_hps_io HPS_IOA_2 USB0:STP +set_hps_io HPS_IOA_3 USB0:DIR +set_hps_io HPS_IOA_4 USB0:DATA0 +set_hps_io HPS_IOA_5 USB0:DATA1 +set_hps_io HPS_IOA_6 USB0:NXT +set_hps_io HPS_IOA_7 USB0:DATA2 +set_hps_io HPS_IOA_8 USB0:DATA3 +set_hps_io HPS_IOA_9 USB0:DATA4 +set_hps_io HPS_IOA_10 USB0:DATA5 +set_hps_io HPS_IOA_11 USB0:DATA6 +set_hps_io HPS_IOA_12 USB0:DATA7 +set_hps_io HPS_IOA_13 EMAC0:TX_CLK +set_hps_io HPS_IOA_14 EMAC0:TX_CTL +set_hps_io HPS_IOA_15 EMAC0:RX_CLK +set_hps_io HPS_IOA_16 EMAC0:RX_CTL +set_hps_io HPS_IOA_17 EMAC0:TXD0 +set_hps_io HPS_IOA_18 EMAC0:TXD1 +set_hps_io HPS_IOA_19 EMAC0:RXD0 +set_hps_io HPS_IOA_20 EMAC0:RXD1 +set_hps_io HPS_IOA_21 EMAC0:TXD2 +set_hps_io HPS_IOA_22 EMAC0:TXD3 +set_hps_io HPS_IOA_23 EMAC0:RXD2 +set_hps_io HPS_IOA_24 EMAC0:RXD3 +set_hps_io HPS_IOB_1 GPIO +set_hps_io HPS_IOB_2 GPIO +set_hps_io HPS_IOB_3 UART0:TX +set_hps_io HPS_IOB_4 UART0:RX +set_hps_io HPS_IOB_5 GPIO +set_hps_io HPS_IOB_6 GPIO +set_hps_io HPS_IOB_7 I2C1:SDA +set_hps_io HPS_IOB_8 I2C1:SCL +set_hps_io HPS_IOB_9 JTAG:TCK +set_hps_io HPS_IOB_10 JTAG:TMS +set_hps_io HPS_IOB_11 JTAG:TDO +set_hps_io HPS_IOB_12 JTAG:TDI +set_hps_io HPS_IOB_13 SDMMC:D0 +set_hps_io HPS_IOB_14 SDMMC:CMD +set_hps_io HPS_IOB_15 SDMMC:CCLK +set_hps_io HPS_IOB_16 SDMMC:D1 +set_hps_io HPS_IOB_17 SDMMC:D2 +set_hps_io HPS_IOB_18 SDMMC:D3 +set_hps_io HPS_IOB_19 HPS_OSC_CLK +set_hps_io HPS_IOB_20 GPIO +set_hps_io HPS_IOB_21 GPIO +set_hps_io HPS_IOB_22 GPIO +set_hps_io HPS_IOB_23 MDIO0:MDIO +set_hps_io HPS_IOB_24 MDIO0:MDC + +add_instance sys_hps intel_agilex_hps +set_instance_parameter_value sys_hps CLK_GPIO_SOURCE {1} +set_instance_parameter_value sys_hps CLK_EMACA_SOURCE {1} +set_instance_parameter_value sys_hps CLK_EMACB_SOURCE {1} +set_instance_parameter_value sys_hps CLK_EMAC_PTP_SOURCE {1} +set_instance_parameter_value sys_hps CLK_PSI_SOURCE {1} +set_instance_parameter_value sys_hps EMAC0_Mode {RGMII_with_MDIO} +set_instance_parameter_value sys_hps EMAC0_PinMuxing {IO} +set_instance_parameter_value sys_hps EMIF_CONDUIT_Enable {1} +set_instance_parameter_value sys_hps EMIF_DDR_WIDTH {64} +set_instance_parameter_value sys_hps F2SINTERRUPT_Enable {1} +set_instance_parameter_value sys_hps F2S_ADDRESS_WIDTH {32} +set_instance_parameter_value sys_hps F2S_Width {5} +set_instance_parameter_value sys_hps FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK {100} +set_instance_parameter_value sys_hps FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK {100} +set_instance_parameter_value sys_hps FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_GTX_CLK {100} +set_instance_parameter_value sys_hps FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK {100} +set_instance_parameter_value sys_hps FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK {100} +set_instance_parameter_value sys_hps FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC0_CLK {100} +set_instance_parameter_value sys_hps FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC1_CLK {100} +set_instance_parameter_value sys_hps FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC2_CLK {100} +set_instance_parameter_value sys_hps FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDMMC_CCLK {100} +set_instance_parameter_value sys_hps FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT {100} +set_instance_parameter_value sys_hps FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT {100} +set_instance_parameter_value sys_hps HPS_IO_Enable $hps_io_list +set_instance_parameter_value sys_hps I2C1_Mode {default} +set_instance_parameter_value sys_hps I2C1_PinMuxing {IO} +set_instance_parameter_value sys_hps IO_OUTPUT_DELAY12 {45} +set_instance_parameter_value sys_hps LWH2F_ADDRESS_WIDTH {21} +set_instance_parameter_value sys_hps LWH2F_Enable {1} +set_instance_parameter_value sys_hps MPU_EVENTS_Enable {0} +set_instance_parameter_value sys_hps S2F_ADDRESS_WIDTH {32} +set_instance_parameter_value sys_hps S2F_Width {3} +set_instance_parameter_value sys_hps SDMMC_Mode {4-bit} +set_instance_parameter_value sys_hps SDMMC_PinMuxing {IO} +set_instance_parameter_value sys_hps STM_Enable {1} +set_instance_parameter_value sys_hps UART0_Mode {No_flow_control} +set_instance_parameter_value sys_hps UART0_PinMuxing {IO} +set_instance_parameter_value sys_hps USB0_Mode {default} +set_instance_parameter_value sys_hps USB0_PinMuxing {IO} +set_instance_parameter_value sys_hps watchdog_reset {1} +# TODO: See if these are necessary +set_instance_parameter_value sys_hps W_RESET_ACTION {0} +set_instance_parameter_value sys_hps IO_INPUT_DELAY0 {126} +set_instance_parameter_value sys_hps IO_INPUT_DELAY1 {126} +set_instance_parameter_value sys_hps IO_INPUT_DELAY2 {126} +set_instance_parameter_value sys_hps IO_INPUT_DELAY3 {126} +set_instance_parameter_value sys_hps IO_INPUT_DELAY4 {126} +set_instance_parameter_value sys_hps IO_INPUT_DELAY5 {126} +set_instance_parameter_value sys_hps IO_INPUT_DELAY6 {126} +set_instance_parameter_value sys_hps IO_INPUT_DELAY7 {126} +set_instance_parameter_value sys_hps IO_INPUT_DELAY8 {126} +set_instance_parameter_value sys_hps IO_INPUT_DELAY9 {126} +set_instance_parameter_value sys_hps IO_INPUT_DELAY10 {126} +set_instance_parameter_value sys_hps IO_INPUT_DELAY11 {126} + +set_instance_parameter_value sys_hps H2F_USER0_CLK_Enable {1} +set_instance_parameter_value sys_hps H2F_USER0_CLK_FREQ {250} +set_instance_parameter_value sys_hps CLK_SDMMC_SOURCE {1} + +add_interface h2f_reset reset source +set_interface_property h2f_reset EXPORT_OF sys_hps.h2f_reset + +add_connection sys_clk.clk sys_hps.h2f_lw_axi_clock +add_connection sys_clk.clk_reset sys_hps.h2f_lw_axi_reset +add_connection sys_clk.clk sys_hps.f2h_axi_clock +add_connection sys_clk.clk_reset sys_hps.f2h_axi_reset +add_connection sys_clk.clk sys_hps.h2f_axi_clock +add_connection sys_clk.clk_reset sys_hps.h2f_axi_reset +add_interface sys_hps_io conduit end +set_interface_property sys_hps_io EXPORT_OF sys_hps.hps_io + +# emif_callbus + +add_instance emif_calbus_0 altera_emif_cal +set_instance_parameter_value emif_calbus_0 DIAG_ENABLE_JTAG_UART {0} +set_instance_parameter_value emif_calbus_0 DIAG_EXPORT_SEQ_AVALON_SLAVE {CAL_DEBUG_EXPORT_MODE_DISABLED} +set_instance_parameter_value emif_calbus_0 DIAG_EXPORT_VJI {0} +set_instance_parameter_value emif_calbus_0 DIAG_EXTRA_CONFIGS {} +set_instance_parameter_value emif_calbus_0 DIAG_SIM_CAL_MODE_ENUM {SIM_CAL_MODE_SKIP} +set_instance_parameter_value emif_calbus_0 DIAG_SIM_VERBOSE {0} +set_instance_parameter_value emif_calbus_0 DIAG_SYNTH_FOR_SIM {0} +set_instance_parameter_value emif_calbus_0 NUM_CALBUS_INTERFACE {1} +set_instance_parameter_value emif_calbus_0 SHORT_QSYS_INTERFACE_NAMES {1} + +# common dma interfaces + +add_instance sys_dma_clk clock_source +set_instance_parameter_value sys_dma_clk {resetSynchronousEdges} {DEASSERT} +set_instance_parameter_value sys_dma_clk {clockFrequencyKnown} {true} +add_connection sys_clk.clk_reset sys_dma_clk.clk_in_reset +add_connection sys_hps.h2f_user0_clock sys_dma_clk.clk_in + +# sys-id + +add_instance sys_id altera_avalon_sysid_qsys +set_instance_parameter_value sys_id {id} {0x00000100} +add_connection sys_clk.clk_reset sys_id.reset +add_connection sys_clk.clk sys_id.clk + +# hps emif + +add_instance emif_hps altera_emif_fm_hps +set_instance_parameter_value emif_hps PROTOCOL_ENUM {PROTOCOL_DDR4} +set_instance_parameter_value emif_hps PHY_DDR4_RATE_ENUM {RATE_QUARTER} +set_instance_parameter_value emif_hps MEM_DDR4_FORMAT_ENUM {MEM_FORMAT_DISCRETE} +set_instance_parameter_value emif_hps MEM_DDR4_DQ_WIDTH {72} +set_instance_parameter_value emif_hps MEM_DDR4_TCL {0} +set_instance_parameter_value emif_hps MEM_DDR4_WTCL {0} +set_instance_parameter_value emif_hps MEM_DDR4_ROW_ADDR_WIDTH {17} +set_instance_parameter_value emif_hps MEM_DDR4_BANK_ADDR_WIDTH {2} +set_instance_parameter_value emif_hps MEM_DDR4_BANK_GROUP_WIDTH {1} +set_instance_parameter_value emif_hps MEM_DDR4_NUM_OF_DIMMS {1} +set_instance_parameter_value emif_hps MEM_DDR4_RANKS_PER_DIMM {1} +set_instance_parameter_value emif_hps MEM_DDR4_CK_WIDTH {1} +set_instance_parameter_value emif_hps MEM_DDR4_RTT_WR_ENUM {DDR4_RTT_WR_ODT_DISABLED} +set_instance_parameter_value emif_hps MEM_DDR4_DRV_STR_ENUM {DDR4_DRV_STR_RZQ_7} +set_instance_parameter_value emif_hps MEM_DDR4_RTT_NOM_ENUM {DDR4_RTT_NOM_ODT_DISABLED} +set_instance_parameter_value emif_hps MEM_DDR4_RTT_PARK {DDR4_RTT_PARK_RZQ_4} +set_instance_parameter_value emif_hps MEM_DDR4_USE_DEFAULT_ODT {false} +set_instance_parameter_value emif_hps MEM_DDR4_R_ODT0_1X1 {off} +set_instance_parameter_value emif_hps MEM_DDR4_W_ODT0_1X1 {off} +set_instance_parameter_value emif_hps MEM_DDR4_DM_EN {true} +set_instance_parameter_value emif_hps MEM_DDR4_READ_DBI {true} +set_instance_parameter_value emif_hps MEM_DDR4_WRITE_DBI {false} +set_instance_parameter_value emif_hps PHY_DDR4_CONFIG_ENUM {CONFIG_PHY_AND_HARD_CTRL} +set_instance_parameter_value emif_hps PHY_DDR4_USER_PING_PONG_EN {false} +set_instance_parameter_value emif_hps PHY_DDR4_DEFAULT_REF_CLK_FREQ {false} +set_instance_parameter_value emif_hps PHY_DDR4_USER_REF_CLK_FREQ_MHZ {166.666} +set_instance_parameter_value emif_hps CTRL_DDR4_ECC_EN {1} +set_instance_parameter_value emif_hps CTRL_DDR4_ECC_AUTO_CORRECTION_EN {1} +set_instance_parameter_value emif_hps PHY_DDR4_DEFAULT_IO {false} +set_instance_parameter_value emif_hps PHY_DDR4_USER_AC_IO_STD_ENUM {IO_STD_SSTL_12} +set_instance_parameter_value emif_hps PHY_DDR4_USER_CK_IO_STD_ENUM {IO_STD_SSTL_12} +set_instance_parameter_value emif_hps PHY_DDR4_USER_DATA_IO_STD_ENUM {IO_STD_POD_12} +set_instance_parameter_value emif_hps PHY_DDR4_USER_AC_MODE_ENUM {OUT_OCT_40_CAL} +set_instance_parameter_value emif_hps PHY_DDR4_USER_CK_MODE_ENUM {OUT_OCT_40_CAL} +set_instance_parameter_value emif_hps PHY_DDR4_USER_DATA_OUT_MODE_ENUM {OUT_OCT_34_CAL} +set_instance_parameter_value emif_hps PHY_DDR4_USER_DATA_IN_MODE_ENUM {IN_OCT_60_CAL} +set_instance_parameter_value emif_hps PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM {IO_STD_TRUE_DIFF_SIGNALING} +set_instance_parameter_value emif_hps PHY_DDR4_USER_RZQ_IO_STD_ENUM {IO_STD_CMOS_12} +set_instance_parameter_value emif_hps PHY_DDR4_MEM_CLK_FREQ_MHZ {1333.33} +set_instance_parameter_value emif_hps DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE {CAL_DEBUG_EXPORT_MODE_DISABLED} +set_instance_parameter_value emif_hps DIAG_ENABLE_JTAG_UART {false} +set_instance_parameter_value emif_hps DIAG_HMC_HRC {OFF} +set_instance_parameter_value emif_hps DIAG_SOFT_NIOS_MODE {SOFT_NIOS_MODE_DISABLED} +set_instance_parameter_value emif_hps MEM_DDR4_SPEEDBIN_ENUM {DDR4_SPEEDBIN_3200} +set_instance_parameter_value emif_hps MEM_DDR4_TCCD_L_CYC {7} +set_instance_parameter_value emif_hps MEM_DDR4_TCCD_S_CYC {4} +set_instance_parameter_value emif_hps MEM_DDR4_TCL {23} +set_instance_parameter_value emif_hps MEM_DDR4_TDIVW_DJ_CYC {0.1} +set_instance_parameter_value emif_hps MEM_DDR4_TDIVW_TOTAL_UI {0.23} +set_instance_parameter_value emif_hps MEM_DDR4_TDQSCK_PS {160} +set_instance_parameter_value emif_hps MEM_DDR4_TDQSQ_PS {66} +set_instance_parameter_value emif_hps MEM_DDR4_TDQSQ_UI {0.2} +set_instance_parameter_value emif_hps MEM_DDR4_TDQSS_CYC {0.27} +set_instance_parameter_value emif_hps MEM_DDR4_TDSH_CYC {0.18} +set_instance_parameter_value emif_hps MEM_DDR4_TDSS_CYC {0.18} +set_instance_parameter_value emif_hps MEM_DDR4_TDVWP_UI {0.72} +set_instance_parameter_value emif_hps MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA {0} +set_instance_parameter_value emif_hps MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE {DDR4_TEMP_CONTROLLED_RFSH_NORMAL} +set_instance_parameter_value emif_hps MEM_DDR4_TEMP_SENSOR_READOUT {0} +set_instance_parameter_value emif_hps MEM_DDR4_TFAW_DLR_CYC {16} +set_instance_parameter_value emif_hps MEM_DDR4_TFAW_NS {30.0} +set_instance_parameter_value emif_hps MEM_DDR4_TIH_DC_MV {65} +set_instance_parameter_value emif_hps MEM_DDR4_TIH_PS {65} +set_instance_parameter_value emif_hps MEM_DDR4_TINIT_US {500} +set_instance_parameter_value emif_hps MEM_DDR4_TIS_AC_MV {90} +set_instance_parameter_value emif_hps MEM_DDR4_TIS_PS {40} +set_instance_parameter_value emif_hps MEM_DDR4_TMRD_CK_CYC {8} +set_instance_parameter_value emif_hps MEM_DDR4_TQH_CYC {0.38} +set_instance_parameter_value emif_hps MEM_DDR4_TQH_UI {0.7} +set_instance_parameter_value emif_hps MEM_DDR4_TQSH_CYC {0.4} +set_instance_parameter_value emif_hps MEM_DDR4_TRAS_NS {32.0} +set_instance_parameter_value emif_hps MEM_DDR4_TRCD_NS {13.75} +set_instance_parameter_value emif_hps MEM_DDR4_TREFI_US {7.8} +set_instance_parameter_value emif_hps MEM_DDR4_TRFC_DLR_NS {350.0} +set_instance_parameter_value emif_hps MEM_DDR4_TRFC_NS {350.0} +set_instance_parameter_value emif_hps MEM_DDR4_TRP_NS {13.75} +set_instance_parameter_value emif_hps MEM_DDR4_TRRD_DLR_CYC {4} +set_instance_parameter_value emif_hps MEM_DDR4_TRRD_L_CYC {9} +set_instance_parameter_value emif_hps MEM_DDR4_TRRD_S_CYC {8} +set_instance_parameter_value emif_hps MEM_DDR4_TWLH_CYC {0.13} +set_instance_parameter_value emif_hps MEM_DDR4_TWLH_PS {0.0} +set_instance_parameter_value emif_hps MEM_DDR4_TWLS_CYC {0.13} +set_instance_parameter_value emif_hps MEM_DDR4_TWLS_PS {0.0} +set_instance_parameter_value emif_hps MEM_DDR4_TWR_NS {15.0} +set_instance_parameter_value emif_hps MEM_DDR4_TWTR_L_CYC {10} +set_instance_parameter_value emif_hps MEM_DDR4_TWTR_S_CYC {4} +set_instance_parameter_value emif_hps MEM_DDR4_USER_VREFDQ_TRAINING_RANGE {DDR4_VREFDQ_TRAINING_RANGE_1} +set_instance_parameter_value emif_hps MEM_DDR4_USER_VREFDQ_TRAINING_VALUE {56.0} +set_instance_parameter_value emif_hps MEM_DDR4_USE_DEFAULT_ODT {1} +set_instance_parameter_value emif_hps MEM_DDR4_VDIVW_TOTAL {110} +set_instance_parameter_value emif_hps MEM_DDR4_WRITE_CRC {0} +set_instance_parameter_value emif_hps MEM_DDR4_WRITE_DBI {0} +set_instance_parameter_value emif_hps MEM_DDR4_WRITE_PREAMBLE {1} +set_instance_parameter_value emif_hps MEM_DDR4_WTCL {18} + +# system id + +add_instance axi_sysid_0 axi_sysid +add_instance rom_sys_0 sysid_rom + +add_connection axi_sysid_0.if_rom_addr rom_sys_0.if_rom_addr +add_connection rom_sys_0.if_rom_data axi_sysid_0.if_sys_rom_data +add_connection sys_clk.clk rom_sys_0.if_clk +add_connection sys_clk.clk axi_sysid_0.s_axi_clock +add_connection sys_clk.clk_reset axi_sysid_0.s_axi_reset + +add_interface pr_rom_data_nc conduit end +set_interface_property pr_rom_data_nc EXPORT_OF axi_sysid_0.if_pr_rom_data + +# jtag + +add_instance fpga_m altera_jtag_avalon_master +add_instance hps_m altera_jtag_avalon_master + +add_connection sys_clk.clk fpga_m.clk +add_connection sys_clk.clk hps_m.clk +add_connection sys_clk.clk_reset fpga_m.clk_reset +add_connection sys_clk.clk_reset hps_m.clk_reset + +set_interface_property fpga_m_master EXPORT_OF fpga_m.master +set_interface_property hps_m_master EXPORT_OF hps_m.master +add_connection hps_m.master sys_hps.f2h_axi_slave + +set_domain_assignment {$system} {qsys_mm.enableEccProtection} {FALSE} +set_domain_assignment {$system} {qsys_mm.insertDefaultSlave} {FALSE} + +# cpu/hps handling + +proc ad_dma_interconnect {m_port} { + + add_connection ${m_port} sys_hps.f2h_axi_slave + set_connection_parameter_value ${m_port}/sys_hps.f2h_axi_slave baseAddress {0x0} +} + +proc ad_cpu_interrupt {m_irq m_port} { + + add_connection sys_hps.f2h_irq0 ${m_port} + set_connection_parameter_value sys_hps.f2h_irq0/${m_port} irqNumber ${m_irq} +} + +proc ad_cpu_interconnect {m_base m_port {avl_bridge ""} {avl_bridge_base 0x00000000} {avl_address_width 18}} { + if {[string equal ${avl_bridge} ""]} { + add_connection sys_hps.h2f_axi_master ${m_port} + set_connection_parameter_value sys_hps.h2f_axi_master/${m_port} baseAddress ${m_base} + } else { + if {[lsearch -exact [get_instances] ${avl_bridge}] == -1} { + ## Instantiate the bridge and connect the interfaces + add_instance ${avl_bridge} altera_avalon_mm_bridge + set_instance_parameter_value ${avl_bridge} {ADDRESS_WIDTH} $avl_address_width + set_instance_parameter_value ${avl_bridge} {SYNC_RESET} {1} + add_connection sys_hps.h2f_axi_master ${avl_bridge}.s0 + set_connection_parameter_value sys_hps.h2f_axi_master/${avl_bridge}.s0 baseAddress ${avl_bridge_base} + add_connection sys_clk.clk ${avl_bridge}.clk + add_connection sys_clk.clk_reset ${avl_bridge}.reset + } + add_connection ${avl_bridge}.m0 ${m_port} + set_connection_parameter_value ${avl_bridge}.m0/${m_port} baseAddress ${m_base} + } +} + +# gpio-bd + +add_instance sys_gpio_bd altera_avalon_pio +set_instance_parameter_value sys_gpio_bd {direction} {InOut} +set_instance_parameter_value sys_gpio_bd {generateIRQ} {1} +set_instance_parameter_value sys_gpio_bd {width} {32} + +add_connection sys_clk.clk sys_gpio_bd.clk +add_connection sys_clk.clk_reset sys_gpio_bd.reset +add_interface sys_gpio_bd conduit end +set_interface_property sys_gpio_bd EXPORT_OF sys_gpio_bd.external_connection + +# gpio-in + +add_instance sys_gpio_in altera_avalon_pio +set_instance_parameter_value sys_gpio_in {direction} {Input} +set_instance_parameter_value sys_gpio_in {generateIRQ} {1} +set_instance_parameter_value sys_gpio_in {width} {32} + +add_connection sys_clk.clk_reset sys_gpio_in.reset +add_connection sys_clk.clk sys_gpio_in.clk +add_interface sys_gpio_in conduit end +set_interface_property sys_gpio_in EXPORT_OF sys_gpio_in.external_connection + +# gpio-out + +add_instance sys_gpio_out altera_avalon_pio +set_instance_parameter_value sys_gpio_out {direction} {Output} +set_instance_parameter_value sys_gpio_out {generateIRQ} {0} +set_instance_parameter_value sys_gpio_out {width} {32} + +add_connection sys_clk.clk_reset sys_gpio_out.reset +add_connection sys_clk.clk sys_gpio_out.clk +add_interface sys_gpio_out conduit end +set_interface_property sys_gpio_out EXPORT_OF sys_gpio_out.external_connection + +# spi + +add_instance sys_spi altera_avalon_spi +set_instance_parameter_value sys_spi {clockPhase} {0} +set_instance_parameter_value sys_spi {clockPolarity} {0} +set_instance_parameter_value sys_spi {dataWidth} {8} +set_instance_parameter_value sys_spi {masterSPI} {1} +set_instance_parameter_value sys_spi {numberOfSlaves} {8} +set_instance_parameter_value sys_spi {targetClockRate} {10000000.0} + +add_connection sys_clk.clk_reset sys_spi.reset +add_connection sys_clk.clk sys_spi.clk +add_interface sys_spi conduit end +set_interface_property sys_spi EXPORT_OF sys_spi.external + +## connections + +# exports + +add_interface emif_calbus_0 conduit INPUT +add_interface hps_emif conduit INPUT +add_interface emif_calbus_clk clock OUTPUT + +add_connection emif_hps.hps_emif/sys_hps.hps_emif +add_connection emif_calbus_0.emif_calbus_clk/emif_hps.emif_calbus_clk +add_connection emif_hps.emif_calbus/emif_calbus_0.emif_calbus_0 + +set_interface_property emif_hps EXPORT_OF emif_hps.oct +set_interface_property emif_hps_ddr EXPORT_OF emif_hps.mem +set_interface_property sys_hps_f2h EXPORT_OF sys_hps.f2h_stm_hw_events +set_interface_property sys_hps_h2f_cs EXPORT_OF sys_hps.h2f_cs +set_interface_property emif_hps_pll_ref EXPORT_OF emif_hps.pll_ref_clk + +# cpu interconnect + +ad_cpu_interconnect 0x000000e0 sys_id.control_slave "avl_peripheral_mm_bridge" 0x0000 17 +ad_cpu_interconnect 0x000000d0 sys_gpio_bd.s1 "avl_peripheral_mm_bridge" +ad_cpu_interconnect 0x00000000 sys_gpio_in.s1 "avl_peripheral_mm_bridge" +ad_cpu_interconnect 0x00000020 sys_gpio_out.s1 "avl_peripheral_mm_bridge" +ad_cpu_interconnect 0x00000040 sys_spi.spi_control_port "avl_peripheral_mm_bridge" +ad_cpu_interconnect 0x00018000 axi_sysid_0.s_axi "avl_peripheral_mm_bridge" + +# interrupts + +ad_cpu_interrupt 5 sys_gpio_in.irq +ad_cpu_interrupt 6 sys_gpio_bd.irq +ad_cpu_interrupt 7 sys_spi.irq + +set xcvr_reconfig_addr_width 11 diff --git a/projects/common/fm87/gpio_slave.v b/projects/common/fm87/gpio_slave.v new file mode 100644 index 0000000000..f51bdae01c --- /dev/null +++ b/projects/common/fm87/gpio_slave.v @@ -0,0 +1,79 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2024 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module gpio_slave ( + input reset_n, + input clk, + input sync, + input mosi, + output miso, + + input [7:0] leds, + output [7:0] dipsw +); + + wire [7:0] i_leds; + reg [7:0] i_dipsw; + reg [7:0] q_leds; + reg [7:0] q_dipsw; + + assign i_leds = ~leds; + assign miso = q_leds[0]; + assign dipsw = q_dipsw; + + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + i_dipsw <= 8'b00000000; + end else begin + i_dipsw <= {mosi, i_dipsw[7:1]}; + end + end + + always @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + q_leds <= 8'b11111111; + q_dipsw <= 8'b00000000; + end else if (sync) begin + q_leds <= i_leds; + q_dipsw <= i_dipsw; + end else begin + q_leds <= {1'b1, q_leds[7:1]}; + q_dipsw <= q_dipsw; + end + end + +endmodule diff --git a/projects/common/fm87/jtag.sdc b/projects/common/fm87/jtag.sdc new file mode 100644 index 0000000000..373434c655 --- /dev/null +++ b/projects/common/fm87/jtag.sdc @@ -0,0 +1,251 @@ +############################################################################### +## Copyright (C) 2024 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_time_format -unit ns -decimal_places 3 + +# This is the main entry point called at the end of this SDC file. +proc set_jtag_timing_constraints { } { + # If the timing characteristic outside of FPGA is well understood, and + # there is a need to provide more slack to allow flexible placement of + # JTAG logic in the FPGA core, use the timing constraints for both + # timing analysis and fitter; otherwise, use the default fitter timing + # constraints. + + # ---customize here--- + set use_fitter_specific_constraint 1 + + if { $use_fitter_specific_constraint && [string equal quartus_fit $::TimingAnalyzerInfo(nameofexecutable)] } { + # Define a different set of timing spec to influence place-and-route + # result in the jtag clock domain. The slacks outside of FPGA are + # maximized. + + set_default_quartus_fit_timing_directive + } else { + # Define a set of timing constraints that describe the JTAG paths + # for the Timing Analyzer to analyze. The Timing Analyzer timing reports show whether + # the JTAG logic in the FPGA core will operates in this setup. + + set_jtag_timing_spec_for_timing_analysis + } +} + +proc set_default_quartus_fit_timing_directive { } { + # A10 supports max 33.3Mhz clock + set jtag_33Mhz_t_period 30 + + create_clock -name {altera_reserved_tck} -period $jtag_33Mhz_t_period [get_ports {altera_reserved_tck}] + set_clock_groups -asynchronous -group {altera_reserved_tck} + # Force fitter to place register driving TDO pin to be as close to + # the JTAG controller as possible to maximize the slack outside of FPGA. + set_max_delay -to [get_ports { altera_reserved_tdo } ] 0 +} + +proc set_jtag_timing_spec_for_timing_analysis { } { + derive_clock_uncertainty + + # There are few possible JTAG chain configurations: + # a. This device is the only device in the JTAG chain + # b. This device is the first one in the JTAG chain + # c. This device is in the middle of the JTAG chain + # d. This device is the last one in the JTAG chain + + # No matter where the device is in the chain. The tck and tms are driven + # directly from JTAG hardware. + set_tck_timing_spec + set_tms_timing_spec + + # Depending on where the device is located along the chain, tdi can be + # either driven by blaster hw (a. b.) or driven by another device in the + # chain(c. d.) + # ---customize here--- + set tdi_is_driven_by_blaster 1 + + if { $tdi_is_driven_by_blaster } { + set_tdi_timing_spec_when_driven_by_blaster + } else { + set_tdi_timing_spec_when_driven_by_device + } + + # Depending on where the device is located along the chain, tdo can + # drive either blaster hw (a. d.) or another device in the chain (b. c.) + # ---customize here--- + set tdo_drive_blaster 1 + + if { $tdo_drive_blaster } { + set_tdo_timing_spec_when_drive_blaster + } else { + set_tdo_timing_spec_when_drive_device + } + + set_optional_ntrst_timing_spec + + # Cut a few timing paths that are not related to JTAG logic in + # the FPGA core, such as security mode. + set_false_path -from [get_ports {altera_reserved_tdi}] -to [get_ports {altera_reserved_tdo}] + if { [get_collection_size [get_registers -nowarn *~jtag_reg]] > 0 } { + set_false_path -from [get_registers *~jtag_reg] -to [get_ports {altera_reserved_tdo}] + } + +} + +proc set_tck_timing_spec { } { + # USB Blaster 1 uses 6 MHz clock = 166.666 ns period + set ub1_t_period 166.666 + # USB Blaster 2 uses 24 MHz clock = 41.666 ns period + set ub2_default_t_period 41.666 + # USB Blaster 2 running at 16 MHz clock safe mode = 62.5 ns period + set ub2_safe_t_period 62.5 + + # ---customize here--- + set tck_t_period $ub2_safe_t_period + + create_clock -name {altera_reserved_tck} -period $tck_t_period [get_ports {altera_reserved_tck}] + set_clock_groups -asynchronous -group {altera_reserved_tck} +} + +proc get_tck_delay_max { } { + set tck_blaster_tco_max 14.603 + set tck_cable_max 11.627 + + # tck delay on the PCB depends on the trace length from JTAG 10-pin + # header to FPGA on board. In general on the PCB, the signal travels + # at the speed of ~160 ps/inch (1000 mils = 1 inch). + # ---customize here--- + set tck_header_trace_max 0.5 + + return [expr $tck_blaster_tco_max + $tck_cable_max + $tck_header_trace_max] +} + +proc get_tck_delay_min { } { + set tck_blaster_tco_min 14.603 + set tck_cable_min 10.00 + + # tck delay on the PCB depends on the trace length from JTAG 10-pin + # header to FPGA on board. In general on the PCB, the signal travels + # at the speed of ~160 ps/inch (1000 mils = 1 inch). + # ---customize here--- + set tck_header_trace_min 0.1 + + return [expr $tck_blaster_tco_min + $tck_cable_min + $tck_header_trace_min] +} + +proc set_tms_timing_spec { } { + set tms_blaster_tco_max 9.468 + set tms_blaster_tco_min 9.468 + + set tms_cable_max 11.627 + set tms_cable_min 10.0 + + # tms delay on the PCB depends on the trace length from JTAG 10-pin + # header to FPGA on board. In general on the PCB, the signal travels + # at the speed of ~160 ps/inch (1000 mils = 1 inch). + # ---customize here--- + set tms_header_trace_max 0.5 + set tms_header_trace_min 0.1 + + set tms_in_max [expr $tms_cable_max + $tms_header_trace_max + $tms_blaster_tco_max - [get_tck_delay_min]] + set tms_in_min [expr $tms_cable_min + $tms_header_trace_min + $tms_blaster_tco_min - [get_tck_delay_max]] + + set_input_delay -add_delay -clock_fall -clock altera_reserved_tck -max $tms_in_max [get_ports {altera_reserved_tms}] + set_input_delay -add_delay -clock_fall -clock altera_reserved_tck -min $tms_in_min [get_ports {altera_reserved_tms}] +} + +proc set_tdi_timing_spec_when_driven_by_blaster { } { + set tdi_blaster_tco_max 8.551 + set tdi_blaster_tco_min 8.551 + + set tdi_cable_max 11.627 + set tdi_cable_min 10.0 + + # tms delay on the PCB depends on the trace length from JTAG 10-pin + # header to FPGA on board. In general on the PCB, the signal travels + # at the speed of ~160 ps/inch (1000 mils = 1 inch). + # ---customize here--- + set tdi_header_trace_max 0.5 + set tdi_header_trace_min 0.1 + + set tdi_in_max [expr $tdi_cable_max + $tdi_header_trace_max + $tdi_blaster_tco_max - [get_tck_delay_min]] + set tdi_in_min [expr $tdi_cable_min + $tdi_header_trace_min + $tdi_blaster_tco_min - [get_tck_delay_max]] + + #TDI launches at the falling edge of TCK per standard + set_input_delay -add_delay -clock_fall -clock altera_reserved_tck -max $tdi_in_max [get_ports {altera_reserved_tdi}] + set_input_delay -add_delay -clock_fall -clock altera_reserved_tck -min $tdi_in_min [get_ports {altera_reserved_tdi}] +} + +proc set_tdi_timing_spec_when_driven_by_device { } { + # TCO timing spec of tdo on the device driving this tdi input + # ---customize here--- + set previous_device_tdo_tco_max 10.0 + set previous_device_tdo_tco_min 10.0 + + # tdi delay on the PCB depends on the trace length from JTAG 10-pin + # header to FPGA on board. In general on the PCB, the signal travels + # at the speed of ~160 ps/inch (1000 mils = 1 inch). + # ---customize here--- + set tdi_trace_max 0.5 + set tdi_trace_min 0.1 + + set tdi_in_max [expr $previous_device_tdo_tco_max + $tdi_trace_max - [get_tck_delay_min]] + set tdi_in_min [expr $previous_device_tdo_tco_min + $tdi_trace_min - [get_tck_delay_max]] + + #TDI launches at the falling edge of TCK per standard + set_input_delay -add_delay -clock_fall -clock altera_reserved_tck -max $tdi_in_max [get_ports {altera_reserved_tdi}] + set_input_delay -add_delay -clock_fall -clock altera_reserved_tck -min $tdi_in_min [get_ports {altera_reserved_tdi}] +} + +proc set_tdo_timing_spec_when_drive_blaster { } { + set tdo_blaster_tsu 5.831 + set tdo_blaster_th -1.651 + + set tdo_cable_max 11.627 + set tdo_cable_min 10.0 + + # tdi delay on the PCB depends on the trace length from JTAG 10-pin + # header to FPGA on board. In general on the PCB, the signal travels + # at the speed of ~160 ps/inch (1000 mils = 1 inch). + # ---customize here--- + set tdo_header_trace_max 0.5 + set tdo_header_trace_min 0.1 + + set tdo_out_max [expr $tdo_cable_max + $tdo_header_trace_max + $tdo_blaster_tsu + [get_tck_delay_max]] + set tdo_out_min [expr $tdo_cable_min + $tdo_header_trace_min - $tdo_blaster_th + [get_tck_delay_min]] + + #TDO does not latch inside the USB Blaster II at the rising edge of TCK, + # it actually is latched one half cycle later in packed mode + # (equivalent to 1 JTAG fall-to-fall cycles) + set_output_delay -add_delay -clock_fall -clock altera_reserved_tck -max $tdo_out_max [get_ports {altera_reserved_tdo}] + set_output_delay -add_delay -clock_fall -clock altera_reserved_tck -min $tdo_out_min [get_ports {altera_reserved_tdo}] +} + +proc set_tdo_timing_spec_when_drive_device { } { + # TCO timing spec of tdi on the device driven by this tdo output + # ---customize here--- + set next_device_tdi_tco_max 10.0 + set next_device_tdi_tco_min 10.0 + + # tdi delay on the PCB depends on the trace length from JTAG 10-pin + # header to FPGA on board. In general on the PCB, the signal travels + # at the speed of ~160 ps/inch (1000 mils = 1 inch). + # ---customize here--- + set tdo_trace_max 0.5 + set tdo_trace_min 0.1 + + set tdo_out_max [expr $next_device_tdi_tco_max + $tdo_trace_max + [get_tck_delay_max]] + set tdo_out_min [expr $next_device_tdi_tco_min + $tdo_trace_min + [get_tck_delay_min]] + + #TDO latches at the rising edge of TCK per standard + set_output_delay -add_delay -clock altera_reserved_tck -max $tdo_out_max [get_ports {altera_reserved_tdo}] + set_output_delay -add_delay -clock altera_reserved_tck -min $tdo_out_min [get_ports {altera_reserved_tdo}] +} + +proc set_optional_ntrst_timing_spec { } { + # ntrst is an optional JTAG pin to asynchronously reset the device JTAG controller. + # There is no path from this pin to any FPGA core fabric. + if { [get_collection_size [get_ports -nowarn {altera_reserved_ntrst}]] > 0 } { + set_false_path -from [get_ports {altera_reserved_ntrst}] + } +} + +set_jtag_timing_constraints diff --git a/projects/common/fm87/system_constr.sdc b/projects/common/fm87/system_constr.sdc new file mode 100644 index 0000000000..40ce50ed41 --- /dev/null +++ b/projects/common/fm87/system_constr.sdc @@ -0,0 +1,13 @@ +############################################################################### +## Copyright (C) 2024 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}] +create_clock -period "6.000 ns" -name emif_ref_clk [get_ports {emif_hps_pll_ref_clk}] + +derive_clock_uncertainty + +source ./jtag.sdc + +set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*] diff --git a/projects/common/fm87/system_project.tcl b/projects/common/fm87/system_project.tcl new file mode 100644 index 0000000000..067824b41a --- /dev/null +++ b/projects/common/fm87/system_project.tcl @@ -0,0 +1,15 @@ +############################################################################### +## Copyright (C) 2024 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +source ../../scripts/adi_project_intel.tcl + +adi_project template_fm87 + +source $ad_hdl_dir/projects/common/fm87/fm87_system_assign.tcl + +set_global_assignment -name VERILOG_FILE $ad_hdl_dir/projects/common/fm87/gpio_slave.v + +execute_flow -compile diff --git a/projects/common/fm87/system_qsys.tcl b/projects/common/fm87/system_qsys.tcl new file mode 100644 index 0000000000..31f885bc22 --- /dev/null +++ b/projects/common/fm87/system_qsys.tcl @@ -0,0 +1,15 @@ +############################################################################### +## Copyright (C) 2024 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source $ad_hdl_dir/projects/scripts/adi_pd.tcl +source $ad_hdl_dir/projects/common/fm87/fm87_system_qsys.tcl + +#system ID +set_instance_parameter_value axi_sysid_0 {ROM_ADDR_BITS} {9} +set_instance_parameter_value rom_sys_0 {ROM_ADDR_BITS} {9} + +set_instance_parameter_value rom_sys_0 {PATH_TO_FILE} "[pwd]/mem_init_sys.txt" + +sysid_gen_sys_init_file; diff --git a/projects/common/fm87/system_top.v b/projects/common/fm87/system_top.v new file mode 100644 index 0000000000..86d60b5e89 --- /dev/null +++ b/projects/common/fm87/system_top.v @@ -0,0 +1,249 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2024 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + // clock and resets + input sys_clk, + input hps_io_ref_clk, + input sys_resetn, + + // board gpio + input [12:0] fpga_gpio, + input fpga_sgpio_sync, + input fpga_sgpio_clk, + input fpga_sgpi, + output fpga_sgpo, + + // hps-emif + input emif_hps_pll_ref_clk, + output emif_hps_mem_clk_p, + output emif_hps_mem_clk_n, + output [16:0] emif_hps_mem_a, + output [ 1:0] emif_hps_mem_ba, + output emif_hps_mem_bg, + output emif_hps_mem_cke, + output emif_hps_mem_cs_n, + output emif_hps_mem_odt, + output emif_hps_mem_reset_n, + output emif_hps_mem_act_n, + output emif_hps_mem_par, + input emif_hps_mem_alert_n, + inout [ 8:0] emif_hps_mem_dqs_p, + inout [ 8:0] emif_hps_mem_dqs_n, + inout [ 8:0] emif_hps_mem_dbi_n, + inout [71:0] emif_hps_mem_dq, + input emif_hps_oct_rzq, + + // hps-emac + input hps_emac_rxclk, + input hps_emac_rxctl, + input [ 3:0] hps_emac_rxd, + output hps_emac_txclk, + output hps_emac_txctl, + output [ 3:0] hps_emac_txd, + output hps_emac_mdc, + inout hps_emac_mdio, + + // hps-sdio + output hps_sdio_clk, + inout hps_sdio_cmd, + inout [ 3:0] hps_sdio_d, + + // hps-usb + input hps_usb_clk, + input hps_usb_dir, + input hps_usb_nxt, + output hps_usb_stp, + inout [ 7:0] hps_usb_d, + + // hps-uart + input hps_uart_rx, + output hps_uart_tx, + + // hps-i2c + inout hps_i2c_sda, + inout hps_i2c_scl, + + // hps-jtag + input hps_jtag_tck, + input hps_jtag_tms, + output hps_jtag_tdo, + input hps_jtag_tdi, + + // hps-OOBE daughter card peripherals + inout hps_gpio_eth_irq, + inout hps_gpio_usb_oci, + inout [ 1:0] hps_gpio_btn, + inout [ 2:0] hps_gpio_led +); + + // internal signals + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [ 7:0] fpga_dipsw; + wire [ 7:0] fpga_led; + wire nconf_done; + wire ninit_done; + wire sys_reset_n; + wire h2f_reset; + wire [43:0] stm_hw_events; + + // Board GPIOs + assign fpga_led = gpio_o[7:0]; + assign gpio_i[ 7: 0] = gpio_o[7:0]; + assign gpio_i[15: 8] = fpga_dipsw; + assign gpio_i[17:16] = fpga_gpio[ 1:0]; // push buttons + assign gpio_i[28:18] = fpga_gpio[12:2]; + + // Unused GPIOs + assign gpio_i[31:29] = gpio_o[31:29]; + assign gpio_i[63:32] = gpio_o[63:32]; + + assign sys_reset_n = sys_resetn & ~h2f_reset & ~ninit_done; + assign stm_hw_events = {14'b0, fpga_led, fpga_dipsw, fpga_gpio[1:0]}; + + gpio_slave i_gpio_slave ( + .reset_n (sys_reset_n), + .clk (fpga_sgpio_clk), + .sync (fpga_sgpio_sync), + .miso (fpga_sgpo), + .mosi (fpga_sgpi), + .leds (fpga_led), + .dipsw (fpga_dipsw)); + + system_bd i_system_bd ( + .sys_clk_clk (sys_clk), + .sys_hps_io_hps_osc_clk (hps_io_ref_clk), + + .sys_rst_reset_n (sys_reset_n), + .rst_ninit_done (ninit_done), + .sys_gpio_bd_in_port (gpio_i[31: 0]), + .sys_gpio_bd_out_port (gpio_o[31: 0]), + .sys_gpio_in_export (gpio_i[63:32]), + .sys_gpio_out_export (gpio_o[63:32]), + + .emif_hps_ddr_mem_ck (emif_hps_mem_clk_p), + .emif_hps_ddr_mem_ck_n (emif_hps_mem_clk_n), + .emif_hps_ddr_mem_a (emif_hps_mem_a), + .emif_hps_ddr_mem_act_n (emif_hps_mem_act_n), + .emif_hps_ddr_mem_ba (emif_hps_mem_ba), + .emif_hps_ddr_mem_bg (emif_hps_mem_bg), + .emif_hps_ddr_mem_cke (emif_hps_mem_cke), + .emif_hps_ddr_mem_cs_n (emif_hps_mem_cs_n), + .emif_hps_ddr_mem_odt (emif_hps_mem_odt), + .emif_hps_ddr_mem_reset_n (emif_hps_mem_reset_n), + .emif_hps_ddr_mem_par (emif_hps_mem_par), + .emif_hps_ddr_mem_alert_n (emif_hps_mem_alert_n), + .emif_hps_ddr_mem_dqs (emif_hps_mem_dqs_p), + .emif_hps_ddr_mem_dqs_n (emif_hps_mem_dqs_n), + .emif_hps_ddr_mem_dq (emif_hps_mem_dq), + .emif_hps_ddr_mem_dbi_n (emif_hps_mem_dbi_n), + .emif_hps_oct_rzqin (emif_hps_oct_rzq), + .emif_hps_pll_ref_clk (emif_hps_pll_ref_clk), + + .sys_hps_io_EMAC0_TX_CLK (hps_emac_txclk), + .sys_hps_io_EMAC0_TX_CTL (hps_emac_txctl), + .sys_hps_io_EMAC0_TXD0 (hps_emac_txd[0]), + .sys_hps_io_EMAC0_TXD1 (hps_emac_txd[1]), + .sys_hps_io_EMAC0_TXD2 (hps_emac_txd[2]), + .sys_hps_io_EMAC0_TXD3 (hps_emac_txd[3]), + .sys_hps_io_EMAC0_RX_CLK (hps_emac_rxclk), + .sys_hps_io_EMAC0_RX_CTL (hps_emac_rxctl), + .sys_hps_io_EMAC0_RXD0 (hps_emac_rxd[0]), + .sys_hps_io_EMAC0_RXD1 (hps_emac_rxd[1]), + .sys_hps_io_EMAC0_RXD2 (hps_emac_rxd[2]), + .sys_hps_io_EMAC0_RXD3 (hps_emac_rxd[3]), + .sys_hps_io_EMAC0_MDIO (hps_emac_mdio), + .sys_hps_io_EMAC0_MDC (hps_emac_mdc), + + .sys_hps_io_SDMMC_CCLK (hps_sdio_clk), + .sys_hps_io_SDMMC_CMD (hps_sdio_cmd), + .sys_hps_io_SDMMC_D0 (hps_sdio_d[0]), + .sys_hps_io_SDMMC_D1 (hps_sdio_d[1]), + .sys_hps_io_SDMMC_D2 (hps_sdio_d[2]), + .sys_hps_io_SDMMC_D3 (hps_sdio_d[3]), + + .sys_hps_io_USB0_CLK (hps_usb_clk), + .sys_hps_io_USB0_STP (hps_usb_stp), + .sys_hps_io_USB0_DIR (hps_usb_dir), + .sys_hps_io_USB0_NXT (hps_usb_nxt), + .sys_hps_io_USB0_DATA0 (hps_usb_d[0]), + .sys_hps_io_USB0_DATA1 (hps_usb_d[1]), + .sys_hps_io_USB0_DATA2 (hps_usb_d[2]), + .sys_hps_io_USB0_DATA3 (hps_usb_d[3]), + .sys_hps_io_USB0_DATA4 (hps_usb_d[4]), + .sys_hps_io_USB0_DATA5 (hps_usb_d[5]), + .sys_hps_io_USB0_DATA6 (hps_usb_d[6]), + .sys_hps_io_USB0_DATA7 (hps_usb_d[7]), + + .sys_hps_io_UART0_RX (hps_uart_rx), + .sys_hps_io_UART0_TX (hps_uart_tx), + + .sys_hps_io_I2C1_SDA (hps_i2c_sda), + .sys_hps_io_I2C1_SCL (hps_i2c_scl), + + .sys_hps_io_jtag_tck (hps_jtag_tck), + .sys_hps_io_jtag_tms (hps_jtag_tms), + .sys_hps_io_jtag_tdo (hps_jtag_tdo), + .sys_hps_io_jtag_tdi (hps_jtag_tdi), + //Terminate the CS_JTAG. + .sys_hps_h2f_cs_ntrst (1'b1), + .sys_hps_h2f_cs_tck (1'b1), + .sys_hps_h2f_cs_tdi (1'b1), + .sys_hps_h2f_cs_tdo (), + .sys_hps_h2f_cs_tdoen (), + .sys_hps_h2f_cs_tms (1'b1), + + .sys_hps_io_gpio1_io0 (hps_gpio_eth_irq), + .sys_hps_io_gpio1_io1 (hps_gpio_usb_oci), + .sys_hps_io_gpio1_io4 (hps_gpio_btn[0]), + .sys_hps_io_gpio1_io5 (hps_gpio_btn[1]), + .sys_hps_io_gpio1_io19 (hps_gpio_led[1]), + .sys_hps_io_gpio1_io20 (hps_gpio_led[0]), + .sys_hps_io_gpio1_io21 (hps_gpio_led[2]), + + .h2f_reset_reset (h2f_reset), + + .sys_hps_f2h_stm_hwevents (stm_hw_events), + + .sys_spi_MISO (1'b0), + .sys_spi_MOSI (), + .sys_spi_SCLK (), + .sys_spi_SS_n ()); + +endmodule diff --git a/projects/scripts/adi_project_intel.tcl b/projects/scripts/adi_project_intel.tcl index b1a0451a55..61d5a946e1 100644 --- a/projects/scripts/adi_project_intel.tcl +++ b/projects/scripts/adi_project_intel.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2017-2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -88,6 +88,12 @@ proc adi_project {project_name {parameter_list {}}} { set system_qip_file ${ad_project_dir}/system_bd/synthesis/system_bd.qip } + if [regexp "fm87" $project_name] { + set family "Agilex 7" + set device AGIB027R31B1E1V + set system_qip_file ${ad_project_dir}/system_bd/synthesis/system_bd.qip + } + # version check set m_version [lindex $quartus(version) 1] @@ -237,4 +243,3 @@ proc adi_project {project_name {parameter_list {}}} { set_parameter -name $param $value } } -