From 337a3796fbea13aaa94a8bf4f70168487be2b766 Mon Sep 17 00:00:00 2001 From: Bogdan Luncan Date: Tue, 5 Nov 2024 07:44:31 +0200 Subject: [PATCH] ad9081_fmca_ebz: common: versal_transceiver: Force progdiv_clk to float The [rx/tx]_progdiv_clock was truncated if the lane rate was an integer. So for a lane rate of '10', the ref clock calculated was 151.000 instead of 151.515. Signed-off-by: Bogdan Luncan --- projects/ad9081_fmca_ebz/common/versal_transceiver.tcl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/projects/ad9081_fmca_ebz/common/versal_transceiver.tcl b/projects/ad9081_fmca_ebz/common/versal_transceiver.tcl index a0409c98c3..43bddb526a 100644 --- a/projects/ad9081_fmca_ebz/common/versal_transceiver.tcl +++ b/projects/ad9081_fmca_ebz/common/versal_transceiver.tcl @@ -215,8 +215,8 @@ proc create_versal_phy { puts "intf_cfg: ${intf_cfg}" puts "assymmetric_mode: ${asymmetric_mode}" - set rx_progdiv_clock [format %.3f [expr $rx_lane_rate * 1000 / ${clk_divider}]] - set tx_progdiv_clock [format %.3f [expr $tx_lane_rate * 1000 / ${clk_divider}]] + set rx_progdiv_clock [format %.3f [expr $rx_lane_rate * 1000.0 / ${clk_divider}]] + set tx_progdiv_clock [format %.3f [expr $tx_lane_rate * 1000.0 / ${clk_divider}]] set preset ${transceiver}-JESD204_64B66B if {$intf_cfg == "RX"} {