hdl_2016_r1

Change log:

1. Supported tools version for this release are :
   • Vivado 2015.4.2 - KCU105 projects requires some patches see bellow
   • Quartus 15.1
2. Library changes :
   • fix data clipping for AXI_HDMI_TX
   • patch for UTIL_DACFIFO
3. Project changes: None
4. New projects:
   • AD7768EVB

Note: The project using the KCU105 carrier requires the following patches

The setup we use is listed below, you may change it to suit your needs.

AR66031

1. Download the zip file from www.xilinx.com/support/answers/66031.html
2. mkdir -p /opt/Xilinx/Vivado/2015.4/KCU105/AR66031
3. unzip ~/Downloads/AR66031_Vivado_2015_4_preliminary_rev66031.zip
   -d /opt/Xilinx/Vivado/2015.4/KCU105/AR66031/
4. export MYVIVADO=/opt/Xilinx/Vivado/2015.4/KCU105/AR66031/vivado

AR66052

1. Download the verilog file from www.xilinx.com/support/answers/66052.html
2. mkdir -p /opt/Xilinx/Vivado/2015.4/KCU105/AR66052
3. cp ~/Downloads/gig_ethernet_pcs_pma_1_serdes_1_to_10_ser8.v
   /opt/Xilinx/Vivado/2015.4/KCU105/AR66052/bd_0_pcs_pma_0_serdes_1_to_10_ser8.v
4. sed -i 's/gig_ethernet_pcs_pma_1/bd_0_pcs_pma_0/g'
   /opt/Xilinx/Vivado/2015.4/KCU105/AR66052/bd_0_pcs_pma_0_serdes_1_to_10_ser8.v

hdl_2015_r2

Change log:

1. The supported tools version for this release are :
   • Vivado 2015.2.1
   • Quartus 15.1
2. Library changes :
   • AXI_JESD_GT core has changed to support per lane control to allow asymmetrical transmit and receive lane sharing.
   • ALL core parameter names made consistent and follow the new naming convention
   • Added DAC FIFO, this core allows to store custom DAC samples from memory, and play back at full rate
   • IPs for Altera have updated interfaces for easier connectivity in QSYS
   • AXI_DMAC auto-detects asynchronous clock configuration
3. Project changes :
   • Added CPACK / UPACK to FMCOMMS1, FMCOMMS5, FMCOMMS6, MOTCON2_FMC projects
   • FMCOMMS2: ARRADIO added (replaces C5SOC)
   • DAQ2: Added DAC FIFO
4. New projects :
   • PicozedSDR (ccfmc/ccbrk/ccpci)
   • DAQ2 for A10GX
   • DAQ2 KCU105 support
   • DAQ3 ZC706
5. Unsupported or in development projects (do NOT use)
   • DAQ1 ZC706
   • FMCJESDADC1 A5SOC
   • USDRX1 A5GT and ZC706
   • USB-FX3 ZC706
   • CFTL_CIP and CFTL_STD
   • FMCOMMS2 ZC706 Partial Reconfiguration (zc706pr)
   • FMCADC5 VC707

hdl_2015_r1

Supported tools:

• Vivado 2014.4.1
• Quartus 15.0

hdl_2014_r2

Supported tools:

• Vivado 2014.2
• Quartus 14.0

hdl_2014_r1

Supported tools:

• Vivado 2013.4
• Quartus 14.0