diff --git a/projects/ad469x_iio/STM32/ad469x_iio.ioc b/projects/ad469x_iio/STM32/ad469x_iio.ioc index 184a786ca..b780ec83b 100644 --- a/projects/ad469x_iio/STM32/ad469x_iio.ioc +++ b/projects/ad469x_iio/STM32/ad469x_iio.ioc @@ -58,63 +58,117 @@ Dma.TIM8_UP.4.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD Dma.TIM8_UP.4.PeriphInc=DMA_PINC_DISABLE Dma.TIM8_UP.4.Priority=DMA_PRIORITY_LOW Dma.TIM8_UP.4.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode +FMC.CASLatency1=FMC_SDRAM_CAS_LATENCY_3 +FMC.IPParameters=CASLatency1,ReadBurst1,ReadBurst2 +FMC.ReadBurst1=FMC_SDRAM_RBURST_ENABLE +FMC.ReadBurst2=FMC_SDRAM_RBURST_ENABLE File.Version=6 GPIO.groupedBy=Group By Peripherals KeepUserPlacement=false Mcu.CPN=STM32F469NIH6 Mcu.Family=STM32F4 Mcu.IP0=DMA -Mcu.IP1=I2C1 -Mcu.IP10=UART5 -Mcu.IP2=NVIC -Mcu.IP3=RCC -Mcu.IP4=SPI1 -Mcu.IP5=SYS -Mcu.IP6=TIM1 -Mcu.IP7=TIM2 -Mcu.IP8=TIM4 -Mcu.IP9=TIM8 -Mcu.IPNb=11 +Mcu.IP1=FMC +Mcu.IP10=TIM8 +Mcu.IP11=UART5 +Mcu.IP2=I2C1 +Mcu.IP3=NVIC +Mcu.IP4=RCC +Mcu.IP5=SPI1 +Mcu.IP6=SYS +Mcu.IP7=TIM1 +Mcu.IP8=TIM2 +Mcu.IP9=TIM4 +Mcu.IPNb=12 Mcu.Name=STM32F469NIHx Mcu.Package=TFBGA216 Mcu.Pin0=PB8 Mcu.Pin1=PB4 -Mcu.Pin10=PH0/OSC_IN -Mcu.Pin11=PH1/OSC_OUT -Mcu.Pin12=PG7 -Mcu.Pin13=PD12 -Mcu.Pin14=PA1 -Mcu.Pin15=PA7 -Mcu.Pin16=PB1 -Mcu.Pin17=VP_SYS_VS_Systick -Mcu.Pin18=VP_TIM1_VS_ClockSourceINT -Mcu.Pin19=VP_TIM2_VS_ClockSourceITR +Mcu.Pin10=PI2 +Mcu.Pin11=PF0 +Mcu.Pin12=PI7 +Mcu.Pin13=PI10 +Mcu.Pin14=PI6 +Mcu.Pin15=PG9 +Mcu.Pin16=PD2 +Mcu.Pin17=PH15 +Mcu.Pin18=PI1 +Mcu.Pin19=PA10 Mcu.Pin2=PB3 -Mcu.Pin20=VP_TIM4_VS_ControllerModeGated -Mcu.Pin21=VP_TIM4_VS_ClockSourceITR -Mcu.Pin22=VP_TIM8_VS_ControllerModeTrigger -Mcu.Pin23=VP_TIM8_VS_ClockSourceINT -Mcu.Pin24=VP_TIM8_VS_ClockSourceITR -Mcu.Pin25=VP_TIM8_VS_no_output1 -Mcu.Pin26=VP_TIM8_VS_OPM +Mcu.Pin20=PF1 +Mcu.Pin21=PI9 +Mcu.Pin22=PH13 +Mcu.Pin23=PH14 +Mcu.Pin24=PI0 +Mcu.Pin25=PH0/OSC_IN +Mcu.Pin26=PF2 +Mcu.Pin27=PH1/OSC_OUT +Mcu.Pin28=PF3 +Mcu.Pin29=PG8 Mcu.Pin3=PC12 +Mcu.Pin30=PF4 +Mcu.Pin31=PH5 +Mcu.Pin32=PH3 +Mcu.Pin33=PF5 +Mcu.Pin34=PH2 +Mcu.Pin35=PD15 +Mcu.Pin36=PD10 +Mcu.Pin37=PD14 +Mcu.Pin38=PD9 +Mcu.Pin39=PD8 Mcu.Pin4=PA15 +Mcu.Pin40=PF12 +Mcu.Pin41=PG1 +Mcu.Pin42=PF15 +Mcu.Pin43=PD12 +Mcu.Pin44=PH12 +Mcu.Pin45=PA1 +Mcu.Pin46=PF13 +Mcu.Pin47=PG0 +Mcu.Pin48=PE8 +Mcu.Pin49=PG5 Mcu.Pin5=PB7 -Mcu.Pin6=PG9 -Mcu.Pin7=PD2 -Mcu.Pin8=PA10 -Mcu.Pin9=PC15/OSC32_OUT -Mcu.PinsNb=27 +Mcu.Pin50=PG4 +Mcu.Pin51=PH9 +Mcu.Pin52=PH11 +Mcu.Pin53=PF14 +Mcu.Pin54=PF11 +Mcu.Pin55=PE9 +Mcu.Pin56=PE11 +Mcu.Pin57=PE14 +Mcu.Pin58=PH8 +Mcu.Pin59=PH10 +Mcu.Pin6=PG15 +Mcu.Pin60=PA7 +Mcu.Pin61=PE7 +Mcu.Pin62=PE10 +Mcu.Pin63=PE12 +Mcu.Pin64=PE15 +Mcu.Pin65=PE13 +Mcu.Pin66=PB15 +Mcu.Pin67=VP_SYS_VS_Systick +Mcu.Pin68=VP_TIM1_VS_ClockSourceINT +Mcu.Pin69=VP_TIM2_VS_ClockSourceITR +Mcu.Pin7=PD0 +Mcu.Pin70=VP_TIM4_VS_ControllerModeGated +Mcu.Pin71=VP_TIM4_VS_ClockSourceITR +Mcu.Pin72=VP_TIM8_VS_ControllerModeTrigger +Mcu.Pin73=VP_TIM8_VS_ClockSourceINT +Mcu.Pin74=VP_TIM8_VS_ClockSourceITR +Mcu.Pin75=VP_TIM8_VS_no_output1 +Mcu.Pin76=VP_TIM8_VS_OPM +Mcu.Pin8=PD1 +Mcu.Pin9=PI3 +Mcu.PinsNb=77 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32F469NIHx -MxCube.Version=6.11.0 -MxDb.Version=DB.6.0.110 +MxCube.Version=6.12.1 +MxDb.Version=DB.6.0.121 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false -NVIC.DMA2_Stream0_IRQn=true\:0\:0\:false\:true\:true\:1\:true\:true\:true +NVIC.DMA2_Stream0_IRQn=true\:0\:0\:false\:true\:false\:1\:true\:true\:true NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false -NVIC.EXTI15_10_IRQn=true\:0\:0\:false\:false\:false\:true\:true\:false -NVIC.EXTI9_5_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true +NVIC.EXTI15_10_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:false NVIC.ForceEnableDMAVector=false NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.I2C1_ER_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true @@ -140,8 +194,8 @@ PA15.Signal=S_TIM2_CH1_ETR PA7.Locked=true PA7.Mode=Full_Duplex_Master PA7.Signal=SPI1_MOSI -PB1.Mode=PWM Generation3 CH3N -PB1.Signal=TIM1_CH3N +PB15.Locked=true +PB15.Signal=GPXTI15 PB3.GPIOParameters=GPIO_PuPd PB3.GPIO_PuPd=GPIO_PULLUP PB3.Locked=true @@ -157,16 +211,43 @@ PB8.Mode=I2C PB8.Signal=I2C1_SCL PC12.Mode=Asynchronous PC12.Signal=UART5_TX -PC15/OSC32_OUT.Locked=true -PC15/OSC32_OUT.Signal=GPXTI15 +PD0.Signal=FMC_D2_DA2 +PD1.Signal=FMC_D3_DA3 +PD10.Signal=FMC_D15_DA15 PD12.Locked=true PD12.Signal=S_TIM4_CH1 +PD14.Signal=FMC_D0_DA0 +PD15.Signal=FMC_D1_DA1 PD2.Mode=Asynchronous PD2.Signal=UART5_RX -PG7.GPIOParameters=GPIO_ModeDefaultEXTI -PG7.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING -PG7.Locked=true -PG7.Signal=GPXTI7 +PD8.Signal=FMC_D13_DA13 +PD9.Signal=FMC_D14_DA14 +PE10.Signal=FMC_D7_DA7 +PE11.Signal=FMC_D8_DA8 +PE12.Signal=FMC_D9_DA9 +PE13.Signal=FMC_D10_DA10 +PE14.Signal=FMC_D11_DA11 +PE15.Signal=FMC_D12_DA12 +PE7.Signal=FMC_D4_DA4 +PE8.Signal=FMC_D5_DA5 +PE9.Signal=FMC_D6_DA6 +PF0.Signal=FMC_A0 +PF1.Signal=FMC_A1 +PF11.Signal=FMC_SDNRAS +PF12.Signal=FMC_A6 +PF13.Signal=FMC_A7 +PF14.Signal=FMC_A8 +PF15.Signal=FMC_A9 +PF2.Signal=FMC_A2 +PF3.Signal=FMC_A3 +PF4.Signal=FMC_A4 +PF5.Signal=FMC_A5 +PG0.Signal=FMC_A10 +PG1.Signal=FMC_A11 +PG15.Signal=FMC_SDNCAS +PG4.Signal=FMC_A14_BA0 +PG5.Signal=FMC_A15_BA1 +PG8.Signal=FMC_SDCLK PG9.GPIOParameters=GPIO_Speed PG9.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH PG9.Locked=true @@ -175,6 +256,27 @@ PH0/OSC_IN.Mode=HSE-External-Oscillator PH0/OSC_IN.Signal=RCC_OSC_IN PH1/OSC_OUT.Mode=HSE-External-Oscillator PH1/OSC_OUT.Signal=RCC_OSC_OUT +PH10.Signal=FMC_D18 +PH11.Signal=FMC_D19 +PH12.Signal=FMC_D20 +PH13.Signal=FMC_D21 +PH14.Signal=FMC_D22 +PH15.Signal=FMC_D23 +PH2.Mode=SdramChipSelect1_1 +PH2.Signal=FMC_SDCKE0 +PH3.Mode=SdramChipSelect1_1 +PH3.Signal=FMC_SDNE0 +PH5.Signal=FMC_SDNWE +PH8.Signal=FMC_D16 +PH9.Signal=FMC_D17 +PI0.Signal=FMC_D24 +PI1.Signal=FMC_D25 +PI10.Signal=FMC_D31 +PI2.Signal=FMC_D26 +PI3.Signal=FMC_D27 +PI6.Signal=FMC_D28 +PI7.Signal=FMC_D29 +PI9.Signal=FMC_D30 PinOutPanel.CurrentBGAView=Top PinOutPanel.RotationAngle=0 ProjectManager.AskForMigrate=true @@ -186,7 +288,7 @@ ProjectManager.CustomerFirmwarePackage= ProjectManager.DefaultFWLocation=true ProjectManager.DeletePrevious=true ProjectManager.DeviceId=STM32F469NIHx -ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.27.1 +ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.28.1 ProjectManager.FreePins=false ProjectManager.HalAssertFull=false ProjectManager.HeapSize=0x200 @@ -200,14 +302,14 @@ ProjectManager.ProjectBuild=false ProjectManager.ProjectFileName=ad469x_iio.ioc ProjectManager.ProjectName=ad469x_iio ProjectManager.ProjectStructure= -ProjectManager.RegisterCallBack=I2C,SPI,TIM,UART +ProjectManager.RegisterCallBack=I2C,SDRAM,SPI,TIM,UART ProjectManager.StackSize=0x400 ProjectManager.TargetToolchain=STM32CubeIDE ProjectManager.ToolChainLocation= ProjectManager.UAScriptAfterPath= ProjectManager.UAScriptBeforePath= ProjectManager.UnderRoot=true -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-false,2-SystemClock_Config-RCC-false-HAL-false,3-MX_DMA_Init-DMA-false-HAL-false,4-MX_UART5_Init-UART5-false-HAL-false,5-MX_SPI1_Init-SPI1-false-HAL-false,6-MX_I2C1_Init-I2C1-false-HAL-false,7-MX_TIM1_Init-TIM1-false-HAL-false,8-MX_TIM2_Init-TIM2-false-HAL-false,9-MX_TIM4_Init-TIM4-false-HAL-false,10-MX_TIM8_Init-TIM8-false-HAL-false +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-false,2-SystemClock_Config-RCC-false-HAL-false,3-MX_DMA_Init-DMA-false-HAL-false,4-MX_UART5_Init-UART5-false-HAL-false,5-MX_SPI1_Init-SPI1-false-HAL-false,6-MX_I2C1_Init-I2C1-false-HAL-false,7-MX_TIM1_Init-TIM1-false-HAL-false,8-MX_TIM2_Init-TIM2-false-HAL-false,9-MX_TIM4_Init-TIM4-false-HAL-false,10-MX_TIM8_Init-TIM8-false-HAL-false,false-11-MX_FMC_Init-FMC-false-HAL-false RCC.AHBFreq_Value=180000000 RCC.APB1CLKDivider=RCC_HCLK_DIV4 RCC.APB1Freq_Value=45000000 @@ -254,11 +356,109 @@ RCC.VCOI2SOutputFreq_Value=384000000 RCC.VCOInputFreq_Value=2000000 RCC.VCOOutputFreq_Value=360000000 RCC.VCOSAIOutputFreq_Value=384000000 +SH.FMC_A0.0=FMC_A0,12b-sda1 +SH.FMC_A0.ConfNb=1 +SH.FMC_A1.0=FMC_A1,12b-sda1 +SH.FMC_A1.ConfNb=1 +SH.FMC_A10.0=FMC_A10,12b-sda1 +SH.FMC_A10.ConfNb=1 +SH.FMC_A11.0=FMC_A11,12b-sda1 +SH.FMC_A11.ConfNb=1 +SH.FMC_A14_BA0.0=FMC_BA0,FourSdramBanks1 +SH.FMC_A14_BA0.ConfNb=1 +SH.FMC_A15_BA1.0=FMC_BA1,FourSdramBanks1 +SH.FMC_A15_BA1.ConfNb=1 +SH.FMC_A2.0=FMC_A2,12b-sda1 +SH.FMC_A2.ConfNb=1 +SH.FMC_A3.0=FMC_A3,12b-sda1 +SH.FMC_A3.ConfNb=1 +SH.FMC_A4.0=FMC_A4,12b-sda1 +SH.FMC_A4.ConfNb=1 +SH.FMC_A5.0=FMC_A5,12b-sda1 +SH.FMC_A5.ConfNb=1 +SH.FMC_A6.0=FMC_A6,12b-sda1 +SH.FMC_A6.ConfNb=1 +SH.FMC_A7.0=FMC_A7,12b-sda1 +SH.FMC_A7.ConfNb=1 +SH.FMC_A8.0=FMC_A8,12b-sda1 +SH.FMC_A8.ConfNb=1 +SH.FMC_A9.0=FMC_A9,12b-sda1 +SH.FMC_A9.ConfNb=1 +SH.FMC_D0_DA0.0=FMC_D0,sd-32b-d1 +SH.FMC_D0_DA0.ConfNb=1 +SH.FMC_D10_DA10.0=FMC_D10,sd-32b-d1 +SH.FMC_D10_DA10.ConfNb=1 +SH.FMC_D11_DA11.0=FMC_D11,sd-32b-d1 +SH.FMC_D11_DA11.ConfNb=1 +SH.FMC_D12_DA12.0=FMC_D12,sd-32b-d1 +SH.FMC_D12_DA12.ConfNb=1 +SH.FMC_D13_DA13.0=FMC_D13,sd-32b-d1 +SH.FMC_D13_DA13.ConfNb=1 +SH.FMC_D14_DA14.0=FMC_D14,sd-32b-d1 +SH.FMC_D14_DA14.ConfNb=1 +SH.FMC_D15_DA15.0=FMC_D15,sd-32b-d1 +SH.FMC_D15_DA15.ConfNb=1 +SH.FMC_D16.0=FMC_D16,sd-32b-d1 +SH.FMC_D16.ConfNb=1 +SH.FMC_D17.0=FMC_D17,sd-32b-d1 +SH.FMC_D17.ConfNb=1 +SH.FMC_D18.0=FMC_D18,sd-32b-d1 +SH.FMC_D18.ConfNb=1 +SH.FMC_D19.0=FMC_D19,sd-32b-d1 +SH.FMC_D19.ConfNb=1 +SH.FMC_D1_DA1.0=FMC_D1,sd-32b-d1 +SH.FMC_D1_DA1.ConfNb=1 +SH.FMC_D20.0=FMC_D20,sd-32b-d1 +SH.FMC_D20.ConfNb=1 +SH.FMC_D21.0=FMC_D21,sd-32b-d1 +SH.FMC_D21.ConfNb=1 +SH.FMC_D22.0=FMC_D22,sd-32b-d1 +SH.FMC_D22.ConfNb=1 +SH.FMC_D23.0=FMC_D23,sd-32b-d1 +SH.FMC_D23.ConfNb=1 +SH.FMC_D24.0=FMC_D24,sd-32b-d1 +SH.FMC_D24.ConfNb=1 +SH.FMC_D25.0=FMC_D25,sd-32b-d1 +SH.FMC_D25.ConfNb=1 +SH.FMC_D26.0=FMC_D26,sd-32b-d1 +SH.FMC_D26.ConfNb=1 +SH.FMC_D27.0=FMC_D27,sd-32b-d1 +SH.FMC_D27.ConfNb=1 +SH.FMC_D28.0=FMC_D28,sd-32b-d1 +SH.FMC_D28.ConfNb=1 +SH.FMC_D29.0=FMC_D29,sd-32b-d1 +SH.FMC_D29.ConfNb=1 +SH.FMC_D2_DA2.0=FMC_D2,sd-32b-d1 +SH.FMC_D2_DA2.ConfNb=1 +SH.FMC_D30.0=FMC_D30,sd-32b-d1 +SH.FMC_D30.ConfNb=1 +SH.FMC_D31.0=FMC_D31,sd-32b-d1 +SH.FMC_D31.ConfNb=1 +SH.FMC_D3_DA3.0=FMC_D3,sd-32b-d1 +SH.FMC_D3_DA3.ConfNb=1 +SH.FMC_D4_DA4.0=FMC_D4,sd-32b-d1 +SH.FMC_D4_DA4.ConfNb=1 +SH.FMC_D5_DA5.0=FMC_D5,sd-32b-d1 +SH.FMC_D5_DA5.ConfNb=1 +SH.FMC_D6_DA6.0=FMC_D6,sd-32b-d1 +SH.FMC_D6_DA6.ConfNb=1 +SH.FMC_D7_DA7.0=FMC_D7,sd-32b-d1 +SH.FMC_D7_DA7.ConfNb=1 +SH.FMC_D8_DA8.0=FMC_D8,sd-32b-d1 +SH.FMC_D8_DA8.ConfNb=1 +SH.FMC_D9_DA9.0=FMC_D9,sd-32b-d1 +SH.FMC_D9_DA9.ConfNb=1 +SH.FMC_SDCLK.0=FMC_SDCLK,12b-sda1 +SH.FMC_SDCLK.ConfNb=1 +SH.FMC_SDNCAS.0=FMC_SDNCAS,12b-sda1 +SH.FMC_SDNCAS.ConfNb=1 +SH.FMC_SDNRAS.0=FMC_SDNRAS,12b-sda1 +SH.FMC_SDNRAS.ConfNb=1 +SH.FMC_SDNWE.0=FMC_SDNWE,12b-sda1 +SH.FMC_SDNWE.ConfNb=1 SH.GPXTI15.0=GPIO_EXTI15 SH.GPXTI15.ConfNb=1 -SH.GPXTI7.0=GPIO_EXTI7 -SH.GPXTI7.ConfNb=1 -SH.S_TIM1_CH3.0=TIM1_CH3 +SH.S_TIM1_CH3.0=TIM1_CH3,PWM Generation3 CH3 SH.S_TIM1_CH3.ConfNb=1 SH.S_TIM2_CH1_ETR.0=TIM2_CH1,PWM Generation1 CH1 SH.S_TIM2_CH1_ETR.ConfNb=1 @@ -271,8 +471,8 @@ SPI1.Direction=SPI_DIRECTION_2LINES SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,DataSize,BaudRatePrescaler SPI1.Mode=SPI_MODE_MASTER SPI1.VirtualType=VM_MASTER -TIM1.Channel-PWM\ Generation3\ CH3N=TIM_CHANNEL_3 -TIM1.IPParameters=Period,Channel-PWM Generation3 CH3N,TIM_MasterOutputTrigger +TIM1.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3 +TIM1.IPParameters=Period,TIM_MasterOutputTrigger,Channel-PWM Generation3 CH3 TIM1.Period=180-1 TIM1.TIM_MasterOutputTrigger=TIM_TRGO_RESET TIM2.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1 diff --git a/projects/ad469x_iio/app/ad469x_iio.c b/projects/ad469x_iio/app/ad469x_iio.c index cdd4beb1f..ab0d1f1c7 100644 --- a/projects/ad469x_iio/app/ad469x_iio.c +++ b/projects/ad469x_iio/app/ad469x_iio.c @@ -117,6 +117,12 @@ static int8_t adc_data_buffer[DATA_BUFFER_SIZE]; /* Scale factor for gain correction */ #define AD469X_GAIN_CORR_SCALE(x) (float)(x) / (float)(ADC_MAX_COUNT_BIPOLAR) +/* Local buffer size */ +#define MAX_LOCAL_BUF_SIZE 8000 + +/* Maximum value the DMA NDTR register can take */ +#define MAX_DMA_NDTR (no_os_min(65535, MAX_LOCAL_BUF_SIZE/2)) + /******************************************************************************/ /*************************** Types Declarations *******************************/ /******************************************************************************/ @@ -289,6 +295,11 @@ struct no_os_dma_ch* rxch; /* Tx DMA channel descriptor */ struct no_os_dma_ch* txch; + +/* Local buffer */ +uint8_t local_buf[MAX_LOCAL_BUF_SIZE]; + +uint32_t callback_count; #endif /******************************************************************************/ @@ -810,6 +821,12 @@ static int32_t ad469x_adc_stop_data_capture(void) if (ret) { return ret; } +#if (DATA_CAPTURE_MODE == BURST_DATA_CAPTURE) + ret = ad469x_exit_conversion_mode(p_ad469x_dev); + if (ret) { + return ret; + } +#endif // DATA_CAPTURE_MODE #endif #if (INTERFACE_MODE == SPI_DMA) /* Stop timers */ @@ -907,7 +924,7 @@ static int32_t ad469x_iio_prepare_transfer(void *dev, uint32_t mask) } #if (DATA_CAPTURE_MODE == CONTINUOUS_DATA_CAPTURE) \ - || (INTERFACE_MODE == SPI_INTERRUPT) + && (INTERFACE_MODE == SPI_INTERRUPT) ret = ad469x_adc_start_data_capture(); if (ret) { return ret; @@ -920,23 +937,13 @@ static int32_t ad469x_iio_prepare_transfer(void *dev, uint32_t mask) } spi_init_param = ad469x_init_str.spi_init->extra; - spi_init_param->pwm_init = &cs_init_params; + spi_init_param->pwm_init = (const struct no_os_pwm_init_param *) + &cs_init_params; spi_init_param->dma_init = &ad469x_dma_init_param; - rxch = (struct no_os_dma_ch*)no_os_calloc(1, sizeof(*rxch)); - if (!rxch) - return -ENOMEM; - - txch = (struct no_os_dma_ch*)no_os_calloc(1, sizeof(*txch)); - if (!txch) - return -ENOMEM; - - rxch->irq_num = Rx_DMA_IRQ_ID; - rxch->extra = &rxdma_channel; - txch->extra = &txdma_channel; - - spi_init_param->rxdma_ch = rxch; - spi_init_param->txdma_ch = txch; + spi_init_param->irq_num = Rx_DMA_IRQ_ID; + spi_init_param->rxdma_ch = &rxdma_channel; + spi_init_param->txdma_ch = &txdma_channel; /* Init SPI interface in DMA Mode */ ret = no_os_spi_init(&p_ad469x_dev->spi_desc, ad469x_init_str.spi_init); @@ -953,9 +960,6 @@ static int32_t ad469x_iio_prepare_transfer(void *dev, uint32_t mask) if (ret) { return ret; } - - /* Configure Timer 1 parameters */ - tim1_config(); #endif return 0; @@ -1056,6 +1060,7 @@ static int32_t ad469x_iio_submit_samples(struct iio_device_data *iio_dev_data) ad469x_conversion_flag = false; uint16_t local_tx_data = 0; nb_of_samples = iio_dev_data->buffer->size / BYTES_PER_SAMPLE; + uint32_t spirxdma_ndtr; #if (INTERFACE_MODE == SPI_DMA) /* STM32 SPI Descriptor */ @@ -1072,7 +1077,7 @@ static int32_t ad469x_iio_submit_samples(struct iio_device_data *iio_dev_data) return -EINVAL; } - global_nb_of_samples = nb_of_samples; + global_nb_of_samples = nb_of_samples; global_iio_dev_data = iio_dev_data; if (!buf_size_updated) { @@ -1129,17 +1134,30 @@ static int32_t ad469x_iio_submit_samples(struct iio_device_data *iio_dev_data) } #else // SPI_DMA_MODE #if (DATA_CAPTURE_MODE == BURST_DATA_CAPTURE) + nb_of_samples *= BYTES_PER_SAMPLE; ret = no_os_cb_prepare_async_write(iio_dev_data->buffer->buf, - nb_of_samples * (BYTES_PER_SAMPLE), &buff_start_addr, &data_read); + nb_of_samples, &buff_start_addr, &data_read); if (ret) { return ret; } if (!dma_config_updated) { - ad469x_spi_msg.rx_buff = (uint32_t*)buff_start_addr; + /* Cap SPI RX DMA NDTR to MAX_DMA_NDTR. */ + spirxdma_ndtr = no_os_min(MAX_DMA_NDTR, nb_of_samples); + rxdma_ndtr = spirxdma_ndtr; + + /* Register half complete callback, for ping-pong buffers implementation. */ + HAL_DMA_RegisterCallback(&hdma_spi1_rx, + HAL_DMA_XFER_HALFCPLT_CB_ID, + halfcmplt_callback); + + /* Update the SPI message */ + ad469x_spi_msg.tx_buff = (uint32_t*)local_tx_data; + ad469x_spi_msg.rx_buff = (uint32_t*)local_buf; + ad469x_spi_msg.bytes_number = spirxdma_ndtr; ret = no_os_spi_transfer_dma_async(p_ad469x_dev->spi_desc, &ad469x_spi_msg, - 1, receivecomplete_callback, NULL); + 1, NULL, NULL); if (ret) { return ret; } @@ -1149,10 +1167,21 @@ static int32_t ad469x_iio_submit_samples(struct iio_device_data *iio_dev_data) htim1.Instance->CNT = 0; dma_config_updated = true; - /* Configure Tx trigger timer parameters */ - tim8_config(); + /* Disable the DMA to update the memory addresses and the no. of + data items to transfer */ + sdesc->hspi.hdmarx->Instance->CR &= ~DMA_SxCR_EN; + sdesc->hspi.hdmarx->Instance->M0AR = (uint32_t*)local_buf; + sdesc->hspi.hdmarx->Instance->NDTR = spirxdma_ndtr; + + /* Enable back the DMA */ + sdesc->hspi.hdmarx->Instance->CR |= DMA_SxCR_EN; } + dma_cycle_count = ((nb_of_samples) / rxdma_ndtr) + 1; + callback_count = dma_cycle_count * 2; + + update_buff(local_buf, buff_start_addr); + /* Enable Timers */ stm32_timer_enable(); @@ -1183,8 +1212,6 @@ static int32_t ad469x_iio_submit_samples(struct iio_device_data *iio_dev_data) htim2.Instance->CNT = 0; htim1.Instance->CNT = 0; dma_config_updated = true; - /* Configure Tx trigger timer parameters */ - tim8_config(); /* Enable timers */ stm32_timer_enable(); @@ -1359,7 +1386,6 @@ int32_t ad469x_iio_initialize(void) return init_status; } -#if !defined(DEV_AD4696) /* Read context attributes */ init_status = get_iio_context_attributes(&iio_init_params.ctx_attrs, &iio_init_params.nb_ctx_attr, @@ -1372,7 +1398,6 @@ int32_t ad469x_iio_initialize(void) } if (hw_mezzanine_is_valid) { -#endif /* Initialize AD469x device and peripheral interface */ init_status = ad469x_init(&p_ad469x_dev, &ad469x_init_str); if (init_status) { @@ -1397,13 +1422,11 @@ int32_t ad469x_iio_initialize(void) return init_status; } -#if !defined(DEV_AD4696) /* Configure the GP0 as the data ready pin */ init_status = ad469x_set_busy(p_ad469x_dev, AD469x_busy_gp0); if (init_status) { return init_status; } -#endif /* Register and initialize the AD469x device into IIO interface */ init_status = ad469x_iio_init(&p_ad469x_iio_dev); @@ -1425,10 +1448,7 @@ int32_t ad469x_iio_initialize(void) (DATA_CAPTURE_MODE == CONTINUOUS_DATA_CAPTURE) iio_init_params.nb_trigs++; #endif - -#if !defined(DEV_AD4696) } -#endif /* Initialize the IIO interface */ iio_init_params.uart_desc = uart_iio_com_desc; diff --git a/projects/ad469x_iio/app/ad469x_iio.h b/projects/ad469x_iio/app/ad469x_iio.h index 107e424e8..c1d53b212 100644 --- a/projects/ad469x_iio/app/ad469x_iio.h +++ b/projects/ad469x_iio/app/ad469x_iio.h @@ -33,6 +33,8 @@ /* AD469x global device instance for accessing device specific APIs */ extern struct ad469x_dev *p_ad469x_dev; +extern uint32_t callback_count; + /******************************************************************************/ /************************ Functions Declarations ******************************/ /******************************************************************************/ diff --git a/projects/ad469x_iio/app/app_config.c b/projects/ad469x_iio/app/app_config.c index ad561f77b..54b2dc42b 100644 --- a/projects/ad469x_iio/app/app_config.c +++ b/projects/ad469x_iio/app/app_config.c @@ -107,7 +107,7 @@ struct no_os_pwm_init_param pwm_init_params = { * also used to trigger a spi tx dma transaction. * */ .duty_cycle_ns = CNV_DUTY_RATIO_NS, - .polarity = NO_OS_PWM_POLARITY_HIGH, + .polarity = NO_OS_PWM_POLARITY_LOW, #else .duty_cycle_ns = CONV_TRIGGER_DUTY_CYCLE_NSEC(CONV_TRIGGER_PERIOD_NSEC(SAMPLING_RATE)), #endif diff --git a/projects/ad469x_iio/app/app_config.h b/projects/ad469x_iio/app/app_config.h index 555c6c928..356fc3059 100644 --- a/projects/ad469x_iio/app/app_config.h +++ b/projects/ad469x_iio/app/app_config.h @@ -131,17 +131,11 @@ #define ADC_RESOLUTION 16 // **** Note for User: Polarity Mode selection **** // -/* Since the pin pairing option is same for all the channels in - * standard sequencer mode, hence polarity mode for all the - * channels is also kept same to avoid stale ADC output codes. - * Make sure to change the JP6 jumper position on the Eval board to A - * to use the PSEUDO_BIPOLAR_MODE. - * - * Select Pseudo bipolar mode (default is unipolar mode) for all the channels. +/* Select the polarity mode. Default is unipolar. * e.g. #define PSEUDO_BIPOLAR_MODE -> This will enable the PSEUDO_BIPOLAR_MODE * for all the channels. * */ -#define DEFAULT_POLARITY_MODE PSEUDO_BIPOLAR_MODE +#define DEFAULT_POLARITY_MODE UNIPOLAR_MODE /* ADC max count (full scale value) for unipolar inputs */ #define ADC_MAX_COUNT_UNIPOLAR (uint32_t)((1 << ADC_RESOLUTION) - 1) @@ -222,6 +216,7 @@ extern struct no_os_pwm_init_param pwm_init_params; extern uint32_t global_nb_of_samples; extern volatile uint32_t* buff_start_addr; extern int32_t data_read; +extern struct no_os_pwm_desc* tx_trigger_desc; #endif /* Initializing system peripherals */ diff --git a/projects/ad469x_iio/app/app_config_mbed.h b/projects/ad469x_iio/app/app_config_mbed.h index 17c613c06..6081b482e 100644 --- a/projects/ad469x_iio/app/app_config_mbed.h +++ b/projects/ad469x_iio/app/app_config_mbed.h @@ -78,13 +78,13 @@ #define UART_IRQ 0 // Unused macro #define SPI_DEVICE_ID 0 // Unused macro #define SPI_CS_PIN_NUM ARDUINO_UNO_D10 -#define CNV_PIN_NUM ARDUINO_UNO_D9 +#define CNV_PIN_NUM ARDUINO_UNO_D6 #define CNV_PORT_NUM 0 // Unused macro #define GP0_PIN_NUM 0 // Unused macro #define GP0_PORT_NUM 0 // Unused macro #define GP1_PIN_NUM 0 // Unused macro #define GP1_PORT_NUM 0 // Unused macro -#define BSY_PIN_NUM ARDUINO_UNO_D2 +#define BSY_PIN_NUM ARDUINO_UNO_D9 #define BSY_PORT_NUM 0 // Unused macro #define RESET_PIN_NUM ARDUINO_UNO_D4 #define RESET_PORT_NUM 0 // Unused macro diff --git a/projects/ad469x_iio/app/app_config_stm32.c b/projects/ad469x_iio/app/app_config_stm32.c index cc083eb06..82ce1cefd 100644 --- a/projects/ad469x_iio/app/app_config_stm32.c +++ b/projects/ad469x_iio/app/app_config_stm32.c @@ -56,7 +56,8 @@ struct stm32_uart_init_param stm32_uart_extra_init_params = { /* STM32 SPI specific parameters */ struct stm32_spi_init_param stm32_spi_extra_init_params = { .chip_select_port = SPI_CS_PORT_NUM, - .get_input_clock = HAL_RCC_GetPCLK2Freq + .get_input_clock = HAL_RCC_GetPCLK2Freq, + .alternate = GPIO_AF1_TIM2 }; /* STM32 GPIO specific parameters */ @@ -85,7 +86,7 @@ struct stm32_gpio_init_param stm32_gpio_reset_extra_init_params = { /* STM32 GPIO IRQ specific parameters */ struct stm32_gpio_irq_init_param stm32_gpio_irq_extra_init_params = { - .port_nb = GP0_PORT_NUM, /* Port G */ + .port_nb = GP0_PORT_NUM, /* Port B */ }; /* STM32 PWM GPIO specific parameters */ @@ -99,11 +100,13 @@ struct stm32_gpio_init_param stm32_pwm_gpio_extra_init_params = { struct stm32_pwm_init_param stm32_pwm_cnv_extra_init_params = { .prescaler = TIMER_1_PRESCALER, .timer_autoreload = true, - .mode = TIM_OC_PWM2, + .mode = TIM_OC_PWM1, .timer_chn = TIMER_CHANNEL_3, - .complementary_channel = true, + .complementary_channel = false, .get_timer_clock = HAL_RCC_GetPCLK2Freq, - .clock_divider = TIMER_1_CLK_DIVIDER + .clock_divider = TIMER_1_CLK_DIVIDER, + .trigger_enable = false, + .trigger_output = PWM_TRGO_OC1 }; #if (INTERFACE_MODE == SPI_DMA) @@ -126,7 +129,13 @@ struct stm32_pwm_init_param stm32_tx_trigger_extra_init_params = { .timer_chn = TIMER_CHANNEL_1, .complementary_channel = false, .get_timer_clock = HAL_RCC_GetPCLK1Freq, - .clock_divider = TIMER_8_CLK_DIVIDER + .clock_divider = TIMER_8_CLK_DIVIDER, + .trigger_enable = true, + .trigger_source = PWM_TS_ITR0, + .repetitions = 1, + .onepulse_enable = true, + .dma_enable = true, + .trigger_output = PWM_TRGO_RESET }; /* STM32 Tx DMA channel extra init params */ @@ -164,6 +173,26 @@ struct stm32_gpio_init_param stm32_cs_gpio_extra_init_params = { /* STM32 SPI Descriptor*/ volatile struct stm32_spi_desc* sdesc; + +/* Value of RXDMA NDTR Reg */ +uint32_t rxdma_ndtr; + +/* Number of times the DMA complete callback needs to be invoked for + * capturing the desired number of samples*/ +uint32_t dma_cycle_count = 0; + +/* IIO Buffer start index */ +uint8_t* iio_buf_start_idx; + +/* DMA Buffer Start index */ +uint8_t* dma_buf_start_idx; + +/* IIO Buffer present index */ +uint8_t* iio_buf_current_idx; + +/* DMA Buffer present index */ +uint8_t* dma_buf_current_idx; + #endif /******************************************************************************/ @@ -213,7 +242,8 @@ void stm32_timer_enable(void) #if (INTERFACE_MODE == SPI_DMA) sdesc = p_ad469x_dev->spi_desc->extra; - no_os_pwm_enable(sdesc->pwm_desc); // CS Pwm; + TIM8->DIER |= TIM_DIER_CC1DE; + no_os_pwm_enable(sdesc->pwm_desc); // CS PWM no_os_pwm_enable(pwm_desc); // CNV PWM #endif } @@ -228,9 +258,8 @@ void stm32_timer_stop(void) int ret; sdesc = p_ad469x_dev->spi_desc->extra; - no_os_pwm_disable(pwm_desc);// CNV PWM + no_os_pwm_disable(pwm_desc); // CNV PWM no_os_pwm_disable(sdesc->pwm_desc); // CS PWM - TIM8->DIER &= ~TIM_DIER_CC1DE; /* Disable RX DMA */ @@ -302,32 +331,10 @@ void stm32_cnv_output_gpio_config(bool is_gpio) #endif } -void tim1_config(void) -{ -#if (INTERFACE_MODE == SPI_DMA) - TIM1->EGR = TIM_EGR_UG;// Generate update event - TIM1->CR2 = (TIM_CR2_MMS_COMPARE_PULSE * - TIM_CR2_MMS_0); -#endif -} - -void tim8_config(void) -{ -#if (INTERFACE_MODE == SPI_DMA) - TIM8->RCR = BYTES_PER_SAMPLE - 1; - TIM8->CCMR1 = (TIM_CCMR_CCS_OUTPUT * TIM_CCMR1_CC1S_0); - TIM8->EGR = TIM_EGR_UG;// Generate update event - TIM8->SMCR = (TIM_ITR_SOURCE * TIM_SMCR_TS_0) - | (TIM_SMCR_SMS_TRIGGER * - TIM_SMCR_SMS_0); - TIM8->CR1 = (1 * TIM_CR1_OPM); // Enable one pulse mode - TIM8->DIER |= TIM_DIER_CC1DE; // Generate DMA request after overflow -#endif -} - /** * @brief Callback function to flag the capture of number * of requested samples. + * @param hdma - DMA handler (Unused) * @return None */ @@ -337,16 +344,86 @@ void receivecomplete_callback(DMA_HandleTypeDef* hdma) #if (DATA_CAPTURE_MODE == BURST_DATA_CAPTURE) sdesc = p_ad469x_dev->spi_desc->extra; - no_os_pwm_disable(sdesc->pwm_desc); // CS PWM - no_os_pwm_disable(pwm_desc);// CNV PWM - htim2.Instance->CNT = 0; + /* Update samples captured so far */ + dma_cycle_count -= 1; - ad469x_conversion_flag = true; + if (!dma_cycle_count) { + ad469x_conversion_flag = true; + memcpy((void*)iio_buf_current_idx, dma_buf_current_idx, rxdma_ndtr / 2); -#else (DATA_CAPTURE_MODE == CONTINUOUS_DATA_CAPTURE) + iio_buf_current_idx = iio_buf_start_idx; + dma_buf_current_idx = dma_buf_start_idx; + } else { + memcpy((void*)iio_buf_current_idx, dma_buf_current_idx, rxdma_ndtr / 2); + + dma_buf_current_idx = dma_buf_start_idx; + iio_buf_current_idx += rxdma_ndtr / 2; + + } + callback_count--; +#else no_os_cb_end_async_write(global_iio_dev_data->buffer->buf); no_os_cb_prepare_async_write(global_iio_dev_data->buffer->buf, global_nb_of_samples * (BYTES_PER_SAMPLE), &buff_start_addr, &data_read); #endif // DATA_CAPTURE_MODE #endif // INTERFACE_MODE +} + +/** + * @brief Callback function to flag the capture of Half the number + * of requested samples. + * @param hdma - DMA Handler (Unused) + * @return None + */ +void halfcmplt_callback(DMA_HandleTypeDef* hdma) +{ +#if (INTERFACE_MODE == SPI_DMA) + if (!dma_cycle_count) { + return; + } + + /* Copy first half of the data to the IIO buffer */ + memcpy((void*)iio_buf_current_idx, dma_buf_current_idx, rxdma_ndtr / 2); + + dma_buf_current_idx += rxdma_ndtr / 2; + iio_buf_current_idx += rxdma_ndtr / 2; + + callback_count--; +#endif +} + +/** + * @brief Update buffer index + * @param local_buf[out] - Local Buffer + * @param buf_start_addr[out] - Buffer start addr + * @return None + */ +void update_buff(uint32_t* local_buf, uint32_t* buf_start_addr) +{ +#if (INTERFACE_MODE == SPI_DMA) + iio_buf_start_idx = (uint8_t*)buf_start_addr; + dma_buf_start_idx = (uint8_t*)local_buf; + + iio_buf_current_idx = iio_buf_start_idx; + dma_buf_current_idx = dma_buf_start_idx; +#endif +} + +/** + * @brief DMA2 Stream0 IRQ Handler + * @param None + * @return None + */ +void DMA2_Stream0_IRQHandler(void) +{ + /* Stop Tx trigger DMA and CNV timer at the last entry + to the callback */ +#if (DATA_CAPTURE_MODE == BURST_DATA_CAPTURE) + if (callback_count == 1) { + TIM8->DIER &= ~TIM_DIER_CC1DE; + no_os_pwm_disable(pwm_desc); + no_os_pwm_disable(sdesc->pwm_desc); + } +#endif + HAL_DMA_IRQHandler(&hdma_spi1_rx); } \ No newline at end of file diff --git a/projects/ad469x_iio/app/app_config_stm32.h b/projects/ad469x_iio/app/app_config_stm32.h index 1b239bcea..a514075cc 100644 --- a/projects/ad469x_iio/app/app_config_stm32.h +++ b/projects/ad469x_iio/app/app_config_stm32.h @@ -44,11 +44,11 @@ #define SPI_CS_PIN_NUM 15 // PA_15 #define SPI_CS_PORT_BASE GPIOA #define SPI_CS_PORT_NUM 0 // PORTA = 0 -#define CNV_PIN_NUM 15 // PB_15 -#define CNV_PORT_NUM 1 // PORTB = 1 -#define CNV_PORT_BASE GPIOB -#define GP0_PIN_NUM 7 // PG_7 -#define GP0_PORT_NUM 6 // PORTG = 6 +#define CNV_PIN_NUM 10 // PA_10 +#define CNV_PORT_NUM 0 // PORTA = 0 +#define CNV_PORT_BASE GPIOA +#define GP0_PIN_NUM 15 // PB_15 +#define GP0_PORT_NUM 1 // PORTB = 1 #define GP1_PIN_NUM 10 // PG_10 #define GP1_PORT_NUM 6 // PORTG = 6 #define BSY_PIN_NUM GP0_PIN_NUM @@ -99,7 +99,7 @@ * above this ODR on IIO oscilloscope */ #if (INTERFACE_MODE == SPI_INTERRUPT) -#define SAMPLING_RATE (62500) +#define SAMPLING_RATE (50000) #define CONV_TRIGGER_DUTY_CYCLE_NSEC(x) (x / 10) #else #define SAMPLING_RATE (500000) @@ -113,7 +113,7 @@ #define TX_TRIGGER_PERIOD 406 #define TX_TRIGGER_DUTY_RATIO 50 -#define CNV_DUTY_RATIO_NS 1310 +#define CNV_DUTY_RATIO_NS 690 /******************************************************************************/ /********************** Public/Extern Declarations ****************************/ @@ -145,15 +145,17 @@ extern DMA_HandleTypeDef hdma_tim8_ch1; extern struct stm32_dma_channel rxdma_channel; extern struct stm32_dma_channel txdma_channel; extern struct stm32_gpio_init_param stm32_cs_pwm_gpio_extra_init_params; +extern uint32_t rxdma_ndtr; +extern uint32_t dma_cycle_count; void receivecomplete_callback(DMA_HandleTypeDef* hdma); +void halfcmplt_callback(DMA_HandleTypeDef* hdma); +void update_buff(uint32_t* local_buf, uint32_t* buf_start_addr); void stm32_cnv_output_gpio_config(bool is_gpio); void stm32_cs_output_gpio_config(bool is_gpio); void stm32_abort_dma_transfer(void); void stm32_timer_enable(void); void stm32_timer_stop(void); -void tim8_config(void); -void tim1_config(void); #endif void stm32_system_init(void);