From ba098e423240f9f947afe98854f73bdf68840091 Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Mon, 26 Aug 2024 11:47:55 +0100 Subject: [PATCH 1/5] dma_sg: Test for IRQ Signed-off-by: Istvan-Zsolt Szekely --- dma_sg_2/Makefile | 63 +++++ dma_sg_2/README.md | 27 +++ dma_sg_2/cfgs/cfg1.tcl | 19 ++ dma_sg_2/environment.sv | 191 ++++++++++++++++ dma_sg_2/system_bd.tcl | 161 +++++++++++++ dma_sg_2/system_project.tcl | 47 ++++ dma_sg_2/system_tb.sv | 45 ++++ dma_sg_2/tests/test_program.sv | 407 +++++++++++++++++++++++++++++++++ dma_sg_2/waves/cfg1.wcfg | 114 +++++++++ 9 files changed, 1074 insertions(+) create mode 100644 dma_sg_2/Makefile create mode 100644 dma_sg_2/README.md create mode 100644 dma_sg_2/cfgs/cfg1.tcl create mode 100644 dma_sg_2/environment.sv create mode 100644 dma_sg_2/system_bd.tcl create mode 100644 dma_sg_2/system_project.tcl create mode 100644 dma_sg_2/system_tb.sv create mode 100644 dma_sg_2/tests/test_program.sv create mode 100644 dma_sg_2/waves/cfg1.wcfg diff --git a/dma_sg_2/Makefile b/dma_sg_2/Makefile new file mode 100644 index 00000000..df753527 --- /dev/null +++ b/dma_sg_2/Makefile @@ -0,0 +1,63 @@ +#################################################################################### +#################################################################################### +## Copyright 2022(c) Analog Devices, Inc. +#################################################################################### +#################################################################################### + +# All test-bench dependencies except test programs +SV_DEPS += ../common/sv/utils.svh +SV_DEPS += ../common/sv/logger_pkg.sv +SV_DEPS += ../common/sv/reg_accessor.sv +SV_DEPS += ../common/sv/m_axis_sequencer.sv +SV_DEPS += ../common/sv/s_axis_sequencer.sv +SV_DEPS += ../common/sv/m_axi_sequencer.sv +SV_DEPS += ../common/sv/s_axi_sequencer.sv +SV_DEPS += ../common/sv/test_harness_env.sv +SV_DEPS += ../common/sv/adi_peripheral_pkg.sv +SV_DEPS += ../common/sv/adi_regmap_pkg.sv +SV_DEPS += ../common/sv/mailbox.sv +SV_DEPS += ../common/sv/x_monitor.sv +SV_DEPS += ../common/sv/scoreboard.sv +SV_DEPS += ../common/sv/dmac_api.sv +SV_DEPS += ../common/sv/dma_trans.sv +SV_DEPS += ../common/sv/adi_regmap_dmac_pkg.sv +SV_DEPS += environment.sv +SV_DEPS += system_tb.sv + +ENV_DEPS += system_project.tcl +ENV_DEPS += system_bd.tcl +ENV_DEPS +=../scripts/adi_sim.tcl +ENV_DEPS +=../scripts/run_sim.tcl + +LIB_DEPS := util_cdc +LIB_DEPS += util_axis_fifo +LIB_DEPS += axi_dmac + +# default test program +TP := test_program + +# config files should have the following format +# cfg__.tcl +CFG_FILES := $(notdir $(wildcard cfgs/cfg*.tcl)) +#$(warning $(CFG_FILES)) + +# List of tests and configuration combinations that has to be run +# Format is: : +TESTS := $(foreach cfg, $(basename $(CFG_FILES)), $(cfg):$(TP)) +#TESTS += cfg1_mm2mm_default:directed_test +#TESTS += cfg1:test_program +#TESTS += cfg2_fsync:test_program +#TESTS += cfg2_fsync:test_frame_delay + +include ../scripts/project-sim.mk + +# usage : +# +# run specific test on a specific configuration in gui mode +# make CFG=cfg2_fsync TST=test_frame_delay MODE=gui +# +# run all test from a configuration +# make cfg1_mm2mm_default + +#################################################################################### +#################################################################################### diff --git a/dma_sg_2/README.md b/dma_sg_2/README.md new file mode 100644 index 00000000..f1495cb4 --- /dev/null +++ b/dma_sg_2/README.md @@ -0,0 +1,27 @@ +Usage : + +Run all tests in batch mode: + + make + + +Run all tests in GUI mode: + + make MODE=gui + + +Run specific test on a specific configuration in gui mode: + + make CFG= TST= MODE=gui + + +Run all test from a configuration: + + make + + +Where: + + * is a file from the cfgs directory without the tcl extension of format cfg\* + * is a file from the tests directory without the tcl extension + diff --git a/dma_sg_2/cfgs/cfg1.tcl b/dma_sg_2/cfgs/cfg1.tcl new file mode 100644 index 00000000..2418b5b4 --- /dev/null +++ b/dma_sg_2/cfgs/cfg1.tcl @@ -0,0 +1,19 @@ +global ad_project_params + +set ad_project_params(ADC_DATA_PATH_WIDTH) 16 ; ## +set ad_project_params(DAC_DATA_PATH_WIDTH) 16 ; ## + +set ad_project_params(ADC_PATH_TYPE) 0 ; ## RX +set ad_project_params(ADC_OFFLOAD_MEM_TYPE) 0 ; ## External storage +set ad_project_params(ADC_OFFLOAD_SIZE) 2048 ; ## Storage size in bytes +set ad_project_params(ADC_OFFLOAD_SRC_DWIDTH) 128 ; ## Source data width +set ad_project_params(ADC_OFFLOAD_DST_DWIDTH) 128 ; ## Destination data width + +set ad_project_params(DAC_PATH_TYPE) 0 ; ## TX +set ad_project_params(DAC_OFFLOAD_MEM_TYPE) 0 ; ## External storage +set ad_project_params(DAC_OFFLOAD_SIZE) 2048 ; ## Storage size in bytes +set ad_project_params(DAC_OFFLOAD_SRC_DWIDTH) 128 ; ## Source data width +set ad_project_params(DAC_OFFLOAD_DST_DWIDTH) 128 ; ## Destination data width + +set ad_project_params(PLDDR_OFFLOAD_DATA_WIDTH) 512 ; ## PLDDR's AXI4 interface data width + diff --git a/dma_sg_2/environment.sv b/dma_sg_2/environment.sv new file mode 100644 index 00000000..66d9165a --- /dev/null +++ b/dma_sg_2/environment.sv @@ -0,0 +1,191 @@ +`include "utils.svh" + +package environment_pkg; + + import m_axi_sequencer_pkg::*; + import s_axi_sequencer_pkg::*; + import m_axis_sequencer_pkg::*; + import s_axis_sequencer_pkg::*; + import logger_pkg::*; + + import axi_vip_pkg::*; + import axi4stream_vip_pkg::*; + import test_harness_env_pkg::*; + import scoreboard_pkg::*; + import x_monitor_pkg::*; + + import `PKGIFY(test_harness, mng_axi_vip)::*; + import `PKGIFY(test_harness, ddr_axi_vip)::*; + + import `PKGIFY(test_harness, adc_src_axis)::*; + import `PKGIFY(test_harness, dac_dst_axis)::*; + import `PKGIFY(test_harness, adc_dst_axi_pt)::*; + import `PKGIFY(test_harness, dac_src_axi_pt)::*; + + class environment extends test_harness_env; + + // agents and sequencers + `AGENT(test_harness, adc_src_axis, mst_t) adc_src_axis_agent; + `AGENT(test_harness, dac_dst_axis, slv_t) dac_dst_axis_agent; + `AGENT(test_harness, adc_dst_axi_pt, passthrough_mem_t) adc_dst_axi_pt_agent; + `AGENT(test_harness, dac_src_axi_pt, passthrough_mem_t) dac_src_axi_pt_agent; + + m_axis_sequencer #(`AGENT(test_harness, adc_src_axis, mst_t), + `AXIS_VIP_PARAMS(test_harness, adc_src_axis) + ) adc_src_axis_seq; + s_axis_sequencer #(`AGENT(test_harness, dac_dst_axis, slv_t)) dac_dst_axis_seq; + s_axi_sequencer #(`AGENT(test_harness, adc_dst_axi_pt, passthrough_mem_t)) adc_dst_axi_pt_seq; + s_axi_sequencer #(`AGENT(test_harness, dac_src_axi_pt, passthrough_mem_t)) dac_src_axi_pt_seq; + + x_axis_monitor #(`AGENT(test_harness, adc_src_axis, mst_t)) adc_src_axis_mon; + x_axis_monitor #(`AGENT(test_harness, dac_dst_axis, slv_t)) dac_dst_axis_mon; + x_axi_monitor #(`AGENT(test_harness, adc_dst_axi_pt, passthrough_mem_t), WRITE_OP) adc_dst_axi_pt_mon; + x_axi_monitor #(`AGENT(test_harness, dac_src_axi_pt, passthrough_mem_t), READ_OP) dac_src_axi_pt_mon; + + scoreboard scoreboard_tx; + scoreboard scoreboard_rx; + + //============================================================================ + // Constructor + //============================================================================ + function new ( + virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(10)) sys_clk_vip_if, + virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(5)) dma_clk_vip_if, + virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(2.5)) ddr_clk_vip_if, + + virtual interface rst_vip_if #(.C_ASYNCHRONOUS(1), .C_RST_POLARITY(1)) sys_rst_vip_if, + + virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, mng_axi_vip)) mng_vip_if, + virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, ddr_axi_vip)) ddr_vip_if, + + virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, adc_src_axis)) adc_src_axis_vip_if, + virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, dac_dst_axis)) dac_dst_axis_vip_if, + virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, adc_dst_axi_pt)) adc_dst_axi_pt_vip_if, + virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, dac_src_axi_pt)) dac_src_axi_pt_vip_if + ); + + // creating the agents + super.new(sys_clk_vip_if, + dma_clk_vip_if, + ddr_clk_vip_if, + sys_rst_vip_if, + mng_vip_if, + ddr_vip_if); + + adc_src_axis_agent = new("ADC Source AXI Stream Agent", adc_src_axis_vip_if); + dac_dst_axis_agent = new("DAC Destination AXI Stream Agent", dac_dst_axis_vip_if); + adc_dst_axi_pt_agent = new("ADC Destination AXI Agent", adc_dst_axi_pt_vip_if); + dac_src_axi_pt_agent = new("DAC Source AXI Agent", dac_src_axi_pt_vip_if); + + adc_src_axis_seq = new(adc_src_axis_agent); + dac_dst_axis_seq = new(dac_dst_axis_agent); + adc_dst_axi_pt_seq = new(adc_dst_axi_pt_agent); + dac_src_axi_pt_seq = new(dac_src_axi_pt_agent); + + adc_src_axis_mon = new("ADC Source AXIS Transaction Monitor", adc_src_axis_agent); + dac_dst_axis_mon = new("DAC Destination AXIS Transaction Monitor", dac_dst_axis_agent); + adc_dst_axi_pt_mon = new("ADC Destination AXI Transaction Monitor", adc_dst_axi_pt_agent); + dac_src_axi_pt_mon = new("DAC Source AXI Transaction Monitor", dac_src_axi_pt_agent); + + scoreboard_tx = new("Data Offload Verification Environment TX Scoreboard"); + scoreboard_rx = new("Data Offload Verification Environment RX Scoreboard"); + + endfunction + + //============================================================================ + // Configure environment + // - Configure the sequencer VIPs with an initial configuration before starting them + //============================================================================ + task configure(); + + // ADC stub + adc_src_axis_seq.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); + adc_src_axis_seq.set_keep_all(); + + // DAC stub + dac_dst_axis_seq.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); + + endtask + + //============================================================================ + // Start environment + // - Connect all the agents to the scoreboard + // - Start the agents + //============================================================================ + task start(); + + super.start(); + + adc_src_axis_agent.start_master(); + dac_dst_axis_agent.start_slave(); + adc_dst_axi_pt_agent.start_monitor(); + dac_src_axi_pt_agent.start_monitor(); + + scoreboard_tx.set_source_stream(dac_src_axi_pt_mon); + scoreboard_tx.set_sink_stream(dac_dst_axis_mon); + + scoreboard_rx.set_source_stream(adc_src_axis_mon); + scoreboard_rx.set_sink_stream(adc_dst_axi_pt_mon); + + endtask + + //============================================================================ + // Start the test + // - start the RX scoreboard and sequencer + // - start the TX scoreboard and sequencer + // - setup the RX DMA + // - setup the TX DMA + //============================================================================ + task test(); + + fork + adc_src_axis_seq.run(); + dac_dst_axis_seq.run(); + + adc_src_axis_mon.run(); + dac_dst_axis_mon.run(); + adc_dst_axi_pt_mon.run(); + dac_src_axi_pt_mon.run(); + + scoreboard_tx.run(); + scoreboard_rx.run(); + join_none + + endtask + + + //============================================================================ + // Post test subroutine + //============================================================================ + task post_test(); + // Evaluate the scoreboard's results + endtask + + //============================================================================ + // Run subroutine + //============================================================================ + task run; + + //pre_test(); + test(); + + endtask + + //============================================================================ + // Stop subroutine + //============================================================================ + task stop; + + super.stop(); + + adc_src_axis_seq.stop(); + adc_src_axis_agent.stop_master(); + dac_dst_axis_agent.stop_slave(); + + post_test(); + + endtask + + endclass + +endpackage diff --git a/dma_sg_2/system_bd.tcl b/dma_sg_2/system_bd.tcl new file mode 100644 index 00000000..5b9c4cab --- /dev/null +++ b/dma_sg_2/system_bd.tcl @@ -0,0 +1,161 @@ +# *************************************************************************** +# *************************************************************************** +# Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +# +# In this HDL repository, there are many different and unique modules, consisting +# of various HDL (Verilog or VHDL) components. The individual modules are +# developed independently, and may be accompanied by separate and unique license +# terms. +# +# The user should read each of these license terms, and understand the +# freedoms and responsibilities that he or she has by using this source/core. +# +# This core is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +# A PARTICULAR PURPOSE. +# +# Redistribution and use of source or resulting binaries, with or without modification +# of this file, are permitted under one of the following two license terms: +# +# 1. The GNU General Public License version 2 as published by the +# Free Software Foundation, which can be found in the top level directory +# of this repository (LICENSE_GPL2), and also online at: +# +# +# OR +# +# 2. An ADI specific BSD license, which can be found in the top level directory +# of this repository (LICENSE_ADIBSD), and also on-line at: +# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# This will allow to generate bit files and not release the source code, +# as long as it attaches to an ADI device. +# +# *************************************************************************** +# *************************************************************************** + +global ad_hdl_dir + +source ../../scripts/adi_env.tcl + +global ad_project_params + +## DUT configuration + +set adc_data_path_width $ad_project_params(ADC_DATA_PATH_WIDTH) +set dac_data_path_width $ad_project_params(DAC_DATA_PATH_WIDTH) + +set adc_path_type $ad_project_params(ADC_PATH_TYPE) +set adc_offload_mem_type $ad_project_params(ADC_OFFLOAD_MEM_TYPE) +set adc_offload_size $ad_project_params(ADC_OFFLOAD_SIZE) +set adc_offload_src_dwidth $ad_project_params(ADC_OFFLOAD_SRC_DWIDTH) +set adc_offload_dst_dwidth $ad_project_params(ADC_OFFLOAD_DST_DWIDTH) + +set dac_path_type $ad_project_params(DAC_PATH_TYPE) +set dac_offload_mem_type $ad_project_params(DAC_OFFLOAD_MEM_TYPE) +set dac_offload_size $ad_project_params(DAC_OFFLOAD_SIZE) +set dac_offload_src_dwidth $ad_project_params(DAC_OFFLOAD_SRC_DWIDTH) +set dac_offload_dst_dwidth $ad_project_params(DAC_OFFLOAD_DST_DWIDTH) + +set plddr_offload_data_width $ad_project_params(PLDDR_OFFLOAD_DATA_WIDTH) + +set ddr_axi_pt_cfg [list \ + INTERFACE_MODE {PASS_THROUGH} \ +] + +ad_ip_instance axi_dmac i_rx_dmac [list \ + DMA_TYPE_SRC 1 \ + DMA_TYPE_DEST 0 \ + ID 0 \ + AXI_SLICE_SRC 1 \ + AXI_SLICE_DEST 1 \ + SYNC_TRANSFER_START 0 \ + DMA_LENGTH_WIDTH 24 \ + DMA_2D_TRANSFER 0 \ + DMA_SG_TRANSFER 1 \ + MAX_BYTES_PER_BURST 4096 \ + CYCLIC 0 \ + DMA_DATA_WIDTH_SRC 512 \ + DMA_DATA_WIDTH_DEST 512 \ + SG_SLOW_TRANSFER 1 \ +] + +ad_ip_instance axi_dmac i_tx_dmac [list \ + DMA_TYPE_SRC 0 \ + DMA_TYPE_DEST 1 \ + ID 0 \ + AXI_SLICE_SRC 1 \ + AXI_SLICE_DEST 1 \ + SYNC_TRANSFER_START 0 \ + DMA_LENGTH_WIDTH 24 \ + DMA_2D_TRANSFER 0 \ + DMA_SG_TRANSFER 1 \ + MAX_BYTES_PER_BURST 4096 \ + CYCLIC 0 \ + DMA_DATA_WIDTH_SRC 512 \ + DMA_DATA_WIDTH_DEST 512 \ +] + +set RX_DMA_BA 0x50000000 +ad_cpu_interconnect ${RX_DMA_BA} i_rx_dmac +adi_sim_add_define "RX_DMA_BA=[format "%d" ${RX_DMA_BA}]" + +set TX_DMA_BA 0x50010000 +ad_cpu_interconnect ${TX_DMA_BA} i_tx_dmac +adi_sim_add_define "TX_DMA_BA=[format "%d" ${TX_DMA_BA}]" + +ad_ip_instance axi4stream_vip adc_src_axis [list \ + INTERFACE_MODE {MASTER} \ + HAS_TREADY {1} \ + HAS_TLAST {1} \ + HAS_TKEEP {1} \ + TDATA_NUM_BYTES 64 \ +] +adi_sim_add_define "ADC_SRC_AXIS=adc_src_axis" + +ad_connect adc_src_axis/m_axis i_rx_dmac/s_axis + +ad_connect sys_dma_clk adc_src_axis/aclk +ad_connect sys_dma_resetn adc_src_axis/aresetn + +ad_connect sys_dma_clk i_rx_dmac/s_axis_aclk +ad_connect sys_mem_clk i_rx_dmac/m_dest_axi_aclk +ad_connect sys_mem_resetn i_rx_dmac/m_dest_axi_aresetn + +ad_ip_instance axi_vip adc_dst_axi_pt $ddr_axi_pt_cfg +adi_sim_add_define "ADC_DST_AXI_PT=adc_dst_axi_pt" + +ad_connect i_rx_dmac/m_dest_axi adc_dst_axi_pt/S_AXI + +ad_mem_hp0_interconnect sys_mem_clk adc_dst_axi_pt/M_AXI +ad_connect sys_mem_resetn adc_dst_axi_pt/aresetn + +ad_mem_hp0_interconnect sys_mem_clk i_rx_dmac/m_sg_axi +ad_connect sys_mem_resetn i_rx_dmac/m_sg_axi_aresetn + +ad_ip_instance axi4stream_vip dac_dst_axis [list \ + INTERFACE_MODE {SLAVE} \ + TDATA_NUM_BYTES 64 \ + HAS_TLAST {1} \ + HAS_TKEEP {1} \ +] +adi_sim_add_define "DAC_DST_AXIS=dac_dst_axis" + +ad_connect sys_dma_clk dac_dst_axis/aclk +ad_connect sys_dma_resetn dac_dst_axis/aresetn + +ad_connect sys_dma_clk i_tx_dmac/m_axis_aclk +ad_connect sys_mem_clk i_tx_dmac/m_src_axi_aclk +ad_connect sys_mem_resetn i_tx_dmac/m_src_axi_aresetn + +ad_connect dac_dst_axis/s_axis i_tx_dmac/m_axis + +ad_ip_instance axi_vip dac_src_axi_pt $ddr_axi_pt_cfg +adi_sim_add_define "DAC_SRC_AXI_PT=dac_src_axi_pt" + +ad_connect i_tx_dmac/m_src_axi dac_src_axi_pt/S_AXI + +ad_mem_hp0_interconnect sys_mem_clk dac_src_axi_pt/M_AXI +ad_connect sys_mem_resetn dac_src_axi_pt/aresetn + +ad_mem_hp0_interconnect sys_mem_clk i_tx_dmac/m_sg_axi +ad_connect sys_mem_resetn i_tx_dmac/m_sg_axi_aresetn diff --git a/dma_sg_2/system_project.tcl b/dma_sg_2/system_project.tcl new file mode 100644 index 00000000..c672a4b8 --- /dev/null +++ b/dma_sg_2/system_project.tcl @@ -0,0 +1,47 @@ +source ../scripts/adi_sim.tcl +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +if {$argc < 1} { + puts "Expecting at least one argument that specifies the test configuration" + exit 1 +} else { + set cfg_file [lindex $argv 0] +} + +# Read config file +source "cfgs/${cfg_file}" + +# Set the project name +set project_name [file rootname $cfg_file] + +# Create the project +adi_sim_project_xilinx $project_name "xcvu9p-flga2104-2L-e" + +# Add test files to the project +adi_sim_project_files [list \ + "../common/sv/utils.svh" \ + "../common/sv/logger_pkg.sv" \ + "../common/sv/reg_accessor.sv" \ + "../common/sv/m_axis_sequencer.sv" \ + "../common/sv/s_axis_sequencer.sv" \ + "../common/sv/m_axi_sequencer.sv" \ + "../common/sv/s_axi_sequencer.sv" \ + "../common/sv/adi_peripheral_pkg.sv" \ + "../common/sv/adi_regmap_pkg.sv" \ + "../common/sv/test_harness_env.sv" \ + "../common/sv/mailbox.sv" \ + "../common/sv/x_monitor.sv" \ + "../common/sv/scoreboard.sv" \ + "../common/sv/dmac_api.sv" \ + "../common/sv/dma_trans.sv" \ + "../common/sv/adi_regmap_dmac_pkg.sv" \ + "environment.sv" \ + "tests/test_program.sv" \ + "system_tb.sv" \ + ] + +#set a default test program +adi_sim_add_define "TEST_PROGRAM=test_program" + +adi_sim_generate $project_name diff --git a/dma_sg_2/system_tb.sv b/dma_sg_2/system_tb.sv new file mode 100644 index 00000000..36eff4db --- /dev/null +++ b/dma_sg_2/system_tb.sv @@ -0,0 +1,45 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +`include "utils.svh" + +module system_tb(); + + `TEST_PROGRAM test(); + test_harness `TH (); + +endmodule diff --git a/dma_sg_2/tests/test_program.sv b/dma_sg_2/tests/test_program.sv new file mode 100644 index 00000000..685346da --- /dev/null +++ b/dma_sg_2/tests/test_program.sv @@ -0,0 +1,407 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// +// +// +`include "utils.svh" + +import axi_vip_pkg::*; +import axi4stream_vip_pkg::*; +import logger_pkg::*; +import environment_pkg::*; +import dmac_api_pkg::*; +import adi_regmap_pkg::*; +import adi_regmap_dmac_pkg::*; + +`define ADC_TRANSFER_LENGTH 32'h600 + +localparam DDR_BASE = 'h8000_0000; + +program test_program; + + // declare the class instances + environment env; + + dmac_api dmac_tx; + dmac_api dmac_rx; + + int val; + + initial begin + + // create environment + env = new(`TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF, + + `TH.`ADC_SRC_AXIS.inst.IF, + `TH.`DAC_DST_AXIS.inst.IF, + `TH.`ADC_DST_AXI_PT.inst.IF, + `TH.`DAC_SRC_AXI_PT.inst.IF + ); + + dmac_tx = new("DMAC TX", env.mng, `TX_DMA_BA); + dmac_rx = new("DMAC RX", env.mng, `RX_DMA_BA); + + //========================================================================= + // Setup generator/monitor stubs + //========================================================================= + + setLoggerVerbosity(10); + + env.start(); + env.sys_reset(); + + // configure environment sequencers + env.configure(); + + `INFO(("Bring up IP from reset.")); + systemBringUp(); + + // Start the ADC/DAC stubs + `INFO(("Call the run() ...")); + env.run(); + + // Init test data + `INFO(("Initialize the memory ...")); + for (int i=0;i<'h4000;i=i+2) begin + env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(DDR_BASE+i*2,(((i+1)) << 16) | i ,'hF); + end + + //========================================================================= + // TX Block descriptors + // DMA 1st Descriptor test data + init_mem_bd( + .bd_addr(DDR_BASE+'h1_0000), + .flags('h0003), + .id('h0001), + .dest_addr(DDR_BASE+'h0000), + .src_addr(DDR_BASE+'h0000), + .next_sg_addr(DDR_BASE+'h1_FFFF), + .y_len('h0000), + .x_len('h0057)); + + // DMA 2nd Descriptor test data + init_mem_bd( + .bd_addr(DDR_BASE+'h1_0030), + .flags('h0003), + .id('h0002), + .dest_addr(DDR_BASE+'h0000), + .src_addr(DDR_BASE+'h1000), + .next_sg_addr(DDR_BASE+'h1_FFFF), + .y_len('h0000), + .x_len('h0024)); + + // DMA 3rd Descriptor test data + init_mem_bd( + .bd_addr(DDR_BASE+'h1_0060), + .flags('h0003), + .id('h0003), + .dest_addr(DDR_BASE+'h0000), + .src_addr(DDR_BASE+'h2000), + .next_sg_addr(DDR_BASE+'h1_FFFF), + .y_len('h0000), + .x_len('h0199)); + + // DMA 4th Descriptor test data + init_mem_bd( + .bd_addr(DDR_BASE+'h1_0090), + .flags('h0003), + .id('hCDEF), + .dest_addr(DDR_BASE+'h0000), + .src_addr(DDR_BASE+'h3000), + .next_sg_addr(DDR_BASE+'h1_FFFF), + .y_len('h0000), + .x_len('h0FFF)); + + // DMA 5th Descriptor test data + init_mem_bd( + .bd_addr(DDR_BASE+'h1_00C0), + .flags('h0003), + .id('hAABB), + .dest_addr(DDR_BASE+'h0000), + .src_addr(DDR_BASE+'h4000), + .next_sg_addr(DDR_BASE+'h1_FFFF), + .y_len('h0000), + .x_len('h0FFF)); + + // DMA 6th Descriptor test data + init_mem_bd( + .bd_addr(DDR_BASE+'h1_00F0), + .flags('h0003), + .id('hCCDD), + .dest_addr(DDR_BASE+'h0000), + .src_addr(DDR_BASE+'h5000), + .next_sg_addr(DDR_BASE+'h1_FFFF), + .y_len('h0000), + .x_len('h0FFF)); + + // DMA 7th Descriptor test data + init_mem_bd( + .bd_addr(DDR_BASE+'h1_0120), + .flags('h0003), + .id('hEEFF), + .dest_addr(DDR_BASE+'h0000), + .src_addr(DDR_BASE+'h6000), + .next_sg_addr(DDR_BASE+'h1_FFFF), + .y_len('h0000), + .x_len('h0FFF)); + + // DMA 8th Descriptor test data + init_mem_bd( + .bd_addr(DDR_BASE+'h1_0150), + .flags('h0003), + .id('h1234), + .dest_addr(DDR_BASE+'h0000), + .src_addr(DDR_BASE+'h7000), + .next_sg_addr(DDR_BASE+'h1_FFFF), + .y_len('h0000), + .x_len('h0FFF)); + + //========================================================================= + // RX Block descriptors + // DMA 1st Descriptor test data + init_mem_bd( + .bd_addr(DDR_BASE+'h1_1000), + .flags('h0002), + .id('h3210), + .dest_addr(DDR_BASE+'h8000), + .src_addr(DDR_BASE+'h0000), + .next_sg_addr(DDR_BASE+'h1_1030), + .y_len('h0000), + .x_len('hFFFF)); + + // DMA 2nd Descriptor test data + init_mem_bd( + .bd_addr(DDR_BASE+'h1_1030), + .flags('h0002), + .id('h7654), + .dest_addr(DDR_BASE+'h9000), + .src_addr(DDR_BASE+'h0000), + .next_sg_addr(DDR_BASE+'h1_1060), + .y_len('h0000), + .x_len('hFFFF)); + + // DMA 3rd Descriptor test data + init_mem_bd( + .bd_addr(DDR_BASE+'h1_1060), + .flags('h0002), + .id('hBA98), + .dest_addr(DDR_BASE+'hA000), + .src_addr(DDR_BASE+'h0000), + .next_sg_addr(DDR_BASE+'h1_1090), + .y_len('h0000), + .x_len('hFFFF)); + + // DMA 4th Descriptor test data + init_mem_bd( + .bd_addr(DDR_BASE+'h1_1090), + .flags('h0002), + .id('hFEDC), + .dest_addr(DDR_BASE+'hB000), + .src_addr(DDR_BASE+'h0000), + .next_sg_addr(DDR_BASE+'h1_10C0), + .y_len('h0000), + .x_len('hFFFF)); + + // DMA 5th Descriptor test data + init_mem_bd( + .bd_addr(DDR_BASE+'h1_10C0), + .flags('h0002), + .id('hDCDC), + .dest_addr(DDR_BASE+'hC000), + .src_addr(DDR_BASE+'h0000), + .next_sg_addr(DDR_BASE+'h1_10F0), + .y_len('h0000), + .x_len('hFFFF)); + + // DMA 6th Descriptor test data + init_mem_bd( + .bd_addr(DDR_BASE+'h1_10F0), + .flags('h0002), + .id('hFEFE), + .dest_addr(DDR_BASE+'hD000), + .src_addr(DDR_BASE+'h0000), + .next_sg_addr(DDR_BASE+'h1_1000), + .y_len('h0000), + .x_len('hFFFF)); + + //========================================================================= + // Test RX DMA + //========================================================================= + + env.adc_src_axis_seq.start(); + + // Generate DMA transfers + `INFO(("Start RX DMA ...")); + do_sg_transfer( + .dma_addr(`RX_DMA_BA), + .control(3'b101), + .flags(3'b110), + .irq_mask(3'b001), + .bd_addr(DDR_BASE+'h1_1000)); + + fork + forever + wait(`TH.i_rx_dmac.irq) begin + env.mng.RegRead32(`RX_DMA_BA + GetAddrs(DMAC_PARTIAL_TRANSFER_LENGTH), val); + `INFO(("PTL: %d", val)); + env.mng.RegRead32(`RX_DMA_BA + GetAddrs(DMAC_PARTIAL_TRANSFER_ID), val); + `INFO(("PTID: %d", val)); + + env.mng.RegRead32(`RX_DMA_BA + GetAddrs(DMAC_DESCRIPTOR_ID), val); + `INFO(("BDID: %d", val)); + + env.mng.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_IRQ_PENDING), 2'b10); + end + join_none + + // create data packet of random size within limits + repeat($urandom_range(5, 10)) + env.adc_src_axis_seq.add_xfer_descriptor($urandom_range(32, 256), 1, 0); + + env.adc_src_axis_seq.wait_empty_descriptor_queue(); + env.scoreboard_rx.wait_until_complete(); + + //========================================================================= + // Test TX DMA + //========================================================================= + + `INFO(("Start TX DMA ...")); + for (int i=0; i<8; i++) + do_sg_transfer( + .dma_addr(`TX_DMA_BA), + .control(3'b101), + .flags(3'b010), + .irq_mask(3'b001), + .bd_addr(DDR_BASE+'h1_0000+i*'h30)); + + #1us; + env.scoreboard_tx.wait_until_complete(); + + env.stop(); + + `INFO(("Test bench done!")); + $finish(); + + end + + // bring up the DMAC instances from reset + task systemBringUp(); + `INFO(("Bring up RX DMAC")); + dmac_rx.enable_dma(); + `INFO(("Bring up TX DMAC")); + dmac_tx.enable_dma(); + endtask: systemBringUp + + // RX DMA transfer generator + task rx_dma_transfer( + input dmac_api dmac, + input int xfer_addr, + input int xfer_length); + + dmac.set_flags('b110); + dmac.set_dest_addr(xfer_addr); + dmac.set_lengths(xfer_length - 1, 0); + dmac.transfer_start(); + endtask: rx_dma_transfer + + task tx_dma_transfer( + input dmac_api dmac, + input int xfer_addr, + input int xfer_length); + + dmac.set_flags('b010); // enable TLAST, CYCLIC + dmac.set_src_addr(xfer_addr); + dmac.set_lengths(xfer_length - 1, 0); + dmac.transfer_start(); + endtask: tx_dma_transfer + + // Memory initialization function for a 8byte DATA_WIDTH AXI4 bus + task init_mem_64( + input longint unsigned addr, + input int byte_length); + + `INFO(("Initial address: %x", addr)); + for (int i=0; i + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RX + label + + + true + STYLE_ENUM_TRANSACTION + fff,fff=blank + true + #00E600 + /system_tb/test_harness/i_rx_dmac/s_axis.streamWaveData + 2 + /system_tb/test_harness/i_rx_dmac/s_axis.linkStarve + #99E600 + /system_tb/test_harness/i_rx_dmac/s_axis.linkStall + #E64C00 + /system_tb/test_harness/i_rx_dmac/s_axis.streamTooltipData + s_axis + s_axis + + + m_sg_axi + m_sg_axi + + + true + STYLE_ENUM_TRANSACTION + 0=blank 1=#D399FF 2=pink + 0=blank;1=Read;2=Write;3=Read/Write + true + turquoise + /system_tb/test_harness/i_rx_dmac/m_dest_axi.readWriteSummary + UNSIGNEDDECRADIX + 36 + m_dest_axi + m_dest_axi + + + irq + irq + + + TX + label + + + m_sg_axi + m_sg_axi + + + m_src_axi + m_src_axi + + + m_axis + m_axis + + + irq + irq + + From dc5a00036cd3f67fe530ce484a820ed420a37eac Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Mon, 26 Aug 2024 12:46:29 +0100 Subject: [PATCH 2/5] dma_sg: Updates and fixes - Fixed parameter name after change - Updated DDR address to use the defined variable - Updated test harness DDR base address define Signed-off-by: Istvan-Zsolt Szekely --- dma_sg_2/system_bd.tcl | 2 +- dma_sg_2/tests/test_program.sv | 120 +++++++++---------- library/utilities/test_harness_system_bd.tcl | 2 +- 3 files changed, 61 insertions(+), 63 deletions(-) diff --git a/dma_sg_2/system_bd.tcl b/dma_sg_2/system_bd.tcl index 5b9c4cab..bfc008b5 100644 --- a/dma_sg_2/system_bd.tcl +++ b/dma_sg_2/system_bd.tcl @@ -76,7 +76,7 @@ ad_ip_instance axi_dmac i_rx_dmac [list \ CYCLIC 0 \ DMA_DATA_WIDTH_SRC 512 \ DMA_DATA_WIDTH_DEST 512 \ - SG_SLOW_TRANSFER 1 \ + SG_DELAYED_INPUT 1 \ ] ad_ip_instance axi_dmac i_tx_dmac [list \ diff --git a/dma_sg_2/tests/test_program.sv b/dma_sg_2/tests/test_program.sv index 685346da..0d3863c3 100644 --- a/dma_sg_2/tests/test_program.sv +++ b/dma_sg_2/tests/test_program.sv @@ -47,8 +47,6 @@ import adi_regmap_dmac_pkg::*; `define ADC_TRANSFER_LENGTH 32'h600 -localparam DDR_BASE = 'h8000_0000; - program test_program; // declare the class instances @@ -100,96 +98,96 @@ program test_program; // Init test data `INFO(("Initialize the memory ...")); for (int i=0;i<'h4000;i=i+2) begin - env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(DDR_BASE+i*2,(((i+1)) << 16) | i ,'hF); + env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(`DDR_BA+i*2,(((i+1)) << 16) | i ,'hF); end //========================================================================= // TX Block descriptors // DMA 1st Descriptor test data init_mem_bd( - .bd_addr(DDR_BASE+'h1_0000), + .bd_addr(`DDR_BA+'h1_0000), .flags('h0003), .id('h0001), - .dest_addr(DDR_BASE+'h0000), - .src_addr(DDR_BASE+'h0000), - .next_sg_addr(DDR_BASE+'h1_FFFF), + .dest_addr(`DDR_BA+'h0000), + .src_addr(`DDR_BA+'h0000), + .next_sg_addr(`DDR_BA+'h1_FFFF), .y_len('h0000), .x_len('h0057)); // DMA 2nd Descriptor test data init_mem_bd( - .bd_addr(DDR_BASE+'h1_0030), + .bd_addr(`DDR_BA+'h1_0030), .flags('h0003), .id('h0002), - .dest_addr(DDR_BASE+'h0000), - .src_addr(DDR_BASE+'h1000), - .next_sg_addr(DDR_BASE+'h1_FFFF), + .dest_addr(`DDR_BA+'h0000), + .src_addr(`DDR_BA+'h1000), + .next_sg_addr(`DDR_BA+'h1_FFFF), .y_len('h0000), .x_len('h0024)); // DMA 3rd Descriptor test data init_mem_bd( - .bd_addr(DDR_BASE+'h1_0060), + .bd_addr(`DDR_BA+'h1_0060), .flags('h0003), .id('h0003), - .dest_addr(DDR_BASE+'h0000), - .src_addr(DDR_BASE+'h2000), - .next_sg_addr(DDR_BASE+'h1_FFFF), + .dest_addr(`DDR_BA+'h0000), + .src_addr(`DDR_BA+'h2000), + .next_sg_addr(`DDR_BA+'h1_FFFF), .y_len('h0000), .x_len('h0199)); // DMA 4th Descriptor test data init_mem_bd( - .bd_addr(DDR_BASE+'h1_0090), + .bd_addr(`DDR_BA+'h1_0090), .flags('h0003), .id('hCDEF), - .dest_addr(DDR_BASE+'h0000), - .src_addr(DDR_BASE+'h3000), - .next_sg_addr(DDR_BASE+'h1_FFFF), + .dest_addr(`DDR_BA+'h0000), + .src_addr(`DDR_BA+'h3000), + .next_sg_addr(`DDR_BA+'h1_FFFF), .y_len('h0000), .x_len('h0FFF)); // DMA 5th Descriptor test data init_mem_bd( - .bd_addr(DDR_BASE+'h1_00C0), + .bd_addr(`DDR_BA+'h1_00C0), .flags('h0003), .id('hAABB), - .dest_addr(DDR_BASE+'h0000), - .src_addr(DDR_BASE+'h4000), - .next_sg_addr(DDR_BASE+'h1_FFFF), + .dest_addr(`DDR_BA+'h0000), + .src_addr(`DDR_BA+'h4000), + .next_sg_addr(`DDR_BA+'h1_FFFF), .y_len('h0000), .x_len('h0FFF)); // DMA 6th Descriptor test data init_mem_bd( - .bd_addr(DDR_BASE+'h1_00F0), + .bd_addr(`DDR_BA+'h1_00F0), .flags('h0003), .id('hCCDD), - .dest_addr(DDR_BASE+'h0000), - .src_addr(DDR_BASE+'h5000), - .next_sg_addr(DDR_BASE+'h1_FFFF), + .dest_addr(`DDR_BA+'h0000), + .src_addr(`DDR_BA+'h5000), + .next_sg_addr(`DDR_BA+'h1_FFFF), .y_len('h0000), .x_len('h0FFF)); // DMA 7th Descriptor test data init_mem_bd( - .bd_addr(DDR_BASE+'h1_0120), + .bd_addr(`DDR_BA+'h1_0120), .flags('h0003), .id('hEEFF), - .dest_addr(DDR_BASE+'h0000), - .src_addr(DDR_BASE+'h6000), - .next_sg_addr(DDR_BASE+'h1_FFFF), + .dest_addr(`DDR_BA+'h0000), + .src_addr(`DDR_BA+'h6000), + .next_sg_addr(`DDR_BA+'h1_FFFF), .y_len('h0000), .x_len('h0FFF)); // DMA 8th Descriptor test data init_mem_bd( - .bd_addr(DDR_BASE+'h1_0150), + .bd_addr(`DDR_BA+'h1_0150), .flags('h0003), .id('h1234), - .dest_addr(DDR_BASE+'h0000), - .src_addr(DDR_BASE+'h7000), - .next_sg_addr(DDR_BASE+'h1_FFFF), + .dest_addr(`DDR_BA+'h0000), + .src_addr(`DDR_BA+'h7000), + .next_sg_addr(`DDR_BA+'h1_FFFF), .y_len('h0000), .x_len('h0FFF)); @@ -197,67 +195,67 @@ program test_program; // RX Block descriptors // DMA 1st Descriptor test data init_mem_bd( - .bd_addr(DDR_BASE+'h1_1000), + .bd_addr(`DDR_BA+'h1_1000), .flags('h0002), .id('h3210), - .dest_addr(DDR_BASE+'h8000), - .src_addr(DDR_BASE+'h0000), - .next_sg_addr(DDR_BASE+'h1_1030), + .dest_addr(`DDR_BA+'h8000), + .src_addr(`DDR_BA+'h0000), + .next_sg_addr(`DDR_BA+'h1_1030), .y_len('h0000), .x_len('hFFFF)); // DMA 2nd Descriptor test data init_mem_bd( - .bd_addr(DDR_BASE+'h1_1030), + .bd_addr(`DDR_BA+'h1_1030), .flags('h0002), .id('h7654), - .dest_addr(DDR_BASE+'h9000), - .src_addr(DDR_BASE+'h0000), - .next_sg_addr(DDR_BASE+'h1_1060), + .dest_addr(`DDR_BA+'h9000), + .src_addr(`DDR_BA+'h0000), + .next_sg_addr(`DDR_BA+'h1_1060), .y_len('h0000), .x_len('hFFFF)); // DMA 3rd Descriptor test data init_mem_bd( - .bd_addr(DDR_BASE+'h1_1060), + .bd_addr(`DDR_BA+'h1_1060), .flags('h0002), .id('hBA98), - .dest_addr(DDR_BASE+'hA000), - .src_addr(DDR_BASE+'h0000), - .next_sg_addr(DDR_BASE+'h1_1090), + .dest_addr(`DDR_BA+'hA000), + .src_addr(`DDR_BA+'h0000), + .next_sg_addr(`DDR_BA+'h1_1090), .y_len('h0000), .x_len('hFFFF)); // DMA 4th Descriptor test data init_mem_bd( - .bd_addr(DDR_BASE+'h1_1090), + .bd_addr(`DDR_BA+'h1_1090), .flags('h0002), .id('hFEDC), - .dest_addr(DDR_BASE+'hB000), - .src_addr(DDR_BASE+'h0000), - .next_sg_addr(DDR_BASE+'h1_10C0), + .dest_addr(`DDR_BA+'hB000), + .src_addr(`DDR_BA+'h0000), + .next_sg_addr(`DDR_BA+'h1_10C0), .y_len('h0000), .x_len('hFFFF)); // DMA 5th Descriptor test data init_mem_bd( - .bd_addr(DDR_BASE+'h1_10C0), + .bd_addr(`DDR_BA+'h1_10C0), .flags('h0002), .id('hDCDC), - .dest_addr(DDR_BASE+'hC000), - .src_addr(DDR_BASE+'h0000), - .next_sg_addr(DDR_BASE+'h1_10F0), + .dest_addr(`DDR_BA+'hC000), + .src_addr(`DDR_BA+'h0000), + .next_sg_addr(`DDR_BA+'h1_10F0), .y_len('h0000), .x_len('hFFFF)); // DMA 6th Descriptor test data init_mem_bd( - .bd_addr(DDR_BASE+'h1_10F0), + .bd_addr(`DDR_BA+'h1_10F0), .flags('h0002), .id('hFEFE), - .dest_addr(DDR_BASE+'hD000), - .src_addr(DDR_BASE+'h0000), - .next_sg_addr(DDR_BASE+'h1_1000), + .dest_addr(`DDR_BA+'hD000), + .src_addr(`DDR_BA+'h0000), + .next_sg_addr(`DDR_BA+'h1_1000), .y_len('h0000), .x_len('hFFFF)); @@ -274,7 +272,7 @@ program test_program; .control(3'b101), .flags(3'b110), .irq_mask(3'b001), - .bd_addr(DDR_BASE+'h1_1000)); + .bd_addr(`DDR_BA+'h1_1000)); fork forever @@ -309,7 +307,7 @@ program test_program; .control(3'b101), .flags(3'b010), .irq_mask(3'b001), - .bd_addr(DDR_BASE+'h1_0000+i*'h30)); + .bd_addr(`DDR_BA+'h1_0000+i*'h30)); #1us; env.scoreboard_tx.wait_until_complete(); diff --git a/library/utilities/test_harness_system_bd.tcl b/library/utilities/test_harness_system_bd.tcl index 13e8337d..91e12886 100644 --- a/library/utilities/test_harness_system_bd.tcl +++ b/library/utilities/test_harness_system_bd.tcl @@ -198,4 +198,4 @@ ad_connect irq axi_intc/irq set DDR_BASE 0x80000000 create_bd_addr_seg -range ${DDR_BASE} -offset ${DDR_BASE} [get_bd_addr_spaces /mng_axi_vip/Master_AXI] \ [get_bd_addr_segs ddr_axi_vip/S_AXI/Reg] SEG_mng_ddr_cntlr -adi_sim_add_define "DDR_BA=[format "%d" ${DDR_BASE}]" +adi_sim_add_define "DDR_BA='h[format "%X" ${DDR_BASE}]" From 8a56f2f18a53660b835cc19c79d33bda5bdd1e6b Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Tue, 8 Oct 2024 14:26:09 +0100 Subject: [PATCH 3/5] dma_sg: Changed DMA configuration Signed-off-by: Istvan-Zsolt Szekely --- dma_sg_2/system_bd.tcl | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/dma_sg_2/system_bd.tcl b/dma_sg_2/system_bd.tcl index bfc008b5..794aa07d 100644 --- a/dma_sg_2/system_bd.tcl +++ b/dma_sg_2/system_bd.tcl @@ -64,19 +64,20 @@ set ddr_axi_pt_cfg [list \ ad_ip_instance axi_dmac i_rx_dmac [list \ DMA_TYPE_SRC 1 \ - DMA_TYPE_DEST 0 \ - ID 0 \ - AXI_SLICE_SRC 1 \ - AXI_SLICE_DEST 1 \ - SYNC_TRANSFER_START 0 \ - DMA_LENGTH_WIDTH 24 \ - DMA_2D_TRANSFER 0 \ - DMA_SG_TRANSFER 1 \ - MAX_BYTES_PER_BURST 4096 \ - CYCLIC 0 \ - DMA_DATA_WIDTH_SRC 512 \ - DMA_DATA_WIDTH_DEST 512 \ - SG_DELAYED_INPUT 1 \ + DMA_TYPE_DEST 0 \ + ID 0 \ + AXI_SLICE_SRC 1 \ + AXI_SLICE_DEST 1 \ + SYNC_TRANSFER_START 0 \ + DMA_LENGTH_WIDTH 24 \ + DMA_2D_TRANSFER 0 \ + DMA_SG_TRANSFER 1 \ + MAX_BYTES_PER_BURST 2048 \ + CYCLIC 0 \ + DMA_DATA_WIDTH_SRC 512 \ + DMA_DATA_WIDTH_DEST 512 \ + SG_DELAYED_INPUT 1 \ + AXIS_TUSER_SYNC 0 \ ] ad_ip_instance axi_dmac i_tx_dmac [list \ @@ -89,10 +90,11 @@ ad_ip_instance axi_dmac i_tx_dmac [list \ DMA_LENGTH_WIDTH 24 \ DMA_2D_TRANSFER 0 \ DMA_SG_TRANSFER 1 \ - MAX_BYTES_PER_BURST 4096 \ + MAX_BYTES_PER_BURST 2048 \ CYCLIC 0 \ DMA_DATA_WIDTH_SRC 512 \ DMA_DATA_WIDTH_DEST 512 \ + AXIS_TUSER_SYNC 0 \ ] set RX_DMA_BA 0x50000000 From 6af370005964ac89bb2e6a74f22aa8d128cfae2d Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Fri, 18 Oct 2024 12:38:08 +0100 Subject: [PATCH 4/5] dma_sg: Moved IRQ test program to its proper directory Signed-off-by: Istvan-Zsolt Szekely --- {dma_sg_2 => testbenches/ip/dma_sg_2}/Makefile | 0 {dma_sg_2 => testbenches/ip/dma_sg_2}/README.md | 0 {dma_sg_2 => testbenches/ip/dma_sg_2}/cfgs/cfg1.tcl | 0 {dma_sg_2 => testbenches/ip/dma_sg_2}/environment.sv | 0 {dma_sg_2 => testbenches/ip/dma_sg_2}/system_bd.tcl | 0 {dma_sg_2 => testbenches/ip/dma_sg_2}/system_project.tcl | 0 {dma_sg_2 => testbenches/ip/dma_sg_2}/system_tb.sv | 0 {dma_sg_2 => testbenches/ip/dma_sg_2}/tests/test_program.sv | 0 {dma_sg_2 => testbenches/ip/dma_sg_2}/waves/cfg1.wcfg | 0 9 files changed, 0 insertions(+), 0 deletions(-) rename {dma_sg_2 => testbenches/ip/dma_sg_2}/Makefile (100%) rename {dma_sg_2 => testbenches/ip/dma_sg_2}/README.md (100%) rename {dma_sg_2 => testbenches/ip/dma_sg_2}/cfgs/cfg1.tcl (100%) rename {dma_sg_2 => testbenches/ip/dma_sg_2}/environment.sv (100%) rename {dma_sg_2 => testbenches/ip/dma_sg_2}/system_bd.tcl (100%) rename {dma_sg_2 => testbenches/ip/dma_sg_2}/system_project.tcl (100%) rename {dma_sg_2 => testbenches/ip/dma_sg_2}/system_tb.sv (100%) rename {dma_sg_2 => testbenches/ip/dma_sg_2}/tests/test_program.sv (100%) rename {dma_sg_2 => testbenches/ip/dma_sg_2}/waves/cfg1.wcfg (100%) diff --git a/dma_sg_2/Makefile b/testbenches/ip/dma_sg_2/Makefile similarity index 100% rename from dma_sg_2/Makefile rename to testbenches/ip/dma_sg_2/Makefile diff --git a/dma_sg_2/README.md b/testbenches/ip/dma_sg_2/README.md similarity index 100% rename from dma_sg_2/README.md rename to testbenches/ip/dma_sg_2/README.md diff --git a/dma_sg_2/cfgs/cfg1.tcl b/testbenches/ip/dma_sg_2/cfgs/cfg1.tcl similarity index 100% rename from dma_sg_2/cfgs/cfg1.tcl rename to testbenches/ip/dma_sg_2/cfgs/cfg1.tcl diff --git a/dma_sg_2/environment.sv b/testbenches/ip/dma_sg_2/environment.sv similarity index 100% rename from dma_sg_2/environment.sv rename to testbenches/ip/dma_sg_2/environment.sv diff --git a/dma_sg_2/system_bd.tcl b/testbenches/ip/dma_sg_2/system_bd.tcl similarity index 100% rename from dma_sg_2/system_bd.tcl rename to testbenches/ip/dma_sg_2/system_bd.tcl diff --git a/dma_sg_2/system_project.tcl b/testbenches/ip/dma_sg_2/system_project.tcl similarity index 100% rename from dma_sg_2/system_project.tcl rename to testbenches/ip/dma_sg_2/system_project.tcl diff --git a/dma_sg_2/system_tb.sv b/testbenches/ip/dma_sg_2/system_tb.sv similarity index 100% rename from dma_sg_2/system_tb.sv rename to testbenches/ip/dma_sg_2/system_tb.sv diff --git a/dma_sg_2/tests/test_program.sv b/testbenches/ip/dma_sg_2/tests/test_program.sv similarity index 100% rename from dma_sg_2/tests/test_program.sv rename to testbenches/ip/dma_sg_2/tests/test_program.sv diff --git a/dma_sg_2/waves/cfg1.wcfg b/testbenches/ip/dma_sg_2/waves/cfg1.wcfg similarity index 100% rename from dma_sg_2/waves/cfg1.wcfg rename to testbenches/ip/dma_sg_2/waves/cfg1.wcfg From ceec1c6ec1512b01b210cfda48d29f4b0372457e Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Mon, 21 Oct 2024 12:24:10 +0100 Subject: [PATCH 5/5] dma_sg: Fixed paths Signed-off-by: Istvan-Zsolt Szekely --- testbenches/ip/dma_sg_2/Makefile | 38 +++++++++++----------- testbenches/ip/dma_sg_2/system_bd.tcl | 2 +- testbenches/ip/dma_sg_2/system_project.tcl | 36 ++++++++++---------- 3 files changed, 38 insertions(+), 38 deletions(-) diff --git a/testbenches/ip/dma_sg_2/Makefile b/testbenches/ip/dma_sg_2/Makefile index df753527..57450c35 100644 --- a/testbenches/ip/dma_sg_2/Makefile +++ b/testbenches/ip/dma_sg_2/Makefile @@ -5,29 +5,29 @@ #################################################################################### # All test-bench dependencies except test programs -SV_DEPS += ../common/sv/utils.svh -SV_DEPS += ../common/sv/logger_pkg.sv -SV_DEPS += ../common/sv/reg_accessor.sv -SV_DEPS += ../common/sv/m_axis_sequencer.sv -SV_DEPS += ../common/sv/s_axis_sequencer.sv -SV_DEPS += ../common/sv/m_axi_sequencer.sv -SV_DEPS += ../common/sv/s_axi_sequencer.sv -SV_DEPS += ../common/sv/test_harness_env.sv -SV_DEPS += ../common/sv/adi_peripheral_pkg.sv -SV_DEPS += ../common/sv/adi_regmap_pkg.sv -SV_DEPS += ../common/sv/mailbox.sv -SV_DEPS += ../common/sv/x_monitor.sv -SV_DEPS += ../common/sv/scoreboard.sv -SV_DEPS += ../common/sv/dmac_api.sv -SV_DEPS += ../common/sv/dma_trans.sv -SV_DEPS += ../common/sv/adi_regmap_dmac_pkg.sv +SV_DEPS += ../../../library/utilities/utils.svh +SV_DEPS += ../../../library/utilities/logger_pkg.sv +SV_DEPS += ../../../library/regmaps/reg_accessor.sv +SV_DEPS += ../../../library/vip/amd/m_axis_sequencer.sv +SV_DEPS += ../../../library/vip/amd/s_axis_sequencer.sv +SV_DEPS += ../../../library/vip/amd/m_axi_sequencer.sv +SV_DEPS += ../../../library/vip/amd/s_axi_sequencer.sv +SV_DEPS += ../../../library/utilities/test_harness_env.sv +SV_DEPS += ../../../library/regmaps/adi_peripheral_pkg.sv +SV_DEPS += ../../../library/regmaps/adi_regmap_pkg.sv +SV_DEPS += ../../../library/drivers/common/mailbox.sv +SV_DEPS += ../../../library/drivers/common/x_monitor.sv +SV_DEPS += ../../../library/drivers/common/scoreboard.sv +SV_DEPS += ../../../library/drivers/dmac/dmac_api.sv +SV_DEPS += ../../../library/drivers/dmac/dma_trans.sv +SV_DEPS += ../../../library/regmaps/adi_regmap_dmac_pkg.sv SV_DEPS += environment.sv SV_DEPS += system_tb.sv ENV_DEPS += system_project.tcl ENV_DEPS += system_bd.tcl -ENV_DEPS +=../scripts/adi_sim.tcl -ENV_DEPS +=../scripts/run_sim.tcl +ENV_DEPS += ../../../scripts/adi_sim.tcl +ENV_DEPS += ../../../scripts/run_sim.tcl LIB_DEPS := util_cdc LIB_DEPS += util_axis_fifo @@ -49,7 +49,7 @@ TESTS := $(foreach cfg, $(basename $(CFG_FILES)), $(cfg):$(TP)) #TESTS += cfg2_fsync:test_program #TESTS += cfg2_fsync:test_frame_delay -include ../scripts/project-sim.mk +include ../../../scripts/project-sim.mk # usage : # diff --git a/testbenches/ip/dma_sg_2/system_bd.tcl b/testbenches/ip/dma_sg_2/system_bd.tcl index 794aa07d..ffb741f5 100644 --- a/testbenches/ip/dma_sg_2/system_bd.tcl +++ b/testbenches/ip/dma_sg_2/system_bd.tcl @@ -35,7 +35,7 @@ global ad_hdl_dir -source ../../scripts/adi_env.tcl +source ../../../../scripts/adi_env.tcl global ad_project_params diff --git a/testbenches/ip/dma_sg_2/system_project.tcl b/testbenches/ip/dma_sg_2/system_project.tcl index c672a4b8..6ea76cfa 100644 --- a/testbenches/ip/dma_sg_2/system_project.tcl +++ b/testbenches/ip/dma_sg_2/system_project.tcl @@ -1,5 +1,5 @@ -source ../scripts/adi_sim.tcl -source ../../scripts/adi_env.tcl +source ../../../scripts/adi_sim.tcl +source ../../../../scripts/adi_env.tcl source $ad_hdl_dir/projects/scripts/adi_board.tcl if {$argc < 1} { @@ -20,22 +20,22 @@ adi_sim_project_xilinx $project_name "xcvu9p-flga2104-2L-e" # Add test files to the project adi_sim_project_files [list \ - "../common/sv/utils.svh" \ - "../common/sv/logger_pkg.sv" \ - "../common/sv/reg_accessor.sv" \ - "../common/sv/m_axis_sequencer.sv" \ - "../common/sv/s_axis_sequencer.sv" \ - "../common/sv/m_axi_sequencer.sv" \ - "../common/sv/s_axi_sequencer.sv" \ - "../common/sv/adi_peripheral_pkg.sv" \ - "../common/sv/adi_regmap_pkg.sv" \ - "../common/sv/test_harness_env.sv" \ - "../common/sv/mailbox.sv" \ - "../common/sv/x_monitor.sv" \ - "../common/sv/scoreboard.sv" \ - "../common/sv/dmac_api.sv" \ - "../common/sv/dma_trans.sv" \ - "../common/sv/adi_regmap_dmac_pkg.sv" \ + "../../../library/utilities/utils.svh" \ + "../../../library/utilities/logger_pkg.sv" \ + "../../../library/regmaps/reg_accessor.sv" \ + "../../../library/vip/amd/m_axis_sequencer.sv" \ + "../../../library/vip/amd/s_axis_sequencer.sv" \ + "../../../library/vip/amd/m_axi_sequencer.sv" \ + "../../../library/vip/amd/s_axi_sequencer.sv" \ + "../../../library/regmaps/adi_peripheral_pkg.sv" \ + "../../../library/regmaps/adi_regmap_pkg.sv" \ + "../../../library/utilities/test_harness_env.sv" \ + "../../../library/drivers/common/mailbox.sv" \ + "../../../library/drivers/common/x_monitor.sv" \ + "../../../library/drivers/common/scoreboard.sv" \ + "../../../library/drivers/dmac/dmac_api.sv" \ + "../../../library/drivers/dmac/dma_trans.sv" \ + "../../../library/regmaps/adi_regmap_dmac_pkg.sv" \ "environment.sv" \ "tests/test_program.sv" \ "system_tb.sv" \