From c6c4aa1000a13f409a44dc65e1d320b59e1d13f8 Mon Sep 17 00:00:00 2001 From: Fish Date: Tue, 29 Oct 2024 02:00:02 -0400 Subject: [PATCH] VEXIRSBConveter: Fix two places where regs do not have tags. (#253) --- ailment/converter_vex.py | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/ailment/converter_vex.py b/ailment/converter_vex.py index 599c58e..c8b9fac 100644 --- a/ailment/converter_vex.py +++ b/ailment/converter_vex.py @@ -762,6 +762,9 @@ def convert(irsb, manager): # pylint:disable=arguments-differ ret_reg_offset, manager.arch.bits, reg_name=manager.arch.translate_register_name(ret_reg_offset, size=manager.arch.bits), + ins_addr=manager.ins_addr, + vex_block_addr=manager.block_addr, + vex_stmt_idx=DEFAULT_STATEMENT, ) fp_ret_reg_offset = manager.arch.fp_ret_offset if fp_ret_reg_offset is not None and fp_ret_reg_offset != ret_expr: @@ -771,6 +774,9 @@ def convert(irsb, manager): # pylint:disable=arguments-differ fp_ret_reg_offset, manager.arch.bits, reg_name=manager.arch.translate_register_name(fp_ret_reg_offset, size=manager.arch.bits), + ins_addr=manager.ins_addr, + vex_block_addr=manager.block_addr, + vex_stmt_idx=DEFAULT_STATEMENT, ) else: fp_ret_expr = None