diff --git a/fuzzing/irsb_fuzzer.py b/fuzzing/irsb_fuzzer.py index 68ff76cd..6259ec04 100644 --- a/fuzzing/irsb_fuzzer.py +++ b/fuzzing/irsb_fuzzer.py @@ -26,7 +26,6 @@ import pyvex # Additional imports -import archinfo from enhanced_fdp import EnhancedFuzzedDataProvider register_error_msg = re.compile("Register .*? does not exist!") @@ -44,7 +43,22 @@ def nostdout(): # Save all available architectures off -available_archs = [tup[3]() for tup in archinfo.arch.arch_id_map if len(tup) >= 3] +available_archs = [ + pyvex.ARCH_X86, + pyvex.ARCH_AMD64, + pyvex.ARCH_ARM_LE, + pyvex.ARCH_ARM_BE, + pyvex.ARCH_ARM64_LE, + pyvex.ARCH_ARM64_BE, + pyvex.ARCH_PPC32, + pyvex.ARCH_PPC64_BE, + pyvex.ARCH_PPC64_LE, + pyvex.ARCH_S390X, + pyvex.ARCH_MIPS32_BE, + pyvex.ARCH_MIPS32_LE, + pyvex.ARCH_MIPS64_BE, + pyvex.ARCH_MIPS64_LE, +] class SupportedOptLevels(IntEnum): @@ -58,7 +72,7 @@ class SupportedOptLevels(IntEnum): StrictOpt = 2 -def consume_random_arch(fdp: atheris.FuzzedDataProvider) -> archinfo.Arch: +def consume_random_arch(fdp: atheris.FuzzedDataProvider) -> pyvex.arches.PyvexArch: return fdp.PickValueInList(available_archs) diff --git a/pyvex/__init__.py b/pyvex/__init__.py index f3d9030b..d287f7f4 100644 --- a/pyvex/__init__.py +++ b/pyvex/__init__.py @@ -5,6 +5,24 @@ __version__ = "9.2.80.dev0" from . import const, expr, stmt +from .arches import ( + ARCH_AMD64, + ARCH_ARM64_BE, + ARCH_ARM64_LE, + ARCH_ARM_BE, + ARCH_ARM_BE_LE, + ARCH_ARM_LE, + ARCH_MIPS32_BE, + ARCH_MIPS32_LE, + ARCH_MIPS64_BE, + ARCH_MIPS64_LE, + ARCH_PPC32, + ARCH_PPC64_BE, + ARCH_PPC64_LE, + ARCH_RISCV64_LE, + ARCH_S390X, + ARCH_X86, +) from .block import IRSB, IRTypeEnv from .const import get_type_size, get_type_spec_size, tag_to_const_class from .enums import ( @@ -54,4 +72,20 @@ "IRStmt", "IRExpr", "IRConst", + "ARCH_X86", + "ARCH_AMD64", + "ARCH_ARM_BE", + "ARCH_ARM_BE_LE", + "ARCH_ARM_LE", + "ARCH_ARM64_LE", + "ARCH_ARM64_BE", + "ARCH_PPC32", + "ARCH_PPC64_BE", + "ARCH_PPC64_LE", + "ARCH_S390X", + "ARCH_MIPS32_BE", + "ARCH_MIPS32_LE", + "ARCH_MIPS64_BE", + "ARCH_MIPS64_LE", + "ARCH_RISCV64_LE", ] diff --git a/pyvex/_register_info.py b/pyvex/_register_info.py new file mode 100644 index 00000000..8f1a237f --- /dev/null +++ b/pyvex/_register_info.py @@ -0,0 +1,1800 @@ +REGISTER_OFFSETS = { + ("x86", "eax"): 8, + ("x86", "ax"): 8, + ("x86", "al"): 8, + ("x86", "ah"): 9, + ("x86", "ecx"): 12, + ("x86", "cx"): 12, + ("x86", "cl"): 12, + ("x86", "ch"): 13, + ("x86", "edx"): 16, + ("x86", "dx"): 16, + ("x86", "dl"): 16, + ("x86", "dh"): 17, + ("x86", "ebx"): 20, + ("x86", "bx"): 20, + ("x86", "bl"): 20, + ("x86", "bh"): 21, + ("x86", "esp"): 24, + ("x86", "sp"): 24, + ("x86", "ebp"): 28, + ("x86", "bp"): 28, + ("x86", "esi"): 32, + ("x86", "si"): 32, + ("x86", "sil"): 32, + ("x86", "sih"): 33, + ("x86", "edi"): 36, + ("x86", "di"): 36, + ("x86", "dil"): 36, + ("x86", "dih"): 37, + ("x86", "cc_op"): 40, + ("x86", "cc_dep1"): 44, + ("x86", "cc_dep2"): 48, + ("x86", "cc_ndep"): 52, + ("x86", "d"): 56, + ("x86", "dflag"): 56, + ("x86", "id"): 60, + ("x86", "idflag"): 60, + ("x86", "ac"): 64, + ("x86", "acflag"): 64, + ("x86", "eip"): 68, + ("x86", "ip"): 68, + ("x86", "pc"): 68, + ("x86", "fpreg"): 72, + ("x86", "fpu_regs"): 72, + ("x86", "mm0"): 72, + ("x86", "mm1"): 80, + ("x86", "mm2"): 88, + ("x86", "mm3"): 96, + ("x86", "mm4"): 104, + ("x86", "mm5"): 112, + ("x86", "mm6"): 120, + ("x86", "mm7"): 128, + ("x86", "fptag"): 136, + ("x86", "fpu_tags"): 136, + ("x86", "fpround"): 144, + ("x86", "fc3210"): 148, + ("x86", "ftop"): 152, + ("x86", "sseround"): 156, + ("x86", "xmm0"): 160, + ("x86", "xmm1"): 176, + ("x86", "xmm2"): 192, + ("x86", "xmm3"): 208, + ("x86", "xmm4"): 224, + ("x86", "xmm5"): 240, + ("x86", "xmm6"): 256, + ("x86", "xmm7"): 272, + ("x86", "cs"): 288, + ("x86", "ds"): 290, + ("x86", "es"): 292, + ("x86", "fs"): 294, + ("x86", "gs"): 296, + ("x86", "ss"): 298, + ("x86", "ldt"): 304, + ("x86", "gdt"): 312, + ("x86", "emnote"): 320, + ("x86", "cmstart"): 324, + ("x86", "cmlen"): 328, + ("x86", "nraddr"): 332, + ("x86", "sc_class"): 336, + ("x86", "ip_at_syscall"): 340, + ("amd64", "rax"): 16, + ("amd64", "eax"): 16, + ("amd64", "ax"): 16, + ("amd64", "al"): 16, + ("amd64", "ah"): 17, + ("amd64", "rcx"): 24, + ("amd64", "ecx"): 24, + ("amd64", "cx"): 24, + ("amd64", "cl"): 24, + ("amd64", "ch"): 25, + ("amd64", "rdx"): 32, + ("amd64", "edx"): 32, + ("amd64", "dx"): 32, + ("amd64", "dl"): 32, + ("amd64", "dh"): 33, + ("amd64", "rbx"): 40, + ("amd64", "ebx"): 40, + ("amd64", "bx"): 40, + ("amd64", "bl"): 40, + ("amd64", "bh"): 41, + ("amd64", "rsp"): 48, + ("amd64", "sp"): 48, + ("amd64", "esp"): 48, + ("amd64", "rbp"): 56, + ("amd64", "bp"): 56, + ("amd64", "ebp"): 56, + ("amd64", "_bp"): 56, + ("amd64", "bpl"): 56, + ("amd64", "bph"): 57, + ("amd64", "rsi"): 64, + ("amd64", "esi"): 64, + ("amd64", "si"): 64, + ("amd64", "sil"): 64, + ("amd64", "sih"): 65, + ("amd64", "rdi"): 72, + ("amd64", "edi"): 72, + ("amd64", "di"): 72, + ("amd64", "dil"): 72, + ("amd64", "dih"): 73, + ("amd64", "r8"): 80, + ("amd64", "r8d"): 80, + ("amd64", "r8w"): 80, + ("amd64", "r8b"): 80, + ("amd64", "r9"): 88, + ("amd64", "r9d"): 88, + ("amd64", "r9w"): 88, + ("amd64", "r9b"): 88, + ("amd64", "r10"): 96, + ("amd64", "r10d"): 96, + ("amd64", "r10w"): 96, + ("amd64", "r10b"): 96, + ("amd64", "r11"): 104, + ("amd64", "r11d"): 104, + ("amd64", "r11w"): 104, + ("amd64", "r11b"): 104, + ("amd64", "r12"): 112, + ("amd64", "r12d"): 112, + ("amd64", "r12w"): 112, + ("amd64", "r12b"): 112, + ("amd64", "r13"): 120, + ("amd64", "r13d"): 120, + ("amd64", "r13w"): 120, + ("amd64", "r13b"): 120, + ("amd64", "r14"): 128, + ("amd64", "r14d"): 128, + ("amd64", "r14w"): 128, + ("amd64", "r14b"): 128, + ("amd64", "r15"): 136, + ("amd64", "r15d"): 136, + ("amd64", "r15w"): 136, + ("amd64", "r15b"): 136, + ("amd64", "cc_op"): 144, + ("amd64", "cc_dep1"): 152, + ("amd64", "cc_dep2"): 160, + ("amd64", "cc_ndep"): 168, + ("amd64", "d"): 176, + ("amd64", "dflag"): 176, + ("amd64", "rip"): 184, + ("amd64", "ip"): 184, + ("amd64", "pc"): 184, + ("amd64", "ac"): 192, + ("amd64", "acflag"): 192, + ("amd64", "id"): 200, + ("amd64", "idflag"): 200, + ("amd64", "fs"): 208, + ("amd64", "fs_const"): 208, + ("amd64", "sseround"): 216, + ("amd64", "cr0"): 768, + ("amd64", "cr2"): 784, + ("amd64", "cr3"): 792, + ("amd64", "cr4"): 800, + ("amd64", "cr8"): 832, + ("amd64", "ymm0"): 224, + ("amd64", "xmm0"): 224, + ("amd64", "xmm0lq"): 224, + ("amd64", "xmm0hq"): 232, + ("amd64", "ymm0hx"): 240, + ("amd64", "ymm1"): 256, + ("amd64", "xmm1"): 256, + ("amd64", "xmm1lq"): 256, + ("amd64", "xmm1hq"): 264, + ("amd64", "ymm1hx"): 272, + ("amd64", "ymm2"): 288, + ("amd64", "xmm2"): 288, + ("amd64", "xmm2lq"): 288, + ("amd64", "xmm2hq"): 296, + ("amd64", "ymm2hx"): 304, + ("amd64", "ymm3"): 320, + ("amd64", "xmm3"): 320, + ("amd64", "xmm3lq"): 320, + ("amd64", "xmm3hq"): 328, + ("amd64", "ymm3hx"): 336, + ("amd64", "ymm4"): 352, + ("amd64", "xmm4"): 352, + ("amd64", "xmm4lq"): 352, + ("amd64", "xmm4hq"): 360, + ("amd64", "ymm4hx"): 368, + ("amd64", "ymm5"): 384, + ("amd64", "xmm5"): 384, + ("amd64", "xmm5lq"): 384, + ("amd64", "xmm5hq"): 392, + ("amd64", "ymm5hx"): 400, + ("amd64", "ymm6"): 416, + ("amd64", "xmm6"): 416, + ("amd64", "xmm6lq"): 416, + ("amd64", "xmm6hq"): 424, + ("amd64", "ymm6hx"): 432, + ("amd64", "ymm7"): 448, + ("amd64", "xmm7"): 448, + ("amd64", "xmm7lq"): 448, + ("amd64", "xmm7hq"): 456, + ("amd64", "ymm7hx"): 464, + ("amd64", "ymm8"): 480, + ("amd64", "xmm8"): 480, + ("amd64", "xmm8lq"): 480, + ("amd64", "xmm8hq"): 488, + ("amd64", "ymm8hx"): 496, + ("amd64", "ymm9"): 512, + ("amd64", "xmm9"): 512, + ("amd64", "xmm9lq"): 512, + ("amd64", "xmm9hq"): 520, + ("amd64", "ymm9hx"): 528, + ("amd64", "ymm10"): 544, + ("amd64", "xmm10"): 544, + ("amd64", "xmm10lq"): 544, + ("amd64", "xmm10hq"): 552, + ("amd64", "ymm10hx"): 560, + ("amd64", "ymm11"): 576, + ("amd64", "xmm11"): 576, + ("amd64", "xmm11lq"): 576, + ("amd64", "xmm11hq"): 584, + ("amd64", "ymm11hx"): 592, + ("amd64", "ymm12"): 608, + ("amd64", "xmm12"): 608, + ("amd64", "xmm12lq"): 608, + ("amd64", "xmm12hq"): 616, + ("amd64", "ymm12hx"): 624, + ("amd64", "ymm13"): 640, + ("amd64", "xmm13"): 640, + ("amd64", "xmm13lq"): 640, + ("amd64", "xmm13hq"): 648, + ("amd64", "ymm13hx"): 656, + ("amd64", "ymm14"): 672, + ("amd64", "xmm14"): 672, + ("amd64", "xmm14lq"): 672, + ("amd64", "xmm14hq"): 680, + ("amd64", "ymm14hx"): 688, + ("amd64", "ymm15"): 704, + ("amd64", "xmm15"): 704, + ("amd64", "xmm15lq"): 704, + ("amd64", "xmm15hq"): 712, + ("amd64", "ymm15hx"): 720, + ("amd64", "ftop"): 896, + ("amd64", "fpreg"): 904, + ("amd64", "fpu_regs"): 904, + ("amd64", "mm0"): 904, + ("amd64", "mm1"): 912, + ("amd64", "mm2"): 920, + ("amd64", "mm3"): 928, + ("amd64", "mm4"): 936, + ("amd64", "mm5"): 944, + ("amd64", "mm6"): 952, + ("amd64", "mm7"): 960, + ("amd64", "fptag"): 968, + ("amd64", "fpu_tags"): 968, + ("amd64", "fpround"): 976, + ("amd64", "fc3210"): 984, + ("amd64", "emnote"): 992, + ("amd64", "cmstart"): 1000, + ("amd64", "cmlen"): 1008, + ("amd64", "nraddr"): 1016, + ("amd64", "gs"): 1032, + ("amd64", "gs_const"): 1032, + ("amd64", "ip_at_syscall"): 1040, + ("amd64", "cs_seg"): 1048, + ("amd64", "ds_seg"): 1050, + ("amd64", "es_seg"): 1052, + ("amd64", "fs_seg"): 1054, + ("amd64", "gs_seg"): 1056, + ("amd64", "ss_seg"): 1058, + ("arm", "r0"): 8, + ("arm", "a1"): 8, + ("arm", "r1"): 12, + ("arm", "a2"): 12, + ("arm", "r2"): 16, + ("arm", "a3"): 16, + ("arm", "r3"): 20, + ("arm", "a4"): 20, + ("arm", "r4"): 24, + ("arm", "v1"): 24, + ("arm", "r5"): 28, + ("arm", "v2"): 28, + ("arm", "r6"): 32, + ("arm", "v3"): 32, + ("arm", "r7"): 36, + ("arm", "v4"): 36, + ("arm", "r8"): 40, + ("arm", "v5"): 40, + ("arm", "r9"): 44, + ("arm", "v6"): 44, + ("arm", "sb"): 44, + ("arm", "r10"): 48, + ("arm", "v7"): 48, + ("arm", "sl"): 48, + ("arm", "r11"): 52, + ("arm", "v8"): 52, + ("arm", "fp"): 52, + ("arm", "bp"): 52, + ("arm", "r12"): 56, + ("arm", "sp"): 60, + ("arm", "r13"): 60, + ("arm", "lr"): 64, + ("arm", "r14"): 64, + ("arm", "pc"): 68, + ("arm", "r15"): 68, + ("arm", "ip"): 68, + ("arm", "cc_op"): 72, + ("arm", "cc_dep1"): 76, + ("arm", "cc_dep2"): 80, + ("arm", "cc_ndep"): 84, + ("arm", "qflag32"): 88, + ("arm", "geflag0"): 92, + ("arm", "geflag1"): 96, + ("arm", "geflag2"): 100, + ("arm", "geflag3"): 104, + ("arm", "emnote"): 108, + ("arm", "cmstart"): 112, + ("arm", "cmlen"): 116, + ("arm", "nraddr"): 120, + ("arm", "ip_at_syscall"): 124, + ("arm", "d0"): 128, + ("arm", "s0"): 128, + ("arm", "s1"): 132, + ("arm", "d1"): 136, + ("arm", "s2"): 136, + ("arm", "s3"): 140, + ("arm", "d2"): 144, + ("arm", "s4"): 144, + ("arm", "s5"): 148, + ("arm", "d3"): 152, + ("arm", "s6"): 152, + ("arm", "s7"): 156, + ("arm", "d4"): 160, + ("arm", "s8"): 160, + ("arm", "s9"): 164, + ("arm", "d5"): 168, + ("arm", "s10"): 168, + ("arm", "s11"): 172, + ("arm", "d6"): 176, + ("arm", "s12"): 176, + ("arm", "s13"): 180, + ("arm", "d7"): 184, + ("arm", "s14"): 184, + ("arm", "s15"): 188, + ("arm", "d8"): 192, + ("arm", "s16"): 192, + ("arm", "s17"): 196, + ("arm", "d9"): 200, + ("arm", "s18"): 200, + ("arm", "s19"): 204, + ("arm", "d10"): 208, + ("arm", "s20"): 208, + ("arm", "s21"): 212, + ("arm", "d11"): 216, + ("arm", "s22"): 216, + ("arm", "s23"): 220, + ("arm", "d12"): 224, + ("arm", "s24"): 224, + ("arm", "s25"): 228, + ("arm", "d13"): 232, + ("arm", "s26"): 232, + ("arm", "s27"): 236, + ("arm", "d14"): 240, + ("arm", "s28"): 240, + ("arm", "s29"): 244, + ("arm", "d15"): 248, + ("arm", "s30"): 248, + ("arm", "s31"): 252, + ("arm", "d16"): 256, + ("arm", "d17"): 264, + ("arm", "d18"): 272, + ("arm", "d19"): 280, + ("arm", "d20"): 288, + ("arm", "d21"): 296, + ("arm", "d22"): 304, + ("arm", "d23"): 312, + ("arm", "d24"): 320, + ("arm", "d25"): 328, + ("arm", "d26"): 336, + ("arm", "d27"): 344, + ("arm", "d28"): 352, + ("arm", "d29"): 360, + ("arm", "d30"): 368, + ("arm", "d31"): 376, + ("arm", "fpscr"): 384, + ("arm", "tpidruro"): 388, + ("arm", "itstate"): 392, + ("arm64", "x0"): 16, + ("arm64", "r0"): 16, + ("arm64", "w0"): 16, + ("arm64", "x1"): 24, + ("arm64", "r1"): 24, + ("arm64", "w1"): 24, + ("arm64", "x2"): 32, + ("arm64", "r2"): 32, + ("arm64", "w2"): 32, + ("arm64", "x3"): 40, + ("arm64", "r3"): 40, + ("arm64", "w3"): 40, + ("arm64", "x4"): 48, + ("arm64", "r4"): 48, + ("arm64", "w4"): 48, + ("arm64", "x5"): 56, + ("arm64", "r5"): 56, + ("arm64", "w5"): 56, + ("arm64", "x6"): 64, + ("arm64", "r6"): 64, + ("arm64", "w6"): 64, + ("arm64", "x7"): 72, + ("arm64", "r7"): 72, + ("arm64", "w7"): 72, + ("arm64", "x8"): 80, + ("arm64", "r8"): 80, + ("arm64", "w8"): 80, + ("arm64", "x9"): 88, + ("arm64", "r9"): 88, + ("arm64", "w9"): 88, + ("arm64", "x10"): 96, + ("arm64", "r10"): 96, + ("arm64", "w10"): 96, + ("arm64", "x11"): 104, + ("arm64", "r11"): 104, + ("arm64", "w11"): 104, + ("arm64", "x12"): 112, + ("arm64", "r12"): 112, + ("arm64", "w12"): 112, + ("arm64", "x13"): 120, + ("arm64", "r13"): 120, + ("arm64", "w13"): 120, + ("arm64", "x14"): 128, + ("arm64", "r14"): 128, + ("arm64", "w14"): 128, + ("arm64", "x15"): 136, + ("arm64", "r15"): 136, + ("arm64", "w15"): 136, + ("arm64", "x16"): 144, + ("arm64", "r16"): 144, + ("arm64", "ip0"): 144, + ("arm64", "w16"): 144, + ("arm64", "x17"): 152, + ("arm64", "r17"): 152, + ("arm64", "ip1"): 152, + ("arm64", "w17"): 152, + ("arm64", "x18"): 160, + ("arm64", "r18"): 160, + ("arm64", "w18"): 160, + ("arm64", "x19"): 168, + ("arm64", "r19"): 168, + ("arm64", "w19"): 168, + ("arm64", "x20"): 176, + ("arm64", "r20"): 176, + ("arm64", "w20"): 176, + ("arm64", "x21"): 184, + ("arm64", "r21"): 184, + ("arm64", "w21"): 184, + ("arm64", "x22"): 192, + ("arm64", "r22"): 192, + ("arm64", "w22"): 192, + ("arm64", "x23"): 200, + ("arm64", "r23"): 200, + ("arm64", "w23"): 200, + ("arm64", "x24"): 208, + ("arm64", "r24"): 208, + ("arm64", "w24"): 208, + ("arm64", "x25"): 216, + ("arm64", "r25"): 216, + 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320, + ("mips32", "f22"): 328, + ("mips32", "f22_lo"): 328, + ("mips32", "f23"): 336, + ("mips32", "f23_lo"): 336, + ("mips32", "f24"): 344, + ("mips32", "f24_lo"): 344, + ("mips32", "f25"): 352, + ("mips32", "f25_lo"): 352, + ("mips32", "f26"): 360, + ("mips32", "f26_lo"): 360, + ("mips32", "f27"): 368, + ("mips32", "f27_lo"): 368, + ("mips32", "f28"): 376, + ("mips32", "f28_lo"): 376, + ("mips32", "f29"): 384, + ("mips32", "f29_lo"): 384, + ("mips32", "f30"): 392, + ("mips32", "f30_lo"): 392, + ("mips32", "f31"): 400, + ("mips32", "f31_lo"): 400, + ("mips32", "fir"): 408, + ("mips32", "fccr"): 412, + ("mips32", "fexr"): 416, + ("mips32", "fenr"): 420, + ("mips32", "fcsr"): 424, + ("mips32", "ulr"): 428, + ("mips32", "emnote"): 432, + ("mips32", "cmstart"): 436, + ("mips32", "cmlen"): 440, + ("mips32", "nraddr"): 444, + ("mips32", "cond"): 448, + ("mips32", "dspcontrol"): 452, + ("mips32", "ac0"): 456, + ("mips32", "ac1"): 464, + ("mips32", "ac2"): 472, + ("mips32", "ac3"): 480, + ("mips32", "cp0_status"): 488, + ("mips32", "ip_at_syscall"): 492, + ("mips64", "zero"): 16, + ("mips64", "r0"): 16, + ("mips64", "at"): 24, + ("mips64", "r1"): 24, + ("mips64", "v0"): 32, + ("mips64", "r2"): 32, + ("mips64", "v1"): 40, + ("mips64", "r3"): 40, + ("mips64", "a0"): 48, + ("mips64", "r4"): 48, + ("mips64", "a1"): 56, + ("mips64", "r5"): 56, + ("mips64", "a2"): 64, + ("mips64", "r6"): 64, + ("mips64", "a3"): 72, + ("mips64", "r7"): 72, + ("mips64", "t0"): 80, + ("mips64", "r8"): 80, + ("mips64", "a4"): 80, + ("mips64", "t1"): 88, + ("mips64", "r9"): 88, + ("mips64", "a5"): 88, + ("mips64", "t2"): 96, + ("mips64", "r10"): 96, + ("mips64", "a6"): 96, + ("mips64", "t3"): 104, + ("mips64", "r11"): 104, + ("mips64", "a7"): 104, + ("mips64", "t4"): 112, + ("mips64", "r12"): 112, + ("mips64", "t5"): 120, + ("mips64", "r13"): 120, + ("mips64", "t6"): 128, + ("mips64", "r14"): 128, + ("mips64", "t7"): 136, + ("mips64", "r15"): 136, + ("mips64", "s0"): 144, + ("mips64", "r16"): 144, + ("mips64", "s1"): 152, + ("mips64", "r17"): 152, + ("mips64", "s2"): 160, + ("mips64", "r18"): 160, + ("mips64", "s3"): 168, + ("mips64", "r19"): 168, + ("mips64", "s4"): 176, + ("mips64", "r20"): 176, + ("mips64", "s5"): 184, + ("mips64", "r21"): 184, + ("mips64", "s6"): 192, + ("mips64", "r22"): 192, + ("mips64", "s7"): 200, + ("mips64", "r23"): 200, + ("mips64", "t8"): 208, + ("mips64", "r24"): 208, + ("mips64", "t9"): 216, + ("mips64", "r25"): 216, + ("mips64", "k0"): 224, + ("mips64", "r26"): 224, + ("mips64", "k1"): 232, + ("mips64", "r27"): 232, + ("mips64", "gp"): 240, + ("mips64", "r28"): 240, + ("mips64", "sp"): 248, + ("mips64", "r29"): 248, + ("mips64", "s8"): 256, + ("mips64", "r30"): 256, + ("mips64", "fp"): 256, + ("mips64", "bp"): 256, + ("mips64", "ra"): 264, + ("mips64", "r31"): 264, + ("mips64", "lr"): 264, + ("mips64", "pc"): 272, + ("mips64", "ip"): 272, + ("mips64", "hi"): 280, + ("mips64", "lo"): 288, + ("mips64", "f0"): 296, + ("mips64", "f0_lo"): 296, + ("mips64", "f1"): 304, + ("mips64", "f1_lo"): 304, + ("mips64", "f2"): 312, + ("mips64", "f2_lo"): 312, + ("mips64", "f3"): 320, + ("mips64", "f3_lo"): 320, + ("mips64", "f4"): 328, + ("mips64", "f4_lo"): 328, + ("mips64", "f5"): 336, + ("mips64", "f5_lo"): 336, + ("mips64", "f6"): 344, + ("mips64", "f6_lo"): 344, + ("mips64", "f7"): 352, + ("mips64", "f7_lo"): 352, + ("mips64", "f8"): 360, + ("mips64", "f8_lo"): 360, + ("mips64", "f9"): 368, + ("mips64", "f9_lo"): 368, + ("mips64", "f10"): 376, + ("mips64", "f10_lo"): 376, + ("mips64", "f11"): 384, + ("mips64", "f11_lo"): 384, + ("mips64", "f12"): 392, + ("mips64", "f12_lo"): 392, + ("mips64", "f13"): 400, + ("mips64", "f13_lo"): 400, + ("mips64", "f14"): 408, + ("mips64", "f14_lo"): 408, + ("mips64", "f15"): 416, + ("mips64", "f15_lo"): 416, + ("mips64", "f16"): 424, + ("mips64", "f16_lo"): 424, + ("mips64", "f17"): 432, + ("mips64", "f17_lo"): 432, + ("mips64", "f18"): 440, + ("mips64", "f18_lo"): 440, + ("mips64", "f19"): 448, + ("mips64", "f19_lo"): 448, + ("mips64", "f20"): 456, + ("mips64", "f20_lo"): 456, + ("mips64", "f21"): 464, + ("mips64", "f21_lo"): 464, + ("mips64", "f22"): 472, + ("mips64", "f22_lo"): 472, + ("mips64", "f23"): 480, + ("mips64", "f23_lo"): 480, + ("mips64", "f24"): 488, + ("mips64", "f24_lo"): 488, + ("mips64", "f25"): 496, + ("mips64", "f25_lo"): 496, + ("mips64", "f26"): 504, + ("mips64", "f26_lo"): 504, + ("mips64", "f27"): 512, + ("mips64", "f27_lo"): 512, + ("mips64", "f28"): 520, + ("mips64", "f28_lo"): 520, + ("mips64", "f29"): 528, + ("mips64", "f29_lo"): 528, + ("mips64", "f30"): 536, + ("mips64", "f30_lo"): 536, + ("mips64", "f31"): 544, + ("mips64", "f31_lo"): 544, + ("mips64", "fir"): 552, + ("mips64", "fccr"): 556, + ("mips64", "fexr"): 560, + ("mips64", "fenr"): 564, + ("mips64", "fcsr"): 568, + ("mips64", "cp0_status"): 572, + ("mips64", "ulr"): 576, + ("mips64", "emnote"): 584, + ("mips64", "cond"): 588, + ("mips64", "cmstart"): 592, + ("mips64", "cmlen"): 600, + ("mips64", "nraddr"): 608, + ("mips64", "ip_at_syscall"): 616, + ("riscv64", "x0"): 16, + ("riscv64", "zero"): 16, + ("riscv64", "x1"): 24, + ("riscv64", "ra"): 24, + ("riscv64", "lr"): 24, + ("riscv64", "x2"): 32, + ("riscv64", "sp"): 32, + ("riscv64", "x3"): 40, + ("riscv64", "gp"): 40, + ("riscv64", "x4"): 48, + ("riscv64", "tp"): 48, + ("riscv64", "x5"): 56, + ("riscv64", "t0"): 56, + ("riscv64", "x6"): 64, + ("riscv64", "t1"): 64, + ("riscv64", "x7"): 72, + ("riscv64", "t2"): 72, + ("riscv64", "x9"): 88, + ("riscv64", "s1"): 88, + ("riscv64", "x10"): 96, + ("riscv64", "a0"): 96, + ("riscv64", "x11"): 104, + ("riscv64", "a1"): 104, + ("riscv64", "x12"): 112, + ("riscv64", "a2"): 112, + ("riscv64", "x13"): 120, + ("riscv64", "a3"): 120, + ("riscv64", "x14"): 128, + ("riscv64", "a4"): 128, + ("riscv64", "x15"): 136, + ("riscv64", "a5"): 136, + ("riscv64", "x16"): 144, + ("riscv64", "a6"): 144, + ("riscv64", "x17"): 152, + ("riscv64", "a7"): 152, + ("riscv64", "x18"): 160, + ("riscv64", "s2"): 160, + ("riscv64", "x19"): 168, + ("riscv64", "s3"): 168, + ("riscv64", "x20"): 176, + ("riscv64", "s4"): 176, + ("riscv64", "x21"): 184, + ("riscv64", "s5"): 184, + ("riscv64", "x22"): 192, + ("riscv64", "s6"): 192, + ("riscv64", "x23"): 200, + ("riscv64", "s7"): 200, + ("riscv64", "x24"): 208, + ("riscv64", "s8"): 208, + ("riscv64", "x25"): 216, + ("riscv64", "s9"): 216, + ("riscv64", "x26"): 224, + ("riscv64", "s10"): 224, + ("riscv64", "x27"): 232, + ("riscv64", "s11"): 232, + ("riscv64", "x28"): 240, + ("riscv64", "t3"): 240, + ("riscv64", "x29"): 248, + ("riscv64", "t4"): 248, + ("riscv64", "x30"): 256, + ("riscv64", "t5"): 256, + ("riscv64", "x31"): 264, + ("riscv64", "t6"): 264, + ("riscv64", "pc"): 272, + ("riscv64", "ip"): 272, + ("riscv64", "f0"): 280, + ("riscv64", "ft0"): 280, + ("riscv64", "f1"): 288, + ("riscv64", "ft1"): 288, + ("riscv64", "f2"): 296, + ("riscv64", "ft2"): 296, + ("riscv64", "f3"): 304, + ("riscv64", "ft3"): 304, + ("riscv64", "f4"): 312, + ("riscv64", "ft4"): 312, + ("riscv64", "f5"): 320, + ("riscv64", "ft5"): 320, + ("riscv64", "f6"): 328, + ("riscv64", "ft6"): 328, + ("riscv64", "f7"): 336, + ("riscv64", "ft7"): 336, + ("riscv64", "f9"): 352, + ("riscv64", "fs1"): 352, + ("riscv64", "f10"): 360, + ("riscv64", "fa0"): 360, + ("riscv64", "f11"): 368, + ("riscv64", "fa1"): 368, + ("riscv64", "f12"): 376, + ("riscv64", "fa2"): 376, + ("riscv64", "f13"): 384, + ("riscv64", "fa3"): 384, + ("riscv64", "f14"): 392, + ("riscv64", "fa4"): 392, + ("riscv64", "f15"): 400, + ("riscv64", "fa5"): 400, + ("riscv64", "f16"): 408, + ("riscv64", "fa6"): 408, + ("riscv64", "f17"): 416, + ("riscv64", "fa7"): 416, + ("riscv64", "f18"): 424, + ("riscv64", "fs2"): 424, + ("riscv64", "f19"): 432, + ("riscv64", "fs3"): 432, + ("riscv64", "f20"): 440, + ("riscv64", "fs4"): 440, + ("riscv64", "f21"): 448, + ("riscv64", "fs5"): 448, + ("riscv64", "f22"): 456, + ("riscv64", "fs6"): 456, + ("riscv64", "f23"): 464, + ("riscv64", "fs7"): 464, + ("riscv64", "f24"): 472, + ("riscv64", "fs8"): 472, + ("riscv64", "f25"): 480, + ("riscv64", "fs9"): 480, + ("riscv64", "f26"): 488, + ("riscv64", "fs10"): 488, + ("riscv64", "f27"): 496, + ("riscv64", "fs11"): 496, + ("riscv64", "f28"): 504, + ("riscv64", "ft8"): 504, + ("riscv64", "f29"): 512, + ("riscv64", "ft9"): 512, + ("riscv64", "f30"): 520, + ("riscv64", "ft10"): 520, + ("riscv64", "f31"): 528, + ("riscv64", "ft11"): 528, +} diff --git a/pyvex/arches.py b/pyvex/arches.py new file mode 100644 index 00000000..9ac8b466 --- /dev/null +++ b/pyvex/arches.py @@ -0,0 +1,96 @@ +from typing import Dict, List, Tuple + +from ._register_info import REGISTER_OFFSETS +from .enums import default_vex_archinfo, vex_endness_from_string +from .types import Register +from .vex_ffi import guest_offsets + + +class PyvexArch: + """ + An architecture definition for use with pyvex - usable version. + """ + + def __init__(self, name: str, bits: int, memory_endness: str, instruction_endness: str = "Iend_BE"): + self.name = name + self.bits = bits + self.memory_endness = memory_endness + self.instruction_endness = instruction_endness + self.byte_width = 8 + self.register_list: List[Register] = [] + self.registers: Dict[str, Tuple[int, int]] = {} + self.vex_arch = { + "X86": "VexArchX86", + "AMD64": "VexArchAMD64", + "ARM": "VexArchARM", + "ARM64": "VexArchARM64", + "PPC32": "VexArchPPC32", + "PPC64": "VexArchPPC64", + "S390X": "VexArchS390X", + "MIPS32": "VexArchMIPS32", + "MIPS64": "VexArchMIPS64", + "RISCV64": "VexArchRISCV64", + }[name] + self.ip_offset = guest_offsets[ + ( + self.vex_name_small, + { + "X86": "eip", + "AMD64": "rip", + "ARM": "r15t", + "ARM64": "pc", + "PPC32": "cia", + "PPC64": "cia", + "S390X": "ia", + "MIPS32": "pc", + "MIPS64": "pc", + "RISCV64": "pc", + }[name], + ) + ] + self.vex_archinfo = default_vex_archinfo() + if memory_endness == "Iend_BE": + self.vex_archinfo["endness"] = vex_endness_from_string("VexEndnessBE") + + def __repr__(self): + return f"" + + @property + def vex_name_small(self): + return self.vex_arch[7:].lower() + + def translate_register_name(self, offset, size=None): # pylint: disable=unused-argument + for (arch, reg), offset2 in guest_offsets.items(): + if arch == self.vex_name_small and offset2 == offset: + return reg + for (arch, reg), offset2 in REGISTER_OFFSETS.items(): + if arch == self.vex_name_small and offset2 == offset: + return reg + return str(offset) + + def get_register_offset(self, name: str) -> int: + arch_reg_tuple = (self.vex_name_small, name) + if arch_reg_tuple in guest_offsets: + return guest_offsets[arch_reg_tuple] + elif arch_reg_tuple in REGISTER_OFFSETS: + return REGISTER_OFFSETS[arch_reg_tuple] + else: + raise KeyError(f"Unknown register {name} for architecture {self.name}") + + +ARCH_X86 = PyvexArch("X86", 32, "Iend_LE") +ARCH_AMD64 = PyvexArch("AMD64", 64, "Iend_LE") +ARCH_ARM_LE = PyvexArch("ARM", 32, "Iend_LE", instruction_endness="Iend_LE") +ARCH_ARM_BE_LE = PyvexArch("ARM", 32, "Iend_BE", instruction_endness="Iend_LE") +ARCH_ARM_BE = PyvexArch("ARM", 32, "Iend_LE") +ARCH_ARM64_LE = PyvexArch("ARM64", 64, "Iend_LE", instruction_endness="Iend_LE") +ARCH_ARM64_BE = PyvexArch("ARM64", 64, "Iend_BE") +ARCH_PPC32 = PyvexArch("PPC32", 32, "Iend_BE") +ARCH_PPC64_BE = PyvexArch("PPC64", 64, "Iend_BE") +ARCH_PPC64_LE = PyvexArch("PPC64", 64, "Iend_LE") +ARCH_S390X = PyvexArch("S390X", 64, "Iend_BE") +ARCH_MIPS32_BE = PyvexArch("MIPS32", 32, "Iend_BE") +ARCH_MIPS32_LE = PyvexArch("MIPS32", 32, "Iend_LE") +ARCH_MIPS64_BE = PyvexArch("MIPS64", 64, "Iend_BE") +ARCH_MIPS64_LE = PyvexArch("MIPS64", 64, "Iend_LE") +ARCH_RISCV64_LE = PyvexArch("RISCV64", 64, "Iend_LE", instruction_endness="Iend_LE") diff --git a/pyvex/block.py b/pyvex/block.py index 3029feeb..c9a87024 100644 --- a/pyvex/block.py +++ b/pyvex/block.py @@ -1,7 +1,7 @@ import copy import itertools import logging -from typing import List, Optional +from typing import List, Optional, Tuple from . import expr, stmt from .const import get_type_size @@ -10,7 +10,20 @@ from .errors import SkipStatementsError from .expr import RdTmp from .native import pvc -from .stmt import CAS, LLSC, Dirty, Exit, IMark, IRExpr, IRStmt, LoadG, WrTmp, get_enum_from_int, get_int_from_enum +from .stmt import ( + CAS, + LLSC, + Dirty, + Exit, + IMark, + IRExpr, + IRStmt, + LoadG, + WrTmp, + get_enum_from_int, + get_int_from_enum, +) +from .types import Arch log = logging.getLogger("pyvex.block") @@ -23,8 +36,7 @@ class IRSB(VEXObject): IRSB stands for *Intermediate Representation Super-Block*. An IRSB in VEX is a single-entry, multiple-exit code block. - :ivar arch: The architecture this block is lifted under - :vartype arch: :class:`archinfo.Arch` + :ivar arch: The architecture this block is lifted under. Must duck-type as :class:`archinfo.arch.Arch` :ivar statements: The statements in this block :vartype statements: list of :class:`IRStmt` :ivar next: The expression for the default exit target of this block @@ -61,7 +73,7 @@ def __init__( self, data, mem_addr, - arch, + arch: Arch, max_inst=None, max_bytes=None, bytes_offset=0, @@ -80,7 +92,6 @@ def __init__( :type data: str or bytes or cffi.FFI.CData or None :param int mem_addr: The address to lift the data at. :param arch: The architecture to lift the data as. - :type arch: :class:`archinfo.Arch` :param max_inst: The maximum number of instructions to lift. (See note below) :param max_bytes: The maximum number of bytes to use. :param num_inst: Replaces max_inst if max_inst is None. If set to None as well, no instruction limit @@ -112,19 +123,19 @@ def __init__( max_bytes = num_bytes VEXObject.__init__(self) self.addr = mem_addr - self.arch = arch + self.arch: Arch = arch self.statements: List[IRStmt] = [] self.next: Optional[IRExpr] = None - self._tyenv = None + self._tyenv: Optional["IRTypeEnv"] = None self.jumpkind: Optional[str] = None - self._direct_next = None - self._size = None - self._instructions = None - self._exit_statements = None + self._direct_next: Optional[bool] = None + self._size: Optional[int] = None + self._instructions: Optional[int] = None + self._exit_statements: Optional[Tuple[Tuple[int, int, IRStmt], ...]] = None self.default_exit_target = None self.data_refs = () - self._instruction_addresses = () + self._instruction_addresses: Tuple[int, ...] = () if data is not None: # This is the slower path (because we need to call _from_py() to copy the content in the returned IRSB to @@ -155,7 +166,7 @@ def empty_block(arch, addr, statements=None, nxt=None, tyenv=None, jumpkind=None return block @property - def tyenv(self): + def tyenv(self) -> "IRTypeEnv": if self._tyenv is None: self._tyenv = IRTypeEnv(self.arch) return self._tyenv @@ -165,34 +176,35 @@ def tyenv(self, v): self._tyenv = v @property - def has_statements(self): - return self.statements is not None and self.statements + def has_statements(self) -> bool: + return self.statements is not None and bool(self.statements) @property - def exit_statements(self): + def exit_statements(self) -> Tuple[Tuple[int, int, IRStmt], ...]: if self._exit_statements is not None: return self._exit_statements # Delayed process if not self.has_statements: - return [] + return () - self._exit_statements = [] + exit_statements = [] ins_addr = None for idx, stmt_ in enumerate(self.statements): if type(stmt_) is IMark: ins_addr = stmt_.addr + stmt_.delta elif type(stmt_) is Exit: - self._exit_statements.append((ins_addr, idx, stmt_)) + assert ins_addr is not None + exit_statements.append((ins_addr, idx, stmt_)) - self._exit_statements = tuple(self._exit_statements) + self._exit_statements = tuple(exit_statements) return self._exit_statements - def copy(self): + def copy(self) -> "IRSB": return copy.deepcopy(self) - def extend(self, extendwith): + def extend(self, extendwith) -> None: """ Appends an irsb to the current irsb. The irsb that is appended is invalidated. The appended irsb's jumpkind and default exit are used. @@ -268,10 +280,10 @@ def convert_expr(expr_): # TODO: Change exit_statements, data_references, etc. - def invalidate_direct_next(self): + def invalidate_direct_next(self) -> None: self._direct_next = None - def pp(self): + def pp(self) -> None: """ Pretty-print the IRSB to stdout. """ @@ -296,7 +308,7 @@ def __eq__(self, other): def __hash__(self): return hash((IRSB, self.addr, self.arch.name, tuple(self.statements), self.next, self.jumpkind)) - def typecheck(self): + def typecheck(self) -> bool: try: # existence assertions assert self.next is not None, "Missing next expression" @@ -338,13 +350,13 @@ def typecheck(self): # @staticmethod - def from_c(c_irsb, mem_addr, arch): + def from_c(c_irsb, mem_addr, arch) -> "IRSB": irsb = IRSB(None, mem_addr, arch) irsb._from_c(c_irsb) return irsb @staticmethod - def from_py(tyenv, stmts, next_expr, jumpkind, mem_addr, arch): + def from_py(tyenv, stmts, next_expr, jumpkind, mem_addr, arch) -> "IRSB": irsb = IRSB(None, mem_addr, arch) irsb.tyenv = tyenv @@ -360,13 +372,13 @@ def from_py(tyenv, stmts, next_expr, jumpkind, mem_addr, arch): # @property - def stmts_used(self): + def stmts_used(self) -> int: if self.statements is None: return 0 return len(self.statements) @property - def offsIP(self): + def offsIP(self) -> int: return self.arch.ip_offset @property @@ -397,15 +409,17 @@ def instructions(self): return self._instructions @property - def instruction_addresses(self): + def instruction_addresses(self) -> Tuple[int, ...]: """ Addresses of instructions in this block. """ if self._instruction_addresses is None: if self.statements is None: - self._instruction_addresses = [] + self._instruction_addresses = () else: - self._instruction_addresses = [(s.addr + s.delta) for s in self.statements if type(s) is stmt.IMark] + self._instruction_addresses = tuple( + (s.addr + s.delta) for s in self.statements if type(s) is stmt.IMark + ) return self._instruction_addresses @property @@ -481,11 +495,9 @@ def constant_jump_targets_and_jumpkinds(self): # private methods # - def _pp_str(self): + def _pp_str(self) -> str: """ Return the pretty-printed IRSB. - - :rtype: str """ sa = [] sa.append("IRSB {") @@ -495,17 +507,17 @@ def _pp_str(self): if self.statements is not None: for i, s in enumerate(self.statements): if isinstance(s, stmt.Put): - stmt_str = s.__str__( + stmt_str = s._pp_str( reg_name=self.arch.translate_register_name(s.offset, s.data.result_size(self.tyenv) // 8) ) elif isinstance(s, stmt.WrTmp) and isinstance(s.data, expr.Get): - stmt_str = s.__str__( + stmt_str = s._pp_str( reg_name=self.arch.translate_register_name(s.data.offset, s.data.result_size(self.tyenv) // 8) ) elif isinstance(s, stmt.Exit): - stmt_str = s.__str__(reg_name=self.arch.translate_register_name(s.offsIP, self.arch.bits // 8)) + stmt_str = s._pp_str(reg_name=self.arch.translate_register_name(s.offsIP, self.arch.bits // 8)) else: - stmt_str = s.__str__() + stmt_str = s._pp_str() sa.append(" %02d | %s" % (i, stmt_str)) else: sa.append(" Statements are omitted.") @@ -543,7 +555,7 @@ def _from_c(self, lift_r, skip_stmts=False): self._instruction_addresses = tuple(itertools.islice(lift_r.inst_addrs, lift_r.insts)) # Conditional exits - self._exit_statements = [] + exit_statements = [] if skip_stmts: if lift_r.exit_count > self.MAX_EXITS: # There are more exits than the default size of the exits array. We will need all statements @@ -551,9 +563,9 @@ def _from_c(self, lift_r, skip_stmts=False): for i in range(lift_r.exit_count): ex = lift_r.exits[i] exit_stmt = stmt.IRStmt._from_c(ex.stmt) - self._exit_statements.append((ex.ins_addr, ex.stmt_idx, exit_stmt)) + exit_statements.append((ex.ins_addr, ex.stmt_idx, exit_stmt)) - self._exit_statements = tuple(self._exit_statements) + self._exit_statements = tuple(exit_statements) else: self._exit_statements = None # It will be generated when self.exit_statements is called # The default exit diff --git a/pyvex/const.py b/pyvex/const.py index ede4c5d4..ef665f77 100644 --- a/pyvex/const.py +++ b/pyvex/const.py @@ -10,10 +10,11 @@ class IRConst(VEXObject): __slots__ = ["_value"] - type: Optional[str] = None - size = None - tag: Optional[str] = None + type: str + size: Optional[int] = None + tag: str c_constructor = None + _value: int def pp(self): print(self.__str__()) diff --git a/pyvex/enums.py b/pyvex/enums.py index d56230c6..e669b8fb 100644 --- a/pyvex/enums.py +++ b/pyvex/enums.py @@ -1,4 +1,4 @@ -from typing import List +from typing import Any, Dict, List from .native import ffi, pvc from .utils import stable_hash @@ -22,9 +22,9 @@ def __eq__(self, other): def __hash__(self): values = [getattr(self, slot) for slot in self.__slots__] - for i in range(len(values)): - if isinstance(values[i], list): - values[i] = tuple(values[i]) + for i, lst_val in enumerate(values): + if isinstance(lst_val, list): + values[i] = tuple(lst_val) return stable_hash(tuple([type(self)] + values)) @@ -55,7 +55,7 @@ def _from_c(c_callee): @staticmethod def _to_c(callee): # pylint: disable=unused-argument - raise Exception( + raise TypeError( "This doesn't work! Please invent a way to get the correct address for the named function from pyvex_c." ) # c_callee = pvc.mkIRCallee(callee.regparms, @@ -95,9 +95,9 @@ def _to_c(arr): return pvc.mkIRRegArray(arr.base, get_int_from_enum(arr.elemTy), arr.nElems) -ints_to_enums = {} -enums_to_ints = {} -irop_enums_to_ints = {} +ints_to_enums: Dict[int, str] = {} +enums_to_ints: Dict[str, int] = {} +irop_enums_to_ints: Dict[str, int] = {} will_be_overwritten = ["Ircr_GT", "Ircr_LT"] @@ -109,12 +109,16 @@ def get_int_from_enum(e): return enums_to_ints[e] +_add_enum_counter = 0 + + def _add_enum(s, i=None): # TODO get rid of this + global _add_enum_counter # pylint: disable=global-statement if i is None: - while _add_enum.counter in ints_to_enums: - _add_enum.counter += 1 - i = _add_enum.counter - _add_enum.counter += 1 # Update for the next iteration + while _add_enum_counter in ints_to_enums: + _add_enum_counter += 1 + i = _add_enum_counter + _add_enum_counter += 1 # Update for the next iteration if i in ints_to_enums: if ints_to_enums[i] not in will_be_overwritten: raise ValueError("Enum with intkey %d already present" % i) @@ -124,8 +128,6 @@ def _add_enum(s, i=None): # TODO get rid of this irop_enums_to_ints[s] = i -_add_enum.counter = 0 - for attr in dir(pvc): if attr[0] in "ABCDEFGHIJKLMNOPQRSTUVWXYZ" and hasattr(pvc, attr) and isinstance(getattr(pvc, attr), int): _add_enum(attr, getattr(pvc, attr)) @@ -135,7 +137,7 @@ def vex_endness_from_string(endness_str): return getattr(pvc, endness_str) -def default_vex_archinfo(): +def default_vex_archinfo() -> Dict[str, Any]: return { "hwcaps": 0, "endness": vex_endness_from_string("VexEndnessLE"), diff --git a/pyvex/expr.py b/pyvex/expr.py index 5e2188dc..942d39bd 100644 --- a/pyvex/expr.py +++ b/pyvex/expr.py @@ -1,8 +1,6 @@ import logging import re -from typing import List, Optional - -from archinfo.types import RegisterOffset, TmpVar +from typing import Dict, List, Optional, Tuple from .const import U8, U16, U32, U64, IRConst, get_type_size from .enums import IRCallee, IRRegArray, VEXObject, get_enum_from_int, get_int_from_enum @@ -23,7 +21,13 @@ class IRExpr(VEXObject): tag_int = 0 # set automatically at bottom of file def pp(self): - print(self.__str__()) + print(str(self)) + + def __str__(self): + return self._pp_str() + + def _pp_str(self) -> str: + raise NotImplementedError @property def child_expressions(self) -> List["IRExpr"]: @@ -91,7 +95,7 @@ def replace_expression(self, replacements): v.replace_expression(replacements) @staticmethod - def _from_c(c_expr) -> "IRExpr": + def _from_c(c_expr) -> Optional["IRExpr"]: if c_expr == ffi.NULL or c_expr[0] == ffi.NULL: return None @@ -125,7 +129,7 @@ class Binder(IRExpr): def __init__(self, binder): self.binder = binder - def __str__(self): + def _pp_str(self): return "Binder" @staticmethod @@ -145,7 +149,7 @@ class VECRET(IRExpr): __slots__ = [] - def __str__(self): + def _pp_str(self): return "VECRET" @staticmethod @@ -165,7 +169,7 @@ class GSPTR(IRExpr): tag = "Iex_GSPTR" - def __str__(self): + def _pp_str(self): return "GSPTR" @staticmethod @@ -202,7 +206,7 @@ def description(self): def index(self): return self.ix - def __str__(self): + def _pp_str(self): return f"GetI({self.descr})[{self.ix},{self.bias}]" @staticmethod @@ -229,14 +233,14 @@ class RdTmp(IRExpr): tag = "Iex_RdTmp" - def __init__(self, tmp: TmpVar): + def __init__(self, tmp): self._tmp = tmp - def __str__(self): + def _pp_str(self): return "t%d" % self.tmp @property - def tmp(self) -> TmpVar: + def tmp(self): return self._tmp @staticmethod @@ -278,7 +282,7 @@ class Get(IRExpr): tag = "Iex_Get" - def __init__(self, offset: RegisterOffset, ty: str, ty_int: Optional[int] = None): + def __init__(self, offset, ty: str, ty_int: Optional[int] = None): self.offset = offset if ty_int is None: self.ty_int = get_int_from_enum(ty) @@ -293,7 +297,7 @@ def ty(self): def type(self): return get_enum_from_int(self.ty_int) - def __str__(self, reg_name=None): + def _pp_str(self, reg_name=None): if reg_name: return f"GET:{self.ty[4:]}({reg_name})" else: @@ -327,7 +331,7 @@ def __init__(self, op, args): self.op = op self.args = args - def __str__(self): + def _pp_str(self): return "{}({})".format(self.op[4:], ",".join(str(a) for a in self.args)) @property @@ -396,7 +400,7 @@ def __init__(self, op, args): self.op = op self.args = args - def __str__(self): + def _pp_str(self): return "{}({})".format(self.op[4:], ",".join(str(a) for a in self.args)) @property @@ -457,7 +461,7 @@ def __init__(self, op, args, op_int=None): self.args = args self._op = op if op is not None else None - def __str__(self): + def _pp_str(self): return "{}({})".format(self.op[4:], ",".join(str(a) for a in self.args)) @property @@ -518,7 +522,7 @@ def __init__(self, op, args): self.op = op self.args = args - def __str__(self): + def _pp_str(self): return "{}({})".format(self.op[4:], ",".join(str(a) for a in self.args)) @property @@ -573,7 +577,7 @@ def endness(self): def type(self): return self.ty - def __str__(self): + def _pp_str(self): return f"LD{self.end[-2:].lower()}:{self.ty[4:]}({self.addr})" @staticmethod @@ -613,7 +617,7 @@ class Const(IRExpr): def __init__(self, con: "IRConst"): self._con = con - def __str__(self): + def _pp_str(self): return str(self.con) @property @@ -661,7 +665,7 @@ def __init__(self, cond, iffalse, iftrue): self.iffalse = iffalse self.iftrue = iftrue - def __str__(self): + def _pp_str(self): return f"ITE({self.cond},{self.iftrue},{self.iffalse})" @staticmethod @@ -720,7 +724,7 @@ def ret_type(self): def callee(self): return self.cee - def __str__(self): + def _pp_str(self): return "{}({}):{}".format(self.cee, ",".join(str(a) for a in self.args), self.retty) @property @@ -756,7 +760,7 @@ def get_op_retty(op): return op_arg_types(op)[0] -op_signatures = {} +op_signatures: Dict[str, Tuple[str, Tuple[str, ...]]] = {} def _request_op_type_from_cache(op): diff --git a/pyvex/lifting/gym/arm_spotter.py b/pyvex/lifting/gym/arm_spotter.py index 6006899d..f69c14b9 100644 --- a/pyvex/lifting/gym/arm_spotter.py +++ b/pyvex/lifting/gym/arm_spotter.py @@ -5,6 +5,7 @@ from pyvex.lifting.util import JumpKind, Type from pyvex.lifting.util.instr_helper import Instruction, ParseError from pyvex.lifting.util.lifter_helper import GymratLifter +from pyvex.types import Arch log = logging.getLogger(__name__) @@ -201,10 +202,8 @@ def match_instruction(self, data, bitstrm): def compute_result(self): # pylint: disable=arguments-differ # test if PC will be set. If so, the jumpkind of this block should be Ijk_Ret log.debug("Spotting an LDM instruction at %#x. This is not fully tested. Prepare for errors.", self.addr) - # l.warning(repr(self.rawbits)) - # l.warning(repr(self.data)) - src_n = int(self.data["b"], 2) + src_n = f"r{int(self.data['b'], 2)}" src = self.get(src_n, Type.int_32) for reg_num, bit in enumerate(self.data["r"]): @@ -216,7 +215,7 @@ def compute_result(self): # pylint: disable=arguments-differ else: src -= 4 val = self.load(src, Type.int_32) - self.put(val, reg_num) + self.put(val, f"r{reg_num}") if self.data["P"] == "0": if self.data["U"] == "0": src += 4 @@ -313,7 +312,7 @@ class Instruction_tMSR(ThumbInstruction): def compute_result(self): # pylint: disable=arguments-differ dest_spec_reg = int(self.data["x"], 2) - src_reg = int(self.data["r"], 2) + src_reg = f"r{int(self.data['r'], 2)}" # If 0, do not write the SPSR if self.data["R"] == "0": @@ -343,7 +342,7 @@ class Instruction_tMRS(ThumbInstruction): def compute_result(self): # pylint: disable=arguments-differ spec_reg = int(self.data["x"], 2) - dest_reg = int(self.data["m"], 2) + dest_reg = f"r{int(self.data['m'], 2)}" # Reading from CPSR if self.data["R"] == "0": @@ -411,8 +410,8 @@ class ARMSpotter(GymratLifter): Instruction_LDC_THUMB, ] - def __init__(self, *args): - super().__init__(*args) + def __init__(self, arch: Arch, addr: int): + super().__init__(arch, addr) self.thumb: bool = False def _lift(self): diff --git a/pyvex/lifting/libvex.py b/pyvex/lifting/libvex.py index 86e8b20a..52329483 100644 --- a/pyvex/lifting/libvex.py +++ b/pyvex/lifting/libvex.py @@ -1,8 +1,10 @@ import logging import threading +from typing import TYPE_CHECKING from pyvex.errors import LiftingException from pyvex.native import ffi, pvc +from pyvex.types import CLiftSource, LibvexArch from .lift_function import Lifter @@ -49,11 +51,15 @@ def get_vex_log(): return bytes(ffi.buffer(pvc.msg_buffer, pvc.msg_current_size)).decode() if pvc.msg_buffer != ffi.NULL else None def _lift(self): + if TYPE_CHECKING: + assert isinstance(self.irsb.arch, LibvexArch) + assert isinstance(self.data, CLiftSource) try: _libvex_lock.acquire() pvc.log_level = log.getEffectiveLevel() - vex_arch = getattr(pvc, self.irsb.arch.vex_arch) + vex_arch = getattr(pvc, self.irsb.arch.vex_arch, None) + assert vex_arch is not None if self.bytes_offset is None: self.bytes_offset = 0 diff --git a/pyvex/lifting/lift_function.py b/pyvex/lifting/lift_function.py index 5346f621..a14dd8bd 100644 --- a/pyvex/lifting/lift_function.py +++ b/pyvex/lifting/lift_function.py @@ -1,7 +1,6 @@ import logging from collections import defaultdict - -import archinfo +from typing import DefaultDict, List, Optional, Type from pyvex import const from pyvex.block import IRSB @@ -9,18 +8,19 @@ from pyvex.errors import LiftingException, NeedStatementsNotification, PyVEXError, SkipStatementsError from pyvex.expr import Const from pyvex.native import ffi +from pyvex.types import LiftSource, PyLiftSource from .lifter import Lifter from .post_processor import Postprocessor log = logging.getLogger(__name__) -lifters = defaultdict(list) -postprocessors = defaultdict(list) +lifters: DefaultDict[str, List[Type[Lifter]]] = defaultdict(list) +postprocessors: DefaultDict[str, List[Type[Postprocessor]]] = defaultdict(list) def lift( - data, + data: LiftSource, addr, arch, max_bytes=None, @@ -44,7 +44,6 @@ def lift( of the data and if they work, their output is appended to the first block. :param arch: The arch to lift the data as. - :type arch: :class:`archinfo.Arch` :param addr: The starting address of the block. Effects the IMarks. :param data: The bytes to lift as either a python string of bytes or a cffi buffer object. :param max_bytes: The maximum number of bytes to lift. If set to None, no byte limit is used. @@ -75,6 +74,7 @@ def lift( if isinstance(data, str): raise TypeError("Cannot pass unicode string as data to lifter") + py_data: Optional[PyLiftSource] if isinstance(data, (bytes, bytearray, memoryview)): py_data = data c_data = None @@ -97,20 +97,25 @@ def lift( for lifter in lifters[arch.name]: try: - u_data = data + u_data: LiftSource = data if lifter.REQUIRE_DATA_C: if c_data is None: - u_data = ffi.from_buffer(ffi.BVoidP, py_data + b"\0" * 8 if isinstance(py_data, bytes) else py_data) + assert py_data is not None + if isinstance(py_data, (bytearray, memoryview)): + u_data = ffi.from_buffer(ffi.BVoidP, py_data) + else: + u_data = ffi.from_buffer(ffi.BVoidP, py_data + b"\0" * 8) max_bytes = min(len(py_data), max_bytes) if max_bytes is not None else len(py_data) else: u_data = c_data skip = 0 elif lifter.REQUIRE_DATA_PY: - if bytes_offset and archinfo.arch_arm.is_arm_arch(arch) and (addr & 1) == 1: + if bytes_offset and arch.name.startswith("ARM") and (addr & 1) == 1: skip = bytes_offset - 1 else: skip = bytes_offset if py_data is None: + assert c_data is not None if max_bytes is None: log.debug("Cannot create py_data from c_data when no max length is given") continue diff --git a/pyvex/lifting/lifter.py b/pyvex/lifting/lifter.py index af1c0e50..d60e0612 100644 --- a/pyvex/lifting/lifter.py +++ b/pyvex/lifting/lifter.py @@ -1,4 +1,7 @@ +from typing import Optional, Union + from pyvex.block import IRSB +from pyvex.types import Arch, LiftSource # pylint:disable=attribute-defined-outside-init @@ -44,26 +47,26 @@ class Lifter: REQUIRE_DATA_C = False REQUIRE_DATA_PY = False - def __init__(self, arch, addr): - self.arch = arch - self.addr = addr + def __init__(self, arch: Arch, addr: int): + self.arch: Arch = arch + self.addr: int = addr def lift( self, - data, - bytes_offset=None, - max_bytes=None, - max_inst=None, - opt_level=1, - traceflags=None, - allow_arch_optimizations=None, - strict_block_end=None, - skip_stmts=False, - collect_data_refs=False, - cross_insn_opt=True, - load_from_ro_regions=False, - disasm=False, - dump_irsb=False, + data: LiftSource, + bytes_offset: Optional[int] = None, + max_bytes: Optional[int] = None, + max_inst: Optional[int] = None, + opt_level: Union[int, float] = 1, + traceflags: Optional[int] = None, + allow_arch_optimizations: Optional[bool] = None, + strict_block_end: Optional[bool] = None, + skip_stmts: bool = False, + collect_data_refs: bool = False, + cross_insn_opt: bool = True, + load_from_ro_regions: bool = False, + disasm: bool = False, + dump_irsb: bool = False, ): """ Wrapper around the `_lift` method on Lifters. Should not be overridden in child classes. @@ -87,7 +90,7 @@ def lift( :param disasm: Should the GymratLifter generate disassembly during lifting. :param dump_irsb: Should the GymratLifter log the lifted IRSB. """ - irsb = IRSB.empty_block(self.arch, self.addr) + irsb: IRSB = IRSB.empty_block(self.arch, self.addr) self.data = data self.bytes_offset = bytes_offset self.opt_level = opt_level diff --git a/pyvex/lifting/util/instr_helper.py b/pyvex/lifting/util/instr_helper.py index ba79df81..8129e74a 100644 --- a/pyvex/lifting/util/instr_helper.py +++ b/pyvex/lifting/util/instr_helper.py @@ -1,5 +1,6 @@ import abc import string +from typing import Dict import bitstring @@ -67,8 +68,8 @@ class Instruction(metaclass=abc.ABCMeta): See the examples provided by gymrat for ideas of how to use this to build your own lifters quickly and easily. """ - data = None - irsb_c = None + data: Dict[str, str] + irsb_c: IRSBCustomizer def __init__(self, bitstrm, arch, addr): """ @@ -254,6 +255,8 @@ def constant(self, val, ty): @staticmethod def _lookup_register(arch, reg): + # TODO: This is a hack to make it work with archinfo where we use + # register indicies instead of names if isinstance(reg, int): if hasattr(arch, "register_index"): reg = arch.register_index[reg] diff --git a/pyvex/lifting/util/irsb_postprocess.py b/pyvex/lifting/util/irsb_postprocess.py deleted file mode 100644 index 88c4d416..00000000 --- a/pyvex/lifting/util/irsb_postprocess.py +++ /dev/null @@ -1,67 +0,0 @@ -from typing import Optional - -from pyvex.block import IRSB -from pyvex.expr import Binop, Const, Get, Qop, RdTmp, Triop, Unop -from pyvex.stmt import IMark, NoOp, Put, Store, WrTmp - -from .vex_helper import IRSBCustomizer - - -def _flatten_and_get_expr(irsb_old, irsb_c, old_to_new_tmp, expr): - if isinstance(expr, Const): - return expr - elif isinstance(expr, RdTmp): - return RdTmp.get_instance(old_to_new_tmp[expr.tmp]) - elif isinstance(expr, Get): - return RdTmp.get_instance(irsb_c.mktmp(expr)) - else: - assert expr.__class__ in [ - Unop, - Binop, - Triop, - Qop, - ], f"Flattening expressions of type {expr.__class__} is not supported yet." - expr_args = [_flatten_and_get_expr(irsb_old, irsb_c, old_to_new_tmp, expr_arg) for expr_arg in expr.args] - return RdTmp.get_instance(irsb_c.mktmp(expr.__class__(expr.op, expr_args))) - - -def irsb_postproc_flatten(irsb_old: IRSB, irsb_new: Optional[IRSB] = None) -> IRSB: - """ - - :param irsb_old: The IRSB to be flattened - :param irsb_new: the IRSB to rewrite the instructions of irsb_old to. If it is None a new empty IRSB will be created - :return: the flattened IRSB - """ - irsb_new = irsb_new if irsb_new is not None else IRSB(None, irsb_old.addr, irsb_old.arch) - irsb_c = IRSBCustomizer(irsb_new) - old_to_new_tmp = {} - - for i, statement in enumerate(irsb_old.statements): - if isinstance(statement, WrTmp): - flat_expr = _flatten_and_get_expr(irsb_old, irsb_c, old_to_new_tmp, statement.data) - if isinstance(flat_expr, RdTmp): - tmp_new = flat_expr.tmp - else: - tmp_new = irsb_c.mktmp(flat_expr) - old_to_new_tmp[statement.tmp] = tmp_new # register our new tmp mapping - - elif isinstance(statement, Put): - flat_expr = _flatten_and_get_expr(irsb_old, irsb_c, old_to_new_tmp, statement.data) - irsb_c.put(flat_expr, statement.offset) - - elif isinstance(statement, Store): - flat_expr = _flatten_and_get_expr(irsb_old, irsb_c, old_to_new_tmp, statement.data) - irsb_c.store(statement.addr, flat_expr, statement.end) - - elif isinstance(statement, IMark): - irsb_c.imark(statement.addr, statement.len, statement.delta) - - elif isinstance(statement, NoOp): - irsb_c.noop() - - irsb_new.next = irsb_old.next - irsb_new.jumpkind = irsb_old.jumpkind - - assert irsb_new == irsb_c.irsb - assert irsb_new.typecheck() - return irsb_new diff --git a/pyvex/lifting/util/lifter_helper.py b/pyvex/lifting/util/lifter_helper.py index 64220849..922c8248 100644 --- a/pyvex/lifting/util/lifter_helper.py +++ b/pyvex/lifting/util/lifter_helper.py @@ -1,4 +1,5 @@ import logging +from typing import TYPE_CHECKING, List, Type import bitstring @@ -8,6 +9,9 @@ from .vex_helper import IRSBCustomizer, JumpKind +if TYPE_CHECKING: + from .instr_helper import Instruction + log = logging.getLogger(__name__) @@ -42,10 +46,10 @@ class GymratLifter(Lifter): ) REQUIRE_DATA_PY = True - instrs = None + instrs: List[Type["Instruction"]] - def __init__(self, *args): - super().__init__(*args) + def __init__(self, arch, addr): + super().__init__(arch, addr) self.bitstrm = None self.errors = None self.thedata = None diff --git a/pyvex/stmt.py b/pyvex/stmt.py index bb9cbf5d..eccfff2f 100644 --- a/pyvex/stmt.py +++ b/pyvex/stmt.py @@ -1,8 +1,6 @@ import logging from typing import Iterator, Optional -from archinfo.types import RegisterOffset, TmpVar - from . import expr from .const import IRConst from .enums import IRCallee, IRRegArray, VEXObject, get_enum_from_int, get_int_from_enum @@ -24,7 +22,7 @@ class IRStmt(VEXObject): __slots__ = [] def pp(self): - print(self.__str__()) + print(str(self)) @property def child_expressions(self) -> Iterator["IRExpr"]: @@ -86,7 +84,10 @@ def replace_expression(self, replacements): if replaced: setattr(self, k, tuple(_lst)) - def __str__(self, reg_name=None, arch=None, tyenv=None): + def __str__(self): + return self._pp_str(None, None, None) + + def _pp_str(self, reg_name=None, arch=None, tyenv=None) -> str: raise NotImplementedError() @@ -99,7 +100,7 @@ class NoOp(IRStmt): tag = "Ist_NoOp" - def __str__(self, reg_name=None, arch=None, tyenv=None): + def _pp_str(self, reg_name=None, arch=None, tyenv=None): return "IR-NoOp" @staticmethod @@ -123,7 +124,7 @@ def __init__(self, addr: int, length: int, delta: int): self.len = length self.delta = delta - def __str__(self, reg_name=None, arch=None, tyenv=None): + def _pp_str(self, reg_name=None, arch=None, tyenv=None): return "------ IMark(0x%x, %d, %d) ------" % (self.addr, self.len, self.delta) @staticmethod @@ -145,7 +146,7 @@ def __init__(self, base, length, nia): self.len = length self.nia = nia - def __str__(self, reg_name=None, arch=None, tyenv=None): + def _pp_str(self, reg_name=None, arch=None, tyenv=None): return "====== AbiHint(0x%s, %d, %s) ======" % (self.base, self.len, self.nia) @staticmethod @@ -164,12 +165,12 @@ class Put(IRStmt): tag = "Ist_Put" - def __init__(self, data: "IRExpr", offset: RegisterOffset): + def __init__(self, data: "IRExpr", offset): self.data = data self.offset = offset ## TODO: Check if result_size and arch are available before looking of arch register name - def __str__(self, reg_name=None, arch=None, tyenv=None): + def _pp_str(self, reg_name=None, arch=None, tyenv=None): if arch is not None and tyenv is not None: reg_name = arch.translate_register_name(self.offset, self.data.result_size(tyenv) // 8) @@ -201,7 +202,7 @@ def __init__(self, descr, ix, data, bias): self.data = data self.bias = bias - def __str__(self, reg_name=None, arch=None, tyenv=None): + def _pp_str(self, reg_name=None, arch=None, tyenv=None): return "PutI(%s)[%s,%d] = %s" % (self.descr, self.ix, self.bias, self.data) @staticmethod @@ -233,18 +234,18 @@ class WrTmp(IRStmt): tag = "Ist_WrTmp" - def __init__(self, tmp: TmpVar, data: "IRExpr"): + def __init__(self, tmp, data: "IRExpr"): self.tmp = tmp self.data = data - def __str__(self, reg_name=None, arch=None, tyenv=None): + def _pp_str(self, reg_name=None, arch=None, tyenv=None): # Support for named register in string representation of expr.Get if arch is not None and tyenv is not None and isinstance(self.data, Get): reg_name = arch.translate_register_name(self.data.offset, self.data.result_size(tyenv) // 8) if reg_name is not None and isinstance(self.data, expr.Get): - return "t%d = %s" % (self.tmp, self.data.__str__(reg_name=reg_name)) + return "t%d = %s" % (self.tmp, self.data._pp_str(reg_name=reg_name)) else: return "t%d = %s" % (self.tmp, self.data) @@ -280,7 +281,7 @@ def __init__(self, addr: "IRExpr", data: "IRExpr", end: str): def endness(self): return self.end - def __str__(self, reg_name=None, arch=None, tyenv=None): + def _pp_str(self, reg_name=None, arch=None, tyenv=None): return f"ST{self.endness[-2:].lower()}({self.addr}) = {self.data}" @staticmethod @@ -330,7 +331,7 @@ def __init__(self, addr, dataLo, dataHi, expdLo, expdHi, oldLo, oldHi, end): def endness(self): return self.end - def __str__(self, reg_name=None, arch=None, tyenv=None): + def _pp_str(self, reg_name=None, arch=None, tyenv=None): return "t({},{}) = CAS{}({} :: ({},{})->({},{}))".format( self.oldLo, self.oldHi, self.end[-2:].lower(), self.addr, self.expdLo, self.expdHi, self.dataLo, self.dataHi ) @@ -412,7 +413,7 @@ def __init__(self, addr, storedata, result, end): def endness(self): return self.end - def __str__(self, reg_name=None, arch=None, tyenv=None): + def _pp_str(self, reg_name=None, arch=None, tyenv=None): if self.storedata is None: return "t%d = LD%s-Linked(%s)" % (self.result, self.end[-2:].lower(), self.addr) else: @@ -459,7 +460,7 @@ class MBE(IRStmt): def __init__(self, event): self.event = event - def __str__(self, reg_name=None, arch=None, tyenv=None): + def _pp_str(self, reg_name=None, arch=None, tyenv=None): return "MBusEvent-" + self.event @staticmethod @@ -482,7 +483,7 @@ def __init__(self, cee, guard, args, tmp, mFx, mAddr, mSize, nFxState): self.mSize = mSize self.nFxState = nFxState - def __str__(self, reg_name=None, arch=None, tyenv=None): + def _pp_str(self, reg_name=None, arch=None, tyenv=None): return "t{} = DIRTY {} {} ::: {}({})".format( self.tmp, self.guard, "TODO(effects)", self.cee, ",".join(str(a) for a in self.args) ) @@ -536,7 +537,7 @@ def __init__(self, guard, dst, jk, offsIP): def jumpkind(self): return self.jk - def __str__(self, reg_name=None, arch=None, tyenv=None): + def _pp_str(self, reg_name=None, arch=None, tyenv=None): if arch is not None and tyenv is not None: reg_name = arch.translate_register_name(self.offsIP, arch.bits // 8) @@ -599,7 +600,7 @@ def __init__(self, end, cvt, dst, addr, alt, guard): def endness(self): return self.end - def __str__(self, reg_name=None, arch=None, tyenv=None): + def _pp_str(self, reg_name=None, arch=None, tyenv=None): return "t%d = if (%s) %s(LD%s(%s)) else %s" % ( self.dst, self.guard, @@ -668,7 +669,7 @@ def __init__(self, end, addr, data, guard): def endness(self): return self.end - def __str__(self, reg_name=None, arch=None, tyenv=None): + def _pp_str(self, reg_name=None, arch=None, tyenv=None): return f"if ({self.guard}) ST{self.end[-2:].lower()}({self.addr}) = {self.data}" @staticmethod diff --git a/pyvex/types.py b/pyvex/types.py new file mode 100644 index 00000000..c7c42314 --- /dev/null +++ b/pyvex/types.py @@ -0,0 +1,50 @@ +from typing import TYPE_CHECKING, Any, Dict, List, Optional, Protocol, Tuple, Union, runtime_checkable + +from cffi.api import FFI + + +class Register(Protocol): + """ + A register. Pyvex should probably not have this dependency. + """ + + name: str + + +class Arch(Protocol): + """ + An architecture description. + """ + + name: str + ip_offset: int + bits: int + instruction_endness: str + memory_endness: str + byte_width: int + register_list: List[Register] + registers: Dict[str, Tuple[int, int]] + + def translate_register_name(self, offset: int, size: Optional[int] = None) -> Optional[str]: + ... + + def get_register_offset(self, name: str) -> int: + ... + + +@runtime_checkable +class LibvexArch(Protocol): + """ + The description for an architecture that is usable with libvex + """ + + vex_arch: str + vex_archinfo: Dict[str, Any] + + +PyLiftSource = Union[bytes, bytearray, memoryview] +if TYPE_CHECKING: + CLiftSource = FFI.CData +else: + CLiftSource = None +LiftSource = Union[PyLiftSource, CLiftSource] diff --git a/pyvex/utils.py b/pyvex/utils.py index d51ea5c5..17129d1b 100644 --- a/pyvex/utils.py +++ b/pyvex/utils.py @@ -1,5 +1,5 @@ import struct -from typing import Tuple +from typing import Any, Callable, Dict, Tuple try: import _md5 as md5lib @@ -54,7 +54,7 @@ def _dump_type(t: type) -> bytes: return t.__name__.encode("ascii") -_DUMP_BY_TYPE = { +_DUMP_BY_TYPE: Dict[type, Callable[[Any], bytes]] = { tuple: _dump_tuple, str: _dump_str, int: _dump_int, diff --git a/setup.cfg b/setup.cfg index ac757a8c..fefe52e8 100644 --- a/setup.cfg +++ b/setup.cfg @@ -22,7 +22,6 @@ classifiers = [options] packages = find: install_requires = - archinfo==9.2.80.dev0 bitstring cffi>=1.0.3;implementation_name == 'cpython' python_requires = >=3.8 diff --git a/tests/test_arm_postprocess.py b/tests/test_arm_postprocess.py index 67fdd4f8..455ad554 100644 --- a/tests/test_arm_postprocess.py +++ b/tests/test_arm_postprocess.py @@ -1,5 +1,3 @@ -import archinfo - import pyvex @@ -19,7 +17,7 @@ def test_arm_postprocess_call(): irsb = pyvex.IRSB( data=(b"\x80\xb4" b"\x00\xaf" b"\x4f\xf0\x06\x01" b"\x78\x46" b"\x00\xeb\x01\x0e" b"\xff\xf7\xec\xbf"), mem_addr=0x1041F, - arch=archinfo.ArchARMEL(), + arch=pyvex.ARCH_ARM_LE, num_inst=6, bytes_offset=1, opt_level=i, @@ -31,7 +29,7 @@ def test_arm_postprocess_call(): irsb = pyvex.IRSB( data=(b"\xfe\x46" b"\xe9\xe7"), mem_addr=0x10431, - arch=archinfo.ArchARMEL(), + arch=pyvex.ARCH_ARM_LE, num_inst=2, bytes_offset=1, opt_level=i, @@ -44,7 +42,7 @@ def test_arm_postprocess_call(): irsb = pyvex.IRSB( data=(b"\x00\xa2" b"\x02\xf1\x06\x0e" b"\xdf\xf8\x34\xf0"), mem_addr=0x10435, - arch=archinfo.ArchARMEL(), + arch=pyvex.ARCH_ARM_LE, num_inst=3, bytes_offset=1, opt_level=i, @@ -69,7 +67,7 @@ def test_arm_postprocess_call(): b"\x87\x46" ), mem_addr=0x1043F, - arch=archinfo.ArchARMEL(), + arch=pyvex.ARCH_ARM_LE, num_inst=7, bytes_offset=1, opt_level=i, @@ -82,7 +80,7 @@ def test_arm_postprocess_call(): irsb = pyvex.IRSB( data=(b"\x80\xea\x00\x00" b"\x86\x46" b"\x01\xe0"), mem_addr=0x10455, - arch=archinfo.ArchARMEL(), + arch=pyvex.ARCH_ARM_LE, num_inst=3, bytes_offset=1, opt_level=i, @@ -98,7 +96,7 @@ def test_arm_postprocess_call(): irsb = pyvex.IRSB( data=(b"\x4f\xf0\x06\x01" b"\x78\x46" b"\x00\xeb\x01\x0e" b"\x00\xf0\xc5\xb8"), mem_addr=0x10325, - arch=archinfo.ArchARMEL(), + arch=pyvex.ARCH_ARM_LE, num_inst=4, bytes_offset=1, opt_level=i, @@ -123,7 +121,7 @@ def test_arm_postprocess_call(): b"\x87\x46" ), mem_addr=0x10333, - arch=archinfo.ArchARMEL(), + arch=pyvex.ARCH_ARM_LE, num_inst=7, bytes_offset=1, opt_level=i, @@ -136,7 +134,7 @@ def test_arm_postprocess_call(): irsb = pyvex.IRSB( data=(b"\x00\xa2" b"\x02\xf1\x06\x0e" b"\xdf\xf8\x1c\xf0"), mem_addr=0x10349, - arch=archinfo.ArchARMEL(), + arch=pyvex.ARCH_ARM_LE, num_inst=3, bytes_offset=1, opt_level=i, @@ -148,7 +146,7 @@ def test_arm_postprocess_call(): irsb = pyvex.IRSB( data=(b"\xfe\x46" b"\xb2\xe0"), mem_addr=0x10353, - arch=archinfo.ArchARMEL(), + arch=pyvex.ARCH_ARM_LE, num_inst=2, bytes_offset=1, opt_level=i, @@ -161,7 +159,7 @@ def test_arm_postprocess_call(): irsb = pyvex.IRSB( data=(b"\x80\xea\x00\x00" b"\x86\x46" b"\x01\xe0"), mem_addr=0x10357, - arch=archinfo.ArchARMEL(), + arch=pyvex.ARCH_ARM_LE, num_inst=3, bytes_offset=1, opt_level=i, @@ -177,7 +175,7 @@ def test_arm_postprocess_call(): irsb = pyvex.IRSB( data=(b"\x04\x10\xa0\xe3" b"\x0f\x00\xa0\xe1" b"\x01\xe0\x80\xe0" b"\x38\xf0\x9f\xe5"), mem_addr=0x10298, - arch=archinfo.ArchARMEL(), + arch=pyvex.ARCH_ARM_LE, num_inst=4, opt_level=i, ) @@ -199,7 +197,7 @@ def test_arm_postprocess_call(): b"\x54\x00\x00\xea" ), mem_addr=0x102A8, - arch=archinfo.ArchARMEL(), + arch=pyvex.ARCH_ARM_LE, num_inst=6, opt_level=i, ) @@ -210,7 +208,7 @@ def test_arm_postprocess_call(): irsb = pyvex.IRSB( data=(b"\x0f\xe0\xa0\xe1" b"\x52\x00\x00\xea"), mem_addr=0x102C0, - arch=archinfo.ArchARMEL(), + arch=pyvex.ARCH_ARM_LE, num_inst=2, opt_level=i, ) @@ -222,7 +220,7 @@ def test_arm_postprocess_call(): irsb = pyvex.IRSB( data=(b"\x00\x00\x20\xe0" b"\x00\xe0\xa0\xe1" b"\x00\x00\x00\xea"), mem_addr=0x102C8, - arch=archinfo.ArchARMEL(), + arch=pyvex.ARCH_ARM_LE, num_inst=3, opt_level=i, ) @@ -246,7 +244,7 @@ def test_arm_postprocess_call(): b"\x44\xf0\x9f\xe5" ), mem_addr=0x103E8, - arch=archinfo.ArchARMEL(), + arch=pyvex.ARCH_ARM_LE, num_inst=6, opt_level=i, ) @@ -268,7 +266,7 @@ def test_arm_postprocess_call(): b"\x54\xff\xff\xea" ), mem_addr=0x10400, - arch=archinfo.ArchARMEL(), + arch=pyvex.ARCH_ARM_LE, num_inst=6, opt_level=i, ) @@ -279,7 +277,7 @@ def test_arm_postprocess_call(): irsb = pyvex.IRSB( data=(b"\x0f\xe0\xa0\xe1" b"\xe8\xff\xff\xea"), mem_addr=0x10418, - arch=archinfo.ArchARMEL(), + arch=pyvex.ARCH_ARM_LE, num_inst=2, opt_level=i, ) @@ -291,7 +289,7 @@ def test_arm_postprocess_call(): irsb = pyvex.IRSB( data=(b"\x00\x00\x20\xe0" b"\x00\xe0\xa0\xe1" b"\x00\x00\x00\xea"), mem_addr=0x10420, - arch=archinfo.ArchARMEL(), + arch=pyvex.ARCH_ARM_LE, num_inst=3, opt_level=i, ) @@ -310,7 +308,7 @@ def test_arm_postprocess_call(): b"\x01\xf0\xa0\xe1" ), mem_addr=0x264B4C, - arch=archinfo.ArchARMEL(), + arch=pyvex.ARCH_ARM_LE, num_inst=6, opt_level=i, ) @@ -324,7 +322,7 @@ def test_arm_postprocess_ret(): irsb = pyvex.IRSB( data=b"\xe9\x1b\xa8\xf0", mem_addr=0xED4028, - arch=archinfo.ArchARMEL(endness=archinfo.Endness.BE), + arch=pyvex.ARCH_ARM_BE_LE, num_inst=1, opt_level=i, ) @@ -335,7 +333,7 @@ def test_arm_postprocess_ret(): irsb = pyvex.IRSB( data=b"\xe9\x1b\xa8\xf0", mem_addr=0x4D4028, - arch=archinfo.ArchARMEL(endness=archinfo.Endness.BE), + arch=pyvex.ARCH_ARM_BE_LE, num_inst=1, opt_level=i, ) @@ -347,7 +345,7 @@ def test_arm_postprocess_ret(): irsb = pyvex.IRSB( data=b"\x00\xa8\x9d\xe8", mem_addr=0xC800B57C, - arch=archinfo.ArchARMEL(endness=archinfo.Endness.LE), + arch=pyvex.ARCH_ARM_BE, num_inst=1, opt_level=1, ) diff --git a/tests/test_gym.py b/tests/test_gym.py index 48578b29..119f2b21 100644 --- a/tests/test_gym.py +++ b/tests/test_gym.py @@ -1,29 +1,27 @@ # pylint: disable=missing-class-docstring import unittest -import archinfo - import pyvex class Tests(unittest.TestCase): def test_x86_aam(self): - irsb = pyvex.lift(b"\xd4\x0b", 0, archinfo.ArchX86()) + irsb = pyvex.lift(b"\xd4\x0b", 0, pyvex.ARCH_X86) self.assertEqual(irsb.jumpkind, "Ijk_Boring") self.assertEqual(irsb.size, 2) def test_x86_aad(self): - irsb = pyvex.lift(b"\xd5\x0b", 0, archinfo.ArchX86()) + irsb = pyvex.lift(b"\xd5\x0b", 0, pyvex.ARCH_X86) self.assertEqual(irsb.jumpkind, "Ijk_Boring") self.assertEqual(irsb.size, 2) def test_x86_xgetbv(self): - irsb = pyvex.lift(b"\x0f\x01\xd0", 0, archinfo.ArchX86()) + irsb = pyvex.lift(b"\x0f\x01\xd0", 0, pyvex.ARCH_X86) self.assertEqual(irsb.jumpkind, "Ijk_Boring") self.assertEqual(irsb.size, 3) def test_x86_rdmsr(self): - irsb = pyvex.lift(b"\x0f\x32", 0, archinfo.ArchX86()) + irsb = pyvex.lift(b"\x0f\x32", 0, pyvex.ARCH_X86) self.assertEqual(irsb.jumpkind, "Ijk_Boring") self.assertEqual(irsb.size, 2) diff --git a/tests/test_irsb_property_caching.py b/tests/test_irsb_property_caching.py index 4b65cf8d..03acfbfa 100644 --- a/tests/test_irsb_property_caching.py +++ b/tests/test_irsb_property_caching.py @@ -1,17 +1,15 @@ # pylint: disable=missing-class-docstring,no-self-use import unittest -import archinfo - import pyvex class TestCacheInvalidationOnExtend(unittest.TestCase): def test_cache_invalidation_on_extend(self): - b = pyvex.block.IRSB(b"\x50", 0, archinfo.ArchX86()) + b = pyvex.block.IRSB(b"\x50", 0, pyvex.ARCH_X86) assert b.size == 1 assert b.instructions == 1 - toappend = pyvex.block.IRSB(b"\x51", 0, archinfo.ArchX86()) + toappend = pyvex.block.IRSB(b"\x51", 0, pyvex.ARCH_X86) toappend.jumpkind = "Ijk_Invalid" toappend._direct_next = None # Invalidate the cache because I manually changed the jumpkind assert not toappend.direct_next diff --git a/tests/test_lift.py b/tests/test_lift.py index e9c1105b..6a0416ab 100644 --- a/tests/test_lift.py +++ b/tests/test_lift.py @@ -1,7 +1,6 @@ import unittest -import archinfo - +import pyvex from pyvex import IRSB, ffi, lift from pyvex.errors import PyVEXError from pyvex.lifting.util import GymratLifter, Instruction, JumpKind @@ -25,7 +24,7 @@ def compute_result(self, *args): class NOPLifter(GymratLifter): instrs = [NOP] - lifter = NOPLifter(archinfo.ArchAMD64(), 0) + lifter = NOPLifter(pyvex.ARCH_AMD64, 0) # this should not throw an exception block = lifter.lift("\x0F\x0Fa") assert block.size == 2 @@ -51,7 +50,7 @@ def test_skipstmts_toomanyexits(self): "3069C059B4C93049B4E9350ABCDF834C1CDF83CE185E8030094" "E803004B9683E8030015A94498C4F7E2EA " ) - arch = archinfo.arch_from_id("ARMEL") + arch = pyvex.ARCH_ARM_LE # Lifting the first four bytes will not cause any problem. Statements should be skipped as expected b = IRSB(bytes_[:34], 0xC6951, arch, opt_level=1, bytes_offset=5, skip_stmts=True) assert len(b.exit_statements) > 0 @@ -69,7 +68,7 @@ def test_skipstmts_toomanyexits(self): def test_max_bytes(self): data = bytes.fromhex("909090909090c3") - arch = archinfo.ArchX86() + arch = pyvex.ARCH_X86 assert lift(data, 0x1000, arch, max_bytes=None).size == len(data) assert lift(data, 0x1000, arch, max_bytes=len(data) - 1).size == len(data) - 1 assert lift(data, 0x1000, arch, max_bytes=len(data) + 1).size == len(data) diff --git a/tests/test_mips32_postprocess.py b/tests/test_mips32_postprocess.py index abe2db65..e154a6af 100644 --- a/tests/test_mips32_postprocess.py +++ b/tests/test_mips32_postprocess.py @@ -1,5 +1,3 @@ -import archinfo - import pyvex @@ -11,7 +9,7 @@ def test_mips32_unconditional_jumps(): irsb = pyvex.IRSB( data=(b"\x10\x00\x00\x02" b"\x00\x00\x00\x00"), mem_addr=0x40000C, - arch=archinfo.ArchMIPS32(), + arch=pyvex.ARCH_MIPS32_BE, num_inst=2, opt_level=0, ) diff --git a/tests/test_pyvex.py b/tests/test_pyvex.py index aa46bc7b..d059ccf2 100644 --- a/tests/test_pyvex.py +++ b/tests/test_pyvex.py @@ -6,8 +6,6 @@ import sys import unittest -from archinfo import ArchAMD64, ArchARM, ArchPPC32, ArchX86, Endness - import pyvex from pyvex.lifting import LibVEXLifter @@ -21,7 +19,7 @@ class TestPyvex(unittest.TestCase): sys.platform == "linux", "Cannot import the resource package on windows, values different on macos." ) def test_memory(self): - arches = [ArchX86(), ArchPPC32(endness=Endness.BE), ArchAMD64(), ArchARM()] + arches = [pyvex.ARCH_X86, pyvex.ARCH_PPC32, pyvex.ARCH_AMD64, pyvex.ARCH_ARM_BE] # we're not including ArchMIPS32 cause it segfaults sometimes # disable logging, as that may fill up log buffers somewhere @@ -74,14 +72,14 @@ def test_ircallee(self): def test_irsb_empty(self): self.assertRaises(Exception, pyvex.IRSB) - self.assertRaises(Exception, pyvex.IRSB, data="", arch=ArchAMD64(), mem_addr=0) + self.assertRaises(Exception, pyvex.IRSB, data="", arch=pyvex.ARCH_AMD64, mem_addr=0) def test_irsb_arm(self): - irsb = pyvex.IRSB(data=b"\x33\xff\x2f\xe1", mem_addr=0, arch=ArchARM()) + irsb = pyvex.IRSB(data=b"\x33\xff\x2f\xe1", mem_addr=0, arch=pyvex.ARCH_ARM_BE) assert len([i for i in irsb.statements if type(i) == pyvex.IRStmt.IMark]) == 1 def test_irsb_popret(self): - irsb = pyvex.IRSB(data=b"\x5d\xc3", mem_addr=0, arch=ArchAMD64()) + irsb = pyvex.IRSB(data=b"\x5d\xc3", mem_addr=0, arch=pyvex.ARCH_AMD64) stmts = irsb.statements irsb.pp() @@ -97,8 +95,8 @@ def test_irsb_popret(self): assert irsb.tyenv.lookup(irsb.statements[10].data.tmp) == "Ity_I64" def test_two_irsb(self): - irsb1 = pyvex.IRSB(data=b"\x5d\xc3", mem_addr=0, arch=ArchAMD64()) - irsb2 = pyvex.IRSB(data=b"\x5d\x5d\x5d\x5d", mem_addr=0, arch=ArchAMD64()) + irsb1 = pyvex.IRSB(data=b"\x5d\xc3", mem_addr=0, arch=pyvex.ARCH_AMD64) + irsb2 = pyvex.IRSB(data=b"\x5d\x5d\x5d\x5d", mem_addr=0, arch=pyvex.ARCH_AMD64) stmts1 = irsb1.statements stmts2 = irsb2.statements @@ -106,7 +104,7 @@ def test_two_irsb(self): assert len(stmts1) != len(stmts2) def test_irsb_deepCopy(self): - irsb = pyvex.IRSB(data=b"\x5d\xc3", mem_addr=0, arch=ArchAMD64()) + irsb = pyvex.IRSB(data=b"\x5d\xc3", mem_addr=0, arch=pyvex.ARCH_AMD64) stmts = irsb.statements irsb2 = copy.deepcopy(irsb) @@ -114,7 +112,7 @@ def test_irsb_deepCopy(self): assert len(stmts) == len(stmts2) def test_irsb_addStmt(self): - irsb = pyvex.IRSB(data=b"\x5d\xc3", mem_addr=0, arch=ArchAMD64()) + irsb = pyvex.IRSB(data=b"\x5d\xc3", mem_addr=0, arch=pyvex.ARCH_AMD64) stmts = irsb.statements irsb2 = copy.deepcopy(irsb) @@ -128,13 +126,13 @@ def test_irsb_addStmt(self): irsb2.pp() def test_irsb_tyenv(self): - irsb = pyvex.IRSB(data=b"\x5d\xc3", mem_addr=0, arch=ArchAMD64()) + irsb = pyvex.IRSB(data=b"\x5d\xc3", mem_addr=0, arch=pyvex.ARCH_AMD64) print(irsb.tyenv) print("Orig") print(irsb.tyenv) print("Empty") - irsb2 = pyvex.IRSB.empty_block(arch=ArchAMD64(), addr=0) + irsb2 = pyvex.IRSB.empty_block(arch=pyvex.ARCH_AMD64, addr=0) print(irsb2.tyenv) print("Unwrapped") @@ -146,7 +144,7 @@ def test_irsb_tyenv(self): ################## def test_irstmt_pp(self): - irsb = pyvex.IRSB(data=b"\x5d\xc3", mem_addr=0, arch=ArchAMD64()) + irsb = pyvex.IRSB(data=b"\x5d\xc3", mem_addr=0, arch=pyvex.ARCH_AMD64) stmts = irsb.statements for i in stmts: print("STMT: ", end=" ") @@ -415,7 +413,7 @@ def test_irexpr_rdtmp(self): assert m.tag == "Iex_RdTmp" assert m.tmp == 123 - irsb = pyvex.IRSB(b"\x90\x5d\xc3", mem_addr=0x0, arch=ArchAMD64()) + irsb = pyvex.IRSB(b"\x90\x5d\xc3", mem_addr=0x0, arch=pyvex.ARCH_AMD64) print("TMP:", irsb.next.tmp) def test_irexpr_get(self): diff --git a/tests/test_s390x_exrl.py b/tests/test_s390x_exrl.py index e4d586b8..037d9d0a 100644 --- a/tests/test_s390x_exrl.py +++ b/tests/test_s390x_exrl.py @@ -1,10 +1,8 @@ -import archinfo - import pyvex def test_s390x_exrl(): - arch = archinfo.ArchS390X() + arch = pyvex.ARCH_S390X irsb = pyvex.lift( b"\xc6\x10\x00\x00\x00\x04" # exrl %r1,0x400408 b"\x07\xfe" # br %r14 diff --git a/tests/test_s390x_lochi.py b/tests/test_s390x_lochi.py index 63d0923f..86fe7222 100644 --- a/tests/test_s390x_lochi.py +++ b/tests/test_s390x_lochi.py @@ -1,10 +1,8 @@ -import archinfo - import pyvex def test_s390x_lochi(): - arch = archinfo.ArchS390X() + arch = pyvex.ARCH_S390X irsb = pyvex.lift(b"\xec\x18\xab\xcd\x00\x42", 0x400400, arch) # lochi %r1,0xabcd,8 irsb_str = str(irsb) diff --git a/tests/test_s390x_vl.py b/tests/test_s390x_vl.py index 592f9ca0..f8745f98 100755 --- a/tests/test_s390x_vl.py +++ b/tests/test_s390x_vl.py @@ -1,11 +1,9 @@ #!/usr/bin/env python3 -import archinfo - import pyvex def test_s390x_vl(): - arch = archinfo.ArchS390X() + arch = pyvex.ARCH_S390X irsb = pyvex.lift(b"\xe7\x40\x90\xa8\x00\x06", 0x11C6C9E, arch) # vl %v4, 0xa8(%r9) irsb_str = str(irsb) diff --git a/tests/test_spotter.py b/tests/test_spotter.py index bed7dd4a..9b52d375 100644 --- a/tests/test_spotter.py +++ b/tests/test_spotter.py @@ -1,7 +1,5 @@ import os -import archinfo - import pyvex import pyvex.lifting from pyvex.lifting import register @@ -38,12 +36,12 @@ class ImaginarySpotter(GymratLifter): def test_basic(): - b = pyvex.block.IRSB(b"\x0f\x0b", 1, archinfo.ArchX86()) + b = pyvex.block.IRSB(b"\x0f\x0b", 1, pyvex.ARCH_X86) assert str(b).strip() == basic_goal.strip() def test_embedded(): - b = pyvex.block.IRSB(b"\x50" * 3 + b"\x0f\x0b" + b"\x50" * 6, 1, archinfo.ArchX86()) + b = pyvex.block.IRSB(b"\x50" * 3 + b"\x0f\x0b" + b"\x50" * 6, 1, pyvex.ARCH_X86) for i, stmt in enumerate(b.statements): if type(stmt) is pyvex.stmt.IMark and stmt.addr == 0x4 and stmt.len == 2 and stmt.delta == 0: imaginary_trans_stmt = b.statements[i + 1] @@ -98,22 +96,22 @@ class CortexSpotter(GymratLifter): def test_tmrs(): - arch = archinfo.arch_from_id("ARMEL") + arch = pyvex.ARCH_ARM_LE ins = b"\xef\xf3\x08\x82" b = pyvex.block.IRSB(ins, 1, arch) assert b.jumpkind == "Ijk_Boring" assert type(b.statements[1].data) == pyvex.expr.Get - assert arch.register_names.get(b.statements[1].data.offset, "") == "sp" + assert arch.translate_register_name(b.statements[1].data.offset) in ["sp", "r13"] assert type(b.statements[2]) == pyvex.stmt.Put def test_tmsr(): - arch = archinfo.arch_from_id("ARMEL") + arch = pyvex.ARCH_ARM_LE inss = b"\x82\xf3\x08\x88" b = pyvex.block.IRSB(inss, 1, arch, opt_level=3) assert b.jumpkind == "Ijk_Boring" assert type(b.statements[1].data) == pyvex.expr.Get - assert arch.register_names.get(b.statements[1].data.offset, "") == "r2" + assert arch.translate_register_name(b.statements[1].data.offset) == "r2" assert type(b.statements[2]) == pyvex.stmt.Put diff --git a/tests/test_ud2.py b/tests/test_ud2.py index 24d6e0e8..45cc7e37 100644 --- a/tests/test_ud2.py +++ b/tests/test_ud2.py @@ -1,5 +1,3 @@ -import archinfo - import pyvex @@ -8,7 +6,7 @@ def test_ud2(): # block that ends with ud2, we should treat it as an explicit NoDecode, instead of skipping the instruction and # resume lifting. - b = pyvex.block.IRSB(b"\x90\x90\x0f\x0b\x90\x90", 0x20, archinfo.ArchAMD64()) + b = pyvex.block.IRSB(b"\x90\x90\x0f\x0b\x90\x90", 0x20, pyvex.ARCH_AMD64) assert b.jumpkind == "Ijk_NoDecode" assert b.next.con.value == 0x22 assert b.size == 4 diff --git a/vex b/vex index 3e4d96a9..8f48c00e 160000 --- a/vex +++ b/vex @@ -1 +1 @@ -Subproject commit 3e4d96a97d9f0a85b128cec82b8910acba83f143 +Subproject commit 8f48c00eadbb31d379b829c01792a9c4a21636d4