FastVDMA Wishbone configuration

[kabrodzki]

I presume that to write the migen wrapper for the fastvdma we need to make it use the same internal bus as the LiteX - Wishbone. Even though the original code is really well-written there is no documentation whatsoever on connecting it to the Wishbone bus.
I had no problems with the Verilog generation for the default AXI4, but I have truly no idea how to configure it for Wishbone

As @rw1nkler suggested here we can use the LiteX module to translate between the AXI and Wishbone, but creating wrapper on top of a wrapper is never a good idea.

I wasn't quite sure where to create this issue, but let's keep everything in one place for now.

[piotr-binkowski]

Currently changing bus interface from AXI4 to Wishbone requires modifications to DMATop, but once you know where to look its not that hard 🙂
You need to:

1. Replace AXI4Lite interface with WishboneSlave
2. Replace AXI4LiteCSR frontend with WishboneCSR

With this it should be possible to attach CSRs to the WIshbone bus inside LiteX.

If you also want to modify either reader or writer part then you will need to replace its interface with WishboneMaster, replace its frontend with appropriate WishboneClassic* frontend and then adjust the configuration ie. Wishbone has no 4K barrier and no maximum burst length

[kabrodzki]

Thanks, I had done what you suggested before, but couldn't figure out why I'm getting exception

[error] (run-main-0) chisel3.internal.ChiselException: Connection between left (DMAController.Bus.WishboneSlave@118) a
nd source (DMAController.Bus.WishboneSlave@91) failed @.err_o: Both Left and Right are drivers

Removing Flipped actually helped. I am going to open a pull request on our fork

[piotr-binkowski]

Sorry, I forgot to mention that Wishbone interfaces have associated direction while AXI ones are bidirectional but require Flipped in some cases