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LiteX normally uses Wishbone bus. The CPU system in Zynq uses AXI to communicate them both you need to add an Wishbone <-> AXI bridge to the design.
This one is quite simple and can be easily integrated: https://github.com/wallento/wb2axi/blob/master/src/wb2axi.sv
The text was updated successfully, but these errors were encountered:
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LiteX normally uses Wishbone bus. The CPU system in Zynq uses AXI to communicate them both you need to add an Wishbone <-> AXI bridge to the design.
This one is quite simple and can be easily integrated: https://github.com/wallento/wb2axi/blob/master/src/wb2axi.sv
The text was updated successfully, but these errors were encountered: