From 9348cebeff5150d3bef3d96e79502c5429666c99 Mon Sep 17 00:00:00 2001 From: Wiktoria Kuna Date: Thu, 28 Nov 2024 17:16:23 +0100 Subject: [PATCH] Add gtkw templates for AXI4LiteCSR Internal-tag: [#69079] Signed-off-by: Wiktoria Kuna --- csr-bus.gtkw | 82 ++++++++++++++++++++++++++ top-level.gtkw | 152 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 234 insertions(+) create mode 100644 csr-bus.gtkw create mode 100644 top-level.gtkw diff --git a/csr-bus.gtkw b/csr-bus.gtkw new file mode 100644 index 0000000..cd2c401 --- /dev/null +++ b/csr-bus.gtkw @@ -0,0 +1,82 @@ +[*] +[*] GTKWave Analyzer v3.3.118 (w)1999-2023 BSI +[*] Thu Nov 28 13:33:09 2024 +[*] +[dumpfile] "/home/wkuna/work/wust-28-11-24/fastvdma/pre_run/ControllerSpec_should_perform_2D_MM2MM_transfer_with_stride_mem_to_mem/DMATopAXI_AXIL_AXI.vcd" +[dumpfile_mtime] "Thu Nov 28 12:38:23 2024" +[dumpfile_size] 56506227 +[savefile] "/home/wkuna/work/wust-28-11-24/fastvdma/csr-bus.gtkw" +[timestart] 0 +[size] 1920 1001 +[pos] -1 -1 +*-6.600000 217 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] DMATopAXI_AXIL_AXI. +[sst_width] 284 +[signals_width] 308 +[sst_expanded] 1 +[sst_vpaned_height] 282 +@28 +DMATopAXI_AXIL_AXI.csrFrontend.clock +DMATopAXI_AXIL_AXI.csrFrontend.reset +@200 +-I/O +@22 +DMATopAXI_AXIL_AXI.csrFrontend.io_bus_addr[3:0] +DMATopAXI_AXIL_AXI.csrFrontend.io_bus_dataIn[31:0] +DMATopAXI_AXIL_AXI.csrFrontend.io_bus_dataOut[31:0] +@28 +DMATopAXI_AXIL_AXI.csrFrontend.io_bus_read +DMATopAXI_AXIL_AXI.csrFrontend.io_bus_write +@200 +- +@22 +DMATopAXI_AXIL_AXI.csrFrontend.io_ctl_ar_araddr[31:0] +@28 +DMATopAXI_AXIL_AXI.csrFrontend.io_ctl_ar_arready +DMATopAXI_AXIL_AXI.csrFrontend.io_ctl_ar_arvalid +@200 +- +@22 +DMATopAXI_AXIL_AXI.csrFrontend.io_ctl_r_rdata[31:0] +@28 +DMATopAXI_AXIL_AXI.csrFrontend.io_ctl_r_rready +DMATopAXI_AXIL_AXI.csrFrontend.io_ctl_r_rvalid +DMATopAXI_AXIL_AXI.csrFrontend.io_ctl_r_rresp[1:0] +@200 +- +@22 +DMATopAXI_AXIL_AXI.csrFrontend.io_ctl_aw_awaddr[31:0] +@28 +DMATopAXI_AXIL_AXI.csrFrontend.io_ctl_aw_awready +DMATopAXI_AXIL_AXI.csrFrontend.io_ctl_aw_awvalid +@200 +- +@22 +DMATopAXI_AXIL_AXI.csrFrontend.io_ctl_w_wdata[31:0] +@28 +DMATopAXI_AXIL_AXI.csrFrontend.io_ctl_w_wready +DMATopAXI_AXIL_AXI.csrFrontend.io_ctl_w_wvalid +@200 +- +@28 +DMATopAXI_AXIL_AXI.csrFrontend.io_ctl_b_bready +DMATopAXI_AXIL_AXI.csrFrontend.io_ctl_b_bresp[1:0] +DMATopAXI_AXIL_AXI.csrFrontend.io_ctl_b_bvalid +@200 +-INSIDE-MODULE LOGIC +@28 +DMATopAXI_AXIL_AXI.csrFrontend.state[2:0] +@200 +- +@22 +DMATopAXI_AXIL_AXI.csrFrontend.addr[31:0] +@28 +DMATopAXI_AXIL_AXI.csrFrontend.arready +DMATopAXI_AXIL_AXI.csrFrontend.awready +DMATopAXI_AXIL_AXI.csrFrontend.wready +DMATopAXI_AXIL_AXI.csrFrontend.bresp[1:0] +DMATopAXI_AXIL_AXI.csrFrontend.bvalid +DMATopAXI_AXIL_AXI.csrFrontend.rresp[1:0] +DMATopAXI_AXIL_AXI.csrFrontend.rvalid +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/top-level.gtkw b/top-level.gtkw new file mode 100644 index 0000000..3b7d5ce --- /dev/null +++ b/top-level.gtkw @@ -0,0 +1,152 @@ +[*] +[*] GTKWave Analyzer v3.3.118 (w)1999-2023 BSI +[*] Thu Nov 28 13:29:23 2024 +[*] +[dumpfile] "/home/wkuna/work/wust-28-11-24/fastvdma/pre_run/ControllerSpec_should_perform_2D_MM2MM_transfer_with_stride_mem_to_mem/DMATopAXI_AXIL_AXI.vcd" +[dumpfile_mtime] "Thu Nov 28 12:38:23 2024" +[dumpfile_size] 56506227 +[savefile] "/home/wkuna/work/wust-28-11-24/fastvdma/wust-28-11-24.gtkw" +[timestart] 0 +[size] 1920 1001 +[pos] -50 -50 +*-18.000000 910000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] DMATopAXI_AXIL_AXI. +[sst_width] 284 +[signals_width] 334 +[sst_expanded] 1 +[sst_vpaned_height] 282 +@28 +DMATopAXI_AXIL_AXI.clock +DMATopAXI_AXIL_AXI.reset +DMATopAXI_AXIL_AXI.io_irq_readerDone +DMATopAXI_AXIL_AXI.io_irq_writerDone +@200 +- +-CONTROL BUS +@22 +DMATopAXI_AXIL_AXI.io_control_ar_araddr[31:0] +@28 +DMATopAXI_AXIL_AXI.io_control_ar_arready +DMATopAXI_AXIL_AXI.io_control_ar_arvalid +@200 +- +@c00022 +DMATopAXI_AXIL_AXI.io_control_r_rdata[31:0] +@28 +(0)DMATopAXI_AXIL_AXI.io_control_r_rdata[31:0] +(1)DMATopAXI_AXIL_AXI.io_control_r_rdata[31:0] +(2)DMATopAXI_AXIL_AXI.io_control_r_rdata[31:0] +(3)DMATopAXI_AXIL_AXI.io_control_r_rdata[31:0] +(4)DMATopAXI_AXIL_AXI.io_control_r_rdata[31:0] +(5)DMATopAXI_AXIL_AXI.io_control_r_rdata[31:0] +(6)DMATopAXI_AXIL_AXI.io_control_r_rdata[31:0] +(7)DMATopAXI_AXIL_AXI.io_control_r_rdata[31:0] +(8)DMATopAXI_AXIL_AXI.io_control_r_rdata[31:0] +(9)DMATopAXI_AXIL_AXI.io_control_r_rdata[31:0] +(10)DMATopAXI_AXIL_AXI.io_control_r_rdata[31:0] +(11)DMATopAXI_AXIL_AXI.io_control_r_rdata[31:0] +(12)DMATopAXI_AXIL_AXI.io_control_r_rdata[31:0] +(13)DMATopAXI_AXIL_AXI.io_control_r_rdata[31:0] +(14)DMATopAXI_AXIL_AXI.io_control_r_rdata[31:0] +(15)DMATopAXI_AXIL_AXI.io_control_r_rdata[31:0] +(16)DMATopAXI_AXIL_AXI.io_control_r_rdata[31:0] +(17)DMATopAXI_AXIL_AXI.io_control_r_rdata[31:0] +(18)DMATopAXI_AXIL_AXI.io_control_r_rdata[31:0] +(19)DMATopAXI_AXIL_AXI.io_control_r_rdata[31:0] +(20)DMATopAXI_AXIL_AXI.io_control_r_rdata[31:0] +(21)DMATopAXI_AXIL_AXI.io_control_r_rdata[31:0] +(22)DMATopAXI_AXIL_AXI.io_control_r_rdata[31:0] +(23)DMATopAXI_AXIL_AXI.io_control_r_rdata[31:0] +(24)DMATopAXI_AXIL_AXI.io_control_r_rdata[31:0] +(25)DMATopAXI_AXIL_AXI.io_control_r_rdata[31:0] +(26)DMATopAXI_AXIL_AXI.io_control_r_rdata[31:0] +(27)DMATopAXI_AXIL_AXI.io_control_r_rdata[31:0] +(28)DMATopAXI_AXIL_AXI.io_control_r_rdata[31:0] +(29)DMATopAXI_AXIL_AXI.io_control_r_rdata[31:0] +(30)DMATopAXI_AXIL_AXI.io_control_r_rdata[31:0] +(31)DMATopAXI_AXIL_AXI.io_control_r_rdata[31:0] +@1401200 +-group_end +@28 +DMATopAXI_AXIL_AXI.io_control_r_rready +DMATopAXI_AXIL_AXI.io_control_r_rvalid +DMATopAXI_AXIL_AXI.io_control_r_rresp[1:0] +@200 +- +@22 +DMATopAXI_AXIL_AXI.io_control_aw_awaddr[31:0] +@28 +DMATopAXI_AXIL_AXI.io_control_aw_awready +DMATopAXI_AXIL_AXI.io_control_aw_awvalid +@200 +- +@22 +DMATopAXI_AXIL_AXI.io_control_w_wdata[31:0] +@28 +DMATopAXI_AXIL_AXI.io_control_w_wready +DMATopAXI_AXIL_AXI.io_control_w_wvalid +@22 +DMATopAXI_AXIL_AXI.io_control_w_wstrb[3:0] +@200 +- +@28 +DMATopAXI_AXIL_AXI.io_control_b_bready +DMATopAXI_AXIL_AXI.io_control_b_bvalid +DMATopAXI_AXIL_AXI.io_control_b_bresp[1:0] +@200 +- +-READ BUS +@22 +DMATopAXI_AXIL_AXI.io_read_ar_araddr[31:0] +@28 +DMATopAXI_AXIL_AXI.io_read_ar_arready +DMATopAXI_AXIL_AXI.io_read_ar_arvalid +DMATopAXI_AXIL_AXI.io_read_ar_arburst[1:0] +@22 +DMATopAXI_AXIL_AXI.io_read_ar_arlen[7:0] +@28 +DMATopAXI_AXIL_AXI.io_read_ar_arsize[2:0] +@200 +- +@22 +DMATopAXI_AXIL_AXI.io_read_r_rdata[31:0] +@28 +DMATopAXI_AXIL_AXI.io_read_r_rready +DMATopAXI_AXIL_AXI.io_read_r_rvalid +DMATopAXI_AXIL_AXI.io_read_r_rlast +DMATopAXI_AXIL_AXI.io_read_r_rresp[1:0] +@200 +- +-WRITE BUS +@22 +DMATopAXI_AXIL_AXI.io_write_aw_awaddr[31:0] +@28 +DMATopAXI_AXIL_AXI.io_write_aw_awready +DMATopAXI_AXIL_AXI.io_write_aw_awvalid +DMATopAXI_AXIL_AXI.io_write_aw_awburst[1:0] +@22 +DMATopAXI_AXIL_AXI.io_write_aw_awlen[7:0] +@28 +DMATopAXI_AXIL_AXI.io_write_aw_awsize[2:0] +@200 +- +@22 +DMATopAXI_AXIL_AXI.io_write_w_wdata[31:0] +@28 +DMATopAXI_AXIL_AXI.io_write_w_wready +DMATopAXI_AXIL_AXI.io_write_w_wvalid +DMATopAXI_AXIL_AXI.io_write_w_wlast +@22 +DMATopAXI_AXIL_AXI.io_write_w_wstrb[3:0] +@200 +- +@28 +DMATopAXI_AXIL_AXI.io_write_b_bready +@29 +DMATopAXI_AXIL_AXI.io_write_b_bvalid +@28 +DMATopAXI_AXIL_AXI.io_write_b_bresp[1:0] +@200 +- +[pattern_trace] 1 +[pattern_trace] 0