From cb97634a5ddbf5a2e16a0230705c62ec2e70f1be Mon Sep 17 00:00:00 2001 From: Michal Czyz Date: Thu, 9 Nov 2023 14:07:27 +0100 Subject: [PATCH] Remove typos in RegisterMap Signed-off-by: Michal Czyz --- docs/RegisterMap.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/docs/RegisterMap.md b/docs/RegisterMap.md index ad81b0a..eec2cdb 100644 --- a/docs/RegisterMap.md +++ b/docs/RegisterMap.md @@ -8,7 +8,7 @@ Current register layout is shown in the table below: |--------|----------------------------| |`0x00` |[Control register](control-register-0x00) | |`0x04` |[Status register](status-register-0x04) | -|`0x08` |[Interrupt mask regiser](interrupt-mask-register-0x08) | +|`0x08` |[Interrupt mask register](interrupt-mask-register-0x08) | |`0x0c` |[Interrupt status register](interrupt-status-register-0x0c) | |`0x10` |[Reader start address](reader-start-address-0x10) | |`0x14` |[Reader line length](reader-line-length-0x14) | @@ -62,8 +62,8 @@ Current register layout is shown in the table below: |Bit |Name |Description | |----|-----------------|--------------------------------------------------------------------------------| -|0 |Writer interrupt |Reads as `1` if writer interrupt has occured, write `1` to clear that interrupt | -|1 |Reader interrupt |Reads as `1` if reader interrupt has occured, write `1` to clear that interrupt | +|0 |Writer interrupt |Reads as `1` if writer interrupt has occurred, write `1` to clear that interrupt | +|1 |Reader interrupt |Reads as `1` if reader interrupt has occurred, write `1` to clear that interrupt | |2-31|- |Unused | --- @@ -146,4 +146,4 @@ Current register layout is shown in the table below: --- -You can also check [WorkerCSRWrapper](https://github.com/antmicro/fastvdma/blob/main/src/main/scala/DMAController/Worker/WorkerCSRWrapper.scala) for the implementation details on how the CSRs are attached to the DMA logic (`io.csr(0)` refers to `0x00`, `io.csr(1)` to `0x04` and so on). \ No newline at end of file +You can also check [WorkerCSRWrapper](https://github.com/antmicro/fastvdma/blob/main/src/main/scala/DMAController/Worker/WorkerCSRWrapper.scala) for the implementation details on how the CSRs are attached to the DMA logic (`io.csr(0)` refers to `0x00`, `io.csr(1)` to `0x04` and so on).