From e816afacb310198e66ee176920230b5647ab6fe5 Mon Sep 17 00:00:00 2001 From: Maciej Dudek Date: Fri, 8 Nov 2024 17:35:17 +0100 Subject: [PATCH] Add support for BANK_ROW_COL DRAM accessing Signed-off-by: Maciej Dudek --- requirements-dev.txt | 4 ---- requirements.txt | 1 + rowhammer_tester/targets/common.py | 30 ++++++++++++++++++++++++++---- third_party/litedram | 2 +- third_party/litex | 2 +- third_party/verilator | 2 +- 6 files changed, 30 insertions(+), 11 deletions(-) delete mode 100644 requirements-dev.txt diff --git a/requirements-dev.txt b/requirements-dev.txt deleted file mode 100644 index 0a7767026..000000000 --- a/requirements-dev.txt +++ /dev/null @@ -1,4 +0,0 @@ -ipython -ipdb -matplotlib -pyqt5 diff --git a/requirements.txt b/requirements.txt index d0be1179b..1e7d8b690 100644 --- a/requirements.txt +++ b/requirements.txt @@ -24,4 +24,5 @@ wheel == 0.41.2 pyvcd == 0.4.0 matplotlib == 3.7.3 ninja == 1.11.1 +parameterized == 0.9.0 diff --git a/rowhammer_tester/targets/common.py b/rowhammer_tester/targets/common.py index d916509d7..311678812 100644 --- a/rowhammer_tester/targets/common.py +++ b/rowhammer_tester/targets/common.py @@ -206,7 +206,7 @@ def __init__(self, *, args, sys_clk_freq, module = module, settings = phy_settings, clk_freq = sys_clk_freq, - verbosity = 3, + verbosity = 0, ) else: # hardware self.submodules.ddrphy = self.get_ddrphy() @@ -225,6 +225,7 @@ def __init__(self): controller_settings.with_refresh = self.controller_settings.refresh.storage controller_settings.refresh_cls = SyncableRefresher controller_settings.cmd_buffer_buffered = True + controller_settings.address_mapping = args.address_mapping assert self.ddrphy.settings.memtype == module.memtype, \ 'Wrong DRAM module type: {} vs {}'.format(self.ddrphy.settings.memtype, module.memtype) @@ -238,6 +239,9 @@ def __init__(self): controller_settings = controller_settings, with_bist = not args.no_sdram_hw_test ) + if args.sim and args.trace_dram_phy_dfi: + for sig, _ in self.sdram.dfii.master.iter_flat(): + sig.attr.add("trace") if controller_settings.phy.memtype == "DDR5": prefixes = [""] if not controller_settings.phy.with_sub_channels else ["A_", "B_"] @@ -296,8 +300,13 @@ def __init__(self): self.logger.info('{}: Length: {}, Data Width: {}-bit, Address width: {}-bit'.format( colorer('Reader BIST pattern'), colorer(pattern_length), colorer(pattern_data_width), colorer(32))) - assert controller_settings.address_mapping == 'ROW_BANK_COL' - row_offset = controller_settings.geom.bankbits + controller_settings.geom.colbits + if controller_settings.address_mapping == 'ROW_BANK_COL': + row_offset = controller_settings.geom.bankbits + controller_settings.geom.colbits + elif controller_settings.address_mapping == 'BANK_ROW_COL': + row_offset = controller_settings.geom.colbits + else: + assert False, f"Unknown address_mapping: {controller_settings.address_mapping}" + inversion_kwargs = dict( rowbits = int(self.args.bist_inversion_rowbits, 0), row_shift = row_offset - self.sdram.controller.interface.address_align, @@ -440,10 +449,20 @@ def _add_common(self, *, sys_clk_freq, module): self.add(g, "--docs", action="store_true", help="Generate documentation") self.add(g, "--sim", action="store_true", help="Build and run in simulation mode") + # Trace args + g = self.add_argument_group(title="Sim tracing", + description="Select the parts of the the design to be traced during the simulation." + "Selecting any option will disable tracing of all other signals.") + self.add(g, "--trace-dram-phy-dfi", action="store_true", help="Trace communication to and from PHY over DFI") + # Target args g = self.add_argument_group(title="Row Hammer tester") self.add(g, "--sys-clk-freq", default=sys_clk_freq, help="System clock frequency") self.add(g, "--rw-bios-mem", action="store_true", help="(debug) Make BIOS memory writable") + self.add(g, "--address-mapping", + default="ROW_BANK_COL", + help="Selects linear to DRAM address translation.\n" + "Available options are: ROW_BANK_COL, BANK_ROW_COL.") self.add(g, "--module", default=module, help="DRAM module") self.add(g, "--from-spd", required=False, help="Use DRAM module data from given file. Overwrites --module") self.add(g, "--speedgrade", default=None, help="DRAM module speedgrade, default value depends on module") @@ -521,9 +540,12 @@ def get_builder_kwargs(args, target_name): def get_sim_kwargs(args, interface='litex-sim'): sim_config = SimConfig() sim_config.add_clocker("sys_clk", freq_hz=int(float(args.sys_clk_freq))) + tun_ip_addr = args.ip_address.split(".") + tun_ip_addr[-1] = "1" if tun_ip_addr[-1] != "1" else "2" + tun_ip_addr = ".".join(tun_ip_addr) sim_config.add_module("ethernet", "eth", args={ "interface": interface, - "ip": args.ip_address, + "ip": tun_ip_addr, }) return dict(sim_config=sim_config, trace=True, trace_fst=True) diff --git a/third_party/litedram b/third_party/litedram index ca1c30eed..2e1617ea3 160000 --- a/third_party/litedram +++ b/third_party/litedram @@ -1 +1 @@ -Subproject commit ca1c30eedd31ef86191421bf6c48355d3122bf43 +Subproject commit 2e1617ea356bd15cb11093d97d017f9e79332c10 diff --git a/third_party/litex b/third_party/litex index cd23335a7..01943ec83 160000 --- a/third_party/litex +++ b/third_party/litex @@ -1 +1 @@ -Subproject commit cd23335a76b649c0c7bd8d97a3fd4dcb203470ad +Subproject commit 01943ec83ae5539d09e337b78c7cbe3e21fce810 diff --git a/third_party/verilator b/third_party/verilator index 191c71ede..2cb1a8de7 160000 --- a/third_party/verilator +++ b/third_party/verilator @@ -1 +1 @@ -Subproject commit 191c71edead666091aaabde6b0941e9134b8a451 +Subproject commit 2cb1a8de73a1be7ee010aa63fe1de606c4a82bf6