DRAM Sequence Control

[notepractice]

I want to run Row Hammer attack tests after changing the values of Mode Registers for DRAM, not a default mode. That is, I want to set the address and control/command value to the desired value every cycle before Row Hammer attack.

I think this question might be related to 'litedram' module. It seems to be available by modifying the sequence and code in the 'sdram_init.py' and 'utils.py' files you provided, but the delay value is added in 'utils.py' file when 'sdram_software_control' mode is on (e.g. 'time.sleep(0.01 + delay * 1e-5') )

Can I set the address and control/command value every cycle?
If so, can the control (dfii_control) and command (dfii_pi0_command) value be set simultaneously at the same cycle?

Thank you for your help.