From 46ca6dfb5f0783d68cd738501a26a1a9455ff74e Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 10 Jan 2025 16:21:53 +0700 Subject: [PATCH] AMDGPU: Add disjoint to or produced from lowering vector ops (#122424) --- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 4a3944358244..529d9ba17d4f 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -7458,7 +7458,8 @@ SDValue SITargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op, DAG.getNode(ISD::AND, SL, IntVT, DAG.getNOT(SL, BFM, IntVT), BCVec); // 4. Get (2) and (3) ORed into the target vector. - SDValue BFI = DAG.getNode(ISD::OR, SL, IntVT, LHS, RHS); + SDValue BFI = + DAG.getNode(ISD::OR, SL, IntVT, LHS, RHS, SDNodeFlags::Disjoint); return DAG.getNode(ISD::BITCAST, SL, VecVT, BFI); } @@ -7666,7 +7667,8 @@ SDValue SITargetLowering::lowerBUILD_VECTOR(SDValue Op, Lo = DAG.getNode(ISD::BITCAST, SL, MVT::i16, Lo); Lo = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Lo); - SDValue Or = DAG.getNode(ISD::OR, SL, MVT::i32, Lo, ShlHi); + SDValue Or = + DAG.getNode(ISD::OR, SL, MVT::i32, Lo, ShlHi, SDNodeFlags::Disjoint); return DAG.getNode(ISD::BITCAST, SL, VT, Or); }