{"payload":{"header_redesign_enabled":false,"results":[{"id":"161163450","archived":false,"color":"#f34b7d","followers":95,"has_funding_file":false,"hl_name":"asyncvlsi/act","hl_trunc_description":"ACT hardware description language and core tools.","language":"C++","mirror":false,"owned_by_organization":true,"public":true,"repo":{"repository":{"id":161163450,"name":"act","owner_id":29312564,"owner_login":"asyncvlsi","updated_at":"2024-07-12T20:24:43.983Z","has_issues":true}},"sponsorable":false,"topics":["language","eda","circuit-simulator","cad","dataflow","chp","dataflow-programming","prs","hdl","vlsi","hardware-description-language","production-rules","design-automation","asynchronous-circuits","vlsi-cad","asynchronous-vlsi","communicating-hardware-processes"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":59,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Aasyncvlsi%252Fact%2B%2Blanguage%253AC%252B%252B","metadata":null,"csrf_tokens":{"/asyncvlsi/act/star":{"post":"dCf2LFVWUVoGTvGTG3D34PX3ogbe8-0IPjVKWtD1zf3rrEyJPdKxr8Jc82_bEptgv6Vo4nG8Nhx_vbJ6uCGS0g"},"/asyncvlsi/act/unstar":{"post":"3UsvhMHqjZG7_ZR4cMxIt5ITKFzUYoRzNumX1fuJ4NNOSyfq0atGT6I2wO1QZUfn-tqU4K6lRi5xFtZgpDeicg"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"JmhEV7NEydlEpu6ejEw-po6A_H1fHq4VH3WnJpOCYdYs309Cl75zlyhnWW76xzezwzhvH0bxO4CsrhSOUPH4Ww"}}},"title":"Repository search results"}