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si5386-registers-default.h
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si5386-registers-default.h
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/*
* Si5386A Rev E Configuration Register Export Header File
*
* This file represents a series of Silicon Labs Si5386A Rev E
* register writes that can be performed to load a single configuration
* on a device. It was created by a Silicon Labs ClockBuilder Pro
* export tool.
*
* Part: Si5386A Rev E
* Design ID: V1
* Includes Pre/Post Download Control Register Writes: Yes
* Created By: ClockBuilder Pro v2.39 [2019-12-11]
* Timestamp: 2020-02-15 18:15:34 GMT+08:00
*
* A complete design report corresponding to this export is included at the end
* of this header file.
*
*/
#ifndef SI5386A_REVE_REG_CONFIG_HEADER
#define SI5386A_REVE_REG_CONFIG_HEADER
#define SI5386A_REVE_REG_CONFIG_NUM_REGS 565
typedef struct
{
unsigned int address; /* 16-bit register address */
unsigned char value; /* 8-bit register data */
} si5386a_reve_register_t;
si5386a_reve_register_t const si5386a_reve_registers[SI5386A_REVE_REG_CONFIG_NUM_REGS] =
{
/* Start configuration preamble */
{ 0x0B24, 0xC0 },
{ 0x0B25, 0x00 },
{ 0x0540, 0x01 },
/* End configuration preamble */
/* Delay 625 msec */
/* Delay is worst case time for device to complete any calibration */
/* that is running due to device state change previous to this script */
/* being processed. */
/* Start configuration registers */
{ 0x0006, 0x00 },
{ 0x0007, 0x00 },
{ 0x0008, 0x00 },
{ 0x000B, 0x68 },
{ 0x0016, 0x02 },
{ 0x0017, 0xDC },
{ 0x0018, 0xDD },
{ 0x0019, 0xDD },
{ 0x001A, 0xDF },
{ 0x002B, 0x02 },
{ 0x002C, 0x02 },
{ 0x002D, 0x00 },
{ 0x002E, 0x00 },
{ 0x002F, 0x00 },
{ 0x0030, 0x3C },
{ 0x0031, 0x00 },
{ 0x0032, 0x00 },
{ 0x0033, 0x00 },
{ 0x0034, 0x00 },
{ 0x0035, 0x00 },
{ 0x0036, 0x00 },
{ 0x0037, 0x00 },
{ 0x0038, 0x02 },
{ 0x0039, 0x00 },
{ 0x003A, 0x00 },
{ 0x003B, 0x00 },
{ 0x003C, 0x00 },
{ 0x003D, 0x00 },
{ 0x003E, 0x20 },
{ 0x003F, 0x22 },
{ 0x0040, 0x04 },
{ 0x0041, 0x00 },
{ 0x0042, 0x0E },
{ 0x0043, 0x00 },
{ 0x0044, 0x00 },
{ 0x0045, 0x0C },
{ 0x0046, 0x00 },
{ 0x0047, 0x32 },
{ 0x0048, 0x00 },
{ 0x0049, 0x00 },
{ 0x004A, 0x00 },
{ 0x004B, 0x32 },
{ 0x004C, 0x00 },
{ 0x004D, 0x00 },
{ 0x004E, 0x50 },
{ 0x004F, 0x00 },
{ 0x0050, 0x0F },
{ 0x0051, 0x00 },
{ 0x0052, 0x03 },
{ 0x0053, 0x00 },
{ 0x0054, 0x00 },
{ 0x0055, 0x00 },
{ 0x0056, 0x03 },
{ 0x0057, 0x00 },
{ 0x0058, 0x00 },
{ 0x0059, 0x04 },
{ 0x005A, 0x00 },
{ 0x005B, 0x00 },
{ 0x005C, 0x00 },
{ 0x005D, 0x00 },
{ 0x005E, 0x67 },
{ 0x005F, 0x45 },
{ 0x0060, 0x23 },
{ 0x0061, 0x01 },
{ 0x0062, 0x00 },
{ 0x0063, 0x00 },
{ 0x0064, 0x00 },
{ 0x0065, 0x00 },
{ 0x0066, 0x00 },
{ 0x0067, 0x00 },
{ 0x0068, 0x00 },
{ 0x0069, 0x00 },
{ 0x0092, 0x02 },
{ 0x0093, 0xA0 },
{ 0x0095, 0x00 },
{ 0x0096, 0x80 },
{ 0x0098, 0x60 },
{ 0x009A, 0x02 },
{ 0x009B, 0x60 },
{ 0x009D, 0x08 },
{ 0x009E, 0x40 },
{ 0x00A0, 0x20 },
{ 0x00A2, 0x00 },
{ 0x00A9, 0xA1 },
{ 0x00AA, 0x61 },
{ 0x00AB, 0x00 },
{ 0x00AC, 0x00 },
{ 0x00E5, 0x00 },
{ 0x00EA, 0x0A },
{ 0x00EB, 0x60 },
{ 0x00EC, 0x00 },
{ 0x00ED, 0x00 },
{ 0x0102, 0x01 },
{ 0x0103, 0x02 },
{ 0x0104, 0x09 },
{ 0x0105, 0x3B },
{ 0x0106, 0x29 },
{ 0x0108, 0x02 },
{ 0x0109, 0x09 },
{ 0x010A, 0x3B },
{ 0x010B, 0x29 },
{ 0x010D, 0x01 },
{ 0x010E, 0x09 },
{ 0x010F, 0x3B },
{ 0x0110, 0x28 },
{ 0x0112, 0x01 },
{ 0x0113, 0x09 },
{ 0x0114, 0x3B },
{ 0x0115, 0x28 },
{ 0x0117, 0x01 },
{ 0x0118, 0x09 },
{ 0x0119, 0x3B },
{ 0x011A, 0x28 },
{ 0x011C, 0x01 },
{ 0x011D, 0x09 },
{ 0x011E, 0x3B },
{ 0x011F, 0x28 },
{ 0x0121, 0x06 },
{ 0x0122, 0x09 },
{ 0x0123, 0x3B },
{ 0x0124, 0x28 },
{ 0x0126, 0x06 },
{ 0x0127, 0x09 },
{ 0x0128, 0x3B },
{ 0x0129, 0x28 },
{ 0x012B, 0x06 },
{ 0x012C, 0x09 },
{ 0x012D, 0x3B },
{ 0x012E, 0x28 },
{ 0x0130, 0x01 },
{ 0x0131, 0x09 },
{ 0x0132, 0x3B },
{ 0x0133, 0x28 },
{ 0x0135, 0x02 },
{ 0x0136, 0x09 },
{ 0x0137, 0x3B },
{ 0x0138, 0x29 },
{ 0x013A, 0x02 },
{ 0x013B, 0x09 },
{ 0x013C, 0x3B },
{ 0x013D, 0x29 },
{ 0x013F, 0x00 },
{ 0x0140, 0x00 },
{ 0x0141, 0x40 },
{ 0x0142, 0xFF },
{ 0x0208, 0x00 },
{ 0x0209, 0x00 },
{ 0x020A, 0x00 },
{ 0x020B, 0x00 },
{ 0x020C, 0x00 },
{ 0x020D, 0x00 },
{ 0x020E, 0x00 },
{ 0x020F, 0x00 },
{ 0x0210, 0x00 },
{ 0x0211, 0x00 },
{ 0x0212, 0x7B },
{ 0x0213, 0x00 },
{ 0x0214, 0x00 },
{ 0x0215, 0x00 },
{ 0x0216, 0x00 },
{ 0x0217, 0x00 },
{ 0x0218, 0x01 },
{ 0x0219, 0x00 },
{ 0x021A, 0x00 },
{ 0x021B, 0x00 },
{ 0x021C, 0x00 },
{ 0x021D, 0x00 },
{ 0x021E, 0x00 },
{ 0x021F, 0x00 },
{ 0x0220, 0x00 },
{ 0x0221, 0x00 },
{ 0x0222, 0x00 },
{ 0x0223, 0x00 },
{ 0x0224, 0x00 },
{ 0x0225, 0x00 },
{ 0x0226, 0x00 },
{ 0x0227, 0x00 },
{ 0x0228, 0x00 },
{ 0x0229, 0x00 },
{ 0x022A, 0x00 },
{ 0x022B, 0x00 },
{ 0x022C, 0x00 },
{ 0x022D, 0x00 },
{ 0x022E, 0x00 },
{ 0x022F, 0x00 },
{ 0x0231, 0x0B },
{ 0x0232, 0x0B },
{ 0x0233, 0x0B },
{ 0x0234, 0x0B },
{ 0x0235, 0x00 },
{ 0x0236, 0x00 },
{ 0x0237, 0x00 },
{ 0x0238, 0x00 },
{ 0x0239, 0x00 },
{ 0x023A, 0x01 },
{ 0x023B, 0x00 },
{ 0x023C, 0x00 },
{ 0x023D, 0x00 },
{ 0x023E, 0xF0 },
{ 0x0247, 0x01 },
{ 0x0248, 0x00 },
{ 0x0249, 0x00 },
{ 0x024A, 0x01 },
{ 0x024B, 0x00 },
{ 0x024C, 0x00 },
{ 0x024D, 0x00 },
{ 0x024E, 0x00 },
{ 0x024F, 0x00 },
{ 0x0250, 0x00 },
{ 0x0251, 0x00 },
{ 0x0252, 0x00 },
{ 0x0253, 0x00 },
{ 0x0254, 0x00 },
{ 0x0255, 0x00 },
{ 0x0256, 0x00 },
{ 0x0257, 0x00 },
{ 0x0258, 0x00 },
{ 0x0259, 0x00 },
{ 0x025A, 0x00 },
{ 0x025B, 0x00 },
{ 0x025C, 0x00 },
{ 0x025D, 0x00 },
{ 0x025E, 0x00 },
{ 0x025F, 0x00 },
{ 0x0260, 0x00 },
{ 0x0261, 0x00 },
{ 0x0262, 0x00 },
{ 0x0263, 0x00 },
{ 0x0264, 0x00 },
{ 0x0265, 0x01 },
{ 0x0266, 0x00 },
{ 0x0267, 0x00 },
{ 0x0268, 0x01 },
{ 0x0269, 0x00 },
{ 0x026A, 0x00 },
{ 0x026B, 0x56 },
{ 0x026C, 0x31 },
{ 0x026D, 0x00 },
{ 0x026E, 0x00 },
{ 0x026F, 0x00 },
{ 0x0270, 0x00 },
{ 0x0271, 0x00 },
{ 0x0272, 0x00 },
{ 0x028A, 0x00 },
{ 0x028B, 0x00 },
{ 0x028C, 0x00 },
{ 0x028D, 0x00 },
{ 0x028E, 0x00 },
{ 0x028F, 0x00 },
{ 0x0290, 0x00 },
{ 0x0291, 0x00 },
{ 0x0292, 0x3F },
{ 0x0293, 0x2F },
{ 0x0294, 0xB0 },
{ 0x0296, 0x02 },
{ 0x0297, 0x02 },
{ 0x0299, 0x02 },
{ 0x029D, 0xFA },
{ 0x029E, 0x01 },
{ 0x029F, 0x00 },
{ 0x02A9, 0xCC },
{ 0x02AA, 0x04 },
{ 0x02AB, 0x00 },
{ 0x02B7, 0xFF },
{ 0x02BC, 0x00 },
{ 0x0302, 0x00 },
{ 0x0303, 0x00 },
{ 0x0304, 0x00 },
{ 0x0305, 0x00 },
{ 0x0306, 0x0F },
{ 0x0307, 0x00 },
{ 0x0308, 0x00 },
{ 0x0309, 0x00 },
{ 0x030A, 0x00 },
{ 0x030B, 0x80 },
{ 0x030C, 0x00 },
{ 0x030D, 0x00 },
{ 0x030E, 0x00 },
{ 0x030F, 0x00 },
{ 0x0310, 0x00 },
{ 0x0311, 0x20 },
{ 0x0312, 0x01 },
{ 0x0313, 0x00 },
{ 0x0314, 0x00 },
{ 0x0315, 0x00 },
{ 0x0316, 0xC8 },
{ 0x0317, 0x00 },
{ 0x0318, 0x00 },
{ 0x0319, 0x00 },
{ 0x031A, 0x00 },
{ 0x031B, 0x00 },
{ 0x031C, 0x00 },
{ 0x031D, 0x00 },
{ 0x031E, 0x00 },
{ 0x031F, 0x00 },
{ 0x0320, 0x00 },
{ 0x0321, 0x00 },
{ 0x0322, 0x00 },
{ 0x0323, 0x00 },
{ 0x0324, 0x00 },
{ 0x0325, 0x00 },
{ 0x0326, 0x00 },
{ 0x0327, 0x00 },
{ 0x0328, 0x00 },
{ 0x0329, 0x00 },
{ 0x032A, 0x00 },
{ 0x032B, 0x00 },
{ 0x032C, 0x00 },
{ 0x032D, 0x00 },
{ 0x032E, 0x00 },
{ 0x032F, 0x00 },
{ 0x0330, 0x00 },
{ 0x0331, 0x00 },
{ 0x0332, 0x00 },
{ 0x0333, 0x00 },
{ 0x0334, 0x00 },
{ 0x0335, 0x00 },
{ 0x0336, 0x00 },
{ 0x0337, 0x00 },
{ 0x0338, 0x00 },
{ 0x0359, 0x00 },
{ 0x035A, 0x00 },
{ 0x035B, 0x00 },
{ 0x035C, 0x00 },
{ 0x035D, 0x00 },
{ 0x035E, 0x00 },
{ 0x035F, 0x00 },
{ 0x0360, 0x00 },
{ 0x0361, 0x00 },
{ 0x0362, 0x00 },
{ 0x0487, 0x00 },
{ 0x0508, 0x0E },
{ 0x0509, 0x1D },
{ 0x050A, 0x0C },
{ 0x050B, 0x0B },
{ 0x050C, 0x3F },
{ 0x050D, 0x0F },
{ 0x050E, 0x11 },
{ 0x050F, 0x25 },
{ 0x0510, 0x09 },
{ 0x0511, 0x08 },
{ 0x0512, 0x3F },
{ 0x0513, 0x0F },
{ 0x0515, 0x00 },
{ 0x0516, 0x00 },
{ 0x0517, 0x00 },
{ 0x0518, 0x00 },
{ 0x0519, 0xE2 },
{ 0x051A, 0x02 },
{ 0x051B, 0x00 },
{ 0x051C, 0x00 },
{ 0x051D, 0x00 },
{ 0x051E, 0x00 },
{ 0x051F, 0x80 },
{ 0x0521, 0x0B },
{ 0x052A, 0x03 },
{ 0x052B, 0x01 },
{ 0x052C, 0x87 },
{ 0x052D, 0x03 },
{ 0x052E, 0x19 },
{ 0x052F, 0x19 },
{ 0x0531, 0x00 },
{ 0x0532, 0x43 },
{ 0x0533, 0x03 },
{ 0x0534, 0x00 },
{ 0x0535, 0x00 },
{ 0x0536, 0x00 },
{ 0x0537, 0x00 },
{ 0x0538, 0x00 },
{ 0x0539, 0x00 },
{ 0x053A, 0x01 },
{ 0x053B, 0x03 },
{ 0x053C, 0x00 },
{ 0x053D, 0x04 },
{ 0x053E, 0x02 },
{ 0x0588, 0x07 },
{ 0x0589, 0x0D },
{ 0x058A, 0x00 },
{ 0x058B, 0x77 },
{ 0x058C, 0x56 },
{ 0x058D, 0x00 },
{ 0x059B, 0x7A },
{ 0x059C, 0x8C },
{ 0x059D, 0x0E },
{ 0x059E, 0x1F },
{ 0x059F, 0x0C },
{ 0x05A0, 0x0B },
{ 0x05A1, 0x3F },
{ 0x05A2, 0x0F },
{ 0x05A4, 0x08 },
{ 0x05A5, 0x00 },
{ 0x05A6, 0x03 },
{ 0x05AC, 0x09 },
{ 0x05AD, 0xE7 },
{ 0x05AE, 0x45 },
{ 0x05B1, 0xDD },
{ 0x05B2, 0x02 },
{ 0x0802, 0x35 },
{ 0x0803, 0x05 },
{ 0x0804, 0x00 },
{ 0x0805, 0x53 },
{ 0x0806, 0x0B },
{ 0x0807, 0x10 },
{ 0x0808, 0x00 },
{ 0x0809, 0x00 },
{ 0x080A, 0x00 },
{ 0x080B, 0x00 },
{ 0x080C, 0x00 },
{ 0x080D, 0x00 },
{ 0x080E, 0x00 },
{ 0x080F, 0x00 },
{ 0x0810, 0x00 },
{ 0x0811, 0x00 },
{ 0x0812, 0x00 },
{ 0x0813, 0x00 },
{ 0x0814, 0x00 },
{ 0x0815, 0x00 },
{ 0x0816, 0x00 },
{ 0x0817, 0x00 },
{ 0x0818, 0x00 },
{ 0x0819, 0x00 },
{ 0x081A, 0x00 },
{ 0x081B, 0x00 },
{ 0x081C, 0x00 },
{ 0x081D, 0x00 },
{ 0x081E, 0x00 },
{ 0x081F, 0x00 },
{ 0x0820, 0x00 },
{ 0x0821, 0x00 },
{ 0x0822, 0x00 },
{ 0x0823, 0x00 },
{ 0x0824, 0x00 },
{ 0x0825, 0x00 },
{ 0x0826, 0x00 },
{ 0x0827, 0x00 },
{ 0x0828, 0x00 },
{ 0x0829, 0x00 },
{ 0x082A, 0x00 },
{ 0x082B, 0x00 },
{ 0x082C, 0x00 },
{ 0x082D, 0x00 },
{ 0x082E, 0x00 },
{ 0x082F, 0x00 },
{ 0x0830, 0x00 },
{ 0x0831, 0x00 },
{ 0x0832, 0x00 },
{ 0x0833, 0x00 },
{ 0x0834, 0x00 },
{ 0x0835, 0x00 },
{ 0x0836, 0x00 },
{ 0x0837, 0x00 },
{ 0x0838, 0x00 },
{ 0x0839, 0x00 },
{ 0x083A, 0x00 },
{ 0x083B, 0x00 },
{ 0x083C, 0x00 },
{ 0x083D, 0x00 },
{ 0x083E, 0x00 },
{ 0x083F, 0x00 },
{ 0x0840, 0x00 },
{ 0x0841, 0x00 },
{ 0x0842, 0x00 },
{ 0x0843, 0x00 },
{ 0x0844, 0x00 },
{ 0x0845, 0x00 },
{ 0x0846, 0x00 },
{ 0x0847, 0x00 },
{ 0x0848, 0x00 },
{ 0x0849, 0x00 },
{ 0x084A, 0x00 },
{ 0x084B, 0x00 },
{ 0x084C, 0x00 },
{ 0x084D, 0x00 },
{ 0x084E, 0x00 },
{ 0x084F, 0x00 },
{ 0x0850, 0x00 },
{ 0x0851, 0x00 },
{ 0x0852, 0x00 },
{ 0x0853, 0x00 },
{ 0x0854, 0x00 },
{ 0x0855, 0x00 },
{ 0x0856, 0x00 },
{ 0x0857, 0x00 },
{ 0x0858, 0x00 },
{ 0x0859, 0x00 },
{ 0x085A, 0x00 },
{ 0x085B, 0x00 },
{ 0x085C, 0x00 },
{ 0x085D, 0x00 },
{ 0x085E, 0x00 },
{ 0x085F, 0x00 },
{ 0x0860, 0x00 },
{ 0x0861, 0x00 },
{ 0x090E, 0x03 },
{ 0x0943, 0x00 },
{ 0x0949, 0x02 },
{ 0x094A, 0x02 },
{ 0x094E, 0x49 },
{ 0x094F, 0xF2 },
{ 0x095E, 0x00 },
{ 0x0A02, 0x00 },
{ 0x0A03, 0x03 },
{ 0x0A04, 0x01 },
{ 0x0A05, 0x03 },
{ 0x0A14, 0x00 },
{ 0x0A1A, 0x00 },
{ 0x0A20, 0x00 },
{ 0x0A26, 0x00 },
{ 0x0A2C, 0x00 },
{ 0x0A38, 0x00 },
{ 0x0A39, 0x00 },
{ 0x0A3A, 0x00 },
{ 0x0A3C, 0x00 },
{ 0x0A3D, 0x00 },
{ 0x0A3E, 0x00 },
{ 0x0A40, 0x00 },
{ 0x0A41, 0x00 },
{ 0x0A42, 0x00 },
{ 0x0A44, 0x00 },
{ 0x0A45, 0x00 },
{ 0x0A46, 0x00 },
{ 0x0A48, 0x00 },
{ 0x0A49, 0x00 },
{ 0x0A4A, 0x00 },
{ 0x0A4C, 0x00 },
{ 0x0A4D, 0x00 },
{ 0x0A4E, 0x00 },
{ 0x0A4F, 0x00 },
{ 0x0A50, 0x00 },
{ 0x0A51, 0x00 },
{ 0x0A52, 0x00 },
{ 0x0A53, 0x00 },
{ 0x0A54, 0x00 },
{ 0x0A55, 0x00 },
{ 0x0A56, 0x00 },
{ 0x0A57, 0x00 },
{ 0x0A58, 0x00 },
{ 0x0A59, 0x00 },
{ 0x0A5A, 0x00 },
{ 0x0A5B, 0x00 },
{ 0x0A5C, 0x00 },
{ 0x0A5D, 0x00 },
{ 0x0A5E, 0x00 },
{ 0x0A5F, 0x00 },
{ 0x0B44, 0x2F },
{ 0x0B45, 0x00 },
{ 0x0B46, 0x00 },
{ 0x0B47, 0x0D },
{ 0x0B48, 0x0D },
{ 0x0B4A, 0x1C },
{ 0x0B53, 0x10 },
{ 0x0B57, 0xF0 },
{ 0x0B58, 0x00 },
{ 0x0C02, 0x03 },
{ 0x0C03, 0x02 },
{ 0x0C07, 0x01 },
{ 0x0C08, 0x01 },
/* End configuration registers */
/* Start configuration postamble */
{ 0x0514, 0x01 },
{ 0x001C, 0x01 },
{ 0x0540, 0x00 },
{ 0x0B24, 0xC3 },
{ 0x0B25, 0x02 },
/* End configuration postamble */
};
/*
* Design Report
*
* Overview
* ========
* Part: Si5386A Rev E
* Project File: C:\projects\5G\datasheet\clock\HUBÅäÖÃ\Si5386A-RevE-V1-Project.slabtimeproj
* Design ID: V1
* Created By: ClockBuilder Pro v2.39 [2019-12-11]
* Timestamp: 2020-02-15 18:15:34 GMT+08:00
*
* Design Rule Check
* =================
* Errors:
* - No errors
*
* Warnings:
* - No warnings
*
* Design
* ======
* Host Interface:
* I/O Power Supply: VDD (Core)
* SPI Mode: 4-Wire
* I2C Address Range: 104d to 107d / 0x68 to 0x6B (selected via A0/A1 pins)
*
* Reference:
* 54 MHz (XO - Oscillator)
*
* Inputs:
* IN0: Unused
* IN1: 245.76 MHz
* Standard Differential and Single-ended
* IN2: Unused
* IN3: Unused
*
* Outputs:
* OUT0A: 10 MHz
* Enabled, LVDS 2.5 V
* OUT0: 10 MHz
* Enabled, LVDS 2.5 V
* OUT1: Unused
* OUT2: Unused
* OUT3: Unused
* OUT4: Unused
* OUT5: 245.76 MHz
* Enabled, LVDS 2.5 V
* OUT6: 245.76 MHz
* Enabled, LVDS 2.5 V
* OUT7: 245.76 MHz
* Enabled, LVDS 2.5 V
* OUT8: Unused
* OUT9: 10 MHz
* Enabled, LVDS 2.5 V
* OUT9A: 10 MHz
* Enabled, LVDS 2.5 V
*
* Frequency Plan
* ==============
* Fvco = 14.7456 GHz
* Fpfd = 1.9980487804878048... MHz [ 1 + 1023/1025 MHz ]
* Fms0 = 491.52 MHz
* Fms1 = 40 MHz
*
* P dividers:
* P0 = Unused
* P1 = 123
* P2 = Unused
* P3 = Unused
* Pxaxb = 1
*
* MXAXB = 273.0666666666666666... [ 273 + 1/15 ]
* M = 1476
* N dividers:
* N0:
* Value: 30
* OUT5: 245.76 MHz [ 245 + 19/25 MHz ]
* OUT6: 245.76 MHz [ 245 + 19/25 MHz ]
* OUT7: 245.76 MHz [ 245 + 19/25 MHz ]
* N1:
* Value: 368.64
* OUT0A: 10 MHz
* OUT0: 10 MHz
* OUT9: 10 MHz
* OUT9A: 10 MHz
* N2:
* Unused
* N3:
* Unused
* N4:
* Unused
*
* R dividers:
* R0A = 4
* R0 = 4
* R1 = Unused
* R2 = Unused
* R3 = Unused
* R4 = Unused
* R5 = 2
* R6 = 2
* R7 = 2
* R8 = Unused
* R9 = 4
* R9A = 4
*
* Nominal Bandwidth:
* Desired: 100.000 Hz
* Actual: 90.265 Hz
* Coefficients:
* BW0: 14
* BW1: 29
* BW2: 12
* BW3: 11
* BW4: 63
* BW5: 15
* Fastlock Bandwidth:
* Desired: 1.000 kHz
* Actual: 722.858 Hz
* Coefficients:
* BW0: 17
* BW1: 37
* BW2: 9
* BW3: 8
* BW4: 63
* BW5: 15
* Holdover Bandwidth:
* N/A (Ramped Exit from Holdover)
*
* Dividers listed above show effective values. These values are translated to register settings by ClockBuilder Pro. For the actual register values, see below. Refer to the Family Reference Manual for information on registers related to frequency plan.
*
* Hitless Input Switching Assistant
* =================================
* Assistant Disabled
*
* Output Skew Control
* ===================
* N0: 30
*
* OUT5 245.76 MHz
* Static O/O Skew Adjust: 0.000 ps
* Relative Static O/O Skew: 0 ps
* OUT6 245.76 MHz
* Static O/O Skew Adjust: 0.000 ps
* Relative Static O/O Skew: 0 ps
* OUT7 245.76 MHz
* Static O/O Skew Adjust: 0.000 ps
* Relative Static O/O Skew: 0 ps
*
* N0_DELAY: 0x0 0d (Twos compliment div 256)
* N0_IODELAY_STEP: 0x0 0d
* N0_IODELAY_COUNT: 0x0 0d
* N0_IODELAY_INC: 0x0
* N0_IODELAY_DEC: 0x0
*
* Desired Dynamic Skew Step: ¡À0.000 ps
* Actual Dynamic Skew Step: ¡À0 ps
* N0_PHASE_STEP: 0x0 0d
* N0_PHASE_COUNT: 0x0 0d
*
* Use N0_PHASE_INC and N0_PHASE_DEC to perform phase step.
*
* N1: 368.64
*
* OUT0A 10 MHz
* Static O/O Skew Adjust: 0.000 ps
* Relative Static O/O Skew: 0 ps
* OUT0 10 MHz
* Static O/O Skew Adjust: 0.000 ps
* Relative Static O/O Skew: 0 ps
* OUT9 10 MHz
* Static O/O Skew Adjust: 0.000 ps
* Relative Static O/O Skew: 0 ps
* OUT9A 10 MHz
* Static O/O Skew Adjust: 0.000 ps
* Relative Static O/O Skew: 0 ps
*
* N1_DELAY: 0x0 0d (Twos compliment div 256)
* N1_IODELAY_STEP: 0x0 0d
* N1_IODELAY_COUNT: 0x0 0d
* N1_IODELAY_INC: 0x0
* N1_IODELAY_DEC: 0x0
*
* Desired Dynamic Skew Step: ¡À0.000 ps
* Actual Dynamic Skew Step: ¡À0 ps
* N1_PHASE_STEP: 0x0 0d
* N1_PHASE_COUNT: 0x0 0d
*
* Use N1_PHASE_INC and N1_PHASE_DEC to perform phase step.
*
* N2 Not Used
*
* N3 Not Used
*
* N4 Not Used
*
* CBPro will, within device limits, align outputs to a common clock edge. The
* static offset value entered in CBPro is relative to this automatic alignment
* and is therefore labeled output-to-output offset.
*
* When aligning outputs, CBPro takes into account VCO frequency, input buffer
* mode, output format, assigned N divider, and R divider values. Due to the
* automatic alignment, static skew registers Nx_DELAY, Nx_IODELAY_STEP, and
* Nx_IODELAY_COUNT will normally be non-zero even when you have 0.0 output-to-
* output skew configured.
*
* Estimated Power & Junction Temperature
* ======================================
* VDD: 1.8 V
* Ta: 25 C
* Theta-JA: 22.0 ¡ãC/W (JEDEC Board with 0 m/s airflow)
*
* Condition On Chip Power Overall Power Ta Tj
* ------------------------------- ------------- ------------- ---- -----
* Typical Ta, Voltage, Current 916 mW 959 mW 25 C 45 C
* Worst-Case Ta, Voltage, Current 1.176 W 1.221 W 85 C 111 C
*
* ----------------------- -----------------------
* Typical Worst-Case
* ----------------------- -----------------------
* Voltage Current Power Voltage Current Power
* Frequency Format (V) (mA) (mW) (V) (mA) (mW)
* ---------- ------ ------- ------- ----- ------- ------- -----
* VDD 1.8 144 260 1.9 236 446
* VDDA 3.3 128 421 3.5 135 469
* VDDO0A 10 MHz LVDS 2.5 15 39 2.6 16 42
* VDDO0 10 MHz LVDS 2.5 15 39 2.6 16 42
* VDDO1 Unused
* VDDO2 Unused
* VDDO3 Unused
* VDDO4 Unused
* VDDO5 245.76 MHz LVDS 2.5 17 41 2.6 17 45
* VDDO6 245.76 MHz LVDS 2.5 17 41 2.6 17 45
* VDDO7 245.76 MHz LVDS 2.5 17 41 2.6 17 45
* VDDO8 Unused
* VDDO9 10 MHz LVDS 2.5 15 39 2.6 16 42
* VDDO9A 10 MHz LVDS 2.5 15 39 2.6 16 42
* ------- ------- ----- ------- ------- -----
* Total 383 959 Total 488 1,221
*
* Note:
*
* -Tj is junction temperature. Tj must be less than 125 ¡ãC (on Si5386 Revision E) for device to comply with datasheet specifications. Tj = Ta + Theta_JA*On_Chip_Power.
* -Overall power includes on-chip power dissipation and adds differential load power dissipation to estimate total power requirements.
* -Above are estimates only: power and temperature should be measured on your PCB.
* -Selection of appropriate Theta-JA is required for most accurate estimate. Ideally, select 'User Specified Theta-JA' and enter a Theta-JA value based on the thermal properties of your PCB.
* -The 'Worst - Case' condition assumes the maximum Ta = 85 ¡ãC operating temperature with all supplies at Nominal+5% voltage. It also takes into account increased leakage current possible at the extremes of normal process variation. It is expected that this combination of conditions will be very unlikely to occur, and is provided to give guidance for maximum current requirements.
*
* Settings
* ========
*
* Location Setting Name Decimal Value Hex Value
* ------------ -------------------------- ----------------- -----------------
* 0x0006[23:0] TOOL_VERSION 0 0x000000
* 0x000B[6:0] I2C_ADDR 104 0x68
* 0x0016[1] LOL_ON_HOLD 1 0x1
* 0x0017[0] SYSINCAL_INTR_MSK 0 0x0
* 0x0017[1] LOSXAXB_INTR_MSK 0 0x0
* 0x0017[2] LOSREF_INTR_MSK 1 0x1
* 0x0017[3] XAXB_ERR_INTR_MSK 1 0x1
* 0x0017[5] SMB_TMOUT_INTR_MSK 0 0x0
* 0x0018[3:0] LOS_INTR_MSK 13 0xD
* 0x0018[7:4] OOF_INTR_MSK 13 0xD
* 0x0019[1] LOL_INTR_MSK 0 0x0
* 0x0019[5] HOLD_INTR_MSK 0 0x0
* 0x001A[5] CAL_INTR_MSK 0 0x0
* 0x002B[3] SPI_3WIRE 0 0x0
* 0x002C[3:0] LOS_EN 2 0x2
* 0x002C[4] LOSXAXB_DIS 0 0x0
* 0x002D[1:0] LOS0_VAL_TIME 0 0x0
* 0x002D[3:2] LOS1_VAL_TIME 0 0x0
* 0x002D[5:4] LOS2_VAL_TIME 0 0x0
* 0x002D[7:6] LOS3_VAL_TIME 0 0x0
* 0x002E[15:0] LOS0_TRG_THR 0 0x0000
* 0x0030[15:0] LOS1_TRG_THR 60 0x003C
* 0x0032[15:0] LOS2_TRG_THR 0 0x0000
* 0x0034[15:0] LOS3_TRG_THR 0 0x0000
* 0x0036[15:0] LOS0_CLR_THR 0 0x0000
* 0x0038[15:0] LOS1_CLR_THR 2 0x0002
* 0x003A[15:0] LOS2_CLR_THR 0 0x0000
* 0x003C[15:0] LOS3_CLR_THR 0 0x0000
* 0x003E[7:4] LOS_MIN_PERIOD_EN 2 0x2
* 0x003F[3:0] OOF_EN 2 0x2
* 0x003F[7:4] FAST_OOF_EN 2 0x2
* 0x0040[2:0] OOF_REF_SEL 4 0x4
* 0x0041[4:0] OOF0_DIV_SEL 0 0x00
* 0x0042[4:0] OOF1_DIV_SEL 14 0x0E
* 0x0043[4:0] OOF2_DIV_SEL 0 0x00
* 0x0044[4:0] OOF3_DIV_SEL 0 0x00
* 0x0045[4:0] OOFXO_DIV_SEL 12 0x0C
* 0x0046[7:0] OOF0_SET_THR 0 0x00
* 0x0047[7:0] OOF1_SET_THR 50 0x32
* 0x0048[7:0] OOF2_SET_THR 0 0x00
* 0x0049[7:0] OOF3_SET_THR 0 0x00
* 0x004A[7:0] OOF0_CLR_THR 0 0x00
* 0x004B[7:0] OOF1_CLR_THR 50 0x32
* 0x004C[7:0] OOF2_CLR_THR 0 0x00
* 0x004D[7:0] OOF3_CLR_THR 0 0x00
* 0x004E[2:0] OOF0_DETWIN_SEL 0 0x0
* 0x004E[6:4] OOF1_DETWIN_SEL 5 0x5
* 0x004F[2:0] OOF2_DETWIN_SEL 0 0x0
* 0x004F[6:4] OOF3_DETWIN_SEL 0 0x0
* 0x0050[3:0] OOF_ON_LOS 15 0xF
* 0x0051[3:0] FAST_OOF0_SET_THR 0 0x0
* 0x0052[3:0] FAST_OOF1_SET_THR 3 0x3
* 0x0053[3:0] FAST_OOF2_SET_THR 0 0x0
* 0x0054[3:0] FAST_OOF3_SET_THR 0 0x0
* 0x0055[3:0] FAST_OOF0_CLR_THR 0 0x0
* 0x0056[3:0] FAST_OOF1_CLR_THR 3 0x3
* 0x0057[3:0] FAST_OOF2_CLR_THR 0 0x0
* 0x0058[3:0] FAST_OOF3_CLR_THR 0 0x0
* 0x0059[1:0] FAST_OOF0_DETWIN_SEL 0 0x0
* 0x0059[3:2] FAST_OOF1_DETWIN_SEL 1 0x1
* 0x0059[5:4] FAST_OOF2_DETWIN_SEL 0 0x0
* 0x0059[7:6] FAST_OOF3_DETWIN_SEL 0 0x0
* 0x005A[25:0] OOF0_RATIO_REF 0 0x0000000
* 0x005E[25:0] OOF1_RATIO_REF 19088743 0x1234567
* 0x0062[25:0] OOF2_RATIO_REF 0 0x0000000
* 0x0066[25:0] OOF3_RATIO_REF 0 0x0000000
* 0x0092[1] LOL_FST_EN 1 0x1
* 0x0093[7:4] LOL_FST_DETWIN_SEL 10 0xA
* 0x0095[3:2] LOL_FST_VALWIN_SEL 0 0x0
* 0x0096[7:4] LOL_FST_SET_THR_SEL 8 0x8
* 0x0098[7:4] LOL_FST_CLR_THR_SEL 6 0x6
* 0x009A[1] LOL_SLOW_EN_PLL 1 0x1
* 0x009B[7:4] LOL_SLW_DETWIN_SEL 6 0x6
* 0x009D[3:2] LOL_SLW_VALWIN_SEL 2 0x2
* 0x009E[7:4] LOL_SLW_SET_THR 4 0x4
* 0x00A0[7:4] LOL_SLW_CLR_THR 2 0x2
* 0x00A2[1] LOL_TIMER_EN 0 0x0
* 0x00A9[28:0] LOL_CLR_DELAY_DIV256 24993 0x000061A1
* 0x00E5[0] FASTLOCK_EXTEND_MASTER_DIS 0 0x0
* 0x00E5[5] FASTLOCK_EXTEND_EN 0 0x0
* 0x00EA[28:0] FASTLOCK_EXTEND 24586 0x0000600A
* 0x0102[0] OUTALL_DISABLE_LOW 1 0x1
* 0x0103[0] OUT0A_PDN 0 0x0
* 0x0103[1] OUT0A_OE 1 0x1
* 0x0103[2] OUT0A_RDIV_FORCE 0 0x0
* 0x0103[3] OUT0A_DIV2_BYP 0 0x0
* 0x0104[2:0] OUT0A_FORMAT 1 0x1
* 0x0104[3] OUT0A_SYNC_EN 1 0x1
* 0x0104[5:4] OUT0A_DIS_STATE 0 0x0
* 0x0104[7:6] OUT0A_CMOS_DRV 0 0x0
* 0x0105[3:0] OUT0A_CM 11 0xB
* 0x0105[6:4] OUT0A_AMPL 3 0x3
* 0x0106[2:0] OUT0A_MUX_SEL 1 0x1
* 0x0106[5:4] OUT0A_VDD_SEL 2 0x2
* 0x0106[3] OUT0A_VDD_SEL_EN 1 0x1
* 0x0106[7:6] OUT0A_INV 0 0x0
* 0x0108[0] OUT0_PDN 0 0x0
* 0x0108[1] OUT0_OE 1 0x1
* 0x0108[2] OUT0_RDIV_FORCE 0 0x0
* 0x0108[3] OUT0_DIV2_BYP 0 0x0
* 0x0109[2:0] OUT0_FORMAT 1 0x1
* 0x0109[3] OUT0_SYNC_EN 1 0x1
* 0x0109[5:4] OUT0_DIS_STATE 0 0x0
* 0x0109[7:6] OUT0_CMOS_DRV 0 0x0
* 0x010A[3:0] OUT0_CM 11 0xB
* 0x010A[6:4] OUT0_AMPL 3 0x3
* 0x010B[2:0] OUT0_MUX_SEL 1 0x1
* 0x010B[5:4] OUT0_VDD_SEL 2 0x2
* 0x010B[3] OUT0_VDD_SEL_EN 1 0x1
* 0x010B[7:6] OUT0_INV 0 0x0
* 0x010D[0] OUT1_PDN 1 0x1
* 0x010D[1] OUT1_OE 0 0x0
* 0x010D[2] OUT1_RDIV_FORCE2 0 0x0
* 0x010D[3] OUT1_DIV2_BYP 0 0x0
* 0x010E[2:0] OUT1_FORMAT 1 0x1
* 0x010E[3] OUT1_SYNC_EN 1 0x1
* 0x010E[5:4] OUT1_DIS_STATE 0 0x0
* 0x010E[7:6] OUT1_CMOS_DRV 0 0x0
* 0x010F[3:0] OUT1_CM 11 0xB
* 0x010F[6:4] OUT1_AMPL 3 0x3
* 0x0110[2:0] OUT1_MUX_SEL 0 0x0
* 0x0110[5:4] OUT1_VDD_SEL 2 0x2
* 0x0110[3] OUT1_VDD_SEL_EN 1 0x1
* 0x0110[7:6] OUT1_INV 0 0x0
* 0x0112[0] OUT2_PDN 1 0x1
* 0x0112[1] OUT2_OE 0 0x0
* 0x0112[2] OUT2_RDIV_FORCE2 0 0x0
* 0x0112[3] OUT2_DIV2_BYP 0 0x0
* 0x0113[2:0] OUT2_FORMAT 1 0x1
* 0x0113[3] OUT2_SYNC_EN 1 0x1
* 0x0113[5:4] OUT2_DIS_STATE 0 0x0
* 0x0113[7:6] OUT2_CMOS_DRV 0 0x0