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Release v1.4.18 (#514)
* Fixed the broken links pointing to the AXI interface specifications * Enable Xilinx 2020.2 tools * Updated FAQ on how to request an AFI limit increase
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‎.gitmodules

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[submodule "Vitis/examples/xilinx_2020.1"]
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path = Vitis/examples/xilinx_2020.1
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url = https://github.com/Xilinx/Vitis_Accel_Examples
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[submodule "Vitis/examples/xilinx_2020.2"]
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path = Vitis/examples/xilinx_2020.2
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url = https://github.com/Xilinx/Vitis_Accel_Examples

‎FAQs.md

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@@ -103,7 +103,15 @@ Every FPGA deployed in AWS cloud includes an AWS Shell, and the developer Custom
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It is the compiled FPGA code that is loaded into an FPGA in AWS for performing the Custom Logic (CL) function created by the developer. AFIs are maintained by AWS according and associated with the AWS account that created them. The AFI includes the CL and AWS FPGA Shell. An AFI ID is used to reference a particular AFI from an F1 instance.
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The developer can create multiple AFIs at no extra cost, up to a defined limited (typically 100 AFIs per region per AWS account). An AFI can be loaded into as many FPGAs as needed.
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The developer can create multiple AFIs at no extra cost, up to a defined limited (typically 500 AFIs per region per AWS account). An AFI can be loaded into as many FPGAs as needed.
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**Q: How do I increase my AFI limit?**
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You can increase your AFI limit by creating an [AWS Support Case](https://console.aws.amazon.com/support/home#/case/create).
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1. Select the `Service Limit Increase` tab
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2. In the `Limit Type`, select `EC2 FPGA`
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3. Select the region(s) where you want your limit to be increased
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4. Add justification for the limit increase.
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**Q: What regions are supported?**

‎Jenkinsfile

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@@ -126,9 +126,9 @@ task_label = [
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]
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// Put the latest version last
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def xilinx_versions = [ '2019.1', '2019.2', '2020.1' ]
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def xilinx_versions = [ '2019.1', '2019.2', '2020.1' , '2020.2' ]
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def vitis_versions = ['2019.2', '2020.1']
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def vitis_versions = ['2019.2', '2020.1' , '2020.2' ]
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// We want the default to be the latest.
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def default_xilinx_version = xilinx_versions.last()
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def xsa_map = [
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'2019.2' : [ 'DYNAMIC':'dyn'],
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'2020.1' : [ 'DYNAMIC':'dyn']
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'2020.1' : [ 'DYNAMIC':'dyn'],
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'2020.2' : [ 'DYNAMIC':'dyn']
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]
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def sdaccel_example_default_map = [
@@ -165,6 +166,14 @@ def vitis_example_default_map = [
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'RTL_Vadd_Debug': 'Vitis/examples/xilinx/rtl_kernels/rtl_vadd_hw_debug',
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'gemm_blas': 'Vitis/examples/xilinx/library_examples/gemm',
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'gzip_app': 'Vitis/examples/xilinx/library_examples/gzip_app'
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],
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'2020.2' : [
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'Hello_World_1ddr': 'Vitis/examples/xilinx/ocl_kernels/cl_helloworld',
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'Gmem_2Banks_2ddr': 'Vitis/examples/xilinx/ocl_kernels/cl_gmem_2banks',
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'Kernel_Global_Bw_4ddr': 'Vitis/examples/xilinx/cpp_kernels/kernel_global_bandwidth',
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'RTL_Vadd_Debug': 'Vitis/examples/xilinx/rtl_kernels/rtl_vadd_hw_debug',
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'gemm_blas': 'Vitis/examples/xilinx/library_examples/gemm',
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'gzip_app': 'Vitis/examples/xilinx/library_examples/gzip_app'
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]
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]
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'vcs': 'synopsys/vcs-mx/P-2019.06-SP1-1',
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'questa': 'questa/2019.4',
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'ies': 'incisive/15.20.079'
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],
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'2020.2' : [
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'vivado': 'xilinx/Vivado/2020.2',
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'vcs': 'synopsys/vcs-mx/Q-2020.03',
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'questa': 'questa/2020.2',
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'ies': 'incisive/15.20.083'
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]
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]
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‎Jenkinsfile_int_sims

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]
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// Put the latest version last
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def xilinx_versions = [ '2019.2' ]
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def xilinx_versions = [ '2020.2' ]
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// We want the default to be the latest.
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def default_xilinx_version = xilinx_versions.last()
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'vcs': 'synopsys/vcs-mx/P-2019.06-SP1-1',
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'questa': 'questa/2019.4',
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'ies': 'incisive/15.20.079'
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],
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'2020.2' : [
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'vivado': 'xilinx/Vivado/2020.2',
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'vcs': 'synopsys/vcs/Q-2020.03',
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'questa': 'questa/2019.4_3',
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'ies': 'incisive/15.20.083'
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]
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]
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@@ -177,7 +183,7 @@ if (test_sims) {
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module purge
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module load python/3.7.2
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module load python/2.7.14
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module load batch
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module load slurm
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module load ${vivado_module}
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module load ${vcs_module}
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module load ${questa_module}

‎README.md

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| Developer Kit Version | Tool Version Supported | Compatible FPGA Developer AMI Version |
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|-----------|-----------|------|
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| 1.4.18+ | 2020.2 | v1.10.X (Xilinx Vivado/Vitis 2020.2) |
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| 1.4.16+ | 2020.1 | v1.9.0-v1.9.X (Xilinx Vivado/Vitis 2020.1) |
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| 1.4.13+ | 2019.2 | v1.8.0-v1.8.X (Xilinx Vivado/Vitis 2019.2) |
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| 1.4.11+ | 2019.1 | v1.7.0-v1.7.X (Xilinx Vivado/SDx 2019.1) |

‎RELEASE_NOTES.md

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# AWS EC2 FPGA HDK+SDK Release Notes
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## Release 1.4.18 (See [ERRATA](./ERRATA.md) for unsupported features)
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* FPGA developer kit now supports Xilinx Vivado/Vitis 2020.2
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## Release 1.4.17 (See [ERRATA](./ERRATA.md) for unsupported features)
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* Updated XDMA Driver to allow builds on newer kernels
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* Updated documentation on Alveo U200 to F1 platform porting

‎Vitis/docs/Create_Runtime_AMI.md

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| Vitis Version used for AFI Development | Compatible Xilinx Runtime |
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|--------------------------------------|-----------------------------|
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| 2020.1 | AWS FPGA Developer AMI 1.9.0 (XRT is pre-installed) or [XRT](https://xilinx.github.io/XRT/2020.1/html/build.html) |
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| 2019.2 | AWS FPGA Developer AMI 1.8.0 (XRT is pre-installed) or [XRT](https://xilinx.github.io/XRT/2019.2/html/build.html) |
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| 2020.2 | AWS FPGA Developer AMI 1.10.x (XRT is pre-installed) or [XRT](https://xilinx.github.io/XRT/2020.2/html/build.html) |
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| 2020.1 | AWS FPGA Developer AMI 1.9.x (XRT is pre-installed) or [XRT](https://xilinx.github.io/XRT/2020.1/html/build.html) |
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| 2019.2 | AWS FPGA Developer AMI 1.8.x (XRT is pre-installed) or [XRT](https://xilinx.github.io/XRT/2019.2/html/build.html) |
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## 1. Launch a Runtime Instance & Install Required Packages
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‎Vitis/docs/XRT_installation_instructions.md

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* We provide pre-built RPM's for Centos/RHEL/AL2 and instructions for building XRT
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* Use the below table as reference to install and use the correct XRT version for your applications.
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| Xilinx Vitis Tool Version | XRT Release Tag | SHA | `xrt`|`xrt-aws` RPM's (Centos/RHEL) |`xrt`|`xrt-aws` RPM's (AL2)
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|---|---|---|---|
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| Xilinx Vitis Tool Version | XRT Release Tag | SHA | `xrt` or `xrt-aws` RPM's (Centos/RHEL) |`xrt` or`xrt-aws` RPM's (AL2) |
8+
|---|---|---|---|---|
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|2020.2| [202020.2.8.743](https://github.com/Xilinx/XRT/releases/tag/202020.2.8.743) | 77d5484b5c4daa691a7f78235053fb036829b1e9 | [xrt_202020.2.8.0_7.9.2009-x86_64-xrt.rpm](https://aws-fpga-developer-ami.s3.amazonaws.com/1.10.0/Patches/XRT_2020_2/xrt_202020.2.8.0_7.9.2009-x86_64-xrt.rpm) [xrt_202020.2.8.0_7.9.2009-x86_64-aws.rpm](https://aws-fpga-developer-ami.s3.amazonaws.com/1.10.0/Patches/XRT_2020_2/xrt_202020.2.8.0_7.9.2009-x86_64-aws.rpm) | [xrt_202020.2.8.0_2-x86_64-xrt.rpm](https://aws-fpga-developer-ami.s3.amazonaws.com/1.10.0/Patches/XRT_2020_2/xrt_202020.2.8.0_2-x86_64-xrt.rpm) [xrt_202020.2.8.0_2-x86_64-aws.rpm](https://aws-fpga-developer-ami.s3.amazonaws.com/1.10.0/Patches/XRT_2020_2/xrt_202020.2.8.0_2-x86_64-aws.rpm)|
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|2020.1| [202010.2.6.AWS](https://github.com/Xilinx/XRT/releases/tag/202010.2.6.AWS) | d09c4a458c16e8d843b3165dcf929c38f7a32b6f | [xrt_202010.2.6.0_7.7.1908-x86_64-xrt.rpm](https://aws-fpga-developer-ami.s3.amazonaws.com/1.9.0/Patches/XRT_2020_1/xrt_202010.2.6.0_7.7.1908-x86_64-xrt.rpm) [xrt_202010.2.6.0_7.7.1908-x86_64-aws.rpm](https://aws-fpga-developer-ami.s3.amazonaws.com/1.9.0/Patches/XRT_2020_1/xrt_202010.2.6.0_7.7.1908-x86_64-aws.rpm) | [xrt_202010.2.6.0_2-x86_64-xrt.rpm](https://aws-fpga-developer-ami.s3.amazonaws.com/1.9.0/Patches/XRT_2020_1/xrt_202010.2.6.0_2-x86_64-xrt.rpm) [xrt_202010.2.6.0_2-x86_64-aws.rpm](https://aws-fpga-developer-ami.s3.amazonaws.com/1.9.0/Patches/XRT_2020_1/xrt_202010.2.6.0_2-x86_64-aws.rpm)|
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|2019.2| [2019.2.0.3](https://github.com/Xilinx/XRT/releases/tag/2019.2.0.3) | 9e13d57c4563e2c19bf5f518993f6e5a8dadc18a | [xrt_201920.2.3.0_7.7.1908-xrt.rpm](https://aws-fpga-developer-ami.s3.amazonaws.com/1.8.0/Patches/XRT_2019_2/xrt_201920.2.3.0_7.7.1908-xrt.rpm) [xrt_201920.2.3.0_7.7.1908-aws.rpm](https://aws-fpga-developer-ami.s3.amazonaws.com/1.8.0/Patches/XRT_2019_2/xrt_201920.2.3.0_7.7.1908-aws.rpm) | N/A |
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‎Vitis/examples/xilinx_2020.2

Submodule xilinx_2020.2 added at f72dff9

‎Vitis/tools/create_vitis_afi.sh

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#STEP 6
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#Create .awsxclbin
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/opt/xilinx/xrt/bin/xclbinutil -i $xclbin --remove-section PARTITION_METADATA --remove-section SYSTEM_METADATA --replace-section BITSTREAM:RAW:${timestamp}_agfi_id.txt -o ${awsxclbin}.awsxclbin
282+
283+
if [ "$RELEASE_VER" == "2020.2" ]
284+
then
285+
/opt/xilinx/xrt/bin/xclbinutil -i $xclbin --remove-section PARTITION_METADATA --replace-section BITSTREAM:RAW:${timestamp}_agfi_id.txt -o ${awsxclbin}.awsxclbin
286+
else
287+
/opt/xilinx/xrt/bin/xclbinutil -i $xclbin --remove-section PARTITION_METADATA --remove-section SYSTEM_METADATA --replace-section BITSTREAM:RAW:${timestamp}_agfi_id.txt -o ${awsxclbin}.awsxclbin
288+
fi

‎Vitis/vitis_xrt_version.txt

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2019.2:9e13d57c4563e2c19bf5f518993f6e5a8dadc18a
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2020.1:12115fd4054cb46a5ade62fafa74c523f59116e6
33
2020.1:d09c4a458c16e8d843b3165dcf929c38f7a32b6f
4-
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2020.2:77d5484b5c4daa691a7f78235053fb036829b1e9

‎docs/on_premise_licensing_help.md

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**NOTE: If you are developing on the AWS cloud and using AWS FPGA Developer AMI provided on AWS Marketplace, you can skip this document.**
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This document helps developers who choose to develop on-premises with specifying and licensing AWS-compatible Xilinx tools for use with the AWS FPGA HDK.
6+
## Requirements for AWS HDK 1.4.18+ (2020.2)
7+
* Xilinx Vivado or Vitis v2020.2
8+
* License: EF-VIVADO-SDX-VU9P-OP
9+
* URL: https://www.xilinx.com/member/forms/download/xef.html?filename=Xilinx_Unified_2020.2_1118_1232.tar.gz
10+
* MD5 SUM Value: 523e8596f114ab5e389c14df50ecb1d8
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## Requirements for AWS HDK 1.4.16+ (2020.1)
813
* Xilinx Vivado or Vitis v2020.1
914
* License: EF-VIVADO-SDX-VU9P-OP
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* URL: https://www.xilinx.com/member/forms/download/xef.html?filename=Xilinx_Unified_2020.1_0602_1208.tar.gz
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* MD5 SUM Value: b018f7b331ab0446137756156ff944d9
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## Requirements for AWS HDK 1.4.13+ (2019.2)
18+
## Requirements for AWS HDK 1.4.13+ (2019.2)
1419
* Xilinx Vivado or Vitis v2019.2
1520
* License: EF-VIVADO-SDX-VU9P-OP
1621
* URL: https://www.xilinx.com/member/forms/download/xef-vitis.html?filename=Xilinx_Vitis_2019.2_1106_2127.tar.gz

‎hdk/README.md

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| 1.4.11-1.4.x | 2019.1 | v1.7.0 (Xilinx Vivado 2019.1) |
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| 1.4.11-1.4.x | 2019.2 | v1.8.x (Xilinx Vivado 2019.2) |
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| 1.4.16-1.4.x | 2020.1 | v1.9.x (Xilinx Vivado 2020.1) |
69+
| 1.4.18-1.4.x | 2020.2 | v1.10.x (Xilinx Vivado 2020.2) |
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* The FPGA Developer Kit version is listed in [hdk_version.txt](./hdk_version.txt)
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‎hdk/cl/examples/cl_dram_dma/build/scripts/create_dcp_from_cl.tcl

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set TOP top_sp
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## Replace with the name of your module
22-
set CL_MODULE cl_dram_dma
22+
set CL_MODULE cl_dram_dma
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2424
#################################################
2525
## Command-line Arguments
@@ -39,7 +39,7 @@ set uram_option [lindex $argv 11]
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set notify_via_sns [lindex $argv 12]
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set VDEFINES [lindex $argv 13]
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##################################################
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## Flow control variables
42+
## Flow control variables
4343
##################################################
4444
set cl.synth 1
4545
set implement 1
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147147
set_msg_config -id {DRC REQP-1853} -suppress
148148
set_msg_config -id {Timing 38-436} -suppress
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150+
set_msg_config -severity "CRITICAL WARNING" -string "WRAPPER_INST/SH" -suppress
151+
set_msg_config -severity "WARNING" -string "WRAPPER_INST/SH" -suppress
152+
150153
# Check that an email address has been set, else unset notify_via_sns
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152155
if {[string compare $notify_via_sns "1"] == 0} {
@@ -159,7 +162,7 @@ if {[string compare $notify_via_sns "1"] == 0} {
159162
}
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161164
##################################################
162-
### Strategy options
165+
### Strategy options
163166
##################################################
164167
switch $strategy {
165168
"BASIC" {
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200203
source $HDK_SHELL_DIR/build/scripts/step_user.tcl -notrace
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202205
########################################
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## Generate clocks based on Recipe
206+
## Generate clocks based on Recipe
204207
########################################
205208

206209
puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling aws_gen_clk_constraints.tcl to generate clock constraints from developer's specified recipe.";
@@ -254,7 +257,7 @@ if {$implement} {
254257
# Apply Clock Properties for Clock Table Recipes
255258
##################################################
256259
puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Sourcing aws_clock_properties.tcl to apply properties to clocks. ";
257-
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258261
# Apply properties to clocks
259262
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385388
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387390
puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Build complete.";
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‎hdk/cl/examples/cl_dram_dma_hlx/build/scripts/create_dcp_from_cl.tcl

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3737
}
3838
}
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40+
# suppress warnings coming from Shell
41+
set_msg_config -severity "CRITICAL WARNING" -string "WRAPPER_INST/SH" -suppress
42+
set_msg_config -severity "WARNING" -string "WRAPPER_INST/SH" -suppress
43+
4044
#################################################
4145
## Create BD (Block Design) of example Hello World design
4246
#################################################

‎hdk/cl/examples/cl_hello_world/build/scripts/create_dcp_from_cl.tcl

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set VDEFINES [lindex $argv 13]
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##################################################
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## Flow control variables
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## Flow control variables
4343
##################################################
4444
set cl.synth 1
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set implement 1
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set_msg_config -id {Synth 8-3917} -suppress
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set_msg_config -id {Opt 31-430} -suppress
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137+
set_msg_config -severity "CRITICAL WARNING" -string "WRAPPER_INST/SH" -suppress
138+
set_msg_config -severity "WARNING" -string "WRAPPER_INST/SH" -suppress
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137140
puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling the encrypt.tcl.";
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# Check that an email address has been set, else unset notify_via_sns
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148151
}
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150153
##################################################
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### Strategy options
154+
### Strategy options
152155
##################################################
153156
switch $strategy {
154157
"BASIC" {
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187190
source $HDK_SHELL_DIR/build/scripts/step_user.tcl -notrace
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########################################
190-
## Generate clocks based on Recipe
193+
## Generate clocks based on Recipe
191194
########################################
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193196
puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling aws_gen_clk_constraints.tcl to generate clock constraints from developer's specified recipe.";
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195198
source $HDK_SHELL_DIR/build/scripts/aws_gen_clk_constraints.tcl
196199
#################################################################
197-
#### Do not remove this setting. Need to workaround bug
200+
#### Do not remove this setting. Need to workaround bug
198201
##################################################################
199202
set_param hd.clockRoutingWireReduction false
200203
##################################################
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236239
# Apply Clock Properties for Clock Table Recipes
237240
##################################################
238241
puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Sourcing aws_clock_properties.tcl to apply properties to clocks. ";
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240243
# Apply properties to clocks
241244
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@@ -365,5 +368,3 @@ if {[string compare $notify_via_sns "1"] == 0} {
365368
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367370
puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Build complete.";
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‎hdk/cl/examples/cl_hello_world/build/scripts/synth_cl_hello_world.tcl

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@@ -21,7 +21,7 @@ set VDEFINES $VDEFINES
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create_project -in_memory -part [DEVICE_TYPE] -force
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########################################
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## Generate clocks based on Recipe
24+
## Generate clocks based on Recipe
2525
########################################
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puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling aws_gen_clk_constraints.tcl to generate clock constraints from developer's specified recipe.";

‎hdk/cl/examples/cl_hello_world_hlx/build/scripts/create_dcp_from_cl.tcl

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@@ -37,6 +37,10 @@ if {[string compare $notify_via_sns "1"] == 0} {
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}
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}
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# suppress warnings coming from Shell
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set_msg_config -severity "CRITICAL WARNING" -string "WRAPPER_INST/SH" -suppress
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set_msg_config -severity "WARNING" -string "WRAPPER_INST/SH" -suppress
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#################################################
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## Create BD (Block Design) of example Hello World design
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#################################################

‎hdk/cl/examples/cl_hello_world_ref_hlx/build/scripts/create_dcp_from_cl.tcl

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@@ -29,6 +29,10 @@ if {[string compare $notify_via_sns "1"] == 0} {
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}
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}
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# suppress warnings coming from Shell
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set_msg_config -severity "CRITICAL WARNING" -string "WRAPPER_INST/SH" -suppress
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set_msg_config -severity "WARNING" -string "WRAPPER_INST/SH" -suppress
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#################################################
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## Create BD (Block Design) of example Hello World design
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#################################################

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