diff --git a/README.md b/README.md index 59db39a..d8e3449 100644 --- a/README.md +++ b/README.md @@ -260,7 +260,7 @@ Build the firmware and deploy the system according to the target platform: | zcu104 | x | x | | | | imx8qm | x | x | | | | tx2 | x | x | | | -| rpi4 | x | x | | | +| rpi4 | x | x | x | | | qemu-aarch64-virt | x | x | x | | | fvp-a-aarch64 | x | x | x | x | | fvp-a-aarch32 | x | x | x | x | diff --git a/demos/linux+zephyr/configs/rpi4.c b/demos/linux+zephyr/configs/rpi4.c new file mode 100644 index 0000000..db6bac4 --- /dev/null +++ b/demos/linux+zephyr/configs/rpi4.c @@ -0,0 +1,131 @@ +#include + +VM_IMAGE(linux_image, XSTR(BAO_DEMOS_WRKDIR_IMGS/linux.bin)); +VM_IMAGE(zephyr_image, XSTR(BAO_DEMOS_WRKDIR_IMGS/zephyr.bin)); + +struct config config = { + + .shmemlist_size = 1, + .shmemlist = (struct shmem[]) { + [0] = { .size = 0x00010000, } + }, + + .vmlist_size = 2, + .vmlist = { + { + .image = { + .base_addr = 0x20000000, + .load_addr = VM_IMAGE_OFFSET(linux_image), + .size = VM_IMAGE_SIZE(linux_image) + }, + + .entry = 0x20000000, + + .platform = { + .cpu_num = 3, + + .region_num = 1, + .regions = (struct vm_mem_region[]) { + { + .base = 0x20000000, + .size = 0x40000000, + .place_phys = true, + .phys = 0x20000000 + } + }, + + .ipc_num = 1, + .ipcs = (struct ipc[]) { + { + .base = 0xf0000000, + .size = 0x00010000, + .shmem_id = 0, + .interrupt_num = 1, + .interrupts = (irqid_t[]) {52} + } + }, + + .dev_num = 2, + .devs = (struct vm_dev_region[]) { + { + /* GENET */ + .pa = 0xfd580000, + .va = 0xfd580000, + .size = 0x10000, + .interrupt_num = 2, + .interrupts = (irqid_t[]) {189, 190} + }, + { + /* Arch timer interrupt */ + .interrupt_num = 1, + .interrupts = + (irqid_t[]) {27} + } + }, + + .arch = { + .gic = { + .gicd_addr = 0xff841000, + .gicc_addr = 0xff842000, + } + } + }, + }, + { + .image = { + .base_addr = 0x80000000, + .load_addr = VM_IMAGE_OFFSET(zephyr_image), + .size = VM_IMAGE_SIZE(zephyr_image) + }, + + .entry = 0x80000000, + + .platform = { + .cpu_num = 1, + + .region_num = 1, + .regions = (struct vm_mem_region[]) { + { + .base = 0x80000000, + .size = 0x8000000 + } + }, + + .ipc_num = 1, + .ipcs = (struct ipc[]) { + { + .base = 0x70000000, + .size = 0x00004000, + .shmem_id = 0, + .interrupt_num = 1, + .interrupts = (irqid_t[]) {52} + } + }, + + .dev_num = 2, + .devs = (struct vm_dev_region[]) { + { + /* UART1 */ + .pa = 0xfe215000, + .va = 0xfe215000, + .size = 0x1000, + .interrupt_num = 1, + .interrupts = (irqid_t[]) {125} + }, + { + /* Arch timer interrupt */ + .interrupt_num = 1, + .interrupts = + (irqid_t[]) {27} + } + }, + .arch = { + .gic = { + .gicd_addr = 0xff841000, + .gicc_addr = 0xff842000, + } + } + }, + }, + }, +}; diff --git a/guests/zephyr/boards/arm64/baovm_fvp-a/baovm_fvp-a.dts b/guests/zephyr/boards/arm64/baovm_fvp-a/baovm_fvp-a.dts index 283bde6..3173783 100644 --- a/guests/zephyr/boards/arm64/baovm_fvp-a/baovm_fvp-a.dts +++ b/guests/zephyr/boards/arm64/baovm_fvp-a/baovm_fvp-a.dts @@ -74,7 +74,7 @@ interrupt-parent = <&gic>; gic: interrupt-controller@2f000000 { - compatible = "arm,gic"; + compatible = "arm,gic-v3", "arm,gic"; reg = <0x2f000000 0x10000>, // GICD <0x2f100000 0x200000>; // GICR interrupt-controller; diff --git a/guests/zephyr/boards/arm64/baovm_fvp-r/baovm_fvp-r.dts b/guests/zephyr/boards/arm64/baovm_fvp-r/baovm_fvp-r.dts index f2946a0..3ff7638 100644 --- a/guests/zephyr/boards/arm64/baovm_fvp-r/baovm_fvp-r.dts +++ b/guests/zephyr/boards/arm64/baovm_fvp-r/baovm_fvp-r.dts @@ -8,6 +8,7 @@ // #include #include #include +#include / { model = "Bao VM for FVP BaseR AEMv8R"; @@ -77,7 +78,7 @@ interrupt-parent = <&gic>; gic: interrupt-controller@af000000 { - compatible = "arm,gic"; + compatible = "arm,gic-v3", "arm,gic"; reg = <0xaf000000 0x10000>, <0xaf100000 0x200000>; interrupt-controller; @@ -102,7 +103,21 @@ dram0: memory@24000000 { compatible = "mmio-dram"; - reg = <0x24000000 DT_SIZE_M((512*3)-64)>; + reg = <0x24000000 DT_SIZE_M(64)>; + }; + + baoipc_region: memory@70000000 { + compatible = "zephyr,memory-region"; + reg = <0x70000000 0x00010000>; + zephyr,memory-region = "BAOIPC"; + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; + }; + + device_region: memory@9a000000 { + compatible = "zephyr,memory-region", "mmio-dram"; + reg = <0x9a000000 0x66000000>; + zephyr,memory-region = "DEVICE_REGION"; + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>; }; }; }; diff --git a/guests/zephyr/boards/arm64/baovm_qemu-aarch64-virt/baovm_qemu-aarch64-virt.dts b/guests/zephyr/boards/arm64/baovm_qemu-aarch64-virt/baovm_qemu-aarch64-virt.dts index caff52b..5400f30 100644 --- a/guests/zephyr/boards/arm64/baovm_qemu-aarch64-virt/baovm_qemu-aarch64-virt.dts +++ b/guests/zephyr/boards/arm64/baovm_qemu-aarch64-virt/baovm_qemu-aarch64-virt.dts @@ -74,7 +74,7 @@ interrupt-parent = <&gic>; gic: interrupt-controller@8000000 { - compatible = "arm,gic"; + compatible = "arm,gic-v3", "arm,gic"; reg = <0x8000000 0x10000>, // GICD <0x80a0000 0x200000>; // GICR interrupt-controller; diff --git a/guests/zephyr/boards/arm64/baovm_rpi4/Kconfig.board b/guests/zephyr/boards/arm64/baovm_rpi4/Kconfig.board new file mode 100644 index 0000000..73a1986 --- /dev/null +++ b/guests/zephyr/boards/arm64/baovm_rpi4/Kconfig.board @@ -0,0 +1,8 @@ +# Copyright (c) 2019 Carlo Caione +# Copyright (c) 2023 Yan-Jie Wang +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RASPBERRY_PI_4B + bool "Raspberry Pi 4B" + depends on SOC_BCM2711 + select ARM64 diff --git a/guests/zephyr/boards/arm64/baovm_rpi4/Kconfig.defconfig b/guests/zephyr/boards/arm64/baovm_rpi4/Kconfig.defconfig new file mode 100644 index 0000000..e854137 --- /dev/null +++ b/guests/zephyr/boards/arm64/baovm_rpi4/Kconfig.defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2019 Carlo Caione +# Copyright (c) 2023 Yan-Jie Wang +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RASPBERRY_PI_4B + +config BUILD_OUTPUT_BIN + default y + +config BOARD + default "raspberry_pi_4b" + +endif # BOARD_RASPBERRY_PI_4B diff --git a/guests/zephyr/boards/arm64/baovm_rpi4/baovm_rpi4.dts b/guests/zephyr/boards/arm64/baovm_rpi4/baovm_rpi4.dts new file mode 100644 index 0000000..9492bc6 --- /dev/null +++ b/guests/zephyr/boards/arm64/baovm_rpi4/baovm_rpi4.dts @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2021 Carlo Caione + * Copyright (c) 2023 Yan-Jie Wang + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +/ { + model = "Bao Raspberry Pi 4 Model B"; + + #address-cells = <1>; + #size-cells = <1>; + + aliases { }; + + chosen { + /* + * The SRAM node is actually located in the + * DRAM region of the FVP Base RevC 2xAEMv8A. + */ + zephyr,sram = &dram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + interrupt-parent = <&gic>; + + gic: interrupt-controller@ff841000 { + compatible = "arm,gic-v2", "arm,gic"; + reg = <0xff841000 0x1000>, + <0xff842000 0x2000>; + interrupt-controller; + #interrupt-cells = <4>; + status = "okay"; + #address-cells = <1>; + #size-cells = <1>; + }; + + uart0: uart@fe215040 { + compatible = "brcm,bcm2711-aux-uart"; + reg = <0xfe215040 0x40>; + clock-frequency = <500000000>; + interrupts = ; + status = "disabled"; + }; + + dram0: memory@80000000 { + compatible = "mmio-sram"; + reg = <0x80000000 DT_SIZE_M(128)>; + }; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; +}; diff --git a/guests/zephyr/boards/arm64/baovm_rpi4/baovm_rpi4_defconfig b/guests/zephyr/boards/arm64/baovm_rpi4/baovm_rpi4_defconfig new file mode 100644 index 0000000..0071c4d --- /dev/null +++ b/guests/zephyr/boards/arm64/baovm_rpi4/baovm_rpi4_defconfig @@ -0,0 +1,12 @@ +CONFIG_SOC_BCM2711=y +CONFIG_BOARD_RASPBERRY_PI_4B=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable serial port +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/guests/zephyr/make.mk b/guests/zephyr/make.mk index fc28d2b..c2be5aa 100644 --- a/guests/zephyr/make.mk +++ b/guests/zephyr/make.mk @@ -1,8 +1,9 @@ zephyr_src:=$(wrkdir_src)/zephyr zephyr_repo:=https://github.com/zephyrproject-rtos/zephyr.git -zephyr_version:=v3.3.0 +zephyr_version:=v3.5.0-rc1 zephyr_cmsis_repo:=https://github.com/zephyrproject-rtos/cmsis.git zephyr_cmsis_src:=$(wrkdir_src)/cmsis +zephyr_cmsis_commit:=5a00331455dd74e31e80efa383a489faea0590e3 zephyr_build:=$(wrkdir_demo_imgs)/zephyr_build zephyr_board_root:=$(bao_demos)/guests/zephyr zephyr_board:=baovm_$(PLATFORM) @@ -20,6 +21,7 @@ zephyr_bin:=$(zephyr_build)/zephyr/zephyr.bin $(zephyr_cmsis_src): git clone $(zephyr_cmsis_repo) $@ + git -C $(zephyr_cmsis_src) checkout $(zephyr_cmsis_commit) $(zephyr_build): $(zephyr_src) $(zephyr_cmsis_src) $(zephyr_env) cmake -DCMAKE_PREFIX_PATH=$(zephyr_src)/share/zephyr-package \ diff --git a/guests/zephyr/patches/v3.3.0/0001-enable-shared-caches-for-cortex-r.patch b/guests/zephyr/patches/v3.3.0/0001-enable-shared-caches-for-cortex-r.patch deleted file mode 100644 index 684a20b..0000000 --- a/guests/zephyr/patches/v3.3.0/0001-enable-shared-caches-for-cortex-r.patch +++ /dev/null @@ -1,113 +0,0 @@ -From 0f73c6a91dc4c48bacf6a250f16af614613ad710 Mon Sep 17 00:00:00 2001 -From: Jose Martins -Date: Sat, 1 Apr 2023 21:23:31 +0100 -Subject: [PATCH 1/2] enable shared caches for cortex-r - -Signed-off-by: Jose Martins ---- - arch/arm/core/aarch32/mpu/arm_mpu.c | 2 +- - arch/arm64/core/cortex_r/arm_mpu.c | 2 +- - include/zephyr/arch/arm/aarch32/mpu/arm_mpu_v8.h | 8 ++++---- - include/zephyr/arch/arm64/cortex_r/arm_mpu.h | 6 +++--- - 4 files changed, 9 insertions(+), 9 deletions(-) - -diff --git a/arch/arm/core/aarch32/mpu/arm_mpu.c b/arch/arm/core/aarch32/mpu/arm_mpu.c -index f41f497e..b9469375 100644 ---- a/arch/arm/core/aarch32/mpu/arm_mpu.c -+++ b/arch/arm/core/aarch32/mpu/arm_mpu.c -@@ -147,7 +147,7 @@ void arm_core_mpu_enable(void) - uint32_t val; - - val = __get_SCTLR(); -- val |= SCTLR_MPU_ENABLE; -+ val |= SCTLR_MPU_ENABLE | SCTLR_C_BIT | SCTLR_I_BIT; - __set_SCTLR(val); - - /* Make sure that all the registers are set before proceeding */ -diff --git a/arch/arm64/core/cortex_r/arm_mpu.c b/arch/arm64/core/cortex_r/arm_mpu.c -index 58b7dcd1..7371e804 100644 ---- a/arch/arm64/core/cortex_r/arm_mpu.c -+++ b/arch/arm64/core/cortex_r/arm_mpu.c -@@ -73,7 +73,7 @@ void arm_core_mpu_enable(void) - uint64_t val; - - val = read_sctlr_el1(); -- val |= SCTLR_M_BIT; -+ val |= SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT; - write_sctlr_el1(val); - dsb(); - isb(); -diff --git a/include/zephyr/arch/arm/aarch32/mpu/arm_mpu_v8.h b/include/zephyr/arch/arm/aarch32/mpu/arm_mpu_v8.h -index 67a5a365..59ebf4fc 100644 ---- a/include/zephyr/arch/arm/aarch32/mpu/arm_mpu_v8.h -+++ b/include/zephyr/arch/arm/aarch32/mpu/arm_mpu_v8.h -@@ -191,7 +191,7 @@ - #define REGION_RAM_ATTR(limit) \ - { \ - .rbar = NOT_EXEC | \ -- P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \ -+ P_RW_U_NA_Msk | INNER_SHAREABLE_Msk, /* AP, XN, SH */ \ - /* Cache-ability */ \ - .mair_idx = MPU_MAIR_INDEX_SRAM, \ - .r_limit = limit - 1, /* Region Limit */ \ -@@ -199,7 +199,7 @@ - - #define REGION_RAM_TEXT_ATTR(limit) \ - { \ -- .rbar = P_RO_U_RO_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \ -+ .rbar = P_RO_U_RO_Msk | INNER_SHAREABLE_Msk, /* AP, XN, SH */ \ - /* Cache-ability */ \ - .mair_idx = MPU_MAIR_INDEX_SRAM, \ - .r_limit = limit - 1, /* Region Limit */ \ -@@ -208,7 +208,7 @@ - #define REGION_RAM_RO_ATTR(limit) \ - { \ - .rbar = NOT_EXEC | \ -- P_RO_U_RO_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \ -+ P_RO_U_RO_Msk | INNER_SHAREABLE_Msk, /* AP, XN, SH */ \ - /* Cache-ability */ \ - .mair_idx = MPU_MAIR_INDEX_SRAM, \ - .r_limit = limit - 1, /* Region Limit */ \ -@@ -248,7 +248,7 @@ - #define REGION_RAM_ATTR(base, size) \ - {\ - .rbar = NOT_EXEC | \ -- P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \ -+ P_RW_U_NA_Msk | INNER_SHAREABLE_Msk, /* AP, XN, SH */ \ - /* Cache-ability */ \ - .mair_idx = MPU_MAIR_INDEX_SRAM, \ - .r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */ \ -diff --git a/include/zephyr/arch/arm64/cortex_r/arm_mpu.h b/include/zephyr/arch/arm64/cortex_r/arm_mpu.h -index e3944a77..63b37871 100644 ---- a/include/zephyr/arch/arm64/cortex_r/arm_mpu.h -+++ b/include/zephyr/arch/arm64/cortex_r/arm_mpu.h -@@ -143,7 +143,7 @@ - #define REGION_RAM_ATTR \ - { \ - /* AP, XN, SH */ \ -- .rbar = NOT_EXEC | P_RW_U_NA_Msk | NON_SHAREABLE_Msk, \ -+ .rbar = NOT_EXEC | P_RW_U_NA_Msk | INNER_SHAREABLE_Msk, \ - /* Cache-ability */ \ - .mair_idx = MPU_MAIR_INDEX_SRAM, \ - } -@@ -151,7 +151,7 @@ - #define REGION_RAM_TEXT_ATTR \ - { \ - /* AP, XN, SH */ \ -- .rbar = P_RO_U_RO_Msk | NON_SHAREABLE_Msk, \ -+ .rbar = P_RO_U_RO_Msk | INNER_SHAREABLE_Msk, \ - /* Cache-ability */ \ - .mair_idx = MPU_MAIR_INDEX_SRAM, \ - } -@@ -159,7 +159,7 @@ - #define REGION_RAM_RO_ATTR \ - { \ - /* AP, XN, SH */ \ -- .rbar = NOT_EXEC | P_RO_U_RO_Msk | NON_SHAREABLE_Msk, \ -+ .rbar = NOT_EXEC | P_RO_U_RO_Msk | INNER_SHAREABLE_Msk , \ - /* Cache-ability */ \ - .mair_idx = MPU_MAIR_INDEX_SRAM, \ - } --- -2.34.1 - diff --git a/guests/zephyr/patches/v3.3.0/0001-add-bao-ipcshmem-drivers.patch b/guests/zephyr/patches/v3.5.0-rc1/0001-add-bao-ipcshmem-drivers.patch similarity index 96% rename from guests/zephyr/patches/v3.3.0/0001-add-bao-ipcshmem-drivers.patch rename to guests/zephyr/patches/v3.5.0-rc1/0001-add-bao-ipcshmem-drivers.patch index cc103f4..7bc7c96 100644 --- a/guests/zephyr/patches/v3.3.0/0001-add-bao-ipcshmem-drivers.patch +++ b/guests/zephyr/patches/v3.5.0-rc1/0001-add-bao-ipcshmem-drivers.patch @@ -1,7 +1,7 @@ -From cd6b2086227930794a6021dc295c92da5a70d638 Mon Sep 17 00:00:00 2001 +From 48283f9d251d5e74f51b00ca47e7d6829a5a5605 Mon Sep 17 00:00:00 2001 From: Jose Martins Date: Sat, 4 Feb 2023 16:54:22 +0000 -Subject: [PATCH] add bao ipcshmem drivers +Subject: [PATCH 1/3] add bao ipcshmem drivers Signed-off-by: Jose Martins --- @@ -20,10 +20,10 @@ Signed-off-by: Jose Martins create mode 100644 include/zephyr/drivers/virtualization/bao_ipcshmem.h diff --git a/drivers/virtualization/CMakeLists.txt b/drivers/virtualization/CMakeLists.txt -index 2829e641..8e65cbd7 100644 +index c16ed84e31..6150c91e69 100644 --- a/drivers/virtualization/CMakeLists.txt +++ b/drivers/virtualization/CMakeLists.txt -@@ -6,3 +6,6 @@ zephyr_library_sources_ifdef(CONFIG_IVSHMEM virt_ivshmem.c) +@@ -10,3 +10,6 @@ zephyr_library_sources_ifdef(CONFIG_IVSHMEM virt_ivshmem.c) zephyr_library_sources_ifdef(CONFIG_IVSHMEM_SHELL virt_ivshmem_shell.c) zephyr_library_sources_ifdef(CONFIG_USERSPACE virt_ivshmem_handlers.c) @@ -31,7 +31,7 @@ index 2829e641..8e65cbd7 100644 +zephyr_library_sources_ifdef(CONFIG_BAO_IPCSHMEM bao_ipcshmem.c) +zephyr_library_sources_ifdef(CONFIG_BAO_IPCSHMEM_SHELL bao_ipcshmem_shell.c) diff --git a/drivers/virtualization/Kconfig b/drivers/virtualization/Kconfig -index a5ac6820..fc9b4a68 100644 +index 4f32552f09..a0dac412e1 100644 --- a/drivers/virtualization/Kconfig +++ b/drivers/virtualization/Kconfig @@ -12,6 +12,23 @@ menuconfig VIRTUALIZATION @@ -60,7 +60,7 @@ index a5ac6820..fc9b4a68 100644 depends on PCIE diff --git a/drivers/virtualization/bao_ipcshmem.c b/drivers/virtualization/bao_ipcshmem.c new file mode 100644 -index 00000000..a323cf0c +index 0000000000..a323cf0ca5 --- /dev/null +++ b/drivers/virtualization/bao_ipcshmem.c @@ -0,0 +1,108 @@ @@ -174,7 +174,7 @@ index 00000000..a323cf0c +DT_INST_FOREACH_STATUS_OKAY(BAO_IPCSHMEM_INSTANTIATE) diff --git a/drivers/virtualization/bao_ipcshmem_internal.h b/drivers/virtualization/bao_ipcshmem_internal.h new file mode 100644 -index 00000000..f3292812 +index 0000000000..f32928126e --- /dev/null +++ b/drivers/virtualization/bao_ipcshmem_internal.h @@ -0,0 +1,28 @@ @@ -208,7 +208,7 @@ index 00000000..f3292812 +#endif /* BAO_IPCSHMEM_INTERNAL_H_ */ diff --git a/drivers/virtualization/bao_ipcshmem_shell.c b/drivers/virtualization/bao_ipcshmem_shell.c new file mode 100644 -index 00000000..9bb5c73e +index 0000000000..9bb5c73e86 --- /dev/null +++ b/drivers/virtualization/bao_ipcshmem_shell.c @@ -0,0 +1,97 @@ @@ -311,7 +311,7 @@ index 00000000..9bb5c73e + "Bao IPC Shared Memory Commands", NULL); diff --git a/dts/bindings/virtualization/bao,ipcshmem.yaml b/dts/bindings/virtualization/bao,ipcshmem.yaml new file mode 100644 -index 00000000..ed7cedef +index 0000000000..ed7cedef9a --- /dev/null +++ b/dts/bindings/virtualization/bao,ipcshmem.yaml @@ -0,0 +1,15 @@ @@ -332,7 +332,7 @@ index 00000000..ed7cedef + type: int diff --git a/include/zephyr/drivers/virtualization/bao_ipcshmem.h b/include/zephyr/drivers/virtualization/bao_ipcshmem.h new file mode 100644 -index 00000000..5f6e6fe9 +index 0000000000..5f6e6fe957 --- /dev/null +++ b/include/zephyr/drivers/virtualization/bao_ipcshmem.h @@ -0,0 +1,46 @@ diff --git a/guests/zephyr/patches/v3.3.0/0001-add-smc-support-for-aarch32-r.patch b/guests/zephyr/patches/v3.5.0-rc1/0002-add-smc-support-for-aarch32-r.patch similarity index 67% rename from guests/zephyr/patches/v3.3.0/0001-add-smc-support-for-aarch32-r.patch rename to guests/zephyr/patches/v3.5.0-rc1/0002-add-smc-support-for-aarch32-r.patch index bc1323e..57dbb94 100644 --- a/guests/zephyr/patches/v3.3.0/0001-add-smc-support-for-aarch32-r.patch +++ b/guests/zephyr/patches/v3.5.0-rc1/0002-add-smc-support-for-aarch32-r.patch @@ -1,32 +1,32 @@ -From 6e8232b9462de3a950a56a51d8718ac60c2fce0f Mon Sep 17 00:00:00 2001 +From a25559cde559e6fc0e41026a8367f4d71357fc86 Mon Sep 17 00:00:00 2001 From: Jose Martins Date: Mon, 6 Feb 2023 19:20:41 +0000 -Subject: [PATCH] add smc support for aarch32-r +Subject: [PATCH 2/3] add smc support for aarch32-r Signed-off-by: Jose Martins --- - .../core/aarch32/cortex_a_r/CMakeLists.txt | 1 + - arch/arm/core/aarch32/cortex_a_r/Kconfig | 7 +++ - arch/arm/core/aarch32/cortex_a_r/smccc-call.S | 41 +++++++++++++++ - include/zephyr/arch/arm/aarch32/arm-smccc.h | 51 +++++++++++++++++++ + arch/arm/core/cortex_a_r/CMakeLists.txt | 1 + + arch/arm/core/cortex_a_r/Kconfig | 7 ++++ + arch/arm/core/cortex_a_r/smccc-call.S | 41 ++++++++++++++++++++ + include/zephyr/arch/arm/arm-smccc.h | 51 +++++++++++++++++++++++++ 4 files changed, 100 insertions(+) - create mode 100644 arch/arm/core/aarch32/cortex_a_r/smccc-call.S - create mode 100644 include/zephyr/arch/arm/aarch32/arm-smccc.h + create mode 100644 arch/arm/core/cortex_a_r/smccc-call.S + create mode 100644 include/zephyr/arch/arm/arm-smccc.h -diff --git a/arch/arm/core/aarch32/cortex_a_r/CMakeLists.txt b/arch/arm/core/aarch32/cortex_a_r/CMakeLists.txt -index d3337a67..878800f4 100644 ---- a/arch/arm/core/aarch32/cortex_a_r/CMakeLists.txt -+++ b/arch/arm/core/aarch32/cortex_a_r/CMakeLists.txt -@@ -17,3 +17,4 @@ zephyr_library_sources( - zephyr_library_sources_ifdef(CONFIG_USERSPACE thread.c) +diff --git a/arch/arm/core/cortex_a_r/CMakeLists.txt b/arch/arm/core/cortex_a_r/CMakeLists.txt +index 8b0dac374e..78271d9a2a 100644 +--- a/arch/arm/core/cortex_a_r/CMakeLists.txt ++++ b/arch/arm/core/cortex_a_r/CMakeLists.txt +@@ -25,3 +25,4 @@ zephyr_library_sources_ifdef(CONFIG_USERSPACE thread.c) zephyr_library_sources_ifdef(CONFIG_SEMIHOST semihost.c) zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE __aeabi_read_tp.S) + zephyr_library_sources_ifdef(CONFIG_ARCH_CACHE cache.c) +zephyr_library_sources_ifdef(CONFIG_HAS_ARM_SMCCC smccc-call.S) -diff --git a/arch/arm/core/aarch32/cortex_a_r/Kconfig b/arch/arm/core/aarch32/cortex_a_r/Kconfig -index 418aa9a0..c9b52a22 100644 ---- a/arch/arm/core/aarch32/cortex_a_r/Kconfig -+++ b/arch/arm/core/aarch32/cortex_a_r/Kconfig -@@ -126,9 +126,16 @@ config ARMV7_R_FP +diff --git a/arch/arm/core/cortex_a_r/Kconfig b/arch/arm/core/cortex_a_r/Kconfig +index 10bf721a87..c43a6e586d 100644 +--- a/arch/arm/core/cortex_a_r/Kconfig ++++ b/arch/arm/core/cortex_a_r/Kconfig +@@ -127,9 +127,16 @@ config ARMV7_R_FP This option signifies the use of an ARMv7-R processor implementation supporting the Floating-Point Extension. @@ -43,11 +43,11 @@ index 418aa9a0..c9b52a22 100644 help This option signifies the use of an ARMv8-R AArch32 processor implementation. -diff --git a/arch/arm/core/aarch32/cortex_a_r/smccc-call.S b/arch/arm/core/aarch32/cortex_a_r/smccc-call.S +diff --git a/arch/arm/core/cortex_a_r/smccc-call.S b/arch/arm/core/cortex_a_r/smccc-call.S new file mode 100644 -index 00000000..f655def9 +index 0000000000..f655def9b2 --- /dev/null -+++ b/arch/arm/core/aarch32/cortex_a_r/smccc-call.S ++++ b/arch/arm/core/cortex_a_r/smccc-call.S @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2019 Carlo Caione @@ -90,11 +90,11 @@ index 00000000..f655def9 +GTEXT(arm_smccc_hvc) +SECTION_FUNC(TEXT, arm_smccc_hvc) + SMCCC hvc -diff --git a/include/zephyr/arch/arm/aarch32/arm-smccc.h b/include/zephyr/arch/arm/aarch32/arm-smccc.h +diff --git a/include/zephyr/arch/arm/arm-smccc.h b/include/zephyr/arch/arm/arm-smccc.h new file mode 100644 -index 00000000..e702ce22 +index 0000000000..e702ce2280 --- /dev/null -+++ b/include/zephyr/arch/arm/aarch32/arm-smccc.h ++++ b/include/zephyr/arch/arm/arm-smccc.h @@ -0,0 +1,51 @@ +/* + * Copyright 2020 Carlo Caione diff --git a/guests/zephyr/patches/v3.5.0-rc1/0003-enable-shared-caches-for-cortex-r.patch b/guests/zephyr/patches/v3.5.0-rc1/0003-enable-shared-caches-for-cortex-r.patch new file mode 100644 index 0000000..e22eb2c --- /dev/null +++ b/guests/zephyr/patches/v3.5.0-rc1/0003-enable-shared-caches-for-cortex-r.patch @@ -0,0 +1,81 @@ +From 170e90c28c7055298d4d23c8505c13918c8bfdaa Mon Sep 17 00:00:00 2001 +From: Jose Martins +Date: Sat, 1 Apr 2023 21:23:31 +0100 +Subject: [PATCH 3/3] enable shared caches for cortex-r + +Signed-off-by: Jose Martins +--- + arch/arm/core/mpu/arm_mpu.c | 2 +- + arch/arm64/core/cortex_r/arm_mpu.c | 2 +- + include/zephyr/arch/arm/mpu/arm_mpu_v8.h | 8 ++++---- + 3 files changed, 6 insertions(+), 6 deletions(-) + +diff --git a/arch/arm/core/mpu/arm_mpu.c b/arch/arm/core/mpu/arm_mpu.c +index 9b2feffe5e..d49a7b6306 100644 +--- a/arch/arm/core/mpu/arm_mpu.c ++++ b/arch/arm/core/mpu/arm_mpu.c +@@ -230,7 +230,7 @@ void arm_core_mpu_enable(void) + uint32_t val; + + val = __get_SCTLR(); +- val |= SCTLR_MPU_ENABLE; ++ val |= SCTLR_MPU_ENABLE | SCTLR_C_BIT | SCTLR_I_BIT; + __set_SCTLR(val); + + /* Make sure that all the registers are set before proceeding */ +diff --git a/arch/arm64/core/cortex_r/arm_mpu.c b/arch/arm64/core/cortex_r/arm_mpu.c +index e303a7c037..c0d2395590 100644 +--- a/arch/arm64/core/cortex_r/arm_mpu.c ++++ b/arch/arm64/core/cortex_r/arm_mpu.c +@@ -96,7 +96,7 @@ FUNC_NO_STACK_PROTECTOR void arm_core_mpu_enable(void) + uint64_t val; + + val = read_sctlr_el1(); +- val |= SCTLR_M_BIT; ++ val |= SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT; + write_sctlr_el1(val); + barrier_dsync_fence_full(); + barrier_isync_fence_full(); +diff --git a/include/zephyr/arch/arm/mpu/arm_mpu_v8.h b/include/zephyr/arch/arm/mpu/arm_mpu_v8.h +index cf60cca99d..f797ab6682 100644 +--- a/include/zephyr/arch/arm/mpu/arm_mpu_v8.h ++++ b/include/zephyr/arch/arm/mpu/arm_mpu_v8.h +@@ -198,7 +198,7 @@ + #define REGION_RAM_ATTR(limit) \ + { \ + .rbar = NOT_EXEC | \ +- P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \ ++ P_RW_U_NA_Msk | INNER_SHAREABLE_Msk, /* AP, XN, SH */ \ + /* Cache-ability */ \ + .mair_idx = MPU_MAIR_INDEX_SRAM, \ + .r_limit = limit - 1, /* Region Limit */ \ +@@ -206,7 +206,7 @@ + + #define REGION_RAM_TEXT_ATTR(limit) \ + { \ +- .rbar = P_RO_U_RO_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \ ++ .rbar = P_RO_U_RO_Msk | INNER_SHAREABLE_Msk, /* AP, XN, SH */ \ + /* Cache-ability */ \ + .mair_idx = MPU_MAIR_INDEX_SRAM, \ + .r_limit = limit - 1, /* Region Limit */ \ +@@ -215,7 +215,7 @@ + #define REGION_RAM_RO_ATTR(limit) \ + { \ + .rbar = NOT_EXEC | \ +- P_RO_U_RO_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \ ++ P_RO_U_RO_Msk | INNER_SHAREABLE_Msk, /* AP, XN, SH */ \ + /* Cache-ability */ \ + .mair_idx = MPU_MAIR_INDEX_SRAM, \ + .r_limit = limit - 1, /* Region Limit */ \ +@@ -266,7 +266,7 @@ + #define REGION_RAM_ATTR(base, size) \ + {\ + .rbar = IF_ENABLED(CONFIG_XIP, (NOT_EXEC |)) \ +- P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \ ++ P_RW_U_NA_Msk | INNER_SHAREABLE_Msk, /* AP, XN, SH */ \ + /* Cache-ability */ \ + .mair_idx = MPU_MAIR_INDEX_SRAM, \ + .r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */ \ +-- +2.34.1 +