From 878ad2b2ed85b8ed383a63e32650ee9363c624d8 Mon Sep 17 00:00:00 2001 From: Diogo Costa Date: Mon, 9 Oct 2023 09:49:34 +0100 Subject: [PATCH] fix(verbose): improve error handling for interrupt reservation Signed-off-by: Diogo Costa --- src/arch/armv8/gic.c | 2 +- src/arch/riscv/iommu.c | 2 +- src/arch/riscv/sbi.c | 2 +- src/core/interrupts.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/arch/armv8/gic.c b/src/arch/armv8/gic.c index c434be0f3..f2027a6af 100644 --- a/src/arch/armv8/gic.c +++ b/src/arch/armv8/gic.c @@ -70,7 +70,7 @@ void gicd_init() if(!interrupts_reserve(platform.arch.gic.maintenance_id, gic_maintenance_handler)) { - ERROR("Failed to assign GIC maintenance interrupt"); + ERROR("Failed to reserve GIC maintenance interrupt"); } } diff --git a/src/arch/riscv/iommu.c b/src/arch/riscv/iommu.c index db31db885..494fa9c9c 100644 --- a/src/arch/riscv/iommu.c +++ b/src/arch/riscv/iommu.c @@ -335,7 +335,7 @@ void rv_iommu_init(void) // Allocate IRQ for FQ if(!interrupts_reserve(platform.arch.iommu.fq_irq_id, rv_iommu_fq_irq_handler)) { - ERROR("Failed to assign IOMMU FQ interrupt"); + ERROR("Failed to reserve IOMMU FQ interrupt"); } interrupts_cpu_enable(platform.arch.iommu.fq_irq_id, true); diff --git a/src/arch/riscv/sbi.c b/src/arch/riscv/sbi.c index 85f395b22..96522cae0 100644 --- a/src/arch/riscv/sbi.c +++ b/src/arch/riscv/sbi.c @@ -477,6 +477,6 @@ void sbi_init() } if(!interrupts_reserve(TIMR_INT_ID, sbi_timer_irq_handler)) { - ERROR("Failed to assign SBI TIMR_INT_ID interrupt"); + ERROR("Failed to reserve SBI TIMR_INT_ID interrupt"); } } diff --git a/src/core/interrupts.c b/src/core/interrupts.c index 346e0f9b9..96f381126 100644 --- a/src/core/interrupts.c +++ b/src/core/interrupts.c @@ -42,7 +42,7 @@ inline void interrupts_init() if (cpu()->id == CPU_MASTER) { if(!interrupts_reserve(IPI_CPU_MSG, cpu_msg_handler)) { - ERROR("Failed to assign IPI_CPU_MSG interrupt"); + ERROR("Failed to reserve IPI_CPU_MSG interrupt"); } }