From d7010d08b1bde7c0e08173da84cca1cc15905c00 Mon Sep 17 00:00:00 2001 From: ElectroQuanta <29806215+ElectroQuanta@users.noreply.github.com> Date: Thu, 10 Oct 2024 01:20:52 +0100 Subject: [PATCH] FIX: PL011 RPi4 UART configuration - Page alignment is required for Bao; all UARTs except for UART0 in the RPi4 are not page aligned, thus requiring an offset. This must be defined by the platform's user (plat/platform.h). - UART_CLK must be overridable and defined by the platform's user (plat/platform.h): in RPi4 PL011 run at 48 MHz Signed-off-by: ElectroQuanta <29806215+ElectroQuanta@users.noreply.github.com> --- .../drivers/pl011_uart/inc/drivers/pl011_uart.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/platform/drivers/pl011_uart/inc/drivers/pl011_uart.h b/src/platform/drivers/pl011_uart/inc/drivers/pl011_uart.h index e62da37d4..a9320f955 100644 --- a/src/platform/drivers/pl011_uart/inc/drivers/pl011_uart.h +++ b/src/platform/drivers/pl011_uart/inc/drivers/pl011_uart.h @@ -8,6 +8,11 @@ #include +#include +#ifndef PL011_PAGE_OFFSET +#define PL011_PAGE_OFFSET (0x000) /**< offset in range of 0-0xFFF */ +#endif + /* UART Base Address (PL011) */ #define UART_BASE_0 0xFDF02000 @@ -28,8 +33,10 @@ #define NUM_UART 6 +#ifndef UART_CLK #define UART_CLK 19200000 -#define UART_BAUD_RATE 115200 +#endif +#define UART_BAUD_RATE 115200 /* UART Data Register */ @@ -177,6 +184,7 @@ /* UART (PL011) register structure */ struct Pl011_Uart_hw { + const uint8_t offset[PL011_PAGE_OFFSET]; // Offset for page alignment volatile uint32_t data; // UART Data Register volatile uint32_t status_error; // UART Receive Status Register/Error Clear // Register