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ocs_hal.h
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ocs_hal.h
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/*
* BSD LICENSE
*
* Copyright (c) 2011-2018 Broadcom. All Rights Reserved.
* The term "Broadcom" refers to Broadcom Inc. and/or its subsidiaries.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @file
* Defines the Hardware Abstraction Layer (HAL) interface functions.
*/
#ifndef _OCS_HAL_H
#define _OCS_HAL_H
#include "sli4.h"
#include "sli4_fc.h"
#include "ocs_hal_config.h"
#include "ocs_stats.h"
#include "ocs_array.h"
typedef struct ocs_hal_io_s ocs_hal_io_t;
#include "ocs_hal_workaround.h"
#if defined(OCS_INCLUDE_DEBUG)
#include "ocs_debug.h"
#else
#define ocs_queue_history_wq(...)
#define ocs_queue_history_cqe(...)
#define ocs_queue_history_init(...)
#define ocs_queue_history_free(...)
#endif
/**
* @brief HAL queue forward declarations
*/
typedef struct hal_eq_s hal_eq_t;
typedef struct hal_cq_s hal_cq_t;
typedef struct hal_mq_s hal_mq_t;
typedef struct hal_wq_s hal_wq_t;
typedef struct hal_rq_s hal_rq_t;
typedef struct hal_rq_grp_s hal_rq_grp_t;
/* HAL asserts/verify
*
*/
extern void _ocs_hal_assert(const char *cond, const char *filename, int linenum);
extern void _ocs_hal_verify(const char *cond, const char *filename, int linenum);
#if defined(HAL_NDEBUG)
#define ocs_hal_assert(cond)
#define ocs_hal_verify(cond, ...)
#else
#define ocs_hal_assert(cond) \
do { \
if ((!(cond))) { \
_ocs_hal_assert(#cond, __FILE__, __LINE__); \
} \
} while (0)
#define ocs_hal_verify(cond, ...) \
do { \
if ((!(cond))) { \
_ocs_hal_verify(#cond, __FILE__, __LINE__); \
return __VA_ARGS__; \
} \
} while (0)
#endif
#define ocs_hal_verify_arg(cond) ocs_hal_verify(cond, OCS_HAL_RTN_INVALID_ARG)
/*
* HAL completion loop control parameters.
*
* The HAL completion loop must terminate periodically to keep the OS happy. The
* loop terminates when a predefined time has elapsed, but to keep the overhead of
* computing time down, the time is only checked after a number of loop iterations
* has completed.
*
* OCS_HAL_TIMECHECK_ITERATIONS number of loop iterations between time checks
*
*/
#define OCS_HAL_TIMECHECK_ITERATIONS 100
#define OCS_HAL_MAX_NUM_MQ 1
#define OCS_HAL_MAX_MRQ_SETS 2
#define OCE_HAL_MAX_NUM_MRQ_PAIRS 16 // MAX pairs in MRQ SET
/* Max we have 8 RX filters and two can be used for MRQ set of 16.
* So total MAX_RQ_PAIRS is 6(normal RQ) + (2 * 16)Sets = 38 RQ Pairs */
#define OCS_HAL_MAX_RQ_PAIRS 38
#define OCS_HAL_MAX_NUM_RQ (OCS_HAL_MAX_RQ_PAIRS * 2)
#define OCS_HAL_MAX_NUM_EQ 128
#define OCS_HAL_MAX_NUM_WQ 128
#define OCS_HAL_MAX_WQ_CLASS 4
#define OCS_HAL_MAX_WQ_CPU 128
/*
* A CQ will be assinged to each WQ (CQ must have 2X entries of the WQ for abort
* processing), plus a separate one for each RQ PAIR and one for MQ
*/
#define OCS_HAL_MAX_NUM_CQ ((OCS_HAL_MAX_NUM_WQ*2) + 1 + (OCS_HAL_MAX_RQ_PAIRS))
/*
* Q hash - size is the maximum of all the queue sizes, rounded up to the next
* power of 2
*/
#define OCS_HAL_Q_HASH_SIZE B32_NEXT_POWER_OF_2(OCS_MAX(OCS_HAL_MAX_NUM_MQ, OCS_MAX(OCS_HAL_MAX_NUM_RQ, \
OCS_MAX(OCS_HAL_MAX_NUM_EQ, OCS_MAX(OCS_HAL_MAX_NUM_WQ, \
OCS_HAL_MAX_NUM_CQ)))))
#define OCS_HAL_RQ_HEADER_SIZE 128
#define OCS_HAL_RQ_HEADER_INDEX 0
/**
* @brief Options for ocs_hal_command().
*/
enum {
OCS_CMD_POLL, /**< command executes synchronously and busy-waits for completion */
OCS_CMD_NOWAIT, /**< command executes asynchronously. Uses callback */
};
typedef enum {
OCS_HAL_RTN_SUCCESS = 0,
OCS_HAL_RTN_SUCCESS_SYNC = 1,
OCS_HAL_RTN_ERROR = -1,
OCS_HAL_RTN_NO_RESOURCES = -2,
OCS_HAL_RTN_NO_MEMORY = -3,
OCS_HAL_RTN_IO_NOT_ACTIVE = -4,
OCS_HAL_RTN_IO_ABORT_IN_PROGRESS = -5,
OCS_HAL_RTN_IO_PORT_OWNED_ALREADY_ABORTED = -6,
OCS_HAL_RTN_INVALID_ARG = -7,
} ocs_hal_rtn_e;
#define OCS_HAL_RTN_IS_ERROR(e) ((e) < 0)
typedef enum {
OCS_HAL_RESET_FUNCTION,
OCS_HAL_RESET_FIRMWARE,
OCS_HAL_RESET_MAX
} ocs_hal_reset_e;
typedef enum {
OCS_HAL_N_IO,
OCS_HAL_N_SGL,
OCS_HAL_MAX_IO,
OCS_HAL_MAX_SGE,
OCS_HAL_MAX_SGL,
OCS_HAL_MAX_NODES,
OCS_HAL_MAX_RQ_ENTRIES,
OCS_HAL_TOPOLOGY, /**< auto, nport, loop */
OCS_HAL_WWN_NODE,
OCS_HAL_WWN_PORT,
OCS_HAL_FW_REV,
OCS_HAL_FW_REV2,
OCS_HAL_IPL,
OCS_HAL_VPD,
OCS_HAL_VPD_LEN,
OCS_HAL_MODE, /**< initiator, target, both */
OCS_HAL_LINK_SPEED,
OCS_HAL_IF_TYPE,
OCS_HAL_SLI_REV,
OCS_HAL_SLI_FAMILY,
OCS_HAL_RQ_PROCESS_LIMIT,
OCS_HAL_RQ_DEFAULT_BUFFER_SIZE,
OCS_HAL_AUTO_XFER_RDY_CAPABLE,
OCS_HAL_AUTO_XFER_RDY_XRI_CNT,
OCS_HAL_AUTO_XFER_RDY_SIZE,
OCS_HAL_AUTO_XFER_RDY_BLK_SIZE,
OCS_HAL_AUTO_XFER_RDY_T10_ENABLE,
OCS_HAL_AUTO_XFER_RDY_P_TYPE,
OCS_HAL_AUTO_XFER_RDY_REF_TAG_IS_LBA,
OCS_HAL_AUTO_XFER_RDY_APP_TAG_VALID,
OCS_HAL_AUTO_XFER_RDY_APP_TAG_VALUE,
OCS_HAL_DIF_CAPABLE,
OCS_HAL_DIF_SEED,
OCS_HAL_DIF_MODE,
OCS_HAL_DIF_MULTI_SEPARATE,
OCS_HAL_DUMP_MAX_SIZE,
OCS_HAL_DUMP_READY,
OCS_HAL_DUMP_PRESENT,
OCS_HAL_RESET_REQUIRED,
OCS_HAL_FW_ERROR,
OCS_HAL_FW_READY,
OCS_HAL_HIGH_LOGIN_MODE,
OCS_HAL_PREREGISTER_SGL,
OCS_HAL_HW_REV1,
OCS_HAL_HW_REV2,
OCS_HAL_HW_REV3,
OCS_HAL_LINKCFG,
OCS_HAL_ETH_LICENSE,
OCS_HAL_LINK_MODULE_TYPE,
OCS_HAL_NUM_CHUTES,
OCS_HAL_WAR_VERSION,
OCS_HAL_DISABLE_AR_TGT_DIF,
OCS_HAL_EMULATE_I_ONLY_AAB, /**< emulate IAAB=0 for initiator-commands only */
OCS_HAL_EMULATE_TARGET_WQE_TIMEOUT, /**< enable driver timeouts for target WQEs */
OCS_HAL_LINK_CONFIG_SPEED,
OCS_HAL_CONFIG_TOPOLOGY,
OCS_HAL_BOUNCE,
OCS_HAL_PORTNUM,
OCS_HAL_BIOS_VERSION_STRING,
OCS_HAL_SGL_CHAINING_CAPABLE,
OCS_HAL_SGL_CHAINING_ALLOWED,
OCS_HAL_SGL_CHAINING_HOST_ALLOCATED,
OCS_HAL_SEND_FRAME_CAPABLE,
OCS_HAL_FILTER_DEF,
OCS_ESOC,
} ocs_hal_property_e;
enum {
OCS_HAL_TOPOLOGY_AUTO,
OCS_HAL_TOPOLOGY_NPORT,
OCS_HAL_TOPOLOGY_LOOP,
OCS_HAL_TOPOLOGY_NONE,
OCS_HAL_TOPOLOGY_MAX
};
enum {
OCS_HAL_MODE_INITIATOR,
OCS_HAL_MODE_TARGET,
OCS_HAL_MODE_BOTH,
OCS_HAL_MODE_MAX
};
/**
* @brief Port protocols
*/
typedef enum {
OCS_HAL_PORT_PROTOCOL_ISCSI,
OCS_HAL_PORT_PROTOCOL_FCOE,
OCS_HAL_PORT_PROTOCOL_FC,
OCS_HAL_PORT_PROTOCOL_OTHER,
} ocs_hal_port_protocol_e;
#define OCS_HAL_MAX_PROFILES 40
/**
* @brief A Profile Descriptor
*/
typedef struct {
uint32_t profile_index;
uint32_t profile_id;
char profile_description[512];
} ocs_hal_profile_descriptor_t;
/**
* @brief A Profile List
*/
typedef struct {
uint32_t num_descriptors;
ocs_hal_profile_descriptor_t descriptors[OCS_HAL_MAX_PROFILES];
} ocs_hal_profile_list_t;
/**
* @brief Defines DIF operation modes
*/
enum {
OCS_HAL_DIF_MODE_INLINE,
OCS_HAL_DIF_MODE_SEPARATE,
};
/**
* @brief Defines the type of RQ buffer
*/
typedef enum {
OCS_HAL_RQ_BUFFER_TYPE_HDR,
OCS_HAL_RQ_BUFFER_TYPE_PAYLOAD,
OCS_HAL_RQ_BUFFER_TYPE_MAX,
} ocs_hal_rq_buffer_type_e;
/**
* @brief Defines a wrapper for the RQ payload buffers so that we can place it
* back on the proper queue.
*/
typedef struct {
uint16_t rqindex;
ocs_dma_t dma;
} ocs_hal_rq_buffer_t;
/**
* @brief T10 DIF operations.
*/
typedef enum {
OCS_HAL_DIF_OPER_DISABLED,
OCS_HAL_SGE_DIF_OP_IN_NODIF_OUT_CRC,
OCS_HAL_SGE_DIF_OP_IN_CRC_OUT_NODIF,
OCS_HAL_SGE_DIF_OP_IN_NODIF_OUT_CHKSUM,
OCS_HAL_SGE_DIF_OP_IN_CHKSUM_OUT_NODIF,
OCS_HAL_SGE_DIF_OP_IN_CRC_OUT_CRC,
OCS_HAL_SGE_DIF_OP_IN_CHKSUM_OUT_CHKSUM,
OCS_HAL_SGE_DIF_OP_IN_CRC_OUT_CHKSUM,
OCS_HAL_SGE_DIF_OP_IN_CHKSUM_OUT_CRC,
OCS_HAL_SGE_DIF_OP_IN_RAW_OUT_RAW,
} ocs_hal_dif_oper_e;
#define OCS_HAL_DIF_OPER_PASS_THRU OCS_HAL_SGE_DIF_OP_IN_CRC_OUT_CRC
#define OCS_HAL_DIF_OPER_STRIP OCS_HAL_SGE_DIF_OP_IN_CRC_OUT_NODIF
#define OCS_HAL_DIF_OPER_INSERT OCS_HAL_SGE_DIF_OP_IN_NODIF_OUT_CRC
/**
* @brief T10 DIF block sizes.
*/
typedef enum {
OCS_HAL_DIF_BK_SIZE_512,
OCS_HAL_DIF_BK_SIZE_1024,
OCS_HAL_DIF_BK_SIZE_2048,
OCS_HAL_DIF_BK_SIZE_4096,
OCS_HAL_DIF_BK_SIZE_520,
OCS_HAL_DIF_BK_SIZE_4104,
OCS_HAL_DIF_BK_SIZE_NA = 0
} ocs_hal_dif_blk_size_e;
/**
* @brief Link configurations.
*/
typedef enum {
OCS_HAL_LINKCFG_4X10G = 0,
OCS_HAL_LINKCFG_1X40G,
OCS_HAL_LINKCFG_2X16G,
OCS_HAL_LINKCFG_4X8G,
OCS_HAL_LINKCFG_4X1G,
OCS_HAL_LINKCFG_2X10G,
OCS_HAL_LINKCFG_2X10G_2X8G,
/* must be last */
OCS_HAL_LINKCFG_NA,
} ocs_hal_linkcfg_e;
/**
* @brief link module types
*
* (note: these just happen to match SLI4 values)
*/
enum {
OCS_HAL_LINK_MODULE_TYPE_1GB = 0x0004,
OCS_HAL_LINK_MODULE_TYPE_2GB = 0x0008,
OCS_HAL_LINK_MODULE_TYPE_4GB = 0x0040,
OCS_HAL_LINK_MODULE_TYPE_8GB = 0x0080,
OCS_HAL_LINK_MODULE_TYPE_10GB = 0x0100,
OCS_HAL_LINK_MODULE_TYPE_16GB = 0x0200,
OCS_HAL_LINK_MODULE_TYPE_32GB = 0x0400,
};
/**
* @brief T10 DIF information passed to the transport.
*/
typedef struct ocs_hal_dif_info_s {
ocs_hal_dif_oper_e dif_oper;
ocs_hal_dif_blk_size_e blk_size;
uint32_t ref_tag_cmp;
uint32_t ref_tag_repl;
uint32_t app_tag_cmp:16,
app_tag_repl:16;
uint32_t check_ref_tag:1,
check_app_tag:1,
check_guard:1,
auto_incr_ref_tag:1,
repl_app_tag:1,
repl_ref_tag:1,
dif:2,
dif_separate:1,
/* If the APP TAG is 0xFFFF, disable checking the REF TAG and CRC fields */
disable_app_ffff:1,
/* if the APP TAG is 0xFFFF and REF TAG is 0xFFFF_FFFF, disable checking the received CRC field. */
disable_app_ref_ffff:1,
:21;
uint16_t dif_seed;
} ocs_hal_dif_info_t;
typedef enum {
OCS_HAL_ELS_REQ, /**< ELS request */
OCS_HAL_ELS_RSP, /**< ELS response */
OCS_HAL_ELS_RSP_SID, /**< ELS response, override the S_ID */
OCS_HAL_FC_CT, /**< FC Common Transport */
OCS_HAL_FC_CT_RSP, /**< FC Common Transport Response */
OCS_HAL_BLS_ACC, /**< BLS accept (BA_ACC) */
OCS_HAL_BLS_ACC_SID, /**< BLS accept (BA_ACC), override the S_ID */
OCS_HAL_BLS_RJT, /**< BLS reject (BA_RJT) */
OCS_HAL_BCAST, /**< Class 3 broadcast sequence */
OCS_HAL_IO_TARGET_READ,
OCS_HAL_IO_TARGET_WRITE,
OCS_HAL_IO_TARGET_RSP,
OCS_HAL_IO_INITIATOR_READ,
OCS_HAL_IO_INITIATOR_WRITE,
OCS_HAL_IO_INITIATOR_NODATA,
OCS_HAL_IO_DNRX_REQUEUE,
OCS_HAL_IO_MAX,
} ocs_hal_io_type_e;
typedef enum {
OCS_HAL_IO_STATE_FREE,
OCS_HAL_IO_STATE_INUSE,
OCS_HAL_IO_STATE_WAIT_FREE,
OCS_HAL_IO_STATE_WAIT_SEC_HIO,
} ocs_hal_io_state_e;
/* Descriptive strings for the HAL IO request types (note: these must always
* match up with the ocs_hal_io_type_e declaration) */
#define OCS_HAL_IO_TYPE_STRINGS \
"ELS request", \
"ELS response", \
"ELS response(set SID)", \
"FC CT request", \
"BLS accept", \
"BLS accept(set SID)", \
"BLS reject", \
"target read", \
"target write", \
"target response", \
"initiator read", \
"initiator write", \
"initiator nodata",
/**
* @brief HAL command context.
*
* Stores the state for the asynchronous commands sent to the hardware.
*/
typedef struct ocs_command_ctx_s {
ocs_list_t link;
/**< Callback function */
int32_t (*cb)(struct ocs_hal_s *, int32_t, uint8_t *, void *);
void *arg; /**< Argument for callback */
uint8_t *buf; /**< buffer holding command / results */
void *ctx; /**< upper layer context */
} ocs_command_ctx_t;
typedef struct ocs_hal_sgl_s {
uintptr_t addr;
size_t len;
} ocs_hal_sgl_t;
/**
* @brief HAL callback type
*
* Typedef for HAL "done" callback.
*/
typedef int32_t (*ocs_hal_done_t)(struct ocs_hal_io_s *, ocs_remote_node_t *, uint32_t len, int32_t status, uint32_t ext, void *ul_arg);
typedef union ocs_hal_io_param_u {
struct {
uint16_t ox_id;
uint16_t rx_id;
uint8_t payload[12]; /**< big enough for ABTS BA_ACC */
} bls;
struct {
uint32_t s_id;
uint16_t ox_id;
uint16_t rx_id;
uint8_t payload[12]; /**< big enough for ABTS BA_ACC */
} bls_sid;
struct {
uint8_t r_ctl;
uint8_t type;
uint8_t df_ctl;
uint8_t timeout;
} bcast;
struct {
uint16_t ox_id;
uint8_t timeout;
} els;
struct {
uint32_t s_id;
uint16_t ox_id;
uint8_t timeout;
} els_sid;
struct {
uint8_t r_ctl;
uint8_t type;
uint8_t df_ctl;
uint8_t timeout;
} fc_ct;
struct {
uint8_t r_ctl;
uint8_t type;
uint8_t df_ctl;
uint8_t timeout;
uint16_t ox_id;
} fc_ct_rsp;
struct {
uint32_t offset;
uint16_t ox_id;
uint16_t flags;
uint8_t cs_ctl;
ocs_hal_dif_oper_e dif_oper;
ocs_hal_dif_blk_size_e blk_size;
uint8_t timeout;
} fcp_tgt;
struct {
ocs_dma_t *cmnd;
ocs_dma_t *rsp;
ocs_hal_dif_oper_e dif_oper;
ocs_hal_dif_blk_size_e blk_size;
uint32_t cmnd_size;
uint16_t flags;
uint8_t timeout;
uint32_t first_burst;
} fcp_ini;
} ocs_hal_io_param_t;
/**
* @brief WQ steering mode
*/
typedef enum {
OCS_HAL_WQ_STEERING_CLASS,
OCS_HAL_WQ_STEERING_REQUEST,
OCS_HAL_WQ_STEERING_CPU,
} ocs_hal_wq_steering_e;
/**
* @brief HAL wqe object
*/
typedef struct {
uint32_t abort_wqe_submit_needed:1, /**< set if abort wqe needs to be submitted */
send_abts:1, /**< set to 1 to have hardware to automatically send ABTS */
auto_xfer_rdy_dnrx:1, /**< TRUE if DNRX was set on this IO */
:29;
uint32_t id;
uint32_t abort_reqtag;
ocs_list_link_t link;
uint8_t *wqebuf; /**< work queue entry buffer */
} ocs_hal_wqe_t;
/**
* @brief HAL IO object.
*
* Stores the per-IO information necessary for both the lower (SLI) and upper
* layers (ocs).
*/
struct ocs_hal_io_s {
// Owned by HAL
ocs_list_link_t link; /**< used for busy, wait_free, free lists */
ocs_list_link_t wqe_link; /**< used for timed_wqe list */
ocs_list_link_t dnrx_link; /**< used for io posted dnrx list */
ocs_hal_io_state_e state; /**< state of IO: free, busy, wait_free */
ocs_hal_wqe_t wqe; /**< Work queue object, with link for pending */
ocs_lock_t axr_lock; /**< Lock to synchronize TRSP and AXT Data/Cmd Cqes */
ocs_hal_t *hal; /**< pointer back to hardware context */
ocs_remote_node_t *rnode;
struct ocs_hal_auto_xfer_rdy_buffer_s *axr_buf;
ocs_dma_t xfer_rdy;
uint16_t type;
uint32_t port_owned_abort_count; /**< IO abort count */
hal_wq_t *wq; /**< WQ assigned to the exchange */
uint32_t xbusy; /**< Exchange is active in FW */
ocs_hal_done_t done; /**< Function called on IO completion */
void *arg; /**< argument passed to "IO done" callback */
ocs_hal_done_t abort_done; /**< Function called on abort completion */
void *abort_arg; /**< argument passed to "abort done" callback */
ocs_ref_t ref; /**< refcount object */
size_t length; /**< needed for bug O127585: length of IO */
uint8_t tgt_wqe_timeout; /**< timeout value for target WQEs */
uint64_t submit_ticks; /**< timestamp when current WQE was submitted */
uint32_t status_saved:1, /**< if TRUE, latched status should be returned */
abort_in_progress:1, /**< if TRUE, abort is in progress */
quarantine:1, /**< set if IO to be quarantined */
quarantine_first_phase:1, /**< set if first phase of IO */
is_port_owned:1, /**< set if POST_XRI was used to send XRI to th chip */
auto_xfer_rdy_dnrx:1, /**< TRUE if DNRX was set on this IO */
:26;
uint32_t saved_status; /**< latched status */
uint32_t saved_len; /**< latched length */
uint32_t saved_ext; /**< latched extended status */
hal_eq_t *eq; /**< EQ that this HIO came up on */
ocs_hal_wq_steering_e wq_steering; /**< WQ steering mode request */
uint8_t wq_class; /**< WQ class if steering mode is Class */
// Owned by SLI layer
uint16_t reqtag; /**< request tag for this HAL IO */
uint32_t abort_reqtag; /**< request tag for an abort of this HAL IO (note: this is a 32 bit value
to allow us to use UINT32_MAX as an uninitialized value) */
uint32_t indicator; /**< XRI */
ocs_dma_t def_sgl; /**< default scatter gather list */
uint32_t def_sgl_count; /**< count of SGEs in default SGL */
ocs_dma_t *sgl; /**< pointer to current active SGL */
uint32_t sgl_count; /**< count of SGEs in io->sgl */
uint32_t first_data_sge; /**< index of first data SGE */
ocs_dma_t *ovfl_sgl; /**< overflow SGL */
uint32_t ovfl_sgl_count; /**< count of SGEs in default SGL */
sli4_lsp_sge_t *ovfl_lsp; /**< pointer to overflow segment length */
ocs_hal_io_t *ovfl_io; /**< Used for SGL chaining on skyhawk */
uint32_t n_sge; /**< number of active SGEs */
uint32_t sge_offset;
/* BZ 161832 Workaround: */
struct ocs_hal_io_s *sec_hio; /**< Secondary HAL IO context */
ocs_hal_io_param_t sec_iparam; /**< Secondary HAL IO context saved iparam */
uint32_t sec_len; /**< Secondary HAL IO context saved len */
/* Owned by upper layer */
void *ul_io; /**< where upper layer can store reference to its IO */
};
typedef enum {
OCS_HAL_PORT_INIT,
OCS_HAL_PORT_SHUTDOWN,
OCS_HAL_PORT_SET_LINK_CONFIG,
} ocs_hal_port_e;
/**
* @brief Fabric/Domain events
*/
typedef enum {
OCS_HAL_DOMAIN_ALLOC_OK, /**< domain successfully allocated */
OCS_HAL_DOMAIN_ALLOC_FAIL, /**< domain allocation failed */
OCS_HAL_DOMAIN_ATTACH_OK, /**< successfully attached to domain */
OCS_HAL_DOMAIN_ATTACH_FAIL, /**< domain attach failed */
OCS_HAL_DOMAIN_FREE_OK, /**< successfully freed domain */
OCS_HAL_DOMAIN_FREE_FAIL, /**< domain free failed */
OCS_HAL_DOMAIN_LOST, /**< previously discovered domain no longer available */
OCS_HAL_DOMAIN_FOUND, /**< new domain discovered */
OCS_HAL_DOMAIN_CHANGED, /**< previously discovered domain properties have changed */
} ocs_hal_domain_event_e;
typedef enum {
OCS_HAL_PORT_ALLOC_OK, /**< port successfully allocated */
OCS_HAL_PORT_ALLOC_FAIL, /**< port allocation failed */
OCS_HAL_PORT_ATTACH_OK, /**< successfully attached to port */
OCS_HAL_PORT_ATTACH_FAIL, /**< port attach failed */
OCS_HAL_PORT_FREE_OK, /**< successfully freed port */
OCS_HAL_PORT_FREE_FAIL, /**< port free failed */
} ocs_hal_port_event_e;
typedef enum {
OCS_HAL_NODE_ATTACH_OK,
OCS_HAL_NODE_ATTACH_FAIL,
OCS_HAL_NODE_FREE_OK,
OCS_HAL_NODE_FREE_FAIL,
OCS_HAL_NODE_FREE_ALL_OK,
OCS_HAL_NODE_FREE_ALL_FAIL,
} ocs_hal_remote_node_event_e;
typedef enum {
OCS_HAL_CB_DOMAIN,
OCS_HAL_CB_PORT,
OCS_HAL_CB_REMOTE_NODE,
OCS_HAL_CB_UNSOLICITED,
OCS_HAL_CB_BOUNCE,
OCS_HAL_CB_MAX, /**< must be last */
} ocs_hal_callback_e;
/**
* @brief HAL unsolicited callback status
*/
typedef enum {
OCS_HAL_UNSOL_SUCCESS,
OCS_HAL_UNSOL_ERROR,
OCS_HAL_UNSOL_ABTS_RCVD,
OCS_HAL_UNSOL_MAX, /**< must be last */
} ocs_hal_unsol_status_e;
/**
* @brief Node group rpi reference
*/
typedef struct {
ocs_atomic_t rpi_count;
ocs_atomic_t rpi_attached;
} ocs_hal_rpi_ref_t;
/**
* @brief HAL link stat types
*/
typedef enum {
OCS_HAL_LINK_STAT_LINK_FAILURE_COUNT,
OCS_HAL_LINK_STAT_LOSS_OF_SYNC_COUNT,
OCS_HAL_LINK_STAT_LOSS_OF_SIGNAL_COUNT,
OCS_HAL_LINK_STAT_PRIMITIVE_SEQ_COUNT,
OCS_HAL_LINK_STAT_INVALID_XMIT_WORD_COUNT,
OCS_HAL_LINK_STAT_CRC_COUNT,
OCS_HAL_LINK_STAT_PRIMITIVE_SEQ_TIMEOUT_COUNT,
OCS_HAL_LINK_STAT_ELASTIC_BUFFER_OVERRUN_COUNT,
OCS_HAL_LINK_STAT_ARB_TIMEOUT_COUNT,
OCS_HAL_LINK_STAT_ADVERTISED_RCV_B2B_CREDIT,
OCS_HAL_LINK_STAT_CURR_RCV_B2B_CREDIT,
OCS_HAL_LINK_STAT_ADVERTISED_XMIT_B2B_CREDIT,
OCS_HAL_LINK_STAT_CURR_XMIT_B2B_CREDIT,
OCS_HAL_LINK_STAT_RCV_EOFA_COUNT,
OCS_HAL_LINK_STAT_RCV_EOFDTI_COUNT,
OCS_HAL_LINK_STAT_RCV_EOFNI_COUNT,
OCS_HAL_LINK_STAT_RCV_SOFF_COUNT,
OCS_HAL_LINK_STAT_RCV_DROPPED_NO_AER_COUNT,
OCS_HAL_LINK_STAT_RCV_DROPPED_NO_RPI_COUNT,
OCS_HAL_LINK_STAT_RCV_DROPPED_NO_XRI_COUNT,
OCS_HAL_LINK_STAT_MAX, /**< must be last */
} ocs_hal_link_stat_e;
typedef enum {
OCS_HAL_HOST_STAT_TX_KBYTE_COUNT,
OCS_HAL_HOST_STAT_RX_KBYTE_COUNT,
OCS_HAL_HOST_STAT_TX_FRAME_COUNT,
OCS_HAL_HOST_STAT_RX_FRAME_COUNT,
OCS_HAL_HOST_STAT_TX_SEQ_COUNT,
OCS_HAL_HOST_STAT_RX_SEQ_COUNT,
OCS_HAL_HOST_STAT_TOTAL_EXCH_ORIG,
OCS_HAL_HOST_STAT_TOTAL_EXCH_RESP,
OCS_HAL_HOSY_STAT_RX_P_BSY_COUNT,
OCS_HAL_HOST_STAT_RX_F_BSY_COUNT,
OCS_HAL_HOST_STAT_DROP_FRM_DUE_TO_NO_RQ_BUF_COUNT,
OCS_HAL_HOST_STAT_EMPTY_RQ_TIMEOUT_COUNT,
OCS_HAL_HOST_STAT_DROP_FRM_DUE_TO_NO_XRI_COUNT,
OCS_HAL_HOST_STAT_EMPTY_XRI_POOL_COUNT,
OCS_HAL_HOST_STAT_MAX /* MUST BE LAST */
} ocs_hal_host_stat_e;
typedef enum {
OCS_HAL_STATE_UNINITIALIZED, /* power-on, no allocations, no initializations */
OCS_HAL_STATE_QUEUES_ALLOCATED, /* chip is reset, allocations are complete (queues not registered) */
OCS_HAL_STATE_ACTIVE, /* chip is up an running */
OCS_HAL_STATE_RESET_IN_PROGRESS, /* chip is being reset */
OCS_HAL_STATE_TEARDOWN_IN_PROGRESS, /* teardown has been started */
} ocs_hal_state_e;
/**
* @brief Defines a general FC sequence object, consisting of a header, payload buffers
* and a HAL IO in the case of port owned XRI
*/
typedef struct {
ocs_hal_t *hal; /**< HAL that owns this sequence */
/* sequence information */
uint8_t fcfi; /**< FCFI associated with sequence */
uint8_t auto_xrdy; /**< If auto XFER_RDY was generated */
uint8_t out_of_xris; /**< If IO would have been assisted if XRIs were available */
ocs_hal_rq_buffer_t *header;
ocs_hal_rq_buffer_t *payload; /**< received frame payload buffer */
/* other "state" information from the SRB (sequence coalescing) */
ocs_hal_unsol_status_e status;
uint32_t xri; /**< XRI associated with sequence; sequence coalescing only */
ocs_hal_io_t *hio; /**< HAL IO */
ocs_list_link_t link;
void *hal_priv; /**< HAL private context */
} ocs_hal_sequence_t;
/**
* @brief Structure to track optimized write buffers posted to chip owned XRIs.
*
* Note: The rqindex will be set the following "fake" indexes. This will be used
* when the buffer is returned via ocs_seq_free() to make the buffer available
* for re-use on another XRI.
*
* The dma->alloc pointer on the dummy header will be used to get back to this structure when the buffer is freed.
*
* More of these object may be allocated on the fly if more XRIs are pushed to the chip.
*/
#define OCS_HAL_RQ_INDEX_DUMMY_HDR 0xFF00
#define OCS_HAL_RQ_INDEX_DUMMY_DATA 0xFF01
typedef struct ocs_hal_auto_xfer_rdy_buffer_s {
fc_header_t hdr; /**< used to build a dummy data header for unsolicited processing */
ocs_hal_rq_buffer_t header; /**< Points to the dummy data header */
ocs_hal_rq_buffer_t payload; /**< received frame payload buffer */
ocs_hal_sequence_t seq; /**< sequence for passing the buffers */
uint8_t data_cqe;
uint8_t cmd_cqe;
/* fields saved from the command header that are needed when the data arrives */
uint8_t fcfi;
/* To handle outof order completions save AXR cmd and data cqes */
uint8_t call_axr_cmd;
uint8_t call_axr_data;
ocs_hal_sequence_t *cmd_seq;
} ocs_hal_auto_xfer_rdy_buffer_t;
/**
* @brief Node group rpi reference
*/
typedef struct {
uint8_t overflow;
uint32_t counter;
} ocs_hal_link_stat_counts_t;
/**
* @brief HAL object describing fc host stats
*/
typedef struct {
uint32_t counter;
} ocs_hal_host_stat_counts_t;
#define TID_HASH_BITS 8
#define TID_HASH_LEN (1U << TID_HASH_BITS)
typedef struct ocs_hal_iopt_s {
char name[32];
uint32_t instance_index;
ocs_thread_t iopt_thread;
ocs_cbuf_t *iopt_free_queue; // multiple reader, multiple writer
ocs_cbuf_t *iopt_work_queue;
ocs_array_t *iopt_cmd_array;
} ocs_hal_iopt_t;
typedef enum {
HAL_CQ_HANDLER_LOCAL,
HAL_CQ_HANDLER_THREAD,
} hal_cq_handler_e;
#include "ocs_hal_queues.h"
/**
* @brief Stucture used for the hash lookup of queue IDs
*/
typedef struct {
uint32_t id:16,
in_use:1,
index:15;
} ocs_queue_hash_t;
/**
* @brief Define the fields required to implement the skyhawk DIF quarantine.
*/
#define OCS_HAL_QUARANTINE_QUEUE_DEPTH 4
typedef struct {
uint32_t quarantine_index;
ocs_hal_io_t *quarantine_ios[OCS_HAL_QUARANTINE_QUEUE_DEPTH];
} ocs_quarantine_info_t;
/**
* @brief Define the WQ callback object
*/
typedef struct {
uint16_t instance_index; /**< use for request tag */
void (*callback)(void *arg, uint8_t *cqe, int32_t status);
void *arg;
} hal_wq_callback_t;
/**
* @brief HAL object
*/
struct ocs_hal_s {
ocs_os_handle_t os;
sli4_t sli;
uint16_t ulp_start;
uint16_t ulp_max;
uint32_t dump_size;
ocs_hal_state_e state;
uint8_t hal_setup_called;
uint8_t sliport_healthcheck;
uint16_t watchdog_timeout;
/** HAL configuration, subject to ocs_hal_set() */
struct {
uint32_t n_eq; /**< number of event queues */
uint32_t n_cq; /**< number of completion queues */
uint32_t n_mq; /**< number of mailbox queues */
uint32_t n_rq; /**< number of receive queues */
uint32_t n_wq; /**< number of work queues */
uint32_t n_io; /**< total number of IO objects */
uint32_t n_sgl;/**< length of SGL */
uint32_t speed; /** requested link speed in Mbps */
uint32_t topology; /** requested link topology */
uint32_t rq_default_buffer_size; /** size of the buffers for first burst */
uint32_t auto_xfer_rdy_xri_cnt; /** Initial XRIs to post to chip at initialization */
uint32_t auto_xfer_rdy_size; /** max size IO to use with this feature */
uint8_t auto_xfer_rdy_blk_size_chip; /** block size to use with this feature */
uint8_t esoc;
uint16_t dif_seed; /** The seed for the DIF CRC calculation */
uint16_t auto_xfer_rdy_app_tag_value;
uint8_t dif_mode; /**< DIF mode to use */
uint8_t i_only_aab; /** Enable initiator-only auto-abort */
uint8_t emulate_tgt_wqe_timeout; /** Enable driver target wqe timeouts */
uint32_t bounce:1;
const char *queue_topology;
uint8_t auto_xfer_rdy_t10_enable; /** Enable t10 PI for auto xfer ready */
uint8_t auto_xfer_rdy_p_type; /** p_type for auto xfer ready */
uint8_t auto_xfer_rdy_ref_tag_is_lba;
uint8_t auto_xfer_rdy_app_tag_valid;
uint32_t filter_def[SLI4_CMD_REG_FCFI_NUM_RQ_CFG];
} config;
/* calculated queue sizes for each type */
uint32_t num_qentries[SLI_QTYPE_MAX];
/* Storage for SLI queue objects */
sli4_queue_t wq[OCS_HAL_MAX_NUM_WQ];
sli4_queue_t rq[OCS_HAL_MAX_NUM_RQ];
uint16_t hal_rq_lookup[OCS_HAL_MAX_NUM_RQ];
sli4_queue_t mq[OCS_HAL_MAX_NUM_MQ];
sli4_queue_t cq[OCS_HAL_MAX_NUM_CQ];
sli4_queue_t eq[OCS_HAL_MAX_NUM_EQ];
/* HAL queue */
uint32_t eq_count;
uint32_t cq_count;
uint32_t mq_count;
uint32_t wq_count;
uint32_t rq_count; /**< count of SLI RQs */
ocs_list_t eq_list;
ocs_queue_hash_t cq_hash[OCS_HAL_Q_HASH_SIZE];
ocs_queue_hash_t rq_hash[OCS_HAL_Q_HASH_SIZE];
ocs_queue_hash_t wq_hash[OCS_HAL_Q_HASH_SIZE];
/* Storage for HAL queue objects */
hal_wq_t *hal_wq[OCS_HAL_MAX_NUM_WQ];
hal_rq_t *hal_rq[OCS_HAL_MAX_NUM_RQ];
hal_mq_t *hal_mq[OCS_HAL_MAX_NUM_MQ];
hal_cq_t *hal_cq[OCS_HAL_MAX_NUM_CQ];
hal_eq_t *hal_eq[OCS_HAL_MAX_NUM_EQ];
uint32_t hal_rq_count; /**< count of hal_rq[] entries */
bool hal_mrq_used;
ocs_varray_t *wq_class_array[OCS_HAL_MAX_WQ_CLASS]; /**< pool per class WQs */
ocs_varray_t *wq_cpu_array[OCS_HAL_MAX_WQ_CPU]; /**< pool per CPU WQs */
/* Sequence objects used in incoming frame processing */
ocs_array_t *seq_pool;
/* Auto XFER RDY Buffers - protect with io_lock */
uint32_t auto_xfer_rdy_enabled:1, /**< TRUE if auto xfer rdy is enabled */
:31;
ocs_pool_t *auto_xfer_rdy_buf_pool; /**< pool of ocs_hal_auto_xfer_rdy_buffer_t objects */
/** Maintain an ordered, linked list of outstanding HAL commands. */
ocs_lock_t cmd_lock;
ocs_list_t cmd_head;
ocs_list_t cmd_pending;
uint32_t cmd_head_count;
sli4_link_event_t link;
ocs_hal_linkcfg_e linkcfg; /**< link configuration setting */
uint32_t eth_license; /**< Ethernet license; to enable FCoE on Lancer */
struct {
/**
* Function + argument used to notify upper layer of domain events.
*
* The final argument to the callback is a generic data pointer:
* - ocs_domain_record_t on OCS_HAL_DOMAIN_FOUND
* - ocs_domain_t on OCS_HAL_DOMAIN_ALLOC_FAIL, OCS_HAL_DOMAIN_ALLOC_OK,
* OCS_HAL_DOMAIN_FREE_FAIL, OCS_HAL_DOMAIN_FREE_OK,
* OCS_HAL_DOMAIN_ATTACH_FAIL, OCS_HAL_DOMAIN_ATTACH_OK, and
* OCS_HAL_DOMAIN_LOST.
*/
int32_t (*domain)(void *, ocs_hal_domain_event_e, void *);
/**
* Function + argument used to notify upper layers of port events.
*
* The final argument to the callback is a pointer to the effected
* SLI port for all events.
*/
int32_t (*port)(void *, ocs_hal_port_event_e, void *);
/** Function + argument used to announce arrival of unsolicited frames */
int32_t (*unsolicited)(void *, ocs_hal_sequence_t *);
int32_t (*rnode)(void *, ocs_hal_remote_node_event_e, void *);
int32_t (*bounce)(void (*)(void *arg), void *arg, uint32_t s_id, uint32_t d_id, uint32_t ox_id);
} callback;
struct {
void *domain;
void *port;
void *unsolicited;
void *rnode;
void *bounce;
} args;
/* OCS domain objects index by FCFI */
int32_t first_domain_idx; /* Workaround for srb->fcfi == 0 */
ocs_domain_t *domains[SLI4_MAX_FCFI];
/* Table of FCFI values index by FCF_index */