From 1e6f0399e25bb76c2bc6509e0081a16306ec1610 Mon Sep 17 00:00:00 2001 From: kaamakshee Date: Thu, 15 Dec 2022 17:02:19 -0800 Subject: [PATCH 01/10] Idiv lzc optimization initial changes --- bsg_misc/bsg_idiv_iterative.v | 29 +++++++++---- bsg_misc/bsg_idiv_iterative_controller.v | 43 ++++++++++++++++--- testing/bsg_misc/bsg_idiv_iterative/Makefile | 18 +++++--- .../bsg_misc/bsg_idiv_iterative/sv.include | 5 +++ .../bsg_misc/bsg_idiv_iterative/unsigned.c | 6 ++- 5 files changed, 81 insertions(+), 20 deletions(-) create mode 100644 testing/bsg_misc/bsg_idiv_iterative/sv.include diff --git a/bsg_misc/bsg_idiv_iterative.v b/bsg_misc/bsg_idiv_iterative.v index db670126d..857cd8c63 100644 --- a/bsg_misc/bsg_idiv_iterative.v +++ b/bsg_misc/bsg_idiv_iterative.v @@ -45,6 +45,7 @@ module bsg_idiv_iterative #(parameter width_p=32, parameter bitstack_p=0, parame ,input yumi_i ); + // synopsys translate_off initial begin assert (bits_per_iter_p == 1 || bits_per_iter_p == 2) @@ -72,6 +73,7 @@ module bsg_idiv_iterative #(parameter width_p=32, parameter bitstack_p=0, parame ,.en_i (latch_signed_div_lo) ,.clk_i(clk_i) ); + //if the divisor is zero wire zero_divisor_li = ~(| opA_r); @@ -87,7 +89,12 @@ module bsg_idiv_iterative #(parameter width_p=32, parameter bitstack_p=0, parame ); wire [width_p:0] opB_mux, opC_mux; - wire [bits_per_iter_p + 1:0] opB_sel_lo, opC_sel_lo; + wire [3:0] opB_sel_lo, opC_sel_lo; + + + wire [$clog2(width_p)-1:0] div_shift; + + let mask(value, select, lsb) = ((2**select-1) & (value >> lsb)); if (bits_per_iter_p == 2) begin @@ -105,20 +112,20 @@ module bsg_idiv_iterative #(parameter width_p=32, parameter bitstack_p=0, parame end else begin - bsg_mux_one_hot #(.width_p(width_p+1), .els_p(3)) muxB - (.data_i( {opC_r, add1_out, {add1_out[width_p-1:0], opC_r[width_p]}} ) + bsg_mux_one_hot #(.width_p(width_p+1), .els_p(4)) muxB + (.data_i( {{mask(add1_out, div_shift+1, 0) << (width_p-div_shift) | mask(opC_r, width_p-div_shift, div_shift)}, opC_r, add1_out, {add1_out[width_p-1:0], opC_r[width_p]}} ) ,.data_o( opB_mux ) ,.sel_one_hot_i(opB_sel_lo) ); - bsg_mux_one_hot #(.width_p(width_p+1), .els_p(3)) muxC - (.data_i( {{dividend_msb, dividend_i},add1_out, {opC_r[width_p-1:0], ~add1_out[width_p]}} ) + bsg_mux_one_hot #(.width_p(width_p+1), .els_p(4)) muxC + (.data_i( {{(mask(opC_r, div_shift, 0) << (1+width_p-div_shift)) | (1< #include #include +#ifndef WIDTH #define WIDTH 4 +#endif +#ifndef ITERS #define ITERS 1 << (WIDTH*2) +#endif // #define ITERS 10000 // Function to compute quotient From 7a8b5a00c9e61191fcd3409084ccf334c0651419 Mon Sep 17 00:00:00 2001 From: Dan Petrisko Date: Mon, 14 Nov 2022 13:25:00 -0800 Subject: [PATCH 02/10] Fixing signed/unsigned --- testing/bsg_misc/bsg_idiv_iterative/README.md | 1 - testing/bsg_misc/bsg_idiv_iterative/test_bsg.v | 4 +--- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/testing/bsg_misc/bsg_idiv_iterative/README.md b/testing/bsg_misc/bsg_idiv_iterative/README.md index 326448b3a..74fd30f98 100644 --- a/testing/bsg_misc/bsg_idiv_iterative/README.md +++ b/testing/bsg_misc/bsg_idiv_iterative/README.md @@ -1,7 +1,6 @@ Testbench: - Set design parameters for design like bits/iteration and design width in the make command -UNSIGN - Test unsigned (default don't test) SIGN - Test signed (default don't test) WIDTH - design width BITS_PER_ITER - 1 or 2 bits per iteration generated (different hardware designs) diff --git a/testing/bsg_misc/bsg_idiv_iterative/test_bsg.v b/testing/bsg_misc/bsg_idiv_iterative/test_bsg.v index bdc6ee105..32b2232ef 100644 --- a/testing/bsg_misc/bsg_idiv_iterative/test_bsg.v +++ b/testing/bsg_misc/bsg_idiv_iterative/test_bsg.v @@ -95,10 +95,8 @@ module test_bsg; $fwrite(f1,"%d %d %d %d\n", s_dividend, s_divisor, s_quotient, s_remainder); $fwrite(f3,"%d %d\n", s_dividend, s_divisor); - `endif - // do the unsigned case - `ifdef UNSIGN + `else u_dividend = dividend; u_divisor = divisor; From 07be79b67a0efff4c9f343fa2f2db3b14736800f Mon Sep 17 00:00:00 2001 From: kaamakshee Date: Thu, 15 Dec 2022 20:30:37 -0800 Subject: [PATCH 03/10] div_shift when divisor is zero --- bsg_misc/bsg_idiv_iterative_controller.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bsg_misc/bsg_idiv_iterative_controller.v b/bsg_misc/bsg_idiv_iterative_controller.v index ef9db0fa0..af73c255c 100644 --- a/bsg_misc/bsg_idiv_iterative_controller.v +++ b/bsg_misc/bsg_idiv_iterative_controller.v @@ -42,7 +42,7 @@ module bsg_idiv_iterative_controller #(parameter width_p=32, parameter bits_per_ ,output logic latch_signed_div_o ,output logic adder1_cin_o - ,output logic [$clog2(width_p)-1:0] div_shift + ,output [$clog2(width_p)-1:0] div_shift ,output logic v_o ,input yumi_i @@ -96,7 +96,7 @@ module bsg_idiv_iterative_controller #(parameter width_p=32, parameter bits_per_ ,.num_zero_o(clz_a_result) ); - assign div_shift = clz_a_result - clz_c_result; + assign div_shift = (zero_divisor_i) ? width_p-1 : clz_a_result - clz_c_result; logic [`BSG_WIDTH(width_p/bits_per_iter_p)-1:0] calc_cnt; wire calc_up_li = (state == CALC) && (calc_cnt < div_shift); From 1a118e5712ef8a65b7eaeae69e8f9e91fdd4b772 Mon Sep 17 00:00:00 2001 From: kaamakshee Date: Thu, 15 Dec 2022 23:35:00 -0800 Subject: [PATCH 04/10] Initial restrictions --- bsg_misc/bsg_idiv_iterative_controller.v | 9 ++++++--- testing/bsg_misc/bsg_idiv_iterative/signed.c | 4 ++++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/bsg_misc/bsg_idiv_iterative_controller.v b/bsg_misc/bsg_idiv_iterative_controller.v index af73c255c..458532d3d 100644 --- a/bsg_misc/bsg_idiv_iterative_controller.v +++ b/bsg_misc/bsg_idiv_iterative_controller.v @@ -56,7 +56,6 @@ module bsg_idiv_iterative_controller #(parameter width_p=32, parameter bits_per_ logic [width_p-1:0] clz_dividend_input, clz_divisor_input; logic [$clog2(width_p)-1:0] clz_c_result, clz_a_result; - //wire [$clog2(width_p)-1:0] div_shift; typedef enum logic[5:0] {WAIT, NEG0, NEG1, SHIFT, @@ -97,10 +96,14 @@ module bsg_idiv_iterative_controller #(parameter width_p=32, parameter bits_per_ ); assign div_shift = (zero_divisor_i) ? width_p-1 : clz_a_result - clz_c_result; + logic [`BSG_WIDTH(width_p/bits_per_iter_p)-1:0] calc_cyc = width_p/bits_per_iter_p; + if (!(signed_div_r_i) && (bits_per_iter_p==1)) begin + assign calc_cyc = div_shift; + end logic [`BSG_WIDTH(width_p/bits_per_iter_p)-1:0] calc_cnt; - wire calc_up_li = (state == CALC) && (calc_cnt < div_shift); - wire calc_done = (calc_cnt == div_shift); + wire calc_up_li = (state == CALC) && (calc_cnt < calc_cyc); + wire calc_done = (calc_cnt == calc_cyc); bsg_counter_clear_up#(.max_val_p(width_p/bits_per_iter_p) ,.init_val_p(0) ,.disable_overflow_warning_p(1)) calc_counter diff --git a/testing/bsg_misc/bsg_idiv_iterative/signed.c b/testing/bsg_misc/bsg_idiv_iterative/signed.c index cf6f37926..afa0255b1 100644 --- a/testing/bsg_misc/bsg_idiv_iterative/signed.c +++ b/testing/bsg_misc/bsg_idiv_iterative/signed.c @@ -3,8 +3,12 @@ // RISC-V ISA Manual: Section 7.2 - Division Operations #include #include +#ifndef WIDTH #define WIDTH 4 +#endif +#ifndef ITERS #define ITERS 1 << (WIDTH * 2) +#endif // #define ITERS 10000 // Function to compute quotient From e487a1a0862d3b15b26f5bca8fb46a517b7d6f28 Mon Sep 17 00:00:00 2001 From: kaamakshee Date: Mon, 19 Dec 2022 00:58:36 -0800 Subject: [PATCH 05/10] Code cleanup & Makefile flow for signed testing --- bsg_misc/bsg_idiv_iterative.v | 6 ++++-- bsg_misc/bsg_idiv_iterative_controller.v | 21 ++++++++------------ testing/bsg_misc/bsg_idiv_iterative/Makefile | 9 +++++++-- 3 files changed, 19 insertions(+), 17 deletions(-) diff --git a/bsg_misc/bsg_idiv_iterative.v b/bsg_misc/bsg_idiv_iterative.v index 857cd8c63..ef57124a6 100644 --- a/bsg_misc/bsg_idiv_iterative.v +++ b/bsg_misc/bsg_idiv_iterative.v @@ -94,8 +94,6 @@ module bsg_idiv_iterative #(parameter width_p=32, parameter bitstack_p=0, parame wire [$clog2(width_p)-1:0] div_shift; - let mask(value, select, lsb) = ((2**select-1) & (value >> lsb)); - if (bits_per_iter_p == 2) begin bsg_mux_one_hot #(.width_p(width_p+1), .els_p(4)) muxB @@ -272,4 +270,8 @@ module bsg_idiv_iterative #(parameter width_p=32, parameter bitstack_p=0, parame ,.v_o(v_o) ,.yumi_i(yumi_i) ); + +function automatic [width_p:0] mask ( [width_p:0] value, [$clog2(width_p)+1:0] select, [$clog2(width_p)+1:0] lsb ); + mask = ((2**select-1) & (value >> lsb)); +endfunction endmodule // divide diff --git a/bsg_misc/bsg_idiv_iterative_controller.v b/bsg_misc/bsg_idiv_iterative_controller.v index 458532d3d..cde9411cb 100644 --- a/bsg_misc/bsg_idiv_iterative_controller.v +++ b/bsg_misc/bsg_idiv_iterative_controller.v @@ -53,8 +53,6 @@ module bsg_idiv_iterative_controller #(parameter width_p=32, parameter bits_per_ logic neg_ld; logic add1_neg_last_r, add2_neg_last_r; - - logic [width_p-1:0] clz_dividend_input, clz_divisor_input; logic [$clog2(width_p)-1:0] clz_c_result, clz_a_result; typedef enum logic[5:0] @@ -77,29 +75,23 @@ module bsg_idiv_iterative_controller #(parameter width_p=32, parameter bits_per_ end end - - assign clz_dividend_input = dividend_i; - assign clz_divisor_input = divisor_i; - bsg_counting_leading_zeros #( .width_p(width_p) ) clz_c ( - .a_i(clz_dividend_input) + .a_i(dividend_i) ,.num_zero_o(clz_c_result) ); bsg_counting_leading_zeros #( .width_p(width_p) ) clz_a ( - .a_i(clz_divisor_input) + .a_i(divisor_i) ,.num_zero_o(clz_a_result) ); - assign div_shift = (zero_divisor_i) ? width_p-1 : clz_a_result - clz_c_result; - logic [`BSG_WIDTH(width_p/bits_per_iter_p)-1:0] calc_cyc = width_p/bits_per_iter_p; - if (!(signed_div_r_i) && (bits_per_iter_p==1)) begin - assign calc_cyc = div_shift; - end + assign div_shift = zero_divisor_i ? width_p-1 : clz_a_result - clz_c_result; + wire [`BSG_WIDTH(width_p/bits_per_iter_p)-1:0] calc_cyc; + assign calc_cyc = ((!signed_div_r_i) && (bits_per_iter_p==1)) ? div_shift : width_p/bits_per_iter_p; logic [`BSG_WIDTH(width_p/bits_per_iter_p)-1:0] calc_cnt; wire calc_up_li = (state == CALC) && (calc_cnt < calc_cyc); @@ -214,6 +206,9 @@ module bsg_idiv_iterative_controller #(parameter width_p=32, parameter bits_per_ if (bits_per_iter_p == 2) begin opC_sel_o = 4'b0010; opB_sel_o = 4'b0010; + end else if (signed_div_r_i) begin + opC_sel_o = 3'b001; + opB_sel_o = 3'b001; end else begin opC_sel_o = 4'b1000; opB_sel_o = 4'b1000; diff --git a/testing/bsg_misc/bsg_idiv_iterative/Makefile b/testing/bsg_misc/bsg_idiv_iterative/Makefile index 4ba946940..30c5a20fd 100644 --- a/testing/bsg_misc/bsg_idiv_iterative/Makefile +++ b/testing/bsg_misc/bsg_idiv_iterative/Makefile @@ -9,7 +9,7 @@ VCS_DEFINES = CC = gcc CFLAGS = -g SRC=unsigned.c -OUT=unsigned.o +SRC1=signed.c ifdef SIGN VCS_DEFINES += +define+SIGN=$(SIGN) @@ -33,10 +33,15 @@ xvcs: $(VCS) -full64 -sverilog -Mupdate -RI -line -f divide.files $(LIB_OPTS) $(PLI_OPTS) test: $(SRC) - $(CC) -o unsigned.o -c $^ $(CFLAGS) -lm -std=c99 -D ITERS=$(ITERS) + $(CC) -o unsigned.o -c $^ $(CFLAGS) -lm -std=c99 -D ITERS=$(ITERS) -D WIDTH=$(WIDTH) $(CC) unsigned.o -o test ./test +test1: $(SRC1) + $(CC) -o signed.o -c $^ $(CFLAGS) -lm -std=c99 -D ITERS=$(ITERS) -D WIDTH=$(WIDTH) + $(CC) signed.o -o test1 + ./test1 + clean: $(RM) -r csrc simv.daidir vcs.key simv ucli.key vcdplus.vpd s_output.txt u_output.txt u.txt s.txt dve64: From 0f38a77c2b3f761d96a7362aa14184a232bd1e31 Mon Sep 17 00:00:00 2001 From: kaamakshee Date: Tue, 20 Dec 2022 13:50:38 -0800 Subject: [PATCH 06/10] Moving div_shift calculation to datapath and passing it to the controller --- bsg_misc/bsg_idiv_iterative.v | 32 ++++++++++++++++-------- bsg_misc/bsg_idiv_iterative_controller.v | 24 ++---------------- 2 files changed, 23 insertions(+), 33 deletions(-) diff --git a/bsg_misc/bsg_idiv_iterative.v b/bsg_misc/bsg_idiv_iterative.v index ef57124a6..802a32ec5 100644 --- a/bsg_misc/bsg_idiv_iterative.v +++ b/bsg_misc/bsg_idiv_iterative.v @@ -45,7 +45,6 @@ module bsg_idiv_iterative #(parameter width_p=32, parameter bitstack_p=0, parame ,input yumi_i ); - // synopsys translate_off initial begin assert (bits_per_iter_p == 1 || bits_per_iter_p == 2) @@ -73,11 +72,29 @@ module bsg_idiv_iterative #(parameter width_p=32, parameter bitstack_p=0, parame ,.en_i (latch_signed_div_lo) ,.clk_i(clk_i) ); + + logic [`BSG_SAFE_CLOG2(width_p)-1:0] clz_c_result, clz_a_result; + bsg_counting_leading_zeros #( + .width_p(width_p) + ) clz_c ( + .a_i(dividend_i) + ,.num_zero_o(clz_c_result) + ); + + bsg_counting_leading_zeros #( + .width_p(width_p) + ) clz_a ( + .a_i(divisor_i) + ,.num_zero_o(clz_a_result) + ); //if the divisor is zero wire zero_divisor_li = ~(| opA_r); + wire [`BSG_SAFE_CLOG2(width_p)-1:0] div_shift; + assign div_shift = zero_divisor_li ? width_p-1 : clz_a_result - clz_c_result; + wire [1:0] opA_sel_lo; wire [width_p:0] opA_mux; @@ -91,9 +108,6 @@ module bsg_idiv_iterative #(parameter width_p=32, parameter bitstack_p=0, parame wire [width_p:0] opB_mux, opC_mux; wire [3:0] opB_sel_lo, opC_sel_lo; - - wire [$clog2(width_p)-1:0] div_shift; - if (bits_per_iter_p == 2) begin bsg_mux_one_hot #(.width_p(width_p+1), .els_p(4)) muxB @@ -111,13 +125,13 @@ module bsg_idiv_iterative #(parameter width_p=32, parameter bitstack_p=0, parame end else begin bsg_mux_one_hot #(.width_p(width_p+1), .els_p(4)) muxB - (.data_i( {{mask(add1_out, div_shift+1, 0) << (width_p-div_shift) | mask(opC_r, width_p-div_shift, div_shift)}, opC_r, add1_out, {add1_out[width_p-1:0], opC_r[width_p]}} ) + (.data_i( {{(add1_out << (width_p-div_shift+1)) | opC_r >> div_shift}, opC_r, add1_out, {add1_out[width_p-1:0], opC_r[width_p]}} ) ,.data_o( opB_mux ) ,.sel_one_hot_i(opB_sel_lo) ); bsg_mux_one_hot #(.width_p(width_p+1), .els_p(4)) muxC - (.data_i( {{(mask(opC_r, div_shift, 0) << (1+width_p-div_shift)) | (1<> width_p) << (width_p-div_shift))}, {dividend_msb, dividend_i},add1_out, {opC_r[width_p-1:0], ~add1_out[width_p]}} ) ,.data_o( opC_mux ) ,.sel_one_hot_i(opC_sel_lo) ); @@ -154,7 +168,6 @@ module bsg_idiv_iterative #(parameter width_p=32, parameter bitstack_p=0, parame wire opA_clr_lo; wire opB_clr_lo; - wire [width_p:0] add1_in0; wire [width_p:0] add1_in1; wire [width_p:0] add2_in0; @@ -246,8 +259,7 @@ module bsg_idiv_iterative #(parameter width_p=32, parameter bitstack_p=0, parame ,.opA_is_neg_i (opA_r[width_p]) ,.opC_is_neg_i (opC_r[width_p]) - ,.dividend_i (dividend_i) - ,.divisor_i (divisor_i) + ,.div_shift (div_shift) ,.opA_sel_o (opA_sel_lo) ,.opA_ld_o (opA_ld_lo) @@ -265,8 +277,6 @@ module bsg_idiv_iterative #(parameter width_p=32, parameter bitstack_p=0, parame ,.latch_signed_div_o (latch_signed_div_lo) ,.adder1_cin_o (adder1_cin_lo) - ,.div_shift (div_shift) - ,.v_o(v_o) ,.yumi_i(yumi_i) ); diff --git a/bsg_misc/bsg_idiv_iterative_controller.v b/bsg_misc/bsg_idiv_iterative_controller.v index cde9411cb..c5c729570 100644 --- a/bsg_misc/bsg_idiv_iterative_controller.v +++ b/bsg_misc/bsg_idiv_iterative_controller.v @@ -22,9 +22,7 @@ module bsg_idiv_iterative_controller #(parameter width_p=32, parameter bits_per_ ,input opA_is_neg_i ,input opC_is_neg_i - - ,input [width_p-1: 0] dividend_i - ,input [width_p-1: 0] divisor_i + ,input [`BSG_SAFE_CLOG2(width_p)-1:0] div_shift ,output logic [1:0] opA_sel_o ,output logic opA_ld_o @@ -42,8 +40,6 @@ module bsg_idiv_iterative_controller #(parameter width_p=32, parameter bits_per_ ,output logic latch_signed_div_o ,output logic adder1_cin_o - ,output [$clog2(width_p)-1:0] div_shift - ,output logic v_o ,input yumi_i ); @@ -53,8 +49,6 @@ module bsg_idiv_iterative_controller #(parameter width_p=32, parameter bits_per_ logic neg_ld; logic add1_neg_last_r, add2_neg_last_r; - logic [$clog2(width_p)-1:0] clz_c_result, clz_a_result; - typedef enum logic[5:0] {WAIT, NEG0, NEG1, SHIFT, CALC, @@ -75,23 +69,9 @@ module bsg_idiv_iterative_controller #(parameter width_p=32, parameter bits_per_ end end - bsg_counting_leading_zeros #( - .width_p(width_p) - ) clz_c ( - .a_i(dividend_i) - ,.num_zero_o(clz_c_result) - ); - - bsg_counting_leading_zeros #( - .width_p(width_p) - ) clz_a ( - .a_i(divisor_i) - ,.num_zero_o(clz_a_result) - ); - - assign div_shift = zero_divisor_i ? width_p-1 : clz_a_result - clz_c_result; wire [`BSG_WIDTH(width_p/bits_per_iter_p)-1:0] calc_cyc; assign calc_cyc = ((!signed_div_r_i) && (bits_per_iter_p==1)) ? div_shift : width_p/bits_per_iter_p; + wire [`BSG_WIDTH(width_p):0] shift_val = (state == SHIFT) && ((!signed_div_r_i) && (bits_per_iter_p==1)) ? div_shift : width_p; logic [`BSG_WIDTH(width_p/bits_per_iter_p)-1:0] calc_cnt; wire calc_up_li = (state == CALC) && (calc_cnt < calc_cyc); From bcebf081e78d920c5e0626fb05cbc6a8b5d406b3 Mon Sep 17 00:00:00 2001 From: kaamakshee Date: Tue, 20 Dec 2022 14:36:15 -0800 Subject: [PATCH 07/10] Eliminating the 4th mux input --- bsg_misc/bsg_idiv_iterative.v | 14 +++++++------- bsg_misc/bsg_idiv_iterative_controller.v | 15 +++++++-------- 2 files changed, 14 insertions(+), 15 deletions(-) diff --git a/bsg_misc/bsg_idiv_iterative.v b/bsg_misc/bsg_idiv_iterative.v index 802a32ec5..c3c20417e 100644 --- a/bsg_misc/bsg_idiv_iterative.v +++ b/bsg_misc/bsg_idiv_iterative.v @@ -106,7 +106,8 @@ module bsg_idiv_iterative #(parameter width_p=32, parameter bitstack_p=0, parame ); wire [width_p:0] opB_mux, opC_mux; - wire [3:0] opB_sel_lo, opC_sel_lo; + wire [bits_per_iter_p + 1:0] opB_sel_lo, opC_sel_lo; + wire [`BSG_WIDTH(width_p):0] shift_val; if (bits_per_iter_p == 2) begin @@ -125,13 +126,13 @@ module bsg_idiv_iterative #(parameter width_p=32, parameter bitstack_p=0, parame end else begin bsg_mux_one_hot #(.width_p(width_p+1), .els_p(4)) muxB - (.data_i( {{(add1_out << (width_p-div_shift+1)) | opC_r >> div_shift}, opC_r, add1_out, {add1_out[width_p-1:0], opC_r[width_p]}} ) + (.data_i( {opC_r, add1_out, {(add1_out << (width_p-shift_val+1)) | opC_r >> shift_val}} ) ,.data_o( opB_mux ) ,.sel_one_hot_i(opB_sel_lo) ); bsg_mux_one_hot #(.width_p(width_p+1), .els_p(4)) muxC - (.data_i( {{(opC_r << (width_p-div_shift+1)) | ((~add1_out >> width_p) << (width_p-div_shift))}, {dividend_msb, dividend_i},add1_out, {opC_r[width_p-1:0], ~add1_out[width_p]}} ) + (.data_i( {{dividend_msb, dividend_i},add1_out, {(opC_r << (width_p-shift_val+1)) | ((~add1_out >> width_p) << (width_p-shift_val))}} ) ,.data_o( opC_mux ) ,.sel_one_hot_i(opC_sel_lo) ); @@ -276,12 +277,11 @@ module bsg_idiv_iterative #(parameter width_p=32, parameter bitstack_p=0, parame ,.latch_signed_div_o (latch_signed_div_lo) ,.adder1_cin_o (adder1_cin_lo) - + + ,.shift_val (shift_val) + ,.v_o(v_o) ,.yumi_i(yumi_i) ); -function automatic [width_p:0] mask ( [width_p:0] value, [$clog2(width_p)+1:0] select, [$clog2(width_p)+1:0] lsb ); - mask = ((2**select-1) & (value >> lsb)); -endfunction endmodule // divide diff --git a/bsg_misc/bsg_idiv_iterative_controller.v b/bsg_misc/bsg_idiv_iterative_controller.v index c5c729570..15543aeeb 100644 --- a/bsg_misc/bsg_idiv_iterative_controller.v +++ b/bsg_misc/bsg_idiv_iterative_controller.v @@ -29,17 +29,19 @@ module bsg_idiv_iterative_controller #(parameter width_p=32, parameter bits_per_ ,output logic opA_inv_o ,output logic opA_clr_l_o - ,output logic [3:0] opB_sel_o + ,output logic [bits_per_iter_p + 1:0] opB_sel_o ,output logic opB_ld_o ,output logic opB_inv_o ,output logic opB_clr_l_o - ,output logic [3:0] opC_sel_o + ,output logic [bits_per_iter_p + 1:0] opC_sel_o ,output logic opC_ld_o ,output logic latch_signed_div_o ,output logic adder1_cin_o + ,output logic [`BSG_WIDTH(width_p):0] shift_val + ,output logic v_o ,input yumi_i ); @@ -71,7 +73,7 @@ module bsg_idiv_iterative_controller #(parameter width_p=32, parameter bits_per_ wire [`BSG_WIDTH(width_p/bits_per_iter_p)-1:0] calc_cyc; assign calc_cyc = ((!signed_div_r_i) && (bits_per_iter_p==1)) ? div_shift : width_p/bits_per_iter_p; - wire [`BSG_WIDTH(width_p):0] shift_val = (state == SHIFT) && ((!signed_div_r_i) && (bits_per_iter_p==1)) ? div_shift : width_p; + assign shift_val = (state == SHIFT) && ((!signed_div_r_i) && (bits_per_iter_p==1)) ? div_shift : width_p; logic [`BSG_WIDTH(width_p/bits_per_iter_p)-1:0] calc_cnt; wire calc_up_li = (state == CALC) && (calc_cnt < calc_cyc); @@ -186,12 +188,9 @@ module bsg_idiv_iterative_controller #(parameter width_p=32, parameter bits_per_ if (bits_per_iter_p == 2) begin opC_sel_o = 4'b0010; opB_sel_o = 4'b0010; - end else if (signed_div_r_i) begin - opC_sel_o = 3'b001; - opB_sel_o = 3'b001; end else begin - opC_sel_o = 4'b1000; - opB_sel_o = 4'b1000; + opC_sel_o = 3'b001; + opB_sel_o = 3'b001; end end From 6a8dd8fa298422933f7426f1345de5dc3592722b Mon Sep 17 00:00:00 2001 From: kaamakshee Date: Tue, 28 Feb 2023 00:26:13 -0800 Subject: [PATCH 08/10] Fixed mux input count --- bsg_misc/bsg_idiv_iterative.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bsg_misc/bsg_idiv_iterative.v b/bsg_misc/bsg_idiv_iterative.v index c3c20417e..619410b52 100644 --- a/bsg_misc/bsg_idiv_iterative.v +++ b/bsg_misc/bsg_idiv_iterative.v @@ -125,13 +125,13 @@ module bsg_idiv_iterative #(parameter width_p=32, parameter bitstack_p=0, parame end else begin - bsg_mux_one_hot #(.width_p(width_p+1), .els_p(4)) muxB + bsg_mux_one_hot #(.width_p(width_p+1), .els_p(3)) muxB (.data_i( {opC_r, add1_out, {(add1_out << (width_p-shift_val+1)) | opC_r >> shift_val}} ) ,.data_o( opB_mux ) ,.sel_one_hot_i(opB_sel_lo) ); - bsg_mux_one_hot #(.width_p(width_p+1), .els_p(4)) muxC + bsg_mux_one_hot #(.width_p(width_p+1), .els_p(3)) muxC (.data_i( {{dividend_msb, dividend_i},add1_out, {(opC_r << (width_p-shift_val+1)) | ((~add1_out >> width_p) << (width_p-shift_val))}} ) ,.data_o( opC_mux ) ,.sel_one_hot_i(opC_sel_lo) From 96ee5c1662cda3c91f73bf2b12c2ce1fbb53ab21 Mon Sep 17 00:00:00 2001 From: kaamakshee Date: Wed, 15 Mar 2023 17:54:19 -0700 Subject: [PATCH 09/10] Bits_per_iter=2 case updates --- bsg_misc/bsg_idiv_iterative.v | 4 ++-- bsg_misc/bsg_idiv_iterative_controller.v | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/bsg_misc/bsg_idiv_iterative.v b/bsg_misc/bsg_idiv_iterative.v index c3c20417e..20d438223 100644 --- a/bsg_misc/bsg_idiv_iterative.v +++ b/bsg_misc/bsg_idiv_iterative.v @@ -112,13 +112,13 @@ module bsg_idiv_iterative #(parameter width_p=32, parameter bitstack_p=0, parame if (bits_per_iter_p == 2) begin bsg_mux_one_hot #(.width_p(width_p+1), .els_p(4)) muxB - (.data_i( {opC_r, add1_out, {add1_out[width_p-1:0], opC_r[width_p]}, {add2_out[width_p-1:0], opC_r[width_p-1]}} ) + (.data_i( {opC_r, add1_out, {(add1_out << (width_p-shift_val+1)) | opC_r >> (shift_val)}, {add2_out[width_p-1:0], opC_r[width_p-1]}} ) ,.data_o( opB_mux ) ,.sel_one_hot_i(opB_sel_lo) ); bsg_mux_one_hot #(.width_p(width_p+1), .els_p(4)) muxC - (.data_i( {{dividend_msb, dividend_i},add1_out, {opC_r[width_p-1:0], ~add1_out[width_p]}, {opC_r[width_p-2:0], ~add1_out[width_p], ~add2_out[width_p]}}) + (.data_i( {{dividend_msb, dividend_i},add1_out, {(opC_r << (width_p-shift_val+1)) | ((~add1_out >> width_p) << (width_p-shift_val))}, {opC_r[width_p-2:0], ~add1_out[width_p], ~add2_out[width_p]}}) ,.data_o( opC_mux ) ,.sel_one_hot_i(opC_sel_lo) ); diff --git a/bsg_misc/bsg_idiv_iterative_controller.v b/bsg_misc/bsg_idiv_iterative_controller.v index 15543aeeb..af91e9b39 100644 --- a/bsg_misc/bsg_idiv_iterative_controller.v +++ b/bsg_misc/bsg_idiv_iterative_controller.v @@ -72,8 +72,8 @@ module bsg_idiv_iterative_controller #(parameter width_p=32, parameter bits_per_ end wire [`BSG_WIDTH(width_p/bits_per_iter_p)-1:0] calc_cyc; - assign calc_cyc = ((!signed_div_r_i) && (bits_per_iter_p==1)) ? div_shift : width_p/bits_per_iter_p; - assign shift_val = (state == SHIFT) && ((!signed_div_r_i) && (bits_per_iter_p==1)) ? div_shift : width_p; + assign calc_cyc = ((!signed_div_r_i)) ? ((bits_per_iter_p==1)?div_shift:(div_shift+1)/2) : width_p/bits_per_iter_p; + assign shift_val = ((state == SHIFT) && ((!signed_div_r_i))) ? ((bits_per_iter_p==1)?div_shift:(calc_cyc*2)) : width_p; logic [`BSG_WIDTH(width_p/bits_per_iter_p)-1:0] calc_cnt; wire calc_up_li = (state == CALC) && (calc_cnt < calc_cyc); From d26fba3d043438fb9f038a5f717bccfcb5b19871 Mon Sep 17 00:00:00 2001 From: kaamakshee Date: Wed, 15 Mar 2023 18:51:39 -0700 Subject: [PATCH 10/10] naming convention fixes --- bsg_misc/bsg_idiv_iterative.v | 18 +++++++++--------- bsg_misc/bsg_idiv_iterative_controller.v | 8 ++++---- 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/bsg_misc/bsg_idiv_iterative.v b/bsg_misc/bsg_idiv_iterative.v index beaaca2a0..35de1bd34 100644 --- a/bsg_misc/bsg_idiv_iterative.v +++ b/bsg_misc/bsg_idiv_iterative.v @@ -92,8 +92,8 @@ module bsg_idiv_iterative #(parameter width_p=32, parameter bitstack_p=0, parame //if the divisor is zero wire zero_divisor_li = ~(| opA_r); - wire [`BSG_SAFE_CLOG2(width_p)-1:0] div_shift; - assign div_shift = zero_divisor_li ? width_p-1 : clz_a_result - clz_c_result; + wire [`BSG_SAFE_CLOG2(width_p)-1:0] div_shift_li; + assign div_shift_li = zero_divisor_li ? width_p-1 : clz_a_result - clz_c_result; wire [1:0] opA_sel_lo; wire [width_p:0] opA_mux; @@ -107,18 +107,18 @@ module bsg_idiv_iterative #(parameter width_p=32, parameter bitstack_p=0, parame wire [width_p:0] opB_mux, opC_mux; wire [bits_per_iter_p + 1:0] opB_sel_lo, opC_sel_lo; - wire [`BSG_WIDTH(width_p):0] shift_val; + wire [`BSG_WIDTH(width_p):0] shift_val_lo; if (bits_per_iter_p == 2) begin bsg_mux_one_hot #(.width_p(width_p+1), .els_p(4)) muxB - (.data_i( {opC_r, add1_out, {(add1_out << (width_p-shift_val+1)) | opC_r >> (shift_val)}, {add2_out[width_p-1:0], opC_r[width_p-1]}} ) + (.data_i( {opC_r, add1_out, {(add1_out << (width_p-shift_val_lo+1)) | opC_r >> (shift_val_lo)}, {add2_out[width_p-1:0], opC_r[width_p-1]}} ) ,.data_o( opB_mux ) ,.sel_one_hot_i(opB_sel_lo) ); bsg_mux_one_hot #(.width_p(width_p+1), .els_p(4)) muxC - (.data_i( {{dividend_msb, dividend_i},add1_out, {(opC_r << (width_p-shift_val+1)) | ((~add1_out >> width_p) << (width_p-shift_val))}, {opC_r[width_p-2:0], ~add1_out[width_p], ~add2_out[width_p]}}) + (.data_i( {{dividend_msb, dividend_i},add1_out, {(opC_r << (width_p-shift_val_lo+1)) | ((~add1_out >> width_p) << (width_p-shift_val_lo))}, {opC_r[width_p-2:0], ~add1_out[width_p], ~add2_out[width_p]}}) ,.data_o( opC_mux ) ,.sel_one_hot_i(opC_sel_lo) ); @@ -126,13 +126,13 @@ module bsg_idiv_iterative #(parameter width_p=32, parameter bitstack_p=0, parame end else begin bsg_mux_one_hot #(.width_p(width_p+1), .els_p(3)) muxB - (.data_i( {opC_r, add1_out, {(add1_out << (width_p-shift_val+1)) | opC_r >> shift_val}} ) + (.data_i( {opC_r, add1_out, {(add1_out << (width_p-shift_val_lo+1)) | opC_r >> shift_val_lo}} ) ,.data_o( opB_mux ) ,.sel_one_hot_i(opB_sel_lo) ); bsg_mux_one_hot #(.width_p(width_p+1), .els_p(3)) muxC - (.data_i( {{dividend_msb, dividend_i},add1_out, {(opC_r << (width_p-shift_val+1)) | ((~add1_out >> width_p) << (width_p-shift_val))}} ) + (.data_i( {{dividend_msb, dividend_i},add1_out, {(opC_r << (width_p-shift_val_lo+1)) | ((~add1_out >> width_p) << (width_p-shift_val_lo))}} ) ,.data_o( opC_mux ) ,.sel_one_hot_i(opC_sel_lo) ); @@ -260,7 +260,7 @@ module bsg_idiv_iterative #(parameter width_p=32, parameter bitstack_p=0, parame ,.opA_is_neg_i (opA_r[width_p]) ,.opC_is_neg_i (opC_r[width_p]) - ,.div_shift (div_shift) + ,.div_shift_i (div_shift_li) ,.opA_sel_o (opA_sel_lo) ,.opA_ld_o (opA_ld_lo) @@ -278,7 +278,7 @@ module bsg_idiv_iterative #(parameter width_p=32, parameter bitstack_p=0, parame ,.latch_signed_div_o (latch_signed_div_lo) ,.adder1_cin_o (adder1_cin_lo) - ,.shift_val (shift_val) + ,.shift_val_o (shift_val_lo) ,.v_o(v_o) ,.yumi_i(yumi_i) diff --git a/bsg_misc/bsg_idiv_iterative_controller.v b/bsg_misc/bsg_idiv_iterative_controller.v index af91e9b39..aa2a79527 100644 --- a/bsg_misc/bsg_idiv_iterative_controller.v +++ b/bsg_misc/bsg_idiv_iterative_controller.v @@ -22,7 +22,7 @@ module bsg_idiv_iterative_controller #(parameter width_p=32, parameter bits_per_ ,input opA_is_neg_i ,input opC_is_neg_i - ,input [`BSG_SAFE_CLOG2(width_p)-1:0] div_shift + ,input [`BSG_SAFE_CLOG2(width_p)-1:0] div_shift_i ,output logic [1:0] opA_sel_o ,output logic opA_ld_o @@ -40,7 +40,7 @@ module bsg_idiv_iterative_controller #(parameter width_p=32, parameter bits_per_ ,output logic latch_signed_div_o ,output logic adder1_cin_o - ,output logic [`BSG_WIDTH(width_p):0] shift_val + ,output logic [`BSG_WIDTH(width_p)-1:0] shift_val_o ,output logic v_o ,input yumi_i @@ -72,8 +72,8 @@ module bsg_idiv_iterative_controller #(parameter width_p=32, parameter bits_per_ end wire [`BSG_WIDTH(width_p/bits_per_iter_p)-1:0] calc_cyc; - assign calc_cyc = ((!signed_div_r_i)) ? ((bits_per_iter_p==1)?div_shift:(div_shift+1)/2) : width_p/bits_per_iter_p; - assign shift_val = ((state == SHIFT) && ((!signed_div_r_i))) ? ((bits_per_iter_p==1)?div_shift:(calc_cyc*2)) : width_p; + assign calc_cyc = ((!signed_div_r_i)) ? ((bits_per_iter_p==1)?div_shift_i:(div_shift_i+1)/2) : width_p/bits_per_iter_p; + assign shift_val_o = ((state == SHIFT) && ((!signed_div_r_i))) ? ((bits_per_iter_p==1)?div_shift_i:(calc_cyc*2)) : width_p; logic [`BSG_WIDTH(width_p/bits_per_iter_p)-1:0] calc_cnt; wire calc_up_li = (state == CALC) && (calc_cnt < calc_cyc);