Merge pull request #13 from FrederikLauer/master

Fix Bug in the Configuration Value for TS4231

Author: ataffanel

Makefile

@@ -17,7 +17,7 @@ $(PROJ).json: LighthouseTopLevel.v
 	yosys -p 'read_verilog LighthouseTopLevel.v; read_verilog  blackboxes.v; synth_ice40 -top LighthouseTopLevel; write_json $@'
 
 %.asc: %.json $(PIN_DEF)
-	nextpnr-ice40 --seed 4 --up5k --package sg48 --json $< --asc $@ --pcf $(PIN_DEF)
+	nextpnr-ice40 --seed 0 --up5k --package sg48 --json $< --asc $@ --pcf $(PIN_DEF)
 	python3 tools/update_bitstream_comment.py $@ "$(VERSION)"
 
 %.bin: %.asc

rtl/ts4231Configurator.v

@@ -45,7 +45,7 @@ module ts4231Configurator (
   reg prev_reconfigure = 0;
   reg config_prev_d = 0;
   reg [5:0] config_bit_counter = 0;
-  reg [14:0] config_value = {14'h392b, 1'b0};
+  reg [15:0] config_value = {15'h392b, 1'b0};
   reg config_bit = 0;
   reg [4:0] config_wait_counter = 0;
   always @(posedge clk) begin