diff --git a/bittide-instances/src/Bittide/Instances/Hitl/SwCcTopologies.hs b/bittide-instances/src/Bittide/Instances/Hitl/SwCcTopologies.hs index 24a61f29c..4edcc8461 100644 --- a/bittide-instances/src/Bittide/Instances/Hitl/SwCcTopologies.hs +++ b/bittide-instances/src/Bittide/Instances/Hitl/SwCcTopologies.hs @@ -70,8 +70,8 @@ import Clash.Annotations.TH (makeTopEntity) import Clash.Class.Counter import Clash.Cores.Xilinx.GTH import Clash.Cores.Xilinx.Ila (Depth (..), IlaConfig (..), ila, ilaConfig) +import Clash.Cores.Xilinx.Xpm (xpmCdcArraySingle) import Clash.Cores.Xilinx.Xpm.Cdc (xpmCdcSingle) --- import Clash.Cores.Xilinx.Xpm.Cdc.Handshake.Extra (xpmCdcMaybeLossy) import Clash.Functor.Extra import Clash.Sized.Extra (unsignedToSigned) import Clash.Sized.Vector.ToTuple (vecToTuple) @@ -81,6 +81,7 @@ import qualified Bittide.Arithmetic.PartsPer as PartsPer import qualified Bittide.Transceiver as Transceiver import qualified Bittide.Transceiver.ResetManager as ResetManager import qualified Data.Map.Strict as Map (fromList) +import qualified Bittide.ClockControl.StabilityChecker as SI type AllStablePeriod = Seconds 5 @@ -194,12 +195,13 @@ clockControlConfig :: clockControlConfig = $(lift (instancesClockConfig (Proxy @Basic125))) --- counterStartUgn :: BitVector 64 --- counterStartUgn = 0xaabb_ccdd_eeff_1234 -counterStartUgn :: BitVector 63 -counterStartUgn = 0x2abb_ccdd_eeff_1234 +txCounterStartUgn :: BitVector 63 +txCounterStartUgn = 0x2abb_ccdd_eeff_1234 --- type FifoSize = 5 -- = 2^5 = 32 +rxCounterStartUgn :: BitVector 64 +rxCounterStartUgn = 0x9122_3344_1122_3344 + +type FifoSize = 5 -- = 2^5 = 32 {- | Instantiates a hardware implementation of Callisto and exports its results. Can be used to drive FINC/FDEC directly (see @FINC_FDEC@ result) or to tie the @@ -231,7 +233,9 @@ topologyTest :: , "ALL_READY" ::: Signal Basic125 Bool , "ALL_STABLE" ::: Signal Basic125 Bool , "CLOCK_SHIFT" ::: Signal Basic125 FincFdecCount - , "ugnsStable" ::: Vec LinkCount (Signal Basic125 Bool) + , "allUgnsStable" ::: Signal Basic125 Bool + , "noFifoOverflows" ::: Signal Basic125 Bool + , "noFifoUnderflows" ::: Signal Basic125 Bool ) topologyTest refClk sysClk IlaControl{syncRst = rst, ..} rxNs rxPs miso cfg ccs = hwSeqX @@ -249,9 +253,10 @@ topologyTest refClk sysClk IlaControl{syncRst = rst, ..} rxNs rxPs miso cfg ccs , allReady , allStable0 , clockShift --- , ugnsStable - , repeat $ pure True - ) + , allUgnsStable + , noFifoOverflows + , noFifoUnderflows + ) where syncRst = rst `orReset` unsafeFromActiveHigh spiErr @@ -307,7 +312,7 @@ topologyTest refClk sysClk IlaControl{syncRst = rst, ..} rxNs rxPs miso cfg ccs othersNotInCCResetSync = zipWith go othersNotInCCReset transceivers.rxClocks where - go sig rxClk = unsafeFromActiveLow $ xpmCdcSingle rxClk sysClk sig + go sig rxClk = xpmCdcSingle rxClk sysClk sig timeSucc = countSucc @(Unsigned 16, Index (PeriodToCycles Basic125 (Milliseconds 1))) timer = register sysClk syncRst enableGen (0, 0) (timeSucc <$> timer) @@ -367,24 +372,24 @@ topologyTest refClk sysClk IlaControl{syncRst = rst, ..} rxNs rxPs miso cfg ccs :> "capture_fdi_0" :> "probe_fdi_milliseconds" :> "probe_allStable0" - :> "probe_transceiversFailedAfterUp" - :> "probe_nFincs" - :> "probe_nFdecs" + -- :> "probe_transceiversFailedAfterUp" + -- :> "probe_nFincs" + -- :> "probe_nFdecs" :> "probe_net_nFincs" - -- :> "probe_ugn0" - -- :> "probe_ugn1" - -- :> "probe_ugn2" - -- :> "probe_ugn3" - -- :> "probe_ugn4" - -- :> "probe_ugn5" - -- :> "probe_ugn6" - :> "stability0" - :> "stability1" - :> "stability2" - :> "stability3" - :> "stability4" - :> "stability5" - :> "stability6" + :> "probe_ugn0" + :> "probe_ugn1" + :> "probe_ugn2" + :> "probe_ugn3" + :> "probe_ugn4" + :> "probe_ugn5" + :> "probe_ugn6" + -- :> "stability0" + -- :> "stability1" + -- :> "stability2" + -- :> "stability3" + -- :> "stability4" + -- :> "stability5" + -- :> "stability6" -- :> "ugnStable0" -- :> "ugnStable1" -- :> "ugnStable2" @@ -392,8 +397,9 @@ topologyTest refClk sysClk IlaControl{syncRst = rst, ..} rxNs rxPs miso cfg ccs -- :> "ugnStable4" -- :> "ugnStable5" -- :> "ugnStable6" - :> "probe_linkReadys" - :> "probe_linkUps" + -- :> "probe_linkReadys" + -- :> "probe_linkUps" + -- :> "probe_txReadys" :> "probe_othersNotInCCReset" -- :> "fifoUnderflows" -- :> "fifoOverflows" @@ -404,59 +410,62 @@ topologyTest refClk sysClk IlaControl{syncRst = rst, ..} rxNs rxPs miso cfg ccs :> "probe_dDiff4" :> "probe_dDiff5" :> "probe_dDiff6" - :> "probe_syncRst" + -- :> "probe_syncRst" -- :> "probe_gthAllReset" - :> "probe_startupDelayRst" - :> "probe_clockControlReset" - :> "probe_notInCCReset" + -- :> "probe_startupDelayRst" + -- :> "probe_clockControlReset" + -- :> "probe_notInCCReset" -- :> "probe_txResets2" - :> "probe_adjustStart" - :> "probe_clocksAdjusted" - :> "probe_adjusting" - :> "probe_adjustCount" - :> "probe_calibratedClockShift" - :> "probe_initialAdjust" - :> "probe_adjustRst" - :> "probe_clockShift" - :> "probe_initialClockShift" - :> "probe_calibrate" - :> "probe_spiDone" - :> "probe_frequencyAdjustments" - :> "probe_allReady" - :> "probe_syncStart" - :> "probe_delayCount" - :> "probe_startupDelay" - :> "probe_spiErr" - :> "probe_mask" + -- :> "probe_adjustStart" + -- :> "probe_clocksAdjusted" + -- :> "probe_adjusting" + -- :> "probe_adjustCount" + -- :> "probe_calibratedClockShift" + -- :> "probe_initialAdjust" + -- :> "probe_adjustRst" + -- :> "probe_clockShift" + -- :> "probe_initialClockShift" + -- :> "probe_calibrate" + -- :> "probe_spiDone" + -- :> "probe_frequencyAdjustments" + -- :> "probe_allReady" + -- :> "probe_syncStart" + -- :> "probe_delayCount" + -- :> "probe_startupDelay" + -- :> "probe_spiErr" + -- :> "probe_mask" + :> "probe_ugnsStable" + :> "probe_fifoOverflows" + :> "probe_fifoUnderflows" :> Nil ) { depth = D16384 } sysClk -- Trigger as soon as we come out of reset - (unsafeToActiveLow rst) + syncStart captureFlag -- Debug probes milliseconds1 allStable0 - transceiversFailedAfterUp - nFincs - nFdecs + -- transceiversFailedAfterUp + -- nFincs + -- nFdecs (fmap unsignedToSigned nFincs - fmap unsignedToSigned nFdecs) - -- ugn0 - -- ugn1 - -- ugn2 - -- ugn3 - -- ugn4 - -- ugn5 - -- ugn6 - stability0 - stability1 - stability2 - stability3 - stability4 - stability5 - stability6 + ugn0 + ugn1 + ugn2 + ugn3 + ugn4 + ugn5 + ugn6 + -- stability0 + -- stability1 + -- stability2 + -- stability3 + -- stability4 + -- stability5 + -- stability6 -- ugnStable0 -- ugnStable1 -- ugnStable2 @@ -464,9 +473,10 @@ topologyTest refClk sysClk IlaControl{syncRst = rst, ..} rxNs rxPs miso cfg ccs -- ugnStable4 -- ugnStable5 -- ugnStable6 - (bundle transceivers.linkReadys) - (bundle transceivers.linkUps) - (bundle $ unsafeToActiveLow <$> othersNotInCCResetSync) + -- (bundle transceivers.linkReadys) + -- (bundle transceivers.linkUps) + -- (bundle $ zipWith (`unsafeSynchronizer` sysClk) transceivers.txClocks transceivers.txReadys) + (bundle othersNotInCCResetSync) -- (pack . reverse <$> bundle fifoUnderflowsFree) -- (pack . reverse <$> bundle fifoOverflowsFree) dDiff0 @@ -476,30 +486,33 @@ topologyTest refClk sysClk IlaControl{syncRst = rst, ..} rxNs rxPs miso cfg ccs dDiff4 dDiff5 dDiff6 - (unsafeFromReset syncRst) + -- (unsafeFromReset syncRst) -- (unsafeFromReset gthAllReset) - (unsafeFromReset startupDelayRst) - (unsafeFromReset clockControlReset) - notInCCReset + -- (unsafeFromReset startupDelayRst) + -- (unsafeFromReset clockControlReset) + -- notInCCReset -- txResetsThing - adjustStart - clocksAdjusted - adjusting - adjustCount - ccs - initialAdjust - (unsafeFromReset adjustRst) - clockShift - (fromMaybe 0 . initialClockShift <$> cfg) - (pack . calibrate <$> cfg) - spiDone - (pack <$> frequencyAdjustments) - allReady - syncStart - delayCount - (startupDelay <$> cfg) - spiErr - (mask <$> cfg) + -- adjustStart + -- clocksAdjusted + -- adjusting + -- adjustCount + -- ccs + -- initialAdjust + -- (unsafeFromReset adjustRst) + -- clockShift + -- (fromMaybe 0 . initialClockShift <$> cfg) + -- (pack . calibrate <$> cfg) + -- spiDone + -- (pack <$> frequencyAdjustments) + -- allReady + -- syncStart + -- delayCount + -- (startupDelay <$> cfg) + -- spiErr + -- (mask <$> cfg) + (bundle ugnsStable) + (bundle fifoOverflowsFree) + (bundle fifoUnderflowsFree) {- clockMod @@ -632,11 +645,10 @@ topologyTest refClk sysClk IlaControl{syncRst = rst, ..} rxNs rxPs miso cfg ccs domainDiffs = zipWith3 (domainDiffCounterExt sysClk) - (orReset clockControlReset <$> othersNotInCCResetSync) + (orReset clockControlReset . unsafeFromActiveLow <$> othersNotInCCResetSync) transceivers.rxClocks transceivers.txClocks - txAllStables = zipWith (xpmCdcSingle sysClk) transceivers.txClocks (repeat allStable1) txResets2 = zipWith @@ -644,48 +656,102 @@ topologyTest refClk sysClk IlaControl{syncRst = rst, ..} rxNs rxPs miso cfg ccs transceivers.txResets (map unsafeFromActiveLow txAllStables) - txCounters = zipWith txCounter transceivers.txClocks txResets2 - txCounter txClk txRst = result + txNotInCCResets :: Vec LinkCount (Signal GthTx Bool) + txNotInCCResets = go <$> transceivers.txClocks + where + go txClk = unsafeSynchronizer sysClk txClk notInCCReset + + txCounters = zipWith3 txCounter transceivers.txClocks txResets2 txNotInCCResets + txCounter txClk txRst notInCCReset' = result where - notInCCReset' = unsafeSynchronizer sysClk txClk notInCCReset notInCCReset'' :: Signal GthTx (BitVector 1) notInCCReset'' = boolToBV <$> notInCCReset' - dataCounter = register txClk txRst enableGen counterStartUgn (dataCounter + 1) + dataCounter = register txClk txRst enableGen txCounterStartUgn (dataCounter + 1) counter = mux notInCCReset' dataCounter 0 result = (++#) <$> notInCCReset'' <*> counter -- see NOTE [magic start values] - -- rxFifos = - -- zipWith4 - -- go - -- transceivers.txClocks - -- transceivers.rxClocks - -- txResets2 - -- transceivers.rxDatas - -- where - -- go = resettableXilinxElasticBuffer @FifoSize @_ @_ @(Maybe (BitVector 64)) + rxFifos = + zipWith4 + go + transceivers.txClocks + transceivers.rxClocks + txResets2 + transceivers.rxDatas + where + go = resettableXilinxElasticBuffer @FifoSize @_ @_ @(Maybe (BitVector 64)) - -- (fillLvls, fifoUnderflowsTx, fifoOverflowsTx, _ebMode, rxCntrs) = unzip5 rxFifos + (_fillLvls, fifoUnderflowsTx, fifoOverflowsTx, _ebMode, mRxCntrs) = unzip5 rxFifos + rxCntrs = zipWith3 go transceivers.txClocks txNotInCCResets mRxCntrs + where + go txClk txRst = regMaybe txClk (unsafeFromActiveLow txRst) enableGen rxCounterStartUgn - -- fifoOverflowsFree :: Vec LinkCount (Signal Basic125 Overflow) - -- fifoOverflowsFree = zipWith (`xpmCdcSingle` sysClk) transceivers.txClocks fifoOverflowsTx - -- fifoUnderflowsFree :: Vec LinkCount (Signal Basic125 Underflow) - -- fifoUnderflowsFree = zipWith (`xpmCdcSingle` sysClk) transceivers.txClocks fifoUnderflowsTx + fifoOverflowsFree :: Vec LinkCount (Signal Basic125 Overflow) + fifoOverflowsFree = zipWith (`xpmCdcSingle` sysClk) transceivers.txClocks fifoOverflowsTx + fifoUnderflowsFree :: Vec LinkCount (Signal Basic125 Underflow) + fifoUnderflowsFree = zipWith (`xpmCdcSingle` sysClk) transceivers.txClocks fifoUnderflowsTx - -- ugns :: Vec LinkCount (Signal GthTx (BitVector 64)) - -- ugns = - -- zipWith - -- (-) - -- txCounters - -- (map (fmap (fromMaybe 0x1122_3344_1122_3344)) rxCntrs) + ugns :: Vec LinkCount (Signal GthTx (BitVector 64)) + ugns = zipWith (-) txCounters rxCntrs -- see NOTE [magic start values] + ugns' :: Vec LinkCount (Signal Basic125 (BitVector 64)) + ugns' = zipWith3 go transceivers.txClocks othersNotInCCResetSync ugns + where + go txClk enaSig = + regEn + sysClk + clockControlReset + enableGen + rxCounterStartUgn + enaSig + . xpmCdcArraySingle txClk sysClk + + ugnsStable :: Vec LinkCount (Signal Basic125 Bool) + ugnsStable = go <$> ugns' + where + go ugn = ugnStable + where + ugn' = bitCoerce <$> ugn + stabInd = + withClockResetEnable + sysClk + syncRst + enableGen + $ SI.stabilityChecker + (SNat @CccStabilityCheckerMargin) + (SNat @(CccStabilityCheckerFramesize GthTx)) + ugn' + ugnStable = SI.stable <$> stabInd + + maskWithCfg :: + Bool -> + Vec LinkCount (Signal Basic125 Bool) -> + Signal Basic125 (Vec LinkCount Bool) + maskWithCfg dflt = liftA2 go1 (mask <$> cfg) . bundle + where + go1 m = zipWith go2 (bitCoerce m) + go2 m val = if m then val else dflt + + allUgnsStable = trueFor (SNat @(Seconds 2)) sysClk clockControlReset + $ and <$> maskWithCfg True ugnsStable + + findFifoError bits = result + where + masked = maskWithCfg False bits + observingError = or <$> masked + observedError = sticky sysClk clockControlReset observingError + result = not <$> observedError + + noFifoOverflows = findFifoError fifoOverflowsFree + noFifoUnderflows = findFifoError fifoUnderflowsFree + -- NOTE [magic start values] -- These values could be anything, but are chosen to be recognisable and help debugging. - -- 0xaabbccddeeff1234 - 0x1122334411223344 = 0x99999999dddcdef0 - -- If you ever see the ugn being a constant 0x99999999dddcdef0 + -- 0x2abbccddeeff1234 - 0x1122334411223344 = 0x19999999dddcdef0 + -- If you ever see the ugn being a constant 0x19999999dddcdef0 -- then you know the your counter isn't running and you're receiving 'Nothing', - -- If you see 0x99999999.......... and it's counting up, then you're receiving Nothing, + -- If you see 0x19999999.......... and it's counting up, then you're receiving Nothing, -- but your counter is running. -- ugnStable1sec = zipWith3 (stableForMs (SNat @1000)) transceivers.txClocks transceivers.txResets ugns @@ -713,13 +779,21 @@ topologyTest refClk sysClk IlaControl{syncRst = rst, ..} rxNs rxPs miso cfg ccs -- , ugnD5 -- , ugnD6 -- ) = vecToTuple freeUgnDatas - -- (ugn0, _fill0, ugnStable0, _fillStats0) = unbundle ugnD0 - -- (ugn1, _fill1, ugnStable1, _fillStats1) = unbundle ugnD1 - -- (ugn2, _fill2, ugnStable2, _fillStats2) = unbundle ugnD2 - -- (ugn3, _fill3, ugnStable3, _fillStats3) = unbundle ugnD3 - -- (ugn4, _fill4, ugnStable4, _fillStats4) = unbundle ugnD4 - -- (ugn5, _fill5, ugnStable5, _fillStats5) = unbundle ugnD5 - -- (ugn6, _fill6, ugnStable6, _fillStats6) = unbundle ugnD6 + -- (ugn0, _fill0, _ugnStable0, _fillStats0) = unbundle ugnD0 + -- (ugn1, _fill1, _ugnStable1, _fillStats1) = unbundle ugnD1 + -- (ugn2, _fill2, _ugnStable2, _fillStats2) = unbundle ugnD2 + -- (ugn3, _fill3, _ugnStable3, _fillStats3) = unbundle ugnD3 + -- (ugn4, _fill4, _ugnStable4, _fillStats4) = unbundle ugnD4 + -- (ugn5, _fill5, _ugnStable5, _fillStats5) = unbundle ugnD5 + -- (ugn6, _fill6, _ugnStable6, _fillStats6) = unbundle ugnD6 + ( ugn0 + , ugn1 + , ugn2 + , ugn3 + , ugn4 + , ugn5 + , ugn6 + ) = vecToTuple ugns' -- ( stability0 -- , stability1 @@ -728,15 +802,15 @@ topologyTest refClk sysClk IlaControl{syncRst = rst, ..} rxNs rxPs miso cfg ccs -- , stability4 -- , stability5 -- , stability6 - -- ) = vecToTuple $ unbundle stabilities - -- ( dDiff0 - -- , dDiff1 - -- , dDiff2 - -- , dDiff3 - -- , dDiff4 - -- , dDiff5 - -- , dDiff6 - -- ) = vecToTuple domainDiffs + -- ) = vecToTuple $ unbundle callistoResult.stability + ( dDiff0 + , dDiff1 + , dDiff2 + , dDiff3 + , dDiff4 + , dDiff5 + , dDiff6 + ) = vecToTuple domainDiffs type WaitCycles dom hold prd = PeriodToCycles dom (prd - hold) @@ -889,17 +963,19 @@ swCcTopologyTest refClkDiff sysClkDiff syncIn rxns rxps miso = testReset = unsafeFromActiveHigh testResetBool -- testStartingSticky = - -- withClockResetEnable + -- stickyBits -- sysClk -- sysRst -- enableGen - -- $ stickyBits (SNat @(PeriodToCycles Basic125 (Seconds 2))) testStarting + -- (SNat @(PeriodToCycles Basic125 (Seconds 2))) + -- testStarting -- testEndingSticky = - -- withClockResetEnable + -- stickyBits -- sysClk -- sysRst -- enableGen - -- $ stickyBits (SNat @(PeriodToCycles Basic125 (Seconds 2))) testEnding + -- (SNat @(PeriodToCycles Basic125 (Seconds 2))) + -- testEnding -- Workaround for tests not resetting properly??? syncNodeProbablyWorking = changepoints sysClk testReset enableGen syncIn @@ -937,7 +1013,9 @@ swCcTopologyTest refClkDiff sysClkDiff syncIn rxns rxps miso = , allReady , allStable , clockShift - , _ugnsStable + , allUgnsStable + , noFifoOverflows + , noFifoUnderflows ) = topologyTest refClk @@ -975,30 +1053,32 @@ swCcTopologyTest refClkDiff sysClkDiff syncIn rxns rxps miso = :> "probe_tle_milliseconds" :> "probe_ilacfg_allReady" :> "probe_ilacfg_startTest" - :> "probe_ilacfg_syncIn" - :> "probe_ilactl_syncRst" - :> "probe_ilactl_syncOut" + -- :> "probe_ilacfg_syncIn" + -- :> "probe_ilactl_syncRst" + -- :> "probe_ilactl_syncOut" :> "probe_ilactl_syncStart" - :> "probe_ilactl_scheduledCapture" - :> "probe_ilactl_globalTimestamp0" - :> "probe_ilactl_globalTimestamp1" - :> "probe_ilactl_skipTest" - -- :> "probe_ilactl_onlyScheduledCaptures" + -- :> "probe_ilactl_scheduledCapture" + -- :> "probe_ilactl_globalTimestamp0" + -- :> "probe_ilactl_globalTimestamp1" + -- :> "probe_ilactl_skipTest" :> "probe_startTest" - :> "probe_skip" + -- :> "probe_skip" :> "probe_allStable" - :> "probe_tle_clockShift" - :> "probe_tle_calibratedClockShift" + :> "probe_tle_allUgnsStable" + :> "probe_tle_noFifoOverflows" + :> "probe_tle_noFifoUnderflows" + -- :> "probe_tle_clockShift" + -- :> "probe_tle_calibratedClockShift" :> "probe_endSuccess" :> "probe_startBeforeAllReady" :> "probe_tle_transceiversFailedAfterUp" :> "probe_testDone" :> "probe_testSuccess" - :> "probe_testCounter" - :> "probe_testStartingSticky2s" - :> "probe_testEndingSticky2s" - :> "probe_syncNodeEnteredReset" - :> "probe_syncNodePrevEnteredReset" + -- :> "probe_testCounter" + -- :> "probe_testStartingSticky2s" + -- :> "probe_testEndingSticky2s" + -- :> "probe_syncNodeEnteredReset" + -- :> "probe_syncNodePrevEnteredReset" :> Nil ) { depth = D16384 @@ -1009,33 +1089,32 @@ swCcTopologyTest refClkDiff sysClkDiff syncIn rxns rxps miso = milliseconds1 allReady startTest - syncIn - (unsafeToActiveHigh syncRst) - syncOut + -- syncIn + -- (unsafeToActiveHigh syncRst) + -- syncOut syncStart - scheduledCapture - gTS0 - gTS1 - skipTest - -- (pure onlyScheduledCaptures :: Signal Basic125 Bool) + -- scheduledCapture + -- gTS0 + -- gTS1 + -- skipTest startTest - skip + -- skip allStable - clockShift - calibratedClockShift + allUgnsStable + noFifoUnderflows + noFifoOverflows + -- clockShift + -- calibratedClockShift endSuccess startBeforeAllReady transceiversFailedAfterUp testDone testSuccess - testCounter - testStartingSticky - testEndingSticky - syncNodeEnteredReset - syncNodePrevEnteredReset - - -- allUgnsStable = and <$> bundle ugnsStable - -- allStable' = allStable .&&. allUgnsStable + -- testCounter + -- testStartingSticky + -- testEndingSticky + -- syncNodeEnteredReset + -- syncNodePrevEnteredReset -- check that tests are not synchronously start before all -- transceivers are up @@ -1044,7 +1123,6 @@ swCcTopologyTest refClkDiff sysClkDiff syncIn rxns rxps miso = sysClk syncRst (syncStart .&&. ((not <$> allReady) .||. transceiversFailedAfterUp)) - -- (syncStart .&&. (not <$> allReady)) calibratedClockShift = capturedOnce where @@ -1069,9 +1147,14 @@ swCcTopologyTest refClkDiff sysClkDiff syncIn rxns rxps miso = notValidatingCalibration = (/= CCCalibrationValidation) . calibrate <$> cfg + fifoSuccess = noFifoUnderflows .&&. noFifoOverflows + endSuccess :: Signal Basic125 Bool endSuccess = - trueFor (SNat @(Seconds 5)) sysClk syncRst allStable + trueFor (SNat @(Seconds 5)) sysClk syncRst + $ allStable + .&&. allUgnsStable + .&&. fifoSuccess .&&. (notValidatingCalibration .||. withinNoiseLevel) skip = maybe False (not . fpgaEnabled) <$> testConfig @@ -1082,13 +1165,15 @@ swCcTopologyTest refClkDiff sysClkDiff syncIn rxns rxps miso = .||. endSuccess .||. transceiversFailedAfterUp .||. startBeforeAllReady + .||. (not <$> fifoSuccess) ) testSuccess = skip .||. ( allStable + .&&. allUgnsStable + .&&. fifoSuccess .&&. (not <$> (transceiversFailedAfterUp .||. startBeforeAllReady)) - -- .&&. (not <$> startBeforeAllReady) ) testConfig :: Signal Basic125 (Maybe TestConfig)