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Model_T_RAM.kicad_pcb
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(kicad_pcb (version 20221018) (generator pcbnew)
(general
(thickness 1.6)
)
(paper "A4")
(title_block
(title "Model T 8K RAM Module")
(date "2022-09-21")
(rev "011")
(company "[email protected]")
(comment 1 "github.com/bkw777/Model_T_RAM")
)
(layers
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(31 "B.Cu" signal)
(32 "B.Adhes" user "B.Adhesive")
(33 "F.Adhes" user "F.Adhesive")
(34 "B.Paste" user)
(35 "F.Paste" user)
(36 "B.SilkS" user "B.Silkscreen")
(37 "F.SilkS" user "F.Silkscreen")
(38 "B.Mask" user)
(39 "F.Mask" user)
(40 "Dwgs.User" user "User.Drawings")
(41 "Cmts.User" user "User.Comments")
(42 "Eco1.User" user "User.Eco1")
(43 "Eco2.User" user "User.Eco2")
(44 "Edge.Cuts" user)
(45 "Margin" user)
(46 "B.CrtYd" user "B.Courtyard")
(47 "F.CrtYd" user "F.Courtyard")
)
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(layer "F.Cu" (type "copper") (thickness 0.035))
(layer "dielectric 1" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
(layer "B.Cu" (type "copper") (thickness 0.035))
(layer "B.Mask" (type "Bottom Solder Mask") (thickness 0.01))
(layer "B.Paste" (type "Bottom Solder Paste"))
(layer "B.SilkS" (type "Bottom Silk Screen"))
(copper_finish "None")
(dielectric_constraints no)
)
(pad_to_mask_clearance 0)
(solder_mask_min_width 0.22)
(grid_origin 147.32 99.06)
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(outputformat 1)
(mirror false)
(drillshape 0)
(scaleselection 1)
(outputdirectory "GERBER_${TITLE}_${REVISION}")
)
)
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(at 147.32 99.06 90)
(descr "28-lead though-hole mounted DIP package, row spacing 700mils")
(tags "THT DIP DIL PDIP 2.54mm 700mil")
(property "Sheetfile" "Model_T_RAM.kicad_sch")
(property "Sheetname" "")
(path "/00000000-0000-0000-0000-000060746ce1")
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(tstamp 622b7f7b-5911-4a50-befb-440ad2290027)
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