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Fix: adiv5/6 JTAG version handling #2054

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merged 3 commits into from
Jan 15, 2025
Merged

Fix: adiv5/6 JTAG version handling #2054

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45e4676
adiv5_jtag: Turned out that the DP version number is not the same as …
dragonmux Jan 15, 2025
b55b6e3
adiv5_jtag: Properly dispatch the Cortex-M33/TEALDAP PARTNO code
dragonmux Jan 15, 2025
d643492
adiv5_jtag: Properly dispatch the LPC43xx PARTNO code
dragonmux Jan 15, 2025
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11 changes: 5 additions & 6 deletions src/target/adiv5.h
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Original file line number Diff line number Diff line change
Expand Up @@ -213,15 +213,14 @@
#define JTAG_IDCODE_PARTNO_SOC400_4BIT 0xba00U
#define JTAG_IDCODE_PARTNO_SOC400_8BIT 0xba03U
/*
* This PARTNO value comes from the LPC43xx parts which have a bugged pair of TAPs.
* This value is actually reserved as a SWD-DPv1 value, but appears anyway on those devices
* for the second and third JTAG-DPs which are still JTAG-DPv0.
* This PARTNO value comes from the LPC43xx parts which have a pair of Cortex-M0's using DPv1 TAPs.
* Value lifted from UM10503, §50.9 JTAG TAP Identification, Table 1170, pg1355
*/
#define JTAG_IDCODE_PARTNO_SOC400_4BIT_ERRATA 0xba01U
#define JTAG_IDCODE_PARTNO_SOC400_4BIT_LPC43xx 0xba01U

/*
* ARM JTAG PARTNO values from Cortex-M33 TRM (ARM document ID 100230, issue 0100)
* A.4.2.2 Identification Code register, IDCODE, Table A-13 pg98
* ARM JTAG PARTNO values from Cortex-M33 TRM (ARM document ID 100230, issue 0100_03)
* Appendix A, §A.4.2 Identification Code register, IDCODE, Table A-13 pg130
* (for TEALDAP/CM33DAP MINDP SWJ-DP/JTAG-DP)
*/
#define JTAG_IDCODE_PARTNO_SOC400_4BIT_CM33 0xba04U
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16 changes: 6 additions & 10 deletions src/target/adiv5_jtag.c
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Original file line number Diff line number Diff line change
Expand Up @@ -80,15 +80,11 @@ void adiv5_jtag_dp_handler(const uint8_t dev_index)

/* Check which version of DP we have here, if it's an ARM-made DP, and set up `dp->version` accordingly */
if (dp->designer_code == JEP106_MANUFACTURER_ARM) {
/* Correct the LPC43xx errata PARTNO values */
if (dp->partno == JTAG_IDCODE_PARTNO_SOC400_4BIT_ERRATA)
dp->partno = JTAG_IDCODE_PARTNO_SOC400_4BIT;
/* Correct the GD32E50x PARTNO value */
else if (dp->partno == JTAG_IDCODE_PARTNO_SOC400_4BIT_CM33)
dp->partno = JTAG_IDCODE_PARTNO_SOC400_4BIT;

if (dp->partno == JTAG_IDCODE_PARTNO_SOC400_4BIT || dp->partno == JTAG_IDCODE_PARTNO_SOC400_8BIT)
dp->version = 0U;
else if (dp->partno == JTAG_IDCODE_PARTNO_SOC400_4BIT_CM33 ||
dp->partno == JTAG_IDCODE_PARTNO_SOC400_4BIT_LPC43xx)
dp->version = 1U;
else if (dp->partno == JTAG_IDCODE_PARTNO_SOC600_4BIT || dp->partno == JTAG_IDCODE_PARTNO_SOC600_8BIT)
dp->version = 3U;
else
Expand Down Expand Up @@ -154,21 +150,21 @@ uint32_t adiv5_jtag_raw_access(
}

/* If this is an ADIv6 JTAG-DPv1, check for fault */
if (dp->version > 0 && ack == JTAG_ADIv6_ACK_FAULT) {
if (dp->version > 2 && ack == JTAG_ADIv6_ACK_FAULT) {
DEBUG_ERROR("JTAG access resulted in fault\n");
/* Use the SWD ack codes for the fault code to be completely consistent between JTAG-vs-SWD */
dp->fault = SWD_ACK_FAULT;
return 0;
}

/* Check for a not-OK ack under ADIv5 JTAG-DPv0, or ADIv6 JTAG-DPv1 */
if ((dp->version == 0 && ack != JTAG_ADIv5_ACK_OK) || (dp->version > 0 && ack != JTAG_ADIv6_ACK_OK)) {
if ((dp->version < 3 && ack != JTAG_ADIv5_ACK_OK) || (dp->version > 2 && ack != JTAG_ADIv6_ACK_OK)) {
DEBUG_ERROR("JTAG access resulted in: %" PRIx32 ":%x\n", result, ack);
raise_exception(EXCEPTION_ERROR, "JTAG-DP invalid ACK");
}

/* ADIv6 needs 8 idle cycles run after we get done to ensure the state machine is idle */
if (dp->version > 0)
if (dp->version > 2)
jtag_proc.jtagtap_cycle(false, false, 8);
return result;
}
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