32BitSingleCycle.qsf

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#
# Copyright (C) 2018  Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Intel Program License 
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors.  Please
# refer to the applicable agreement for further details.
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# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 13:02:17  September 02, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		32BitSingleCycle_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus Prime software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name DEVICE 10M50DAF484C6GES
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:02:17  SEPTEMBER 02, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name BOARD "MAX 10 DE10 - Lite"
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
set_global_assignment -name SYSTEMVERILOG_FILE instructMem.sv
set_global_assignment -name SYSTEMVERILOG_FILE dataMemory.sv
set_global_assignment -name SYSTEMVERILOG_FILE registerMem.sv
set_global_assignment -name SYSTEMVERILOG_FILE flopr.sv
set_global_assignment -name SYSTEMVERILOG_FILE dataPath.sv
set_global_assignment -name SYSTEMVERILOG_FILE alu.sv
set_global_assignment -name SYSTEMVERILOG_FILE extendSign.sv
set_global_assignment -name SYSTEMVERILOG_FILE adder.sv
set_global_assignment -name SYSTEMVERILOG_FILE mux2.sv
set_global_assignment -name SYSTEMVERILOG_FILE shift_left_2.sv
set_global_assignment -name SYSTEMVERILOG_FILE control_unit.sv
set_global_assignment -name SYSTEMVERILOG_FILE mainDecoder.sv
set_global_assignment -name SYSTEMVERILOG_FILE alu_decoder.sv
set_global_assignment -name SYSTEMVERILOG_FILE mips32Single.sv
set_global_assignment -name SYSTEMVERILOG_FILE top.sv
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VERILOG_TEST_BENCH_FILE testbench.sv
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH testBench -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME testBench -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id testBench
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME testBench -section_id testBench
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST ON -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_FILE testbench.sv -section_id testBench
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top